From e1155b048013a680af439000682c15580f43fe0b Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Wed, 18 Sep 2024 16:37:03 +1000 Subject: [PATCH] stm32/boards: Add definition for STM32H747I-DISCO. Signed-off-by: Andrew Leech --- ports/stm32/boards/STM32H747I-DISCO/bdev.c | 45 +++ .../stm32/boards/STM32H747I-DISCO/board.json | 21 ++ .../stm32/boards/STM32H747I-DISCO/manifest.py | 2 + .../boards/STM32H747I-DISCO/mpconfigboard.h | 331 ++++++++++++++++++ .../boards/STM32H747I-DISCO/mpconfigboard.mk | 30 ++ ports/stm32/boards/STM32H747I-DISCO/pins.csv | 254 ++++++++++++++ .../boards/STM32H747I-DISCO/stm32h747.ld | 50 +++ .../STM32H747I-DISCO/stm32h7xx_hal_conf.h | 51 +++ 8 files changed, 784 insertions(+) create mode 100644 ports/stm32/boards/STM32H747I-DISCO/bdev.c create mode 100644 ports/stm32/boards/STM32H747I-DISCO/board.json create mode 100644 ports/stm32/boards/STM32H747I-DISCO/manifest.py create mode 100644 ports/stm32/boards/STM32H747I-DISCO/mpconfigboard.h create mode 100644 ports/stm32/boards/STM32H747I-DISCO/mpconfigboard.mk create mode 100644 ports/stm32/boards/STM32H747I-DISCO/pins.csv create mode 100644 ports/stm32/boards/STM32H747I-DISCO/stm32h747.ld create mode 100644 ports/stm32/boards/STM32H747I-DISCO/stm32h7xx_hal_conf.h diff --git a/ports/stm32/boards/STM32H747I-DISCO/bdev.c b/ports/stm32/boards/STM32H747I-DISCO/bdev.c new file mode 100644 index 0000000000000..b9dcd81451e5a --- /dev/null +++ b/ports/stm32/boards/STM32H747I-DISCO/bdev.c @@ -0,0 +1,45 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2024 Andrew Leech + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "storage.h" +#include "qspi.h" + +#if MICROPY_HW_SPIFLASH_ENABLE_CACHE +// Shared cache for first and second SPI block devices +static mp_spiflash_cache_t spi_bdev_cache; +#endif + +// First external SPI flash uses hardware QSPI interface +const mp_spiflash_config_t spiflash_config = { + .bus_kind = MP_SPIFLASH_BUS_QSPI, + .bus.u_qspi.data = NULL, + .bus.u_qspi.proto = &qspi_proto, + #if MICROPY_HW_SPIFLASH_ENABLE_CACHE + .cache = &spi_bdev_cache, + #endif +}; + +spi_bdev_t spi_bdev; diff --git a/ports/stm32/boards/STM32H747I-DISCO/board.json b/ports/stm32/boards/STM32H747I-DISCO/board.json new file mode 100644 index 0000000000000..e32445c308859 --- /dev/null +++ b/ports/stm32/boards/STM32H747I-DISCO/board.json @@ -0,0 +1,21 @@ +{ + "deploy": [ + "../deploy.md" + ], + "docs": "", + "features": [ + "Dual-core", + "Ethernet", + "External Flash", + "External RAM", + "USB" + ], + "images": [ + ".jpg" + ], + "mcu": "stm32h747", + "product": "STM Discovery kit with STM32H747XI MCU", + "thumbnail": "", + "url": "https://www.st.com/en/evaluation-tools/stm32h747i-disco.html", + "vendor": "STMicroelectronics" +} diff --git a/ports/stm32/boards/STM32H747I-DISCO/manifest.py b/ports/stm32/boards/STM32H747I-DISCO/manifest.py new file mode 100644 index 0000000000000..ebfecd4844ade --- /dev/null +++ b/ports/stm32/boards/STM32H747I-DISCO/manifest.py @@ -0,0 +1,2 @@ +include("$(PORT_DIR)/boards/manifest.py") +require("bundle-networking") diff --git a/ports/stm32/boards/STM32H747I-DISCO/mpconfigboard.h b/ports/stm32/boards/STM32H747I-DISCO/mpconfigboard.h new file mode 100644 index 0000000000000..99e8b2d73d468 --- /dev/null +++ b/ports/stm32/boards/STM32H747I-DISCO/mpconfigboard.h @@ -0,0 +1,331 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * The MIT License (MIT) + * Copyright (c) 2024 Andrew Leech + */ + +#define MICROPY_HW_BOARD_NAME "STM32H747I-DISCO" +#define MICROPY_HW_MCU_NAME "STM32H747" +#define MICROPY_HW_FLASH_FS_LABEL "STM32H747I-DISCO" + +// Network config +#define MICROPY_PY_NETWORK_HOSTNAME_DEFAULT "STM32H747I-DISCO" + +// #define MICROPY_OBJ_REPR (MICROPY_OBJ_REPR_C) +// #define UINT_FMT "%u" +// #define INT_FMT "%d" +// typedef int mp_int_t; // must be pointer size +// typedef unsigned int mp_uint_t; // must be pointer size + +#define MICROPY_FATFS_EXFAT (1) +#define MICROPY_HW_ENABLE_RTC (1) +#define MICROPY_HW_ENABLE_RNG (1) +#define MICROPY_HW_ENABLE_ADC (1) +#define MICROPY_HW_ENABLE_DAC (1) +#define MICROPY_HW_ENABLE_USB (1) +#define MICROPY_HW_HAS_SWITCH (0) +#define MICROPY_HW_HAS_FLASH (1) +#define MICROPY_HW_ENABLE_SERVO (1) +#define MICROPY_HW_ENABLE_TIMER (1) +#define MICROPY_HW_ENABLE_SDCARD (1) +#define MICROPY_HW_ENABLE_MMCARD (0) + +// Flash storage config +#define MICROPY_HW_SPIFLASH_ENABLE_CACHE (1) +#define MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE (0) + +// #define MICROPY_BOARD_STARTUP PORTENTA_board_startup +// void PORTENTA_board_startup(void); + +// #define MICROPY_BOARD_EARLY_INIT PORTENTA_board_early_init +// void PORTENTA_board_early_init(void); + +// #define MICROPY_BOARD_ENTER_BOOTLOADER(nargs, args) PORTENTA_board_enter_bootloader() +// void PORTENTA_board_enter_bootloader(void); + +// void PORTENTA_board_low_power(int mode); +// #define MICROPY_BOARD_LEAVE_STOP PORTENTA_board_low_power(0); +// #define MICROPY_BOARD_ENTER_STOP PORTENTA_board_low_power(1); +// #define MICROPY_BOARD_ENTER_STANDBY PORTENTA_board_low_power(2); + +// void PORTENTA_board_osc_enable(int enable); +// #define MICROPY_BOARD_OSC_ENABLE PORTENTA_board_osc_enable(1); +// #define MICROPY_BOARD_OSC_DISABLE PORTENTA_board_osc_enable(0); + +// PLL1 400MHz/50MHz for SDMMC and FDCAN +// USB and RNG are clocked from the HSI48 +#define MICROPY_HW_CLK_PLLM (5) +#define MICROPY_HW_CLK_PLLN (160) +#define MICROPY_HW_CLK_PLLP (2) +#define MICROPY_HW_CLK_PLLQ (16) +#define MICROPY_HW_CLK_PLLR (2) +#define MICROPY_HW_CLK_PLLVCI (RCC_PLL1VCIRANGE_2) +#define MICROPY_HW_CLK_PLLVCO (RCC_PLL1VCOWIDE) +#define MICROPY_HW_CLK_PLLFRAC (0) + +// PLL2 200MHz for FMC and QSPI. +#define MICROPY_HW_CLK_PLL2M (5) +#define MICROPY_HW_CLK_PLL2N (80) +#define MICROPY_HW_CLK_PLL2P (2) +#define MICROPY_HW_CLK_PLL2Q (2) +#define MICROPY_HW_CLK_PLL2R (2) +#define MICROPY_HW_CLK_PLL2VCI (RCC_PLL2VCIRANGE_2) +#define MICROPY_HW_CLK_PLL2VCO (RCC_PLL2VCOWIDE) +#define MICROPY_HW_CLK_PLL2FRAC (0) + +// PLL3 160MHz for ADC and SPI123 +#define MICROPY_HW_CLK_PLL3M (5) +#define MICROPY_HW_CLK_PLL3N (160) +#define MICROPY_HW_CLK_PLL3P (2) +#define MICROPY_HW_CLK_PLL3Q (5) +#define MICROPY_HW_CLK_PLL3R (2) +#define MICROPY_HW_CLK_PLL3VCI (RCC_PLL3VCIRANGE_2) +#define MICROPY_HW_CLK_PLL3VCO (RCC_PLL3VCOWIDE) +#define MICROPY_HW_CLK_PLL3FRAC (0) + +// HSE in BYPASS mode. +#define MICROPY_HW_CLK_USE_BYPASS (1) + +// Bus clock divider values +#define MICROPY_HW_CLK_AHB_DIV (RCC_HCLK_DIV2) +#define MICROPY_HW_CLK_APB1_DIV (RCC_APB1_DIV2) +#define MICROPY_HW_CLK_APB2_DIV (RCC_APB2_DIV2) +#define MICROPY_HW_CLK_APB3_DIV (RCC_APB3_DIV2) +#define MICROPY_HW_CLK_APB4_DIV (RCC_APB4_DIV2) + +// Peripheral clock sources +#define MICROPY_HW_RCC_HSI48_STATE (RCC_HSI48_ON) +#define MICROPY_HW_RCC_USB_CLKSOURCE (RCC_USBCLKSOURCE_HSI48) +#define MICROPY_HW_RCC_RTC_CLKSOURCE (RCC_RTCCLKSOURCE_LSI) +#define MICROPY_HW_RCC_FMC_CLKSOURCE (RCC_FMCCLKSOURCE_PLL2) +#define MICROPY_HW_RCC_RNG_CLKSOURCE (RCC_RNGCLKSOURCE_HSI48) +#define MICROPY_HW_RCC_ADC_CLKSOURCE (RCC_ADCCLKSOURCE_PLL3) +#define MICROPY_HW_RCC_SDMMC_CLKSOURCE (RCC_SDMMCCLKSOURCE_PLL) +#define MICROPY_HW_RCC_FDCAN_CLKSOURCE (RCC_FDCANCLKSOURCE_PLL) +#define MICROPY_HW_RCC_SPI123_CLKSOURCE (RCC_SPI123CLKSOURCE_PLL3) +#define MICROPY_HW_RCC_I2C123_CLKSOURCE (RCC_I2C123CLKSOURCE_D2PCLK1) +#define MICROPY_HW_RCC_QSPI_CLKSOURCE (RCC_QSPICLKSOURCE_PLL2) + +// SMPS configuration +#define MICROPY_HW_PWR_SMPS_CONFIG (PWR_SMPS_1V8_SUPPLIES_LDO) + +// Configure the analog switches for dual-pad pins. +#define MICROPY_HW_ANALOG_SWITCH_PA0 (SYSCFG_SWITCH_PA0_OPEN) +#define MICROPY_HW_ANALOG_SWITCH_PA1 (SYSCFG_SWITCH_PA1_OPEN) +#define MICROPY_HW_ANALOG_SWITCH_PC2 (SYSCFG_SWITCH_PC2_OPEN) +#define MICROPY_HW_ANALOG_SWITCH_PC3 (SYSCFG_SWITCH_PC3_OPEN) + +// There is an external 32kHz xtal +// #define RTC_ASYNCH_PREDIV (0) +// #define RTC_SYNCH_PREDIV (0x7fff) +// #define MICROPY_HW_RTC_USE_BYPASS (0) +// #define MICROPY_HW_RTC_USE_US (1) +// #define MICROPY_HW_RTC_USE_CALOUT (1) + +#if (MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE == 0) +// QSPI flash #1 for storage +#define MICROPY_HW_QSPI_PRESCALER (2) // 100MHz +#define MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2 (27) +// Reserve 1MiB at the end for compatibility with alternate firmware that places WiFi blob here. +#define MICROPY_HW_SPIFLASH_SIZE_BITS (120 * 1024 * 1024) +#define MICROPY_HW_QSPIFLASH_CS (pyb_pin_QSPI2_CS) +#define MICROPY_HW_QSPIFLASH_SCK (pyb_pin_QSPI2_CLK) +#define MICROPY_HW_QSPIFLASH_IO0 (pyb_pin_QSPI2_D0) +#define MICROPY_HW_QSPIFLASH_IO1 (pyb_pin_QSPI2_D1) +#define MICROPY_HW_QSPIFLASH_IO2 (pyb_pin_QSPI2_D2) +#define MICROPY_HW_QSPIFLASH_IO3 (pyb_pin_QSPI2_D3) + +// SPI flash #1, block device config +extern const struct _mp_spiflash_config_t spiflash_config; +extern struct _spi_bdev_t spi_bdev; +#define MICROPY_HW_BDEV_SPIFLASH (&spi_bdev) +#define MICROPY_HW_BDEV_SPIFLASH_CONFIG (&spiflash_config) +#define MICROPY_HW_BDEV_SPIFLASH_SIZE_BYTES (MICROPY_HW_SPIFLASH_SIZE_BITS / 8) +#define MICROPY_HW_BDEV_SPIFLASH_EXTENDED (&spi_bdev) +#endif + +// 4 wait states +#define MICROPY_HW_FLASH_LATENCY FLASH_LATENCY_2 + +// UART config +#define MICROPY_HW_UART1_TX (pin_A9) +#define MICROPY_HW_UART1_RX (pin_A10) +#define MICROPY_HW_UART_REPL PYB_UART_1 +#define MICROPY_HW_UART_REPL_BAUD 115200 + +// UART config +#define MICROPY_HW_UART8_TX (pin_J8) +#define MICROPY_HW_UART8_RX (pin_J9) + +// UART7 config +// #define MICROPY_HW_UART7_TX (pyb_pin_BT_TXD) +// #define MICROPY_HW_UART7_RX (pyb_pin_BT_RXD) +// #define MICROPY_HW_UART7_RTS (pyb_pin_BT_RTS) +// #define MICROPY_HW_UART7_CTS (pyb_pin_BT_CTS) + +// I2C buses +#define MICROPY_HW_I2C1_SCL (pin_B6) +#define MICROPY_HW_I2C1_SDA (pin_B7) + +#define MICROPY_HW_I2C3_SCL (pin_H7) +#define MICROPY_HW_I2C3_SDA (pin_H8) + +// SPI buses +#define MICROPY_HW_SPI1_NSS (pin_C13) +#define MICROPY_HW_SPI1_SCK (pin_B3) +#define MICROPY_HW_SPI1_MISO (pin_B4) +#define MICROPY_HW_SPI1_MOSI (pin_D7) + +#define MICROPY_HW_SPI2_NSS (pin_I0) +#define MICROPY_HW_SPI2_SCK (pin_I1) +#define MICROPY_HW_SPI2_MISO (pin_C2) +#define MICROPY_HW_SPI2_MOSI (pin_C3) + +// USRSW is pulled low. Pressing the button makes the input go high. +#define MICROPY_HW_USRSW_PIN (pin_C13) +#define MICROPY_HW_USRSW_PULL (GPIO_NOPULL) +#define MICROPY_HW_USRSW_EXTI_MODE (GPIO_MODE_IT_RISING) +#define MICROPY_HW_USRSW_PRESSED (1) + +// LEDs +#define MICROPY_HW_LED1 (pyb_pin_LED_RED) // red +#define MICROPY_HW_LED2 (pyb_pin_LED_GREEN) // green +#define MICROPY_HW_LED3 (pyb_pin_LED_BLUE) // yellow +#define MICROPY_HW_LED_ON(pin) (mp_hal_pin_low(pin)) +#define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_high(pin)) + +// SD Card SDMMC +#define MICROPY_HW_SDCARD_SDMMC (2) +#define MICROPY_HW_SDCARD_CK (pin_D6) +#define MICROPY_HW_SDCARD_CMD (pin_D7) +#define MICROPY_HW_SDCARD_D0 (pin_B14) +#define MICROPY_HW_SDCARD_D1 (pin_B15) +#define MICROPY_HW_SDCARD_D2 (pin_B3) +#define MICROPY_HW_SDCARD_D3 (pin_B4) +#define MICROPY_HW_SDCARD_MOUNT_AT_BOOT (0) + +// FDCAN bus +#define MICROPY_HW_CAN1_NAME "FDCAN1" +#define MICROPY_HW_CAN1_TX (pin_H13) +#define MICROPY_HW_CAN1_RX (pin_B8) + +// USB config +#define MICROPY_HW_USB_HS (1) +#define MICROPY_HW_USB_HS_ULPI_NXT (pin_H4) +#define MICROPY_HW_USB_HS_ULPI_STP (pin_C0) +#define MICROPY_HW_USB_HS_ULPI_DIR (pin_I11) +#define MICROPY_HW_USB_HS_ULPI3320 (1) + +#define MICROPY_HW_USB_CDC_RX_DATA_SIZE (1024) +#define MICROPY_HW_USB_CDC_TX_DATA_SIZE (1024) +#define MICROPY_HW_USB_CDC_1200BPS_TOUCH (1) +#define GPIO_AF10_OTG_HS (GPIO_AF10_OTG2_HS) + + +// SDRAM +#define MICROPY_HW_SDRAM_SIZE (64 / 8 * 1024 * 1024) // 64 Mbit +#define MICROPY_HW_SDRAM_STARTUP_TEST (1) +#define MICROPY_HW_SDRAM_TEST_FAIL_ON_ERROR (true) +#define MICROPY_HW_FMC_SWAP_BANKS (1) + +// Timing configuration for 200MHz/2=100MHz (10ns) +#define MICROPY_HW_SDRAM_CLOCK_PERIOD 2 +#define MICROPY_HW_SDRAM_CAS_LATENCY 2 +#define MICROPY_HW_SDRAM_FREQUENCY (100000) // 100 MHz +#define MICROPY_HW_SDRAM_TIMING_TMRD (2) +#define MICROPY_HW_SDRAM_TIMING_TXSR (7) +#define MICROPY_HW_SDRAM_TIMING_TRAS (5) +#define MICROPY_HW_SDRAM_TIMING_TRC (7) +#define MICROPY_HW_SDRAM_TIMING_TWR (2) +#define MICROPY_HW_SDRAM_TIMING_TRP (3) +#define MICROPY_HW_SDRAM_TIMING_TRCD (3) + +#define MICROPY_HW_SDRAM_ROW_BITS_NUM 12 +#define MICROPY_HW_SDRAM_MEM_BUS_WIDTH 16 +#define MICROPY_HW_SDRAM_REFRESH_CYCLES 4096 + +#define MICROPY_HW_SDRAM_COLUMN_BITS_NUM 8 +#define MICROPY_HW_SDRAM_INTERN_BANKS_NUM 4 +#define MICROPY_HW_SDRAM_RPIPE_DELAY 0 +#define MICROPY_HW_SDRAM_RBURST (1) +#define MICROPY_HW_SDRAM_WRITE_PROTECTION (0) + +#define MICROPY_HW_SDRAM_AUTOREFRESH_NUM (8) +#define MICROPY_HW_SDRAM_BURST_LENGTH 1 +#define MICROPY_HW_SDRAM_REFRESH_RATE (64) // ms + +// SDRAM configuration +#define MICROPY_HW_FMC_SDCKE0 (pin_H2) +#define MICROPY_HW_FMC_SDNE0 (pin_H3) +#define MICROPY_HW_FMC_SDNBL0 (pin_E0) +#define MICROPY_HW_FMC_SDNBL1 (pin_E1) +#define MICROPY_HW_FMC_SDCLK (pin_G8) +#define MICROPY_HW_FMC_SDNCAS (pin_G15) +#define MICROPY_HW_FMC_SDNRAS (pin_F11) +#define MICROPY_HW_FMC_SDNWE (pin_H5) +#define MICROPY_HW_FMC_BA0 (pin_G4) +#define MICROPY_HW_FMC_BA1 (pin_G5) +#define MICROPY_HW_FMC_NBL0 (pin_E0) +#define MICROPY_HW_FMC_NBL1 (pin_E1) +#define MICROPY_HW_FMC_A0 (pin_F0) +#define MICROPY_HW_FMC_A1 (pin_F1) +#define MICROPY_HW_FMC_A2 (pin_F2) +#define MICROPY_HW_FMC_A3 (pin_F3) +#define MICROPY_HW_FMC_A4 (pin_F4) +#define MICROPY_HW_FMC_A5 (pin_F5) +#define MICROPY_HW_FMC_A6 (pin_F12) +#define MICROPY_HW_FMC_A7 (pin_F13) +#define MICROPY_HW_FMC_A8 (pin_F14) +#define MICROPY_HW_FMC_A9 (pin_F15) +#define MICROPY_HW_FMC_A10 (pin_G0) +#define MICROPY_HW_FMC_A11 (pin_G1) +#define MICROPY_HW_FMC_A12 (pin_G2) +#define MICROPY_HW_FMC_D0 (pin_D14) +#define MICROPY_HW_FMC_D1 (pin_D15) +#define MICROPY_HW_FMC_D2 (pin_D0) +#define MICROPY_HW_FMC_D3 (pin_D1) +#define MICROPY_HW_FMC_D4 (pin_E7) +#define MICROPY_HW_FMC_D5 (pin_E8) +#define MICROPY_HW_FMC_D6 (pin_E9) +#define MICROPY_HW_FMC_D7 (pin_E10) +#define MICROPY_HW_FMC_D8 (pin_E11) +#define MICROPY_HW_FMC_D9 (pin_E12) +#define MICROPY_HW_FMC_D10 (pin_E13) +#define MICROPY_HW_FMC_D11 (pin_E14) +#define MICROPY_HW_FMC_D12 (pin_E15) +#define MICROPY_HW_FMC_D13 (pin_D8) +#define MICROPY_HW_FMC_D14 (pin_D9) +#define MICROPY_HW_FMC_D15 (pin_D10) + +// Ethernet via RMII +#define MICROPY_HW_ETH_MDC (pin_C1) +#define MICROPY_HW_ETH_MDIO (pin_A2) +#define MICROPY_HW_ETH_RMII_REF_CLK (pin_A1) +#define MICROPY_HW_ETH_RMII_CRS_DV (pin_A7) +#define MICROPY_HW_ETH_RMII_RXD0 (pin_C4) +#define MICROPY_HW_ETH_RMII_RXD1 (pin_C5) +#define MICROPY_HW_ETH_RMII_TX_EN (pin_G11) +#define MICROPY_HW_ETH_RMII_TXD0 (pin_G13) +#define MICROPY_HW_ETH_RMII_TXD1 (pin_G12) + +// #define MICROPY_HW_USB_VID 0x2341 +// #define MICROPY_HW_USB_PID 0x055B +// #define MICROPY_HW_USB_PID_CDC_MSC (MICROPY_HW_USB_PID) +// #define MICROPY_HW_USB_PID_CDC_HID (MICROPY_HW_USB_PID) +// #define MICROPY_HW_USB_PID_CDC (MICROPY_HW_USB_PID) +// #define MICROPY_HW_USB_PID_MSC (MICROPY_HW_USB_PID) +// #define MICROPY_HW_USB_PID_CDC2_MSC (MICROPY_HW_USB_PID) +// #define MICROPY_HW_USB_PID_CDC2 (MICROPY_HW_USB_PID) +// #define MICROPY_HW_USB_PID_CDC3 (MICROPY_HW_USB_PID) +// #define MICROPY_HW_USB_PID_CDC3_MSC (MICROPY_HW_USB_PID) +// #define MICROPY_HW_USB_PID_CDC_MSC_HID (MICROPY_HW_USB_PID) +// #define MICROPY_HW_USB_PID_CDC2_MSC_HID (MICROPY_HW_USB_PID) +// #define MICROPY_HW_USB_PID_CDC3_MSC_HID (MICROPY_HW_USB_PID) +// #define MICROPY_HW_USB_LANGID_STRING 0x409 +// #define MICROPY_HW_USB_MANUFACTURER_STRING "Arduino" +// #define MICROPY_HW_USB_PRODUCT_FS_STRING "Portenta Virtual Comm Port in FS Mode" +// #define MICROPY_HW_USB_PRODUCT_HS_STRING "Portenta Virtual Comm Port in HS Mode" +// #define MICROPY_HW_USB_INTERFACE_FS_STRING "Portenta Interface" +// #define MICROPY_HW_USB_INTERFACE_HS_STRING "Portenta Interface" +// #define MICROPY_HW_USB_CONFIGURATION_FS_STRING "Portenta Config" +// #define MICROPY_HW_USB_CONFIGURATION_HS_STRING "Portenta Config" diff --git a/ports/stm32/boards/STM32H747I-DISCO/mpconfigboard.mk b/ports/stm32/boards/STM32H747I-DISCO/mpconfigboard.mk new file mode 100644 index 0000000000000..1b3fb6941755a --- /dev/null +++ b/ports/stm32/boards/STM32H747I-DISCO/mpconfigboard.mk @@ -0,0 +1,30 @@ +# For dual core HAL drivers. +CFLAGS += -DCORE_CM7 + +USE_MBOOT ?= 0 + +# MCU settings +MCU_SERIES = h7 +CMSIS_MCU = STM32H747xx +MICROPY_FLOAT_IMPL = double +AF_FILE = boards/stm32h743_af.csv + +ifeq ($(USE_MBOOT),1) +# When using Mboot all the text goes together after the filesystem +LD_FILES = boards/STM32H747I-DISCO/stm32h747.ld boards/common_blifs.ld +TEXT0_ADDR = 0x08020000 +else +# When not using Mboot the ISR text goes first, then the rest after the filesystem +LD_FILES = boards/STM32H747I-DISCO/stm32h747.ld boards/common_ifs.ld +TEXT0_ADDR = 0x08000000 +endif + +# MicroPython settings +MICROPY_PY_LWIP = 1 +MICROPY_PY_SSL = 1 +MICROPY_SSL_MBEDTLS = 1 +#MICROPY_PY_OPENAMP = 1 +#MICROPY_PY_OPENAMP_REMOTEPROC = 1 + +FROZEN_MANIFEST = $(BOARD_DIR)/manifest.py +# MBEDTLS_CONFIG_FILE = '"$(BOARD_DIR)/mbedtls_config_board.h"' diff --git a/ports/stm32/boards/STM32H747I-DISCO/pins.csv b/ports/stm32/boards/STM32H747I-DISCO/pins.csv new file mode 100644 index 0000000000000..4ce1085712114 --- /dev/null +++ b/ports/stm32/boards/STM32H747I-DISCO/pins.csv @@ -0,0 +1,254 @@ +PA0,PA0 +PA1,PA1 +PA2,-PA2 +PA3,-PA3 +PA4,PA4 +PA5,-PA5 +PA6,-PA6 +PA7,-PA7 +PA8,PA8 +PA9,PA9 +PA10,PA10 +PA11,PA11 +PA12,PA12 +PA13,PA13 +PA14,PA14 +PA15,PA15 +PB0,-PB0 +PB1,-PB1 +PB2,PB2 +PB3,PB3 +PB4,PB4 +PB5,PB5 +PB6,PB6 +PB7,PB7 +PB8,PB8 +PB9,PB9 +PB10,PB10 +PB11,PB11 +PB12,PB12 +PB13,PB13 +PB14,PB14 +PB15,PB15 +PC0,-PC0 +PC1,-PC1 +PC2,PC2 +PC3,PC3 +PC4,-PC4 +PC5,-PC5 +PC6,PC6 +PC7,PC7 +PC8,PC8 +PC9,PC9 +PC10,PC10 +PC11,PC11 +PC12,PC12 +PC13,PC13 +PC14,PC14 +PC15,PC15 +PD0,PD0 +PD1,PD1 +PD2,PD2 +PD3,PD3 +PD4,PD4 +PD5,PD5 +PD6,PD6 +PD7,PD7 +PD8,PD8 +PD9,PD9 +PD10,PD10 +PD11,PD11 +PD12,PD12 +PD13,PD13 +PD14,PD14 +PD15,PD15 +PE0,PE0 +PE1,PE1 +PE2,PE2 +PE3,PE3 +PE4,PE4 +PE5,PE5 +PE6,PE6 +PE7,PE7 +PE8,PE8 +PE9,PE9 +PE10,PE10 +PE11,PE11 +PE12,PE12 +PE13,PE13 +PE14,PE14 +PE15,PE15 +PF0,PF0 +PF1,PF1 +PF2,PF2 +PF3,-PF3 +PF4,-PF4 +PF5,-PF5 +PF6,-PF6 +PF7,-PF7 +PF8,-PF8 +PF9,-PF9 +PF10,-PF10 +PF11,-PF11 +PF12,PF12 +PF13,PF13 +PF14,-PF14 +PF15,PF15 +PG0,PG0 +PG1,PG1 +PG2,PG2 +PG3,PG3 +PG4,PG4 +PG5,PG5 +PG6,PG6 +PG7,PG7 +PG8,PG8 +PG9,PG9 +PG10,PG10 +PG11,PG11 +PG12,PG12 +PG13,PG13 +PG14,PG14 +PG15,PG15 +PH0,PH0 +PH1,PH1 +PH2,-PH2 +PH3,-PH3 +PH4,-PH4 +PH5,-PH5 +PH6,PH6 +PH7,PH7 +PH8,PH8 +PH9,PH9 +PH10,PH10 +PH11,PH11 +PH12,PH12 +PH13,PH13 +PH14,PH14 +PH15,PH15 +PI0,PI0 +PI1,PI1 +PI2,PI2 +PI3,PI3 +PI4,PI4 +PI5,PI5 +PI6,PI6 +PI7,PI7 +PI8,PI8 +PI9,PI9 +PI10,PI10 +PI11,PI11 +PI12,PI12 +PI13,PI13 +PI14,PI14 +PI15,PI15 +PJ0,PJ0 +PJ1,PJ1 +PJ2,PJ2 +PJ3,PJ3 +PJ4,PJ4 +PJ5,PJ5 +PJ6,PJ6 +PJ7,PJ7 +PJ8,PJ8 +PJ9,PJ9 +PJ10,PJ10 +PJ11,PJ11 +PJ12,PJ12 +PJ13,PJ13 +PJ14,PJ14 +PJ15,PJ15 +PK0,PK0 +PK1,PK1 +PK2,PK2 +PK3,PK3 +PK4,PK4 +PK5,PK5 +PK6,PK6 +PK7,PK7 + +# Arduino Digital Pins +D0,PH15 +D1,PK1 +D2,PJ11 +D3,PG7 +D4,PC7 +D5,PC6 +D6,PA8 +D7,PI0 +D8,PC3 +D9,PI1 +D10,PC2 +D11,PH8 +D12,PH7 +D13,PA10 +D14,PA9 +D20,PC3 +D21,PA4 + +# Arduino Analog Pins +A0,PA0_C +A1,PA1_C +A2,PC2_C +A3,PC3_C +A4,PC2 +A5,PC3 +A6,PA4 +A7,PA6 + +UART1_TX,PA9 +UART1_RX,PA10 +UART4_TX,PA0 +UART4_RX,PI9 +UART6_TX,PG14 +UART6_RX,PG9 +UART8_TX,PJ8 +UART8_RX,PJ9 +-ETH_RST,PJ15 +-ETH_RMII_REF_CLK,PA1 +-ETH_MDIO,-PA2 +-ETH_RMII_CRS_DV,-PA7 +-ETH_MDC,-PC1 +-ETH_RMII_RXD0,-PC4 +-ETH_RMII_RXD1,-PC5 +-ETH_RMII_TX_EN,PG11 +-ETH_RMII_TXD0,PG13 +-ETH_RMII_TXD1,PG12 +-USB_HS_CLK,-PA5 +-USB_HS_STP,-PC0 +-USB_HS_NXT,-PH4 +-USB_HS_DIR,PI11 +-USB_HS_D0,-PA3 +-USB_HS_D1,-PB0 +-USB_HS_D2,-PB1 +-USB_HS_D3,PB10 +-USB_HS_D4,PB11 +-USB_HS_D5,PB12 +-USB_HS_D6,PB13 +-USB_HS_D7,PB5 +-USB_HS_RST,PJ4 +-USB_DM,PA11 +-USB_DP,PA12 +#BOOT0,BOOT0 +OSCEN,PH1 +DAC1,PA4 +DAC2,-PA5 +I2C1_SDA,PB7 +I2C1_SCL,PB6 +I2C3_SDA,PH8 +I2C3_SCL,PH7 +-QSPI2_CS,PG6 +-QSPI2_CLK,-PF10 +-QSPI2_D0,PD11 +-QSPI2_D1,PD12 +-QSPI2_D2,-PF7 +-QSPI2_D3,PD13 +-SE05X_EN,-PI12 + +LEDR,PI12 +LEDG,PI13 +LEDB,PI14 +LED_RED,PI12 +LED_GREEN,PI13 +LED_BLUE,PI14 +LED_BUILTIN,PI15 \ No newline at end of file diff --git a/ports/stm32/boards/STM32H747I-DISCO/stm32h747.ld b/ports/stm32/boards/STM32H747I-DISCO/stm32h747.ld new file mode 100644 index 0000000000000..99e0caa81388a --- /dev/null +++ b/ports/stm32/boards/STM32H747I-DISCO/stm32h747.ld @@ -0,0 +1,50 @@ +/* + GNU linker script for STM32H747 +*/ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 2048K /* Total available flash */ + FLASH_START (rx) : ORIGIN = 0x08000000, LENGTH = 128K /* bootloader if installed */ + /*FLASH_FS (r) : ORIGIN = 0x08020000, LENGTH = 128K */ /* filesystem */ + FLASH_TEXT (rx) : ORIGIN = 0x08020000, LENGTH = 1408K /* CM7 firmware */ + FLASH_CM4 (rx) : ORIGIN = 0x08180000, LENGTH = 512K /* CM4 firmware */ + FLASH_FS (rx) : ORIGIN = 0x90000000, LENGTH = 16384K /* 16MBs external QSPI flash */ + + ITCM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K + DTCM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K + RAM (xrw) : ORIGIN = 0x24000000, LENGTH = 512K /* AXI SRAM D1 */ + SRAM1 (xrw) : ORIGIN = 0x30000000, LENGTH = 128K /* SRAM1 D2 */ + SRAM2 (xrw) : ORIGIN = 0x30020000, LENGTH = 128K /* SRAM2 D2 */ + SRAM3 (xrw) : ORIGIN = 0x30040000, LENGTH = 32K /* SRAM3 D2 */ + SRAM4 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K /* SRAM4 D3 */ +} + +/* produce a link error if there is not this amount of RAM for these sections */ +_minimum_stack_size = 2K; +_minimum_heap_size = 16K; + +/* Define the stack. The stack is full descending so begins just above last byte + of RAM. Note that EABI requires the stack to be 8-byte aligned for a call. */ +_estack = ORIGIN(RAM) + LENGTH(RAM) - _estack_reserve; +_sstack = _estack - 16K; /* tunable */ + +/* RAM extents for the garbage collector */ +_ram_start = ORIGIN(RAM); +_ram_end = ORIGIN(RAM) + LENGTH(RAM); +_heap_start = _ebss; /* heap starts just after statically allocated memory */ +_heap_end = _sstack; + +/* Note the following varilables are only used if the filesystem flash storage is enabled */ +/* Location of filesystem RAM cache */ +_micropy_hw_internal_flash_storage_ram_cache_start = ORIGIN(DTCM); +_micropy_hw_internal_flash_storage_ram_cache_end = ORIGIN(DTCM) + LENGTH(DTCM); + +/* Location of filesystem flash storage */ +_micropy_hw_internal_flash_storage_start = ORIGIN(FLASH_FS); +_micropy_hw_internal_flash_storage_end = ORIGIN(FLASH_FS) + LENGTH(FLASH_FS); + +/* OpenAMP shared memory region */ +_openamp_shm_region_start = ORIGIN(SRAM4); +_openamp_shm_region_end = ORIGIN(SRAM4) + LENGTH(SRAM4); diff --git a/ports/stm32/boards/STM32H747I-DISCO/stm32h7xx_hal_conf.h b/ports/stm32/boards/STM32H747I-DISCO/stm32h7xx_hal_conf.h new file mode 100644 index 0000000000000..7576caa836eb6 --- /dev/null +++ b/ports/stm32/boards/STM32H747I-DISCO/stm32h7xx_hal_conf.h @@ -0,0 +1,51 @@ +/* This file is part of the MicroPython project, http://micropython.org/ + * The MIT License (MIT) + * Copyright (c) 2024 Andrew Leech + */ +#ifndef MICROPY_INCLUDED_STM32H7XX_HAL_CONF_H +#define MICROPY_INCLUDED_STM32H7XX_HAL_CONF_H + +// Oscillator values in Hz +#define HSE_VALUE (25000000) +#define LSE_VALUE (32768) +#define EXTERNAL_CLOCK_VALUE (12288000) + +// Oscillator timeouts in ms +#define HSE_STARTUP_TIMEOUT (5000) +#define LSE_STARTUP_TIMEOUT (5000) + +#define DATA_CACHE_ENABLE 1 +#define INSTRUCTION_CACHE_ENABLE 1 +#define DATA_CACHE_ENABLE 1 +#define INSTRUCTION_CACHE_ENABLE 1 +#define PREFETCH_ENABLE 1 +#define USE_RTOS 0 + +#define HAL_HSEM_MODULE_ENABLED +#define HAL_JPEG_MODULE_ENABLED +#define HAL_LPTIM_MODULE_ENABLED +#define HAL_LTDC_MODULE_ENABLED +#define HAL_MDIOS_MODULE_ENABLED +#define HAL_MDMA_MODULE_ENABLED +#define HAL_MMC_MODULE_ENABLED +#define HAL_NAND_MODULE_ENABLED +#define HAL_OPAMP_MODULE_ENABLED +#define HAL_QSPI_MODULE_ENABLED +#define HAL_RNG_MODULE_ENABLED +#define HAL_SAI_MODULE_ENABLED +#define HAL_SMBUS_MODULE_ENABLED +#define HAL_SPDIFRX_MODULE_ENABLED +#define HAL_SRAM_MODULE_ENABLED +#define HAL_SWPMI_MODULE_ENABLED + +#ifdef HAL_HSEM_MODULE_ENABLED +#include "stm32h7xx_hal_hsem.h" +#endif + +#ifdef HAL_MMC_MODULE_ENABLED +#include "stm32h7xx_hal_mmc.h" +#endif + +#include "boards/stm32h7xx_hal_conf_base.h" + +#endif // MICROPY_INCLUDED_STM32H7XX_HAL_CONF_H