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+Arty-A7 board +::: + +The following instructions explain how to set up the board. +For FPGA digital design documentation for this board, refer to the [Digital design](build/arty/documentation/index.rst) chapter. + +## Board configuration + +Connect the board USB and Ethernet cables to your computer and configure the network. +The bitstream will be loaded from flash memory upon device power-on or after pressing the PROG button. diff --git a/_sources/build/arty/documentation/controller_settings.rst.txt b/_sources/build/arty/documentation/controller_settings.rst.txt new file mode 100644 index 000000000..cc67b4b83 --- /dev/null +++ b/_sources/build/arty/documentation/controller_settings.rst.txt @@ -0,0 +1,34 @@ +CONTROLLER_SETTINGS +=================== + +Allows to change LiteDRAMController behaviour at runtime +-------------------------------------------------------- + + +Register Listing for CONTROLLER_SETTINGS +---------------------------------------- + ++------------------------------------------------------------------+-------------------------------------------------+ +| Register | Address | ++==================================================================+=================================================+ +| :ref:`CONTROLLER_SETTINGS_REFRESH ` | :ref:`0xf0001000 ` | ++------------------------------------------------------------------+-------------------------------------------------+ + +CONTROLLER_SETTINGS_REFRESH +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0001000 + 0x0 = 0xf0001000` + + Enable/disable Refresh commands sending + + .. wavedrom:: + :caption: CONTROLLER_SETTINGS_REFRESH + + { + "reg": [ + {"name": "refresh", "attr": 'reset: 1', "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/arty/documentation/ctrl.rst.txt b/_sources/build/arty/documentation/ctrl.rst.txt new file mode 100644 index 000000000..8e9663760 --- /dev/null +++ b/_sources/build/arty/documentation/ctrl.rst.txt @@ -0,0 +1,78 @@ +CTRL +==== + +Register Listing for CTRL +------------------------- + ++------------------------------------------+-------------------------------------+ +| Register | Address | ++==========================================+=====================================+ +| :ref:`CTRL__RESET ` | :ref:`0xf0005000 ` | ++------------------------------------------+-------------------------------------+ +| :ref:`CTRL_SCRATCH ` | :ref:`0xf0005004 ` | ++------------------------------------------+-------------------------------------+ +| :ref:`CTRL_BUS_ERRORS ` | :ref:`0xf0005008 ` | ++------------------------------------------+-------------------------------------+ + +CTRL__RESET +^^^^^^^^^^^ + +`Address: 0xf0005000 + 0x0 = 0xf0005000` + + + .. wavedrom:: + :caption: CTRL__RESET + + { + "reg": [ + {"name": "soc_rst", "type": 4, "bits": 1}, + {"name": "cpu_rst", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+---------+------------------------------------------------------------------------+ +| Field | Name | Description | ++=======+=========+========================================================================+ +| [0] | SOC_RST | Write `1` to this register to reset the full SoC (Pulse Reset) | ++-------+---------+------------------------------------------------------------------------+ +| [1] | CPU_RST | Write `1` to this register to reset the CPU(s) of the SoC (Hold Reset) | ++-------+---------+------------------------------------------------------------------------+ + +CTRL_SCRATCH +^^^^^^^^^^^^ + +`Address: 0xf0005000 + 0x4 = 0xf0005004` + + Use this register as a scratch space to verify that software read/write accesses + to the Wishbone/CSR bus are working correctly. The initial reset value of + 0x1234578 can be used to verify endianness. + + .. wavedrom:: + :caption: CTRL_SCRATCH + + { + "reg": [ + {"name": "scratch[31:0]", "attr": 'reset: 305419896', "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +CTRL_BUS_ERRORS +^^^^^^^^^^^^^^^ + +`Address: 0xf0005000 + 0x8 = 0xf0005008` + + Total number of Wishbone bus errors (timeouts) since start. + + .. wavedrom:: + :caption: CTRL_BUS_ERRORS + + { + "reg": [ + {"name": "bus_errors[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/arty/documentation/ddrctrl.rst.txt b/_sources/build/arty/documentation/ddrctrl.rst.txt new file mode 100644 index 000000000..59563d8b1 --- /dev/null +++ b/_sources/build/arty/documentation/ddrctrl.rst.txt @@ -0,0 +1,48 @@ +DDRCTRL +======= + +Register Listing for DDRCTRL +---------------------------- + ++------------------------------------------------+----------------------------------------+ +| Register | Address | ++================================================+========================================+ +| :ref:`DDRCTRL_INIT_DONE ` | :ref:`0xf0001800 ` | ++------------------------------------------------+----------------------------------------+ +| :ref:`DDRCTRL_INIT_ERROR ` | :ref:`0xf0001804 ` | ++------------------------------------------------+----------------------------------------+ + +DDRCTRL_INIT_DONE +^^^^^^^^^^^^^^^^^ + +`Address: 0xf0001800 + 0x0 = 0xf0001800` + + + .. wavedrom:: + :caption: DDRCTRL_INIT_DONE + + { + "reg": [ + {"name": "init_done", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRCTRL_INIT_ERROR +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0001800 + 0x4 = 0xf0001804` + + + .. wavedrom:: + :caption: DDRCTRL_INIT_ERROR + + { + "reg": [ + {"name": "init_error", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/arty/documentation/ddrphy.rst.txt b/_sources/build/arty/documentation/ddrphy.rst.txt new file mode 100644 index 000000000..75b3571a6 --- /dev/null +++ b/_sources/build/arty/documentation/ddrphy.rst.txt @@ -0,0 +1,257 @@ +DDRPHY +====== + +Register Listing for DDRPHY +--------------------------- + ++----------------------------------------------------------------+------------------------------------------------+ +| Register | Address | ++================================================================+================================================+ +| :ref:`DDRPHY_RST ` | :ref:`0xf0000800 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_DLY_SEL ` | :ref:`0xf0000804 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_HALF_SYS8X_TAPS ` | :ref:`0xf0000808 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_WLEVEL_EN ` | :ref:`0xf000080c ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_WLEVEL_STROBE ` | :ref:`0xf0000810 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_RDLY_DQ_RST ` | :ref:`0xf0000814 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_RDLY_DQ_INC ` | :ref:`0xf0000818 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_RDLY_DQ_BITSLIP_RST ` | :ref:`0xf000081c ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_RDLY_DQ_BITSLIP ` | :ref:`0xf0000820 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_WDLY_DQ_BITSLIP_RST ` | :ref:`0xf0000824 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_WDLY_DQ_BITSLIP ` | :ref:`0xf0000828 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_RDPHASE ` | :ref:`0xf000082c ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_WRPHASE ` | :ref:`0xf0000830 ` | ++----------------------------------------------------------------+------------------------------------------------+ + +DDRPHY_RST +^^^^^^^^^^ + +`Address: 0xf0000800 + 0x0 = 0xf0000800` + + + .. wavedrom:: + :caption: DDRPHY_RST + + { + "reg": [ + {"name": "rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_DLY_SEL +^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x4 = 0xf0000804` + + + .. wavedrom:: + :caption: DDRPHY_DLY_SEL + + { + "reg": [ + {"name": "dly_sel[1:0]", "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_HALF_SYS8X_TAPS +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x8 = 0xf0000808` + + + .. wavedrom:: + :caption: DDRPHY_HALF_SYS8X_TAPS + + { + "reg": [ + {"name": "half_sys8x_taps[4:0]", "attr": 'reset: 8', "bits": 5}, + {"bits": 27}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_WLEVEL_EN +^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xc = 0xf000080c` + + + .. wavedrom:: + :caption: DDRPHY_WLEVEL_EN + + { + "reg": [ + {"name": "wlevel_en", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_WLEVEL_STROBE +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x10 = 0xf0000810` + + + .. wavedrom:: + :caption: DDRPHY_WLEVEL_STROBE + + { + "reg": [ + {"name": "wlevel_strobe", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_RDLY_DQ_RST +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x14 = 0xf0000814` + + + .. wavedrom:: + :caption: DDRPHY_RDLY_DQ_RST + + { + "reg": [ + {"name": "rdly_dq_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_RDLY_DQ_INC +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x18 = 0xf0000818` + + + .. wavedrom:: + :caption: DDRPHY_RDLY_DQ_INC + + { + "reg": [ + {"name": "rdly_dq_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_RDLY_DQ_BITSLIP_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x1c = 0xf000081c` + + + .. wavedrom:: + :caption: DDRPHY_RDLY_DQ_BITSLIP_RST + + { + "reg": [ + {"name": "rdly_dq_bitslip_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_RDLY_DQ_BITSLIP +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x20 = 0xf0000820` + + + .. wavedrom:: + :caption: DDRPHY_RDLY_DQ_BITSLIP + + { + "reg": [ + {"name": "rdly_dq_bitslip", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_WDLY_DQ_BITSLIP_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x24 = 0xf0000824` + + + .. wavedrom:: + :caption: DDRPHY_WDLY_DQ_BITSLIP_RST + + { + "reg": [ + {"name": "wdly_dq_bitslip_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_WDLY_DQ_BITSLIP +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x28 = 0xf0000828` + + + .. wavedrom:: + :caption: DDRPHY_WDLY_DQ_BITSLIP + + { + "reg": [ + {"name": "wdly_dq_bitslip", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_RDPHASE +^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x2c = 0xf000082c` + + + .. wavedrom:: + :caption: DDRPHY_RDPHASE + + { + "reg": [ + {"name": "rdphase[1:0]", "attr": 'reset: 2', "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_WRPHASE +^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x30 = 0xf0000830` + + + .. wavedrom:: + :caption: DDRPHY_WRPHASE + + { + "reg": [ + {"name": "wrphase[1:0]", "attr": 'reset: 3', "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/arty/documentation/dfi_switch.rst.txt b/_sources/build/arty/documentation/dfi_switch.rst.txt new file mode 100644 index 000000000..595b322c3 --- /dev/null +++ b/_sources/build/arty/documentation/dfi_switch.rst.txt @@ -0,0 +1,71 @@ +DFI_SWITCH +========== + +Register Listing for DFI_SWITCH +------------------------------- + ++--------------------------------------------------------------+-----------------------------------------------+ +| Register | Address | ++==============================================================+===============================================+ +| :ref:`DFI_SWITCH_REFRESH_COUNT ` | :ref:`0xf0004000 ` | ++--------------------------------------------------------------+-----------------------------------------------+ +| :ref:`DFI_SWITCH_AT_REFRESH ` | :ref:`0xf0004004 ` | ++--------------------------------------------------------------+-----------------------------------------------+ +| :ref:`DFI_SWITCH_REFRESH_UPDATE ` | :ref:`0xf0004008 ` | ++--------------------------------------------------------------+-----------------------------------------------+ + +DFI_SWITCH_REFRESH_COUNT +^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0004000 + 0x0 = 0xf0004000` + + Count of all refresh commands issued (both by Memory Controller and Payload + Executor). Value is latched from internal counter on mode trasition: MC -> PE or + by writing to the `refresh_update` CSR. + + .. wavedrom:: + :caption: DFI_SWITCH_REFRESH_COUNT + + { + "reg": [ + {"name": "refresh_count[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DFI_SWITCH_AT_REFRESH +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0004000 + 0x4 = 0xf0004004` + + If set to a value different than 0 the mode transition MC -> PE will be peformed + only when the value of this register matches the current refresh commands count. + + .. wavedrom:: + :caption: DFI_SWITCH_AT_REFRESH + + { + "reg": [ + {"name": "at_refresh[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DFI_SWITCH_REFRESH_UPDATE +^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0004000 + 0x8 = 0xf0004008` + + Force an update of the `refresh_count` CSR. + + .. wavedrom:: + :caption: DFI_SWITCH_REFRESH_UPDATE + + { + "reg": [ + {"name": "refresh_update", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/arty/documentation/ethphy.rst.txt b/_sources/build/arty/documentation/ethphy.rst.txt new file mode 100644 index 000000000..5e9c48d6b --- /dev/null +++ b/_sources/build/arty/documentation/ethphy.rst.txt @@ -0,0 +1,81 @@ +ETHPHY +====== + +Register Listing for ETHPHY +--------------------------- + ++--------------------------------------------+--------------------------------------+ +| Register | Address | ++============================================+======================================+ +| :ref:`ETHPHY_CRG_RESET ` | :ref:`0xf0002000 ` | ++--------------------------------------------+--------------------------------------+ +| :ref:`ETHPHY_MDIO_W ` | :ref:`0xf0002004 ` | ++--------------------------------------------+--------------------------------------+ +| :ref:`ETHPHY_MDIO_R ` | :ref:`0xf0002008 ` | ++--------------------------------------------+--------------------------------------+ + +ETHPHY_CRG_RESET +^^^^^^^^^^^^^^^^ + +`Address: 0xf0002000 + 0x0 = 0xf0002000` + + + .. wavedrom:: + :caption: ETHPHY_CRG_RESET + + { + "reg": [ + {"name": "crg_reset", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +ETHPHY_MDIO_W +^^^^^^^^^^^^^ + +`Address: 0xf0002000 + 0x4 = 0xf0002004` + + + .. wavedrom:: + :caption: ETHPHY_MDIO_W + + { + "reg": [ + {"name": "mdc", "bits": 1}, + {"name": "oe", "bits": 1}, + {"name": "w", "bits": 1}, + {"bits": 29} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------+ +| Field | Name | Description | ++=======+======+=============+ ++-------+------+-------------+ ++-------+------+-------------+ ++-------+------+-------------+ + +ETHPHY_MDIO_R +^^^^^^^^^^^^^ + +`Address: 0xf0002000 + 0x8 = 0xf0002008` + + + .. wavedrom:: + :caption: ETHPHY_MDIO_R + + { + "reg": [ + {"name": "r", "bits": 1}, + {"bits": 31} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------+ +| Field | Name | Description | ++=======+======+=============+ ++-------+------+-------------+ + diff --git a/_sources/build/arty/documentation/identifier_mem.rst.txt b/_sources/build/arty/documentation/identifier_mem.rst.txt new file mode 100644 index 000000000..982bd0102 --- /dev/null +++ b/_sources/build/arty/documentation/identifier_mem.rst.txt @@ -0,0 +1,30 @@ +IDENTIFIER_MEM +============== + +Register Listing for IDENTIFIER_MEM +----------------------------------- + ++----------------------------------------+------------------------------------+ +| Register | Address | ++========================================+====================================+ +| :ref:`IDENTIFIER_MEM ` | :ref:`0xf0005800 ` | ++----------------------------------------+------------------------------------+ + +IDENTIFIER_MEM +^^^^^^^^^^^^^^ + +`Address: 0xf0005800 + 0x0 = 0xf0005800` + + 8 x 110-bit memory + + .. wavedrom:: + :caption: IDENTIFIER_MEM + + { + "reg": [ + {"name": "identifier_mem[7:0]", "bits": 8}, + {"bits": 24}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/arty/documentation/index.rst.txt b/_sources/build/arty/documentation/index.rst.txt new file mode 100644 index 000000000..0fb21221f --- /dev/null +++ b/_sources/build/arty/documentation/index.rst.txt @@ -0,0 +1,37 @@ +=========================================== +Documentation for Row Hammer Tester Arty-A7 +=========================================== + + + +Modules +======= + +.. toctree:: + :maxdepth: 1 + + interrupts + +Register Groups +=============== + +.. toctree:: + :maxdepth: 1 + + leds + ddrphy + controller_settings + ddrctrl + ethphy + rowhammer + writer + reader + dfi_switch + payload_executor + ctrl + identifier_mem + sdram + sdram_checker + sdram_generator + timer0 + uart diff --git a/_sources/build/arty/documentation/interrupts.rst.txt b/_sources/build/arty/documentation/interrupts.rst.txt new file mode 100644 index 000000000..bfc948fb1 --- /dev/null +++ b/_sources/build/arty/documentation/interrupts.rst.txt @@ -0,0 +1,22 @@ +Interrupt Controller +==================== + +This device has an ``EventManager``-based interrupt system. Individual modules +generate `events` which are wired into a central interrupt controller. + +When an interrupt occurs, you should look the interrupt number up in the CPU- +specific interrupt table and then call the relevant module. + +Assigned Interrupts +------------------- + +The following interrupts are assigned on this system: + ++-----------+------------------------+ +| Interrupt | Module | ++===========+========================+ +| 1 | :doc:`TIMER0 ` | ++-----------+------------------------+ +| 0 | :doc:`UART ` | ++-----------+------------------------+ + diff --git a/_sources/build/arty/documentation/leds.rst.txt b/_sources/build/arty/documentation/leds.rst.txt new file mode 100644 index 000000000..5163a0c3d --- /dev/null +++ b/_sources/build/arty/documentation/leds.rst.txt @@ -0,0 +1,30 @@ +LEDS +==== + +Register Listing for LEDS +------------------------- + ++----------------------------+------------------------------+ +| Register | Address | ++============================+==============================+ +| :ref:`LEDS_OUT ` | :ref:`0xf0000000 ` | ++----------------------------+------------------------------+ + +LEDS_OUT +^^^^^^^^ + +`Address: 0xf0000000 + 0x0 = 0xf0000000` + + Led Output(s) Control. + + .. wavedrom:: + :caption: LEDS_OUT + + { + "reg": [ + {"name": "out[3:0]", "bits": 4}, + {"bits": 28}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/arty/documentation/payload_executor.rst.txt b/_sources/build/arty/documentation/payload_executor.rst.txt new file mode 100644 index 000000000..9c9b21975 --- /dev/null +++ b/_sources/build/arty/documentation/payload_executor.rst.txt @@ -0,0 +1,137 @@ +PAYLOAD_EXECUTOR +================ + + + + Executes the DRAM payload from memory + + + **Instruction decoder** + + All instructions are 32-bit. The format of most instructions is the same, + except for the LOOP instruction, which has a constant TIMESLICE of 1. + + NOOP with a TIMESLICE of 0 is a special case which is interpreted as + STOP instruction. When this instruction is encountered execution gets + finished immediately. + + **NOTE:** TIMESLICE is the number of cycles the instruction will take. This + means that instructions other than NOOP that use TIMESLICE=0 are illegal + (although will silently be executed as having TIMESLICE=1). + + **NOTE2:** LOOP instruction will *jump* COUNT times, meaning that the "code" + inside the loop will effectively be executed COUNT+1 times. + + Op codes: + ++------+-------+ ++ Op + Value + ++======+=======+ ++ NOOP | 0b000 + ++------+-------+ ++ LOOP | 0b111 + ++------+-------+ ++ ACT | 0b100 + ++------+-------+ ++ PRE | 0b101 + ++------+-------+ ++ REF | 0b110 + ++------+-------+ ++ ZQC | 0b001 + ++------+-------+ ++ READ | 0b010 + ++------+-------+ + + Instruction format:: + + LSB MSB + dfi: OP_CODE | TIMESLICE | ADDRESS + noop: OP_CODE | TIMESLICE_NOOP + loop: OP_CODE | COUNT | JUMP + stop: | 0 + + Where ADDRESS depends on the DFI command and is one of:: + + LSB MSB + RANK | BANK | COLUMN + RANK | BANK | ROW + + + +Register Listing for PAYLOAD_EXECUTOR +------------------------------------- + ++------------------------------------------------------------------+-------------------------------------------------+ +| Register | Address | ++==================================================================+=================================================+ +| :ref:`PAYLOAD_EXECUTOR_START ` | :ref:`0xf0004800 ` | ++------------------------------------------------------------------+-------------------------------------------------+ +| :ref:`PAYLOAD_EXECUTOR_STATUS ` | :ref:`0xf0004804 ` | ++------------------------------------------------------------------+-------------------------------------------------+ +| :ref:`PAYLOAD_EXECUTOR_READ_COUNT ` | :ref:`0xf0004808 ` | ++------------------------------------------------------------------+-------------------------------------------------+ + +PAYLOAD_EXECUTOR_START +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0004800 + 0x0 = 0xf0004800` + + Writing to this register initializes payload execution + + .. wavedrom:: + :caption: PAYLOAD_EXECUTOR_START + + { + "reg": [ + {"name": "start", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +PAYLOAD_EXECUTOR_STATUS +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0004800 + 0x4 = 0xf0004804` + + Payload executor status register + + .. wavedrom:: + :caption: PAYLOAD_EXECUTOR_STATUS + + { + "reg": [ + {"name": "ready", "bits": 1}, + {"name": "overflow", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+----------+---------------------------------------------------------------------------------+ +| Field | Name | Description | ++=======+==========+=================================================================================+ +| [0] | READY | Indicates that the executor is not running | ++-------+----------+---------------------------------------------------------------------------------+ +| [1] | OVERFLOW | Indicates the scratchpad memory address counter has overflown due to the number | +| | | of READ commands sent during execution | ++-------+----------+---------------------------------------------------------------------------------+ + +PAYLOAD_EXECUTOR_READ_COUNT +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0004800 + 0x8 = 0xf0004808` + + Number of data from READ commands that is stored in the scratchpad memory + + .. wavedrom:: + :caption: PAYLOAD_EXECUTOR_READ_COUNT + + { + "reg": [ + {"name": "read_count[5:0]", "bits": 6}, + {"bits": 26}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/arty/documentation/reader.rst.txt b/_sources/build/arty/documentation/reader.rst.txt new file mode 100644 index 000000000..e61032a17 --- /dev/null +++ b/_sources/build/arty/documentation/reader.rst.txt @@ -0,0 +1,500 @@ +READER +====== + + + +DMA DRAM reader. + +Allows to check DRAM contents against a predefined pattern using DMA. + +Pattern +------- + + + Provides access to RAM to store access pattern: `mem_addr` and `mem_data`. + The pattern address space can be limited using the `data_mask`. + + For example, having `mem_adr` filled with `[ 0x04, 0x02, 0x03, ... ]` + and `mem_data` filled with `[ 0xff, 0xaa, 0x55, ... ]` and setting + `data_mask = 0b01`, the pattern [(address, data), ...] written will be: + `[(0x04, 0xff), (0x02, 0xaa), (0x04, 0xff), ...]` (wraps due to masking). + + DRAM memory range that is being accessed can be configured using `mem_mask`. + + To use this module, make sure that `ready` is 1, then write the desired + number of transfers to `count`. Writing to the `start` CSR will initialize + the operation. When the operation is ongoing `ready` will be 0. + + +Reading errors +-------------- + +This module allows to check the locations of errors in the memory. +It scans the configured memory area and compares the values read to +the predefined pattern. If `skip_fifo` is 0, this module will stop +after each error encountered, so that it can be examined. Wait until +the `error_ready` CSR is 1. Then use the CSRs `error_offset`, +`error_data` and `error_expected` to examine the errors in the current +transfer. To continue reading, write 1 to `error_continue` CSR. +Setting `skip_fifo` to 1 will disable this behaviour entirely. + +The final number of errors can be read from `error_count`. +NOTE: This value represents the number of erroneous *DMA transfers*. + +The current progress can be read from the `done` CSR. + + +Register Listing for READER +--------------------------- + ++------------------------------------------------------------------------+----------------------------------------------------+ +| Register | Address | ++========================================================================+====================================================+ +| :ref:`READER_START ` | :ref:`0xf0003800 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_READY ` | :ref:`0xf0003804 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_MODULO ` | :ref:`0xf0003808 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_COUNT ` | :ref:`0xf000380c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_DONE ` | :ref:`0xf0003810 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_MEM_MASK ` | :ref:`0xf0003814 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_DATA_MASK ` | :ref:`0xf0003818 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_DATA_DIV ` | :ref:`0xf000381c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_INVERTER_DIVISOR_MASK ` | :ref:`0xf0003820 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_INVERTER_SELECTION_MASK ` | :ref:`0xf0003824 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_COUNT ` | :ref:`0xf0003828 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_SKIP_FIFO ` | :ref:`0xf000382c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_OFFSET ` | :ref:`0xf0003830 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA3 ` | :ref:`0xf0003834 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA2 ` | :ref:`0xf0003838 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA1 ` | :ref:`0xf000383c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA0 ` | :ref:`0xf0003840 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED3 ` | :ref:`0xf0003844 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED2 ` | :ref:`0xf0003848 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED1 ` | :ref:`0xf000384c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED0 ` | :ref:`0xf0003850 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_READY ` | :ref:`0xf0003854 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_CONTINUE ` | :ref:`0xf0003858 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ + +READER_START +^^^^^^^^^^^^ + +`Address: 0xf0003800 + 0x0 = 0xf0003800` + + Write to the register starts the transfer (if ready=1) + + .. wavedrom:: + :caption: READER_START + + { + "reg": [ + {"name": "start", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_READY +^^^^^^^^^^^^ + +`Address: 0xf0003800 + 0x4 = 0xf0003804` + + Indicates that the transfer is not ongoing + + .. wavedrom:: + :caption: READER_READY + + { + "reg": [ + {"name": "ready", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_MODULO +^^^^^^^^^^^^^ + +`Address: 0xf0003800 + 0x8 = 0xf0003808` + + When set use modulo to calculate DMA transfers address rather than bit masking + + .. wavedrom:: + :caption: READER_MODULO + + { + "reg": [ + {"name": "modulo", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_COUNT +^^^^^^^^^^^^ + +`Address: 0xf0003800 + 0xc = 0xf000380c` + + Desired number of DMA transfers + + .. wavedrom:: + :caption: READER_COUNT + + { + "reg": [ + {"name": "count[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_DONE +^^^^^^^^^^^ + +`Address: 0xf0003800 + 0x10 = 0xf0003810` + + Number of completed DMA transfers + + .. wavedrom:: + :caption: READER_DONE + + { + "reg": [ + {"name": "done[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_MEM_MASK +^^^^^^^^^^^^^^^ + +`Address: 0xf0003800 + 0x14 = 0xf0003814` + + DRAM address mask for DMA transfers + + .. wavedrom:: + :caption: READER_MEM_MASK + + { + "reg": [ + {"name": "mem_mask[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_DATA_MASK +^^^^^^^^^^^^^^^^ + +`Address: 0xf0003800 + 0x18 = 0xf0003818` + + Pattern memory address mask + + .. wavedrom:: + :caption: READER_DATA_MASK + + { + "reg": [ + {"name": "data_mask[5:0]", "bits": 6}, + {"bits": 26}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_DATA_DIV +^^^^^^^^^^^^^^^ + +`Address: 0xf0003800 + 0x1c = 0xf000381c` + + Pattern memory address divisior-1 + + .. wavedrom:: + :caption: READER_DATA_DIV + + { + "reg": [ + {"name": "data_div[5:0]", "bits": 6}, + {"bits": 26}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_INVERTER_DIVISOR_MASK +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003800 + 0x20 = 0xf0003820` + + Divisor mask for selecting rows for which pattern data gets inverted + + .. wavedrom:: + :caption: READER_INVERTER_DIVISOR_MASK + + { + "reg": [ + {"name": "inverter_divisor_mask[4:0]", "bits": 5}, + {"bits": 27}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_INVERTER_SELECTION_MASK +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003800 + 0x24 = 0xf0003824` + + Selection mask for selecting rows for which pattern data gets inverted + + .. wavedrom:: + :caption: READER_INVERTER_SELECTION_MASK + + { + "reg": [ + {"name": "inverter_selection_mask[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_COUNT +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003800 + 0x28 = 0xf0003828` + + Number of errors detected + + .. wavedrom:: + :caption: READER_ERROR_COUNT + + { + "reg": [ + {"name": "error_count[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_SKIP_FIFO +^^^^^^^^^^^^^^^^ + +`Address: 0xf0003800 + 0x2c = 0xf000382c` + + Skip waiting for user to read the errors FIFO + + .. wavedrom:: + :caption: READER_SKIP_FIFO + + { + "reg": [ + {"name": "skip_fifo", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_ERROR_OFFSET +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003800 + 0x30 = 0xf0003830` + + Current offset of the error + + .. wavedrom:: + :caption: READER_ERROR_OFFSET + + { + "reg": [ + {"name": "error_offset[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA3 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003800 + 0x34 = 0xf0003834` + + Bits 96-127 of `READER_ERROR_DATA`. Erroneous value read from DRAM memory + + .. wavedrom:: + :caption: READER_ERROR_DATA3 + + { + "reg": [ + {"name": "error_data[127:96]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA2 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003800 + 0x38 = 0xf0003838` + + Bits 64-95 of `READER_ERROR_DATA`. + + .. wavedrom:: + :caption: READER_ERROR_DATA2 + + { + "reg": [ + {"name": "error_data[95:64]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA1 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003800 + 0x3c = 0xf000383c` + + Bits 32-63 of `READER_ERROR_DATA`. + + .. wavedrom:: + :caption: READER_ERROR_DATA1 + + { + "reg": [ + {"name": "error_data[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA0 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003800 + 0x40 = 0xf0003840` + + Bits 0-31 of `READER_ERROR_DATA`. + + .. wavedrom:: + :caption: READER_ERROR_DATA0 + + { + "reg": [ + {"name": "error_data[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED3 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003800 + 0x44 = 0xf0003844` + + Bits 96-127 of `READER_ERROR_EXPECTED`. Value expected to be read from DRAM + memory + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED3 + + { + "reg": [ + {"name": "error_expected[127:96]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED2 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003800 + 0x48 = 0xf0003848` + + Bits 64-95 of `READER_ERROR_EXPECTED`. + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED2 + + { + "reg": [ + {"name": "error_expected[95:64]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED1 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003800 + 0x4c = 0xf000384c` + + Bits 32-63 of `READER_ERROR_EXPECTED`. + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED1 + + { + "reg": [ + {"name": "error_expected[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED0 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003800 + 0x50 = 0xf0003850` + + Bits 0-31 of `READER_ERROR_EXPECTED`. + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED0 + + { + "reg": [ + {"name": "error_expected[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_READY +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003800 + 0x54 = 0xf0003854` + + Error detected and ready to read + + .. wavedrom:: + :caption: READER_ERROR_READY + + { + "reg": [ + {"name": "error_ready", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_ERROR_CONTINUE +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003800 + 0x58 = 0xf0003858` + + Continue reading until the next error + + .. wavedrom:: + :caption: READER_ERROR_CONTINUE + + { + "reg": [ + {"name": "error_continue", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/arty/documentation/rowhammer.rst.txt b/_sources/build/arty/documentation/rowhammer.rst.txt new file mode 100644 index 000000000..4e195f57b --- /dev/null +++ b/_sources/build/arty/documentation/rowhammer.rst.txt @@ -0,0 +1,102 @@ +ROWHAMMER +========= + + + +Row Hammer DMA attacker + +This module allows to perform a Row Hammer attack by configuring it with +two addresses that map to different rows of a single bank. When enabled, +it will perform alternating DMA reads from the given locations, which will +result in the DRAM controller having to repeatedly open/close rows at each +read access. + + +Register Listing for ROWHAMMER +------------------------------ + ++------------------------------------------------+----------------------------------------+ +| Register | Address | ++================================================+========================================+ +| :ref:`ROWHAMMER_ENABLED ` | :ref:`0xf0002800 ` | ++------------------------------------------------+----------------------------------------+ +| :ref:`ROWHAMMER_ADDRESS1 ` | :ref:`0xf0002804 ` | ++------------------------------------------------+----------------------------------------+ +| :ref:`ROWHAMMER_ADDRESS2 ` | :ref:`0xf0002808 ` | ++------------------------------------------------+----------------------------------------+ +| :ref:`ROWHAMMER_COUNT ` | :ref:`0xf000280c ` | ++------------------------------------------------+----------------------------------------+ + +ROWHAMMER_ENABLED +^^^^^^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x0 = 0xf0002800` + + Used to start/stop the operation of the module + + .. wavedrom:: + :caption: ROWHAMMER_ENABLED + + { + "reg": [ + {"name": "enabled", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +ROWHAMMER_ADDRESS1 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x4 = 0xf0002804` + + First attacked address + + .. wavedrom:: + :caption: ROWHAMMER_ADDRESS1 + + { + "reg": [ + {"name": "address1[23:0]", "bits": 24}, + {"bits": 8}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +ROWHAMMER_ADDRESS2 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x8 = 0xf0002808` + + Second attacked address + + .. wavedrom:: + :caption: ROWHAMMER_ADDRESS2 + + { + "reg": [ + {"name": "address2[23:0]", "bits": 24}, + {"bits": 8}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +ROWHAMMER_COUNT +^^^^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0xc = 0xf000280c` + + This is the number of DMA accesses performed. When the module is enabled, the + value can be freely read. When the module is disabled, the register is clear-on- + write and has to be read before the next attack. + + .. wavedrom:: + :caption: ROWHAMMER_COUNT + + { + "reg": [ + {"name": "count[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/arty/documentation/sdram.rst.txt b/_sources/build/arty/documentation/sdram.rst.txt new file mode 100644 index 000000000..09896219d --- /dev/null +++ b/_sources/build/arty/documentation/sdram.rst.txt @@ -0,0 +1,1175 @@ +SDRAM +===== + +Register Listing for SDRAM +-------------------------- + ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| Register | Address | ++================================================================================+========================================================+ +| :ref:`SDRAM_DFII_CONTROL ` | :ref:`0xf0006000 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI0_COMMAND ` | :ref:`0xf0006004 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI0_COMMAND_ISSUE ` | :ref:`0xf0006008 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI0_ADDRESS ` | :ref:`0xf000600c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI0_BADDRESS ` | :ref:`0xf0006010 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI0_WRDATA ` | :ref:`0xf0006014 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI0_RDDATA ` | :ref:`0xf0006018 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI1_COMMAND ` | :ref:`0xf000601c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI1_COMMAND_ISSUE ` | :ref:`0xf0006020 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI1_ADDRESS ` | :ref:`0xf0006024 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI1_BADDRESS ` | :ref:`0xf0006028 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI1_WRDATA ` | :ref:`0xf000602c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI1_RDDATA ` | :ref:`0xf0006030 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI2_COMMAND ` | :ref:`0xf0006034 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI2_COMMAND_ISSUE ` | :ref:`0xf0006038 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI2_ADDRESS ` | :ref:`0xf000603c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI2_BADDRESS ` | :ref:`0xf0006040 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI2_WRDATA ` | :ref:`0xf0006044 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI2_RDDATA ` | :ref:`0xf0006048 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI3_COMMAND ` | :ref:`0xf000604c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI3_COMMAND_ISSUE ` | :ref:`0xf0006050 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI3_ADDRESS ` | :ref:`0xf0006054 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI3_BADDRESS ` | :ref:`0xf0006058 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI3_WRDATA ` | :ref:`0xf000605c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI3_RDDATA ` | :ref:`0xf0006060 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRP ` | :ref:`0xf0006064 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRCD ` | :ref:`0xf0006068 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TWR ` | :ref:`0xf000606c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TWTR ` | :ref:`0xf0006070 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TREFI ` | :ref:`0xf0006074 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRFC ` | :ref:`0xf0006078 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TFAW ` | :ref:`0xf000607c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TCCD ` | :ref:`0xf0006080 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TCCD_WR ` | :ref:`0xf0006084 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRTP ` | :ref:`0xf0006088 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRRD ` | :ref:`0xf000608c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRC ` | :ref:`0xf0006090 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRAS ` | :ref:`0xf0006094 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TZQCS ` | :ref:`0xf0006098 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_0 ` | :ref:`0xf000609c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_0 ` | :ref:`0xf00060a0 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_1 ` | :ref:`0xf00060a4 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_1 ` | :ref:`0xf00060a8 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_2 ` | :ref:`0xf00060ac ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_2 ` | :ref:`0xf00060b0 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_3 ` | :ref:`0xf00060b4 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_3 ` | :ref:`0xf00060b8 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_4 ` | :ref:`0xf00060bc ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_4 ` | :ref:`0xf00060c0 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_5 ` | :ref:`0xf00060c4 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_5 ` | :ref:`0xf00060c8 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_6 ` | :ref:`0xf00060cc ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_6 ` | :ref:`0xf00060d0 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_7 ` | :ref:`0xf00060d4 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_7 ` | :ref:`0xf00060d8 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ + +SDRAM_DFII_CONTROL +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x0 = 0xf0006000` + + Control DFI signals common to all phases + + .. wavedrom:: + :caption: SDRAM_DFII_CONTROL + + { + "reg": [ + {"name": "sel", "attr": '1', "bits": 1}, + {"name": "cke", "bits": 1}, + {"name": "odt", "bits": 1}, + {"name": "reset_n", "bits": 1}, + {"bits": 28} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+---------+-------------------------------------------+ +| Field | Name | Description | ++=======+=========+===========================================+ +| [0] | SEL | | +| | | | +| | | +---------+-----------------------------+ | +| | | | Value | Description | | +| | | +=========+=============================+ | +| | | | ``0b0`` | Software (CPU) control. | | +| | | +---------+-----------------------------+ | +| | | | ``0b1`` | Hardware control (default). | | +| | | +---------+-----------------------------+ | ++-------+---------+-------------------------------------------+ +| [1] | CKE | DFI clock enable bus | ++-------+---------+-------------------------------------------+ +| [2] | ODT | DFI on-die termination bus | ++-------+---------+-------------------------------------------+ +| [3] | RESET_N | DFI clock reset bus | ++-------+---------+-------------------------------------------+ + +SDRAM_DFII_PI0_COMMAND +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x4 = 0xf0006004` + + Control DFI signals on a single phase + + .. wavedrom:: + :caption: SDRAM_DFII_PI0_COMMAND + + { + "reg": [ + {"name": "cs", "bits": 1}, + {"name": "we", "bits": 1}, + {"name": "cas", "bits": 1}, + {"name": "ras", "bits": 1}, + {"name": "wren", "bits": 1}, + {"name": "rden", "bits": 1}, + {"bits": 26} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------------------------+ +| Field | Name | Description | ++=======+======+===============================+ +| [0] | CS | DFI chip select bus | ++-------+------+-------------------------------+ +| [1] | WE | DFI write enable bus | ++-------+------+-------------------------------+ +| [2] | CAS | DFI column address strobe bus | ++-------+------+-------------------------------+ +| [3] | RAS | DFI row address strobe bus | ++-------+------+-------------------------------+ +| [4] | WREN | DFI write data enable bus | ++-------+------+-------------------------------+ +| [5] | RDEN | DFI read data enable bus | ++-------+------+-------------------------------+ + +SDRAM_DFII_PI0_COMMAND_ISSUE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x8 = 0xf0006008` + + + .. wavedrom:: + :caption: SDRAM_DFII_PI0_COMMAND_ISSUE + + { + "reg": [ + {"name": "dfii_pi0_command_issue", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_PI0_ADDRESS +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xc = 0xf000600c` + + DFI address bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI0_ADDRESS + + { + "reg": [ + {"name": "dfii_pi0_address[13:0]", "bits": 14}, + {"bits": 18}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI0_BADDRESS +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x10 = 0xf0006010` + + DFI bank address bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI0_BADDRESS + + { + "reg": [ + {"name": "dfii_pi0_baddress[2:0]", "bits": 3}, + {"bits": 29}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_PI0_WRDATA +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x14 = 0xf0006014` + + DFI write data bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI0_WRDATA + + { + "reg": [ + {"name": "dfii_pi0_wrdata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI0_RDDATA +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x18 = 0xf0006018` + + DFI read data bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI0_RDDATA + + { + "reg": [ + {"name": "dfii_pi0_rddata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI1_COMMAND +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x1c = 0xf000601c` + + Control DFI signals on a single phase + + .. wavedrom:: + :caption: SDRAM_DFII_PI1_COMMAND + + { + "reg": [ + {"name": "cs", "bits": 1}, + {"name": "we", "bits": 1}, + {"name": "cas", "bits": 1}, + {"name": "ras", "bits": 1}, + {"name": "wren", "bits": 1}, + {"name": "rden", "bits": 1}, + {"bits": 26} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------------------------+ +| Field | Name | Description | ++=======+======+===============================+ +| [0] | CS | DFI chip select bus | ++-------+------+-------------------------------+ +| [1] | WE | DFI write enable bus | ++-------+------+-------------------------------+ +| [2] | CAS | DFI column address strobe bus | ++-------+------+-------------------------------+ +| [3] | RAS | DFI row address strobe bus | ++-------+------+-------------------------------+ +| [4] | WREN | DFI write data enable bus | ++-------+------+-------------------------------+ +| [5] | RDEN | DFI read data enable bus | ++-------+------+-------------------------------+ + +SDRAM_DFII_PI1_COMMAND_ISSUE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x20 = 0xf0006020` + + + .. wavedrom:: + :caption: SDRAM_DFII_PI1_COMMAND_ISSUE + + { + "reg": [ + {"name": "dfii_pi1_command_issue", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_PI1_ADDRESS +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x24 = 0xf0006024` + + DFI address bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI1_ADDRESS + + { + "reg": [ + {"name": "dfii_pi1_address[13:0]", "bits": 14}, + {"bits": 18}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI1_BADDRESS +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x28 = 0xf0006028` + + DFI bank address bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI1_BADDRESS + + { + "reg": [ + {"name": "dfii_pi1_baddress[2:0]", "bits": 3}, + {"bits": 29}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_PI1_WRDATA +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x2c = 0xf000602c` + + DFI write data bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI1_WRDATA + + { + "reg": [ + {"name": "dfii_pi1_wrdata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI1_RDDATA +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x30 = 0xf0006030` + + DFI read data bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI1_RDDATA + + { + "reg": [ + {"name": "dfii_pi1_rddata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI2_COMMAND +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x34 = 0xf0006034` + + Control DFI signals on a single phase + + .. wavedrom:: + :caption: SDRAM_DFII_PI2_COMMAND + + { + "reg": [ + {"name": "cs", "bits": 1}, + {"name": "we", "bits": 1}, + {"name": "cas", "bits": 1}, + {"name": "ras", "bits": 1}, + {"name": "wren", "bits": 1}, + {"name": "rden", "bits": 1}, + {"bits": 26} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------------------------+ +| Field | Name | Description | ++=======+======+===============================+ +| [0] | CS | DFI chip select bus | ++-------+------+-------------------------------+ +| [1] | WE | DFI write enable bus | ++-------+------+-------------------------------+ +| [2] | CAS | DFI column address strobe bus | ++-------+------+-------------------------------+ +| [3] | RAS | DFI row address strobe bus | ++-------+------+-------------------------------+ +| [4] | WREN | DFI write data enable bus | ++-------+------+-------------------------------+ +| [5] | RDEN | DFI read data enable bus | ++-------+------+-------------------------------+ + +SDRAM_DFII_PI2_COMMAND_ISSUE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x38 = 0xf0006038` + + + .. wavedrom:: + :caption: SDRAM_DFII_PI2_COMMAND_ISSUE + + { + "reg": [ + {"name": "dfii_pi2_command_issue", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_PI2_ADDRESS +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x3c = 0xf000603c` + + DFI address bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI2_ADDRESS + + { + "reg": [ + {"name": "dfii_pi2_address[13:0]", "bits": 14}, + {"bits": 18}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI2_BADDRESS +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x40 = 0xf0006040` + + DFI bank address bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI2_BADDRESS + + { + "reg": [ + {"name": "dfii_pi2_baddress[2:0]", "bits": 3}, + {"bits": 29}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_PI2_WRDATA +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x44 = 0xf0006044` + + DFI write data bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI2_WRDATA + + { + "reg": [ + {"name": "dfii_pi2_wrdata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI2_RDDATA +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x48 = 0xf0006048` + + DFI read data bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI2_RDDATA + + { + "reg": [ + {"name": "dfii_pi2_rddata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI3_COMMAND +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x4c = 0xf000604c` + + Control DFI signals on a single phase + + .. wavedrom:: + :caption: SDRAM_DFII_PI3_COMMAND + + { + "reg": [ + {"name": "cs", "bits": 1}, + {"name": "we", "bits": 1}, + {"name": "cas", "bits": 1}, + {"name": "ras", "bits": 1}, + {"name": "wren", "bits": 1}, + {"name": "rden", "bits": 1}, + {"bits": 26} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------------------------+ +| Field | Name | Description | ++=======+======+===============================+ +| [0] | CS | DFI chip select bus | ++-------+------+-------------------------------+ +| [1] | WE | DFI write enable bus | ++-------+------+-------------------------------+ +| [2] | CAS | DFI column address strobe bus | ++-------+------+-------------------------------+ +| [3] | RAS | DFI row address strobe bus | ++-------+------+-------------------------------+ +| [4] | WREN | DFI write data enable bus | ++-------+------+-------------------------------+ +| [5] | RDEN | DFI read data enable bus | ++-------+------+-------------------------------+ + +SDRAM_DFII_PI3_COMMAND_ISSUE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x50 = 0xf0006050` + + + .. wavedrom:: + :caption: SDRAM_DFII_PI3_COMMAND_ISSUE + + { + "reg": [ + {"name": "dfii_pi3_command_issue", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_PI3_ADDRESS +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x54 = 0xf0006054` + + DFI address bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI3_ADDRESS + + { + "reg": [ + {"name": "dfii_pi3_address[13:0]", "bits": 14}, + {"bits": 18}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI3_BADDRESS +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x58 = 0xf0006058` + + DFI bank address bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI3_BADDRESS + + { + "reg": [ + {"name": "dfii_pi3_baddress[2:0]", "bits": 3}, + {"bits": 29}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_PI3_WRDATA +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x5c = 0xf000605c` + + DFI write data bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI3_WRDATA + + { + "reg": [ + {"name": "dfii_pi3_wrdata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI3_RDDATA +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x60 = 0xf0006060` + + DFI read data bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI3_RDDATA + + { + "reg": [ + {"name": "dfii_pi3_rddata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_TRP +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x64 = 0xf0006064` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRP + + { + "reg": [ + {"name": "controller_trp[1:0]", "attr": 'reset: 3', "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TRCD +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x68 = 0xf0006068` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRCD + + { + "reg": [ + {"name": "controller_trcd[1:0]", "attr": 'reset: 3', "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TWR +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x6c = 0xf000606c` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TWR + + { + "reg": [ + {"name": "controller_twr[1:0]", "attr": 'reset: 3', "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TWTR +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x70 = 0xf0006070` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TWTR + + { + "reg": [ + {"name": "controller_twtr[1:0]", "attr": 'reset: 2', "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TREFI +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x74 = 0xf0006074` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TREFI + + { + "reg": [ + {"name": "controller_trefi[9:0]", "attr": 'reset: 782', "bits": 10}, + {"bits": 22}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_TRFC +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x78 = 0xf0006078` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRFC + + { + "reg": [ + {"name": "controller_trfc[5:0]", "attr": 'reset: 16', "bits": 6}, + {"bits": 26}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TFAW +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x7c = 0xf000607c` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TFAW + + { + "reg": [ + {"name": "controller_tfaw[2:0]", "attr": 'reset: 6', "bits": 3}, + {"bits": 29}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TCCD +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x80 = 0xf0006080` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TCCD + + { + "reg": [ + {"name": "controller_tccd", "attr": 'reset: 1', "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TCCD_WR +^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x84 = 0xf0006084` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TCCD_WR + + { + "reg": [ + {"name": "controller_tccd_wr", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TRTP +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x88 = 0xf0006088` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRTP + + { + "reg": [ + {"name": "controller_trtp", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TRRD +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x8c = 0xf000608c` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRRD + + { + "reg": [ + {"name": "controller_trrd[1:0]", "attr": 'reset: 2', "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TRC +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x90 = 0xf0006090` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRC + + { + "reg": [ + {"name": "controller_trc[2:0]", "attr": 'reset: 6', "bits": 3}, + {"bits": 29}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TRAS +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x94 = 0xf0006094` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRAS + + { + "reg": [ + {"name": "controller_tras[2:0]", "attr": 'reset: 5', "bits": 3}, + {"bits": 29}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TZQCS +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x98 = 0xf0006098` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TZQCS + + { + "reg": [ + {"name": "controller_tzqcs[7:0]", "attr": 'reset: 16', "bits": 8}, + {"bits": 24}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_0 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x9c = 0xf000609c` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_0 + + { + "reg": [ + {"name": "controller_last_addr_0[20:0]", "bits": 21}, + {"bits": 11}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_0 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xa0 = 0xf00060a0` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_0 + + { + "reg": [ + {"name": "controller_last_active_row_0[13:0]", "bits": 14}, + {"bits": 18}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_1 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xa4 = 0xf00060a4` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_1 + + { + "reg": [ + {"name": "controller_last_addr_1[20:0]", "bits": 21}, + {"bits": 11}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_1 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xa8 = 0xf00060a8` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_1 + + { + "reg": [ + {"name": "controller_last_active_row_1[13:0]", "bits": 14}, + {"bits": 18}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_2 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xac = 0xf00060ac` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_2 + + { + "reg": [ + {"name": "controller_last_addr_2[20:0]", "bits": 21}, + {"bits": 11}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_2 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xb0 = 0xf00060b0` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_2 + + { + "reg": [ + {"name": "controller_last_active_row_2[13:0]", "bits": 14}, + {"bits": 18}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_3 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xb4 = 0xf00060b4` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_3 + + { + "reg": [ + {"name": "controller_last_addr_3[20:0]", "bits": 21}, + {"bits": 11}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_3 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xb8 = 0xf00060b8` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_3 + + { + "reg": [ + {"name": "controller_last_active_row_3[13:0]", "bits": 14}, + {"bits": 18}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_4 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xbc = 0xf00060bc` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_4 + + { + "reg": [ + {"name": "controller_last_addr_4[20:0]", "bits": 21}, + {"bits": 11}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_4 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xc0 = 0xf00060c0` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_4 + + { + "reg": [ + {"name": "controller_last_active_row_4[13:0]", "bits": 14}, + {"bits": 18}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_5 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xc4 = 0xf00060c4` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_5 + + { + "reg": [ + {"name": "controller_last_addr_5[20:0]", "bits": 21}, + {"bits": 11}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_5 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xc8 = 0xf00060c8` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_5 + + { + "reg": [ + {"name": "controller_last_active_row_5[13:0]", "bits": 14}, + {"bits": 18}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_6 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xcc = 0xf00060cc` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_6 + + { + "reg": [ + {"name": "controller_last_addr_6[20:0]", "bits": 21}, + {"bits": 11}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_6 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xd0 = 0xf00060d0` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_6 + + { + "reg": [ + {"name": "controller_last_active_row_6[13:0]", "bits": 14}, + {"bits": 18}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_7 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xd4 = 0xf00060d4` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_7 + + { + "reg": [ + {"name": "controller_last_addr_7[20:0]", "bits": 21}, + {"bits": 11}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_7 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xd8 = 0xf00060d8` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_7 + + { + "reg": [ + {"name": "controller_last_active_row_7[13:0]", "bits": 14}, + {"bits": 18}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/arty/documentation/sdram_checker.rst.txt b/_sources/build/arty/documentation/sdram_checker.rst.txt new file mode 100644 index 000000000..a096248bf --- /dev/null +++ b/_sources/build/arty/documentation/sdram_checker.rst.txt @@ -0,0 +1,186 @@ +SDRAM_CHECKER +============= + +Register Listing for SDRAM_CHECKER +---------------------------------- + ++----------------------------------------------------+------------------------------------------+ +| Register | Address | ++====================================================+==========================================+ +| :ref:`SDRAM_CHECKER_RESET ` | :ref:`0xf0006800 ` | ++----------------------------------------------------+------------------------------------------+ +| :ref:`SDRAM_CHECKER_START ` | :ref:`0xf0006804 ` | ++----------------------------------------------------+------------------------------------------+ +| :ref:`SDRAM_CHECKER_DONE ` | :ref:`0xf0006808 ` | ++----------------------------------------------------+------------------------------------------+ +| :ref:`SDRAM_CHECKER_BASE ` | :ref:`0xf000680c ` | ++----------------------------------------------------+------------------------------------------+ +| :ref:`SDRAM_CHECKER_END ` | :ref:`0xf0006810 ` | ++----------------------------------------------------+------------------------------------------+ +| :ref:`SDRAM_CHECKER_LENGTH ` | :ref:`0xf0006814 ` | ++----------------------------------------------------+------------------------------------------+ +| :ref:`SDRAM_CHECKER_RANDOM ` | :ref:`0xf0006818 ` | ++----------------------------------------------------+------------------------------------------+ +| :ref:`SDRAM_CHECKER_TICKS ` | :ref:`0xf000681c ` | ++----------------------------------------------------+------------------------------------------+ +| :ref:`SDRAM_CHECKER_ERRORS ` | :ref:`0xf0006820 ` | ++----------------------------------------------------+------------------------------------------+ + +SDRAM_CHECKER_RESET +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x0 = 0xf0006800` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_RESET + + { + "reg": [ + {"name": "reset", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CHECKER_START +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x4 = 0xf0006804` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_START + + { + "reg": [ + {"name": "start", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CHECKER_DONE +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x8 = 0xf0006808` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_DONE + + { + "reg": [ + {"name": "done", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CHECKER_BASE +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xc = 0xf000680c` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_BASE + + { + "reg": [ + {"name": "base[27:0]", "bits": 28}, + {"bits": 4}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CHECKER_END +^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x10 = 0xf0006810` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_END + + { + "reg": [ + {"name": "end[27:0]", "bits": 28}, + {"bits": 4}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CHECKER_LENGTH +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x14 = 0xf0006814` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_LENGTH + + { + "reg": [ + {"name": "length[27:0]", "bits": 28}, + {"bits": 4}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CHECKER_RANDOM +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x18 = 0xf0006818` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_RANDOM + + { + "reg": [ + {"name": "data", "bits": 1}, + {"name": "addr", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------+ +| Field | Name | Description | ++=======+======+=============+ ++-------+------+-------------+ ++-------+------+-------------+ + +SDRAM_CHECKER_TICKS +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x1c = 0xf000681c` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_TICKS + + { + "reg": [ + {"name": "ticks[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CHECKER_ERRORS +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x20 = 0xf0006820` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_ERRORS + + { + "reg": [ + {"name": "errors[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/arty/documentation/sdram_generator.rst.txt b/_sources/build/arty/documentation/sdram_generator.rst.txt new file mode 100644 index 000000000..bd5a2ead4 --- /dev/null +++ b/_sources/build/arty/documentation/sdram_generator.rst.txt @@ -0,0 +1,168 @@ +SDRAM_GENERATOR +=============== + +Register Listing for SDRAM_GENERATOR +------------------------------------ + ++--------------------------------------------------------+--------------------------------------------+ +| Register | Address | ++========================================================+============================================+ +| :ref:`SDRAM_GENERATOR_RESET ` | :ref:`0xf0007000 ` | ++--------------------------------------------------------+--------------------------------------------+ +| :ref:`SDRAM_GENERATOR_START ` | :ref:`0xf0007004 ` | ++--------------------------------------------------------+--------------------------------------------+ +| :ref:`SDRAM_GENERATOR_DONE ` | :ref:`0xf0007008 ` | ++--------------------------------------------------------+--------------------------------------------+ +| :ref:`SDRAM_GENERATOR_BASE ` | :ref:`0xf000700c ` | ++--------------------------------------------------------+--------------------------------------------+ +| :ref:`SDRAM_GENERATOR_END ` | :ref:`0xf0007010 ` | ++--------------------------------------------------------+--------------------------------------------+ +| :ref:`SDRAM_GENERATOR_LENGTH ` | :ref:`0xf0007014 ` | ++--------------------------------------------------------+--------------------------------------------+ +| :ref:`SDRAM_GENERATOR_RANDOM ` | :ref:`0xf0007018 ` | ++--------------------------------------------------------+--------------------------------------------+ +| :ref:`SDRAM_GENERATOR_TICKS ` | :ref:`0xf000701c ` | ++--------------------------------------------------------+--------------------------------------------+ + +SDRAM_GENERATOR_RESET +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x0 = 0xf0007000` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_RESET + + { + "reg": [ + {"name": "reset", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_GENERATOR_START +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x4 = 0xf0007004` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_START + + { + "reg": [ + {"name": "start", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_GENERATOR_DONE +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x8 = 0xf0007008` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_DONE + + { + "reg": [ + {"name": "done", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_GENERATOR_BASE +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0xc = 0xf000700c` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_BASE + + { + "reg": [ + {"name": "base[27:0]", "bits": 28}, + {"bits": 4}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_GENERATOR_END +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x10 = 0xf0007010` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_END + + { + "reg": [ + {"name": "end[27:0]", "bits": 28}, + {"bits": 4}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_GENERATOR_LENGTH +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x14 = 0xf0007014` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_LENGTH + + { + "reg": [ + {"name": "length[27:0]", "bits": 28}, + {"bits": 4}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_GENERATOR_RANDOM +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x18 = 0xf0007018` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_RANDOM + + { + "reg": [ + {"name": "data", "bits": 1}, + {"name": "addr", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------+ +| Field | Name | Description | ++=======+======+=============+ ++-------+------+-------------+ ++-------+------+-------------+ + +SDRAM_GENERATOR_TICKS +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x1c = 0xf000701c` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_TICKS + + { + "reg": [ + {"name": "ticks[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/arty/documentation/timer0.rst.txt b/_sources/build/arty/documentation/timer0.rst.txt new file mode 100644 index 000000000..4cf544f1c --- /dev/null +++ b/_sources/build/arty/documentation/timer0.rst.txt @@ -0,0 +1,228 @@ +TIMER0 +====== + +Timer +----- + +Provides a generic Timer core. + +The Timer is implemented as a countdown timer that can be used in various modes: + +- Polling : Returns current countdown value to software +- One-Shot: Loads itself and stops when value reaches ``0`` +- Periodic: (Re-)Loads itself when value reaches ``0`` + +``en`` register allows the user to enable/disable the Timer. When the Timer is enabled, it is +automatically loaded with the value of `load` register. + +When the Timer reaches ``0``, it is automatically reloaded with value of `reload` register. + +The user can latch the current countdown value by writing to ``update_value`` register, it will +update ``value`` register with current countdown value. + +To use the Timer in One-Shot mode, the user needs to: + +- Disable the timer +- Set the ``load`` register to the expected duration +- (Re-)Enable the Timer + +To use the Timer in Periodic mode, the user needs to: + +- Disable the Timer +- Set the ``load`` register to 0 +- Set the ``reload`` register to the expected period +- Enable the Timer + +For both modes, the CPU can be advertised by an IRQ that the duration/period has elapsed. (The +CPU can also do software polling with ``update_value`` and ``value`` to know the elapsed duration) + + +Register Listing for TIMER0 +--------------------------- + ++--------------------------------------------------+-----------------------------------------+ +| Register | Address | ++==================================================+=========================================+ +| :ref:`TIMER0_LOAD ` | :ref:`0xf0007800 ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_RELOAD ` | :ref:`0xf0007804 ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_EN ` | :ref:`0xf0007808 ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_UPDATE_VALUE ` | :ref:`0xf000780c ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_VALUE ` | :ref:`0xf0007810 ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_EV_STATUS ` | :ref:`0xf0007814 ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_EV_PENDING ` | :ref:`0xf0007818 ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_EV_ENABLE ` | :ref:`0xf000781c ` | ++--------------------------------------------------+-----------------------------------------+ + +TIMER0_LOAD +^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x0 = 0xf0007800` + + Load value when Timer is (re-)enabled. In One-Shot mode, the value written to + this register specifies the Timer's duration in clock cycles. + + .. wavedrom:: + :caption: TIMER0_LOAD + + { + "reg": [ + {"name": "load[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +TIMER0_RELOAD +^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x4 = 0xf0007804` + + Reload value when Timer reaches ``0``. In Periodic mode, the value written to + this register specify the Timer's period in clock cycles. + + .. wavedrom:: + :caption: TIMER0_RELOAD + + { + "reg": [ + {"name": "reload[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +TIMER0_EN +^^^^^^^^^ + +`Address: 0xf0007800 + 0x8 = 0xf0007808` + + Enable flag of the Timer. Set this flag to ``1`` to enable/start the Timer. Set + to ``0`` to disable the Timer. + + .. wavedrom:: + :caption: TIMER0_EN + + { + "reg": [ + {"name": "en", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +TIMER0_UPDATE_VALUE +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0xc = 0xf000780c` + + Update trigger for the current countdown value. A write to this register latches + the current countdown value to ``value`` register. + + .. wavedrom:: + :caption: TIMER0_UPDATE_VALUE + + { + "reg": [ + {"name": "update_value", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +TIMER0_VALUE +^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x10 = 0xf0007810` + + Latched countdown value. This value is updated by writing to ``update_value``. + + .. wavedrom:: + :caption: TIMER0_VALUE + + { + "reg": [ + {"name": "value[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +TIMER0_EV_STATUS +^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x14 = 0xf0007814` + + This register contains the current raw level of the zero event trigger. Writes + to this register have no effect. + + .. wavedrom:: + :caption: TIMER0_EV_STATUS + + { + "reg": [ + {"name": "zero", "bits": 1}, + {"bits": 31} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-----------------------------+ +| Field | Name | Description | ++=======+======+=============================+ +| [0] | ZERO | Level of the ``zero`` event | ++-------+------+-----------------------------+ + +TIMER0_EV_PENDING +^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x18 = 0xf0007818` + + When a zero event occurs, the corresponding bit will be set in this register. + To clear the Event, set the corresponding bit in this register. + + .. wavedrom:: + :caption: TIMER0_EV_PENDING + + { + "reg": [ + {"name": "zero", "bits": 1}, + {"bits": 31} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+--------------------------------------------------------------------------------+ +| Field | Name | Description | ++=======+======+================================================================================+ +| [0] | ZERO | `1` if a `zero` event occurred. This Event is triggered on a **falling** edge. | ++-------+------+--------------------------------------------------------------------------------+ + +TIMER0_EV_ENABLE +^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x1c = 0xf000781c` + + This register enables the corresponding zero events. Write a ``0`` to this + register to disable individual events. + + .. wavedrom:: + :caption: TIMER0_EV_ENABLE + + { + "reg": [ + {"name": "zero", "bits": 1}, + {"bits": 31} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+--------------------------------------------+ +| Field | Name | Description | ++=======+======+============================================+ +| [0] | ZERO | Write a ``1`` to enable the ``zero`` Event | ++-------+------+--------------------------------------------+ + diff --git a/_sources/build/arty/documentation/uart.rst.txt b/_sources/build/arty/documentation/uart.rst.txt new file mode 100644 index 000000000..2fff7323c --- /dev/null +++ b/_sources/build/arty/documentation/uart.rst.txt @@ -0,0 +1,388 @@ +UART +==== + +Register Listing for UART +------------------------- + ++------------------------------------------------------+-------------------------------------------+ +| Register | Address | ++======================================================+===========================================+ +| :ref:`UART_RXTX ` | :ref:`0xf0008000 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_TXFULL ` | :ref:`0xf0008004 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_RXEMPTY ` | :ref:`0xf0008008 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_EV_STATUS ` | :ref:`0xf000800c ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_EV_PENDING ` | :ref:`0xf0008010 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_EV_ENABLE ` | :ref:`0xf0008014 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_TXEMPTY ` | :ref:`0xf0008018 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_RXFULL ` | :ref:`0xf000801c ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_RXTX ` | :ref:`0xf0008020 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_TXFULL ` | :ref:`0xf0008024 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_RXEMPTY ` | :ref:`0xf0008028 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_EV_STATUS ` | :ref:`0xf000802c ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_EV_PENDING ` | :ref:`0xf0008030 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_EV_ENABLE ` | :ref:`0xf0008034 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_TXEMPTY ` | :ref:`0xf0008038 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_RXFULL ` | :ref:`0xf000803c ` | ++------------------------------------------------------+-------------------------------------------+ + +UART_RXTX +^^^^^^^^^ + +`Address: 0xf0008000 + 0x0 = 0xf0008000` + + + .. wavedrom:: + :caption: UART_RXTX + + { + "reg": [ + {"name": "rxtx[7:0]", "bits": 8}, + {"bits": 24}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +UART_TXFULL +^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x4 = 0xf0008004` + + TX FIFO Full. + + .. wavedrom:: + :caption: UART_TXFULL + + { + "reg": [ + {"name": "txfull", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_RXEMPTY +^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x8 = 0xf0008008` + + RX FIFO Empty. + + .. wavedrom:: + :caption: UART_RXEMPTY + + { + "reg": [ + {"name": "rxempty", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_EV_STATUS +^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0xc = 0xf000800c` + + This register contains the current raw level of the rx event trigger. Writes to + this register have no effect. + + .. wavedrom:: + :caption: UART_EV_STATUS + + { + "reg": [ + {"name": "tx", "bits": 1}, + {"name": "rx", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+---------------------------+ +| Field | Name | Description | ++=======+======+===========================+ +| [0] | TX | Level of the ``tx`` event | ++-------+------+---------------------------+ +| [1] | RX | Level of the ``rx`` event | ++-------+------+---------------------------+ + +UART_EV_PENDING +^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x10 = 0xf0008010` + + When a rx event occurs, the corresponding bit will be set in this register. To + clear the Event, set the corresponding bit in this register. + + .. wavedrom:: + :caption: UART_EV_PENDING + + { + "reg": [ + {"name": "tx", "bits": 1}, + {"name": "rx", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+------------------------------------------------------------------------------+ +| Field | Name | Description | ++=======+======+==============================================================================+ +| [0] | TX | `1` if a `tx` event occurred. This Event is triggered on a **falling** edge. | ++-------+------+------------------------------------------------------------------------------+ +| [1] | RX | `1` if a `rx` event occurred. This Event is triggered on a **falling** edge. | ++-------+------+------------------------------------------------------------------------------+ + +UART_EV_ENABLE +^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x14 = 0xf0008014` + + This register enables the corresponding rx events. Write a ``0`` to this + register to disable individual events. + + .. wavedrom:: + :caption: UART_EV_ENABLE + + { + "reg": [ + {"name": "tx", "bits": 1}, + {"name": "rx", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+------------------------------------------+ +| Field | Name | Description | ++=======+======+==========================================+ +| [0] | TX | Write a ``1`` to enable the ``tx`` Event | ++-------+------+------------------------------------------+ +| [1] | RX | Write a ``1`` to enable the ``rx`` Event | ++-------+------+------------------------------------------+ + +UART_TXEMPTY +^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x18 = 0xf0008018` + + TX FIFO Empty. + + .. wavedrom:: + :caption: UART_TXEMPTY + + { + "reg": [ + {"name": "txempty", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_RXFULL +^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x1c = 0xf000801c` + + RX FIFO Full. + + .. wavedrom:: + :caption: UART_RXFULL + + { + "reg": [ + {"name": "rxfull", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_XOVER_RXTX +^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x20 = 0xf0008020` + + + .. wavedrom:: + :caption: UART_XOVER_RXTX + + { + "reg": [ + {"name": "xover_rxtx[7:0]", "bits": 8}, + {"bits": 24}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +UART_XOVER_TXFULL +^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x24 = 0xf0008024` + + TX FIFO Full. + + .. wavedrom:: + :caption: UART_XOVER_TXFULL + + { + "reg": [ + {"name": "xover_txfull", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_XOVER_RXEMPTY +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x28 = 0xf0008028` + + RX FIFO Empty. + + .. wavedrom:: + :caption: UART_XOVER_RXEMPTY + + { + "reg": [ + {"name": "xover_rxempty", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_XOVER_EV_STATUS +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x2c = 0xf000802c` + + This register contains the current raw level of the rx event trigger. Writes to + this register have no effect. + + .. wavedrom:: + :caption: UART_XOVER_EV_STATUS + + { + "reg": [ + {"name": "tx", "bits": 1}, + {"name": "rx", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+---------------------------+ +| Field | Name | Description | ++=======+======+===========================+ +| [0] | TX | Level of the ``tx`` event | ++-------+------+---------------------------+ +| [1] | RX | Level of the ``rx`` event | ++-------+------+---------------------------+ + +UART_XOVER_EV_PENDING +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x30 = 0xf0008030` + + When a rx event occurs, the corresponding bit will be set in this register. To + clear the Event, set the corresponding bit in this register. + + .. wavedrom:: + :caption: UART_XOVER_EV_PENDING + + { + "reg": [ + {"name": "tx", "bits": 1}, + {"name": "rx", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+------------------------------------------------------------------------------+ +| Field | Name | Description | ++=======+======+==============================================================================+ +| [0] | TX | `1` if a `tx` event occurred. This Event is triggered on a **falling** edge. | ++-------+------+------------------------------------------------------------------------------+ +| [1] | RX | `1` if a `rx` event occurred. This Event is triggered on a **falling** edge. | ++-------+------+------------------------------------------------------------------------------+ + +UART_XOVER_EV_ENABLE +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x34 = 0xf0008034` + + This register enables the corresponding rx events. Write a ``0`` to this + register to disable individual events. + + .. wavedrom:: + :caption: UART_XOVER_EV_ENABLE + + { + "reg": [ + {"name": "tx", "bits": 1}, + {"name": "rx", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+------------------------------------------+ +| Field | Name | Description | ++=======+======+==========================================+ +| [0] | TX | Write a ``1`` to enable the ``tx`` Event | ++-------+------+------------------------------------------+ +| [1] | RX | Write a ``1`` to enable the ``rx`` Event | ++-------+------+------------------------------------------+ + +UART_XOVER_TXEMPTY +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x38 = 0xf0008038` + + TX FIFO Empty. + + .. wavedrom:: + :caption: UART_XOVER_TXEMPTY + + { + "reg": [ + {"name": "xover_txempty", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_XOVER_RXFULL +^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x3c = 0xf000803c` + + RX FIFO Full. + + .. wavedrom:: + :caption: UART_XOVER_RXFULL + + { + "reg": [ + {"name": "xover_rxfull", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/arty/documentation/writer.rst.txt b/_sources/build/arty/documentation/writer.rst.txt new file mode 100644 index 000000000..7065def1c --- /dev/null +++ b/_sources/build/arty/documentation/writer.rst.txt @@ -0,0 +1,251 @@ +WRITER +====== + + + +DMA DRAM writer. + +Allows to fill DRAM with a predefined pattern using DMA. + +Pattern +------- + + + Provides access to RAM to store access pattern: `mem_addr` and `mem_data`. + The pattern address space can be limited using the `data_mask`. + + For example, having `mem_adr` filled with `[ 0x04, 0x02, 0x03, ... ]` + and `mem_data` filled with `[ 0xff, 0xaa, 0x55, ... ]` and setting + `data_mask = 0b01`, the pattern [(address, data), ...] written will be: + `[(0x04, 0xff), (0x02, 0xaa), (0x04, 0xff), ...]` (wraps due to masking). + + DRAM memory range that is being accessed can be configured using `mem_mask`. + + To use this module, make sure that `ready` is 1, then write the desired + number of transfers to `count`. Writing to the `start` CSR will initialize + the operation. When the operation is ongoing `ready` will be 0. + + + +Register Listing for WRITER +--------------------------- + ++------------------------------------------------------------------------+----------------------------------------------------+ +| Register | Address | ++========================================================================+====================================================+ +| :ref:`WRITER_START ` | :ref:`0xf0003000 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_READY ` | :ref:`0xf0003004 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_MODULO ` | :ref:`0xf0003008 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_COUNT ` | :ref:`0xf000300c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_DONE ` | :ref:`0xf0003010 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_MEM_MASK ` | :ref:`0xf0003014 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_DATA_MASK ` | :ref:`0xf0003018 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_DATA_DIV ` | :ref:`0xf000301c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_INVERTER_DIVISOR_MASK ` | :ref:`0xf0003020 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_INVERTER_SELECTION_MASK ` | :ref:`0xf0003024 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_LAST_ADDRESS ` | :ref:`0xf0003028 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ + +WRITER_START +^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x0 = 0xf0003000` + + Write to the register starts the transfer (if ready=1) + + .. wavedrom:: + :caption: WRITER_START + + { + "reg": [ + {"name": "start", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +WRITER_READY +^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x4 = 0xf0003004` + + Indicates that the transfer is not ongoing + + .. wavedrom:: + :caption: WRITER_READY + + { + "reg": [ + {"name": "ready", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +WRITER_MODULO +^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x8 = 0xf0003008` + + When set use modulo to calculate DMA transfers address rather than bit masking + + .. wavedrom:: + :caption: WRITER_MODULO + + { + "reg": [ + {"name": "modulo", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +WRITER_COUNT +^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0xc = 0xf000300c` + + Desired number of DMA transfers + + .. wavedrom:: + :caption: WRITER_COUNT + + { + "reg": [ + {"name": "count[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +WRITER_DONE +^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x10 = 0xf0003010` + + Number of completed DMA transfers + + .. wavedrom:: + :caption: WRITER_DONE + + { + "reg": [ + {"name": "done[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +WRITER_MEM_MASK +^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x14 = 0xf0003014` + + DRAM address mask for DMA transfers + + .. wavedrom:: + :caption: WRITER_MEM_MASK + + { + "reg": [ + {"name": "mem_mask[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +WRITER_DATA_MASK +^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x18 = 0xf0003018` + + Pattern memory address mask + + .. wavedrom:: + :caption: WRITER_DATA_MASK + + { + "reg": [ + {"name": "data_mask[5:0]", "bits": 6}, + {"bits": 26}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +WRITER_DATA_DIV +^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x1c = 0xf000301c` + + Pattern memory address divisior-1 + + .. wavedrom:: + :caption: WRITER_DATA_DIV + + { + "reg": [ + {"name": "data_div[5:0]", "bits": 6}, + {"bits": 26}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +WRITER_INVERTER_DIVISOR_MASK +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x20 = 0xf0003020` + + Divisor mask for selecting rows for which pattern data gets inverted + + .. wavedrom:: + :caption: WRITER_INVERTER_DIVISOR_MASK + + { + "reg": [ + {"name": "inverter_divisor_mask[4:0]", "bits": 5}, + {"bits": 27}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +WRITER_INVERTER_SELECTION_MASK +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x24 = 0xf0003024` + + Selection mask for selecting rows for which pattern data gets inverted + + .. wavedrom:: + :caption: WRITER_INVERTER_SELECTION_MASK + + { + "reg": [ + {"name": "inverter_selection_mask[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +WRITER_LAST_ADDRESS +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x28 = 0xf0003028` + + Number of completed DMA transfers + + .. wavedrom:: + :caption: WRITER_LAST_ADDRESS + + { + "reg": [ + {"name": "last_address[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/ddr4_datacenter_test_board/documentation/controller_settings.rst.txt b/_sources/build/ddr4_datacenter_test_board/documentation/controller_settings.rst.txt new file mode 100644 index 000000000..cc67b4b83 --- /dev/null +++ b/_sources/build/ddr4_datacenter_test_board/documentation/controller_settings.rst.txt @@ -0,0 +1,34 @@ +CONTROLLER_SETTINGS +=================== + +Allows to change LiteDRAMController behaviour at runtime +-------------------------------------------------------- + + +Register Listing for CONTROLLER_SETTINGS +---------------------------------------- + ++------------------------------------------------------------------+-------------------------------------------------+ +| Register | Address | ++==================================================================+=================================================+ +| :ref:`CONTROLLER_SETTINGS_REFRESH ` | :ref:`0xf0001000 ` | ++------------------------------------------------------------------+-------------------------------------------------+ + +CONTROLLER_SETTINGS_REFRESH +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0001000 + 0x0 = 0xf0001000` + + Enable/disable Refresh commands sending + + .. wavedrom:: + :caption: CONTROLLER_SETTINGS_REFRESH + + { + "reg": [ + {"name": "refresh", "attr": 'reset: 1', "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/ddr4_datacenter_test_board/documentation/ctrl.rst.txt b/_sources/build/ddr4_datacenter_test_board/documentation/ctrl.rst.txt new file mode 100644 index 000000000..8e9663760 --- /dev/null +++ b/_sources/build/ddr4_datacenter_test_board/documentation/ctrl.rst.txt @@ -0,0 +1,78 @@ +CTRL +==== + +Register Listing for CTRL +------------------------- + ++------------------------------------------+-------------------------------------+ +| Register | Address | ++==========================================+=====================================+ +| :ref:`CTRL__RESET ` | :ref:`0xf0005000 ` | ++------------------------------------------+-------------------------------------+ +| :ref:`CTRL_SCRATCH ` | :ref:`0xf0005004 ` | ++------------------------------------------+-------------------------------------+ +| :ref:`CTRL_BUS_ERRORS ` | :ref:`0xf0005008 ` | ++------------------------------------------+-------------------------------------+ + +CTRL__RESET +^^^^^^^^^^^ + +`Address: 0xf0005000 + 0x0 = 0xf0005000` + + + .. wavedrom:: + :caption: CTRL__RESET + + { + "reg": [ + {"name": "soc_rst", "type": 4, "bits": 1}, + {"name": "cpu_rst", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+---------+------------------------------------------------------------------------+ +| Field | Name | Description | ++=======+=========+========================================================================+ +| [0] | SOC_RST | Write `1` to this register to reset the full SoC (Pulse Reset) | ++-------+---------+------------------------------------------------------------------------+ +| [1] | CPU_RST | Write `1` to this register to reset the CPU(s) of the SoC (Hold Reset) | ++-------+---------+------------------------------------------------------------------------+ + +CTRL_SCRATCH +^^^^^^^^^^^^ + +`Address: 0xf0005000 + 0x4 = 0xf0005004` + + Use this register as a scratch space to verify that software read/write accesses + to the Wishbone/CSR bus are working correctly. The initial reset value of + 0x1234578 can be used to verify endianness. + + .. wavedrom:: + :caption: CTRL_SCRATCH + + { + "reg": [ + {"name": "scratch[31:0]", "attr": 'reset: 305419896', "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +CTRL_BUS_ERRORS +^^^^^^^^^^^^^^^ + +`Address: 0xf0005000 + 0x8 = 0xf0005008` + + Total number of Wishbone bus errors (timeouts) since start. + + .. wavedrom:: + :caption: CTRL_BUS_ERRORS + + { + "reg": [ + {"name": "bus_errors[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/ddr4_datacenter_test_board/documentation/ddrctrl.rst.txt b/_sources/build/ddr4_datacenter_test_board/documentation/ddrctrl.rst.txt new file mode 100644 index 000000000..59563d8b1 --- /dev/null +++ b/_sources/build/ddr4_datacenter_test_board/documentation/ddrctrl.rst.txt @@ -0,0 +1,48 @@ +DDRCTRL +======= + +Register Listing for DDRCTRL +---------------------------- + ++------------------------------------------------+----------------------------------------+ +| Register | Address | ++================================================+========================================+ +| :ref:`DDRCTRL_INIT_DONE ` | :ref:`0xf0001800 ` | ++------------------------------------------------+----------------------------------------+ +| :ref:`DDRCTRL_INIT_ERROR ` | :ref:`0xf0001804 ` | ++------------------------------------------------+----------------------------------------+ + +DDRCTRL_INIT_DONE +^^^^^^^^^^^^^^^^^ + +`Address: 0xf0001800 + 0x0 = 0xf0001800` + + + .. wavedrom:: + :caption: DDRCTRL_INIT_DONE + + { + "reg": [ + {"name": "init_done", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRCTRL_INIT_ERROR +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0001800 + 0x4 = 0xf0001804` + + + .. wavedrom:: + :caption: DDRCTRL_INIT_ERROR + + { + "reg": [ + {"name": "init_error", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/ddr4_datacenter_test_board/documentation/ddrphy.rst.txt b/_sources/build/ddr4_datacenter_test_board/documentation/ddrphy.rst.txt new file mode 100644 index 000000000..fad60bc92 --- /dev/null +++ b/_sources/build/ddr4_datacenter_test_board/documentation/ddrphy.rst.txt @@ -0,0 +1,409 @@ +DDRPHY +====== + +Register Listing for DDRPHY +--------------------------- + ++----------------------------------------------------------------+------------------------------------------------+ +| Register | Address | ++================================================================+================================================+ +| :ref:`DDRPHY_RST ` | :ref:`0xf0000800 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_DLY_SEL ` | :ref:`0xf0000804 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_HALF_SYS8X_TAPS ` | :ref:`0xf0000808 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_WLEVEL_EN ` | :ref:`0xf000080c ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_WLEVEL_STROBE ` | :ref:`0xf0000810 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_CDLY_RST ` | :ref:`0xf0000814 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_CDLY_INC ` | :ref:`0xf0000818 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_RDLY_DQ_RST ` | :ref:`0xf000081c ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_RDLY_DQ_INC ` | :ref:`0xf0000820 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_RDLY_DQ_BITSLIP_RST ` | :ref:`0xf0000824 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_RDLY_DQ_BITSLIP ` | :ref:`0xf0000828 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_WDLY_DQ_RST ` | :ref:`0xf000082c ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_WDLY_DQ_INC ` | :ref:`0xf0000830 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_WDLY_DQS_RST ` | :ref:`0xf0000834 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_WDLY_DQS_INC ` | :ref:`0xf0000838 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_WDLY_DQ_BITSLIP_RST ` | :ref:`0xf000083c ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_WDLY_DQ_BITSLIP ` | :ref:`0xf0000840 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_RDPHASE ` | :ref:`0xf0000844 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_WRPHASE ` | :ref:`0xf0000848 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_ALERT ` | :ref:`0xf000084c ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_RST_ALERT ` | :ref:`0xf0000850 ` | ++----------------------------------------------------------------+------------------------------------------------+ + +DDRPHY_RST +^^^^^^^^^^ + +`Address: 0xf0000800 + 0x0 = 0xf0000800` + + + .. wavedrom:: + :caption: DDRPHY_RST + + { + "reg": [ + {"name": "rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_DLY_SEL +^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x4 = 0xf0000804` + + + .. wavedrom:: + :caption: DDRPHY_DLY_SEL + + { + "reg": [ + {"name": "dly_sel[7:0]", "bits": 8}, + {"bits": 24}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DDRPHY_HALF_SYS8X_TAPS +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x8 = 0xf0000808` + + + .. wavedrom:: + :caption: DDRPHY_HALF_SYS8X_TAPS + + { + "reg": [ + {"name": "half_sys8x_taps[4:0]", "attr": 'reset: 8', "bits": 5}, + {"bits": 27}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_WLEVEL_EN +^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xc = 0xf000080c` + + + .. wavedrom:: + :caption: DDRPHY_WLEVEL_EN + + { + "reg": [ + {"name": "wlevel_en", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_WLEVEL_STROBE +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x10 = 0xf0000810` + + + .. wavedrom:: + :caption: DDRPHY_WLEVEL_STROBE + + { + "reg": [ + {"name": "wlevel_strobe", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CDLY_RST +^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x14 = 0xf0000814` + + + .. wavedrom:: + :caption: DDRPHY_CDLY_RST + + { + "reg": [ + {"name": "cdly_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CDLY_INC +^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x18 = 0xf0000818` + + + .. wavedrom:: + :caption: DDRPHY_CDLY_INC + + { + "reg": [ + {"name": "cdly_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_RDLY_DQ_RST +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x1c = 0xf000081c` + + + .. wavedrom:: + :caption: DDRPHY_RDLY_DQ_RST + + { + "reg": [ + {"name": "rdly_dq_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_RDLY_DQ_INC +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x20 = 0xf0000820` + + + .. wavedrom:: + :caption: DDRPHY_RDLY_DQ_INC + + { + "reg": [ + {"name": "rdly_dq_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_RDLY_DQ_BITSLIP_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x24 = 0xf0000824` + + + .. wavedrom:: + :caption: DDRPHY_RDLY_DQ_BITSLIP_RST + + { + "reg": [ + {"name": "rdly_dq_bitslip_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_RDLY_DQ_BITSLIP +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x28 = 0xf0000828` + + + .. wavedrom:: + :caption: DDRPHY_RDLY_DQ_BITSLIP + + { + "reg": [ + {"name": "rdly_dq_bitslip", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_WDLY_DQ_RST +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x2c = 0xf000082c` + + + .. wavedrom:: + :caption: DDRPHY_WDLY_DQ_RST + + { + "reg": [ + {"name": "wdly_dq_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_WDLY_DQ_INC +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x30 = 0xf0000830` + + + .. wavedrom:: + :caption: DDRPHY_WDLY_DQ_INC + + { + "reg": [ + {"name": "wdly_dq_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_WDLY_DQS_RST +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x34 = 0xf0000834` + + + .. wavedrom:: + :caption: DDRPHY_WDLY_DQS_RST + + { + "reg": [ + {"name": "wdly_dqs_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_WDLY_DQS_INC +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x38 = 0xf0000838` + + + .. wavedrom:: + :caption: DDRPHY_WDLY_DQS_INC + + { + "reg": [ + {"name": "wdly_dqs_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_WDLY_DQ_BITSLIP_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x3c = 0xf000083c` + + + .. wavedrom:: + :caption: DDRPHY_WDLY_DQ_BITSLIP_RST + + { + "reg": [ + {"name": "wdly_dq_bitslip_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_WDLY_DQ_BITSLIP +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x40 = 0xf0000840` + + + .. wavedrom:: + :caption: DDRPHY_WDLY_DQ_BITSLIP + + { + "reg": [ + {"name": "wdly_dq_bitslip", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_RDPHASE +^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x44 = 0xf0000844` + + + .. wavedrom:: + :caption: DDRPHY_RDPHASE + + { + "reg": [ + {"name": "rdphase[1:0]", "attr": 'reset: 3', "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_WRPHASE +^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x48 = 0xf0000848` + + + .. wavedrom:: + :caption: DDRPHY_WRPHASE + + { + "reg": [ + {"name": "wrphase[1:0]", "attr": 'reset: 3', "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_ALERT +^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x4c = 0xf000084c` + + + .. wavedrom:: + :caption: DDRPHY_ALERT + + { + "reg": [ + {"name": "alert", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_RST_ALERT +^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x50 = 0xf0000850` + + + .. wavedrom:: + :caption: DDRPHY_RST_ALERT + + { + "reg": [ + {"name": "rst_alert", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/ddr4_datacenter_test_board/documentation/dfi_switch.rst.txt b/_sources/build/ddr4_datacenter_test_board/documentation/dfi_switch.rst.txt new file mode 100644 index 000000000..718d8cc34 --- /dev/null +++ b/_sources/build/ddr4_datacenter_test_board/documentation/dfi_switch.rst.txt @@ -0,0 +1,71 @@ +DFI_SWITCH +========== + +Register Listing for DFI_SWITCH +------------------------------- + ++--------------------------------------------------------------+-----------------------------------------------+ +| Register | Address | ++==============================================================+===============================================+ +| :ref:`DFI_SWITCH_REFRESH_COUNT ` | :ref:`0xf0003800 ` | ++--------------------------------------------------------------+-----------------------------------------------+ +| :ref:`DFI_SWITCH_AT_REFRESH ` | :ref:`0xf0003804 ` | ++--------------------------------------------------------------+-----------------------------------------------+ +| :ref:`DFI_SWITCH_REFRESH_UPDATE ` | :ref:`0xf0003808 ` | ++--------------------------------------------------------------+-----------------------------------------------+ + +DFI_SWITCH_REFRESH_COUNT +^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003800 + 0x0 = 0xf0003800` + + Count of all refresh commands issued (both by Memory Controller and Payload + Executor). Value is latched from internal counter on mode trasition: MC -> PE or + by writing to the `refresh_update` CSR. + + .. wavedrom:: + :caption: DFI_SWITCH_REFRESH_COUNT + + { + "reg": [ + {"name": "refresh_count[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DFI_SWITCH_AT_REFRESH +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003800 + 0x4 = 0xf0003804` + + If set to a value different than 0 the mode transition MC -> PE will be peformed + only when the value of this register matches the current refresh commands count. + + .. wavedrom:: + :caption: DFI_SWITCH_AT_REFRESH + + { + "reg": [ + {"name": "at_refresh[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DFI_SWITCH_REFRESH_UPDATE +^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003800 + 0x8 = 0xf0003808` + + Force an update of the `refresh_count` CSR. + + .. wavedrom:: + :caption: DFI_SWITCH_REFRESH_UPDATE + + { + "reg": [ + {"name": "refresh_update", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/ddr4_datacenter_test_board/documentation/ethphy.rst.txt b/_sources/build/ddr4_datacenter_test_board/documentation/ethphy.rst.txt new file mode 100644 index 000000000..29c3d6a1e --- /dev/null +++ b/_sources/build/ddr4_datacenter_test_board/documentation/ethphy.rst.txt @@ -0,0 +1,81 @@ +ETHPHY +====== + +Register Listing for ETHPHY +--------------------------- + ++--------------------------------------------+--------------------------------------+ +| Register | Address | ++============================================+======================================+ +| :ref:`ETHPHY_CRG_RESET ` | :ref:`0xf0005800 ` | ++--------------------------------------------+--------------------------------------+ +| :ref:`ETHPHY_MDIO_W ` | :ref:`0xf0005804 ` | ++--------------------------------------------+--------------------------------------+ +| :ref:`ETHPHY_MDIO_R ` | :ref:`0xf0005808 ` | ++--------------------------------------------+--------------------------------------+ + +ETHPHY_CRG_RESET +^^^^^^^^^^^^^^^^ + +`Address: 0xf0005800 + 0x0 = 0xf0005800` + + + .. wavedrom:: + :caption: ETHPHY_CRG_RESET + + { + "reg": [ + {"name": "crg_reset", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +ETHPHY_MDIO_W +^^^^^^^^^^^^^ + +`Address: 0xf0005800 + 0x4 = 0xf0005804` + + + .. wavedrom:: + :caption: ETHPHY_MDIO_W + + { + "reg": [ + {"name": "mdc", "bits": 1}, + {"name": "oe", "bits": 1}, + {"name": "w", "bits": 1}, + {"bits": 29} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------+ +| Field | Name | Description | ++=======+======+=============+ ++-------+------+-------------+ ++-------+------+-------------+ ++-------+------+-------------+ + +ETHPHY_MDIO_R +^^^^^^^^^^^^^ + +`Address: 0xf0005800 + 0x8 = 0xf0005808` + + + .. wavedrom:: + :caption: ETHPHY_MDIO_R + + { + "reg": [ + {"name": "r", "bits": 1}, + {"bits": 31} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------+ +| Field | Name | Description | ++=======+======+=============+ ++-------+------+-------------+ + diff --git a/_sources/build/ddr4_datacenter_test_board/documentation/i2c.rst.txt b/_sources/build/ddr4_datacenter_test_board/documentation/i2c.rst.txt new file mode 100644 index 000000000..2771d3bc0 --- /dev/null +++ b/_sources/build/ddr4_datacenter_test_board/documentation/i2c.rst.txt @@ -0,0 +1,62 @@ +I2C +=== + +Register Listing for I2C +------------------------ + ++----------------------+---------------------------+ +| Register | Address | ++======================+===========================+ +| :ref:`I2C_W ` | :ref:`0xf0004800 ` | ++----------------------+---------------------------+ +| :ref:`I2C_R ` | :ref:`0xf0004804 ` | ++----------------------+---------------------------+ + +I2C_W +^^^^^ + +`Address: 0xf0004800 + 0x0 = 0xf0004800` + + + .. wavedrom:: + :caption: I2C_W + + { + "reg": [ + {"name": "scl", "attr": '1', "bits": 1}, + {"name": "oe", "bits": 1}, + {"name": "sda", "attr": '1', "bits": 1}, + {"bits": 29} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------+ +| Field | Name | Description | ++=======+======+=============+ ++-------+------+-------------+ ++-------+------+-------------+ ++-------+------+-------------+ + +I2C_R +^^^^^ + +`Address: 0xf0004800 + 0x4 = 0xf0004804` + + + .. wavedrom:: + :caption: I2C_R + + { + "reg": [ + {"name": "sda", "bits": 1}, + {"bits": 31} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------+ +| Field | Name | Description | ++=======+======+=============+ ++-------+------+-------------+ + diff --git a/_sources/build/ddr4_datacenter_test_board/documentation/identifier_mem.rst.txt b/_sources/build/ddr4_datacenter_test_board/documentation/identifier_mem.rst.txt new file mode 100644 index 000000000..59e4df69c --- /dev/null +++ b/_sources/build/ddr4_datacenter_test_board/documentation/identifier_mem.rst.txt @@ -0,0 +1,30 @@ +IDENTIFIER_MEM +============== + +Register Listing for IDENTIFIER_MEM +----------------------------------- + ++----------------------------------------+------------------------------------+ +| Register | Address | ++========================================+====================================+ +| :ref:`IDENTIFIER_MEM ` | :ref:`0xf0006000 ` | ++----------------------------------------+------------------------------------+ + +IDENTIFIER_MEM +^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x0 = 0xf0006000` + + 8 x 109-bit memory + + .. wavedrom:: + :caption: IDENTIFIER_MEM + + { + "reg": [ + {"name": "identifier_mem[7:0]", "bits": 8}, + {"bits": 24}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/ddr4_datacenter_test_board/documentation/index.rst.txt b/_sources/build/ddr4_datacenter_test_board/documentation/index.rst.txt new file mode 100644 index 000000000..ede49bed0 --- /dev/null +++ b/_sources/build/ddr4_datacenter_test_board/documentation/index.rst.txt @@ -0,0 +1,38 @@ +=========================================================== +Documentation for Row Hammer Tester Data Center DRAM Tester +=========================================================== + + + +Modules +======= + +.. toctree:: + :maxdepth: 1 + + interrupts + +Register Groups +=============== + +.. toctree:: + :maxdepth: 1 + + leds + ddrphy + controller_settings + ddrctrl + rowhammer + writer + reader + dfi_switch + payload_executor + i2c + ctrl + ethphy + identifier_mem + sdram + sdram_checker + sdram_generator + timer0 + uart diff --git a/_sources/build/ddr4_datacenter_test_board/documentation/interrupts.rst.txt b/_sources/build/ddr4_datacenter_test_board/documentation/interrupts.rst.txt new file mode 100644 index 000000000..bfc948fb1 --- /dev/null +++ b/_sources/build/ddr4_datacenter_test_board/documentation/interrupts.rst.txt @@ -0,0 +1,22 @@ +Interrupt Controller +==================== + +This device has an ``EventManager``-based interrupt system. Individual modules +generate `events` which are wired into a central interrupt controller. + +When an interrupt occurs, you should look the interrupt number up in the CPU- +specific interrupt table and then call the relevant module. + +Assigned Interrupts +------------------- + +The following interrupts are assigned on this system: + ++-----------+------------------------+ +| Interrupt | Module | ++===========+========================+ +| 1 | :doc:`TIMER0 ` | ++-----------+------------------------+ +| 0 | :doc:`UART ` | ++-----------+------------------------+ + diff --git a/_sources/build/ddr4_datacenter_test_board/documentation/leds.rst.txt b/_sources/build/ddr4_datacenter_test_board/documentation/leds.rst.txt new file mode 100644 index 000000000..7d5de2ee2 --- /dev/null +++ b/_sources/build/ddr4_datacenter_test_board/documentation/leds.rst.txt @@ -0,0 +1,30 @@ +LEDS +==== + +Register Listing for LEDS +------------------------- + ++----------------------------+------------------------------+ +| Register | Address | ++============================+==============================+ +| :ref:`LEDS_OUT ` | :ref:`0xf0000000 ` | ++----------------------------+------------------------------+ + +LEDS_OUT +^^^^^^^^ + +`Address: 0xf0000000 + 0x0 = 0xf0000000` + + Led Output(s) Control. + + .. wavedrom:: + :caption: LEDS_OUT + + { + "reg": [ + {"name": "out[4:0]", "bits": 5}, + {"bits": 27}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/ddr4_datacenter_test_board/documentation/payload_executor.rst.txt b/_sources/build/ddr4_datacenter_test_board/documentation/payload_executor.rst.txt new file mode 100644 index 000000000..96fce0378 --- /dev/null +++ b/_sources/build/ddr4_datacenter_test_board/documentation/payload_executor.rst.txt @@ -0,0 +1,137 @@ +PAYLOAD_EXECUTOR +================ + + + + Executes the DRAM payload from memory + + + **Instruction decoder** + + All instructions are 32-bit. The format of most instructions is the same, + except for the LOOP instruction, which has a constant TIMESLICE of 1. + + NOOP with a TIMESLICE of 0 is a special case which is interpreted as + STOP instruction. When this instruction is encountered execution gets + finished immediately. + + **NOTE:** TIMESLICE is the number of cycles the instruction will take. This + means that instructions other than NOOP that use TIMESLICE=0 are illegal + (although will silently be executed as having TIMESLICE=1). + + **NOTE2:** LOOP instruction will *jump* COUNT times, meaning that the "code" + inside the loop will effectively be executed COUNT+1 times. + + Op codes: + ++------+-------+ ++ Op + Value + ++======+=======+ ++ NOOP | 0b000 + ++------+-------+ ++ LOOP | 0b111 + ++------+-------+ ++ ACT | 0b100 + ++------+-------+ ++ PRE | 0b101 + ++------+-------+ ++ REF | 0b110 + ++------+-------+ ++ ZQC | 0b001 + ++------+-------+ ++ READ | 0b010 + ++------+-------+ + + Instruction format:: + + LSB MSB + dfi: OP_CODE | TIMESLICE | ADDRESS + noop: OP_CODE | TIMESLICE_NOOP + loop: OP_CODE | COUNT | JUMP + stop: | 0 + + Where ADDRESS depends on the DFI command and is one of:: + + LSB MSB + RANK | BANK | COLUMN + RANK | BANK | ROW + + + +Register Listing for PAYLOAD_EXECUTOR +------------------------------------- + ++------------------------------------------------------------------+-------------------------------------------------+ +| Register | Address | ++==================================================================+=================================================+ +| :ref:`PAYLOAD_EXECUTOR_START ` | :ref:`0xf0004000 ` | ++------------------------------------------------------------------+-------------------------------------------------+ +| :ref:`PAYLOAD_EXECUTOR_STATUS ` | :ref:`0xf0004004 ` | ++------------------------------------------------------------------+-------------------------------------------------+ +| :ref:`PAYLOAD_EXECUTOR_READ_COUNT ` | :ref:`0xf0004008 ` | ++------------------------------------------------------------------+-------------------------------------------------+ + +PAYLOAD_EXECUTOR_START +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0004000 + 0x0 = 0xf0004000` + + Writing to this register initializes payload execution + + .. wavedrom:: + :caption: PAYLOAD_EXECUTOR_START + + { + "reg": [ + {"name": "start", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +PAYLOAD_EXECUTOR_STATUS +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0004000 + 0x4 = 0xf0004004` + + Payload executor status register + + .. wavedrom:: + :caption: PAYLOAD_EXECUTOR_STATUS + + { + "reg": [ + {"name": "ready", "bits": 1}, + {"name": "overflow", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+----------+---------------------------------------------------------------------------------+ +| Field | Name | Description | ++=======+==========+=================================================================================+ +| [0] | READY | Indicates that the executor is not running | ++-------+----------+---------------------------------------------------------------------------------+ +| [1] | OVERFLOW | Indicates the scratchpad memory address counter has overflown due to the number | +| | | of READ commands sent during execution | ++-------+----------+---------------------------------------------------------------------------------+ + +PAYLOAD_EXECUTOR_READ_COUNT +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0004000 + 0x8 = 0xf0004008` + + Number of data from READ commands that is stored in the scratchpad memory + + .. wavedrom:: + :caption: PAYLOAD_EXECUTOR_READ_COUNT + + { + "reg": [ + {"name": "read_count[4:0]", "bits": 5}, + {"bits": 27}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/ddr4_datacenter_test_board/documentation/reader.rst.txt b/_sources/build/ddr4_datacenter_test_board/documentation/reader.rst.txt new file mode 100644 index 000000000..116392e53 --- /dev/null +++ b/_sources/build/ddr4_datacenter_test_board/documentation/reader.rst.txt @@ -0,0 +1,652 @@ +READER +====== + + + +DMA DRAM reader. + +Allows to check DRAM contents against a predefined pattern using DMA. + +Pattern +------- + + + Provides access to RAM to store access pattern: `mem_addr` and `mem_data`. + The pattern address space can be limited using the `data_mask`. + + For example, having `mem_adr` filled with `[ 0x04, 0x02, 0x03, ... ]` + and `mem_data` filled with `[ 0xff, 0xaa, 0x55, ... ]` and setting + `data_mask = 0b01`, the pattern [(address, data), ...] written will be: + `[(0x04, 0xff), (0x02, 0xaa), (0x04, 0xff), ...]` (wraps due to masking). + + DRAM memory range that is being accessed can be configured using `mem_mask`. + + To use this module, make sure that `ready` is 1, then write the desired + number of transfers to `count`. Writing to the `start` CSR will initialize + the operation. When the operation is ongoing `ready` will be 0. + + +Reading errors +-------------- + +This module allows to check the locations of errors in the memory. +It scans the configured memory area and compares the values read to +the predefined pattern. If `skip_fifo` is 0, this module will stop +after each error encountered, so that it can be examined. Wait until +the `error_ready` CSR is 1. Then use the CSRs `error_offset`, +`error_data` and `error_expected` to examine the errors in the current +transfer. To continue reading, write 1 to `error_continue` CSR. +Setting `skip_fifo` to 1 will disable this behaviour entirely. + +The final number of errors can be read from `error_count`. +NOTE: This value represents the number of erroneous *DMA transfers*. + +The current progress can be read from the `done` CSR. + + +Register Listing for READER +--------------------------- + ++------------------------------------------------------------------------+----------------------------------------------------+ +| Register | Address | ++========================================================================+====================================================+ +| :ref:`READER_START ` | :ref:`0xf0003000 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_READY ` | :ref:`0xf0003004 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_MODULO ` | :ref:`0xf0003008 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_COUNT ` | :ref:`0xf000300c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_DONE ` | :ref:`0xf0003010 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_MEM_MASK ` | :ref:`0xf0003014 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_DATA_MASK ` | :ref:`0xf0003018 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_DATA_DIV ` | :ref:`0xf000301c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_INVERTER_DIVISOR_MASK ` | :ref:`0xf0003020 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_INVERTER_SELECTION_MASK ` | :ref:`0xf0003024 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_COUNT ` | :ref:`0xf0003028 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_SKIP_FIFO ` | :ref:`0xf000302c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_OFFSET ` | :ref:`0xf0003030 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA7 ` | :ref:`0xf0003034 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA6 ` | :ref:`0xf0003038 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA5 ` | :ref:`0xf000303c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA4 ` | :ref:`0xf0003040 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA3 ` | :ref:`0xf0003044 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA2 ` | :ref:`0xf0003048 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA1 ` | :ref:`0xf000304c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA0 ` | :ref:`0xf0003050 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED7 ` | :ref:`0xf0003054 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED6 ` | :ref:`0xf0003058 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED5 ` | :ref:`0xf000305c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED4 ` | :ref:`0xf0003060 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED3 ` | :ref:`0xf0003064 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED2 ` | :ref:`0xf0003068 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED1 ` | :ref:`0xf000306c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED0 ` | :ref:`0xf0003070 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_READY ` | :ref:`0xf0003074 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_CONTINUE ` | :ref:`0xf0003078 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ + +READER_START +^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x0 = 0xf0003000` + + Write to the register starts the transfer (if ready=1) + + .. wavedrom:: + :caption: READER_START + + { + "reg": [ + {"name": "start", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_READY +^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x4 = 0xf0003004` + + Indicates that the transfer is not ongoing + + .. wavedrom:: + :caption: READER_READY + + { + "reg": [ + {"name": "ready", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_MODULO +^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x8 = 0xf0003008` + + When set use modulo to calculate DMA transfers address rather than bit masking + + .. wavedrom:: + :caption: READER_MODULO + + { + "reg": [ + {"name": "modulo", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_COUNT +^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0xc = 0xf000300c` + + Desired number of DMA transfers + + .. wavedrom:: + :caption: READER_COUNT + + { + "reg": [ + {"name": "count[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_DONE +^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x10 = 0xf0003010` + + Number of completed DMA transfers + + .. wavedrom:: + :caption: READER_DONE + + { + "reg": [ + {"name": "done[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_MEM_MASK +^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x14 = 0xf0003014` + + DRAM address mask for DMA transfers + + .. wavedrom:: + :caption: READER_MEM_MASK + + { + "reg": [ + {"name": "mem_mask[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_DATA_MASK +^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x18 = 0xf0003018` + + Pattern memory address mask + + .. wavedrom:: + :caption: READER_DATA_MASK + + { + "reg": [ + {"name": "data_mask[4:0]", "bits": 5}, + {"bits": 27}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_DATA_DIV +^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x1c = 0xf000301c` + + Pattern memory address divisior-1 + + .. wavedrom:: + :caption: READER_DATA_DIV + + { + "reg": [ + {"name": "data_div[4:0]", "bits": 5}, + {"bits": 27}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_INVERTER_DIVISOR_MASK +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x20 = 0xf0003020` + + Divisor mask for selecting rows for which pattern data gets inverted + + .. wavedrom:: + :caption: READER_INVERTER_DIVISOR_MASK + + { + "reg": [ + {"name": "inverter_divisor_mask[4:0]", "bits": 5}, + {"bits": 27}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_INVERTER_SELECTION_MASK +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x24 = 0xf0003024` + + Selection mask for selecting rows for which pattern data gets inverted + + .. wavedrom:: + :caption: READER_INVERTER_SELECTION_MASK + + { + "reg": [ + {"name": "inverter_selection_mask[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_COUNT +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x28 = 0xf0003028` + + Number of errors detected + + .. wavedrom:: + :caption: READER_ERROR_COUNT + + { + "reg": [ + {"name": "error_count[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_SKIP_FIFO +^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x2c = 0xf000302c` + + Skip waiting for user to read the errors FIFO + + .. wavedrom:: + :caption: READER_SKIP_FIFO + + { + "reg": [ + {"name": "skip_fifo", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_ERROR_OFFSET +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x30 = 0xf0003030` + + Current offset of the error + + .. wavedrom:: + :caption: READER_ERROR_OFFSET + + { + "reg": [ + {"name": "error_offset[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA7 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x34 = 0xf0003034` + + Bits 224-255 of `READER_ERROR_DATA`. Erroneous value read from DRAM memory + + .. wavedrom:: + :caption: READER_ERROR_DATA7 + + { + "reg": [ + {"name": "error_data[255:224]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA6 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x38 = 0xf0003038` + + Bits 192-223 of `READER_ERROR_DATA`. + + .. wavedrom:: + :caption: READER_ERROR_DATA6 + + { + "reg": [ + {"name": "error_data[223:192]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA5 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x3c = 0xf000303c` + + Bits 160-191 of `READER_ERROR_DATA`. + + .. wavedrom:: + :caption: READER_ERROR_DATA5 + + { + "reg": [ + {"name": "error_data[191:160]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA4 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x40 = 0xf0003040` + + Bits 128-159 of `READER_ERROR_DATA`. + + .. wavedrom:: + :caption: READER_ERROR_DATA4 + + { + "reg": [ + {"name": "error_data[159:128]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA3 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x44 = 0xf0003044` + + Bits 96-127 of `READER_ERROR_DATA`. + + .. wavedrom:: + :caption: READER_ERROR_DATA3 + + { + "reg": [ + {"name": "error_data[127:96]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA2 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x48 = 0xf0003048` + + Bits 64-95 of `READER_ERROR_DATA`. + + .. wavedrom:: + :caption: READER_ERROR_DATA2 + + { + "reg": [ + {"name": "error_data[95:64]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA1 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x4c = 0xf000304c` + + Bits 32-63 of `READER_ERROR_DATA`. + + .. wavedrom:: + :caption: READER_ERROR_DATA1 + + { + "reg": [ + {"name": "error_data[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA0 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x50 = 0xf0003050` + + Bits 0-31 of `READER_ERROR_DATA`. + + .. wavedrom:: + :caption: READER_ERROR_DATA0 + + { + "reg": [ + {"name": "error_data[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED7 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x54 = 0xf0003054` + + Bits 224-255 of `READER_ERROR_EXPECTED`. Value expected to be read from DRAM + memory + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED7 + + { + "reg": [ + {"name": "error_expected[255:224]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED6 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x58 = 0xf0003058` + + Bits 192-223 of `READER_ERROR_EXPECTED`. + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED6 + + { + "reg": [ + {"name": "error_expected[223:192]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED5 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x5c = 0xf000305c` + + Bits 160-191 of `READER_ERROR_EXPECTED`. + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED5 + + { + "reg": [ + {"name": "error_expected[191:160]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED4 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x60 = 0xf0003060` + + Bits 128-159 of `READER_ERROR_EXPECTED`. + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED4 + + { + "reg": [ + {"name": "error_expected[159:128]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED3 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x64 = 0xf0003064` + + Bits 96-127 of `READER_ERROR_EXPECTED`. + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED3 + + { + "reg": [ + {"name": "error_expected[127:96]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED2 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x68 = 0xf0003068` + + Bits 64-95 of `READER_ERROR_EXPECTED`. + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED2 + + { + "reg": [ + {"name": "error_expected[95:64]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED1 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x6c = 0xf000306c` + + Bits 32-63 of `READER_ERROR_EXPECTED`. + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED1 + + { + "reg": [ + {"name": "error_expected[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED0 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x70 = 0xf0003070` + + Bits 0-31 of `READER_ERROR_EXPECTED`. + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED0 + + { + "reg": [ + {"name": "error_expected[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_READY +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x74 = 0xf0003074` + + Error detected and ready to read + + .. wavedrom:: + :caption: READER_ERROR_READY + + { + "reg": [ + {"name": "error_ready", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_ERROR_CONTINUE +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x78 = 0xf0003078` + + Continue reading until the next error + + .. wavedrom:: + :caption: READER_ERROR_CONTINUE + + { + "reg": [ + {"name": "error_continue", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/ddr4_datacenter_test_board/documentation/rowhammer.rst.txt b/_sources/build/ddr4_datacenter_test_board/documentation/rowhammer.rst.txt new file mode 100644 index 000000000..4056995d8 --- /dev/null +++ b/_sources/build/ddr4_datacenter_test_board/documentation/rowhammer.rst.txt @@ -0,0 +1,102 @@ +ROWHAMMER +========= + + + +Row Hammer DMA attacker + +This module allows to perform a Row Hammer attack by configuring it with +two addresses that map to different rows of a single bank. When enabled, +it will perform alternating DMA reads from the given locations, which will +result in the DRAM controller having to repeatedly open/close rows at each +read access. + + +Register Listing for ROWHAMMER +------------------------------ + ++------------------------------------------------+----------------------------------------+ +| Register | Address | ++================================================+========================================+ +| :ref:`ROWHAMMER_ENABLED ` | :ref:`0xf0002000 ` | ++------------------------------------------------+----------------------------------------+ +| :ref:`ROWHAMMER_ADDRESS1 ` | :ref:`0xf0002004 ` | ++------------------------------------------------+----------------------------------------+ +| :ref:`ROWHAMMER_ADDRESS2 ` | :ref:`0xf0002008 ` | ++------------------------------------------------+----------------------------------------+ +| :ref:`ROWHAMMER_COUNT ` | :ref:`0xf000200c ` | ++------------------------------------------------+----------------------------------------+ + +ROWHAMMER_ENABLED +^^^^^^^^^^^^^^^^^ + +`Address: 0xf0002000 + 0x0 = 0xf0002000` + + Used to start/stop the operation of the module + + .. wavedrom:: + :caption: ROWHAMMER_ENABLED + + { + "reg": [ + {"name": "enabled", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +ROWHAMMER_ADDRESS1 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0002000 + 0x4 = 0xf0002004` + + First attacked address + + .. wavedrom:: + :caption: ROWHAMMER_ADDRESS1 + + { + "reg": [ + {"name": "address1[27:0]", "bits": 28}, + {"bits": 4}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +ROWHAMMER_ADDRESS2 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0002000 + 0x8 = 0xf0002008` + + Second attacked address + + .. wavedrom:: + :caption: ROWHAMMER_ADDRESS2 + + { + "reg": [ + {"name": "address2[27:0]", "bits": 28}, + {"bits": 4}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +ROWHAMMER_COUNT +^^^^^^^^^^^^^^^ + +`Address: 0xf0002000 + 0xc = 0xf000200c` + + This is the number of DMA accesses performed. When the module is enabled, the + value can be freely read. When the module is disabled, the register is clear-on- + write and has to be read before the next attack. + + .. wavedrom:: + :caption: ROWHAMMER_COUNT + + { + "reg": [ + {"name": "count[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/ddr4_datacenter_test_board/documentation/sdram.rst.txt b/_sources/build/ddr4_datacenter_test_board/documentation/sdram.rst.txt new file mode 100644 index 000000000..ee688ad9c --- /dev/null +++ b/_sources/build/ddr4_datacenter_test_board/documentation/sdram.rst.txt @@ -0,0 +1,1631 @@ +SDRAM +===== + +Register Listing for SDRAM +-------------------------- + ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| Register | Address | ++==================================================================================+=========================================================+ +| :ref:`SDRAM_DFII_CONTROL ` | :ref:`0xf0006800 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI0_COMMAND ` | :ref:`0xf0006804 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI0_COMMAND_ISSUE ` | :ref:`0xf0006808 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI0_ADDRESS ` | :ref:`0xf000680c ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI0_BADDRESS ` | :ref:`0xf0006810 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI0_WRDATA1 ` | :ref:`0xf0006814 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI0_WRDATA0 ` | :ref:`0xf0006818 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI0_RDDATA1 ` | :ref:`0xf000681c ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI0_RDDATA0 ` | :ref:`0xf0006820 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI1_COMMAND ` | :ref:`0xf0006824 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI1_COMMAND_ISSUE ` | :ref:`0xf0006828 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI1_ADDRESS ` | :ref:`0xf000682c ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI1_BADDRESS ` | :ref:`0xf0006830 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI1_WRDATA1 ` | :ref:`0xf0006834 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI1_WRDATA0 ` | :ref:`0xf0006838 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI1_RDDATA1 ` | :ref:`0xf000683c ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI1_RDDATA0 ` | :ref:`0xf0006840 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI2_COMMAND ` | :ref:`0xf0006844 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI2_COMMAND_ISSUE ` | :ref:`0xf0006848 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI2_ADDRESS ` | :ref:`0xf000684c ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI2_BADDRESS ` | :ref:`0xf0006850 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI2_WRDATA1 ` | :ref:`0xf0006854 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI2_WRDATA0 ` | :ref:`0xf0006858 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI2_RDDATA1 ` | :ref:`0xf000685c ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI2_RDDATA0 ` | :ref:`0xf0006860 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI3_COMMAND ` | :ref:`0xf0006864 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI3_COMMAND_ISSUE ` | :ref:`0xf0006868 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI3_ADDRESS ` | :ref:`0xf000686c ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI3_BADDRESS ` | :ref:`0xf0006870 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI3_WRDATA1 ` | :ref:`0xf0006874 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI3_WRDATA0 ` | :ref:`0xf0006878 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI3_RDDATA1 ` | :ref:`0xf000687c ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI3_RDDATA0 ` | :ref:`0xf0006880 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRP ` | :ref:`0xf0006884 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRCD ` | :ref:`0xf0006888 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TWR ` | :ref:`0xf000688c ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TWTR ` | :ref:`0xf0006890 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TREFI ` | :ref:`0xf0006894 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRFC ` | :ref:`0xf0006898 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TFAW ` | :ref:`0xf000689c ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TCCD ` | :ref:`0xf00068a0 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TCCD_WR ` | :ref:`0xf00068a4 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRTP ` | :ref:`0xf00068a8 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRRD ` | :ref:`0xf00068ac ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRC ` | :ref:`0xf00068b0 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRAS ` | :ref:`0xf00068b4 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TZQCS ` | :ref:`0xf00068b8 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_0 ` | :ref:`0xf00068bc ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_0 ` | :ref:`0xf00068c0 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_1 ` | :ref:`0xf00068c4 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_1 ` | :ref:`0xf00068c8 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_2 ` | :ref:`0xf00068cc ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_2 ` | :ref:`0xf00068d0 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_3 ` | :ref:`0xf00068d4 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_3 ` | :ref:`0xf00068d8 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_4 ` | :ref:`0xf00068dc ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_4 ` | :ref:`0xf00068e0 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_5 ` | :ref:`0xf00068e4 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_5 ` | :ref:`0xf00068e8 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_6 ` | :ref:`0xf00068ec ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_6 ` | :ref:`0xf00068f0 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_7 ` | :ref:`0xf00068f4 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_7 ` | :ref:`0xf00068f8 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_8 ` | :ref:`0xf00068fc ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_8 ` | :ref:`0xf0006900 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_9 ` | :ref:`0xf0006904 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_9 ` | :ref:`0xf0006908 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_10 ` | :ref:`0xf000690c ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_10 ` | :ref:`0xf0006910 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_11 ` | :ref:`0xf0006914 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_11 ` | :ref:`0xf0006918 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_12 ` | :ref:`0xf000691c ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_12 ` | :ref:`0xf0006920 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_13 ` | :ref:`0xf0006924 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_13 ` | :ref:`0xf0006928 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_14 ` | :ref:`0xf000692c ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_14 ` | :ref:`0xf0006930 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_15 ` | :ref:`0xf0006934 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_15 ` | :ref:`0xf0006938 ` | ++----------------------------------------------------------------------------------+---------------------------------------------------------+ + +SDRAM_DFII_CONTROL +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x0 = 0xf0006800` + + Control DFI signals common to all phases + + .. wavedrom:: + :caption: SDRAM_DFII_CONTROL + + { + "reg": [ + {"name": "sel", "attr": '1', "bits": 1}, + {"name": "cke", "bits": 1}, + {"name": "odt", "bits": 1}, + {"name": "reset_n", "bits": 1}, + {"bits": 28} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+---------+-------------------------------------------+ +| Field | Name | Description | ++=======+=========+===========================================+ +| [0] | SEL | | +| | | | +| | | +---------+-----------------------------+ | +| | | | Value | Description | | +| | | +=========+=============================+ | +| | | | ``0b0`` | Software (CPU) control. | | +| | | +---------+-----------------------------+ | +| | | | ``0b1`` | Hardware control (default). | | +| | | +---------+-----------------------------+ | ++-------+---------+-------------------------------------------+ +| [1] | CKE | DFI clock enable bus | ++-------+---------+-------------------------------------------+ +| [2] | ODT | DFI on-die termination bus | ++-------+---------+-------------------------------------------+ +| [3] | RESET_N | DFI clock reset bus | ++-------+---------+-------------------------------------------+ + +SDRAM_DFII_PI0_COMMAND +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x4 = 0xf0006804` + + Control DFI signals on a single phase + + .. wavedrom:: + :caption: SDRAM_DFII_PI0_COMMAND + + { + "reg": [ + {"name": "cs", "bits": 1}, + {"name": "we", "bits": 1}, + {"name": "cas", "bits": 1}, + {"name": "ras", "bits": 1}, + {"name": "wren", "bits": 1}, + {"name": "rden", "bits": 1}, + {"bits": 26} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------------------------+ +| Field | Name | Description | ++=======+======+===============================+ +| [0] | CS | DFI chip select bus | ++-------+------+-------------------------------+ +| [1] | WE | DFI write enable bus | ++-------+------+-------------------------------+ +| [2] | CAS | DFI column address strobe bus | ++-------+------+-------------------------------+ +| [3] | RAS | DFI row address strobe bus | ++-------+------+-------------------------------+ +| [4] | WREN | DFI write data enable bus | ++-------+------+-------------------------------+ +| [5] | RDEN | DFI read data enable bus | ++-------+------+-------------------------------+ + +SDRAM_DFII_PI0_COMMAND_ISSUE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x8 = 0xf0006808` + + + .. wavedrom:: + :caption: SDRAM_DFII_PI0_COMMAND_ISSUE + + { + "reg": [ + {"name": "dfii_pi0_command_issue", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_PI0_ADDRESS +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xc = 0xf000680c` + + DFI address bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI0_ADDRESS + + { + "reg": [ + {"name": "dfii_pi0_address[16:0]", "bits": 17}, + {"bits": 15}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI0_BADDRESS +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x10 = 0xf0006810` + + DFI bank address bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI0_BADDRESS + + { + "reg": [ + {"name": "dfii_pi0_baddress[3:0]", "bits": 4}, + {"bits": 28}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_PI0_WRDATA1 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x14 = 0xf0006814` + + Bits 32-63 of `SDRAM_DFII_PI0_WRDATA`. DFI write data bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI0_WRDATA1 + + { + "reg": [ + {"name": "dfii_pi0_wrdata[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI0_WRDATA0 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x18 = 0xf0006818` + + Bits 0-31 of `SDRAM_DFII_PI0_WRDATA`. + + .. wavedrom:: + :caption: SDRAM_DFII_PI0_WRDATA0 + + { + "reg": [ + {"name": "dfii_pi0_wrdata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI0_RDDATA1 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x1c = 0xf000681c` + + Bits 32-63 of `SDRAM_DFII_PI0_RDDATA`. DFI read data bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI0_RDDATA1 + + { + "reg": [ + {"name": "dfii_pi0_rddata[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI0_RDDATA0 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x20 = 0xf0006820` + + Bits 0-31 of `SDRAM_DFII_PI0_RDDATA`. + + .. wavedrom:: + :caption: SDRAM_DFII_PI0_RDDATA0 + + { + "reg": [ + {"name": "dfii_pi0_rddata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI1_COMMAND +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x24 = 0xf0006824` + + Control DFI signals on a single phase + + .. wavedrom:: + :caption: SDRAM_DFII_PI1_COMMAND + + { + "reg": [ + {"name": "cs", "bits": 1}, + {"name": "we", "bits": 1}, + {"name": "cas", "bits": 1}, + {"name": "ras", "bits": 1}, + {"name": "wren", "bits": 1}, + {"name": "rden", "bits": 1}, + {"bits": 26} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------------------------+ +| Field | Name | Description | ++=======+======+===============================+ +| [0] | CS | DFI chip select bus | ++-------+------+-------------------------------+ +| [1] | WE | DFI write enable bus | ++-------+------+-------------------------------+ +| [2] | CAS | DFI column address strobe bus | ++-------+------+-------------------------------+ +| [3] | RAS | DFI row address strobe bus | ++-------+------+-------------------------------+ +| [4] | WREN | DFI write data enable bus | ++-------+------+-------------------------------+ +| [5] | RDEN | DFI read data enable bus | ++-------+------+-------------------------------+ + +SDRAM_DFII_PI1_COMMAND_ISSUE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x28 = 0xf0006828` + + + .. wavedrom:: + :caption: SDRAM_DFII_PI1_COMMAND_ISSUE + + { + "reg": [ + {"name": "dfii_pi1_command_issue", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_PI1_ADDRESS +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x2c = 0xf000682c` + + DFI address bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI1_ADDRESS + + { + "reg": [ + {"name": "dfii_pi1_address[16:0]", "bits": 17}, + {"bits": 15}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI1_BADDRESS +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x30 = 0xf0006830` + + DFI bank address bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI1_BADDRESS + + { + "reg": [ + {"name": "dfii_pi1_baddress[3:0]", "bits": 4}, + {"bits": 28}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_PI1_WRDATA1 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x34 = 0xf0006834` + + Bits 32-63 of `SDRAM_DFII_PI1_WRDATA`. DFI write data bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI1_WRDATA1 + + { + "reg": [ + {"name": "dfii_pi1_wrdata[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI1_WRDATA0 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x38 = 0xf0006838` + + Bits 0-31 of `SDRAM_DFII_PI1_WRDATA`. + + .. wavedrom:: + :caption: SDRAM_DFII_PI1_WRDATA0 + + { + "reg": [ + {"name": "dfii_pi1_wrdata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI1_RDDATA1 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x3c = 0xf000683c` + + Bits 32-63 of `SDRAM_DFII_PI1_RDDATA`. DFI read data bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI1_RDDATA1 + + { + "reg": [ + {"name": "dfii_pi1_rddata[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI1_RDDATA0 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x40 = 0xf0006840` + + Bits 0-31 of `SDRAM_DFII_PI1_RDDATA`. + + .. wavedrom:: + :caption: SDRAM_DFII_PI1_RDDATA0 + + { + "reg": [ + {"name": "dfii_pi1_rddata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI2_COMMAND +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x44 = 0xf0006844` + + Control DFI signals on a single phase + + .. wavedrom:: + :caption: SDRAM_DFII_PI2_COMMAND + + { + "reg": [ + {"name": "cs", "bits": 1}, + {"name": "we", "bits": 1}, + {"name": "cas", "bits": 1}, + {"name": "ras", "bits": 1}, + {"name": "wren", "bits": 1}, + {"name": "rden", "bits": 1}, + {"bits": 26} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------------------------+ +| Field | Name | Description | ++=======+======+===============================+ +| [0] | CS | DFI chip select bus | ++-------+------+-------------------------------+ +| [1] | WE | DFI write enable bus | ++-------+------+-------------------------------+ +| [2] | CAS | DFI column address strobe bus | ++-------+------+-------------------------------+ +| [3] | RAS | DFI row address strobe bus | ++-------+------+-------------------------------+ +| [4] | WREN | DFI write data enable bus | ++-------+------+-------------------------------+ +| [5] | RDEN | DFI read data enable bus | ++-------+------+-------------------------------+ + +SDRAM_DFII_PI2_COMMAND_ISSUE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x48 = 0xf0006848` + + + .. wavedrom:: + :caption: SDRAM_DFII_PI2_COMMAND_ISSUE + + { + "reg": [ + {"name": "dfii_pi2_command_issue", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_PI2_ADDRESS +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x4c = 0xf000684c` + + DFI address bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI2_ADDRESS + + { + "reg": [ + {"name": "dfii_pi2_address[16:0]", "bits": 17}, + {"bits": 15}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI2_BADDRESS +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x50 = 0xf0006850` + + DFI bank address bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI2_BADDRESS + + { + "reg": [ + {"name": "dfii_pi2_baddress[3:0]", "bits": 4}, + {"bits": 28}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_PI2_WRDATA1 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x54 = 0xf0006854` + + Bits 32-63 of `SDRAM_DFII_PI2_WRDATA`. DFI write data bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI2_WRDATA1 + + { + "reg": [ + {"name": "dfii_pi2_wrdata[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI2_WRDATA0 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x58 = 0xf0006858` + + Bits 0-31 of `SDRAM_DFII_PI2_WRDATA`. + + .. wavedrom:: + :caption: SDRAM_DFII_PI2_WRDATA0 + + { + "reg": [ + {"name": "dfii_pi2_wrdata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI2_RDDATA1 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x5c = 0xf000685c` + + Bits 32-63 of `SDRAM_DFII_PI2_RDDATA`. DFI read data bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI2_RDDATA1 + + { + "reg": [ + {"name": "dfii_pi2_rddata[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI2_RDDATA0 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x60 = 0xf0006860` + + Bits 0-31 of `SDRAM_DFII_PI2_RDDATA`. + + .. wavedrom:: + :caption: SDRAM_DFII_PI2_RDDATA0 + + { + "reg": [ + {"name": "dfii_pi2_rddata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI3_COMMAND +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x64 = 0xf0006864` + + Control DFI signals on a single phase + + .. wavedrom:: + :caption: SDRAM_DFII_PI3_COMMAND + + { + "reg": [ + {"name": "cs", "bits": 1}, + {"name": "we", "bits": 1}, + {"name": "cas", "bits": 1}, + {"name": "ras", "bits": 1}, + {"name": "wren", "bits": 1}, + {"name": "rden", "bits": 1}, + {"bits": 26} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------------------------+ +| Field | Name | Description | ++=======+======+===============================+ +| [0] | CS | DFI chip select bus | ++-------+------+-------------------------------+ +| [1] | WE | DFI write enable bus | ++-------+------+-------------------------------+ +| [2] | CAS | DFI column address strobe bus | ++-------+------+-------------------------------+ +| [3] | RAS | DFI row address strobe bus | ++-------+------+-------------------------------+ +| [4] | WREN | DFI write data enable bus | ++-------+------+-------------------------------+ +| [5] | RDEN | DFI read data enable bus | ++-------+------+-------------------------------+ + +SDRAM_DFII_PI3_COMMAND_ISSUE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x68 = 0xf0006868` + + + .. wavedrom:: + :caption: SDRAM_DFII_PI3_COMMAND_ISSUE + + { + "reg": [ + {"name": "dfii_pi3_command_issue", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_PI3_ADDRESS +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x6c = 0xf000686c` + + DFI address bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI3_ADDRESS + + { + "reg": [ + {"name": "dfii_pi3_address[16:0]", "bits": 17}, + {"bits": 15}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI3_BADDRESS +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x70 = 0xf0006870` + + DFI bank address bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI3_BADDRESS + + { + "reg": [ + {"name": "dfii_pi3_baddress[3:0]", "bits": 4}, + {"bits": 28}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_PI3_WRDATA1 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x74 = 0xf0006874` + + Bits 32-63 of `SDRAM_DFII_PI3_WRDATA`. DFI write data bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI3_WRDATA1 + + { + "reg": [ + {"name": "dfii_pi3_wrdata[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI3_WRDATA0 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x78 = 0xf0006878` + + Bits 0-31 of `SDRAM_DFII_PI3_WRDATA`. + + .. wavedrom:: + :caption: SDRAM_DFII_PI3_WRDATA0 + + { + "reg": [ + {"name": "dfii_pi3_wrdata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI3_RDDATA1 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x7c = 0xf000687c` + + Bits 32-63 of `SDRAM_DFII_PI3_RDDATA`. DFI read data bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI3_RDDATA1 + + { + "reg": [ + {"name": "dfii_pi3_rddata[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI3_RDDATA0 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x80 = 0xf0006880` + + Bits 0-31 of `SDRAM_DFII_PI3_RDDATA`. + + .. wavedrom:: + :caption: SDRAM_DFII_PI3_RDDATA0 + + { + "reg": [ + {"name": "dfii_pi3_rddata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_TRP +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x84 = 0xf0006884` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRP + + { + "reg": [ + {"name": "controller_trp[1:0]", "attr": 'reset: 3', "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TRCD +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x88 = 0xf0006888` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRCD + + { + "reg": [ + {"name": "controller_trcd[1:0]", "attr": 'reset: 3', "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TWR +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x8c = 0xf000688c` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TWR + + { + "reg": [ + {"name": "controller_twr[1:0]", "attr": 'reset: 3', "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TWTR +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x90 = 0xf0006890` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TWTR + + { + "reg": [ + {"name": "controller_twtr[1:0]", "attr": 'reset: 2', "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TREFI +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x94 = 0xf0006894` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TREFI + + { + "reg": [ + {"name": "controller_trefi[9:0]", "attr": 'reset: 782', "bits": 10}, + {"bits": 22}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_TRFC +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x98 = 0xf0006898` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRFC + + { + "reg": [ + {"name": "controller_trfc[5:0]", "attr": 'reset: 36', "bits": 6}, + {"bits": 26}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TFAW +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x9c = 0xf000689c` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TFAW + + { + "reg": [ + {"name": "controller_tfaw[2:0]", "attr": 'reset: 5', "bits": 3}, + {"bits": 29}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TCCD +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xa0 = 0xf00068a0` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TCCD + + { + "reg": [ + {"name": "controller_tccd[1:0]", "attr": 'reset: 1', "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TCCD_WR +^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xa4 = 0xf00068a4` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TCCD_WR + + { + "reg": [ + {"name": "controller_tccd_wr", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TRTP +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xa8 = 0xf00068a8` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRTP + + { + "reg": [ + {"name": "controller_trtp", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TRRD +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xac = 0xf00068ac` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRRD + + { + "reg": [ + {"name": "controller_trrd[1:0]", "attr": 'reset: 2', "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TRC +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xb0 = 0xf00068b0` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRC + + { + "reg": [ + {"name": "controller_trc[2:0]", "attr": 'reset: 6', "bits": 3}, + {"bits": 29}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TRAS +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xb4 = 0xf00068b4` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRAS + + { + "reg": [ + {"name": "controller_tras[2:0]", "attr": 'reset: 4', "bits": 3}, + {"bits": 29}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TZQCS +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xb8 = 0xf00068b8` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TZQCS + + { + "reg": [ + {"name": "controller_tzqcs[7:0]", "attr": 'reset: 32', "bits": 8}, + {"bits": 24}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_0 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xbc = 0xf00068bc` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_0 + + { + "reg": [ + {"name": "controller_last_addr_0[23:0]", "bits": 24}, + {"bits": 8}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_0 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xc0 = 0xf00068c0` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_0 + + { + "reg": [ + {"name": "controller_last_active_row_0[16:0]", "bits": 17}, + {"bits": 15}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_1 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xc4 = 0xf00068c4` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_1 + + { + "reg": [ + {"name": "controller_last_addr_1[23:0]", "bits": 24}, + {"bits": 8}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_1 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xc8 = 0xf00068c8` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_1 + + { + "reg": [ + {"name": "controller_last_active_row_1[16:0]", "bits": 17}, + {"bits": 15}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_2 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xcc = 0xf00068cc` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_2 + + { + "reg": [ + {"name": "controller_last_addr_2[23:0]", "bits": 24}, + {"bits": 8}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_2 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xd0 = 0xf00068d0` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_2 + + { + "reg": [ + {"name": "controller_last_active_row_2[16:0]", "bits": 17}, + {"bits": 15}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_3 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xd4 = 0xf00068d4` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_3 + + { + "reg": [ + {"name": "controller_last_addr_3[23:0]", "bits": 24}, + {"bits": 8}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_3 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xd8 = 0xf00068d8` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_3 + + { + "reg": [ + {"name": "controller_last_active_row_3[16:0]", "bits": 17}, + {"bits": 15}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_4 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xdc = 0xf00068dc` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_4 + + { + "reg": [ + {"name": "controller_last_addr_4[23:0]", "bits": 24}, + {"bits": 8}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_4 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xe0 = 0xf00068e0` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_4 + + { + "reg": [ + {"name": "controller_last_active_row_4[16:0]", "bits": 17}, + {"bits": 15}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_5 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xe4 = 0xf00068e4` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_5 + + { + "reg": [ + {"name": "controller_last_addr_5[23:0]", "bits": 24}, + {"bits": 8}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_5 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xe8 = 0xf00068e8` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_5 + + { + "reg": [ + {"name": "controller_last_active_row_5[16:0]", "bits": 17}, + {"bits": 15}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_6 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xec = 0xf00068ec` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_6 + + { + "reg": [ + {"name": "controller_last_addr_6[23:0]", "bits": 24}, + {"bits": 8}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_6 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xf0 = 0xf00068f0` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_6 + + { + "reg": [ + {"name": "controller_last_active_row_6[16:0]", "bits": 17}, + {"bits": 15}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_7 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xf4 = 0xf00068f4` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_7 + + { + "reg": [ + {"name": "controller_last_addr_7[23:0]", "bits": 24}, + {"bits": 8}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_7 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xf8 = 0xf00068f8` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_7 + + { + "reg": [ + {"name": "controller_last_active_row_7[16:0]", "bits": 17}, + {"bits": 15}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_8 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xfc = 0xf00068fc` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_8 + + { + "reg": [ + {"name": "controller_last_addr_8[23:0]", "bits": 24}, + {"bits": 8}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_8 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x100 = 0xf0006900` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_8 + + { + "reg": [ + {"name": "controller_last_active_row_8[16:0]", "bits": 17}, + {"bits": 15}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_9 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x104 = 0xf0006904` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_9 + + { + "reg": [ + {"name": "controller_last_addr_9[23:0]", "bits": 24}, + {"bits": 8}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_9 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x108 = 0xf0006908` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_9 + + { + "reg": [ + {"name": "controller_last_active_row_9[16:0]", "bits": 17}, + {"bits": 15}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_10 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x10c = 0xf000690c` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_10 + + { + "reg": [ + {"name": "controller_last_addr_10[23:0]", "bits": 24}, + {"bits": 8}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_10 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x110 = 0xf0006910` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_10 + + { + "reg": [ + {"name": "controller_last_active_row_10[16:0]", "bits": 17}, + {"bits": 15}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_11 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x114 = 0xf0006914` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_11 + + { + "reg": [ + {"name": "controller_last_addr_11[23:0]", "bits": 24}, + {"bits": 8}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_11 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x118 = 0xf0006918` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_11 + + { + "reg": [ + {"name": "controller_last_active_row_11[16:0]", "bits": 17}, + {"bits": 15}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_12 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x11c = 0xf000691c` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_12 + + { + "reg": [ + {"name": "controller_last_addr_12[23:0]", "bits": 24}, + {"bits": 8}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_12 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x120 = 0xf0006920` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_12 + + { + "reg": [ + {"name": "controller_last_active_row_12[16:0]", "bits": 17}, + {"bits": 15}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_13 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x124 = 0xf0006924` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_13 + + { + "reg": [ + {"name": "controller_last_addr_13[23:0]", "bits": 24}, + {"bits": 8}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_13 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x128 = 0xf0006928` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_13 + + { + "reg": [ + {"name": "controller_last_active_row_13[16:0]", "bits": 17}, + {"bits": 15}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_14 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x12c = 0xf000692c` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_14 + + { + "reg": [ + {"name": "controller_last_addr_14[23:0]", "bits": 24}, + {"bits": 8}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_14 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x130 = 0xf0006930` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_14 + + { + "reg": [ + {"name": "controller_last_active_row_14[16:0]", "bits": 17}, + {"bits": 15}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_15 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x134 = 0xf0006934` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_15 + + { + "reg": [ + {"name": "controller_last_addr_15[23:0]", "bits": 24}, + {"bits": 8}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_15 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x138 = 0xf0006938` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_15 + + { + "reg": [ + {"name": "controller_last_active_row_15[16:0]", "bits": 17}, + {"bits": 15}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/ddr4_datacenter_test_board/documentation/sdram_checker.rst.txt b/_sources/build/ddr4_datacenter_test_board/documentation/sdram_checker.rst.txt new file mode 100644 index 000000000..a19021433 --- /dev/null +++ b/_sources/build/ddr4_datacenter_test_board/documentation/sdram_checker.rst.txt @@ -0,0 +1,243 @@ +SDRAM_CHECKER +============= + +Register Listing for SDRAM_CHECKER +---------------------------------- + ++------------------------------------------------------+-------------------------------------------+ +| Register | Address | ++======================================================+===========================================+ +| :ref:`SDRAM_CHECKER_RESET ` | :ref:`0xf0007000 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`SDRAM_CHECKER_START ` | :ref:`0xf0007004 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`SDRAM_CHECKER_DONE ` | :ref:`0xf0007008 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`SDRAM_CHECKER_BASE1 ` | :ref:`0xf000700c ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`SDRAM_CHECKER_BASE0 ` | :ref:`0xf0007010 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`SDRAM_CHECKER_END1 ` | :ref:`0xf0007014 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`SDRAM_CHECKER_END0 ` | :ref:`0xf0007018 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`SDRAM_CHECKER_LENGTH1 ` | :ref:`0xf000701c ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`SDRAM_CHECKER_LENGTH0 ` | :ref:`0xf0007020 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`SDRAM_CHECKER_RANDOM ` | :ref:`0xf0007024 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`SDRAM_CHECKER_TICKS ` | :ref:`0xf0007028 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`SDRAM_CHECKER_ERRORS ` | :ref:`0xf000702c ` | ++------------------------------------------------------+-------------------------------------------+ + +SDRAM_CHECKER_RESET +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x0 = 0xf0007000` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_RESET + + { + "reg": [ + {"name": "reset", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CHECKER_START +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x4 = 0xf0007004` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_START + + { + "reg": [ + {"name": "start", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CHECKER_DONE +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x8 = 0xf0007008` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_DONE + + { + "reg": [ + {"name": "done", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CHECKER_BASE1 +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0xc = 0xf000700c` + + Bits 32-32 of `SDRAM_CHECKER_BASE`. + + .. wavedrom:: + :caption: SDRAM_CHECKER_BASE1 + + { + "reg": [ + {"name": "base[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CHECKER_BASE0 +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x10 = 0xf0007010` + + Bits 0-31 of `SDRAM_CHECKER_BASE`. + + .. wavedrom:: + :caption: SDRAM_CHECKER_BASE0 + + { + "reg": [ + {"name": "base[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CHECKER_END1 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x14 = 0xf0007014` + + Bits 32-32 of `SDRAM_CHECKER_END`. + + .. wavedrom:: + :caption: SDRAM_CHECKER_END1 + + { + "reg": [ + {"name": "end[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CHECKER_END0 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x18 = 0xf0007018` + + Bits 0-31 of `SDRAM_CHECKER_END`. + + .. wavedrom:: + :caption: SDRAM_CHECKER_END0 + + { + "reg": [ + {"name": "end[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CHECKER_LENGTH1 +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x1c = 0xf000701c` + + Bits 32-32 of `SDRAM_CHECKER_LENGTH`. + + .. wavedrom:: + :caption: SDRAM_CHECKER_LENGTH1 + + { + "reg": [ + {"name": "length[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CHECKER_LENGTH0 +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x20 = 0xf0007020` + + Bits 0-31 of `SDRAM_CHECKER_LENGTH`. + + .. wavedrom:: + :caption: SDRAM_CHECKER_LENGTH0 + + { + "reg": [ + {"name": "length[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CHECKER_RANDOM +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x24 = 0xf0007024` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_RANDOM + + { + "reg": [ + {"name": "data", "bits": 1}, + {"name": "addr", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------+ +| Field | Name | Description | ++=======+======+=============+ ++-------+------+-------------+ ++-------+------+-------------+ + +SDRAM_CHECKER_TICKS +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x28 = 0xf0007028` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_TICKS + + { + "reg": [ + {"name": "ticks[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CHECKER_ERRORS +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x2c = 0xf000702c` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_ERRORS + + { + "reg": [ + {"name": "errors[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/ddr4_datacenter_test_board/documentation/sdram_generator.rst.txt b/_sources/build/ddr4_datacenter_test_board/documentation/sdram_generator.rst.txt new file mode 100644 index 000000000..74b435d79 --- /dev/null +++ b/_sources/build/ddr4_datacenter_test_board/documentation/sdram_generator.rst.txt @@ -0,0 +1,225 @@ +SDRAM_GENERATOR +=============== + +Register Listing for SDRAM_GENERATOR +------------------------------------ + ++----------------------------------------------------------+---------------------------------------------+ +| Register | Address | ++==========================================================+=============================================+ +| :ref:`SDRAM_GENERATOR_RESET ` | :ref:`0xf0007800 ` | ++----------------------------------------------------------+---------------------------------------------+ +| :ref:`SDRAM_GENERATOR_START ` | :ref:`0xf0007804 ` | ++----------------------------------------------------------+---------------------------------------------+ +| :ref:`SDRAM_GENERATOR_DONE ` | :ref:`0xf0007808 ` | ++----------------------------------------------------------+---------------------------------------------+ +| :ref:`SDRAM_GENERATOR_BASE1 ` | :ref:`0xf000780c ` | ++----------------------------------------------------------+---------------------------------------------+ +| :ref:`SDRAM_GENERATOR_BASE0 ` | :ref:`0xf0007810 ` | ++----------------------------------------------------------+---------------------------------------------+ +| :ref:`SDRAM_GENERATOR_END1 ` | :ref:`0xf0007814 ` | ++----------------------------------------------------------+---------------------------------------------+ +| :ref:`SDRAM_GENERATOR_END0 ` | :ref:`0xf0007818 ` | ++----------------------------------------------------------+---------------------------------------------+ +| :ref:`SDRAM_GENERATOR_LENGTH1 ` | :ref:`0xf000781c ` | ++----------------------------------------------------------+---------------------------------------------+ +| :ref:`SDRAM_GENERATOR_LENGTH0 ` | :ref:`0xf0007820 ` | ++----------------------------------------------------------+---------------------------------------------+ +| :ref:`SDRAM_GENERATOR_RANDOM ` | :ref:`0xf0007824 ` | ++----------------------------------------------------------+---------------------------------------------+ +| :ref:`SDRAM_GENERATOR_TICKS ` | :ref:`0xf0007828 ` | ++----------------------------------------------------------+---------------------------------------------+ + +SDRAM_GENERATOR_RESET +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x0 = 0xf0007800` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_RESET + + { + "reg": [ + {"name": "reset", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_GENERATOR_START +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x4 = 0xf0007804` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_START + + { + "reg": [ + {"name": "start", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_GENERATOR_DONE +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x8 = 0xf0007808` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_DONE + + { + "reg": [ + {"name": "done", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_GENERATOR_BASE1 +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0xc = 0xf000780c` + + Bits 32-32 of `SDRAM_GENERATOR_BASE`. + + .. wavedrom:: + :caption: SDRAM_GENERATOR_BASE1 + + { + "reg": [ + {"name": "base[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_GENERATOR_BASE0 +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x10 = 0xf0007810` + + Bits 0-31 of `SDRAM_GENERATOR_BASE`. + + .. wavedrom:: + :caption: SDRAM_GENERATOR_BASE0 + + { + "reg": [ + {"name": "base[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_GENERATOR_END1 +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x14 = 0xf0007814` + + Bits 32-32 of `SDRAM_GENERATOR_END`. + + .. wavedrom:: + :caption: SDRAM_GENERATOR_END1 + + { + "reg": [ + {"name": "end[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_GENERATOR_END0 +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x18 = 0xf0007818` + + Bits 0-31 of `SDRAM_GENERATOR_END`. + + .. wavedrom:: + :caption: SDRAM_GENERATOR_END0 + + { + "reg": [ + {"name": "end[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_GENERATOR_LENGTH1 +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x1c = 0xf000781c` + + Bits 32-32 of `SDRAM_GENERATOR_LENGTH`. + + .. wavedrom:: + :caption: SDRAM_GENERATOR_LENGTH1 + + { + "reg": [ + {"name": "length[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_GENERATOR_LENGTH0 +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x20 = 0xf0007820` + + Bits 0-31 of `SDRAM_GENERATOR_LENGTH`. + + .. wavedrom:: + :caption: SDRAM_GENERATOR_LENGTH0 + + { + "reg": [ + {"name": "length[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_GENERATOR_RANDOM +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x24 = 0xf0007824` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_RANDOM + + { + "reg": [ + {"name": "data", "bits": 1}, + {"name": "addr", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------+ +| Field | Name | Description | ++=======+======+=============+ ++-------+------+-------------+ ++-------+------+-------------+ + +SDRAM_GENERATOR_TICKS +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x28 = 0xf0007828` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_TICKS + + { + "reg": [ + {"name": "ticks[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/ddr4_datacenter_test_board/documentation/timer0.rst.txt b/_sources/build/ddr4_datacenter_test_board/documentation/timer0.rst.txt new file mode 100644 index 000000000..65b92303b --- /dev/null +++ b/_sources/build/ddr4_datacenter_test_board/documentation/timer0.rst.txt @@ -0,0 +1,228 @@ +TIMER0 +====== + +Timer +----- + +Provides a generic Timer core. + +The Timer is implemented as a countdown timer that can be used in various modes: + +- Polling : Returns current countdown value to software +- One-Shot: Loads itself and stops when value reaches ``0`` +- Periodic: (Re-)Loads itself when value reaches ``0`` + +``en`` register allows the user to enable/disable the Timer. When the Timer is enabled, it is +automatically loaded with the value of `load` register. + +When the Timer reaches ``0``, it is automatically reloaded with value of `reload` register. + +The user can latch the current countdown value by writing to ``update_value`` register, it will +update ``value`` register with current countdown value. + +To use the Timer in One-Shot mode, the user needs to: + +- Disable the timer +- Set the ``load`` register to the expected duration +- (Re-)Enable the Timer + +To use the Timer in Periodic mode, the user needs to: + +- Disable the Timer +- Set the ``load`` register to 0 +- Set the ``reload`` register to the expected period +- Enable the Timer + +For both modes, the CPU can be advertised by an IRQ that the duration/period has elapsed. (The +CPU can also do software polling with ``update_value`` and ``value`` to know the elapsed duration) + + +Register Listing for TIMER0 +--------------------------- + ++--------------------------------------------------+-----------------------------------------+ +| Register | Address | ++==================================================+=========================================+ +| :ref:`TIMER0_LOAD ` | :ref:`0xf0008000 ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_RELOAD ` | :ref:`0xf0008004 ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_EN ` | :ref:`0xf0008008 ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_UPDATE_VALUE ` | :ref:`0xf000800c ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_VALUE ` | :ref:`0xf0008010 ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_EV_STATUS ` | :ref:`0xf0008014 ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_EV_PENDING ` | :ref:`0xf0008018 ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_EV_ENABLE ` | :ref:`0xf000801c ` | ++--------------------------------------------------+-----------------------------------------+ + +TIMER0_LOAD +^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x0 = 0xf0008000` + + Load value when Timer is (re-)enabled. In One-Shot mode, the value written to + this register specifies the Timer's duration in clock cycles. + + .. wavedrom:: + :caption: TIMER0_LOAD + + { + "reg": [ + {"name": "load[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +TIMER0_RELOAD +^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x4 = 0xf0008004` + + Reload value when Timer reaches ``0``. In Periodic mode, the value written to + this register specify the Timer's period in clock cycles. + + .. wavedrom:: + :caption: TIMER0_RELOAD + + { + "reg": [ + {"name": "reload[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +TIMER0_EN +^^^^^^^^^ + +`Address: 0xf0008000 + 0x8 = 0xf0008008` + + Enable flag of the Timer. Set this flag to ``1`` to enable/start the Timer. Set + to ``0`` to disable the Timer. + + .. wavedrom:: + :caption: TIMER0_EN + + { + "reg": [ + {"name": "en", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +TIMER0_UPDATE_VALUE +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0xc = 0xf000800c` + + Update trigger for the current countdown value. A write to this register latches + the current countdown value to ``value`` register. + + .. wavedrom:: + :caption: TIMER0_UPDATE_VALUE + + { + "reg": [ + {"name": "update_value", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +TIMER0_VALUE +^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x10 = 0xf0008010` + + Latched countdown value. This value is updated by writing to ``update_value``. + + .. wavedrom:: + :caption: TIMER0_VALUE + + { + "reg": [ + {"name": "value[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +TIMER0_EV_STATUS +^^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x14 = 0xf0008014` + + This register contains the current raw level of the zero event trigger. Writes + to this register have no effect. + + .. wavedrom:: + :caption: TIMER0_EV_STATUS + + { + "reg": [ + {"name": "zero", "bits": 1}, + {"bits": 31} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-----------------------------+ +| Field | Name | Description | ++=======+======+=============================+ +| [0] | ZERO | Level of the ``zero`` event | ++-------+------+-----------------------------+ + +TIMER0_EV_PENDING +^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x18 = 0xf0008018` + + When a zero event occurs, the corresponding bit will be set in this register. + To clear the Event, set the corresponding bit in this register. + + .. wavedrom:: + :caption: TIMER0_EV_PENDING + + { + "reg": [ + {"name": "zero", "bits": 1}, + {"bits": 31} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+--------------------------------------------------------------------------------+ +| Field | Name | Description | ++=======+======+================================================================================+ +| [0] | ZERO | `1` if a `zero` event occurred. This Event is triggered on a **falling** edge. | ++-------+------+--------------------------------------------------------------------------------+ + +TIMER0_EV_ENABLE +^^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x1c = 0xf000801c` + + This register enables the corresponding zero events. Write a ``0`` to this + register to disable individual events. + + .. wavedrom:: + :caption: TIMER0_EV_ENABLE + + { + "reg": [ + {"name": "zero", "bits": 1}, + {"bits": 31} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+--------------------------------------------+ +| Field | Name | Description | ++=======+======+============================================+ +| [0] | ZERO | Write a ``1`` to enable the ``zero`` Event | ++-------+------+--------------------------------------------+ + diff --git a/_sources/build/ddr4_datacenter_test_board/documentation/uart.rst.txt b/_sources/build/ddr4_datacenter_test_board/documentation/uart.rst.txt new file mode 100644 index 000000000..36d4199d6 --- /dev/null +++ b/_sources/build/ddr4_datacenter_test_board/documentation/uart.rst.txt @@ -0,0 +1,388 @@ +UART +==== + +Register Listing for UART +------------------------- + ++------------------------------------------------------+-------------------------------------------+ +| Register | Address | ++======================================================+===========================================+ +| :ref:`UART_RXTX ` | :ref:`0xf0008800 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_TXFULL ` | :ref:`0xf0008804 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_RXEMPTY ` | :ref:`0xf0008808 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_EV_STATUS ` | :ref:`0xf000880c ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_EV_PENDING ` | :ref:`0xf0008810 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_EV_ENABLE ` | :ref:`0xf0008814 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_TXEMPTY ` | :ref:`0xf0008818 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_RXFULL ` | :ref:`0xf000881c ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_RXTX ` | :ref:`0xf0008820 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_TXFULL ` | :ref:`0xf0008824 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_RXEMPTY ` | :ref:`0xf0008828 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_EV_STATUS ` | :ref:`0xf000882c ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_EV_PENDING ` | :ref:`0xf0008830 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_EV_ENABLE ` | :ref:`0xf0008834 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_TXEMPTY ` | :ref:`0xf0008838 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_RXFULL ` | :ref:`0xf000883c ` | ++------------------------------------------------------+-------------------------------------------+ + +UART_RXTX +^^^^^^^^^ + +`Address: 0xf0008800 + 0x0 = 0xf0008800` + + + .. wavedrom:: + :caption: UART_RXTX + + { + "reg": [ + {"name": "rxtx[7:0]", "bits": 8}, + {"bits": 24}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +UART_TXFULL +^^^^^^^^^^^ + +`Address: 0xf0008800 + 0x4 = 0xf0008804` + + TX FIFO Full. + + .. wavedrom:: + :caption: UART_TXFULL + + { + "reg": [ + {"name": "txfull", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_RXEMPTY +^^^^^^^^^^^^ + +`Address: 0xf0008800 + 0x8 = 0xf0008808` + + RX FIFO Empty. + + .. wavedrom:: + :caption: UART_RXEMPTY + + { + "reg": [ + {"name": "rxempty", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_EV_STATUS +^^^^^^^^^^^^^^ + +`Address: 0xf0008800 + 0xc = 0xf000880c` + + This register contains the current raw level of the rx event trigger. Writes to + this register have no effect. + + .. wavedrom:: + :caption: UART_EV_STATUS + + { + "reg": [ + {"name": "tx", "bits": 1}, + {"name": "rx", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+---------------------------+ +| Field | Name | Description | ++=======+======+===========================+ +| [0] | TX | Level of the ``tx`` event | ++-------+------+---------------------------+ +| [1] | RX | Level of the ``rx`` event | ++-------+------+---------------------------+ + +UART_EV_PENDING +^^^^^^^^^^^^^^^ + +`Address: 0xf0008800 + 0x10 = 0xf0008810` + + When a rx event occurs, the corresponding bit will be set in this register. To + clear the Event, set the corresponding bit in this register. + + .. wavedrom:: + :caption: UART_EV_PENDING + + { + "reg": [ + {"name": "tx", "bits": 1}, + {"name": "rx", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+------------------------------------------------------------------------------+ +| Field | Name | Description | ++=======+======+==============================================================================+ +| [0] | TX | `1` if a `tx` event occurred. This Event is triggered on a **falling** edge. | ++-------+------+------------------------------------------------------------------------------+ +| [1] | RX | `1` if a `rx` event occurred. This Event is triggered on a **falling** edge. | ++-------+------+------------------------------------------------------------------------------+ + +UART_EV_ENABLE +^^^^^^^^^^^^^^ + +`Address: 0xf0008800 + 0x14 = 0xf0008814` + + This register enables the corresponding rx events. Write a ``0`` to this + register to disable individual events. + + .. wavedrom:: + :caption: UART_EV_ENABLE + + { + "reg": [ + {"name": "tx", "bits": 1}, + {"name": "rx", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+------------------------------------------+ +| Field | Name | Description | ++=======+======+==========================================+ +| [0] | TX | Write a ``1`` to enable the ``tx`` Event | ++-------+------+------------------------------------------+ +| [1] | RX | Write a ``1`` to enable the ``rx`` Event | ++-------+------+------------------------------------------+ + +UART_TXEMPTY +^^^^^^^^^^^^ + +`Address: 0xf0008800 + 0x18 = 0xf0008818` + + TX FIFO Empty. + + .. wavedrom:: + :caption: UART_TXEMPTY + + { + "reg": [ + {"name": "txempty", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_RXFULL +^^^^^^^^^^^ + +`Address: 0xf0008800 + 0x1c = 0xf000881c` + + RX FIFO Full. + + .. wavedrom:: + :caption: UART_RXFULL + + { + "reg": [ + {"name": "rxfull", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_XOVER_RXTX +^^^^^^^^^^^^^^^ + +`Address: 0xf0008800 + 0x20 = 0xf0008820` + + + .. wavedrom:: + :caption: UART_XOVER_RXTX + + { + "reg": [ + {"name": "xover_rxtx[7:0]", "bits": 8}, + {"bits": 24}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +UART_XOVER_TXFULL +^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008800 + 0x24 = 0xf0008824` + + TX FIFO Full. + + .. wavedrom:: + :caption: UART_XOVER_TXFULL + + { + "reg": [ + {"name": "xover_txfull", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_XOVER_RXEMPTY +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008800 + 0x28 = 0xf0008828` + + RX FIFO Empty. + + .. wavedrom:: + :caption: UART_XOVER_RXEMPTY + + { + "reg": [ + {"name": "xover_rxempty", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_XOVER_EV_STATUS +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008800 + 0x2c = 0xf000882c` + + This register contains the current raw level of the rx event trigger. Writes to + this register have no effect. + + .. wavedrom:: + :caption: UART_XOVER_EV_STATUS + + { + "reg": [ + {"name": "tx", "bits": 1}, + {"name": "rx", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+---------------------------+ +| Field | Name | Description | ++=======+======+===========================+ +| [0] | TX | Level of the ``tx`` event | ++-------+------+---------------------------+ +| [1] | RX | Level of the ``rx`` event | ++-------+------+---------------------------+ + +UART_XOVER_EV_PENDING +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008800 + 0x30 = 0xf0008830` + + When a rx event occurs, the corresponding bit will be set in this register. To + clear the Event, set the corresponding bit in this register. + + .. wavedrom:: + :caption: UART_XOVER_EV_PENDING + + { + "reg": [ + {"name": "tx", "bits": 1}, + {"name": "rx", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+------------------------------------------------------------------------------+ +| Field | Name | Description | ++=======+======+==============================================================================+ +| [0] | TX | `1` if a `tx` event occurred. This Event is triggered on a **falling** edge. | ++-------+------+------------------------------------------------------------------------------+ +| [1] | RX | `1` if a `rx` event occurred. This Event is triggered on a **falling** edge. | ++-------+------+------------------------------------------------------------------------------+ + +UART_XOVER_EV_ENABLE +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008800 + 0x34 = 0xf0008834` + + This register enables the corresponding rx events. Write a ``0`` to this + register to disable individual events. + + .. wavedrom:: + :caption: UART_XOVER_EV_ENABLE + + { + "reg": [ + {"name": "tx", "bits": 1}, + {"name": "rx", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+------------------------------------------+ +| Field | Name | Description | ++=======+======+==========================================+ +| [0] | TX | Write a ``1`` to enable the ``tx`` Event | ++-------+------+------------------------------------------+ +| [1] | RX | Write a ``1`` to enable the ``rx`` Event | ++-------+------+------------------------------------------+ + +UART_XOVER_TXEMPTY +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008800 + 0x38 = 0xf0008838` + + TX FIFO Empty. + + .. wavedrom:: + :caption: UART_XOVER_TXEMPTY + + { + "reg": [ + {"name": "xover_txempty", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_XOVER_RXFULL +^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008800 + 0x3c = 0xf000883c` + + RX FIFO Full. + + .. wavedrom:: + :caption: UART_XOVER_RXFULL + + { + "reg": [ + {"name": "xover_rxfull", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/ddr4_datacenter_test_board/documentation/writer.rst.txt b/_sources/build/ddr4_datacenter_test_board/documentation/writer.rst.txt new file mode 100644 index 000000000..9f637032a --- /dev/null +++ b/_sources/build/ddr4_datacenter_test_board/documentation/writer.rst.txt @@ -0,0 +1,251 @@ +WRITER +====== + + + +DMA DRAM writer. + +Allows to fill DRAM with a predefined pattern using DMA. + +Pattern +------- + + + Provides access to RAM to store access pattern: `mem_addr` and `mem_data`. + The pattern address space can be limited using the `data_mask`. + + For example, having `mem_adr` filled with `[ 0x04, 0x02, 0x03, ... ]` + and `mem_data` filled with `[ 0xff, 0xaa, 0x55, ... ]` and setting + `data_mask = 0b01`, the pattern [(address, data), ...] written will be: + `[(0x04, 0xff), (0x02, 0xaa), (0x04, 0xff), ...]` (wraps due to masking). + + DRAM memory range that is being accessed can be configured using `mem_mask`. + + To use this module, make sure that `ready` is 1, then write the desired + number of transfers to `count`. Writing to the `start` CSR will initialize + the operation. When the operation is ongoing `ready` will be 0. + + + +Register Listing for WRITER +--------------------------- + ++------------------------------------------------------------------------+----------------------------------------------------+ +| Register | Address | ++========================================================================+====================================================+ +| :ref:`WRITER_START ` | :ref:`0xf0002800 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_READY ` | :ref:`0xf0002804 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_MODULO ` | :ref:`0xf0002808 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_COUNT ` | :ref:`0xf000280c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_DONE ` | :ref:`0xf0002810 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_MEM_MASK ` | :ref:`0xf0002814 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_DATA_MASK ` | :ref:`0xf0002818 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_DATA_DIV ` | :ref:`0xf000281c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_INVERTER_DIVISOR_MASK ` | :ref:`0xf0002820 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_INVERTER_SELECTION_MASK ` | :ref:`0xf0002824 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_LAST_ADDRESS ` | :ref:`0xf0002828 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ + +WRITER_START +^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x0 = 0xf0002800` + + Write to the register starts the transfer (if ready=1) + + .. wavedrom:: + :caption: WRITER_START + + { + "reg": [ + {"name": "start", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +WRITER_READY +^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x4 = 0xf0002804` + + Indicates that the transfer is not ongoing + + .. wavedrom:: + :caption: WRITER_READY + + { + "reg": [ + {"name": "ready", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +WRITER_MODULO +^^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x8 = 0xf0002808` + + When set use modulo to calculate DMA transfers address rather than bit masking + + .. wavedrom:: + :caption: WRITER_MODULO + + { + "reg": [ + {"name": "modulo", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +WRITER_COUNT +^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0xc = 0xf000280c` + + Desired number of DMA transfers + + .. wavedrom:: + :caption: WRITER_COUNT + + { + "reg": [ + {"name": "count[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +WRITER_DONE +^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x10 = 0xf0002810` + + Number of completed DMA transfers + + .. wavedrom:: + :caption: WRITER_DONE + + { + "reg": [ + {"name": "done[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +WRITER_MEM_MASK +^^^^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x14 = 0xf0002814` + + DRAM address mask for DMA transfers + + .. wavedrom:: + :caption: WRITER_MEM_MASK + + { + "reg": [ + {"name": "mem_mask[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +WRITER_DATA_MASK +^^^^^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x18 = 0xf0002818` + + Pattern memory address mask + + .. wavedrom:: + :caption: WRITER_DATA_MASK + + { + "reg": [ + {"name": "data_mask[4:0]", "bits": 5}, + {"bits": 27}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +WRITER_DATA_DIV +^^^^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x1c = 0xf000281c` + + Pattern memory address divisior-1 + + .. wavedrom:: + :caption: WRITER_DATA_DIV + + { + "reg": [ + {"name": "data_div[4:0]", "bits": 5}, + {"bits": 27}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +WRITER_INVERTER_DIVISOR_MASK +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x20 = 0xf0002820` + + Divisor mask for selecting rows for which pattern data gets inverted + + .. wavedrom:: + :caption: WRITER_INVERTER_DIVISOR_MASK + + { + "reg": [ + {"name": "inverter_divisor_mask[4:0]", "bits": 5}, + {"bits": 27}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +WRITER_INVERTER_SELECTION_MASK +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x24 = 0xf0002824` + + Selection mask for selecting rows for which pattern data gets inverted + + .. wavedrom:: + :caption: WRITER_INVERTER_SELECTION_MASK + + { + "reg": [ + {"name": "inverter_selection_mask[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +WRITER_LAST_ADDRESS +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x28 = 0xf0002828` + + Number of completed DMA transfers + + .. wavedrom:: + :caption: WRITER_LAST_ADDRESS + + { + "reg": [ + {"name": "last_address[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/ddr5_test_board/documentation/controller_settings.rst.txt b/_sources/build/ddr5_test_board/documentation/controller_settings.rst.txt new file mode 100644 index 000000000..cc67b4b83 --- /dev/null +++ b/_sources/build/ddr5_test_board/documentation/controller_settings.rst.txt @@ -0,0 +1,34 @@ +CONTROLLER_SETTINGS +=================== + +Allows to change LiteDRAMController behaviour at runtime +-------------------------------------------------------- + + +Register Listing for CONTROLLER_SETTINGS +---------------------------------------- + ++------------------------------------------------------------------+-------------------------------------------------+ +| Register | Address | ++==================================================================+=================================================+ +| :ref:`CONTROLLER_SETTINGS_REFRESH ` | :ref:`0xf0001000 ` | ++------------------------------------------------------------------+-------------------------------------------------+ + +CONTROLLER_SETTINGS_REFRESH +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0001000 + 0x0 = 0xf0001000` + + Enable/disable Refresh commands sending + + .. wavedrom:: + :caption: CONTROLLER_SETTINGS_REFRESH + + { + "reg": [ + {"name": "refresh", "attr": 'reset: 1', "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/ddr5_test_board/documentation/ctrl.rst.txt b/_sources/build/ddr5_test_board/documentation/ctrl.rst.txt new file mode 100644 index 000000000..ca08edbd0 --- /dev/null +++ b/_sources/build/ddr5_test_board/documentation/ctrl.rst.txt @@ -0,0 +1,78 @@ +CTRL +==== + +Register Listing for CTRL +------------------------- + ++------------------------------------------+-------------------------------------+ +| Register | Address | ++==========================================+=====================================+ +| :ref:`CTRL__RESET ` | :ref:`0xf0004800 ` | ++------------------------------------------+-------------------------------------+ +| :ref:`CTRL_SCRATCH ` | :ref:`0xf0004804 ` | ++------------------------------------------+-------------------------------------+ +| :ref:`CTRL_BUS_ERRORS ` | :ref:`0xf0004808 ` | ++------------------------------------------+-------------------------------------+ + +CTRL__RESET +^^^^^^^^^^^ + +`Address: 0xf0004800 + 0x0 = 0xf0004800` + + + .. wavedrom:: + :caption: CTRL__RESET + + { + "reg": [ + {"name": "soc_rst", "type": 4, "bits": 1}, + {"name": "cpu_rst", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+---------+------------------------------------------------------------------------+ +| Field | Name | Description | ++=======+=========+========================================================================+ +| [0] | SOC_RST | Write `1` to this register to reset the full SoC (Pulse Reset) | ++-------+---------+------------------------------------------------------------------------+ +| [1] | CPU_RST | Write `1` to this register to reset the CPU(s) of the SoC (Hold Reset) | ++-------+---------+------------------------------------------------------------------------+ + +CTRL_SCRATCH +^^^^^^^^^^^^ + +`Address: 0xf0004800 + 0x4 = 0xf0004804` + + Use this register as a scratch space to verify that software read/write accesses + to the Wishbone/CSR bus are working correctly. The initial reset value of + 0x1234578 can be used to verify endianness. + + .. wavedrom:: + :caption: CTRL_SCRATCH + + { + "reg": [ + {"name": "scratch[31:0]", "attr": 'reset: 305419896', "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +CTRL_BUS_ERRORS +^^^^^^^^^^^^^^^ + +`Address: 0xf0004800 + 0x8 = 0xf0004808` + + Total number of Wishbone bus errors (timeouts) since start. + + .. wavedrom:: + :caption: CTRL_BUS_ERRORS + + { + "reg": [ + {"name": "bus_errors[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/ddr5_test_board/documentation/ddrctrl.rst.txt b/_sources/build/ddr5_test_board/documentation/ddrctrl.rst.txt new file mode 100644 index 000000000..59563d8b1 --- /dev/null +++ b/_sources/build/ddr5_test_board/documentation/ddrctrl.rst.txt @@ -0,0 +1,48 @@ +DDRCTRL +======= + +Register Listing for DDRCTRL +---------------------------- + ++------------------------------------------------+----------------------------------------+ +| Register | Address | ++================================================+========================================+ +| :ref:`DDRCTRL_INIT_DONE ` | :ref:`0xf0001800 ` | ++------------------------------------------------+----------------------------------------+ +| :ref:`DDRCTRL_INIT_ERROR ` | :ref:`0xf0001804 ` | ++------------------------------------------------+----------------------------------------+ + +DDRCTRL_INIT_DONE +^^^^^^^^^^^^^^^^^ + +`Address: 0xf0001800 + 0x0 = 0xf0001800` + + + .. wavedrom:: + :caption: DDRCTRL_INIT_DONE + + { + "reg": [ + {"name": "init_done", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRCTRL_INIT_ERROR +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0001800 + 0x4 = 0xf0001804` + + + .. wavedrom:: + :caption: DDRCTRL_INIT_ERROR + + { + "reg": [ + {"name": "init_error", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/ddr5_test_board/documentation/ddrphy.rst.txt b/_sources/build/ddr5_test_board/documentation/ddrphy.rst.txt new file mode 100644 index 000000000..320a69ef4 --- /dev/null +++ b/_sources/build/ddr5_test_board/documentation/ddrphy.rst.txt @@ -0,0 +1,1007 @@ +DDRPHY +====== + +Register Listing for DDRPHY +--------------------------- + ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| Register | Address | ++================================================================================+========================================================+ +| :ref:`DDRPHY_CSRMODULE_ENABLE_FIFOS ` | :ref:`0xf0000800 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_RST ` | :ref:`0xf0000804 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_RDIMM_MODE ` | :ref:`0xf0000808 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_RDPHASE ` | :ref:`0xf000080c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_WRPHASE ` | :ref:`0xf0000810 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_ALERT ` | :ref:`0xf0000814 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_ALERT_REDUCE ` | :ref:`0xf0000818 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_SAMPLE_ALERT ` | :ref:`0xf000081c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_RESET_ALERT ` | :ref:`0xf0000820 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_CKDLY_RST ` | :ref:`0xf0000824 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_CKDLY_INC ` | :ref:`0xf0000828 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_PREAMBLE ` | :ref:`0xf000082c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_WLEVEL_EN ` | :ref:`0xf0000830 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_PAR_ENABLE ` | :ref:`0xf0000834 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_PAR_VALUE ` | :ref:`0xf0000838 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_DISCARD_RD_FIFO ` | :ref:`0xf000083c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_DLY_SEL ` | :ref:`0xf0000840 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_DQ_DQS_RATIO ` | :ref:`0xf0000844 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_CK_RDLY_INC ` | :ref:`0xf0000848 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_CK_RDLY_RST ` | :ref:`0xf000084c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_CK_RDDLY ` | :ref:`0xf0000850 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_CK_RDDLY_PREAMBLE ` | :ref:`0xf0000854 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_CK_WDLY_INC ` | :ref:`0xf0000858 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_CK_WDLY_RST ` | :ref:`0xf000085c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_CK_WDLY_DQS ` | :ref:`0xf0000860 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_CK_WDDLY_INC ` | :ref:`0xf0000864 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_CK_WDDLY_RST ` | :ref:`0xf0000868 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_CK_WDLY_DQ ` | :ref:`0xf000086c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_DQ_DLY_SEL ` | :ref:`0xf0000870 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_CSDLY_RST ` | :ref:`0xf0000874 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_CSDLY_INC ` | :ref:`0xf0000878 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_CADLY_RST ` | :ref:`0xf000087c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_CADLY_INC ` | :ref:`0xf0000880 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_PARDLY_RST ` | :ref:`0xf0000884 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_PARDLY_INC ` | :ref:`0xf0000888 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_CSDLY ` | :ref:`0xf000088c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_CADLY ` | :ref:`0xf0000890 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_RDLY_DQ_RST ` | :ref:`0xf0000894 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_RDLY_DQ_INC ` | :ref:`0xf0000898 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_RDLY_DQS_RST ` | :ref:`0xf000089c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_RDLY_DQS_INC ` | :ref:`0xf00008a0 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_RDLY_DQS ` | :ref:`0xf00008a4 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_RDLY_DQ ` | :ref:`0xf00008a8 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_WDLY_DQ_RST ` | :ref:`0xf00008ac ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_WDLY_DQ_INC ` | :ref:`0xf00008b0 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_WDLY_DM_RST ` | :ref:`0xf00008b4 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_WDLY_DM_INC ` | :ref:`0xf00008b8 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_WDLY_DQS_RST ` | :ref:`0xf00008bc ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_WDLY_DQS_INC ` | :ref:`0xf00008c0 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_WDLY_DQS ` | :ref:`0xf00008c4 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_WDLY_DQ ` | :ref:`0xf00008c8 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_WDLY_DM ` | :ref:`0xf00008cc ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ + +DDRPHY_CSRMODULE_ENABLE_FIFOS +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x0 = 0xf0000800` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_ENABLE_FIFOS + + { + "reg": [ + {"name": "csrmodule_enable_fifos", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_RST +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x4 = 0xf0000804` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_RST + + { + "reg": [ + {"name": "csrmodule_rst", "attr": 'reset: 1', "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_RDIMM_MODE +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x8 = 0xf0000808` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_RDIMM_MODE + + { + "reg": [ + {"name": "csrmodule_rdimm_mode", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_RDPHASE +^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xc = 0xf000080c` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_RDPHASE + + { + "reg": [ + {"name": "csrmodule_rdphase[1:0]", "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_WRPHASE +^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x10 = 0xf0000810` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_WRPHASE + + { + "reg": [ + {"name": "csrmodule_wrphase[1:0]", "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_ALERT +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x14 = 0xf0000814` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_ALERT + + { + "reg": [ + {"name": "csrmodule_alert", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_ALERT_REDUCE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x18 = 0xf0000818` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_ALERT_REDUCE + + { + "reg": [ + {"name": "initial_state", "bits": 1}, + {"name": "operation", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+---------------+------------------------------+ +| Field | Name | Description | ++=======+===============+==============================+ +| [0] | INITIAL_STATE | Initial value of all bits | ++-------+---------------+------------------------------+ +| [1] | OPERATION | 0 - `or` (default), 1 -`and` | ++-------+---------------+------------------------------+ + +DDRPHY_CSRMODULE_SAMPLE_ALERT +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x1c = 0xf000081c` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_SAMPLE_ALERT + + { + "reg": [ + {"name": "csrmodule_sample_alert", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_RESET_ALERT +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x20 = 0xf0000820` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_RESET_ALERT + + { + "reg": [ + {"name": "csrmodule_reset_alert", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_CKDLY_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x24 = 0xf0000824` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_CKDLY_RST + + { + "reg": [ + {"name": "csrmodule_ckdly_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_CKDLY_INC +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x28 = 0xf0000828` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_CKDLY_INC + + { + "reg": [ + {"name": "csrmodule_ckdly_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_PREAMBLE +^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x2c = 0xf000082c` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_PREAMBLE + + { + "reg": [ + {"name": "csrmodule_preamble[3:0]", "bits": 4}, + {"bits": 28}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_WLEVEL_EN +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x30 = 0xf0000830` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_WLEVEL_EN + + { + "reg": [ + {"name": "csrmodule_wlevel_en", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_PAR_ENABLE +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x34 = 0xf0000834` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_PAR_ENABLE + + { + "reg": [ + {"name": "csrmodule_par_enable", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_PAR_VALUE +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x38 = 0xf0000838` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_PAR_VALUE + + { + "reg": [ + {"name": "csrmodule_par_value", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_DISCARD_RD_FIFO +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x3c = 0xf000083c` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_DISCARD_RD_FIFO + + { + "reg": [ + {"name": "csrmodule_discard_rd_fifo", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_DLY_SEL +^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x40 = 0xf0000840` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_DLY_SEL + + { + "reg": [ + {"name": "csrmodule_dly_sel[13:0]", "bits": 14}, + {"bits": 18}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DDRPHY_CSRMODULE_DQ_DQS_RATIO +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x44 = 0xf0000844` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_DQ_DQS_RATIO + + { + "reg": [ + {"name": "csrmodule_dq_dqs_ratio[3:0]", "attr": 'reset: 8', "bits": 4}, + {"bits": 28}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_CK_RDLY_INC +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x48 = 0xf0000848` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_CK_RDLY_INC + + { + "reg": [ + {"name": "csrmodule_ck_rdly_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_CK_RDLY_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x4c = 0xf000084c` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_CK_RDLY_RST + + { + "reg": [ + {"name": "csrmodule_ck_rdly_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_CK_RDDLY +^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x50 = 0xf0000850` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_CK_RDDLY + + { + "reg": [ + {"name": "csrmodule_ck_rddly[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DDRPHY_CSRMODULE_CK_RDDLY_PREAMBLE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x54 = 0xf0000854` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_CK_RDDLY_PREAMBLE + + { + "reg": [ + {"name": "csrmodule_ck_rddly_preamble[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DDRPHY_CSRMODULE_CK_WDLY_INC +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x58 = 0xf0000858` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_CK_WDLY_INC + + { + "reg": [ + {"name": "csrmodule_ck_wdly_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_CK_WDLY_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x5c = 0xf000085c` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_CK_WDLY_RST + + { + "reg": [ + {"name": "csrmodule_ck_wdly_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_CK_WDLY_DQS +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x60 = 0xf0000860` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_CK_WDLY_DQS + + { + "reg": [ + {"name": "csrmodule_ck_wdly_dqs[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DDRPHY_CSRMODULE_CK_WDDLY_INC +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x64 = 0xf0000864` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_CK_WDDLY_INC + + { + "reg": [ + {"name": "csrmodule_ck_wddly_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_CK_WDDLY_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x68 = 0xf0000868` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_CK_WDDLY_RST + + { + "reg": [ + {"name": "csrmodule_ck_wddly_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_CK_WDLY_DQ +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x6c = 0xf000086c` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_CK_WDLY_DQ + + { + "reg": [ + {"name": "csrmodule_ck_wdly_dq[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DDRPHY_CSRMODULE_DQ_DLY_SEL +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x70 = 0xf0000870` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_DQ_DLY_SEL + + { + "reg": [ + {"name": "csrmodule_dq_dly_sel[7:0]", "bits": 8}, + {"bits": 24}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DDRPHY_CSRMODULE_CSDLY_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x74 = 0xf0000874` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_CSDLY_RST + + { + "reg": [ + {"name": "csrmodule_csdly_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_CSDLY_INC +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x78 = 0xf0000878` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_CSDLY_INC + + { + "reg": [ + {"name": "csrmodule_csdly_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_CADLY_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x7c = 0xf000087c` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_CADLY_RST + + { + "reg": [ + {"name": "csrmodule_cadly_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_CADLY_INC +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x80 = 0xf0000880` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_CADLY_INC + + { + "reg": [ + {"name": "csrmodule_cadly_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_PARDLY_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x84 = 0xf0000884` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_PARDLY_RST + + { + "reg": [ + {"name": "csrmodule_pardly_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_PARDLY_INC +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x88 = 0xf0000888` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_PARDLY_INC + + { + "reg": [ + {"name": "csrmodule_pardly_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_CSDLY +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x8c = 0xf000088c` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_CSDLY + + { + "reg": [ + {"name": "csrmodule_csdly[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DDRPHY_CSRMODULE_CADLY +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x90 = 0xf0000890` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_CADLY + + { + "reg": [ + {"name": "csrmodule_cadly[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DDRPHY_CSRMODULE_RDLY_DQ_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x94 = 0xf0000894` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_RDLY_DQ_RST + + { + "reg": [ + {"name": "csrmodule_rdly_dq_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_RDLY_DQ_INC +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x98 = 0xf0000898` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_RDLY_DQ_INC + + { + "reg": [ + {"name": "csrmodule_rdly_dq_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_RDLY_DQS_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x9c = 0xf000089c` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_RDLY_DQS_RST + + { + "reg": [ + {"name": "csrmodule_rdly_dqs_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_RDLY_DQS_INC +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xa0 = 0xf00008a0` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_RDLY_DQS_INC + + { + "reg": [ + {"name": "csrmodule_rdly_dqs_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_RDLY_DQS +^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xa4 = 0xf00008a4` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_RDLY_DQS + + { + "reg": [ + {"name": "csrmodule_rdly_dqs[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DDRPHY_CSRMODULE_RDLY_DQ +^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xa8 = 0xf00008a8` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_RDLY_DQ + + { + "reg": [ + {"name": "csrmodule_rdly_dq[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DDRPHY_CSRMODULE_WDLY_DQ_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xac = 0xf00008ac` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_WDLY_DQ_RST + + { + "reg": [ + {"name": "csrmodule_wdly_dq_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_WDLY_DQ_INC +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xb0 = 0xf00008b0` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_WDLY_DQ_INC + + { + "reg": [ + {"name": "csrmodule_wdly_dq_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_WDLY_DM_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xb4 = 0xf00008b4` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_WDLY_DM_RST + + { + "reg": [ + {"name": "csrmodule_wdly_dm_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_WDLY_DM_INC +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xb8 = 0xf00008b8` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_WDLY_DM_INC + + { + "reg": [ + {"name": "csrmodule_wdly_dm_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_WDLY_DQS_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xbc = 0xf00008bc` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_WDLY_DQS_RST + + { + "reg": [ + {"name": "csrmodule_wdly_dqs_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_WDLY_DQS_INC +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xc0 = 0xf00008c0` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_WDLY_DQS_INC + + { + "reg": [ + {"name": "csrmodule_wdly_dqs_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_WDLY_DQS +^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xc4 = 0xf00008c4` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_WDLY_DQS + + { + "reg": [ + {"name": "csrmodule_wdly_dqs[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DDRPHY_CSRMODULE_WDLY_DQ +^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xc8 = 0xf00008c8` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_WDLY_DQ + + { + "reg": [ + {"name": "csrmodule_wdly_dq[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DDRPHY_CSRMODULE_WDLY_DM +^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xcc = 0xf00008cc` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_WDLY_DM + + { + "reg": [ + {"name": "csrmodule_wdly_dm[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/ddr5_test_board/documentation/dfi_switch.rst.txt b/_sources/build/ddr5_test_board/documentation/dfi_switch.rst.txt new file mode 100644 index 000000000..718d8cc34 --- /dev/null +++ b/_sources/build/ddr5_test_board/documentation/dfi_switch.rst.txt @@ -0,0 +1,71 @@ +DFI_SWITCH +========== + +Register Listing for DFI_SWITCH +------------------------------- + ++--------------------------------------------------------------+-----------------------------------------------+ +| Register | Address | ++==============================================================+===============================================+ +| :ref:`DFI_SWITCH_REFRESH_COUNT ` | :ref:`0xf0003800 ` | ++--------------------------------------------------------------+-----------------------------------------------+ +| :ref:`DFI_SWITCH_AT_REFRESH ` | :ref:`0xf0003804 ` | ++--------------------------------------------------------------+-----------------------------------------------+ +| :ref:`DFI_SWITCH_REFRESH_UPDATE ` | :ref:`0xf0003808 ` | ++--------------------------------------------------------------+-----------------------------------------------+ + +DFI_SWITCH_REFRESH_COUNT +^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003800 + 0x0 = 0xf0003800` + + Count of all refresh commands issued (both by Memory Controller and Payload + Executor). Value is latched from internal counter on mode trasition: MC -> PE or + by writing to the `refresh_update` CSR. + + .. wavedrom:: + :caption: DFI_SWITCH_REFRESH_COUNT + + { + "reg": [ + {"name": "refresh_count[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DFI_SWITCH_AT_REFRESH +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003800 + 0x4 = 0xf0003804` + + If set to a value different than 0 the mode transition MC -> PE will be peformed + only when the value of this register matches the current refresh commands count. + + .. wavedrom:: + :caption: DFI_SWITCH_AT_REFRESH + + { + "reg": [ + {"name": "at_refresh[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DFI_SWITCH_REFRESH_UPDATE +^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003800 + 0x8 = 0xf0003808` + + Force an update of the `refresh_count` CSR. + + .. wavedrom:: + :caption: DFI_SWITCH_REFRESH_UPDATE + + { + "reg": [ + {"name": "refresh_update", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/ddr5_test_board/documentation/ethphy.rst.txt b/_sources/build/ddr5_test_board/documentation/ethphy.rst.txt new file mode 100644 index 000000000..f917d9907 --- /dev/null +++ b/_sources/build/ddr5_test_board/documentation/ethphy.rst.txt @@ -0,0 +1,81 @@ +ETHPHY +====== + +Register Listing for ETHPHY +--------------------------- + ++--------------------------------------------+--------------------------------------+ +| Register | Address | ++============================================+======================================+ +| :ref:`ETHPHY_CRG_RESET ` | :ref:`0xf0005000 ` | ++--------------------------------------------+--------------------------------------+ +| :ref:`ETHPHY_MDIO_W ` | :ref:`0xf0005004 ` | ++--------------------------------------------+--------------------------------------+ +| :ref:`ETHPHY_MDIO_R ` | :ref:`0xf0005008 ` | ++--------------------------------------------+--------------------------------------+ + +ETHPHY_CRG_RESET +^^^^^^^^^^^^^^^^ + +`Address: 0xf0005000 + 0x0 = 0xf0005000` + + + .. wavedrom:: + :caption: ETHPHY_CRG_RESET + + { + "reg": [ + {"name": "crg_reset", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +ETHPHY_MDIO_W +^^^^^^^^^^^^^ + +`Address: 0xf0005000 + 0x4 = 0xf0005004` + + + .. wavedrom:: + :caption: ETHPHY_MDIO_W + + { + "reg": [ + {"name": "mdc", "bits": 1}, + {"name": "oe", "bits": 1}, + {"name": "w", "bits": 1}, + {"bits": 29} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------+ +| Field | Name | Description | ++=======+======+=============+ ++-------+------+-------------+ ++-------+------+-------------+ ++-------+------+-------------+ + +ETHPHY_MDIO_R +^^^^^^^^^^^^^ + +`Address: 0xf0005000 + 0x8 = 0xf0005008` + + + .. wavedrom:: + :caption: ETHPHY_MDIO_R + + { + "reg": [ + {"name": "r", "bits": 1}, + {"bits": 31} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------+ +| Field | Name | Description | ++=======+======+=============+ ++-------+------+-------------+ + diff --git a/_sources/build/ddr5_test_board/documentation/identifier_mem.rst.txt b/_sources/build/ddr5_test_board/documentation/identifier_mem.rst.txt new file mode 100644 index 000000000..285bccdc0 --- /dev/null +++ b/_sources/build/ddr5_test_board/documentation/identifier_mem.rst.txt @@ -0,0 +1,30 @@ +IDENTIFIER_MEM +============== + +Register Listing for IDENTIFIER_MEM +----------------------------------- + ++----------------------------------------+------------------------------------+ +| Register | Address | ++========================================+====================================+ +| :ref:`IDENTIFIER_MEM ` | :ref:`0xf0005800 ` | ++----------------------------------------+------------------------------------+ + +IDENTIFIER_MEM +^^^^^^^^^^^^^^ + +`Address: 0xf0005800 + 0x0 = 0xf0005800` + + 8 x 108-bit memory + + .. wavedrom:: + :caption: IDENTIFIER_MEM + + { + "reg": [ + {"name": "identifier_mem[7:0]", "bits": 8}, + {"bits": 24}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/ddr5_test_board/documentation/index.rst.txt b/_sources/build/ddr5_test_board/documentation/index.rst.txt new file mode 100644 index 000000000..11f8340ec --- /dev/null +++ b/_sources/build/ddr5_test_board/documentation/index.rst.txt @@ -0,0 +1,38 @@ +=================================================== +Documentation for Row Hammer Tester DDR5 Test Board +=================================================== + + + +Modules +======= + +.. toctree:: + :maxdepth: 1 + + interrupts + +Register Groups +=============== + +.. toctree:: + :maxdepth: 1 + + leds + ddrphy + controller_settings + ddrctrl + rowhammer + writer + reader + dfi_switch + payload_executor + ctrl + ethphy + identifier_mem + main + sdram + sdram_checker + sdram_generator + timer0 + uart diff --git a/_sources/build/ddr5_test_board/documentation/interrupts.rst.txt b/_sources/build/ddr5_test_board/documentation/interrupts.rst.txt new file mode 100644 index 000000000..bfc948fb1 --- /dev/null +++ b/_sources/build/ddr5_test_board/documentation/interrupts.rst.txt @@ -0,0 +1,22 @@ +Interrupt Controller +==================== + +This device has an ``EventManager``-based interrupt system. Individual modules +generate `events` which are wired into a central interrupt controller. + +When an interrupt occurs, you should look the interrupt number up in the CPU- +specific interrupt table and then call the relevant module. + +Assigned Interrupts +------------------- + +The following interrupts are assigned on this system: + ++-----------+------------------------+ +| Interrupt | Module | ++===========+========================+ +| 1 | :doc:`TIMER0 ` | ++-----------+------------------------+ +| 0 | :doc:`UART ` | ++-----------+------------------------+ + diff --git a/_sources/build/ddr5_test_board/documentation/leds.rst.txt b/_sources/build/ddr5_test_board/documentation/leds.rst.txt new file mode 100644 index 000000000..7d5de2ee2 --- /dev/null +++ b/_sources/build/ddr5_test_board/documentation/leds.rst.txt @@ -0,0 +1,30 @@ +LEDS +==== + +Register Listing for LEDS +------------------------- + ++----------------------------+------------------------------+ +| Register | Address | ++============================+==============================+ +| :ref:`LEDS_OUT ` | :ref:`0xf0000000 ` | ++----------------------------+------------------------------+ + +LEDS_OUT +^^^^^^^^ + +`Address: 0xf0000000 + 0x0 = 0xf0000000` + + Led Output(s) Control. + + .. wavedrom:: + :caption: LEDS_OUT + + { + "reg": [ + {"name": "out[4:0]", "bits": 5}, + {"bits": 27}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/ddr5_test_board/documentation/main.rst.txt b/_sources/build/ddr5_test_board/documentation/main.rst.txt new file mode 100644 index 000000000..4ca615cf1 --- /dev/null +++ b/_sources/build/ddr5_test_board/documentation/main.rst.txt @@ -0,0 +1,48 @@ +MAIN +==== + +Register Listing for MAIN +------------------------- + ++------------------------------------------------+----------------------------------------+ +| Register | Address | ++================================================+========================================+ +| :ref:`MAIN_DQ_REMAPPING1 ` | :ref:`0xf0006000 ` | ++------------------------------------------------+----------------------------------------+ +| :ref:`MAIN_DQ_REMAPPING0 ` | :ref:`0xf0006004 ` | ++------------------------------------------------+----------------------------------------+ + +MAIN_DQ_REMAPPING1 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x0 = 0xf0006000` + + Bits 32-63 of `MAIN_DQ_REMAPPING`. + + .. wavedrom:: + :caption: MAIN_DQ_REMAPPING1 + + { + "reg": [ + {"name": "dq_remapping[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +MAIN_DQ_REMAPPING0 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x4 = 0xf0006004` + + Bits 0-31 of `MAIN_DQ_REMAPPING`. + + .. wavedrom:: + :caption: MAIN_DQ_REMAPPING0 + + { + "reg": [ + {"name": "dq_remapping[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/ddr5_test_board/documentation/payload_executor.rst.txt b/_sources/build/ddr5_test_board/documentation/payload_executor.rst.txt new file mode 100644 index 000000000..132b9f768 --- /dev/null +++ b/_sources/build/ddr5_test_board/documentation/payload_executor.rst.txt @@ -0,0 +1,137 @@ +PAYLOAD_EXECUTOR +================ + + + + Executes the DRAM payload from memory + + + **Instruction decoder** + + All instructions are 32-bit. The format of most instructions is the same, + except for the LOOP instruction, which has a constant TIMESLICE of 1. + + NOOP with a TIMESLICE of 0 is a special case which is interpreted as + STOP instruction. When this instruction is encountered execution gets + finished immediately. + + **NOTE:** TIMESLICE is the number of cycles the instruction will take. This + means that instructions other than NOOP that use TIMESLICE=0 are illegal + (although will silently be executed as having TIMESLICE=1). + + **NOTE2:** LOOP instruction will *jump* COUNT times, meaning that the "code" + inside the loop will effectively be executed COUNT+1 times. + + Op codes: + ++------+-------+ ++ Op + Value + ++======+=======+ ++ NOOP | 0b000 + ++------+-------+ ++ LOOP | 0b111 + ++------+-------+ ++ ACT | 0b100 + ++------+-------+ ++ PRE | 0b101 + ++------+-------+ ++ REF | 0b110 + ++------+-------+ ++ ZQC | 0b001 + ++------+-------+ ++ READ | 0b010 + ++------+-------+ + + Instruction format:: + + LSB MSB + dfi: OP_CODE | TIMESLICE | ADDRESS + noop: OP_CODE | TIMESLICE_NOOP + loop: OP_CODE | COUNT | JUMP + stop: | 0 + + Where ADDRESS depends on the DFI command and is one of:: + + LSB MSB + RANK | BANK | COLUMN + RANK | BANK | ROW + + + +Register Listing for PAYLOAD_EXECUTOR +------------------------------------- + ++------------------------------------------------------------------+-------------------------------------------------+ +| Register | Address | ++==================================================================+=================================================+ +| :ref:`PAYLOAD_EXECUTOR_START ` | :ref:`0xf0004000 ` | ++------------------------------------------------------------------+-------------------------------------------------+ +| :ref:`PAYLOAD_EXECUTOR_STATUS ` | :ref:`0xf0004004 ` | ++------------------------------------------------------------------+-------------------------------------------------+ +| :ref:`PAYLOAD_EXECUTOR_READ_COUNT ` | :ref:`0xf0004008 ` | ++------------------------------------------------------------------+-------------------------------------------------+ + +PAYLOAD_EXECUTOR_START +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0004000 + 0x0 = 0xf0004000` + + Writing to this register initializes payload execution + + .. wavedrom:: + :caption: PAYLOAD_EXECUTOR_START + + { + "reg": [ + {"name": "start", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +PAYLOAD_EXECUTOR_STATUS +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0004000 + 0x4 = 0xf0004004` + + Payload executor status register + + .. wavedrom:: + :caption: PAYLOAD_EXECUTOR_STATUS + + { + "reg": [ + {"name": "ready", "bits": 1}, + {"name": "overflow", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+----------+---------------------------------------------------------------------------------+ +| Field | Name | Description | ++=======+==========+=================================================================================+ +| [0] | READY | Indicates that the executor is not running | ++-------+----------+---------------------------------------------------------------------------------+ +| [1] | OVERFLOW | Indicates the scratchpad memory address counter has overflown due to the number | +| | | of READ commands sent during execution | ++-------+----------+---------------------------------------------------------------------------------+ + +PAYLOAD_EXECUTOR_READ_COUNT +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0004000 + 0x8 = 0xf0004008` + + Number of data from READ commands that is stored in the scratchpad memory + + .. wavedrom:: + :caption: PAYLOAD_EXECUTOR_READ_COUNT + + { + "reg": [ + {"name": "read_count[6:0]", "bits": 7}, + {"bits": 25}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/ddr5_test_board/documentation/reader.rst.txt b/_sources/build/ddr5_test_board/documentation/reader.rst.txt new file mode 100644 index 000000000..650615413 --- /dev/null +++ b/_sources/build/ddr5_test_board/documentation/reader.rst.txt @@ -0,0 +1,424 @@ +READER +====== + + + +DMA DRAM reader. + +Allows to check DRAM contents against a predefined pattern using DMA. + +Pattern +------- + + + Provides access to RAM to store access pattern: `mem_addr` and `mem_data`. + The pattern address space can be limited using the `data_mask`. + + For example, having `mem_adr` filled with `[ 0x04, 0x02, 0x03, ... ]` + and `mem_data` filled with `[ 0xff, 0xaa, 0x55, ... ]` and setting + `data_mask = 0b01`, the pattern [(address, data), ...] written will be: + `[(0x04, 0xff), (0x02, 0xaa), (0x04, 0xff), ...]` (wraps due to masking). + + DRAM memory range that is being accessed can be configured using `mem_mask`. + + To use this module, make sure that `ready` is 1, then write the desired + number of transfers to `count`. Writing to the `start` CSR will initialize + the operation. When the operation is ongoing `ready` will be 0. + + +Reading errors +-------------- + +This module allows to check the locations of errors in the memory. +It scans the configured memory area and compares the values read to +the predefined pattern. If `skip_fifo` is 0, this module will stop +after each error encountered, so that it can be examined. Wait until +the `error_ready` CSR is 1. Then use the CSRs `error_offset`, +`error_data` and `error_expected` to examine the errors in the current +transfer. To continue reading, write 1 to `error_continue` CSR. +Setting `skip_fifo` to 1 will disable this behaviour entirely. + +The final number of errors can be read from `error_count`. +NOTE: This value represents the number of erroneous *DMA transfers*. + +The current progress can be read from the `done` CSR. + + +Register Listing for READER +--------------------------- + ++------------------------------------------------------------------------+----------------------------------------------------+ +| Register | Address | ++========================================================================+====================================================+ +| :ref:`READER_START ` | :ref:`0xf0003000 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_READY ` | :ref:`0xf0003004 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_MODULO ` | :ref:`0xf0003008 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_COUNT ` | :ref:`0xf000300c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_DONE ` | :ref:`0xf0003010 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_MEM_MASK ` | :ref:`0xf0003014 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_DATA_MASK ` | :ref:`0xf0003018 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_DATA_DIV ` | :ref:`0xf000301c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_INVERTER_DIVISOR_MASK ` | :ref:`0xf0003020 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_INVERTER_SELECTION_MASK ` | :ref:`0xf0003024 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_COUNT ` | :ref:`0xf0003028 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_SKIP_FIFO ` | :ref:`0xf000302c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_OFFSET ` | :ref:`0xf0003030 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA1 ` | :ref:`0xf0003034 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA0 ` | :ref:`0xf0003038 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED1 ` | :ref:`0xf000303c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED0 ` | :ref:`0xf0003040 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_READY ` | :ref:`0xf0003044 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_CONTINUE ` | :ref:`0xf0003048 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ + +READER_START +^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x0 = 0xf0003000` + + Write to the register starts the transfer (if ready=1) + + .. wavedrom:: + :caption: READER_START + + { + "reg": [ + {"name": "start", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_READY +^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x4 = 0xf0003004` + + Indicates that the transfer is not ongoing + + .. wavedrom:: + :caption: READER_READY + + { + "reg": [ + {"name": "ready", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_MODULO +^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x8 = 0xf0003008` + + When set use modulo to calculate DMA transfers address rather than bit masking + + .. wavedrom:: + :caption: READER_MODULO + + { + "reg": [ + {"name": "modulo", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_COUNT +^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0xc = 0xf000300c` + + Desired number of DMA transfers + + .. wavedrom:: + :caption: READER_COUNT + + { + "reg": [ + {"name": "count[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_DONE +^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x10 = 0xf0003010` + + Number of completed DMA transfers + + .. wavedrom:: + :caption: READER_DONE + + { + "reg": [ + {"name": "done[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_MEM_MASK +^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x14 = 0xf0003014` + + DRAM address mask for DMA transfers + + .. wavedrom:: + :caption: READER_MEM_MASK + + { + "reg": [ + {"name": "mem_mask[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_DATA_MASK +^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x18 = 0xf0003018` + + Pattern memory address mask + + .. wavedrom:: + :caption: READER_DATA_MASK + + { + "reg": [ + {"name": "data_mask[6:0]", "bits": 7}, + {"bits": 25}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_DATA_DIV +^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x1c = 0xf000301c` + + Pattern memory address divisior-1 + + .. wavedrom:: + :caption: READER_DATA_DIV + + { + "reg": [ + {"name": "data_div[6:0]", "bits": 7}, + {"bits": 25}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_INVERTER_DIVISOR_MASK +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x20 = 0xf0003020` + + Divisor mask for selecting rows for which pattern data gets inverted + + .. wavedrom:: + :caption: READER_INVERTER_DIVISOR_MASK + + { + "reg": [ + {"name": "inverter_divisor_mask[4:0]", "bits": 5}, + {"bits": 27}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_INVERTER_SELECTION_MASK +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x24 = 0xf0003024` + + Selection mask for selecting rows for which pattern data gets inverted + + .. wavedrom:: + :caption: READER_INVERTER_SELECTION_MASK + + { + "reg": [ + {"name": "inverter_selection_mask[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_COUNT +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x28 = 0xf0003028` + + Number of errors detected + + .. wavedrom:: + :caption: READER_ERROR_COUNT + + { + "reg": [ + {"name": "error_count[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_SKIP_FIFO +^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x2c = 0xf000302c` + + Skip waiting for user to read the errors FIFO + + .. wavedrom:: + :caption: READER_SKIP_FIFO + + { + "reg": [ + {"name": "skip_fifo", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_ERROR_OFFSET +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x30 = 0xf0003030` + + Current offset of the error + + .. wavedrom:: + :caption: READER_ERROR_OFFSET + + { + "reg": [ + {"name": "error_offset[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA1 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x34 = 0xf0003034` + + Bits 32-63 of `READER_ERROR_DATA`. Erroneous value read from DRAM memory + + .. wavedrom:: + :caption: READER_ERROR_DATA1 + + { + "reg": [ + {"name": "error_data[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA0 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x38 = 0xf0003038` + + Bits 0-31 of `READER_ERROR_DATA`. + + .. wavedrom:: + :caption: READER_ERROR_DATA0 + + { + "reg": [ + {"name": "error_data[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED1 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x3c = 0xf000303c` + + Bits 32-63 of `READER_ERROR_EXPECTED`. Value expected to be read from DRAM + memory + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED1 + + { + "reg": [ + {"name": "error_expected[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED0 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x40 = 0xf0003040` + + Bits 0-31 of `READER_ERROR_EXPECTED`. + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED0 + + { + "reg": [ + {"name": "error_expected[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_READY +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x44 = 0xf0003044` + + Error detected and ready to read + + .. wavedrom:: + :caption: READER_ERROR_READY + + { + "reg": [ + {"name": "error_ready", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_ERROR_CONTINUE +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x48 = 0xf0003048` + + Continue reading until the next error + + .. wavedrom:: + :caption: READER_ERROR_CONTINUE + + { + "reg": [ + {"name": "error_continue", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/ddr5_test_board/documentation/rowhammer.rst.txt b/_sources/build/ddr5_test_board/documentation/rowhammer.rst.txt new file mode 100644 index 000000000..4056995d8 --- /dev/null +++ b/_sources/build/ddr5_test_board/documentation/rowhammer.rst.txt @@ -0,0 +1,102 @@ +ROWHAMMER +========= + + + +Row Hammer DMA attacker + +This module allows to perform a Row Hammer attack by configuring it with +two addresses that map to different rows of a single bank. When enabled, +it will perform alternating DMA reads from the given locations, which will +result in the DRAM controller having to repeatedly open/close rows at each +read access. + + +Register Listing for ROWHAMMER +------------------------------ + ++------------------------------------------------+----------------------------------------+ +| Register | Address | ++================================================+========================================+ +| :ref:`ROWHAMMER_ENABLED ` | :ref:`0xf0002000 ` | ++------------------------------------------------+----------------------------------------+ +| :ref:`ROWHAMMER_ADDRESS1 ` | :ref:`0xf0002004 ` | ++------------------------------------------------+----------------------------------------+ +| :ref:`ROWHAMMER_ADDRESS2 ` | :ref:`0xf0002008 ` | ++------------------------------------------------+----------------------------------------+ +| :ref:`ROWHAMMER_COUNT ` | :ref:`0xf000200c ` | ++------------------------------------------------+----------------------------------------+ + +ROWHAMMER_ENABLED +^^^^^^^^^^^^^^^^^ + +`Address: 0xf0002000 + 0x0 = 0xf0002000` + + Used to start/stop the operation of the module + + .. wavedrom:: + :caption: ROWHAMMER_ENABLED + + { + "reg": [ + {"name": "enabled", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +ROWHAMMER_ADDRESS1 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0002000 + 0x4 = 0xf0002004` + + First attacked address + + .. wavedrom:: + :caption: ROWHAMMER_ADDRESS1 + + { + "reg": [ + {"name": "address1[27:0]", "bits": 28}, + {"bits": 4}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +ROWHAMMER_ADDRESS2 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0002000 + 0x8 = 0xf0002008` + + Second attacked address + + .. wavedrom:: + :caption: ROWHAMMER_ADDRESS2 + + { + "reg": [ + {"name": "address2[27:0]", "bits": 28}, + {"bits": 4}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +ROWHAMMER_COUNT +^^^^^^^^^^^^^^^ + +`Address: 0xf0002000 + 0xc = 0xf000200c` + + This is the number of DMA accesses performed. When the module is enabled, the + value can be freely read. When the module is disabled, the register is clear-on- + write and has to be read before the next attack. + + .. wavedrom:: + :caption: ROWHAMMER_COUNT + + { + "reg": [ + {"name": "count[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/ddr5_test_board/documentation/sdram.rst.txt b/_sources/build/ddr5_test_board/documentation/sdram.rst.txt new file mode 100644 index 000000000..9bce423b5 --- /dev/null +++ b/_sources/build/ddr5_test_board/documentation/sdram.rst.txt @@ -0,0 +1,1926 @@ +SDRAM +===== + +Register Listing for SDRAM +-------------------------- + ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| Register | Address | ++========================================================================================================+====================================================================+ +| :ref:`SDRAM_DFII_CONTROL ` | :ref:`0xf0006800 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_FORCE_ISSUE ` | :ref:`0xf0006804 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_CMDINJECTOR_COMMAND_STORAGE ` | :ref:`0xf0006808 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_CMDINJECTOR_COMMAND_STORAGE_WR_MASK ` | :ref:`0xf000680c ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_CMDINJECTOR_PHASE_ADDR ` | :ref:`0xf0006810 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_CMDINJECTOR_STORE_CONTINUOUS_CMD ` | :ref:`0xf0006814 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_CMDINJECTOR_STORE_SINGLESHOT_CMD ` | :ref:`0xf0006818 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_CMDINJECTOR_SINGLE_SHOT ` | :ref:`0xf000681c ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_CMDINJECTOR_ISSUE_COMMAND ` | :ref:`0xf0006820 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_CMDINJECTOR_WRDATA_SELECT ` | :ref:`0xf0006824 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_CMDINJECTOR_WRDATA ` | :ref:`0xf0006828 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_CMDINJECTOR_WRDATA_S ` | :ref:`0xf000682c ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_CMDINJECTOR_WRDATA_STORE ` | :ref:`0xf0006830 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_CMDINJECTOR_SETUP ` | :ref:`0xf0006834 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_CMDINJECTOR_SAMPLE ` | :ref:`0xf0006838 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_CMDINJECTOR_RESULT_ARRAY ` | :ref:`0xf000683c ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_CMDINJECTOR_RESET ` | :ref:`0xf0006840 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_CMDINJECTOR_RDDATA_SELECT ` | :ref:`0xf0006844 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_CMDINJECTOR_RDDATA_CAPTURE_CNT ` | :ref:`0xf0006848 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_CMDINJECTOR_RDDATA ` | :ref:`0xf000684c ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRP ` | :ref:`0xf0006850 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRCD ` | :ref:`0xf0006854 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TWR ` | :ref:`0xf0006858 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TWTR ` | :ref:`0xf000685c ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TREFI ` | :ref:`0xf0006860 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRFC ` | :ref:`0xf0006864 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TFAW ` | :ref:`0xf0006868 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TCCD ` | :ref:`0xf000686c ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TCCD_WR ` | :ref:`0xf0006870 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRTP ` | :ref:`0xf0006874 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRRD ` | :ref:`0xf0006878 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRC ` | :ref:`0xf000687c ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRAS ` | :ref:`0xf0006880 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_0 ` | :ref:`0xf0006884 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_0 ` | :ref:`0xf0006888 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_1 ` | :ref:`0xf000688c ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_1 ` | :ref:`0xf0006890 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_2 ` | :ref:`0xf0006894 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_2 ` | :ref:`0xf0006898 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_3 ` | :ref:`0xf000689c ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_3 ` | :ref:`0xf00068a0 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_4 ` | :ref:`0xf00068a4 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_4 ` | :ref:`0xf00068a8 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_5 ` | :ref:`0xf00068ac ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_5 ` | :ref:`0xf00068b0 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_6 ` | :ref:`0xf00068b4 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_6 ` | :ref:`0xf00068b8 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_7 ` | :ref:`0xf00068bc ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_7 ` | :ref:`0xf00068c0 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_8 ` | :ref:`0xf00068c4 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_8 ` | :ref:`0xf00068c8 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_9 ` | :ref:`0xf00068cc ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_9 ` | :ref:`0xf00068d0 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_10 ` | :ref:`0xf00068d4 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_10 ` | :ref:`0xf00068d8 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_11 ` | :ref:`0xf00068dc ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_11 ` | :ref:`0xf00068e0 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_12 ` | :ref:`0xf00068e4 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_12 ` | :ref:`0xf00068e8 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_13 ` | :ref:`0xf00068ec ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_13 ` | :ref:`0xf00068f0 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_14 ` | :ref:`0xf00068f4 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_14 ` | :ref:`0xf00068f8 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_15 ` | :ref:`0xf00068fc ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_15 ` | :ref:`0xf0006900 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_16 ` | :ref:`0xf0006904 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_16 ` | :ref:`0xf0006908 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_17 ` | :ref:`0xf000690c ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_17 ` | :ref:`0xf0006910 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_18 ` | :ref:`0xf0006914 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_18 ` | :ref:`0xf0006918 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_19 ` | :ref:`0xf000691c ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_19 ` | :ref:`0xf0006920 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_20 ` | :ref:`0xf0006924 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_20 ` | :ref:`0xf0006928 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_21 ` | :ref:`0xf000692c ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_21 ` | :ref:`0xf0006930 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_22 ` | :ref:`0xf0006934 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_22 ` | :ref:`0xf0006938 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_23 ` | :ref:`0xf000693c ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_23 ` | :ref:`0xf0006940 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_24 ` | :ref:`0xf0006944 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_24 ` | :ref:`0xf0006948 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_25 ` | :ref:`0xf000694c ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_25 ` | :ref:`0xf0006950 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_26 ` | :ref:`0xf0006954 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_26 ` | :ref:`0xf0006958 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_27 ` | :ref:`0xf000695c ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_27 ` | :ref:`0xf0006960 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_28 ` | :ref:`0xf0006964 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_28 ` | :ref:`0xf0006968 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_29 ` | :ref:`0xf000696c ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_29 ` | :ref:`0xf0006970 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_30 ` | :ref:`0xf0006974 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_30 ` | :ref:`0xf0006978 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_31 ` | :ref:`0xf000697c ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_31 ` | :ref:`0xf0006980 ` | ++--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+ + +SDRAM_DFII_CONTROL +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x0 = 0xf0006800` + + Control DFI signals common to all phases + + .. wavedrom:: + :caption: SDRAM_DFII_CONTROL + + { + "reg": [ + {"name": "sel", "attr": '1', "bits": 1}, + {"name": "cke", "bits": 1}, + {"name": "odt", "bits": 1}, + {"name": "reset_n", "bits": 1}, + {"name": "mode_2n", "attr": '1', "bits": 1}, + {"name": "control", "bits": 1}, + {"bits": 26} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+---------+-------------------------------------------+ +| Field | Name | Description | ++=======+=========+===========================================+ +| [0] | SEL | | +| | | | +| | | +---------+-----------------------------+ | +| | | | Value | Description | | +| | | +=========+=============================+ | +| | | | ``0b0`` | Software (CPU) control. | | +| | | +---------+-----------------------------+ | +| | | | ``0b1`` | Hardware control (default). | | +| | | +---------+-----------------------------+ | ++-------+---------+-------------------------------------------+ +| [1] | CKE | DFI clock enable bus | ++-------+---------+-------------------------------------------+ +| [2] | ODT | DFI on-die termination bus | ++-------+---------+-------------------------------------------+ +| [3] | RESET_N | DFI clock reset bus | ++-------+---------+-------------------------------------------+ +| [4] | MODE_2N | | +| | | | +| | | +---------+----------------------+ | +| | | | Value | Description | | +| | | +=========+======================+ | +| | | | ``0b0`` | In 1N mode | | +| | | +---------+----------------------+ | +| | | | ``0b1`` | In 2N mode (Default) | | +| | | +---------+----------------------+ | ++-------+---------+-------------------------------------------+ +| [5] | CONTROL | | +| | | | +| | | +---------+--------------+ | +| | | | Value | Description | | +| | | +=========+==============+ | +| | | | ``0b1`` | Cmd Injector | | +| | | +---------+--------------+ | ++-------+---------+-------------------------------------------+ + +SDRAM_DFII_FORCE_ISSUE +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x4 = 0xf0006804` + + + .. wavedrom:: + :caption: SDRAM_DFII_FORCE_ISSUE + + { + "reg": [ + {"name": "dfii_force_issue", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_CMDINJECTOR_COMMAND_STORAGE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x8 = 0xf0006808` + + DDR5 command and control signals + + .. wavedrom:: + :caption: SDRAM_DFII_CMDINJECTOR_COMMAND_STORAGE + + { + "reg": [ + {"name": "ca", "bits": 14}, + {"name": "cs", "bits": 1}, + {"name": "wrdata_en", "bits": 1}, + {"name": "rddata_en", "bits": 1}, + {"bits": 15} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++--------+-----------+---------------------+ +| Field | Name | Description | ++========+===========+=====================+ +| [13:0] | CA | Command/Address bus | ++--------+-----------+---------------------+ +| [14] | CS | DFI chip select bus | ++--------+-----------+---------------------+ ++--------+-----------+---------------------+ ++--------+-----------+---------------------+ + +SDRAM_DFII_CMDINJECTOR_COMMAND_STORAGE_WR_MASK +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xc = 0xf000680c` + + DDR5 wrdata mask control signals + + .. wavedrom:: + :caption: SDRAM_DFII_CMDINJECTOR_COMMAND_STORAGE_WR_MASK + + { + "reg": [ + {"name": "wrdata_mask", "bits": 2}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+-------------+-------------+ +| Field | Name | Description | ++=======+=============+=============+ ++-------+-------------+-------------+ + +SDRAM_DFII_CMDINJECTOR_PHASE_ADDR +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x10 = 0xf0006810` + + + .. wavedrom:: + :caption: SDRAM_DFII_CMDINJECTOR_PHASE_ADDR + + { + "reg": [ + {"name": "dfii_cmdinjector_phase_addr[7:0]", "bits": 8}, + {"bits": 24}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_CMDINJECTOR_STORE_CONTINUOUS_CMD +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x14 = 0xf0006814` + + + .. wavedrom:: + :caption: SDRAM_DFII_CMDINJECTOR_STORE_CONTINUOUS_CMD + + { + "reg": [ + {"name": "dfii_cmdinjector_store_continuous_cmd", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_CMDINJECTOR_STORE_SINGLESHOT_CMD +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x18 = 0xf0006818` + + + .. wavedrom:: + :caption: SDRAM_DFII_CMDINJECTOR_STORE_SINGLESHOT_CMD + + { + "reg": [ + {"name": "dfii_cmdinjector_store_singleshot_cmd", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_CMDINJECTOR_SINGLE_SHOT +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x1c = 0xf000681c` + + + .. wavedrom:: + :caption: SDRAM_DFII_CMDINJECTOR_SINGLE_SHOT + + { + "reg": [ + {"name": "dfii_cmdinjector_single_shot", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_CMDINJECTOR_ISSUE_COMMAND +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x20 = 0xf0006820` + + + .. wavedrom:: + :caption: SDRAM_DFII_CMDINJECTOR_ISSUE_COMMAND + + { + "reg": [ + {"name": "dfii_cmdinjector_issue_command", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_CMDINJECTOR_WRDATA_SELECT +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x24 = 0xf0006824` + + + .. wavedrom:: + :caption: SDRAM_DFII_CMDINJECTOR_WRDATA_SELECT + + { + "reg": [ + {"name": "dfii_cmdinjector_wrdata_select[3:0]", "bits": 4}, + {"bits": 28}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_CMDINJECTOR_WRDATA +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x28 = 0xf0006828` + + + .. wavedrom:: + :caption: SDRAM_DFII_CMDINJECTOR_WRDATA + + { + "reg": [ + {"name": "dfii_cmdinjector_wrdata[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_CMDINJECTOR_WRDATA_S +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x2c = 0xf000682c` + + + .. wavedrom:: + :caption: SDRAM_DFII_CMDINJECTOR_WRDATA_S + + { + "reg": [ + {"name": "dfii_cmdinjector_wrdata_s[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_CMDINJECTOR_WRDATA_STORE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x30 = 0xf0006830` + + + .. wavedrom:: + :caption: SDRAM_DFII_CMDINJECTOR_WRDATA_STORE + + { + "reg": [ + {"name": "dfii_cmdinjector_wrdata_store", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_CMDINJECTOR_SETUP +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x34 = 0xf0006834` + + + .. wavedrom:: + :caption: SDRAM_DFII_CMDINJECTOR_SETUP + + { + "reg": [ + {"name": "initial_state", "bits": 1}, + {"name": "operation", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+---------------+------------------------------+ +| Field | Name | Description | ++=======+===============+==============================+ +| [0] | INITIAL_STATE | Initial value of all bits | ++-------+---------------+------------------------------+ +| [1] | OPERATION | 0 - `or` (default), 1 -`and` | ++-------+---------------+------------------------------+ + +SDRAM_DFII_CMDINJECTOR_SAMPLE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x38 = 0xf0006838` + + + .. wavedrom:: + :caption: SDRAM_DFII_CMDINJECTOR_SAMPLE + + { + "reg": [ + {"name": "dfii_cmdinjector_sample", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_CMDINJECTOR_RESULT_ARRAY +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x3c = 0xf000683c` + + + .. wavedrom:: + :caption: SDRAM_DFII_CMDINJECTOR_RESULT_ARRAY + + { + "reg": [ + {"name": "dfii_cmdinjector_result_array[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_CMDINJECTOR_RESET +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x40 = 0xf0006840` + + + .. wavedrom:: + :caption: SDRAM_DFII_CMDINJECTOR_RESET + + { + "reg": [ + {"name": "dfii_cmdinjector_reset", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_CMDINJECTOR_RDDATA_SELECT +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x44 = 0xf0006844` + + + .. wavedrom:: + :caption: SDRAM_DFII_CMDINJECTOR_RDDATA_SELECT + + { + "reg": [ + {"name": "dfii_cmdinjector_rddata_select[3:0]", "bits": 4}, + {"bits": 28}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_CMDINJECTOR_RDDATA_CAPTURE_CNT +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x48 = 0xf0006848` + + + .. wavedrom:: + :caption: SDRAM_DFII_CMDINJECTOR_RDDATA_CAPTURE_CNT + + { + "reg": [ + {"name": "dfii_cmdinjector_rddata_capture_cnt[3:0]", "bits": 4}, + {"bits": 28}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_CMDINJECTOR_RDDATA +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x4c = 0xf000684c` + + + .. wavedrom:: + :caption: SDRAM_DFII_CMDINJECTOR_RDDATA + + { + "reg": [ + {"name": "dfii_cmdinjector_rddata[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_TRP +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x50 = 0xf0006850` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRP + + { + "reg": [ + {"name": "controller_trp[2:0]", "attr": 'reset: 5', "bits": 3}, + {"bits": 29}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TRCD +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x54 = 0xf0006854` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRCD + + { + "reg": [ + {"name": "controller_trcd[2:0]", "attr": 'reset: 5', "bits": 3}, + {"bits": 29}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TWR +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x58 = 0xf0006858` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TWR + + { + "reg": [ + {"name": "controller_twr[3:0]", "attr": 'reset: 7', "bits": 4}, + {"bits": 28}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TWTR +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x5c = 0xf000685c` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TWTR + + { + "reg": [ + {"name": "controller_twtr[4:0]", "attr": 'reset: 4', "bits": 5}, + {"bits": 27}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TREFI +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x60 = 0xf0006860` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TREFI + + { + "reg": [ + {"name": "controller_trefi[9:0]", "attr": 'reset: 779', "bits": 10}, + {"bits": 22}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_TRFC +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x64 = 0xf0006864` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRFC + + { + "reg": [ + {"name": "controller_trfc[6:0]", "attr": 'reset: 60', "bits": 7}, + {"bits": 25}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TFAW +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x68 = 0xf0006868` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TFAW + + { + "reg": [ + {"name": "controller_tfaw[3:0]", "attr": 'reset: 8', "bits": 4}, + {"bits": 28}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TCCD +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x6c = 0xf000686c` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TCCD + + { + "reg": [ + {"name": "controller_tccd[1:0]", "attr": 'reset: 2', "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TCCD_WR +^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x70 = 0xf0006870` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TCCD_WR + + { + "reg": [ + {"name": "controller_tccd_wr[3:0]", "attr": 'reset: 8', "bits": 4}, + {"bits": 28}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TRTP +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x74 = 0xf0006874` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRTP + + { + "reg": [ + {"name": "controller_trtp[1:0]", "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TRRD +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x78 = 0xf0006878` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRRD + + { + "reg": [ + {"name": "controller_trrd[1:0]", "attr": 'reset: 2', "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TRC +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x7c = 0xf000687c` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRC + + { + "reg": [ + {"name": "controller_trc[3:0]", "attr": 'reset: 11', "bits": 4}, + {"bits": 28}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TRAS +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x80 = 0xf0006880` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRAS + + { + "reg": [ + {"name": "controller_tras[3:0]", "attr": 'reset: 8', "bits": 4}, + {"bits": 28}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_LAST_ADDR_0 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x84 = 0xf0006884` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_0 + + { + "reg": [ + {"name": "controller_last_addr_0[22:0]", "bits": 23}, + {"bits": 9}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_0 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x88 = 0xf0006888` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_0 + + { + "reg": [ + {"name": "controller_last_active_row_0[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_1 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x8c = 0xf000688c` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_1 + + { + "reg": [ + {"name": "controller_last_addr_1[22:0]", "bits": 23}, + {"bits": 9}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_1 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x90 = 0xf0006890` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_1 + + { + "reg": [ + {"name": "controller_last_active_row_1[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_2 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x94 = 0xf0006894` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_2 + + { + "reg": [ + {"name": "controller_last_addr_2[22:0]", "bits": 23}, + {"bits": 9}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_2 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x98 = 0xf0006898` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_2 + + { + "reg": [ + {"name": "controller_last_active_row_2[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_3 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x9c = 0xf000689c` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_3 + + { + "reg": [ + {"name": "controller_last_addr_3[22:0]", "bits": 23}, + {"bits": 9}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_3 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xa0 = 0xf00068a0` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_3 + + { + "reg": [ + {"name": "controller_last_active_row_3[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_4 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xa4 = 0xf00068a4` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_4 + + { + "reg": [ + {"name": "controller_last_addr_4[22:0]", "bits": 23}, + {"bits": 9}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_4 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xa8 = 0xf00068a8` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_4 + + { + "reg": [ + {"name": "controller_last_active_row_4[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_5 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xac = 0xf00068ac` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_5 + + { + "reg": [ + {"name": "controller_last_addr_5[22:0]", "bits": 23}, + {"bits": 9}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_5 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xb0 = 0xf00068b0` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_5 + + { + "reg": [ + {"name": "controller_last_active_row_5[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_6 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xb4 = 0xf00068b4` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_6 + + { + "reg": [ + {"name": "controller_last_addr_6[22:0]", "bits": 23}, + {"bits": 9}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_6 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xb8 = 0xf00068b8` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_6 + + { + "reg": [ + {"name": "controller_last_active_row_6[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_7 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xbc = 0xf00068bc` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_7 + + { + "reg": [ + {"name": "controller_last_addr_7[22:0]", "bits": 23}, + {"bits": 9}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_7 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xc0 = 0xf00068c0` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_7 + + { + "reg": [ + {"name": "controller_last_active_row_7[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_8 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xc4 = 0xf00068c4` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_8 + + { + "reg": [ + {"name": "controller_last_addr_8[22:0]", "bits": 23}, + {"bits": 9}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_8 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xc8 = 0xf00068c8` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_8 + + { + "reg": [ + {"name": "controller_last_active_row_8[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_9 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xcc = 0xf00068cc` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_9 + + { + "reg": [ + {"name": "controller_last_addr_9[22:0]", "bits": 23}, + {"bits": 9}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_9 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xd0 = 0xf00068d0` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_9 + + { + "reg": [ + {"name": "controller_last_active_row_9[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_10 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xd4 = 0xf00068d4` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_10 + + { + "reg": [ + {"name": "controller_last_addr_10[22:0]", "bits": 23}, + {"bits": 9}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_10 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xd8 = 0xf00068d8` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_10 + + { + "reg": [ + {"name": "controller_last_active_row_10[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_11 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xdc = 0xf00068dc` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_11 + + { + "reg": [ + {"name": "controller_last_addr_11[22:0]", "bits": 23}, + {"bits": 9}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_11 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xe0 = 0xf00068e0` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_11 + + { + "reg": [ + {"name": "controller_last_active_row_11[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_12 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xe4 = 0xf00068e4` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_12 + + { + "reg": [ + {"name": "controller_last_addr_12[22:0]", "bits": 23}, + {"bits": 9}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_12 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xe8 = 0xf00068e8` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_12 + + { + "reg": [ + {"name": "controller_last_active_row_12[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_13 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xec = 0xf00068ec` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_13 + + { + "reg": [ + {"name": "controller_last_addr_13[22:0]", "bits": 23}, + {"bits": 9}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_13 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xf0 = 0xf00068f0` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_13 + + { + "reg": [ + {"name": "controller_last_active_row_13[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_14 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xf4 = 0xf00068f4` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_14 + + { + "reg": [ + {"name": "controller_last_addr_14[22:0]", "bits": 23}, + {"bits": 9}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_14 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xf8 = 0xf00068f8` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_14 + + { + "reg": [ + {"name": "controller_last_active_row_14[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_15 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xfc = 0xf00068fc` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_15 + + { + "reg": [ + {"name": "controller_last_addr_15[22:0]", "bits": 23}, + {"bits": 9}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_15 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x100 = 0xf0006900` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_15 + + { + "reg": [ + {"name": "controller_last_active_row_15[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_16 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x104 = 0xf0006904` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_16 + + { + "reg": [ + {"name": "controller_last_addr_16[22:0]", "bits": 23}, + {"bits": 9}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_16 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x108 = 0xf0006908` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_16 + + { + "reg": [ + {"name": "controller_last_active_row_16[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_17 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x10c = 0xf000690c` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_17 + + { + "reg": [ + {"name": "controller_last_addr_17[22:0]", "bits": 23}, + {"bits": 9}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_17 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x110 = 0xf0006910` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_17 + + { + "reg": [ + {"name": "controller_last_active_row_17[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_18 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x114 = 0xf0006914` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_18 + + { + "reg": [ + {"name": "controller_last_addr_18[22:0]", "bits": 23}, + {"bits": 9}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_18 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x118 = 0xf0006918` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_18 + + { + "reg": [ + {"name": "controller_last_active_row_18[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_19 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x11c = 0xf000691c` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_19 + + { + "reg": [ + {"name": "controller_last_addr_19[22:0]", "bits": 23}, + {"bits": 9}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_19 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x120 = 0xf0006920` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_19 + + { + "reg": [ + {"name": "controller_last_active_row_19[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_20 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x124 = 0xf0006924` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_20 + + { + "reg": [ + {"name": "controller_last_addr_20[22:0]", "bits": 23}, + {"bits": 9}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_20 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x128 = 0xf0006928` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_20 + + { + "reg": [ + {"name": "controller_last_active_row_20[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_21 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x12c = 0xf000692c` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_21 + + { + "reg": [ + {"name": "controller_last_addr_21[22:0]", "bits": 23}, + {"bits": 9}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_21 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x130 = 0xf0006930` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_21 + + { + "reg": [ + {"name": "controller_last_active_row_21[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_22 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x134 = 0xf0006934` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_22 + + { + "reg": [ + {"name": "controller_last_addr_22[22:0]", "bits": 23}, + {"bits": 9}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_22 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x138 = 0xf0006938` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_22 + + { + "reg": [ + {"name": "controller_last_active_row_22[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_23 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x13c = 0xf000693c` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_23 + + { + "reg": [ + {"name": "controller_last_addr_23[22:0]", "bits": 23}, + {"bits": 9}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_23 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x140 = 0xf0006940` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_23 + + { + "reg": [ + {"name": "controller_last_active_row_23[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_24 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x144 = 0xf0006944` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_24 + + { + "reg": [ + {"name": "controller_last_addr_24[22:0]", "bits": 23}, + {"bits": 9}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_24 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x148 = 0xf0006948` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_24 + + { + "reg": [ + {"name": "controller_last_active_row_24[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_25 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x14c = 0xf000694c` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_25 + + { + "reg": [ + {"name": "controller_last_addr_25[22:0]", "bits": 23}, + {"bits": 9}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_25 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x150 = 0xf0006950` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_25 + + { + "reg": [ + {"name": "controller_last_active_row_25[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_26 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x154 = 0xf0006954` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_26 + + { + "reg": [ + {"name": "controller_last_addr_26[22:0]", "bits": 23}, + {"bits": 9}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_26 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x158 = 0xf0006958` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_26 + + { + "reg": [ + {"name": "controller_last_active_row_26[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_27 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x15c = 0xf000695c` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_27 + + { + "reg": [ + {"name": "controller_last_addr_27[22:0]", "bits": 23}, + {"bits": 9}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_27 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x160 = 0xf0006960` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_27 + + { + "reg": [ + {"name": "controller_last_active_row_27[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_28 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x164 = 0xf0006964` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_28 + + { + "reg": [ + {"name": "controller_last_addr_28[22:0]", "bits": 23}, + {"bits": 9}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_28 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x168 = 0xf0006968` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_28 + + { + "reg": [ + {"name": "controller_last_active_row_28[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_29 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x16c = 0xf000696c` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_29 + + { + "reg": [ + {"name": "controller_last_addr_29[22:0]", "bits": 23}, + {"bits": 9}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_29 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x170 = 0xf0006970` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_29 + + { + "reg": [ + {"name": "controller_last_active_row_29[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_30 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x174 = 0xf0006974` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_30 + + { + "reg": [ + {"name": "controller_last_addr_30[22:0]", "bits": 23}, + {"bits": 9}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_30 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x178 = 0xf0006978` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_30 + + { + "reg": [ + {"name": "controller_last_active_row_30[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_31 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x17c = 0xf000697c` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_31 + + { + "reg": [ + {"name": "controller_last_addr_31[22:0]", "bits": 23}, + {"bits": 9}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_31 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x180 = 0xf0006980` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_31 + + { + "reg": [ + {"name": "controller_last_active_row_31[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/ddr5_test_board/documentation/sdram_checker.rst.txt b/_sources/build/ddr5_test_board/documentation/sdram_checker.rst.txt new file mode 100644 index 000000000..4ec6a17e9 --- /dev/null +++ b/_sources/build/ddr5_test_board/documentation/sdram_checker.rst.txt @@ -0,0 +1,186 @@ +SDRAM_CHECKER +============= + +Register Listing for SDRAM_CHECKER +---------------------------------- + ++----------------------------------------------------+------------------------------------------+ +| Register | Address | ++====================================================+==========================================+ +| :ref:`SDRAM_CHECKER_RESET ` | :ref:`0xf0007000 ` | ++----------------------------------------------------+------------------------------------------+ +| :ref:`SDRAM_CHECKER_START ` | :ref:`0xf0007004 ` | ++----------------------------------------------------+------------------------------------------+ +| :ref:`SDRAM_CHECKER_DONE ` | :ref:`0xf0007008 ` | ++----------------------------------------------------+------------------------------------------+ +| :ref:`SDRAM_CHECKER_BASE ` | :ref:`0xf000700c ` | ++----------------------------------------------------+------------------------------------------+ +| :ref:`SDRAM_CHECKER_END ` | :ref:`0xf0007010 ` | ++----------------------------------------------------+------------------------------------------+ +| :ref:`SDRAM_CHECKER_LENGTH ` | :ref:`0xf0007014 ` | ++----------------------------------------------------+------------------------------------------+ +| :ref:`SDRAM_CHECKER_RANDOM ` | :ref:`0xf0007018 ` | ++----------------------------------------------------+------------------------------------------+ +| :ref:`SDRAM_CHECKER_TICKS ` | :ref:`0xf000701c ` | ++----------------------------------------------------+------------------------------------------+ +| :ref:`SDRAM_CHECKER_ERRORS ` | :ref:`0xf0007020 ` | ++----------------------------------------------------+------------------------------------------+ + +SDRAM_CHECKER_RESET +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x0 = 0xf0007000` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_RESET + + { + "reg": [ + {"name": "reset", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CHECKER_START +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x4 = 0xf0007004` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_START + + { + "reg": [ + {"name": "start", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CHECKER_DONE +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x8 = 0xf0007008` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_DONE + + { + "reg": [ + {"name": "done", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CHECKER_BASE +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0xc = 0xf000700c` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_BASE + + { + "reg": [ + {"name": "base[30:0]", "bits": 31}, + {"bits": 1}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CHECKER_END +^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x10 = 0xf0007010` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_END + + { + "reg": [ + {"name": "end[30:0]", "bits": 31}, + {"bits": 1}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CHECKER_LENGTH +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x14 = 0xf0007014` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_LENGTH + + { + "reg": [ + {"name": "length[30:0]", "bits": 31}, + {"bits": 1}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CHECKER_RANDOM +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x18 = 0xf0007018` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_RANDOM + + { + "reg": [ + {"name": "data", "bits": 1}, + {"name": "addr", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------+ +| Field | Name | Description | ++=======+======+=============+ ++-------+------+-------------+ ++-------+------+-------------+ + +SDRAM_CHECKER_TICKS +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x1c = 0xf000701c` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_TICKS + + { + "reg": [ + {"name": "ticks[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CHECKER_ERRORS +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x20 = 0xf0007020` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_ERRORS + + { + "reg": [ + {"name": "errors[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/ddr5_test_board/documentation/sdram_generator.rst.txt b/_sources/build/ddr5_test_board/documentation/sdram_generator.rst.txt new file mode 100644 index 000000000..27e1a8a22 --- /dev/null +++ b/_sources/build/ddr5_test_board/documentation/sdram_generator.rst.txt @@ -0,0 +1,168 @@ +SDRAM_GENERATOR +=============== + +Register Listing for SDRAM_GENERATOR +------------------------------------ + ++--------------------------------------------------------+--------------------------------------------+ +| Register | Address | ++========================================================+============================================+ +| :ref:`SDRAM_GENERATOR_RESET ` | :ref:`0xf0007800 ` | ++--------------------------------------------------------+--------------------------------------------+ +| :ref:`SDRAM_GENERATOR_START ` | :ref:`0xf0007804 ` | ++--------------------------------------------------------+--------------------------------------------+ +| :ref:`SDRAM_GENERATOR_DONE ` | :ref:`0xf0007808 ` | ++--------------------------------------------------------+--------------------------------------------+ +| :ref:`SDRAM_GENERATOR_BASE ` | :ref:`0xf000780c ` | ++--------------------------------------------------------+--------------------------------------------+ +| :ref:`SDRAM_GENERATOR_END ` | :ref:`0xf0007810 ` | ++--------------------------------------------------------+--------------------------------------------+ +| :ref:`SDRAM_GENERATOR_LENGTH ` | :ref:`0xf0007814 ` | ++--------------------------------------------------------+--------------------------------------------+ +| :ref:`SDRAM_GENERATOR_RANDOM ` | :ref:`0xf0007818 ` | ++--------------------------------------------------------+--------------------------------------------+ +| :ref:`SDRAM_GENERATOR_TICKS ` | :ref:`0xf000781c ` | ++--------------------------------------------------------+--------------------------------------------+ + +SDRAM_GENERATOR_RESET +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x0 = 0xf0007800` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_RESET + + { + "reg": [ + {"name": "reset", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_GENERATOR_START +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x4 = 0xf0007804` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_START + + { + "reg": [ + {"name": "start", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_GENERATOR_DONE +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x8 = 0xf0007808` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_DONE + + { + "reg": [ + {"name": "done", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_GENERATOR_BASE +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0xc = 0xf000780c` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_BASE + + { + "reg": [ + {"name": "base[30:0]", "bits": 31}, + {"bits": 1}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_GENERATOR_END +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x10 = 0xf0007810` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_END + + { + "reg": [ + {"name": "end[30:0]", "bits": 31}, + {"bits": 1}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_GENERATOR_LENGTH +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x14 = 0xf0007814` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_LENGTH + + { + "reg": [ + {"name": "length[30:0]", "bits": 31}, + {"bits": 1}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_GENERATOR_RANDOM +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x18 = 0xf0007818` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_RANDOM + + { + "reg": [ + {"name": "data", "bits": 1}, + {"name": "addr", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------+ +| Field | Name | Description | ++=======+======+=============+ ++-------+------+-------------+ ++-------+------+-------------+ + +SDRAM_GENERATOR_TICKS +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x1c = 0xf000781c` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_TICKS + + { + "reg": [ + {"name": "ticks[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/ddr5_test_board/documentation/timer0.rst.txt b/_sources/build/ddr5_test_board/documentation/timer0.rst.txt new file mode 100644 index 000000000..65b92303b --- /dev/null +++ b/_sources/build/ddr5_test_board/documentation/timer0.rst.txt @@ -0,0 +1,228 @@ +TIMER0 +====== + +Timer +----- + +Provides a generic Timer core. + +The Timer is implemented as a countdown timer that can be used in various modes: + +- Polling : Returns current countdown value to software +- One-Shot: Loads itself and stops when value reaches ``0`` +- Periodic: (Re-)Loads itself when value reaches ``0`` + +``en`` register allows the user to enable/disable the Timer. When the Timer is enabled, it is +automatically loaded with the value of `load` register. + +When the Timer reaches ``0``, it is automatically reloaded with value of `reload` register. + +The user can latch the current countdown value by writing to ``update_value`` register, it will +update ``value`` register with current countdown value. + +To use the Timer in One-Shot mode, the user needs to: + +- Disable the timer +- Set the ``load`` register to the expected duration +- (Re-)Enable the Timer + +To use the Timer in Periodic mode, the user needs to: + +- Disable the Timer +- Set the ``load`` register to 0 +- Set the ``reload`` register to the expected period +- Enable the Timer + +For both modes, the CPU can be advertised by an IRQ that the duration/period has elapsed. (The +CPU can also do software polling with ``update_value`` and ``value`` to know the elapsed duration) + + +Register Listing for TIMER0 +--------------------------- + ++--------------------------------------------------+-----------------------------------------+ +| Register | Address | ++==================================================+=========================================+ +| :ref:`TIMER0_LOAD ` | :ref:`0xf0008000 ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_RELOAD ` | :ref:`0xf0008004 ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_EN ` | :ref:`0xf0008008 ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_UPDATE_VALUE ` | :ref:`0xf000800c ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_VALUE ` | :ref:`0xf0008010 ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_EV_STATUS ` | :ref:`0xf0008014 ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_EV_PENDING ` | :ref:`0xf0008018 ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_EV_ENABLE ` | :ref:`0xf000801c ` | ++--------------------------------------------------+-----------------------------------------+ + +TIMER0_LOAD +^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x0 = 0xf0008000` + + Load value when Timer is (re-)enabled. In One-Shot mode, the value written to + this register specifies the Timer's duration in clock cycles. + + .. wavedrom:: + :caption: TIMER0_LOAD + + { + "reg": [ + {"name": "load[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +TIMER0_RELOAD +^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x4 = 0xf0008004` + + Reload value when Timer reaches ``0``. In Periodic mode, the value written to + this register specify the Timer's period in clock cycles. + + .. wavedrom:: + :caption: TIMER0_RELOAD + + { + "reg": [ + {"name": "reload[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +TIMER0_EN +^^^^^^^^^ + +`Address: 0xf0008000 + 0x8 = 0xf0008008` + + Enable flag of the Timer. Set this flag to ``1`` to enable/start the Timer. Set + to ``0`` to disable the Timer. + + .. wavedrom:: + :caption: TIMER0_EN + + { + "reg": [ + {"name": "en", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +TIMER0_UPDATE_VALUE +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0xc = 0xf000800c` + + Update trigger for the current countdown value. A write to this register latches + the current countdown value to ``value`` register. + + .. wavedrom:: + :caption: TIMER0_UPDATE_VALUE + + { + "reg": [ + {"name": "update_value", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +TIMER0_VALUE +^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x10 = 0xf0008010` + + Latched countdown value. This value is updated by writing to ``update_value``. + + .. wavedrom:: + :caption: TIMER0_VALUE + + { + "reg": [ + {"name": "value[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +TIMER0_EV_STATUS +^^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x14 = 0xf0008014` + + This register contains the current raw level of the zero event trigger. Writes + to this register have no effect. + + .. wavedrom:: + :caption: TIMER0_EV_STATUS + + { + "reg": [ + {"name": "zero", "bits": 1}, + {"bits": 31} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-----------------------------+ +| Field | Name | Description | ++=======+======+=============================+ +| [0] | ZERO | Level of the ``zero`` event | ++-------+------+-----------------------------+ + +TIMER0_EV_PENDING +^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x18 = 0xf0008018` + + When a zero event occurs, the corresponding bit will be set in this register. + To clear the Event, set the corresponding bit in this register. + + .. wavedrom:: + :caption: TIMER0_EV_PENDING + + { + "reg": [ + {"name": "zero", "bits": 1}, + {"bits": 31} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+--------------------------------------------------------------------------------+ +| Field | Name | Description | ++=======+======+================================================================================+ +| [0] | ZERO | `1` if a `zero` event occurred. This Event is triggered on a **falling** edge. | ++-------+------+--------------------------------------------------------------------------------+ + +TIMER0_EV_ENABLE +^^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x1c = 0xf000801c` + + This register enables the corresponding zero events. Write a ``0`` to this + register to disable individual events. + + .. wavedrom:: + :caption: TIMER0_EV_ENABLE + + { + "reg": [ + {"name": "zero", "bits": 1}, + {"bits": 31} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+--------------------------------------------+ +| Field | Name | Description | ++=======+======+============================================+ +| [0] | ZERO | Write a ``1`` to enable the ``zero`` Event | ++-------+------+--------------------------------------------+ + diff --git a/_sources/build/ddr5_test_board/documentation/uart.rst.txt b/_sources/build/ddr5_test_board/documentation/uart.rst.txt new file mode 100644 index 000000000..36d4199d6 --- /dev/null +++ b/_sources/build/ddr5_test_board/documentation/uart.rst.txt @@ -0,0 +1,388 @@ +UART +==== + +Register Listing for UART +------------------------- + ++------------------------------------------------------+-------------------------------------------+ +| Register | Address | ++======================================================+===========================================+ +| :ref:`UART_RXTX ` | :ref:`0xf0008800 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_TXFULL ` | :ref:`0xf0008804 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_RXEMPTY ` | :ref:`0xf0008808 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_EV_STATUS ` | :ref:`0xf000880c ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_EV_PENDING ` | :ref:`0xf0008810 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_EV_ENABLE ` | :ref:`0xf0008814 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_TXEMPTY ` | :ref:`0xf0008818 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_RXFULL ` | :ref:`0xf000881c ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_RXTX ` | :ref:`0xf0008820 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_TXFULL ` | :ref:`0xf0008824 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_RXEMPTY ` | :ref:`0xf0008828 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_EV_STATUS ` | :ref:`0xf000882c ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_EV_PENDING ` | :ref:`0xf0008830 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_EV_ENABLE ` | :ref:`0xf0008834 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_TXEMPTY ` | :ref:`0xf0008838 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_RXFULL ` | :ref:`0xf000883c ` | ++------------------------------------------------------+-------------------------------------------+ + +UART_RXTX +^^^^^^^^^ + +`Address: 0xf0008800 + 0x0 = 0xf0008800` + + + .. wavedrom:: + :caption: UART_RXTX + + { + "reg": [ + {"name": "rxtx[7:0]", "bits": 8}, + {"bits": 24}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +UART_TXFULL +^^^^^^^^^^^ + +`Address: 0xf0008800 + 0x4 = 0xf0008804` + + TX FIFO Full. + + .. wavedrom:: + :caption: UART_TXFULL + + { + "reg": [ + {"name": "txfull", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_RXEMPTY +^^^^^^^^^^^^ + +`Address: 0xf0008800 + 0x8 = 0xf0008808` + + RX FIFO Empty. + + .. wavedrom:: + :caption: UART_RXEMPTY + + { + "reg": [ + {"name": "rxempty", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_EV_STATUS +^^^^^^^^^^^^^^ + +`Address: 0xf0008800 + 0xc = 0xf000880c` + + This register contains the current raw level of the rx event trigger. Writes to + this register have no effect. + + .. wavedrom:: + :caption: UART_EV_STATUS + + { + "reg": [ + {"name": "tx", "bits": 1}, + {"name": "rx", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+---------------------------+ +| Field | Name | Description | ++=======+======+===========================+ +| [0] | TX | Level of the ``tx`` event | ++-------+------+---------------------------+ +| [1] | RX | Level of the ``rx`` event | ++-------+------+---------------------------+ + +UART_EV_PENDING +^^^^^^^^^^^^^^^ + +`Address: 0xf0008800 + 0x10 = 0xf0008810` + + When a rx event occurs, the corresponding bit will be set in this register. To + clear the Event, set the corresponding bit in this register. + + .. wavedrom:: + :caption: UART_EV_PENDING + + { + "reg": [ + {"name": "tx", "bits": 1}, + {"name": "rx", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+------------------------------------------------------------------------------+ +| Field | Name | Description | ++=======+======+==============================================================================+ +| [0] | TX | `1` if a `tx` event occurred. This Event is triggered on a **falling** edge. | ++-------+------+------------------------------------------------------------------------------+ +| [1] | RX | `1` if a `rx` event occurred. This Event is triggered on a **falling** edge. | ++-------+------+------------------------------------------------------------------------------+ + +UART_EV_ENABLE +^^^^^^^^^^^^^^ + +`Address: 0xf0008800 + 0x14 = 0xf0008814` + + This register enables the corresponding rx events. Write a ``0`` to this + register to disable individual events. + + .. wavedrom:: + :caption: UART_EV_ENABLE + + { + "reg": [ + {"name": "tx", "bits": 1}, + {"name": "rx", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+------------------------------------------+ +| Field | Name | Description | ++=======+======+==========================================+ +| [0] | TX | Write a ``1`` to enable the ``tx`` Event | ++-------+------+------------------------------------------+ +| [1] | RX | Write a ``1`` to enable the ``rx`` Event | ++-------+------+------------------------------------------+ + +UART_TXEMPTY +^^^^^^^^^^^^ + +`Address: 0xf0008800 + 0x18 = 0xf0008818` + + TX FIFO Empty. + + .. wavedrom:: + :caption: UART_TXEMPTY + + { + "reg": [ + {"name": "txempty", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_RXFULL +^^^^^^^^^^^ + +`Address: 0xf0008800 + 0x1c = 0xf000881c` + + RX FIFO Full. + + .. wavedrom:: + :caption: UART_RXFULL + + { + "reg": [ + {"name": "rxfull", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_XOVER_RXTX +^^^^^^^^^^^^^^^ + +`Address: 0xf0008800 + 0x20 = 0xf0008820` + + + .. wavedrom:: + :caption: UART_XOVER_RXTX + + { + "reg": [ + {"name": "xover_rxtx[7:0]", "bits": 8}, + {"bits": 24}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +UART_XOVER_TXFULL +^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008800 + 0x24 = 0xf0008824` + + TX FIFO Full. + + .. wavedrom:: + :caption: UART_XOVER_TXFULL + + { + "reg": [ + {"name": "xover_txfull", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_XOVER_RXEMPTY +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008800 + 0x28 = 0xf0008828` + + RX FIFO Empty. + + .. wavedrom:: + :caption: UART_XOVER_RXEMPTY + + { + "reg": [ + {"name": "xover_rxempty", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_XOVER_EV_STATUS +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008800 + 0x2c = 0xf000882c` + + This register contains the current raw level of the rx event trigger. Writes to + this register have no effect. + + .. wavedrom:: + :caption: UART_XOVER_EV_STATUS + + { + "reg": [ + {"name": "tx", "bits": 1}, + {"name": "rx", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+---------------------------+ +| Field | Name | Description | ++=======+======+===========================+ +| [0] | TX | Level of the ``tx`` event | ++-------+------+---------------------------+ +| [1] | RX | Level of the ``rx`` event | ++-------+------+---------------------------+ + +UART_XOVER_EV_PENDING +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008800 + 0x30 = 0xf0008830` + + When a rx event occurs, the corresponding bit will be set in this register. To + clear the Event, set the corresponding bit in this register. + + .. wavedrom:: + :caption: UART_XOVER_EV_PENDING + + { + "reg": [ + {"name": "tx", "bits": 1}, + {"name": "rx", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+------------------------------------------------------------------------------+ +| Field | Name | Description | ++=======+======+==============================================================================+ +| [0] | TX | `1` if a `tx` event occurred. This Event is triggered on a **falling** edge. | ++-------+------+------------------------------------------------------------------------------+ +| [1] | RX | `1` if a `rx` event occurred. This Event is triggered on a **falling** edge. | ++-------+------+------------------------------------------------------------------------------+ + +UART_XOVER_EV_ENABLE +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008800 + 0x34 = 0xf0008834` + + This register enables the corresponding rx events. Write a ``0`` to this + register to disable individual events. + + .. wavedrom:: + :caption: UART_XOVER_EV_ENABLE + + { + "reg": [ + {"name": "tx", "bits": 1}, + {"name": "rx", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+------------------------------------------+ +| Field | Name | Description | ++=======+======+==========================================+ +| [0] | TX | Write a ``1`` to enable the ``tx`` Event | ++-------+------+------------------------------------------+ +| [1] | RX | Write a ``1`` to enable the ``rx`` Event | ++-------+------+------------------------------------------+ + +UART_XOVER_TXEMPTY +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008800 + 0x38 = 0xf0008838` + + TX FIFO Empty. + + .. wavedrom:: + :caption: UART_XOVER_TXEMPTY + + { + "reg": [ + {"name": "xover_txempty", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_XOVER_RXFULL +^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008800 + 0x3c = 0xf000883c` + + RX FIFO Full. + + .. wavedrom:: + :caption: UART_XOVER_RXFULL + + { + "reg": [ + {"name": "xover_rxfull", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/ddr5_test_board/documentation/writer.rst.txt b/_sources/build/ddr5_test_board/documentation/writer.rst.txt new file mode 100644 index 000000000..6504d2809 --- /dev/null +++ b/_sources/build/ddr5_test_board/documentation/writer.rst.txt @@ -0,0 +1,251 @@ +WRITER +====== + + + +DMA DRAM writer. + +Allows to fill DRAM with a predefined pattern using DMA. + +Pattern +------- + + + Provides access to RAM to store access pattern: `mem_addr` and `mem_data`. + The pattern address space can be limited using the `data_mask`. + + For example, having `mem_adr` filled with `[ 0x04, 0x02, 0x03, ... ]` + and `mem_data` filled with `[ 0xff, 0xaa, 0x55, ... ]` and setting + `data_mask = 0b01`, the pattern [(address, data), ...] written will be: + `[(0x04, 0xff), (0x02, 0xaa), (0x04, 0xff), ...]` (wraps due to masking). + + DRAM memory range that is being accessed can be configured using `mem_mask`. + + To use this module, make sure that `ready` is 1, then write the desired + number of transfers to `count`. Writing to the `start` CSR will initialize + the operation. When the operation is ongoing `ready` will be 0. + + + +Register Listing for WRITER +--------------------------- + ++------------------------------------------------------------------------+----------------------------------------------------+ +| Register | Address | ++========================================================================+====================================================+ +| :ref:`WRITER_START ` | :ref:`0xf0002800 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_READY ` | :ref:`0xf0002804 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_MODULO ` | :ref:`0xf0002808 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_COUNT ` | :ref:`0xf000280c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_DONE ` | :ref:`0xf0002810 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_MEM_MASK ` | :ref:`0xf0002814 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_DATA_MASK ` | :ref:`0xf0002818 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_DATA_DIV ` | :ref:`0xf000281c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_INVERTER_DIVISOR_MASK ` | :ref:`0xf0002820 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_INVERTER_SELECTION_MASK ` | :ref:`0xf0002824 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_LAST_ADDRESS ` | :ref:`0xf0002828 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ + +WRITER_START +^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x0 = 0xf0002800` + + Write to the register starts the transfer (if ready=1) + + .. wavedrom:: + :caption: WRITER_START + + { + "reg": [ + {"name": "start", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +WRITER_READY +^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x4 = 0xf0002804` + + Indicates that the transfer is not ongoing + + .. wavedrom:: + :caption: WRITER_READY + + { + "reg": [ + {"name": "ready", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +WRITER_MODULO +^^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x8 = 0xf0002808` + + When set use modulo to calculate DMA transfers address rather than bit masking + + .. wavedrom:: + :caption: WRITER_MODULO + + { + "reg": [ + {"name": "modulo", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +WRITER_COUNT +^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0xc = 0xf000280c` + + Desired number of DMA transfers + + .. wavedrom:: + :caption: WRITER_COUNT + + { + "reg": [ + {"name": "count[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +WRITER_DONE +^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x10 = 0xf0002810` + + Number of completed DMA transfers + + .. wavedrom:: + :caption: WRITER_DONE + + { + "reg": [ + {"name": "done[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +WRITER_MEM_MASK +^^^^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x14 = 0xf0002814` + + DRAM address mask for DMA transfers + + .. wavedrom:: + :caption: WRITER_MEM_MASK + + { + "reg": [ + {"name": "mem_mask[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +WRITER_DATA_MASK +^^^^^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x18 = 0xf0002818` + + Pattern memory address mask + + .. wavedrom:: + :caption: WRITER_DATA_MASK + + { + "reg": [ + {"name": "data_mask[6:0]", "bits": 7}, + {"bits": 25}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +WRITER_DATA_DIV +^^^^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x1c = 0xf000281c` + + Pattern memory address divisior-1 + + .. wavedrom:: + :caption: WRITER_DATA_DIV + + { + "reg": [ + {"name": "data_div[6:0]", "bits": 7}, + {"bits": 25}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +WRITER_INVERTER_DIVISOR_MASK +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x20 = 0xf0002820` + + Divisor mask for selecting rows for which pattern data gets inverted + + .. wavedrom:: + :caption: WRITER_INVERTER_DIVISOR_MASK + + { + "reg": [ + {"name": "inverter_divisor_mask[4:0]", "bits": 5}, + {"bits": 27}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +WRITER_INVERTER_SELECTION_MASK +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x24 = 0xf0002824` + + Selection mask for selecting rows for which pattern data gets inverted + + .. wavedrom:: + :caption: WRITER_INVERTER_SELECTION_MASK + + { + "reg": [ + {"name": "inverter_selection_mask[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +WRITER_LAST_ADDRESS +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x28 = 0xf0002828` + + Number of completed DMA transfers + + .. wavedrom:: + :caption: WRITER_LAST_ADDRESS + + { + "reg": [ + {"name": "last_address[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/ddr5_tester/documentation/PHYCRG.rst.txt b/_sources/build/ddr5_tester/documentation/PHYCRG.rst.txt new file mode 100644 index 000000000..b7194fb68 --- /dev/null +++ b/_sources/build/ddr5_tester/documentation/PHYCRG.rst.txt @@ -0,0 +1,19 @@ +PHYCRG +====== + +S7CRGPHY +-------- +This module contains 7 series specific clock and reset generation for S7DDR5 PHY. +It adds: + +- BUFMRCE to control multi region PHYs (UDIMMs and/or RDIMMs), +- BUFMRCE/BUFRs reset sequence, +- ISERDES reset sequence correct with Xilinx documentation and design advisories, +- OSERDES reset sequence. + + +DDR5 Tester Clock tree +---------------------- +.. image:: ddr5_tester_CRG.png + + diff --git a/_sources/build/ddr5_tester/documentation/controller_settings.rst.txt b/_sources/build/ddr5_tester/documentation/controller_settings.rst.txt new file mode 100644 index 000000000..cc67b4b83 --- /dev/null +++ b/_sources/build/ddr5_tester/documentation/controller_settings.rst.txt @@ -0,0 +1,34 @@ +CONTROLLER_SETTINGS +=================== + +Allows to change LiteDRAMController behaviour at runtime +-------------------------------------------------------- + + +Register Listing for CONTROLLER_SETTINGS +---------------------------------------- + ++------------------------------------------------------------------+-------------------------------------------------+ +| Register | Address | ++==================================================================+=================================================+ +| :ref:`CONTROLLER_SETTINGS_REFRESH ` | :ref:`0xf0001000 ` | ++------------------------------------------------------------------+-------------------------------------------------+ + +CONTROLLER_SETTINGS_REFRESH +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0001000 + 0x0 = 0xf0001000` + + Enable/disable Refresh commands sending + + .. wavedrom:: + :caption: CONTROLLER_SETTINGS_REFRESH + + { + "reg": [ + {"name": "refresh", "attr": 'reset: 1', "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/ddr5_tester/documentation/ctrl.rst.txt b/_sources/build/ddr5_tester/documentation/ctrl.rst.txt new file mode 100644 index 000000000..8e9663760 --- /dev/null +++ b/_sources/build/ddr5_tester/documentation/ctrl.rst.txt @@ -0,0 +1,78 @@ +CTRL +==== + +Register Listing for CTRL +------------------------- + ++------------------------------------------+-------------------------------------+ +| Register | Address | ++==========================================+=====================================+ +| :ref:`CTRL__RESET ` | :ref:`0xf0005000 ` | ++------------------------------------------+-------------------------------------+ +| :ref:`CTRL_SCRATCH ` | :ref:`0xf0005004 ` | ++------------------------------------------+-------------------------------------+ +| :ref:`CTRL_BUS_ERRORS ` | :ref:`0xf0005008 ` | ++------------------------------------------+-------------------------------------+ + +CTRL__RESET +^^^^^^^^^^^ + +`Address: 0xf0005000 + 0x0 = 0xf0005000` + + + .. wavedrom:: + :caption: CTRL__RESET + + { + "reg": [ + {"name": "soc_rst", "type": 4, "bits": 1}, + {"name": "cpu_rst", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+---------+------------------------------------------------------------------------+ +| Field | Name | Description | ++=======+=========+========================================================================+ +| [0] | SOC_RST | Write `1` to this register to reset the full SoC (Pulse Reset) | ++-------+---------+------------------------------------------------------------------------+ +| [1] | CPU_RST | Write `1` to this register to reset the CPU(s) of the SoC (Hold Reset) | ++-------+---------+------------------------------------------------------------------------+ + +CTRL_SCRATCH +^^^^^^^^^^^^ + +`Address: 0xf0005000 + 0x4 = 0xf0005004` + + Use this register as a scratch space to verify that software read/write accesses + to the Wishbone/CSR bus are working correctly. The initial reset value of + 0x1234578 can be used to verify endianness. + + .. wavedrom:: + :caption: CTRL_SCRATCH + + { + "reg": [ + {"name": "scratch[31:0]", "attr": 'reset: 305419896', "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +CTRL_BUS_ERRORS +^^^^^^^^^^^^^^^ + +`Address: 0xf0005000 + 0x8 = 0xf0005008` + + Total number of Wishbone bus errors (timeouts) since start. + + .. wavedrom:: + :caption: CTRL_BUS_ERRORS + + { + "reg": [ + {"name": "bus_errors[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/ddr5_tester/documentation/ddrctrl.rst.txt b/_sources/build/ddr5_tester/documentation/ddrctrl.rst.txt new file mode 100644 index 000000000..59563d8b1 --- /dev/null +++ b/_sources/build/ddr5_tester/documentation/ddrctrl.rst.txt @@ -0,0 +1,48 @@ +DDRCTRL +======= + +Register Listing for DDRCTRL +---------------------------- + ++------------------------------------------------+----------------------------------------+ +| Register | Address | ++================================================+========================================+ +| :ref:`DDRCTRL_INIT_DONE ` | :ref:`0xf0001800 ` | ++------------------------------------------------+----------------------------------------+ +| :ref:`DDRCTRL_INIT_ERROR ` | :ref:`0xf0001804 ` | ++------------------------------------------------+----------------------------------------+ + +DDRCTRL_INIT_DONE +^^^^^^^^^^^^^^^^^ + +`Address: 0xf0001800 + 0x0 = 0xf0001800` + + + .. wavedrom:: + :caption: DDRCTRL_INIT_DONE + + { + "reg": [ + {"name": "init_done", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRCTRL_INIT_ERROR +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0001800 + 0x4 = 0xf0001804` + + + .. wavedrom:: + :caption: DDRCTRL_INIT_ERROR + + { + "reg": [ + {"name": "init_error", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/ddr5_tester/documentation/ddrphy.rst.txt b/_sources/build/ddr5_tester/documentation/ddrphy.rst.txt new file mode 100644 index 000000000..a03516898 --- /dev/null +++ b/_sources/build/ddr5_tester/documentation/ddrphy.rst.txt @@ -0,0 +1,1786 @@ +DDRPHY +====== + +Register Listing for DDRPHY +--------------------------- + ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| Register | Address | ++====================================================================================+==========================================================+ +| :ref:`DDRPHY_CSRMODULE_ENABLE_FIFOS ` | :ref:`0xf0000800 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_RST ` | :ref:`0xf0000804 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_RDIMM_MODE ` | :ref:`0xf0000808 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_RDPHASE ` | :ref:`0xf000080c ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_WRPHASE ` | :ref:`0xf0000810 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_ALERT ` | :ref:`0xf0000814 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_ALERT_REDUCE ` | :ref:`0xf0000818 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_SAMPLE_ALERT ` | :ref:`0xf000081c ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_RESET_ALERT ` | :ref:`0xf0000820 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_CKDLY_RST ` | :ref:`0xf0000824 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_CKDLY_INC ` | :ref:`0xf0000828 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_A_PREAMBLE ` | :ref:`0xf000082c ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_A_WLEVEL_EN ` | :ref:`0xf0000830 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_A_PAR_ENABLE ` | :ref:`0xf0000834 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_A_PAR_VALUE ` | :ref:`0xf0000838 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_A_DISCARD_RD_FIFO ` | :ref:`0xf000083c ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_A_DLY_SEL ` | :ref:`0xf0000840 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_A_DQ_DQS_RATIO ` | :ref:`0xf0000844 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_A_CK_RDLY_INC ` | :ref:`0xf0000848 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_A_CK_RDLY_RST ` | :ref:`0xf000084c ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_A_CK_RDDLY ` | :ref:`0xf0000850 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_A_CK_RDDLY_PREAMBLE ` | :ref:`0xf0000854 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_A_CK_WDLY_INC ` | :ref:`0xf0000858 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_A_CK_WDLY_RST ` | :ref:`0xf000085c ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_A_CK_WDLY_DQS ` | :ref:`0xf0000860 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_A_CK_WDDLY_INC ` | :ref:`0xf0000864 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_A_CK_WDDLY_RST ` | :ref:`0xf0000868 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_A_CK_WDLY_DQ ` | :ref:`0xf000086c ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_A_DQ_DLY_SEL ` | :ref:`0xf0000870 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_A_CSDLY_RST ` | :ref:`0xf0000874 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_A_CSDLY_INC ` | :ref:`0xf0000878 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_A_CADLY_RST ` | :ref:`0xf000087c ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_A_CADLY_INC ` | :ref:`0xf0000880 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_A_PARDLY_RST ` | :ref:`0xf0000884 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_A_PARDLY_INC ` | :ref:`0xf0000888 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_A_CSDLY ` | :ref:`0xf000088c ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_A_CADLY ` | :ref:`0xf0000890 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_A_RDLY_DQ_RST ` | :ref:`0xf0000894 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_A_RDLY_DQ_INC ` | :ref:`0xf0000898 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_A_RDLY_DQS_RST ` | :ref:`0xf000089c ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_A_RDLY_DQS_INC ` | :ref:`0xf00008a0 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_A_RDLY_DQS ` | :ref:`0xf00008a4 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_A_RDLY_DQ ` | :ref:`0xf00008a8 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_A_WDLY_DQ_RST ` | :ref:`0xf00008ac ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_A_WDLY_DQ_INC ` | :ref:`0xf00008b0 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_A_WDLY_DM_RST ` | :ref:`0xf00008b4 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_A_WDLY_DM_INC ` | :ref:`0xf00008b8 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_A_WDLY_DQS_RST ` | :ref:`0xf00008bc ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_A_WDLY_DQS_INC ` | :ref:`0xf00008c0 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_A_WDLY_DQS ` | :ref:`0xf00008c4 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_A_WDLY_DQ ` | :ref:`0xf00008c8 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_A_WDLY_DM ` | :ref:`0xf00008cc ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_B_PREAMBLE ` | :ref:`0xf00008d0 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_B_WLEVEL_EN ` | :ref:`0xf00008d4 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_B_PAR_ENABLE ` | :ref:`0xf00008d8 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_B_PAR_VALUE ` | :ref:`0xf00008dc ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_B_DISCARD_RD_FIFO ` | :ref:`0xf00008e0 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_B_DLY_SEL ` | :ref:`0xf00008e4 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_B_DQ_DQS_RATIO ` | :ref:`0xf00008e8 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_B_CK_RDLY_INC ` | :ref:`0xf00008ec ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_B_CK_RDLY_RST ` | :ref:`0xf00008f0 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_B_CK_RDDLY ` | :ref:`0xf00008f4 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_B_CK_RDDLY_PREAMBLE ` | :ref:`0xf00008f8 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_B_CK_WDLY_INC ` | :ref:`0xf00008fc ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_B_CK_WDLY_RST ` | :ref:`0xf0000900 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_B_CK_WDLY_DQS ` | :ref:`0xf0000904 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_B_CK_WDDLY_INC ` | :ref:`0xf0000908 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_B_CK_WDDLY_RST ` | :ref:`0xf000090c ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_B_CK_WDLY_DQ ` | :ref:`0xf0000910 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_B_DQ_DLY_SEL ` | :ref:`0xf0000914 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_B_CSDLY_RST ` | :ref:`0xf0000918 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_B_CSDLY_INC ` | :ref:`0xf000091c ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_B_CADLY_RST ` | :ref:`0xf0000920 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_B_CADLY_INC ` | :ref:`0xf0000924 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_B_PARDLY_RST ` | :ref:`0xf0000928 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_B_PARDLY_INC ` | :ref:`0xf000092c ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_B_CSDLY ` | :ref:`0xf0000930 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_B_CADLY ` | :ref:`0xf0000934 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_B_RDLY_DQ_RST ` | :ref:`0xf0000938 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_B_RDLY_DQ_INC ` | :ref:`0xf000093c ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_B_RDLY_DQS_RST ` | :ref:`0xf0000940 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_B_RDLY_DQS_INC ` | :ref:`0xf0000944 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_B_RDLY_DQS ` | :ref:`0xf0000948 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_B_RDLY_DQ ` | :ref:`0xf000094c ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_B_WDLY_DQ_RST ` | :ref:`0xf0000950 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_B_WDLY_DQ_INC ` | :ref:`0xf0000954 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_B_WDLY_DM_RST ` | :ref:`0xf0000958 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_B_WDLY_DM_INC ` | :ref:`0xf000095c ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_B_WDLY_DQS_RST ` | :ref:`0xf0000960 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_B_WDLY_DQS_INC ` | :ref:`0xf0000964 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_B_WDLY_DQS ` | :ref:`0xf0000968 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_B_WDLY_DQ ` | :ref:`0xf000096c ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ +| :ref:`DDRPHY_CSRMODULE_B_WDLY_DM ` | :ref:`0xf0000970 ` | ++------------------------------------------------------------------------------------+----------------------------------------------------------+ + +DDRPHY_CSRMODULE_ENABLE_FIFOS +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x0 = 0xf0000800` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_ENABLE_FIFOS + + { + "reg": [ + {"name": "csrmodule_enable_fifos", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_RST +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x4 = 0xf0000804` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_RST + + { + "reg": [ + {"name": "csrmodule_rst", "attr": 'reset: 1', "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_RDIMM_MODE +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x8 = 0xf0000808` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_RDIMM_MODE + + { + "reg": [ + {"name": "csrmodule_rdimm_mode", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_RDPHASE +^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xc = 0xf000080c` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_RDPHASE + + { + "reg": [ + {"name": "csrmodule_rdphase[1:0]", "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_WRPHASE +^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x10 = 0xf0000810` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_WRPHASE + + { + "reg": [ + {"name": "csrmodule_wrphase[1:0]", "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_ALERT +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x14 = 0xf0000814` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_ALERT + + { + "reg": [ + {"name": "csrmodule_alert", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_ALERT_REDUCE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x18 = 0xf0000818` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_ALERT_REDUCE + + { + "reg": [ + {"name": "initial_state", "bits": 1}, + {"name": "operation", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+---------------+------------------------------+ +| Field | Name | Description | ++=======+===============+==============================+ +| [0] | INITIAL_STATE | Initial value of all bits | ++-------+---------------+------------------------------+ +| [1] | OPERATION | 0 - `or` (default), 1 -`and` | ++-------+---------------+------------------------------+ + +DDRPHY_CSRMODULE_SAMPLE_ALERT +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x1c = 0xf000081c` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_SAMPLE_ALERT + + { + "reg": [ + {"name": "csrmodule_sample_alert", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_RESET_ALERT +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x20 = 0xf0000820` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_RESET_ALERT + + { + "reg": [ + {"name": "csrmodule_reset_alert", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_CKDLY_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x24 = 0xf0000824` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_CKDLY_RST + + { + "reg": [ + {"name": "csrmodule_ckdly_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_CKDLY_INC +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x28 = 0xf0000828` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_CKDLY_INC + + { + "reg": [ + {"name": "csrmodule_ckdly_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_A_PREAMBLE +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x2c = 0xf000082c` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_A_PREAMBLE + + { + "reg": [ + {"name": "csrmodule_a_preamble[3:0]", "bits": 4}, + {"bits": 28}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_A_WLEVEL_EN +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x30 = 0xf0000830` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_A_WLEVEL_EN + + { + "reg": [ + {"name": "csrmodule_a_wlevel_en", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_A_PAR_ENABLE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x34 = 0xf0000834` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_A_PAR_ENABLE + + { + "reg": [ + {"name": "csrmodule_a_par_enable", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_A_PAR_VALUE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x38 = 0xf0000838` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_A_PAR_VALUE + + { + "reg": [ + {"name": "csrmodule_a_par_value", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_A_DISCARD_RD_FIFO +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x3c = 0xf000083c` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_A_DISCARD_RD_FIFO + + { + "reg": [ + {"name": "csrmodule_a_discard_rd_fifo", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_A_DLY_SEL +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x40 = 0xf0000840` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_A_DLY_SEL + + { + "reg": [ + {"name": "csrmodule_a_dly_sel[13:0]", "bits": 14}, + {"bits": 18}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DDRPHY_CSRMODULE_A_DQ_DQS_RATIO +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x44 = 0xf0000844` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_A_DQ_DQS_RATIO + + { + "reg": [ + {"name": "csrmodule_a_dq_dqs_ratio[3:0]", "attr": 'reset: 4', "bits": 4}, + {"bits": 28}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_A_CK_RDLY_INC +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x48 = 0xf0000848` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_A_CK_RDLY_INC + + { + "reg": [ + {"name": "csrmodule_a_ck_rdly_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_A_CK_RDLY_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x4c = 0xf000084c` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_A_CK_RDLY_RST + + { + "reg": [ + {"name": "csrmodule_a_ck_rdly_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_A_CK_RDDLY +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x50 = 0xf0000850` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_A_CK_RDDLY + + { + "reg": [ + {"name": "csrmodule_a_ck_rddly[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DDRPHY_CSRMODULE_A_CK_RDDLY_PREAMBLE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x54 = 0xf0000854` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_A_CK_RDDLY_PREAMBLE + + { + "reg": [ + {"name": "csrmodule_a_ck_rddly_preamble[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DDRPHY_CSRMODULE_A_CK_WDLY_INC +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x58 = 0xf0000858` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_A_CK_WDLY_INC + + { + "reg": [ + {"name": "csrmodule_a_ck_wdly_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_A_CK_WDLY_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x5c = 0xf000085c` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_A_CK_WDLY_RST + + { + "reg": [ + {"name": "csrmodule_a_ck_wdly_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_A_CK_WDLY_DQS +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x60 = 0xf0000860` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_A_CK_WDLY_DQS + + { + "reg": [ + {"name": "csrmodule_a_ck_wdly_dqs[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DDRPHY_CSRMODULE_A_CK_WDDLY_INC +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x64 = 0xf0000864` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_A_CK_WDDLY_INC + + { + "reg": [ + {"name": "csrmodule_a_ck_wddly_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_A_CK_WDDLY_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x68 = 0xf0000868` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_A_CK_WDDLY_RST + + { + "reg": [ + {"name": "csrmodule_a_ck_wddly_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_A_CK_WDLY_DQ +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x6c = 0xf000086c` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_A_CK_WDLY_DQ + + { + "reg": [ + {"name": "csrmodule_a_ck_wdly_dq[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DDRPHY_CSRMODULE_A_DQ_DLY_SEL +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x70 = 0xf0000870` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_A_DQ_DLY_SEL + + { + "reg": [ + {"name": "csrmodule_a_dq_dly_sel[3:0]", "bits": 4}, + {"bits": 28}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_A_CSDLY_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x74 = 0xf0000874` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_A_CSDLY_RST + + { + "reg": [ + {"name": "csrmodule_a_csdly_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_A_CSDLY_INC +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x78 = 0xf0000878` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_A_CSDLY_INC + + { + "reg": [ + {"name": "csrmodule_a_csdly_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_A_CADLY_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x7c = 0xf000087c` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_A_CADLY_RST + + { + "reg": [ + {"name": "csrmodule_a_cadly_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_A_CADLY_INC +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x80 = 0xf0000880` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_A_CADLY_INC + + { + "reg": [ + {"name": "csrmodule_a_cadly_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_A_PARDLY_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x84 = 0xf0000884` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_A_PARDLY_RST + + { + "reg": [ + {"name": "csrmodule_a_pardly_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_A_PARDLY_INC +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x88 = 0xf0000888` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_A_PARDLY_INC + + { + "reg": [ + {"name": "csrmodule_a_pardly_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_A_CSDLY +^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x8c = 0xf000088c` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_A_CSDLY + + { + "reg": [ + {"name": "csrmodule_a_csdly[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DDRPHY_CSRMODULE_A_CADLY +^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x90 = 0xf0000890` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_A_CADLY + + { + "reg": [ + {"name": "csrmodule_a_cadly[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DDRPHY_CSRMODULE_A_RDLY_DQ_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x94 = 0xf0000894` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_A_RDLY_DQ_RST + + { + "reg": [ + {"name": "csrmodule_a_rdly_dq_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_A_RDLY_DQ_INC +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x98 = 0xf0000898` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_A_RDLY_DQ_INC + + { + "reg": [ + {"name": "csrmodule_a_rdly_dq_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_A_RDLY_DQS_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x9c = 0xf000089c` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_A_RDLY_DQS_RST + + { + "reg": [ + {"name": "csrmodule_a_rdly_dqs_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_A_RDLY_DQS_INC +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xa0 = 0xf00008a0` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_A_RDLY_DQS_INC + + { + "reg": [ + {"name": "csrmodule_a_rdly_dqs_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_A_RDLY_DQS +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xa4 = 0xf00008a4` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_A_RDLY_DQS + + { + "reg": [ + {"name": "csrmodule_a_rdly_dqs[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DDRPHY_CSRMODULE_A_RDLY_DQ +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xa8 = 0xf00008a8` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_A_RDLY_DQ + + { + "reg": [ + {"name": "csrmodule_a_rdly_dq[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DDRPHY_CSRMODULE_A_WDLY_DQ_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xac = 0xf00008ac` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_A_WDLY_DQ_RST + + { + "reg": [ + {"name": "csrmodule_a_wdly_dq_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_A_WDLY_DQ_INC +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xb0 = 0xf00008b0` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_A_WDLY_DQ_INC + + { + "reg": [ + {"name": "csrmodule_a_wdly_dq_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_A_WDLY_DM_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xb4 = 0xf00008b4` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_A_WDLY_DM_RST + + { + "reg": [ + {"name": "csrmodule_a_wdly_dm_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_A_WDLY_DM_INC +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xb8 = 0xf00008b8` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_A_WDLY_DM_INC + + { + "reg": [ + {"name": "csrmodule_a_wdly_dm_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_A_WDLY_DQS_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xbc = 0xf00008bc` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_A_WDLY_DQS_RST + + { + "reg": [ + {"name": "csrmodule_a_wdly_dqs_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_A_WDLY_DQS_INC +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xc0 = 0xf00008c0` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_A_WDLY_DQS_INC + + { + "reg": [ + {"name": "csrmodule_a_wdly_dqs_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_A_WDLY_DQS +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xc4 = 0xf00008c4` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_A_WDLY_DQS + + { + "reg": [ + {"name": "csrmodule_a_wdly_dqs[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DDRPHY_CSRMODULE_A_WDLY_DQ +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xc8 = 0xf00008c8` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_A_WDLY_DQ + + { + "reg": [ + {"name": "csrmodule_a_wdly_dq[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DDRPHY_CSRMODULE_A_WDLY_DM +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xcc = 0xf00008cc` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_A_WDLY_DM + + { + "reg": [ + {"name": "csrmodule_a_wdly_dm[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DDRPHY_CSRMODULE_B_PREAMBLE +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xd0 = 0xf00008d0` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_B_PREAMBLE + + { + "reg": [ + {"name": "csrmodule_b_preamble[3:0]", "bits": 4}, + {"bits": 28}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_B_WLEVEL_EN +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xd4 = 0xf00008d4` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_B_WLEVEL_EN + + { + "reg": [ + {"name": "csrmodule_b_wlevel_en", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_B_PAR_ENABLE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xd8 = 0xf00008d8` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_B_PAR_ENABLE + + { + "reg": [ + {"name": "csrmodule_b_par_enable", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_B_PAR_VALUE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xdc = 0xf00008dc` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_B_PAR_VALUE + + { + "reg": [ + {"name": "csrmodule_b_par_value", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_B_DISCARD_RD_FIFO +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xe0 = 0xf00008e0` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_B_DISCARD_RD_FIFO + + { + "reg": [ + {"name": "csrmodule_b_discard_rd_fifo", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_B_DLY_SEL +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xe4 = 0xf00008e4` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_B_DLY_SEL + + { + "reg": [ + {"name": "csrmodule_b_dly_sel[13:0]", "bits": 14}, + {"bits": 18}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DDRPHY_CSRMODULE_B_DQ_DQS_RATIO +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xe8 = 0xf00008e8` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_B_DQ_DQS_RATIO + + { + "reg": [ + {"name": "csrmodule_b_dq_dqs_ratio[3:0]", "attr": 'reset: 4', "bits": 4}, + {"bits": 28}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_B_CK_RDLY_INC +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xec = 0xf00008ec` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_B_CK_RDLY_INC + + { + "reg": [ + {"name": "csrmodule_b_ck_rdly_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_B_CK_RDLY_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xf0 = 0xf00008f0` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_B_CK_RDLY_RST + + { + "reg": [ + {"name": "csrmodule_b_ck_rdly_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_B_CK_RDDLY +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xf4 = 0xf00008f4` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_B_CK_RDDLY + + { + "reg": [ + {"name": "csrmodule_b_ck_rddly[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DDRPHY_CSRMODULE_B_CK_RDDLY_PREAMBLE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xf8 = 0xf00008f8` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_B_CK_RDDLY_PREAMBLE + + { + "reg": [ + {"name": "csrmodule_b_ck_rddly_preamble[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DDRPHY_CSRMODULE_B_CK_WDLY_INC +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xfc = 0xf00008fc` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_B_CK_WDLY_INC + + { + "reg": [ + {"name": "csrmodule_b_ck_wdly_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_B_CK_WDLY_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x100 = 0xf0000900` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_B_CK_WDLY_RST + + { + "reg": [ + {"name": "csrmodule_b_ck_wdly_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_B_CK_WDLY_DQS +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x104 = 0xf0000904` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_B_CK_WDLY_DQS + + { + "reg": [ + {"name": "csrmodule_b_ck_wdly_dqs[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DDRPHY_CSRMODULE_B_CK_WDDLY_INC +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x108 = 0xf0000908` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_B_CK_WDDLY_INC + + { + "reg": [ + {"name": "csrmodule_b_ck_wddly_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_B_CK_WDDLY_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x10c = 0xf000090c` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_B_CK_WDDLY_RST + + { + "reg": [ + {"name": "csrmodule_b_ck_wddly_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_B_CK_WDLY_DQ +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x110 = 0xf0000910` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_B_CK_WDLY_DQ + + { + "reg": [ + {"name": "csrmodule_b_ck_wdly_dq[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DDRPHY_CSRMODULE_B_DQ_DLY_SEL +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x114 = 0xf0000914` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_B_DQ_DLY_SEL + + { + "reg": [ + {"name": "csrmodule_b_dq_dly_sel[3:0]", "bits": 4}, + {"bits": 28}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_B_CSDLY_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x118 = 0xf0000918` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_B_CSDLY_RST + + { + "reg": [ + {"name": "csrmodule_b_csdly_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_B_CSDLY_INC +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x11c = 0xf000091c` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_B_CSDLY_INC + + { + "reg": [ + {"name": "csrmodule_b_csdly_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_B_CADLY_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x120 = 0xf0000920` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_B_CADLY_RST + + { + "reg": [ + {"name": "csrmodule_b_cadly_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_B_CADLY_INC +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x124 = 0xf0000924` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_B_CADLY_INC + + { + "reg": [ + {"name": "csrmodule_b_cadly_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_B_PARDLY_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x128 = 0xf0000928` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_B_PARDLY_RST + + { + "reg": [ + {"name": "csrmodule_b_pardly_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_B_PARDLY_INC +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x12c = 0xf000092c` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_B_PARDLY_INC + + { + "reg": [ + {"name": "csrmodule_b_pardly_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_B_CSDLY +^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x130 = 0xf0000930` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_B_CSDLY + + { + "reg": [ + {"name": "csrmodule_b_csdly[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DDRPHY_CSRMODULE_B_CADLY +^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x134 = 0xf0000934` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_B_CADLY + + { + "reg": [ + {"name": "csrmodule_b_cadly[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DDRPHY_CSRMODULE_B_RDLY_DQ_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x138 = 0xf0000938` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_B_RDLY_DQ_RST + + { + "reg": [ + {"name": "csrmodule_b_rdly_dq_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_B_RDLY_DQ_INC +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x13c = 0xf000093c` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_B_RDLY_DQ_INC + + { + "reg": [ + {"name": "csrmodule_b_rdly_dq_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_B_RDLY_DQS_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x140 = 0xf0000940` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_B_RDLY_DQS_RST + + { + "reg": [ + {"name": "csrmodule_b_rdly_dqs_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_B_RDLY_DQS_INC +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x144 = 0xf0000944` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_B_RDLY_DQS_INC + + { + "reg": [ + {"name": "csrmodule_b_rdly_dqs_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_B_RDLY_DQS +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x148 = 0xf0000948` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_B_RDLY_DQS + + { + "reg": [ + {"name": "csrmodule_b_rdly_dqs[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DDRPHY_CSRMODULE_B_RDLY_DQ +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x14c = 0xf000094c` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_B_RDLY_DQ + + { + "reg": [ + {"name": "csrmodule_b_rdly_dq[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DDRPHY_CSRMODULE_B_WDLY_DQ_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x150 = 0xf0000950` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_B_WDLY_DQ_RST + + { + "reg": [ + {"name": "csrmodule_b_wdly_dq_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_B_WDLY_DQ_INC +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x154 = 0xf0000954` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_B_WDLY_DQ_INC + + { + "reg": [ + {"name": "csrmodule_b_wdly_dq_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_B_WDLY_DM_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x158 = 0xf0000958` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_B_WDLY_DM_RST + + { + "reg": [ + {"name": "csrmodule_b_wdly_dm_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_B_WDLY_DM_INC +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x15c = 0xf000095c` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_B_WDLY_DM_INC + + { + "reg": [ + {"name": "csrmodule_b_wdly_dm_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_B_WDLY_DQS_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x160 = 0xf0000960` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_B_WDLY_DQS_RST + + { + "reg": [ + {"name": "csrmodule_b_wdly_dqs_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_B_WDLY_DQS_INC +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x164 = 0xf0000964` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_B_WDLY_DQS_INC + + { + "reg": [ + {"name": "csrmodule_b_wdly_dqs_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CSRMODULE_B_WDLY_DQS +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x168 = 0xf0000968` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_B_WDLY_DQS + + { + "reg": [ + {"name": "csrmodule_b_wdly_dqs[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DDRPHY_CSRMODULE_B_WDLY_DQ +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x16c = 0xf000096c` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_B_WDLY_DQ + + { + "reg": [ + {"name": "csrmodule_b_wdly_dq[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DDRPHY_CSRMODULE_B_WDLY_DM +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x170 = 0xf0000970` + + + .. wavedrom:: + :caption: DDRPHY_CSRMODULE_B_WDLY_DM + + { + "reg": [ + {"name": "csrmodule_b_wdly_dm[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/ddr5_tester/documentation/dfi_switch.rst.txt b/_sources/build/ddr5_tester/documentation/dfi_switch.rst.txt new file mode 100644 index 000000000..718d8cc34 --- /dev/null +++ b/_sources/build/ddr5_tester/documentation/dfi_switch.rst.txt @@ -0,0 +1,71 @@ +DFI_SWITCH +========== + +Register Listing for DFI_SWITCH +------------------------------- + ++--------------------------------------------------------------+-----------------------------------------------+ +| Register | Address | ++==============================================================+===============================================+ +| :ref:`DFI_SWITCH_REFRESH_COUNT ` | :ref:`0xf0003800 ` | ++--------------------------------------------------------------+-----------------------------------------------+ +| :ref:`DFI_SWITCH_AT_REFRESH ` | :ref:`0xf0003804 ` | ++--------------------------------------------------------------+-----------------------------------------------+ +| :ref:`DFI_SWITCH_REFRESH_UPDATE ` | :ref:`0xf0003808 ` | ++--------------------------------------------------------------+-----------------------------------------------+ + +DFI_SWITCH_REFRESH_COUNT +^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003800 + 0x0 = 0xf0003800` + + Count of all refresh commands issued (both by Memory Controller and Payload + Executor). Value is latched from internal counter on mode trasition: MC -> PE or + by writing to the `refresh_update` CSR. + + .. wavedrom:: + :caption: DFI_SWITCH_REFRESH_COUNT + + { + "reg": [ + {"name": "refresh_count[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DFI_SWITCH_AT_REFRESH +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003800 + 0x4 = 0xf0003804` + + If set to a value different than 0 the mode transition MC -> PE will be peformed + only when the value of this register matches the current refresh commands count. + + .. wavedrom:: + :caption: DFI_SWITCH_AT_REFRESH + + { + "reg": [ + {"name": "at_refresh[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DFI_SWITCH_REFRESH_UPDATE +^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003800 + 0x8 = 0xf0003808` + + Force an update of the `refresh_count` CSR. + + .. wavedrom:: + :caption: DFI_SWITCH_REFRESH_UPDATE + + { + "reg": [ + {"name": "refresh_update", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/ddr5_tester/documentation/ethphy.rst.txt b/_sources/build/ddr5_tester/documentation/ethphy.rst.txt new file mode 100644 index 000000000..29c3d6a1e --- /dev/null +++ b/_sources/build/ddr5_tester/documentation/ethphy.rst.txt @@ -0,0 +1,81 @@ +ETHPHY +====== + +Register Listing for ETHPHY +--------------------------- + ++--------------------------------------------+--------------------------------------+ +| Register | Address | ++============================================+======================================+ +| :ref:`ETHPHY_CRG_RESET ` | :ref:`0xf0005800 ` | ++--------------------------------------------+--------------------------------------+ +| :ref:`ETHPHY_MDIO_W ` | :ref:`0xf0005804 ` | ++--------------------------------------------+--------------------------------------+ +| :ref:`ETHPHY_MDIO_R ` | :ref:`0xf0005808 ` | ++--------------------------------------------+--------------------------------------+ + +ETHPHY_CRG_RESET +^^^^^^^^^^^^^^^^ + +`Address: 0xf0005800 + 0x0 = 0xf0005800` + + + .. wavedrom:: + :caption: ETHPHY_CRG_RESET + + { + "reg": [ + {"name": "crg_reset", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +ETHPHY_MDIO_W +^^^^^^^^^^^^^ + +`Address: 0xf0005800 + 0x4 = 0xf0005804` + + + .. wavedrom:: + :caption: ETHPHY_MDIO_W + + { + "reg": [ + {"name": "mdc", "bits": 1}, + {"name": "oe", "bits": 1}, + {"name": "w", "bits": 1}, + {"bits": 29} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------+ +| Field | Name | Description | ++=======+======+=============+ ++-------+------+-------------+ ++-------+------+-------------+ ++-------+------+-------------+ + +ETHPHY_MDIO_R +^^^^^^^^^^^^^ + +`Address: 0xf0005800 + 0x8 = 0xf0005808` + + + .. wavedrom:: + :caption: ETHPHY_MDIO_R + + { + "reg": [ + {"name": "r", "bits": 1}, + {"bits": 31} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------+ +| Field | Name | Description | ++=======+======+=============+ ++-------+------+-------------+ + diff --git a/_sources/build/ddr5_tester/documentation/i2c.rst.txt b/_sources/build/ddr5_tester/documentation/i2c.rst.txt new file mode 100644 index 000000000..2771d3bc0 --- /dev/null +++ b/_sources/build/ddr5_tester/documentation/i2c.rst.txt @@ -0,0 +1,62 @@ +I2C +=== + +Register Listing for I2C +------------------------ + ++----------------------+---------------------------+ +| Register | Address | ++======================+===========================+ +| :ref:`I2C_W ` | :ref:`0xf0004800 ` | ++----------------------+---------------------------+ +| :ref:`I2C_R ` | :ref:`0xf0004804 ` | ++----------------------+---------------------------+ + +I2C_W +^^^^^ + +`Address: 0xf0004800 + 0x0 = 0xf0004800` + + + .. wavedrom:: + :caption: I2C_W + + { + "reg": [ + {"name": "scl", "attr": '1', "bits": 1}, + {"name": "oe", "bits": 1}, + {"name": "sda", "attr": '1', "bits": 1}, + {"bits": 29} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------+ +| Field | Name | Description | ++=======+======+=============+ ++-------+------+-------------+ ++-------+------+-------------+ ++-------+------+-------------+ + +I2C_R +^^^^^ + +`Address: 0xf0004800 + 0x4 = 0xf0004804` + + + .. wavedrom:: + :caption: I2C_R + + { + "reg": [ + {"name": "sda", "bits": 1}, + {"bits": 31} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------+ +| Field | Name | Description | ++=======+======+=============+ ++-------+------+-------------+ + diff --git a/_sources/build/ddr5_tester/documentation/identifier_mem.rst.txt b/_sources/build/ddr5_tester/documentation/identifier_mem.rst.txt new file mode 100644 index 000000000..59e4df69c --- /dev/null +++ b/_sources/build/ddr5_tester/documentation/identifier_mem.rst.txt @@ -0,0 +1,30 @@ +IDENTIFIER_MEM +============== + +Register Listing for IDENTIFIER_MEM +----------------------------------- + ++----------------------------------------+------------------------------------+ +| Register | Address | ++========================================+====================================+ +| :ref:`IDENTIFIER_MEM ` | :ref:`0xf0006000 ` | ++----------------------------------------+------------------------------------+ + +IDENTIFIER_MEM +^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x0 = 0xf0006000` + + 8 x 109-bit memory + + .. wavedrom:: + :caption: IDENTIFIER_MEM + + { + "reg": [ + {"name": "identifier_mem[7:0]", "bits": 8}, + {"bits": 24}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/ddr5_tester/documentation/index.rst.txt b/_sources/build/ddr5_tester/documentation/index.rst.txt new file mode 100644 index 000000000..6e52d6948 --- /dev/null +++ b/_sources/build/ddr5_tester/documentation/index.rst.txt @@ -0,0 +1,40 @@ +=============================================== +Documentation for Row Hammer Tester DDR5 Tester +=============================================== + + + +Modules +======= + +.. toctree:: + :maxdepth: 1 + + interrupts + PHYCRG + +Register Groups +=============== + +.. toctree:: + :maxdepth: 1 + + leds + ddrphy + controller_settings + ddrctrl + rowhammer + writer + reader + dfi_switch + payload_executor + i2c + ctrl + ethphy + identifier_mem + main + sdram + sdram_checker + sdram_generator + timer0 + uart diff --git a/_sources/build/ddr5_tester/documentation/interrupts.rst.txt b/_sources/build/ddr5_tester/documentation/interrupts.rst.txt new file mode 100644 index 000000000..bfc948fb1 --- /dev/null +++ b/_sources/build/ddr5_tester/documentation/interrupts.rst.txt @@ -0,0 +1,22 @@ +Interrupt Controller +==================== + +This device has an ``EventManager``-based interrupt system. Individual modules +generate `events` which are wired into a central interrupt controller. + +When an interrupt occurs, you should look the interrupt number up in the CPU- +specific interrupt table and then call the relevant module. + +Assigned Interrupts +------------------- + +The following interrupts are assigned on this system: + ++-----------+------------------------+ +| Interrupt | Module | ++===========+========================+ +| 1 | :doc:`TIMER0 ` | ++-----------+------------------------+ +| 0 | :doc:`UART ` | ++-----------+------------------------+ + diff --git a/_sources/build/ddr5_tester/documentation/leds.rst.txt b/_sources/build/ddr5_tester/documentation/leds.rst.txt new file mode 100644 index 000000000..7d5de2ee2 --- /dev/null +++ b/_sources/build/ddr5_tester/documentation/leds.rst.txt @@ -0,0 +1,30 @@ +LEDS +==== + +Register Listing for LEDS +------------------------- + ++----------------------------+------------------------------+ +| Register | Address | ++============================+==============================+ +| :ref:`LEDS_OUT ` | :ref:`0xf0000000 ` | ++----------------------------+------------------------------+ + +LEDS_OUT +^^^^^^^^ + +`Address: 0xf0000000 + 0x0 = 0xf0000000` + + Led Output(s) Control. + + .. wavedrom:: + :caption: LEDS_OUT + + { + "reg": [ + {"name": "out[4:0]", "bits": 5}, + {"bits": 27}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/ddr5_tester/documentation/main.rst.txt b/_sources/build/ddr5_tester/documentation/main.rst.txt new file mode 100644 index 000000000..f8605e6e0 --- /dev/null +++ b/_sources/build/ddr5_tester/documentation/main.rst.txt @@ -0,0 +1,162 @@ +MAIN +==== + +Register Listing for MAIN +------------------------- + ++----------------------------------------------------+------------------------------------------+ +| Register | Address | ++====================================================+==========================================+ +| :ref:`MAIN_A_DQ_REMAPPING3 ` | :ref:`0xf0006800 ` | ++----------------------------------------------------+------------------------------------------+ +| :ref:`MAIN_A_DQ_REMAPPING2 ` | :ref:`0xf0006804 ` | ++----------------------------------------------------+------------------------------------------+ +| :ref:`MAIN_A_DQ_REMAPPING1 ` | :ref:`0xf0006808 ` | ++----------------------------------------------------+------------------------------------------+ +| :ref:`MAIN_A_DQ_REMAPPING0 ` | :ref:`0xf000680c ` | ++----------------------------------------------------+------------------------------------------+ +| :ref:`MAIN_B_DQ_REMAPPING3 ` | :ref:`0xf0006810 ` | ++----------------------------------------------------+------------------------------------------+ +| :ref:`MAIN_B_DQ_REMAPPING2 ` | :ref:`0xf0006814 ` | ++----------------------------------------------------+------------------------------------------+ +| :ref:`MAIN_B_DQ_REMAPPING1 ` | :ref:`0xf0006818 ` | ++----------------------------------------------------+------------------------------------------+ +| :ref:`MAIN_B_DQ_REMAPPING0 ` | :ref:`0xf000681c ` | ++----------------------------------------------------+------------------------------------------+ + +MAIN_A_DQ_REMAPPING3 +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x0 = 0xf0006800` + + Bits 96-127 of `MAIN_A_DQ_REMAPPING`. + + .. wavedrom:: + :caption: MAIN_A_DQ_REMAPPING3 + + { + "reg": [ + {"name": "a_dq_remapping[127:96]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +MAIN_A_DQ_REMAPPING2 +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x4 = 0xf0006804` + + Bits 64-95 of `MAIN_A_DQ_REMAPPING`. + + .. wavedrom:: + :caption: MAIN_A_DQ_REMAPPING2 + + { + "reg": [ + {"name": "a_dq_remapping[95:64]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +MAIN_A_DQ_REMAPPING1 +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x8 = 0xf0006808` + + Bits 32-63 of `MAIN_A_DQ_REMAPPING`. + + .. wavedrom:: + :caption: MAIN_A_DQ_REMAPPING1 + + { + "reg": [ + {"name": "a_dq_remapping[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +MAIN_A_DQ_REMAPPING0 +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xc = 0xf000680c` + + Bits 0-31 of `MAIN_A_DQ_REMAPPING`. + + .. wavedrom:: + :caption: MAIN_A_DQ_REMAPPING0 + + { + "reg": [ + {"name": "a_dq_remapping[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +MAIN_B_DQ_REMAPPING3 +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x10 = 0xf0006810` + + Bits 96-127 of `MAIN_B_DQ_REMAPPING`. + + .. wavedrom:: + :caption: MAIN_B_DQ_REMAPPING3 + + { + "reg": [ + {"name": "b_dq_remapping[127:96]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +MAIN_B_DQ_REMAPPING2 +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x14 = 0xf0006814` + + Bits 64-95 of `MAIN_B_DQ_REMAPPING`. + + .. wavedrom:: + :caption: MAIN_B_DQ_REMAPPING2 + + { + "reg": [ + {"name": "b_dq_remapping[95:64]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +MAIN_B_DQ_REMAPPING1 +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x18 = 0xf0006818` + + Bits 32-63 of `MAIN_B_DQ_REMAPPING`. + + .. wavedrom:: + :caption: MAIN_B_DQ_REMAPPING1 + + { + "reg": [ + {"name": "b_dq_remapping[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +MAIN_B_DQ_REMAPPING0 +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x1c = 0xf000681c` + + Bits 0-31 of `MAIN_B_DQ_REMAPPING`. + + .. wavedrom:: + :caption: MAIN_B_DQ_REMAPPING0 + + { + "reg": [ + {"name": "b_dq_remapping[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/ddr5_tester/documentation/payload_executor.rst.txt b/_sources/build/ddr5_tester/documentation/payload_executor.rst.txt new file mode 100644 index 000000000..96fce0378 --- /dev/null +++ b/_sources/build/ddr5_tester/documentation/payload_executor.rst.txt @@ -0,0 +1,137 @@ +PAYLOAD_EXECUTOR +================ + + + + Executes the DRAM payload from memory + + + **Instruction decoder** + + All instructions are 32-bit. The format of most instructions is the same, + except for the LOOP instruction, which has a constant TIMESLICE of 1. + + NOOP with a TIMESLICE of 0 is a special case which is interpreted as + STOP instruction. When this instruction is encountered execution gets + finished immediately. + + **NOTE:** TIMESLICE is the number of cycles the instruction will take. This + means that instructions other than NOOP that use TIMESLICE=0 are illegal + (although will silently be executed as having TIMESLICE=1). + + **NOTE2:** LOOP instruction will *jump* COUNT times, meaning that the "code" + inside the loop will effectively be executed COUNT+1 times. + + Op codes: + ++------+-------+ ++ Op + Value + ++======+=======+ ++ NOOP | 0b000 + ++------+-------+ ++ LOOP | 0b111 + ++------+-------+ ++ ACT | 0b100 + ++------+-------+ ++ PRE | 0b101 + ++------+-------+ ++ REF | 0b110 + ++------+-------+ ++ ZQC | 0b001 + ++------+-------+ ++ READ | 0b010 + ++------+-------+ + + Instruction format:: + + LSB MSB + dfi: OP_CODE | TIMESLICE | ADDRESS + noop: OP_CODE | TIMESLICE_NOOP + loop: OP_CODE | COUNT | JUMP + stop: | 0 + + Where ADDRESS depends on the DFI command and is one of:: + + LSB MSB + RANK | BANK | COLUMN + RANK | BANK | ROW + + + +Register Listing for PAYLOAD_EXECUTOR +------------------------------------- + ++------------------------------------------------------------------+-------------------------------------------------+ +| Register | Address | ++==================================================================+=================================================+ +| :ref:`PAYLOAD_EXECUTOR_START ` | :ref:`0xf0004000 ` | ++------------------------------------------------------------------+-------------------------------------------------+ +| :ref:`PAYLOAD_EXECUTOR_STATUS ` | :ref:`0xf0004004 ` | ++------------------------------------------------------------------+-------------------------------------------------+ +| :ref:`PAYLOAD_EXECUTOR_READ_COUNT ` | :ref:`0xf0004008 ` | ++------------------------------------------------------------------+-------------------------------------------------+ + +PAYLOAD_EXECUTOR_START +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0004000 + 0x0 = 0xf0004000` + + Writing to this register initializes payload execution + + .. wavedrom:: + :caption: PAYLOAD_EXECUTOR_START + + { + "reg": [ + {"name": "start", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +PAYLOAD_EXECUTOR_STATUS +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0004000 + 0x4 = 0xf0004004` + + Payload executor status register + + .. wavedrom:: + :caption: PAYLOAD_EXECUTOR_STATUS + + { + "reg": [ + {"name": "ready", "bits": 1}, + {"name": "overflow", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+----------+---------------------------------------------------------------------------------+ +| Field | Name | Description | ++=======+==========+=================================================================================+ +| [0] | READY | Indicates that the executor is not running | ++-------+----------+---------------------------------------------------------------------------------+ +| [1] | OVERFLOW | Indicates the scratchpad memory address counter has overflown due to the number | +| | | of READ commands sent during execution | ++-------+----------+---------------------------------------------------------------------------------+ + +PAYLOAD_EXECUTOR_READ_COUNT +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0004000 + 0x8 = 0xf0004008` + + Number of data from READ commands that is stored in the scratchpad memory + + .. wavedrom:: + :caption: PAYLOAD_EXECUTOR_READ_COUNT + + { + "reg": [ + {"name": "read_count[4:0]", "bits": 5}, + {"bits": 27}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/ddr5_tester/documentation/reader.rst.txt b/_sources/build/ddr5_tester/documentation/reader.rst.txt new file mode 100644 index 000000000..116392e53 --- /dev/null +++ b/_sources/build/ddr5_tester/documentation/reader.rst.txt @@ -0,0 +1,652 @@ +READER +====== + + + +DMA DRAM reader. + +Allows to check DRAM contents against a predefined pattern using DMA. + +Pattern +------- + + + Provides access to RAM to store access pattern: `mem_addr` and `mem_data`. + The pattern address space can be limited using the `data_mask`. + + For example, having `mem_adr` filled with `[ 0x04, 0x02, 0x03, ... ]` + and `mem_data` filled with `[ 0xff, 0xaa, 0x55, ... ]` and setting + `data_mask = 0b01`, the pattern [(address, data), ...] written will be: + `[(0x04, 0xff), (0x02, 0xaa), (0x04, 0xff), ...]` (wraps due to masking). + + DRAM memory range that is being accessed can be configured using `mem_mask`. + + To use this module, make sure that `ready` is 1, then write the desired + number of transfers to `count`. Writing to the `start` CSR will initialize + the operation. When the operation is ongoing `ready` will be 0. + + +Reading errors +-------------- + +This module allows to check the locations of errors in the memory. +It scans the configured memory area and compares the values read to +the predefined pattern. If `skip_fifo` is 0, this module will stop +after each error encountered, so that it can be examined. Wait until +the `error_ready` CSR is 1. Then use the CSRs `error_offset`, +`error_data` and `error_expected` to examine the errors in the current +transfer. To continue reading, write 1 to `error_continue` CSR. +Setting `skip_fifo` to 1 will disable this behaviour entirely. + +The final number of errors can be read from `error_count`. +NOTE: This value represents the number of erroneous *DMA transfers*. + +The current progress can be read from the `done` CSR. + + +Register Listing for READER +--------------------------- + ++------------------------------------------------------------------------+----------------------------------------------------+ +| Register | Address | ++========================================================================+====================================================+ +| :ref:`READER_START ` | :ref:`0xf0003000 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_READY ` | :ref:`0xf0003004 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_MODULO ` | :ref:`0xf0003008 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_COUNT ` | :ref:`0xf000300c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_DONE ` | :ref:`0xf0003010 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_MEM_MASK ` | :ref:`0xf0003014 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_DATA_MASK ` | :ref:`0xf0003018 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_DATA_DIV ` | :ref:`0xf000301c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_INVERTER_DIVISOR_MASK ` | :ref:`0xf0003020 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_INVERTER_SELECTION_MASK ` | :ref:`0xf0003024 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_COUNT ` | :ref:`0xf0003028 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_SKIP_FIFO ` | :ref:`0xf000302c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_OFFSET ` | :ref:`0xf0003030 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA7 ` | :ref:`0xf0003034 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA6 ` | :ref:`0xf0003038 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA5 ` | :ref:`0xf000303c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA4 ` | :ref:`0xf0003040 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA3 ` | :ref:`0xf0003044 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA2 ` | :ref:`0xf0003048 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA1 ` | :ref:`0xf000304c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA0 ` | :ref:`0xf0003050 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED7 ` | :ref:`0xf0003054 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED6 ` | :ref:`0xf0003058 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED5 ` | :ref:`0xf000305c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED4 ` | :ref:`0xf0003060 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED3 ` | :ref:`0xf0003064 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED2 ` | :ref:`0xf0003068 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED1 ` | :ref:`0xf000306c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED0 ` | :ref:`0xf0003070 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_READY ` | :ref:`0xf0003074 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_CONTINUE ` | :ref:`0xf0003078 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ + +READER_START +^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x0 = 0xf0003000` + + Write to the register starts the transfer (if ready=1) + + .. wavedrom:: + :caption: READER_START + + { + "reg": [ + {"name": "start", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_READY +^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x4 = 0xf0003004` + + Indicates that the transfer is not ongoing + + .. wavedrom:: + :caption: READER_READY + + { + "reg": [ + {"name": "ready", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_MODULO +^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x8 = 0xf0003008` + + When set use modulo to calculate DMA transfers address rather than bit masking + + .. wavedrom:: + :caption: READER_MODULO + + { + "reg": [ + {"name": "modulo", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_COUNT +^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0xc = 0xf000300c` + + Desired number of DMA transfers + + .. wavedrom:: + :caption: READER_COUNT + + { + "reg": [ + {"name": "count[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_DONE +^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x10 = 0xf0003010` + + Number of completed DMA transfers + + .. wavedrom:: + :caption: READER_DONE + + { + "reg": [ + {"name": "done[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_MEM_MASK +^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x14 = 0xf0003014` + + DRAM address mask for DMA transfers + + .. wavedrom:: + :caption: READER_MEM_MASK + + { + "reg": [ + {"name": "mem_mask[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_DATA_MASK +^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x18 = 0xf0003018` + + Pattern memory address mask + + .. wavedrom:: + :caption: READER_DATA_MASK + + { + "reg": [ + {"name": "data_mask[4:0]", "bits": 5}, + {"bits": 27}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_DATA_DIV +^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x1c = 0xf000301c` + + Pattern memory address divisior-1 + + .. wavedrom:: + :caption: READER_DATA_DIV + + { + "reg": [ + {"name": "data_div[4:0]", "bits": 5}, + {"bits": 27}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_INVERTER_DIVISOR_MASK +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x20 = 0xf0003020` + + Divisor mask for selecting rows for which pattern data gets inverted + + .. wavedrom:: + :caption: READER_INVERTER_DIVISOR_MASK + + { + "reg": [ + {"name": "inverter_divisor_mask[4:0]", "bits": 5}, + {"bits": 27}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_INVERTER_SELECTION_MASK +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x24 = 0xf0003024` + + Selection mask for selecting rows for which pattern data gets inverted + + .. wavedrom:: + :caption: READER_INVERTER_SELECTION_MASK + + { + "reg": [ + {"name": "inverter_selection_mask[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_COUNT +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x28 = 0xf0003028` + + Number of errors detected + + .. wavedrom:: + :caption: READER_ERROR_COUNT + + { + "reg": [ + {"name": "error_count[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_SKIP_FIFO +^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x2c = 0xf000302c` + + Skip waiting for user to read the errors FIFO + + .. wavedrom:: + :caption: READER_SKIP_FIFO + + { + "reg": [ + {"name": "skip_fifo", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_ERROR_OFFSET +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x30 = 0xf0003030` + + Current offset of the error + + .. wavedrom:: + :caption: READER_ERROR_OFFSET + + { + "reg": [ + {"name": "error_offset[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA7 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x34 = 0xf0003034` + + Bits 224-255 of `READER_ERROR_DATA`. Erroneous value read from DRAM memory + + .. wavedrom:: + :caption: READER_ERROR_DATA7 + + { + "reg": [ + {"name": "error_data[255:224]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA6 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x38 = 0xf0003038` + + Bits 192-223 of `READER_ERROR_DATA`. + + .. wavedrom:: + :caption: READER_ERROR_DATA6 + + { + "reg": [ + {"name": "error_data[223:192]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA5 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x3c = 0xf000303c` + + Bits 160-191 of `READER_ERROR_DATA`. + + .. wavedrom:: + :caption: READER_ERROR_DATA5 + + { + "reg": [ + {"name": "error_data[191:160]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA4 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x40 = 0xf0003040` + + Bits 128-159 of `READER_ERROR_DATA`. + + .. wavedrom:: + :caption: READER_ERROR_DATA4 + + { + "reg": [ + {"name": "error_data[159:128]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA3 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x44 = 0xf0003044` + + Bits 96-127 of `READER_ERROR_DATA`. + + .. wavedrom:: + :caption: READER_ERROR_DATA3 + + { + "reg": [ + {"name": "error_data[127:96]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA2 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x48 = 0xf0003048` + + Bits 64-95 of `READER_ERROR_DATA`. + + .. wavedrom:: + :caption: READER_ERROR_DATA2 + + { + "reg": [ + {"name": "error_data[95:64]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA1 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x4c = 0xf000304c` + + Bits 32-63 of `READER_ERROR_DATA`. + + .. wavedrom:: + :caption: READER_ERROR_DATA1 + + { + "reg": [ + {"name": "error_data[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA0 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x50 = 0xf0003050` + + Bits 0-31 of `READER_ERROR_DATA`. + + .. wavedrom:: + :caption: READER_ERROR_DATA0 + + { + "reg": [ + {"name": "error_data[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED7 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x54 = 0xf0003054` + + Bits 224-255 of `READER_ERROR_EXPECTED`. Value expected to be read from DRAM + memory + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED7 + + { + "reg": [ + {"name": "error_expected[255:224]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED6 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x58 = 0xf0003058` + + Bits 192-223 of `READER_ERROR_EXPECTED`. + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED6 + + { + "reg": [ + {"name": "error_expected[223:192]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED5 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x5c = 0xf000305c` + + Bits 160-191 of `READER_ERROR_EXPECTED`. + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED5 + + { + "reg": [ + {"name": "error_expected[191:160]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED4 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x60 = 0xf0003060` + + Bits 128-159 of `READER_ERROR_EXPECTED`. + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED4 + + { + "reg": [ + {"name": "error_expected[159:128]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED3 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x64 = 0xf0003064` + + Bits 96-127 of `READER_ERROR_EXPECTED`. + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED3 + + { + "reg": [ + {"name": "error_expected[127:96]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED2 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x68 = 0xf0003068` + + Bits 64-95 of `READER_ERROR_EXPECTED`. + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED2 + + { + "reg": [ + {"name": "error_expected[95:64]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED1 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x6c = 0xf000306c` + + Bits 32-63 of `READER_ERROR_EXPECTED`. + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED1 + + { + "reg": [ + {"name": "error_expected[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED0 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x70 = 0xf0003070` + + Bits 0-31 of `READER_ERROR_EXPECTED`. + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED0 + + { + "reg": [ + {"name": "error_expected[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_READY +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x74 = 0xf0003074` + + Error detected and ready to read + + .. wavedrom:: + :caption: READER_ERROR_READY + + { + "reg": [ + {"name": "error_ready", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_ERROR_CONTINUE +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x78 = 0xf0003078` + + Continue reading until the next error + + .. wavedrom:: + :caption: READER_ERROR_CONTINUE + + { + "reg": [ + {"name": "error_continue", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/ddr5_tester/documentation/rowhammer.rst.txt b/_sources/build/ddr5_tester/documentation/rowhammer.rst.txt new file mode 100644 index 000000000..1decae81b --- /dev/null +++ b/_sources/build/ddr5_tester/documentation/rowhammer.rst.txt @@ -0,0 +1,102 @@ +ROWHAMMER +========= + + + +Row Hammer DMA attacker + +This module allows to perform a Row Hammer attack by configuring it with +two addresses that map to different rows of a single bank. When enabled, +it will perform alternating DMA reads from the given locations, which will +result in the DRAM controller having to repeatedly open/close rows at each +read access. + + +Register Listing for ROWHAMMER +------------------------------ + ++------------------------------------------------+----------------------------------------+ +| Register | Address | ++================================================+========================================+ +| :ref:`ROWHAMMER_ENABLED ` | :ref:`0xf0002000 ` | ++------------------------------------------------+----------------------------------------+ +| :ref:`ROWHAMMER_ADDRESS1 ` | :ref:`0xf0002004 ` | ++------------------------------------------------+----------------------------------------+ +| :ref:`ROWHAMMER_ADDRESS2 ` | :ref:`0xf0002008 ` | ++------------------------------------------------+----------------------------------------+ +| :ref:`ROWHAMMER_COUNT ` | :ref:`0xf000200c ` | ++------------------------------------------------+----------------------------------------+ + +ROWHAMMER_ENABLED +^^^^^^^^^^^^^^^^^ + +`Address: 0xf0002000 + 0x0 = 0xf0002000` + + Used to start/stop the operation of the module + + .. wavedrom:: + :caption: ROWHAMMER_ENABLED + + { + "reg": [ + {"name": "enabled", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +ROWHAMMER_ADDRESS1 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0002000 + 0x4 = 0xf0002004` + + First attacked address + + .. wavedrom:: + :caption: ROWHAMMER_ADDRESS1 + + { + "reg": [ + {"name": "address1[30:0]", "bits": 31}, + {"bits": 1}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +ROWHAMMER_ADDRESS2 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0002000 + 0x8 = 0xf0002008` + + Second attacked address + + .. wavedrom:: + :caption: ROWHAMMER_ADDRESS2 + + { + "reg": [ + {"name": "address2[30:0]", "bits": 31}, + {"bits": 1}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +ROWHAMMER_COUNT +^^^^^^^^^^^^^^^ + +`Address: 0xf0002000 + 0xc = 0xf000200c` + + This is the number of DMA accesses performed. When the module is enabled, the + value can be freely read. When the module is disabled, the register is clear-on- + write and has to be read before the next attack. + + .. wavedrom:: + :caption: ROWHAMMER_COUNT + + { + "reg": [ + {"name": "count[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/ddr5_tester/documentation/sdram.rst.txt b/_sources/build/ddr5_tester/documentation/sdram.rst.txt new file mode 100644 index 000000000..e9e2184e6 --- /dev/null +++ b/_sources/build/ddr5_tester/documentation/sdram.rst.txt @@ -0,0 +1,2298 @@ +SDRAM +===== + +Register Listing for SDRAM +-------------------------- + ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| Register | Address | ++============================================================================================================+======================================================================+ +| :ref:`SDRAM_DFII_CONTROL ` | :ref:`0xf0007000 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_FORCE_ISSUE ` | :ref:`0xf0007004 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_A_CMDINJECTOR_COMMAND_STORAGE ` | :ref:`0xf0007008 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_A_CMDINJECTOR_COMMAND_STORAGE_WR_MASK ` | :ref:`0xf000700c ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_A_CMDINJECTOR_PHASE_ADDR ` | :ref:`0xf0007010 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_A_CMDINJECTOR_STORE_CONTINUOUS_CMD ` | :ref:`0xf0007014 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_A_CMDINJECTOR_STORE_SINGLESHOT_CMD ` | :ref:`0xf0007018 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_A_CMDINJECTOR_SINGLE_SHOT ` | :ref:`0xf000701c ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_A_CMDINJECTOR_ISSUE_COMMAND ` | :ref:`0xf0007020 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_A_CMDINJECTOR_WRDATA_SELECT ` | :ref:`0xf0007024 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_A_CMDINJECTOR_WRDATA ` | :ref:`0xf0007028 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_A_CMDINJECTOR_WRDATA_S ` | :ref:`0xf000702c ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_A_CMDINJECTOR_WRDATA_STORE ` | :ref:`0xf0007030 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_A_CMDINJECTOR_SETUP ` | :ref:`0xf0007034 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_A_CMDINJECTOR_SAMPLE ` | :ref:`0xf0007038 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_A_CMDINJECTOR_RESULT_ARRAY ` | :ref:`0xf000703c ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_A_CMDINJECTOR_RESET ` | :ref:`0xf0007040 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_A_CMDINJECTOR_RDDATA_SELECT ` | :ref:`0xf0007044 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_A_CMDINJECTOR_RDDATA_CAPTURE_CNT ` | :ref:`0xf0007048 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_A_CMDINJECTOR_RDDATA ` | :ref:`0xf000704c ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_B_CMDINJECTOR_COMMAND_STORAGE ` | :ref:`0xf0007050 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_B_CMDINJECTOR_COMMAND_STORAGE_WR_MASK ` | :ref:`0xf0007054 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_B_CMDINJECTOR_PHASE_ADDR ` | :ref:`0xf0007058 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_B_CMDINJECTOR_STORE_CONTINUOUS_CMD ` | :ref:`0xf000705c ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_B_CMDINJECTOR_STORE_SINGLESHOT_CMD ` | :ref:`0xf0007060 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_B_CMDINJECTOR_SINGLE_SHOT ` | :ref:`0xf0007064 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_B_CMDINJECTOR_ISSUE_COMMAND ` | :ref:`0xf0007068 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_B_CMDINJECTOR_WRDATA_SELECT ` | :ref:`0xf000706c ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_B_CMDINJECTOR_WRDATA ` | :ref:`0xf0007070 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_B_CMDINJECTOR_WRDATA_S ` | :ref:`0xf0007074 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_B_CMDINJECTOR_WRDATA_STORE ` | :ref:`0xf0007078 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_B_CMDINJECTOR_SETUP ` | :ref:`0xf000707c ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_B_CMDINJECTOR_SAMPLE ` | :ref:`0xf0007080 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_B_CMDINJECTOR_RESULT_ARRAY ` | :ref:`0xf0007084 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_B_CMDINJECTOR_RESET ` | :ref:`0xf0007088 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_B_CMDINJECTOR_RDDATA_SELECT ` | :ref:`0xf000708c ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_B_CMDINJECTOR_RDDATA_CAPTURE_CNT ` | :ref:`0xf0007090 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_DFII_B_CMDINJECTOR_RDDATA ` | :ref:`0xf0007094 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRP ` | :ref:`0xf0007098 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRCD ` | :ref:`0xf000709c ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TWR ` | :ref:`0xf00070a0 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TWTR ` | :ref:`0xf00070a4 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TREFI ` | :ref:`0xf00070a8 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRFC ` | :ref:`0xf00070ac ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TFAW ` | :ref:`0xf00070b0 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TCCD ` | :ref:`0xf00070b4 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TCCD_WR ` | :ref:`0xf00070b8 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRTP ` | :ref:`0xf00070bc ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRRD ` | :ref:`0xf00070c0 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRC ` | :ref:`0xf00070c4 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRAS ` | :ref:`0xf00070c8 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_0 ` | :ref:`0xf00070cc ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_0 ` | :ref:`0xf00070d0 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_1 ` | :ref:`0xf00070d4 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_1 ` | :ref:`0xf00070d8 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_2 ` | :ref:`0xf00070dc ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_2 ` | :ref:`0xf00070e0 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_3 ` | :ref:`0xf00070e4 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_3 ` | :ref:`0xf00070e8 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_4 ` | :ref:`0xf00070ec ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_4 ` | :ref:`0xf00070f0 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_5 ` | :ref:`0xf00070f4 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_5 ` | :ref:`0xf00070f8 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_6 ` | :ref:`0xf00070fc ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_6 ` | :ref:`0xf0007100 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_7 ` | :ref:`0xf0007104 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_7 ` | :ref:`0xf0007108 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_8 ` | :ref:`0xf000710c ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_8 ` | :ref:`0xf0007110 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_9 ` | :ref:`0xf0007114 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_9 ` | :ref:`0xf0007118 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_10 ` | :ref:`0xf000711c ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_10 ` | :ref:`0xf0007120 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_11 ` | :ref:`0xf0007124 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_11 ` | :ref:`0xf0007128 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_12 ` | :ref:`0xf000712c ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_12 ` | :ref:`0xf0007130 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_13 ` | :ref:`0xf0007134 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_13 ` | :ref:`0xf0007138 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_14 ` | :ref:`0xf000713c ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_14 ` | :ref:`0xf0007140 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_15 ` | :ref:`0xf0007144 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_15 ` | :ref:`0xf0007148 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_16 ` | :ref:`0xf000714c ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_16 ` | :ref:`0xf0007150 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_17 ` | :ref:`0xf0007154 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_17 ` | :ref:`0xf0007158 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_18 ` | :ref:`0xf000715c ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_18 ` | :ref:`0xf0007160 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_19 ` | :ref:`0xf0007164 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_19 ` | :ref:`0xf0007168 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_20 ` | :ref:`0xf000716c ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_20 ` | :ref:`0xf0007170 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_21 ` | :ref:`0xf0007174 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_21 ` | :ref:`0xf0007178 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_22 ` | :ref:`0xf000717c ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_22 ` | :ref:`0xf0007180 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_23 ` | :ref:`0xf0007184 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_23 ` | :ref:`0xf0007188 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_24 ` | :ref:`0xf000718c ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_24 ` | :ref:`0xf0007190 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_25 ` | :ref:`0xf0007194 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_25 ` | :ref:`0xf0007198 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_26 ` | :ref:`0xf000719c ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_26 ` | :ref:`0xf00071a0 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_27 ` | :ref:`0xf00071a4 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_27 ` | :ref:`0xf00071a8 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_28 ` | :ref:`0xf00071ac ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_28 ` | :ref:`0xf00071b0 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_29 ` | :ref:`0xf00071b4 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_29 ` | :ref:`0xf00071b8 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_30 ` | :ref:`0xf00071bc ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_30 ` | :ref:`0xf00071c0 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_31 ` | :ref:`0xf00071c4 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_31 ` | :ref:`0xf00071c8 ` | ++------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+ + +SDRAM_DFII_CONTROL +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x0 = 0xf0007000` + + Control DFI signals common to all phases + + .. wavedrom:: + :caption: SDRAM_DFII_CONTROL + + { + "reg": [ + {"name": "sel", "attr": '1', "bits": 1}, + {"name": "cke", "bits": 1}, + {"name": "odt", "bits": 1}, + {"name": "reset_n", "bits": 1}, + {"name": "mode_2n", "attr": '1', "bits": 1}, + {"name": "A_control", "bits": 1}, + {"name": "B_control", "bits": 1}, + {"bits": 25} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+-----------+-------------------------------------------+ +| Field | Name | Description | ++=======+===========+===========================================+ +| [0] | SEL | | +| | | | +| | | +---------+-----------------------------+ | +| | | | Value | Description | | +| | | +=========+=============================+ | +| | | | ``0b0`` | Software (CPU) control. | | +| | | +---------+-----------------------------+ | +| | | | ``0b1`` | Hardware control (default). | | +| | | +---------+-----------------------------+ | ++-------+-----------+-------------------------------------------+ +| [1] | CKE | DFI clock enable bus | ++-------+-----------+-------------------------------------------+ +| [2] | ODT | DFI on-die termination bus | ++-------+-----------+-------------------------------------------+ +| [3] | RESET_N | DFI clock reset bus | ++-------+-----------+-------------------------------------------+ +| [4] | MODE_2N | | +| | | | +| | | +---------+----------------------+ | +| | | | Value | Description | | +| | | +=========+======================+ | +| | | | ``0b0`` | In 1N mode | | +| | | +---------+----------------------+ | +| | | | ``0b1`` | In 2N mode (Default) | | +| | | +---------+----------------------+ | ++-------+-----------+-------------------------------------------+ +| [5] | A_CONTROL | | +| | | | +| | | +---------+----------------+ | +| | | | Value | Description | | +| | | +=========+================+ | +| | | | ``0b1`` | A_Cmd Injector | | +| | | +---------+----------------+ | ++-------+-----------+-------------------------------------------+ +| [6] | B_CONTROL | | +| | | | +| | | +---------+----------------+ | +| | | | Value | Description | | +| | | +=========+================+ | +| | | | ``0b1`` | B_Cmd Injector | | +| | | +---------+----------------+ | ++-------+-----------+-------------------------------------------+ + +SDRAM_DFII_FORCE_ISSUE +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x4 = 0xf0007004` + + + .. wavedrom:: + :caption: SDRAM_DFII_FORCE_ISSUE + + { + "reg": [ + {"name": "dfii_force_issue", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_A_CMDINJECTOR_COMMAND_STORAGE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x8 = 0xf0007008` + + DDR5 command and control signals + + .. wavedrom:: + :caption: SDRAM_DFII_A_CMDINJECTOR_COMMAND_STORAGE + + { + "reg": [ + {"name": "ca", "bits": 14}, + {"name": "cs", "bits": 2}, + {"name": "wrdata_en", "bits": 1}, + {"name": "rddata_en", "bits": 1}, + {"bits": 14} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++---------+-----------+---------------------+ +| Field | Name | Description | ++=========+===========+=====================+ +| [13:0] | CA | Command/Address bus | ++---------+-----------+---------------------+ +| [15:14] | CS | DFI chip select bus | ++---------+-----------+---------------------+ ++---------+-----------+---------------------+ ++---------+-----------+---------------------+ + +SDRAM_DFII_A_CMDINJECTOR_COMMAND_STORAGE_WR_MASK +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0xc = 0xf000700c` + + DDR5 wrdata mask control signals + + .. wavedrom:: + :caption: SDRAM_DFII_A_CMDINJECTOR_COMMAND_STORAGE_WR_MASK + + { + "reg": [ + {"name": "wrdata_mask", "bits": 4}, + {"bits": 28} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+-------------+-------------+ +| Field | Name | Description | ++=======+=============+=============+ ++-------+-------------+-------------+ + +SDRAM_DFII_A_CMDINJECTOR_PHASE_ADDR +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x10 = 0xf0007010` + + + .. wavedrom:: + :caption: SDRAM_DFII_A_CMDINJECTOR_PHASE_ADDR + + { + "reg": [ + {"name": "dfii_a_cmdinjector_phase_addr[7:0]", "bits": 8}, + {"bits": 24}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_A_CMDINJECTOR_STORE_CONTINUOUS_CMD +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x14 = 0xf0007014` + + + .. wavedrom:: + :caption: SDRAM_DFII_A_CMDINJECTOR_STORE_CONTINUOUS_CMD + + { + "reg": [ + {"name": "dfii_a_cmdinjector_store_continuous_cmd", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_A_CMDINJECTOR_STORE_SINGLESHOT_CMD +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x18 = 0xf0007018` + + + .. wavedrom:: + :caption: SDRAM_DFII_A_CMDINJECTOR_STORE_SINGLESHOT_CMD + + { + "reg": [ + {"name": "dfii_a_cmdinjector_store_singleshot_cmd", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_A_CMDINJECTOR_SINGLE_SHOT +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x1c = 0xf000701c` + + + .. wavedrom:: + :caption: SDRAM_DFII_A_CMDINJECTOR_SINGLE_SHOT + + { + "reg": [ + {"name": "dfii_a_cmdinjector_single_shot", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_A_CMDINJECTOR_ISSUE_COMMAND +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x20 = 0xf0007020` + + + .. wavedrom:: + :caption: SDRAM_DFII_A_CMDINJECTOR_ISSUE_COMMAND + + { + "reg": [ + {"name": "dfii_a_cmdinjector_issue_command", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_A_CMDINJECTOR_WRDATA_SELECT +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x24 = 0xf0007024` + + + .. wavedrom:: + :caption: SDRAM_DFII_A_CMDINJECTOR_WRDATA_SELECT + + { + "reg": [ + {"name": "dfii_a_cmdinjector_wrdata_select[3:0]", "bits": 4}, + {"bits": 28}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_A_CMDINJECTOR_WRDATA +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x28 = 0xf0007028` + + + .. wavedrom:: + :caption: SDRAM_DFII_A_CMDINJECTOR_WRDATA + + { + "reg": [ + {"name": "dfii_a_cmdinjector_wrdata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_A_CMDINJECTOR_WRDATA_S +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x2c = 0xf000702c` + + + .. wavedrom:: + :caption: SDRAM_DFII_A_CMDINJECTOR_WRDATA_S + + { + "reg": [ + {"name": "dfii_a_cmdinjector_wrdata_s[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_A_CMDINJECTOR_WRDATA_STORE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x30 = 0xf0007030` + + + .. wavedrom:: + :caption: SDRAM_DFII_A_CMDINJECTOR_WRDATA_STORE + + { + "reg": [ + {"name": "dfii_a_cmdinjector_wrdata_store", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_A_CMDINJECTOR_SETUP +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x34 = 0xf0007034` + + + .. wavedrom:: + :caption: SDRAM_DFII_A_CMDINJECTOR_SETUP + + { + "reg": [ + {"name": "initial_state", "bits": 1}, + {"name": "operation", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+---------------+------------------------------+ +| Field | Name | Description | ++=======+===============+==============================+ +| [0] | INITIAL_STATE | Initial value of all bits | ++-------+---------------+------------------------------+ +| [1] | OPERATION | 0 - `or` (default), 1 -`and` | ++-------+---------------+------------------------------+ + +SDRAM_DFII_A_CMDINJECTOR_SAMPLE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x38 = 0xf0007038` + + + .. wavedrom:: + :caption: SDRAM_DFII_A_CMDINJECTOR_SAMPLE + + { + "reg": [ + {"name": "dfii_a_cmdinjector_sample", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_A_CMDINJECTOR_RESULT_ARRAY +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x3c = 0xf000703c` + + + .. wavedrom:: + :caption: SDRAM_DFII_A_CMDINJECTOR_RESULT_ARRAY + + { + "reg": [ + {"name": "dfii_a_cmdinjector_result_array[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_A_CMDINJECTOR_RESET +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x40 = 0xf0007040` + + + .. wavedrom:: + :caption: SDRAM_DFII_A_CMDINJECTOR_RESET + + { + "reg": [ + {"name": "dfii_a_cmdinjector_reset", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_A_CMDINJECTOR_RDDATA_SELECT +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x44 = 0xf0007044` + + + .. wavedrom:: + :caption: SDRAM_DFII_A_CMDINJECTOR_RDDATA_SELECT + + { + "reg": [ + {"name": "dfii_a_cmdinjector_rddata_select[3:0]", "bits": 4}, + {"bits": 28}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_A_CMDINJECTOR_RDDATA_CAPTURE_CNT +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x48 = 0xf0007048` + + + .. wavedrom:: + :caption: SDRAM_DFII_A_CMDINJECTOR_RDDATA_CAPTURE_CNT + + { + "reg": [ + {"name": "dfii_a_cmdinjector_rddata_capture_cnt[3:0]", "bits": 4}, + {"bits": 28}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_A_CMDINJECTOR_RDDATA +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x4c = 0xf000704c` + + + .. wavedrom:: + :caption: SDRAM_DFII_A_CMDINJECTOR_RDDATA + + { + "reg": [ + {"name": "dfii_a_cmdinjector_rddata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_B_CMDINJECTOR_COMMAND_STORAGE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x50 = 0xf0007050` + + DDR5 command and control signals + + .. wavedrom:: + :caption: SDRAM_DFII_B_CMDINJECTOR_COMMAND_STORAGE + + { + "reg": [ + {"name": "ca", "bits": 14}, + {"name": "cs", "bits": 2}, + {"name": "wrdata_en", "bits": 1}, + {"name": "rddata_en", "bits": 1}, + {"bits": 14} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++---------+-----------+---------------------+ +| Field | Name | Description | ++=========+===========+=====================+ +| [13:0] | CA | Command/Address bus | ++---------+-----------+---------------------+ +| [15:14] | CS | DFI chip select bus | ++---------+-----------+---------------------+ ++---------+-----------+---------------------+ ++---------+-----------+---------------------+ + +SDRAM_DFII_B_CMDINJECTOR_COMMAND_STORAGE_WR_MASK +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x54 = 0xf0007054` + + DDR5 wrdata mask control signals + + .. wavedrom:: + :caption: SDRAM_DFII_B_CMDINJECTOR_COMMAND_STORAGE_WR_MASK + + { + "reg": [ + {"name": "wrdata_mask", "bits": 4}, + {"bits": 28} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+-------------+-------------+ +| Field | Name | Description | ++=======+=============+=============+ ++-------+-------------+-------------+ + +SDRAM_DFII_B_CMDINJECTOR_PHASE_ADDR +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x58 = 0xf0007058` + + + .. wavedrom:: + :caption: SDRAM_DFII_B_CMDINJECTOR_PHASE_ADDR + + { + "reg": [ + {"name": "dfii_b_cmdinjector_phase_addr[7:0]", "bits": 8}, + {"bits": 24}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_B_CMDINJECTOR_STORE_CONTINUOUS_CMD +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x5c = 0xf000705c` + + + .. wavedrom:: + :caption: SDRAM_DFII_B_CMDINJECTOR_STORE_CONTINUOUS_CMD + + { + "reg": [ + {"name": "dfii_b_cmdinjector_store_continuous_cmd", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_B_CMDINJECTOR_STORE_SINGLESHOT_CMD +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x60 = 0xf0007060` + + + .. wavedrom:: + :caption: SDRAM_DFII_B_CMDINJECTOR_STORE_SINGLESHOT_CMD + + { + "reg": [ + {"name": "dfii_b_cmdinjector_store_singleshot_cmd", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_B_CMDINJECTOR_SINGLE_SHOT +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x64 = 0xf0007064` + + + .. wavedrom:: + :caption: SDRAM_DFII_B_CMDINJECTOR_SINGLE_SHOT + + { + "reg": [ + {"name": "dfii_b_cmdinjector_single_shot", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_B_CMDINJECTOR_ISSUE_COMMAND +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x68 = 0xf0007068` + + + .. wavedrom:: + :caption: SDRAM_DFII_B_CMDINJECTOR_ISSUE_COMMAND + + { + "reg": [ + {"name": "dfii_b_cmdinjector_issue_command", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_B_CMDINJECTOR_WRDATA_SELECT +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x6c = 0xf000706c` + + + .. wavedrom:: + :caption: SDRAM_DFII_B_CMDINJECTOR_WRDATA_SELECT + + { + "reg": [ + {"name": "dfii_b_cmdinjector_wrdata_select[3:0]", "bits": 4}, + {"bits": 28}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_B_CMDINJECTOR_WRDATA +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x70 = 0xf0007070` + + + .. wavedrom:: + :caption: SDRAM_DFII_B_CMDINJECTOR_WRDATA + + { + "reg": [ + {"name": "dfii_b_cmdinjector_wrdata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_B_CMDINJECTOR_WRDATA_S +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x74 = 0xf0007074` + + + .. wavedrom:: + :caption: SDRAM_DFII_B_CMDINJECTOR_WRDATA_S + + { + "reg": [ + {"name": "dfii_b_cmdinjector_wrdata_s[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_B_CMDINJECTOR_WRDATA_STORE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x78 = 0xf0007078` + + + .. wavedrom:: + :caption: SDRAM_DFII_B_CMDINJECTOR_WRDATA_STORE + + { + "reg": [ + {"name": "dfii_b_cmdinjector_wrdata_store", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_B_CMDINJECTOR_SETUP +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x7c = 0xf000707c` + + + .. wavedrom:: + :caption: SDRAM_DFII_B_CMDINJECTOR_SETUP + + { + "reg": [ + {"name": "initial_state", "bits": 1}, + {"name": "operation", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+---------------+------------------------------+ +| Field | Name | Description | ++=======+===============+==============================+ +| [0] | INITIAL_STATE | Initial value of all bits | ++-------+---------------+------------------------------+ +| [1] | OPERATION | 0 - `or` (default), 1 -`and` | ++-------+---------------+------------------------------+ + +SDRAM_DFII_B_CMDINJECTOR_SAMPLE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x80 = 0xf0007080` + + + .. wavedrom:: + :caption: SDRAM_DFII_B_CMDINJECTOR_SAMPLE + + { + "reg": [ + {"name": "dfii_b_cmdinjector_sample", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_B_CMDINJECTOR_RESULT_ARRAY +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x84 = 0xf0007084` + + + .. wavedrom:: + :caption: SDRAM_DFII_B_CMDINJECTOR_RESULT_ARRAY + + { + "reg": [ + {"name": "dfii_b_cmdinjector_result_array[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_B_CMDINJECTOR_RESET +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x88 = 0xf0007088` + + + .. wavedrom:: + :caption: SDRAM_DFII_B_CMDINJECTOR_RESET + + { + "reg": [ + {"name": "dfii_b_cmdinjector_reset", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_B_CMDINJECTOR_RDDATA_SELECT +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x8c = 0xf000708c` + + + .. wavedrom:: + :caption: SDRAM_DFII_B_CMDINJECTOR_RDDATA_SELECT + + { + "reg": [ + {"name": "dfii_b_cmdinjector_rddata_select[3:0]", "bits": 4}, + {"bits": 28}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_B_CMDINJECTOR_RDDATA_CAPTURE_CNT +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x90 = 0xf0007090` + + + .. wavedrom:: + :caption: SDRAM_DFII_B_CMDINJECTOR_RDDATA_CAPTURE_CNT + + { + "reg": [ + {"name": "dfii_b_cmdinjector_rddata_capture_cnt[3:0]", "bits": 4}, + {"bits": 28}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_B_CMDINJECTOR_RDDATA +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x94 = 0xf0007094` + + + .. wavedrom:: + :caption: SDRAM_DFII_B_CMDINJECTOR_RDDATA + + { + "reg": [ + {"name": "dfii_b_cmdinjector_rddata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_TRP +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x98 = 0xf0007098` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRP + + { + "reg": [ + {"name": "controller_trp[2:0]", "attr": 'reset: 4', "bits": 3}, + {"bits": 29}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TRCD +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x9c = 0xf000709c` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRCD + + { + "reg": [ + {"name": "controller_trcd[2:0]", "attr": 'reset: 4', "bits": 3}, + {"bits": 29}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TWR +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0xa0 = 0xf00070a0` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TWR + + { + "reg": [ + {"name": "controller_twr[3:0]", "attr": 'reset: 7', "bits": 4}, + {"bits": 28}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TWTR +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0xa4 = 0xf00070a4` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TWTR + + { + "reg": [ + {"name": "controller_twtr[4:0]", "attr": 'reset: 4', "bits": 5}, + {"bits": 27}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TREFI +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0xa8 = 0xf00070a8` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TREFI + + { + "reg": [ + {"name": "controller_trefi[9:0]", "attr": 'reset: 779', "bits": 10}, + {"bits": 22}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_TRFC +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0xac = 0xf00070ac` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRFC + + { + "reg": [ + {"name": "controller_trfc[6:0]", "attr": 'reset: 60', "bits": 7}, + {"bits": 25}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TFAW +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0xb0 = 0xf00070b0` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TFAW + + { + "reg": [ + {"name": "controller_tfaw[3:0]", "attr": 'reset: 8', "bits": 4}, + {"bits": 28}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TCCD +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0xb4 = 0xf00070b4` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TCCD + + { + "reg": [ + {"name": "controller_tccd[1:0]", "attr": 'reset: 2', "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TCCD_WR +^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0xb8 = 0xf00070b8` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TCCD_WR + + { + "reg": [ + {"name": "controller_tccd_wr[3:0]", "attr": 'reset: 8', "bits": 4}, + {"bits": 28}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TRTP +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0xbc = 0xf00070bc` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRTP + + { + "reg": [ + {"name": "controller_trtp[1:0]", "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TRRD +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0xc0 = 0xf00070c0` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRRD + + { + "reg": [ + {"name": "controller_trrd[1:0]", "attr": 'reset: 2', "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TRC +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0xc4 = 0xf00070c4` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRC + + { + "reg": [ + {"name": "controller_trc[3:0]", "attr": 'reset: 11', "bits": 4}, + {"bits": 28}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TRAS +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0xc8 = 0xf00070c8` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRAS + + { + "reg": [ + {"name": "controller_tras[3:0]", "attr": 'reset: 8', "bits": 4}, + {"bits": 28}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_LAST_ADDR_0 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0xcc = 0xf00070cc` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_0 + + { + "reg": [ + {"name": "controller_last_addr_0[25:0]", "bits": 26}, + {"bits": 6}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_0 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0xd0 = 0xf00070d0` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_0 + + { + "reg": [ + {"name": "controller_last_active_row_0[17:0]", "bits": 18}, + {"bits": 14}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_1 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0xd4 = 0xf00070d4` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_1 + + { + "reg": [ + {"name": "controller_last_addr_1[25:0]", "bits": 26}, + {"bits": 6}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_1 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0xd8 = 0xf00070d8` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_1 + + { + "reg": [ + {"name": "controller_last_active_row_1[17:0]", "bits": 18}, + {"bits": 14}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_2 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0xdc = 0xf00070dc` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_2 + + { + "reg": [ + {"name": "controller_last_addr_2[25:0]", "bits": 26}, + {"bits": 6}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_2 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0xe0 = 0xf00070e0` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_2 + + { + "reg": [ + {"name": "controller_last_active_row_2[17:0]", "bits": 18}, + {"bits": 14}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_3 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0xe4 = 0xf00070e4` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_3 + + { + "reg": [ + {"name": "controller_last_addr_3[25:0]", "bits": 26}, + {"bits": 6}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_3 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0xe8 = 0xf00070e8` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_3 + + { + "reg": [ + {"name": "controller_last_active_row_3[17:0]", "bits": 18}, + {"bits": 14}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_4 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0xec = 0xf00070ec` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_4 + + { + "reg": [ + {"name": "controller_last_addr_4[25:0]", "bits": 26}, + {"bits": 6}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_4 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0xf0 = 0xf00070f0` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_4 + + { + "reg": [ + {"name": "controller_last_active_row_4[17:0]", "bits": 18}, + {"bits": 14}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_5 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0xf4 = 0xf00070f4` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_5 + + { + "reg": [ + {"name": "controller_last_addr_5[25:0]", "bits": 26}, + {"bits": 6}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_5 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0xf8 = 0xf00070f8` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_5 + + { + "reg": [ + {"name": "controller_last_active_row_5[17:0]", "bits": 18}, + {"bits": 14}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_6 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0xfc = 0xf00070fc` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_6 + + { + "reg": [ + {"name": "controller_last_addr_6[25:0]", "bits": 26}, + {"bits": 6}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_6 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x100 = 0xf0007100` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_6 + + { + "reg": [ + {"name": "controller_last_active_row_6[17:0]", "bits": 18}, + {"bits": 14}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_7 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x104 = 0xf0007104` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_7 + + { + "reg": [ + {"name": "controller_last_addr_7[25:0]", "bits": 26}, + {"bits": 6}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_7 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x108 = 0xf0007108` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_7 + + { + "reg": [ + {"name": "controller_last_active_row_7[17:0]", "bits": 18}, + {"bits": 14}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_8 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x10c = 0xf000710c` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_8 + + { + "reg": [ + {"name": "controller_last_addr_8[25:0]", "bits": 26}, + {"bits": 6}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_8 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x110 = 0xf0007110` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_8 + + { + "reg": [ + {"name": "controller_last_active_row_8[17:0]", "bits": 18}, + {"bits": 14}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_9 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x114 = 0xf0007114` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_9 + + { + "reg": [ + {"name": "controller_last_addr_9[25:0]", "bits": 26}, + {"bits": 6}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_9 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x118 = 0xf0007118` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_9 + + { + "reg": [ + {"name": "controller_last_active_row_9[17:0]", "bits": 18}, + {"bits": 14}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_10 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x11c = 0xf000711c` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_10 + + { + "reg": [ + {"name": "controller_last_addr_10[25:0]", "bits": 26}, + {"bits": 6}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_10 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x120 = 0xf0007120` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_10 + + { + "reg": [ + {"name": "controller_last_active_row_10[17:0]", "bits": 18}, + {"bits": 14}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_11 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x124 = 0xf0007124` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_11 + + { + "reg": [ + {"name": "controller_last_addr_11[25:0]", "bits": 26}, + {"bits": 6}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_11 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x128 = 0xf0007128` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_11 + + { + "reg": [ + {"name": "controller_last_active_row_11[17:0]", "bits": 18}, + {"bits": 14}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_12 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x12c = 0xf000712c` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_12 + + { + "reg": [ + {"name": "controller_last_addr_12[25:0]", "bits": 26}, + {"bits": 6}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_12 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x130 = 0xf0007130` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_12 + + { + "reg": [ + {"name": "controller_last_active_row_12[17:0]", "bits": 18}, + {"bits": 14}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_13 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x134 = 0xf0007134` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_13 + + { + "reg": [ + {"name": "controller_last_addr_13[25:0]", "bits": 26}, + {"bits": 6}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_13 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x138 = 0xf0007138` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_13 + + { + "reg": [ + {"name": "controller_last_active_row_13[17:0]", "bits": 18}, + {"bits": 14}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_14 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x13c = 0xf000713c` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_14 + + { + "reg": [ + {"name": "controller_last_addr_14[25:0]", "bits": 26}, + {"bits": 6}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_14 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x140 = 0xf0007140` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_14 + + { + "reg": [ + {"name": "controller_last_active_row_14[17:0]", "bits": 18}, + {"bits": 14}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_15 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x144 = 0xf0007144` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_15 + + { + "reg": [ + {"name": "controller_last_addr_15[25:0]", "bits": 26}, + {"bits": 6}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_15 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x148 = 0xf0007148` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_15 + + { + "reg": [ + {"name": "controller_last_active_row_15[17:0]", "bits": 18}, + {"bits": 14}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_16 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x14c = 0xf000714c` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_16 + + { + "reg": [ + {"name": "controller_last_addr_16[25:0]", "bits": 26}, + {"bits": 6}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_16 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x150 = 0xf0007150` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_16 + + { + "reg": [ + {"name": "controller_last_active_row_16[17:0]", "bits": 18}, + {"bits": 14}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_17 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x154 = 0xf0007154` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_17 + + { + "reg": [ + {"name": "controller_last_addr_17[25:0]", "bits": 26}, + {"bits": 6}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_17 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x158 = 0xf0007158` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_17 + + { + "reg": [ + {"name": "controller_last_active_row_17[17:0]", "bits": 18}, + {"bits": 14}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_18 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x15c = 0xf000715c` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_18 + + { + "reg": [ + {"name": "controller_last_addr_18[25:0]", "bits": 26}, + {"bits": 6}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_18 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x160 = 0xf0007160` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_18 + + { + "reg": [ + {"name": "controller_last_active_row_18[17:0]", "bits": 18}, + {"bits": 14}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_19 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x164 = 0xf0007164` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_19 + + { + "reg": [ + {"name": "controller_last_addr_19[25:0]", "bits": 26}, + {"bits": 6}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_19 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x168 = 0xf0007168` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_19 + + { + "reg": [ + {"name": "controller_last_active_row_19[17:0]", "bits": 18}, + {"bits": 14}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_20 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x16c = 0xf000716c` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_20 + + { + "reg": [ + {"name": "controller_last_addr_20[25:0]", "bits": 26}, + {"bits": 6}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_20 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x170 = 0xf0007170` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_20 + + { + "reg": [ + {"name": "controller_last_active_row_20[17:0]", "bits": 18}, + {"bits": 14}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_21 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x174 = 0xf0007174` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_21 + + { + "reg": [ + {"name": "controller_last_addr_21[25:0]", "bits": 26}, + {"bits": 6}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_21 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x178 = 0xf0007178` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_21 + + { + "reg": [ + {"name": "controller_last_active_row_21[17:0]", "bits": 18}, + {"bits": 14}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_22 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x17c = 0xf000717c` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_22 + + { + "reg": [ + {"name": "controller_last_addr_22[25:0]", "bits": 26}, + {"bits": 6}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_22 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x180 = 0xf0007180` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_22 + + { + "reg": [ + {"name": "controller_last_active_row_22[17:0]", "bits": 18}, + {"bits": 14}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_23 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x184 = 0xf0007184` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_23 + + { + "reg": [ + {"name": "controller_last_addr_23[25:0]", "bits": 26}, + {"bits": 6}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_23 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x188 = 0xf0007188` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_23 + + { + "reg": [ + {"name": "controller_last_active_row_23[17:0]", "bits": 18}, + {"bits": 14}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_24 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x18c = 0xf000718c` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_24 + + { + "reg": [ + {"name": "controller_last_addr_24[25:0]", "bits": 26}, + {"bits": 6}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_24 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x190 = 0xf0007190` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_24 + + { + "reg": [ + {"name": "controller_last_active_row_24[17:0]", "bits": 18}, + {"bits": 14}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_25 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x194 = 0xf0007194` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_25 + + { + "reg": [ + {"name": "controller_last_addr_25[25:0]", "bits": 26}, + {"bits": 6}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_25 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x198 = 0xf0007198` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_25 + + { + "reg": [ + {"name": "controller_last_active_row_25[17:0]", "bits": 18}, + {"bits": 14}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_26 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x19c = 0xf000719c` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_26 + + { + "reg": [ + {"name": "controller_last_addr_26[25:0]", "bits": 26}, + {"bits": 6}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_26 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x1a0 = 0xf00071a0` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_26 + + { + "reg": [ + {"name": "controller_last_active_row_26[17:0]", "bits": 18}, + {"bits": 14}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_27 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x1a4 = 0xf00071a4` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_27 + + { + "reg": [ + {"name": "controller_last_addr_27[25:0]", "bits": 26}, + {"bits": 6}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_27 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x1a8 = 0xf00071a8` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_27 + + { + "reg": [ + {"name": "controller_last_active_row_27[17:0]", "bits": 18}, + {"bits": 14}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_28 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x1ac = 0xf00071ac` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_28 + + { + "reg": [ + {"name": "controller_last_addr_28[25:0]", "bits": 26}, + {"bits": 6}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_28 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x1b0 = 0xf00071b0` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_28 + + { + "reg": [ + {"name": "controller_last_active_row_28[17:0]", "bits": 18}, + {"bits": 14}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_29 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x1b4 = 0xf00071b4` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_29 + + { + "reg": [ + {"name": "controller_last_addr_29[25:0]", "bits": 26}, + {"bits": 6}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_29 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x1b8 = 0xf00071b8` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_29 + + { + "reg": [ + {"name": "controller_last_active_row_29[17:0]", "bits": 18}, + {"bits": 14}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_30 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x1bc = 0xf00071bc` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_30 + + { + "reg": [ + {"name": "controller_last_addr_30[25:0]", "bits": 26}, + {"bits": 6}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_30 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x1c0 = 0xf00071c0` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_30 + + { + "reg": [ + {"name": "controller_last_active_row_30[17:0]", "bits": 18}, + {"bits": 14}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_31 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x1c4 = 0xf00071c4` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_31 + + { + "reg": [ + {"name": "controller_last_addr_31[25:0]", "bits": 26}, + {"bits": 6}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_31 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x1c8 = 0xf00071c8` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_31 + + { + "reg": [ + {"name": "controller_last_active_row_31[17:0]", "bits": 18}, + {"bits": 14}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/ddr5_tester/documentation/sdram_checker.rst.txt b/_sources/build/ddr5_tester/documentation/sdram_checker.rst.txt new file mode 100644 index 000000000..0b77c7272 --- /dev/null +++ b/_sources/build/ddr5_tester/documentation/sdram_checker.rst.txt @@ -0,0 +1,243 @@ +SDRAM_CHECKER +============= + +Register Listing for SDRAM_CHECKER +---------------------------------- + ++------------------------------------------------------+-------------------------------------------+ +| Register | Address | ++======================================================+===========================================+ +| :ref:`SDRAM_CHECKER_RESET ` | :ref:`0xf0007800 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`SDRAM_CHECKER_START ` | :ref:`0xf0007804 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`SDRAM_CHECKER_DONE ` | :ref:`0xf0007808 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`SDRAM_CHECKER_BASE1 ` | :ref:`0xf000780c ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`SDRAM_CHECKER_BASE0 ` | :ref:`0xf0007810 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`SDRAM_CHECKER_END1 ` | :ref:`0xf0007814 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`SDRAM_CHECKER_END0 ` | :ref:`0xf0007818 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`SDRAM_CHECKER_LENGTH1 ` | :ref:`0xf000781c ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`SDRAM_CHECKER_LENGTH0 ` | :ref:`0xf0007820 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`SDRAM_CHECKER_RANDOM ` | :ref:`0xf0007824 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`SDRAM_CHECKER_TICKS ` | :ref:`0xf0007828 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`SDRAM_CHECKER_ERRORS ` | :ref:`0xf000782c ` | ++------------------------------------------------------+-------------------------------------------+ + +SDRAM_CHECKER_RESET +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x0 = 0xf0007800` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_RESET + + { + "reg": [ + {"name": "reset", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CHECKER_START +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x4 = 0xf0007804` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_START + + { + "reg": [ + {"name": "start", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CHECKER_DONE +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x8 = 0xf0007808` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_DONE + + { + "reg": [ + {"name": "done", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CHECKER_BASE1 +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0xc = 0xf000780c` + + Bits 32-35 of `SDRAM_CHECKER_BASE`. + + .. wavedrom:: + :caption: SDRAM_CHECKER_BASE1 + + { + "reg": [ + {"name": "base[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CHECKER_BASE0 +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x10 = 0xf0007810` + + Bits 0-31 of `SDRAM_CHECKER_BASE`. + + .. wavedrom:: + :caption: SDRAM_CHECKER_BASE0 + + { + "reg": [ + {"name": "base[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CHECKER_END1 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x14 = 0xf0007814` + + Bits 32-35 of `SDRAM_CHECKER_END`. + + .. wavedrom:: + :caption: SDRAM_CHECKER_END1 + + { + "reg": [ + {"name": "end[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CHECKER_END0 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x18 = 0xf0007818` + + Bits 0-31 of `SDRAM_CHECKER_END`. + + .. wavedrom:: + :caption: SDRAM_CHECKER_END0 + + { + "reg": [ + {"name": "end[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CHECKER_LENGTH1 +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x1c = 0xf000781c` + + Bits 32-35 of `SDRAM_CHECKER_LENGTH`. + + .. wavedrom:: + :caption: SDRAM_CHECKER_LENGTH1 + + { + "reg": [ + {"name": "length[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CHECKER_LENGTH0 +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x20 = 0xf0007820` + + Bits 0-31 of `SDRAM_CHECKER_LENGTH`. + + .. wavedrom:: + :caption: SDRAM_CHECKER_LENGTH0 + + { + "reg": [ + {"name": "length[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CHECKER_RANDOM +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x24 = 0xf0007824` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_RANDOM + + { + "reg": [ + {"name": "data", "bits": 1}, + {"name": "addr", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------+ +| Field | Name | Description | ++=======+======+=============+ ++-------+------+-------------+ ++-------+------+-------------+ + +SDRAM_CHECKER_TICKS +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x28 = 0xf0007828` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_TICKS + + { + "reg": [ + {"name": "ticks[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CHECKER_ERRORS +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x2c = 0xf000782c` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_ERRORS + + { + "reg": [ + {"name": "errors[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/ddr5_tester/documentation/sdram_generator.rst.txt b/_sources/build/ddr5_tester/documentation/sdram_generator.rst.txt new file mode 100644 index 000000000..68f1678f9 --- /dev/null +++ b/_sources/build/ddr5_tester/documentation/sdram_generator.rst.txt @@ -0,0 +1,225 @@ +SDRAM_GENERATOR +=============== + +Register Listing for SDRAM_GENERATOR +------------------------------------ + ++----------------------------------------------------------+---------------------------------------------+ +| Register | Address | ++==========================================================+=============================================+ +| :ref:`SDRAM_GENERATOR_RESET ` | :ref:`0xf0008000 ` | ++----------------------------------------------------------+---------------------------------------------+ +| :ref:`SDRAM_GENERATOR_START ` | :ref:`0xf0008004 ` | ++----------------------------------------------------------+---------------------------------------------+ +| :ref:`SDRAM_GENERATOR_DONE ` | :ref:`0xf0008008 ` | ++----------------------------------------------------------+---------------------------------------------+ +| :ref:`SDRAM_GENERATOR_BASE1 ` | :ref:`0xf000800c ` | ++----------------------------------------------------------+---------------------------------------------+ +| :ref:`SDRAM_GENERATOR_BASE0 ` | :ref:`0xf0008010 ` | ++----------------------------------------------------------+---------------------------------------------+ +| :ref:`SDRAM_GENERATOR_END1 ` | :ref:`0xf0008014 ` | ++----------------------------------------------------------+---------------------------------------------+ +| :ref:`SDRAM_GENERATOR_END0 ` | :ref:`0xf0008018 ` | ++----------------------------------------------------------+---------------------------------------------+ +| :ref:`SDRAM_GENERATOR_LENGTH1 ` | :ref:`0xf000801c ` | ++----------------------------------------------------------+---------------------------------------------+ +| :ref:`SDRAM_GENERATOR_LENGTH0 ` | :ref:`0xf0008020 ` | ++----------------------------------------------------------+---------------------------------------------+ +| :ref:`SDRAM_GENERATOR_RANDOM ` | :ref:`0xf0008024 ` | ++----------------------------------------------------------+---------------------------------------------+ +| :ref:`SDRAM_GENERATOR_TICKS ` | :ref:`0xf0008028 ` | ++----------------------------------------------------------+---------------------------------------------+ + +SDRAM_GENERATOR_RESET +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x0 = 0xf0008000` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_RESET + + { + "reg": [ + {"name": "reset", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_GENERATOR_START +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x4 = 0xf0008004` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_START + + { + "reg": [ + {"name": "start", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_GENERATOR_DONE +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x8 = 0xf0008008` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_DONE + + { + "reg": [ + {"name": "done", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_GENERATOR_BASE1 +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0xc = 0xf000800c` + + Bits 32-35 of `SDRAM_GENERATOR_BASE`. + + .. wavedrom:: + :caption: SDRAM_GENERATOR_BASE1 + + { + "reg": [ + {"name": "base[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_GENERATOR_BASE0 +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x10 = 0xf0008010` + + Bits 0-31 of `SDRAM_GENERATOR_BASE`. + + .. wavedrom:: + :caption: SDRAM_GENERATOR_BASE0 + + { + "reg": [ + {"name": "base[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_GENERATOR_END1 +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x14 = 0xf0008014` + + Bits 32-35 of `SDRAM_GENERATOR_END`. + + .. wavedrom:: + :caption: SDRAM_GENERATOR_END1 + + { + "reg": [ + {"name": "end[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_GENERATOR_END0 +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x18 = 0xf0008018` + + Bits 0-31 of `SDRAM_GENERATOR_END`. + + .. wavedrom:: + :caption: SDRAM_GENERATOR_END0 + + { + "reg": [ + {"name": "end[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_GENERATOR_LENGTH1 +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x1c = 0xf000801c` + + Bits 32-35 of `SDRAM_GENERATOR_LENGTH`. + + .. wavedrom:: + :caption: SDRAM_GENERATOR_LENGTH1 + + { + "reg": [ + {"name": "length[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_GENERATOR_LENGTH0 +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x20 = 0xf0008020` + + Bits 0-31 of `SDRAM_GENERATOR_LENGTH`. + + .. wavedrom:: + :caption: SDRAM_GENERATOR_LENGTH0 + + { + "reg": [ + {"name": "length[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_GENERATOR_RANDOM +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x24 = 0xf0008024` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_RANDOM + + { + "reg": [ + {"name": "data", "bits": 1}, + {"name": "addr", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------+ +| Field | Name | Description | ++=======+======+=============+ ++-------+------+-------------+ ++-------+------+-------------+ + +SDRAM_GENERATOR_TICKS +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x28 = 0xf0008028` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_TICKS + + { + "reg": [ + {"name": "ticks[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/ddr5_tester/documentation/timer0.rst.txt b/_sources/build/ddr5_tester/documentation/timer0.rst.txt new file mode 100644 index 000000000..c831cd736 --- /dev/null +++ b/_sources/build/ddr5_tester/documentation/timer0.rst.txt @@ -0,0 +1,228 @@ +TIMER0 +====== + +Timer +----- + +Provides a generic Timer core. + +The Timer is implemented as a countdown timer that can be used in various modes: + +- Polling : Returns current countdown value to software +- One-Shot: Loads itself and stops when value reaches ``0`` +- Periodic: (Re-)Loads itself when value reaches ``0`` + +``en`` register allows the user to enable/disable the Timer. When the Timer is enabled, it is +automatically loaded with the value of `load` register. + +When the Timer reaches ``0``, it is automatically reloaded with value of `reload` register. + +The user can latch the current countdown value by writing to ``update_value`` register, it will +update ``value`` register with current countdown value. + +To use the Timer in One-Shot mode, the user needs to: + +- Disable the timer +- Set the ``load`` register to the expected duration +- (Re-)Enable the Timer + +To use the Timer in Periodic mode, the user needs to: + +- Disable the Timer +- Set the ``load`` register to 0 +- Set the ``reload`` register to the expected period +- Enable the Timer + +For both modes, the CPU can be advertised by an IRQ that the duration/period has elapsed. (The +CPU can also do software polling with ``update_value`` and ``value`` to know the elapsed duration) + + +Register Listing for TIMER0 +--------------------------- + ++--------------------------------------------------+-----------------------------------------+ +| Register | Address | ++==================================================+=========================================+ +| :ref:`TIMER0_LOAD ` | :ref:`0xf0008800 ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_RELOAD ` | :ref:`0xf0008804 ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_EN ` | :ref:`0xf0008808 ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_UPDATE_VALUE ` | :ref:`0xf000880c ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_VALUE ` | :ref:`0xf0008810 ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_EV_STATUS ` | :ref:`0xf0008814 ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_EV_PENDING ` | :ref:`0xf0008818 ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_EV_ENABLE ` | :ref:`0xf000881c ` | ++--------------------------------------------------+-----------------------------------------+ + +TIMER0_LOAD +^^^^^^^^^^^ + +`Address: 0xf0008800 + 0x0 = 0xf0008800` + + Load value when Timer is (re-)enabled. In One-Shot mode, the value written to + this register specifies the Timer's duration in clock cycles. + + .. wavedrom:: + :caption: TIMER0_LOAD + + { + "reg": [ + {"name": "load[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +TIMER0_RELOAD +^^^^^^^^^^^^^ + +`Address: 0xf0008800 + 0x4 = 0xf0008804` + + Reload value when Timer reaches ``0``. In Periodic mode, the value written to + this register specify the Timer's period in clock cycles. + + .. wavedrom:: + :caption: TIMER0_RELOAD + + { + "reg": [ + {"name": "reload[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +TIMER0_EN +^^^^^^^^^ + +`Address: 0xf0008800 + 0x8 = 0xf0008808` + + Enable flag of the Timer. Set this flag to ``1`` to enable/start the Timer. Set + to ``0`` to disable the Timer. + + .. wavedrom:: + :caption: TIMER0_EN + + { + "reg": [ + {"name": "en", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +TIMER0_UPDATE_VALUE +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008800 + 0xc = 0xf000880c` + + Update trigger for the current countdown value. A write to this register latches + the current countdown value to ``value`` register. + + .. wavedrom:: + :caption: TIMER0_UPDATE_VALUE + + { + "reg": [ + {"name": "update_value", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +TIMER0_VALUE +^^^^^^^^^^^^ + +`Address: 0xf0008800 + 0x10 = 0xf0008810` + + Latched countdown value. This value is updated by writing to ``update_value``. + + .. wavedrom:: + :caption: TIMER0_VALUE + + { + "reg": [ + {"name": "value[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +TIMER0_EV_STATUS +^^^^^^^^^^^^^^^^ + +`Address: 0xf0008800 + 0x14 = 0xf0008814` + + This register contains the current raw level of the zero event trigger. Writes + to this register have no effect. + + .. wavedrom:: + :caption: TIMER0_EV_STATUS + + { + "reg": [ + {"name": "zero", "bits": 1}, + {"bits": 31} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-----------------------------+ +| Field | Name | Description | ++=======+======+=============================+ +| [0] | ZERO | Level of the ``zero`` event | ++-------+------+-----------------------------+ + +TIMER0_EV_PENDING +^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008800 + 0x18 = 0xf0008818` + + When a zero event occurs, the corresponding bit will be set in this register. + To clear the Event, set the corresponding bit in this register. + + .. wavedrom:: + :caption: TIMER0_EV_PENDING + + { + "reg": [ + {"name": "zero", "bits": 1}, + {"bits": 31} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+--------------------------------------------------------------------------------+ +| Field | Name | Description | ++=======+======+================================================================================+ +| [0] | ZERO | `1` if a `zero` event occurred. This Event is triggered on a **falling** edge. | ++-------+------+--------------------------------------------------------------------------------+ + +TIMER0_EV_ENABLE +^^^^^^^^^^^^^^^^ + +`Address: 0xf0008800 + 0x1c = 0xf000881c` + + This register enables the corresponding zero events. Write a ``0`` to this + register to disable individual events. + + .. wavedrom:: + :caption: TIMER0_EV_ENABLE + + { + "reg": [ + {"name": "zero", "bits": 1}, + {"bits": 31} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+--------------------------------------------+ +| Field | Name | Description | ++=======+======+============================================+ +| [0] | ZERO | Write a ``1`` to enable the ``zero`` Event | ++-------+------+--------------------------------------------+ + diff --git a/_sources/build/ddr5_tester/documentation/uart.rst.txt b/_sources/build/ddr5_tester/documentation/uart.rst.txt new file mode 100644 index 000000000..81cf90ed9 --- /dev/null +++ b/_sources/build/ddr5_tester/documentation/uart.rst.txt @@ -0,0 +1,388 @@ +UART +==== + +Register Listing for UART +------------------------- + ++------------------------------------------------------+-------------------------------------------+ +| Register | Address | ++======================================================+===========================================+ +| :ref:`UART_RXTX ` | :ref:`0xf0009000 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_TXFULL ` | :ref:`0xf0009004 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_RXEMPTY ` | :ref:`0xf0009008 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_EV_STATUS ` | :ref:`0xf000900c ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_EV_PENDING ` | :ref:`0xf0009010 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_EV_ENABLE ` | :ref:`0xf0009014 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_TXEMPTY ` | :ref:`0xf0009018 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_RXFULL ` | :ref:`0xf000901c ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_RXTX ` | :ref:`0xf0009020 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_TXFULL ` | :ref:`0xf0009024 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_RXEMPTY ` | :ref:`0xf0009028 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_EV_STATUS ` | :ref:`0xf000902c ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_EV_PENDING ` | :ref:`0xf0009030 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_EV_ENABLE ` | :ref:`0xf0009034 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_TXEMPTY ` | :ref:`0xf0009038 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_RXFULL ` | :ref:`0xf000903c ` | ++------------------------------------------------------+-------------------------------------------+ + +UART_RXTX +^^^^^^^^^ + +`Address: 0xf0009000 + 0x0 = 0xf0009000` + + + .. wavedrom:: + :caption: UART_RXTX + + { + "reg": [ + {"name": "rxtx[7:0]", "bits": 8}, + {"bits": 24}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +UART_TXFULL +^^^^^^^^^^^ + +`Address: 0xf0009000 + 0x4 = 0xf0009004` + + TX FIFO Full. + + .. wavedrom:: + :caption: UART_TXFULL + + { + "reg": [ + {"name": "txfull", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_RXEMPTY +^^^^^^^^^^^^ + +`Address: 0xf0009000 + 0x8 = 0xf0009008` + + RX FIFO Empty. + + .. wavedrom:: + :caption: UART_RXEMPTY + + { + "reg": [ + {"name": "rxempty", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_EV_STATUS +^^^^^^^^^^^^^^ + +`Address: 0xf0009000 + 0xc = 0xf000900c` + + This register contains the current raw level of the rx event trigger. Writes to + this register have no effect. + + .. wavedrom:: + :caption: UART_EV_STATUS + + { + "reg": [ + {"name": "tx", "bits": 1}, + {"name": "rx", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+---------------------------+ +| Field | Name | Description | ++=======+======+===========================+ +| [0] | TX | Level of the ``tx`` event | ++-------+------+---------------------------+ +| [1] | RX | Level of the ``rx`` event | ++-------+------+---------------------------+ + +UART_EV_PENDING +^^^^^^^^^^^^^^^ + +`Address: 0xf0009000 + 0x10 = 0xf0009010` + + When a rx event occurs, the corresponding bit will be set in this register. To + clear the Event, set the corresponding bit in this register. + + .. wavedrom:: + :caption: UART_EV_PENDING + + { + "reg": [ + {"name": "tx", "bits": 1}, + {"name": "rx", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+------------------------------------------------------------------------------+ +| Field | Name | Description | ++=======+======+==============================================================================+ +| [0] | TX | `1` if a `tx` event occurred. This Event is triggered on a **falling** edge. | ++-------+------+------------------------------------------------------------------------------+ +| [1] | RX | `1` if a `rx` event occurred. This Event is triggered on a **falling** edge. | ++-------+------+------------------------------------------------------------------------------+ + +UART_EV_ENABLE +^^^^^^^^^^^^^^ + +`Address: 0xf0009000 + 0x14 = 0xf0009014` + + This register enables the corresponding rx events. Write a ``0`` to this + register to disable individual events. + + .. wavedrom:: + :caption: UART_EV_ENABLE + + { + "reg": [ + {"name": "tx", "bits": 1}, + {"name": "rx", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+------------------------------------------+ +| Field | Name | Description | ++=======+======+==========================================+ +| [0] | TX | Write a ``1`` to enable the ``tx`` Event | ++-------+------+------------------------------------------+ +| [1] | RX | Write a ``1`` to enable the ``rx`` Event | ++-------+------+------------------------------------------+ + +UART_TXEMPTY +^^^^^^^^^^^^ + +`Address: 0xf0009000 + 0x18 = 0xf0009018` + + TX FIFO Empty. + + .. wavedrom:: + :caption: UART_TXEMPTY + + { + "reg": [ + {"name": "txempty", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_RXFULL +^^^^^^^^^^^ + +`Address: 0xf0009000 + 0x1c = 0xf000901c` + + RX FIFO Full. + + .. wavedrom:: + :caption: UART_RXFULL + + { + "reg": [ + {"name": "rxfull", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_XOVER_RXTX +^^^^^^^^^^^^^^^ + +`Address: 0xf0009000 + 0x20 = 0xf0009020` + + + .. wavedrom:: + :caption: UART_XOVER_RXTX + + { + "reg": [ + {"name": "xover_rxtx[7:0]", "bits": 8}, + {"bits": 24}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +UART_XOVER_TXFULL +^^^^^^^^^^^^^^^^^ + +`Address: 0xf0009000 + 0x24 = 0xf0009024` + + TX FIFO Full. + + .. wavedrom:: + :caption: UART_XOVER_TXFULL + + { + "reg": [ + {"name": "xover_txfull", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_XOVER_RXEMPTY +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0009000 + 0x28 = 0xf0009028` + + RX FIFO Empty. + + .. wavedrom:: + :caption: UART_XOVER_RXEMPTY + + { + "reg": [ + {"name": "xover_rxempty", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_XOVER_EV_STATUS +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0009000 + 0x2c = 0xf000902c` + + This register contains the current raw level of the rx event trigger. Writes to + this register have no effect. + + .. wavedrom:: + :caption: UART_XOVER_EV_STATUS + + { + "reg": [ + {"name": "tx", "bits": 1}, + {"name": "rx", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+---------------------------+ +| Field | Name | Description | ++=======+======+===========================+ +| [0] | TX | Level of the ``tx`` event | ++-------+------+---------------------------+ +| [1] | RX | Level of the ``rx`` event | ++-------+------+---------------------------+ + +UART_XOVER_EV_PENDING +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0009000 + 0x30 = 0xf0009030` + + When a rx event occurs, the corresponding bit will be set in this register. To + clear the Event, set the corresponding bit in this register. + + .. wavedrom:: + :caption: UART_XOVER_EV_PENDING + + { + "reg": [ + {"name": "tx", "bits": 1}, + {"name": "rx", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+------------------------------------------------------------------------------+ +| Field | Name | Description | ++=======+======+==============================================================================+ +| [0] | TX | `1` if a `tx` event occurred. This Event is triggered on a **falling** edge. | ++-------+------+------------------------------------------------------------------------------+ +| [1] | RX | `1` if a `rx` event occurred. This Event is triggered on a **falling** edge. | ++-------+------+------------------------------------------------------------------------------+ + +UART_XOVER_EV_ENABLE +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0009000 + 0x34 = 0xf0009034` + + This register enables the corresponding rx events. Write a ``0`` to this + register to disable individual events. + + .. wavedrom:: + :caption: UART_XOVER_EV_ENABLE + + { + "reg": [ + {"name": "tx", "bits": 1}, + {"name": "rx", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+------------------------------------------+ +| Field | Name | Description | ++=======+======+==========================================+ +| [0] | TX | Write a ``1`` to enable the ``tx`` Event | ++-------+------+------------------------------------------+ +| [1] | RX | Write a ``1`` to enable the ``rx`` Event | ++-------+------+------------------------------------------+ + +UART_XOVER_TXEMPTY +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0009000 + 0x38 = 0xf0009038` + + TX FIFO Empty. + + .. wavedrom:: + :caption: UART_XOVER_TXEMPTY + + { + "reg": [ + {"name": "xover_txempty", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_XOVER_RXFULL +^^^^^^^^^^^^^^^^^ + +`Address: 0xf0009000 + 0x3c = 0xf000903c` + + RX FIFO Full. + + .. wavedrom:: + :caption: UART_XOVER_RXFULL + + { + "reg": [ + {"name": "xover_rxfull", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/ddr5_tester/documentation/writer.rst.txt b/_sources/build/ddr5_tester/documentation/writer.rst.txt new file mode 100644 index 000000000..9f637032a --- /dev/null +++ b/_sources/build/ddr5_tester/documentation/writer.rst.txt @@ -0,0 +1,251 @@ +WRITER +====== + + + +DMA DRAM writer. + +Allows to fill DRAM with a predefined pattern using DMA. + +Pattern +------- + + + Provides access to RAM to store access pattern: `mem_addr` and `mem_data`. + The pattern address space can be limited using the `data_mask`. + + For example, having `mem_adr` filled with `[ 0x04, 0x02, 0x03, ... ]` + and `mem_data` filled with `[ 0xff, 0xaa, 0x55, ... ]` and setting + `data_mask = 0b01`, the pattern [(address, data), ...] written will be: + `[(0x04, 0xff), (0x02, 0xaa), (0x04, 0xff), ...]` (wraps due to masking). + + DRAM memory range that is being accessed can be configured using `mem_mask`. + + To use this module, make sure that `ready` is 1, then write the desired + number of transfers to `count`. Writing to the `start` CSR will initialize + the operation. When the operation is ongoing `ready` will be 0. + + + +Register Listing for WRITER +--------------------------- + ++------------------------------------------------------------------------+----------------------------------------------------+ +| Register | Address | ++========================================================================+====================================================+ +| :ref:`WRITER_START ` | :ref:`0xf0002800 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_READY ` | :ref:`0xf0002804 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_MODULO ` | :ref:`0xf0002808 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_COUNT ` | :ref:`0xf000280c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_DONE ` | :ref:`0xf0002810 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_MEM_MASK ` | :ref:`0xf0002814 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_DATA_MASK ` | :ref:`0xf0002818 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_DATA_DIV ` | :ref:`0xf000281c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_INVERTER_DIVISOR_MASK ` | :ref:`0xf0002820 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_INVERTER_SELECTION_MASK ` | :ref:`0xf0002824 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_LAST_ADDRESS ` | :ref:`0xf0002828 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ + +WRITER_START +^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x0 = 0xf0002800` + + Write to the register starts the transfer (if ready=1) + + .. wavedrom:: + :caption: WRITER_START + + { + "reg": [ + {"name": "start", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +WRITER_READY +^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x4 = 0xf0002804` + + Indicates that the transfer is not ongoing + + .. wavedrom:: + :caption: WRITER_READY + + { + "reg": [ + {"name": "ready", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +WRITER_MODULO +^^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x8 = 0xf0002808` + + When set use modulo to calculate DMA transfers address rather than bit masking + + .. wavedrom:: + :caption: WRITER_MODULO + + { + "reg": [ + {"name": "modulo", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +WRITER_COUNT +^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0xc = 0xf000280c` + + Desired number of DMA transfers + + .. wavedrom:: + :caption: WRITER_COUNT + + { + "reg": [ + {"name": "count[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +WRITER_DONE +^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x10 = 0xf0002810` + + Number of completed DMA transfers + + .. wavedrom:: + :caption: WRITER_DONE + + { + "reg": [ + {"name": "done[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +WRITER_MEM_MASK +^^^^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x14 = 0xf0002814` + + DRAM address mask for DMA transfers + + .. wavedrom:: + :caption: WRITER_MEM_MASK + + { + "reg": [ + {"name": "mem_mask[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +WRITER_DATA_MASK +^^^^^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x18 = 0xf0002818` + + Pattern memory address mask + + .. wavedrom:: + :caption: WRITER_DATA_MASK + + { + "reg": [ + {"name": "data_mask[4:0]", "bits": 5}, + {"bits": 27}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +WRITER_DATA_DIV +^^^^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x1c = 0xf000281c` + + Pattern memory address divisior-1 + + .. wavedrom:: + :caption: WRITER_DATA_DIV + + { + "reg": [ + {"name": "data_div[4:0]", "bits": 5}, + {"bits": 27}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +WRITER_INVERTER_DIVISOR_MASK +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x20 = 0xf0002820` + + Divisor mask for selecting rows for which pattern data gets inverted + + .. wavedrom:: + :caption: WRITER_INVERTER_DIVISOR_MASK + + { + "reg": [ + {"name": "inverter_divisor_mask[4:0]", "bits": 5}, + {"bits": 27}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +WRITER_INVERTER_SELECTION_MASK +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x24 = 0xf0002824` + + Selection mask for selecting rows for which pattern data gets inverted + + .. wavedrom:: + :caption: WRITER_INVERTER_SELECTION_MASK + + { + "reg": [ + {"name": "inverter_selection_mask[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +WRITER_LAST_ADDRESS +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x28 = 0xf0002828` + + Number of completed DMA transfers + + .. wavedrom:: + :caption: WRITER_LAST_ADDRESS + + { + "reg": [ + {"name": "last_address[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/lpddr4_test_board/documentation/controller_settings.rst.txt b/_sources/build/lpddr4_test_board/documentation/controller_settings.rst.txt new file mode 100644 index 000000000..cc67b4b83 --- /dev/null +++ b/_sources/build/lpddr4_test_board/documentation/controller_settings.rst.txt @@ -0,0 +1,34 @@ +CONTROLLER_SETTINGS +=================== + +Allows to change LiteDRAMController behaviour at runtime +-------------------------------------------------------- + + +Register Listing for CONTROLLER_SETTINGS +---------------------------------------- + ++------------------------------------------------------------------+-------------------------------------------------+ +| Register | Address | ++==================================================================+=================================================+ +| :ref:`CONTROLLER_SETTINGS_REFRESH ` | :ref:`0xf0001000 ` | ++------------------------------------------------------------------+-------------------------------------------------+ + +CONTROLLER_SETTINGS_REFRESH +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0001000 + 0x0 = 0xf0001000` + + Enable/disable Refresh commands sending + + .. wavedrom:: + :caption: CONTROLLER_SETTINGS_REFRESH + + { + "reg": [ + {"name": "refresh", "attr": 'reset: 1', "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/lpddr4_test_board/documentation/ctrl.rst.txt b/_sources/build/lpddr4_test_board/documentation/ctrl.rst.txt new file mode 100644 index 000000000..ca08edbd0 --- /dev/null +++ b/_sources/build/lpddr4_test_board/documentation/ctrl.rst.txt @@ -0,0 +1,78 @@ +CTRL +==== + +Register Listing for CTRL +------------------------- + ++------------------------------------------+-------------------------------------+ +| Register | Address | ++==========================================+=====================================+ +| :ref:`CTRL__RESET ` | :ref:`0xf0004800 ` | ++------------------------------------------+-------------------------------------+ +| :ref:`CTRL_SCRATCH ` | :ref:`0xf0004804 ` | ++------------------------------------------+-------------------------------------+ +| :ref:`CTRL_BUS_ERRORS ` | :ref:`0xf0004808 ` | ++------------------------------------------+-------------------------------------+ + +CTRL__RESET +^^^^^^^^^^^ + +`Address: 0xf0004800 + 0x0 = 0xf0004800` + + + .. wavedrom:: + :caption: CTRL__RESET + + { + "reg": [ + {"name": "soc_rst", "type": 4, "bits": 1}, + {"name": "cpu_rst", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+---------+------------------------------------------------------------------------+ +| Field | Name | Description | ++=======+=========+========================================================================+ +| [0] | SOC_RST | Write `1` to this register to reset the full SoC (Pulse Reset) | ++-------+---------+------------------------------------------------------------------------+ +| [1] | CPU_RST | Write `1` to this register to reset the CPU(s) of the SoC (Hold Reset) | ++-------+---------+------------------------------------------------------------------------+ + +CTRL_SCRATCH +^^^^^^^^^^^^ + +`Address: 0xf0004800 + 0x4 = 0xf0004804` + + Use this register as a scratch space to verify that software read/write accesses + to the Wishbone/CSR bus are working correctly. The initial reset value of + 0x1234578 can be used to verify endianness. + + .. wavedrom:: + :caption: CTRL_SCRATCH + + { + "reg": [ + {"name": "scratch[31:0]", "attr": 'reset: 305419896', "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +CTRL_BUS_ERRORS +^^^^^^^^^^^^^^^ + +`Address: 0xf0004800 + 0x8 = 0xf0004808` + + Total number of Wishbone bus errors (timeouts) since start. + + .. wavedrom:: + :caption: CTRL_BUS_ERRORS + + { + "reg": [ + {"name": "bus_errors[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/lpddr4_test_board/documentation/ddrctrl.rst.txt b/_sources/build/lpddr4_test_board/documentation/ddrctrl.rst.txt new file mode 100644 index 000000000..59563d8b1 --- /dev/null +++ b/_sources/build/lpddr4_test_board/documentation/ddrctrl.rst.txt @@ -0,0 +1,48 @@ +DDRCTRL +======= + +Register Listing for DDRCTRL +---------------------------- + ++------------------------------------------------+----------------------------------------+ +| Register | Address | ++================================================+========================================+ +| :ref:`DDRCTRL_INIT_DONE ` | :ref:`0xf0001800 ` | ++------------------------------------------------+----------------------------------------+ +| :ref:`DDRCTRL_INIT_ERROR ` | :ref:`0xf0001804 ` | ++------------------------------------------------+----------------------------------------+ + +DDRCTRL_INIT_DONE +^^^^^^^^^^^^^^^^^ + +`Address: 0xf0001800 + 0x0 = 0xf0001800` + + + .. wavedrom:: + :caption: DDRCTRL_INIT_DONE + + { + "reg": [ + {"name": "init_done", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRCTRL_INIT_ERROR +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0001800 + 0x4 = 0xf0001804` + + + .. wavedrom:: + :caption: DDRCTRL_INIT_ERROR + + { + "reg": [ + {"name": "init_error", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/lpddr4_test_board/documentation/ddrphy.rst.txt b/_sources/build/lpddr4_test_board/documentation/ddrphy.rst.txt new file mode 100644 index 000000000..e9b347b12 --- /dev/null +++ b/_sources/build/lpddr4_test_board/documentation/ddrphy.rst.txt @@ -0,0 +1,409 @@ +DDRPHY +====== + +Register Listing for DDRPHY +--------------------------- + ++----------------------------------------------------------------+------------------------------------------------+ +| Register | Address | ++================================================================+================================================+ +| :ref:`DDRPHY_RST ` | :ref:`0xf0000800 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_WLEVEL_EN ` | :ref:`0xf0000804 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_WLEVEL_STROBE ` | :ref:`0xf0000808 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_DLY_SEL ` | :ref:`0xf000080c ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_RDLY_DQ_BITSLIP_RST ` | :ref:`0xf0000810 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_RDLY_DQ_BITSLIP ` | :ref:`0xf0000814 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_WDLY_DQ_BITSLIP_RST ` | :ref:`0xf0000818 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_WDLY_DQ_BITSLIP ` | :ref:`0xf000081c ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_RDPHASE ` | :ref:`0xf0000820 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_WRPHASE ` | :ref:`0xf0000824 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_HALF_SYS8X_TAPS ` | :ref:`0xf0000828 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_RDLY_DQ_RST ` | :ref:`0xf000082c ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_RDLY_DQ_INC ` | :ref:`0xf0000830 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_RDLY_DQS_RST ` | :ref:`0xf0000834 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_RDLY_DQS_INC ` | :ref:`0xf0000838 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_CDLY_RST ` | :ref:`0xf000083c ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_CDLY_INC ` | :ref:`0xf0000840 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_WDLY_DQ_RST ` | :ref:`0xf0000844 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_WDLY_DQ_INC ` | :ref:`0xf0000848 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_WDLY_DQS_RST ` | :ref:`0xf000084c ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_WDLY_DQS_INC ` | :ref:`0xf0000850 ` | ++----------------------------------------------------------------+------------------------------------------------+ + +DDRPHY_RST +^^^^^^^^^^ + +`Address: 0xf0000800 + 0x0 = 0xf0000800` + + + .. wavedrom:: + :caption: DDRPHY_RST + + { + "reg": [ + {"name": "rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_WLEVEL_EN +^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x4 = 0xf0000804` + + + .. wavedrom:: + :caption: DDRPHY_WLEVEL_EN + + { + "reg": [ + {"name": "wlevel_en", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_WLEVEL_STROBE +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x8 = 0xf0000808` + + + .. wavedrom:: + :caption: DDRPHY_WLEVEL_STROBE + + { + "reg": [ + {"name": "wlevel_strobe", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_DLY_SEL +^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xc = 0xf000080c` + + + .. wavedrom:: + :caption: DDRPHY_DLY_SEL + + { + "reg": [ + {"name": "dly_sel[1:0]", "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_RDLY_DQ_BITSLIP_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x10 = 0xf0000810` + + + .. wavedrom:: + :caption: DDRPHY_RDLY_DQ_BITSLIP_RST + + { + "reg": [ + {"name": "rdly_dq_bitslip_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_RDLY_DQ_BITSLIP +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x14 = 0xf0000814` + + + .. wavedrom:: + :caption: DDRPHY_RDLY_DQ_BITSLIP + + { + "reg": [ + {"name": "rdly_dq_bitslip", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_WDLY_DQ_BITSLIP_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x18 = 0xf0000818` + + + .. wavedrom:: + :caption: DDRPHY_WDLY_DQ_BITSLIP_RST + + { + "reg": [ + {"name": "wdly_dq_bitslip_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_WDLY_DQ_BITSLIP +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x1c = 0xf000081c` + + + .. wavedrom:: + :caption: DDRPHY_WDLY_DQ_BITSLIP + + { + "reg": [ + {"name": "wdly_dq_bitslip", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_RDPHASE +^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x20 = 0xf0000820` + + + .. wavedrom:: + :caption: DDRPHY_RDPHASE + + { + "reg": [ + {"name": "rdphase[2:0]", "attr": 'reset: 6', "bits": 3}, + {"bits": 29}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_WRPHASE +^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x24 = 0xf0000824` + + + .. wavedrom:: + :caption: DDRPHY_WRPHASE + + { + "reg": [ + {"name": "wrphase[2:0]", "attr": 'reset: 6', "bits": 3}, + {"bits": 29}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_HALF_SYS8X_TAPS +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x28 = 0xf0000828` + + + .. wavedrom:: + :caption: DDRPHY_HALF_SYS8X_TAPS + + { + "reg": [ + {"name": "half_sys8x_taps[4:0]", "attr": 'reset: 8', "bits": 5}, + {"bits": 27}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_RDLY_DQ_RST +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x2c = 0xf000082c` + + + .. wavedrom:: + :caption: DDRPHY_RDLY_DQ_RST + + { + "reg": [ + {"name": "rdly_dq_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_RDLY_DQ_INC +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x30 = 0xf0000830` + + + .. wavedrom:: + :caption: DDRPHY_RDLY_DQ_INC + + { + "reg": [ + {"name": "rdly_dq_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_RDLY_DQS_RST +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x34 = 0xf0000834` + + + .. wavedrom:: + :caption: DDRPHY_RDLY_DQS_RST + + { + "reg": [ + {"name": "rdly_dqs_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_RDLY_DQS_INC +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x38 = 0xf0000838` + + + .. wavedrom:: + :caption: DDRPHY_RDLY_DQS_INC + + { + "reg": [ + {"name": "rdly_dqs_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CDLY_RST +^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x3c = 0xf000083c` + + + .. wavedrom:: + :caption: DDRPHY_CDLY_RST + + { + "reg": [ + {"name": "cdly_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CDLY_INC +^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x40 = 0xf0000840` + + + .. wavedrom:: + :caption: DDRPHY_CDLY_INC + + { + "reg": [ + {"name": "cdly_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_WDLY_DQ_RST +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x44 = 0xf0000844` + + + .. wavedrom:: + :caption: DDRPHY_WDLY_DQ_RST + + { + "reg": [ + {"name": "wdly_dq_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_WDLY_DQ_INC +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x48 = 0xf0000848` + + + .. wavedrom:: + :caption: DDRPHY_WDLY_DQ_INC + + { + "reg": [ + {"name": "wdly_dq_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_WDLY_DQS_RST +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x4c = 0xf000084c` + + + .. wavedrom:: + :caption: DDRPHY_WDLY_DQS_RST + + { + "reg": [ + {"name": "wdly_dqs_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_WDLY_DQS_INC +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x50 = 0xf0000850` + + + .. wavedrom:: + :caption: DDRPHY_WDLY_DQS_INC + + { + "reg": [ + {"name": "wdly_dqs_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/lpddr4_test_board/documentation/dfi_switch.rst.txt b/_sources/build/lpddr4_test_board/documentation/dfi_switch.rst.txt new file mode 100644 index 000000000..718d8cc34 --- /dev/null +++ b/_sources/build/lpddr4_test_board/documentation/dfi_switch.rst.txt @@ -0,0 +1,71 @@ +DFI_SWITCH +========== + +Register Listing for DFI_SWITCH +------------------------------- + ++--------------------------------------------------------------+-----------------------------------------------+ +| Register | Address | ++==============================================================+===============================================+ +| :ref:`DFI_SWITCH_REFRESH_COUNT ` | :ref:`0xf0003800 ` | ++--------------------------------------------------------------+-----------------------------------------------+ +| :ref:`DFI_SWITCH_AT_REFRESH ` | :ref:`0xf0003804 ` | ++--------------------------------------------------------------+-----------------------------------------------+ +| :ref:`DFI_SWITCH_REFRESH_UPDATE ` | :ref:`0xf0003808 ` | ++--------------------------------------------------------------+-----------------------------------------------+ + +DFI_SWITCH_REFRESH_COUNT +^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003800 + 0x0 = 0xf0003800` + + Count of all refresh commands issued (both by Memory Controller and Payload + Executor). Value is latched from internal counter on mode trasition: MC -> PE or + by writing to the `refresh_update` CSR. + + .. wavedrom:: + :caption: DFI_SWITCH_REFRESH_COUNT + + { + "reg": [ + {"name": "refresh_count[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DFI_SWITCH_AT_REFRESH +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003800 + 0x4 = 0xf0003804` + + If set to a value different than 0 the mode transition MC -> PE will be peformed + only when the value of this register matches the current refresh commands count. + + .. wavedrom:: + :caption: DFI_SWITCH_AT_REFRESH + + { + "reg": [ + {"name": "at_refresh[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DFI_SWITCH_REFRESH_UPDATE +^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003800 + 0x8 = 0xf0003808` + + Force an update of the `refresh_count` CSR. + + .. wavedrom:: + :caption: DFI_SWITCH_REFRESH_UPDATE + + { + "reg": [ + {"name": "refresh_update", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/lpddr4_test_board/documentation/ethphy.rst.txt b/_sources/build/lpddr4_test_board/documentation/ethphy.rst.txt new file mode 100644 index 000000000..f917d9907 --- /dev/null +++ b/_sources/build/lpddr4_test_board/documentation/ethphy.rst.txt @@ -0,0 +1,81 @@ +ETHPHY +====== + +Register Listing for ETHPHY +--------------------------- + ++--------------------------------------------+--------------------------------------+ +| Register | Address | ++============================================+======================================+ +| :ref:`ETHPHY_CRG_RESET ` | :ref:`0xf0005000 ` | ++--------------------------------------------+--------------------------------------+ +| :ref:`ETHPHY_MDIO_W ` | :ref:`0xf0005004 ` | ++--------------------------------------------+--------------------------------------+ +| :ref:`ETHPHY_MDIO_R ` | :ref:`0xf0005008 ` | ++--------------------------------------------+--------------------------------------+ + +ETHPHY_CRG_RESET +^^^^^^^^^^^^^^^^ + +`Address: 0xf0005000 + 0x0 = 0xf0005000` + + + .. wavedrom:: + :caption: ETHPHY_CRG_RESET + + { + "reg": [ + {"name": "crg_reset", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +ETHPHY_MDIO_W +^^^^^^^^^^^^^ + +`Address: 0xf0005000 + 0x4 = 0xf0005004` + + + .. wavedrom:: + :caption: ETHPHY_MDIO_W + + { + "reg": [ + {"name": "mdc", "bits": 1}, + {"name": "oe", "bits": 1}, + {"name": "w", "bits": 1}, + {"bits": 29} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------+ +| Field | Name | Description | ++=======+======+=============+ ++-------+------+-------------+ ++-------+------+-------------+ ++-------+------+-------------+ + +ETHPHY_MDIO_R +^^^^^^^^^^^^^ + +`Address: 0xf0005000 + 0x8 = 0xf0005008` + + + .. wavedrom:: + :caption: ETHPHY_MDIO_R + + { + "reg": [ + {"name": "r", "bits": 1}, + {"bits": 31} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------+ +| Field | Name | Description | ++=======+======+=============+ ++-------+------+-------------+ + diff --git a/_sources/build/lpddr4_test_board/documentation/identifier_mem.rst.txt b/_sources/build/lpddr4_test_board/documentation/identifier_mem.rst.txt new file mode 100644 index 000000000..285bccdc0 --- /dev/null +++ b/_sources/build/lpddr4_test_board/documentation/identifier_mem.rst.txt @@ -0,0 +1,30 @@ +IDENTIFIER_MEM +============== + +Register Listing for IDENTIFIER_MEM +----------------------------------- + ++----------------------------------------+------------------------------------+ +| Register | Address | ++========================================+====================================+ +| :ref:`IDENTIFIER_MEM ` | :ref:`0xf0005800 ` | ++----------------------------------------+------------------------------------+ + +IDENTIFIER_MEM +^^^^^^^^^^^^^^ + +`Address: 0xf0005800 + 0x0 = 0xf0005800` + + 8 x 108-bit memory + + .. wavedrom:: + :caption: IDENTIFIER_MEM + + { + "reg": [ + {"name": "identifier_mem[7:0]", "bits": 8}, + {"bits": 24}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/lpddr4_test_board/documentation/index.rst.txt b/_sources/build/lpddr4_test_board/documentation/index.rst.txt new file mode 100644 index 000000000..cd64bdbbd --- /dev/null +++ b/_sources/build/lpddr4_test_board/documentation/index.rst.txt @@ -0,0 +1,37 @@ +===================================================== +Documentation for Row Hammer Tester LPDDR4 Test Board +===================================================== + + + +Modules +======= + +.. toctree:: + :maxdepth: 1 + + interrupts + +Register Groups +=============== + +.. toctree:: + :maxdepth: 1 + + leds + ddrphy + controller_settings + ddrctrl + rowhammer + writer + reader + dfi_switch + payload_executor + ctrl + ethphy + identifier_mem + sdram + sdram_checker + sdram_generator + timer0 + uart diff --git a/_sources/build/lpddr4_test_board/documentation/interrupts.rst.txt b/_sources/build/lpddr4_test_board/documentation/interrupts.rst.txt new file mode 100644 index 000000000..bfc948fb1 --- /dev/null +++ b/_sources/build/lpddr4_test_board/documentation/interrupts.rst.txt @@ -0,0 +1,22 @@ +Interrupt Controller +==================== + +This device has an ``EventManager``-based interrupt system. Individual modules +generate `events` which are wired into a central interrupt controller. + +When an interrupt occurs, you should look the interrupt number up in the CPU- +specific interrupt table and then call the relevant module. + +Assigned Interrupts +------------------- + +The following interrupts are assigned on this system: + ++-----------+------------------------+ +| Interrupt | Module | ++===========+========================+ +| 1 | :doc:`TIMER0 ` | ++-----------+------------------------+ +| 0 | :doc:`UART ` | ++-----------+------------------------+ + diff --git a/_sources/build/lpddr4_test_board/documentation/leds.rst.txt b/_sources/build/lpddr4_test_board/documentation/leds.rst.txt new file mode 100644 index 000000000..7d5de2ee2 --- /dev/null +++ b/_sources/build/lpddr4_test_board/documentation/leds.rst.txt @@ -0,0 +1,30 @@ +LEDS +==== + +Register Listing for LEDS +------------------------- + ++----------------------------+------------------------------+ +| Register | Address | ++============================+==============================+ +| :ref:`LEDS_OUT ` | :ref:`0xf0000000 ` | ++----------------------------+------------------------------+ + +LEDS_OUT +^^^^^^^^ + +`Address: 0xf0000000 + 0x0 = 0xf0000000` + + Led Output(s) Control. + + .. wavedrom:: + :caption: LEDS_OUT + + { + "reg": [ + {"name": "out[4:0]", "bits": 5}, + {"bits": 27}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/lpddr4_test_board/documentation/payload_executor.rst.txt b/_sources/build/lpddr4_test_board/documentation/payload_executor.rst.txt new file mode 100644 index 000000000..96fce0378 --- /dev/null +++ b/_sources/build/lpddr4_test_board/documentation/payload_executor.rst.txt @@ -0,0 +1,137 @@ +PAYLOAD_EXECUTOR +================ + + + + Executes the DRAM payload from memory + + + **Instruction decoder** + + All instructions are 32-bit. The format of most instructions is the same, + except for the LOOP instruction, which has a constant TIMESLICE of 1. + + NOOP with a TIMESLICE of 0 is a special case which is interpreted as + STOP instruction. When this instruction is encountered execution gets + finished immediately. + + **NOTE:** TIMESLICE is the number of cycles the instruction will take. This + means that instructions other than NOOP that use TIMESLICE=0 are illegal + (although will silently be executed as having TIMESLICE=1). + + **NOTE2:** LOOP instruction will *jump* COUNT times, meaning that the "code" + inside the loop will effectively be executed COUNT+1 times. + + Op codes: + ++------+-------+ ++ Op + Value + ++======+=======+ ++ NOOP | 0b000 + ++------+-------+ ++ LOOP | 0b111 + ++------+-------+ ++ ACT | 0b100 + ++------+-------+ ++ PRE | 0b101 + ++------+-------+ ++ REF | 0b110 + ++------+-------+ ++ ZQC | 0b001 + ++------+-------+ ++ READ | 0b010 + ++------+-------+ + + Instruction format:: + + LSB MSB + dfi: OP_CODE | TIMESLICE | ADDRESS + noop: OP_CODE | TIMESLICE_NOOP + loop: OP_CODE | COUNT | JUMP + stop: | 0 + + Where ADDRESS depends on the DFI command and is one of:: + + LSB MSB + RANK | BANK | COLUMN + RANK | BANK | ROW + + + +Register Listing for PAYLOAD_EXECUTOR +------------------------------------- + ++------------------------------------------------------------------+-------------------------------------------------+ +| Register | Address | ++==================================================================+=================================================+ +| :ref:`PAYLOAD_EXECUTOR_START ` | :ref:`0xf0004000 ` | ++------------------------------------------------------------------+-------------------------------------------------+ +| :ref:`PAYLOAD_EXECUTOR_STATUS ` | :ref:`0xf0004004 ` | ++------------------------------------------------------------------+-------------------------------------------------+ +| :ref:`PAYLOAD_EXECUTOR_READ_COUNT ` | :ref:`0xf0004008 ` | ++------------------------------------------------------------------+-------------------------------------------------+ + +PAYLOAD_EXECUTOR_START +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0004000 + 0x0 = 0xf0004000` + + Writing to this register initializes payload execution + + .. wavedrom:: + :caption: PAYLOAD_EXECUTOR_START + + { + "reg": [ + {"name": "start", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +PAYLOAD_EXECUTOR_STATUS +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0004000 + 0x4 = 0xf0004004` + + Payload executor status register + + .. wavedrom:: + :caption: PAYLOAD_EXECUTOR_STATUS + + { + "reg": [ + {"name": "ready", "bits": 1}, + {"name": "overflow", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+----------+---------------------------------------------------------------------------------+ +| Field | Name | Description | ++=======+==========+=================================================================================+ +| [0] | READY | Indicates that the executor is not running | ++-------+----------+---------------------------------------------------------------------------------+ +| [1] | OVERFLOW | Indicates the scratchpad memory address counter has overflown due to the number | +| | | of READ commands sent during execution | ++-------+----------+---------------------------------------------------------------------------------+ + +PAYLOAD_EXECUTOR_READ_COUNT +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0004000 + 0x8 = 0xf0004008` + + Number of data from READ commands that is stored in the scratchpad memory + + .. wavedrom:: + :caption: PAYLOAD_EXECUTOR_READ_COUNT + + { + "reg": [ + {"name": "read_count[4:0]", "bits": 5}, + {"bits": 27}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/lpddr4_test_board/documentation/reader.rst.txt b/_sources/build/lpddr4_test_board/documentation/reader.rst.txt new file mode 100644 index 000000000..116392e53 --- /dev/null +++ b/_sources/build/lpddr4_test_board/documentation/reader.rst.txt @@ -0,0 +1,652 @@ +READER +====== + + + +DMA DRAM reader. + +Allows to check DRAM contents against a predefined pattern using DMA. + +Pattern +------- + + + Provides access to RAM to store access pattern: `mem_addr` and `mem_data`. + The pattern address space can be limited using the `data_mask`. + + For example, having `mem_adr` filled with `[ 0x04, 0x02, 0x03, ... ]` + and `mem_data` filled with `[ 0xff, 0xaa, 0x55, ... ]` and setting + `data_mask = 0b01`, the pattern [(address, data), ...] written will be: + `[(0x04, 0xff), (0x02, 0xaa), (0x04, 0xff), ...]` (wraps due to masking). + + DRAM memory range that is being accessed can be configured using `mem_mask`. + + To use this module, make sure that `ready` is 1, then write the desired + number of transfers to `count`. Writing to the `start` CSR will initialize + the operation. When the operation is ongoing `ready` will be 0. + + +Reading errors +-------------- + +This module allows to check the locations of errors in the memory. +It scans the configured memory area and compares the values read to +the predefined pattern. If `skip_fifo` is 0, this module will stop +after each error encountered, so that it can be examined. Wait until +the `error_ready` CSR is 1. Then use the CSRs `error_offset`, +`error_data` and `error_expected` to examine the errors in the current +transfer. To continue reading, write 1 to `error_continue` CSR. +Setting `skip_fifo` to 1 will disable this behaviour entirely. + +The final number of errors can be read from `error_count`. +NOTE: This value represents the number of erroneous *DMA transfers*. + +The current progress can be read from the `done` CSR. + + +Register Listing for READER +--------------------------- + ++------------------------------------------------------------------------+----------------------------------------------------+ +| Register | Address | ++========================================================================+====================================================+ +| :ref:`READER_START ` | :ref:`0xf0003000 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_READY ` | :ref:`0xf0003004 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_MODULO ` | :ref:`0xf0003008 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_COUNT ` | :ref:`0xf000300c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_DONE ` | :ref:`0xf0003010 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_MEM_MASK ` | :ref:`0xf0003014 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_DATA_MASK ` | :ref:`0xf0003018 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_DATA_DIV ` | :ref:`0xf000301c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_INVERTER_DIVISOR_MASK ` | :ref:`0xf0003020 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_INVERTER_SELECTION_MASK ` | :ref:`0xf0003024 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_COUNT ` | :ref:`0xf0003028 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_SKIP_FIFO ` | :ref:`0xf000302c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_OFFSET ` | :ref:`0xf0003030 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA7 ` | :ref:`0xf0003034 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA6 ` | :ref:`0xf0003038 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA5 ` | :ref:`0xf000303c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA4 ` | :ref:`0xf0003040 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA3 ` | :ref:`0xf0003044 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA2 ` | :ref:`0xf0003048 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA1 ` | :ref:`0xf000304c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA0 ` | :ref:`0xf0003050 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED7 ` | :ref:`0xf0003054 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED6 ` | :ref:`0xf0003058 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED5 ` | :ref:`0xf000305c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED4 ` | :ref:`0xf0003060 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED3 ` | :ref:`0xf0003064 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED2 ` | :ref:`0xf0003068 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED1 ` | :ref:`0xf000306c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED0 ` | :ref:`0xf0003070 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_READY ` | :ref:`0xf0003074 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_CONTINUE ` | :ref:`0xf0003078 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ + +READER_START +^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x0 = 0xf0003000` + + Write to the register starts the transfer (if ready=1) + + .. wavedrom:: + :caption: READER_START + + { + "reg": [ + {"name": "start", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_READY +^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x4 = 0xf0003004` + + Indicates that the transfer is not ongoing + + .. wavedrom:: + :caption: READER_READY + + { + "reg": [ + {"name": "ready", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_MODULO +^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x8 = 0xf0003008` + + When set use modulo to calculate DMA transfers address rather than bit masking + + .. wavedrom:: + :caption: READER_MODULO + + { + "reg": [ + {"name": "modulo", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_COUNT +^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0xc = 0xf000300c` + + Desired number of DMA transfers + + .. wavedrom:: + :caption: READER_COUNT + + { + "reg": [ + {"name": "count[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_DONE +^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x10 = 0xf0003010` + + Number of completed DMA transfers + + .. wavedrom:: + :caption: READER_DONE + + { + "reg": [ + {"name": "done[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_MEM_MASK +^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x14 = 0xf0003014` + + DRAM address mask for DMA transfers + + .. wavedrom:: + :caption: READER_MEM_MASK + + { + "reg": [ + {"name": "mem_mask[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_DATA_MASK +^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x18 = 0xf0003018` + + Pattern memory address mask + + .. wavedrom:: + :caption: READER_DATA_MASK + + { + "reg": [ + {"name": "data_mask[4:0]", "bits": 5}, + {"bits": 27}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_DATA_DIV +^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x1c = 0xf000301c` + + Pattern memory address divisior-1 + + .. wavedrom:: + :caption: READER_DATA_DIV + + { + "reg": [ + {"name": "data_div[4:0]", "bits": 5}, + {"bits": 27}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_INVERTER_DIVISOR_MASK +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x20 = 0xf0003020` + + Divisor mask for selecting rows for which pattern data gets inverted + + .. wavedrom:: + :caption: READER_INVERTER_DIVISOR_MASK + + { + "reg": [ + {"name": "inverter_divisor_mask[4:0]", "bits": 5}, + {"bits": 27}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_INVERTER_SELECTION_MASK +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x24 = 0xf0003024` + + Selection mask for selecting rows for which pattern data gets inverted + + .. wavedrom:: + :caption: READER_INVERTER_SELECTION_MASK + + { + "reg": [ + {"name": "inverter_selection_mask[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_COUNT +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x28 = 0xf0003028` + + Number of errors detected + + .. wavedrom:: + :caption: READER_ERROR_COUNT + + { + "reg": [ + {"name": "error_count[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_SKIP_FIFO +^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x2c = 0xf000302c` + + Skip waiting for user to read the errors FIFO + + .. wavedrom:: + :caption: READER_SKIP_FIFO + + { + "reg": [ + {"name": "skip_fifo", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_ERROR_OFFSET +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x30 = 0xf0003030` + + Current offset of the error + + .. wavedrom:: + :caption: READER_ERROR_OFFSET + + { + "reg": [ + {"name": "error_offset[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA7 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x34 = 0xf0003034` + + Bits 224-255 of `READER_ERROR_DATA`. Erroneous value read from DRAM memory + + .. wavedrom:: + :caption: READER_ERROR_DATA7 + + { + "reg": [ + {"name": "error_data[255:224]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA6 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x38 = 0xf0003038` + + Bits 192-223 of `READER_ERROR_DATA`. + + .. wavedrom:: + :caption: READER_ERROR_DATA6 + + { + "reg": [ + {"name": "error_data[223:192]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA5 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x3c = 0xf000303c` + + Bits 160-191 of `READER_ERROR_DATA`. + + .. wavedrom:: + :caption: READER_ERROR_DATA5 + + { + "reg": [ + {"name": "error_data[191:160]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA4 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x40 = 0xf0003040` + + Bits 128-159 of `READER_ERROR_DATA`. + + .. wavedrom:: + :caption: READER_ERROR_DATA4 + + { + "reg": [ + {"name": "error_data[159:128]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA3 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x44 = 0xf0003044` + + Bits 96-127 of `READER_ERROR_DATA`. + + .. wavedrom:: + :caption: READER_ERROR_DATA3 + + { + "reg": [ + {"name": "error_data[127:96]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA2 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x48 = 0xf0003048` + + Bits 64-95 of `READER_ERROR_DATA`. + + .. wavedrom:: + :caption: READER_ERROR_DATA2 + + { + "reg": [ + {"name": "error_data[95:64]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA1 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x4c = 0xf000304c` + + Bits 32-63 of `READER_ERROR_DATA`. + + .. wavedrom:: + :caption: READER_ERROR_DATA1 + + { + "reg": [ + {"name": "error_data[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA0 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x50 = 0xf0003050` + + Bits 0-31 of `READER_ERROR_DATA`. + + .. wavedrom:: + :caption: READER_ERROR_DATA0 + + { + "reg": [ + {"name": "error_data[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED7 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x54 = 0xf0003054` + + Bits 224-255 of `READER_ERROR_EXPECTED`. Value expected to be read from DRAM + memory + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED7 + + { + "reg": [ + {"name": "error_expected[255:224]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED6 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x58 = 0xf0003058` + + Bits 192-223 of `READER_ERROR_EXPECTED`. + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED6 + + { + "reg": [ + {"name": "error_expected[223:192]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED5 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x5c = 0xf000305c` + + Bits 160-191 of `READER_ERROR_EXPECTED`. + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED5 + + { + "reg": [ + {"name": "error_expected[191:160]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED4 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x60 = 0xf0003060` + + Bits 128-159 of `READER_ERROR_EXPECTED`. + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED4 + + { + "reg": [ + {"name": "error_expected[159:128]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED3 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x64 = 0xf0003064` + + Bits 96-127 of `READER_ERROR_EXPECTED`. + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED3 + + { + "reg": [ + {"name": "error_expected[127:96]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED2 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x68 = 0xf0003068` + + Bits 64-95 of `READER_ERROR_EXPECTED`. + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED2 + + { + "reg": [ + {"name": "error_expected[95:64]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED1 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x6c = 0xf000306c` + + Bits 32-63 of `READER_ERROR_EXPECTED`. + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED1 + + { + "reg": [ + {"name": "error_expected[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED0 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x70 = 0xf0003070` + + Bits 0-31 of `READER_ERROR_EXPECTED`. + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED0 + + { + "reg": [ + {"name": "error_expected[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_READY +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x74 = 0xf0003074` + + Error detected and ready to read + + .. wavedrom:: + :caption: READER_ERROR_READY + + { + "reg": [ + {"name": "error_ready", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_ERROR_CONTINUE +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x78 = 0xf0003078` + + Continue reading until the next error + + .. wavedrom:: + :caption: READER_ERROR_CONTINUE + + { + "reg": [ + {"name": "error_continue", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/lpddr4_test_board/documentation/rowhammer.rst.txt b/_sources/build/lpddr4_test_board/documentation/rowhammer.rst.txt new file mode 100644 index 000000000..c82043545 --- /dev/null +++ b/_sources/build/lpddr4_test_board/documentation/rowhammer.rst.txt @@ -0,0 +1,102 @@ +ROWHAMMER +========= + + + +Row Hammer DMA attacker + +This module allows to perform a Row Hammer attack by configuring it with +two addresses that map to different rows of a single bank. When enabled, +it will perform alternating DMA reads from the given locations, which will +result in the DRAM controller having to repeatedly open/close rows at each +read access. + + +Register Listing for ROWHAMMER +------------------------------ + ++------------------------------------------------+----------------------------------------+ +| Register | Address | ++================================================+========================================+ +| :ref:`ROWHAMMER_ENABLED ` | :ref:`0xf0002000 ` | ++------------------------------------------------+----------------------------------------+ +| :ref:`ROWHAMMER_ADDRESS1 ` | :ref:`0xf0002004 ` | ++------------------------------------------------+----------------------------------------+ +| :ref:`ROWHAMMER_ADDRESS2 ` | :ref:`0xf0002008 ` | ++------------------------------------------------+----------------------------------------+ +| :ref:`ROWHAMMER_COUNT ` | :ref:`0xf000200c ` | ++------------------------------------------------+----------------------------------------+ + +ROWHAMMER_ENABLED +^^^^^^^^^^^^^^^^^ + +`Address: 0xf0002000 + 0x0 = 0xf0002000` + + Used to start/stop the operation of the module + + .. wavedrom:: + :caption: ROWHAMMER_ENABLED + + { + "reg": [ + {"name": "enabled", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +ROWHAMMER_ADDRESS1 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0002000 + 0x4 = 0xf0002004` + + First attacked address + + .. wavedrom:: + :caption: ROWHAMMER_ADDRESS1 + + { + "reg": [ + {"name": "address1[23:0]", "bits": 24}, + {"bits": 8}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +ROWHAMMER_ADDRESS2 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0002000 + 0x8 = 0xf0002008` + + Second attacked address + + .. wavedrom:: + :caption: ROWHAMMER_ADDRESS2 + + { + "reg": [ + {"name": "address2[23:0]", "bits": 24}, + {"bits": 8}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +ROWHAMMER_COUNT +^^^^^^^^^^^^^^^ + +`Address: 0xf0002000 + 0xc = 0xf000200c` + + This is the number of DMA accesses performed. When the module is enabled, the + value can be freely read. When the module is disabled, the register is clear-on- + write and has to be read before the next attack. + + .. wavedrom:: + :caption: ROWHAMMER_COUNT + + { + "reg": [ + {"name": "count[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/lpddr4_test_board/documentation/sdram.rst.txt b/_sources/build/lpddr4_test_board/documentation/sdram.rst.txt new file mode 100644 index 000000000..5885acb88 --- /dev/null +++ b/_sources/build/lpddr4_test_board/documentation/sdram.rst.txt @@ -0,0 +1,1708 @@ +SDRAM +===== + +Register Listing for SDRAM +-------------------------- + ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| Register | Address | ++================================================================================+========================================================+ +| :ref:`SDRAM_DFII_CONTROL ` | :ref:`0xf0006000 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI0_COMMAND ` | :ref:`0xf0006004 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI0_COMMAND_ISSUE ` | :ref:`0xf0006008 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI0_ADDRESS ` | :ref:`0xf000600c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI0_BADDRESS ` | :ref:`0xf0006010 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI0_WRDATA ` | :ref:`0xf0006014 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI0_RDDATA ` | :ref:`0xf0006018 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI1_COMMAND ` | :ref:`0xf000601c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI1_COMMAND_ISSUE ` | :ref:`0xf0006020 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI1_ADDRESS ` | :ref:`0xf0006024 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI1_BADDRESS ` | :ref:`0xf0006028 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI1_WRDATA ` | :ref:`0xf000602c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI1_RDDATA ` | :ref:`0xf0006030 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI2_COMMAND ` | :ref:`0xf0006034 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI2_COMMAND_ISSUE ` | :ref:`0xf0006038 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI2_ADDRESS ` | :ref:`0xf000603c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI2_BADDRESS ` | :ref:`0xf0006040 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI2_WRDATA ` | :ref:`0xf0006044 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI2_RDDATA ` | :ref:`0xf0006048 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI3_COMMAND ` | :ref:`0xf000604c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI3_COMMAND_ISSUE ` | :ref:`0xf0006050 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI3_ADDRESS ` | :ref:`0xf0006054 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI3_BADDRESS ` | :ref:`0xf0006058 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI3_WRDATA ` | :ref:`0xf000605c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI3_RDDATA ` | :ref:`0xf0006060 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI4_COMMAND ` | :ref:`0xf0006064 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI4_COMMAND_ISSUE ` | :ref:`0xf0006068 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI4_ADDRESS ` | :ref:`0xf000606c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI4_BADDRESS ` | :ref:`0xf0006070 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI4_WRDATA ` | :ref:`0xf0006074 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI4_RDDATA ` | :ref:`0xf0006078 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI5_COMMAND ` | :ref:`0xf000607c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI5_COMMAND_ISSUE ` | :ref:`0xf0006080 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI5_ADDRESS ` | :ref:`0xf0006084 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI5_BADDRESS ` | :ref:`0xf0006088 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI5_WRDATA ` | :ref:`0xf000608c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI5_RDDATA ` | :ref:`0xf0006090 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI6_COMMAND ` | :ref:`0xf0006094 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI6_COMMAND_ISSUE ` | :ref:`0xf0006098 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI6_ADDRESS ` | :ref:`0xf000609c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI6_BADDRESS ` | :ref:`0xf00060a0 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI6_WRDATA ` | :ref:`0xf00060a4 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI6_RDDATA ` | :ref:`0xf00060a8 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI7_COMMAND ` | :ref:`0xf00060ac ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI7_COMMAND_ISSUE ` | :ref:`0xf00060b0 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI7_ADDRESS ` | :ref:`0xf00060b4 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI7_BADDRESS ` | :ref:`0xf00060b8 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI7_WRDATA ` | :ref:`0xf00060bc ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI7_RDDATA ` | :ref:`0xf00060c0 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRP ` | :ref:`0xf00060c4 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRCD ` | :ref:`0xf00060c8 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TWR ` | :ref:`0xf00060cc ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TWTR ` | :ref:`0xf00060d0 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TREFI ` | :ref:`0xf00060d4 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRFC ` | :ref:`0xf00060d8 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TFAW ` | :ref:`0xf00060dc ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TCCD ` | :ref:`0xf00060e0 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TCCD_WR ` | :ref:`0xf00060e4 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRTP ` | :ref:`0xf00060e8 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRRD ` | :ref:`0xf00060ec ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRC ` | :ref:`0xf00060f0 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRAS ` | :ref:`0xf00060f4 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_0 ` | :ref:`0xf00060f8 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_0 ` | :ref:`0xf00060fc ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_1 ` | :ref:`0xf0006100 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_1 ` | :ref:`0xf0006104 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_2 ` | :ref:`0xf0006108 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_2 ` | :ref:`0xf000610c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_3 ` | :ref:`0xf0006110 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_3 ` | :ref:`0xf0006114 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_4 ` | :ref:`0xf0006118 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_4 ` | :ref:`0xf000611c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_5 ` | :ref:`0xf0006120 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_5 ` | :ref:`0xf0006124 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_6 ` | :ref:`0xf0006128 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_6 ` | :ref:`0xf000612c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_7 ` | :ref:`0xf0006130 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_7 ` | :ref:`0xf0006134 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ + +SDRAM_DFII_CONTROL +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x0 = 0xf0006000` + + Control DFI signals common to all phases + + .. wavedrom:: + :caption: SDRAM_DFII_CONTROL + + { + "reg": [ + {"name": "sel", "attr": '1', "bits": 1}, + {"name": "cke", "bits": 1}, + {"name": "odt", "bits": 1}, + {"name": "reset_n", "bits": 1}, + {"bits": 28} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+---------+-------------------------------------------+ +| Field | Name | Description | ++=======+=========+===========================================+ +| [0] | SEL | | +| | | | +| | | +---------+-----------------------------+ | +| | | | Value | Description | | +| | | +=========+=============================+ | +| | | | ``0b0`` | Software (CPU) control. | | +| | | +---------+-----------------------------+ | +| | | | ``0b1`` | Hardware control (default). | | +| | | +---------+-----------------------------+ | ++-------+---------+-------------------------------------------+ +| [1] | CKE | DFI clock enable bus | ++-------+---------+-------------------------------------------+ +| [2] | ODT | DFI on-die termination bus | ++-------+---------+-------------------------------------------+ +| [3] | RESET_N | DFI clock reset bus | ++-------+---------+-------------------------------------------+ + +SDRAM_DFII_PI0_COMMAND +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x4 = 0xf0006004` + + Control DFI signals on a single phase + + .. wavedrom:: + :caption: SDRAM_DFII_PI0_COMMAND + + { + "reg": [ + {"name": "cs", "bits": 1}, + {"name": "we", "bits": 1}, + {"name": "cas", "bits": 1}, + {"name": "ras", "bits": 1}, + {"name": "wren", "bits": 1}, + {"name": "rden", "bits": 1}, + {"bits": 26} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------------------------+ +| Field | Name | Description | ++=======+======+===============================+ +| [0] | CS | DFI chip select bus | ++-------+------+-------------------------------+ +| [1] | WE | DFI write enable bus | ++-------+------+-------------------------------+ +| [2] | CAS | DFI column address strobe bus | ++-------+------+-------------------------------+ +| [3] | RAS | DFI row address strobe bus | ++-------+------+-------------------------------+ +| [4] | WREN | DFI write data enable bus | ++-------+------+-------------------------------+ +| [5] | RDEN | DFI read data enable bus | ++-------+------+-------------------------------+ + +SDRAM_DFII_PI0_COMMAND_ISSUE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x8 = 0xf0006008` + + + .. wavedrom:: + :caption: SDRAM_DFII_PI0_COMMAND_ISSUE + + { + "reg": [ + {"name": "dfii_pi0_command_issue", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_PI0_ADDRESS +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xc = 0xf000600c` + + DFI address bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI0_ADDRESS + + { + "reg": [ + {"name": "dfii_pi0_address[16:0]", "bits": 17}, + {"bits": 15}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI0_BADDRESS +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x10 = 0xf0006010` + + DFI bank address bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI0_BADDRESS + + { + "reg": [ + {"name": "dfii_pi0_baddress[5:0]", "bits": 6}, + {"bits": 26}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_PI0_WRDATA +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x14 = 0xf0006014` + + DFI write data bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI0_WRDATA + + { + "reg": [ + {"name": "dfii_pi0_wrdata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI0_RDDATA +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x18 = 0xf0006018` + + DFI read data bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI0_RDDATA + + { + "reg": [ + {"name": "dfii_pi0_rddata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI1_COMMAND +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x1c = 0xf000601c` + + Control DFI signals on a single phase + + .. wavedrom:: + :caption: SDRAM_DFII_PI1_COMMAND + + { + "reg": [ + {"name": "cs", "bits": 1}, + {"name": "we", "bits": 1}, + {"name": "cas", "bits": 1}, + {"name": "ras", "bits": 1}, + {"name": "wren", "bits": 1}, + {"name": "rden", "bits": 1}, + {"bits": 26} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------------------------+ +| Field | Name | Description | ++=======+======+===============================+ +| [0] | CS | DFI chip select bus | ++-------+------+-------------------------------+ +| [1] | WE | DFI write enable bus | ++-------+------+-------------------------------+ +| [2] | CAS | DFI column address strobe bus | ++-------+------+-------------------------------+ +| [3] | RAS | DFI row address strobe bus | ++-------+------+-------------------------------+ +| [4] | WREN | DFI write data enable bus | ++-------+------+-------------------------------+ +| [5] | RDEN | DFI read data enable bus | ++-------+------+-------------------------------+ + +SDRAM_DFII_PI1_COMMAND_ISSUE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x20 = 0xf0006020` + + + .. wavedrom:: + :caption: SDRAM_DFII_PI1_COMMAND_ISSUE + + { + "reg": [ + {"name": "dfii_pi1_command_issue", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_PI1_ADDRESS +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x24 = 0xf0006024` + + DFI address bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI1_ADDRESS + + { + "reg": [ + {"name": "dfii_pi1_address[16:0]", "bits": 17}, + {"bits": 15}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI1_BADDRESS +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x28 = 0xf0006028` + + DFI bank address bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI1_BADDRESS + + { + "reg": [ + {"name": "dfii_pi1_baddress[5:0]", "bits": 6}, + {"bits": 26}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_PI1_WRDATA +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x2c = 0xf000602c` + + DFI write data bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI1_WRDATA + + { + "reg": [ + {"name": "dfii_pi1_wrdata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI1_RDDATA +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x30 = 0xf0006030` + + DFI read data bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI1_RDDATA + + { + "reg": [ + {"name": "dfii_pi1_rddata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI2_COMMAND +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x34 = 0xf0006034` + + Control DFI signals on a single phase + + .. wavedrom:: + :caption: SDRAM_DFII_PI2_COMMAND + + { + "reg": [ + {"name": "cs", "bits": 1}, + {"name": "we", "bits": 1}, + {"name": "cas", "bits": 1}, + {"name": "ras", "bits": 1}, + {"name": "wren", "bits": 1}, + {"name": "rden", "bits": 1}, + {"bits": 26} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------------------------+ +| Field | Name | Description | ++=======+======+===============================+ +| [0] | CS | DFI chip select bus | ++-------+------+-------------------------------+ +| [1] | WE | DFI write enable bus | ++-------+------+-------------------------------+ +| [2] | CAS | DFI column address strobe bus | ++-------+------+-------------------------------+ +| [3] | RAS | DFI row address strobe bus | ++-------+------+-------------------------------+ +| [4] | WREN | DFI write data enable bus | ++-------+------+-------------------------------+ +| [5] | RDEN | DFI read data enable bus | ++-------+------+-------------------------------+ + +SDRAM_DFII_PI2_COMMAND_ISSUE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x38 = 0xf0006038` + + + .. wavedrom:: + :caption: SDRAM_DFII_PI2_COMMAND_ISSUE + + { + "reg": [ + {"name": "dfii_pi2_command_issue", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_PI2_ADDRESS +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x3c = 0xf000603c` + + DFI address bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI2_ADDRESS + + { + "reg": [ + {"name": "dfii_pi2_address[16:0]", "bits": 17}, + {"bits": 15}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI2_BADDRESS +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x40 = 0xf0006040` + + DFI bank address bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI2_BADDRESS + + { + "reg": [ + {"name": "dfii_pi2_baddress[5:0]", "bits": 6}, + {"bits": 26}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_PI2_WRDATA +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x44 = 0xf0006044` + + DFI write data bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI2_WRDATA + + { + "reg": [ + {"name": "dfii_pi2_wrdata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI2_RDDATA +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x48 = 0xf0006048` + + DFI read data bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI2_RDDATA + + { + "reg": [ + {"name": "dfii_pi2_rddata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI3_COMMAND +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x4c = 0xf000604c` + + Control DFI signals on a single phase + + .. wavedrom:: + :caption: SDRAM_DFII_PI3_COMMAND + + { + "reg": [ + {"name": "cs", "bits": 1}, + {"name": "we", "bits": 1}, + {"name": "cas", "bits": 1}, + {"name": "ras", "bits": 1}, + {"name": "wren", "bits": 1}, + {"name": "rden", "bits": 1}, + {"bits": 26} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------------------------+ +| Field | Name | Description | ++=======+======+===============================+ +| [0] | CS | DFI chip select bus | ++-------+------+-------------------------------+ +| [1] | WE | DFI write enable bus | ++-------+------+-------------------------------+ +| [2] | CAS | DFI column address strobe bus | ++-------+------+-------------------------------+ +| [3] | RAS | DFI row address strobe bus | ++-------+------+-------------------------------+ +| [4] | WREN | DFI write data enable bus | ++-------+------+-------------------------------+ +| [5] | RDEN | DFI read data enable bus | ++-------+------+-------------------------------+ + +SDRAM_DFII_PI3_COMMAND_ISSUE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x50 = 0xf0006050` + + + .. wavedrom:: + :caption: SDRAM_DFII_PI3_COMMAND_ISSUE + + { + "reg": [ + {"name": "dfii_pi3_command_issue", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_PI3_ADDRESS +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x54 = 0xf0006054` + + DFI address bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI3_ADDRESS + + { + "reg": [ + {"name": "dfii_pi3_address[16:0]", "bits": 17}, + {"bits": 15}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI3_BADDRESS +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x58 = 0xf0006058` + + DFI bank address bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI3_BADDRESS + + { + "reg": [ + {"name": "dfii_pi3_baddress[5:0]", "bits": 6}, + {"bits": 26}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_PI3_WRDATA +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x5c = 0xf000605c` + + DFI write data bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI3_WRDATA + + { + "reg": [ + {"name": "dfii_pi3_wrdata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI3_RDDATA +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x60 = 0xf0006060` + + DFI read data bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI3_RDDATA + + { + "reg": [ + {"name": "dfii_pi3_rddata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI4_COMMAND +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x64 = 0xf0006064` + + Control DFI signals on a single phase + + .. wavedrom:: + :caption: SDRAM_DFII_PI4_COMMAND + + { + "reg": [ + {"name": "cs", "bits": 1}, + {"name": "we", "bits": 1}, + {"name": "cas", "bits": 1}, + {"name": "ras", "bits": 1}, + {"name": "wren", "bits": 1}, + {"name": "rden", "bits": 1}, + {"bits": 26} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------------------------+ +| Field | Name | Description | ++=======+======+===============================+ +| [0] | CS | DFI chip select bus | ++-------+------+-------------------------------+ +| [1] | WE | DFI write enable bus | ++-------+------+-------------------------------+ +| [2] | CAS | DFI column address strobe bus | ++-------+------+-------------------------------+ +| [3] | RAS | DFI row address strobe bus | ++-------+------+-------------------------------+ +| [4] | WREN | DFI write data enable bus | ++-------+------+-------------------------------+ +| [5] | RDEN | DFI read data enable bus | ++-------+------+-------------------------------+ + +SDRAM_DFII_PI4_COMMAND_ISSUE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x68 = 0xf0006068` + + + .. wavedrom:: + :caption: SDRAM_DFII_PI4_COMMAND_ISSUE + + { + "reg": [ + {"name": "dfii_pi4_command_issue", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_PI4_ADDRESS +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x6c = 0xf000606c` + + DFI address bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI4_ADDRESS + + { + "reg": [ + {"name": "dfii_pi4_address[16:0]", "bits": 17}, + {"bits": 15}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI4_BADDRESS +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x70 = 0xf0006070` + + DFI bank address bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI4_BADDRESS + + { + "reg": [ + {"name": "dfii_pi4_baddress[5:0]", "bits": 6}, + {"bits": 26}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_PI4_WRDATA +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x74 = 0xf0006074` + + DFI write data bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI4_WRDATA + + { + "reg": [ + {"name": "dfii_pi4_wrdata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI4_RDDATA +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x78 = 0xf0006078` + + DFI read data bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI4_RDDATA + + { + "reg": [ + {"name": "dfii_pi4_rddata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI5_COMMAND +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x7c = 0xf000607c` + + Control DFI signals on a single phase + + .. wavedrom:: + :caption: SDRAM_DFII_PI5_COMMAND + + { + "reg": [ + {"name": "cs", "bits": 1}, + {"name": "we", "bits": 1}, + {"name": "cas", "bits": 1}, + {"name": "ras", "bits": 1}, + {"name": "wren", "bits": 1}, + {"name": "rden", "bits": 1}, + {"bits": 26} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------------------------+ +| Field | Name | Description | ++=======+======+===============================+ +| [0] | CS | DFI chip select bus | ++-------+------+-------------------------------+ +| [1] | WE | DFI write enable bus | ++-------+------+-------------------------------+ +| [2] | CAS | DFI column address strobe bus | ++-------+------+-------------------------------+ +| [3] | RAS | DFI row address strobe bus | ++-------+------+-------------------------------+ +| [4] | WREN | DFI write data enable bus | ++-------+------+-------------------------------+ +| [5] | RDEN | DFI read data enable bus | ++-------+------+-------------------------------+ + +SDRAM_DFII_PI5_COMMAND_ISSUE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x80 = 0xf0006080` + + + .. wavedrom:: + :caption: SDRAM_DFII_PI5_COMMAND_ISSUE + + { + "reg": [ + {"name": "dfii_pi5_command_issue", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_PI5_ADDRESS +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x84 = 0xf0006084` + + DFI address bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI5_ADDRESS + + { + "reg": [ + {"name": "dfii_pi5_address[16:0]", "bits": 17}, + {"bits": 15}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI5_BADDRESS +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x88 = 0xf0006088` + + DFI bank address bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI5_BADDRESS + + { + "reg": [ + {"name": "dfii_pi5_baddress[5:0]", "bits": 6}, + {"bits": 26}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_PI5_WRDATA +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x8c = 0xf000608c` + + DFI write data bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI5_WRDATA + + { + "reg": [ + {"name": "dfii_pi5_wrdata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI5_RDDATA +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x90 = 0xf0006090` + + DFI read data bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI5_RDDATA + + { + "reg": [ + {"name": "dfii_pi5_rddata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI6_COMMAND +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x94 = 0xf0006094` + + Control DFI signals on a single phase + + .. wavedrom:: + :caption: SDRAM_DFII_PI6_COMMAND + + { + "reg": [ + {"name": "cs", "bits": 1}, + {"name": "we", "bits": 1}, + {"name": "cas", "bits": 1}, + {"name": "ras", "bits": 1}, + {"name": "wren", "bits": 1}, + {"name": "rden", "bits": 1}, + {"bits": 26} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------------------------+ +| Field | Name | Description | ++=======+======+===============================+ +| [0] | CS | DFI chip select bus | ++-------+------+-------------------------------+ +| [1] | WE | DFI write enable bus | ++-------+------+-------------------------------+ +| [2] | CAS | DFI column address strobe bus | ++-------+------+-------------------------------+ +| [3] | RAS | DFI row address strobe bus | ++-------+------+-------------------------------+ +| [4] | WREN | DFI write data enable bus | ++-------+------+-------------------------------+ +| [5] | RDEN | DFI read data enable bus | ++-------+------+-------------------------------+ + +SDRAM_DFII_PI6_COMMAND_ISSUE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x98 = 0xf0006098` + + + .. wavedrom:: + :caption: SDRAM_DFII_PI6_COMMAND_ISSUE + + { + "reg": [ + {"name": "dfii_pi6_command_issue", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_PI6_ADDRESS +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x9c = 0xf000609c` + + DFI address bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI6_ADDRESS + + { + "reg": [ + {"name": "dfii_pi6_address[16:0]", "bits": 17}, + {"bits": 15}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI6_BADDRESS +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xa0 = 0xf00060a0` + + DFI bank address bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI6_BADDRESS + + { + "reg": [ + {"name": "dfii_pi6_baddress[5:0]", "bits": 6}, + {"bits": 26}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_PI6_WRDATA +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xa4 = 0xf00060a4` + + DFI write data bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI6_WRDATA + + { + "reg": [ + {"name": "dfii_pi6_wrdata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI6_RDDATA +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xa8 = 0xf00060a8` + + DFI read data bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI6_RDDATA + + { + "reg": [ + {"name": "dfii_pi6_rddata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI7_COMMAND +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xac = 0xf00060ac` + + Control DFI signals on a single phase + + .. wavedrom:: + :caption: SDRAM_DFII_PI7_COMMAND + + { + "reg": [ + {"name": "cs", "bits": 1}, + {"name": "we", "bits": 1}, + {"name": "cas", "bits": 1}, + {"name": "ras", "bits": 1}, + {"name": "wren", "bits": 1}, + {"name": "rden", "bits": 1}, + {"bits": 26} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------------------------+ +| Field | Name | Description | ++=======+======+===============================+ +| [0] | CS | DFI chip select bus | ++-------+------+-------------------------------+ +| [1] | WE | DFI write enable bus | ++-------+------+-------------------------------+ +| [2] | CAS | DFI column address strobe bus | ++-------+------+-------------------------------+ +| [3] | RAS | DFI row address strobe bus | ++-------+------+-------------------------------+ +| [4] | WREN | DFI write data enable bus | ++-------+------+-------------------------------+ +| [5] | RDEN | DFI read data enable bus | ++-------+------+-------------------------------+ + +SDRAM_DFII_PI7_COMMAND_ISSUE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xb0 = 0xf00060b0` + + + .. wavedrom:: + :caption: SDRAM_DFII_PI7_COMMAND_ISSUE + + { + "reg": [ + {"name": "dfii_pi7_command_issue", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_PI7_ADDRESS +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xb4 = 0xf00060b4` + + DFI address bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI7_ADDRESS + + { + "reg": [ + {"name": "dfii_pi7_address[16:0]", "bits": 17}, + {"bits": 15}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI7_BADDRESS +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xb8 = 0xf00060b8` + + DFI bank address bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI7_BADDRESS + + { + "reg": [ + {"name": "dfii_pi7_baddress[5:0]", "bits": 6}, + {"bits": 26}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_PI7_WRDATA +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xbc = 0xf00060bc` + + DFI write data bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI7_WRDATA + + { + "reg": [ + {"name": "dfii_pi7_wrdata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI7_RDDATA +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xc0 = 0xf00060c0` + + DFI read data bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI7_RDDATA + + { + "reg": [ + {"name": "dfii_pi7_rddata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_TRP +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xc4 = 0xf00060c4` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRP + + { + "reg": [ + {"name": "controller_trp[1:0]", "attr": 'reset: 2', "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TRCD +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xc8 = 0xf00060c8` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRCD + + { + "reg": [ + {"name": "controller_trcd[1:0]", "attr": 'reset: 2', "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TWR +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xcc = 0xf00060cc` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TWR + + { + "reg": [ + {"name": "controller_twr[1:0]", "attr": 'reset: 2', "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TWTR +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xd0 = 0xf00060d0` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TWTR + + { + "reg": [ + {"name": "controller_twtr[1:0]", "attr": 'reset: 2', "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TREFI +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xd4 = 0xf00060d4` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TREFI + + { + "reg": [ + {"name": "controller_trefi[7:0]", "attr": 'reset: 196', "bits": 8}, + {"bits": 24}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_TRFC +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xd8 = 0xf00060d8` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRFC + + { + "reg": [ + {"name": "controller_trfc[4:0]", "attr": 'reset: 10', "bits": 5}, + {"bits": 27}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TFAW +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xdc = 0xf00060dc` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TFAW + + { + "reg": [ + {"name": "controller_tfaw[1:0]", "attr": 'reset: 3', "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TCCD +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xe0 = 0xf00060e0` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TCCD + + { + "reg": [ + {"name": "controller_tccd[2:0]", "attr": 'reset: 4', "bits": 3}, + {"bits": 29}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TCCD_WR +^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xe4 = 0xf00060e4` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TCCD_WR + + { + "reg": [ + {"name": "controller_tccd_wr", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TRTP +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xe8 = 0xf00060e8` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRTP + + { + "reg": [ + {"name": "controller_trtp", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TRRD +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xec = 0xf00060ec` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRRD + + { + "reg": [ + {"name": "controller_trrd[1:0]", "attr": 'reset: 2', "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TRC +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xf0 = 0xf00060f0` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRC + + { + "reg": [ + {"name": "controller_trc[2:0]", "attr": 'reset: 5', "bits": 3}, + {"bits": 29}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TRAS +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xf4 = 0xf00060f4` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRAS + + { + "reg": [ + {"name": "controller_tras[2:0]", "attr": 'reset: 3', "bits": 3}, + {"bits": 29}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_LAST_ADDR_0 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xf8 = 0xf00060f8` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_0 + + { + "reg": [ + {"name": "controller_last_addr_0[20:0]", "bits": 21}, + {"bits": 11}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_0 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xfc = 0xf00060fc` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_0 + + { + "reg": [ + {"name": "controller_last_active_row_0[14:0]", "bits": 15}, + {"bits": 17}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_1 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x100 = 0xf0006100` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_1 + + { + "reg": [ + {"name": "controller_last_addr_1[20:0]", "bits": 21}, + {"bits": 11}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_1 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x104 = 0xf0006104` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_1 + + { + "reg": [ + {"name": "controller_last_active_row_1[14:0]", "bits": 15}, + {"bits": 17}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_2 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x108 = 0xf0006108` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_2 + + { + "reg": [ + {"name": "controller_last_addr_2[20:0]", "bits": 21}, + {"bits": 11}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_2 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x10c = 0xf000610c` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_2 + + { + "reg": [ + {"name": "controller_last_active_row_2[14:0]", "bits": 15}, + {"bits": 17}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_3 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x110 = 0xf0006110` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_3 + + { + "reg": [ + {"name": "controller_last_addr_3[20:0]", "bits": 21}, + {"bits": 11}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_3 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x114 = 0xf0006114` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_3 + + { + "reg": [ + {"name": "controller_last_active_row_3[14:0]", "bits": 15}, + {"bits": 17}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_4 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x118 = 0xf0006118` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_4 + + { + "reg": [ + {"name": "controller_last_addr_4[20:0]", "bits": 21}, + {"bits": 11}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_4 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x11c = 0xf000611c` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_4 + + { + "reg": [ + {"name": "controller_last_active_row_4[14:0]", "bits": 15}, + {"bits": 17}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_5 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x120 = 0xf0006120` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_5 + + { + "reg": [ + {"name": "controller_last_addr_5[20:0]", "bits": 21}, + {"bits": 11}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_5 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x124 = 0xf0006124` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_5 + + { + "reg": [ + {"name": "controller_last_active_row_5[14:0]", "bits": 15}, + {"bits": 17}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_6 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x128 = 0xf0006128` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_6 + + { + "reg": [ + {"name": "controller_last_addr_6[20:0]", "bits": 21}, + {"bits": 11}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_6 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x12c = 0xf000612c` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_6 + + { + "reg": [ + {"name": "controller_last_active_row_6[14:0]", "bits": 15}, + {"bits": 17}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_7 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x130 = 0xf0006130` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_7 + + { + "reg": [ + {"name": "controller_last_addr_7[20:0]", "bits": 21}, + {"bits": 11}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_7 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x134 = 0xf0006134` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_7 + + { + "reg": [ + {"name": "controller_last_active_row_7[14:0]", "bits": 15}, + {"bits": 17}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/lpddr4_test_board/documentation/sdram_checker.rst.txt b/_sources/build/lpddr4_test_board/documentation/sdram_checker.rst.txt new file mode 100644 index 000000000..aa1701db8 --- /dev/null +++ b/_sources/build/lpddr4_test_board/documentation/sdram_checker.rst.txt @@ -0,0 +1,186 @@ +SDRAM_CHECKER +============= + +Register Listing for SDRAM_CHECKER +---------------------------------- + ++----------------------------------------------------+------------------------------------------+ +| Register | Address | ++====================================================+==========================================+ +| :ref:`SDRAM_CHECKER_RESET ` | :ref:`0xf0006800 ` | ++----------------------------------------------------+------------------------------------------+ +| :ref:`SDRAM_CHECKER_START ` | :ref:`0xf0006804 ` | ++----------------------------------------------------+------------------------------------------+ +| :ref:`SDRAM_CHECKER_DONE ` | :ref:`0xf0006808 ` | ++----------------------------------------------------+------------------------------------------+ +| :ref:`SDRAM_CHECKER_BASE ` | :ref:`0xf000680c ` | ++----------------------------------------------------+------------------------------------------+ +| :ref:`SDRAM_CHECKER_END ` | :ref:`0xf0006810 ` | ++----------------------------------------------------+------------------------------------------+ +| :ref:`SDRAM_CHECKER_LENGTH ` | :ref:`0xf0006814 ` | ++----------------------------------------------------+------------------------------------------+ +| :ref:`SDRAM_CHECKER_RANDOM ` | :ref:`0xf0006818 ` | ++----------------------------------------------------+------------------------------------------+ +| :ref:`SDRAM_CHECKER_TICKS ` | :ref:`0xf000681c ` | ++----------------------------------------------------+------------------------------------------+ +| :ref:`SDRAM_CHECKER_ERRORS ` | :ref:`0xf0006820 ` | ++----------------------------------------------------+------------------------------------------+ + +SDRAM_CHECKER_RESET +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x0 = 0xf0006800` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_RESET + + { + "reg": [ + {"name": "reset", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CHECKER_START +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x4 = 0xf0006804` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_START + + { + "reg": [ + {"name": "start", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CHECKER_DONE +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x8 = 0xf0006808` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_DONE + + { + "reg": [ + {"name": "done", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CHECKER_BASE +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xc = 0xf000680c` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_BASE + + { + "reg": [ + {"name": "base[28:0]", "bits": 29}, + {"bits": 3}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CHECKER_END +^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x10 = 0xf0006810` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_END + + { + "reg": [ + {"name": "end[28:0]", "bits": 29}, + {"bits": 3}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CHECKER_LENGTH +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x14 = 0xf0006814` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_LENGTH + + { + "reg": [ + {"name": "length[28:0]", "bits": 29}, + {"bits": 3}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CHECKER_RANDOM +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x18 = 0xf0006818` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_RANDOM + + { + "reg": [ + {"name": "data", "bits": 1}, + {"name": "addr", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------+ +| Field | Name | Description | ++=======+======+=============+ ++-------+------+-------------+ ++-------+------+-------------+ + +SDRAM_CHECKER_TICKS +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x1c = 0xf000681c` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_TICKS + + { + "reg": [ + {"name": "ticks[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CHECKER_ERRORS +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x20 = 0xf0006820` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_ERRORS + + { + "reg": [ + {"name": "errors[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/lpddr4_test_board/documentation/sdram_generator.rst.txt b/_sources/build/lpddr4_test_board/documentation/sdram_generator.rst.txt new file mode 100644 index 000000000..6f8d66f0e --- /dev/null +++ b/_sources/build/lpddr4_test_board/documentation/sdram_generator.rst.txt @@ -0,0 +1,168 @@ +SDRAM_GENERATOR +=============== + +Register Listing for SDRAM_GENERATOR +------------------------------------ + ++--------------------------------------------------------+--------------------------------------------+ +| Register | Address | ++========================================================+============================================+ +| :ref:`SDRAM_GENERATOR_RESET ` | :ref:`0xf0007000 ` | ++--------------------------------------------------------+--------------------------------------------+ +| :ref:`SDRAM_GENERATOR_START ` | :ref:`0xf0007004 ` | ++--------------------------------------------------------+--------------------------------------------+ +| :ref:`SDRAM_GENERATOR_DONE ` | :ref:`0xf0007008 ` | ++--------------------------------------------------------+--------------------------------------------+ +| :ref:`SDRAM_GENERATOR_BASE ` | :ref:`0xf000700c ` | ++--------------------------------------------------------+--------------------------------------------+ +| :ref:`SDRAM_GENERATOR_END ` | :ref:`0xf0007010 ` | ++--------------------------------------------------------+--------------------------------------------+ +| :ref:`SDRAM_GENERATOR_LENGTH ` | :ref:`0xf0007014 ` | ++--------------------------------------------------------+--------------------------------------------+ +| :ref:`SDRAM_GENERATOR_RANDOM ` | :ref:`0xf0007018 ` | ++--------------------------------------------------------+--------------------------------------------+ +| :ref:`SDRAM_GENERATOR_TICKS ` | :ref:`0xf000701c ` | ++--------------------------------------------------------+--------------------------------------------+ + +SDRAM_GENERATOR_RESET +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x0 = 0xf0007000` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_RESET + + { + "reg": [ + {"name": "reset", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_GENERATOR_START +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x4 = 0xf0007004` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_START + + { + "reg": [ + {"name": "start", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_GENERATOR_DONE +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x8 = 0xf0007008` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_DONE + + { + "reg": [ + {"name": "done", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_GENERATOR_BASE +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0xc = 0xf000700c` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_BASE + + { + "reg": [ + {"name": "base[28:0]", "bits": 29}, + {"bits": 3}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_GENERATOR_END +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x10 = 0xf0007010` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_END + + { + "reg": [ + {"name": "end[28:0]", "bits": 29}, + {"bits": 3}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_GENERATOR_LENGTH +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x14 = 0xf0007014` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_LENGTH + + { + "reg": [ + {"name": "length[28:0]", "bits": 29}, + {"bits": 3}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_GENERATOR_RANDOM +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x18 = 0xf0007018` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_RANDOM + + { + "reg": [ + {"name": "data", "bits": 1}, + {"name": "addr", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------+ +| Field | Name | Description | ++=======+======+=============+ ++-------+------+-------------+ ++-------+------+-------------+ + +SDRAM_GENERATOR_TICKS +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x1c = 0xf000701c` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_TICKS + + { + "reg": [ + {"name": "ticks[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/lpddr4_test_board/documentation/timer0.rst.txt b/_sources/build/lpddr4_test_board/documentation/timer0.rst.txt new file mode 100644 index 000000000..4cf544f1c --- /dev/null +++ b/_sources/build/lpddr4_test_board/documentation/timer0.rst.txt @@ -0,0 +1,228 @@ +TIMER0 +====== + +Timer +----- + +Provides a generic Timer core. + +The Timer is implemented as a countdown timer that can be used in various modes: + +- Polling : Returns current countdown value to software +- One-Shot: Loads itself and stops when value reaches ``0`` +- Periodic: (Re-)Loads itself when value reaches ``0`` + +``en`` register allows the user to enable/disable the Timer. When the Timer is enabled, it is +automatically loaded with the value of `load` register. + +When the Timer reaches ``0``, it is automatically reloaded with value of `reload` register. + +The user can latch the current countdown value by writing to ``update_value`` register, it will +update ``value`` register with current countdown value. + +To use the Timer in One-Shot mode, the user needs to: + +- Disable the timer +- Set the ``load`` register to the expected duration +- (Re-)Enable the Timer + +To use the Timer in Periodic mode, the user needs to: + +- Disable the Timer +- Set the ``load`` register to 0 +- Set the ``reload`` register to the expected period +- Enable the Timer + +For both modes, the CPU can be advertised by an IRQ that the duration/period has elapsed. (The +CPU can also do software polling with ``update_value`` and ``value`` to know the elapsed duration) + + +Register Listing for TIMER0 +--------------------------- + ++--------------------------------------------------+-----------------------------------------+ +| Register | Address | ++==================================================+=========================================+ +| :ref:`TIMER0_LOAD ` | :ref:`0xf0007800 ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_RELOAD ` | :ref:`0xf0007804 ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_EN ` | :ref:`0xf0007808 ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_UPDATE_VALUE ` | :ref:`0xf000780c ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_VALUE ` | :ref:`0xf0007810 ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_EV_STATUS ` | :ref:`0xf0007814 ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_EV_PENDING ` | :ref:`0xf0007818 ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_EV_ENABLE ` | :ref:`0xf000781c ` | ++--------------------------------------------------+-----------------------------------------+ + +TIMER0_LOAD +^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x0 = 0xf0007800` + + Load value when Timer is (re-)enabled. In One-Shot mode, the value written to + this register specifies the Timer's duration in clock cycles. + + .. wavedrom:: + :caption: TIMER0_LOAD + + { + "reg": [ + {"name": "load[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +TIMER0_RELOAD +^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x4 = 0xf0007804` + + Reload value when Timer reaches ``0``. In Periodic mode, the value written to + this register specify the Timer's period in clock cycles. + + .. wavedrom:: + :caption: TIMER0_RELOAD + + { + "reg": [ + {"name": "reload[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +TIMER0_EN +^^^^^^^^^ + +`Address: 0xf0007800 + 0x8 = 0xf0007808` + + Enable flag of the Timer. Set this flag to ``1`` to enable/start the Timer. Set + to ``0`` to disable the Timer. + + .. wavedrom:: + :caption: TIMER0_EN + + { + "reg": [ + {"name": "en", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +TIMER0_UPDATE_VALUE +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0xc = 0xf000780c` + + Update trigger for the current countdown value. A write to this register latches + the current countdown value to ``value`` register. + + .. wavedrom:: + :caption: TIMER0_UPDATE_VALUE + + { + "reg": [ + {"name": "update_value", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +TIMER0_VALUE +^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x10 = 0xf0007810` + + Latched countdown value. This value is updated by writing to ``update_value``. + + .. wavedrom:: + :caption: TIMER0_VALUE + + { + "reg": [ + {"name": "value[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +TIMER0_EV_STATUS +^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x14 = 0xf0007814` + + This register contains the current raw level of the zero event trigger. Writes + to this register have no effect. + + .. wavedrom:: + :caption: TIMER0_EV_STATUS + + { + "reg": [ + {"name": "zero", "bits": 1}, + {"bits": 31} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-----------------------------+ +| Field | Name | Description | ++=======+======+=============================+ +| [0] | ZERO | Level of the ``zero`` event | ++-------+------+-----------------------------+ + +TIMER0_EV_PENDING +^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x18 = 0xf0007818` + + When a zero event occurs, the corresponding bit will be set in this register. + To clear the Event, set the corresponding bit in this register. + + .. wavedrom:: + :caption: TIMER0_EV_PENDING + + { + "reg": [ + {"name": "zero", "bits": 1}, + {"bits": 31} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+--------------------------------------------------------------------------------+ +| Field | Name | Description | ++=======+======+================================================================================+ +| [0] | ZERO | `1` if a `zero` event occurred. This Event is triggered on a **falling** edge. | ++-------+------+--------------------------------------------------------------------------------+ + +TIMER0_EV_ENABLE +^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x1c = 0xf000781c` + + This register enables the corresponding zero events. Write a ``0`` to this + register to disable individual events. + + .. wavedrom:: + :caption: TIMER0_EV_ENABLE + + { + "reg": [ + {"name": "zero", "bits": 1}, + {"bits": 31} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+--------------------------------------------+ +| Field | Name | Description | ++=======+======+============================================+ +| [0] | ZERO | Write a ``1`` to enable the ``zero`` Event | ++-------+------+--------------------------------------------+ + diff --git a/_sources/build/lpddr4_test_board/documentation/uart.rst.txt b/_sources/build/lpddr4_test_board/documentation/uart.rst.txt new file mode 100644 index 000000000..2fff7323c --- /dev/null +++ b/_sources/build/lpddr4_test_board/documentation/uart.rst.txt @@ -0,0 +1,388 @@ +UART +==== + +Register Listing for UART +------------------------- + ++------------------------------------------------------+-------------------------------------------+ +| Register | Address | ++======================================================+===========================================+ +| :ref:`UART_RXTX ` | :ref:`0xf0008000 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_TXFULL ` | :ref:`0xf0008004 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_RXEMPTY ` | :ref:`0xf0008008 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_EV_STATUS ` | :ref:`0xf000800c ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_EV_PENDING ` | :ref:`0xf0008010 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_EV_ENABLE ` | :ref:`0xf0008014 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_TXEMPTY ` | :ref:`0xf0008018 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_RXFULL ` | :ref:`0xf000801c ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_RXTX ` | :ref:`0xf0008020 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_TXFULL ` | :ref:`0xf0008024 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_RXEMPTY ` | :ref:`0xf0008028 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_EV_STATUS ` | :ref:`0xf000802c ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_EV_PENDING ` | :ref:`0xf0008030 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_EV_ENABLE ` | :ref:`0xf0008034 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_TXEMPTY ` | :ref:`0xf0008038 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_RXFULL ` | :ref:`0xf000803c ` | ++------------------------------------------------------+-------------------------------------------+ + +UART_RXTX +^^^^^^^^^ + +`Address: 0xf0008000 + 0x0 = 0xf0008000` + + + .. wavedrom:: + :caption: UART_RXTX + + { + "reg": [ + {"name": "rxtx[7:0]", "bits": 8}, + {"bits": 24}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +UART_TXFULL +^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x4 = 0xf0008004` + + TX FIFO Full. + + .. wavedrom:: + :caption: UART_TXFULL + + { + "reg": [ + {"name": "txfull", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_RXEMPTY +^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x8 = 0xf0008008` + + RX FIFO Empty. + + .. wavedrom:: + :caption: UART_RXEMPTY + + { + "reg": [ + {"name": "rxempty", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_EV_STATUS +^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0xc = 0xf000800c` + + This register contains the current raw level of the rx event trigger. Writes to + this register have no effect. + + .. wavedrom:: + :caption: UART_EV_STATUS + + { + "reg": [ + {"name": "tx", "bits": 1}, + {"name": "rx", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+---------------------------+ +| Field | Name | Description | ++=======+======+===========================+ +| [0] | TX | Level of the ``tx`` event | ++-------+------+---------------------------+ +| [1] | RX | Level of the ``rx`` event | ++-------+------+---------------------------+ + +UART_EV_PENDING +^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x10 = 0xf0008010` + + When a rx event occurs, the corresponding bit will be set in this register. To + clear the Event, set the corresponding bit in this register. + + .. wavedrom:: + :caption: UART_EV_PENDING + + { + "reg": [ + {"name": "tx", "bits": 1}, + {"name": "rx", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+------------------------------------------------------------------------------+ +| Field | Name | Description | ++=======+======+==============================================================================+ +| [0] | TX | `1` if a `tx` event occurred. This Event is triggered on a **falling** edge. | ++-------+------+------------------------------------------------------------------------------+ +| [1] | RX | `1` if a `rx` event occurred. This Event is triggered on a **falling** edge. | ++-------+------+------------------------------------------------------------------------------+ + +UART_EV_ENABLE +^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x14 = 0xf0008014` + + This register enables the corresponding rx events. Write a ``0`` to this + register to disable individual events. + + .. wavedrom:: + :caption: UART_EV_ENABLE + + { + "reg": [ + {"name": "tx", "bits": 1}, + {"name": "rx", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+------------------------------------------+ +| Field | Name | Description | ++=======+======+==========================================+ +| [0] | TX | Write a ``1`` to enable the ``tx`` Event | ++-------+------+------------------------------------------+ +| [1] | RX | Write a ``1`` to enable the ``rx`` Event | ++-------+------+------------------------------------------+ + +UART_TXEMPTY +^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x18 = 0xf0008018` + + TX FIFO Empty. + + .. wavedrom:: + :caption: UART_TXEMPTY + + { + "reg": [ + {"name": "txempty", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_RXFULL +^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x1c = 0xf000801c` + + RX FIFO Full. + + .. wavedrom:: + :caption: UART_RXFULL + + { + "reg": [ + {"name": "rxfull", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_XOVER_RXTX +^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x20 = 0xf0008020` + + + .. wavedrom:: + :caption: UART_XOVER_RXTX + + { + "reg": [ + {"name": "xover_rxtx[7:0]", "bits": 8}, + {"bits": 24}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +UART_XOVER_TXFULL +^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x24 = 0xf0008024` + + TX FIFO Full. + + .. wavedrom:: + :caption: UART_XOVER_TXFULL + + { + "reg": [ + {"name": "xover_txfull", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_XOVER_RXEMPTY +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x28 = 0xf0008028` + + RX FIFO Empty. + + .. wavedrom:: + :caption: UART_XOVER_RXEMPTY + + { + "reg": [ + {"name": "xover_rxempty", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_XOVER_EV_STATUS +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x2c = 0xf000802c` + + This register contains the current raw level of the rx event trigger. Writes to + this register have no effect. + + .. wavedrom:: + :caption: UART_XOVER_EV_STATUS + + { + "reg": [ + {"name": "tx", "bits": 1}, + {"name": "rx", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+---------------------------+ +| Field | Name | Description | ++=======+======+===========================+ +| [0] | TX | Level of the ``tx`` event | ++-------+------+---------------------------+ +| [1] | RX | Level of the ``rx`` event | ++-------+------+---------------------------+ + +UART_XOVER_EV_PENDING +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x30 = 0xf0008030` + + When a rx event occurs, the corresponding bit will be set in this register. To + clear the Event, set the corresponding bit in this register. + + .. wavedrom:: + :caption: UART_XOVER_EV_PENDING + + { + "reg": [ + {"name": "tx", "bits": 1}, + {"name": "rx", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+------------------------------------------------------------------------------+ +| Field | Name | Description | ++=======+======+==============================================================================+ +| [0] | TX | `1` if a `tx` event occurred. This Event is triggered on a **falling** edge. | ++-------+------+------------------------------------------------------------------------------+ +| [1] | RX | `1` if a `rx` event occurred. This Event is triggered on a **falling** edge. | ++-------+------+------------------------------------------------------------------------------+ + +UART_XOVER_EV_ENABLE +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x34 = 0xf0008034` + + This register enables the corresponding rx events. Write a ``0`` to this + register to disable individual events. + + .. wavedrom:: + :caption: UART_XOVER_EV_ENABLE + + { + "reg": [ + {"name": "tx", "bits": 1}, + {"name": "rx", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+------------------------------------------+ +| Field | Name | Description | ++=======+======+==========================================+ +| [0] | TX | Write a ``1`` to enable the ``tx`` Event | ++-------+------+------------------------------------------+ +| [1] | RX | Write a ``1`` to enable the ``rx`` Event | ++-------+------+------------------------------------------+ + +UART_XOVER_TXEMPTY +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x38 = 0xf0008038` + + TX FIFO Empty. + + .. wavedrom:: + :caption: UART_XOVER_TXEMPTY + + { + "reg": [ + {"name": "xover_txempty", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_XOVER_RXFULL +^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x3c = 0xf000803c` + + RX FIFO Full. + + .. wavedrom:: + :caption: UART_XOVER_RXFULL + + { + "reg": [ + {"name": "xover_rxfull", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/lpddr4_test_board/documentation/writer.rst.txt b/_sources/build/lpddr4_test_board/documentation/writer.rst.txt new file mode 100644 index 000000000..9f637032a --- /dev/null +++ b/_sources/build/lpddr4_test_board/documentation/writer.rst.txt @@ -0,0 +1,251 @@ +WRITER +====== + + + +DMA DRAM writer. + +Allows to fill DRAM with a predefined pattern using DMA. + +Pattern +------- + + + Provides access to RAM to store access pattern: `mem_addr` and `mem_data`. + The pattern address space can be limited using the `data_mask`. + + For example, having `mem_adr` filled with `[ 0x04, 0x02, 0x03, ... ]` + and `mem_data` filled with `[ 0xff, 0xaa, 0x55, ... ]` and setting + `data_mask = 0b01`, the pattern [(address, data), ...] written will be: + `[(0x04, 0xff), (0x02, 0xaa), (0x04, 0xff), ...]` (wraps due to masking). + + DRAM memory range that is being accessed can be configured using `mem_mask`. + + To use this module, make sure that `ready` is 1, then write the desired + number of transfers to `count`. Writing to the `start` CSR will initialize + the operation. When the operation is ongoing `ready` will be 0. + + + +Register Listing for WRITER +--------------------------- + ++------------------------------------------------------------------------+----------------------------------------------------+ +| Register | Address | ++========================================================================+====================================================+ +| :ref:`WRITER_START ` | :ref:`0xf0002800 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_READY ` | :ref:`0xf0002804 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_MODULO ` | :ref:`0xf0002808 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_COUNT ` | :ref:`0xf000280c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_DONE ` | :ref:`0xf0002810 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_MEM_MASK ` | :ref:`0xf0002814 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_DATA_MASK ` | :ref:`0xf0002818 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_DATA_DIV ` | :ref:`0xf000281c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_INVERTER_DIVISOR_MASK ` | :ref:`0xf0002820 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_INVERTER_SELECTION_MASK ` | :ref:`0xf0002824 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_LAST_ADDRESS ` | :ref:`0xf0002828 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ + +WRITER_START +^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x0 = 0xf0002800` + + Write to the register starts the transfer (if ready=1) + + .. wavedrom:: + :caption: WRITER_START + + { + "reg": [ + {"name": "start", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +WRITER_READY +^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x4 = 0xf0002804` + + Indicates that the transfer is not ongoing + + .. wavedrom:: + :caption: WRITER_READY + + { + "reg": [ + {"name": "ready", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +WRITER_MODULO +^^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x8 = 0xf0002808` + + When set use modulo to calculate DMA transfers address rather than bit masking + + .. wavedrom:: + :caption: WRITER_MODULO + + { + "reg": [ + {"name": "modulo", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +WRITER_COUNT +^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0xc = 0xf000280c` + + Desired number of DMA transfers + + .. wavedrom:: + :caption: WRITER_COUNT + + { + "reg": [ + {"name": "count[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +WRITER_DONE +^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x10 = 0xf0002810` + + Number of completed DMA transfers + + .. wavedrom:: + :caption: WRITER_DONE + + { + "reg": [ + {"name": "done[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +WRITER_MEM_MASK +^^^^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x14 = 0xf0002814` + + DRAM address mask for DMA transfers + + .. wavedrom:: + :caption: WRITER_MEM_MASK + + { + "reg": [ + {"name": "mem_mask[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +WRITER_DATA_MASK +^^^^^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x18 = 0xf0002818` + + Pattern memory address mask + + .. wavedrom:: + :caption: WRITER_DATA_MASK + + { + "reg": [ + {"name": "data_mask[4:0]", "bits": 5}, + {"bits": 27}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +WRITER_DATA_DIV +^^^^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x1c = 0xf000281c` + + Pattern memory address divisior-1 + + .. wavedrom:: + :caption: WRITER_DATA_DIV + + { + "reg": [ + {"name": "data_div[4:0]", "bits": 5}, + {"bits": 27}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +WRITER_INVERTER_DIVISOR_MASK +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x20 = 0xf0002820` + + Divisor mask for selecting rows for which pattern data gets inverted + + .. wavedrom:: + :caption: WRITER_INVERTER_DIVISOR_MASK + + { + "reg": [ + {"name": "inverter_divisor_mask[4:0]", "bits": 5}, + {"bits": 27}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +WRITER_INVERTER_SELECTION_MASK +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x24 = 0xf0002824` + + Selection mask for selecting rows for which pattern data gets inverted + + .. wavedrom:: + :caption: WRITER_INVERTER_SELECTION_MASK + + { + "reg": [ + {"name": "inverter_selection_mask[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +WRITER_LAST_ADDRESS +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x28 = 0xf0002828` + + Number of completed DMA transfers + + .. wavedrom:: + :caption: WRITER_LAST_ADDRESS + + { + "reg": [ + {"name": "last_address[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/zcu104/documentation/controller_settings.rst.txt b/_sources/build/zcu104/documentation/controller_settings.rst.txt new file mode 100644 index 000000000..cc67b4b83 --- /dev/null +++ b/_sources/build/zcu104/documentation/controller_settings.rst.txt @@ -0,0 +1,34 @@ +CONTROLLER_SETTINGS +=================== + +Allows to change LiteDRAMController behaviour at runtime +-------------------------------------------------------- + + +Register Listing for CONTROLLER_SETTINGS +---------------------------------------- + ++------------------------------------------------------------------+-------------------------------------------------+ +| Register | Address | ++==================================================================+=================================================+ +| :ref:`CONTROLLER_SETTINGS_REFRESH ` | :ref:`0xf0001000 ` | ++------------------------------------------------------------------+-------------------------------------------------+ + +CONTROLLER_SETTINGS_REFRESH +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0001000 + 0x0 = 0xf0001000` + + Enable/disable Refresh commands sending + + .. wavedrom:: + :caption: CONTROLLER_SETTINGS_REFRESH + + { + "reg": [ + {"name": "refresh", "attr": 'reset: 1', "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/zcu104/documentation/ctrl.rst.txt b/_sources/build/zcu104/documentation/ctrl.rst.txt new file mode 100644 index 000000000..8e9663760 --- /dev/null +++ b/_sources/build/zcu104/documentation/ctrl.rst.txt @@ -0,0 +1,78 @@ +CTRL +==== + +Register Listing for CTRL +------------------------- + ++------------------------------------------+-------------------------------------+ +| Register | Address | ++==========================================+=====================================+ +| :ref:`CTRL__RESET ` | :ref:`0xf0005000 ` | ++------------------------------------------+-------------------------------------+ +| :ref:`CTRL_SCRATCH ` | :ref:`0xf0005004 ` | ++------------------------------------------+-------------------------------------+ +| :ref:`CTRL_BUS_ERRORS ` | :ref:`0xf0005008 ` | ++------------------------------------------+-------------------------------------+ + +CTRL__RESET +^^^^^^^^^^^ + +`Address: 0xf0005000 + 0x0 = 0xf0005000` + + + .. wavedrom:: + :caption: CTRL__RESET + + { + "reg": [ + {"name": "soc_rst", "type": 4, "bits": 1}, + {"name": "cpu_rst", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+---------+------------------------------------------------------------------------+ +| Field | Name | Description | ++=======+=========+========================================================================+ +| [0] | SOC_RST | Write `1` to this register to reset the full SoC (Pulse Reset) | ++-------+---------+------------------------------------------------------------------------+ +| [1] | CPU_RST | Write `1` to this register to reset the CPU(s) of the SoC (Hold Reset) | ++-------+---------+------------------------------------------------------------------------+ + +CTRL_SCRATCH +^^^^^^^^^^^^ + +`Address: 0xf0005000 + 0x4 = 0xf0005004` + + Use this register as a scratch space to verify that software read/write accesses + to the Wishbone/CSR bus are working correctly. The initial reset value of + 0x1234578 can be used to verify endianness. + + .. wavedrom:: + :caption: CTRL_SCRATCH + + { + "reg": [ + {"name": "scratch[31:0]", "attr": 'reset: 305419896', "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +CTRL_BUS_ERRORS +^^^^^^^^^^^^^^^ + +`Address: 0xf0005000 + 0x8 = 0xf0005008` + + Total number of Wishbone bus errors (timeouts) since start. + + .. wavedrom:: + :caption: CTRL_BUS_ERRORS + + { + "reg": [ + {"name": "bus_errors[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/zcu104/documentation/ddrctrl.rst.txt b/_sources/build/zcu104/documentation/ddrctrl.rst.txt new file mode 100644 index 000000000..59563d8b1 --- /dev/null +++ b/_sources/build/zcu104/documentation/ddrctrl.rst.txt @@ -0,0 +1,48 @@ +DDRCTRL +======= + +Register Listing for DDRCTRL +---------------------------- + ++------------------------------------------------+----------------------------------------+ +| Register | Address | ++================================================+========================================+ +| :ref:`DDRCTRL_INIT_DONE ` | :ref:`0xf0001800 ` | ++------------------------------------------------+----------------------------------------+ +| :ref:`DDRCTRL_INIT_ERROR ` | :ref:`0xf0001804 ` | ++------------------------------------------------+----------------------------------------+ + +DDRCTRL_INIT_DONE +^^^^^^^^^^^^^^^^^ + +`Address: 0xf0001800 + 0x0 = 0xf0001800` + + + .. wavedrom:: + :caption: DDRCTRL_INIT_DONE + + { + "reg": [ + {"name": "init_done", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRCTRL_INIT_ERROR +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0001800 + 0x4 = 0xf0001804` + + + .. wavedrom:: + :caption: DDRCTRL_INIT_ERROR + + { + "reg": [ + {"name": "init_error", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/zcu104/documentation/ddrphy.rst.txt b/_sources/build/zcu104/documentation/ddrphy.rst.txt new file mode 100644 index 000000000..e6b0fcf61 --- /dev/null +++ b/_sources/build/zcu104/documentation/ddrphy.rst.txt @@ -0,0 +1,428 @@ +DDRPHY +====== + +Register Listing for DDRPHY +--------------------------- + ++----------------------------------------------------------------+------------------------------------------------+ +| Register | Address | ++================================================================+================================================+ +| :ref:`DDRPHY_RST ` | :ref:`0xf0000800 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_EN_VTC ` | :ref:`0xf0000804 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_HALF_SYS8X_TAPS ` | :ref:`0xf0000808 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_WLEVEL_EN ` | :ref:`0xf000080c ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_WLEVEL_STROBE ` | :ref:`0xf0000810 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_CDLY_RST ` | :ref:`0xf0000814 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_CDLY_INC ` | :ref:`0xf0000818 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_CDLY_VALUE ` | :ref:`0xf000081c ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_DLY_SEL ` | :ref:`0xf0000820 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_RDLY_DQ_RST ` | :ref:`0xf0000824 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_RDLY_DQ_INC ` | :ref:`0xf0000828 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_RDLY_DQ_BITSLIP_RST ` | :ref:`0xf000082c ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_RDLY_DQ_BITSLIP ` | :ref:`0xf0000830 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_WDLY_DQ_RST ` | :ref:`0xf0000834 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_WDLY_DQ_INC ` | :ref:`0xf0000838 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_WDLY_DQS_RST ` | :ref:`0xf000083c ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_WDLY_DQS_INC ` | :ref:`0xf0000840 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_WDLY_DQS_INC_COUNT ` | :ref:`0xf0000844 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_WDLY_DQ_BITSLIP_RST ` | :ref:`0xf0000848 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_WDLY_DQ_BITSLIP ` | :ref:`0xf000084c ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_RDPHASE ` | :ref:`0xf0000850 ` | ++----------------------------------------------------------------+------------------------------------------------+ +| :ref:`DDRPHY_WRPHASE ` | :ref:`0xf0000854 ` | ++----------------------------------------------------------------+------------------------------------------------+ + +DDRPHY_RST +^^^^^^^^^^ + +`Address: 0xf0000800 + 0x0 = 0xf0000800` + + + .. wavedrom:: + :caption: DDRPHY_RST + + { + "reg": [ + {"name": "rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_EN_VTC +^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x4 = 0xf0000804` + + + .. wavedrom:: + :caption: DDRPHY_EN_VTC + + { + "reg": [ + {"name": "en_vtc", "attr": 'reset: 1', "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_HALF_SYS8X_TAPS +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x8 = 0xf0000808` + + + .. wavedrom:: + :caption: DDRPHY_HALF_SYS8X_TAPS + + { + "reg": [ + {"name": "half_sys8x_taps[8:0]", "bits": 9}, + {"bits": 23}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DDRPHY_WLEVEL_EN +^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0xc = 0xf000080c` + + + .. wavedrom:: + :caption: DDRPHY_WLEVEL_EN + + { + "reg": [ + {"name": "wlevel_en", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_WLEVEL_STROBE +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x10 = 0xf0000810` + + + .. wavedrom:: + :caption: DDRPHY_WLEVEL_STROBE + + { + "reg": [ + {"name": "wlevel_strobe", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CDLY_RST +^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x14 = 0xf0000814` + + + .. wavedrom:: + :caption: DDRPHY_CDLY_RST + + { + "reg": [ + {"name": "cdly_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CDLY_INC +^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x18 = 0xf0000818` + + + .. wavedrom:: + :caption: DDRPHY_CDLY_INC + + { + "reg": [ + {"name": "cdly_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_CDLY_VALUE +^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x1c = 0xf000081c` + + + .. wavedrom:: + :caption: DDRPHY_CDLY_VALUE + + { + "reg": [ + {"name": "cdly_value[8:0]", "bits": 9}, + {"bits": 23}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DDRPHY_DLY_SEL +^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x20 = 0xf0000820` + + + .. wavedrom:: + :caption: DDRPHY_DLY_SEL + + { + "reg": [ + {"name": "dly_sel[7:0]", "bits": 8}, + {"bits": 24}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DDRPHY_RDLY_DQ_RST +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x24 = 0xf0000824` + + + .. wavedrom:: + :caption: DDRPHY_RDLY_DQ_RST + + { + "reg": [ + {"name": "rdly_dq_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_RDLY_DQ_INC +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x28 = 0xf0000828` + + + .. wavedrom:: + :caption: DDRPHY_RDLY_DQ_INC + + { + "reg": [ + {"name": "rdly_dq_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_RDLY_DQ_BITSLIP_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x2c = 0xf000082c` + + + .. wavedrom:: + :caption: DDRPHY_RDLY_DQ_BITSLIP_RST + + { + "reg": [ + {"name": "rdly_dq_bitslip_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_RDLY_DQ_BITSLIP +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x30 = 0xf0000830` + + + .. wavedrom:: + :caption: DDRPHY_RDLY_DQ_BITSLIP + + { + "reg": [ + {"name": "rdly_dq_bitslip", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_WDLY_DQ_RST +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x34 = 0xf0000834` + + + .. wavedrom:: + :caption: DDRPHY_WDLY_DQ_RST + + { + "reg": [ + {"name": "wdly_dq_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_WDLY_DQ_INC +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x38 = 0xf0000838` + + + .. wavedrom:: + :caption: DDRPHY_WDLY_DQ_INC + + { + "reg": [ + {"name": "wdly_dq_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_WDLY_DQS_RST +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x3c = 0xf000083c` + + + .. wavedrom:: + :caption: DDRPHY_WDLY_DQS_RST + + { + "reg": [ + {"name": "wdly_dqs_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_WDLY_DQS_INC +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x40 = 0xf0000840` + + + .. wavedrom:: + :caption: DDRPHY_WDLY_DQS_INC + + { + "reg": [ + {"name": "wdly_dqs_inc", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_WDLY_DQS_INC_COUNT +^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x44 = 0xf0000844` + + + .. wavedrom:: + :caption: DDRPHY_WDLY_DQS_INC_COUNT + + { + "reg": [ + {"name": "wdly_dqs_inc_count[8:0]", "bits": 9}, + {"bits": 23}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DDRPHY_WDLY_DQ_BITSLIP_RST +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x48 = 0xf0000848` + + + .. wavedrom:: + :caption: DDRPHY_WDLY_DQ_BITSLIP_RST + + { + "reg": [ + {"name": "wdly_dq_bitslip_rst", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_WDLY_DQ_BITSLIP +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x4c = 0xf000084c` + + + .. wavedrom:: + :caption: DDRPHY_WDLY_DQ_BITSLIP + + { + "reg": [ + {"name": "wdly_dq_bitslip", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_RDPHASE +^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x50 = 0xf0000850` + + + .. wavedrom:: + :caption: DDRPHY_RDPHASE + + { + "reg": [ + {"name": "rdphase[1:0]", "attr": 'reset: 3', "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +DDRPHY_WRPHASE +^^^^^^^^^^^^^^ + +`Address: 0xf0000800 + 0x54 = 0xf0000854` + + + .. wavedrom:: + :caption: DDRPHY_WRPHASE + + { + "reg": [ + {"name": "wrphase[1:0]", "attr": 'reset: 3', "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/zcu104/documentation/dfi_switch.rst.txt b/_sources/build/zcu104/documentation/dfi_switch.rst.txt new file mode 100644 index 000000000..718d8cc34 --- /dev/null +++ b/_sources/build/zcu104/documentation/dfi_switch.rst.txt @@ -0,0 +1,71 @@ +DFI_SWITCH +========== + +Register Listing for DFI_SWITCH +------------------------------- + ++--------------------------------------------------------------+-----------------------------------------------+ +| Register | Address | ++==============================================================+===============================================+ +| :ref:`DFI_SWITCH_REFRESH_COUNT ` | :ref:`0xf0003800 ` | ++--------------------------------------------------------------+-----------------------------------------------+ +| :ref:`DFI_SWITCH_AT_REFRESH ` | :ref:`0xf0003804 ` | ++--------------------------------------------------------------+-----------------------------------------------+ +| :ref:`DFI_SWITCH_REFRESH_UPDATE ` | :ref:`0xf0003808 ` | ++--------------------------------------------------------------+-----------------------------------------------+ + +DFI_SWITCH_REFRESH_COUNT +^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003800 + 0x0 = 0xf0003800` + + Count of all refresh commands issued (both by Memory Controller and Payload + Executor). Value is latched from internal counter on mode trasition: MC -> PE or + by writing to the `refresh_update` CSR. + + .. wavedrom:: + :caption: DFI_SWITCH_REFRESH_COUNT + + { + "reg": [ + {"name": "refresh_count[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DFI_SWITCH_AT_REFRESH +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003800 + 0x4 = 0xf0003804` + + If set to a value different than 0 the mode transition MC -> PE will be peformed + only when the value of this register matches the current refresh commands count. + + .. wavedrom:: + :caption: DFI_SWITCH_AT_REFRESH + + { + "reg": [ + {"name": "at_refresh[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +DFI_SWITCH_REFRESH_UPDATE +^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003800 + 0x8 = 0xf0003808` + + Force an update of the `refresh_count` CSR. + + .. wavedrom:: + :caption: DFI_SWITCH_REFRESH_UPDATE + + { + "reg": [ + {"name": "refresh_update", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/zcu104/documentation/i2c.rst.txt b/_sources/build/zcu104/documentation/i2c.rst.txt new file mode 100644 index 000000000..2771d3bc0 --- /dev/null +++ b/_sources/build/zcu104/documentation/i2c.rst.txt @@ -0,0 +1,62 @@ +I2C +=== + +Register Listing for I2C +------------------------ + ++----------------------+---------------------------+ +| Register | Address | ++======================+===========================+ +| :ref:`I2C_W ` | :ref:`0xf0004800 ` | ++----------------------+---------------------------+ +| :ref:`I2C_R ` | :ref:`0xf0004804 ` | ++----------------------+---------------------------+ + +I2C_W +^^^^^ + +`Address: 0xf0004800 + 0x0 = 0xf0004800` + + + .. wavedrom:: + :caption: I2C_W + + { + "reg": [ + {"name": "scl", "attr": '1', "bits": 1}, + {"name": "oe", "bits": 1}, + {"name": "sda", "attr": '1', "bits": 1}, + {"bits": 29} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------+ +| Field | Name | Description | ++=======+======+=============+ ++-------+------+-------------+ ++-------+------+-------------+ ++-------+------+-------------+ + +I2C_R +^^^^^ + +`Address: 0xf0004800 + 0x4 = 0xf0004804` + + + .. wavedrom:: + :caption: I2C_R + + { + "reg": [ + {"name": "sda", "bits": 1}, + {"bits": 31} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------+ +| Field | Name | Description | ++=======+======+=============+ ++-------+------+-------------+ + diff --git a/_sources/build/zcu104/documentation/identifier_mem.rst.txt b/_sources/build/zcu104/documentation/identifier_mem.rst.txt new file mode 100644 index 000000000..259503807 --- /dev/null +++ b/_sources/build/zcu104/documentation/identifier_mem.rst.txt @@ -0,0 +1,30 @@ +IDENTIFIER_MEM +============== + +Register Listing for IDENTIFIER_MEM +----------------------------------- + ++----------------------------------------+------------------------------------+ +| Register | Address | ++========================================+====================================+ +| :ref:`IDENTIFIER_MEM ` | :ref:`0xf0005800 ` | ++----------------------------------------+------------------------------------+ + +IDENTIFIER_MEM +^^^^^^^^^^^^^^ + +`Address: 0xf0005800 + 0x0 = 0xf0005800` + + 8 x 113-bit memory + + .. wavedrom:: + :caption: IDENTIFIER_MEM + + { + "reg": [ + {"name": "identifier_mem[7:0]", "bits": 8}, + {"bits": 24}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/zcu104/documentation/index.rst.txt b/_sources/build/zcu104/documentation/index.rst.txt new file mode 100644 index 000000000..f43d5a2c1 --- /dev/null +++ b/_sources/build/zcu104/documentation/index.rst.txt @@ -0,0 +1,37 @@ +========================================== +Documentation for Row Hammer Tester ZCU104 +========================================== + + + +Modules +======= + +.. toctree:: + :maxdepth: 1 + + interrupts + +Register Groups +=============== + +.. toctree:: + :maxdepth: 1 + + leds + ddrphy + controller_settings + ddrctrl + rowhammer + writer + reader + dfi_switch + payload_executor + i2c + ctrl + identifier_mem + sdram + sdram_checker + sdram_generator + timer0 + uart diff --git a/_sources/build/zcu104/documentation/interrupts.rst.txt b/_sources/build/zcu104/documentation/interrupts.rst.txt new file mode 100644 index 000000000..bfc948fb1 --- /dev/null +++ b/_sources/build/zcu104/documentation/interrupts.rst.txt @@ -0,0 +1,22 @@ +Interrupt Controller +==================== + +This device has an ``EventManager``-based interrupt system. Individual modules +generate `events` which are wired into a central interrupt controller. + +When an interrupt occurs, you should look the interrupt number up in the CPU- +specific interrupt table and then call the relevant module. + +Assigned Interrupts +------------------- + +The following interrupts are assigned on this system: + ++-----------+------------------------+ +| Interrupt | Module | ++===========+========================+ +| 1 | :doc:`TIMER0 ` | ++-----------+------------------------+ +| 0 | :doc:`UART ` | ++-----------+------------------------+ + diff --git a/_sources/build/zcu104/documentation/leds.rst.txt b/_sources/build/zcu104/documentation/leds.rst.txt new file mode 100644 index 000000000..5163a0c3d --- /dev/null +++ b/_sources/build/zcu104/documentation/leds.rst.txt @@ -0,0 +1,30 @@ +LEDS +==== + +Register Listing for LEDS +------------------------- + ++----------------------------+------------------------------+ +| Register | Address | ++============================+==============================+ +| :ref:`LEDS_OUT ` | :ref:`0xf0000000 ` | ++----------------------------+------------------------------+ + +LEDS_OUT +^^^^^^^^ + +`Address: 0xf0000000 + 0x0 = 0xf0000000` + + Led Output(s) Control. + + .. wavedrom:: + :caption: LEDS_OUT + + { + "reg": [ + {"name": "out[3:0]", "bits": 4}, + {"bits": 28}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/zcu104/documentation/payload_executor.rst.txt b/_sources/build/zcu104/documentation/payload_executor.rst.txt new file mode 100644 index 000000000..643168412 --- /dev/null +++ b/_sources/build/zcu104/documentation/payload_executor.rst.txt @@ -0,0 +1,137 @@ +PAYLOAD_EXECUTOR +================ + + + + Executes the DRAM payload from memory + + + **Instruction decoder** + + All instructions are 32-bit. The format of most instructions is the same, + except for the LOOP instruction, which has a constant TIMESLICE of 1. + + NOOP with a TIMESLICE of 0 is a special case which is interpreted as + STOP instruction. When this instruction is encountered execution gets + finished immediately. + + **NOTE:** TIMESLICE is the number of cycles the instruction will take. This + means that instructions other than NOOP that use TIMESLICE=0 are illegal + (although will silently be executed as having TIMESLICE=1). + + **NOTE2:** LOOP instruction will *jump* COUNT times, meaning that the "code" + inside the loop will effectively be executed COUNT+1 times. + + Op codes: + ++------+-------+ ++ Op + Value + ++======+=======+ ++ NOOP | 0b000 + ++------+-------+ ++ LOOP | 0b111 + ++------+-------+ ++ ACT | 0b100 + ++------+-------+ ++ PRE | 0b101 + ++------+-------+ ++ REF | 0b110 + ++------+-------+ ++ ZQC | 0b001 + ++------+-------+ ++ READ | 0b010 + ++------+-------+ + + Instruction format:: + + LSB MSB + dfi: OP_CODE | TIMESLICE | ADDRESS + noop: OP_CODE | TIMESLICE_NOOP + loop: OP_CODE | COUNT | JUMP + stop: | 0 + + Where ADDRESS depends on the DFI command and is one of:: + + LSB MSB + RANK | BANK | COLUMN + RANK | BANK | ROW + + + +Register Listing for PAYLOAD_EXECUTOR +------------------------------------- + ++------------------------------------------------------------------+-------------------------------------------------+ +| Register | Address | ++==================================================================+=================================================+ +| :ref:`PAYLOAD_EXECUTOR_START ` | :ref:`0xf0004000 ` | ++------------------------------------------------------------------+-------------------------------------------------+ +| :ref:`PAYLOAD_EXECUTOR_STATUS ` | :ref:`0xf0004004 ` | ++------------------------------------------------------------------+-------------------------------------------------+ +| :ref:`PAYLOAD_EXECUTOR_READ_COUNT ` | :ref:`0xf0004008 ` | ++------------------------------------------------------------------+-------------------------------------------------+ + +PAYLOAD_EXECUTOR_START +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0004000 + 0x0 = 0xf0004000` + + Writing to this register initializes payload execution + + .. wavedrom:: + :caption: PAYLOAD_EXECUTOR_START + + { + "reg": [ + {"name": "start", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +PAYLOAD_EXECUTOR_STATUS +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0004000 + 0x4 = 0xf0004004` + + Payload executor status register + + .. wavedrom:: + :caption: PAYLOAD_EXECUTOR_STATUS + + { + "reg": [ + {"name": "ready", "bits": 1}, + {"name": "overflow", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+----------+---------------------------------------------------------------------------------+ +| Field | Name | Description | ++=======+==========+=================================================================================+ +| [0] | READY | Indicates that the executor is not running | ++-------+----------+---------------------------------------------------------------------------------+ +| [1] | OVERFLOW | Indicates the scratchpad memory address counter has overflown due to the number | +| | | of READ commands sent during execution | ++-------+----------+---------------------------------------------------------------------------------+ + +PAYLOAD_EXECUTOR_READ_COUNT +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0004000 + 0x8 = 0xf0004008` + + Number of data from READ commands that is stored in the scratchpad memory + + .. wavedrom:: + :caption: PAYLOAD_EXECUTOR_READ_COUNT + + { + "reg": [ + {"name": "read_count[3:0]", "bits": 4}, + {"bits": 28}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/zcu104/documentation/reader.rst.txt b/_sources/build/zcu104/documentation/reader.rst.txt new file mode 100644 index 000000000..976abf3a8 --- /dev/null +++ b/_sources/build/zcu104/documentation/reader.rst.txt @@ -0,0 +1,956 @@ +READER +====== + + + +DMA DRAM reader. + +Allows to check DRAM contents against a predefined pattern using DMA. + +Pattern +------- + + + Provides access to RAM to store access pattern: `mem_addr` and `mem_data`. + The pattern address space can be limited using the `data_mask`. + + For example, having `mem_adr` filled with `[ 0x04, 0x02, 0x03, ... ]` + and `mem_data` filled with `[ 0xff, 0xaa, 0x55, ... ]` and setting + `data_mask = 0b01`, the pattern [(address, data), ...] written will be: + `[(0x04, 0xff), (0x02, 0xaa), (0x04, 0xff), ...]` (wraps due to masking). + + DRAM memory range that is being accessed can be configured using `mem_mask`. + + To use this module, make sure that `ready` is 1, then write the desired + number of transfers to `count`. Writing to the `start` CSR will initialize + the operation. When the operation is ongoing `ready` will be 0. + + +Reading errors +-------------- + +This module allows to check the locations of errors in the memory. +It scans the configured memory area and compares the values read to +the predefined pattern. If `skip_fifo` is 0, this module will stop +after each error encountered, so that it can be examined. Wait until +the `error_ready` CSR is 1. Then use the CSRs `error_offset`, +`error_data` and `error_expected` to examine the errors in the current +transfer. To continue reading, write 1 to `error_continue` CSR. +Setting `skip_fifo` to 1 will disable this behaviour entirely. + +The final number of errors can be read from `error_count`. +NOTE: This value represents the number of erroneous *DMA transfers*. + +The current progress can be read from the `done` CSR. + + +Register Listing for READER +--------------------------- + ++------------------------------------------------------------------------+----------------------------------------------------+ +| Register | Address | ++========================================================================+====================================================+ +| :ref:`READER_START ` | :ref:`0xf0003000 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_READY ` | :ref:`0xf0003004 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_MODULO ` | :ref:`0xf0003008 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_COUNT ` | :ref:`0xf000300c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_DONE ` | :ref:`0xf0003010 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_MEM_MASK ` | :ref:`0xf0003014 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_DATA_MASK ` | :ref:`0xf0003018 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_DATA_DIV ` | :ref:`0xf000301c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_INVERTER_DIVISOR_MASK ` | :ref:`0xf0003020 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_INVERTER_SELECTION_MASK ` | :ref:`0xf0003024 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_COUNT ` | :ref:`0xf0003028 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_SKIP_FIFO ` | :ref:`0xf000302c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_OFFSET ` | :ref:`0xf0003030 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA15 ` | :ref:`0xf0003034 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA14 ` | :ref:`0xf0003038 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA13 ` | :ref:`0xf000303c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA12 ` | :ref:`0xf0003040 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA11 ` | :ref:`0xf0003044 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA10 ` | :ref:`0xf0003048 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA9 ` | :ref:`0xf000304c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA8 ` | :ref:`0xf0003050 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA7 ` | :ref:`0xf0003054 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA6 ` | :ref:`0xf0003058 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA5 ` | :ref:`0xf000305c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA4 ` | :ref:`0xf0003060 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA3 ` | :ref:`0xf0003064 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA2 ` | :ref:`0xf0003068 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA1 ` | :ref:`0xf000306c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_DATA0 ` | :ref:`0xf0003070 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED15 ` | :ref:`0xf0003074 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED14 ` | :ref:`0xf0003078 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED13 ` | :ref:`0xf000307c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED12 ` | :ref:`0xf0003080 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED11 ` | :ref:`0xf0003084 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED10 ` | :ref:`0xf0003088 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED9 ` | :ref:`0xf000308c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED8 ` | :ref:`0xf0003090 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED7 ` | :ref:`0xf0003094 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED6 ` | :ref:`0xf0003098 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED5 ` | :ref:`0xf000309c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED4 ` | :ref:`0xf00030a0 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED3 ` | :ref:`0xf00030a4 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED2 ` | :ref:`0xf00030a8 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED1 ` | :ref:`0xf00030ac ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_EXPECTED0 ` | :ref:`0xf00030b0 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_READY ` | :ref:`0xf00030b4 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`READER_ERROR_CONTINUE ` | :ref:`0xf00030b8 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ + +READER_START +^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x0 = 0xf0003000` + + Write to the register starts the transfer (if ready=1) + + .. wavedrom:: + :caption: READER_START + + { + "reg": [ + {"name": "start", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_READY +^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x4 = 0xf0003004` + + Indicates that the transfer is not ongoing + + .. wavedrom:: + :caption: READER_READY + + { + "reg": [ + {"name": "ready", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_MODULO +^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x8 = 0xf0003008` + + When set use modulo to calculate DMA transfers address rather than bit masking + + .. wavedrom:: + :caption: READER_MODULO + + { + "reg": [ + {"name": "modulo", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_COUNT +^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0xc = 0xf000300c` + + Desired number of DMA transfers + + .. wavedrom:: + :caption: READER_COUNT + + { + "reg": [ + {"name": "count[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_DONE +^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x10 = 0xf0003010` + + Number of completed DMA transfers + + .. wavedrom:: + :caption: READER_DONE + + { + "reg": [ + {"name": "done[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_MEM_MASK +^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x14 = 0xf0003014` + + DRAM address mask for DMA transfers + + .. wavedrom:: + :caption: READER_MEM_MASK + + { + "reg": [ + {"name": "mem_mask[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_DATA_MASK +^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x18 = 0xf0003018` + + Pattern memory address mask + + .. wavedrom:: + :caption: READER_DATA_MASK + + { + "reg": [ + {"name": "data_mask[3:0]", "bits": 4}, + {"bits": 28}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_DATA_DIV +^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x1c = 0xf000301c` + + Pattern memory address divisior-1 + + .. wavedrom:: + :caption: READER_DATA_DIV + + { + "reg": [ + {"name": "data_div[3:0]", "bits": 4}, + {"bits": 28}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_INVERTER_DIVISOR_MASK +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x20 = 0xf0003020` + + Divisor mask for selecting rows for which pattern data gets inverted + + .. wavedrom:: + :caption: READER_INVERTER_DIVISOR_MASK + + { + "reg": [ + {"name": "inverter_divisor_mask[4:0]", "bits": 5}, + {"bits": 27}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_INVERTER_SELECTION_MASK +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x24 = 0xf0003024` + + Selection mask for selecting rows for which pattern data gets inverted + + .. wavedrom:: + :caption: READER_INVERTER_SELECTION_MASK + + { + "reg": [ + {"name": "inverter_selection_mask[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_COUNT +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x28 = 0xf0003028` + + Number of errors detected + + .. wavedrom:: + :caption: READER_ERROR_COUNT + + { + "reg": [ + {"name": "error_count[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_SKIP_FIFO +^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x2c = 0xf000302c` + + Skip waiting for user to read the errors FIFO + + .. wavedrom:: + :caption: READER_SKIP_FIFO + + { + "reg": [ + {"name": "skip_fifo", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_ERROR_OFFSET +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x30 = 0xf0003030` + + Current offset of the error + + .. wavedrom:: + :caption: READER_ERROR_OFFSET + + { + "reg": [ + {"name": "error_offset[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA15 +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x34 = 0xf0003034` + + Bits 480-511 of `READER_ERROR_DATA`. Erroneous value read from DRAM memory + + .. wavedrom:: + :caption: READER_ERROR_DATA15 + + { + "reg": [ + {"name": "error_data[511:480]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA14 +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x38 = 0xf0003038` + + Bits 448-479 of `READER_ERROR_DATA`. + + .. wavedrom:: + :caption: READER_ERROR_DATA14 + + { + "reg": [ + {"name": "error_data[479:448]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA13 +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x3c = 0xf000303c` + + Bits 416-447 of `READER_ERROR_DATA`. + + .. wavedrom:: + :caption: READER_ERROR_DATA13 + + { + "reg": [ + {"name": "error_data[447:416]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA12 +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x40 = 0xf0003040` + + Bits 384-415 of `READER_ERROR_DATA`. + + .. wavedrom:: + :caption: READER_ERROR_DATA12 + + { + "reg": [ + {"name": "error_data[415:384]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA11 +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x44 = 0xf0003044` + + Bits 352-383 of `READER_ERROR_DATA`. + + .. wavedrom:: + :caption: READER_ERROR_DATA11 + + { + "reg": [ + {"name": "error_data[383:352]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA10 +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x48 = 0xf0003048` + + Bits 320-351 of `READER_ERROR_DATA`. + + .. wavedrom:: + :caption: READER_ERROR_DATA10 + + { + "reg": [ + {"name": "error_data[351:320]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA9 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x4c = 0xf000304c` + + Bits 288-319 of `READER_ERROR_DATA`. + + .. wavedrom:: + :caption: READER_ERROR_DATA9 + + { + "reg": [ + {"name": "error_data[319:288]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA8 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x50 = 0xf0003050` + + Bits 256-287 of `READER_ERROR_DATA`. + + .. wavedrom:: + :caption: READER_ERROR_DATA8 + + { + "reg": [ + {"name": "error_data[287:256]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA7 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x54 = 0xf0003054` + + Bits 224-255 of `READER_ERROR_DATA`. + + .. wavedrom:: + :caption: READER_ERROR_DATA7 + + { + "reg": [ + {"name": "error_data[255:224]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA6 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x58 = 0xf0003058` + + Bits 192-223 of `READER_ERROR_DATA`. + + .. wavedrom:: + :caption: READER_ERROR_DATA6 + + { + "reg": [ + {"name": "error_data[223:192]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA5 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x5c = 0xf000305c` + + Bits 160-191 of `READER_ERROR_DATA`. + + .. wavedrom:: + :caption: READER_ERROR_DATA5 + + { + "reg": [ + {"name": "error_data[191:160]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA4 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x60 = 0xf0003060` + + Bits 128-159 of `READER_ERROR_DATA`. + + .. wavedrom:: + :caption: READER_ERROR_DATA4 + + { + "reg": [ + {"name": "error_data[159:128]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA3 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x64 = 0xf0003064` + + Bits 96-127 of `READER_ERROR_DATA`. + + .. wavedrom:: + :caption: READER_ERROR_DATA3 + + { + "reg": [ + {"name": "error_data[127:96]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA2 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x68 = 0xf0003068` + + Bits 64-95 of `READER_ERROR_DATA`. + + .. wavedrom:: + :caption: READER_ERROR_DATA2 + + { + "reg": [ + {"name": "error_data[95:64]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA1 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x6c = 0xf000306c` + + Bits 32-63 of `READER_ERROR_DATA`. + + .. wavedrom:: + :caption: READER_ERROR_DATA1 + + { + "reg": [ + {"name": "error_data[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_DATA0 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x70 = 0xf0003070` + + Bits 0-31 of `READER_ERROR_DATA`. + + .. wavedrom:: + :caption: READER_ERROR_DATA0 + + { + "reg": [ + {"name": "error_data[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED15 +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x74 = 0xf0003074` + + Bits 480-511 of `READER_ERROR_EXPECTED`. Value expected to be read from DRAM + memory + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED15 + + { + "reg": [ + {"name": "error_expected[511:480]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED14 +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x78 = 0xf0003078` + + Bits 448-479 of `READER_ERROR_EXPECTED`. + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED14 + + { + "reg": [ + {"name": "error_expected[479:448]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED13 +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x7c = 0xf000307c` + + Bits 416-447 of `READER_ERROR_EXPECTED`. + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED13 + + { + "reg": [ + {"name": "error_expected[447:416]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED12 +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x80 = 0xf0003080` + + Bits 384-415 of `READER_ERROR_EXPECTED`. + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED12 + + { + "reg": [ + {"name": "error_expected[415:384]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED11 +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x84 = 0xf0003084` + + Bits 352-383 of `READER_ERROR_EXPECTED`. + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED11 + + { + "reg": [ + {"name": "error_expected[383:352]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED10 +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x88 = 0xf0003088` + + Bits 320-351 of `READER_ERROR_EXPECTED`. + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED10 + + { + "reg": [ + {"name": "error_expected[351:320]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED9 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x8c = 0xf000308c` + + Bits 288-319 of `READER_ERROR_EXPECTED`. + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED9 + + { + "reg": [ + {"name": "error_expected[319:288]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED8 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x90 = 0xf0003090` + + Bits 256-287 of `READER_ERROR_EXPECTED`. + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED8 + + { + "reg": [ + {"name": "error_expected[287:256]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED7 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x94 = 0xf0003094` + + Bits 224-255 of `READER_ERROR_EXPECTED`. + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED7 + + { + "reg": [ + {"name": "error_expected[255:224]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED6 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x98 = 0xf0003098` + + Bits 192-223 of `READER_ERROR_EXPECTED`. + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED6 + + { + "reg": [ + {"name": "error_expected[223:192]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED5 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0x9c = 0xf000309c` + + Bits 160-191 of `READER_ERROR_EXPECTED`. + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED5 + + { + "reg": [ + {"name": "error_expected[191:160]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED4 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0xa0 = 0xf00030a0` + + Bits 128-159 of `READER_ERROR_EXPECTED`. + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED4 + + { + "reg": [ + {"name": "error_expected[159:128]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED3 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0xa4 = 0xf00030a4` + + Bits 96-127 of `READER_ERROR_EXPECTED`. + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED3 + + { + "reg": [ + {"name": "error_expected[127:96]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED2 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0xa8 = 0xf00030a8` + + Bits 64-95 of `READER_ERROR_EXPECTED`. + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED2 + + { + "reg": [ + {"name": "error_expected[95:64]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED1 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0xac = 0xf00030ac` + + Bits 32-63 of `READER_ERROR_EXPECTED`. + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED1 + + { + "reg": [ + {"name": "error_expected[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_EXPECTED0 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0xb0 = 0xf00030b0` + + Bits 0-31 of `READER_ERROR_EXPECTED`. + + .. wavedrom:: + :caption: READER_ERROR_EXPECTED0 + + { + "reg": [ + {"name": "error_expected[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +READER_ERROR_READY +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0xb4 = 0xf00030b4` + + Error detected and ready to read + + .. wavedrom:: + :caption: READER_ERROR_READY + + { + "reg": [ + {"name": "error_ready", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +READER_ERROR_CONTINUE +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0003000 + 0xb8 = 0xf00030b8` + + Continue reading until the next error + + .. wavedrom:: + :caption: READER_ERROR_CONTINUE + + { + "reg": [ + {"name": "error_continue", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/zcu104/documentation/rowhammer.rst.txt b/_sources/build/zcu104/documentation/rowhammer.rst.txt new file mode 100644 index 000000000..f37aa0901 --- /dev/null +++ b/_sources/build/zcu104/documentation/rowhammer.rst.txt @@ -0,0 +1,102 @@ +ROWHAMMER +========= + + + +Row Hammer DMA attacker + +This module allows to perform a Row Hammer attack by configuring it with +two addresses that map to different rows of a single bank. When enabled, +it will perform alternating DMA reads from the given locations, which will +result in the DRAM controller having to repeatedly open/close rows at each +read access. + + +Register Listing for ROWHAMMER +------------------------------ + ++------------------------------------------------+----------------------------------------+ +| Register | Address | ++================================================+========================================+ +| :ref:`ROWHAMMER_ENABLED ` | :ref:`0xf0002000 ` | ++------------------------------------------------+----------------------------------------+ +| :ref:`ROWHAMMER_ADDRESS1 ` | :ref:`0xf0002004 ` | ++------------------------------------------------+----------------------------------------+ +| :ref:`ROWHAMMER_ADDRESS2 ` | :ref:`0xf0002008 ` | ++------------------------------------------------+----------------------------------------+ +| :ref:`ROWHAMMER_COUNT ` | :ref:`0xf000200c ` | ++------------------------------------------------+----------------------------------------+ + +ROWHAMMER_ENABLED +^^^^^^^^^^^^^^^^^ + +`Address: 0xf0002000 + 0x0 = 0xf0002000` + + Used to start/stop the operation of the module + + .. wavedrom:: + :caption: ROWHAMMER_ENABLED + + { + "reg": [ + {"name": "enabled", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +ROWHAMMER_ADDRESS1 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0002000 + 0x4 = 0xf0002004` + + First attacked address + + .. wavedrom:: + :caption: ROWHAMMER_ADDRESS1 + + { + "reg": [ + {"name": "address1[25:0]", "bits": 26}, + {"bits": 6}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +ROWHAMMER_ADDRESS2 +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0002000 + 0x8 = 0xf0002008` + + Second attacked address + + .. wavedrom:: + :caption: ROWHAMMER_ADDRESS2 + + { + "reg": [ + {"name": "address2[25:0]", "bits": 26}, + {"bits": 6}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +ROWHAMMER_COUNT +^^^^^^^^^^^^^^^ + +`Address: 0xf0002000 + 0xc = 0xf000200c` + + This is the number of DMA accesses performed. When the module is enabled, the + value can be freely read. When the module is disabled, the register is clear-on- + write and has to be read before the next attack. + + .. wavedrom:: + :caption: ROWHAMMER_COUNT + + { + "reg": [ + {"name": "count[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/zcu104/documentation/sdram.rst.txt b/_sources/build/zcu104/documentation/sdram.rst.txt new file mode 100644 index 000000000..2f684ce55 --- /dev/null +++ b/_sources/build/zcu104/documentation/sdram.rst.txt @@ -0,0 +1,1631 @@ +SDRAM +===== + +Register Listing for SDRAM +-------------------------- + ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| Register | Address | ++================================================================================+========================================================+ +| :ref:`SDRAM_DFII_CONTROL ` | :ref:`0xf0006000 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI0_COMMAND ` | :ref:`0xf0006004 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI0_COMMAND_ISSUE ` | :ref:`0xf0006008 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI0_ADDRESS ` | :ref:`0xf000600c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI0_BADDRESS ` | :ref:`0xf0006010 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI0_WRDATA3 ` | :ref:`0xf0006014 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI0_WRDATA2 ` | :ref:`0xf0006018 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI0_WRDATA1 ` | :ref:`0xf000601c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI0_WRDATA0 ` | :ref:`0xf0006020 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI0_RDDATA3 ` | :ref:`0xf0006024 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI0_RDDATA2 ` | :ref:`0xf0006028 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI0_RDDATA1 ` | :ref:`0xf000602c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI0_RDDATA0 ` | :ref:`0xf0006030 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI1_COMMAND ` | :ref:`0xf0006034 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI1_COMMAND_ISSUE ` | :ref:`0xf0006038 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI1_ADDRESS ` | :ref:`0xf000603c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI1_BADDRESS ` | :ref:`0xf0006040 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI1_WRDATA3 ` | :ref:`0xf0006044 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI1_WRDATA2 ` | :ref:`0xf0006048 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI1_WRDATA1 ` | :ref:`0xf000604c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI1_WRDATA0 ` | :ref:`0xf0006050 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI1_RDDATA3 ` | :ref:`0xf0006054 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI1_RDDATA2 ` | :ref:`0xf0006058 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI1_RDDATA1 ` | :ref:`0xf000605c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI1_RDDATA0 ` | :ref:`0xf0006060 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI2_COMMAND ` | :ref:`0xf0006064 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI2_COMMAND_ISSUE ` | :ref:`0xf0006068 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI2_ADDRESS ` | :ref:`0xf000606c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI2_BADDRESS ` | :ref:`0xf0006070 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI2_WRDATA3 ` | :ref:`0xf0006074 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI2_WRDATA2 ` | :ref:`0xf0006078 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI2_WRDATA1 ` | :ref:`0xf000607c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI2_WRDATA0 ` | :ref:`0xf0006080 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI2_RDDATA3 ` | :ref:`0xf0006084 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI2_RDDATA2 ` | :ref:`0xf0006088 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI2_RDDATA1 ` | :ref:`0xf000608c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI2_RDDATA0 ` | :ref:`0xf0006090 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI3_COMMAND ` | :ref:`0xf0006094 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI3_COMMAND_ISSUE ` | :ref:`0xf0006098 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI3_ADDRESS ` | :ref:`0xf000609c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI3_BADDRESS ` | :ref:`0xf00060a0 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI3_WRDATA3 ` | :ref:`0xf00060a4 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI3_WRDATA2 ` | :ref:`0xf00060a8 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI3_WRDATA1 ` | :ref:`0xf00060ac ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI3_WRDATA0 ` | :ref:`0xf00060b0 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI3_RDDATA3 ` | :ref:`0xf00060b4 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI3_RDDATA2 ` | :ref:`0xf00060b8 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI3_RDDATA1 ` | :ref:`0xf00060bc ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_DFII_PI3_RDDATA0 ` | :ref:`0xf00060c0 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRP ` | :ref:`0xf00060c4 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRCD ` | :ref:`0xf00060c8 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TWR ` | :ref:`0xf00060cc ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TWTR ` | :ref:`0xf00060d0 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TREFI ` | :ref:`0xf00060d4 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRFC ` | :ref:`0xf00060d8 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TFAW ` | :ref:`0xf00060dc ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TCCD ` | :ref:`0xf00060e0 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TCCD_WR ` | :ref:`0xf00060e4 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRTP ` | :ref:`0xf00060e8 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRRD ` | :ref:`0xf00060ec ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRC ` | :ref:`0xf00060f0 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TRAS ` | :ref:`0xf00060f4 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_TZQCS ` | :ref:`0xf00060f8 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_0 ` | :ref:`0xf00060fc ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_0 ` | :ref:`0xf0006100 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_1 ` | :ref:`0xf0006104 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_1 ` | :ref:`0xf0006108 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_2 ` | :ref:`0xf000610c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_2 ` | :ref:`0xf0006110 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_3 ` | :ref:`0xf0006114 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_3 ` | :ref:`0xf0006118 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_4 ` | :ref:`0xf000611c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_4 ` | :ref:`0xf0006120 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_5 ` | :ref:`0xf0006124 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_5 ` | :ref:`0xf0006128 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_6 ` | :ref:`0xf000612c ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_6 ` | :ref:`0xf0006130 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ADDR_7 ` | :ref:`0xf0006134 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ +| :ref:`SDRAM_CONTROLLER_LAST_ACTIVE_ROW_7 ` | :ref:`0xf0006138 ` | ++--------------------------------------------------------------------------------+--------------------------------------------------------+ + +SDRAM_DFII_CONTROL +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x0 = 0xf0006000` + + Control DFI signals common to all phases + + .. wavedrom:: + :caption: SDRAM_DFII_CONTROL + + { + "reg": [ + {"name": "sel", "attr": '1', "bits": 1}, + {"name": "cke", "bits": 1}, + {"name": "odt", "bits": 1}, + {"name": "reset_n", "bits": 1}, + {"bits": 28} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+---------+-------------------------------------------+ +| Field | Name | Description | ++=======+=========+===========================================+ +| [0] | SEL | | +| | | | +| | | +---------+-----------------------------+ | +| | | | Value | Description | | +| | | +=========+=============================+ | +| | | | ``0b0`` | Software (CPU) control. | | +| | | +---------+-----------------------------+ | +| | | | ``0b1`` | Hardware control (default). | | +| | | +---------+-----------------------------+ | ++-------+---------+-------------------------------------------+ +| [1] | CKE | DFI clock enable bus | ++-------+---------+-------------------------------------------+ +| [2] | ODT | DFI on-die termination bus | ++-------+---------+-------------------------------------------+ +| [3] | RESET_N | DFI clock reset bus | ++-------+---------+-------------------------------------------+ + +SDRAM_DFII_PI0_COMMAND +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x4 = 0xf0006004` + + Control DFI signals on a single phase + + .. wavedrom:: + :caption: SDRAM_DFII_PI0_COMMAND + + { + "reg": [ + {"name": "cs", "bits": 1}, + {"name": "we", "bits": 1}, + {"name": "cas", "bits": 1}, + {"name": "ras", "bits": 1}, + {"name": "wren", "bits": 1}, + {"name": "rden", "bits": 1}, + {"bits": 26} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------------------------+ +| Field | Name | Description | ++=======+======+===============================+ +| [0] | CS | DFI chip select bus | ++-------+------+-------------------------------+ +| [1] | WE | DFI write enable bus | ++-------+------+-------------------------------+ +| [2] | CAS | DFI column address strobe bus | ++-------+------+-------------------------------+ +| [3] | RAS | DFI row address strobe bus | ++-------+------+-------------------------------+ +| [4] | WREN | DFI write data enable bus | ++-------+------+-------------------------------+ +| [5] | RDEN | DFI read data enable bus | ++-------+------+-------------------------------+ + +SDRAM_DFII_PI0_COMMAND_ISSUE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x8 = 0xf0006008` + + + .. wavedrom:: + :caption: SDRAM_DFII_PI0_COMMAND_ISSUE + + { + "reg": [ + {"name": "dfii_pi0_command_issue", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_PI0_ADDRESS +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xc = 0xf000600c` + + DFI address bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI0_ADDRESS + + { + "reg": [ + {"name": "dfii_pi0_address[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI0_BADDRESS +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x10 = 0xf0006010` + + DFI bank address bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI0_BADDRESS + + { + "reg": [ + {"name": "dfii_pi0_baddress[2:0]", "bits": 3}, + {"bits": 29}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_PI0_WRDATA3 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x14 = 0xf0006014` + + Bits 96-127 of `SDRAM_DFII_PI0_WRDATA`. DFI write data bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI0_WRDATA3 + + { + "reg": [ + {"name": "dfii_pi0_wrdata[127:96]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI0_WRDATA2 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x18 = 0xf0006018` + + Bits 64-95 of `SDRAM_DFII_PI0_WRDATA`. + + .. wavedrom:: + :caption: SDRAM_DFII_PI0_WRDATA2 + + { + "reg": [ + {"name": "dfii_pi0_wrdata[95:64]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI0_WRDATA1 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x1c = 0xf000601c` + + Bits 32-63 of `SDRAM_DFII_PI0_WRDATA`. + + .. wavedrom:: + :caption: SDRAM_DFII_PI0_WRDATA1 + + { + "reg": [ + {"name": "dfii_pi0_wrdata[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI0_WRDATA0 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x20 = 0xf0006020` + + Bits 0-31 of `SDRAM_DFII_PI0_WRDATA`. + + .. wavedrom:: + :caption: SDRAM_DFII_PI0_WRDATA0 + + { + "reg": [ + {"name": "dfii_pi0_wrdata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI0_RDDATA3 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x24 = 0xf0006024` + + Bits 96-127 of `SDRAM_DFII_PI0_RDDATA`. DFI read data bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI0_RDDATA3 + + { + "reg": [ + {"name": "dfii_pi0_rddata[127:96]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI0_RDDATA2 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x28 = 0xf0006028` + + Bits 64-95 of `SDRAM_DFII_PI0_RDDATA`. + + .. wavedrom:: + :caption: SDRAM_DFII_PI0_RDDATA2 + + { + "reg": [ + {"name": "dfii_pi0_rddata[95:64]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI0_RDDATA1 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x2c = 0xf000602c` + + Bits 32-63 of `SDRAM_DFII_PI0_RDDATA`. + + .. wavedrom:: + :caption: SDRAM_DFII_PI0_RDDATA1 + + { + "reg": [ + {"name": "dfii_pi0_rddata[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI0_RDDATA0 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x30 = 0xf0006030` + + Bits 0-31 of `SDRAM_DFII_PI0_RDDATA`. + + .. wavedrom:: + :caption: SDRAM_DFII_PI0_RDDATA0 + + { + "reg": [ + {"name": "dfii_pi0_rddata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI1_COMMAND +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x34 = 0xf0006034` + + Control DFI signals on a single phase + + .. wavedrom:: + :caption: SDRAM_DFII_PI1_COMMAND + + { + "reg": [ + {"name": "cs", "bits": 1}, + {"name": "we", "bits": 1}, + {"name": "cas", "bits": 1}, + {"name": "ras", "bits": 1}, + {"name": "wren", "bits": 1}, + {"name": "rden", "bits": 1}, + {"bits": 26} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------------------------+ +| Field | Name | Description | ++=======+======+===============================+ +| [0] | CS | DFI chip select bus | ++-------+------+-------------------------------+ +| [1] | WE | DFI write enable bus | ++-------+------+-------------------------------+ +| [2] | CAS | DFI column address strobe bus | ++-------+------+-------------------------------+ +| [3] | RAS | DFI row address strobe bus | ++-------+------+-------------------------------+ +| [4] | WREN | DFI write data enable bus | ++-------+------+-------------------------------+ +| [5] | RDEN | DFI read data enable bus | ++-------+------+-------------------------------+ + +SDRAM_DFII_PI1_COMMAND_ISSUE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x38 = 0xf0006038` + + + .. wavedrom:: + :caption: SDRAM_DFII_PI1_COMMAND_ISSUE + + { + "reg": [ + {"name": "dfii_pi1_command_issue", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_PI1_ADDRESS +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x3c = 0xf000603c` + + DFI address bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI1_ADDRESS + + { + "reg": [ + {"name": "dfii_pi1_address[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI1_BADDRESS +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x40 = 0xf0006040` + + DFI bank address bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI1_BADDRESS + + { + "reg": [ + {"name": "dfii_pi1_baddress[2:0]", "bits": 3}, + {"bits": 29}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_PI1_WRDATA3 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x44 = 0xf0006044` + + Bits 96-127 of `SDRAM_DFII_PI1_WRDATA`. DFI write data bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI1_WRDATA3 + + { + "reg": [ + {"name": "dfii_pi1_wrdata[127:96]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI1_WRDATA2 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x48 = 0xf0006048` + + Bits 64-95 of `SDRAM_DFII_PI1_WRDATA`. + + .. wavedrom:: + :caption: SDRAM_DFII_PI1_WRDATA2 + + { + "reg": [ + {"name": "dfii_pi1_wrdata[95:64]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI1_WRDATA1 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x4c = 0xf000604c` + + Bits 32-63 of `SDRAM_DFII_PI1_WRDATA`. + + .. wavedrom:: + :caption: SDRAM_DFII_PI1_WRDATA1 + + { + "reg": [ + {"name": "dfii_pi1_wrdata[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI1_WRDATA0 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x50 = 0xf0006050` + + Bits 0-31 of `SDRAM_DFII_PI1_WRDATA`. + + .. wavedrom:: + :caption: SDRAM_DFII_PI1_WRDATA0 + + { + "reg": [ + {"name": "dfii_pi1_wrdata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI1_RDDATA3 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x54 = 0xf0006054` + + Bits 96-127 of `SDRAM_DFII_PI1_RDDATA`. DFI read data bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI1_RDDATA3 + + { + "reg": [ + {"name": "dfii_pi1_rddata[127:96]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI1_RDDATA2 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x58 = 0xf0006058` + + Bits 64-95 of `SDRAM_DFII_PI1_RDDATA`. + + .. wavedrom:: + :caption: SDRAM_DFII_PI1_RDDATA2 + + { + "reg": [ + {"name": "dfii_pi1_rddata[95:64]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI1_RDDATA1 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x5c = 0xf000605c` + + Bits 32-63 of `SDRAM_DFII_PI1_RDDATA`. + + .. wavedrom:: + :caption: SDRAM_DFII_PI1_RDDATA1 + + { + "reg": [ + {"name": "dfii_pi1_rddata[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI1_RDDATA0 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x60 = 0xf0006060` + + Bits 0-31 of `SDRAM_DFII_PI1_RDDATA`. + + .. wavedrom:: + :caption: SDRAM_DFII_PI1_RDDATA0 + + { + "reg": [ + {"name": "dfii_pi1_rddata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI2_COMMAND +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x64 = 0xf0006064` + + Control DFI signals on a single phase + + .. wavedrom:: + :caption: SDRAM_DFII_PI2_COMMAND + + { + "reg": [ + {"name": "cs", "bits": 1}, + {"name": "we", "bits": 1}, + {"name": "cas", "bits": 1}, + {"name": "ras", "bits": 1}, + {"name": "wren", "bits": 1}, + {"name": "rden", "bits": 1}, + {"bits": 26} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------------------------+ +| Field | Name | Description | ++=======+======+===============================+ +| [0] | CS | DFI chip select bus | ++-------+------+-------------------------------+ +| [1] | WE | DFI write enable bus | ++-------+------+-------------------------------+ +| [2] | CAS | DFI column address strobe bus | ++-------+------+-------------------------------+ +| [3] | RAS | DFI row address strobe bus | ++-------+------+-------------------------------+ +| [4] | WREN | DFI write data enable bus | ++-------+------+-------------------------------+ +| [5] | RDEN | DFI read data enable bus | ++-------+------+-------------------------------+ + +SDRAM_DFII_PI2_COMMAND_ISSUE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x68 = 0xf0006068` + + + .. wavedrom:: + :caption: SDRAM_DFII_PI2_COMMAND_ISSUE + + { + "reg": [ + {"name": "dfii_pi2_command_issue", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_PI2_ADDRESS +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x6c = 0xf000606c` + + DFI address bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI2_ADDRESS + + { + "reg": [ + {"name": "dfii_pi2_address[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI2_BADDRESS +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x70 = 0xf0006070` + + DFI bank address bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI2_BADDRESS + + { + "reg": [ + {"name": "dfii_pi2_baddress[2:0]", "bits": 3}, + {"bits": 29}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_PI2_WRDATA3 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x74 = 0xf0006074` + + Bits 96-127 of `SDRAM_DFII_PI2_WRDATA`. DFI write data bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI2_WRDATA3 + + { + "reg": [ + {"name": "dfii_pi2_wrdata[127:96]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI2_WRDATA2 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x78 = 0xf0006078` + + Bits 64-95 of `SDRAM_DFII_PI2_WRDATA`. + + .. wavedrom:: + :caption: SDRAM_DFII_PI2_WRDATA2 + + { + "reg": [ + {"name": "dfii_pi2_wrdata[95:64]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI2_WRDATA1 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x7c = 0xf000607c` + + Bits 32-63 of `SDRAM_DFII_PI2_WRDATA`. + + .. wavedrom:: + :caption: SDRAM_DFII_PI2_WRDATA1 + + { + "reg": [ + {"name": "dfii_pi2_wrdata[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI2_WRDATA0 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x80 = 0xf0006080` + + Bits 0-31 of `SDRAM_DFII_PI2_WRDATA`. + + .. wavedrom:: + :caption: SDRAM_DFII_PI2_WRDATA0 + + { + "reg": [ + {"name": "dfii_pi2_wrdata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI2_RDDATA3 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x84 = 0xf0006084` + + Bits 96-127 of `SDRAM_DFII_PI2_RDDATA`. DFI read data bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI2_RDDATA3 + + { + "reg": [ + {"name": "dfii_pi2_rddata[127:96]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI2_RDDATA2 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x88 = 0xf0006088` + + Bits 64-95 of `SDRAM_DFII_PI2_RDDATA`. + + .. wavedrom:: + :caption: SDRAM_DFII_PI2_RDDATA2 + + { + "reg": [ + {"name": "dfii_pi2_rddata[95:64]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI2_RDDATA1 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x8c = 0xf000608c` + + Bits 32-63 of `SDRAM_DFII_PI2_RDDATA`. + + .. wavedrom:: + :caption: SDRAM_DFII_PI2_RDDATA1 + + { + "reg": [ + {"name": "dfii_pi2_rddata[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI2_RDDATA0 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x90 = 0xf0006090` + + Bits 0-31 of `SDRAM_DFII_PI2_RDDATA`. + + .. wavedrom:: + :caption: SDRAM_DFII_PI2_RDDATA0 + + { + "reg": [ + {"name": "dfii_pi2_rddata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI3_COMMAND +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x94 = 0xf0006094` + + Control DFI signals on a single phase + + .. wavedrom:: + :caption: SDRAM_DFII_PI3_COMMAND + + { + "reg": [ + {"name": "cs", "bits": 1}, + {"name": "we", "bits": 1}, + {"name": "cas", "bits": 1}, + {"name": "ras", "bits": 1}, + {"name": "wren", "bits": 1}, + {"name": "rden", "bits": 1}, + {"bits": 26} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------------------------+ +| Field | Name | Description | ++=======+======+===============================+ +| [0] | CS | DFI chip select bus | ++-------+------+-------------------------------+ +| [1] | WE | DFI write enable bus | ++-------+------+-------------------------------+ +| [2] | CAS | DFI column address strobe bus | ++-------+------+-------------------------------+ +| [3] | RAS | DFI row address strobe bus | ++-------+------+-------------------------------+ +| [4] | WREN | DFI write data enable bus | ++-------+------+-------------------------------+ +| [5] | RDEN | DFI read data enable bus | ++-------+------+-------------------------------+ + +SDRAM_DFII_PI3_COMMAND_ISSUE +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x98 = 0xf0006098` + + + .. wavedrom:: + :caption: SDRAM_DFII_PI3_COMMAND_ISSUE + + { + "reg": [ + {"name": "dfii_pi3_command_issue", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_PI3_ADDRESS +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x9c = 0xf000609c` + + DFI address bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI3_ADDRESS + + { + "reg": [ + {"name": "dfii_pi3_address[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI3_BADDRESS +^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xa0 = 0xf00060a0` + + DFI bank address bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI3_BADDRESS + + { + "reg": [ + {"name": "dfii_pi3_baddress[2:0]", "bits": 3}, + {"bits": 29}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_DFII_PI3_WRDATA3 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xa4 = 0xf00060a4` + + Bits 96-127 of `SDRAM_DFII_PI3_WRDATA`. DFI write data bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI3_WRDATA3 + + { + "reg": [ + {"name": "dfii_pi3_wrdata[127:96]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI3_WRDATA2 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xa8 = 0xf00060a8` + + Bits 64-95 of `SDRAM_DFII_PI3_WRDATA`. + + .. wavedrom:: + :caption: SDRAM_DFII_PI3_WRDATA2 + + { + "reg": [ + {"name": "dfii_pi3_wrdata[95:64]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI3_WRDATA1 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xac = 0xf00060ac` + + Bits 32-63 of `SDRAM_DFII_PI3_WRDATA`. + + .. wavedrom:: + :caption: SDRAM_DFII_PI3_WRDATA1 + + { + "reg": [ + {"name": "dfii_pi3_wrdata[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI3_WRDATA0 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xb0 = 0xf00060b0` + + Bits 0-31 of `SDRAM_DFII_PI3_WRDATA`. + + .. wavedrom:: + :caption: SDRAM_DFII_PI3_WRDATA0 + + { + "reg": [ + {"name": "dfii_pi3_wrdata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI3_RDDATA3 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xb4 = 0xf00060b4` + + Bits 96-127 of `SDRAM_DFII_PI3_RDDATA`. DFI read data bus + + .. wavedrom:: + :caption: SDRAM_DFII_PI3_RDDATA3 + + { + "reg": [ + {"name": "dfii_pi3_rddata[127:96]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI3_RDDATA2 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xb8 = 0xf00060b8` + + Bits 64-95 of `SDRAM_DFII_PI3_RDDATA`. + + .. wavedrom:: + :caption: SDRAM_DFII_PI3_RDDATA2 + + { + "reg": [ + {"name": "dfii_pi3_rddata[95:64]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI3_RDDATA1 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xbc = 0xf00060bc` + + Bits 32-63 of `SDRAM_DFII_PI3_RDDATA`. + + .. wavedrom:: + :caption: SDRAM_DFII_PI3_RDDATA1 + + { + "reg": [ + {"name": "dfii_pi3_rddata[63:32]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_DFII_PI3_RDDATA0 +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xc0 = 0xf00060c0` + + Bits 0-31 of `SDRAM_DFII_PI3_RDDATA`. + + .. wavedrom:: + :caption: SDRAM_DFII_PI3_RDDATA0 + + { + "reg": [ + {"name": "dfii_pi3_rddata[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_TRP +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xc4 = 0xf00060c4` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRP + + { + "reg": [ + {"name": "controller_trp[1:0]", "attr": 'reset: 3', "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TRCD +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xc8 = 0xf00060c8` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRCD + + { + "reg": [ + {"name": "controller_trcd[1:0]", "attr": 'reset: 3', "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TWR +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xcc = 0xf00060cc` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TWR + + { + "reg": [ + {"name": "controller_twr[1:0]", "attr": 'reset: 3', "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TWTR +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xd0 = 0xf00060d0` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TWTR + + { + "reg": [ + {"name": "controller_twtr[1:0]", "attr": 'reset: 2', "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TREFI +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xd4 = 0xf00060d4` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TREFI + + { + "reg": [ + {"name": "controller_trefi[9:0]", "attr": 'reset: 977', "bits": 10}, + {"bits": 22}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_TRFC +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xd8 = 0xf00060d8` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRFC + + { + "reg": [ + {"name": "controller_trfc[6:0]", "attr": 'reset: 45', "bits": 7}, + {"bits": 25}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TFAW +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xdc = 0xf00060dc` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TFAW + + { + "reg": [ + {"name": "controller_tfaw[2:0]", "attr": 'reset: 5', "bits": 3}, + {"bits": 29}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TCCD +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xe0 = 0xf00060e0` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TCCD + + { + "reg": [ + {"name": "controller_tccd[1:0]", "attr": 'reset: 1', "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TCCD_WR +^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xe4 = 0xf00060e4` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TCCD_WR + + { + "reg": [ + {"name": "controller_tccd_wr", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TRTP +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xe8 = 0xf00060e8` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRTP + + { + "reg": [ + {"name": "controller_trtp", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TRRD +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xec = 0xf00060ec` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRRD + + { + "reg": [ + {"name": "controller_trrd[1:0]", "attr": 'reset: 2', "bits": 2}, + {"bits": 30}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TRC +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xf0 = 0xf00060f0` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRC + + { + "reg": [ + {"name": "controller_trc[2:0]", "attr": 'reset: 7', "bits": 3}, + {"bits": 29}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TRAS +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xf4 = 0xf00060f4` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TRAS + + { + "reg": [ + {"name": "controller_tras[2:0]", "attr": 'reset: 5', "bits": 3}, + {"bits": 29}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CONTROLLER_TZQCS +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xf8 = 0xf00060f8` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_TZQCS + + { + "reg": [ + {"name": "controller_tzqcs[7:0]", "attr": 'reset: 32', "bits": 8}, + {"bits": 24}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_0 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0xfc = 0xf00060fc` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_0 + + { + "reg": [ + {"name": "controller_last_addr_0[22:0]", "bits": 23}, + {"bits": 9}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_0 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x100 = 0xf0006100` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_0 + + { + "reg": [ + {"name": "controller_last_active_row_0[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_1 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x104 = 0xf0006104` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_1 + + { + "reg": [ + {"name": "controller_last_addr_1[22:0]", "bits": 23}, + {"bits": 9}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_1 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x108 = 0xf0006108` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_1 + + { + "reg": [ + {"name": "controller_last_active_row_1[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_2 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x10c = 0xf000610c` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_2 + + { + "reg": [ + {"name": "controller_last_addr_2[22:0]", "bits": 23}, + {"bits": 9}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_2 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x110 = 0xf0006110` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_2 + + { + "reg": [ + {"name": "controller_last_active_row_2[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_3 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x114 = 0xf0006114` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_3 + + { + "reg": [ + {"name": "controller_last_addr_3[22:0]", "bits": 23}, + {"bits": 9}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_3 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x118 = 0xf0006118` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_3 + + { + "reg": [ + {"name": "controller_last_active_row_3[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_4 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x11c = 0xf000611c` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_4 + + { + "reg": [ + {"name": "controller_last_addr_4[22:0]", "bits": 23}, + {"bits": 9}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_4 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x120 = 0xf0006120` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_4 + + { + "reg": [ + {"name": "controller_last_active_row_4[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_5 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x124 = 0xf0006124` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_5 + + { + "reg": [ + {"name": "controller_last_addr_5[22:0]", "bits": 23}, + {"bits": 9}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_5 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x128 = 0xf0006128` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_5 + + { + "reg": [ + {"name": "controller_last_active_row_5[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_6 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x12c = 0xf000612c` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_6 + + { + "reg": [ + {"name": "controller_last_addr_6[22:0]", "bits": 23}, + {"bits": 9}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_6 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x130 = 0xf0006130` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_6 + + { + "reg": [ + {"name": "controller_last_active_row_6[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ADDR_7 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x134 = 0xf0006134` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ADDR_7 + + { + "reg": [ + {"name": "controller_last_addr_7[22:0]", "bits": 23}, + {"bits": 9}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CONTROLLER_LAST_ACTIVE_ROW_7 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006000 + 0x138 = 0xf0006138` + + + .. wavedrom:: + :caption: SDRAM_CONTROLLER_LAST_ACTIVE_ROW_7 + + { + "reg": [ + {"name": "controller_last_active_row_7[15:0]", "bits": 16}, + {"bits": 16}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/zcu104/documentation/sdram_checker.rst.txt b/_sources/build/zcu104/documentation/sdram_checker.rst.txt new file mode 100644 index 000000000..d391ab821 --- /dev/null +++ b/_sources/build/zcu104/documentation/sdram_checker.rst.txt @@ -0,0 +1,183 @@ +SDRAM_CHECKER +============= + +Register Listing for SDRAM_CHECKER +---------------------------------- + ++----------------------------------------------------+------------------------------------------+ +| Register | Address | ++====================================================+==========================================+ +| :ref:`SDRAM_CHECKER_RESET ` | :ref:`0xf0006800 ` | ++----------------------------------------------------+------------------------------------------+ +| :ref:`SDRAM_CHECKER_START ` | :ref:`0xf0006804 ` | ++----------------------------------------------------+------------------------------------------+ +| :ref:`SDRAM_CHECKER_DONE ` | :ref:`0xf0006808 ` | ++----------------------------------------------------+------------------------------------------+ +| :ref:`SDRAM_CHECKER_BASE ` | :ref:`0xf000680c ` | ++----------------------------------------------------+------------------------------------------+ +| :ref:`SDRAM_CHECKER_END ` | :ref:`0xf0006810 ` | ++----------------------------------------------------+------------------------------------------+ +| :ref:`SDRAM_CHECKER_LENGTH ` | :ref:`0xf0006814 ` | ++----------------------------------------------------+------------------------------------------+ +| :ref:`SDRAM_CHECKER_RANDOM ` | :ref:`0xf0006818 ` | ++----------------------------------------------------+------------------------------------------+ +| :ref:`SDRAM_CHECKER_TICKS ` | :ref:`0xf000681c ` | ++----------------------------------------------------+------------------------------------------+ +| :ref:`SDRAM_CHECKER_ERRORS ` | :ref:`0xf0006820 ` | ++----------------------------------------------------+------------------------------------------+ + +SDRAM_CHECKER_RESET +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x0 = 0xf0006800` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_RESET + + { + "reg": [ + {"name": "reset", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CHECKER_START +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x4 = 0xf0006804` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_START + + { + "reg": [ + {"name": "start", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CHECKER_DONE +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x8 = 0xf0006808` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_DONE + + { + "reg": [ + {"name": "done", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_CHECKER_BASE +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0xc = 0xf000680c` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_BASE + + { + "reg": [ + {"name": "base[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CHECKER_END +^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x10 = 0xf0006810` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_END + + { + "reg": [ + {"name": "end[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CHECKER_LENGTH +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x14 = 0xf0006814` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_LENGTH + + { + "reg": [ + {"name": "length[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CHECKER_RANDOM +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x18 = 0xf0006818` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_RANDOM + + { + "reg": [ + {"name": "data", "bits": 1}, + {"name": "addr", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------+ +| Field | Name | Description | ++=======+======+=============+ ++-------+------+-------------+ ++-------+------+-------------+ + +SDRAM_CHECKER_TICKS +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x1c = 0xf000681c` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_TICKS + + { + "reg": [ + {"name": "ticks[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_CHECKER_ERRORS +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0006800 + 0x20 = 0xf0006820` + + + .. wavedrom:: + :caption: SDRAM_CHECKER_ERRORS + + { + "reg": [ + {"name": "errors[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/zcu104/documentation/sdram_generator.rst.txt b/_sources/build/zcu104/documentation/sdram_generator.rst.txt new file mode 100644 index 000000000..37cca0e0e --- /dev/null +++ b/_sources/build/zcu104/documentation/sdram_generator.rst.txt @@ -0,0 +1,165 @@ +SDRAM_GENERATOR +=============== + +Register Listing for SDRAM_GENERATOR +------------------------------------ + ++--------------------------------------------------------+--------------------------------------------+ +| Register | Address | ++========================================================+============================================+ +| :ref:`SDRAM_GENERATOR_RESET ` | :ref:`0xf0007000 ` | ++--------------------------------------------------------+--------------------------------------------+ +| :ref:`SDRAM_GENERATOR_START ` | :ref:`0xf0007004 ` | ++--------------------------------------------------------+--------------------------------------------+ +| :ref:`SDRAM_GENERATOR_DONE ` | :ref:`0xf0007008 ` | ++--------------------------------------------------------+--------------------------------------------+ +| :ref:`SDRAM_GENERATOR_BASE ` | :ref:`0xf000700c ` | ++--------------------------------------------------------+--------------------------------------------+ +| :ref:`SDRAM_GENERATOR_END ` | :ref:`0xf0007010 ` | ++--------------------------------------------------------+--------------------------------------------+ +| :ref:`SDRAM_GENERATOR_LENGTH ` | :ref:`0xf0007014 ` | ++--------------------------------------------------------+--------------------------------------------+ +| :ref:`SDRAM_GENERATOR_RANDOM ` | :ref:`0xf0007018 ` | ++--------------------------------------------------------+--------------------------------------------+ +| :ref:`SDRAM_GENERATOR_TICKS ` | :ref:`0xf000701c ` | ++--------------------------------------------------------+--------------------------------------------+ + +SDRAM_GENERATOR_RESET +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x0 = 0xf0007000` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_RESET + + { + "reg": [ + {"name": "reset", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_GENERATOR_START +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x4 = 0xf0007004` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_START + + { + "reg": [ + {"name": "start", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_GENERATOR_DONE +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x8 = 0xf0007008` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_DONE + + { + "reg": [ + {"name": "done", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +SDRAM_GENERATOR_BASE +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0xc = 0xf000700c` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_BASE + + { + "reg": [ + {"name": "base[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_GENERATOR_END +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x10 = 0xf0007010` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_END + + { + "reg": [ + {"name": "end[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_GENERATOR_LENGTH +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x14 = 0xf0007014` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_LENGTH + + { + "reg": [ + {"name": "length[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +SDRAM_GENERATOR_RANDOM +^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x18 = 0xf0007018` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_RANDOM + + { + "reg": [ + {"name": "data", "bits": 1}, + {"name": "addr", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-------------+ +| Field | Name | Description | ++=======+======+=============+ ++-------+------+-------------+ ++-------+------+-------------+ + +SDRAM_GENERATOR_TICKS +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007000 + 0x1c = 0xf000701c` + + + .. wavedrom:: + :caption: SDRAM_GENERATOR_TICKS + + { + "reg": [ + {"name": "ticks[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/build/zcu104/documentation/timer0.rst.txt b/_sources/build/zcu104/documentation/timer0.rst.txt new file mode 100644 index 000000000..4cf544f1c --- /dev/null +++ b/_sources/build/zcu104/documentation/timer0.rst.txt @@ -0,0 +1,228 @@ +TIMER0 +====== + +Timer +----- + +Provides a generic Timer core. + +The Timer is implemented as a countdown timer that can be used in various modes: + +- Polling : Returns current countdown value to software +- One-Shot: Loads itself and stops when value reaches ``0`` +- Periodic: (Re-)Loads itself when value reaches ``0`` + +``en`` register allows the user to enable/disable the Timer. When the Timer is enabled, it is +automatically loaded with the value of `load` register. + +When the Timer reaches ``0``, it is automatically reloaded with value of `reload` register. + +The user can latch the current countdown value by writing to ``update_value`` register, it will +update ``value`` register with current countdown value. + +To use the Timer in One-Shot mode, the user needs to: + +- Disable the timer +- Set the ``load`` register to the expected duration +- (Re-)Enable the Timer + +To use the Timer in Periodic mode, the user needs to: + +- Disable the Timer +- Set the ``load`` register to 0 +- Set the ``reload`` register to the expected period +- Enable the Timer + +For both modes, the CPU can be advertised by an IRQ that the duration/period has elapsed. (The +CPU can also do software polling with ``update_value`` and ``value`` to know the elapsed duration) + + +Register Listing for TIMER0 +--------------------------- + ++--------------------------------------------------+-----------------------------------------+ +| Register | Address | ++==================================================+=========================================+ +| :ref:`TIMER0_LOAD ` | :ref:`0xf0007800 ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_RELOAD ` | :ref:`0xf0007804 ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_EN ` | :ref:`0xf0007808 ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_UPDATE_VALUE ` | :ref:`0xf000780c ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_VALUE ` | :ref:`0xf0007810 ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_EV_STATUS ` | :ref:`0xf0007814 ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_EV_PENDING ` | :ref:`0xf0007818 ` | ++--------------------------------------------------+-----------------------------------------+ +| :ref:`TIMER0_EV_ENABLE ` | :ref:`0xf000781c ` | ++--------------------------------------------------+-----------------------------------------+ + +TIMER0_LOAD +^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x0 = 0xf0007800` + + Load value when Timer is (re-)enabled. In One-Shot mode, the value written to + this register specifies the Timer's duration in clock cycles. + + .. wavedrom:: + :caption: TIMER0_LOAD + + { + "reg": [ + {"name": "load[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +TIMER0_RELOAD +^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x4 = 0xf0007804` + + Reload value when Timer reaches ``0``. In Periodic mode, the value written to + this register specify the Timer's period in clock cycles. + + .. wavedrom:: + :caption: TIMER0_RELOAD + + { + "reg": [ + {"name": "reload[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +TIMER0_EN +^^^^^^^^^ + +`Address: 0xf0007800 + 0x8 = 0xf0007808` + + Enable flag of the Timer. Set this flag to ``1`` to enable/start the Timer. Set + to ``0`` to disable the Timer. + + .. wavedrom:: + :caption: TIMER0_EN + + { + "reg": [ + {"name": "en", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +TIMER0_UPDATE_VALUE +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0xc = 0xf000780c` + + Update trigger for the current countdown value. A write to this register latches + the current countdown value to ``value`` register. + + .. wavedrom:: + :caption: TIMER0_UPDATE_VALUE + + { + "reg": [ + {"name": "update_value", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +TIMER0_VALUE +^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x10 = 0xf0007810` + + Latched countdown value. This value is updated by writing to ``update_value``. + + .. wavedrom:: + :caption: TIMER0_VALUE + + { + "reg": [ + {"name": "value[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +TIMER0_EV_STATUS +^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x14 = 0xf0007814` + + This register contains the current raw level of the zero event trigger. Writes + to this register have no effect. + + .. wavedrom:: + :caption: TIMER0_EV_STATUS + + { + "reg": [ + {"name": "zero", "bits": 1}, + {"bits": 31} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+-----------------------------+ +| Field | Name | Description | ++=======+======+=============================+ +| [0] | ZERO | Level of the ``zero`` event | ++-------+------+-----------------------------+ + +TIMER0_EV_PENDING +^^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x18 = 0xf0007818` + + When a zero event occurs, the corresponding bit will be set in this register. + To clear the Event, set the corresponding bit in this register. + + .. wavedrom:: + :caption: TIMER0_EV_PENDING + + { + "reg": [ + {"name": "zero", "bits": 1}, + {"bits": 31} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+--------------------------------------------------------------------------------+ +| Field | Name | Description | ++=======+======+================================================================================+ +| [0] | ZERO | `1` if a `zero` event occurred. This Event is triggered on a **falling** edge. | ++-------+------+--------------------------------------------------------------------------------+ + +TIMER0_EV_ENABLE +^^^^^^^^^^^^^^^^ + +`Address: 0xf0007800 + 0x1c = 0xf000781c` + + This register enables the corresponding zero events. Write a ``0`` to this + register to disable individual events. + + .. wavedrom:: + :caption: TIMER0_EV_ENABLE + + { + "reg": [ + {"name": "zero", "bits": 1}, + {"bits": 31} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+--------------------------------------------+ +| Field | Name | Description | ++=======+======+============================================+ +| [0] | ZERO | Write a ``1`` to enable the ``zero`` Event | ++-------+------+--------------------------------------------+ + diff --git a/_sources/build/zcu104/documentation/uart.rst.txt b/_sources/build/zcu104/documentation/uart.rst.txt new file mode 100644 index 000000000..2fff7323c --- /dev/null +++ b/_sources/build/zcu104/documentation/uart.rst.txt @@ -0,0 +1,388 @@ +UART +==== + +Register Listing for UART +------------------------- + ++------------------------------------------------------+-------------------------------------------+ +| Register | Address | ++======================================================+===========================================+ +| :ref:`UART_RXTX ` | :ref:`0xf0008000 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_TXFULL ` | :ref:`0xf0008004 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_RXEMPTY ` | :ref:`0xf0008008 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_EV_STATUS ` | :ref:`0xf000800c ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_EV_PENDING ` | :ref:`0xf0008010 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_EV_ENABLE ` | :ref:`0xf0008014 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_TXEMPTY ` | :ref:`0xf0008018 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_RXFULL ` | :ref:`0xf000801c ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_RXTX ` | :ref:`0xf0008020 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_TXFULL ` | :ref:`0xf0008024 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_RXEMPTY ` | :ref:`0xf0008028 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_EV_STATUS ` | :ref:`0xf000802c ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_EV_PENDING ` | :ref:`0xf0008030 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_EV_ENABLE ` | :ref:`0xf0008034 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_TXEMPTY ` | :ref:`0xf0008038 ` | ++------------------------------------------------------+-------------------------------------------+ +| :ref:`UART_XOVER_RXFULL ` | :ref:`0xf000803c ` | ++------------------------------------------------------+-------------------------------------------+ + +UART_RXTX +^^^^^^^^^ + +`Address: 0xf0008000 + 0x0 = 0xf0008000` + + + .. wavedrom:: + :caption: UART_RXTX + + { + "reg": [ + {"name": "rxtx[7:0]", "bits": 8}, + {"bits": 24}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +UART_TXFULL +^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x4 = 0xf0008004` + + TX FIFO Full. + + .. wavedrom:: + :caption: UART_TXFULL + + { + "reg": [ + {"name": "txfull", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_RXEMPTY +^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x8 = 0xf0008008` + + RX FIFO Empty. + + .. wavedrom:: + :caption: UART_RXEMPTY + + { + "reg": [ + {"name": "rxempty", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_EV_STATUS +^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0xc = 0xf000800c` + + This register contains the current raw level of the rx event trigger. Writes to + this register have no effect. + + .. wavedrom:: + :caption: UART_EV_STATUS + + { + "reg": [ + {"name": "tx", "bits": 1}, + {"name": "rx", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+---------------------------+ +| Field | Name | Description | ++=======+======+===========================+ +| [0] | TX | Level of the ``tx`` event | ++-------+------+---------------------------+ +| [1] | RX | Level of the ``rx`` event | ++-------+------+---------------------------+ + +UART_EV_PENDING +^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x10 = 0xf0008010` + + When a rx event occurs, the corresponding bit will be set in this register. To + clear the Event, set the corresponding bit in this register. + + .. wavedrom:: + :caption: UART_EV_PENDING + + { + "reg": [ + {"name": "tx", "bits": 1}, + {"name": "rx", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+------------------------------------------------------------------------------+ +| Field | Name | Description | ++=======+======+==============================================================================+ +| [0] | TX | `1` if a `tx` event occurred. This Event is triggered on a **falling** edge. | ++-------+------+------------------------------------------------------------------------------+ +| [1] | RX | `1` if a `rx` event occurred. This Event is triggered on a **falling** edge. | ++-------+------+------------------------------------------------------------------------------+ + +UART_EV_ENABLE +^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x14 = 0xf0008014` + + This register enables the corresponding rx events. Write a ``0`` to this + register to disable individual events. + + .. wavedrom:: + :caption: UART_EV_ENABLE + + { + "reg": [ + {"name": "tx", "bits": 1}, + {"name": "rx", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+------------------------------------------+ +| Field | Name | Description | ++=======+======+==========================================+ +| [0] | TX | Write a ``1`` to enable the ``tx`` Event | ++-------+------+------------------------------------------+ +| [1] | RX | Write a ``1`` to enable the ``rx`` Event | ++-------+------+------------------------------------------+ + +UART_TXEMPTY +^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x18 = 0xf0008018` + + TX FIFO Empty. + + .. wavedrom:: + :caption: UART_TXEMPTY + + { + "reg": [ + {"name": "txempty", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_RXFULL +^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x1c = 0xf000801c` + + RX FIFO Full. + + .. wavedrom:: + :caption: UART_RXFULL + + { + "reg": [ + {"name": "rxfull", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_XOVER_RXTX +^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x20 = 0xf0008020` + + + .. wavedrom:: + :caption: UART_XOVER_RXTX + + { + "reg": [ + {"name": "xover_rxtx[7:0]", "bits": 8}, + {"bits": 24}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +UART_XOVER_TXFULL +^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x24 = 0xf0008024` + + TX FIFO Full. + + .. wavedrom:: + :caption: UART_XOVER_TXFULL + + { + "reg": [ + {"name": "xover_txfull", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_XOVER_RXEMPTY +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x28 = 0xf0008028` + + RX FIFO Empty. + + .. wavedrom:: + :caption: UART_XOVER_RXEMPTY + + { + "reg": [ + {"name": "xover_rxempty", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_XOVER_EV_STATUS +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x2c = 0xf000802c` + + This register contains the current raw level of the rx event trigger. Writes to + this register have no effect. + + .. wavedrom:: + :caption: UART_XOVER_EV_STATUS + + { + "reg": [ + {"name": "tx", "bits": 1}, + {"name": "rx", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+---------------------------+ +| Field | Name | Description | ++=======+======+===========================+ +| [0] | TX | Level of the ``tx`` event | ++-------+------+---------------------------+ +| [1] | RX | Level of the ``rx`` event | ++-------+------+---------------------------+ + +UART_XOVER_EV_PENDING +^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x30 = 0xf0008030` + + When a rx event occurs, the corresponding bit will be set in this register. To + clear the Event, set the corresponding bit in this register. + + .. wavedrom:: + :caption: UART_XOVER_EV_PENDING + + { + "reg": [ + {"name": "tx", "bits": 1}, + {"name": "rx", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+------------------------------------------------------------------------------+ +| Field | Name | Description | ++=======+======+==============================================================================+ +| [0] | TX | `1` if a `tx` event occurred. This Event is triggered on a **falling** edge. | ++-------+------+------------------------------------------------------------------------------+ +| [1] | RX | `1` if a `rx` event occurred. This Event is triggered on a **falling** edge. | ++-------+------+------------------------------------------------------------------------------+ + +UART_XOVER_EV_ENABLE +^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x34 = 0xf0008034` + + This register enables the corresponding rx events. Write a ``0`` to this + register to disable individual events. + + .. wavedrom:: + :caption: UART_XOVER_EV_ENABLE + + { + "reg": [ + {"name": "tx", "bits": 1}, + {"name": "rx", "bits": 1}, + {"bits": 30} + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + ++-------+------+------------------------------------------+ +| Field | Name | Description | ++=======+======+==========================================+ +| [0] | TX | Write a ``1`` to enable the ``tx`` Event | ++-------+------+------------------------------------------+ +| [1] | RX | Write a ``1`` to enable the ``rx`` Event | ++-------+------+------------------------------------------+ + +UART_XOVER_TXEMPTY +^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x38 = 0xf0008038` + + TX FIFO Empty. + + .. wavedrom:: + :caption: UART_XOVER_TXEMPTY + + { + "reg": [ + {"name": "xover_txempty", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +UART_XOVER_RXFULL +^^^^^^^^^^^^^^^^^ + +`Address: 0xf0008000 + 0x3c = 0xf000803c` + + RX FIFO Full. + + .. wavedrom:: + :caption: UART_XOVER_RXFULL + + { + "reg": [ + {"name": "xover_rxfull", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + diff --git a/_sources/build/zcu104/documentation/writer.rst.txt b/_sources/build/zcu104/documentation/writer.rst.txt new file mode 100644 index 000000000..06244071e --- /dev/null +++ b/_sources/build/zcu104/documentation/writer.rst.txt @@ -0,0 +1,251 @@ +WRITER +====== + + + +DMA DRAM writer. + +Allows to fill DRAM with a predefined pattern using DMA. + +Pattern +------- + + + Provides access to RAM to store access pattern: `mem_addr` and `mem_data`. + The pattern address space can be limited using the `data_mask`. + + For example, having `mem_adr` filled with `[ 0x04, 0x02, 0x03, ... ]` + and `mem_data` filled with `[ 0xff, 0xaa, 0x55, ... ]` and setting + `data_mask = 0b01`, the pattern [(address, data), ...] written will be: + `[(0x04, 0xff), (0x02, 0xaa), (0x04, 0xff), ...]` (wraps due to masking). + + DRAM memory range that is being accessed can be configured using `mem_mask`. + + To use this module, make sure that `ready` is 1, then write the desired + number of transfers to `count`. Writing to the `start` CSR will initialize + the operation. When the operation is ongoing `ready` will be 0. + + + +Register Listing for WRITER +--------------------------- + ++------------------------------------------------------------------------+----------------------------------------------------+ +| Register | Address | ++========================================================================+====================================================+ +| :ref:`WRITER_START ` | :ref:`0xf0002800 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_READY ` | :ref:`0xf0002804 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_MODULO ` | :ref:`0xf0002808 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_COUNT ` | :ref:`0xf000280c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_DONE ` | :ref:`0xf0002810 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_MEM_MASK ` | :ref:`0xf0002814 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_DATA_MASK ` | :ref:`0xf0002818 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_DATA_DIV ` | :ref:`0xf000281c ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_INVERTER_DIVISOR_MASK ` | :ref:`0xf0002820 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_INVERTER_SELECTION_MASK ` | :ref:`0xf0002824 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ +| :ref:`WRITER_LAST_ADDRESS ` | :ref:`0xf0002828 ` | ++------------------------------------------------------------------------+----------------------------------------------------+ + +WRITER_START +^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x0 = 0xf0002800` + + Write to the register starts the transfer (if ready=1) + + .. wavedrom:: + :caption: WRITER_START + + { + "reg": [ + {"name": "start", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +WRITER_READY +^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x4 = 0xf0002804` + + Indicates that the transfer is not ongoing + + .. wavedrom:: + :caption: WRITER_READY + + { + "reg": [ + {"name": "ready", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +WRITER_MODULO +^^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x8 = 0xf0002808` + + When set use modulo to calculate DMA transfers address rather than bit masking + + .. wavedrom:: + :caption: WRITER_MODULO + + { + "reg": [ + {"name": "modulo", "bits": 1}, + {"bits": 31}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +WRITER_COUNT +^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0xc = 0xf000280c` + + Desired number of DMA transfers + + .. wavedrom:: + :caption: WRITER_COUNT + + { + "reg": [ + {"name": "count[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +WRITER_DONE +^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x10 = 0xf0002810` + + Number of completed DMA transfers + + .. wavedrom:: + :caption: WRITER_DONE + + { + "reg": [ + {"name": "done[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +WRITER_MEM_MASK +^^^^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x14 = 0xf0002814` + + DRAM address mask for DMA transfers + + .. wavedrom:: + :caption: WRITER_MEM_MASK + + { + "reg": [ + {"name": "mem_mask[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +WRITER_DATA_MASK +^^^^^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x18 = 0xf0002818` + + Pattern memory address mask + + .. wavedrom:: + :caption: WRITER_DATA_MASK + + { + "reg": [ + {"name": "data_mask[3:0]", "bits": 4}, + {"bits": 28}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +WRITER_DATA_DIV +^^^^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x1c = 0xf000281c` + + Pattern memory address divisior-1 + + .. wavedrom:: + :caption: WRITER_DATA_DIV + + { + "reg": [ + {"name": "data_div[3:0]", "bits": 4}, + {"bits": 28}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +WRITER_INVERTER_DIVISOR_MASK +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x20 = 0xf0002820` + + Divisor mask for selecting rows for which pattern data gets inverted + + .. wavedrom:: + :caption: WRITER_INVERTER_DIVISOR_MASK + + { + "reg": [ + {"name": "inverter_divisor_mask[4:0]", "bits": 5}, + {"bits": 27}, + ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4} + } + + +WRITER_INVERTER_SELECTION_MASK +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x24 = 0xf0002824` + + Selection mask for selecting rows for which pattern data gets inverted + + .. wavedrom:: + :caption: WRITER_INVERTER_SELECTION_MASK + + { + "reg": [ + {"name": "inverter_selection_mask[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + +WRITER_LAST_ADDRESS +^^^^^^^^^^^^^^^^^^^ + +`Address: 0xf0002800 + 0x28 = 0xf0002828` + + Number of completed DMA transfers + + .. wavedrom:: + :caption: WRITER_LAST_ADDRESS + + { + "reg": [ + {"name": "last_address[31:0]", "bits": 32} + ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1} + } + + diff --git a/_sources/building_linux.md.txt b/_sources/building_linux.md.txt new file mode 100644 index 000000000..3f27fdc73 --- /dev/null +++ b/_sources/building_linux.md.txt @@ -0,0 +1,231 @@ +# Building Linux target + +The memory controllers synhesized for Rowhammer testing can be utilized as parts of a regular digital design that is capable of booting an operating system. +In such scenario the memory controller is used by the operating system for interacting with a DRAM memory. +This chapter describes a separate target configuration that has been created in order to synthesize a Linux-capable system that you can run on Antmicro's [RDIMM DDR5 Tester](rdimm_ddr5_tester.md). + +## Base DDR5 Tester Linux Options + +The `ddr5_tester_linux` target is configured via specifying the ``TARGET_ARGS`` variable and requires the following arguments: + +| Option | Documentation | +|:------------------------:|:-------------------------------------------------------------------------------------------------------------------------------:| +| `--build` | When specified will invoke synthesis and hardware analysis tool (Vivado by default).
Will produce programmable bitstream. | +| `--l2-size` | Specifies the L2 cache size. | +| `--iodelay-clk-freq` | IODELAY clock frequency. | +| `--module` | The DDR5 module to be used. | +| `--with-wishbone-memory` | VexRiscV SMP specific option.
Disables native LiteDRAM interface. | +| `--wishbone-force-32b` | VexRiscV SMP specific option.
Forces the wishbone bus to be 32 bits wide. | + +Additionally, you can set up ``EtherBone`` or ``Ethernet`` to communicate with the system as described below. + +### Ethernet Options + +| Option | Documentation | +|:---------------------:|:--------------------------------------------------------------:| +| `--with-ethernet` | Sets up Ethernet for the DDR5 Tester board. | +| `--remote-ip-address` | The IP address of the remote machine connected to DDR5 Tester. | +| `--local-ip-address` | Local (DDR5 Tester's) IP address. | + +### Etherbone Options + +| Option | Documentation | +|:------------------:|:-----------------------------------------:| +| `--with-etherbone` | Sets up Ethernet for DDR5 Tester board. | +| `--ip-address` | IP address to be used for the EtherBone. | +| `--mac-address` | MAC address to be used for the EtherBone. | + +## Building the RDIMM DDR5 Tester Linux Target + +After configuring the RDIMM DDR5 Tester Linux, the target can be build with `make build`. +Below you can see a use example of a DDR5 Tester Linux Target with Ethernet configured: + +```sh +make build TARGET=ddr5_tester_linux TARGET_ARGS="--build --l2-size 256 --iodelay-clk-freq 400e6 --module MTC10F1084S1RC --with-wishbone-memory --wishbone-force-32b --with-ethernet --remote-ip-address 192.168.100.100 --local-ip-address 192.168.100.50" +``` + +## Interacting with RDIMM DDR5 Tester Linux Target + +First, load the bitstream onto the RDIMM DDR5 Tester with the help of `OpenFPGALoader`: + +```bash +openFPGALoader --board antmicro_ddr5_tester build/ddr5_tester_linux/gateware/antmicro_ddr5_tester.bit --freq 3e6 +``` + +In order to connect to the board, assign the `192.168.100.100` IP Address to the Ethernet interface that is plugged to the DDR5 Tester board and set up the device if needed, e.g. by running: + +```sh +ip addr add 192.168.100.100/24 dev $ETH +ip link set dev $ETH up +``` + +Where ``ETH`` is the name of your Ethernet interface. +When the Ethernet interface has been set up correctly, you may access the BIOS console on the DDR5 Tester with: + +```sh +picocom -b 115200 /dev/ttyUSB2 +``` + +## Setting up a TFTP Server + +Several Linux boot methods can be invoked here but booting via Ethernet is recommended. +In order to enable netboot, you need to set up a TFTP server first. + +```{note} +Running a TFTP server varies between distributions in terms of TFTP implementation names and locations of the configuration file. +``` + +As an example, below is a quick guide on how to configure a TFTP server for Arch Linux. +Firstly, if not equipped already, get an implementation of a TFTP server, for example: + +```sh +pacman -S tftp-hpa +``` + +The TFTP server is configured via a `/etc/conf.d/tftpd` file. +Here's a suggested configuration for the DDR5 Tester Linux boot process: + +```sh +TFTP_USERNAME="tftp" +TFTPD_OPTIONS="--secure" +TFTP_DIRECTORY="/srv/tftp" +TFTP_ADDRESS="192.168.100.100:69" +``` + +``TFTP_ADDRESS`` is specified with the ``--remote-ip-address`` option whilst building the target and the port is the default one for the TFTP server. +The ``TFTP_DIRECTORY`` is the TFTP's root directory. + +To start the TFTP service, run: + +```sh +systemctl start tftpd +``` + +To check whether the TFTP sever is set up properly, run: + +```sh +cd /srv/tftp/ && echo "TEST TFTP SERVER" > test + +cd ~/ && tftp 192.168.100.100 -c get test +``` + +The ``test`` file should appear in the home directory with "TEST TFTP SERVER" as its content. + +## Booting Linux on RDIMM DDR5 Tester Linux Target + +You will need the following binaries: + +* Linux kernel Image +* Compiled devicetree +* Opensbi's `fw_jump.bin` +* rootfs.cpio + +All of these can be obtained with the use of provided `firmware/ddr5_tester/buildroot` buildroot external configuration. +To build binaries with buildroot, run: + +```sh +git clone --single-branch -b 2023.05.x https://github.com/buildroot/buildroot.git +pushd buildroot +make BR2_EXTERNAL="$(pwd)/../firmware/ddr5_tester/buildroot" ddr5_vexriscv_defconfig +``` + +Then, transfer the binaries to the TFTP root directory: + +```sh +mv buildroot/output/images/* /srv/tftp/ +mv /srv/tftp/fw_jump.bin /srv/tftp/opensbi.bin +``` + +The address map of the binaries alongside boot arguments can be contained within the `boot.json` file, for example: + +```json +{ + "/srv/tftp/Image": "0x40000000", + "/srv/tftp/rv32.dtb": "0x40ef0000", + "/srv/tftp/rootfs.cpio": "0x42000000", + "/srv/tftp/opensbi.bin": "0x40f00000", + "bootargs": { + "r1": "0x00000000", + "r2": "0x40ef0000", + "r3": "0x00000000", + "addr": "0x40f00000" + } +``` + +With Linux boot binaries in the TFTP's root directory with `boot.json`, netboot can be invoked from the BIOS console with: + +```sh +netboot /srv/tftp/boot.json +``` + +Upon successful execution a similar log will be printed: + +``` +litex> netboot /srv/tftp/boot.json +Booting from network... +Local IP: 192.168.100.50 +Remote IP: 192.168.100.100 +Booting from /srv/tftp/boot.json (JSON)... +Copying /srv/tftp/Image to 0x40000000... (7395804 bytes) +Copying /srv/tftp/rv32.dtb to 0x40ef0000... (2463 bytes) +Copying /srv/tftp/rootfs.cpio to 0x42000000... (22128128 bytes) +Copying /srv/tftp/opensbi.bin to 0x40f00000... (1007056 bytes) +Executing booted program at 0x40f00000 + +--============= Liftoff! ===============-- +``` + +Then, the OpenSBI and Linux boot log should follow: + +``` +OpenSBI v1.3-24-g84c6dc1 + ____ _____ ____ _____ + / __ \ / ____| _ \_ _| + | | | |_ __ ___ _ __ | (___ | |_) || | + | | | | '_ \ / _ \ '_ \ \___ \| _ < | | + | |__| | |_) | __/ | | |____) | |_) || |_ + \____/| .__/ \___|_| |_|_____/|____/_____| + | | + |_| + +Platform Name : LiteX / VexRiscv-SMP +Platform Features : medeleg +Platform HART Count : 8 +Platform IPI Device : aclint-mswi +Platform Timer Device : aclint-mtimer @ 100000000Hz +Platform Console Device : litex_uart +(...) +[ 0.000000] Linux version 5.11.0 (riscv32-buildroot-linux-gnu-gcc.br_real (Buildroot 2023.05.2-154-g787a633711) 11.4.0, GNU ld (GNU Binutils) 2.38) #2 SMP Mon Sep 25 10:52:22 CEST 2023 +[ 0.000000] earlycon: sbi0 at I/O port 0x0 (options '') +[ 0.000000] printk: bootconsole [sbi0] enabled +(...) +``` + +And then: + +``` +Welcome to Buildroot +buildroot login: root + _ _ + | | (_) + | | _ _ __ _ ___ __ + | | | | '_ \| | | \ \/ / + | |___| | | | | |_| |> < + \_____/_|_| |_|\__,_/_/\_\ + _ _ _ + (_) | | | + __ ___| |_| |__ + \ \ /\ / / | __| '_ \ + \ V V /| | |_| | | | + \_/\_/ |_|\__|_| |_| + __________________ _____ + | _ \ _ \ ___ \ ___| + | | | | | | | |_/ /___ \ + | | | | | | | / \ \ + | |/ /| |/ /| |\ \/\__/ / + |___/ |___/ \_| \_\____/ + + 32-bit RISC-V Linux running on DDR5 Tester. + +login[65]: root login on 'console' +``` diff --git a/_sources/building_rowhammer.md.txt b/_sources/building_rowhammer.md.txt new file mode 100644 index 000000000..e0123f9fd --- /dev/null +++ b/_sources/building_rowhammer.md.txt @@ -0,0 +1,271 @@ +# Building Rowhammer designs + +This chapter provides building instructions for synthesizing the digital design for physical DRAM testers and simulation models. + +## Building and uploading the bitstreams + +The bitstream building process is coordinated with a `Makefile` located in the main folder of the Rowhammer Tester repository. +Currently, 6 main targets are provided, each targeting a different DRAM type and memory form factor. +Use the tab view below to select a DRAM memory type of interest. +You will be provided with a name of the built target, building instruction and a link to the relevant hardware platform. + +````{tab} DDR3 (IC) +This is supported by the Digilent [Arty](arty.md) boards. +In this setup the Rowhammer Tester targets a single DDR3 IC installed on board. +For Arty A7-100T with the XC7A100TCSG324-1 FPGA use: + +```sh +export TARGET=arty +make build TARGET_ARGS="--variant a7-100" +``` + +For Arty A7-35T with the XC7A35TICSG324-1L FPGA use: + +```sh +export TARGET=arty +make build +``` + +To upload the bitstream to volatile FPGA configuration RAM use: + +```sh +export TARGET=arty +make upload +``` + +To write the bitstream into non-volatile (Q)SPI Flash memory use: + +```sh +export TARGET=arty +make flash +``` + +```` +````{tab} DDR4 (SO-DIMM) + +This targets an off-the-shelf DDR4 SO-DIMMs installed on AMD-Xilinx [ZCU104](zcu104.md). +You can build the target with: + +```sh +export TARGET=zcu104 +make build +``` + +The generated bitstream file must be named `zcu104.bit` and written to an SD card used for booting the board. +Please refer to the [Loading the bitstream](zcu104.md#loading-the-bitstream) section for more details. + +```` +````{tab} DDR4 (RDIMM) + +This targets an off-the-shelf DDR4 RDIMMs installed on Antmicro [RDIMM DDR4 Tester](rdimm_ddr4_tester.md). +You can build the target with: + +```sh +export TARGET=ddr4_datacenter_test_board +make build +``` + +To upload the bitstream to volatile FPGA configuration RAM use: + +```sh +export TARGET=ddr4_datacenter_test_board +make upload +``` + +To write the bitstream into non-volatile (Q)SPI Flash memory use: + +```sh +export TARGET=ddr4_datacenter_test_board +make flash +``` + +```` +````{tab} LPDDR4 (IC) + +This targets single LPDDR4 ICs soldered to interchangeable testbeds installed on Antmicro [LPDDR4 Test Board](lpddr4_test_board.md). +You can build the target with: + +```sh +export TARGET=lpddr4_test_board +make build +``` + +To upload the bitstream to volatile FPGA configuration RAM use: + +```sh +export TARGET=lpddr4_test_board +make upload +``` + +To write the bitstream into non-volatile (Q)SPI Flash memory use: + +```sh +export TARGET=lpddr4_test_board +make flash +``` + +```` +````{tab} DDR5 (RDIMM) + +This targets an off-the-shelf DDR5 RDIMMs installed on Antmicro [RDIMM DDR5 Tester](rdimm_ddr5_tester.md). +A typical building command is: + +```sh +export TARGET=ddr5_tester +make build TARGET_ARGS="--l2-size 256 --build --iodelay-clk-freq 400e6 --bios-lto --rw-bios --module MTC10F1084S1RC --no-sdram-hw-test" +``` + +The target can be customized with the following build parameters +* ``--l2-size`` sets L2 cache size +* ``--iodelayclk-freq`` specifies IODELAY clock frequency +* ``--module`` specifies RDIMM DDR5 module family +* ``--no-sdram-hw-test`` disables hardware accelerated memory test + +To upload the bitstream to volatile FPGA configuration RAM use: + +```sh +export TARGET=ddr5_tester +make upload +``` + +To write the bitstream into non-volatile (Q)SPI Flash memory use: + +```sh +export TARGET=ddr5_tester +make flash +``` + +```` +````{tab} DDR5 (SO-DIMM) + +This targets an off-the-shelf DDR5 SO-DIMMs installed on Antmicro [SO-DIMM DDR5 Tester](so_dimm_ddr5_tester.md). +A typical building command is: + +```sh +export TARGET=sodimm_ddr5_tester +make build TARGET_ARGS="--l2-size 256 --build --iodelay-clk-freq 400e6 --bios-lto --rw-bios --no-sdram-hw-test" +``` + +The target can be customized with the following build parameters +* ``--l2-size`` sets L2 cache size +* ``--iodelayclk-freq`` specifies IODELAY clock frequency +* ``--no-sdram-hw-test`` disables hardware accelerated memory test + +To upload the bitstream to volatile FPGA configuration RAM use: + +```sh +export TARGET=sodimm_ddr5_tester +make upload +``` + +To write the bitstream into non-volatile (Q)SPI Flash memory use: + +```sh +export TARGET=sodimm_ddr5_tester +make flash +``` + +```` + +```{note} +Running `make` will generate build files without invoking Vivado. +``` + +The generated bitstreams are stored in the `./build//gateware/` folder named after respective target name used for building. + +```{note} +The FPGA configuration RAM is a volatile memory so you would need to write the generated bitstream every time you power-cycle the board or reset the configuration state of the FPGA. +The on-board FPGA will get automatically configured with a bitstream stored in the Flash memory on power-on. +Please refer to the board-specific chapters (provided along with build instructions) for further information on how to connect the board to a host PC and and how to configure it for uploading the bitstream. +``` + +## Ethernet connection + +The hardware platforms flashed with a generated bitstream can be accessed via Ethernet connection. +The board's default IP address is `192.168.100.50` and you need to ensure the board and a host PC are registered within the same subnet (so, for example, you can use `192.168.100.2/24`). + +```{note} +In order to change the default IP address assigned to the board please set the `IP_ADDRESS` environment variable, rebuild the bitstream and re-upload it to the board. +``` + +Boards are controlled the same way for both simulation and hardware runs. +In order to communicate with the board via EtherBone, start `litex_server` with the following command: + +```sh +export IP_ADDRESS=192.168.100.50 # optional, should match the one used during build +make srv +``` + +The build files (CSRs address list) must be up-to-date. +The build files can be re-generated with `make`. + +Then, in another terminal, you can use the Python scripts provided. +*Remember to enter the Python virtual environment before running the scripts!* +Also, the `TARGET` variable should be set to load configuration for the given target. +For example, to use the `leds.py` script, run the following: + +```sh +source ./venv/bin/activate +export TARGET=arty # (or zcu104) required to load target configuration +cd rowhammer_tester/scripts/ +python leds.py # stop with Ctrl-C +``` + +## Packaging the bitstream + +To save the bitstream and use it later or share it, use the `make pack` utility target. +It packs the files necessary to load the bitstream and run rowhammer scripts on it. +These files are: + +* `build/$TARGET/gateware/$TOP.bit` +* `build/$TARGET/csr.csv` +* `build/$TARGET/defs.csv` +* `build/$TARGET/sdram_init.py` +* `build/$TARGET/litedram_settings.json` + +Running `make pack` creates a zip file named, for instance, `$TARGET-$BRANCH-$COMMIT.zip`. + +To use a bitstream packaged this way, run `unzip your-bitstream-file.zip`. + +## Building for simulation + +Select `TARGET`, generate intermediate files & run the simulation: + +```sh +export TARGET=arty +make sim +``` + +This command will generate intermediate files & simulate them with Verilator. +After simulation has finished, a signal dump can be investigated using [gtkwave](http://gtkwave.sourceforge.net/): + +```sh +gtkwave build/$TARGET/gateware/sim.fst +``` + +```{warning} +To run the simulation and the rowhammer scripts on a physical board at the same time, change the ``IP_ADDRESS`` variable, otherwise the simulation can conflict with the communication with your board. +``` + +1. Create the TUN interface: + + ```sh + tunctl -u $USER -t litex-sim + ``` + +1. Configure the IP address of the interface: + + ```sh + ifconfig litex-sim 192.168.100.1/24 up + ``` + +1. Optionally allow network traffic on this interface: + + ```sh + iptables -A INPUT -i litex-sim -j ACCEPT + iptables -A OUTPUT -o litex-sim -j ACCEPT + ``` + +```{note} +Typing `make ARGS="--sim"` will cause LiteX to only generate intermediate files and stop right after. +``` diff --git a/_sources/hammering.md.txt b/_sources/hammering.md.txt new file mode 100644 index 000000000..5387df0db --- /dev/null +++ b/_sources/hammering.md.txt @@ -0,0 +1,556 @@ +# Performing attacks (hammering) + +Rowhammer attacks can be run against a DRAM module. +The results can be then used for measuring cell retention. +For the complete list of script modifiers, see `--help`. + +There are two versions of the rowhammer script: + +* `rowhammer.py` - uses regular memory access via EtherBone to fill/check the memory (slower) +* `hw_rowhammer.py` - BIST blocks will be used to fill/check the memory (much faster, but with some limitations regarding fill pattern) + +BIST blocks are faster and are the intended way of running Rowhammer tester. + +Hammering of a row is done by reading it. +There are two ways to specify a number of reads: + +* `--read_count N` - one pass of `N` reads +* `--read_count_range K M N` - multiple passes of reads, as generated by `range(K, M, N)` + +Regardless of which one is used, the number of reads in one pass is divided equally between the hammered rows. +If a user specifies `--read_count 1000`, then each row will be hammered 500 times. + +By default, hammering is performed via DMA, but there is an alternative way with `--payload-executor` which bypasses the DMA and talks directly with the PHY. +That allows the user to issue specific activation, refresh and precharge commands. + +## Attack modes + +Several attack and row selection modes are available, but only one mode can be specified at a time. + +* `--hammer-only` + + Hammers rows without error checks or reports. + When run with `rowhammer.py`, the attack is limited to one row pair. + `hw_rowhammer.py` can attack up to 32 rows. + With `--payload-executor` enabled, the row limit is dictated by the payload memory size. + + For example, the following command will hammer rows 4 and 6 1000 times total (so 500 times each): + + ```sh + (venv) $ python hw_rowhammer.py --hammer-only 4 6 --read_count 1000 + ``` + +* `--all-rows` + + Row pairs generated from the `range(start-row, nrows - row-pair-distance, row-jump)` expression will be hammered. + + The generated pairs come in the format of `(i, i + row-pair-distance)`. + {numref}`default-all-rows-arguments` shows default values for arguments: + +:::{table} Default values for arguments +:name: default-all-rows-arguments + + | argument | default | + | --------------------- | ------- | + | `--start-row` | 0 | + | `--row-jump` | 1 | + | `--row-pair-distance` | 2 | + +::: + + For instance, to hammer rows `(0, 2), (1, 3), (2, 4)`, run the following command: + + ```sh + (venv) $ python hw_rowhammer.py --all-rows --nrows 5 + ``` + + And to hammer rows `(10, 13), (12, 15)`, run: + + ```sh + (venv) $ python hw_rowhammer.py --all-rows --start-row 10 --nrows 16 --row-jump 2 --row-distance 3 + ``` + + Setting `--row-pair-distance` to 0 lets you check how hammering a single row affects other rows. + Normally, activations and deactivations are achieved with row reads using the DMA, but in this case this is not possible. + Since a single row is being read all the time, no deactivation command would be sent by the DMA. + In this case, the `--payload-executor` argument is required as it bypasses the DMA and sends deactivation commands on its own: + + ```sh + (venv) $ python hw_rowhammer.py --all-rows --nrows 5 --row-pair-distance 0 --payload-executor + ``` + +* `--row-pairs sequential` + + Hammers pairs of `(start-row, start-row + n)`, where `n` is a value from `0` to `nrows`, e.g.: + + ```sh + (venv) $ python hw_rowhammer.py --row-pairs sequential --start-row 4 --nrows 10 + ``` + + The command above will hammer the following set of row pairs: + + ``` + (4, 4 + 0) + (4, 4 + 1) + ... + (4, 4 + 9) + (4, 4 + 10) + ``` + +* `--row-pairs const` + + Two rows specified with the `const-rows-pair` parameter will be hammered: + + ```sh + (venv) $ python hw_rowhammer.py --row-pairs const --const-rows-pair 4 6 + ``` + +* `--row-pairs random` + + `nrows` pairs of random rows will be hammered. Row numbers will be between `start-row` and `start-row + nrows`. + + ```sh + (venv) $ python hw_rowhammer.py --row-pairs random --start-row 4 --nrows 10 + ``` + +* `--no-attack-time