From 5d8206079eacc2f91bb364d66f98c0331077ae0d Mon Sep 17 00:00:00 2001 From: Wojciech Juszczak Date: Fri, 22 Mar 2024 10:12:36 +0100 Subject: [PATCH] [#56898] Descibre SO-DIMM DDR5 Tester target configuration --- docs/source/sodimm_ddr5_tester.md | 39 ++++++++++++++++++++++++++++--- 1 file changed, 36 insertions(+), 3 deletions(-) diff --git a/docs/source/sodimm_ddr5_tester.md b/docs/source/sodimm_ddr5_tester.md index 370b3e667..41101d732 100644 --- a/docs/source/sodimm_ddr5_tester.md +++ b/docs/source/sodimm_ddr5_tester.md @@ -8,11 +8,45 @@ The SO-DIMM DDR5 tester is an open source hardware test platform that enables te The hardware is open and can be found on GitHub: +## Rowhammer Tester Target Configuration + The following instructions explain how to set up the board. +Connect the board USB-C `J3` and Ethernet `J6` via cable to your computer, plug the board into the power socket `J7` and turn it on using power switch `SW5`. Then configure the network. The board's IP address will be `192.168.100.50` (so you could e.g. use `192.168.100.2/24`). The `IP_ADDRESS` environment variable can be used to modify the board's address. +Next, generate the FPGA bitstream: + +```sh +export TARGET=sodimm_ddr5_tester +make build TARGET_ARGS="--l2-size 256 --build --iodelay-clk-freq 400e6 --bios-lto --rw-bios --no-sdram-hw-test" +``` + +```{note} +--l2-size 256 sets L2 cache size to 256 bytes + +--no-sdram-hw-test disables hw accelerated memory test +``` + +```{note} +By typing `make` (without `build`) LiteX will generate build files without invoking Vivado. +``` + +The results will be located in: `build/sodimm_ddr5_tester/gateware/antmicro_sodimm_ddr5_tester.bit`. To upload it, use: + +```sh +export TARGET=sodimm_ddr5_tester +make upload +``` + +To save bitstream in flash memory, use: + +```sh +export TARGET=sodimm_ddr5_tester +make flash +``` + ```{warning} -There is a `SW1` `MODE` selector on the right close to FPGA. -The default configuration mode is set to ```JTAG```. If the bitstream needs to be loaded from the Flash memory, select ```Master SPI``` mode. +There is a `SW1` `MODE` selector to the right of the FPGA. +If the bitstream needs to be loaded from the Flash memory, select ```Master SPI``` mode. This configuration is set by default | Configuration mode | MODE[2] | MODE[1] | MODE[0] | |--------------------|---------|---------|---------| @@ -28,4 +62,3 @@ Bitstream will be loaded from flash memory upon device power-on or after a PROG ``` -