From 6efd2221acb4fa77758864babffbb1642960f4a6 Mon Sep 17 00:00:00 2001 From: Wiktoria Kuna Date: Thu, 7 Nov 2024 15:27:06 +0100 Subject: [PATCH] targets/common.py: Do not place a false path between eth_tx and eth_rx clock Internal-tag: [#67942] Signed-off-by: Wiktoria Kuna --- rowhammer_tester/targets/common.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/rowhammer_tester/targets/common.py b/rowhammer_tester/targets/common.py index 31167881..3d583aab 100644 --- a/rowhammer_tester/targets/common.py +++ b/rowhammer_tester/targets/common.py @@ -125,7 +125,8 @@ def add_host_bridge(self): eth_tx_clk.attr.add("keep") # Period constraint is specified in ns self.platform.add_period_constraint(clock_pads.rx, 1e9/phy.rx_clk_freq) - self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk) + self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk) + self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_tx_clk) # Common SoC configuration ---------------------------------------------------------------------