The RefreshCounter in Payload executor is 32-bits

[sqazi]

Hi,

Longer running tests using the at_refresh feature can get discrepancies in their behavior when the counter overflows. This takes about 4 hours. Would it be possible to expand this to 64 bits to avoid this situation?

[pjattke]

A question related to this: if we disable the memory controller-issued REFs right before the memory training, we still always observe around 3.5M REFs after the FPGA booted up. Do we correctly assume that this means the FPGA starts sendings REFs to the DRAM device immediately after booting up (already before the memory training started)?

[mtdudek]

@sqazi We've checked the code behind the at_refresh feature. It seems to be possible to change it from 32 bit to 64 bit counters w/o serious code refactor.
We'll update RTL and Python code to use 64 bits and check this.

@pjattke As for REF count after training. REF counting is done by observing the DFI interface that enters PHY.
Our system has 2 DFI switches:

• first one selects between MC and payload executor
• second one selects between output from first switch and training command injector.

Once the system reset is complete the Memory Controller (MC) starts refresh timer and sends the REF commands accordingly. Both mux are set to pass DFI traffic from MC to PHY, so before system enters training, MC will send some number of refreshes. After selecting signal delays, training code runs 2 MiB memory test, during which MC is connected back to the PHY, so more REF commands will be sent.

[mtdudek]

@sqazi @pjattke We just pushed 64-bit refresh counter changes to the main branch.