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bigger payload size will allocate more blockrams for storing the program. This will need more logic to handle this and makes it harder for the tools to route. If you have timing violations the system may simply not work correctly in the end. This can result in failed training.
Can you share the exact command you used for running the build?
Also - new HW revision should make it easier to have more memory in the system. US+ FPGAs have more memory resources.
Memory training failed very quickly. I also noticed that the build showed a red error message showing that timing constraints were not met.
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