diff --git a/fpga_topwrap/elaboratable_wrapper.py b/fpga_topwrap/elaboratable_wrapper.py
index 8c49aa0e..fa43be02 100644
--- a/fpga_topwrap/elaboratable_wrapper.py
+++ b/fpga_topwrap/elaboratable_wrapper.py
@@ -43,10 +43,14 @@ def get_ports_hier(self) -> SignalMapping:
         """Maps elaboratable's Signature to a nested dictionary of WrapperPorts.
         See _gather_signature_ports for more details.
         """
-        return self._gather_signature_ports(self.elaboratable.signature) | {
-            "clk": self.clk,
-            "rst": self.rst,
-        }
+        ports = self._gather_signature_ports(self.elaboratable.signature)
+        ports.update(
+            {
+                "clk": self.clk,
+                "rst": self.rst,
+            }
+        )
+        return ports
 
     @lru_cache(maxsize=None)
     def _cached_wrapper(