Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Thin margin in blocks of circuit plots #19

Open
mofeing opened this issue Dec 27, 2022 · 2 comments
Open

Thin margin in blocks of circuit plots #19

mofeing opened this issue Dec 27, 2022 · 2 comments
Labels
bug Something isn't working help wanted Extra attention is needed

Comments

@mofeing
Copy link
Member

mofeing commented Dec 27, 2022

Current plotting mechanism consists in drawing small blocks (1 block ⁄ qubit ⨉ moment) and then joining them together.

It seems like circuit plots drawn by joining blocks have a visual artifact: a small margin around the blocks. For example, check the image in #18.

209679389-ae8b015e-93c1-4350-afb8-de93baa0e07c

It is unknown if this is an artifact of our code or a bug in Luxor.jl

@mofeing mofeing added bug Something isn't working help wanted Extra attention is needed labels Dec 27, 2022
@mofeing mofeing changed the title Remove thin margin in blocks of circuit plots Thin margin in blocks of circuit plots Dec 28, 2022
@jofrevalles
Copy link
Member

I think this is the intended behavior of svg images. Since we draw each of these cells one by one, the visualization of svg images in VSCode shows a small separation, but if we download the file and we open it with a program that supports vectorized images (e.g. Inkscape) we can clearly see that this separation does not exist:
image

Furthermore, if we take this same image in VSCode and we zoom in, we can also see how the separation vanishes:
image

To conclude, I would say that the drawing is fine and this is an artifact of the visualization in VSCode. However, if we wanted to fix this problem we would have to first draw the background of the whole canvas, and then draw the circuit elements on top of that, I could try to do this.

@mofeing
Copy link
Member Author

mofeing commented Jan 3, 2023

To conclude, I would say that the drawing is fine and this is an artifact of the visualization in VSCode. However, if we wanted to fix this problem we would have to first draw the background of the whole canvas, and then draw the circuit elements on top of that, I could try to do this.

It make sense that the artifact is the fault of the VSCode renderer but I don't completely agree with the solution because the separation margin appears also between wires.

The solution would be to draw the full lines instead of drawing the cells and joining. This also would make the rendering somewhat less complex as it would involve less SVG elements. However, the code would need to be a lil more complex.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
bug Something isn't working help wanted Extra attention is needed
Projects
None yet
Development

No branches or pull requests

2 participants