From 33631edd60efa3eecb06479d4d62b5873e8f0ee1 Mon Sep 17 00:00:00 2001 From: bugobliterator Date: Wed, 17 Jul 2024 14:19:12 +1000 Subject: [PATCH] AP_HAL_ChibiOS: CubeRedPrimary: setup to use double data rate on QSPI --- .../hwdef/CubeRedPrimary/hwdef-bl.dat | 17 ++++++++++------- .../hwdef/CubeRedPrimary/hwdef.dat | 14 ++++++++------ 2 files changed, 18 insertions(+), 13 deletions(-) diff --git a/libraries/AP_HAL_ChibiOS/hwdef/CubeRedPrimary/hwdef-bl.dat b/libraries/AP_HAL_ChibiOS/hwdef/CubeRedPrimary/hwdef-bl.dat index bb4cfa826fdf4f..cd4a45bcc83883 100644 --- a/libraries/AP_HAL_ChibiOS/hwdef/CubeRedPrimary/hwdef-bl.dat +++ b/libraries/AP_HAL_ChibiOS/hwdef/CubeRedPrimary/hwdef-bl.dat @@ -63,19 +63,22 @@ define HAL_HAVE_DUAL_USB_CDC 1 RAM_RESERVE_START 256 # QSPI Flash -PD11 QUADSPI_BK1_IO0 QUADSPI1 -PD12 QUADSPI_BK1_IO1 QUADSPI1 -PE2 QUADSPI_BK1_IO2 QUADSPI1 -PD13 QUADSPI_BK1_IO3 QUADSPI1 -PB10 QUADSPI_BK1_NCS QUADSPI1 -PB2 QUADSPI_CLK QUADSPI1 +PD11 QUADSPI_BK1_IO0 QUADSPI1 SPEED_HIGH +PD12 QUADSPI_BK1_IO1 QUADSPI1 SPEED_HIGH +PE2 QUADSPI_BK1_IO2 QUADSPI1 SPEED_HIGH +PD13 QUADSPI_BK1_IO3 QUADSPI1 SPEED_HIGH +PB10 QUADSPI_BK1_NCS QUADSPI1 SPEED_HIGH +PB2 QUADSPI_CLK QUADSPI1 SPEED_HIGH EXT_FLASH_SIZE_MB 32 INT_FLASH_PRIMARY 1 # IFace Device Name Bus QSPI Mode Clk Freq Size (Pow2) NCS Delay -QSPIDEV w25q-dtr QUADSPI1 MODE1 100*MHZ 31 1 +QSPIDEV w25q-dtr QUADSPI1 MODE1 80*MHZ 31 1 # disable peripheral and sensor power in the bootloader PG0 VDD_3V3_SENSORS_EN OUTPUT LOW PF2 nVDD_5V_PERIPH_EN OUTPUT LOW + +define STM32_WSPI_SET_CR_SSHIFT FALSE +define STM32_QSPISEL STM32_QSPISEL_PLL1_Q_CK \ No newline at end of file diff --git a/libraries/AP_HAL_ChibiOS/hwdef/CubeRedPrimary/hwdef.dat b/libraries/AP_HAL_ChibiOS/hwdef/CubeRedPrimary/hwdef.dat index d6e7dfa8e38aad..052f3bb4d59fed 100644 --- a/libraries/AP_HAL_ChibiOS/hwdef/CubeRedPrimary/hwdef.dat +++ b/libraries/AP_HAL_ChibiOS/hwdef/CubeRedPrimary/hwdef.dat @@ -183,12 +183,14 @@ define AP_NETWORKING_DEFAULT_MAC_ADDR "A8:B0:28:00:00:00" PB7 TIM4_CH2 TIM4 RCININT PULLDOWN # QUADSPI -PD11 QUADSPI_BK1_IO0 QUADSPI1 -PD12 QUADSPI_BK1_IO1 QUADSPI1 -PE2 QUADSPI_BK1_IO2 QUADSPI1 -PD13 QUADSPI_BK1_IO3 QUADSPI1 -PB10 QUADSPI_BK1_NCS QUADSPI1 -PB2 QUADSPI_CLK QUADSPI1 +PD11 QUADSPI_BK1_IO0 QUADSPI1 SPEED_HIGH +PD12 QUADSPI_BK1_IO1 QUADSPI1 SPEED_HIGH +PE2 QUADSPI_BK1_IO2 QUADSPI1 SPEED_HIGH +PD13 QUADSPI_BK1_IO3 QUADSPI1 SPEED_HIGH +PB10 QUADSPI_BK1_NCS QUADSPI1 SPEED_HIGH +PB2 QUADSPI_CLK QUADSPI1 SPEED_HIGH +define STM32_WSPI_SET_CR_SSHIFT FALSE +define STM32_QSPISEL STM32_QSPISEL_PLL1_Q_CK # SDMMC PC10 SDMMC1_D2 SDMMC1