.gitmodules

[submodule "deps/migen"]
	path = deps/migen
	url = https://github.com/m-labs/migen.git
[submodule "deps/litex"]
	path = deps/litex
	url = https://github.com/buncram/litex.git
[submodule "deps/litescope"]
	path = deps/litescope
	url = https://github.com/enjoy-digital/litescope
[submodule "deps/pyserial"]
	path = deps/pyserial
	url = https://github.com/pyserial/pyserial.git
[submodule "deps/litedram"]
	path = deps/litedram
	url = https://github.com/enjoy-digital/litedram.git
[submodule "deps/gateware"]
	path = deps/gateware
	url = https://github.com/betrusted-io/gateware.git
	branch = main
[submodule "deps/valentyusb"]
	path = deps/valentyusb
	url = https://github.com/betrusted-io/valentyusb.git
	branch = burst-support
[submodule "deps/compiler_rt"]
	path = deps/compiler_rt
	url = https://github.com/litex-hub/pythondata-software-compiler_rt.git
[submodule "deps/pythondata-software-picolibc"]
	path = deps/pythondata-software-picolibc
	url = https://github.com/litex-hub/pythondata-software-picolibc
[submodule "deps/verilog-axi"]
	path = deps/verilog-axi
	url = https://github.com/buncram/verilog-axi.git
[submodule "deps/SpinalHDL"]
	path = deps/SpinalHDL
	url = https://github.com/SpinalHDL/SpinalHDL
[submodule "deps/VexRiscv"]
	path = deps/VexRiscv
	url = https://github.com/SpinalHDL/VexRiscv
[submodule "deps/pio/upstream"]
	path = deps/pio/upstream
	url = git@github.com:lawrie/fpga_pio.git