dut.py

#!/usr/bin/env python3

import sys
import os
import argparse

# universally required
from migen import *
import litex.soc.doc as lxsocdoc
from litex.build.generic_platform import *
from litex.soc.integration.builder import *

# pull in the common objects from sim_bench
from sim_support.sim_bench import Sim, Platform, SimRunner, BiosHelper, CheckSim, Preamble

# handy to keep around in case a DUT framework needs it
from litex.soc.integration.soc_core import *
from litex.soc.integration.soc import SoCRegion
from litex.soc.cores.clock import *
from litex.soc.integration.doc import AutoDoc, ModuleDoc
from litex.soc.interconnect.csr import *

# specific to a given DUT
from gateware import memlcd
from gateware import sram_32

## todo: make automated waveform writing for ci mode

# top-level IOs specific to the DUT
dutio = [
    # LCD interface
    ("lcd", 0,
     Subsignal("sclk", Pins("A17"), IOStandard("LVCMOS33")),
     Subsignal("scs", Pins("C18"), IOStandard("LVCMOS33")),
     Subsignal("si", Pins("D17"), IOStandard("LVCMOS33")),
     ),

    # SRAM
    ("sram", 0,
     Subsignal("adr", Pins(
         "V12 M5 P5 N4  V14 M3 R17 U15",
         "M4  L6 K3 R18 U16 K1 R5  T2",
         "U1  N1 L5 K2  M18 T6"),
               IOStandard("LVCMOS18")),
     Subsignal("ce_n", Pins("V5"), IOStandard("LVCMOS18")),
     Subsignal("oe_n", Pins("U12"), IOStandard("LVCMOS18")),
     Subsignal("we_n", Pins("K4"), IOStandard("LVCMOS18")),
     Subsignal("zz_n", Pins("V17"), IOStandard("LVCMOS18")),
     Subsignal("d", Pins(
         "M2  R4  P2  L4  L1  M1  R1  P1 "
         "U3  V2  V4  U2  N2  T1  K6  J6 "
         "V16 V15 U17 U18 P17 T18 P18 M17 "
         "N3  T4  V13 P15 T14 R15 T3  R7 "), IOStandard("LVCMOS18")),
     Subsignal("dm_n", Pins("V3 R2 T5 T13"), IOStandard("LVCMOS18")),
     ),
]

local_clocks = {
    "clk12": [12e6, 0],
    # add more clocks here, formatted as {"name" : [freq, phase]}
}

boot_from_spi=False

# add the submodules we're testing to the SoC, which is encapsulated in the Sim class
class Dut(Sim):
    def __init__(self, platform, spiboot=False, **kwargs):
        Sim.__init__(self, platform, custom_clocks=local_clocks, spiboot=spiboot, **kwargs) # SoC magic is in here

        # LCD interface
        self.submodules.memlcd = memlcd.MemLCD(platform.request("lcd"))
        self.add_csr("memlcd")
        self.bus.add_slave("memlcd", self.memlcd.bus, SoCRegion(origin=self.mem_map["memlcd"], size=self.memlcd.fb_depth*4, mode="rw", cached=False))
        # self.register_mem("memlcd", self.mem_map["memlcd"], self.memlcd.bus, size=self.memlcd.fb_depth*4)

        # external SRAM for testing the build system
        self.submodules.sram_ext = sram_32.SRAM32(platform.request("sram"), rd_timing=7, wr_timing=6, page_rd_timing=2)
        self.add_csr("sram_ext")
        self.register_mem("sram_ext", self.mem_map["sram_ext"],
                  self.sram_ext.bus, size=0x1000000)


# generate all the files necessary to run xsim
def generate_top():
    global dutio
    global boot_from_spi

    # we have to do two passes: once to make the SVD, without compiling the BIOS
    # second, to compile the BIOS, which is then built into the gateware.
    Preamble()

    # pass #1 -- make the SVD
    platform = Platform(dutio)
    soc = Dut(platform, spiboot=boot_from_spi)

    builder = Builder(soc, output_dir="./run", csr_svd="build/software/soc.svd", compile_gateware=False, compile_software=False)
    builder.software_packages = []
    vns = builder.build(run=False)
    soc.do_exit(vns)

    BiosHelper(soc, boot_from_spi)

    # pass #2 -- generate the SoC, incorporating the now-built BIOS
    platform = Platform(dutio)
    soc = Dut(platform)

    builder = Builder(soc, output_dir="./run", compile_software=False)
    builder.software_packages = []
    os.environ["DUTNAME"] = 'memlcd'
    vns = builder.build(run=False)
    soc.do_exit(vns)


# script to drive xsim
def run_sim(ci=False):
    SimRunner(ci, [])



def main():
    from datetime import datetime

    parser = argparse.ArgumentParser(description="Gateware simulation framework")
    parser.add_argument(
        "-c", "--ci", default=False, action="store_true", help="Run with settings for automated CI"
    )

    args = parser.parse_args()

    start = datetime.now()
    generate_top()
    run_sim(ci=args.ci)
    print("Run completed in {}".format(datetime.now()-start))
    if args.ci:
        if CheckSim() != 0:
            sys.exit(1)

    sys.exit(0)


if __name__ == "__main__":
    main()