From d57c67c4f5dafe1cf75492cfa3c903465d65fbff Mon Sep 17 00:00:00 2001 From: Mark Pizzolato Date: Fri, 19 May 2023 17:14:58 -1000 Subject: [PATCH] PDP11: Change Interrupt names from RP, TU and RS to RHA, RHB and RHC Interrupts come through the respective Massbus adapters. This is consistent with the interrupt naming in the VAX Massbus adapters. --- PDP11/pdp11_defs.h | 18 ++++---- PDP11/pdp11_rh.c | 105 ++++++++++++++++++++++++++++++++++----------- 2 files changed, 90 insertions(+), 33 deletions(-) diff --git a/PDP11/pdp11_defs.h b/PDP11/pdp11_defs.h index 7c9e1fc12..a158488fb 100644 --- a/PDP11/pdp11_defs.h +++ b/PDP11/pdp11_defs.h @@ -617,7 +617,7 @@ typedef struct pdp_dib DIB; #define INT_V_RL 2 #define INT_V_RX 3 #define INT_V_TM 4 -#define INT_V_RP 5 +#define INT_V_RHA 5 #define INT_V_TS 6 #define INT_V_HK 7 #define INT_V_RQ 8 @@ -627,10 +627,10 @@ typedef struct pdp_dib DIB; #define INT_V_RY 12 #define INT_V_XQ 13 #define INT_V_XU 14 -#define INT_V_TU 15 +#define INT_V_RHB 15 #define INT_V_RF 16 #define INT_V_RC 17 -#define INT_V_RS 18 +#define INT_V_RHC 18 #define INT_V_DMCRX 19 #define INT_V_DMCTX 20 #define INT_V_DUPRX 21 @@ -685,7 +685,7 @@ typedef struct pdp_dib DIB; #define INT_RL (1u << INT_V_RL) #define INT_RX (1u << INT_V_RX) #define INT_TM (1u << INT_V_TM) -#define INT_RP (1u << INT_V_RP) +#define INT_RHA (1u << INT_V_RHA) #define INT_TS (1u << INT_V_TS) #define INT_HK (1u << INT_V_HK) #define INT_RQ (1u << INT_V_RQ) @@ -695,10 +695,10 @@ typedef struct pdp_dib DIB; #define INT_RY (1u << INT_V_RY) #define INT_XQ (1u << INT_V_XQ) #define INT_XU (1u << INT_V_XU) -#define INT_TU (1u << INT_V_TU) +#define INT_RHB (1u << INT_V_RHB) #define INT_RF (1u << INT_V_RF) #define INT_RC (1u << INT_V_RC) -#define INT_RS (1u << INT_V_RS) +#define INT_RHC (1u << INT_V_RHC) #define INT_DMCRX (1u << INT_V_DMCRX) #define INT_DMCTX (1u << INT_V_DMCTX) #define INT_KMCA (1u << INT_V_KMCA) @@ -755,7 +755,7 @@ typedef struct pdp_dib DIB; #define IPL_RL 5 #define IPL_RX 5 #define IPL_TM 5 -#define IPL_RP 5 +#define IPL_RHA 5 #define IPL_TS 5 #define IPL_HK 5 #define IPL_RQ 5 @@ -766,10 +766,10 @@ typedef struct pdp_dib DIB; #define IPL_XQ 5 #define IPL_XU 5 #define IPL_CH 5 -#define IPL_TU 5 +#define IPL_RHB 5 #define IPL_RF 5 #define IPL_RC 5 -#define IPL_RS 5 +#define IPL_RHC 5 #define IPL_DMCRX 5 #define IPL_DMCTX 5 #define IPL_KMCA 5 diff --git a/PDP11/pdp11_rh.c b/PDP11/pdp11_rh.c index 7877d4342..eb7369a65 100644 --- a/PDP11/pdp11_rh.c +++ b/PDP11/pdp11_rh.c @@ -202,7 +202,7 @@ static int32 mba_mapofs[(MBA_OFSMASK + 1) >> 1] = { DIB mba0_dib = { IOBA_AUTO, 0, &mba_rd, &mba_wr, - 1, IVCL (RP), VEC_AUTO, { &mba0_inta } + 1, IVCL (RHA), VEC_AUTO, { &mba0_inta } }; UNIT mba0_unit = { UDATA (NULL, 0, 0) }; @@ -216,7 +216,7 @@ REG mba0_reg[] = { { ORDATAD (BAE, massbus[0].bae, 6, "bus address extension") }, { ORDATAD (CS3, massbus[0].cs3, 16, "control/status register 3") }, { FLDATAD (IFF, massbus[0].iff, 0, "transfer complete interrupt request flag") }, - { FLDATAD (INT, IREQ (RP), INT_V_RP, "interrupt pending flag (RP)") }, + { FLDATAD (INT, IREQ (RHA), INT_V_RHA, "interrupt pending flag (RP)") }, { FLDATAD (SC, massbus[0].cs1, CSR_V_ERR, "special condition (CSR1<15>)") }, { FLDATAD (DONE, massbus[0].cs1, CSR_V_DONE, "device done flag (CSR1<7>)") }, { FLDATAD (IE, massbus[0].cs1, CSR_V_IE, "interrupt enable flag (CSR1<6>)") }, @@ -237,7 +237,7 @@ MTAB mba0_mod[] = { DIB mba1_dib = { IOBA_AUTO, 0, &mba_rd, &mba_wr, - 1, IVCL (TU), VEC_AUTO, { &mba1_inta } + 1, IVCL (RHB), VEC_AUTO, { &mba1_inta } }; UNIT mba1_unit = { UDATA (NULL, 0, 0) }; @@ -251,7 +251,7 @@ REG mba1_reg[] = { { ORDATAD (BAE, massbus[1].bae, 6, "bus address extension") }, { ORDATAD (CS3, massbus[1].cs3, 16, "control/status register 3") }, { FLDATAD (IFF, massbus[1].iff, 0, "transfer complete interrupt request flag") }, - { FLDATAD (INT, IREQ (TU), INT_V_TU, "interrupt pending flag (TU)") }, + { FLDATAD (INT, IREQ (RHB), INT_V_RHB, "interrupt pending flag (TU)") }, { FLDATAD (SC, massbus[1].cs1, CSR_V_ERR, "special condition (CSR1<15>)") }, { FLDATAD (DONE, massbus[1].cs1, CSR_V_DONE, "device done flag (CSR1<7>)") }, { FLDATAD (IE, massbus[1].cs1, CSR_V_IE, "interrupt enable flag (CSR1<6>)") }, @@ -272,7 +272,7 @@ MTAB mba1_mod[] = { DIB mba2_dib = { IOBA_AUTO, 0, &mba_rd, &mba_wr, - 1, IVCL (RS), VEC_AUTO, { &mba2_inta } + 1, IVCL (RHC), VEC_AUTO, { &mba2_inta } }; UNIT mba2_unit = { UDATA (NULL, 0, 0) }; @@ -286,7 +286,7 @@ REG mba2_reg[] = { { ORDATAD (BAE, massbus[2].bae, 6, "bus address extension") }, { ORDATAD (CS3, massbus[2].cs3, 16, "control/status register 3") }, { FLDATAD (IFF, massbus[2].iff, 0, "transfer complete interrupt request flag") }, - { FLDATAD (INT, IREQ (RS), INT_V_RS, "interrupt pending flag (RS)") }, + { FLDATAD (INT, IREQ (RHC), INT_V_RHC, "interrupt pending flag (RS)") }, { FLDATAD (SC, massbus[2].cs1, CSR_V_ERR, "special condition (CSR1<15>)") }, { FLDATAD (DONE, massbus[2].cs1, CSR_V_DONE, "device done flag (CSR1<7>)") }, { FLDATAD (IE, massbus[2].cs1, CSR_V_IE, "interrupt enable flag (CSR1<6>)") }, @@ -305,6 +305,43 @@ MTAB mba2_mod[] = { { 0 } }; +#if MBA_NUM != 3 +DIB mba3_dib = { + IOBA_AUTO, 0, &mba_rd, &mba_wr, + 1, IVCL (RHD), VEC_AUTO, { &mba3_inta } + }; + +UNIT mba3_unit = { UDATA (NULL, 0, 0) }; + +REG mba3_reg[] = { + { ORDATAD (CS1, massbus[3].cs1, 16, "control/status register 1") }, + { ORDATAD (WC, massbus[3].wc, 16, "word count") }, + { ORDATAD (BA, massbus[3].ba, 16, "bus address") }, + { ORDATAD (CS2, massbus[3].cs2, 16, "control/status register 2") }, + { ORDATAD (DB, massbus[3].db, 16, "data buffer") }, + { ORDATAD (BAE, massbus[3].bae, 6, "bus address extension") }, + { ORDATAD (CS3, massbus[3].cs3, 16, "control/status register 3") }, + { FLDATAD (IFF, massbus[3].iff, 0, "transfer complete interrupt request flag") }, + { FLDATAD (INT, IREQ (RHD), INT_V_RHC, "interrupt pending flag (RS)") }, + { FLDATAD (SC, massbus[3].cs1, CSR_V_ERR, "special condition (CSR1<15>)") }, + { FLDATAD (DONE, massbus[3].cs1, CSR_V_DONE, "device done flag (CSR1<7>)") }, + { FLDATAD (IE, massbus[3].cs1, CSR_V_IE, "interrupt enable flag (CSR1<6>)") }, + { ORDATA (DEVADDR, mba3_dib.ba, 32), REG_HRO }, + { ORDATA (DEVVEC, mba3_dib.vec, 16), REG_HRO }, + { NULL } + }; + +MTAB mba3_mod[] = { + { MTAB_XTD|MTAB_VDV|MTAB_VALR, 0040, "ADDRESS", "ADDRESS", + &set_addr, &show_addr, NULL, "Bus address" }, + { MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, "VECTOR", "VECTOR", + &set_vec, &show_vec, NULL, "Interrupt vector" }, + { MTAB_XTD|MTAB_VDV, 0, "TYPE", NULL, + NULL, &mba_show_type, NULL, "Massbus Adapter Type" }, + { 0 } + }; +#endif + DEVICE mba_dev[] = { { "RHA", &mba0_unit, mba0_reg, mba0_mod, @@ -332,6 +369,17 @@ DEVICE mba_dev[] = { &mba2_dib, DEV_DEBUG | DEV_UBUS | DEV_QBUS, 0, NULL, NULL, NULL, &rh_help, NULL, NULL, &rh_description +#if MBA_NUM != 3 + }, + { + "RHD", &mba3_unit, mba3_reg, mba2_mod, + 1, 0, 0, 0, 0, 0, + NULL, NULL, &mba_reset, + NULL, NULL, NULL, + &mba3_dib, DEV_DEBUG | DEV_UBUS | DEV_QBUS, 0, + NULL, NULL, NULL, &rh_help, NULL, NULL, + &rh_description +#endif } }; @@ -915,7 +963,7 @@ for (i = mba_devs = 0; sim_devices[i] != NULL; i++) { t_stat build_mbus_tab (DEVICE *dptr, DIB *dibp) { uint32 idx; -static const char *mbus_devs[MBA_NUM+1] = {"RP", "TU", "RS", NULL}; +static const char *mbus_devs[] = {"RP", "TU", "RS", NULL}; if ((dptr == NULL) || (dibp == NULL)) /* validate args */ return SCPE_IERR; @@ -923,18 +971,16 @@ for (idx = 0; mbus_devs[idx]; idx++) if (!strcmp (dptr->name, mbus_devs[idx])) break; if ((!mbus_devs[idx]) || (idx >= MBA_NUM)) - return SCPE_IERR; + return sim_messagef (SCPE_IERR, "More Massbus devices than Massbuses, can't support %s\n", dptr->name); dibp->ba = idx; /* Mbus # */ if ((mbregR[idx] && dibp->rd && /* conflict? */ (mbregR[idx] != dibp->rd)) || (mbregW[idx] && dibp->wr && (mbregW[idx] != dibp->wr)) || (mbabort[idx] && dibp->ack[0] && - (mbabort[idx] != dibp->ack[0]))) { - sim_printf ("Massbus %s assignment conflict at %d\n", - sim_dname (dptr), dibp->ba); - return SCPE_STOP; - } + (mbabort[idx] != dibp->ack[0]))) + return sim_messagef (SCPE_STOP, "Massbus %s assignment conflict at %d\n", + sim_dname (dptr), dibp->ba); mbregR[idx] = dibp->rd; /* set rd dispatch */ mbregW[idx] = dibp->wr; /* set wr dispatch */ mbabort[idx] = dibp->ack[0]; /* set abort dispatch */ @@ -948,26 +994,37 @@ t_stat rh_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr { const char *const text = /*567901234567890123456789012345678901234567890123456789012345678901234567890*/ +#if MBA_NUM == 3 " RH11/RH70/RH70-emulating Massbus adapters (RHA, RHB, RHC)\n" +#else +"1RH11/RH70/RH70-emulating Massbus adapters (RHA, RHB, RHC, RHD)\n" +#endif "\n" " The RH70/RH11/RH70-emulating Massbus adapters interface Massbus\n" " peripherals to the memory bus or Unibus of the CPU. The simulator\n" +#if MBA_NUM == 3 " provides three Massbus adapters. These adapters (RHA, RHB, and RHC)\n" -" are used by (in order):\n" -" 1) the RP family of disk drives.\n" -" 2) the TU family of tape controllers.\n" -" 3) the RS family of fixed head disks.\n" -" Depending on which of the RP, TU, and RS devices are enabled, will\n" -" determine which adapter is assigned to which device.\n" +" are used by (in order):\n\n" +#else +" provides four Massbus adapters. These adapters (RHA, RHB, RHC and\n" +" RHD) are used by (in order):\n\n" +#endif +"++1) the RP family of disk drives.\n" +"++2) the TU family of tape controllers.\n" +"++3) the RS family of fixed head disks.\n" +#if MBA_NUM != 3 +"++4) the RPB additional RP family fixed head disks.\n" +#endif +"\n" " In a Unibus system, the RH adapters implement 22b addressing for the\n" " 11/70 and 18b addressing for all other models. In a Qbus system, the\n" " RH adapters always implement 22b addressing.\n" /*567901234567890123456789012345678901234567890123456789012345678901234567890*/ -"\n"; -fprintf (st, "%s", text); -fprint_show_help (st, dptr); -fprint_reg_help (st, dptr); -return SCPE_OK; +"\n" +"1$Set commands\n" +"1$Show commands\n" +"1$Registers\n"; +return scp_help (st, dptr, uptr, flag, text, ""); } const char *rh_description (DEVICE *dptr)