Glitches are a common problem in digital design. They are caused by the propagation delay of signals through combinational logic. In this lecture, we will discuss how glitches can occur in finite state machines (FSMs) and how to avoid them.
- Chapter 10 sections 6-8 from RTL Hardware Design Using VHDL book (ignore the VHDL code examples for now). Download the pdf from this textbook as you will use it later in the semester.
- 10.6: State assignment. This should be review.
- 10.7: Moore output buffering. This is a new topic. Make sure you read and understand this carefully including the "Look ahead" circuit.
- 10.8: These are FSM examples you can browse through. Don't worry about the VHDL but review the state machine and its purpose
- Source of output glitches in FSMs (transitioning between states and OFL logic glitches)
- FSM Encoding approaches
- Moore output buffering and inability to implement Mealy output buffering
- FSM Output glitches