In this lecture we will review the key syntax and semantics of SystemVerilog that you learned in ECEN 220/ECEN 323 (we will not cover any new material that you have not had in a previous class). We will focus primarily on syntax for structural design in SystemVerilog and combinational logic design using dataflow statements.
- Review chapters 8, 11, and 14 Dr. Nelson's ECEN 220 textbook
- Purpose of SystemVerilog and how it differs from other programming languages
- Module definition (ports, module naming) (chapter 8)
- Parameterization (chapter ?)
- Defining wires/logic (chapter 11)
- Module instantiation/parameterization (chapter 11)
- SystemVerilog constants (chapter 11)
- Multi-bit wire accessing (chapter 11)
- Dataflow statements and operators (chapter 14)