We will have a guest lecturer who will discuss UVM and how it is used in industry.
Download the following two documents from IEEE (uyou will need an IEEE account to download these documents). Students can get a IEEE login for free.
- IEEE Standard for SystemVerilog— Unified Hardware Design, Specification, and Verification Language (IEEE Std 1800-2023)
- Read Sections 1.1, 1.2, and 1.3
- IEEE Standard for Universal Verification Methodology Language Reference Manual (IEEE Std 1800.2-2020)
- Read Sections 1.1 and 1.2 (only a paragraph each)
- Read these blog entries:
- Accellera Guide, Chapter 1
Reading