diff --git a/README.md b/README.md
index 57084041c..7070e2e35 100644
--- a/README.md
+++ b/README.md
@@ -14,7 +14,7 @@ See the License for the specific language governing permissions and
limitations under the License.*_
# **Caliptra Hands-On Guide** #
-_*Last Update: 2023/08/24*_
+_*Last Update: 2023/09/06*_
## **Tools Used** ##
@@ -44,9 +44,10 @@ Synthesis:
GCC:
- RISCV Toolchain for generating memory initialization files
- - `riscv64-unknown-elf-gcc-8.2.0-2019.02.0-x86_64-linux-centos6`
- - G++ Used to compile Verilator objects
- - `g++ (GCC) 8.2.0`
+ - `Version 2023.04.29`
+ - `riscv64-unknown-elf-gcc (g) 12.2.0`
+ - G++ Used to compile Verilator objects and test firmware
+ - `g++ (GCC) 11.2.0`
Other:
- Playbook (Microsoft Internal workflow management tool)
@@ -78,11 +79,11 @@ Required for Firmware (i.e. Test suites) makefile:
Caliptra
|-- LICENSE
|-- README.md
-|-- Release_notes.txt
+|-- Release_Notes.md
|-- docs
| |-- Caliptra_Integration_Specification.pdf
-| |-- Caliptra_Hardware_Spec.pdf
-| |-- Caliptra_TestPlan_L1.pdf
+| |-- Caliptra_Hardware_Specification.pdf
+| `-- Caliptra_TestPlan.xlsx
|-- src
| |-- aes
| |-- ahb_lite_bus
@@ -108,11 +109,11 @@ Caliptra
| |-- sha512_masked
| |-- soc_ifc
| |-- spi_host
-| |-- uart
+| `-- uart
`-- tools
- |-- config
|-- README
- `-- scripts
+ |-- scripts
+ `-- templates
```
The root of the repository is structured as shown above, to a depth of 2 layers.
Each sub-component is accompanied by a file list summary (located in src//config/.vf) that comprises all the filenames required to compile the component, and an optional testbench filelist for unit-level simulation.
@@ -133,6 +134,7 @@ The "Integration" sub-component contains the top-level fileset for Caliptra. `sr
`run_verilator_l0_regression.py`: Wrapper to run the L0 smoke test regression suite using the Makefile flow in Verilator
`integration_vector_gen.py`: Generates test vectors for crypto core tests
`veer_build_command.sh`: Shell script used to generate the VeeR-EL2 repository present in `src/riscv_core/veer_el2`
+`openocd`: Open-Source FW debug utility used for JTAG testing in automated workflows
## **Simulation Flow** ##
diff --git a/Release_Notes.md b/Release_Notes.md
index 5a7af9ed0..3dc7c388d 100644
--- a/Release_Notes.md
+++ b/Release_Notes.md
@@ -14,13 +14,113 @@ See the License for the specific language governing permissions and
limitations under the License.*_
# **Release Notes** #
-_*Last Update: 2023/08/24*_
+_*Last Update: 2023/09/13*_
-## Rev 0p8 ##
+## Rev 1p0 ##
-### DISCALIMER: This is NOT A BUG-FREE MODEL YET. This is a 0p8 release model. Please see testplan document in docs folder to know the status of validation. ###
-#### This model is released mainly for interface, floorplan planning purposes for consumers. ####
-#### Rev 0p8 release date: 03-31-2023 ####
+### Rev 1p0 release date: (pending ROM release for official declaration) ###
+- Caliptra IP Specification: see docs/ folder
+- Caliptra Integration Specification: see docs/ folder
+- Caliptra testplan: see docs/ folder
+- Data Vault
+- RISC-V Timers
+ - mtime + mtimecmp implementation
+ - Watchdog timer configuration by SOC; escalate interrupts to error
+- Reliability, Availability, Serviceability Features
+ - Connectivity for cptra_error_fatal/cptra_error_non_fatal interrupts
+ - Mailbox protocol violation detection and Error state
+ - SRAM ECC error detection and reporting for ICCM, DCCM, Mailbox
+ - Key clearing and system reset on fatal errors
+- SOC Interface
+ - QSPI inout changed to input+output+enable
+ - FUSE PAUSER config registers and enforcement
+- Reset Domain Crossing (RDC) fixes
+ - Reset-triggered clock gating on cross-domain registers
+ - Reset timing changes for noncore reset assertion
+ - Migrate most internal logic to the noncore reset domain
+ - Migrate APB interface to noncore reset domain
+- FIPS compliance updates
+ - SHA Accelerator LOCK default to Caliptra-owned
+ - LMS Fuse
+ - SOC Stepping ID field in HW Revision
+ - Extended pcr_nonce from 32-bit to 256-bit
+ - TRNG Data Clear
+- RISC-V Core
+ - Increase ROM size to 48KiB
+ - Added 2:1 AHB lite mux on LSU and SB buses to allow debug access to
+ peripherals
+- Timing Optimizations
+ - Remove PSEL loopback path in APB slave
+ - Remove unnecessary Mailbox SRAM ECC writeback path
+- Validation enhancements
+ - SOC_IFC/Mailbox randomized regressions via UVM testbench
+ - SOC Interface Register validation via directed + random tests
+ - Coverage reporting and analysis for all interfaces, registers, FSM
+ - Automated GitHub action using OpenOCD for interactive JTAG debugging
+ - SHA Formal Verification
+
+### Bug Fixes ###
+[CLK GATING] Fatal error should wake up clks
+[CLK GATING] JTAG accesses need to wake up clocks
+[DOE] add zeroize to clear all internal regs
+[DOE] DOE IV reg needs hwclr input
+[DOE] doe_fsm incr_dest_sel logic can be removed since FE now only takes up 12 dwords
+[DOE] doe_fsm write_offset increments to 0xC
+[DOE] Simplify kv_write dest_valid hardcoded value in doe_fsm
+[ECC] ECC input register bound check
+[ECC] ECC output register bound check
+[ECC] ECC Public key validation check
+[ECC] mismatch of final reduction in Mont. mult in the case of prime<= p_internal
+[ECC] mismatch of modular addition result in the case of p<= a+b < 2^384
+[ECC] remove FW read access to kv/privkey reg
+[ECC} error trigger when pcr_sign ctrl input is set in keygen/verifying mode
+[KV] Debug Mode and Scan Mode switch doesn't flush locked registers
+[KV] Debug mode should flush KV even if core is asleep
+[KV] Dest_valid and last_dword should check lock_use to clear along with lock_wr
+[KV] KV may still contain secrets during scan mode
+[KV] kv_reg.rdl still has 6 bits for dest_valid while we have 5 valid clients
+[KV] KV->SHA ->FW read path and KV->HMAC->FW read path should NOT exist in the design
+[KV] last dword of secret values stays in KV/crypto interface
+[KV] Suppress writes to an entry altogether when it's being cleared
+[MBOX] ECC error decode may detect error on mbox_sram when a write is in progress
+[MBOX] First resp read data is zero after handling a command with DLEN > MBOX SIZE
+[MBOX] HWCLR triggered by force-unlock has lower precedence than SW writes
+[MBOX] Mailbox data length limiting reads is calculated incorrectly
+[MBOX] Mailbox does not flag protocol error for attempted writes to DLEN
+[MBOX] mailbox returns non-zero data in an overread case
+[MBOX] New RAS feature to detect protocol violation incorrectly decodes certain reg accesses as errors
+[MBOX] SOC can read mbox_dataout with stale data
+[MBOX] Writes beyond the mailbox size overwrite the last data dword in mailbox memory
+[MBOX] Writes to (a) unaligned addresses (b) size < AHB_DATA_WIDTH may corrupt memory
+[MBOX] error_cmd_fail_sts.hwset is continuously set when mailbox protocol error occurs
+[PCR] Extend PCR Nonce from 32-bit to 256-bit to protect replay attack
+[PCR] PCR dword mismatch
+[PCR] Update the reset of the 'lock' PCR control to the core reset domain (so that a FW update reset or warm reset can also unlock the PCR)
+[PCR] zeroize doesn't take effect if is set with pcr at the same cycle
+[SHA ACCEL] SoC requester can use mailbox mode
+[SOC_IFC] Arbiter lets direct request dv through at the same time as soc ifc mailbox request causing deadlock
+[SOC_IFC] Breakpoint is unreachable
+[SOC_IFC] Fuse Registers can never be written using non-default values programmed in FUSE_VALID_PAUSER
+[SOC_IFC] Generic Input Wires toggle (any bit) should trigger notification interrupt to uC
+[SOC_IFC] INTERNAL_HW_ERROR_FATAL_MASK and INTERNAL_HW_ERROR_NON_FATAL_MASK allow writes to (and non-zero reads from) reserved fields.
+[SOC_IFC] Mailbox ECC errors detected during SHA Accel direct accesses are not detected/corrected
+[SOC_IFC] mbox_execute can be cleared by SOC at any point after acquiring lock
+[SOC_IFC] uC can't write to CPTRA_FW_ERROR regs (Github issue #64)
+[SOC_IFC] WDT may not correctly detect when uC services the timer expiration interrupt
+[WDT] CPTRA_WDT_STATUS reg should be FW writeable so it can clear the flags
+[WDT] First stage interrupt output should be "error_intr" instead of "notif_intr"
+[WDT] WDT registers need to be on ungated clk
+[AHB] AHB 2:1 Mux hangs with back to back transactions after a stall
+[RST] scan_mode should not corrupt resets
+[TOP] EL2 Mem interface is not instantiated with a modport at all levels
+
+## Previous Releases ##
+
+### Rev 0p8 ###
+
+#### DISCALIMER: This is NOT A BUG-FREE MODEL YET. This is a 0p8 release model. Please see testplan document in docs folder to know the status of validation. ####
+##### This model is released mainly for interface, floorplan planning purposes for consumers. #####
+##### Rev 0p8 release date: 03-31-2023 #####
- Caliptra IP Specification: see docs/ folder
- Caliptra Integration Specification: see docs/ folder
@@ -59,13 +159,6 @@ _*Last Update: 2023/08/24*_
- UVMF for multiple DUT blocks and SOC interface
- DV complete for first cut of the boot & reset flows, Fuses, SOC registers, Crypto blocks, Key vault, PCR Vault, PCR extend, PCR signing, Mailbox
-## Pending for RTL 1p0: ##
-- Timers, integrated-TRNG integration w/ Caliptra, Error domain logic
-- Lots of bug fixes :-)
-- Data Vault, TRNG REQ protocol, SHA384 acceleration, More mailbox val, PCR val, cross product flows
-
-## Previous Releases ##
-
### Rev Pre0p8: ###
#### DISCLAIMER: This is NOT A BUG-FREE MODEL. This is a pre-0p8 development model that will be sync’d every week. ####
#### This model is released mainly for interface, floorplan planning purposes for consumers. ####
diff --git a/coverage/config/aes_caliptra_tb.yml b/coverage/config/aes_caliptra_tb.yml
deleted file mode 100644
index 99567571a..000000000
--- a/coverage/config/aes_caliptra_tb.yml
+++ /dev/null
@@ -1,13 +0,0 @@
-# Copyright (C) Microsoft Corporation. All rights reserved.
-
-# Repo/Bench config specific settings
-# For repo-specific file, common settings like retention policy, additional merge options etc can be specified
-
-#
-# https://dev.azure.com/ms-tsd/Base_Verification/_wiki/wikis/Base_Verification.wiki/34333/Coverage-merge-YAML
-#
-
-variables:
- BENCH_CONFIG: aes_caliptra_tb
-
-template: caliptra_cov_cfg.yml
diff --git a/coverage/config/caliptra_cov_cfg.yml b/coverage/config/caliptra_cov_cfg.yml
deleted file mode 100644
index 3266626ee..000000000
--- a/coverage/config/caliptra_cov_cfg.yml
+++ /dev/null
@@ -1,48 +0,0 @@
-# Copyright (C) Microsoft Corporation. All rights reserved.
-
-# Repo/Bench config specific settings
-# For repo-specific file, common settings like retention policy, additional merge options etc can be specified
-#
-# https://dev.azure.com/ms-tsd/Base_Verification/_wiki/wikis/Base_Verification.wiki/34333/Coverage-merge-YAML
-#
-
-variables:
- COV_DISK: ${PRJ_COV_DISK}/integration_lib
- NIGHTLY_SAMPLE_CNT: 14
- #24x7_SAMPLE_CNT: 14
- NIGHTLY_SAMPLE_RETAIN_CNT: 30
- #24x7_SAMPLE_RETAIN_CNT: 30
- NIGHTLY_DIRECTED_PIPELINE_ID: 3194 #nightly directed regression
- NIGHTLY_RANDOM_PIPELINE_ID: 3195 #nightly random regression
-
- #24x7_PIPELINE_ID: 2772 #FIXME
-
-project: AHA_POC
-
-merge:
-
- merge_opts: -flex_merge reference -flex_merge tgl
-
- search_dir:
- #${COV_DISK}/${NIGHTLY_DIRECTED_PIPELINE_ID}/${BENCH_CONFIG}: ${NIGHTLY_SAMPLE_CNT}
- ${COV_DISK}/${NIGHTLY_RANDOM_PIPELINE_ID}/${BENCH_CONFIG}: ${NIGHTLY_SAMPLE_CNT}
- #${COV_DISK}/${24x7_PIPELINE_ID}/${BENCH_CONFIG}: ${24x7_SAMPLE_CNT}
-
- target_dir: ${COV_DISK}/${SYSTEM_DEFINITIONID}/${BENCH_CONFIG}/nightly_merge_${BUILD_BUILDID}_${PIPELINE_START_TIME}
-
-publish:
- name_scope:
- - ${BENCH_CONFIG}
- - caliptra_top
-
-report:
- #ellist:
- #- ${CALIPTRA_ROOT}/coverage/exclusions/caliptra_top.ellist
- #- ${CALIPTRA_ROOT}/coverage/exclusions/code/${BENCH_CONFIG}_stub.el
-
- hvp: ${CALIPTRA_ROOT}/src/integration/testplan/caliptra_top.hvp
-
-retention:
- #${COV_DISK}/${NIGHTLY_DIRECTED_PIPELINE_ID}/${BENCH_CONFIG}: ${NIGHTLY_SAMPLE_RETAIN_CNT}
- ${COV_DISK}/${NIGHTLY_RANDOM_PIPELINE_ID}/${BENCH_CONFIG}: ${NIGHTLY_SAMPLE_RETAIN_CNT}
- #${COV_DISK}/${24x7_PIPELINE_ID}/${BENCH_CONFIG}: ${24x7_SAMPLE_CNT}
\ No newline at end of file
diff --git a/coverage/config/caliptra_merge_bench_cov_cfg.yml b/coverage/config/caliptra_merge_bench_cov_cfg.yml
deleted file mode 100644
index 919b0d1ed..000000000
--- a/coverage/config/caliptra_merge_bench_cov_cfg.yml
+++ /dev/null
@@ -1,48 +0,0 @@
-# Copyright (C) Microsoft Corporation. All rights reserved.
-
-# Repo/Bench config specific settings
-# For repo-specific file, common settings like retention policy, additional merge options etc can be specified
-#
-# https://dev.azure.com/ms-tsd/Base_Verification/_wiki/wikis/Base_Verification.wiki/34333/Coverage-merge-YAML
-#
-
-variables:
- COV_DISK: ${PRJ_COV_DISK}/integration_lib
- MERGE_DIR_NAME: caliptra_merge_bench_cov_cfg
- MERGE_SAMPLE_CNT: 1
- MERGE_SAMPLE_RETAIN_CNT: 30
- MERGE_PIPELINE_ID: ${SYSTEM_DEFINITIONID}
-
-project: AHA_POC
-
-merge:
-
- merge_opts: -flex_merge reference -flex_merge tgl -merge_across_libs
-
- search_dir:
- ${COV_DISK}/${SYSTEM_DEFINITIONID}/caliptra_top_tb: ${MERGE_SAMPLE_CNT}
- ${COV_DISK}/${SYSTEM_DEFINITIONID}/sha512_caliptra_tb: ${MERGE_SAMPLE_CNT}
- ${COV_DISK}/${SYSTEM_DEFINITIONID}/soc_ifc_caliptra_tb: ${MERGE_SAMPLE_CNT}
- ${COV_DISK}/${SYSTEM_DEFINITIONID}/uvmf_2022: ${MERGE_SAMPLE_CNT}
- ${COV_DISK}/${SYSTEM_DEFINITIONID}/uvmf_caliptra_top: ${MERGE_SAMPLE_CNT}
- ${COV_DISK}/${SYSTEM_DEFINITIONID}/uvmf_ecc: ${MERGE_SAMPLE_CNT}
- ${COV_DISK}/${SYSTEM_DEFINITIONID}/uvmf_hmac: ${MERGE_SAMPLE_CNT}
- ${COV_DISK}/${SYSTEM_DEFINITIONID}/uvmf_kv: ${MERGE_SAMPLE_CNT}
- ${COV_DISK}/${SYSTEM_DEFINITIONID}/uvmf_pv: ${MERGE_SAMPLE_CNT}
- ${COV_DISK}/${SYSTEM_DEFINITIONID}/uvmf_sha512: ${MERGE_SAMPLE_CNT}
- ${COV_DISK}/${SYSTEM_DEFINITIONID}/uvmf_soc_ifc: ${MERGE_SAMPLE_CNT}
-
- target_dir: ${COV_DISK}/${SYSTEM_DEFINITIONID}/${MERGE_DIR_NAME}/nightly_merge_${BUILD_BUILDID}_${PIPELINE_START_TIME}
-
-publish:
- name_scope:
- - caliptra_top
-
-report:
- ellist:
- - ${CALIPTRA_ROOT}/coverage/exclusions/caliptra_top.ellist
-
- hvp: ${CALIPTRA_ROOT}/src/integration/testplan/caliptra_top.hvp
-
-retention:
- ${COV_DISK}/${MERGE_PIPELINE_ID}/${MERGE_DIR_NAME}: ${MERGE_SAMPLE_RETAIN_CNT}
\ No newline at end of file
diff --git a/coverage/config/caliptra_top_tb.yml b/coverage/config/caliptra_top_tb.yml
deleted file mode 100644
index cecb0a9da..000000000
--- a/coverage/config/caliptra_top_tb.yml
+++ /dev/null
@@ -1,13 +0,0 @@
-# Copyright (C) Microsoft Corporation. All rights reserved.
-
-# Repo/Bench config specific settings
-# For repo-specific file, common settings like retention policy, additional merge options etc can be specified
-
-#
-# https://dev.azure.com/ms-tsd/Base_Verification/_wiki/wikis/Base_Verification.wiki/34333/Coverage-merge-YAML
-#
-
-variables:
- BENCH_CONFIG: caliptra_top_tb
-
-template: caliptra_cov_cfg.yml
diff --git a/coverage/config/csrng_caliptra_tb.yml b/coverage/config/csrng_caliptra_tb.yml
deleted file mode 100644
index 77a16d5a9..000000000
--- a/coverage/config/csrng_caliptra_tb.yml
+++ /dev/null
@@ -1,13 +0,0 @@
-# Copyright (C) Microsoft Corporation. All rights reserved.
-
-# Repo/Bench config specific settings
-# For repo-specific file, common settings like retention policy, additional merge options etc can be specified
-
-#
-# https://dev.azure.com/ms-tsd/Base_Verification/_wiki/wikis/Base_Verification.wiki/34333/Coverage-merge-YAML
-#
-
-variables:
- BENCH_CONFIG: csrng_caliptra_tb
-
-template: caliptra_cov_cfg.yml
diff --git a/coverage/config/datavault_caliptra_tb.yml b/coverage/config/datavault_caliptra_tb.yml
deleted file mode 100644
index b934ba2a6..000000000
--- a/coverage/config/datavault_caliptra_tb.yml
+++ /dev/null
@@ -1,13 +0,0 @@
-# Copyright (C) Microsoft Corporation. All rights reserved.
-
-# Repo/Bench config specific settings
-# For repo-specific file, common settings like retention policy, additional merge options etc can be specified
-
-#
-# https://dev.azure.com/ms-tsd/Base_Verification/_wiki/wikis/Base_Verification.wiki/34333/Coverage-merge-YAML
-#
-
-variables:
- BENCH_CONFIG: datavault_caliptra_tb
-
-template: caliptra_cov_cfg.yml
diff --git a/coverage/config/doe_caliptra_tb.yml b/coverage/config/doe_caliptra_tb.yml
deleted file mode 100644
index 77aa2a1a3..000000000
--- a/coverage/config/doe_caliptra_tb.yml
+++ /dev/null
@@ -1,13 +0,0 @@
-# Copyright (C) Microsoft Corporation. All rights reserved.
-
-# Repo/Bench config specific settings
-# For repo-specific file, common settings like retention policy, additional merge options etc can be specified
-
-#
-# https://dev.azure.com/ms-tsd/Base_Verification/_wiki/wikis/Base_Verification.wiki/34333/Coverage-merge-YAML
-#
-
-variables:
- BENCH_CONFIG: doe_caliptra_tb
-
-template: caliptra_cov_cfg.yml
diff --git a/coverage/config/ecc_caliptra_tb.yml b/coverage/config/ecc_caliptra_tb.yml
deleted file mode 100644
index fc726b607..000000000
--- a/coverage/config/ecc_caliptra_tb.yml
+++ /dev/null
@@ -1,13 +0,0 @@
-# Copyright (C) Microsoft Corporation. All rights reserved.
-
-# Repo/Bench config specific settings
-# For repo-specific file, common settings like retention policy, additional merge options etc can be specified
-
-#
-# https://dev.azure.com/ms-tsd/Base_Verification/_wiki/wikis/Base_Verification.wiki/34333/Coverage-merge-YAML
-#
-
-variables:
- BENCH_CONFIG: uvmf_ecc
-
-template: caliptra_cov_cfg.yml
diff --git a/coverage/config/edn_caliptra_tb.yml b/coverage/config/edn_caliptra_tb.yml
deleted file mode 100644
index 6f069ae50..000000000
--- a/coverage/config/edn_caliptra_tb.yml
+++ /dev/null
@@ -1,13 +0,0 @@
-# Copyright (C) Microsoft Corporation. All rights reserved.
-
-# Repo/Bench config specific settings
-# For repo-specific file, common settings like retention policy, additional merge options etc can be specified
-
-#
-# https://dev.azure.com/ms-tsd/Base_Verification/_wiki/wikis/Base_Verification.wiki/34333/Coverage-merge-YAML
-#
-
-variables:
- BENCH_CONFIG: edn_caliptra_tb
-
-template: caliptra_cov_cfg.yml
diff --git a/coverage/config/entropy_src_caliptra_tb.yml b/coverage/config/entropy_src_caliptra_tb.yml
deleted file mode 100644
index 3bf952068..000000000
--- a/coverage/config/entropy_src_caliptra_tb.yml
+++ /dev/null
@@ -1,13 +0,0 @@
-# Copyright (C) Microsoft Corporation. All rights reserved.
-
-# Repo/Bench config specific settings
-# For repo-specific file, common settings like retention policy, additional merge options etc can be specified
-
-#
-# https://dev.azure.com/ms-tsd/Base_Verification/_wiki/wikis/Base_Verification.wiki/34333/Coverage-merge-YAML
-#
-
-variables:
- BENCH_CONFIG: entropy_src_caliptra_tb
-
-template: caliptra_cov_cfg.yml
diff --git a/coverage/config/hmac_caliptra_tb.yml b/coverage/config/hmac_caliptra_tb.yml
deleted file mode 100644
index dd92d607c..000000000
--- a/coverage/config/hmac_caliptra_tb.yml
+++ /dev/null
@@ -1,13 +0,0 @@
-# Copyright (C) Microsoft Corporation. All rights reserved.
-
-# Repo/Bench config specific settings
-# For repo-specific file, common settings like retention policy, additional merge options etc can be specified
-
-#
-# https://dev.azure.com/ms-tsd/Base_Verification/_wiki/wikis/Base_Verification.wiki/34333/Coverage-merge-YAML
-#
-
-variables:
- BENCH_CONFIG: uvmf_hmac
-
-template: caliptra_cov_cfg.yml
diff --git a/coverage/config/hmac_drbg_caliptra_tb.yml b/coverage/config/hmac_drbg_caliptra_tb.yml
deleted file mode 100644
index 15870bdb7..000000000
--- a/coverage/config/hmac_drbg_caliptra_tb.yml
+++ /dev/null
@@ -1,13 +0,0 @@
-# Copyright (C) Microsoft Corporation. All rights reserved.
-
-# Repo/Bench config specific settings
-# For repo-specific file, common settings like retention policy, additional merge options etc can be specified
-
-#
-# https://dev.azure.com/ms-tsd/Base_Verification/_wiki/wikis/Base_Verification.wiki/34333/Coverage-merge-YAML
-#
-
-variables:
- BENCH_CONFIG: hmac_drbg_caliptra_tb
-
-template: caliptra_cov_cfg.yml
diff --git a/coverage/config/keyvault_caliptra_tb.yml b/coverage/config/keyvault_caliptra_tb.yml
deleted file mode 100644
index cedf96b79..000000000
--- a/coverage/config/keyvault_caliptra_tb.yml
+++ /dev/null
@@ -1,13 +0,0 @@
-# Copyright (C) Microsoft Corporation. All rights reserved.
-
-# Repo/Bench config specific settings
-# For repo-specific file, common settings like retention policy, additional merge options etc can be specified
-
-#
-# https://dev.azure.com/ms-tsd/Base_Verification/_wiki/wikis/Base_Verification.wiki/34333/Coverage-merge-YAML
-#
-
-variables:
- BENCH_CONFIG: uvmf_kv
-
-template: caliptra_cov_cfg.yml
diff --git a/coverage/config/kmac_caliptra_tb.yml b/coverage/config/kmac_caliptra_tb.yml
deleted file mode 100644
index 034fe215f..000000000
--- a/coverage/config/kmac_caliptra_tb.yml
+++ /dev/null
@@ -1,13 +0,0 @@
-# Copyright (C) Microsoft Corporation. All rights reserved.
-
-# Repo/Bench config specific settings
-# For repo-specific file, common settings like retention policy, additional merge options etc can be specified
-
-#
-# https://dev.azure.com/ms-tsd/Base_Verification/_wiki/wikis/Base_Verification.wiki/34333/Coverage-merge-YAML
-#
-
-variables:
- BENCH_CONFIG: kmac_caliptra_tb
-
-template: caliptra_cov_cfg.yml
diff --git a/coverage/config/lc_ctrl_caliptra_tb.yml b/coverage/config/lc_ctrl_caliptra_tb.yml
deleted file mode 100644
index d5aff89f0..000000000
--- a/coverage/config/lc_ctrl_caliptra_tb.yml
+++ /dev/null
@@ -1,13 +0,0 @@
-# Copyright (C) Microsoft Corporation. All rights reserved.
-
-# Repo/Bench config specific settings
-# For repo-specific file, common settings like retention policy, additional merge options etc can be specified
-
-#
-# https://dev.azure.com/ms-tsd/Base_Verification/_wiki/wikis/Base_Verification.wiki/34333/Coverage-merge-YAML
-#
-
-variables:
- BENCH_CONFIG: lc_ctrl_caliptra_tb
-
-template: caliptra_cov_cfg.yml
diff --git a/coverage/config/pcrvault_caliptra_tb.yml b/coverage/config/pcrvault_caliptra_tb.yml
deleted file mode 100644
index c8430f915..000000000
--- a/coverage/config/pcrvault_caliptra_tb.yml
+++ /dev/null
@@ -1,13 +0,0 @@
-# Copyright (C) Microsoft Corporation. All rights reserved.
-
-# Repo/Bench config specific settings
-# For repo-specific file, common settings like retention policy, additional merge options etc can be specified
-
-#
-# https://dev.azure.com/ms-tsd/Base_Verification/_wiki/wikis/Base_Verification.wiki/34333/Coverage-merge-YAML
-#
-
-variables:
- BENCH_CONFIG: uvmf_pv
-
-template: caliptra_cov_cfg.yml
diff --git a/coverage/config/prim_caliptra_tb.yml b/coverage/config/prim_caliptra_tb.yml
deleted file mode 100644
index b88b0119f..000000000
--- a/coverage/config/prim_caliptra_tb.yml
+++ /dev/null
@@ -1,13 +0,0 @@
-# Copyright (C) Microsoft Corporation. All rights reserved.
-
-# Repo/Bench config specific settings
-# For repo-specific file, common settings like retention policy, additional merge options etc can be specified
-
-#
-# https://dev.azure.com/ms-tsd/Base_Verification/_wiki/wikis/Base_Verification.wiki/34333/Coverage-merge-YAML
-#
-
-variables:
- BENCH_CONFIG: prim_caliptra_tb
-
-template: caliptra_cov_cfg.yml
diff --git a/coverage/config/prim_generic_caliptra_tb.yml b/coverage/config/prim_generic_caliptra_tb.yml
deleted file mode 100644
index 2fcb3746d..000000000
--- a/coverage/config/prim_generic_caliptra_tb.yml
+++ /dev/null
@@ -1,13 +0,0 @@
-# Copyright (C) Microsoft Corporation. All rights reserved.
-
-# Repo/Bench config specific settings
-# For repo-specific file, common settings like retention policy, additional merge options etc can be specified
-
-#
-# https://dev.azure.com/ms-tsd/Base_Verification/_wiki/wikis/Base_Verification.wiki/34333/Coverage-merge-YAML
-#
-
-variables:
- BENCH_CONFIG: prim_generic_caliptra_tb
-
-template: caliptra_cov_cfg.yml
diff --git a/coverage/config/sha256_caliptra_tb.yml b/coverage/config/sha256_caliptra_tb.yml
deleted file mode 100644
index 6b02df493..000000000
--- a/coverage/config/sha256_caliptra_tb.yml
+++ /dev/null
@@ -1,13 +0,0 @@
-# Copyright (C) Microsoft Corporation. All rights reserved.
-
-# Repo/Bench config specific settings
-# For repo-specific file, common settings like retention policy, additional merge options etc can be specified
-
-#
-# https://dev.azure.com/ms-tsd/Base_Verification/_wiki/wikis/Base_Verification.wiki/34333/Coverage-merge-YAML
-#
-
-variables:
- BENCH_CONFIG: sha256_caliptra_tb
-
-template: caliptra_cov_cfg.yml
diff --git a/coverage/config/sha512_caliptra_tb.yml b/coverage/config/sha512_caliptra_tb.yml
deleted file mode 100644
index 050ab2d07..000000000
--- a/coverage/config/sha512_caliptra_tb.yml
+++ /dev/null
@@ -1,13 +0,0 @@
-# Copyright (C) Microsoft Corporation. All rights reserved.
-
-# Repo/Bench config specific settings
-# For repo-specific file, common settings like retention policy, additional merge options etc can be specified
-
-#
-# https://dev.azure.com/ms-tsd/Base_Verification/_wiki/wikis/Base_Verification.wiki/34333/Coverage-merge-YAML
-#
-
-variables:
- BENCH_CONFIG: uvmf_sha512
-
-template: caliptra_cov_cfg.yml
diff --git a/coverage/config/sha512_masked_caliptra_tb.yml b/coverage/config/sha512_masked_caliptra_tb.yml
deleted file mode 100644
index 04534c8a6..000000000
--- a/coverage/config/sha512_masked_caliptra_tb.yml
+++ /dev/null
@@ -1,13 +0,0 @@
-# Copyright (C) Microsoft Corporation. All rights reserved.
-
-# Repo/Bench config specific settings
-# For repo-specific file, common settings like retention policy, additional merge options etc can be specified
-
-#
-# https://dev.azure.com/ms-tsd/Base_Verification/_wiki/wikis/Base_Verification.wiki/34333/Coverage-merge-YAML
-#
-
-variables:
- BENCH_CONFIG: sha512_masked_caliptra_tb
-
-template: caliptra_cov_cfg.yml
diff --git a/coverage/config/soc_ifc_caliptra_tb.yml b/coverage/config/soc_ifc_caliptra_tb.yml
deleted file mode 100644
index de768258e..000000000
--- a/coverage/config/soc_ifc_caliptra_tb.yml
+++ /dev/null
@@ -1,13 +0,0 @@
-# Copyright (C) Microsoft Corporation. All rights reserved.
-
-# Repo/Bench config specific settings
-# For repo-specific file, common settings like retention policy, additional merge options etc can be specified
-
-#
-# https://dev.azure.com/ms-tsd/Base_Verification/_wiki/wikis/Base_Verification.wiki/34333/Coverage-merge-YAML
-#
-
-variables:
- BENCH_CONFIG: uvmf_soc_ifc
-
-template: caliptra_cov_cfg.yml
diff --git a/coverage/config/uart_caliptra_tb.yml b/coverage/config/uart_caliptra_tb.yml
deleted file mode 100644
index e91763f23..000000000
--- a/coverage/config/uart_caliptra_tb.yml
+++ /dev/null
@@ -1,13 +0,0 @@
-# Copyright (C) Microsoft Corporation. All rights reserved.
-
-# Repo/Bench config specific settings
-# For repo-specific file, common settings like retention policy, additional merge options etc can be specified
-
-#
-# https://dev.azure.com/ms-tsd/Base_Verification/_wiki/wikis/Base_Verification.wiki/34333/Coverage-merge-YAML
-#
-
-variables:
- BENCH_CONFIG: uart_caliptra_tb
-
-template: caliptra_cov_cfg.yml
diff --git a/coverage/config/uvmf_caliptra_top_tb.yml b/coverage/config/uvmf_caliptra_top_tb.yml
deleted file mode 100644
index 643b141b9..000000000
--- a/coverage/config/uvmf_caliptra_top_tb.yml
+++ /dev/null
@@ -1,13 +0,0 @@
-# Copyright (C) Microsoft Corporation. All rights reserved.
-
-# Repo/Bench config specific settings
-# For repo-specific file, common settings like retention policy, additional merge options etc can be specified
-
-#
-# https://dev.azure.com/ms-tsd/Base_Verification/_wiki/wikis/Base_Verification.wiki/34333/Coverage-merge-YAML
-#
-
-variables:
- BENCH_CONFIG: uvmf_caliptra_top
-
-template: caliptra_cov_cfg.yml
diff --git a/docs/Caliptra_Integration_Specification.pdf b/docs/Caliptra_Integration_Specification.pdf
index d58dc68c2..0cc3f9ebe 100755
Binary files a/docs/Caliptra_Integration_Specification.pdf and b/docs/Caliptra_Integration_Specification.pdf differ
diff --git a/etc/pipelines/coverage-pipeline-launch.yml b/etc/pipelines/coverage-pipeline-launch.yml
deleted file mode 100644
index d0427c036..000000000
--- a/etc/pipelines/coverage-pipeline-launch.yml
+++ /dev/null
@@ -1,33 +0,0 @@
-# Copyright (C) Microsoft Corporation. All rights reserved.
-
-trigger: none
-
-pr: none
-
-# Scheduled run for 04:19(EST)/01:19(PST), time in UTC
-# * * * * * CMD
-# | | | | |
-# | | | | +------> Day of the week (0-6)
-# | | | +--------> Month of the year (1-12)
-# | | +----------> Day of the month (1-31)
-# | +------------> Hour (0-23)
-# +--------------> Minute (0-59)
-
-schedules:
- - cron: 0 15 * * *
- displayName: CALIPTRA Coverage Merges
- branches:
- include:
- - master
- always: true
-
-parameters:
- - name: skip_db_update
- displayName: Skip merged coverage summary upload to Kusto
- type: boolean
- default: false
-
-extends:
- template: coverage-pipeline.yml
- parameters:
- skip_db_update: ${{ parameters.skip_db_update }}
\ No newline at end of file
diff --git a/etc/pipelines/coverage-pipeline.yml b/etc/pipelines/coverage-pipeline.yml
deleted file mode 100644
index 0a7e45384..000000000
--- a/etc/pipelines/coverage-pipeline.yml
+++ /dev/null
@@ -1,77 +0,0 @@
-# Copyright (C) Microsoft Corporation. All rights reserved.
-
-resources:
- repositories:
- - repository: templates
- type: git
- name: Ether/pipelines
-
-variables:
- - group: AHA_POC_Pipelines
- - name: progress_web
- value: true
-
- - name: pipeline.start_time
- value: $[format('{0:yyyyMMddHH}', pipeline.startTime)]
-
- - name: SUBMIT_SMALL_NC_JOBS
- value: submit -i --memory=60
-
- - name: skip_db_upload_arg
- ${{ if eq(parameters.skip_db_update, 'true') }}:
- value : '--skip_publish'
- ${{ if ne(parameters.skip_db_update, 'true') }}:
- value : ''
-
-parameters:
- - name: skip_db_update
- displayName: Skip merged coverage summary upload to Kusto
- type: boolean
- default: false
-
- - name: cov_dut_list
- displayName: List of duts that are being processed
- type: object
- default:
- # - aes_caliptra_tb
- - caliptra_top_tb
- # - csrng_caliptra_tb
- # - datavault_caliptra_tb
- # - doe_caliptra_tb
- - ecc_caliptra_tb
- # - edn_caliptra_tb
- # - entropy_src_caliptra_tb
- - hmac_caliptra_tb
- # - hmac_drbg_caliptra_tb
- - keyvault_caliptra_tb
- # - kmac_caliptra_tb
- # - lc_ctrl_caliptra_tb
- - pcrvault_caliptra_tb
- # - prim_caliptra_tb
- # - prim_generic_caliptra_tb
- # - sha256_caliptra_tb
- - sha512_caliptra_tb
- # - sha512_masked_caliptra_tb
- - soc_ifc_caliptra_tb
- # - uart_caliptra_tb
- - uvmf_caliptra_top_tb
-
-stages:
-- template: etc/pipelines/templates/promote-pipeline-template.yml@templates
- parameters:
- project: 'AHA_POC'
- repo_url: 'git@ssh.dev.azure.com:v3/ms-tsd/AHA_POC/Caliptra'
- target_branch: 'master'
- top_repo: ''
-
- additional_test_steps:
- - ${{ each cov_dut in parameters.cov_dut_list }}:
- - ${{ cov_dut }}:
- - enabled: true
- - display_name: Coverage merge for ${{ cov_dut }}
- - commands:
- - $(SUBMIT_SMALL_NC_JOBS) python3w -r requirements.txt \${VERIF_TOOLS}/coverage_merge/coverage_merge.py -f \${CALIPTRA_ROOT}/coverage/config/${{ cov_dut }}.yml $(skip_db_upload_arg)
- - timeout: 60
- - run_in_workspace: true
-
-
\ No newline at end of file
diff --git a/etc/pipelines/github-nightly-directed-pipeline.yml b/etc/pipelines/github-nightly-directed-pipeline.yml
deleted file mode 100644
index 807893113..000000000
--- a/etc/pipelines/github-nightly-directed-pipeline.yml
+++ /dev/null
@@ -1,202 +0,0 @@
-# Copyright (C) Microsoft Corporation. All rights reserved.
-
-trigger: none
-pr: none
-schedules:
- - cron: '0 8 * * 0,2-6'
- displayName: GitHub Mirror Repo Nightly Directed Regression (new commits only)
- branches:
- include:
- - main
- always: false
- - cron: '0 8 * * 1'
- displayName: Github MWeekly Directed Regression (always)
- branches:
- include:
- - main
- always: true
-
-# Point to another repository for the pipeline template
-resources:
- repositories:
- - repository: templates
- type: git
- name: Ether/pipelines
-
-variables:
-- group: AHA_POC_Pipelines
-
-- name: pipeline.start_time
- value: $[format('{0:yyyyMMddHH}', pipeline.startTime)]
-
-- name: coverage_dir_path
- value: $[format('/home/scratch/caliptra/coverage/{{namespace}}/{0}/{{provider}}/{{tag}}_{1}_{2:yyyyMMddHH}', variables['System.DefinitionId'], variables['Build.BuildId'], pipeline.startTime)]
-
-- name: coverage_root_args
- ${{ if or(eq(parameters.force_global_coverage, 'true'), eq(variables['Build.SourceBranchName'], 'master')) }}:
- value : --coverage-root $COVERAGE_DIR_PATH
-
-- name: PROJECT_SUFFIX
- value: nightly
-
-parameters:
- - name: force_global_coverage
- displayName: Force global coverage collection when running from non-master branch (not recommended)
- type: boolean
- default: false
-
-stages:
- - template: /etc/pipelines/templates/nightly-pipeline-template.yml@templates # Template reference
- parameters:
- project: 'AHA_POC'
- repo_url: 'git@ssh.dev.azure.com:v3/ms-tsd/AHA_POC/Caliptra'
- target_branch: 'master'
- enable_pipeline_audits: True
- legal_header: false
- legal_header_warning: false
- #fixme_args: --exclude-dirs *SCA*
-
- pre_steps:
- setup: []
- build: []
- test: []
- regress: []
-
- # Define TB invocations for each crypto block
- build_and_sim_map:
-# TODO: Add this back once aes uvmf project is fixed
-# - uvmf_aes:
-# - display_name: 'UVMF_AES'
-# - enabled: true
-# - configspec_name: 'integration_lib'
-# - dut: 'uvmf_cbc_AllKAT'
-# - args: ''
-# - testsuites:
-# - l1_regress:
-# - enabled: true
-# - configspec_name: 'integration_lib'
-# - dut: 'uvmf_cbc_AllKAT'
-# - path: 'Caliptra/src/aes/stimulus/L1_regression.yml'
-# - timeout: 15
- - ecc_top_tb:
- - display_name: 'ECC_TOP_TB'
- - enabled: true
- - configspec_name: 'integration_lib'
- - dut: 'ecc_top_tb'
- - args: '+COVERAGE +CM_HIER=${WORKSPACE}/Caliptra/src/ecc/coverage/config/ecc_cm_hier.cfg --submit-resource-args RAM/28000'
- - testsuites:
- - nightly_directed:
- - enabled: true
- - configspec_name: 'integration_lib'
- - dut: 'ecc_top_tb'
- - sim_args: '+COVERAGE ${{ variables.coverage_root_args }}'
- - path: '${WORKSPACE}/Caliptra/src/ecc/stimulus/testsuites/ecc_nightly_directed_regression.yml'
- - timeout: 60
-
- - hmac_ctrl_tb:
- - display_name: 'HMAC_CTRL_TB'
- - enabled: true
- - configspec_name: 'integration_lib'
- - dut: 'hmac_ctrl_tb'
- - args: '+COVERAGE +CM_HIER=${WORKSPACE}/Caliptra/src/hmac/coverage/config/hmac_cm_hier.cfg --submit-resource-args RAM/28000'
- - testsuites:
- - nightly_directed:
- - enabled: true
- - configspec_name: 'integration_lib'
- - dut: 'hmac_ctrl_tb'
- - sim_args: '+COVERAGE ${{ variables.coverage_root_args }}'
- - path: '${WORKSPACE}/Caliptra/src/hmac/stimulus/testsuites/hmac_nightly_directed_regression.yml'
- - timeout: 60
-
- - sha512_ctrl_32bit_tb:
- - display_name: 'SHA512_CTRL_TB'
- - enabled: true
- - configspec_name: 'integration_lib'
- - dut: 'sha512_ctrl_32bit_tb'
- - args: '+COVERAGE +CM_HIER=${WORKSPACE}/Caliptra/src/sha512/coverage/config/sha512_cm_hier.cfg --submit-resource-args RAM/28000'
- - testsuites:
- - nightly_directed:
- - enabled: true
- - configspec_name: 'integration_lib'
- - dut: 'sha512_ctrl_32bit_tb'
- - sim_args: '+COVERAGE ${{ variables.coverage_root_args }}'
- - path: '${WORKSPACE}/Caliptra/src/sha512/stimulus/testsuites/sha512_nightly_directed_regression.yml'
- - timeout: 60
-
- - sha256_ctrl_tb:
- - display_name: 'SHA256_CTRL_TB'
- - enabled: true
- - configspec_name: 'integration_lib'
- - dut: 'sha256_ctrl_tb'
- - args: '+COVERAGE +CM_HIER=${WORKSPACE}/Caliptra/src/sha256/coverage/config/sha256_cm_hier.cfg --submit-resource-args RAM/28000'
- - testsuites:
- - nightly_directed:
- - enabled: true
- - configspec_name: 'integration_lib'
- - dut: 'sha256_ctrl_tb'
- - sim_args: '+COVERAGE ${{ variables.coverage_root_args }}'
- - path: '${WORKSPACE}/Caliptra/src/sha256/stimulus/testsuites/sha256_nightly_directed_regression.yml'
- - timeout: 60
-
- - doe_core_cbc_tb:
- - display_name: 'DOE_CORE_CBC_TB'
- - enabled: true
- - configspec_name: 'integration_lib'
- - dut: 'doe_core_cbc_tb'
- - args: '+COVERAGE +CM_HIER=${WORKSPACE}/Caliptra/src/doe/coverage/config/doe_cm_hier.cfg --submit-resource-args RAM/28000'
- - testsuites:
- - nightly_directed:
- - enabled: true
- - configspec_name: 'integration_lib'
- - dut: 'doe_core_cbc_tb'
- - sim_args: '+COVERAGE ${{ variables.coverage_root_args }}'
- - path: '${WORKSPACE}/Caliptra/src/doe/stimulus/testsuites/doe_nightly_directed_regression.yml'
- - timeout: 60
-
- - soc_ifc_tb:
- - display_name: 'SOC_IFC_TB'
- - enabled: true
- - configspec_name: 'integration_lib'
- - dut: 'soc_ifc_tb'
- - args: '+COVERAGE +CM_HIER=${WORKSPACE}/Caliptra/src/soc_ifc/coverage/config/soc_ifc_cm_hier.cfg --submit-resource-args RAM/28000'
- - timeout: 10
- - testsuites:
- - nightly_directed:
- - enabled: true
- - configspec_name: 'integration_lib'
- - dut: 'soc_ifc_tb'
- - sim_args: '+COVERAGE ${{ variables.coverage_root_args }}'
- - path: '${WORKSPACE}/Caliptra/src/soc_ifc/stimulus/testsuites/soc_ifc_nightly_directed_regression.yml'
- - timeout: 30
-
- - firmware_tb:
- - display_name: 'FIRMWARE_TB'
- - enabled: true
- - configspec_name: 'integration_lib'
- - dut: 'caliptra_top_tb'
- - args: ''
- - timeout: 10
- - testsuites:
- - nightly_directed:
- - enabled: true
- - configspec_name: 'integration_lib'
- - dut: 'caliptra_top_tb'
- - sim_args: '+COVERAGE ${{ variables.coverage_root_args }}'
- - path: '${WORKSPACE}/Caliptra/src/integration/stimulus/testsuites/caliptra_top_nightly_directed_regression.yml'
- - timeout: 30
-
-# This runs for a veeeery long time and throws UVM failures on some mismatched transactions... need to fix before adding to pipeline
-# - ROM_tb:
-# - display_name: 'ROM_TB'
-# - enabled: true
-# - configspec_name: 'integration_lib'
-# - dut: 'uvmf_caliptra_top'
-# - args: '+COVERAGE +CM_HIER=${WORKSPACE}/Caliptra/src/integration/uvmf_caliptra_top/coverage/config/uvmf_caliptra_top_cm_hier.cfg --submit-resource-args RAM/28000'
-# - testsuites:
-# - l1_regress:
-# - enabled: true
-# - configspec_name: 'integration_lib'
-# - dut: 'uvmf_caliptra_top'
-# - sim_args: '+COVERAGE ${{ variables.coverage_root_args }} +CLP_REGRESSION'
-# - path: '${WORKSPACE}/Caliptra/src/integration/stimulus/testsuites/uvmf_caliptra_top_nightly_directed_regression.yml'
-# - timeout: 1440
diff --git a/etc/pipelines/github-nightly-random-pipeline.yml b/etc/pipelines/github-nightly-random-pipeline.yml
deleted file mode 100644
index ed0660a31..000000000
--- a/etc/pipelines/github-nightly-random-pipeline.yml
+++ /dev/null
@@ -1,202 +0,0 @@
-# Copyright (C) Microsoft Corporation. All rights reserved.
-
-trigger: none
-pr: none
-schedules:
- - cron: '0 8 * * *'
- displayName: GitHub Mirror Repo Nightly Random Regression
- branches:
- include:
- - main
- always: true
-
-# Point to another repository for the pipeline template
-resources:
- repositories:
- - repository: templates
- type: git
- name: Ether/pipelines
-
-variables:
-- group: AHA_POC_Pipelines
-
-- name: pipeline.start_time
- value: $[format('{0:yyyyMMddHH}', pipeline.startTime)]
-
-- name: coverage_dir_path
- value: $[format('/home/scratch/caliptra/coverage/{{namespace}}/{0}/{{provider}}/{{tag}}_{1}_{2:yyyyMMddHH}', variables['System.DefinitionId'], variables['Build.BuildId'], pipeline.startTime)]
-
-- name: coverage_root_args
- ${{ if or(eq(parameters.force_global_coverage, 'true'), eq(variables['Build.SourceBranchName'], 'master')) }}:
- value : --coverage-root $COVERAGE_DIR_PATH
-
-- name: PROJECT_SUFFIX
- value: nightly
-
-parameters:
- - name: force_global_coverage
- displayName: Force global coverage collection when running from non-master branch (not recommended)
- type: boolean
- default: false
-
-stages:
- - template: /etc/pipelines/templates/nightly-pipeline-template.yml@templates # Template reference
- parameters:
- project: 'AHA_POC'
- repo_url: 'git@ssh.dev.azure.com:v3/ms-tsd/AHA_POC/Caliptra'
- target_branch: 'master'
- enable_pipeline_audits: True
- legal_header: false
- legal_header_warning: false
- #fixme_args: --exclude-dirs *SCA*
-
- pre_steps:
- setup: []
- build: []
- test: []
- regress: []
-
- # Define UVMF playbook invocations
- build_and_sim_map:
-# TODO: Add this back once aes uvmf project is fixed
-# - uvmf_aes:
-# - display_name: 'UVMF_AES'
-# - enabled: true
-# - configspec_name: 'integration_lib'
-# - dut: 'uvmf_cbc_AllKAT'
-# - args: ''
-# - testsuites:
-# - l1_regress:
-# - enabled: true
-# - configspec_name: 'integration_lib'
-# - dut: 'uvmf_cbc_AllKAT'
-# - path: 'Caliptra/src/aes/stimulus/L1_regression.yml'
-# - timeout: 15
- - uvmf_ecc:
- - display_name: 'UVMF_ECC'
- - enabled: true
- - configspec_name: 'integration_lib'
- - dut: 'uvmf_ecc'
- - args: '+COVERAGE +CM_HIER=${WORKSPACE}/Caliptra/src/ecc/uvmf_ecc/coverage/config/uvmf_ecc_cm_hier.cfg --submit-resource-args RAM/28000'
- - testsuites:
- - l1_regress:
- - enabled: true
- - configspec_name: 'integration_lib'
- - dut: 'uvmf_ecc'
- - sim_args: '+COVERAGE ${{ variables.coverage_root_args }}'
- - path: '${WORKSPACE}/Caliptra/src/ecc/stimulus/testsuites/ecc_nightly_random_regression.yml'
- - timeout: 1440
- - uvmf_hmac:
- - display_name: 'UVMF_HMAC'
- - enabled: true
- - configspec_name: 'integration_lib'
- - dut: 'uvmf_hmac'
- - args: '+COVERAGE +CM_HIER=${WORKSPACE}/Caliptra/src/hmac/uvmf_2022/coverage/config/uvmf_hmac_cm_hier.cfg --submit-resource-args RAM/28000'
- - testsuites:
- - l1_regress:
- - enabled: true
- - configspec_name: 'integration_lib'
- - dut: 'uvmf_hmac'
- - sim_args: '+COVERAGE ${{ variables.coverage_root_args }}'
- - path: '${WORKSPACE}/Caliptra/src/hmac/stimulus/testsuites/hmac_nightly_random_regression.yml'
- - timeout: 1440
- - uvmf_sha512:
- - display_name: 'UVMF_SHA512'
- - enabled: true
- - configspec_name: 'integration_lib'
- - dut: 'uvmf_sha512'
- - args: '+COVERAGE +CM_HIER=${WORKSPACE}/Caliptra/src/sha512/uvmf_sha512/coverage/config/uvmf_sha512_cm_hier.cfg --submit-resource-args RAM/28000'
- - testsuites:
- - l1_regress:
- - enabled: true
- - configspec_name: 'integration_lib'
- - dut: 'uvmf_sha512'
- - sim_args: '+COVERAGE ${{ variables.coverage_root_args }}'
- - path: '${WORKSPACE}/Caliptra/src/sha512/stimulus/testsuites/sha512_nightly_random_regression.yml'
- - timeout: 1440
- - sha256_random_test:
- - display_name: 'SHA256_RANDOM_TEST'
- - enabled: true
- - configspec_name: 'integration_lib'
- - dut: 'sha256_random_test'
- #- args: '+COVERAGE +CM_HIER=${WORKSPACE}/Caliptra/src/sha256/coverage/config/sha256_cm_hier.cfg --submit-resource-args RAM/28000'
- - testsuites:
- - l1_regress:
- - enabled: true
- - configspec_name: 'integration_lib'
- - dut: 'sha256_random_test'
- #- sim_args: '+COVERAGE ${{ variables.coverage_root_args }}'
- - path: '${WORKSPACE}/Caliptra/src/sha256/stimulus/testsuites/sha256_nightly_random_regression.yml'
- - timeout: 1440
- - uvmf_soc_ifc:
- - display_name: 'UVMF_SOC_IFC'
- - enabled: true
- - configspec_name: 'integration_lib'
- - dut: 'uvmf_soc_ifc'
- - args: '+COVERAGE +CM_HIER=${WORKSPACE}/Caliptra/src/soc_ifc/uvmf_soc_ifc/coverage/config/uvmf_soc_ifc_cm_hier.cfg --submit-resource-args RAM/28000'
- - testsuites:
- - l1_regress:
- - enabled: true
- - configspec_name: 'integration_lib'
- - dut: 'uvmf_soc_ifc'
- # TODO forcibly disable uvm warnings in soc_ifc_predictor and soc_ifc_scoreboard for now. Remove this once they're stabilized.
- - sim_args: '+COVERAGE ${{ variables.coverage_root_args }} +CLP_REGRESSION'
- - path: '${WORKSPACE}/Caliptra/src/soc_ifc/stimulus/testsuites/soc_ifc_nightly_random_regression.yml'
- - timeout: 1440
- - uvmf_kv:
- - display_name: 'UVMF_KV'
- - enabled: true
- - configspec_name: 'integration_lib'
- - dut: 'uvmf_kv'
- - args: '+COVERAGE +CM_HIER=${WORKSPACE}/Caliptra/src/keyvault/uvmf_kv/coverage/config/uvmf_kv_cm_hier.cfg --submit-resource-args RAM/28000'
- - testsuites:
- - l1_regress:
- - enabled: true
- - configspec_name: 'integration_lib'
- - dut: 'uvmf_kv'
- - sim_args: '+COVERAGE ${{ variables.coverage_root_args }}'
- - path: '${WORKSPACE}/Caliptra/src/keyvault/stimulus/testsuites/kv_nightly_random_regression.yml'
- - timeout: 1440
- - uvmf_pv:
- - display_name: 'UVMF_PV'
- - enabled: true
- - configspec_name: 'integration_lib'
- - dut: 'uvmf_pv'
- - args: '+COVERAGE +CM_HIER=${WORKSPACE}/Caliptra/src/pcrvault/uvmf_pv/coverage/config/uvmf_pv_cm_hier.cfg --submit-resource-args RAM/28000'
- - testsuites:
- - l1_regress:
- - enabled: true
- - configspec_name: 'integration_lib'
- - dut: 'uvmf_pv'
- - sim_args: '+COVERAGE ${{ variables.coverage_root_args }}'
- - path: '${WORKSPACE}/Caliptra/src/pcrvault/stimulus/testsuites/pv_nightly_random_regression.yml'
- - timeout: 1440
- - uvmf_caliptra_top:
- - display_name: 'UVMF_CALIPTRA_TOP'
- - enabled: true
- - configspec_name: 'integration_lib'
- - dut: 'uvmf_caliptra_top'
- - args: '+COVERAGE +CM_HIER=${WORKSPACE}/Caliptra/src/integration/uvmf_caliptra_top/coverage/config/uvmf_caliptra_top_cm_hier.cfg --submit-resource-args RAM/28000'
- - testsuites:
- - l1_regress:
- - enabled: true
- - configspec_name: 'integration_lib'
- - dut: 'uvmf_caliptra_top'
- # TODO forcibly disable uvm warnings in soc_ifc_predictor and soc_ifc_scoreboard for now. Remove this once they're stabilized.
- - sim_args: '+COVERAGE ${{ variables.coverage_root_args }} +CLP_REGRESSION'
- - path: '${WORKSPACE}/Caliptra/src/integration/stimulus/testsuites/caliptra_top_nightly_random_regression.yml'
- - timeout: 1440
- - caliptra_top_tb:
- - display_name: 'CALIPTRA_TOP_TB'
- - enabled: true
- - configspec_name: 'integration_lib'
- - dut: 'caliptra_top_tb'
- #- args: '+CLP_REGRESSION'
- - testsuites:
- - l1_regress:
- - enabled: true
- - configspec_name: 'integration_lib'
- - dut: 'caliptra_top_tb'
- - sim_args: '+CLP_REGRESSION'
- - path: '${WORKSPACE}/Caliptra/src/integration/stimulus/testsuites/caliptra_top_tb_nightly_random_regression.yml'
- - timeout: 1440
diff --git a/src/caliptra_prim/rtl/caliptra_prim_assert_sec_cm.svh b/src/caliptra_prim/rtl/caliptra_prim_assert_sec_cm.svh
index 11ba287e0..096b7b61f 100644
--- a/src/caliptra_prim/rtl/caliptra_prim_assert_sec_cm.svh
+++ b/src/caliptra_prim/rtl/caliptra_prim_assert_sec_cm.svh
@@ -45,21 +45,4 @@
`CALIPTRA_ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ALERT(NAME_, \
REG_TOP_HIER_.u_caliptra_prim_reg_we_check.u_caliptra_prim_onehot_check, ALERT_, GATE_, MAX_CYCLES_)
-// macros for security countermeasures that will trigger other errors
-`define CALIPTRA_ASSERT_PRIM_FSM_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_ = 0, MAX_CYCLES_ = 2, CLK_ = clk_i, RST_ = !rst_ni) \
- `CALIPTRA_ASSERT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_, MAX_CYCLES_, unused_err_o, CLK_, RST_)
-
-`define CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_ = 0, MAX_CYCLES_ = 2, CLK_ = clk_i, RST_ = !rst_ni) \
- `CALIPTRA_ASSERT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_, MAX_CYCLES_, err_o, CLK_, RST_)
-
-`define CALIPTRA_ASSERT_PRIM_DOUBLE_LFSR_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_ = 0, MAX_CYCLES_ = 2, CLK_ = clk_i, RST_ = !rst_ni) \
- `CALIPTRA_ASSERT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_, MAX_CYCLES_, err_o, CLK_, RST_)
-
-`define CALIPTRA_ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_ = 0, MAX_CYCLES_ = `_CALIPTRA_SEC_CM_ALERT_MAX_CYC, CLK_ = clk_i, RST_ = !rst_ni) \
- `CALIPTRA_ASSERT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_, MAX_CYCLES_, err_o, CLK_, RST_)
-
-`define CALIPTRA_ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ERR(NAME_, REG_TOP_HIER_, ERR_, GATE_ = 0, MAX_CYCLES_ = `_CALIPTRA_SEC_CM_ALERT_MAX_CYC, CLK_ = clk_i, RST_ = !rst_ni) \
- `CALIPTRA_ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ERR(NAME_, \
- REG_TOP_HIER_.u_caliptra_prim_reg_we_check.u_caliptra_prim_onehot_check, ERR_, GATE_, MAX_CYCLES_, CLK_, RST_)
-
`endif // PRIM_ASSERT_SEC_CM_SVH
diff --git a/src/csrng/rtl/csrng_reg_top.sv b/src/csrng/rtl/csrng_reg_top.sv
index efa24f788..70a8d0056 100644
--- a/src/csrng/rtl/csrng_reg_top.sv
+++ b/src/csrng/rtl/csrng_reg_top.sv
@@ -2059,10 +2059,6 @@ module csrng_reg_top #(
addr_hit[16]: begin
reg_rdata_next[7:0] = main_sm_state_qs;
end
-
- default: begin
- reg_rdata_next = '1;
- end
endcase
end
diff --git a/src/entropy_src/rtl/entropy_src_reg_top.sv b/src/entropy_src/rtl/entropy_src_reg_top.sv
index 0abcc3d6e..e443608a4 100644
--- a/src/entropy_src/rtl/entropy_src_reg_top.sv
+++ b/src/entropy_src/rtl/entropy_src_reg_top.sv
@@ -3892,10 +3892,6 @@ module entropy_src_reg_top #(
addr_hit[56]: begin
reg_rdata_next[8:0] = main_sm_state_qs;
end
-
- default: begin
- reg_rdata_next = '1;
- end
endcase
end
diff --git a/src/integration/asserts/caliptra_top_sva.sv b/src/integration/asserts/caliptra_top_sva.sv
index 19fa0f0f3..8da8234aa 100644
--- a/src/integration/asserts/caliptra_top_sva.sv
+++ b/src/integration/asserts/caliptra_top_sva.sv
@@ -284,14 +284,14 @@ module caliptra_top_sva
UDS_fuse_wr_check: assert property (
@(posedge `SVA_RDC_CLK)
disable iff(`CPTRA_TOP_PATH.cptra_in_debug_scan_mode || clear_obf_secrets_int || cptra_in_debug_scan_mode_int)
- (`SOC_IFC_TOP_PATH.soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value) |-> `CPTRA_TOP_PATH.obf_uds_seed_dbg == $past(`CPTRA_TOP_PATH.obf_uds_seed_dbg)
+ (`SOC_IFC_TOP_PATH.soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value) |-> `CPTRA_TOP_PATH.obf_uds_seed == $past(`CPTRA_TOP_PATH.obf_uds_seed)
)
else $display("SVA ERROR: Unexpected write to obf uds seed!");
FE_fuse_wr_check: assert property (
@(posedge `SVA_RDC_CLK)
disable iff(`CPTRA_TOP_PATH.cptra_in_debug_scan_mode || clear_obf_secrets_int || cptra_in_debug_scan_mode_int)
- (`SOC_IFC_TOP_PATH.soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value) |-> `CPTRA_TOP_PATH.obf_field_entropy_dbg == $past(`CPTRA_TOP_PATH.obf_field_entropy_dbg)
+ (`SOC_IFC_TOP_PATH.soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value) |-> `CPTRA_TOP_PATH.obf_field_entropy == $past(`CPTRA_TOP_PATH.obf_field_entropy)
)
else $display("SVA ERROR: Unexpected write to obf field entropy!");
diff --git a/src/integration/rtl/caliptra_top.sv b/src/integration/rtl/caliptra_top.sv
index 4319daa81..3937626d9 100755
--- a/src/integration/rtl/caliptra_top.sv
+++ b/src/integration/rtl/caliptra_top.sv
@@ -71,7 +71,7 @@ module caliptra_top
//TODO update with I3C interface signals
// Caliptra Memory Export Interface
- el2_mem_if el2_mem_export,
+ el2_mem_if.veer_sram_src el2_mem_export,
//SRAM interface for mbox
output logic mbox_sram_cs,
@@ -127,6 +127,7 @@ module caliptra_top
logic clk_cg ;
logic soc_ifc_clk_cg ;
logic rdc_clk_cg ;
+ logic uc_clk_cg ;
logic [31:0] ic_haddr ;
logic [2:0] ic_hburst ;
@@ -410,7 +411,7 @@ el2_veer_wrapper rvtop (
.rst_l ( cptra_uc_rst_b),
`endif
.dbg_rst_l ( cptra_pwrgood),
- .clk ( rdc_clk_cg ),
+ .clk ( uc_clk_cg ),
.rst_vec ( reset_vector[31:1]),
.nmi_int ( nmi_int ),
.nmi_vec ( nmi_vector[31:1]),
@@ -649,9 +650,11 @@ clk_gate cg (
.clk_gate_en(clk_gating_en),
.cpu_halt_status(o_cpu_halt_status),
.rdc_clk_dis(rdc_clk_dis),
+ .rdc_clk_dis_uc (fw_update_rst_window),
.clk_cg (clk_cg),
.soc_ifc_clk_cg (soc_ifc_clk_cg),
.rdc_clk_cg (rdc_clk_cg),
+ .uc_clk_cg (uc_clk_cg),
.generic_input_wires(generic_input_wires),
.cptra_error_fatal(cptra_error_fatal),
.cptra_in_debug_scan_mode(cptra_in_debug_scan_mode),
diff --git a/src/integration/stimulus/L0_regression.yml b/src/integration/stimulus/L0_regression.yml
index 66e8a16fc..e979afb51 100644
--- a/src/integration/stimulus/L0_regression.yml
+++ b/src/integration/stimulus/L0_regression.yml
@@ -46,6 +46,7 @@ contents:
- ../test_suites/smoke_test_ahb_mux/smoke_test_ahb_mux.yml
- ../test_suites/smoke_test_doe_rand/smoke_test_doe_rand.yml
- ../test_suites/smoke_test_doe_scan/smoke_test_doe_scan.yml
+ - ../test_suites/smoke_test_zeroize_crypto/smoke_test_zeroize_crypto.yml
#- ../test_suites/smoke_test_doe_cg/smoke_test_doe_cg.yml
# data vault tests
- ../test_suites/smoke_test_datavault_basic/smoke_test_datavault_basic.yml
diff --git a/src/integration/stimulus/testsuites/caliptra_top_nightly_random_regression.yml b/src/integration/stimulus/testsuites/caliptra_top_nightly_random_regression.yml
index a255a97ca..70c33e93e 100644
--- a/src/integration/stimulus/testsuites/caliptra_top_nightly_random_regression.yml
+++ b/src/integration/stimulus/testsuites/caliptra_top_nightly_random_regression.yml
@@ -16,3 +16,5 @@ contents:
path: "{template_basename}__{seed}.yml"
templates:
$CALIPTRA_ROOT/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_rand_test : { weight 100 }
+ $CALIPTRA_ROOT/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_wdt_test : { weight 100 }
+ $CALIPTRA_ROOT/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_wdt_independent_test : { weight 100 }
diff --git a/src/integration/tb/caliptra_top_tb.sv b/src/integration/tb/caliptra_top_tb.sv
index 12fbb8487..ca7f5e21e 100755
--- a/src/integration/tb/caliptra_top_tb.sv
+++ b/src/integration/tb/caliptra_top_tb.sv
@@ -1092,7 +1092,7 @@ caliptra_top caliptra_top_dut (
.uart_rx(uart_loopback),
`endif
- .el2_mem_export(el2_mem_export),
+ .el2_mem_export(el2_mem_export.veer_sram_src),
.ready_for_fuses(ready_for_fuses),
.ready_for_fw_push(ready_for_fw_push),
@@ -1193,7 +1193,7 @@ caliptra_top_tb_services #(
.cptra_rst_b(cptra_rst_b),
// Caliptra Memory Export Interface
- .el2_mem_export (el2_mem_export),
+ .el2_mem_export (el2_mem_export.veer_sram_sink),
//SRAM interface for mbox
.mbox_sram_cs (mbox_sram_cs ),
diff --git a/src/integration/tb/caliptra_top_tb_services.sv b/src/integration/tb/caliptra_top_tb_services.sv
index 8534e5660..e274b6565 100644
--- a/src/integration/tb/caliptra_top_tb_services.sv
+++ b/src/integration/tb/caliptra_top_tb_services.sv
@@ -45,7 +45,7 @@ module caliptra_top_tb_services
input wire logic cptra_rst_b,
// Caliptra Memory Export Interface
- el2_mem_if.top el2_mem_export,
+ el2_mem_if.veer_sram_sink el2_mem_export,
//SRAM interface for mbox
input wire logic mbox_sram_cs,
@@ -234,6 +234,7 @@ module caliptra_top_tb_services
// 8'h91 - Issue PCR singing with randomized vector
// 8'h92 - Check PCR singing with randomized vector
// 8'h98 - Inject invalid zero sign_r into ECC
+ // 8'h99 - Inject zeroize into HMAC
// 8'ha0: 8'ha7 - Inject HMAC_KEY to kv_key register
// 8'hc0: 8'hc7 - Inject SHA_BLOCK to kv_key register
// 8'he0 - Set random ICCM SRAM single bit error injection
@@ -559,6 +560,40 @@ endgenerate //IV_NO
en_jtag_access <= 'b0;
end
end
+
+ logic inject_zeroize_to_hmac;
+ logic inject_zeroize_to_hmac_cmd;
+ logic [3 : 0] inject_zeroize_to_hmac_cnt;
+ always@(posedge clk or negedge cptra_rst_b) begin
+ if (~cptra_rst_b) begin
+ inject_zeroize_to_hmac_cmd <= 1'b0;
+ inject_zeroize_to_hmac <= 1'b0;
+ inject_zeroize_to_hmac_cnt <= '0;
+ end
+ else if((WriteData == 'h99) && mailbox_write) begin
+ inject_zeroize_to_hmac_cmd <= 1'b1;
+ end
+ else if (inject_zeroize_to_hmac_cmd) begin
+ if (caliptra_top_dut.hmac.hmac_inst.core_tag_we) begin
+ inject_zeroize_to_hmac <= 1'b1;
+ end
+ if (inject_zeroize_to_hmac) begin
+ if (inject_zeroize_to_hmac_cnt < 4'hf) begin
+ inject_zeroize_to_hmac_cnt <= inject_zeroize_to_hmac_cnt + 1'b1;
+ end
+ end
+ end
+ end
+ always@(negedge clk) begin
+ if (inject_zeroize_to_hmac) begin
+ if (inject_zeroize_to_hmac_cnt == 4'h5) begin
+ force caliptra_top_dut.hmac.hmac_inst.i_hmac_reg.field_storage.HMAC384_CTRL.ZEROIZE.value = 1'b1;
+ end
+ else begin
+ release caliptra_top_dut.hmac.hmac_inst.i_hmac_reg.field_storage.HMAC384_CTRL.ZEROIZE.value;
+ end
+ end
+ end
//Inject fatal error after a delay
logic inject_fatal_error;
diff --git a/src/integration/tb/caliptra_veer_sram_export.sv b/src/integration/tb/caliptra_veer_sram_export.sv
index 65e1f66cc..04e717840 100644
--- a/src/integration/tb/caliptra_veer_sram_export.sv
+++ b/src/integration/tb/caliptra_veer_sram_export.sv
@@ -23,7 +23,7 @@ module caliptra_veer_sram_export import caliptra_top_tb_pkg::*; #(
// [2] - Single bit, DCCM Error Injection
// [3] - Double bit, DCCM Error Injection
input veer_sram_error_injection_mode_t sram_error_injection_mode,
- el2_mem_if.top el2_mem_export
+ el2_mem_if.veer_sram_sink el2_mem_export
);
//////////////////////////////////////////////////////
diff --git a/src/integration/test_suites/caliptra_rt/caliptra_isr.h b/src/integration/test_suites/caliptra_rt/caliptra_isr.h
index 60a25c298..1f7d023bc 100644
--- a/src/integration/test_suites/caliptra_rt/caliptra_isr.h
+++ b/src/integration/test_suites/caliptra_rt/caliptra_isr.h
@@ -66,7 +66,7 @@ void init_interrupts(void);
// otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr"
inline void service_doe_error_intr() {return;}
inline void service_doe_notif_intr() {
- uint32_t * reg = (uint32_t *) (CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+ volatile uint32_t * reg = (volatile uint32_t *) (CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
uint32_t sts = *reg;
/* Write 1 to Clear the pending interrupt */
if (sts & DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
@@ -82,7 +82,7 @@ inline void service_doe_notif_intr() {
inline void service_ecc_error_intr() {return;}
inline void service_ecc_notif_intr() {
- uint32_t * reg = (uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+ volatile uint32_t * reg = (volatile uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
uint32_t sts = *reg;
/* Write 1 to Clear the pending interrupt */
if (sts & ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
@@ -98,7 +98,7 @@ inline void service_ecc_notif_intr() {
inline void service_hmac_error_intr() {return;}
inline void service_hmac_notif_intr() {
- uint32_t * reg = (uint32_t *) (CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+ volatile uint32_t * reg = (volatile uint32_t *) (CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
uint32_t sts = *reg;
/* Write 1 to Clear the pending interrupt */
if (sts & HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
@@ -116,7 +116,7 @@ inline void service_kv_error_intr() {return;}
inline void service_kv_notif_intr() {return;}
inline void service_sha512_error_intr() {return;}
inline void service_sha512_notif_intr() {
- uint32_t * reg = (uint32_t *) (CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+ volatile uint32_t * reg = (volatile uint32_t *) (CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
uint32_t sts = *reg;
/* Write 1 to Clear the pending interrupt */
if (sts & SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
@@ -132,7 +132,7 @@ inline void service_sha512_notif_intr() {
inline void service_sha256_error_intr() {return;}
inline void service_sha256_notif_intr() {
- uint32_t * reg = (uint32_t *) (CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+ volatile uint32_t * reg = (volatile uint32_t *) (CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
uint32_t sts = *reg;
/* Write 1 to Clear the pending interrupt */
if (sts & SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
@@ -154,7 +154,7 @@ inline void service_i3c_error_intr() {return;}
inline void service_i3c_notif_intr() {return;}
inline void service_soc_ifc_error_intr() {
- uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+ volatile uint32_t * reg = (volatile uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
uint32_t sts = *reg;
/* Write 1 to Clear the pending interrupt */
if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
@@ -181,14 +181,14 @@ inline void service_soc_ifc_error_intr() {
*reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
}
- if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK) {
- *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK;
- cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK;
- }
- if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK) {
- *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK;
- cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK;
- }
+ // if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK) {
+ // *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK;
+ // cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK;
+ // }
+ // if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK) {
+ // *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK;
+ // cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK;
+ // }
if (sts == 0) {
VPRINTF(ERROR,"bad soc_ifc_error_intr sts:%x\n", sts);
SEND_STDOUT_CTRL(0x1);
@@ -197,7 +197,7 @@ inline void service_soc_ifc_error_intr() {
}
inline void service_soc_ifc_notif_intr () {
- uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+ volatile uint32_t * reg = (volatile uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
uint32_t sts = *reg;
/* Write 1 to Clear the pending interrupt */
if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
@@ -233,7 +233,7 @@ inline void service_soc_ifc_notif_intr () {
inline void service_sha512_acc_error_intr() {return;}
inline void service_sha512_acc_notif_intr() {
- uint32_t * reg = (uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+ volatile uint32_t * reg = (volatile uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
uint32_t sts = *reg;
/* Write 1 to Clear the pending interrupt */
if (sts & SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
diff --git a/src/integration/test_suites/caliptra_rt/caliptra_rt.c b/src/integration/test_suites/caliptra_rt/caliptra_rt.c
index 64dfe16cb..5474d3032 100644
--- a/src/integration/test_suites/caliptra_rt/caliptra_rt.c
+++ b/src/integration/test_suites/caliptra_rt/caliptra_rt.c
@@ -72,6 +72,20 @@ volatile caliptra_intr_received_s cptra_intr_rcv = {
.sha512_acc_error = 0,
.sha512_acc_notif = 0,
};
+#define CLEAR_INTR_FLAG_SAFELY(flag, mask) \
+ csr_clr_bits_mstatus(MSTATUS_MIE_BIT_MASK); \
+ flag &= mask; \
+ csr_set_bits_mstatus(MSTATUS_MIE_BIT_MASK);
+
+#ifndef MY_RANDOM_SEED
+#define MY_RANDOM_SEED 17
+#endif // MY_RANDOM_SEED
+
+
+enum gen_in_value {
+ WDT_CASCADE = 0x0000abab,
+ WDT_INDEPENDENT = 0x0000efef
+};
/* --------------- Function Definitions --------------- */
void nmi_handler() {
@@ -111,13 +125,14 @@ void caliptra_rt() {
uint32_t reg_addr;
uint32_t read_data;
uint32_t loop_iter;
+ uint32_t loop_iter2;
uint32_t temp; // multi-purpose variable
//WDT vars
int i;
int wdt_rand_t1_val;
int wdt_rand_t2_val;
- int mode;
+ int mode = 0;
VPRINTF(MEDIUM, "----------------------------------\n");
VPRINTF(LOW, "- Caliptra Validation RT!!\n" );
@@ -126,25 +141,52 @@ void caliptra_rt() {
//set NMI vector
lsu_write_32((uintptr_t) (CLP_SOC_IFC_REG_INTERNAL_NMI_VECTOR), (uint32_t) (nmi_handler));
+ // Initialize rand num generator
+ VPRINTF(LOW,"\nUsing random seed = %d\n\n", MY_RANDOM_SEED);
+ srand((uint32_t) MY_RANDOM_SEED);
+
// Runtime flow -- set ready for RT
soc_ifc_set_flow_status_field(SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_RUNTIME_MASK);
+#ifdef WDT_TEST
VPRINTF(LOW, "Enabling WDT intr\n");
lsu_write_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R, SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_WDT_TIMER1_TIMEOUT_EN_MASK | SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_WDT_TIMER2_TIMEOUT_EN_MASK);
lsu_write_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R, SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK);
+ //Generate constrained random WDT timer periods
wdt_rand_t1_val = rand() % 0xfff;
wdt_rand_t2_val = rand() % 0xfff;
- mode = rand() % 2; //0 - independent mode, 1 - cascade mode
- if (mode){
- VPRINTF(LOW, "Restarting WDT in cascade mode (only t1 timeout)\n");
- //TODO also add t2 timeout (NMI event)
+
+ while (!(lsu_read_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R) & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK));
+ if (lsu_read_32(CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0) == WDT_CASCADE) { //rand() % 2; //0 - independent mode, 1 - cascade mode
+ VPRINTF(LOW, "Restarting WDT in cascade mode\n");
+ //Enable timer1 to start cascade mode
lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_EN, SOC_IFC_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_MASK);
+ //Set timer1 period to a small random value, so core can see timer1 timing out
lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0, wdt_rand_t1_val);
lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1, 0x00000000);
+ //Restart timer1
+ lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL, SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART_MASK);
+
+ while (!(lsu_read_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R) & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK));
+ //Clear timer1 intr
+ lsu_write_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R, SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK);
+
+ //Program timer1 and 2 periods to <= 0x100 to test NMI generation
+ wdt_rand_t1_val = rand() % 0x100;
+ wdt_rand_t2_val = rand() % 0x100;
+ //WDT cascade mode with t2 timeout
+ lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_EN, !SOC_IFC_REG_CPTRA_WDT_TIMER2_EN_TIMER2_EN_MASK);
+ lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0, wdt_rand_t1_val);
+ lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1, 0x00000000);
+ lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0, wdt_rand_t2_val);
+ lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1, 0x00000000);
lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL, SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART_MASK);
+ // lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL, SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART_MASK);
+
+ //Don't service interrupts so it can timeout and cause NMI
}
- else {
+ else if (lsu_read_32(CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0) == WDT_INDEPENDENT){
VPRINTF(LOW, "Restarting WDT in independent mode\n");
lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_EN, SOC_IFC_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_MASK);
lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0, wdt_rand_t1_val);
@@ -158,15 +200,27 @@ void caliptra_rt() {
lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL, SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART_MASK);
while (!(lsu_read_32(CLP_SOC_IFC_REG_CPTRA_WDT_STATUS) & SOC_IFC_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_MASK));
- //Reset timer period to avoid hangs in test
+ //Reset timer1 period to avoid hangs in test
lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0, 0xffffffff);
lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1, 0xffffffff);
+ while (!(lsu_read_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R) & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK));
+ //Clear timer1 intr
+ lsu_write_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R, SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK);
+ cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK;
+
+ //Reset timer2 period to avoid hangs in test
while (!(lsu_read_32(CLP_SOC_IFC_REG_CPTRA_WDT_STATUS) & SOC_IFC_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_MASK));
lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0, 0xffffffff);
lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1, 0xffffffff);
+ while (!(lsu_read_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R) & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK));
+ //Clear timer2 intr
+ lsu_write_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R, SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK);
+ cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK;
+
}
+#endif
// Initialization
init_interrupts();
lsu_write_32(CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTR_EN_R, 0); // FIXME tmp workaround to UVM issue with predicting SHA accelerator interrupts
@@ -177,34 +231,38 @@ void caliptra_rt() {
if (cptra_intr_rcv.soc_ifc_error ) {
VPRINTF(ERROR, "Intr received: soc_ifc_error\n");
if (cptra_intr_rcv.soc_ifc_error & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
- cptra_intr_rcv.soc_ifc_error &= ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+ CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK)
}
if (cptra_intr_rcv.soc_ifc_error & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) {
- cptra_intr_rcv.soc_ifc_error &= ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+ CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK)
}
if (cptra_intr_rcv.soc_ifc_error & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
enum mbox_fsm_e state;
- cptra_intr_rcv.soc_ifc_error &= ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+ CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK)
// If we entered the error state, we must use force-unlock to reset the mailbox state
state = (lsu_read_32(CLP_MBOX_CSR_MBOX_STATUS) & MBOX_CSR_MBOX_STATUS_MBOX_FSM_PS_MASK) >> MBOX_CSR_MBOX_STATUS_MBOX_FSM_PS_LOW;
if (state == MBOX_ERROR) {
+ // clr command interrupt to avoid attempted re-processing after force-unlock
+ if (cptra_intr_rcv.soc_ifc_notif & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
+ CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_notif, ~SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK)
+ }
lsu_write_32(CLP_MBOX_CSR_MBOX_UNLOCK, MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK);
}
}
if (cptra_intr_rcv.soc_ifc_error & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK) {
- cptra_intr_rcv.soc_ifc_error &= ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+ CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK)
}
if (cptra_intr_rcv.soc_ifc_error & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK) {
- cptra_intr_rcv.soc_ifc_error &= ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+ CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK)
}
if (cptra_intr_rcv.soc_ifc_error & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) {
- cptra_intr_rcv.soc_ifc_error &= ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+ CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK)
}
if (cptra_intr_rcv.soc_ifc_error & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK) {
- cptra_intr_rcv.soc_ifc_error &= ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK;
+ CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK)
}
if (cptra_intr_rcv.soc_ifc_error & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK) {
- cptra_intr_rcv.soc_ifc_error &= ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK;
+ CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK)
}
if (cptra_intr_rcv.soc_ifc_error & (~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK &
~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK &
@@ -227,7 +285,7 @@ void caliptra_rt() {
if (cptra_intr_rcv.ecc_error ) {
VPRINTF(ERROR, "Intr received: ecc_error\n");
if (cptra_intr_rcv.ecc_error & ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
- cptra_intr_rcv.ecc_error &= ~ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+ CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.ecc_error, ~ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK)
}
if (cptra_intr_rcv.ecc_error & ~ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
VPRINTF(FATAL, "Intr received: unsupported ecc_error (0x%x)\n", cptra_intr_rcv.ecc_error);
@@ -272,13 +330,13 @@ void caliptra_rt() {
uint8_t fsm_chk;
VPRINTF(LOW, "Intr received: soc_ifc_notif\n");
if (cptra_intr_rcv.soc_ifc_notif & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
- cptra_intr_rcv.soc_ifc_notif &= ~SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+ CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_notif, ~SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK)
fsm_chk = soc_ifc_chk_execute_uc();
if (fsm_chk != 0) {
if (fsm_chk == 0xF) {
if (cptra_intr_rcv.soc_ifc_error & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
- cptra_intr_rcv.soc_ifc_error &= ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
- VPRINTF(LOW, "Clearing FW soc_ifc_error intr bit after servicing\n");
+ CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK)
+ VPRINTF(LOW, "Clearing FW soc_ifc_error intr bit (cmd fail) after servicing\n");
} else {
VPRINTF(ERROR, "After finding an error and resetting the mailbox with force unlock, RT firmware has not received an soc_ifc_err_intr!\n");
SEND_STDOUT_CTRL(0x1);
@@ -296,7 +354,7 @@ void caliptra_rt() {
}
VPRINTF(MEDIUM, "Triggering FW update reset\n");
//Trigger firmware update reset, new fw will get copied over from ROM
- soc_ifc_set_fw_update_reset();
+ soc_ifc_set_fw_update_reset((uint8_t) (rand() & 0xFF));
}
else if (op.cmd & MBOX_CMD_FIELD_RESP_MASK) {
VPRINTF(MEDIUM, "Received mailbox command (expecting RESP) from SOC! Got 0x%x\n", op.cmd);
@@ -324,16 +382,20 @@ void caliptra_rt() {
mode = (op.cmd == MBOX_CMD_SHA384_REQ) ? SHA_MBOX_384 : SHA_MBOX_512;
//First dword contains the start address
temp = soc_ifc_mbox_read_dataout_single();
- //dlen in bytes
- read_data = lsu_read_32(CLP_MBOX_CSR_MBOX_DLEN);
- read_data = read_data - temp;
+ //ignore the bytes used for start address
+ op.dlen = op.dlen - 4;
+ //Copy the KAT to the start address using direct access
+ for (loop_iter = 0; loop_iter 5 ? "will override" : wait_cycles > 0 ? "will use default 5" : "won't override");
+ // A 0-value argument means don't override the current value
+ if (wait_cycles) {
+ // Enforce minimum wait_cycles of 5
+ if (wait_cycles > 5) {
+ lsu_write_32(CLP_SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES, wait_cycles);
+ } else {
+ lsu_write_32(CLP_SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES, 5);
+ }
+ }
reg = lsu_read_32(CLP_SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET);
reg = (reg | SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_CORE_RST_MASK);
lsu_write_32(CLP_SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET,reg);
diff --git a/src/integration/test_suites/libs/soc_ifc/soc_ifc.h b/src/integration/test_suites/libs/soc_ifc/soc_ifc.h
index 488fb7c89..99fd2a28e 100644
--- a/src/integration/test_suites/libs/soc_ifc/soc_ifc.h
+++ b/src/integration/test_suites/libs/soc_ifc/soc_ifc.h
@@ -94,15 +94,18 @@ enum sha_accel_mode_e {
inline uint32_t soc_ifc_mbox_read_dataout_single() {
return lsu_read_32(CLP_MBOX_CSR_MBOX_DATAOUT);
}
-inline uint32_t soc_ifc_mbox_dir_read_dataout_single(uint32_t rdptr) {
+inline uint32_t soc_ifc_mbox_dir_read_single(uint32_t rdptr) {
return lsu_read_32(0x30000000 + rdptr);
}
+inline uint32_t soc_ifc_mbox_dir_write_single(uint32_t wrptr, uint32_t wrdata) {
+ lsu_write_32(0x30000000 + wrptr, wrdata);
+}
void soc_ifc_clear_execute_reg();
uint8_t soc_ifc_chk_execute_uc();
void soc_ifc_set_mbox_status_field(enum mbox_status_e field);
void soc_ifc_set_flow_status_field(uint32_t field);
void soc_ifc_clr_flow_status_field(uint32_t field);
-void soc_ifc_set_fw_update_reset();
+void soc_ifc_set_fw_update_reset(uint8_t wait_cycles);
inline void soc_ifc_set_iccm_lock() {
lsu_write_32((CLP_SOC_IFC_REG_INTERNAL_ICCM_LOCK), SOC_IFC_REG_INTERNAL_ICCM_LOCK_LOCK_MASK);
}
diff --git a/src/integration/test_suites/smoke_test_cg_wdt/smoke_test_cg_wdt.c b/src/integration/test_suites/smoke_test_cg_wdt/smoke_test_cg_wdt.c
index b05ba541f..ecbc2b28d 100644
--- a/src/integration/test_suites/smoke_test_cg_wdt/smoke_test_cg_wdt.c
+++ b/src/integration/test_suites/smoke_test_cg_wdt/smoke_test_cg_wdt.c
@@ -156,6 +156,19 @@ void main() {
VPRINTF(LOW, "Debug mode unlocked\n====================\n");
SEND_STDOUT_CTRL(0xfa);
+ for (int i = 0; i < 1000; i++); //sleep
+
+ //Issue warm reset to capture debug mode
+ rst_count++;
+ SEND_STDOUT_CTRL(0xf6);
+ }
+ else if (rst_count == 1) {
+
+ rst_count++;
+ SEND_STDOUT_CTRL(0xf6);
+ }
+ else if (rst_count == 2) {
+
set_mit0_and_halt_core(mitb0, mie_timer0_ext_int_en);
//Disable ss tran
@@ -168,7 +181,7 @@ void main() {
rst_count++;
SEND_STDOUT_CTRL(0xf6);
}
- else if(rst_count == 1) {
+ else if(rst_count == 3) {
//Enable internal timer0
__asm__ volatile ("csrwi %0, %1" \
: /* output: none */ \
diff --git a/src/integration/test_suites/smoke_test_zeroize_crypto/caliptra_isr.h b/src/integration/test_suites/smoke_test_zeroize_crypto/caliptra_isr.h
new file mode 100644
index 000000000..8f5779e04
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_zeroize_crypto/caliptra_isr.h
@@ -0,0 +1,247 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// ---------------------------------------------------------------------
+// File: caliptra_isr.h
+// Description:
+// Provides function declarations for use by external test files, so
+// that the ISR functionality may behave like a library.
+// TODO:
+// This header file includes inline function definitions for event and
+// test specific interrupt service behavior, so it should be copied and
+// modified for each test.
+// ---------------------------------------------------------------------
+
+#ifndef CALIPTRA_ISR_H
+ #define CALIPTRA_ISR_H
+
+#define EN_ISR_PRINTS 1
+
+#include "caliptra_defines.h"
+#include
+#include "printf.h"
+
+/* --------------- symbols/typedefs --------------- */
+typedef struct {
+ uint32_t doe_error;
+ uint32_t doe_notif;
+ uint32_t ecc_error;
+ uint32_t ecc_notif;
+ uint32_t hmac_error;
+ uint32_t hmac_notif;
+ uint32_t kv_error;
+ uint32_t kv_notif;
+ uint32_t sha512_error;
+ uint32_t sha512_notif;
+ uint32_t sha256_error;
+ uint32_t sha256_notif;
+ uint32_t qspi_error;
+ uint32_t qspi_notif;
+ uint32_t uart_error;
+ uint32_t uart_notif;
+ uint32_t i3c_error;
+ uint32_t i3c_notif;
+ uint32_t soc_ifc_error;
+ uint32_t soc_ifc_notif;
+ uint32_t sha512_acc_error;
+ uint32_t sha512_acc_notif;
+} caliptra_intr_received_s;
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
+
+//////////////////////////////////////////////////////////////////////////////
+// Function Declarations
+//
+
+// Performs all the CSR setup to configure and enable vectored external interrupts
+void init_interrupts(void);
+
+// These inline functions are used to insert event-specific functionality into the
+// otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr"
+inline void service_doe_error_intr() {return;}
+inline void service_doe_notif_intr() {
+ uint32_t * reg = (uint32_t *) (CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+ uint32_t sts = *reg;
+ /* Write 1 to Clear the pending interrupt */
+ if (sts & DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+ *reg = DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+ cptra_intr_rcv.doe_notif |= DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+ }
+ if (sts == 0) {
+ VPRINTF(ERROR,"bad doe_notif_intr sts:%x\n", sts);
+ SEND_STDOUT_CTRL(0x1);
+ while(1);
+ }
+}
+
+inline void service_ecc_error_intr() {return;}
+inline void service_ecc_notif_intr() {
+ uint32_t * reg = (uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+ uint32_t sts = *reg;
+ /* Write 1 to Clear the pending interrupt */
+ if (sts & ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+ *reg = ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+ cptra_intr_rcv.ecc_notif |= ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+ }
+ if (sts == 0) {
+ VPRINTF(ERROR,"bad ecc_notif_intr sts:%x\n", sts);
+ SEND_STDOUT_CTRL(0x1);
+ while(1);
+ }
+}
+
+inline void service_hmac_error_intr() {return;}
+inline void service_hmac_notif_intr() {
+ uint32_t * reg = (uint32_t *) (CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+ uint32_t sts = *reg;
+ /* Write 1 to Clear the pending interrupt */
+ if (sts & HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+ *reg = HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+ cptra_intr_rcv.hmac_notif |= HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+ }
+ if (sts == 0) {
+ VPRINTF(ERROR,"bad hmac_notif_intr sts:%x\n", sts);
+ SEND_STDOUT_CTRL(0x1);
+ while(1);
+ }
+}
+
+inline void service_kv_error_intr() {return;}
+inline void service_kv_notif_intr() {return;}
+inline void service_sha512_error_intr() {return;}
+inline void service_sha512_notif_intr() {
+ uint32_t * reg = (uint32_t *) (CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+ uint32_t sts = *reg;
+ /* Write 1 to Clear the pending interrupt */
+ if (sts & SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+ *reg = SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+ cptra_intr_rcv.sha512_notif |= SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+ }
+ if (sts == 0) {
+ VPRINTF(ERROR,"bad sha512_notif_intr sts:%x\n", sts);
+ SEND_STDOUT_CTRL(0x1);
+ while(1);
+ }
+}
+
+inline void service_sha256_error_intr() {return;}
+inline void service_sha256_notif_intr() {
+ uint32_t * reg = (uint32_t *) (CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+ uint32_t sts = *reg;
+ /* Write 1 to Clear the pending interrupt */
+ if (sts & SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+ *reg = SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+ cptra_intr_rcv.sha256_notif |= SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+ }
+ if (sts == 0) {
+ VPRINTF(ERROR,"bad sha256_notif_intr sts:%x\n", sts);
+ SEND_STDOUT_CTRL(0x1);
+ while(1);
+ }
+}
+
+inline void service_qspi_error_intr() {return;}
+inline void service_qspi_notif_intr() {return;}
+inline void service_uart_error_intr() {return;}
+inline void service_uart_notif_intr() {return;}
+inline void service_i3c_error_intr() {return;}
+inline void service_i3c_notif_intr() {return;}
+
+inline void service_soc_ifc_error_intr() {
+ uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+ uint32_t sts = *reg;
+ /* Write 1 to Clear the pending interrupt */
+ if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
+ *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+ cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+ }
+ if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) {
+ *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+ cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+ }
+ if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
+ *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+ cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+ }
+ if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK) {
+ *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+ cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+ }
+ if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK) {
+ *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+ cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+ }
+ if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) {
+ *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+ cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+ }
+ if (sts == 0) {
+ VPRINTF(ERROR,"bad soc_ifc_error_intr sts:%x\n", sts);
+ SEND_STDOUT_CTRL(0x1);
+ while(1);
+ }
+}
+
+inline void service_soc_ifc_notif_intr () {
+ uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+ uint32_t sts = *reg;
+ /* Write 1 to Clear the pending interrupt */
+ if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
+ *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+ cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+ }
+ if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK) {
+ *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+ cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+ }
+ if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+ *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+ cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+ }
+ if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+ *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+ cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+ }
+ if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+ *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+ cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+ }
+ if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+ *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+ cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+ }
+ if (sts == 0) {
+ VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
+ SEND_STDOUT_CTRL(0x1);
+ while(1);
+ }
+}
+
+inline void service_sha512_acc_error_intr() {return;}
+inline void service_sha512_acc_notif_intr() {
+ uint32_t * reg = (uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+ uint32_t sts = *reg;
+ /* Write 1 to Clear the pending interrupt */
+ if (sts & SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+ *reg = SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+ cptra_intr_rcv.sha512_acc_notif |= SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+ }
+ if (sts == 0) {
+ VPRINTF(ERROR,"bad sha512_acc_notif_intr sts:%x\n", sts);
+ SEND_STDOUT_CTRL(0x1);
+ while(1);
+ }
+}
+
+
+#endif //CALIPTRA_ISR_H
diff --git a/src/integration/test_suites/smoke_test_zeroize_crypto/smoke_test_zeroize_crypto.c b/src/integration/test_suites/smoke_test_zeroize_crypto/smoke_test_zeroize_crypto.c
new file mode 100644
index 000000000..5d2305faf
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_zeroize_crypto/smoke_test_zeroize_crypto.c
@@ -0,0 +1,203 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+
+#include "caliptra_defines.h"
+#include "caliptra_isr.h"
+#include "riscv_hw_if.h"
+#include "riscv-csr.h"
+#include
+#include
+#include
+#include "printf.h"
+#include "hmac.h"
+
+volatile char* stdout = (char *)STDOUT;
+volatile uint32_t intr_count = 0;
+
+#ifdef CPT_VERBOSITY
+ enum printf_verbosity verbosity_g = CPT_VERBOSITY;
+#else
+ enum printf_verbosity verbosity_g = LOW;
+#endif
+
+volatile caliptra_intr_received_s cptra_intr_rcv = {
+ .doe_error = 0,
+ .doe_notif = 0,
+ .ecc_error = 0,
+ .ecc_notif = 0,
+ .hmac_error = 0,
+ .hmac_notif = 0,
+ .kv_error = 0,
+ .kv_notif = 0,
+ .sha512_error = 0,
+ .sha512_notif = 0,
+ .sha256_error = 0,
+ .sha256_notif = 0,
+ .qspi_error = 0,
+ .qspi_notif = 0,
+ .uart_error = 0,
+ .uart_notif = 0,
+ .i3c_error = 0,
+ .i3c_notif = 0,
+ .soc_ifc_error = 0,
+ .soc_ifc_notif = 0,
+ .sha512_acc_error = 0,
+ .sha512_acc_notif = 0,
+};
+
+
+/* HMAC384 test vector
+ KEY = 0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b
+ BLOCK = 4869205468657265800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000440
+ LFSR_SEED = C8F518D4F3AA1BD46ED56C1C3C9E16FB800AF504
+ TAG = b6a8d5636f5c6a7224f9977dcf7ee6c7fb6d0c48cbdee9737a959796489bddbc4c5df61d5b3297b4fb68dab9f1b582c2
+*/
+
+
+
+
+void main() {
+ printf("----------------------------------\n");
+ printf(" Smoke Test With Crypto Zeroize !!\n");
+ printf("----------------------------------\n");
+
+ //Call interrupt init
+ init_interrupts();
+
+ uint32_t block[32] = {0x48692054,
+ 0x68657265,
+ 0x80000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000440};
+
+ //this is a random lfsr_seed 160-bit
+ uint32_t lfsr_seed_data[5] = {0xC8F518D4,
+ 0xF3AA1BD4,
+ 0x6ED56C1C,
+ 0x3C9E16FB,
+ 0x800AF504};
+
+ uint32_t expected_tag[12] = {0xb6a8d563,
+ 0x6f5c6a72,
+ 0x24f9977d,
+ 0xcf7ee6c7,
+ 0xfb6d0c48,
+ 0xcbdee973,
+ 0x7a959796,
+ 0x489bddbc,
+ 0x4c5df61d,
+ 0x5b3297b4,
+ 0xfb68dab9,
+ 0xf1b582c2};
+
+
+ uint8_t hmackey_kv_id = 0x2;
+ uint8_t tag_kv_id = 0x0;
+ uint8_t offset;
+ volatile uint32_t * reg_ptr;
+ uint8_t fail_cmd = 0x1;
+ uint32_t check_data;
+
+ //inject hmac_key to kv key reg (in RTL)
+ uint8_t key_inject_cmd = 0xa0 + (hmackey_kv_id & 0x7);
+ printf("%c", key_inject_cmd);
+
+ // wait for HMAC to be ready
+ while((lsu_read_32(CLP_HMAC_REG_HMAC384_STATUS) & HMAC_REG_HMAC384_STATUS_READY_MASK) == 0);
+
+
+ // Program KEY Read with 12 dwords from key_kv_id
+ lsu_write_32(CLP_HMAC_REG_HMAC384_KV_RD_KEY_CTRL, HMAC_REG_HMAC384_KV_RD_KEY_CTRL_READ_EN_MASK |
+ ((hmackey_kv_id << HMAC_REG_HMAC384_KV_RD_KEY_CTRL_READ_ENTRY_LOW) & HMAC_REG_HMAC384_KV_RD_KEY_CTRL_READ_ENTRY_MASK));
+
+ // Check that HMAC KEY is loaded
+ while((lsu_read_32(CLP_HMAC_REG_HMAC384_KV_RD_KEY_STATUS) & HMAC_REG_HMAC384_KV_RD_KEY_STATUS_VALID_MASK) == 0);
+
+
+
+ reg_ptr = (uint32_t*) CLP_HMAC_REG_HMAC384_BLOCK_0;
+ offset = 0;
+ while (reg_ptr <= (uint32_t*) CLP_HMAC_REG_HMAC384_BLOCK_31) {
+ *reg_ptr++ = block[offset++];
+ }
+
+
+ // Program LFSR_SEED
+ reg_ptr = (uint32_t*) CLP_HMAC_REG_HMAC384_LFSR_SEED_0;
+ offset = 0;
+ while (reg_ptr <= (uint32_t*) CLP_HMAC_REG_HMAC384_LFSR_SEED_4) {
+ *reg_ptr++ = lfsr_seed_data[offset++];
+ }
+
+ // if we want to store the results into kv
+ // set tag DEST to write
+
+ lsu_write_32(CLP_HMAC_REG_HMAC384_KV_WR_CTRL, HMAC_REG_HMAC384_KV_WR_CTRL_WRITE_EN_MASK |
+ HMAC_REG_HMAC384_KV_WR_CTRL_HMAC_KEY_DEST_VALID_MASK |
+ HMAC_REG_HMAC384_KV_WR_CTRL_HMAC_BLOCK_DEST_VALID_MASK|
+ HMAC_REG_HMAC384_KV_WR_CTRL_SHA_BLOCK_DEST_VALID_MASK |
+ HMAC_REG_HMAC384_KV_WR_CTRL_ECC_PKEY_DEST_VALID_MASK |
+ HMAC_REG_HMAC384_KV_WR_CTRL_ECC_SEED_DEST_VALID_MASK |
+ ((tag_kv_id << HMAC_REG_HMAC384_KV_WR_CTRL_WRITE_ENTRY_LOW) & HMAC_REG_HMAC384_KV_WR_CTRL_WRITE_ENTRY_MASK));
+
+
+ //inject zeroize command (in RTL)
+ SEND_STDOUT_CTRL(0x99);
+
+ // Enable HMAC core
+ lsu_write_32(CLP_HMAC_REG_HMAC384_CTRL, HMAC_REG_HMAC384_CTRL_INIT_MASK);
+
+ // wait for HMAC to be ready
+ while((lsu_read_32(CLP_HMAC_REG_HMAC384_STATUS) & HMAC_REG_HMAC384_STATUS_READY_MASK) == 0);
+
+ // check that dest valid bits are 0 since the key generation was interrupted
+ check_data = lsu_read_32(CLP_KV_REG_KEY_CTRL_0);
+ if ((check_data & (KV_REG_KEY_CTRL_0_DEST_VALID_MASK)) != 0) {
+ VPRINTF(ERROR, "ERROR: Dest valid mismatch actual (0x%x) expected (0x00000000)\n", check_data);
+ SEND_STDOUT_CTRL(0x1);
+ while(1);
+ } else {
+ SEND_STDOUT_CTRL(0xff); //End the test
+ }
+
+
+}
diff --git a/src/integration/test_suites/smoke_test_zeroize_crypto/smoke_test_zeroize_crypto.yml b/src/integration/test_suites/smoke_test_zeroize_crypto/smoke_test_zeroize_crypto.yml
new file mode 100644
index 000000000..fe168f04a
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_zeroize_crypto/smoke_test_zeroize_crypto.yml
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+---
+seed: 1
+testname: smoke_test_zeroize_crypto
\ No newline at end of file
diff --git a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/caliptra_top_sequences_pkg.sv b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/caliptra_top_sequences_pkg.sv
index b045cc380..e890eda40 100644
--- a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/caliptra_top_sequences_pkg.sv
+++ b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/caliptra_top_sequences_pkg.sv
@@ -73,6 +73,7 @@ package caliptra_top_sequences_pkg;
`include "src/caliptra_top_cmdline_sequence.svh"
`include "src/caliptra_top_rom_sequence.svh"
`include "src/caliptra_top_wdt_sequence.svh"
+ `include "src/caliptra_top_wdt_independent_sequence.svh"
// pragma uvmf custom package_item_additional end
endpackage
diff --git a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_rand_sequence.svh b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_rand_sequence.svh
index 5e6d44890..b09954f4e 100644
--- a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_rand_sequence.svh
+++ b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_rand_sequence.svh
@@ -68,6 +68,9 @@ class caliptra_top_rand_sequence extends caliptra_top_bench_sequence_base;
IDX_SOC_IFC_ENV_MBOX_REG_AXS_INV_SMALL,
IDX_SOC_IFC_ENV_MBOX_REG_AXS_INV_MEDIUM,
IDX_SOC_IFC_ENV_MBOX_REG_AXS_INV_LARGE,
+ IDX_SOC_IFC_ENV_MBOX_2BIT_FLIP_SMALL,
+ IDX_SOC_IFC_ENV_MBOX_2BIT_FLIP_MEDIUM,
+ IDX_SOC_IFC_ENV_MBOX_2BIT_FLIP_LARGE,
IDX_SOC_IFC_ENV_MBOX_MULTI_AGENT,
IDX_SOC_IFC_ENV_RST_WARM,
IDX_SOC_IFC_ENV_RST_COLD,
@@ -109,6 +112,9 @@ class caliptra_top_rand_sequence extends caliptra_top_bench_sequence_base;
IDX_SOC_IFC_ENV_MBOX_REG_AXS_INV_SMALL := 200,
IDX_SOC_IFC_ENV_MBOX_REG_AXS_INV_MEDIUM := 200,
IDX_SOC_IFC_ENV_MBOX_REG_AXS_INV_LARGE := 20,
+ IDX_SOC_IFC_ENV_MBOX_2BIT_FLIP_SMALL := 200,
+ IDX_SOC_IFC_ENV_MBOX_2BIT_FLIP_MEDIUM := 200,
+ IDX_SOC_IFC_ENV_MBOX_2BIT_FLIP_LARGE := 10,
IDX_SOC_IFC_ENV_MBOX_MULTI_AGENT := 200,
IDX_SOC_IFC_ENV_RST_WARM := 100,
IDX_SOC_IFC_ENV_RST_COLD := 100,
@@ -131,6 +137,7 @@ class caliptra_top_rand_sequence extends caliptra_top_bench_sequence_base;
IDX_SOC_IFC_ENV_MBOX_DLEN_OVERFLOW_LARGE,
IDX_SOC_IFC_ENV_MBOX_DLEN_UNDERFLOW_LARGE,
IDX_SOC_IFC_ENV_MBOX_REG_AXS_INV_LARGE,
+ IDX_SOC_IFC_ENV_MBOX_2BIT_FLIP_LARGE,
IDX_SOC_IFC_ENV_MBOX_MULTI_AGENT});
}
constraint iter_count_c {
@@ -238,11 +245,11 @@ class caliptra_top_rand_sequence extends caliptra_top_bench_sequence_base;
// join
fork
forever begin
- if (!std::randomize(mbox_ecc_single_error_burst,mbox_ecc_single_error_delay_clocks) with {mbox_ecc_single_error_burst dist {1 :/ 1000, [2:5] :/ 100, [6:31] :/ 20, [32:131071] :/ 1, [131072:524288] :/ 1};
+ if (!std::randomize(mbox_ecc_single_error_burst,mbox_ecc_single_error_delay_clocks) with {mbox_ecc_single_error_burst dist {1 :/ 10000, [2:5] :/ 2000, [6:31] :/ 200, [32:1023] :/ 10, [1024:131071] :/ 2, [131072:524288] :/ 1};
mbox_ecc_single_error_delay_clocks dist {1 :/ 1, [2:31] :/ 3, [32:127] :/ 5, [128:1023] :/ 3, [1024:131072] :/ 1}; })
`uvm_fatal("CALIPTRA_TOP_RAND_TEST", "Failed to randomize mbox ecc bit flip injection parameters")
else
- `uvm_info("CALIPTRA_TOP_RAND_TEST", $sformatf("Randomized mbox ecc bit flip injection parameters: burst [%0d] delay [%0d clocks]", mbox_ecc_single_error_burst, mbox_ecc_single_error_delay_clocks), UVM_DEBUG)
+ `uvm_info("CALIPTRA_TOP_RAND_TEST", $sformatf("Randomized mbox ecc bit flip injection parameters: burst [%0d] delay [%0d clocks]", mbox_ecc_single_error_burst, mbox_ecc_single_error_delay_clocks), UVM_FULL)
soc_ifc_subenv_soc_ifc_ctrl_agent_config.wait_for_num_clocks(mbox_ecc_single_error_delay_clocks);
`uvm_info("CALIPTRA_TOP_RAND_TEST", $sformatf("Injecting mbox ecc error with burst [%0d]", mbox_ecc_single_error_burst), UVM_DEBUG)
repeat(mbox_ecc_single_error_burst) begin
@@ -346,6 +353,12 @@ class caliptra_top_rand_sequence extends caliptra_top_bench_sequence_base;
obj = soc_ifc_env_mbox_reg_axs_invalid_medium_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
IDX_SOC_IFC_ENV_MBOX_REG_AXS_INV_LARGE:
obj = soc_ifc_env_mbox_reg_axs_invalid_large_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
+ IDX_SOC_IFC_ENV_MBOX_2BIT_FLIP_SMALL:
+ obj = soc_ifc_env_mbox_sram_double_bit_flip_small_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
+ IDX_SOC_IFC_ENV_MBOX_2BIT_FLIP_MEDIUM:
+ obj = soc_ifc_env_mbox_sram_double_bit_flip_medium_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
+ IDX_SOC_IFC_ENV_MBOX_2BIT_FLIP_LARGE:
+ obj = soc_ifc_env_mbox_sram_double_bit_flip_large_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
IDX_SOC_IFC_ENV_MBOX_MULTI_AGENT:
// TODO PAUSER init first?
obj = soc_ifc_env_mbox_rand_multi_agent_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
diff --git a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_wdt_independent_sequence.svh b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_wdt_independent_sequence.svh
new file mode 100644
index 000000000..426616a3a
--- /dev/null
+++ b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_wdt_independent_sequence.svh
@@ -0,0 +1,160 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: This file contains the top level sequence used in caliptra_top_wdt_test.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+class caliptra_top_wdt_independent_sequence extends caliptra_top_bench_sequence_base;
+
+ `uvm_object_utils( caliptra_top_wdt_independent_sequence );
+
+ rand soc_ifc_env_bringup_sequence_t soc_ifc_env_bringup_seq;
+ rand soc_ifc_env_pauser_init_sequence_t soc_ifc_env_pauser_init_seq;
+ rand soc_ifc_env_mbox_real_fw_sequence_t soc_ifc_env_mbox_fmc_seq;
+ rand soc_ifc_env_mbox_real_fw_sequence_t soc_ifc_env_mbox_rt_seq;
+ rand soc_ifc_env_reset_warm_sequence_t soc_ifc_env_reset_warm_seq;
+ rand soc_ifc_env_reset_cold_sequence_t soc_ifc_env_reset_cold_seq;
+ rand soc_ifc_env_cptra_wdt_independent_sequence_t soc_ifc_env_wdt_indep_seq;
+ rand soc_ifc_env_cptra_wdt_cascade_sequence_t soc_ifc_env_wdt_cascade_seq;
+ // Local handle to register model for convenience
+ soc_ifc_reg_model_top reg_model;
+
+
+ rand int iteration_count;
+ int sts_rsp_count = 0;
+ int rsp_count = 0;
+
+
+ function new(string name = "" );
+ super.new(name);
+ reg_model = top_configuration.soc_ifc_subenv_config.soc_ifc_rm;
+ endfunction
+
+ // ****************************************************************************
+ virtual task run_firmware_init(soc_ifc_env_mbox_real_fw_sequence_t fmc_seq, soc_ifc_env_mbox_real_fw_sequence_t rt_seq);
+ bit ready_for_fw = 0;
+ bit ready_for_rt = 0;
+ while (!ready_for_fw) begin
+ while(!sts_rsp_count)soc_ifc_subenv_soc_ifc_ctrl_agent_config.wait_for_num_clocks(1); // Wait for new status updates
+ `uvm_info("CALIPTRA_TOP_WDT_INDEP_TEST", "Observed status response, checking contents", UVM_DEBUG)
+ sts_rsp_count = 0; // We only care about the latest rsp, so even if count > 1, reset back to 0
+ ready_for_fw = soc_ifc_subenv_soc_ifc_status_agent_responder_seq.rsp.ready_for_fw_push;
+ end
+ if (!fmc_seq.randomize() with { fmc_seq.mbox_op_rand.cmd == mbox_cmd_e'(MBOX_CMD_FMC_UPDATE); })
+ `uvm_fatal("CALIPTRA_TOP_WDT_INDEP_TEST", "caliptra_top_wdt_independent_sequence::body() - fmc_seq randomization failed")
+ fmc_seq.start(top_configuration.soc_ifc_subenv_config.vsqr);
+ if (!rt_seq.randomize() with { rt_seq.mbox_op_rand.cmd == mbox_cmd_e'(MBOX_CMD_RT_UPDATE); })
+ `uvm_fatal("CALIPTRA_TOP_WDT_INDEP_TEST", "caliptra_top_wdt_independent_sequence::body() - rt_seq randomization failed")
+ rt_seq.start(top_configuration.soc_ifc_subenv_config.vsqr);
+
+ // Wait for RT image to set the ready_for_rt bit
+ while (!ready_for_rt) begin
+ while(!sts_rsp_count)soc_ifc_subenv_soc_ifc_ctrl_agent_config.wait_for_num_clocks(1); // Wait for new status updates
+ `uvm_info("CALIPTRA_TOP_WDT_INDEP_TEST", "Observed status response, checking contents", UVM_DEBUG)
+ sts_rsp_count = 0; // We only care about the latest rsp, so even if count > 1, reset back to 0
+ ready_for_rt = soc_ifc_subenv_soc_ifc_status_agent_responder_seq.rsp.ready_for_runtime;
+ end
+ endtask
+
+ // ****************************************************************************
+ virtual task body();
+ // pragma uvmf custom body begin
+ // Construct sequences here
+ bit pauser_valid_initialized = 1'b0;
+ uvm_object obj;
+ int ii;
+ bit nmi_intr;
+ bit hw_error_fatal;
+ uvm_status_e reg_sts;
+ uvm_reg_data_t wdt_status_data;
+
+ caliptra_top_env_seq = caliptra_top_env_sequence_base_t::type_id::create("caliptra_top_env_seq");
+ soc_ifc_env_bringup_seq = soc_ifc_env_bringup_sequence_t::type_id::create("soc_ifc_env_bringup_seq");
+ soc_ifc_env_pauser_init_seq = soc_ifc_env_pauser_init_sequence_t::type_id::create("soc_ifc_env_pauser_init_seq");
+ soc_ifc_env_mbox_fmc_seq = soc_ifc_env_mbox_real_fw_sequence_t::type_id::create("soc_ifc_env_mbox_fmc_seq");
+ soc_ifc_env_mbox_rt_seq = soc_ifc_env_mbox_real_fw_sequence_t::type_id::create("soc_ifc_env_mbox_rt_seq");
+ soc_ifc_env_reset_warm_seq = soc_ifc_env_reset_warm_sequence_t::type_id::create("soc_ifc_env_reset_warm_seq");
+ soc_ifc_env_reset_cold_seq = soc_ifc_env_reset_cold_sequence_t::type_id::create("soc_ifc_env_reset_cold_seq");
+ soc_ifc_env_wdt_indep_seq = soc_ifc_env_cptra_wdt_independent_sequence_t::type_id::create("soc_ifc_env_wdt_indep_seq");
+ soc_ifc_env_wdt_cascade_seq = soc_ifc_env_cptra_wdt_cascade_sequence_t::type_id::create("soc_ifc_env_wdt_cascade_seq");
+
+ soc_ifc_subenv_soc_ifc_ctrl_agent_random_seq = soc_ifc_subenv_soc_ifc_ctrl_agent_random_seq_t::type_id::create("soc_ifc_subenv_soc_ifc_ctrl_agent_random_seq");
+ soc_ifc_subenv_soc_ifc_status_agent_responder_seq = soc_ifc_subenv_soc_ifc_status_agent_responder_seq_t::type_id::create("soc_ifc_subenv_soc_ifc_status_agent_responder_seq");
+ soc_ifc_subenv_mbox_sram_agent_responder_seq = soc_ifc_subenv_mbox_sram_agent_responder_seq_t::type_id::create("soc_ifc_subenv_mbox_sram_agent_responder_seq");
+
+ // Handle to the responder sequence for getting response transactions
+ soc_ifc_env_bringup_seq.soc_ifc_status_agent_rsp_seq = soc_ifc_subenv_soc_ifc_status_agent_responder_seq;
+ soc_ifc_env_pauser_init_seq.soc_ifc_status_agent_rsp_seq = soc_ifc_subenv_soc_ifc_status_agent_responder_seq;
+ soc_ifc_env_mbox_fmc_seq.soc_ifc_status_agent_rsp_seq = soc_ifc_subenv_soc_ifc_status_agent_responder_seq;
+ soc_ifc_env_mbox_rt_seq.soc_ifc_status_agent_rsp_seq = soc_ifc_subenv_soc_ifc_status_agent_responder_seq;
+ soc_ifc_env_reset_warm_seq.soc_ifc_status_agent_rsp_seq = soc_ifc_subenv_soc_ifc_status_agent_responder_seq;
+ soc_ifc_env_reset_cold_seq.soc_ifc_status_agent_rsp_seq = soc_ifc_subenv_soc_ifc_status_agent_responder_seq;
+ soc_ifc_env_wdt_indep_seq.soc_ifc_status_agent_rsp_seq = soc_ifc_subenv_soc_ifc_status_agent_responder_seq;
+ soc_ifc_env_wdt_cascade_seq.soc_ifc_status_agent_rsp_seq = soc_ifc_subenv_soc_ifc_status_agent_responder_seq;
+
+ reg_model.reset();
+ // Start RESPONDER sequences here
+ fork
+ soc_ifc_subenv_soc_ifc_status_agent_responder_seq.start(soc_ifc_subenv_soc_ifc_status_agent_sequencer);
+ soc_ifc_subenv_mbox_sram_agent_responder_seq.start(soc_ifc_subenv_mbox_sram_agent_sequencer);
+ join_none
+
+ fork
+ forever @(soc_ifc_subenv_soc_ifc_status_agent_responder_seq.new_rsp) begin
+ sts_rsp_count++;
+ rsp_count++;
+ end
+ join_none
+
+ if(!soc_ifc_env_bringup_seq.randomize())
+ `uvm_fatal("CALIPTRA_TOP_WDT_INDEP_TEST", "caliptra_top_wdt_independent_sequence::body() - soc_ifc_env_bringup_seq randomization failed")
+ soc_ifc_env_bringup_seq.start(top_configuration.soc_ifc_subenv_config.vsqr);
+
+ `uvm_info("CALIPTRA_TOP_BRINGUP", "SoC completed poweron and observed reset deassertion to system", UVM_LOW)
+
+ run_firmware_init(soc_ifc_env_mbox_fmc_seq,soc_ifc_env_mbox_rt_seq);
+
+ soc_ifc_env_wdt_indep_seq.start(top_configuration.soc_ifc_subenv_config.vsqr);
+
+ // UVMF_CHANGE_ME : Extend the simulation XXX number of clocks after
+ // the last sequence to allow for the last sequence item to flow
+ // through the design.
+ fork
+ soc_ifc_subenv_soc_ifc_ctrl_agent_config.wait_for_num_clocks(10000);
+ soc_ifc_subenv_cptra_ctrl_agent_config.wait_for_num_clocks(10000);
+ soc_ifc_subenv_soc_ifc_status_agent_config.wait_for_num_clocks(10000);
+ soc_ifc_subenv_cptra_status_agent_config.wait_for_num_clocks(10000);
+ soc_ifc_subenv_mbox_sram_agent_config.wait_for_num_clocks(10000);
+ join
+
+ // pragma uvmf custom body end
+ endtask
+
+endclass
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_wdt_sequence.svh b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_wdt_sequence.svh
index 4f38ab7d5..a06e803c8 100644
--- a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_wdt_sequence.svh
+++ b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_wdt_sequence.svh
@@ -37,6 +37,8 @@ class caliptra_top_wdt_sequence extends caliptra_top_bench_sequence_base;
rand soc_ifc_env_mbox_real_fw_sequence_t soc_ifc_env_mbox_rt_seq;
rand soc_ifc_env_reset_warm_sequence_t soc_ifc_env_reset_warm_seq;
rand soc_ifc_env_reset_cold_sequence_t soc_ifc_env_reset_cold_seq;
+ rand soc_ifc_env_cptra_wdt_independent_sequence_t soc_ifc_env_wdt_indep_seq;
+ rand soc_ifc_env_cptra_wdt_cascade_sequence_t soc_ifc_env_wdt_cascade_seq;
// Local handle to register model for convenience
soc_ifc_reg_model_top reg_model;
@@ -96,6 +98,8 @@ class caliptra_top_wdt_sequence extends caliptra_top_bench_sequence_base;
soc_ifc_env_mbox_rt_seq = soc_ifc_env_mbox_real_fw_sequence_t::type_id::create("soc_ifc_env_mbox_rt_seq");
soc_ifc_env_reset_warm_seq = soc_ifc_env_reset_warm_sequence_t::type_id::create("soc_ifc_env_reset_warm_seq");
soc_ifc_env_reset_cold_seq = soc_ifc_env_reset_cold_sequence_t::type_id::create("soc_ifc_env_reset_cold_seq");
+ soc_ifc_env_wdt_indep_seq = soc_ifc_env_cptra_wdt_independent_sequence_t::type_id::create("soc_ifc_env_wdt_indep_seq");
+ soc_ifc_env_wdt_cascade_seq = soc_ifc_env_cptra_wdt_cascade_sequence_t::type_id::create("soc_ifc_env_wdt_cascade_seq");
soc_ifc_subenv_soc_ifc_ctrl_agent_random_seq = soc_ifc_subenv_soc_ifc_ctrl_agent_random_seq_t::type_id::create("soc_ifc_subenv_soc_ifc_ctrl_agent_random_seq");
soc_ifc_subenv_soc_ifc_status_agent_responder_seq = soc_ifc_subenv_soc_ifc_status_agent_responder_seq_t::type_id::create("soc_ifc_subenv_soc_ifc_status_agent_responder_seq");
@@ -108,6 +112,8 @@ class caliptra_top_wdt_sequence extends caliptra_top_bench_sequence_base;
soc_ifc_env_mbox_rt_seq.soc_ifc_status_agent_rsp_seq = soc_ifc_subenv_soc_ifc_status_agent_responder_seq;
soc_ifc_env_reset_warm_seq.soc_ifc_status_agent_rsp_seq = soc_ifc_subenv_soc_ifc_status_agent_responder_seq;
soc_ifc_env_reset_cold_seq.soc_ifc_status_agent_rsp_seq = soc_ifc_subenv_soc_ifc_status_agent_responder_seq;
+ soc_ifc_env_wdt_indep_seq.soc_ifc_status_agent_rsp_seq = soc_ifc_subenv_soc_ifc_status_agent_responder_seq;
+ soc_ifc_env_wdt_cascade_seq.soc_ifc_status_agent_rsp_seq = soc_ifc_subenv_soc_ifc_status_agent_responder_seq;
reg_model.reset();
// Start RESPONDER sequences here
@@ -131,33 +137,32 @@ class caliptra_top_wdt_sequence extends caliptra_top_bench_sequence_base;
run_firmware_init(soc_ifc_env_mbox_fmc_seq,soc_ifc_env_mbox_rt_seq);
- // //--------------------------------
- // //Wait for NMI to occur - TODO
- // `uvm_info("KNU", $sformatf("FW init done, hw_error_fatal = %0d", hw_error_fatal),UVM_MEDIUM);
- // while (!hw_error_fatal) begin
- // `uvm_info("KNU", "Inside while loop",UVM_MEDIUM);
- // while(!rsp_count)soc_ifc_subenv_soc_ifc_ctrl_agent_config.wait_for_num_clocks(1); // Wait for new status updates
- // `uvm_info("CALIPTRA_TOP_WDT_TEST", "Observed status response, checking contents", UVM_MEDIUM)
- // `uvm_info("CALIPTRA_TOP_WDT_TEST", soc_ifc_subenv_soc_ifc_status_agent_responder_seq.rsp.convert2string(), UVM_MEDIUM)
- // // `uvm_info("CALIPTRA_TOP_WDT_TEST", $sformatf("response error fatal = %0d",soc_ifc_subenv_soc_ifc_status_agent_responder_seq.rsp.cptra_error_fatal_intr_pending), UVM_MEDIUM)
- // rsp_count = 0; // We only care about the latest rsp, so even if count > 1, reset back to 0
- // hw_error_fatal = soc_ifc_subenv_soc_ifc_status_agent_responder_seq.rsp.cptra_error_fatal_intr_pending;
- // end
- // `uvm_info("KNU", $sformatf("Outside while loop, hw_error_fatal = %h", hw_error_fatal),UVM_MEDIUM);
-
- // // //TODO: add APB seq to read hw_error_fatal reg to see if it's NMI or not
- // `uvm_info("CALIPTRA_TOP_WDT_TEST", "Encountered NMI, issuing reset", UVM_MEDIUM);
- // //soc_ifc_env_bringup_seq.start(top_configuration.soc_ifc_subenv_config.vsqr);
- // reg_model.reset(); //TODO needed?
- // // if (!soc_ifc_env_reset_cold_seq.randomize())
- // // `uvm_fatal("CALIPTRA_TOP_WDT_TEST", "caliptra_top_wdt_sequence::body() - soc_ifc_env_bringup_seq randomization failed")
- // // soc_ifc_env_reset_cold_seq.start(top_configuration.soc_ifc_subenv_config.vsqr);
- // // reg_model.reset(); //TODO needed?
- // if(!soc_ifc_env_bringup_seq.randomize())
- // `uvm_fatal("CALIPTRA_TOP_WDT_TEST", "caliptra_top_wdt_sequence::body() - soc_ifc_env_bringup_seq randomization failed")
- // soc_ifc_env_bringup_seq.start(top_configuration.soc_ifc_subenv_config.vsqr);
+ soc_ifc_env_wdt_cascade_seq.start(top_configuration.soc_ifc_subenv_config.vsqr);
+
//--------------------------------
-
+ //Wait for NMI to occur
+ while (!hw_error_fatal) begin
+ while(!rsp_count)soc_ifc_subenv_soc_ifc_ctrl_agent_config.wait_for_num_clocks(1); // Wait for new status updates
+ `uvm_info("CALIPTRA_TOP_WDT_TEST", "Observed status response, checking contents", UVM_MEDIUM)
+ `uvm_info("CALIPTRA_TOP_WDT_TEST", soc_ifc_subenv_soc_ifc_status_agent_responder_seq.rsp.convert2string(), UVM_MEDIUM)
+ rsp_count = 0; // We only care about the latest rsp, so even if count > 1, reset back to 0
+ hw_error_fatal = soc_ifc_subenv_soc_ifc_status_agent_responder_seq.rsp.cptra_error_fatal_intr_pending;
+ end
+
+ //Check that NMI bit was set in the fatal error reg
+ if (reg_model.soc_ifc_reg_rm.CPTRA_HW_ERROR_FATAL.nmi_pin.get_mirrored_value()) begin
+ `uvm_info("CALIPTRA_TOP_WDT_TEST", "Encountered NMI, issuing reset", UVM_MEDIUM);
+
+ //Issue warm reset
+ if(!soc_ifc_env_reset_warm_seq.randomize())
+ `uvm_fatal("CALIPTRA_TOP_WDT_TEST", "caliptra_top_wdt_sequence::body() - soc_ifc_env_reset_warm_seq randomization failed")
+ soc_ifc_env_reset_warm_seq.start(top_configuration.soc_ifc_subenv_config.vsqr);
+ // //--------------------------------
+ end
+ else begin
+ `uvm_error("CALIPTRA_TOP_WDT_TEST", "Did not see expected NMI interrupt")
+ end
+
// UVMF_CHANGE_ME : Extend the simulation XXX number of clocks after
// the last sequence to allow for the last sequence item to flow
// through the design.
diff --git a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/testbench/hdl_top.sv b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/testbench/hdl_top.sv
index 6ad20d141..3084672f4 100644
--- a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/testbench/hdl_top.sv
+++ b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/testbench/hdl_top.sv
@@ -178,7 +178,7 @@ import uvmf_base_pkg_hdl::*;
assign uvm_test_top_environment_soc_ifc_subenv_qvip_ahb_lite_slave_subenv_qvip_hdl.default_clk_gen_CLK = clk;
assign uvm_test_top_environment_soc_ifc_subenv_qvip_ahb_lite_slave_subenv_qvip_hdl.default_reset_gen_RESET = caliptra_top_dut.cptra_noncore_rst_b;
assign uvm_test_top_environment_soc_ifc_subenv_qvip_apb5_slave_subenv_qvip_hdl.default_clk_gen_CLK = clk;
- assign uvm_test_top_environment_soc_ifc_subenv_qvip_apb5_slave_subenv_qvip_hdl.default_reset_gen_RESET = soc_ifc_subenv_soc_ifc_ctrl_agent_bus.cptra_rst_b;
+ assign uvm_test_top_environment_soc_ifc_subenv_qvip_apb5_slave_subenv_qvip_hdl.default_reset_gen_RESET = caliptra_top_dut.cptra_noncore_rst_b;
//=========================================================================-
@@ -214,7 +214,7 @@ import uvmf_base_pkg_hdl::*;
.qspi_d_o (/*TODO*/),
.qspi_d_en_o (/*TODO*/),
- .el2_mem_export(el2_mem_export),
+ .el2_mem_export(el2_mem_export.veer_sram_src),
.ready_for_fuses (soc_ifc_subenv_soc_ifc_status_agent_bus.ready_for_fuses ),
.ready_for_fw_push(soc_ifc_subenv_soc_ifc_status_agent_bus.ready_for_fw_push ),
@@ -346,7 +346,7 @@ import uvmf_base_pkg_hdl::*;
.cptra_rst_b(soc_ifc_subenv_soc_ifc_ctrl_agent_bus.cptra_rst_b ),
// Caliptra Memory Export Interface
- .el2_mem_export (el2_mem_export),
+ .el2_mem_export (el2_mem_export.veer_sram_sink),
//SRAM interface for mbox
.mbox_sram_cs (mbox_sram_cs_stub_inactive ),
diff --git a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/caliptra_top_tests_pkg.sv b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/caliptra_top_tests_pkg.sv
index 051084252..751ca96c5 100644
--- a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/caliptra_top_tests_pkg.sv
+++ b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/caliptra_top_tests_pkg.sv
@@ -66,6 +66,7 @@ package caliptra_top_tests_pkg;
`include "src/example_derived_test.svh"
`include "src/caliptra_top_rand_test.svh"
`include "src/caliptra_top_wdt_test.svh"
+ `include "src/caliptra_top_wdt_independent_test.svh"
`include "src/caliptra_top_cmdline_test.svh"
`include "src/caliptra_top_rom_test.svh"
diff --git a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_wdt_independent_test.svh b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_wdt_independent_test.svh
new file mode 100644
index 000000000..b1138994a
--- /dev/null
+++ b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_wdt_independent_test.svh
@@ -0,0 +1,72 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: This test extends test_top and makes
+// changes to test_top using the UVM factory type_override:
+//
+// Test scenario:
+// Randomized activity to Caliptra
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+class caliptra_top_wdt_independent_test extends test_top;
+
+ `uvm_component_utils( caliptra_top_wdt_independent_test );
+
+ function new( string name = "", uvm_component parent = null );
+ super.new( name, parent );
+ endfunction
+
+ virtual function void build_phase(uvm_phase phase);
+ // The factory override below is an example of how to replace the caliptra_top_bench_sequence_base
+ // sequence with the example_derived_test_sequence.
+ caliptra_top_bench_sequence_base::type_id::set_type_override(caliptra_top_wdt_independent_sequence::get_type());
+ // Execute the build_phase of test_top AFTER all factory overrides have been created.
+ super.build_phase(phase);
+ // pragma uvmf custom configuration_settings_post_randomize begin
+ // UVMF_CHANGE_ME Test specific configuration values can be set here.
+ // The configuration structure has already been randomized.
+ // pragma uvmf custom configuration_settings_post_randomize end
+ endfunction
+
+ // FIXME this disables uvm_warning messages! We should fix the warnings, but for
+ // now this reduces sim.log (for regressions) to a manageable level
+ // NOTE: UVM_WARNING now re-enabled, need to clean this up after some regression cycles
+ virtual function void start_of_simulation_phase(uvm_phase phase);
+ super.start_of_simulation_phase(phase);
+ if ($test$plusargs("CLP_REGRESSION")) begin
+ uvm_top.set_report_verbosity_level_hier(UVM_NONE);
+// this.environment.soc_ifc_subenv.soc_ifc_pred.set_report_severity_action(UVM_WARNING,UVM_NO_ACTION);
+// this.environment.soc_ifc_subenv.soc_ifc_sb.set_report_severity_action(UVM_WARNING,UVM_NO_ACTION);
+ // Since en_sb is recently set to 0, this is unavailable and gives null-object
+ //this.environment.soc_ifc_subenv.qvip_apb5_slave_subenv.apb5_master_0.get_analysis_component("checker").set_report_severity_id_action(UVM_WARNING,"scoreboard_debug",UVM_NO_ACTION);
+ end
+ endfunction
+
+endclass
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
+
diff --git a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_wdt_independent_test.yml b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_wdt_independent_test.yml
new file mode 100644
index 000000000..1be3f550b
--- /dev/null
+++ b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_wdt_independent_test.yml
@@ -0,0 +1,6 @@
+---
+# Random seed desired...
+seed: ${PLAYBOOK_RANDOM_SEED}
+plusargs:
+- '+UVM_TESTNAME=caliptra_top_wdt_independent_test'
+testname: caliptra_top_wdt_independent_test
diff --git a/src/libs/rtl/clk_gate.sv b/src/libs/rtl/clk_gate.sv
index 448a03bc6..73e9ba1bd 100644
--- a/src/libs/rtl/clk_gate.sv
+++ b/src/libs/rtl/clk_gate.sv
@@ -18,6 +18,7 @@ module clk_gate (
input logic psel,
input logic clk_gate_en,
input logic rdc_clk_dis,
+ input logic rdc_clk_dis_uc,
input logic cpu_halt_status,
input logic [63:0] generic_input_wires,
input logic cptra_error_fatal,
@@ -25,11 +26,13 @@ module clk_gate (
output logic clk_cg,
output logic soc_ifc_clk_cg,
output logic rdc_clk_cg,
+ output logic uc_clk_cg,
input logic cptra_dmi_reg_en_preQ //JTAG access
);
logic disable_clk;
logic disable_soc_ifc_clk;
+logic disable_uc_clk;
logic [63:0] generic_input_wires_f;
logic change_in_generic_wires;
logic sleep_condition;
@@ -71,6 +74,7 @@ always_comb begin
sleep_condition = (cpu_halt_status && !change_in_generic_wires && !cptra_error_fatal && !cptra_in_debug_scan_mode && !cptra_dmi_reg_en_preQ);
disable_clk = (clk_gate_en && sleep_condition) | rdc_clk_dis;
disable_soc_ifc_clk = (clk_gate_en && (sleep_condition && !psel)) | rdc_clk_dis;
+ disable_uc_clk = (rdc_clk_dis | rdc_clk_dis_uc);
end
@@ -78,10 +82,12 @@ end
`USER_ICG user_icg (.clk(clk), .en(!disable_clk), .clk_cg(clk_cg));
`USER_ICG user_soc_ifc_icg (.clk(clk), .en(!disable_soc_ifc_clk), .clk_cg(soc_ifc_clk_cg));
`USER_ICG user_rdc_icg (.clk(clk), .en(!rdc_clk_dis), .clk_cg(rdc_clk_cg));
+ `USER_ICG user_rdc_uc_icg (.clk(clk), .en(!disable_uc_clk), .clk_cg(uc_clk_cg));
`else
`CALIPTRA_ICG caliptra_icg (.clk(clk), .en(!disable_clk), .clk_cg(clk_cg));
`CALIPTRA_ICG caliptra_soc_ifc_icg (.clk(clk), .en(!disable_soc_ifc_clk), .clk_cg(soc_ifc_clk_cg));
`CALIPTRA_ICG caliptra_rdc_icg (.clk(clk), .en(!rdc_clk_dis), .clk_cg(rdc_clk_cg));
+ `CALIPTRA_ICG caliptra_rdc_uc_icg (.clk(clk), .en(!disable_uc_clk), .clk_cg(uc_clk_cg));
`endif
endmodule
diff --git a/src/riscv_core/veer_el2/rtl/common_defines.sv b/src/riscv_core/veer_el2/rtl/common_defines.sv
index 702abf75b..afcbaa9a1 100644
--- a/src/riscv_core/veer_el2/rtl/common_defines.sv
+++ b/src/riscv_core/veer_el2/rtl/common_defines.sv
@@ -157,9 +157,11 @@
`define RV_LDERR_ROLLBACK 1
`define CPU_TOP `RV_TOP.veer
`define RV_EXT_DATAWIDTH 64
+`ifndef SYNTHESIS
`ifndef VERILATOR
`define RV_ASSERT_ON
`endif
+`endif
`define RV_EXT_ADDRWIDTH 32
`define RV_BTB_ENABLE 1
`define RV_BTB_BTAG_FOLD 0
diff --git a/src/riscv_core/veer_el2/rtl/el2_mem.sv b/src/riscv_core/veer_el2/rtl/el2_mem.sv
index 80e770c5c..605b3120f 100644
--- a/src/riscv_core/veer_el2/rtl/el2_mem.sv
+++ b/src/riscv_core/veer_el2/rtl/el2_mem.sv
@@ -79,7 +79,7 @@ import el2_pkg::*;
output logic [pt.ICACHE_NUM_WAYS-1:0] ic_rd_hit,
output logic ic_tag_perr, // Icache Tag parity error
- el2_mem_if mem_export,
+ el2_mem_if.veer_sram_src mem_export,
input logic scan_mode
@@ -87,13 +87,29 @@ import el2_pkg::*;
);
logic active_clk;
+ el2_mem_if mem_export_local ();
rvoclkhdr active_cg ( .en(1'b1), .l1clk(active_clk), .* );
+ assign mem_export .clk = clk;
+ assign mem_export_local.clk = clk;
+
+ assign mem_export .iccm_clken = mem_export_local.iccm_clken;
+ assign mem_export .iccm_wren_bank = mem_export_local.iccm_wren_bank;
+ assign mem_export .iccm_addr_bank = mem_export_local.iccm_addr_bank;
+ assign mem_export .iccm_bank_wr_data = mem_export_local.iccm_bank_wr_data;
+ assign mem_export_local.iccm_bank_dout = mem_export. iccm_bank_dout;
+
+ assign mem_export .dccm_clken = mem_export_local.dccm_clken;
+ assign mem_export .dccm_wren_bank = mem_export_local.dccm_wren_bank;
+ assign mem_export .dccm_addr_bank = mem_export_local.dccm_addr_bank;
+ assign mem_export .dccm_wr_data_bank = mem_export_local.dccm_wr_data_bank;
+ assign mem_export_local.dccm_bank_dout = mem_export .dccm_bank_dout;
+
// DCCM Instantiation
if (pt.DCCM_ENABLE == 1) begin: Gen_dccm_enable
el2_lsu_dccm_mem #(.pt(pt)) dccm (
.clk_override(dccm_clk_override),
- .dccm_mem_export(mem_export.veer_dccm),
+ .dccm_mem_export(mem_export_local.veer_dccm),
.*
);
end else begin: Gen_dccm_disable
@@ -121,7 +137,7 @@ if (pt.ICCM_ENABLE) begin : iccm
.clk_override(icm_clk_override),
.iccm_rw_addr(iccm_rw_addr[pt.ICCM_BITS-1:1]),
.iccm_rd_data(iccm_rd_data[63:0]),
- .iccm_mem_export(mem_export.veer_iccm)
+ .iccm_mem_export(mem_export_local.veer_iccm)
);
end
else begin
diff --git a/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv b/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv
index 7295a5ffe..cec4d24cf 100755
--- a/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv
+++ b/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv
@@ -319,7 +319,7 @@ import soc_ifc_pkg::*;
input logic [31:4] core_id,
// Caliptra Memory Export Interface
- el2_mem_if el2_mem_export,
+ el2_mem_if.veer_sram_src el2_mem_export,
// Caliptra ECC status signals
output logic cptra_iccm_ecc_single_error,
@@ -710,7 +710,6 @@ import soc_ifc_pkg::*;
.mem_export(el2_mem_export),
.*
);
- assign el2_mem_export.clk = active_l2clk;
// JTAG/DMI instance
diff --git a/src/riscv_core/veer_el2/rtl/lib/el2_mem_if.sv b/src/riscv_core/veer_el2/rtl/lib/el2_mem_if.sv
index 2f6b22a75..1d0a83723 100644
--- a/src/riscv_core/veer_el2/rtl/lib/el2_mem_if.sv
+++ b/src/riscv_core/veer_el2/rtl/lib/el2_mem_if.sv
@@ -85,7 +85,17 @@ modport veer_dccm (
input dccm_bank_dout
);
-modport top (
+modport veer_sram_src (
+ output clk,
+ // ICCM
+ output iccm_clken, iccm_wren_bank, iccm_addr_bank, iccm_bank_wr_data,
+ input iccm_bank_dout,
+ // DCCM
+ output dccm_clken, dccm_wren_bank, dccm_addr_bank, dccm_wr_data_bank,
+ input dccm_bank_dout
+);
+
+modport veer_sram_sink (
input clk,
// ICCM
input iccm_clken, iccm_wren_bank, iccm_addr_bank, iccm_bank_wr_data,
diff --git a/src/soc_ifc/coverage/soc_ifc_cov_if.sv b/src/soc_ifc/coverage/soc_ifc_cov_if.sv
index 8906d1f8a..74d9d4177 100644
--- a/src/soc_ifc/coverage/soc_ifc_cov_if.sv
+++ b/src/soc_ifc/coverage/soc_ifc_cov_if.sv
@@ -333,6 +333,9 @@ interface soc_ifc_cov_if
end
*/
+
+
+
// -------------------------------------------------------------------
// begin SCRIPT_OUTPUT
// -------------------------------------------------------------------
@@ -340,7 +343,7 @@ interface soc_ifc_cov_if
// ------------------- COVERGROUP related signals & assigns -------------------
- logic hit_CPTRA_HW_ERROR_FATAL;
+ logic hit_CPTRA_HW_ERROR_FATAL;
logic [3:0] bus_CPTRA_HW_ERROR_FATAL;
logic [31:0] full_addr_CPTRA_HW_ERROR_FATAL = `CLP_SOC_IFC_REG_CPTRA_HW_ERROR_FATAL;
@@ -434,6 +437,10 @@ interface soc_ifc_cov_if
assign full_addr_CPTRA_TRNG_DATA[10] = `CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_10;
assign full_addr_CPTRA_TRNG_DATA[11] = `CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_11;
+ logic hit_CPTRA_TRNG_CTRL;
+ logic [3:0] bus_CPTRA_TRNG_CTRL;
+ logic [31:0] full_addr_CPTRA_TRNG_CTRL = `CLP_SOC_IFC_REG_CPTRA_TRNG_CTRL;
+
logic hit_CPTRA_TRNG_STATUS;
logic [3:0] bus_CPTRA_TRNG_STATUS;
logic [31:0] full_addr_CPTRA_TRNG_STATUS = `CLP_SOC_IFC_REG_CPTRA_TRNG_STATUS;
@@ -524,6 +531,26 @@ interface soc_ifc_cov_if
logic [3:0] bus_CPTRA_FUSE_PAUSER_LOCK;
logic [31:0] full_addr_CPTRA_FUSE_PAUSER_LOCK = `CLP_SOC_IFC_REG_CPTRA_FUSE_PAUSER_LOCK;
+ logic hit_CPTRA_WDT_CFG[0:1];
+ logic [3:0] bus_CPTRA_WDT_CFG[0:1];
+ logic [31:0] full_addr_CPTRA_WDT_CFG[0:1];
+ assign full_addr_CPTRA_WDT_CFG[0] = `CLP_SOC_IFC_REG_CPTRA_WDT_CFG_0;
+ assign full_addr_CPTRA_WDT_CFG[1] = `CLP_SOC_IFC_REG_CPTRA_WDT_CFG_1;
+
+ logic hit_CPTRA_iTRNG_ENTROPY_CONFIG_0;
+ logic [3:0] bus_CPTRA_iTRNG_ENTROPY_CONFIG_0;
+ logic [31:0] full_addr_CPTRA_iTRNG_ENTROPY_CONFIG_0 = `CLP_SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0;
+
+ logic hit_CPTRA_iTRNG_ENTROPY_CONFIG_1;
+ logic [3:0] bus_CPTRA_iTRNG_ENTROPY_CONFIG_1;
+ logic [31:0] full_addr_CPTRA_iTRNG_ENTROPY_CONFIG_1 = `CLP_SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1;
+
+ logic hit_CPTRA_RSVD_REG[0:1];
+ logic [3:0] bus_CPTRA_RSVD_REG[0:1];
+ logic [31:0] full_addr_CPTRA_RSVD_REG[0:1];
+ assign full_addr_CPTRA_RSVD_REG[0] = `CLP_SOC_IFC_REG_CPTRA_RSVD_REG_0;
+ assign full_addr_CPTRA_RSVD_REG[1] = `CLP_SOC_IFC_REG_CPTRA_RSVD_REG_1;
+
logic hit_fuse_uds_seed[0:11];
logic [3:0] bus_fuse_uds_seed[0:11];
logic [31:0] full_addr_fuse_uds_seed[0:11];
@@ -644,6 +671,18 @@ interface soc_ifc_cov_if
logic [3:0] bus_fuse_life_cycle;
logic [31:0] full_addr_fuse_life_cycle = `CLP_SOC_IFC_REG_FUSE_LIFE_CYCLE;
+ logic hit_fuse_lms_verify;
+ logic [3:0] bus_fuse_lms_verify;
+ logic [31:0] full_addr_fuse_lms_verify = `CLP_SOC_IFC_REG_FUSE_LMS_VERIFY;
+
+ logic hit_fuse_lms_revocation;
+ logic [3:0] bus_fuse_lms_revocation;
+ logic [31:0] full_addr_fuse_lms_revocation = `CLP_SOC_IFC_REG_FUSE_LMS_REVOCATION;
+
+ logic hit_fuse_soc_stepping_id;
+ logic [3:0] bus_fuse_soc_stepping_id;
+ logic [31:0] full_addr_fuse_soc_stepping_id = `CLP_SOC_IFC_REG_FUSE_SOC_STEPPING_ID;
+
logic hit_internal_obf_key[0:7];
logic [3:0] bus_internal_obf_key[0:7];
logic [31:0] full_addr_internal_obf_key[0:7];
@@ -672,6 +711,178 @@ interface soc_ifc_cov_if
logic [3:0] bus_internal_nmi_vector;
logic [31:0] full_addr_internal_nmi_vector = `CLP_SOC_IFC_REG_INTERNAL_NMI_VECTOR;
+ logic hit_internal_hw_error_fatal_mask;
+ logic [3:0] bus_internal_hw_error_fatal_mask;
+ logic [31:0] full_addr_internal_hw_error_fatal_mask = `CLP_SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK;
+
+ logic hit_internal_hw_error_non_fatal_mask;
+ logic [3:0] bus_internal_hw_error_non_fatal_mask;
+ logic [31:0] full_addr_internal_hw_error_non_fatal_mask = `CLP_SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK;
+
+ logic hit_internal_fw_error_fatal_mask;
+ logic [3:0] bus_internal_fw_error_fatal_mask;
+ logic [31:0] full_addr_internal_fw_error_fatal_mask = `CLP_SOC_IFC_REG_INTERNAL_FW_ERROR_FATAL_MASK;
+
+ logic hit_internal_fw_error_non_fatal_mask;
+ logic [3:0] bus_internal_fw_error_non_fatal_mask;
+ logic [31:0] full_addr_internal_fw_error_non_fatal_mask = `CLP_SOC_IFC_REG_INTERNAL_FW_ERROR_NON_FATAL_MASK;
+
+ logic hit_internal_rv_mtime_l;
+ logic [3:0] bus_internal_rv_mtime_l;
+ logic [31:0] full_addr_internal_rv_mtime_l = `CLP_SOC_IFC_REG_INTERNAL_RV_MTIME_L;
+
+ logic hit_internal_rv_mtime_h;
+ logic [3:0] bus_internal_rv_mtime_h;
+ logic [31:0] full_addr_internal_rv_mtime_h = `CLP_SOC_IFC_REG_INTERNAL_RV_MTIME_H;
+
+ logic hit_internal_rv_mtimecmp_l;
+ logic [3:0] bus_internal_rv_mtimecmp_l;
+ logic [31:0] full_addr_internal_rv_mtimecmp_l = `CLP_SOC_IFC_REG_INTERNAL_RV_MTIMECMP_L;
+
+ logic hit_internal_rv_mtimecmp_h;
+ logic [3:0] bus_internal_rv_mtimecmp_h;
+ logic [31:0] full_addr_internal_rv_mtimecmp_h = `CLP_SOC_IFC_REG_INTERNAL_RV_MTIMECMP_H;
+
+ logic hit_intr_brf_global_intr_en_r;
+ logic [3:0] bus_intr_brf_global_intr_en_r;
+ logic [31:0] full_addr_intr_brf_global_intr_en_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R;
+
+ logic hit_intr_brf_error_intr_en_r;
+ logic [3:0] bus_intr_brf_error_intr_en_r;
+ logic [31:0] full_addr_intr_brf_error_intr_en_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R;
+
+ logic hit_intr_brf_notif_intr_en_r;
+ logic [3:0] bus_intr_brf_notif_intr_en_r;
+ logic [31:0] full_addr_intr_brf_notif_intr_en_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R;
+
+ logic hit_intr_brf_error_global_intr_r;
+ logic [3:0] bus_intr_brf_error_global_intr_r;
+ logic [31:0] full_addr_intr_brf_error_global_intr_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R;
+
+ logic hit_intr_brf_notif_global_intr_r;
+ logic [3:0] bus_intr_brf_notif_global_intr_r;
+ logic [31:0] full_addr_intr_brf_notif_global_intr_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R;
+
+ logic hit_intr_brf_error_internal_intr_r;
+ logic [3:0] bus_intr_brf_error_internal_intr_r;
+ logic [31:0] full_addr_intr_brf_error_internal_intr_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R;
+
+ logic hit_intr_brf_notif_internal_intr_r;
+ logic [3:0] bus_intr_brf_notif_internal_intr_r;
+ logic [31:0] full_addr_intr_brf_notif_internal_intr_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R;
+
+ logic hit_intr_brf_error_intr_trig_r;
+ logic [3:0] bus_intr_brf_error_intr_trig_r;
+ logic [31:0] full_addr_intr_brf_error_intr_trig_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R;
+
+ logic hit_intr_brf_notif_intr_trig_r;
+ logic [3:0] bus_intr_brf_notif_intr_trig_r;
+ logic [31:0] full_addr_intr_brf_notif_intr_trig_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R;
+
+ logic hit_intr_brf_error_internal_intr_count_r;
+ logic [3:0] bus_intr_brf_error_internal_intr_count_r;
+ logic [31:0] full_addr_intr_brf_error_internal_intr_count_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_R;
+
+ logic hit_intr_brf_error_inv_dev_intr_count_r;
+ logic [3:0] bus_intr_brf_error_inv_dev_intr_count_r;
+ logic [31:0] full_addr_intr_brf_error_inv_dev_intr_count_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INV_DEV_INTR_COUNT_R;
+
+ logic hit_intr_brf_error_cmd_fail_intr_count_r;
+ logic [3:0] bus_intr_brf_error_cmd_fail_intr_count_r;
+ logic [31:0] full_addr_intr_brf_error_cmd_fail_intr_count_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_CMD_FAIL_INTR_COUNT_R;
+
+ logic hit_intr_brf_error_bad_fuse_intr_count_r;
+ logic [3:0] bus_intr_brf_error_bad_fuse_intr_count_r;
+ logic [31:0] full_addr_intr_brf_error_bad_fuse_intr_count_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_BAD_FUSE_INTR_COUNT_R;
+
+ logic hit_intr_brf_error_iccm_blocked_intr_count_r;
+ logic [3:0] bus_intr_brf_error_iccm_blocked_intr_count_r;
+ logic [31:0] full_addr_intr_brf_error_iccm_blocked_intr_count_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_ICCM_BLOCKED_INTR_COUNT_R;
+
+ logic hit_intr_brf_error_mbox_ecc_unc_intr_count_r;
+ logic [3:0] bus_intr_brf_error_mbox_ecc_unc_intr_count_r;
+ logic [31:0] full_addr_intr_brf_error_mbox_ecc_unc_intr_count_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_MBOX_ECC_UNC_INTR_COUNT_R;
+
+ logic hit_intr_brf_error_wdt_timer1_timeout_intr_count_r;
+ logic [3:0] bus_intr_brf_error_wdt_timer1_timeout_intr_count_r;
+ logic [31:0] full_addr_intr_brf_error_wdt_timer1_timeout_intr_count_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_R;
+
+ logic hit_intr_brf_error_wdt_timer2_timeout_intr_count_r;
+ logic [3:0] bus_intr_brf_error_wdt_timer2_timeout_intr_count_r;
+ logic [31:0] full_addr_intr_brf_error_wdt_timer2_timeout_intr_count_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_R;
+
+ logic hit_intr_brf_notif_cmd_avail_intr_count_r;
+ logic [3:0] bus_intr_brf_notif_cmd_avail_intr_count_r;
+ logic [31:0] full_addr_intr_brf_notif_cmd_avail_intr_count_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_CMD_AVAIL_INTR_COUNT_R;
+
+ logic hit_intr_brf_notif_mbox_ecc_cor_intr_count_r;
+ logic [3:0] bus_intr_brf_notif_mbox_ecc_cor_intr_count_r;
+ logic [31:0] full_addr_intr_brf_notif_mbox_ecc_cor_intr_count_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_R;
+
+ logic hit_intr_brf_notif_debug_locked_intr_count_r;
+ logic [3:0] bus_intr_brf_notif_debug_locked_intr_count_r;
+ logic [31:0] full_addr_intr_brf_notif_debug_locked_intr_count_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_R;
+
+ logic hit_intr_brf_notif_scan_mode_intr_count_r;
+ logic [3:0] bus_intr_brf_notif_scan_mode_intr_count_r;
+ logic [31:0] full_addr_intr_brf_notif_scan_mode_intr_count_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_R;
+
+ logic hit_intr_brf_notif_soc_req_lock_intr_count_r;
+ logic [3:0] bus_intr_brf_notif_soc_req_lock_intr_count_r;
+ logic [31:0] full_addr_intr_brf_notif_soc_req_lock_intr_count_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_R;
+
+ logic hit_intr_brf_notif_gen_in_toggle_intr_count_r;
+ logic [3:0] bus_intr_brf_notif_gen_in_toggle_intr_count_r;
+ logic [31:0] full_addr_intr_brf_notif_gen_in_toggle_intr_count_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_R;
+
+ logic hit_intr_brf_error_internal_intr_count_incr_r;
+ logic [3:0] bus_intr_brf_error_internal_intr_count_incr_r;
+ logic [31:0] full_addr_intr_brf_error_internal_intr_count_incr_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R;
+
+ logic hit_intr_brf_error_inv_dev_intr_count_incr_r;
+ logic [3:0] bus_intr_brf_error_inv_dev_intr_count_incr_r;
+ logic [31:0] full_addr_intr_brf_error_inv_dev_intr_count_incr_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INV_DEV_INTR_COUNT_INCR_R;
+
+ logic hit_intr_brf_error_cmd_fail_intr_count_incr_r;
+ logic [3:0] bus_intr_brf_error_cmd_fail_intr_count_incr_r;
+ logic [31:0] full_addr_intr_brf_error_cmd_fail_intr_count_incr_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_CMD_FAIL_INTR_COUNT_INCR_R;
+
+ logic hit_intr_brf_error_bad_fuse_intr_count_incr_r;
+ logic [3:0] bus_intr_brf_error_bad_fuse_intr_count_incr_r;
+ logic [31:0] full_addr_intr_brf_error_bad_fuse_intr_count_incr_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_BAD_FUSE_INTR_COUNT_INCR_R;
+
+ logic hit_intr_brf_error_iccm_blocked_intr_count_incr_r;
+ logic [3:0] bus_intr_brf_error_iccm_blocked_intr_count_incr_r;
+ logic [31:0] full_addr_intr_brf_error_iccm_blocked_intr_count_incr_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_ICCM_BLOCKED_INTR_COUNT_INCR_R;
+
+ logic hit_intr_brf_error_mbox_ecc_unc_intr_count_incr_r;
+ logic [3:0] bus_intr_brf_error_mbox_ecc_unc_intr_count_incr_r;
+ logic [31:0] full_addr_intr_brf_error_mbox_ecc_unc_intr_count_incr_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_MBOX_ECC_UNC_INTR_COUNT_INCR_R;
+
+ logic hit_intr_brf_error_wdt_timer1_timeout_intr_count_incr_r;
+ logic [3:0] bus_intr_brf_error_wdt_timer1_timeout_intr_count_incr_r;
+ logic [31:0] full_addr_intr_brf_error_wdt_timer1_timeout_intr_count_incr_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_INCR_R;
+
+ logic hit_intr_brf_error_wdt_timer2_timeout_intr_count_incr_r;
+ logic [3:0] bus_intr_brf_error_wdt_timer2_timeout_intr_count_incr_r;
+ logic [31:0] full_addr_intr_brf_error_wdt_timer2_timeout_intr_count_incr_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_INCR_R;
+
+ logic hit_intr_brf_notif_cmd_avail_intr_count_incr_r;
+ logic [3:0] bus_intr_brf_notif_cmd_avail_intr_count_incr_r;
+ logic [31:0] full_addr_intr_brf_notif_cmd_avail_intr_count_incr_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_CMD_AVAIL_INTR_COUNT_INCR_R;
+
+ logic hit_intr_brf_notif_mbox_ecc_cor_intr_count_incr_r;
+ logic [3:0] bus_intr_brf_notif_mbox_ecc_cor_intr_count_incr_r;
+ logic [31:0] full_addr_intr_brf_notif_mbox_ecc_cor_intr_count_incr_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_INCR_R;
+
+ logic hit_intr_brf_notif_debug_locked_intr_count_incr_r;
+ logic [3:0] bus_intr_brf_notif_debug_locked_intr_count_incr_r;
+ logic [31:0] full_addr_intr_brf_notif_debug_locked_intr_count_incr_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_INCR_R;
+
+ logic hit_intr_brf_notif_soc_req_lock_intr_count_incr_r;
+ logic [3:0] bus_intr_brf_notif_soc_req_lock_intr_count_incr_r;
+ logic [31:0] full_addr_intr_brf_notif_soc_req_lock_intr_count_incr_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R;
+
assign hit_CPTRA_HW_ERROR_FATAL = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_HW_ERROR_FATAL[APB_ADDR_WIDTH-1:0]);
assign bus_CPTRA_HW_ERROR_FATAL = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_HW_ERROR_FATAL}};
@@ -799,6 +1010,9 @@ interface soc_ifc_cov_if
assign hit_CPTRA_TRNG_DATA[11] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_TRNG_DATA[11][18-1:0]);
assign bus_CPTRA_TRNG_DATA[11] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_TRNG_DATA[11]}};
+ assign hit_CPTRA_TRNG_CTRL = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_TRNG_CTRL[APB_ADDR_WIDTH-1:0]);
+ assign bus_CPTRA_TRNG_CTRL = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_TRNG_CTRL}};
+
assign hit_CPTRA_TRNG_STATUS = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_TRNG_STATUS[APB_ADDR_WIDTH-1:0]);
assign bus_CPTRA_TRNG_STATUS = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_TRNG_STATUS}};
@@ -874,6 +1088,24 @@ interface soc_ifc_cov_if
assign hit_CPTRA_FUSE_PAUSER_LOCK = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_FUSE_PAUSER_LOCK[APB_ADDR_WIDTH-1:0]);
assign bus_CPTRA_FUSE_PAUSER_LOCK = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_FUSE_PAUSER_LOCK}};
+ assign hit_CPTRA_WDT_CFG[0] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_WDT_CFG[0][18-1:0]);
+ assign bus_CPTRA_WDT_CFG[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_WDT_CFG[0]}};
+
+ assign hit_CPTRA_WDT_CFG[1] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_WDT_CFG[1][18-1:0]);
+ assign bus_CPTRA_WDT_CFG[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_WDT_CFG[1]}};
+
+ assign hit_CPTRA_iTRNG_ENTROPY_CONFIG_0 = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_iTRNG_ENTROPY_CONFIG_0[APB_ADDR_WIDTH-1:0]);
+ assign bus_CPTRA_iTRNG_ENTROPY_CONFIG_0 = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_iTRNG_ENTROPY_CONFIG_0}};
+
+ assign hit_CPTRA_iTRNG_ENTROPY_CONFIG_1 = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_iTRNG_ENTROPY_CONFIG_1[APB_ADDR_WIDTH-1:0]);
+ assign bus_CPTRA_iTRNG_ENTROPY_CONFIG_1 = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_iTRNG_ENTROPY_CONFIG_1}};
+
+ assign hit_CPTRA_RSVD_REG[0] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_RSVD_REG[0][18-1:0]);
+ assign bus_CPTRA_RSVD_REG[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_RSVD_REG[0]}};
+
+ assign hit_CPTRA_RSVD_REG[1] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_RSVD_REG[1][18-1:0]);
+ assign bus_CPTRA_RSVD_REG[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_RSVD_REG[1]}};
+
assign hit_fuse_uds_seed[0] = (soc_ifc_reg_req_data.addr == full_addr_fuse_uds_seed[0][18-1:0]);
assign bus_fuse_uds_seed[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_uds_seed[0]}};
@@ -1114,6 +1346,15 @@ interface soc_ifc_cov_if
assign hit_fuse_life_cycle = (soc_ifc_reg_req_data.addr == full_addr_fuse_life_cycle[APB_ADDR_WIDTH-1:0]);
assign bus_fuse_life_cycle = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_life_cycle}};
+ assign hit_fuse_lms_verify = (soc_ifc_reg_req_data.addr == full_addr_fuse_lms_verify[APB_ADDR_WIDTH-1:0]);
+ assign bus_fuse_lms_verify = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_lms_verify}};
+
+ assign hit_fuse_lms_revocation = (soc_ifc_reg_req_data.addr == full_addr_fuse_lms_revocation[APB_ADDR_WIDTH-1:0]);
+ assign bus_fuse_lms_revocation = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_lms_revocation}};
+
+ assign hit_fuse_soc_stepping_id = (soc_ifc_reg_req_data.addr == full_addr_fuse_soc_stepping_id[APB_ADDR_WIDTH-1:0]);
+ assign bus_fuse_soc_stepping_id = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_soc_stepping_id}};
+
assign hit_internal_obf_key[0] = (soc_ifc_reg_req_data.addr == full_addr_internal_obf_key[0][18-1:0]);
assign bus_internal_obf_key[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_obf_key[0]}};
@@ -1150,6 +1391,135 @@ interface soc_ifc_cov_if
assign hit_internal_nmi_vector = (soc_ifc_reg_req_data.addr == full_addr_internal_nmi_vector[APB_ADDR_WIDTH-1:0]);
assign bus_internal_nmi_vector = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_nmi_vector}};
+ assign hit_internal_hw_error_fatal_mask = (soc_ifc_reg_req_data.addr == full_addr_internal_hw_error_fatal_mask[APB_ADDR_WIDTH-1:0]);
+ assign bus_internal_hw_error_fatal_mask = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_hw_error_fatal_mask}};
+
+ assign hit_internal_hw_error_non_fatal_mask = (soc_ifc_reg_req_data.addr == full_addr_internal_hw_error_non_fatal_mask[APB_ADDR_WIDTH-1:0]);
+ assign bus_internal_hw_error_non_fatal_mask = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_hw_error_non_fatal_mask}};
+
+ assign hit_internal_fw_error_fatal_mask = (soc_ifc_reg_req_data.addr == full_addr_internal_fw_error_fatal_mask[APB_ADDR_WIDTH-1:0]);
+ assign bus_internal_fw_error_fatal_mask = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_fw_error_fatal_mask}};
+
+ assign hit_internal_fw_error_non_fatal_mask = (soc_ifc_reg_req_data.addr == full_addr_internal_fw_error_non_fatal_mask[APB_ADDR_WIDTH-1:0]);
+ assign bus_internal_fw_error_non_fatal_mask = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_fw_error_non_fatal_mask}};
+
+ assign hit_internal_rv_mtime_l = (soc_ifc_reg_req_data.addr == full_addr_internal_rv_mtime_l[APB_ADDR_WIDTH-1:0]);
+ assign bus_internal_rv_mtime_l = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_rv_mtime_l}};
+
+ assign hit_internal_rv_mtime_h = (soc_ifc_reg_req_data.addr == full_addr_internal_rv_mtime_h[APB_ADDR_WIDTH-1:0]);
+ assign bus_internal_rv_mtime_h = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_rv_mtime_h}};
+
+ assign hit_internal_rv_mtimecmp_l = (soc_ifc_reg_req_data.addr == full_addr_internal_rv_mtimecmp_l[APB_ADDR_WIDTH-1:0]);
+ assign bus_internal_rv_mtimecmp_l = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_rv_mtimecmp_l}};
+
+ assign hit_internal_rv_mtimecmp_h = (soc_ifc_reg_req_data.addr == full_addr_internal_rv_mtimecmp_h[APB_ADDR_WIDTH-1:0]);
+ assign bus_internal_rv_mtimecmp_h = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_rv_mtimecmp_h}};
+
+ assign hit_intr_brf_global_intr_en_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_global_intr_en_r[APB_ADDR_WIDTH-1:0]);
+ assign bus_intr_brf_global_intr_en_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_global_intr_en_r}};
+
+ assign hit_intr_brf_error_intr_en_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_intr_en_r[APB_ADDR_WIDTH-1:0]);
+ assign bus_intr_brf_error_intr_en_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_intr_en_r}};
+
+ assign hit_intr_brf_notif_intr_en_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_intr_en_r[APB_ADDR_WIDTH-1:0]);
+ assign bus_intr_brf_notif_intr_en_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_intr_en_r}};
+
+ assign hit_intr_brf_error_global_intr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_global_intr_r[APB_ADDR_WIDTH-1:0]);
+ assign bus_intr_brf_error_global_intr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_global_intr_r}};
+
+ assign hit_intr_brf_notif_global_intr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_global_intr_r[APB_ADDR_WIDTH-1:0]);
+ assign bus_intr_brf_notif_global_intr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_global_intr_r}};
+
+ assign hit_intr_brf_error_internal_intr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_internal_intr_r[APB_ADDR_WIDTH-1:0]);
+ assign bus_intr_brf_error_internal_intr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_internal_intr_r}};
+
+ assign hit_intr_brf_notif_internal_intr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_internal_intr_r[APB_ADDR_WIDTH-1:0]);
+ assign bus_intr_brf_notif_internal_intr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_internal_intr_r}};
+
+ assign hit_intr_brf_error_intr_trig_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_intr_trig_r[APB_ADDR_WIDTH-1:0]);
+ assign bus_intr_brf_error_intr_trig_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_intr_trig_r}};
+
+ assign hit_intr_brf_notif_intr_trig_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_intr_trig_r[APB_ADDR_WIDTH-1:0]);
+ assign bus_intr_brf_notif_intr_trig_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_intr_trig_r}};
+
+ assign hit_intr_brf_error_internal_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_internal_intr_count_r[APB_ADDR_WIDTH-1:0]);
+ assign bus_intr_brf_error_internal_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_internal_intr_count_r}};
+
+ assign hit_intr_brf_error_inv_dev_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_inv_dev_intr_count_r[APB_ADDR_WIDTH-1:0]);
+ assign bus_intr_brf_error_inv_dev_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_inv_dev_intr_count_r}};
+
+ assign hit_intr_brf_error_cmd_fail_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_cmd_fail_intr_count_r[APB_ADDR_WIDTH-1:0]);
+ assign bus_intr_brf_error_cmd_fail_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_cmd_fail_intr_count_r}};
+
+ assign hit_intr_brf_error_bad_fuse_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_bad_fuse_intr_count_r[APB_ADDR_WIDTH-1:0]);
+ assign bus_intr_brf_error_bad_fuse_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_bad_fuse_intr_count_r}};
+
+ assign hit_intr_brf_error_iccm_blocked_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_iccm_blocked_intr_count_r[APB_ADDR_WIDTH-1:0]);
+ assign bus_intr_brf_error_iccm_blocked_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_iccm_blocked_intr_count_r}};
+
+ assign hit_intr_brf_error_mbox_ecc_unc_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_mbox_ecc_unc_intr_count_r[APB_ADDR_WIDTH-1:0]);
+ assign bus_intr_brf_error_mbox_ecc_unc_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_mbox_ecc_unc_intr_count_r}};
+
+ assign hit_intr_brf_error_wdt_timer1_timeout_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_wdt_timer1_timeout_intr_count_r[APB_ADDR_WIDTH-1:0]);
+ assign bus_intr_brf_error_wdt_timer1_timeout_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_wdt_timer1_timeout_intr_count_r}};
+
+ assign hit_intr_brf_error_wdt_timer2_timeout_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_wdt_timer2_timeout_intr_count_r[APB_ADDR_WIDTH-1:0]);
+ assign bus_intr_brf_error_wdt_timer2_timeout_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_wdt_timer2_timeout_intr_count_r}};
+
+ assign hit_intr_brf_notif_cmd_avail_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_cmd_avail_intr_count_r[APB_ADDR_WIDTH-1:0]);
+ assign bus_intr_brf_notif_cmd_avail_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_cmd_avail_intr_count_r}};
+
+ assign hit_intr_brf_notif_mbox_ecc_cor_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_mbox_ecc_cor_intr_count_r[APB_ADDR_WIDTH-1:0]);
+ assign bus_intr_brf_notif_mbox_ecc_cor_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_mbox_ecc_cor_intr_count_r}};
+
+ assign hit_intr_brf_notif_debug_locked_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_debug_locked_intr_count_r[APB_ADDR_WIDTH-1:0]);
+ assign bus_intr_brf_notif_debug_locked_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_debug_locked_intr_count_r}};
+
+ assign hit_intr_brf_notif_scan_mode_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_scan_mode_intr_count_r[APB_ADDR_WIDTH-1:0]);
+ assign bus_intr_brf_notif_scan_mode_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_scan_mode_intr_count_r}};
+
+ assign hit_intr_brf_notif_soc_req_lock_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_soc_req_lock_intr_count_r[APB_ADDR_WIDTH-1:0]);
+ assign bus_intr_brf_notif_soc_req_lock_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_soc_req_lock_intr_count_r}};
+
+ assign hit_intr_brf_notif_gen_in_toggle_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_gen_in_toggle_intr_count_r[APB_ADDR_WIDTH-1:0]);
+ assign bus_intr_brf_notif_gen_in_toggle_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_gen_in_toggle_intr_count_r}};
+
+ assign hit_intr_brf_error_internal_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_internal_intr_count_incr_r[APB_ADDR_WIDTH-1:0]);
+ assign bus_intr_brf_error_internal_intr_count_incr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_internal_intr_count_incr_r}};
+
+ assign hit_intr_brf_error_inv_dev_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_inv_dev_intr_count_incr_r[APB_ADDR_WIDTH-1:0]);
+ assign bus_intr_brf_error_inv_dev_intr_count_incr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_inv_dev_intr_count_incr_r}};
+
+ assign hit_intr_brf_error_cmd_fail_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_cmd_fail_intr_count_incr_r[APB_ADDR_WIDTH-1:0]);
+ assign bus_intr_brf_error_cmd_fail_intr_count_incr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_cmd_fail_intr_count_incr_r}};
+
+ assign hit_intr_brf_error_bad_fuse_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_bad_fuse_intr_count_incr_r[APB_ADDR_WIDTH-1:0]);
+ assign bus_intr_brf_error_bad_fuse_intr_count_incr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_bad_fuse_intr_count_incr_r}};
+
+ assign hit_intr_brf_error_iccm_blocked_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_iccm_blocked_intr_count_incr_r[APB_ADDR_WIDTH-1:0]);
+ assign bus_intr_brf_error_iccm_blocked_intr_count_incr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_iccm_blocked_intr_count_incr_r}};
+
+ assign hit_intr_brf_error_mbox_ecc_unc_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_mbox_ecc_unc_intr_count_incr_r[APB_ADDR_WIDTH-1:0]);
+ assign bus_intr_brf_error_mbox_ecc_unc_intr_count_incr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_mbox_ecc_unc_intr_count_incr_r}};
+
+ assign hit_intr_brf_error_wdt_timer1_timeout_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_wdt_timer1_timeout_intr_count_incr_r[APB_ADDR_WIDTH-1:0]);
+ assign bus_intr_brf_error_wdt_timer1_timeout_intr_count_incr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_wdt_timer1_timeout_intr_count_incr_r}};
+
+ assign hit_intr_brf_error_wdt_timer2_timeout_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_wdt_timer2_timeout_intr_count_incr_r[APB_ADDR_WIDTH-1:0]);
+ assign bus_intr_brf_error_wdt_timer2_timeout_intr_count_incr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_wdt_timer2_timeout_intr_count_incr_r}};
+
+ assign hit_intr_brf_notif_cmd_avail_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_cmd_avail_intr_count_incr_r[APB_ADDR_WIDTH-1:0]);
+ assign bus_intr_brf_notif_cmd_avail_intr_count_incr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_cmd_avail_intr_count_incr_r}};
+
+ assign hit_intr_brf_notif_mbox_ecc_cor_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_mbox_ecc_cor_intr_count_incr_r[APB_ADDR_WIDTH-1:0]);
+ assign bus_intr_brf_notif_mbox_ecc_cor_intr_count_incr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_mbox_ecc_cor_intr_count_incr_r}};
+
+ assign hit_intr_brf_notif_debug_locked_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_debug_locked_intr_count_incr_r[APB_ADDR_WIDTH-1:0]);
+ assign bus_intr_brf_notif_debug_locked_intr_count_incr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_debug_locked_intr_count_incr_r}};
+
+ assign hit_intr_brf_notif_soc_req_lock_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_soc_req_lock_intr_count_incr_r[APB_ADDR_WIDTH-1:0]);
+ assign bus_intr_brf_notif_soc_req_lock_intr_count_incr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_soc_req_lock_intr_count_incr_r}};
+
// ----------------------- COVERGROUP CPTRA_HW_ERROR_FATAL -----------------------
covergroup soc_ifc_CPTRA_HW_ERROR_FATAL_cg (ref logic [3:0] bus_event) @(posedge clk);
CPTRA_HW_ERROR_FATAL_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_HW_ERROR_FATAL;
@@ -1424,6 +1794,15 @@ interface soc_ifc_cov_if
}
endgroup
+ // ----------------------- COVERGROUP CPTRA_TRNG_CTRL -----------------------
+ covergroup soc_ifc_CPTRA_TRNG_CTRL_cg (ref logic [3:0] bus_event) @(posedge clk);
+ CPTRA_TRNG_CTRL_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TRNG_CTRL;
+ bus_CPTRA_TRNG_CTRL_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
// ----------------------- COVERGROUP CPTRA_TRNG_STATUS -----------------------
covergroup soc_ifc_CPTRA_TRNG_STATUS_cg (ref logic [3:0] bus_event) @(posedge clk);
CPTRA_TRNG_STATUS_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TRNG_STATUS;
@@ -1629,6 +2008,52 @@ interface soc_ifc_cov_if
}
endgroup
+ // ----------------------- COVERGROUP CPTRA_WDT_CFG [0:1] -----------------------
+ covergroup soc_ifc_CPTRA_WDT_CFG_cg (ref logic [3:0] bus_event[0:1]) @(posedge clk);
+ CPTRA_WDT_CFG0_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_WDT_CFG[0];
+ bus_CPTRA_WDT_CFG0_cp : coverpoint bus_event[0] {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ CPTRA_WDT_CFG1_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_WDT_CFG[1];
+ bus_CPTRA_WDT_CFG1_cp : coverpoint bus_event[1] {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP CPTRA_iTRNG_ENTROPY_CONFIG_0 -----------------------
+ covergroup soc_ifc_CPTRA_iTRNG_ENTROPY_CONFIG_0_cg (ref logic [3:0] bus_event) @(posedge clk);
+ CPTRA_iTRNG_ENTROPY_CONFIG_0_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_0;
+ bus_CPTRA_iTRNG_ENTROPY_CONFIG_0_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP CPTRA_iTRNG_ENTROPY_CONFIG_1 -----------------------
+ covergroup soc_ifc_CPTRA_iTRNG_ENTROPY_CONFIG_1_cg (ref logic [3:0] bus_event) @(posedge clk);
+ CPTRA_iTRNG_ENTROPY_CONFIG_1_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_1;
+ bus_CPTRA_iTRNG_ENTROPY_CONFIG_1_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP CPTRA_RSVD_REG [0:1] -----------------------
+ covergroup soc_ifc_CPTRA_RSVD_REG_cg (ref logic [3:0] bus_event[0:1]) @(posedge clk);
+ CPTRA_RSVD_REG0_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_RSVD_REG[0];
+ bus_CPTRA_RSVD_REG0_cp : coverpoint bus_event[0] {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ CPTRA_RSVD_REG1_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_RSVD_REG[1];
+ bus_CPTRA_RSVD_REG1_cp : coverpoint bus_event[1] {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
// ----------------------- COVERGROUP fuse_uds_seed [0:11] -----------------------
covergroup soc_ifc_fuse_uds_seed_cg (ref logic [3:0] bus_event[0:11]) @(posedge clk);
fuse_uds_seed0_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_uds_seed[0];
@@ -2073,6 +2498,33 @@ interface soc_ifc_cov_if
}
endgroup
+ // ----------------------- COVERGROUP fuse_lms_verify -----------------------
+ covergroup soc_ifc_fuse_lms_verify_cg (ref logic [3:0] bus_event) @(posedge clk);
+ fuse_lms_verify_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_lms_verify;
+ bus_fuse_lms_verify_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP fuse_lms_revocation -----------------------
+ covergroup soc_ifc_fuse_lms_revocation_cg (ref logic [3:0] bus_event) @(posedge clk);
+ fuse_lms_revocation_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_lms_revocation;
+ bus_fuse_lms_revocation_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP fuse_soc_stepping_id -----------------------
+ covergroup soc_ifc_fuse_soc_stepping_id_cg (ref logic [3:0] bus_event) @(posedge clk);
+ fuse_soc_stepping_id_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_soc_stepping_id;
+ bus_fuse_soc_stepping_id_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
// ----------------------- COVERGROUP internal_obf_key [0:7] -----------------------
covergroup soc_ifc_internal_obf_key_cg (ref logic [3:0] bus_event[0:7]) @(posedge clk);
internal_obf_key0_cp : coverpoint i_soc_ifc_reg.field_storage.internal_obf_key[0];
@@ -2153,6 +2605,393 @@ interface soc_ifc_cov_if
}
endgroup
+ // ----------------------- COVERGROUP internal_hw_error_fatal_mask -----------------------
+ covergroup soc_ifc_internal_hw_error_fatal_mask_cg (ref logic [3:0] bus_event) @(posedge clk);
+ internal_hw_error_fatal_mask_cp : coverpoint i_soc_ifc_reg.field_storage.internal_hw_error_fatal_mask;
+ bus_internal_hw_error_fatal_mask_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP internal_hw_error_non_fatal_mask -----------------------
+ covergroup soc_ifc_internal_hw_error_non_fatal_mask_cg (ref logic [3:0] bus_event) @(posedge clk);
+ internal_hw_error_non_fatal_mask_cp : coverpoint i_soc_ifc_reg.field_storage.internal_hw_error_non_fatal_mask;
+ bus_internal_hw_error_non_fatal_mask_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP internal_fw_error_fatal_mask -----------------------
+ covergroup soc_ifc_internal_fw_error_fatal_mask_cg (ref logic [3:0] bus_event) @(posedge clk);
+ internal_fw_error_fatal_mask_cp : coverpoint i_soc_ifc_reg.field_storage.internal_fw_error_fatal_mask;
+ bus_internal_fw_error_fatal_mask_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP internal_fw_error_non_fatal_mask -----------------------
+ covergroup soc_ifc_internal_fw_error_non_fatal_mask_cg (ref logic [3:0] bus_event) @(posedge clk);
+ internal_fw_error_non_fatal_mask_cp : coverpoint i_soc_ifc_reg.field_storage.internal_fw_error_non_fatal_mask;
+ bus_internal_fw_error_non_fatal_mask_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP internal_rv_mtime_l -----------------------
+ covergroup soc_ifc_internal_rv_mtime_l_cg (ref logic [3:0] bus_event) @(posedge clk);
+ internal_rv_mtime_l_cp : coverpoint i_soc_ifc_reg.field_storage.internal_rv_mtime_l;
+ bus_internal_rv_mtime_l_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP internal_rv_mtime_h -----------------------
+ covergroup soc_ifc_internal_rv_mtime_h_cg (ref logic [3:0] bus_event) @(posedge clk);
+ internal_rv_mtime_h_cp : coverpoint i_soc_ifc_reg.field_storage.internal_rv_mtime_h;
+ bus_internal_rv_mtime_h_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP internal_rv_mtimecmp_l -----------------------
+ covergroup soc_ifc_internal_rv_mtimecmp_l_cg (ref logic [3:0] bus_event) @(posedge clk);
+ internal_rv_mtimecmp_l_cp : coverpoint i_soc_ifc_reg.field_storage.internal_rv_mtimecmp_l;
+ bus_internal_rv_mtimecmp_l_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP internal_rv_mtimecmp_h -----------------------
+ covergroup soc_ifc_internal_rv_mtimecmp_h_cg (ref logic [3:0] bus_event) @(posedge clk);
+ internal_rv_mtimecmp_h_cp : coverpoint i_soc_ifc_reg.field_storage.internal_rv_mtimecmp_h;
+ bus_internal_rv_mtimecmp_h_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP intr_brf_global_intr_en_r -----------------------
+ covergroup soc_ifc_intr_brf_global_intr_en_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+ intr_brf_global_intr_en_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.global_intr_en_r;
+ bus_intr_brf_global_intr_en_r_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP intr_brf_error_intr_en_r -----------------------
+ covergroup soc_ifc_intr_brf_error_intr_en_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+ intr_brf_error_intr_en_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_intr_en_r;
+ bus_intr_brf_error_intr_en_r_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP intr_brf_notif_intr_en_r -----------------------
+ covergroup soc_ifc_intr_brf_notif_intr_en_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+ intr_brf_notif_intr_en_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_en_r;
+ bus_intr_brf_notif_intr_en_r_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP intr_brf_error_global_intr_r -----------------------
+ covergroup soc_ifc_intr_brf_error_global_intr_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+ intr_brf_error_global_intr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_global_intr_r;
+ bus_intr_brf_error_global_intr_r_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP intr_brf_notif_global_intr_r -----------------------
+ covergroup soc_ifc_intr_brf_notif_global_intr_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+ intr_brf_notif_global_intr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_global_intr_r;
+ bus_intr_brf_notif_global_intr_r_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP intr_brf_error_internal_intr_r -----------------------
+ covergroup soc_ifc_intr_brf_error_internal_intr_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+ intr_brf_error_internal_intr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_internal_intr_r;
+ bus_intr_brf_error_internal_intr_r_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP intr_brf_notif_internal_intr_r -----------------------
+ covergroup soc_ifc_intr_brf_notif_internal_intr_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+ intr_brf_notif_internal_intr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_internal_intr_r;
+ bus_intr_brf_notif_internal_intr_r_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP intr_brf_error_intr_trig_r -----------------------
+ covergroup soc_ifc_intr_brf_error_intr_trig_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+ intr_brf_error_intr_trig_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_intr_trig_r;
+ bus_intr_brf_error_intr_trig_r_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP intr_brf_notif_intr_trig_r -----------------------
+ covergroup soc_ifc_intr_brf_notif_intr_trig_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+ intr_brf_notif_intr_trig_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_trig_r;
+ bus_intr_brf_notif_intr_trig_r_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP intr_brf_error_internal_intr_count_r -----------------------
+ covergroup soc_ifc_intr_brf_error_internal_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+ intr_brf_error_internal_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_internal_intr_count_r;
+ bus_intr_brf_error_internal_intr_count_r_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP intr_brf_error_inv_dev_intr_count_r -----------------------
+ covergroup soc_ifc_intr_brf_error_inv_dev_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+ intr_brf_error_inv_dev_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_inv_dev_intr_count_r;
+ bus_intr_brf_error_inv_dev_intr_count_r_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP intr_brf_error_cmd_fail_intr_count_r -----------------------
+ covergroup soc_ifc_intr_brf_error_cmd_fail_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+ intr_brf_error_cmd_fail_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_cmd_fail_intr_count_r;
+ bus_intr_brf_error_cmd_fail_intr_count_r_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP intr_brf_error_bad_fuse_intr_count_r -----------------------
+ covergroup soc_ifc_intr_brf_error_bad_fuse_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+ intr_brf_error_bad_fuse_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_bad_fuse_intr_count_r;
+ bus_intr_brf_error_bad_fuse_intr_count_r_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP intr_brf_error_iccm_blocked_intr_count_r -----------------------
+ covergroup soc_ifc_intr_brf_error_iccm_blocked_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+ intr_brf_error_iccm_blocked_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_iccm_blocked_intr_count_r;
+ bus_intr_brf_error_iccm_blocked_intr_count_r_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP intr_brf_error_mbox_ecc_unc_intr_count_r -----------------------
+ covergroup soc_ifc_intr_brf_error_mbox_ecc_unc_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+ intr_brf_error_mbox_ecc_unc_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_r;
+ bus_intr_brf_error_mbox_ecc_unc_intr_count_r_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP intr_brf_error_wdt_timer1_timeout_intr_count_r -----------------------
+ covergroup soc_ifc_intr_brf_error_wdt_timer1_timeout_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+ intr_brf_error_wdt_timer1_timeout_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_r;
+ bus_intr_brf_error_wdt_timer1_timeout_intr_count_r_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP intr_brf_error_wdt_timer2_timeout_intr_count_r -----------------------
+ covergroup soc_ifc_intr_brf_error_wdt_timer2_timeout_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+ intr_brf_error_wdt_timer2_timeout_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_r;
+ bus_intr_brf_error_wdt_timer2_timeout_intr_count_r_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP intr_brf_notif_cmd_avail_intr_count_r -----------------------
+ covergroup soc_ifc_intr_brf_notif_cmd_avail_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+ intr_brf_notif_cmd_avail_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_cmd_avail_intr_count_r;
+ bus_intr_brf_notif_cmd_avail_intr_count_r_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP intr_brf_notif_mbox_ecc_cor_intr_count_r -----------------------
+ covergroup soc_ifc_intr_brf_notif_mbox_ecc_cor_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+ intr_brf_notif_mbox_ecc_cor_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_r;
+ bus_intr_brf_notif_mbox_ecc_cor_intr_count_r_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP intr_brf_notif_debug_locked_intr_count_r -----------------------
+ covergroup soc_ifc_intr_brf_notif_debug_locked_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+ intr_brf_notif_debug_locked_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_debug_locked_intr_count_r;
+ bus_intr_brf_notif_debug_locked_intr_count_r_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP intr_brf_notif_scan_mode_intr_count_r -----------------------
+ covergroup soc_ifc_intr_brf_notif_scan_mode_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+ intr_brf_notif_scan_mode_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_scan_mode_intr_count_r;
+ bus_intr_brf_notif_scan_mode_intr_count_r_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP intr_brf_notif_soc_req_lock_intr_count_r -----------------------
+ covergroup soc_ifc_intr_brf_notif_soc_req_lock_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+ intr_brf_notif_soc_req_lock_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_soc_req_lock_intr_count_r;
+ bus_intr_brf_notif_soc_req_lock_intr_count_r_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP intr_brf_notif_gen_in_toggle_intr_count_r -----------------------
+ covergroup soc_ifc_intr_brf_notif_gen_in_toggle_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+ intr_brf_notif_gen_in_toggle_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_r;
+ bus_intr_brf_notif_gen_in_toggle_intr_count_r_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP intr_brf_error_internal_intr_count_incr_r -----------------------
+ covergroup soc_ifc_intr_brf_error_internal_intr_count_incr_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+ intr_brf_error_internal_intr_count_incr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_internal_intr_count_incr_r;
+ bus_intr_brf_error_internal_intr_count_incr_r_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP intr_brf_error_inv_dev_intr_count_incr_r -----------------------
+ covergroup soc_ifc_intr_brf_error_inv_dev_intr_count_incr_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+ intr_brf_error_inv_dev_intr_count_incr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_inv_dev_intr_count_incr_r;
+ bus_intr_brf_error_inv_dev_intr_count_incr_r_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP intr_brf_error_cmd_fail_intr_count_incr_r -----------------------
+ covergroup soc_ifc_intr_brf_error_cmd_fail_intr_count_incr_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+ intr_brf_error_cmd_fail_intr_count_incr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_cmd_fail_intr_count_incr_r;
+ bus_intr_brf_error_cmd_fail_intr_count_incr_r_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP intr_brf_error_bad_fuse_intr_count_incr_r -----------------------
+ covergroup soc_ifc_intr_brf_error_bad_fuse_intr_count_incr_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+ intr_brf_error_bad_fuse_intr_count_incr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_bad_fuse_intr_count_incr_r;
+ bus_intr_brf_error_bad_fuse_intr_count_incr_r_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP intr_brf_error_iccm_blocked_intr_count_incr_r -----------------------
+ covergroup soc_ifc_intr_brf_error_iccm_blocked_intr_count_incr_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+ intr_brf_error_iccm_blocked_intr_count_incr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_iccm_blocked_intr_count_incr_r;
+ bus_intr_brf_error_iccm_blocked_intr_count_incr_r_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP intr_brf_error_mbox_ecc_unc_intr_count_incr_r -----------------------
+ covergroup soc_ifc_intr_brf_error_mbox_ecc_unc_intr_count_incr_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+ intr_brf_error_mbox_ecc_unc_intr_count_incr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r;
+ bus_intr_brf_error_mbox_ecc_unc_intr_count_incr_r_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP intr_brf_error_wdt_timer1_timeout_intr_count_incr_r -----------------------
+ covergroup soc_ifc_intr_brf_error_wdt_timer1_timeout_intr_count_incr_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+ intr_brf_error_wdt_timer1_timeout_intr_count_incr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r;
+ bus_intr_brf_error_wdt_timer1_timeout_intr_count_incr_r_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP intr_brf_error_wdt_timer2_timeout_intr_count_incr_r -----------------------
+ covergroup soc_ifc_intr_brf_error_wdt_timer2_timeout_intr_count_incr_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+ intr_brf_error_wdt_timer2_timeout_intr_count_incr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r;
+ bus_intr_brf_error_wdt_timer2_timeout_intr_count_incr_r_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP intr_brf_notif_cmd_avail_intr_count_incr_r -----------------------
+ covergroup soc_ifc_intr_brf_notif_cmd_avail_intr_count_incr_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+ intr_brf_notif_cmd_avail_intr_count_incr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_cmd_avail_intr_count_incr_r;
+ bus_intr_brf_notif_cmd_avail_intr_count_incr_r_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP intr_brf_notif_mbox_ecc_cor_intr_count_incr_r -----------------------
+ covergroup soc_ifc_intr_brf_notif_mbox_ecc_cor_intr_count_incr_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+ intr_brf_notif_mbox_ecc_cor_intr_count_incr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r;
+ bus_intr_brf_notif_mbox_ecc_cor_intr_count_incr_r_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP intr_brf_notif_debug_locked_intr_count_incr_r -----------------------
+ covergroup soc_ifc_intr_brf_notif_debug_locked_intr_count_incr_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+ intr_brf_notif_debug_locked_intr_count_incr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_debug_locked_intr_count_incr_r;
+ bus_intr_brf_notif_debug_locked_intr_count_incr_r_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP intr_brf_notif_soc_req_lock_intr_count_incr_r -----------------------
+ covergroup soc_ifc_intr_brf_notif_soc_req_lock_intr_count_incr_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+ intr_brf_notif_soc_req_lock_intr_count_incr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_soc_req_lock_intr_count_incr_r;
+ bus_intr_brf_notif_soc_req_lock_intr_count_incr_r_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
// ----------------------- COVERGROUP Instantiations -----------------------
@@ -2172,6 +3011,7 @@ interface soc_ifc_cov_if
soc_ifc_CPTRA_TRNG_VALID_PAUSER_cg CPTRA_TRNG_VALID_PAUSER_cg = new(bus_CPTRA_TRNG_VALID_PAUSER);
soc_ifc_CPTRA_TRNG_PAUSER_LOCK_cg CPTRA_TRNG_PAUSER_LOCK_cg = new(bus_CPTRA_TRNG_PAUSER_LOCK);
soc_ifc_CPTRA_TRNG_DATA_cg CPTRA_TRNG_DATA_cg = new(bus_CPTRA_TRNG_DATA);
+ soc_ifc_CPTRA_TRNG_CTRL_cg CPTRA_TRNG_CTRL_cg = new(bus_CPTRA_TRNG_CTRL);
soc_ifc_CPTRA_TRNG_STATUS_cg CPTRA_TRNG_STATUS_cg = new(bus_CPTRA_TRNG_STATUS);
soc_ifc_CPTRA_FUSE_WR_DONE_cg CPTRA_FUSE_WR_DONE_cg = new(bus_CPTRA_FUSE_WR_DONE);
soc_ifc_CPTRA_TIMER_CONFIG_cg CPTRA_TIMER_CONFIG_cg = new(bus_CPTRA_TIMER_CONFIG);
@@ -2192,6 +3032,10 @@ interface soc_ifc_cov_if
soc_ifc_CPTRA_WDT_STATUS_cg CPTRA_WDT_STATUS_cg = new(bus_CPTRA_WDT_STATUS);
soc_ifc_CPTRA_FUSE_VALID_PAUSER_cg CPTRA_FUSE_VALID_PAUSER_cg = new(bus_CPTRA_FUSE_VALID_PAUSER);
soc_ifc_CPTRA_FUSE_PAUSER_LOCK_cg CPTRA_FUSE_PAUSER_LOCK_cg = new(bus_CPTRA_FUSE_PAUSER_LOCK);
+ soc_ifc_CPTRA_WDT_CFG_cg CPTRA_WDT_CFG_cg = new(bus_CPTRA_WDT_CFG);
+ soc_ifc_CPTRA_iTRNG_ENTROPY_CONFIG_0_cg CPTRA_iTRNG_ENTROPY_CONFIG_0_cg = new(bus_CPTRA_iTRNG_ENTROPY_CONFIG_0);
+ soc_ifc_CPTRA_iTRNG_ENTROPY_CONFIG_1_cg CPTRA_iTRNG_ENTROPY_CONFIG_1_cg = new(bus_CPTRA_iTRNG_ENTROPY_CONFIG_1);
+ soc_ifc_CPTRA_RSVD_REG_cg CPTRA_RSVD_REG_cg = new(bus_CPTRA_RSVD_REG);
soc_ifc_fuse_uds_seed_cg fuse_uds_seed_cg = new(bus_fuse_uds_seed);
soc_ifc_fuse_field_entropy_cg fuse_field_entropy_cg = new(bus_fuse_field_entropy);
soc_ifc_fuse_key_manifest_pk_hash_cg fuse_key_manifest_pk_hash_cg = new(bus_fuse_key_manifest_pk_hash);
@@ -2203,17 +3047,64 @@ interface soc_ifc_cov_if
soc_ifc_fuse_idevid_cert_attr_cg fuse_idevid_cert_attr_cg = new(bus_fuse_idevid_cert_attr);
soc_ifc_fuse_idevid_manuf_hsm_id_cg fuse_idevid_manuf_hsm_id_cg = new(bus_fuse_idevid_manuf_hsm_id);
soc_ifc_fuse_life_cycle_cg fuse_life_cycle_cg = new(bus_fuse_life_cycle);
+ soc_ifc_fuse_lms_verify_cg fuse_lms_verify_cg = new(bus_fuse_lms_verify);
+ soc_ifc_fuse_lms_revocation_cg fuse_lms_revocation_cg = new(bus_fuse_lms_revocation);
+ soc_ifc_fuse_soc_stepping_id_cg fuse_soc_stepping_id_cg = new(bus_fuse_soc_stepping_id);
soc_ifc_internal_obf_key_cg internal_obf_key_cg = new(bus_internal_obf_key);
soc_ifc_internal_iccm_lock_cg internal_iccm_lock_cg = new(bus_internal_iccm_lock);
soc_ifc_internal_fw_update_reset_cg internal_fw_update_reset_cg = new(bus_internal_fw_update_reset);
soc_ifc_internal_fw_update_reset_wait_cycles_cg internal_fw_update_reset_wait_cycles_cg = new(bus_internal_fw_update_reset_wait_cycles);
soc_ifc_internal_nmi_vector_cg internal_nmi_vector_cg = new(bus_internal_nmi_vector);
+ soc_ifc_internal_hw_error_fatal_mask_cg internal_hw_error_fatal_mask_cg = new(bus_internal_hw_error_fatal_mask);
+ soc_ifc_internal_hw_error_non_fatal_mask_cg internal_hw_error_non_fatal_mask_cg = new(bus_internal_hw_error_non_fatal_mask);
+ soc_ifc_internal_fw_error_fatal_mask_cg internal_fw_error_fatal_mask_cg = new(bus_internal_fw_error_fatal_mask);
+ soc_ifc_internal_fw_error_non_fatal_mask_cg internal_fw_error_non_fatal_mask_cg = new(bus_internal_fw_error_non_fatal_mask);
+ soc_ifc_internal_rv_mtime_l_cg internal_rv_mtime_l_cg = new(bus_internal_rv_mtime_l);
+ soc_ifc_internal_rv_mtime_h_cg internal_rv_mtime_h_cg = new(bus_internal_rv_mtime_h);
+ soc_ifc_internal_rv_mtimecmp_l_cg internal_rv_mtimecmp_l_cg = new(bus_internal_rv_mtimecmp_l);
+ soc_ifc_internal_rv_mtimecmp_h_cg internal_rv_mtimecmp_h_cg = new(bus_internal_rv_mtimecmp_h);
+ soc_ifc_intr_brf_global_intr_en_r_cg intr_brf_global_intr_en_r_cg = new(bus_intr_brf_global_intr_en_r);
+ soc_ifc_intr_brf_error_intr_en_r_cg intr_brf_error_intr_en_r_cg = new(bus_intr_brf_error_intr_en_r);
+ soc_ifc_intr_brf_notif_intr_en_r_cg intr_brf_notif_intr_en_r_cg = new(bus_intr_brf_notif_intr_en_r);
+ soc_ifc_intr_brf_error_global_intr_r_cg intr_brf_error_global_intr_r_cg = new(bus_intr_brf_error_global_intr_r);
+ soc_ifc_intr_brf_notif_global_intr_r_cg intr_brf_notif_global_intr_r_cg = new(bus_intr_brf_notif_global_intr_r);
+ soc_ifc_intr_brf_error_internal_intr_r_cg intr_brf_error_internal_intr_r_cg = new(bus_intr_brf_error_internal_intr_r);
+ soc_ifc_intr_brf_notif_internal_intr_r_cg intr_brf_notif_internal_intr_r_cg = new(bus_intr_brf_notif_internal_intr_r);
+ soc_ifc_intr_brf_error_intr_trig_r_cg intr_brf_error_intr_trig_r_cg = new(bus_intr_brf_error_intr_trig_r);
+ soc_ifc_intr_brf_notif_intr_trig_r_cg intr_brf_notif_intr_trig_r_cg = new(bus_intr_brf_notif_intr_trig_r);
+ soc_ifc_intr_brf_error_internal_intr_count_r_cg intr_brf_error_internal_intr_count_r_cg = new(bus_intr_brf_error_internal_intr_count_r);
+ soc_ifc_intr_brf_error_inv_dev_intr_count_r_cg intr_brf_error_inv_dev_intr_count_r_cg = new(bus_intr_brf_error_inv_dev_intr_count_r);
+ soc_ifc_intr_brf_error_cmd_fail_intr_count_r_cg intr_brf_error_cmd_fail_intr_count_r_cg = new(bus_intr_brf_error_cmd_fail_intr_count_r);
+ soc_ifc_intr_brf_error_bad_fuse_intr_count_r_cg intr_brf_error_bad_fuse_intr_count_r_cg = new(bus_intr_brf_error_bad_fuse_intr_count_r);
+ soc_ifc_intr_brf_error_iccm_blocked_intr_count_r_cg intr_brf_error_iccm_blocked_intr_count_r_cg = new(bus_intr_brf_error_iccm_blocked_intr_count_r);
+ soc_ifc_intr_brf_error_mbox_ecc_unc_intr_count_r_cg intr_brf_error_mbox_ecc_unc_intr_count_r_cg = new(bus_intr_brf_error_mbox_ecc_unc_intr_count_r);
+ soc_ifc_intr_brf_error_wdt_timer1_timeout_intr_count_r_cg intr_brf_error_wdt_timer1_timeout_intr_count_r_cg = new(bus_intr_brf_error_wdt_timer1_timeout_intr_count_r);
+ soc_ifc_intr_brf_error_wdt_timer2_timeout_intr_count_r_cg intr_brf_error_wdt_timer2_timeout_intr_count_r_cg = new(bus_intr_brf_error_wdt_timer2_timeout_intr_count_r);
+ soc_ifc_intr_brf_notif_cmd_avail_intr_count_r_cg intr_brf_notif_cmd_avail_intr_count_r_cg = new(bus_intr_brf_notif_cmd_avail_intr_count_r);
+ soc_ifc_intr_brf_notif_mbox_ecc_cor_intr_count_r_cg intr_brf_notif_mbox_ecc_cor_intr_count_r_cg = new(bus_intr_brf_notif_mbox_ecc_cor_intr_count_r);
+ soc_ifc_intr_brf_notif_debug_locked_intr_count_r_cg intr_brf_notif_debug_locked_intr_count_r_cg = new(bus_intr_brf_notif_debug_locked_intr_count_r);
+ soc_ifc_intr_brf_notif_scan_mode_intr_count_r_cg intr_brf_notif_scan_mode_intr_count_r_cg = new(bus_intr_brf_notif_scan_mode_intr_count_r);
+ soc_ifc_intr_brf_notif_soc_req_lock_intr_count_r_cg intr_brf_notif_soc_req_lock_intr_count_r_cg = new(bus_intr_brf_notif_soc_req_lock_intr_count_r);
+ soc_ifc_intr_brf_notif_gen_in_toggle_intr_count_r_cg intr_brf_notif_gen_in_toggle_intr_count_r_cg = new(bus_intr_brf_notif_gen_in_toggle_intr_count_r);
+ soc_ifc_intr_brf_error_internal_intr_count_incr_r_cg intr_brf_error_internal_intr_count_incr_r_cg = new(bus_intr_brf_error_internal_intr_count_incr_r);
+ soc_ifc_intr_brf_error_inv_dev_intr_count_incr_r_cg intr_brf_error_inv_dev_intr_count_incr_r_cg = new(bus_intr_brf_error_inv_dev_intr_count_incr_r);
+ soc_ifc_intr_brf_error_cmd_fail_intr_count_incr_r_cg intr_brf_error_cmd_fail_intr_count_incr_r_cg = new(bus_intr_brf_error_cmd_fail_intr_count_incr_r);
+ soc_ifc_intr_brf_error_bad_fuse_intr_count_incr_r_cg intr_brf_error_bad_fuse_intr_count_incr_r_cg = new(bus_intr_brf_error_bad_fuse_intr_count_incr_r);
+ soc_ifc_intr_brf_error_iccm_blocked_intr_count_incr_r_cg intr_brf_error_iccm_blocked_intr_count_incr_r_cg = new(bus_intr_brf_error_iccm_blocked_intr_count_incr_r);
+ soc_ifc_intr_brf_error_mbox_ecc_unc_intr_count_incr_r_cg intr_brf_error_mbox_ecc_unc_intr_count_incr_r_cg = new(bus_intr_brf_error_mbox_ecc_unc_intr_count_incr_r);
+ soc_ifc_intr_brf_error_wdt_timer1_timeout_intr_count_incr_r_cg intr_brf_error_wdt_timer1_timeout_intr_count_incr_r_cg = new(bus_intr_brf_error_wdt_timer1_timeout_intr_count_incr_r);
+ soc_ifc_intr_brf_error_wdt_timer2_timeout_intr_count_incr_r_cg intr_brf_error_wdt_timer2_timeout_intr_count_incr_r_cg = new(bus_intr_brf_error_wdt_timer2_timeout_intr_count_incr_r);
+ soc_ifc_intr_brf_notif_cmd_avail_intr_count_incr_r_cg intr_brf_notif_cmd_avail_intr_count_incr_r_cg = new(bus_intr_brf_notif_cmd_avail_intr_count_incr_r);
+ soc_ifc_intr_brf_notif_mbox_ecc_cor_intr_count_incr_r_cg intr_brf_notif_mbox_ecc_cor_intr_count_incr_r_cg = new(bus_intr_brf_notif_mbox_ecc_cor_intr_count_incr_r);
+ soc_ifc_intr_brf_notif_debug_locked_intr_count_incr_r_cg intr_brf_notif_debug_locked_intr_count_incr_r_cg = new(bus_intr_brf_notif_debug_locked_intr_count_incr_r);
+ soc_ifc_intr_brf_notif_soc_req_lock_intr_count_incr_r_cg intr_brf_notif_soc_req_lock_intr_count_incr_r_cg = new(bus_intr_brf_notif_soc_req_lock_intr_count_incr_r);
// -------------------------------------------------------------------
// end SCRIPT_OUTPUT
// -------------------------------------------------------------------
-
endinterface
+
`endif
+
diff --git a/src/soc_ifc/rtl/mbox.sv b/src/soc_ifc/rtl/mbox.sv
index f86604b25..2413f6954 100644
--- a/src/soc_ifc/rtl/mbox.sv
+++ b/src/soc_ifc/rtl/mbox.sv
@@ -115,8 +115,6 @@ logic [MBOX_ECC_DATA_W-1:0] sram_rdata_cor_ecc;
logic sram_we;
logic mbox_protocol_sram_we;
logic mbox_protocol_sram_rd, mbox_protocol_sram_rd_f;
-logic sram_ecc_cor_we;
-logic [$clog2(DEPTH)-1:0] sram_ecc_cor_waddr;
logic dir_req_dv_q, dir_req_rd_phase;
logic dir_req_wr_ph;
logic mask_rdata;
@@ -273,6 +271,7 @@ always_comb begin : mbox_fsm_combo
mbox_fsm_ns = MBOX_IDLE;
rst_mbox_wrptr = 1;
rst_mbox_rdptr = 1;
+ mbox_protocol_error_nxt = '{default: 0};
end
end
MBOX_RDY_FOR_DLEN: begin
@@ -287,6 +286,7 @@ always_comb begin : mbox_fsm_combo
mbox_fsm_ns = MBOX_IDLE;
rst_mbox_wrptr = 1;
rst_mbox_rdptr = 1;
+ mbox_protocol_error_nxt = '{default: 0};
end
end
MBOX_RDY_FOR_DATA: begin
@@ -310,8 +310,11 @@ always_comb begin : mbox_fsm_combo
end
if (arc_FORCE_MBOX_UNLOCK) begin
mbox_fsm_ns = MBOX_IDLE;
+ inc_wrptr = 0;
+ inc_rdptr = 0;
rst_mbox_wrptr = 1;
rst_mbox_rdptr = 1;
+ mbox_protocol_error_nxt = '{default: 0};
end
end
//SoC set execute, data is for the uC
@@ -337,8 +340,11 @@ always_comb begin : mbox_fsm_combo
end
if (arc_FORCE_MBOX_UNLOCK) begin
mbox_fsm_ns = MBOX_IDLE;
+ inc_wrptr = 0;
+ inc_rdptr = 0;
rst_mbox_wrptr = 1;
rst_mbox_rdptr = 1;
+ mbox_protocol_error_nxt = '{default: 0};
end
end
//uC set execute, data is for the SoC
@@ -364,12 +370,15 @@ always_comb begin : mbox_fsm_combo
end
if (arc_FORCE_MBOX_UNLOCK) begin
mbox_fsm_ns = MBOX_IDLE;
+ inc_wrptr = 0;
+ inc_rdptr = 0;
rst_mbox_wrptr = 1;
rst_mbox_rdptr = 1;
+ mbox_protocol_error_nxt = '{default: 0};
end
end
MBOX_ERROR: begin
- mbox_protocol_error_nxt = '0;
+ mbox_protocol_error_nxt = '{default: 0};
if (arc_FORCE_MBOX_UNLOCK) begin
mbox_fsm_ns = MBOX_IDLE;
rst_mbox_wrptr = 1;
@@ -407,7 +416,6 @@ always_ff @(posedge clk or negedge rst_b) begin
mbox_rdptr <= '0;
mbox_rd_full <= '0;
mbox_protocol_sram_rd_f <= '0;
- sram_ecc_cor_waddr <= '0;
dlen_in_dws <= '0;
mbox_protocol_error <= '0;
sram_rd_ecc_en <= '0;
@@ -423,8 +431,6 @@ always_ff @(posedge clk or negedge rst_b) begin
mbox_protocol_sram_rd_f <= (mbox_protocol_sram_rd | mbox_protocol_sram_rd_f) ? mbox_protocol_sram_rd : mbox_protocol_sram_rd_f;
mbox_rd_full <= (inc_rdptr | rst_mbox_rdptr) ? mbox_rd_full_nxt : mbox_rd_full;
mbox_rd_valid_f <= (mbox_rd_valid | mbox_rd_valid_f) ? mbox_rd_valid : mbox_rd_valid_f;
- sram_ecc_cor_waddr <= /*dir_req_rd_phase ? sram_ecc_cor_waddr :*/
- sram_rdaddr;
dlen_in_dws <= latch_dlen_in_dws ? dlen_in_dws_nxt : dlen_in_dws;
mbox_protocol_error <= mbox_protocol_error_nxt;
@@ -449,16 +455,14 @@ always_comb req_hold = (dir_req_dv_q & ~req_data.write) |
(dir_req_dv & sha_sram_req_dv) |
(hwif_out.mbox_dataout.dataout.swacc & mbox_protocol_sram_rd_f);
-always_comb sha_sram_hold = sram_single_ecc_error/* || sram_ecc_cor_we*/;
+always_comb sha_sram_hold = 1'b0;
//SRAM interface
-always_comb sram_ecc_cor_we = sram_single_ecc_error; // TODO we probably want this to be a reg-stage to reduce combo logic SRAM -> rdata -> wdata -> SRAM
-always_comb sram_we = dir_req_wr_ph | mbox_protocol_sram_we | sram_ecc_cor_we;
+always_comb sram_we = dir_req_wr_ph | mbox_protocol_sram_we;
//align the direct address to a word
always_comb sram_rdaddr = dir_req_dv_q ? dir_req_addr :
rst_mbox_rdptr ? 'd0 : mbox_rdptr;
-always_comb sram_waddr = sram_ecc_cor_we ? sram_ecc_cor_waddr :
- dir_req_dv_q ? dir_req_addr : mbox_wrptr;
+always_comb sram_waddr = dir_req_dv_q ? dir_req_addr : mbox_wrptr;
//data phase after request for direct access
//We want to mask the read data for certain accesses
always_comb rdata = ({DATA_W{~mask_rdata}} & csr_rdata);
@@ -466,11 +470,11 @@ always_comb dir_rdata = dir_req_rd_phase ? sram_rdata_cor : '0;
always_comb begin: mbox_sram_inf
//read live on direct access, or when pointer has been incremented, for pre-load on read pointer reset, or ecc correction
- mbox_sram_req.cs = dir_req_dv_q | mbox_protocol_sram_we | mbox_protocol_sram_rd | sram_ecc_cor_we;
+ mbox_sram_req.cs = dir_req_dv_q | mbox_protocol_sram_we | mbox_protocol_sram_rd;
mbox_sram_req.we = sram_we;
mbox_sram_req.addr = sram_we ? sram_waddr : sram_rdaddr;
- mbox_sram_req.wdata.data = sram_ecc_cor_we ? sram_rdata_cor : sram_wdata;
- mbox_sram_req.wdata.ecc = sram_ecc_cor_we ? sram_rdata_cor_ecc : sram_wdata_ecc;
+ mbox_sram_req.wdata.data = sram_wdata;
+ mbox_sram_req.wdata.ecc = sram_wdata_ecc;
sram_rdata = mbox_sram_resp.rdata.data;
sram_rdata_ecc = mbox_sram_resp.rdata.ecc;
@@ -593,7 +597,7 @@ mbox_csr1(
.hwif_out(hwif_out)
);
-`CALIPTRA_ASSERT_MUTEX(ERR_MBOX_ACCESS_MUTEX, {dir_req_dv_q | mbox_protocol_sram_we | mbox_protocol_sram_rd | sram_ecc_cor_we}, clk, rst_b)
+`CALIPTRA_ASSERT_MUTEX(ERR_MBOX_ACCESS_MUTEX, {dir_req_dv_q , mbox_protocol_sram_we , mbox_protocol_sram_rd }, clk, rst_b)
`CALIPTRA_ASSERT_MUTEX(ERR_MBOX_DIR_SHA_COLLISION, {dir_req_dv, sha_sram_req_dv}, clk, rst_b)
`CALIPTRA_ASSERT_NEVER(ERR_MBOX_DIR_REQ_FROM_SOC, (dir_req_dv & req_data.soc_req), clk, rst_b)
diff --git a/src/soc_ifc/rtl/soc_ifc_pkg.sv b/src/soc_ifc/rtl/soc_ifc_pkg.sv
index f71430ec2..8934bdb55 100644
--- a/src/soc_ifc/rtl/soc_ifc_pkg.sv
+++ b/src/soc_ifc/rtl/soc_ifc_pkg.sv
@@ -70,6 +70,14 @@ package soc_ifc_pkg;
parameter DMI_REG_CPTRA_DBG_MANUF_SERVICE_REG = 7'h60;
parameter DMI_REG_BOOTFSM_GO = 7'h61;
+ // This parameter describes the hard-coded implementation in the BOOT FSM
+ // that results in noncore reset assertion being delayed from the soft reset
+ // (cptra_rst_b) by some integer number of clock cycles, due to synchronization
+ // stages and the rst window signaling.
+ // This is useful in validation environments for controlling the predicted
+ // timing in a reset event.
+ parameter SOC_IFC_CPTRA_RST_NONCORE_RST_DELAY = 4;
+
//BOOT FSM
typedef enum logic [2:0] {
BOOT_IDLE = 3'b000,
diff --git a/src/soc_ifc/stimulus/tests/directed/fuse_reg_perm_test.yml b/src/soc_ifc/stimulus/tests/directed/fuse_reg_perm_test.yml
index 768ed209f..014e9b8eb 100644
--- a/src/soc_ifc/stimulus/tests/directed/fuse_reg_perm_test.yml
+++ b/src/soc_ifc/stimulus/tests/directed/fuse_reg_perm_test.yml
@@ -17,4 +17,5 @@ plusargs:
- +SOC_IFC_TEST='fuse_reg_perm_test'
testname: fuse_reg_perm_test
-seed: ${PLAYBOOK_RANDOM_SEED}
+# seed: ${PLAYBOOK_RANDOM_SEED}
+seed: 1692834441
diff --git a/src/soc_ifc/stimulus/tests/directed/soc_reg_intrblk_test.yml b/src/soc_ifc/stimulus/tests/directed/soc_reg_intrblk_test.yml
index 3b04429ef..a77dad5af 100644
--- a/src/soc_ifc/stimulus/tests/directed/soc_reg_intrblk_test.yml
+++ b/src/soc_ifc/stimulus/tests/directed/soc_reg_intrblk_test.yml
@@ -18,3 +18,4 @@ plusargs:
testname: soc_reg_intrblk_test
seed: ${PLAYBOOK_RANDOM_SEED}
+# seed: 1692153169
diff --git a/src/soc_ifc/tb/fuse_reg_pauser_test.svh b/src/soc_ifc/tb/fuse_reg_pauser_test.svh
index d8714de07..6a8a979fa 100644
--- a/src/soc_ifc/tb/fuse_reg_pauser_test.svh
+++ b/src/soc_ifc/tb/fuse_reg_pauser_test.svh
@@ -15,9 +15,6 @@
//======================================================================
-`define FORLOOP_COMB(x) always_comb for (int j = 0; j < x; j++)
-`define STR_RMPFX(astr, bstr) astr.substr(bstr.len(), astr.len() - 1).atoi()
-
// Declarations for internal signal probing
logic [31:0] fuse_uds_seed [0:11];
@@ -83,6 +80,8 @@ task fuse_reg_pauser_test;
init_sim();
reset_dut();
+ wait (ready_for_fuses);
+
//-------------------------------------------------------------------------------------------
print_banner("1a. Default pauser and unlocked. APB write to registers, check values");
tphase = "1a";
diff --git a/src/soc_ifc/tb/fuse_reg_perm_test.svh b/src/soc_ifc/tb/fuse_reg_perm_test.svh
index fff476837..88b60898b 100644
--- a/src/soc_ifc/tb/fuse_reg_perm_test.svh
+++ b/src/soc_ifc/tb/fuse_reg_perm_test.svh
@@ -52,11 +52,13 @@ any subsequent writes to a fuse register will be dropped unless
init_sim();
reset_dut();
+ wait(ready_for_fuses);
// -----------------------------------------------------------------
// PHASE 1. Normal sequence
// -----------------------------------------------------------------
$display ("1a. APB write twice to registers, lock fuses and attempt to modify\n");
+ tphase = "1a";
write_regs(SET_APB, fuse_regnames, 0, 3); // effect changes
repeat (5) @(posedge clk_tb);
@@ -74,6 +76,7 @@ any subsequent writes to a fuse register will be dropped unless
repeat (5) @(posedge clk_tb);
$display ("\n1b. Following writes should have no effect on locked state -- which is still set!\n");
+ tphase = "1b";
sb.del_all();
@@ -88,11 +91,14 @@ any subsequent writes to a fuse register will be dropped unless
// -----------------------------------------------------------------
// PHASE 2. Perform Cold Reset and Repeat APB Write & Read from 1a
// -----------------------------------------------------------------
+ $display ("\n2a. Write to registers after cold boot and check back writes");
+ tphase = "2a";
+
reset_dut(); // expect to be clearing CPTRA_FUSE_WR_DONE effect
reset_exp_data();
sb.del_all();
-
- $display ("\n2a. Write to registers after cold boot and check back writes");
+ wait(ready_for_fuses);
+ @(posedge clk_tb);
write_regs(SET_APB, fuse_regnames, 0, 3);
read_regs(GET_APB, fuse_regnames, 0, 3);
@@ -107,9 +113,12 @@ any subsequent writes to a fuse register will be dropped unless
// PHASE 3. Perform Warm Reset, read values & Repeat APB Write & Read from 1a
// -----------------------------------------------------------------
$display ("\n3a. Perform a warm reset then repeat steps 1a (just APB)");
+ tphase = "3a";
warm_reset_dut();
warm_reset_exp_data();
+ wait(ready_for_fuses);
+ @(posedge clk_tb);
read_regs(GET_APB, fuse_regnames, 0, 3); // should be old sticky values
sb.del_all();
diff --git a/src/soc_ifc/tb/soc_ifc_tb.sv b/src/soc_ifc/tb/soc_ifc_tb.sv
index 808760bc7..7a50704d0 100644
--- a/src/soc_ifc/tb/soc_ifc_tb.sv
+++ b/src/soc_ifc/tb/soc_ifc_tb.sv
@@ -31,6 +31,10 @@ import "DPI-C" function string getenv(input string env_name);
`define REG_HIER_BOOT_FSM_PS dut.boot_fsm_ps
`define REG_HIER_PFX dut.i_soc_ifc_reg.field_storage
+`define FORLOOP_COMB(x) always_comb for (int j = 0; j < x; j++)
+`define STR_RMPFX(astr, bstr) astr.substr(bstr.len(), astr.len() - 1).atoi()
+
+
module soc_ifc_tb
import soc_ifc_pkg::*;
import soc_ifc_tb_pkg::*;
@@ -169,10 +173,13 @@ module soc_ifc_tb
bit reg_sva_off = 1'b1; // Enable only during register assertion checks
+ logic [APB_DATA_WIDTH-1:0] prdata_o_latched;
-
-
+ always @(negedge clk_tb) begin
+ prdata_o_latched <= prdata_o_tb;
+ end
+
always_comb begin
mbox_sram_cs = mbox_sram_req.cs;
mbox_sram_we = mbox_sram_req.we;
@@ -432,11 +439,14 @@ module soc_ifc_tb
begin
$display("*** Toggle reset.");
- reset_generic_input_wires(-1, -1);
+ set_generic_input_wires(-1, -1);
cptra_pwrgood_tb = '0;
cptra_rst_b_tb = 0;
+ set_initval("CPTRA_GENERIC_INPUT_WIRES0", generic_input_wires0); // The init val will take effect
+ set_initval("CPTRA_GENERIC_INPUT_WIRES1", generic_input_wires1); // after reset deassertion
+
repeat (5) @(posedge clk_tb);
socregs.unlock_fuses();
@@ -446,6 +456,7 @@ module soc_ifc_tb
repeat (5) @(posedge clk_tb);
cptra_rst_b_tb = 1;
+ repeat (5) @(posedge clk_tb);
$display("");
end
endtask // reset_dut
@@ -460,7 +471,7 @@ module soc_ifc_tb
begin
$display("*** Perform warm reset. ***");
- reset_generic_input_wires(-1, -1);
+ set_generic_input_wires(-1, -1);
reset_flow_status();
cptra_rst_b_tb = 0;
@@ -468,6 +479,7 @@ module soc_ifc_tb
repeat (5) @(posedge clk_tb);
cptra_rst_b_tb = 1;
+ repeat (5) @(posedge clk_tb);
$display("");
end
endtask // reset_dut
@@ -831,25 +843,21 @@ module soc_ifc_tb
//----------------------------------------------------------------
- // reset_generic_input_wires()
+ // set_generic_input_wires()
//
// sets the generic_input_wires to a predetermined or random value
//----------------------------------------------------------------
- task reset_generic_input_wires(input int v0, int v1);
+ task set_generic_input_wires(input int v0, int v1);
begin
generic_input_wires0 = (v0 < 0) ? $urandom() : v0;
generic_input_wires1 = (v1 < 0) ? $urandom() : v1;
repeat (2) @(posedge clk_tb);
- set_initval("CPTRA_GENERIC_INPUT_WIRES0", generic_input_wires0_q);
- set_initval("CPTRA_GENERIC_INPUT_WIRES1", generic_input_wires1_q);
update_CPTRA_GENERIC_INPUT_WIRES(generic_input_wires0_q, 1'b0);
update_CPTRA_GENERIC_INPUT_WIRES(generic_input_wires1_q, 1'b1);
-
- @(posedge clk_tb);
end
- endtask
+ endtask // set_generic_input_wires
//----------------------------------------------------------------
@@ -1262,12 +1270,14 @@ module soc_ifc_tb
if (modifier == GET_AHB) begin
read_single_word_ahb(addr);
valid_hrdata = addr[2] ? hrdata_o_tb[`AHB64_HI] :hrdata_o_tb[`AHB64_LO];
- $display(" Read over AHB: addr = %-40s (0x%08x), data = 0x%08x", rname, addr, valid_hrdata);
+ $display(" Read over AHB: addr = %-40s (0x%08x), data = 0x%08x on cycle %08d", rname, addr, valid_hrdata, cycle_ctr);
rdtrans.update(addr, valid_hrdata, tid);
end else if (modifier == GET_APB) begin
read_single_word_apb(addr);
- $display(" Read over APB: addr = %-40s (0x%08x), data = 0x%08x", rname, addr, prdata_o_tb);
- rdtrans.update(addr, prdata_o_tb, tid);
+ // $display(" Read over APB: addr = %-40s (0x%08x), data = 0x%08x at time %12t (cycle %08d)", rname, addr, prdata_o_latched, $realtime, cycle_ctr); // used to be prdata_o_tb
+ $display(" Read over APB: addr = %-40s (0x%08x), data = 0x%08x on cycle %08d", rname, addr, prdata_o_tb, cycle_ctr); // used to be prdata_o_tb
+ // rdtrans.update(addr, prdata_o_latched, tid); // used to be prdata_o_tb
+ rdtrans.update(addr, prdata_o_tb, tid);
end else
$error("TB ERROR. Unsupported access modifier %s", modifier.name());
diff --git a/src/soc_ifc/tb/soc_ifc_tb_pkg.sv b/src/soc_ifc/tb/soc_ifc_tb_pkg.sv
index 9150d838d..4115bdd98 100644
--- a/src/soc_ifc/tb/soc_ifc_tb_pkg.sv
+++ b/src/soc_ifc/tb/soc_ifc_tb_pkg.sv
@@ -104,6 +104,10 @@ package soc_ifc_tb_pkg;
"CPTRA_GENERIC_INPUT_WIRES" : 2,
"CPTRA_GENERIC_OUTPUT_WIRES" : 2,
"CPTRA_FW_REV_ID" : 2,
+ "CPTRA_WDT_TIMER1_TIMEOUT_PERIOD" : 2,
+ "CPTRA_WDT_TIMER2_TIMEOUT_PERIOD" : 2,
+ "CPTRA_WDT_CFG" : 2,
+ "CPTRA_RSVD_REG" : 2,
"FUSE_UDS_SEED" : 12,
"FUSE_FIELD_ENTROPY" : 8,
"FUSE_KEY_MANIFEST_PK_HASH" : 12,
@@ -117,112 +121,118 @@ package soc_ifc_tb_pkg;
// ** NOTE. INTR_BRF (== INTR_BLOCK_RF) registers are NOT explictly tested. Only provided to check for undefined ranges, and for future **
//
- // Identifier Base Addr Offset // Offset Description
+ // Identifier Base Addr Offset // Offset Description
word_addr_t _soc_register_dict [string] = {
- "CPTRA_HW_ERROR_FATAL" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_HW_ERROR_FATAL, // 0x000 Hardware Error Fatal
- "CPTRA_HW_ERROR_NON_FATAL" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL, // 0x004 Hardware Error Non-Fatal
- "CPTRA_FW_ERROR_FATAL" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_FW_ERROR_FATAL, // 0x008 Firmware Error Fatal
- "CPTRA_FW_ERROR_NON_FATAL" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_FW_ERROR_NON_FATAL, // 0x00c Firmware Error Non-Fatal
- "CPTRA_HW_ERROR_ENC" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_HW_ERROR_ENC, // 0x010 Hardware Error Encoding
- "CPTRA_FW_ERROR_ENC" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_FW_ERROR_ENC, // 0x014 Firmware Error Encoding
- "CPTRA_FW_EXTENDED_ERROR_INFO" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_0, // 0x018 [8] Firmware Extended Error Information
- "CPTRA_BOOT_STATUS" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_BOOT_STATUS, // 0x038 Boot Status
- "CPTRA_FLOW_STATUS" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_FLOW_STATUS, // 0x03c Flow Status
- "CPTRA_RESET_REASON" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_RESET_REASON, // 0x040 Reset Reason
- "CPTRA_SECURITY_STATE" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_SECURITY_STATE, // 0x044 Security State
- "CPTRA_MBOX_VALID_PAUSER" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_0, // 0x048 [5] Valid User Registers
- "CPTRA_MBOX_PAUSER_LOCK" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_0, // 0x05c [5] Valid User Register Lock
- "CPTRA_TRNG_VALID_PAUSER" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_TRNG_VALID_PAUSER, // 0x070 Valid User for TRNG
- "CPTRA_TRNG_PAUSER_LOCK" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_TRNG_PAUSER_LOCK, // 0x074 Valid User for TRNG PAUSER Lock
- "CPTRA_TRNG_DATA" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_TRNG_DATA_0, // 0x078 [12] TRNG Data
- "CPTRA_TRNG_STATUS" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_TRNG_STATUS, // 0x0a8 TRNG Status
- "CPTRA_FUSE_WR_DONE" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_FUSE_WR_DONE, // 0x0ac Fuse Write Done
- "CPTRA_TIMER_CONFIG" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_TIMER_CONFIG, // 0x0b0 Timer Config
- "CPTRA_BOOTFSM_GO" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_BOOTFSM_GO, // 0x0b4 BOOTFSM GO
- "CPTRA_DBG_MANUF_SERVICE_REG" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_DBG_MANUF_SERVICE_REG, // 0x0b8 DEBUG & MANUF SERVICE REG
- "CPTRA_CLK_GATING_EN" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_CLK_GATING_EN, // 0x0bc Global Caliptra Clk gating enable
- "CPTRA_GENERIC_INPUT_WIRES" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0, // 0x0c0 [2] Generic Input Wires
- "CPTRA_GENERIC_OUTPUT_WIRES" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_0, // 0x0c8 [2] Generic Output Wires
- "CPTRA_HW_REV_ID" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_HW_REV_ID, // 0x0d0 Caliptra HW RevID
- "CPTRA_FW_REV_ID" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_FW_REV_ID_0, // 0x0d4 Caliptra FW RevID
- "CPTRA_HW_CONFIG" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_HW_CONFIG, // 0x0dc Caliptra HW Config
- "CPTRA_WDT_TIMER1_EN" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_WDT_TIMER1_EN, // 0x0e0 Caliptra WDT Timer1 EN register
- "CPTRA_WDT_TIMER1_CTRL" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL, // 0x0e4 Caliptra WDT Timer1 CTRL register
- "CPTRA_WDT_TIMER1_TIMEOUT_PERIOD" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0, // 0x0e8 [2] Caliptra WDT Timer1 Timeout Period register
- "CPTRA_WDT_TIMER2_EN" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_WDT_TIMER2_EN, // 0x0f0 Caliptra WDT Timer2 EN register
- "CPTRA_WDT_TIMER2_CTRL" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL, // 0x0f4 Caliptra WDT Timer2 CTRL register
- "CPTRA_WDT_TIMER2_TIMEOUT_PERIOD" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0, // 0x0f8 [2] Caliptra WDT Timer2 Timeout Period register
- "CPTRA_WDT_STATUS" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_WDT_STATUS, // 0x100 Caliptra WDT STATUS register
- "CPTRA_FUSE_VALID_PAUSER" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_FUSE_VALID_PAUSER, // 0x104 Valid User for FUSE
- "CPTRA_FUSE_PAUSER_LOCK" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_FUSE_PAUSER_LOCK, // 0x108 Valid User for FUSE PAUSER Lock
- // 0x10c..0x1fc
- "FUSE_UDS_SEED" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_UDS_SEED_0, // 0x200 [12] Unique Device Secret
- "FUSE_FIELD_ENTROPY" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_FIELD_ENTROPY_0, // 0x230 [8] Field Entropy
- "FUSE_KEY_MANIFEST_PK_HASH" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_0, // 0x250 [12] -
- "FUSE_KEY_MANIFEST_PK_HASH_MASK" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK, // 0x280 -
- "FUSE_OWNER_PK_HASH" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_OWNER_PK_HASH_0, // 0x284 [12] -
- "FUSE_FMC_KEY_MANIFEST_SVN" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_FMC_KEY_MANIFEST_SVN, // 0x2b4 -
- "FUSE_RUNTIME_SVN" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_RUNTIME_SVN_0, // 0x2b8 [4] -
- "FUSE_ANTI_ROLLBACK_DISABLE" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_ANTI_ROLLBACK_DISABLE, // 0x2c8 -
- "FUSE_IDEVID_CERT_ATTR" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_0, // 0x2cc [24] -
- "FUSE_IDEVID_MANUF_HSM_ID" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_0, // 0x32c [4] -
- "FUSE_LIFE_CYCLE" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_LIFE_CYCLE, // 0x33c -
- "FUSE_LMS_VERIFY" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_LMS_VERIFY, // 0x340 -
- "FUSE_LMS_REVOCATION" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_LMS_REVOCATION, // 0x344 -
- // 0x348..0x5fc
- "INTERNAL_OBF_KEY" : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_OBF_KEY_0, // 0x600 [8] De-Obfuscation Key
- "INTERNAL_ICCM_LOCK" : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_ICCM_LOCK, // 0x620 ICCM Lock
- "INTERNAL_FW_UPDATE_RESET" : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET, // 0x624 FW Update Reset
- "INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES" : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES, // 0x628 FW Update Reset Wait Cycles
- "INTERNAL_NMI_VECTOR" : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_NMI_VECTOR, // 0x62c NMI Vector
- "INTERNAL_HW_ERROR_FATAL_MASK" : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK, // 0x630 Hardware Error Fatal Mask
- "INTERNAL_HW_ERROR_NON_FATAL_MASK" : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK, // 0x634 Hardware Error Non-Fatal Mask
- "INTERNAL_FW_ERROR_FATAL_MASK" : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_FW_ERROR_FATAL_MASK, // 0x638 Firmware Error Fatal Mask
- "INTERNAL_FW_ERROR_NON_FATAL_MASK" : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_FW_ERROR_NON_FATAL_MASK, // 0x63C Firmware Error Non-Fatal Mask 0
- "INTERNAL_RV_MTIME_L" : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_RV_MTIME_L, // 0x640 mtime low
- "INTERNAL_RV_MTIME_H" : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_RV_MTIME_H, // 0x644 mtime high
- "INTERNAL_RV_MTIMECMP_L" : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_RV_MTIMECMP_L, // 0x648 mtimecmp low
- "INTERNAL_RV_MTIMECMP_H" : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_RV_MTIMECMP_H, // 0x64C mtimecmp high
+ "CPTRA_HW_ERROR_FATAL" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_HW_ERROR_FATAL, // 0x000 Hardware Error Fatal
+ "CPTRA_HW_ERROR_NON_FATAL" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL, // 0x004 Hardware Error Non-Fatal
+ "CPTRA_FW_ERROR_FATAL" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_FW_ERROR_FATAL, // 0x008 Firmware Error Fatal
+ "CPTRA_FW_ERROR_NON_FATAL" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_FW_ERROR_NON_FATAL, // 0x00c Firmware Error Non-Fatal
+ "CPTRA_HW_ERROR_ENC" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_HW_ERROR_ENC, // 0x010 Hardware Error Encoding
+ "CPTRA_FW_ERROR_ENC" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_FW_ERROR_ENC, // 0x014 Firmware Error Encoding
+ "CPTRA_FW_EXTENDED_ERROR_INFO" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_0, // 0x018 [8] Firmware Extended Error Information
+ "CPTRA_BOOT_STATUS" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_BOOT_STATUS, // 0x038 Boot Status
+ "CPTRA_FLOW_STATUS" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_FLOW_STATUS, // 0x03c Flow Status
+ "CPTRA_RESET_REASON" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_RESET_REASON, // 0x040 Reset Reason
+ "CPTRA_SECURITY_STATE" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_SECURITY_STATE, // 0x044 Security State
+ "CPTRA_MBOX_VALID_PAUSER" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_0, // 0x048 [5] Valid User Registers
+ "CPTRA_MBOX_PAUSER_LOCK" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_0, // 0x05c [5] Valid User Register Lock
+ "CPTRA_TRNG_VALID_PAUSER" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_TRNG_VALID_PAUSER, // 0x070 Valid User for TRNG
+ "CPTRA_TRNG_PAUSER_LOCK" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_TRNG_PAUSER_LOCK, // 0x074 Valid User for TRNG PAUSER Lock
+ "CPTRA_TRNG_DATA" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_TRNG_DATA_0, // 0x078 [12] TRNG Data
+ "CPTRA_TRNG_CTRL" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_TRNG_CTRL, // 0x0a8 TRNG Ctrl
+ "CPTRA_TRNG_STATUS" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_TRNG_STATUS, // 0x0ac TRNG Status
+ "CPTRA_FUSE_WR_DONE" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_FUSE_WR_DONE, // 0x0b0 Fuse Write Done
+ "CPTRA_TIMER_CONFIG" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_TIMER_CONFIG, // 0x0b4 Timer Config
+ "CPTRA_BOOTFSM_GO" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_BOOTFSM_GO, // 0x0b8 BOOTFSM GO
+ "CPTRA_DBG_MANUF_SERVICE_REG" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_DBG_MANUF_SERVICE_REG, // 0x0bc DEBUG & MANUF SERVICE REG
+ "CPTRA_CLK_GATING_EN" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_CLK_GATING_EN, // 0x0c0 Global Caliptra Clk gating enable
+ "CPTRA_GENERIC_INPUT_WIRES" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0, // 0x0c8 [2] Generic Input Wires
+ "CPTRA_GENERIC_OUTPUT_WIRES" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_0, // 0x0d0 [2] Generic Output Wires
+ "CPTRA_HW_REV_ID" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_HW_REV_ID, // 0x0d4 Caliptra HW RevID
+ "CPTRA_FW_REV_ID" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_FW_REV_ID_0, // 0x0dc Caliptra FW RevID
+ "CPTRA_HW_CONFIG" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_HW_CONFIG, // 0x0e0 Caliptra HW Config
+ "CPTRA_WDT_TIMER1_EN" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_WDT_TIMER1_EN, // 0x0e4 Caliptra WDT Timer1 EN register
+ "CPTRA_WDT_TIMER1_CTRL" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL, // 0x0e8 Caliptra WDT Timer1 CTRL register
+ "CPTRA_WDT_TIMER1_TIMEOUT_PERIOD" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0, // 0x0f0 [2] Caliptra WDT Timer1 Timeout Period register
+ "CPTRA_WDT_TIMER2_EN" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_WDT_TIMER2_EN, // 0x0f4 Caliptra WDT Timer2 EN register
+ "CPTRA_WDT_TIMER2_CTRL" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL, // 0x0f8 Caliptra WDT Timer2 CTRL register
+ "CPTRA_WDT_TIMER2_TIMEOUT_PERIOD" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0, // 0x100 [2] Caliptra WDT Timer2 Timeout Period register
+ "CPTRA_WDT_STATUS" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_WDT_STATUS, // 0x104 Caliptra WDT STATUS register
+ "CPTRA_FUSE_VALID_PAUSER" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_FUSE_VALID_PAUSER, // 0x108 Valid User for FUSE
+ "CPTRA_FUSE_PAUSER_LOCK" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_FUSE_PAUSER_LOCK, // 0x10c Valid User for FUSE PAUSER Lock
+ "CPTRA_WDT_CFG" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_WDT_CFG_0, // 0x110 [2] Caliptra WDT1 Config
+ "CPTRA_ITRNG_ENTROPY_CONFIG_0" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0, // 0x118 Caliptra iTRNG Entropy Configuration 0
+ "CPTRA_ITRNG_ENTROPY_CONFIG_1" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1, // 0x11c Caliptra iTRNG Entropy Configuration 1
+ "CPTRA_RSVD_REG" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_RSVD_REG_0, // 0x120 [2] Caliptra Reserved Registers
+ // 0x128..0x1fc
+ "FUSE_UDS_SEED" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_UDS_SEED_0, // 0x200 [12] Unique Device Secret
+ "FUSE_FIELD_ENTROPY" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_FIELD_ENTROPY_0, // 0x230 [8] Field Entropy
+ "FUSE_KEY_MANIFEST_PK_HASH" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_0, // 0x250 [12] -
+ "FUSE_KEY_MANIFEST_PK_HASH_MASK" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK, // 0x280 -
+ "FUSE_OWNER_PK_HASH" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_OWNER_PK_HASH_0, // 0x284 [12] -
+ "FUSE_FMC_KEY_MANIFEST_SVN" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_FMC_KEY_MANIFEST_SVN, // 0x2b4 -
+ "FUSE_RUNTIME_SVN" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_RUNTIME_SVN_0, // 0x2b8 [4] -
+ "FUSE_ANTI_ROLLBACK_DISABLE" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_ANTI_ROLLBACK_DISABLE, // 0x2c8 -
+ "FUSE_IDEVID_CERT_ATTR" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_0, // 0x2cc [24] -
+ "FUSE_IDEVID_MANUF_HSM_ID" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_0, // 0x32c [4] -
+ "FUSE_LIFE_CYCLE" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_LIFE_CYCLE, // 0x33c -
+ "FUSE_LMS_VERIFY" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_LMS_VERIFY, // 0x340 -
+ "FUSE_LMS_REVOCATION" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_LMS_REVOCATION, // 0x344 -
+ "FUSE_SOC_STEPPING_ID" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_SOC_STEPPING_ID, // 0x348 -
+ // 0x34c..0x5fc
+ "INTERNAL_OBF_KEY" : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_OBF_KEY_0, // 0x600 [8] De-Obfuscation Key
+ "INTERNAL_ICCM_LOCK" : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_ICCM_LOCK, // 0x620 ICCM Lock
+ "INTERNAL_FW_UPDATE_RESET" : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET, // 0x624 FW Update Reset
+ "INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES" : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES, // 0x628 FW Update Reset Wait Cycles
+ "INTERNAL_NMI_VECTOR" : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_NMI_VECTOR, // 0x62c NMI Vector
+ "INTERNAL_HW_ERROR_FATAL_MASK" : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK, // 0x630 Hardware Error Fatal Mask
+ "INTERNAL_HW_ERROR_NON_FATAL_MASK" : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK, // 0x634 Hardware Error Non-Fatal Mask
+ "INTERNAL_FW_ERROR_FATAL_MASK" : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_FW_ERROR_FATAL_MASK, // 0x638 Firmware Error Fatal Mask
+ "INTERNAL_FW_ERROR_NON_FATAL_MASK" : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_FW_ERROR_NON_FATAL_MASK, // 0x63C Firmware Error Non-Fatal Mask 0
+ "INTERNAL_RV_MTIME_L" : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_RV_MTIME_L, // 0x640 mtime low
+ "INTERNAL_RV_MTIME_H" : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_RV_MTIME_H, // 0x644 mtime high
+ "INTERNAL_RV_MTIMECMP_L" : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_RV_MTIMECMP_L, // 0x648 mtimecmp low
+ "INTERNAL_RV_MTIMECMP_H" : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_RV_MTIMECMP_H, // 0x64C mtimecmp high
// 0x650..0x7fc
// SoC IFC Interrupt Block Register
- "INTR_BRF_GLOBAL_INTR_EN_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R, // 0x800
- "INTR_BRF_ERROR_INTR_EN_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R, // 0x804
- "INTR_BRF_NOTIF_INTR_EN_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R, // 0x808
- "INTR_BRF_ERROR_GLOBAL_INTR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R, // 0x80c
- "INTR_BRF_NOTIF_GLOBAL_INTR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R, // 0x810
- "INTR_BRF_ERROR_INTERNAL_INTR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R, // 0x814
- "INTR_BRF_NOTIF_INTERNAL_INTR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R, // 0x818
- "INTR_BRF_ERROR_INTR_TRIG_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R, // 0x81c
- "INTR_BRF_NOTIF_INTR_TRIG_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R, // 0x820
+ "INTR_BRF_GLOBAL_INTR_EN_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R, // 0x800
+ "INTR_BRF_ERROR_INTR_EN_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R, // 0x804
+ "INTR_BRF_NOTIF_INTR_EN_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R, // 0x808
+ "INTR_BRF_ERROR_GLOBAL_INTR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R, // 0x80c
+ "INTR_BRF_NOTIF_GLOBAL_INTR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R, // 0x810
+ "INTR_BRF_ERROR_INTERNAL_INTR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R, // 0x814
+ "INTR_BRF_NOTIF_INTERNAL_INTR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R, // 0x818
+ "INTR_BRF_ERROR_INTR_TRIG_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R, // 0x81c
+ "INTR_BRF_NOTIF_INTR_TRIG_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R, // 0x820
// 0x824..0x8fc
- "INTR_BRF_ERROR_INTERNAL_INTR_COUNT_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_R, // 0x900
- "INTR_BRF_ERROR_INV_DEV_INTR_COUNT_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INV_DEV_INTR_COUNT_R, // 0x904
- "INTR_BRF_ERROR_CMD_FAIL_INTR_COUNT_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_CMD_FAIL_INTR_COUNT_R, // 0x908
- "INTR_BRF_ERROR_BAD_FUSE_INTR_COUNT_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_BAD_FUSE_INTR_COUNT_R, // 0x90c
- "INTR_BRF_ERROR_ICCM_BLOCKED_INTR_COUNT_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_ICCM_BLOCKED_INTR_COUNT_R, // 0x910
- "INTR_BRF_ERROR_MBOX_ECC_UNC_INTR_COUNT_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_MBOX_ECC_UNC_INTR_COUNT_R, // 0x914
- "INTR_BRF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_R": SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_R,// 0x918
- "INTR_BRF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_R": SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_R,// 0x91c
+ "INTR_BRF_ERROR_INTERNAL_INTR_COUNT_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_R, // 0x900
+ "INTR_BRF_ERROR_INV_DEV_INTR_COUNT_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INV_DEV_INTR_COUNT_R, // 0x904
+ "INTR_BRF_ERROR_CMD_FAIL_INTR_COUNT_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_CMD_FAIL_INTR_COUNT_R, // 0x908
+ "INTR_BRF_ERROR_BAD_FUSE_INTR_COUNT_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_BAD_FUSE_INTR_COUNT_R, // 0x90c
+ "INTR_BRF_ERROR_ICCM_BLOCKED_INTR_COUNT_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_ICCM_BLOCKED_INTR_COUNT_R, // 0x910
+ "INTR_BRF_ERROR_MBOX_ECC_UNC_INTR_COUNT_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_MBOX_ECC_UNC_INTR_COUNT_R, // 0x914
+ "INTR_BRF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_R": SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_R, // 0x918
+ "INTR_BRF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_R": SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_R, // 0x91c
// 0x920..0x97c
- "INTR_BRF_NOTIF_CMD_AVAIL_INTR_COUNT_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_CMD_AVAIL_INTR_COUNT_R, // 0x980
- "INTR_BRF_NOTIF_MBOX_ECC_COR_INTR_COUNT_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_R, // 0x984
- "INTR_BRF_NOTIF_DEBUG_LOCKED_INTR_COUNT_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_R, // 0x988
- "INTR_BRF_NOTIF_SCAN_MODE_INTR_COUNT_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_R, // 0x98c
- "INTR_BRF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_R, // 0x990
- "INTR_BRF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_R, // 0x994
+ "INTR_BRF_NOTIF_CMD_AVAIL_INTR_COUNT_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_CMD_AVAIL_INTR_COUNT_R, // 0x980
+ "INTR_BRF_NOTIF_MBOX_ECC_COR_INTR_COUNT_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_R, // 0x984
+ "INTR_BRF_NOTIF_DEBUG_LOCKED_INTR_COUNT_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_R, // 0x988
+ "INTR_BRF_NOTIF_SCAN_MODE_INTR_COUNT_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_R, // 0x98c
+ "INTR_BRF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_R, // 0x990
+ "INTR_BRF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_R, // 0x994
// 0x998..0x9fc
- "INTR_BRF_ERROR_INTERNAL_INTR_COUNT_INCR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R, // 0xa00
- "INTR_BRF_ERROR_INV_DEV_INTR_COUNT_INCR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INV_DEV_INTR_COUNT_INCR_R, // 0xa04
- "INTR_BRF_ERROR_CMD_FAIL_INTR_COUNT_INCR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_CMD_FAIL_INTR_COUNT_INCR_R, // 0xa08
- "INTR_BRF_ERROR_BAD_FUSE_INTR_COUNT_INCR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_BAD_FUSE_INTR_COUNT_INCR_R, // 0xa0c
- "INTR_BRF_ERROR_ICCM_BLOCKED_INTR_COUNT_INCR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_ICCM_BLOCKED_INTR_COUNT_INCR_R, // 0xa10
- "INTR_BRF_ERROR_MBOX_ECC_UNC_INTR_COUNT_INCR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_MBOX_ECC_UNC_INTR_COUNT_INCR_R, // 0xa14
+ "INTR_BRF_ERROR_INTERNAL_INTR_COUNT_INCR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R, // 0xa00
+ "INTR_BRF_ERROR_INV_DEV_INTR_COUNT_INCR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INV_DEV_INTR_COUNT_INCR_R, // 0xa04
+ "INTR_BRF_ERROR_CMD_FAIL_INTR_COUNT_INCR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_CMD_FAIL_INTR_COUNT_INCR_R, // 0xa08
+ "INTR_BRF_ERROR_BAD_FUSE_INTR_COUNT_INCR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_BAD_FUSE_INTR_COUNT_INCR_R, // 0xa0c
+ "INTR_BRF_ERROR_ICCM_BLOCKED_INTR_COUNT_INCR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_ICCM_BLOCKED_INTR_COUNT_INCR_R, // 0xa10
+ "INTR_BRF_ERROR_MBOX_ECC_UNC_INTR_COUNT_INCR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_MBOX_ECC_UNC_INTR_COUNT_INCR_R, // 0xa14
"INTR_BRF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_INCR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_INCR_R, // 0xa18
"INTR_BRF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_INCR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_INCR_R, // 0xa1c
- "INTR_BRF_NOTIF_CMD_AVAIL_INTR_COUNT_INCR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_CMD_AVAIL_INTR_COUNT_INCR_R, // 0xa20
- "INTR_BRF_NOTIF_MBOX_ECC_COR_INTR_COUNT_INCR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_INCR_R, // 0xa24
- "INTR_BRF_NOTIF_DEBUG_LOCKED_INTR_COUNT_INCR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_INCR_R, // 0xa28
- "INTR_BRF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R, // 0xa2c
+ "INTR_BRF_NOTIF_CMD_AVAIL_INTR_COUNT_INCR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_CMD_AVAIL_INTR_COUNT_INCR_R, // 0xa20
+ "INTR_BRF_NOTIF_MBOX_ECC_COR_INTR_COUNT_INCR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_INCR_R, // 0xa24
+ "INTR_BRF_NOTIF_DEBUG_LOCKED_INTR_COUNT_INCR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_INCR_R, // 0xa28
+ "INTR_BRF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R, // 0xa2c
// SHA Accelerator Interrupt Block Registers
"SHA_ACC_INTR_BRF_GLOBAL_INTR_EN_R" : SHAACC_BASE + `SHA512_ACC_CSR_INTR_BLOCK_RF_GLOBAL_INTR_EN_R, // 0x800 Per-Type Intr Enable Reg
@@ -276,41 +286,48 @@ package soc_ifc_tb_pkg;
// Sticky registers preserve values across warm reset -- groups of regs might be populated by code
// mask of all bits to be protected in case of warm reset
word_addr_t _sticky_register_prefix_dict [string] = {
- "FUSE_": 32'hffff_ffff,
- "CPTRA_HW_ERROR_": 32'hffff_ffff, // FATAL, NON_FATAL, ENC
- "CPTRA_FW_ERROR_": 32'hffff_ffff, // FATAL, NON_FATAL, ENC
- "CPTRA_FW_EXTENDED_ERROR_INFO": 32'hffff_ffff,
- "CPTRA_RESET_REASON": 32'h2, // field WARM_RESET
- "CPTRA_FUSE_WR_DONE": 32'h1, // field 0
- "CPTRA_FUSE_VALID_PAUSER": 32'hffff_ffff,
- "CPTRA_FUSE_PAUSER_LOCK": 32'h1,
- "CPTRA_TIMER_CONFIG": 32'hffff_ffff,
- "INTERNAL_RV_MTIME_L": 32'hffff_ffff,
- "INTERNAL_RV_MTIME_H": 32'hffff_ffff,
- "INTERNAL_RV_MTIMECMP_L": 32'hffff_ffff,
- "INTERNAL_RV_MTIMECMP_H": 32'hffff_ffff,
- "INTR_BRF_ERROR_INTERNAL_INTR_R": 32'h3f, // fields 5:0
- "INTR_BRF_ERROR_INTERNAL_INTR_COUNT_R": 32'hffff_ffff,
- "INTR_BRF_ERROR_INV_DEV_INTR_COUNT_R": 32'hffff_ffff,
- "INTR_BRF_ERROR_CMD_FAIL_INTR_COUNT_R": 32'hffff_ffff,
- "INTR_BRF_ERROR_BAD_FUSE_INTR_COUNT_R": 32'hffff_ffff,
- "INTR_BRF_ERROR_ICCM_BLOCKED_INTR_COUNT_R": 32'hffff_ffff,
- "INTR_BRF_ERROR_MBOX_ECC_UNC_INTR_COUNT_R": 32'hffff_ffff,
- "INTR_BRF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_R": 32'hffff_ffff,
- "INTR_BRF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_R": 32'hffff_ffff
+ "FUSE_UDS_SEED" : 32'hffff_ffff,
+ "FUSE_FIELD_ENTROPY" : 32'hffff_ffff,
+ "FUSE_KEY_MANIFEST_PK_HASH" : 32'hffff_ffff ,
+ "FUSE_KEY_MANIFEST_PK_HASH_MASK" : 32'hf, // field 3:0
+ "FUSE_OWNER_PK_HASH" : 32'hffff_ffff,
+ "FUSE_FMC_KEY_MANIFEST_SVN" : 32'hffff_ffff,
+ "FUSE_RUNTIME_SVN" : 32'hffff_ffff,
+ "FUSE_ANTI_ROLLBACK_DISABLE" : 32'h1, // field 0
+ "FUSE_IDEVID_CERT_ATTR" : 32'hffff_ffff,
+ "FUSE_IDEVID_MANUF_HSM_ID" : 32'hffff_ffff,
+ "FUSE_LIFE_CYCLE" : 32'h3, // field 1:0
+ "FUSE_LMS_VERIFY" : 32'h1, // field 0
+ "FUSE_LMS_REVOCATION" : 32'hffff_ffff,
+ "FUSE_SOC_STEPPING_ID" : 32'hffff, // field 15:0
+ "CPTRA_HW_ERROR_" : 32'hffff_ffff, // FATAL, NON_FATAL, ENC
+ "CPTRA_FW_ERROR_" : 32'hffff_ffff, // FATAL, NON_FATAL, ENC
+ "CPTRA_FW_EXTENDED_ERROR_INFO" : 32'hffff_ffff,
+ "CPTRA_RESET_REASON" : 32'h2, // field WARM_RESET
+ "CPTRA_FUSE_WR_DONE" : 32'h1, // field 0
+ "CPTRA_HW_REV_ID" : 32'hffff_ffff, // field SOC_STEPPING_ID, CPTRA_GENERATION
+ "CPTRA_FUSE_VALID_PAUSER" : 32'hffff_ffff,
+ "CPTRA_FUSE_PAUSER_LOCK" : 32'h1,
+ "CPTRA_TIMER_CONFIG" : 32'hffff_ffff,
+ "CPTRA_WDT_CFG" : 32'hffff_ffff,
+ "INTERNAL_RV_MTIME" : 32'hffff_ffff, // for MTIME_L/H, MTIMECMP_L/H
+ "INTR_BRF_ERROR_INTERNAL_INTR_R" : 32'hff, // fields 5:0
+ "INTR_BRF_ERROR_INTERNAL_INTR_COUNT_R" : 32'hffff_ffff,
+ "INTR_BRF_ERROR_INV_DEV_INTR_COUNT_R" : 32'hffff_ffff,
+ "INTR_BRF_ERROR_CMD_FAIL_INTR_COUNT_R" : 32'hffff_ffff,
+ "INTR_BRF_ERROR_BAD_FUSE_INTR_COUNT_R" : 32'hffff_ffff,
+ "INTR_BRF_ERROR_ICCM_BLOCKED_INTR_COUNT_R" : 32'hffff_ffff,
+ "INTR_BRF_ERROR_MBOX_ECC_UNC_INTR_COUNT_R" : 32'hffff_ffff,
+ "INTR_BRF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_R" : 32'hffff_ffff,
+ "INTR_BRF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_R" : 32'hffff_ffff
};
-
// mask bits that reflect which fields can be modified
dword_t _soc_register_mask_dict [string] = {
"CPTRA_HW_CONFIG" : (`SOC_IFC_REG_CPTRA_HW_CONFIG_ITRNG_EN_MASK |
`SOC_IFC_REG_CPTRA_HW_CONFIG_QSPI_EN_MASK |
`SOC_IFC_REG_CPTRA_HW_CONFIG_I3C_EN_MASK),
- "FUSE_ANTI_ROLLBACK_DISABLE" : `SOC_IFC_REG_FUSE_ANTI_ROLLBACK_DISABLE_DIS_MASK,
- "FUSE_KEY_MANIFEST_PK_HASH_MASK" : `SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_MASK_MASK,
- "FUSE_LIFE_CYCLE" : `SOC_IFC_REG_FUSE_LIFE_CYCLE_LIFE_CYCLE_MASK,
- "FUSE_LMS_VERIFY" : `SOC_IFC_REG_FUSE_LMS_VERIFY_LMS_VERIFY_MASK,
"CPTRA_FLOW_STATUS" : (`SOC_IFC_REG_CPTRA_FLOW_STATUS_STATUS_MASK |
`SOC_IFC_REG_CPTRA_FLOW_STATUS_IDEVID_CSR_READY_MASK |
//`SOC_IFC_REG_CPTRA_FLOW_STATUS_BOOT_FSM_PS_MASK |
@@ -320,11 +337,14 @@ package soc_ifc_tb_pkg;
`SOC_IFC_REG_CPTRA_FLOW_STATUS_MAILBOX_FLOW_DONE_MASK),
"CPTRA_MBOX_PAUSER_LOCK" : `SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_0_LOCK_MASK, // same for all 5 pausers
"CPTRA_TRNG_PAUSER_LOCK" : `SOC_IFC_REG_CPTRA_TRNG_PAUSER_LOCK_LOCK_MASK,
+ "CPTRA_TRNG_CTRL" : `SOC_IFC_REG_CPTRA_TRNG_CTRL_CLEAR_MASK,
"CPTRA_TRNG_STATUS.APB" : `SOC_IFC_REG_CPTRA_TRNG_STATUS_DATA_WR_DONE_MASK,
"CPTRA_TRNG_STATUS.AHB" : `SOC_IFC_REG_CPTRA_TRNG_STATUS_DATA_REQ_MASK,
"CPTRA_FUSE_WR_DONE" : `SOC_IFC_REG_CPTRA_FUSE_WR_DONE_DONE_MASK,
"CPTRA_BOOTFSM_GO" : `SOC_IFC_REG_CPTRA_BOOTFSM_GO_GO_MASK,
"CPTRA_CLK_GATING_EN" : `SOC_IFC_REG_CPTRA_CLK_GATING_EN_CLK_GATING_EN_MASK,
+ "CPTRA_HW_REV_ID" : (`SOC_IFC_REG_CPTRA_HW_REV_ID_CPTRA_GENERATION_MASK |
+ `SOC_IFC_REG_CPTRA_HW_REV_ID_SOC_STEPPING_ID_MASK),
"CPTRA_WDT_TIMER1_EN" : `SOC_IFC_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_MASK,
"CPTRA_WDT_TIMER1_CTRL" : `SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART_MASK,
"CPTRA_WDT_TIMER2_EN" : `SOC_IFC_REG_CPTRA_WDT_TIMER2_EN_TIMER2_EN_MASK,
@@ -332,6 +352,11 @@ package soc_ifc_tb_pkg;
"CPTRA_WDT_STATUS" : (`SOC_IFC_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_MASK |
`SOC_IFC_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_MASK),
"CPTRA_FUSE_PAUSER_LOCK" : `SOC_IFC_REG_CPTRA_FUSE_PAUSER_LOCK_LOCK_MASK,
+ "FUSE_ANTI_ROLLBACK_DISABLE" : `SOC_IFC_REG_FUSE_ANTI_ROLLBACK_DISABLE_DIS_MASK,
+ "FUSE_KEY_MANIFEST_PK_HASH_MASK" : `SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_MASK_MASK,
+ "FUSE_LIFE_CYCLE" : `SOC_IFC_REG_FUSE_LIFE_CYCLE_LIFE_CYCLE_MASK,
+ "FUSE_LMS_VERIFY" : `SOC_IFC_REG_FUSE_LMS_VERIFY_LMS_VERIFY_MASK,
+ "FUSE_SOC_STEPPING_ID" : `SOC_IFC_REG_FUSE_SOC_STEPPING_ID_SOC_STEPPING_ID_MASK,
"INTERNAL_ICCM_LOCK" : `SOC_IFC_REG_INTERNAL_ICCM_LOCK_LOCK_MASK,
"INTERNAL_FW_UPDATE_RESET" : `SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_CORE_RST_MASK,
"INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES" : `SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES_WAIT_CYCLES_MASK,
@@ -354,6 +379,7 @@ package soc_ifc_tb_pkg;
"INTR_BRF_NOTIF_INTR_EN_R" : (`SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_AVAIL_EN_MASK |
`SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_MBOX_ECC_COR_EN_MASK |
`SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_DEBUG_LOCKED_EN_MASK |
+ `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_SCAN_MODE_EN_MASK |
`SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_SOC_REQ_LOCK_EN_MASK |
`SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_GEN_IN_TOGGLE_EN_MASK ),
"INTR_BRF_ERROR_GLOBAL_INTR_R" : `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK,
@@ -369,6 +395,7 @@ package soc_ifc_tb_pkg;
"INTR_BRF_NOTIF_INTERNAL_INTR_R": (`SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK |
`SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK |
`SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK |
+ `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK |
`SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK |
`SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK ),
"INTR_BRF_ERROR_INTR_TRIG_R": (`SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_INTERNAL_TRIG_MASK |
@@ -382,6 +409,7 @@ package soc_ifc_tb_pkg;
"INTR_BRF_NOTIF_INTR_TRIG_R": (`SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_AVAIL_TRIG_MASK |
`SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_MBOX_ECC_COR_TRIG_MASK |
`SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_DEBUG_LOCKED_TRIG_MASK |
+ `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_SCAN_MODE_TRIG_MASK |
`SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_SOC_REQ_LOCK_TRIG_MASK |
`SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_GEN_IN_TOGGLE_TRIG_MASK ),
"INTR_BRF_ERROR_INTERNAL_INTR_COUNT_INCR_R" : `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R_PULSE_MASK,
@@ -544,8 +572,8 @@ package soc_ifc_tb_pkg;
begin
tmp_data = _exp_register_data_dict["INTR_BRF_NOTIF_INTERNAL_INTR_R"];
- tmp_data = tmp_data & (32'hffff_ffff ^ `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK)
- & (32'hffff_ffff ^ `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK);
+ // tmp_data = tmp_data & (32'hffff_ffff ^ `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK)
+ // & (32'hffff_ffff ^ `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK);
tmp_data = tmp_data | mask_shifted(debug_locked, `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK)
| mask_shifted(gen_input_wire_toggle, `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK);
update_exp_regval("INTR_BRF_NOTIF_INTERNAL_INTR_R", tmp_data, SET_DIRECT);
@@ -569,7 +597,7 @@ package soc_ifc_tb_pkg;
tmp_data = tmp_data | mask_shifted(fuse_ready_val, `SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FUSES_MASK);
tmp_data = tmp_data & (32'hffff_ffff ^ `SOC_IFC_REG_CPTRA_FLOW_STATUS_BOOT_FSM_PS_MASK);
tmp_data = tmp_data | mask_shifted(boot_fsm_ps, `SOC_IFC_REG_CPTRA_FLOW_STATUS_BOOT_FSM_PS_MASK);
- $display( "TB DEBUG. update_CPTRA_FLOW_STATUS(%x, %x) at time %t. new tmp_data = 0x%08x", fuse_ready_val, boot_fsm_ps, $realtime, tmp_data);
+ // $display( "TB DEBUG. update_CPTRA_FLOW_STATUS(%x, %x) at time %t. new tmp_data = 0x%08x", fuse_ready_val, boot_fsm_ps, $realtime, tmp_data);
update_exp_regval("CPTRA_FLOW_STATUS", tmp_data, SET_DIRECT);
@@ -610,6 +638,7 @@ package soc_ifc_tb_pkg;
dword_t sscode;
dword_t tmp_data;
+ dword_t mask;
begin
@@ -635,8 +664,10 @@ package soc_ifc_tb_pkg;
if (modify == SET_DIRECT) begin
_exp_register_data_dict[addr_name] = indata;
if ((addr_name == "INTERNAL_FW_UPDATE_RESET") & (indata[0] == 1'b1)) begin
- _exp_register_data_dict["INTERNAL_ICCM_LOCK"] = '0;
- $display ("TB INFO: Cross modification - Writing '1' to INTERNAL_FW_UPDATE_RESET also reset INTERNAL_ICCM_LOCK");
+ // NOTE. The expected value of INTERNAL_ICCM_LOCK must be updated outside of package, or at least outside of
+ // a function call since there could be a significant delay
+ // _exp_register_data_dict["INTERNAL_ICCM_LOCK"] = '0;
+ // $display ("TB INFO: Cross modification - Writing '1' to INTERNAL_FW_UPDATE_RESET also reset INTERNAL_ICCM_LOCK");
tmp_data = _exp_register_data_dict["CPTRA_RESET_REASON"];
tmp_data = tmp_data & (32'hffff_ffff ^ `SOC_IFC_REG_CPTRA_RESET_REASON_FW_UPD_RESET_MASK) |
@@ -669,7 +700,17 @@ package soc_ifc_tb_pkg;
end else if ((str_startswith(addr_name, "FUSE_UDS_SEED")) || (str_startswith(addr_name, "FUSE_FIELD_ENTROPY")))
exp_data = '0; // not accessible over APB or AHB
- else if (str_startswith(addr_name, "FUSE_"))
+ else if (addr_name == "FUSE_SOC_STEPPING_ID") begin // Normal fuse register operation + cross modification of register
+ exp_data = fuses_locked ? curr_data : (ahb_rodata | apb_indata & get_mask(addr_name)); // ahb-RO
+ $display ("TB INFO: Cross modification - Updating FUSE_SOC_STEPPING_ID also updates CPTRA_HW_REV_ID");
+
+ tmp_data = _exp_register_data_dict["CPTRA_HW_REV_ID"] &
+ mask_shifted(16'hffff, `SOC_IFC_REG_CPTRA_HW_REV_ID_CPTRA_GENERATION_MASK); // pick out cptra_generation
+ _exp_register_data_dict["CPTRA_HW_REV_ID"] =
+ mask_shifted(tmp_data, `SOC_IFC_REG_CPTRA_HW_REV_ID_CPTRA_GENERATION_MASK) | // add back cptra_generation
+ mask_shifted(exp_data, `SOC_IFC_REG_CPTRA_HW_REV_ID_SOC_STEPPING_ID_MASK); // and new stepping_id
+
+ end else if (str_startswith(addr_name, "FUSE_"))
exp_data = fuses_locked ? curr_data : (ahb_rodata | apb_indata & get_mask(addr_name)); // ahb-RO
else if (str_startswith(addr_name, "CPTRA_MBOX_VALID_PAUSER")) begin // find equivalent pauser lock & if set, apb-RO
@@ -693,6 +734,10 @@ package soc_ifc_tb_pkg;
else if (str_startswith(addr_name, "CPTRA_HW_CONFIG"))
exp_data = curr_data & get_mask("CPTRA_HW_CONFIG"); // all bits are RO
+ else if (str_startswith(addr_name, "CPTRA_WDT_TIMER1_TIMEOUT_PERIOD") ||
+ str_startswith(addr_name, "CPTRA_WDT_TIMER2_TIMEOUT_PERIOD"))
+ exp_data = ahb_indata | apb_rodata;
+
else if (str_startswith(addr_name, "INTERNAL_OBF_KEY"))
exp_data = '0; // not accessible over APB or AHB
@@ -734,10 +779,19 @@ package soc_ifc_tb_pkg;
exp_data = '0; // write-one to clear -- effectively always 0
end
- "CPTRA_FLOW_STATUS" : exp_data = curr_data & ~get_mask(addr_name) |
- ahb_indata & get_mask(addr_name) | apb_rodata; // 32'hb1ff_ffff; // apb-RO
- "CPTRA_RESET_REASON" : exp_data = ahb_rodata | apb_rodata; // bit 1:0 is RO
- "CPTRA_SECURITY_STATE" : exp_data = curr_data & get_mask(addr_name); // & sscode; // bit 3:0 is RO
+ "CPTRA_FLOW_STATUS" : begin
+ if (modify == SET_APB) // apb-RO
+ exp_data = apb_rodata;
+ else if (modify == SET_AHB) begin // some fields are ro
+ mask = get_mask(addr_name);
+ exp_data = (mask & ahb_indata) | (~mask & curr_data);
+ // $display ("TB DEBUG: for CPTRA_FLOW_STATUS ahb_indata = 0x%08x, curr_data = 0x%08x, exp_data = 0x%08x",
+ // ahb_indata, curr_data, exp_data);
+ end
+ end
+
+ "CPTRA_RESET_REASON" : exp_data = ahb_rodata | apb_rodata; // bit 1:0 is RO
+ "CPTRA_SECURITY_STATE" : exp_data = curr_data & get_mask(addr_name); // & sscode; // bit 3:0 is RO
"CPTRA_TRNG_VALID_PAUSER" : begin // find equivalent pauser lock & if set, apb-RO
pauser_locked = _exp_register_data_dict["CPTRA_TRNG_PAUSER_LOCK"];
@@ -750,6 +804,8 @@ package soc_ifc_tb_pkg;
exp_data = pauser_locked ? curr_data & lock_mask : (ahb_indata | apb_indata) & lock_mask;
end
+ "CPTRA_TRNG_CTRL" : exp_data = apb_rodata; // pulsed w/ahb
+
"CPTRA_TRNG_STATUS": begin // WR_DONE REQ
dword_t ahb_mask = get_mask("CPTRA_TRNG_STATUS.AHB");
dword_t apb_mask = get_mask("CPTRA_TRNG_STATUS.APB");
@@ -757,18 +813,16 @@ package soc_ifc_tb_pkg;
(apb_rodata & ~apb_mask | apb_indata & apb_mask) ; // SOC Access: RW RO
end
- "CPTRA_HW_REV_ID" : exp_data = curr_data;
- "CPTRA_WDT_TIMER1_EN" : exp_data = ahb_indata & get_mask(addr_name) | apb_rodata;
- "CPTRA_WDT_TIMER1_CTRL" : exp_data = ((ahb_indata & get_mask(addr_name)) != 0) ? '0: apb_rodata; // TODO. Pulsed reg
- "CPTRA_WDT_TIMER1_TIMEOUT_PERIOD" : exp_data = ahb_indata | apb_rodata;
- "CPTRA_WDT_TIMER2_EN" : exp_data = ahb_indata & get_mask(addr_name) | apb_rodata;
- "CPTRA_WDT_TIMER2_CTRL" : exp_data = ((ahb_indata & get_mask(addr_name)) != 0) ? '0: apb_rodata; // TODO. Pulsed reg
- "CPTRA_WDT_TIMER2_TIMEOUT_PERIOD" : exp_data = ahb_indata | apb_rodata;
- "CPTRA_WDT_STATUS" : exp_data = curr_data;
- "CPTRA_FUSE_WR_DONE" : exp_data = fuses_locked ? curr_data : (ahb_rodata | apb_indata & get_mask(addr_name));
- "CPTRA_BOOTFSM_GO" : exp_data = ahb_rodata | apb_indata & get_mask(addr_name) ;
- "CPTRA_BOOT_STATUS" : exp_data = ahb_indata | apb_rodata;
- "CPTRA_CLK_GATING_EN" : exp_data = ahb_rodata | apb_indata & get_mask(addr_name) ;
+ "CPTRA_HW_REV_ID" : exp_data = curr_data;
+ "CPTRA_WDT_TIMER1_EN" : exp_data = ahb_indata & get_mask(addr_name) | apb_rodata;
+ "CPTRA_WDT_TIMER1_CTRL" : exp_data = ((ahb_indata & get_mask(addr_name)) != 0) ? '0: apb_rodata; // TODO. Pulsed reg
+ "CPTRA_WDT_TIMER2_EN" : exp_data = ahb_indata & get_mask(addr_name) | apb_rodata;
+ "CPTRA_WDT_TIMER2_CTRL" : exp_data = ((ahb_indata & get_mask(addr_name)) != 0) ? '0: apb_rodata; // TODO. Pulsed reg
+ "CPTRA_WDT_STATUS" : exp_data = curr_data;
+ "CPTRA_FUSE_WR_DONE" : exp_data = fuses_locked ? curr_data : (ahb_rodata | apb_indata & get_mask(addr_name));
+ "CPTRA_BOOTFSM_GO" : exp_data = ahb_rodata | apb_indata & get_mask(addr_name) ;
+ "CPTRA_BOOT_STATUS" : exp_data = ahb_indata | apb_rodata;
+ "CPTRA_CLK_GATING_EN" : exp_data = ahb_rodata | apb_indata & get_mask(addr_name) ;
"CPTRA_FUSE_VALID_PAUSER" : begin // find equivalent pauser lock & if set, apb-RO
pauser_locked = _exp_register_data_dict["CPTRA_FUSE_PAUSER_LOCK"];
@@ -791,8 +845,10 @@ package soc_ifc_tb_pkg;
// $display ("TB DEBUG: ahb_indata = 0x%x and exp_data for INTERNAL_FW_UPDATE_RESET = 0x%x", ahb_indata, exp_data);
if (exp_data[0]) begin // write-one to clear
- _exp_register_data_dict["INTERNAL_ICCM_LOCK"] = '0;
- $display ("TB INFO: Cross modification - Writing '1' to INTERNAL_FW_UPDATE_RESET also reset INTERNAL_ICCM_LOCK");
+ // NOTE. The expected value of INTERNAL_ICCM_LOCK must be updated outside of package, or at least outside of
+ // a function call since there could be a significant delay
+ // _exp_register_data_dict["INTERNAL_ICCM_LOCK"] = '0;
+ // $display ("TB INFO: Cross modification - Writing '1' to INTERNAL_FW_UPDATE_RESET also reset INTERNAL_ICCM_LOCK");
_exp_register_data_dict["CPTRA_RESET_REASON"] = 32'h1; //TODO. Ignoring warm reset for now
$display ("-- CPTRA_RESET_REASON is now %d", _exp_register_data_dict["CPTRA_RESET_REASON"]);
@@ -800,18 +856,18 @@ package soc_ifc_tb_pkg;
end
end
- "INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES" : exp_data = ahb_indata & get_mask(addr_name) | apb_rodata;
- "INTERNAL_NMI_VECTOR" : exp_data = ahb_indata | apb_rodata;
- "INTERNAL_HW_ERROR_FATAL_MASK" : exp_data = ahb_indata & get_mask(addr_name) | apb_rodata;
- "INTERNAL_HW_ERROR_NON_FATAL_MASK" : exp_data = ahb_indata & get_mask(addr_name) | apb_rodata;
- "INTERNAL_FW_ERROR_FATAL_MASK" : exp_data = ahb_indata | apb_rodata;
- "INTERNAL_FW_ERROR_NON_FATAL_MASK" : exp_data = ahb_indata | apb_rodata;
- "INTERNAL_RV_MTIME_L" : exp_data = ahb_indata | apb_rodata;
- "INTERNAL_RV_MTIME_H" : exp_data = ahb_indata | apb_rodata;
- "INTERNAL_RV_MTIMECMP_L" : exp_data = ahb_indata | apb_rodata;
- "INTERNAL_RV_MTIMECMP_H" : exp_data = ahb_indata | apb_rodata;
+ "INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES" : exp_data = ahb_indata & get_mask(addr_name) | apb_rodata;
+ "INTERNAL_NMI_VECTOR" : exp_data = ahb_indata | apb_rodata;
+ "INTERNAL_HW_ERROR_FATAL_MASK" : exp_data = ahb_indata & get_mask(addr_name) | apb_rodata;
+ "INTERNAL_HW_ERROR_NON_FATAL_MASK" : exp_data = ahb_indata & get_mask(addr_name) | apb_rodata;
+ "INTERNAL_FW_ERROR_FATAL_MASK" : exp_data = ahb_indata | apb_rodata;
+ "INTERNAL_FW_ERROR_NON_FATAL_MASK" : exp_data = ahb_indata | apb_rodata;
+ "INTERNAL_RV_MTIME_L" : exp_data = ahb_indata | apb_rodata;
+ "INTERNAL_RV_MTIME_H" : exp_data = ahb_indata | apb_rodata;
+ "INTERNAL_RV_MTIMECMP_L" : exp_data = ahb_indata | apb_rodata;
+ "INTERNAL_RV_MTIMECMP_H" : exp_data = ahb_indata | apb_rodata;
- default: exp_data = indata;
+ default: exp_data = indata & get_mask(addr_name);
endcase
@@ -967,8 +1023,9 @@ package soc_ifc_tb_pkg;
begin
$display ("** Clearing all expected reg values for cold reset **");
- foreach (_soc_register_dict[rname])
+ foreach (_soc_register_dict[rname]) begin
_exp_register_data_dict[rname] = get_initval(rname);
+ end
end
endfunction // reset_exp_data
@@ -1020,7 +1077,7 @@ package soc_ifc_tb_pkg;
// ---------------------------------------------------------------------------
// -- Generic Utility functions that have less to do with custom data types
// ---------------------------------------------------------------------------
- function automatic int str_startswith(string s1, string s2);
+ function automatic logic str_startswith(string s1, string s2);
return (s2 == s1.substr(0, s2.len() - 1));
@@ -1038,16 +1095,36 @@ package soc_ifc_tb_pkg;
function automatic del_from_strq(inout strq_t mutable_strq, input string name);
+ // NOTE. This function works ONLY for a single name that matches one-index
- automatic int iq [$];
+ int iq [$];
+ int j;
iq = mutable_strq.find_index with (item == name);
- foreach (iq[i])
- mutable_strq.delete(iq[i]);
+ j = iq[0];
+
+ mutable_strq.delete(j);
endfunction // del_from_strq
+ function automatic delm_from_strq(inout strq_t mutable_strq, input string pfx);
+ // NOTE. This function works by deleting multiple names with matching prefix
+
+ strq_t filtq;
+
+ foreach(mutable_strq[i]) begin
+ if (str_startswith(mutable_strq[i], pfx))
+ continue;
+ filtq.push_back(mutable_strq[i]);
+ end
+
+ mutable_strq = {};
+ mutable_strq = filtq;
+
+ endfunction // delm_from_strq
+
+
function automatic dword_t mask_shifted(dword_t v, dword_t n);
/* Shift 'v' by number of bits that mask 'n' has zeros on right. Example:
@@ -1581,7 +1658,7 @@ package soc_ifc_tb_pkg;
addr_table.delete(addr);
else begin
$display("TB WARNING. Multiple tid %d found for addr (0x%08x) in scoreboard", tid, addr);
- foreach (qi[i])
+ foreach (qi[i]) // Note. This works fine for a hash table, not a queue/array
addr_table[addr].delete(qi[i]);
end
diff --git a/src/soc_ifc/tb/soc_reg_intrblk_test.svh b/src/soc_ifc/tb/soc_reg_intrblk_test.svh
index 0cd8283cc..85e92c8ef 100644
--- a/src/soc_ifc/tb/soc_reg_intrblk_test.svh
+++ b/src/soc_ifc/tb/soc_reg_intrblk_test.svh
@@ -17,13 +17,13 @@
// Keeping all declarations and assignments of internal signals for possibly future use
logic [1:0] global_intr_en_r;
logic [7:0] error_intr_en_r;
- logic [4:0] notif_intr_en_r;
- logic error_global_intr_r; // *RO*
- logic notif_global_intr_r; // *RO*
+ logic [5:0] notif_intr_en_r;
+ logic error_global_intr_r; // *RO*
+ logic notif_global_intr_r; // *RO*
logic [7:0] error_internal_intr_r; // *WO*
- logic [4:0] notif_internal_intr_r; // *WO*
- logic [12:0] error_intr_trig_r; // *WO*
- logic [4:0] notif_intr_trig_r; // *WO*
+ logic [5:0] notif_internal_intr_r; // *WO*
+ logic [7:0] error_intr_trig_r; // *WO*
+ logic [5:0] notif_intr_trig_r; // *WO*
logic error_internal_intr_count_r;
logic error_inv_dev_intr_count_r;
logic error_cmd_fail_intr_count_r;
@@ -37,6 +37,7 @@
logic notif_debug_locked_intr_count_r;
logic notif_soc_req_lock_intr_count_r;
logic notif_gen_in_toggle_intr_count_r;
+ // Following are already covered via other tests and implications; not needed for INTR_BLOCK
// logic error_internal_intr_count_incr_r; dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value;
// logic error_inv_dev_intr_count_incr_r; dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.value;
// logic error_cmd_fail_intr_count_incr_r; dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.value;
@@ -51,7 +52,6 @@
// logic notif_soc_req_lock_intr_count_incr_r; dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.value;
// logic notif_gen_in_toggle_intr_count_incr_r; dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.value;
-
assign global_intr_en_r = {dut.i_soc_ifc_reg.field_storage.intr_block_rf.global_intr_en_r.error_en.value,
dut.i_soc_ifc_reg.field_storage.intr_block_rf.global_intr_en_r.notif_en.value};
assign error_intr_en_r = {dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value,
@@ -63,10 +63,11 @@
dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer1_timeout_en.value,
dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer2_timeout_en};
assign notif_intr_en_r = {dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_avail_en.value,
- dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_en_r.notif_mbox_ecc_cor_en,
- dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_en_r.notif_debug_locked_en,
- dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_en_r.notif_soc_req_lock_en,
- dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_en_r.notif_gen_in_toggle_en};
+ dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_en_r.notif_mbox_ecc_cor_en.value,
+ dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_en_r.notif_debug_locked_en.value,
+ dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_en_r.notif_scan_mode_en.value,
+ dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_en_r.notif_soc_req_lock_en.value,
+ dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_en_r.notif_gen_in_toggle_en.value};
assign error_global_intr_r = dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_global_intr_r.agg_sts.value; // *RO*
assign notif_global_intr_r = dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value; // *RO*
assign error_internal_intr_r = {dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value,
@@ -80,26 +81,24 @@
assign notif_internal_intr_r = {dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_avail_sts.value,
dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_internal_intr_r.notif_mbox_ecc_cor_sts.value,
dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_internal_intr_r.notif_debug_locked_sts.value,
+ dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts.value,
dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_internal_intr_r.notif_soc_req_lock_sts.value,
- dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.value};
- assign error_intr_trig_r = {dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value,
- dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_intr_trig_r.error_inv_dev_trig.value,
- dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_intr_trig_r.error_cmd_fail_trig.value,
- dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_intr_trig_r.error_bad_fuse_trig.value,
- dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_intr_trig_r.error_iccm_blocked_trig.value,
- dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_intr_trig_r.error_mbox_ecc_unc_trig.value,
+ dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.value};
+ assign error_intr_trig_r = {dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer2_timeout_trig.value,
dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer1_timeout_trig.value,
- dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer2_timeout_trig.value,
- dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_avail_trig.value,
- dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_trig_r.notif_mbox_ecc_cor_trig,
- dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_trig_r.notif_debug_locked_trig.value,
+ dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_intr_trig_r.error_mbox_ecc_unc_trig.value,
+ dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_intr_trig_r.error_iccm_blocked_trig.value,
+ dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_intr_trig_r.error_bad_fuse_trig.value,
+ dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_intr_trig_r.error_cmd_fail_trig.value,
+ dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_intr_trig_r.error_inv_dev_trig.value,
+ dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value};
+ assign notif_intr_trig_r = {dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.value,
dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.value,
- dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.value};
- assign notif_intr_trig_r = {dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_avail_trig.value,
- dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_trig_r.notif_mbox_ecc_cor_trig.value,
+ dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.value,
dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_trig_r.notif_debug_locked_trig.value,
- dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.value,
- dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.value};
+ dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_trig_r.notif_mbox_ecc_cor_trig.value,
+ dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_avail_trig.value};
+
assign error_internal_intr_count_r = dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value;
assign error_inv_dev_intr_count_r = dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_inv_dev_intr_count_r.cnt.value;
assign error_cmd_fail_intr_count_r = dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_cmd_fail_intr_count_r.cnt.value;
@@ -126,16 +125,22 @@
word_addr_t addr;
int tid = 0; // TID is to be updated ONLY if multiple writes to an address
strq_t intrblk_regnames;
- string rname;
- // int iq [$];
+ string rname, associated_rname;
- // transaction_t entry;
- // transq_t entries;
WordTransaction wrtrans, rdtrans;
- strq_t ro_regnames, wo_regnames, special_regnames;
+ strq_t ro_regnames, wo_regnames, wo_associated_regnames;
logic [31:0] nonzero_cyc = '0;
- dword_t regval, ahb_wrdata;
+ dword_t ahb_wrdata;
+
+ int changeup;
+ int changedn;
+ int changeup_cyc = 0;
+ int changedn_cyc = 0;
+ dword_t nonzero_regval;
+ dword_t final_regval;
+ dword_t associated_regval;
+
begin
$display("Executing task soc_reg_intrblk_test");
@@ -155,10 +160,8 @@
update_exp_regval("INTR_BRF_NOTIF_GLOBAL_INTR_R", error_global_intr_r, SET_DIRECT);
// Write-one to clear regs need special handling
- wo_regnames = { "INTR_BRF_ERROR_INTERNAL_INTR_R",
- "INTR_BRF_NOTIF_INTERNAL_INTR_R",
- "INTR_BRF_ERROR_INTR_TRIG_R",
- "INTR_BRF_NOTIF_INTR_TRIG_R" };
+ wo_regnames = { "INTR_BRF_ERROR_INTR_TRIG_R", "INTR_BRF_NOTIF_INTR_TRIG_R" };
+ wo_associated_regnames = { "INTR_BRF_ERROR_INTERNAL_INTR_R", "INTR_BRF_NOTIF_INTERNAL_INTR_R" };
repeat (5) @(posedge clk_tb);
@@ -180,6 +183,7 @@
$display ("\n------------------------------------------------------------------------------");
$display ("1a. Writing/Reading back to back using AHB/AHB every 3 cycles");
$display ("------------------------------------------------------------------------------");
+ tphase = "1a";
write_read_regs(SET_AHB, GET_AHB, intrblk_regnames, tid, 3);
repeat (20) @(posedge clk_tb);
@@ -189,15 +193,17 @@
$display ("\n------------------------------------------------------------------------------");
$display ("1b. Read over AHB. Then Writing/Reading back to back using APB/APB every 3 cycles");
$display ("------------------------------------------------------------------------------");
+ tphase = "1b";
// Read out the data over AHB. Ensure APB writes cannot modify the registers
// Implicity test neither can AHB reads.
foreach (intrblk_regnames[i]) begin
+ $display("-- expect no modification over apb writes --");
rname = intrblk_regnames[i];
rdtrans.update(socregs.get_addr(rname), 32'hffff_ffff, tid);
read_reg_trans(GET_AHB, rdtrans);
update_exp_regval(rname, rdtrans.data, SET_DIRECT); // what has been just read cannot be changed by APB
- write_regs(SET_APB, intrblk_regnames, tid, 3);
+ write_regs(SET_APB, {rname}, tid, 3);
end
read_regs(GET_APB, intrblk_regnames, tid, 3);
@@ -208,15 +214,18 @@
$display ("\n------------------------------------------------------------------------------");
$display ("1c. Read over APB. Then Writing/Reading back to back using APB/AHB every 3 cycles");
$display ("------------------------------------------------------------------------------");
+ tphase = "1c";
// Read out the data over APB. Ensure APB writes cannot modify the registers either
// Implicity test neither can APB reads.
foreach (intrblk_regnames[i]) begin
+ $display("-- expect no modification over apb writes --");
+ rname = intrblk_regnames[i];
rname = intrblk_regnames[i];
rdtrans.update(socregs.get_addr(rname), 32'hffff_ffff, tid);
read_reg_trans(GET_APB, rdtrans);
update_exp_regval(rname, rdtrans.data, SET_DIRECT); // what has been read cannot be changed by APB
- write_regs(SET_APB, intrblk_regnames, tid, 3);
+ write_regs(SET_APB, {rname}, tid, 3);
end
read_regs(GET_AHB, intrblk_regnames, tid, 3);
@@ -226,76 +235,101 @@
// Don't need to test AHB/APB write read anymore; included in sequences above
// $display ("1d. Writing/Reading back to back using AHB/APB every 3 cycles");
- error_ctr += sb.err_count;
-
$display ("\n------------------------------------------------------------------------------");
$display ("2a. Handle WO special registers");
$display ("------------------------------------------------------------------------------");
+ tphase = "2a";
- // First expect to clear all write-to-clear data
- foreach (wo_regnames[i]) begin
- rname = wo_regnames[i];
- wrtrans.update(socregs.get_addr(rname), 32'hffff_ffff, tid);
+ // For WO_ASSOCIATED_REGNAMES.
+ // First expect to clear all write-to-clear data (check it too)
+ // Then randomly set bits and ensure only those bits are cleared.
+ foreach (wo_associated_regnames[i]) begin
+ rname = wo_associated_regnames[i];
+ addr = socregs.get_addr(rname);
+ $display ("\n-- Handling WO register 0x%08x (%s) --", addr, rname);
+
+ $display ("\n -- First clear register and check --");
+ wrtrans.update_byname(rname, 32'hffff_ffff, tid);
write_reg_trans(SET_AHB, wrtrans);
- repeat (10) @(posedge clk_tb);
+ repeat (5) @(posedge clk_tb);
+
+ rdtrans.update_byname(rname, 0, tid);
+ read_reg_trans(GET_AHB, rdtrans);
+ if (rdtrans.data != '0) begin
+ $display("TB ERROR. Expected a write ones to clear register for addr 0x%08x (%s). Instead received 0x%08x",
+ addr, rname, rdtrans.data);
+ error_ctr += 1;
+ continue;
+ end
end
- // Then randomly set bits AFTER checking for 0 state
+ // Repeat. Longer squence for WO_REGNAMES.
+ // First expect to clear all write-to-clear data (check it too)
+ // Then randomly set bits and ensure only those bits are cleared.
foreach (wo_regnames[i]) begin
rname = wo_regnames[i];
addr = socregs.get_addr(rname);
+ $display ("\n-- Handling WO register 0x%08x (%s) --", addr, rname);
+
+ $display ("\n -- First clear register and check --");
+ wrtrans.update_byname(rname, 32'hffff_ffff, tid);
+ write_reg_trans(SET_AHB, wrtrans);
+ repeat (5) @(posedge clk_tb);
- rdtrans.update(addr, 0, tid);
+ rdtrans.update_byname(rname, 0, tid);
read_reg_trans(GET_AHB, rdtrans);
if (rdtrans.data != '0) begin
- $display("TB ERROR. Expected a write ones to clear register for addr 0x%08x (%s). Instead received 0x%08x", addr, rname, rdtrans.data);
+ $display("TB ERROR. Expected a write ones to clear register for addr 0x%08x (%s). Instead received 0x%08x",
+ addr, rname, rdtrans.data);
error_ctr += 1;
continue;
end
-
- wrtrans.update(addr, 0, tid);
+
+ // Now randomly set bits after reg is all clear
+ wrtrans.update_byname(rname, 0, tid);
wrtrans.randomize();
ahb_wrdata = wrtrans.data & get_mask(rname);
+ // $display ("TB DEBUG. Now randomly set bits to write 0x%08x; w/masking expect to write 0x%08x",
+ // wrtrans.data, ahb_wrdata);
+
+ $display ("\n -- Finally check for non-zero value and then transition to 0 --");
+
- nonzero_cyc = '0;
fork
begin : writing_over_ahb
write_reg_trans(SET_AHB, wrtrans);
repeat (10) @(posedge clk_tb);
end
+
begin : checking_for_transition
- repeat (10) begin
- @(posedge clk_tb);
- regval = 32'hffff_ffff & ((rname == "INTR_BRF_ERROR_INTERNAL_INTR_R") ? error_internal_intr_r :
- (rname == "INTR_BRF_NOTIF_INTERNAL_INTR_R") ? notif_internal_intr_r :
- (rname == "INTR_BRF_ERROR_INTR_TRIG_R") ? error_intr_trig_r :
- (rname == "INTR_BRF_NOTIF_INTR_TRIG_R") ? notif_intr_trig_r : 0);
-
- if ((regval != '0) && (regval != ahb_wrdata)) begin
- $display ("TB ERROR from addr 0x%08x (%s). Directly probed reg val = 0x%08x | expected 0x%08x or '0", addr, rname, regval, ahb_wrdata);
- error_ctr += 1;
- continue;
- end else if (regval == ahb_wrdata) begin
- nonzero_cyc = cycle_ctr_since_pwrgood;
- end
- end
+ monitor_pulsed_reg(rname, 10, nonzero_regval, final_regval, changeup, changedn);
end
join
- regval = 32'hffff_ffff & ((rname == "INTR_BRF_ERROR_INTERNAL_INTR_R") ? error_internal_intr_r :
- (rname == "INTR_BRF_NOTIF_INTERNAL_INTR_R") ? notif_internal_intr_r :
- (rname == "INTR_BRF_ERROR_INTR_TRIG_R") ? error_intr_trig_r :
- (rname == "INTR_BRF_NOTIF_INTR_TRIG_R") ? notif_intr_trig_r : 0);
+ $display("Inspecting rname %s = addr 0x%08x", rname, addr);
+ $display ("TB DEBUG. All said and done; from addr 0x%08x (%s). Directly probed non-zero val = 0x%08x and final val = 0x%08x| expected non-zero = 0x%08x",
+ addr, rname, nonzero_regval, final_regval, ahb_wrdata);
- // Either a transition from 0 did not happen
- if (nonzero_cyc == 0) begin
- $display("TB ERROR did not see a transition to non-zero value for addr 0x%08x (%s)", addr, rname);
- error_ctr += 1;
- end else if (regval != '0) begin // Or a transition back to 0 did not happen
- $display("TB ERROR did not see a transition back to a zero value for addr 0x%08x (%s) and stayed at 0x%08x", addr, rname, regval);
+ associated_rname = "INTR_BRF_ERROR_INTR_TRIG_R" ? "INTR_BRF_ERROR_INTERNAL_INTR_R" :
+ "INTR_BRF_NOTIF_INTR_TRIG_R" ? "INTR_BRF_NOTIF_INTERNAL_INTR_R" :
+ "UNDEFINED";
+
+ associated_regval = probe_reg(associated_rname);
+ $display ("TB INFO. Checking associated address %s related to trigger %s; associaated value = 0x%08x, trigger value %08x",
+ associated_rname, rname, associated_regval, nonzero_regval);
+
+
+ if (changeup && changedn && (nonzero_regval == ahb_wrdata) && (final_regval == '0))
+ $display ("TB INFO. Both up and down transitions noted correctly; all good with addr 0x%08x (%s)!", addr, rname);
+ else begin
error_ctr += 1;
+ if (!changeup)
+ $display("TB ERROR did not see a transition to non-zero value for addr 0x%08x (%s)", addr, rname);
+ else if (!changedn)
+ $display("TB ERROR did not see a transition back to a zero value for addr 0x%08x (%s) and stayed at 0x%08x", addr, rname, final_regval);
+ if (nonzero_regval != ahb_wrdata)
+ $display("TB ERROR Nonzero value noted for addr 0x%08x (%s) is 0x%08x | expected 0x%08x", addr, rname, nonzero_regval, ahb_wrdata);
end
-
end
end
@@ -303,6 +337,54 @@
endtask // soc_reg_intrblk_test;
+
+ task automatic monitor_pulsed_reg(input string regname, input int num_cycles,
+ inout dword_t nonzero_val, inout dword_t final_val, inout up, inout dn);
+
+ dword_t probed_val = 32'hbead_face;
+ dword_t latched_val = 32'hbead_face;
+
+ begin
+
+ up = 0;
+ dn = 0;
+
+ repeat (num_cycles) begin
+ probed_val = probe_reg(regname);
+
+ if (up && dn) begin
+ $display("TB INFO. Saw both up and dn for register %s", regname);
+ break;
+ end
+
+ up = up | ((probed_val != latched_val) && (latched_val == '0)); // Sticky transition up
+ dn = dn | ((probed_val == '0) && (latched_val != '0)); // Sticky transition down
+
+ if (probed_val != '0)
+ nonzero_val = probed_val;
+
+ @(posedge clk_tb);
+ latched_val = probed_val;
+ end
+
+ final_val = probe_reg(regname);
+
+ // $display("TB DEBUG. For register %s Checking past initated ahb_write_trans. Probed regval = 0x%08x", rname, probed_val);
+ end
+
+ endtask // monitor_pulsed_reg
+
+
+ function automatic dword_t probe_reg(string regname);
+
+ return (regname == "INTR_BRF_ERROR_INTERNAL_INTR_R") ? error_internal_intr_r :
+ (regname == "INTR_BRF_NOTIF_INTERNAL_INTR_R") ? notif_internal_intr_r :
+ (regname == "INTR_BRF_ERROR_INTR_TRIG_R") ? error_intr_trig_r :
+ (regname == "INTR_BRF_NOTIF_INTR_TRIG_R") ? notif_intr_trig_r : 32'hdead_face;
+
+ endfunction
+
+
/*
// Placeholder reference
diff --git a/src/soc_ifc/tb/soc_reg_reset_test.svh b/src/soc_ifc/tb/soc_reg_reset_test.svh
index dda5a6404..a73ed44fe 100644
--- a/src/soc_ifc/tb/soc_reg_reset_test.svh
+++ b/src/soc_ifc/tb/soc_reg_reset_test.svh
@@ -96,7 +96,6 @@
sb.del_all();
sb.record_reset_values(0, COLD_RESET);
- reset_generic_input_wires(0, 0);
read_regs(GET_APB, soc_regnames, 0, 3);
_read_special_register(GET_APB, "INTERNAL_RV_MTIME_L", 0); // *** special register ***
diff --git a/src/soc_ifc/tb/soc_reg_test.svh b/src/soc_ifc/tb/soc_reg_test.svh
index 300ab621e..cc2fdf33c 100644
--- a/src/soc_ifc/tb/soc_reg_test.svh
+++ b/src/soc_ifc/tb/soc_reg_test.svh
@@ -45,9 +45,7 @@
del_from_strq(soc_regnames, "CPTRA_TRNG_STATUS");
// -- Exclude CPTRA_TRNG_DATA*
- iq = soc_regnames.find_index with (str_startswith(item, "CPTRA_TRNG_DATA"));
- foreach(iq[i])
- soc_regnames.delete(iq[i]);
+ delm_from_strq(soc_regnames, "CPTRA_TRNG_DATA");
repeat (5) @(posedge clk_tb);
@@ -73,6 +71,9 @@
write_read_regs(SET_AHB, GET_AHB, soc_regnames, tid, 3);
+ //FIXME. Need to add test for delayed cross modification of INTERNAL_ICCM_LOCK
+ // if ((addr_name == "INTERNAL_FW_UPDATE_RESET") & (indata[0] == 1'b1)) begin
+
repeat (20) @(posedge clk_tb);
sb.del_all();
@@ -100,6 +101,9 @@
$display ("-------------------------------------------------------------");
write_read_regs(SET_AHB, GET_APB, soc_regnames, tid, 3);
+
+ //FIXME. Need to add test for delayed cross modification of INTERNAL_ICCM_LOCK
+ // if ((addr_name == "INTERNAL_FW_UPDATE_RESET") & (indata[0] == 1'b1)) begin
error_ctr += sb.err_count;
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/testbench/hdl_top.sv b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/testbench/hdl_top.sv
index 20a92522c..621ee5af9 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/testbench/hdl_top.sv
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/testbench/hdl_top.sv
@@ -129,7 +129,7 @@ import uvmf_base_pkg_hdl::*;
assign uvm_test_top_environment_qvip_ahb_lite_slave_subenv_qvip_hdl.default_clk_gen_CLK = clk;
assign uvm_test_top_environment_qvip_ahb_lite_slave_subenv_qvip_hdl.default_reset_gen_RESET = cptra_status_agent_bus.cptra_noncore_rst_b;
assign uvm_test_top_environment_qvip_apb5_slave_subenv_qvip_hdl.default_clk_gen_CLK = clk;
- assign uvm_test_top_environment_qvip_apb5_slave_subenv_qvip_hdl.default_reset_gen_RESET = soc_ifc_ctrl_agent_bus.cptra_rst_b;
+ assign uvm_test_top_environment_qvip_apb5_slave_subenv_qvip_hdl.default_reset_gen_RESET = cptra_status_agent_bus.cptra_noncore_rst_b;
// DUT
soc_ifc_top #(
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_intr_block_rf_ext_notif_internal_intr_r_base.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_intr_block_rf_ext_notif_internal_intr_r_base.svh
index 6946128d1..6f194c35c 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_intr_block_rf_ext_notif_internal_intr_r_base.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_intr_block_rf_ext_notif_internal_intr_r_base.svh
@@ -138,7 +138,6 @@ class soc_ifc_reg_cbs_intr_block_rf_ext_notif_internal_intr_r_base extends uvm_r
// Global interrupt pin "agg_sts" is non-sticky
if ((value & ~previous))
begin
- `uvm_info("SOC_IFC_REG_CBS", {"Predicted update to ", fld.get_name(), " triggers interrupt output pin check delay job"}, UVM_MEDIUM)
delay_job.req_fld = fld;
delay_job.sts_reg = sts_reg;
delay_job.en_reg = en_reg;
@@ -146,14 +145,15 @@ class soc_ifc_reg_cbs_intr_block_rf_ext_notif_internal_intr_r_base extends uvm_r
delay_job.en_glb = en_glb;
delay_job.grab_values();
delay_jobs.push_back(delay_job);
+ `uvm_info("SOC_IFC_REG_CBS", {"Predicted update to ", fld.get_name(), " triggers interrupt output pin check delay job"}, UVM_MEDIUM)
end
// On falling edge of field value, caused by W1C, check if another thread
// is already attempting to perform hwset to this interrupt field (hwset is
// higher priority than W1C).
else if ((~value & previous) && fld_hwset_active)
begin
- `uvm_info("SOC_IFC_REG_CBS", {"Predicted update to ", fld.get_name(), " attempts to clear the interrupt bit but is preempted by an active hwset"}, UVM_MEDIUM)
value = previous;
+ `uvm_info("SOC_IFC_REG_CBS", {"Predicted update to ", fld.get_name(), " attempts to clear the interrupt bit but is preempted by an active hwset"}, UVM_MEDIUM)
// NOTE: No delay job is scheduled because no changes are predicted to
// other interrupt register fields based on this activity
end
@@ -163,7 +163,6 @@ class soc_ifc_reg_cbs_intr_block_rf_ext_notif_internal_intr_r_base extends uvm_r
// Global interrupt pin "agg_sts" is non-sticky
else if ((~value & previous))
begin
- `uvm_info("SOC_IFC_REG_CBS", {"Predicted update to ", fld.get_name(), " triggers interrupt output pin check delay job"}, UVM_MEDIUM)
delay_job.req_fld = fld;
delay_job.sts_reg = sts_reg;
delay_job.en_reg = en_reg;
@@ -171,6 +170,7 @@ class soc_ifc_reg_cbs_intr_block_rf_ext_notif_internal_intr_r_base extends uvm_r
delay_job.en_glb = en_glb;
delay_job.grab_values();
delay_jobs.push_back(delay_job);
+ `uvm_info("SOC_IFC_REG_CBS", {"Predicted update to ", fld.get_name(), " triggers interrupt output pin check delay job"}, UVM_MEDIUM)
end
else begin
`uvm_info("SOC_IFC_REG_CBS",
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_delay_job_intr_block_rf_ext.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_delay_job_intr_block_rf_ext.svh
index ce1d56484..bc8f55aaf 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_delay_job_intr_block_rf_ext.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_delay_job_intr_block_rf_ext.svh
@@ -56,7 +56,7 @@ class soc_ifc_reg_delay_job_intr_block_rf_ext extends soc_ifc_reg_delay_job;
sts_reg.get_mirrored_value(), val_sts_reg,
en_glb.get_mirrored_value(), val_en_glb ,
sts_glb.get_mirrored_value(), val_sts_glb),
- UVM_HIGH)
+ UVM_MEDIUM)
end
else if (/*val_sts_glb*/sts_glb.get_mirrored_value() && !(|(val_sts_reg/*sts_reg.get_mirrored_value()*/ & val_en_reg/*en_reg.get_mirrored_value()*/) /*&& val_en_glb / * en_glb.get_mirrored_value()*/)) begin
sts_glb.predict(1'b0);
@@ -67,7 +67,7 @@ class soc_ifc_reg_delay_job_intr_block_rf_ext extends soc_ifc_reg_delay_job;
sts_reg.get_mirrored_value(), val_sts_reg,
en_glb.get_mirrored_value(), val_en_glb ,
sts_glb.get_mirrored_value(), val_sts_glb),
- UVM_HIGH)
+ UVM_MEDIUM)
end
else begin
`uvm_info("SOC_IFC_REG_DELAY_JOB",
@@ -77,7 +77,7 @@ class soc_ifc_reg_delay_job_intr_block_rf_ext extends soc_ifc_reg_delay_job;
sts_reg.get_mirrored_value(), val_sts_reg,
en_glb.get_mirrored_value(), val_en_glb ,
sts_glb.get_mirrored_value(), val_sts_glb),
- UVM_MEDIUM)
+ UVM_HIGH)
end
endtask
endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_model_top_pkg.sv b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_model_top_pkg.sv
index b4fd5cab5..ed868206a 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_model_top_pkg.sv
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_model_top_pkg.sv
@@ -832,6 +832,17 @@ package soc_ifc_reg_model_top_pkg;
super.new(name, build_coverage(UVM_CVR_ALL));
endfunction
+ // Function: reset
+ //
+ function void reset(string kind = "HARD");
+ super.reset(kind);
+ if (kind inside {"HARD", "NONCORE"}) begin
+ // Purge all pending jobs to update the register model
+ `uvm_info("SOC_IFC_REG_MODEL_TOP", {"Reset of kind ", kind, " results in delay_jobs being cleared"}, UVM_HIGH)
+ delay_jobs.delete();
+ end
+ endfunction
+
// Function: build
//
virtual function void build();
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_handler_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_handler_sequence.svh
index 7ea25378e..608f241e2 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_handler_sequence.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_handler_sequence.svh
@@ -41,7 +41,7 @@ class soc_ifc_env_cptra_mbox_handler_sequence extends soc_ifc_env_sequence_base
rand longint unsigned force_unlock_delay_cycles;
bit unlock_proc_active = 1'b0;
- bit op_started = 1'b0;
+ bit op_active = 1'b0;
bit seq_done = 1'b0;
uvm_event in_report_reg_sts;
@@ -130,7 +130,15 @@ class soc_ifc_env_cptra_mbox_handler_sequence extends soc_ifc_env_sequence_base
// If resp data is required, set DATAIN
if (op.cmd.cmd_s.resp_reqd) begin
- mbox_push_datain();
+ if (mbox_resp_expected_dlen == 0) begin
+ // We should only have 'resp_reqd' and 'exp_dlen == 0' if
+ // a spurious write triggered MBOX_ERROR and caused us to fail
+ // on reading back the dataout
+ mbox_check_fsm();
+ end
+ else begin
+ mbox_push_datain();
+ end
end
// Set STATUS
@@ -158,7 +166,7 @@ class soc_ifc_env_cptra_mbox_handler_sequence extends soc_ifc_env_sequence_base
// After forcibly unlocking mailbox, kill any remaining activity.
// If force unlock is randomized to "off" for this run
// of the sequence, this won't ever run.
- if (op_started)
+ if (op_active)
in_report_reg_sts.wait_on(); /* Wait for pending bus transfers (in ALL_TIME_CONSUMING_TASKS) to finish to avoid deadlock */
disable ALL_TIME_CONSUMING_TASKS;
`uvm_info("CPTRA_MBOX_HANDLER", "Disabled ALL_TIME_CONSUMING_TASKS", UVM_HIGH)
@@ -238,7 +246,7 @@ task soc_ifc_env_cptra_mbox_handler_sequence::mbox_wait_for_command(output op_st
end
end
ntf_rsp_count = 0;
- op_started = 1;
+ op_active = 1;
// Clear interrupt
reg_model.soc_ifc_reg_rm.intr_block_rf_ext.notif_internal_intr_r.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
report_reg_sts(reg_sts, "notif_internal_intr_r");
@@ -334,7 +342,13 @@ task soc_ifc_env_cptra_mbox_handler_sequence::mbox_check_fsm();
report_reg_sts(reg_sts, "mbox_status");
fsm_state = mbox_fsm_state_e'(data >> reg_model.mbox_csr_rm.mbox_status.mbox_fsm_ps.get_lsb_pos());
- if (op.cmd.cmd_s.resp_reqd && fsm_state != MBOX_EXECUTE_SOC) begin
+ // In the error state, simply wait for the force-unlock to reset the mailbox and end the sequence (killing this routine in the process)
+ if (fsm_state == MBOX_ERROR) begin
+ `uvm_info("CPTRA_MBOX_HANDLER", $sformatf("On detecting mailbox FSM state: %p, wait for force_unlock to end the sequence", fsm_state), UVM_MEDIUM)
+ op_active = 1'b0; // So the force-unlock branch knows it's safe to terminate this task
+ forever configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(10000);
+ end
+ else if (op.cmd.cmd_s.resp_reqd && fsm_state != MBOX_EXECUTE_SOC) begin
`uvm_error("CPTRA_MBOX_HANDLER", $sformatf("Unexpected mailbox FSM state: %p", fsm_state))
end
endtask
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_interference_handler_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_interference_handler_sequence.svh
index 1f7c6d80d..755c60628 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_interference_handler_sequence.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_interference_handler_sequence.svh
@@ -55,7 +55,7 @@ task soc_ifc_env_cptra_mbox_interference_handler_sequence::mbox_wait_for_command
uvm_reg_data_t data;
op_sts = CPTRA_TIMEOUT;
- op_started = 1;
+ op_active = 1;
// Wait for notification interrupt indicating command is available
while (ntf_rsp_count == 0) begin
uvm_reg_data_t dlen;
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_req_sequence_base.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_req_sequence_base.svh
index 0fb458a71..46863df42 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_req_sequence_base.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_req_sequence_base.svh
@@ -172,7 +172,32 @@ endclass
// - Any functionality implemented in derived classes
//==========================================
task soc_ifc_env_cptra_mbox_req_sequence_base::mbox_setup();
- // TODO nothing to do yet
+ uvm_reg_data_t data;
+ uvm_reg_field flds[$];
+
+ // Clear any interrupts already asserted at sequence start
+ // Notifications
+ reg_model.soc_ifc_reg_rm.intr_block_rf_ext.notif_internal_intr_r.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
+ report_reg_sts(reg_sts, "notif_internal_intr_r");
+ reg_model.soc_ifc_reg_rm.intr_block_rf_ext.notif_internal_intr_r.write(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
+ report_reg_sts(reg_sts, "notif_internal_intr_r");
+ reg_model.soc_ifc_reg_rm.intr_block_rf_ext.notif_internal_intr_r.get_fields(flds);
+ foreach (flds[ii]) begin
+ if (data[flds[ii].get_lsb_pos()])
+ `uvm_info("CPTRA_MBOX_SEQ", {"At sequence start, observed notification_interrupt for bit: ", flds[ii].get_name()}, UVM_HIGH)
+ end
+
+ // Errors
+ reg_model.soc_ifc_reg_rm.intr_block_rf_ext.error_internal_intr_r.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
+ report_reg_sts(reg_sts, "error_internal_intr_r");
+ reg_model.soc_ifc_reg_rm.intr_block_rf_ext.error_internal_intr_r.write(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
+ report_reg_sts(reg_sts, "error_internal_intr_r");
+ flds.delete();
+ reg_model.soc_ifc_reg_rm.intr_block_rf_ext.error_internal_intr_r.get_fields(flds);
+ foreach (flds[ii]) begin
+ if (data[flds[ii].get_lsb_pos()])
+ `uvm_info("CPTRA_MBOX_SEQ", {"At sequence start, observed error_interrupt for bit: ", flds[ii].get_name()}, UVM_HIGH)
+ end
endtask
//==========================================
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sequence_base.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sequence_base.svh
index ab62c1dfd..166e40bc7 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sequence_base.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sequence_base.svh
@@ -139,13 +139,13 @@ class soc_ifc_env_mbox_sequence_base extends soc_ifc_env_sequence_base #(.CONFIG
[4:7] :/ 25,
[8:31]:/ 1};}
constraint medium_delay_c { rand_delay dist { 0 :/ 10,
- [1:7] :/ 25,
+ [1:7] :/ 50,
[8:31] :/ 100,
- [32:255]:/ 1000};}
+ [32:255]:/ 50};}
constraint large_delay_c { rand_delay dist { 15 :/ 1,
- [ 16 : 255] :/ 25,
- [ 256:1023] :/ 500,
- [1024:8191] :/ 300};}
+ [ 16 : 255] :/ 50,
+ [ 256:1023] :/ 100,
+ [1024:8191] :/ 25};}
// This deliberately intractable constraint must be overridden
// by a child sequence if random delays are expected to be driven
// by some custom rule set.
@@ -505,7 +505,13 @@ task soc_ifc_env_mbox_sequence_base::mbox_read_resp_data();
report_reg_sts(reg_sts, "mbox_dlen");
end
if (dlen != mbox_resp_expected_dlen) begin
- `uvm_error("MBOX_SEQ", $sformatf("SOC received response data with mbox_dlen [%0d] that does not match the expected data amount [%0d]!", dlen, mbox_resp_expected_dlen))
+ if (this.get_type_name() inside {"soc_ifc_env_mbox_reg_axs_invalid_sequence",
+ "soc_ifc_env_mbox_reg_axs_invalid_small_sequence",
+ "soc_ifc_env_mbox_reg_axs_invalid_medium_sequence",
+ "soc_ifc_env_mbox_reg_axs_invalid_large_sequence"})
+ `uvm_info("MBOX_SEQ", $sformatf("SOC received response data with mbox_dlen [%0d] that does not match the expected data amount [%0d]! Not flagging err since this is an invalid reg-access sequence [%s]", dlen, mbox_resp_expected_dlen, this.get_type_name()), UVM_LOW)
+ else
+ `uvm_error("MBOX_SEQ", $sformatf("SOC received response data with mbox_dlen [%0d] that does not match the expected data amount [%0d]!", dlen, mbox_resp_expected_dlen))
end
if (rand_delay_en) do_rand_delay(1, step_delay);
for (ii=0; ii < dlen; ii+=4) begin
@@ -554,7 +560,7 @@ task soc_ifc_env_mbox_sequence_base::mbox_poll_status();
end
else if (data == CMD_FAILURE) begin
if (sts_rsp_count > 0 && soc_ifc_status_agent_rsp_seq.rsp.cptra_error_non_fatal_intr_pending) begin
- `uvm_info("MBOX_SEQ", $sformatf("Unexpected mailbox status [%p] likely is the result of a spurious reg access injection specifically intended to cause a protocol violation", data), UVM_HIGH)
+ `uvm_info("MBOX_SEQ", $sformatf("Unexpected mailbox status [%p] likely is the result of a spurious reg access injection specifically intended to cause a protocol violation or a mailbox SRAM double bit flip", data), UVM_HIGH)
end
else begin
`uvm_error("MBOX_SEQ", $sformatf("Received mailbox status %p unexpectedly, since there is no pending non_fatal error interrupt", data))
@@ -593,7 +599,7 @@ task soc_ifc_env_mbox_sequence_base::mbox_clr_execute();
if (rand_delay_en) do_rand_delay(1, step_delay);
- // Check for any non-fatal mailbox protocol errors that occurred during the test
+ // Check for any non-fatal mailbox protocol or sram errors that occurred during the test
reg_model.soc_ifc_reg_rm.CPTRA_HW_ERROR_NON_FATAL.read(reg_sts, err, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(500)));
// don't use report_reg_sts since this isn't a mbox reg and doesn't have pauser requirements
if (reg_sts != UVM_IS_OK) begin
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sha_accel_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sha_accel_sequence.svh
index f86d996f6..aa6f609cf 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sha_accel_sequence.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sha_accel_sequence.svh
@@ -67,6 +67,15 @@ class soc_ifc_env_mbox_sha_accel_sequence extends soc_ifc_env_mbox_sequence_base
constraint start_addr_c {start_addr inside { [4:131068] };
start_addr[1:0] == '0; }
+ //==========================================
+ // Function: new
+ // Description: Constructor
+ //==========================================
+ function new(string name = "" );
+ super.new(name);
+ this.mbox_dlen_min_c.constraint_mode(0);
+ endfunction
+
endclass
task soc_ifc_env_mbox_sha_accel_sequence::mbox_setup();
@@ -127,15 +136,24 @@ task soc_ifc_env_mbox_sha_accel_sequence::mbox_setup();
byte_shift = 'd4 - this.dlen[1:0];
sha_block_data = sha_block_data << (byte_shift * 8);
- // Restrict the start addr so that we don't overflow the mailbox
- if ( (this.start_addr + this.dlen) > MBOX_SIZE_BYTES ) begin
- //if we would have overflowed, just lower start address so the data fits in the mailbox at the end
- this.start_addr = MBOX_SIZE_BYTES - (this.dlen);
- //round it down to match the alignment of the data
- this.start_addr[1:0] = '0;
+ // Override dlen to reflect the size of the SHA data + the start address dword
+ this.mbox_op_rand.dlen = 4 + this.dlen;
+
+ // Ensure that the start address is after the data
+ if ( (this.start_addr <= this.mbox_op_rand.dlen) || ( (this.start_addr + this.dlen) > MBOX_SIZE_BYTES )) begin
+ // Re-randomize start address to ensure it is after the valid data
+ // and still meets alignment requirements.
+ // Restrict the start addr so that we don't overflow the mailbox
+ this.randomize(this.start_addr) with { this.start_addr >= this.mbox_op_rand.dlen + 4;
+ this.start_addr + this.dlen <= MBOX_SIZE_BYTES;
+ this.start_addr[1:0] == 2'b00; };
+ end
+ // This shouldn't happen - if it does we bail out
+ // Check that re-randomizing start_addr for overlow didn't cause us to
+ // overlap. Key would have to be like half the mailbox in length which is impossible
+ if ( (this.start_addr < this.mbox_op_rand.dlen)) begin
+ `uvm_error("SHA_ACCEL_SEQ",$sformatf("Can't place the key in the mailbox properly Start_Addr: %x Dlen: %x", this.start_addr, this.mbox_op_rand.dlen))
end
- // Override dlen to reflect the size of the SHA data
- this.mbox_op_rand.dlen = this.start_addr + this.dlen;
endtask
// This should be overridden with real data to write
@@ -143,20 +161,20 @@ task soc_ifc_env_mbox_sha_accel_sequence::mbox_push_datain();
int ii;
reg [31:0] data;
int most_sig_dword;
- int sha_block_start_dw;
+ //int sha_block_start_dw;
//write 0's until the start address
- sha_block_start_dw = this.start_addr >> 2;
+ //sha_block_start_dw = this.start_addr >> 2;
//write the start address into the first dword
reg_model.mbox_csr_rm.mbox_datain.write(reg_sts, uvm_reg_data_t'(this.start_addr), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(PAUSER_PROB_DATAIN)));
report_reg_sts(reg_sts, "mbox_datain");
//pad the data until start address
- for (ii=1; ii < sha_block_start_dw; ii++) begin
- reg_model.mbox_csr_rm.mbox_datain.write(reg_sts, uvm_reg_data_t'('0), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(PAUSER_PROB_DATAIN)));
- report_reg_sts(reg_sts, "mbox_datain");
- end
+ //for (ii=1; ii < sha_block_start_dw; ii++) begin
+ // reg_model.mbox_csr_rm.mbox_datain.write(reg_sts, uvm_reg_data_t'('0), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(PAUSER_PROB_DATAIN)));
+ // report_reg_sts(reg_sts, "mbox_datain");
+ //end
//write the sha block
most_sig_dword = (this.dlen[1:0] == 2'b00) ? (this.dlen >> 2) - 1 : (this.dlen >> 2);
@@ -190,4 +208,4 @@ task soc_ifc_env_mbox_sha_accel_sequence::mbox_read_resp_data();
`uvm_error("SHA_ACCEL_SEQ",$sformatf("SHA512 Digest Mismatch - Digest[%x] Expected: %x Actual: %x", ii, sha_digest[digest_dwords-1-ii], data))
end
end
-endtask
\ No newline at end of file
+endtask
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_large_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_large_sequence.svh
new file mode 100644
index 000000000..b26f72ab5
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_large_sequence.svh
@@ -0,0 +1,44 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Extended from Mailbox SRAM double bit flip injection
+// sequence for the special 'large' test case
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_mbox_sram_double_bit_flip_large_sequence extends soc_ifc_env_mbox_sram_double_bit_flip_sequence;
+
+ `uvm_object_utils( soc_ifc_env_mbox_sram_double_bit_flip_large_sequence )
+
+ // Constrain size to a large command
+ // Min. size: 16KiB
+ constraint mbox_dlen_min_large_c { mbox_op_rand.dlen > 32'h0000_4000; }
+ // Constrain response data size to also be large
+ // Min. size: 16KiB
+ constraint mbox_resp_dlen_min_large_c { mbox_op_rand.cmd.cmd_s.resp_reqd -> mbox_resp_expected_dlen >= 32'h0000_4000; }
+ // Valid solution for the custom delay ruleset, to control random delays while
+ // waiting to inject random error accesses
+ constraint custom_delay_c { rand_delay > 0;
+ rand_delay dist {[1 :mbox_op_rand.dlen*2 -1] :/ 250,
+ [mbox_op_rand.dlen*2 :mbox_op_rand.dlen*5 -1] :/ 100,
+ [mbox_op_rand.dlen*5 :mbox_op_rand.dlen*15-1] :/ 25}; }
+
+endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_medium_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_medium_sequence.svh
new file mode 100644
index 000000000..35c7e14ca
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_medium_sequence.svh
@@ -0,0 +1,48 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Extended from Mailbox SRAM double bit flip injection
+// sequence for the special 'medium' test case
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_mbox_sram_double_bit_flip_medium_sequence extends soc_ifc_env_mbox_sram_double_bit_flip_sequence;
+
+ `uvm_object_utils( soc_ifc_env_mbox_sram_double_bit_flip_medium_sequence )
+
+ // Constrain dlen to be a medium command
+ // Max. size: 4096B
+ constraint mbox_dlen_max_medium_c { mbox_op_rand.dlen <= 32'h0000_1000; }
+ // Minimum 512B
+ constraint mbox_dlen_min_medium_c { mbox_op_rand.dlen >= 32'h0000_0200; }
+ // Constrain response data size to also be medium
+ // Max. size: 4096B
+ // Min. size: 512B
+ constraint mbox_resp_dlen_max_medium_c { mbox_resp_expected_dlen <= 32'h0000_1000; }
+ constraint mbox_resp_dlen_min_medium_c { mbox_op_rand.cmd.cmd_s.resp_reqd -> mbox_resp_expected_dlen >= 32'h0000_0200; }
+ // Valid solution for the custom delay ruleset, to control random delays while
+ // waiting to inject random error accesses
+ constraint custom_delay_c { rand_delay > 0;
+ rand_delay dist {[1 :mbox_op_rand.dlen*2 -1] :/ 250,
+ [mbox_op_rand.dlen*2 :mbox_op_rand.dlen*5 -1] :/ 100,
+ [mbox_op_rand.dlen*5 :mbox_op_rand.dlen*15-1] :/ 25}; }
+
+endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_sequence.svh
new file mode 100644
index 000000000..22f0a3134
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_sequence.svh
@@ -0,0 +1,105 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Extended from mbox sequence base to exercise double-bit flips
+// on the mailbox SRAM.
+// Desired result is to observe the internal error interrupt and
+// assertion of the cptra_error_non_fatal pin.
+// After responding to the error by clearing the interrupts, the
+// mailbox flow will be terminated.
+// NOTES:
+// - SOC may respond with any of:
+// 1. Wait for uC to clear the internal interrupt / reset the mbox
+// FSM (or proceed with the cmd as normal), then proceed to
+// clear the cptra_error_non_fatal pin
+// 2. Clear the cptra_error_non_fatal pin immediately, issue a new command
+// (still requires waiting for LOCK)
+// 3. Reset Caliptra
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_mbox_sram_double_bit_flip_sequence extends soc_ifc_env_mbox_sequence_base;
+
+ `uvm_object_utils( soc_ifc_env_mbox_sram_double_bit_flip_sequence )
+
+ // Constrain command to undefined opcode
+ constraint mbox_cmd_undef_c { !(mbox_op_rand.cmd.cmd_s inside {defined_cmds}); }
+
+ function new(string name = "" );
+ super.new(name);
+ endfunction
+
+ //==========================================
+ // Task: body
+ // Description: Implement main functionality for
+ // SOC-side transmission of mailbox request.
+ // Override default body to inject double
+ // bit flips into the Mailbox SRAM at random
+ // throughout a normal test flow.
+ //==========================================
+ virtual task body();
+
+ op_sts_e op_sts;
+ process mbox_flow_proc;
+ process err_proc;
+
+ sts_rsp_count = 0;
+
+ fork
+ forever begin
+ @(soc_ifc_status_agent_rsp_seq.new_rsp) sts_rsp_count++;
+ end
+ join_none
+
+ `uvm_info("MBOX_SEQ", $sformatf("Initiating command sequence to mailbox with cmd: [%p] dlen: [%p] resp_dlen: [%p]", mbox_op_rand.cmd.cmd_e, mbox_op_rand.dlen, mbox_resp_expected_dlen), UVM_MEDIUM)
+
+ fork
+ begin: MBOX_FLOW
+ mbox_setup(); if (rand_delay_en) do_rand_delay(1, step_delay);
+ mbox_acquire_lock(op_sts); if (rand_delay_en) do_rand_delay(1, step_delay);
+ mbox_flow_proc = process::self();
+ mbox_set_cmd(mbox_op_rand); if (rand_delay_en) do_rand_delay(1, step_delay);
+ mbox_push_datain(); if (rand_delay_en) do_rand_delay(1, step_delay);
+ mbox_execute(); if (rand_delay_en) do_rand_delay(1, step_delay);
+ mbox_poll_status(); if (rand_delay_en) do_rand_delay(1, step_delay);
+ if (err_proc.status() == process::WAITING) begin
+ `uvm_info("MBOX_SEQ", "Ending SRAM bit flip injection thread before it has completed!", UVM_LOW)
+ disable ERR_INJECT_FLOW;
+ end
+ else if (err_proc.status() != process::FINISHED) begin
+ `uvm_error("MBOX_SEQ", $sformatf("Error process is in unexpected state %s!", err_proc.status().name()))
+ end
+ end
+ begin: ERR_INJECT_FLOW
+ err_proc = process::self();
+ wait(mbox_flow_proc != null);
+ // Wait and do the SRAM error injection at some random point in the sequence
+ do_rand_delay(1, DLY_CUSTOM);
+ `uvm_info("MBOX_SEQ", "Triggering Mailbox SRAM double-bit flip injection", UVM_LOW)
+ set_mbox_sram_ecc_double_error_injection();
+ end
+ join
+ mbox_clr_execute(); if (rand_delay_en) do_rand_delay(1, step_delay);
+ mbox_teardown();
+
+ endtask
+
+endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_small_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_small_sequence.svh
new file mode 100644
index 000000000..37e77b4b1
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_small_sequence.svh
@@ -0,0 +1,44 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Extended from Mailbox SRAM double bit flip injection
+// sequence for the special 'small' test case
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_mbox_sram_double_bit_flip_small_sequence extends soc_ifc_env_mbox_sram_double_bit_flip_sequence;
+
+ `uvm_object_utils( soc_ifc_env_mbox_sram_double_bit_flip_small_sequence )
+
+ // Constrain dlen to be a small command
+ // Max. size: 512B
+ constraint mbox_dlen_max_small_c { mbox_op_rand.dlen <= 32'h0000_0200; }
+ // Constrain response data size to also be small
+ // Max. size: 512B
+ constraint mbox_resp_dlen_max_small_c { mbox_resp_expected_dlen < 32'h0000_0200; }
+ // Valid solution for the custom delay ruleset, to control random delays while
+ // waiting to inject random error accesses
+ constraint custom_delay_c { rand_delay > 0;
+ rand_delay dist {[1 :mbox_op_rand.dlen*2 -1] :/ 250,
+ [mbox_op_rand.dlen*2 :mbox_op_rand.dlen*5 -1] :/ 100,
+ [mbox_op_rand.dlen*5 :mbox_op_rand.dlen*15-1] :/ 25}; }
+
+endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_soc_mbox_reg_axs_invalid_handler_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_soc_mbox_reg_axs_invalid_handler_sequence.svh
index 44cf1d5ec..9c5b1a209 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_soc_mbox_reg_axs_invalid_handler_sequence.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_soc_mbox_reg_axs_invalid_handler_sequence.svh
@@ -45,6 +45,7 @@ class soc_ifc_env_soc_mbox_reg_axs_invalid_handler_sequence extends soc_ifc_env_
virtual task body();
op_sts_e op_sts;
+ bit do_fsm_chk = 1;
process mbox_flow_proc;
reg_model = configuration.soc_ifc_rm;
@@ -73,9 +74,14 @@ class soc_ifc_env_soc_mbox_reg_axs_invalid_handler_sequence extends soc_ifc_env_
mbox_pop_dataout();
// Return control to uC
+ if (sts_rsp_count && !soc_ifc_status_agent_rsp_seq.rsp.mailbox_data_avail) begin
+ // Our random_reg_write may write to mbox_status and cause us to exit EXECUTE_SOC early...
+ do_fsm_chk = 0;
+ end
mbox_set_status();
configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(2); // Takes a few cycles for FSM update to propagate into register
- mbox_check_fsm();
+ if (do_fsm_chk)
+ mbox_check_fsm();
end
begin: ERR_INJECT_FLOW
wait(mbox_flow_proc != null);
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/wdt/cptra/soc_ifc_env_cptra_wdt_cascade_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/wdt/cptra/soc_ifc_env_cptra_wdt_cascade_sequence.svh
new file mode 100644
index 000000000..58822372a
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/wdt/cptra/soc_ifc_env_cptra_wdt_cascade_sequence.svh
@@ -0,0 +1,49 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Bringup sequence for the SOC_IFC environment
+// (essentially just a cold-reset sequence)
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_cptra_wdt_cascade_sequence extends soc_ifc_env_wdt_sequence_base;
+
+
+ `uvm_object_utils( soc_ifc_env_cptra_wdt_cascade_sequence )
+
+ // typedef soc_ifc_ctrl_sequence_base soc_ifc_ctrl_sequence_t;
+ // soc_ifc_ctrl_sequence_t soc_ifc_ctrl_seq;
+
+ typedef soc_ifc_ctrl_wdt_cascade_sequence soc_ifc_ctrl_wdt_cascade_sequence_t;
+
+ function new(string name = "" );
+ uvm_object obj;
+ super.new(name);
+ // soc_ifc_ctrl_seq = soc_ifc_ctrl_sequence_t::type_id::create("soc_ifc_ctrl_seq");
+ obj = soc_ifc_ctrl_wdt_cascade_sequence_t::get_type().create_object("soc_ifc_ctrl_wdt_cascade_seq");
+ if (!$cast(soc_ifc_ctrl_seq,obj))
+ `uvm_fatal("SOC_IFC_WDT", "Failed to cast object as WDT sequence!")
+ endfunction
+
+ endclass
+
\ No newline at end of file
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/wdt/cptra/soc_ifc_env_cptra_wdt_independent_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/wdt/cptra/soc_ifc_env_cptra_wdt_independent_sequence.svh
new file mode 100644
index 000000000..9334e1004
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/wdt/cptra/soc_ifc_env_cptra_wdt_independent_sequence.svh
@@ -0,0 +1,49 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Bringup sequence for the SOC_IFC environment
+// (essentially just a cold-reset sequence)
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_cptra_wdt_independent_sequence extends soc_ifc_env_wdt_sequence_base;
+
+
+ `uvm_object_utils( soc_ifc_env_cptra_wdt_independent_sequence )
+
+ // typedef soc_ifc_ctrl_sequence_base soc_ifc_ctrl_sequence_t;
+ // soc_ifc_ctrl_sequence_t soc_ifc_ctrl_seq;
+
+ typedef soc_ifc_ctrl_wdt_independent_sequence soc_ifc_ctrl_wdt_independent_sequence_t;
+
+ function new(string name = "" );
+ uvm_object obj;
+ super.new(name);
+ // soc_ifc_ctrl_seq = soc_ifc_ctrl_sequence_t::type_id::create("soc_ifc_ctrl_seq");
+ obj = soc_ifc_ctrl_wdt_independent_sequence_t::get_type().create_object("soc_ifc_ctrl_wdt_independent_seq");
+ if (!$cast(soc_ifc_ctrl_seq,obj))
+ `uvm_fatal("SOC_IFC_WDT", "Failed to cast object as WDT sequence!")
+ endfunction
+
+ endclass
+
\ No newline at end of file
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/wdt/cptra/soc_ifc_env_wdt_sequence_base.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/wdt/cptra/soc_ifc_env_wdt_sequence_base.svh
new file mode 100644
index 000000000..940209c2f
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/wdt/cptra/soc_ifc_env_wdt_sequence_base.svh
@@ -0,0 +1,120 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Issue a reset in the soc_ifc environment
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_wdt_sequence_base extends soc_ifc_env_sequence_base #(.CONFIG_T(soc_ifc_env_configuration_t));
+
+
+ `uvm_object_utils( soc_ifc_env_wdt_sequence_base )
+
+ typedef soc_ifc_ctrl_sequence_base soc_ifc_ctrl_sequence_t;
+ soc_ifc_ctrl_sequence_t soc_ifc_ctrl_seq;
+
+ // caliptra_apb_user apb_user_obj;
+
+ // typedef struct packed {
+ // bit set_bootfsm_breakpoint;
+ // security_state_t security_state;
+ // } ctrl_reset_seq_context_t;
+
+ // rand uvm_reg_data_t uds_seed_rand [12];
+ // rand uvm_reg_data_t field_entropy_rand [32];
+ // rand uvm_reg_data_t owner_pk_hash_rand [12];
+ // rand uvm_reg_data_t key_manifest_pk_hash_rand [12];
+ // rand uvm_reg_data_t idevid_cert_attr_rand [24];
+ // rand uvm_reg_data_t soc_stepping_id_rand;
+ // rand struct packed {
+ // bit uds;
+ // bit field_entropy;
+ // bit [0:11] key_manifest_pk_hash;
+ // bit [0:11] owner_pk_hash;
+ // bit soc_stepping_id;
+ // bit [0:23] idevid_cert_attr;
+ // bit lms_verify;
+ // } fuses_to_set;
+
+
+ //==========================================
+ // Name: new
+ // Description: Constructor
+ //==========================================
+ function new(string name = "" );
+ super.new(name);
+ soc_ifc_ctrl_seq = soc_ifc_ctrl_sequence_t::type_id::create("soc_ifc_ctrl_seq");
+
+ // Setup a User object to override PAUSER
+ // apb_user_obj = new();
+
+ endfunction
+
+
+ //==========================================
+ // Name: run_ctrl_seq
+ // Description: Run low-level soc_ifc_ctrl sequence to wiggle gen input wires to let RT fw know which mode of WDT to enable
+ //==========================================
+ virtual task run_ctrl_seq();
+ if ( configuration.soc_ifc_ctrl_agent_config.sequencer != null )
+ soc_ifc_ctrl_seq.start(configuration.soc_ifc_ctrl_agent_config.sequencer);
+ else
+ `uvm_error("SOC_IFC_WDT", "soc_ifc_ctrl_agent_config.sequencer is null!")
+
+ endtask
+
+
+
+
+ //==========================================
+ // Name: pre_body
+ // Description: Setup tasks to:
+ // - get a reg model handle
+ // - check for a valid responder handle
+ //==========================================
+ virtual task pre_body();
+ super.pre_body();
+ reg_model = configuration.soc_ifc_rm;
+ if (soc_ifc_status_agent_rsp_seq == null)
+ `uvm_fatal("SOC_IFC_WDT", "SOC_IFC ENV wdt sequence expected a handle to the soc_ifc status agent responder sequence (from bench-level sequence) but got null!")
+ // apb_user_obj.set_addr_user(reg_model.soc_ifc_reg_rm.CPTRA_MBOX_VALID_PAUSER[0].PAUSER.get_reset("HARD"));
+ endtask
+
+
+ //==========================================
+ // Name: body
+ // Description: Run the main functionality
+ //==========================================
+ virtual task body();
+
+
+ // Run ctrl seq
+ run_ctrl_seq();
+
+
+
+ endtask
+
+ endclass
+
+
\ No newline at end of file
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/soc_ifc_env_pkg.sv b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/soc_ifc_env_pkg.sv
index 336300eda..38fae2c2f 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/soc_ifc_env_pkg.sv
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/soc_ifc_env_pkg.sv
@@ -187,6 +187,14 @@ package soc_ifc_env_pkg;
typedef soc_ifc_env_mbox_dlen_underflow_medium_sequence soc_ifc_env_mbox_dlen_underflow_medium_sequence_t;
`include "sequences/mbox/soc_ifc/soc_ifc_env_mbox_dlen_underflow_large_sequence.svh"
typedef soc_ifc_env_mbox_dlen_underflow_large_sequence soc_ifc_env_mbox_dlen_underflow_large_sequence_t;
+ `include "sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_sequence.svh"
+ typedef soc_ifc_env_mbox_sram_double_bit_flip_sequence soc_ifc_env_mbox_sram_double_bit_flip_sequence_t;
+ `include "sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_small_sequence.svh"
+ typedef soc_ifc_env_mbox_sram_double_bit_flip_small_sequence soc_ifc_env_mbox_sram_double_bit_flip_small_sequence_t;
+ `include "sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_medium_sequence.svh"
+ typedef soc_ifc_env_mbox_sram_double_bit_flip_medium_sequence soc_ifc_env_mbox_sram_double_bit_flip_medium_sequence_t;
+ `include "sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_large_sequence.svh"
+ typedef soc_ifc_env_mbox_sram_double_bit_flip_large_sequence soc_ifc_env_mbox_sram_double_bit_flip_large_sequence_t;
`include "sequences/mbox/soc_ifc/soc_ifc_env_mbox_rand_multi_agent_sequence.svh"
typedef soc_ifc_env_mbox_rand_multi_agent_sequence soc_ifc_env_mbox_rand_multi_agent_sequence_t;
`include "sequences/mbox/soc_ifc/soc_ifc_env_mbox_rst_sequence.svh"
@@ -207,6 +215,12 @@ package soc_ifc_env_pkg;
typedef soc_ifc_env_soc_mbox_handler_sequence soc_ifc_env_soc_mbox_handler_sequence_t;
`include "sequences/mbox/soc_ifc/soc_ifc_env_soc_mbox_reg_axs_invalid_handler_sequence.svh"
typedef soc_ifc_env_soc_mbox_reg_axs_invalid_handler_sequence soc_ifc_env_soc_mbox_reg_axs_invalid_handler_sequence_t;
+ `include "sequences/wdt/cptra/soc_ifc_env_wdt_sequence_base.svh"
+ typedef soc_ifc_env_wdt_sequence_base soc_ifc_env_wdt_sequence_base_t;
+ `include "sequences/wdt/cptra/soc_ifc_env_cptra_wdt_independent_sequence.svh"
+ typedef soc_ifc_env_cptra_wdt_independent_sequence soc_ifc_env_cptra_wdt_independent_sequence_t;
+ `include "sequences/wdt/cptra/soc_ifc_env_cptra_wdt_cascade_sequence.svh"
+ typedef soc_ifc_env_cptra_wdt_cascade_sequence soc_ifc_env_cptra_wdt_cascade_sequence_t;
///////////////////// Sequences usable from soc_ifc bench only /////////////////////
// These sequences include stimulus for the internal/caliptra-side of the
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_environment.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_environment.svh
index 2be6c1251..0b2c30b66 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_environment.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_environment.svh
@@ -319,6 +319,10 @@ function void soc_ifc_environment::set_can_handle_reset(bit en = 1'b1);
endfunction
task soc_ifc_environment::handle_reset(string kind = "HARD");
+ uvm_object obj;
+ uvm_event reset_synchro;
+ reset_flag rst_sync_flag;
+
// Reset status agents (needed to reset monitor transaction keys)
this.cptra_status_agent.handle_reset(kind);
this.soc_ifc_status_agent.handle_reset(kind);
@@ -330,7 +334,32 @@ task soc_ifc_environment::handle_reset(string kind = "HARD");
this.soc_ifc_sb.handle_reset(kind);
// Reset predictor according to kind
- this.soc_ifc_pred.handle_reset(kind);
+ this.soc_ifc_pred.handle_reset(kind, reset_synchro);
+
+ // A "SOFT" reset (cptra_rst_b) is followed by noncore reset assertion; we
+ // need to time the assertion of the reset to all the soc_ifc_env components
+ // based on the predictor
+ if (kind == "SOFT") begin
+ `uvm_info("SOC_IFC_ENV_HANDLE_RESET", "After receiving SOFT reset, waiting for predictor to signal the NONCORE reset so environment can be reset", UVM_LOW)
+
+ reset_synchro.wait_trigger_data(obj);
+ $cast(rst_sync_flag, obj);
+ if (rst_sync_flag.get_name() != "noncore_reset_flag")
+ `uvm_error("SOC_IFC_ENV_HANDLE_RESET", {"Reset synchronization event returned a reset event of unexpected type! ", rst_sync_flag.get_name()})
+
+ // Reset status agents (needed to reset monitor transaction keys)
+ this.cptra_status_agent.handle_reset("NONCORE");
+ this.soc_ifc_status_agent.handle_reset("NONCORE");
+
+ // Reset mbox_sram agent (needed to reset the ECC error injection)
+ this.mbox_sram_agent.handle_reset("NONCORE");
+
+ // Reset scoreboard according to kind
+ this.soc_ifc_sb.handle_reset("NONCORE");
+
+ `uvm_info("SOC_IFC_ENV_HANDLE_RESET", "After receiving NONCORE reset signal from soc_ifc_predictor, completed environment-level NONCORE reset prerequisites and continuing with reset prediction", UVM_LOW)
+ reset_synchro.reset();
+ end
// TODO does this happen naturally from hdl_top driving reset?
// Reset APB
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_predictor.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_predictor.svh
index ea6ed26c0..9e1465f0f 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_predictor.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_predictor.svh
@@ -161,6 +161,8 @@ class soc_ifc_predictor #(
uvm_analysis_port #(mvc_sequence_item_base) soc_ifc_ahb_reg_ap;
uvm_analysis_port #(mvc_sequence_item_base) soc_ifc_apb_reg_ap;
+ process running_dly_jobs[$];
+ int unsigned job_end_count[time];
bit cptra_pwrgood_asserted = 1'b0;
bit soc_ifc_rst_in_asserted = 1'b1;
bit noncore_rst_out_asserted = 1'b1;
@@ -187,10 +189,12 @@ class soc_ifc_predictor #(
int datain_count = 0;
int dataout_count = 0;
+ bit dataout_mismatch_expected = 1'b0;
+
bit [31:0] nmi_vector = 32'h0;
bit iccm_locked = 1'b0;
bit [`CLP_OBF_KEY_DWORDS-1:0] [31:0] cptra_obf_key_reg = '{default:32'h0}; // FIXME use reg-model value?
- security_state_t security_state = '{debug_locked: 1'b1, device_lifecycle: DEVICE_UNPROVISIONED};
+ security_state_t security_state = '{debug_locked: 1'b1, device_lifecycle: DEVICE_UNPROVISIONED}; // FIXME unused
bit bootfsm_breakpoint = 1'b0;
bit cptra_in_dbg_or_manuf_mode = 1'b0;
int unsigned fw_update_wait_count = 0;
@@ -219,6 +223,7 @@ class soc_ifc_predictor #(
reset_flag hard_reset_flag;
reset_flag soft_reset_flag;
+ reset_flag noncore_reset_flag;
//WDT vars:
bit [63:0] t1_count, t2_count;
@@ -238,12 +243,11 @@ class soc_ifc_predictor #(
extern task mtime_counter_task();
extern function bit mtime_lt_mtimecmp();
extern task wdt_counter_task();
- extern task wdt_counter_trial();
extern function bit valid_requester(input uvm_transaction txn);
extern function bit valid_receiver(input uvm_transaction txn);
extern function bit sha_valid_user(input uvm_transaction txn);
extern function void predict_boot_wait_boot_done();
- extern task handle_reset(input string kind = "HARD");
+ extern task handle_reset(input string kind = "HARD", output uvm_event reset_synchro);
extern function void predict_reset(input string kind = "HARD");
extern function bit soc_ifc_status_txn_expected_after_noncore_reset();
extern function bit cptra_status_txn_expected_after_noncore_reset();
@@ -289,6 +293,7 @@ class soc_ifc_predictor #(
reset_handled = new("reset_handled");
hard_reset_flag = new("hard_reset_flag"); // Used as trigger data for reset events. In UVM 1.2, data changes from a uvm_object to a string
soft_reset_flag = new("soft_reset_flag"); // Used as trigger data for reset events. In UVM 1.2, data changes from a uvm_object to a string
+ noncore_reset_flag = new("noncore_reset_flag"); // Used as trigger data for reset events. In UVM 1.2, data changes from a uvm_object to a string
// pragma uvmf custom build_phase end
endfunction
@@ -414,22 +419,24 @@ class soc_ifc_predictor #(
if (soc_ifc_rst_in_asserted) begin
// Todo check for breakpoint assertion and flag an expected AHB write to clear it
soc_ifc_rst_in_asserted = 1'b0;
- p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_FLOW_STATUS.ready_for_fuses.predict(1'b1);
cptra_in_dbg_or_manuf_mode = ~t.security_state.debug_locked || t.security_state.device_lifecycle == DEVICE_MANUFACTURING;
bootfsm_breakpoint = t.set_bootfsm_breakpoint && cptra_in_dbg_or_manuf_mode;
reset_predicted.reset();
- send_soc_ifc_sts_txn = 1;
+ send_soc_ifc_sts_txn = 0; // prediction for ready_for_fuses done in predict_reset after noncore reset deassertion
send_cptra_sts_txn = 0; // cptra sts transaction not expected until after CPTRA_FUSE_WR_DONE
reset_wdt_count = 1'b0;
- fork
- configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(6); // FIXME, correct delay value?
- rdc_clk_gate_active = 1'b0;
- join_none
`uvm_info("PRED_SOC_IFC_CTRL", $sformatf("In response to warm_reset deassertion, send_soc_ifc_sts_txn: %d", send_soc_ifc_sts_txn), UVM_NONE)
end
// Normal operation
else begin
//TODO this block needs more logic
+ if (t.generic_input_val ^ {SOC_IFC_DATA_W'(p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_GENERIC_INPUT_WIRES[1].generic_wires.get_mirrored_value()), SOC_IFC_DATA_W'(p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_GENERIC_INPUT_WIRES[0].generic_wires.get_mirrored_value())}) begin
+ `uvm_info("PRED_SOC_IFC_CTRL", "Detected toggle in generic_input_wires", UVM_HIGH)
+ p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.notif_internal_intr_r.notif_gen_in_toggle_sts.predict(1'b1, -1, UVM_PREDICT_READ, UVM_PREDICT, p_soc_ifc_AHB_map); /* AHB-access only, use AHB map*/
+ //Update reg model with the generic_input_val
+ p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_GENERIC_INPUT_WIRES[0].generic_wires.predict(t.generic_input_val[31:0], -1, UVM_PREDICT_READ, UVM_PREDICT, p_soc_ifc_AHB_map);
+ p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_GENERIC_INPUT_WIRES[1].generic_wires.predict(t.generic_input_val[63:32], -1, UVM_PREDICT_READ, UVM_PREDICT, p_soc_ifc_AHB_map);
+ end
end
end
@@ -588,8 +595,15 @@ class soc_ifc_predictor #(
soc_ifc_sb_ahb_ap_output_transaction = soc_ifc_sb_ahb_ap_output_transaction_t::type_id::create("soc_ifc_sb_ahb_ap_output_transaction");
soc_ifc_sb_apb_ap_output_transaction = soc_ifc_sb_apb_ap_output_transaction_t::type_id::create("soc_ifc_sb_apb_ap_output_transaction");
- if (t.is_read && t.ecc_double_bit_error) begin
+ if (rdc_clk_gate_active || noncore_rst_out_asserted) begin
+ `uvm_info("PRED_MBOX_SRAM", "Received transaction while RDC clock gate is active, no system prediction to do since interrupt bits cannot be set", UVM_MEDIUM)
+ end
+ else if (t.is_read && t.ecc_double_bit_error) begin
p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.error_internal_intr_r.error_mbox_ecc_unc_sts.predict(1'b1, -1, UVM_PREDICT_READ, UVM_PREDICT, p_soc_ifc_AHB_map); /* AHB-access only, use AHB map*/
+ p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc.predict(1'b1, -1, UVM_PREDICT_READ, UVM_PREDICT, p_soc_ifc_AHB_map);
+ dataout_mismatch_expected = 1'b1;
+ cptra_error_non_fatal = 1'b1;
+ send_soc_ifc_sts_txn = 1'b1;
`uvm_info("PRED_MBOX_SRAM", "Received read transaction with Double bit ECC corruption, triggering the err interrupt", UVM_MEDIUM)
end
else if (t.is_read && t.ecc_single_bit_error) begin
@@ -599,7 +613,6 @@ class soc_ifc_predictor #(
else begin
`uvm_info("PRED_MBOX_SRAM", "Received mailbox SRAM transaction does not cause a system state change prediction", UVM_FULL)
end
- // TODO HW_ERROR_NON_FATAL activity?
// Code for sending output transaction out through soc_ifc_sb_ap
// Please note that each broadcasted transaction should be a different object than previously
@@ -609,7 +622,7 @@ class soc_ifc_predictor #(
if (send_soc_ifc_sts_txn) begin
populate_expected_soc_ifc_status_txn(soc_ifc_sb_ap_output_transaction);
soc_ifc_sb_ap.write(soc_ifc_sb_ap_output_transaction);
- `uvm_error("PRED_MBOX_SRAM", "NULL Transaction submitted through soc_ifc_sb_ap")
+ `uvm_info("PRED_MBOX_SRAM", "Transaction submitted through soc_ifc_sb_ap", UVM_MEDIUM)
end
// Code for sending output transaction out through cptra_sb_ap
// Please note that each broadcasted transaction should be a different object than previously
@@ -775,6 +788,14 @@ class soc_ifc_predictor #(
// "Expected" read data for scoreboard is current
// mirrored value prior to running do_predict
soc_ifc_sb_ahb_ap_output_transaction.data[0] = axs_reg.get_mirrored_value() << 8*(address_aligned % (ahb_lite_slave_0_params::AHB_WDATA_WIDTH/8));
+ // ... unless it's an ECC double bit error, just use the
+ // observed data to avoid a scoreboard error (since the
+ // mismatch is anticipated)
+ if (dataout_mismatch_expected) begin
+ `uvm_info("PRED_AHB", "Ignoring mbox_dataout predicted contents and using observed AHB data due to prior ECC double bit flip", UVM_HIGH)
+ dataout_mismatch_expected = 1'b0;
+ soc_ifc_sb_ahb_ap_output_transaction.data[0] = ahb_txn.data[0];
+ end
dataout_count++;
end
else begin
@@ -1253,11 +1274,16 @@ class soc_ifc_predictor #(
end
end
"CPTRA_WDT_TIMER1_CTRL": begin
- if (ahb_txn.RnW == AHB_WRITE) begin
- // Handled in callbacks via reg predictor
- `uvm_info("PRED_AHB", $sformatf("Handling access to %s. This will restart WDT timer1", axs_reg.get_name()), UVM_MEDIUM);
- //Capture restart bit so the counters can be updated
- wdt_t1_restart = data_active[p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_TIMER1_CTRL.timer1_restart.get_lsb_pos()];
+ if (ahb_txn.RnW == AHB_WRITE && data_active[p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_TIMER1_CTRL.timer1_restart.get_lsb_pos()]) begin
+ `uvm_info("PRED_AHB", $sformatf("Handling access to %s. This will restart WDT timer1 after 1 clock cycle", axs_reg.get_name()), UVM_MEDIUM);
+ fork
+ begin
+ configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(1);
+ //Capture restart bit so the counters can be updated
+ wdt_t1_restart = 1;
+ `uvm_info("PRED_AHB", $sformatf("After delay from access to %s - restart WDT timer1", axs_reg.get_name()), UVM_MEDIUM);
+ end
+ join_none
end
end
"CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[0]",
@@ -1272,11 +1298,16 @@ class soc_ifc_predictor #(
end
end
"CPTRA_WDT_TIMER2_CTRL": begin
- if (ahb_txn.RnW == AHB_WRITE) begin
- // Handled in callbacks via reg predictor
- `uvm_info("PRED_AHB", $sformatf("Handling access to %s. This will restart WDT timer2", axs_reg.get_name()), UVM_MEDIUM);
- //Capture restart bit so the counters can be updated
- wdt_t2_restart = data_active[p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_TIMER2_CTRL.timer2_restart.get_lsb_pos()];
+ if (ahb_txn.RnW == AHB_WRITE && data_active[p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_TIMER2_CTRL.timer2_restart.get_lsb_pos()]) begin
+ `uvm_info("PRED_AHB", $sformatf("Handling access to %s. This will restart WDT timer2 after 1 clock cycle", axs_reg.get_name()), UVM_MEDIUM);
+ fork
+ begin
+ configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(1);
+ //Capture restart bit so the counters can be updated
+ wdt_t2_restart = 1;
+ `uvm_info("PRED_AHB", $sformatf("After delay from access to %s - restart WDT timer2", axs_reg.get_name()), UVM_MEDIUM);
+ end
+ join_none
end
end
"CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[0]",
@@ -1343,18 +1374,11 @@ class soc_ifc_predictor #(
`uvm_error("PRED_AHB", {"Unexpected write to ",axs_reg.get_name()," register on AHB interface"})
end
end
- "internal_fw_update_reset": begin
+ "internal_fw_update_reset",
+ "internal_fw_update_reset_wait_cycles": begin
// Handled in callbacks via reg predictor
`uvm_info("PRED_AHB", $sformatf("Handling access to register %s. Nothing to do.", axs_reg.get_name()), UVM_DEBUG)
end
- "internal_fw_update_reset_wait_cycles": begin
- if (ahb_txn.RnW == AHB_WRITE) begin
- `uvm_error("PRED_AHB", $sformatf("FIXME - need to add logic for writes to register %s", axs_reg.get_name())) // TODO
- end
- else begin
- `uvm_info("PRED_AHB", {"Read from ", axs_reg.get_name(), " has no effect"}, UVM_DEBUG)
- end
- end
"internal_nmi_vector": begin
if (ahb_txn.RnW == AHB_WRITE) begin
if (nmi_vector != data_active) begin
@@ -1730,6 +1754,14 @@ class soc_ifc_predictor #(
// "Expected" read data for scoreboard is current
// mirrored value prior to running do_predict
soc_ifc_sb_apb_ap_output_transaction.rd_data = axs_reg.get_mirrored_value();
+ // ... unless it's an ECC double bit error, just use the
+ // observed data to avoid a scoreboard error (since the
+ // mismatch is anticipated)
+ if (dataout_mismatch_expected) begin
+ `uvm_info("PRED_APB", "Ignoring mbox_dataout predicted contents and using observed APB data due to prior ECC double bit flip", UVM_HIGH)
+ dataout_mismatch_expected = 1'b0;
+ soc_ifc_sb_apb_ap_output_transaction.rd_data = apb_txn.rd_data;
+ end
dataout_count++;
end
else begin
@@ -2455,12 +2487,14 @@ function void soc_ifc_predictor::send_delayed_expected_transactions();
soc_ifc_notif_intr_pending = 1'b0;
end
- // mbox protocol violations TODO
- if (!cptra_error_fatal && |p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_HW_ERROR_FATAL.get_mirrored_value()) begin
- `uvm_info("PRED_DLY", "Delay job triggers cptra_error_fatal output", UVM_HIGH)
- cptra_error_fatal = 1;
- send_soc_ifc_sts_txn = 1'b1;
- end
+// if (!cptra_error_fatal && |p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_HW_ERROR_FATAL.get_mirrored_value()) begin
+// `uvm_info("PRED_DLY", "Delay job triggers cptra_error_fatal output", UVM_HIGH)
+// cptra_error_fatal = 1;
+// send_soc_ifc_sts_txn = 1'b1;
+// end
+ // mbox protocol violations
+ // TODO The interrupt is cleared by warm reset even though reg values are not - the assertion
+ // should be tied directly to the event detection instead of comparing the interrupt value with the reg mirror value
if (!cptra_error_non_fatal && |p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_HW_ERROR_NON_FATAL.get_mirrored_value()) begin
`uvm_info("PRED_DLY", "Delay job triggers cptra_error_non_fatal output", UVM_HIGH)
cptra_error_non_fatal = 1;
@@ -2476,6 +2510,10 @@ function void soc_ifc_predictor::send_delayed_expected_transactions();
else if (soc_ifc_error_intr_pending && !(p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.error_global_intr_r.agg_sts.get_mirrored_value() && p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.global_intr_en_r.error_en.get_mirrored_value())) begin
`uvm_info("PRED_DLY", "Delay job causes soc_ifc error_intr deassertion", UVM_HIGH)
soc_ifc_error_intr_pending = 1'b0;
+ if (p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_STATUS.t1_timeout.get_mirrored_value())
+ p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_STATUS.t1_timeout.predict(1'b0, -1, UVM_PREDICT_READ, UVM_PREDICT, p_soc_ifc_AHB_map);
+ if (p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_STATUS.t2_timeout.get_mirrored_value())
+ p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_STATUS.t2_timeout.predict(1'b0, -1, UVM_PREDICT_READ, UVM_PREDICT, p_soc_ifc_AHB_map);
end
// Check for Timer Interrupt
@@ -2563,19 +2601,32 @@ endfunction
// This task detects those scheduled jobs and runs them after waiting for
// the specified delay.
task soc_ifc_predictor::poll_and_run_delay_jobs();
- // FIXME reset!
forever begin
while (p_soc_ifc_rm.delay_jobs.size() > 0) begin
fork
soc_ifc_reg_delay_job job = p_soc_ifc_rm.delay_jobs.pop_front();
- begin
+ if (!noncore_rst_out_asserted) begin
+ int idx[$];
+ time end_time;
+ running_dly_jobs.push_back(process::self()); // This tracks all the delay_jobs that are pending so they can be clobbered on rst
+ `uvm_info("PRED_DLY", $sformatf("Doing delay of %0d cycles before running delay job with signature: %s", job.get_delay_cycles(), job.get_name()), UVM_HIGH/*UVM_FULL*/)
+ end_time = $time + 10*job.get_delay_cycles();
+ job_end_count[end_time] += 1;
// delay cycles reported as 0's based value, since 1-cycle delay
// is inherent to this forever loop
if (job.get_delay_cycles()) configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(job.get_delay_cycles());
uvm_wait_for_nba_region();
+ idx = running_dly_jobs.find_first_index(pr) with (pr == process::self());
+ running_dly_jobs.delete(idx.pop_front());
job.do_job();
+ job_end_count[end_time] -= 1;
// p_soc_ifc_rm.sample_values(); /* Sample coverage after completing any delayed prediction/mirror updates */ // NOTE: Added sample post_predict callback to reg fields instead
- send_delayed_expected_transactions();
+ // Aggregate the results of all delay jobs that end on the same clock cycle into a
+ // single method call that sends all the predited transactions
+ if (job_end_count[end_time] == 0) begin
+ job_end_count.delete(end_time);
+ send_delayed_expected_transactions();
+ end
end
join_none
end
@@ -2834,7 +2885,9 @@ task soc_ifc_predictor::wdt_counter_task();
bit wdt_t1_restart_temp;
cptra_sb_ap_output_transaction_t local_cptra_sb_ap_txn;
+ soc_ifc_sb_ap_output_transaction_t local_soc_ifc_sb_ap_txn;
local_cptra_sb_ap_txn = cptra_sb_ap_output_transaction_t::type_id::create("local_cptra_sb_ap_txn");
+ local_soc_ifc_sb_ap_txn = soc_ifc_sb_ap_output_transaction_t::type_id::create("local_soc_ifc_sb_ap_txn");
//Poll for WDT enable bits
wdt_reg_data = p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_TIMER1_EN.timer1_en.get(); //_mirrored_value();
@@ -2846,14 +2899,14 @@ task soc_ifc_predictor::wdt_counter_task();
cascade = (wdt_t1_en && !wdt_t2_en);
independent = wdt_t2_en;
- wdt_reg_data = p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[0].timer1_timeout_period.get();
+ wdt_reg_data = p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[0].timer1_timeout_period.get_mirrored_value();
wdt_t1_period[31:0] = wdt_reg_data[31:0];
- wdt_reg_data = p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[1].timer1_timeout_period.get();
+ wdt_reg_data = p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[1].timer1_timeout_period.get_mirrored_value();
wdt_t1_period[63:32] = wdt_reg_data[31:0];
- wdt_reg_data = p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[0].timer2_timeout_period.get();
+ wdt_reg_data = p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[0].timer2_timeout_period.get_mirrored_value();
wdt_t2_period[31:0] = wdt_reg_data[31:0];
- wdt_reg_data = p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[1].timer2_timeout_period.get();
+ wdt_reg_data = p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[1].timer2_timeout_period.get_mirrored_value();
wdt_t2_period[63:32] = wdt_reg_data[31:0];
//Reset event
@@ -2864,11 +2917,13 @@ task soc_ifc_predictor::wdt_counter_task();
this.wdt_error_intr_sent = 1'b0;
this.wdt_t2_error_intr_sent = 1'b0;
this.wdt_nmi_intr_sent = 1'b0;
+ p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_STATUS.t1_timeout.predict(1'b0, -1, UVM_PREDICT_READ, UVM_PREDICT, p_soc_ifc_AHB_map);
+ p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_STATUS.t2_timeout.predict(1'b0, -1, UVM_PREDICT_READ, UVM_PREDICT, p_soc_ifc_AHB_map);
end
//Cascade mode
if (cascade) begin
- if (this.wdt_t1_restart) begin
+ if (this.wdt_t1_restart && !p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_STATUS.t1_timeout.get_mirrored_value()) begin
this.t1_count = 'h0;
`uvm_info("PRED_WDT", "Cascade mode, received t1 pet - restarting t1 count", UVM_MEDIUM)
this.wdt_t1_restart = 1'b0; //Reset flag so we can capture another restart event
@@ -2883,7 +2938,7 @@ task soc_ifc_predictor::wdt_counter_task();
if (!this.wdt_error_intr_sent) begin
`uvm_info("PRED_WDT", "Timer1 expired in cascade mode. Starting timer2", UVM_MEDIUM)
p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.error_internal_intr_r.error_wdt_timer1_timeout_sts.predict(1'b1, -1, UVM_PREDICT_READ, UVM_PREDICT, p_soc_ifc_AHB_map);
-
+ p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_STATUS.t1_timeout.predict(1'b1, -1, UVM_PREDICT_READ, UVM_PREDICT, p_soc_ifc_AHB_map);
//Set a flag so we don't keep sending transactions while the timer holds value until interrupt
//is serviced or reset
this.wdt_error_intr_sent = 1'b1;
@@ -2901,11 +2956,25 @@ task soc_ifc_predictor::wdt_counter_task();
if (!this.wdt_nmi_intr_sent) begin
`uvm_info("PRED_WDT", "Timer2 expired in cascade mode. Expecting NMI to be handled", UVM_MEDIUM);
p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_HW_ERROR_FATAL.nmi_pin.predict(1'b1, -1, UVM_PREDICT_READ, UVM_PREDICT, p_soc_ifc_AHB_map); //TODO: use default map?
+ p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_STATUS.t2_timeout.predict(1'b1, -1, UVM_PREDICT_READ, UVM_PREDICT, p_soc_ifc_AHB_map);
//Sending cptra_status_txn in the same clock as NMI
nmi_intr_pending = 1'b1;
populate_expected_cptra_status_txn(local_cptra_sb_ap_txn);
cptra_sb_ap.write(local_cptra_sb_ap_txn);
+ `uvm_info("PRED_WDT", "Transaction submitted through cptra_sb_ap", UVM_MEDIUM)
+
+ // Fatal error interrupt is delayed by 1 cycle due to reg state
+ fork
+ configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(1);
+ if (!noncore_rst_out_asserted) begin
+ `uvm_info("PRED_WDT", "Watchdog timeout triggers cptra_error_fatal output", UVM_HIGH)
+ cptra_error_fatal = 1;
+ populate_expected_soc_ifc_status_txn(local_soc_ifc_sb_ap_txn);
+ soc_ifc_sb_ap.write(local_soc_ifc_sb_ap_txn);
+ `uvm_info("PRED_WDT", "Transaction submitted through soc_ifc_sb_ap", UVM_MEDIUM)
+ end
+ join_none
//Set a flag so we don't keep sending transactions while the timer holds value until interrupt
//is serviced or reset
@@ -2915,7 +2984,7 @@ task soc_ifc_predictor::wdt_counter_task();
end
end //Cascade mode
else if (independent) begin
- if (this.wdt_t1_restart) begin
+ if (this.wdt_t1_restart && !p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_STATUS.t1_timeout.get_mirrored_value()) begin
this.t1_count = 'h0;
`uvm_info("PRED_WDT", "Independent mode, received t1 pet - restarting t1 count", UVM_MEDIUM)
this.wdt_t1_restart = 1'b0; //Reset flag so we can capture another restart event
@@ -2930,6 +2999,7 @@ task soc_ifc_predictor::wdt_counter_task();
if (!this.wdt_error_intr_sent) begin
`uvm_info("PRED_WDT", "Independent mode, T1 expired", UVM_MEDIUM)
p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.error_internal_intr_r.error_wdt_timer1_timeout_sts.predict(1'b1, -1, UVM_PREDICT_READ, UVM_PREDICT, p_soc_ifc_AHB_map);
+ p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_STATUS.t1_timeout.predict(1'b1, -1, UVM_PREDICT_READ, UVM_PREDICT, p_soc_ifc_AHB_map);
//Set a flag so we don't keep sending transactions while the timer holds value until interrupt
//is serviced or reset
@@ -2944,7 +3014,7 @@ task soc_ifc_predictor::wdt_counter_task();
//-------------------------------------------------
//Timer 2
//-------------------------------------------------
- if (this.wdt_t2_restart) begin
+ if (this.wdt_t2_restart && !p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_STATUS.t2_timeout.get_mirrored_value()) begin
this.t2_count = 'h0;
`uvm_info("PRED_WDT", "Independent mode, received t2 pet - restarting t2 count", UVM_MEDIUM)
this.wdt_t2_restart = 1'b0; //Reset flag so we can capture another restart event
@@ -2959,6 +3029,7 @@ task soc_ifc_predictor::wdt_counter_task();
if (!this.wdt_t2_error_intr_sent) begin
`uvm_info("PRED_WDT", "Independent mode, T2 expired", UVM_MEDIUM)
p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.error_internal_intr_r.error_wdt_timer2_timeout_sts.predict(1'b1, -1, UVM_PREDICT_READ, UVM_PREDICT, p_soc_ifc_AHB_map);
+ p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_STATUS.t2_timeout.predict(1'b1, -1, UVM_PREDICT_READ, UVM_PREDICT, p_soc_ifc_AHB_map);
//Set a flag so we don't keep sending transactions while the timer holds value until interrupt
//is serviced or reset
@@ -3172,7 +3243,7 @@ function void soc_ifc_predictor::predict_boot_wait_boot_done();
endfunction
-task soc_ifc_predictor::handle_reset(input string kind = "HARD");
+task soc_ifc_predictor::handle_reset(input string kind = "HARD", output uvm_event reset_synchro);
uvm_object obj_triggered;
reset_flag kind_predicted;
reset_flag kind_handled;
@@ -3181,11 +3252,16 @@ task soc_ifc_predictor::handle_reset(input string kind = "HARD");
kind == "SOFT" ? soft_reset_flag :
null;
reset_handled.trigger(kind_handled);
+ `uvm_info("PRED_HANDLE_RESET", "On call to handle_reset, waiting to receive the ctrl reset transaction", UVM_HIGH)
reset_predicted.wait_trigger_data(obj_triggered);
+ `uvm_info("PRED_HANDLE_RESET", "In call to handle_reset, received the ctrl reset transaction", UVM_HIGH)
if (!$cast(kind_predicted, obj_triggered))
`uvm_fatal("PRED_HANDLE_RESET", "Failed to retrieve triggered reset_flag")
if (kind_handled != kind_predicted)
`uvm_error("PRED_HANDLE_RESET", $sformatf("handle_reset called with different reset type [%s] than was processed in predictor [%s]!", kind_handled.get_name(), kind_predicted.get_name()))
+ // Used to synchronize the noncore reset in the reset of the environment with
+ // the predictor (all other components must be reset before predictor)
+ reset_synchro = reset_handled;
endtask
function void soc_ifc_predictor::predict_reset(input string kind = "HARD");
@@ -3211,7 +3287,22 @@ function void soc_ifc_predictor::predict_reset(input string kind = "HARD");
// Do the noncore reset
`uvm_info("PRED_RESET", $sformatf("Reset prediction of kind: %p results in assertion of internal resets after a delay", kind), UVM_MEDIUM)
- configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(3); // FIXME, correct delay value?
+ fork
+ begin
+ // FIXME need to implement clk gating features in uvmf_soc_ifc
+ if (configuration.cptra_ctrl_agent_config.active_passive == PASSIVE) begin
+ configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(2);
+ uvm_wait_for_nba_region();
+ rdc_clk_gate_active = 1'b1;
+ `uvm_info("PRED_RESET", $sformatf("Reset prediction of kind: %p results in assertion of RDC clk gate", kind), UVM_MEDIUM)
+ end
+ end
+ configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(SOC_IFC_CPTRA_RST_NONCORE_RST_DELAY);
+ join
+ // Synchronize the noncore reset with the reset of the environment and allow other
+ // components to reset before proceeding with predicted activity
+ reset_handled.trigger(noncore_reset_flag);
+ reset_handled.wait_off();
predict_reset("NONCORE");
// Send predicted transactions
@@ -3230,11 +3321,10 @@ function void soc_ifc_predictor::predict_reset(input string kind = "HARD");
end: DELAY_INTERNAL_RESET_ASSERTION
join_none
end
- else if (kind == "NONCORE") begin: IMMEDIATE_INTERNAL_RESET_DEASSERTION
+ else if (kind == "NONCORE") begin: NONCORE_INTERNAL_RESET_ASSERTION
`uvm_info("PRED_RESET", $sformatf("Reset prediction of kind: %p results in assertion of internal resets", kind), UVM_MEDIUM)
noncore_rst_out_asserted = 1'b1;
uc_rst_out_asserted = 1'b1;
- rdc_clk_gate_active = 1'b1;
end
// Track the BOOT FSM internally
@@ -3246,6 +3336,9 @@ function void soc_ifc_predictor::predict_reset(input string kind = "HARD");
fork
begin
cptra_sb_ap_output_transaction_t local_cptra_sb_ap_txn;
+ soc_ifc_sb_ap_output_transaction_t local_soc_ifc_sb_ap_txn;
+
+ // Wait for cptra_rst_b deassertion
`uvm_info("PRED_RESET", $sformatf("Reset prediction of kind: %p will result in state change after reset deasserts. Wait for cptra_rst_b==1...", kind), UVM_MEDIUM)
while (last_predicted_kind != soft_reset_flag) begin
uvm_object obj_predicted;
@@ -3254,6 +3347,13 @@ function void soc_ifc_predictor::predict_reset(input string kind = "HARD");
$cast(last_predicted_kind,obj_predicted);
`uvm_info("PRED_RESET", $sformatf("After reset_predicted was cleared, last predicted kind was: %s", last_predicted_kind.get_name()), UVM_MEDIUM)
end
+
+ // Additional delay until RDC clock comes back alive
+ // NOTE: Not implemented in uvmf_soc_ifc, only occurs in caliptra_top. TODO
+ if (configuration.cptra_ctrl_agent_config.active_passive == PASSIVE)
+ configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(4); // FIXME, correct delay value?
+ rdc_clk_gate_active = 1'b0;
+
p_soc_ifc_rm.soc_ifc_reg_rm.boot_fn_state_sigs = '{boot_fuse: 1'b1, default: 1'b0};
`uvm_info("PRED_RESET", $sformatf("After detecting warm reset deassertion, boot FSM state change predicted: [%p]", p_soc_ifc_rm.soc_ifc_reg_rm.boot_fn_state_sigs), UVM_MEDIUM)
// NOTE: Next state progression is triggered by write to CPTRA_FUSE_WR_DONE
@@ -3261,14 +3361,24 @@ function void soc_ifc_predictor::predict_reset(input string kind = "HARD");
// Now, deassertion of noncore reset is delayed from state transition by 2 cycles
configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(2); // FIXME, correct delay value?
noncore_rst_out_asserted = 1'b0;
+ reset_wdt_count = 1'b0;
+ p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_FLOW_STATUS.ready_for_fuses.predict(1'b1);
// Send predicted transactions
if (1) begin
+ // cptra status is for noncore reset deassertion
local_cptra_sb_ap_txn = cptra_sb_ap_output_transaction_t::type_id::create("local_cptra_sb_ap_txn");
populate_expected_cptra_status_txn(local_cptra_sb_ap_txn);
cptra_sb_ap.write(local_cptra_sb_ap_txn);
`uvm_info("PRED_RESET", "Transaction submitted through cptra_sb_ap", UVM_MEDIUM)
end
+ if (1) begin
+ // soc_ifc status is for ready_for_fuses
+ local_soc_ifc_sb_ap_txn = soc_ifc_sb_ap_output_transaction_t::type_id::create("local_soc_ifc_sb_ap_txn");
+ populate_expected_soc_ifc_status_txn(local_soc_ifc_sb_ap_txn);
+ soc_ifc_sb_ap.write(local_soc_ifc_sb_ap_txn);
+ `uvm_info("PRED_RESET", "Transaction submitted through soc_ifc_sb_ap", UVM_MEDIUM)
+ end
end
join_none
end
@@ -3279,9 +3389,6 @@ function void soc_ifc_predictor::predict_reset(input string kind = "HARD");
if (kind inside {"HARD", "SOFT"}) begin: RESET_VAL_CHANGES_HARD_SOFT
soc_ifc_rst_in_asserted = 1'b1;
p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_FLOW_STATUS.ready_for_fuses.predict(1'b0);
-
- cptra_error_fatal = 1'b0;
- cptra_error_non_fatal = 1'b0;
end: RESET_VAL_CHANGES_HARD_SOFT
// Signals that are tied to reg values are not reset by warm reset until it
@@ -3300,6 +3407,9 @@ function void soc_ifc_predictor::predict_reset(input string kind = "HARD");
generic_output_wires = '0;
+ cptra_error_fatal = 1'b0;
+ cptra_error_non_fatal = 1'b0;
+
//WDT
nmi_intr_pending = 1'b0; //Reset nmi_intr on reset assertion
reset_wdt_count = 1'b1;
@@ -3336,6 +3446,8 @@ function void soc_ifc_predictor::predict_reset(input string kind = "HARD");
datain_count = 0;
dataout_count = 0;
+ dataout_mismatch_expected = 1'b0;
+
end: RESET_VAL_CHANGES_HARD_NONCORE
if (kind == "HARD") begin: RESET_VAL_CHANGES_HARD
@@ -3344,14 +3456,26 @@ function void soc_ifc_predictor::predict_reset(input string kind = "HARD");
fuse_update_enabled = 1'b1; // Fuses only latch new values from APB write after a cold-reset (which clears CPTRA_FUSE_WR_DONE)
end: RESET_VAL_CHANGES_HARD
- // TODO clear the delay_jobs queue?
-
// HARD reset is the default for a reg-model
- // FIXME SOFT reset is not fully defined for our reg-model yet
// FIXME move this to env?
p_soc_ifc_rm.reset(kind);
+ // Kill any delay_jobs that have been initiated but not completed yet
+ if (kind inside {"HARD","NONCORE"}) begin: KILL_DLY_JOBS_HARD_NONCORE
+ if (running_dly_jobs.size() > 0)
+ `uvm_info("PRED_RESET", $sformatf("Terminating %0d active delayed jobs.", running_dly_jobs.size()), UVM_HIGH)
+ while (running_dly_jobs.size() > 0) begin
+ process job_to_kill = running_dly_jobs.pop_front();
+ if (job_to_kill.status() inside {process::KILLED,process::SUSPENDED,process::FINISHED}) begin
+ `uvm_fatal("PRED_RESET", $sformatf("Found delay job in the running jobs queue with unexpected status %s", job_to_kill.status().name()))
+ end
+ else begin
+ job_to_kill.kill();
+ end
+ end
+ job_end_count.delete();
+ end
- if (kind inside {"HARD","NONCORE"}) begin: RESET_REG_BUSY_NONCORE_HARD
+ if (kind inside {"HARD","NONCORE"}) begin: RESET_REG_BUSY_HARD_NONCORE
// If any reg access was in progress when reset occurred, clear the busy
// flag (since the APB/AHB sequencers and any mailbox sequences were killed).
// We don't run this for warm/soft resets because cptra_rst_b doesn't immediately
@@ -3365,11 +3489,13 @@ function void soc_ifc_predictor::predict_reset(input string kind = "HARD");
all_regs[ii].Xset_busyX(0);
end
end
- end: RESET_REG_BUSY_NONCORE_HARD
+ end: RESET_REG_BUSY_HARD_NONCORE
- // TODO skip key reset for SOFT reset type?
- soc_ifc_status_txn_key = 0;
- cptra_status_txn_key = 0;
+ // Key keeps on rolling after a SOFT reset because activity continues until NONCORE reset asserts
+ if (kind inside {"HARD","NONCORE"}) begin: RESET_TXN_KEY_HARD_NONCORE
+ soc_ifc_status_txn_key = 0;
+ cptra_status_txn_key = 0;
+ end: RESET_TXN_KEY_HARD_NONCORE
endfunction
function bit [`CLP_OBF_FE_DWORDS-1:0] [31:0] soc_ifc_predictor::get_expected_obf_field_entropy();
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_scoreboard.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_scoreboard.svh
index ce8e4b7b2..ca05dce58 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_scoreboard.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_scoreboard.svh
@@ -165,6 +165,7 @@ class soc_ifc_scoreboard #(
uvm_event reset_handled;
reset_flag hard_reset_flag;
reset_flag soft_reset_flag;
+ reset_flag noncore_reset_flag;
extern function void handle_reset(string kind = "HARD");
extern function void disable_wait_for_scoreboard_empty();
@@ -196,6 +197,7 @@ class soc_ifc_scoreboard #(
reset_handled = new("reset_handled");
hard_reset_flag = new("hard_reset_flag"); // Used as trigger data for reset events. In UVM 1.2, data changes from a uvm_object to a string
soft_reset_flag = new("soft_reset_flag"); // Used as trigger data for reset events. In UVM 1.2, data changes from a uvm_object to a string
+ noncore_reset_flag = new("noncore_reset_flag"); // Used as trigger data for reset events. In UVM 1.2, data changes from a uvm_object to a string
// pragma uvmf custom build_phase end
endfunction
@@ -570,30 +572,39 @@ endclass
// Used to facilitate reset handling for different kinds of reset
// that may occur in soc_ifc environment.
// "SOFT" reset (aka cptra_rst_b=0)
- // * Causes flush of all expected and actual transactions
+ // * Causes flush of all expected and actual transactions after a delay
+ // representing the eventual assertion of noncore reset
// * Initiates an event trigger to indicate reset was called
// "HARD" reset (aka cptra_pwrgood=0)
// * Causes flush of all expected and actual transactions
// * Initiates an event trigger to indicate reset was called
+ // This function is called in the soc_ifc_environment prior to handle_reset
+ // in the soc_ifc_predictor.
function void soc_ifc_scoreboard::handle_reset(string kind = "HARD");
reset_flag kind_handled;
- kind_handled = kind == "HARD" ? hard_reset_flag :
- kind == "SOFT" ? soft_reset_flag :
- null;
-
- // Flush transactions
- soc_ifc_expected_hash.delete();
- cptra_expected_hash .delete();
- ahb_expected_q.delete();
- apb_expected_q.delete();
-
- // Clear toggle counter
- soc_ifc_status_monitor_struct = '{default:0};
- soc_ifc_status_monitor_struct_prev = '{default:0};
- soc_ifc_status_monitor_toggle_count = '{default:2'b00};
-
- // Event trigger
- reset_handled.trigger(kind_handled);
+ kind_handled = kind == "HARD" ? hard_reset_flag :
+ kind == "SOFT" ? soft_reset_flag :
+ kind == "NONCORE" ? noncore_reset_flag :
+ null;
+
+ if (kind inside {"HARD","NONCORE"}) begin
+ `uvm_info("SCBD_HANDLE_RESET", {"On call to handle_reset of kind [", kind , "] executing scoreboard reset"}, UVM_HIGH)
+
+ // Flush transactions
+ soc_ifc_expected_hash.delete();
+ cptra_expected_hash .delete();
+ ahb_expected_q.delete();
+ apb_expected_q.delete();
+
+ // Clear toggle counter
+ soc_ifc_status_monitor_struct = '{default:0};
+ soc_ifc_status_monitor_struct_prev = '{default:0};
+ soc_ifc_status_monitor_toggle_count = '{default:2'b00};
+
+ // Event trigger
+ reset_handled.trigger(kind_handled);
+ `uvm_info("SCBD_HANDLE_RESET", "On call to handle_reset, triggered the event indicating an expected status transaction for internal resets", UVM_HIGH)
+ end
endfunction
// FUNCTION: disable_wait_for_scoreboard_empty
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_monitor.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_monitor.svh
index ce2b62266..50d6612ba 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_monitor.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_monitor.svh
@@ -103,7 +103,8 @@ endclass
// pragma uvmf custom external begin
task cptra_status_monitor::handle_reset(string kind = "HARD");
- txn_key = 0;
+ if (kind inside {"HARD", "NONCORE"})
+ txn_key = 0;
endtask
// pragma uvmf custom external end
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/soc_ifc_ctrl_pkg.sv b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/soc_ifc_ctrl_pkg.sv
index 992625f5a..32a87187f 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/soc_ifc_ctrl_pkg.sv
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/soc_ifc_ctrl_pkg.sv
@@ -88,6 +88,8 @@ package soc_ifc_ctrl_pkg;
`include "src/soc_ifc_ctrl_rom_poweron_sequence.svh"
`include "src/soc_ifc_ctrl_reset_warm_sequence.svh"
`include "src/soc_ifc_ctrl_reset_cold_sequence.svh"
+ `include "src/soc_ifc_ctrl_wdt_cascade_sequence.svh"
+ `include "src/soc_ifc_ctrl_wdt_independent_sequence.svh"
// pragma uvmf custom package_item_additional end
endpackage
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_wdt_cascade_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_wdt_cascade_sequence.svh
new file mode 100644
index 000000000..bd100d1dd
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_wdt_cascade_sequence.svh
@@ -0,0 +1,70 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION:
+// This sequences randomizes the soc_ifc_ctrl transaction and sends it
+// to the UVM driver.
+//
+// This sequence constructs and randomizes a soc_ifc_ctrl_transaction.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_ctrl_wdt_cascade_sequence
+ extends soc_ifc_ctrl_sequence_base ;
+
+ `uvm_object_utils( soc_ifc_ctrl_wdt_cascade_sequence )
+
+ // pragma uvmf custom class_item_additional begin
+ // pragma uvmf custom class_item_additional end
+
+ //*****************************************************************
+ function new(string name = "");
+ super.new(name);
+ endfunction: new
+
+ // ****************************************************************************
+ // TASK : body()
+ // This task is automatically executed when this sequence is started using the
+ // start(sequencerHandle) task.
+ //
+ task body();
+
+ // Construct the transaction
+ req=soc_ifc_ctrl_transaction::type_id::create("req");
+ start_item(req);
+ // Randomize the transaction
+ if(!req.randomize()) `uvm_fatal("SEQ", "soc_ifc_ctrl_wdt_cascade_sequence::body()-soc_ifc_ctrl_transaction randomization failed")
+ req.generic_input_val = 64'hABAB;
+ req.set_pwrgood = 'b1;
+ req.assert_rst = 'b0;
+ // Send the transaction to the soc_ifc_ctrl_driver_bfm via the sequencer and soc_ifc_ctrl_driver.
+ finish_item(req);
+ `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM)
+
+ endtask
+
+endclass: soc_ifc_ctrl_wdt_cascade_sequence
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_wdt_independent_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_wdt_independent_sequence.svh
new file mode 100644
index 000000000..ff420478f
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_wdt_independent_sequence.svh
@@ -0,0 +1,84 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION:
+// This sequences randomizes the soc_ifc_ctrl transaction and sends it
+// to the UVM driver.
+//
+// This sequence constructs and randomizes a soc_ifc_ctrl_transaction.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_ctrl_wdt_independent_sequence
+ extends soc_ifc_ctrl_sequence_base ;
+
+ `uvm_object_utils( soc_ifc_ctrl_wdt_independent_sequence )
+
+ // pragma uvmf custom class_item_additional begin
+ // pragma uvmf custom class_item_additional end
+
+ //*****************************************************************
+ function new(string name = "");
+ super.new(name);
+ endfunction: new
+
+ // ****************************************************************************
+ // TASK : body()
+ // This task is automatically executed when this sequence is started using the
+ // start(sequencerHandle) task.
+ //
+ task body();
+
+ // Construct the transaction
+ req=soc_ifc_ctrl_transaction::type_id::create("req");
+ start_item(req);
+ // Randomize the transaction
+ if(!req.randomize()) `uvm_fatal("SEQ", "soc_ifc_ctrl_wdt_independent_sequence::body()-soc_ifc_ctrl_transaction randomization failed")
+ // req.wait_cycles = 'd1000;
+ req.generic_input_val = 64'h1234_5678_90AB_CDEF;
+ req.set_pwrgood = 'b1;
+ req.assert_rst = 'b0;
+ // Send the transaction to the soc_ifc_ctrl_driver_bfm via the sequencer and soc_ifc_ctrl_driver.
+ finish_item(req);
+ `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM)
+
+ // Construct the transaction
+ req=soc_ifc_ctrl_transaction::type_id::create("req");
+ start_item(req);
+ // Randomize the transaction
+ if(!req.randomize()) `uvm_fatal("SEQ", "soc_ifc_ctrl_wdt_independent_sequence::body()-soc_ifc_ctrl_transaction randomization failed")
+ // req.wait_cycles = 'd1000;
+ req.generic_input_val = 64'hEFEF;
+ req.set_pwrgood = 'b1;
+ req.assert_rst = 'b0;
+ // Send the transaction to the soc_ifc_ctrl_driver_bfm via the sequencer and soc_ifc_ctrl_driver.
+ finish_item(req);
+ `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM)
+
+ endtask
+
+endclass: soc_ifc_ctrl_wdt_independent_sequence
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src/soc_ifc_status_monitor.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src/soc_ifc_status_monitor.svh
index 07a530944..ef48ed8cf 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src/soc_ifc_status_monitor.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src/soc_ifc_status_monitor.svh
@@ -111,7 +111,7 @@ function void soc_ifc_status_monitor::force_advance_txn_key(int unsigned incr);
endfunction
task soc_ifc_status_monitor::handle_reset(string kind = "HARD");
- txn_key = 0;
+ if (kind inside {"HARD","NONCORE"})
+ txn_key = 0;
endtask
// pragma uvmf custom external end
-
diff --git a/tools/scripts/Makefile b/tools/scripts/Makefile
index ce14a41c9..6a7efb724 100755
--- a/tools/scripts/Makefile
+++ b/tools/scripts/Makefile
@@ -14,7 +14,8 @@
#
PLAYBOOK_RANDOM_SEED ?= $(shell date +%s)
-TEST_CFLAGS = -g -O3 -DMY_RANDOM_SEED=$(PLAYBOOK_RANDOM_SEED)
+BUILD_CFLAGS ?=
+TEST_CFLAGS = -g -O3 -DMY_RANDOM_SEED=$(PLAYBOOK_RANDOM_SEED) $(BUILD_CFLAGS)
ABI = -mabi=ilp32 -march=rv32imc
@@ -186,6 +187,9 @@ ifdef FORCE_CPU_RESET
VERILATOR_TB_DEFS += +define+CALIPTRA_FORCE_CPU_RESET
endif
+# Run time arguments from command line
+VERILATOR_RUN_ARGS ?= ""
+
# Add testbench lib include paths
CFLAGS += $(addprefix -I$(CALIPTRA_ROOT)/src/integration/test_suites/libs/,$(dir $(VERILATOR_TB_LIBS)))
@@ -198,6 +202,9 @@ clean:
dataset.asdb library.cfg vsimsa.cfg riviera-build wave.asdb sim.vcd \
*.h
+clean_fw:
+ rm -rf *.o *.h
+
############ Model Builds ###############################
verilator-build: $(TBFILES) $(INCLUDES_DIR)/defines.h $(VERILATOR_TB_SRCS)
@@ -224,7 +231,7 @@ vcs-build: $(TBFILES) $(INCLUDES_DIR)/defines.h
############ TEST Simulation ###############################
verilator: program.hex verilator-build
- ./obj_dir/Vcaliptra_top_tb
+ ./obj_dir/Vcaliptra_top_tb $(VERILATOR_RUN_ARGS)
vcs: program.hex vcs-build
./simv.caliptra_top_tb
@@ -303,5 +310,5 @@ help:
@echo Make sure the environment variable RV_ROOT is set.
@echo Possible targets: verilator vcs irun vlog riviera help clean all verilator-build irun-build vcs-build riviera-build program.hex
-.PHONY: help clean verilator vcs irun vlog riviera
+.PHONY: help clean clean_fw verilator vcs irun vlog riviera
diff --git a/tools/scripts/promote_file_list_check.sh b/tools/scripts/promote_file_list_check.sh
deleted file mode 100644
index 9b5ecc1f9..000000000
--- a/tools/scripts/promote_file_list_check.sh
+++ /dev/null
@@ -1,44 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-#
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-
-if [[ $# -ne 1 ]]; then
- echo "Error, requires branch name argument"
- exit 1
-else
- merge_dest=$1
-fi
-
-cd $AHA_POC_REPO
-
-yml_mod_count=$(git diff --merge-base ${merge_dest} --name-status | grep -c 'compile.yml$\|compilespecs.yml$\|gen_pb_file_lists.sh$')
-if [[ ${yml_mod_count} -gt 0 ]]; then
- # Run the Filelist generator script
- bash $AHA_POC_REPO/tools/scripts/gen_pb_file_lists.sh
-
- # Check for any file changes
- if [[ $(git status -s --untracked-files=all --ignored=traditional | grep "\.vf" -c) -gt 0 ]]; then
- echo "Regenerating VF file lists produced some file changes:";
- git status -s --untracked-files=all --ignored=traditional | grep "\.vf";
- git diff;
- echo "*****************************************";
- echo "Review above changes locally and resubmit pipeline";
- echo "(Hint: Check $AHA_POC_REPO for the above changes)";
- echo "*****************************************";
- exit 1;
- fi
-else
- echo "skipping file_list check since no compile.yml were modified"
-fi
diff --git a/tools/scripts/promote_rdl_check.sh b/tools/scripts/promote_rdl_check.sh
deleted file mode 100644
index 881eb5958..000000000
--- a/tools/scripts/promote_rdl_check.sh
+++ /dev/null
@@ -1,48 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-#
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-
-if [[ $# -ne 1 ]]; then
- echo "Error, requires branch name argument"
- exit 1
-else
- merge_dest=$1
-fi
-
-cd $AHA_POC_REPO
-
-rdl_mod_count=$(git diff --merge-base ${merge_dest} --name-status | grep -c '\.rdl$\|tools\/templates\/rdl\|reg_gen.sh\|reg_gen.py\|reg_doc_gen.sh\|reg_doc_gen.py')
-if [[ ${rdl_mod_count} -gt 0 ]]; then
- # Run the HTML Doc generator script (to update the REG macro header files)
- # and the individual reg generator script but then remove the docs directories
- bash $AHA_POC_REPO/tools/scripts/reg_gen.sh
- bash $AHA_POC_REPO/tools/scripts/reg_doc_gen.sh
- rm -rf $AHA_POC_REPO/src/integration/docs
- rm -rf $AHA_POC_REPO/src/soc_ifc/docs
-
- # Check for any file changes
- if [[ $(git status -s --untracked-files=all --ignored=traditional -- $AHA_POC_REPO/src/ | wc -l) -gt 0 ]]; then
- echo "Regenerating reg RDL outputs produced some file changes:";
- git status -s --untracked-files=all --ignored=traditional;
- git diff;
- echo "*****************************************";
- echo "Review above changes locally and resubmit pipeline";
- echo "(Hint: Check $AHA_POC_REPO for the above changes)";
- echo "*****************************************";
- exit 1;
- fi
-else
- echo "skipping RDL check since no RDL files were modified"
-fi
diff --git a/tools/scripts/run_verilator_l0_regression.py b/tools/scripts/run_verilator_l0_regression.py
index a11afc338..a4cbbd2ee 100644
--- a/tools/scripts/run_verilator_l0_regression.py
+++ b/tools/scripts/run_verilator_l0_regression.py
@@ -155,7 +155,7 @@ def runTest(args):
# Invoke makefile for the current test
mfile = os.path.join(os.environ.get('CALIPTRA_ROOT'),"tools/scripts/Makefile")
testname = "TESTNAME=" + test
- cmd = " ".join(["make", "-C", testdir, "-f", mfile, testname, "verilator"])
+ cmd = " ".join(["make", "-C", testdir, "-f", mfile, testname, "verilator", "VERILATOR_RUN_ARGS=+CLP_REGRESSION"])
exitcode, resultout, resulterr = runBashScript(cmd)
# Parse and log the results