diff --git a/.github/scripts/build_tests_matrix.py b/.github/scripts/build_tests_matrix.py
index a3bb3329e..69d18560e 100644
--- a/.github/scripts/build_tests_matrix.py
+++ b/.github/scripts/build_tests_matrix.py
@@ -1,4 +1,5 @@
 #!/usr/bin/env python3
+import os
 import yaml
 
 def main():
@@ -8,6 +9,10 @@ def main():
     with open(file_name, "r") as fp:
         yaml_root = yaml.safe_load(fp)
 
+    # Get excluded test list
+    excluded = os.environ.get("EXCLUDE_TESTS", "")
+    excluded = [s.strip() for s in excluded.strip().split(",")]
+
     # Get test list
     content = yaml_root["contents"][0]
     tests = content["tests"]
@@ -20,7 +25,9 @@ def main():
 
         for i, part in enumerate(parts):
             if part == "test_suites" and i + 1 < len(parts):
-                test_list.append(parts[i+1])
+                test_name = parts[i+1]
+                if test_name not in excluded:
+                    test_list.append(test_name)
                 break
 
     # Output names
diff --git a/.github/scripts/gdb_test.sh b/.github/scripts/gdb_test.sh
new file mode 100755
index 000000000..90eb5ac6b
--- /dev/null
+++ b/.github/scripts/gdb_test.sh
@@ -0,0 +1,87 @@
+#!/bin/bash
+#
+# This script runs Verilator RTL simulation and OpenOCD in background, invokes
+# the supplied test command and shuts everything down.
+
+SIM_LOG=`realpath sim.log`
+OPENOCD_LOG=`realpath openocd.log`
+
+set +e
+
+if [ "$#" -lt 1 ]; then
+    echo "Usage: gdb_test.sh <command> [args ...]"
+    exit 1
+fi
+
+# Utils
+source `dirname ${BASH_SOURCE[0]}`/utils.sh
+
+terminate_all () {
+    terminate ${OPENOCD_PID}
+    terminate ${SIM_PID}
+}
+
+print_logs () {
+    echo -e "${COLOR_WHITE}======== Simulation log ========${COLOR_OFF}"
+    cat ${SIM_LOG} || true
+    echo -e "${COLOR_WHITE}======== OpenOCD log ========${COLOR_OFF}"
+    cat ${OPENOCD_LOG} || true
+}
+
+echo -e "${COLOR_WHITE}======== Launching interactive simulation ========${COLOR_OFF}"
+
+# Start the simulation
+echo -e "Starting simulation..."
+obj_dir/Vcaliptra_top_tb >"${SIM_LOG}" 2>&1 &
+SIM_PID=$!
+
+# Wait
+wait_for_phrase "${SIM_LOG}" "CLP: ROM Flow in progress..."
+if [ $? -ne 0 ]; then
+    echo -e "${COLOR_RED}Failed to start the simulation!${COLOR_OFF}"
+    print_logs
+    terminate_all; exit -1
+fi
+echo -e "Simulation running and ready (pid=${SIM_PID})"
+
+# Launch OpenOCD
+echo -e "Launching OpenOCD..."
+cd ${CALIPTRA_ROOT}/tools/scripts/openocd && openocd -d2 -f board/caliptra-verilator.cfg >"${OPENOCD_LOG}" 2>&1 &
+OPENOCD_PID=$!
+
+# Wait
+wait_for_phrase "${OPENOCD_LOG}" "Listening on port 3333 for gdb connections"
+if [ $? -ne 0 ]; then
+    echo -e "${COLOR_RED}Failed to start OpenOCD!${COLOR_OFF}"
+    print_logs
+    terminate_all; exit -1
+fi
+echo -e "OpenOCD running and ready (pid=${OPENOCD_PID})"
+
+# Wait a bit
+sleep 1s
+
+# Run the test
+echo -e "${COLOR_WHITE}======== Running test '$@' ========${COLOR_OFF}"
+
+bash -c "$(printf ' %q' "$@")"
+EXITCODE=$?
+
+if [ ${EXITCODE} -eq 0 ]; then
+    echo -e "${COLOR_GREEN}[PASSED]${COLOR_OFF}"
+else
+    echo -e "${COLOR_RED}[FAILED]${COLOR_OFF}"
+fi
+
+sleep 1s
+
+# Terminate
+echo -e "${COLOR_WHITE}Terminating...${COLOR_OFF}"
+terminate_all
+
+# Display logs
+print_logs
+
+# Honor the exitcode
+exit ${EXITCODE}
+
diff --git a/.github/scripts/openocd_test.sh b/.github/scripts/openocd_test.sh
new file mode 100755
index 000000000..75a96ba6a
--- /dev/null
+++ b/.github/scripts/openocd_test.sh
@@ -0,0 +1,68 @@
+#!/bin/bash
+#
+# This script runs Verilator RTL simulation in background and invokes OpenOCD
+# to perform JTAG access test
+
+SIM_LOG=`realpath sim.log`
+OPENOCD_LOG=`realpath openocd.log`
+
+set +e
+
+if [ "$#" -lt 1 ]; then
+    echo "Usage: openocd_test.sh [openocd args ...]"
+    exit 1
+fi
+OPENOCD_ARGS=$@
+
+# Utils
+source `dirname ${BASH_SOURCE[0]}`/utils.sh
+
+print_logs () {
+    echo -e "${COLOR_WHITE}======== Simulation log ========${COLOR_OFF}"
+    cat ${SIM_LOG} || true
+    echo -e "${COLOR_WHITE}======== OpenOCD log ========${COLOR_OFF}"
+    cat ${OPENOCD_LOG} || true
+}
+
+echo -e "${COLOR_WHITE}======== Launching interactive simulation ========${COLOR_OFF}"
+
+# Start the simulation
+echo -e "Starting simulation..."
+obj_dir/Vcaliptra_top_tb >"${SIM_LOG}" 2>&1 &
+SIM_PID=$!
+
+# Wait
+wait_for_phrase "${SIM_LOG}" "CLP: ROM Flow in progress..."
+if [ $? -ne 0 ]; then
+    echo -e "${COLOR_RED}Failed to start the simulation!${COLOR_OFF}"
+    print_logs
+    terminate ${SIM_PID}; exit -1
+fi
+echo -e "Simulation running and ready (pid=${SIM_PID})"
+
+# Wait a bit
+sleep 5s
+
+# Run the test
+echo -e "${COLOR_WHITE}======== Running OpenOCD test '$@' ========${COLOR_OFF}"
+cd ${CALIPTRA_ROOT}/tools/scripts/openocd && openocd -d2 ${OPENOCD_ARGS} >"${OPENOCD_LOG}" 2>&1
+EXITCODE=$?
+
+if [ ${EXITCODE} -eq 0 ]; then
+    echo -e "${COLOR_GREEN}[PASSED]${COLOR_OFF}"
+else
+    echo -e "${COLOR_RED}[FAILED]${COLOR_OFF}"
+fi
+
+sleep 1s
+
+# Terminate
+echo -e "${COLOR_WHITE}Terminating...${COLOR_OFF}"
+terminate ${SIM_PID}
+
+# Display logs
+print_logs
+
+# Honor the exitcode
+exit ${EXITCODE}
+
diff --git a/.github/scripts/utils.sh b/.github/scripts/utils.sh
new file mode 100644
index 000000000..e5496afd9
--- /dev/null
+++ b/.github/scripts/utils.sh
@@ -0,0 +1,49 @@
+#!/bin/bash
+
+# Colors
+COLOR_OFF='\033[0m'
+COLOR_RED='\033[31m'
+COLOR_GREEN='\033[32m'
+COLOR_WHITE='\033[1;37m'
+
+# Waits until the given phrase appears in a log file (actively written to)
+# Usage: wait_for_phrase <log_file> <phrase>
+wait_for_phrase () {
+
+    # Check if the log exists
+    sleep 1s
+    if ! [ -f "$1" ]; then
+        echo -e "${COLOR_RED}Log file '$1' not found!${COLOR_OFF}"
+        return -1
+    fi
+
+    # Wait for the phrase
+    DEADLINE=$((${EPOCHSECONDS} + 30))
+    while [ ${EPOCHSECONDS} -lt ${DEADLINE} ]
+    do
+        # Check for the phrase
+        grep "$2" "$1" >/dev/null
+        if [ $? -eq 0 ]; then
+            return 0
+        fi
+
+        # Sleep and retry
+        sleep 1s
+    done
+
+    # Timeout
+    return -1
+}
+
+# Terminates a process. First via SIGINT and if this doesn't work after 10s
+# retries with SIGKILL
+# Usage: terminate <pid>
+terminate () {
+
+    local PID=$1
+
+    # Gently interrupt, wait some time and then kill
+    /bin/kill -s SIGINT  ${PID} || true
+    sleep 10s
+    /bin/kill -s SIGKILL ${PID} || true
+}
diff --git a/.github/workflows/build-test-verilator.yml b/.github/workflows/build-test-verilator.yml
index e39295552..53d8b407c 100644
--- a/.github/workflows/build-test-verilator.yml
+++ b/.github/workflows/build-test-verilator.yml
@@ -13,8 +13,7 @@ env:
   CARGO_INCREMENTAL: 0
   SCCACHE_VERSION: 0.3.3
   RISCV_VERSION: v12.1.0
-  # TODO: To update to 5.006, clean up lint errors
-  VERILATOR_VERSION: v5.002
+  VERILATOR_VERSION: v5.012
   PKG_CONFIG_PATH: /opt/verilator/share/pkgconfig
   SCCACHE_GHA_CACHE_TO: sccache-verilator-10000
   SCCACHE_GHA_CACHE_FROM: sccache-verilator-
@@ -22,32 +21,10 @@ env:
   SCCACHE_C_CUSTOM_CACHE_BUSTER: f3e6951f0c1d
 
 jobs:
-  build_matrix:
-    name: Build Smoke Test matrix
+  build_tools:
+    name: Build Tools
     runs-on: ubuntu-22.04
-    outputs:
-      test_names: ${{ steps.output-matrix.outputs.test_names  }}
-    steps:
-      - uses: actions/checkout@v3
-      - name: Install deps
-        run: |
-          sudo apt-get update -qy && sudo apt-get install -qy --no-install-recommends \
-            python3-minimal python3-yaml
-      - name: Build matrix
-        id: output-matrix
-        run: |
-          echo "test_names=$(python3 .github/scripts/build_tests_matrix.py)" >> $GITHUB_OUTPUT
-
-  build_and_test:
-    name: Verilator Smoke Test
-    runs-on: ubuntu-22.04
-    needs: build_matrix
-
-    strategy:
-      fail-fast: false
-      matrix:
-        test_name: ${{fromJSON(needs.build_matrix.outputs.test_names)}}
-
+    
     steps:
       - uses: actions/checkout@v3
         with:
@@ -145,6 +122,8 @@ jobs:
     needs: build_tools
     outputs:
       test_names: ${{ steps.output-matrix.outputs.test_names  }}
+    env:
+      EXCLUDE_TESTS: "smoke_test_clk_gating, smoke_test_cg_wdt, smoke_test_mbox_cg, smoke_test_kv_cg, smoke_test_doe_cg"
     steps:
       - uses: actions/checkout@v3
       - name: Install deps
@@ -157,7 +136,7 @@ jobs:
           echo "test_names=$(python3 .github/scripts/build_tests_matrix.py)" >> $GITHUB_OUTPUT
 
   build_and_test:
-    name: Verilator Smoke Test
+    name: Verilator
     runs-on: ubuntu-22.04
     needs: build_matrix
 
@@ -211,7 +190,6 @@ jobs:
         run: |
           CALIPTRA_ROOT=$(pwd)
           cd tools/scripts
-
           make verilator CALIPTRA_ROOT=$CALIPTRA_ROOT TESTNAME=${{ matrix.test_name  }} | tee output.log
           # Search the last 30 lines of the output for "TESTCASE PASSED"
           tail -n 30 output.log | grep "TESTCASE PASSED"
diff --git a/.github/workflows/interactive-debugging.yml b/.github/workflows/interactive-debugging.yml
new file mode 100644
index 000000000..570323a50
--- /dev/null
+++ b/.github/workflows/interactive-debugging.yml
@@ -0,0 +1,317 @@
+# docs: https://docs.github.com/en/actions/using-workflows/workflow-syntax-for-github-actions
+
+name: Interactive debugging
+
+on:
+  push:
+    branches: ["main", "dev-goog", "dev-msft", "dev-public"]
+  pull_request:
+
+  workflow_dispatch:
+
+jobs:
+  build_verilator:
+    name: 
+    runs-on: ubuntu-22.04
+
+    env:
+      CARGO_INCREMENTAL: 0
+      SCCACHE_VERSION: 0.3.3
+      # TODO: To update to 5.006, clean up lint errors
+      VERILATOR_VERSION: v5.012
+      SCCACHE_GHA_CACHE_TO: sccache-verilator-10000
+      SCCACHE_GHA_CACHE_FROM: sccache-verilator-
+      # Change this to a new random value if you suspect the cache is corrupted
+      SCCACHE_C_CUSTOM_CACHE_BUSTER: f3e6951f0c1d
+
+    steps:
+      - name: Restore sccache binary
+        uses: actions/cache/restore@v3
+        id: sccache_bin_restore
+        with:
+          path: ~/.cargo/bin/sccache
+          key: sccache-bin-${{ env.SCCACHE_VERSION }}-${{ env.SCCACHE_C_CUSTOM_CACHE_BUSTER }}
+
+      - name: Install sccache
+        if: steps.sccache_bin_restore.outputs.cache-hit != 'true'
+        run: |
+          cargo install sccache --version ${SCCACHE_VERSION} --no-default-features --features=gha
+
+      - name: Save sccache binary
+        uses: actions/cache/save@v3
+        if: steps.sccache_bin_restore.outputs.cache-hit != 'true'
+        with:
+          path: ~/.cargo/bin/sccache
+          key: sccache-bin-${{ env.SCCACHE_VERSION }}-${{ env.SCCACHE_C_CUSTOM_CACHE_BUSTER }}
+
+      - name: Configure sccache
+        uses: actions/github-script@v6
+        with:
+          script: |
+            core.exportVariable('ACTIONS_CACHE_URL', process.env.ACTIONS_CACHE_URL || '');
+            core.exportVariable('ACTIONS_RUNTIME_TOKEN', process.env.ACTIONS_RUNTIME_TOKEN || '');
+
+      - name: Restore verilator dir
+        uses: actions/cache/restore@v3
+        id: verilator_restore
+        with:
+          path: /opt/verilator
+          key: verilator-${{ env.VERILATOR_VERSION }}-${{ env.SCCACHE_C_CUSTOM_CACHE_BUSTER }}
+
+      - name: Install verilator
+        if: steps.verilator_restore.outputs.cache-hit != 'true'
+        run: |
+          sudo apt-get install flex bison libfl2 libfl-dev help2man
+          cd /tmp/
+          git clone -b "${VERILATOR_VERSION}" https://github.com/verilator/verilator
+          cd verilator
+          autoconf
+          ./configure --prefix=/opt/verilator CC="sccache gcc" CXX="sccache g++"
+          make -j6
+          sudo make install
+
+      - name: Save verilator dir
+        uses: actions/cache/save@v3
+        if: steps.verilator_restore.outputs.cache-hit != 'true'
+        with:
+          path: /opt/verilator
+          key: verilator-${{ env.VERILATOR_VERSION }}-${{ env.SCCACHE_C_CUSTOM_CACHE_BUSTER }}
+
+      - name: Pack Verilator
+        run: |
+          cd /opt && tar -czvf verilator.tar.gz verilator/
+
+      - name: Store Verilator binaries
+        uses: actions/upload-artifact@v3
+        with:
+          name: verilator
+          path: /opt/*.tar.gz
+          retention-days: 1
+
+  build_openocd:
+    name: 
+    runs-on: ubuntu-22.04
+
+    env:
+      CARGO_INCREMENTAL: 0
+      SCCACHE_VERSION: 0.3.3
+      # A custom fork is needed to allow bypassing core examination and accessing
+      # peripherals regardless of core state.
+      OPENOCD_REPO: https://github.com/antmicro/openocd
+      OPENOCD_VERSION: riscv-nohalt
+      SCCACHE_GHA_CACHE_TO: sccache-openocd-10000
+      SCCACHE_GHA_CACHE_FROM: sccache-openocd-
+      # Change this to a new random value if you suspect the cache is corrupted
+      SCCACHE_C_CUSTOM_CACHE_BUSTER: f3e6951f0c1e
+
+    steps:
+      - name: Restore sccache binary
+        uses: actions/cache/restore@v3
+        id: sccache_bin_restore
+        with:
+          path: ~/.cargo/bin/sccache
+          key: sccache-bin-${{ env.SCCACHE_VERSION }}-${{ env.SCCACHE_C_CUSTOM_CACHE_BUSTER }}
+
+      - name: Install sccache
+        if: steps.sccache_bin_restore.outputs.cache-hit != 'true'
+        run: |
+          cargo install sccache --version ${SCCACHE_VERSION} --no-default-features --features=gha
+
+      - name: Save sccache binary
+        uses: actions/cache/save@v3
+        if: steps.sccache_bin_restore.outputs.cache-hit != 'true'
+        with:
+          path: ~/.cargo/bin/sccache
+          key: sccache-bin-${{ env.SCCACHE_VERSION }}-${{ env.SCCACHE_C_CUSTOM_CACHE_BUSTER }}
+
+      - name: Configure sccache
+        uses: actions/github-script@v6
+        with:
+          script: |
+            core.exportVariable('ACTIONS_CACHE_URL', process.env.ACTIONS_CACHE_URL || '');
+            core.exportVariable('ACTIONS_RUNTIME_TOKEN', process.env.ACTIONS_RUNTIME_TOKEN || '');
+
+      - name: Restore OpenOCD dir
+        uses: actions/cache/restore@v3
+        id: openocd_restore
+        with:
+          path: /opt/openocd
+          key: openocd-${{ env.OPENOCD_VERSION }}-${{ env.SCCACHE_C_CUSTOM_CACHE_BUSTER }}
+
+      - name: Install OpenOCD
+        if: steps.openocd_restore.outputs.cache-hit != 'true'
+        run: |
+          sudo apt-get install make libtool pkg-config autoconf automake texinfo
+          cd /tmp/
+          git clone -b "${OPENOCD_VERSION}" https://github.com/antmicro/openocd
+          cd openocd
+          ./bootstrap
+          ./configure --prefix=/opt/openocd --enable-remote-bitbang \
+            CC="sccache gcc" CXX="sccache g++" \
+            CFLAGS="-Wno-error=misleading-indentation -Wno-error=stringop-overflow"
+          make -j6
+          sudo make install
+
+      - name: Save OpenOCD dir
+        uses: actions/cache/save@v3
+        if: steps.openocd_restore.outputs.cache-hit != 'true'
+        with:
+          path: /opt/openocd
+          key: openocd-${{ env.OPENOCD_VERSION }}-${{ env.SCCACHE_C_CUSTOM_CACHE_BUSTER }}
+
+      - name: Pack OpenOCD
+        run: |
+          cd /opt && tar -czvf openocd.tar.gz openocd/
+
+      - name: Store OpenOCD binaries
+        uses: actions/upload-artifact@v3
+        with:
+          name: openocd
+          path: /opt/*.tar.gz
+          retention-days: 1
+
+  gdb_tests:
+    name: Run GDB debugging tests
+    runs-on: ubuntu-22.04
+    needs: [build_verilator, build_openocd]
+
+    env:
+      CARGO_INCREMENTAL: 0
+      PKG_CONFIG_PATH: /opt/verilator/share/pkgconfig
+      DEBIAN_FRONTEND: "noninteractive"
+
+    steps:
+
+      - name: Install Risc V Toolchain
+        run: |
+          # Building from source takes around 6.65 GB of disk and download size
+          wget -O toolchain.tar.gz https://github.com/stnolting/riscv-gcc-prebuilt/releases/download/rv64imc-3.0.0/riscv64-unknown-elf.gcc-12.1.0.tar.gz
+          mkdir /opt/riscv
+          tar -xzf toolchain.tar.gz -C /opt/riscv/
+
+      - name: Install dependencies
+        run: |
+          # For some reason GDB requires libpython3.8.so
+          sudo add-apt-repository ppa:deadsnakes/ppa -y
+          sudo apt update -qy && sudo apt install -qy --no-install-recommends \
+            libpython3.8
+
+      - name: Download Verilator binaries
+        uses: actions/download-artifact@v3
+        with:
+          name: verilator
+          path: /opt
+
+      - name: Download OpenOCD binaries
+        uses: actions/download-artifact@v3
+        with:
+          name: openocd
+          path: /opt
+
+      - name: Unpack binaries
+        run: |
+          pushd /opt
+            tar -zxvf verilator.tar.gz
+            tar -zxvf openocd.tar.gz
+          popd
+
+      - name: Setup path
+        run: |
+          echo /opt/riscv/bin:/opt/verilator/bin:/opt/openocd/bin >> $GITHUB_PATH
+
+      - name: Clone repository
+        uses: actions/checkout@v3
+        with:
+          submodules: 'true'
+
+      - name: Build Verilated simulation
+        run: |
+          export CALIPTRA_ROOT=$(pwd)
+          mkdir run
+          make -C run -f ${CALIPTRA_ROOT}/tools/scripts/Makefile verilator-build TESTNAME=infinite_loop DEBUG_UNLOCKED=1 \
+            OBJCACHE="" CC=gcc CXX=g++ LINK=g++
+          make -C run -f ${CALIPTRA_ROOT}/tools/scripts/Makefile program.hex TESTNAME=infinite_loop
+
+      - name: Test core register access
+        run: |
+          export CALIPTRA_ROOT=$(pwd)
+          cd run
+          ${CALIPTRA_ROOT}/.github/scripts/gdb_test.sh \
+            /bin/bash -c 'cd ${CALIPTRA_ROOT}/src/integration/test_suites/infinite_loop && ./dump_and_compare.sh'
+
+      - name: Test memory access
+        run: |
+          export CALIPTRA_ROOT=$(pwd)
+          cd run
+          ${CALIPTRA_ROOT}/.github/scripts/gdb_test.sh \
+            /bin/bash -c 'cd ${CALIPTRA_ROOT}/src/integration/test_suites/infinite_loop && ./mem_access.sh'
+
+      - name: Test peripheral access
+        run: |
+          export CALIPTRA_ROOT=$(pwd)
+          cd run
+          ${CALIPTRA_ROOT}/.github/scripts/gdb_test.sh \
+            /bin/bash -c 'cd ${CALIPTRA_ROOT}/src/integration/test_suites/infinite_loop && ./peripheral_access.sh'
+
+  openocd_tests:
+    name: Run OpenOCD debugging tests
+    runs-on: ubuntu-22.04
+    needs: [build_verilator, build_openocd]
+
+    env:
+      CARGO_INCREMENTAL: 0
+      PKG_CONFIG_PATH: /opt/verilator/share/pkgconfig
+      DEBIAN_FRONTEND: "noninteractive"
+
+    steps:
+
+      - name: Install Risc V Toolchain
+        run: |
+          # Building from source takes around 6.65 GB of disk and download size
+          wget -O toolchain.tar.gz https://github.com/stnolting/riscv-gcc-prebuilt/releases/download/rv64imc-3.0.0/riscv64-unknown-elf.gcc-12.1.0.tar.gz
+          mkdir /opt/riscv
+          tar -xzf toolchain.tar.gz -C /opt/riscv/
+
+      - name: Download Verilator binaries
+        uses: actions/download-artifact@v3
+        with:
+          name: verilator
+          path: /opt
+
+      - name: Download OpenOCD binaries
+        uses: actions/download-artifact@v3
+        with:
+          name: openocd
+          path: /opt
+
+      - name: Unpack binaries
+        run: |
+          pushd /opt
+            tar -zxvf verilator.tar.gz
+            tar -zxvf openocd.tar.gz
+          popd
+
+      - name: Setup path
+        run: |
+          echo /opt/riscv/bin:/opt/verilator/bin:/opt/openocd/bin >> $GITHUB_PATH
+
+      - name: Clone repository
+        uses: actions/checkout@v3
+        with:
+          submodules: 'true'
+
+      - name: Build Verilated simulation
+        run: |
+          export CALIPTRA_ROOT=$(pwd)
+          mkdir run
+          make -C run -f ${CALIPTRA_ROOT}/tools/scripts/Makefile verilator-build TESTNAME=infinite_loop DEBUG_UNLOCKED=1 FORCE_CPU_RESET=1 \
+            OBJCACHE="" CC=gcc CXX=g++ LINK=g++
+          make -C run -f ${CALIPTRA_ROOT}/tools/scripts/Makefile program.hex TESTNAME=infinite_loop
+
+      - name: Test peripheral access with core in reset
+        run: |
+          export CALIPTRA_ROOT=$(pwd)
+          cd run
+          ${CALIPTRA_ROOT}/.github/scripts/openocd_test.sh \
+            -f board/caliptra-verilator-rst.cfg \
+            -f ${CALIPTRA_ROOT}/src/integration/test_suites/infinite_loop/peripheral_access.tcl
diff --git a/README.md b/README.md
index 09599077e..7070e2e35 100644
--- a/README.md
+++ b/README.md
@@ -14,7 +14,7 @@ See the License for the specific language governing permissions and<BR>
 limitations under the License.*_<BR>
 
 # **Caliptra Hands-On Guide** #
-_*Last Update: 2023/05/09*_
+_*Last Update: 2023/09/06*_
 
 
 ## **Tools Used** ##
@@ -32,7 +32,7 @@ Simulation:
  - Synopsys VCS with Verdi
    - `Version R-2020.12-SP2-7_Full64`
  - Verilator
-   - `Version 4.228`
+   - `Version 5.012`
  - Mentor Graphics QVIP
    - `Version 2021.2.1` of AHB/APB models
  - UVM installation
@@ -44,13 +44,28 @@ Synthesis:
 
 GCC:
  - RISCV Toolchain for generating memory initialization files
-   - `riscv64-unknown-elf-gcc-8.2.0-2019.02.0-x86_64-linux-centos6`
- - G++ Used to compile Verilator objects
-   - `g++ (GCC) 8.2.0`
+   - `Version 2023.04.29`
+   - `riscv64-unknown-elf-gcc (g) 12.2.0`
+ - G++ Used to compile Verilator objects and test firmware
+   - `g++ (GCC) 11.2.0`
 
 Other:
  - Playbook (Microsoft Internal workflow management tool)
 
+### **RISCV Toolchain installation** ###
+Note that there is significant configurability when installing the RISCV toolchain.
+These instructions may be used to create a RISCV installation that will be compatible
+with the provided Makefile for compiling test C programs.
+
+1. Install from this repository:
+    - https://github.com/riscv-collab/riscv-gnu-toolchain
+    - Follow the included README in that repository for installation instructions
+2. The most recently tested toolchain build that was confirmed to work was 2023-04-29
+    - https://github.com/riscv-collab/riscv-gnu-toolchain/releases/tag/2023.04.29
+3. A compatible tool installation requires newlib cross-compiler, multilib support, and the zicsr/zifencei extensions. Use this configure command:
+    - `./configure --enable-multilib --prefix=/path/to/tools/riscv-gnu/2023.04.29 --with-multilib-generator="rv32imc-ilp32--a*zicsr*zifencei"`
+4. Use `make` instead of `make linux` to install the tool (using newlib option)
+
 ## **ENVIRONMENT VARIABLES** ##
 Required for simulation:<BR>
 `CALIPTRA_WORKSPACE`: Defines the absolute path to the directory where the Verilator "scratch" output directory will be created. Recommended to define as the absolute path to the directory that contains the Project repository root (called "Caliptra" or "caliptra-rtl")<BR>
@@ -64,14 +79,16 @@ Required for Firmware (i.e. Test suites) makefile:<BR>
 Caliptra
 |-- LICENSE
 |-- README.md
-|-- Release_notes.txt
+|-- Release_Notes.md
 |-- docs
 |   |-- Caliptra_Integration_Specification.pdf
-|   |-- Caliptra_Hardware_Spec.pdf
-|   |-- Caliptra_TestPlan_L1.pdf
+|   |-- Caliptra_Hardware_Specification.pdf
+|   `-- Caliptra_TestPlan.xlsx
 |-- src
 |   |-- aes
 |   |-- ahb_lite_bus
+|   |-- caliptra_prim
+|   |-- caliptra_prim_generic
 |   |-- csrng
 |   |-- datavault
 |   |-- doe
@@ -86,19 +103,17 @@ Caliptra
 |   |-- lc_ctrl
 |   |-- libs
 |   |-- pcrvault
-|   |-- prim
-|   |-- prim_generic
 |   |-- riscv_core
 |   |-- sha256
 |   |-- sha512
 |   |-- sha512_masked
 |   |-- soc_ifc
 |   |-- spi_host
-|   |-- uart
+|   `-- uart
 `-- tools
-    |-- config
     |-- README
-    `-- scripts
+    |-- scripts
+    `-- templates
 ```
 The root of the repository is structured as shown above, to a depth of 2 layers.<BR>
 Each sub-component is accompanied by a file list summary (located in src/<component>/config/<name>.vf) that comprises all the filenames required to compile the component, and an optional testbench filelist for unit-level simulation. <BR>
@@ -119,38 +134,41 @@ The "Integration" sub-component contains the top-level fileset for Caliptra. `sr
 `run_verilator_l0_regression.py`: Wrapper to run the L0 smoke test regression suite using the Makefile flow in Verilator<BR>
 `integration_vector_gen.py`: Generates test vectors for crypto core tests<BR>
 `veer_build_command.sh`: Shell script used to generate the VeeR-EL2 repository present in `src/riscv_core/veer_el2`<BR>
+`openocd`: Open-Source FW debug utility used for JTAG testing in automated workflows
 
 ## **Simulation Flow** ##
 
 ### VCS Steps: ###
 1. Setup tools, add to PATH (ensure riscv64-unknown-elf-gcc is also available)
-1. Define all environment variables above
+2. Define all environment variables above
     - For the initial test run after downloading repository, `iccm_lock` is recommended for TESTNAME
-1. Create a run folder for build outputs (and cd to it)
-1. Invoke `${CALIPTRA_ROOT}/tools/scripts/Makefile` with target 'program.hex' to produce SRAM initialization files from the firmware found in `src/integration/test_suites/${TESTNAME}`
+3. Create a run folder for build outputs (and cd to it)
+4. [OPTIONAL] By default, this run flow will use the riscv64 toolchain to compile test firmware (according to TESTNAME) into program.hex, iccm.hex, dccm.hex, and mailbox.hex. As a first pass, integrators may alternatively use the pre-built hexfiles for convenience (available for `iccm_lock` test). To do this, copy `iccm_lock.hex` to the run directory and rename to `program.hex`. `dccm.hex` should also be copied to the run directory, as-is. Use `touch iccm.hex mailbox.hex` to create empty hex files, as these are unnecessary for `iccm_lock` test.
+5. Invoke `${CALIPTRA_ROOT}/tools/scripts/Makefile` with target 'program.hex' to produce SRAM initialization files from the firmware found in `src/integration/test_suites/${TESTNAME}`
     - E.g.: `make -f ${CALIPTRA_ROOT}/tools/scripts/Makefile program.hex`
-1. Compile complete project using `src/integration/config/caliptra_top_tb.vf` as a compilation target in VCS. When running the `vcs` command to generate simv, users should ensure that `caliptra_top_tb` is explicitly specified as the top-level component in their command to ensure this is the sole "top" that gets simulated.
-1. Simulate project with `caliptra_top_tb` as the top target
+6. Compile complete project using `src/integration/config/caliptra_top_tb.vf` as a compilation target in VCS. When running the `vcs` command to generate simv, users should ensure that `caliptra_top_tb` is explicitly specified as the top-level component in their command to ensure this is the sole "top" that gets simulated.
+7. Simulate project with `caliptra_top_tb` as the top target
 
 ### Verilator Steps: ###
 1. Setup tools, add to PATH (ensure Verilator, GCC, and riscv64-unknown-elf-gcc are available)
-1. Define all environment variables above
+2. Define all environment variables above
     - For the initial test run after downloading repository, `iccm_lock` is recommended for TESTNAME
-1. Create a run folder for build outputs
+3. Create a run folder for build outputs
     - Recommended to place run folder under `${CALIPTRA_WORKSPACE}/scratch/$USER/verilator/<date>`
-1. Run Caliptra/tools/scripts/Makefile, which provides steps to run a top-level simulation in Verilator
+4. [OPTIONAL] By default, this run flow will use the riscv64 toolchain to compile test firmware (according to TESTNAME) into program.hex, iccm.hex, dccm.hex, and mailbox.hex. As a first pass, integrators may alternatively use the pre-built hexfiles for convenience (available for `iccm_lock` test). To do this, copy `iccm_lock.hex` to the run directory and rename to `program.hex`. `dccm.hex` should also be copied to the run directory, as-is. Use `touch iccm.hex mailbox.hex` to create empty hex files, as these are unnecessary for `iccm_lock` test.
+5. Run Caliptra/tools/scripts/Makefile, which provides steps to run a top-level simulation in Verilator
     - Example command:
         `make -C <path/to/run/folder> -f ${CALIPTRA_ROOT}/tools/scripts/Makefile TESTNAME=${TESTNAME} debug=1 verilator`
     - NOTE: `debug=1` is optional; if provided, the verilator run will produce a .vcd file with waveform information
     - NOTE: `TESTNAME=${TESTNAME}` is optional; if not provided, test defaults to value of TESTNAME environment variable, then to `iccm_lock`
     - NOTE: Users may wish to produce a run log by piping the make command to a tee command, e.g.:
         `make ... <args> ... | tee <path/to/run/folder>/verilate.log`
-1. Users have the option to run the entire suite of smoke tests using the provided python script `run_verilator_l0_regression.py`
+6. Users have the option to run the entire suite of smoke tests using the provided python script `run_verilator_l0_regression.py`
     1. Ensure Python 3.9.2 is available by adding to the $PATH variable
-    1. Run the script with:
+    2. Run the script with:
         `python3 run_verilator_l0_regression.py`
-    1. NOTE: The script automatically creates run output folders at `${CALIPTRA_WORKSPACE}/scratch/$USER/verilator/<timestamp>/<testname>` for each test run
-    1. NOTE: The output folder is populated with a run log that reports the run results and pass/fail status
+    3. NOTE: The script automatically creates run output folders at `${CALIPTRA_WORKSPACE}/scratch/$USER/verilator/<timestamp>/<testname>` for each test run
+    4. NOTE: The output folder is populated with a run log that reports the run results and pass/fail status
 
 ### UVM Testbench Steps for `caliptra_top`: <BR>
 
@@ -163,16 +181,18 @@ The UVM Framework generation tool was used to create the baseline UVM testbench
 
 Steps:<BR>
 1. Compile UVM 1.1d library
-1. Compile the AHB/APB QVIP source
-1. Compile the UVMF wrapper for APB/AHB in Caliptra/src/libs/uvmf
-1. Compile the `verification_ip` provided for `soc_ifc` found in `Caliptra/src/soc_ifc/uvmf_soc_ifc`
-1. Compile the `caliptra_top` testbench found in `Caliptra/src/integration/uvmf_caliptra_top`
-1. `Caliptra/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/testbench/hdl_top.sv` is the top-level TB wrapper for the system
-1. Select a test to run from the set of tests in `Caliptra/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src`
-1. Provide `+UVM_TESTNAME=<test>` argument to simulation
+2. Compile the AHB/APB QVIP source
+3. Compile the UVMF wrapper for APB/AHB in Caliptra/src/libs/uvmf
+4. Compile the `verification_ip` provided for `soc_ifc` found in `Caliptra/src/soc_ifc/uvmf_soc_ifc`
+5. Compile the `caliptra_top` testbench found in `Caliptra/src/integration/uvmf_caliptra_top`
+6. `Caliptra/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/testbench/hdl_top.sv` is the top-level TB wrapper for the system
+7. Select a test to run from the set of tests in `Caliptra/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src`
+8. Provide `+UVM_TESTNAME=<test>` argument to simulation
+
+## **Regression Tests** ##
 
+Only tests from the L0 Regression List should be run. 
 ## **NOTES** ##
 
-* The internal registers are auto rendered at the [GitHub
-  page](https://chipsalliance.github.io/caliptra-rtl/main/internal-regs)
+* The internal registers are auto rendered at the [GitHub page](https://chipsalliance.github.io/caliptra-rtl/main/internal-regs)
 * So are the [external registers](https://chipsalliance.github.io/caliptra-rtl/main/external-regs)
diff --git a/Release_Notes.md b/Release_Notes.md
index e0986bb3b..3dc7c388d 100644
--- a/Release_Notes.md
+++ b/Release_Notes.md
@@ -14,13 +14,113 @@ See the License for the specific language governing permissions and<BR>
 limitations under the License.*_<BR>
 
 # **Release Notes** #
-_*Last Update: 2023/05/09*_
+_*Last Update: 2023/09/13*_
 
-## Rev 0p8 ##
+## Rev 1p0 ##
 
-### DISCALIMER: This is NOT A BUG-FREE MODEL YET. This is a 0p8 release model. Please see testplan document in docs folder to know the status of validation. ###
-#### This model is released mainly for interface, floorplan planning purposes for consumers. ####
-#### Rev 0p8 release date: 03-31-2023 ####
+### Rev 1p0 release date: (pending ROM release for official declaration) ###
+- Caliptra IP Specification: see docs/ folder
+- Caliptra Integration Specification: see docs/ folder
+- Caliptra testplan: see docs/ folder
+- Data Vault
+- RISC-V Timers
+  - mtime + mtimecmp implementation
+  - Watchdog timer configuration by SOC; escalate interrupts to error
+- Reliability, Availability, Serviceability Features
+  - Connectivity for cptra_error_fatal/cptra_error_non_fatal interrupts
+  - Mailbox protocol violation detection and Error state
+  - SRAM ECC error detection and reporting for ICCM, DCCM, Mailbox
+  - Key clearing and system reset on fatal errors
+- SOC Interface
+  - QSPI inout changed to input+output+enable
+  - FUSE PAUSER config registers and enforcement
+- Reset Domain Crossing (RDC) fixes
+  - Reset-triggered clock gating on cross-domain registers
+  - Reset timing changes for noncore reset assertion
+  - Migrate most internal logic to the noncore reset domain
+  - Migrate APB interface to noncore reset domain
+- FIPS compliance updates
+  - SHA Accelerator LOCK default to Caliptra-owned
+  - LMS Fuse
+  - SOC Stepping ID field in HW Revision
+  - Extended pcr_nonce from 32-bit to 256-bit
+  - TRNG Data Clear
+- RISC-V Core
+  - Increase ROM size to 48KiB
+  - Added 2:1 AHB lite mux on LSU and SB buses to allow debug access to
+    peripherals
+- Timing Optimizations
+  - Remove PSEL loopback path in APB slave
+  - Remove unnecessary Mailbox SRAM ECC writeback path
+- Validation enhancements
+  - SOC_IFC/Mailbox randomized regressions via UVM testbench
+  - SOC Interface Register validation via directed + random tests
+  - Coverage reporting and analysis for all interfaces, registers, FSM
+  - Automated GitHub action using OpenOCD for interactive JTAG debugging
+  - SHA Formal Verification
+
+### Bug Fixes ###
+[CLK GATING] Fatal error should wake up clks<br>
+[CLK GATING] JTAG accesses need to wake up clocks<br>
+[DOE] add zeroize to clear all internal regs<br>
+[DOE] DOE IV reg needs hwclr input<br>
+[DOE] doe_fsm incr_dest_sel logic can be removed since FE now only takes up 12 dwords<br>
+[DOE] doe_fsm write_offset increments to 0xC<br>
+[DOE] Simplify kv_write dest_valid hardcoded value in doe_fsm<br>
+[ECC] ECC input register bound check<br>
+[ECC] ECC output register bound check<br>
+[ECC] ECC Public key validation check<br>
+[ECC] mismatch of final reduction in Mont. mult in the case of prime<= p_internal<br>
+[ECC] mismatch of modular addition result in the case of p<= a+b < 2^384<br>
+[ECC] remove FW read access to kv/privkey reg<br>
+[ECC} error trigger when pcr_sign ctrl input is set in keygen/verifying mode<br>
+[KV] Debug Mode and Scan Mode switch doesn't flush locked registers<br>
+[KV] Debug mode should flush KV even if core is asleep<br>
+[KV] Dest_valid and last_dword should check lock_use to clear along with lock_wr<br>
+[KV] KV may still contain secrets during scan mode<br>
+[KV] kv_reg.rdl still has 6 bits for dest_valid while we have 5 valid clients<br>
+[KV] KV->SHA ->FW read path and KV->HMAC->FW read path should NOT exist in the design<br>
+[KV] last dword of secret values stays in KV/crypto interface<br>
+[KV] Suppress writes to an entry altogether when it's being cleared<br>
+[MBOX] ECC error decode may detect error on mbox_sram when a write is in progress<br>
+[MBOX] First resp read data is zero after handling a command with DLEN > MBOX SIZE<br>
+[MBOX] HWCLR triggered by force-unlock has lower precedence than SW writes<br>
+[MBOX] Mailbox data length limiting reads is calculated incorrectly<br>
+[MBOX] Mailbox does not flag protocol error for attempted writes to DLEN<br>
+[MBOX] mailbox returns non-zero data in an overread case<br>
+[MBOX] New RAS feature to detect protocol violation incorrectly decodes certain reg accesses as errors<br>
+[MBOX] SOC can read mbox_dataout with stale data<br>
+[MBOX] Writes beyond the mailbox size overwrite the last data dword in mailbox memory<br>
+[MBOX] Writes to (a) unaligned addresses (b) size < AHB_DATA_WIDTH may corrupt memory<br>
+[MBOX] error_cmd_fail_sts.hwset is continuously set when mailbox protocol error occurs<br>
+[PCR] Extend PCR Nonce from 32-bit to 256-bit to protect replay attack<br>
+[PCR] PCR dword mismatch<br>
+[PCR] Update the reset of the 'lock' PCR control to the core reset domain (so that a FW update reset or warm reset can also unlock the PCR)<br>
+[PCR] zeroize doesn't take effect if is set with pcr at the same cycle<br>
+[SHA ACCEL] SoC requester can use mailbox mode<br>
+[SOC_IFC] Arbiter lets direct request dv through at the same time as soc ifc mailbox request causing deadlock<br>
+[SOC_IFC] Breakpoint is unreachable<br>
+[SOC_IFC] Fuse Registers can never be written using non-default values programmed in FUSE_VALID_PAUSER<br>
+[SOC_IFC] Generic Input Wires toggle (any bit) should trigger notification interrupt to uC<br>
+[SOC_IFC] INTERNAL_HW_ERROR_FATAL_MASK and INTERNAL_HW_ERROR_NON_FATAL_MASK allow writes to (and non-zero reads from) reserved fields.<br>
+[SOC_IFC] Mailbox ECC errors detected during SHA Accel direct accesses are not detected/corrected<br>
+[SOC_IFC] mbox_execute can be cleared by SOC at any point after acquiring lock<br>
+[SOC_IFC] uC can't write to CPTRA_FW_ERROR regs (Github issue #64)<br>
+[SOC_IFC] WDT may not correctly detect when uC services the timer expiration interrupt<br>
+[WDT] CPTRA_WDT_STATUS reg should be FW writeable so it can clear the flags<br>
+[WDT] First stage interrupt output should be "error_intr" instead of "notif_intr"<br>
+[WDT] WDT registers need to be on ungated clk<br>
+[AHB] AHB 2:1 Mux hangs with back to back transactions after a stall<br>
+[RST] scan_mode should not corrupt resets<br>
+[TOP] EL2 Mem interface is not instantiated with a modport at all levels
+
+## Previous Releases ##
+
+### Rev 0p8 ###
+
+#### DISCALIMER: This is NOT A BUG-FREE MODEL YET. This is a 0p8 release model. Please see testplan document in docs folder to know the status of validation. ####
+##### This model is released mainly for interface, floorplan planning purposes for consumers. #####
+##### Rev 0p8 release date: 03-31-2023 #####
 
 - Caliptra IP Specification: see docs/ folder
 - Caliptra Integration Specification: see docs/ folder
@@ -59,13 +159,6 @@ _*Last Update: 2023/05/09*_
     - UVMF for multiple DUT blocks and SOC interface
     - DV complete for first cut of the boot & reset flows, Fuses, SOC registers, Crypto blocks, Key vault, PCR Vault, PCR extend, PCR signing, Mailbox
 
-## Pending for RTL 1p0: ##
-- Timers, integrated-TRNG integration w/ Caliptra, Error domain logic
-- Lots of bug fixes :-)
-- Data Vault, TRNG REQ protocol, SHA384 acceleration, More mailbox val, PCR val, cross product flows
-
-## Previous Releases ##
-
 ### Rev Pre0p8: ###
 #### DISCLAIMER: This is NOT A BUG-FREE MODEL. This is a pre-0p8 development model that will be sync’d every week. ####
 #### This model is released mainly for interface, floorplan planning purposes for consumers. ####
diff --git a/docs/Caliptra_Hardware_Specification.pdf b/docs/Caliptra_Hardware_Specification.pdf
index 6896ae8e2..68f46575c 100755
Binary files a/docs/Caliptra_Hardware_Specification.pdf and b/docs/Caliptra_Hardware_Specification.pdf differ
diff --git a/docs/Caliptra_Integration_Specification.pdf b/docs/Caliptra_Integration_Specification.pdf
index 2d8aed469..0cc3f9ebe 100755
Binary files a/docs/Caliptra_Integration_Specification.pdf and b/docs/Caliptra_Integration_Specification.pdf differ
diff --git a/docs/Caliptra_TestPlan.pdf b/docs/Caliptra_TestPlan.pdf
deleted file mode 100755
index 30d1afd45..000000000
Binary files a/docs/Caliptra_TestPlan.pdf and /dev/null differ
diff --git a/docs/Caliptra_TestPlan.xlsx b/docs/Caliptra_TestPlan.xlsx
new file mode 100755
index 000000000..f93fe7421
Binary files /dev/null and b/docs/Caliptra_TestPlan.xlsx differ
diff --git a/src/aes/config/aes.vf b/src/aes/config/aes.vf
index 2c5c07735..9592049a5 100644
--- a/src/aes/config/aes.vf
+++ b/src/aes/config/aes.vf
@@ -1,10 +1,15 @@
++incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl
 +incdir+${CALIPTRA_ROOT}/src/integration/rtl
 +incdir+${CALIPTRA_ROOT}/src/libs/rtl
-+incdir+${CALIPTRA_ROOT}/src/prim/rtl
++incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl
 +incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl
 +incdir+${CALIPTRA_ROOT}/src/edn/rtl
++incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl
 +incdir+${CALIPTRA_ROOT}/src/aes/rtl
-+incdir+${CALIPTRA_ROOT}/src/prim_generic/rtl
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm_pkg.sv
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_ack_sm_pkg.sv
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_reg_pkg.sv
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_pkg.sv
 ${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh
 ${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh
 ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sva.svh
@@ -16,51 +21,56 @@ ${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_util_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_alert_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_mubi_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_cipher_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_pkg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv
 ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv
 ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv
 ${CALIPTRA_ROOT}/src/edn/rtl/edn_pkg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_en.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cdc_rand_delay.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lfsr.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi4_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_diff_decode.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_slicer.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_count.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_dom_and_2share.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_reg_we_check.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_max_tree.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_arb.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_intr_hw.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_onehot_check.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi8_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync_cnt.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lc_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_receiver.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_sender.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv
 ${CALIPTRA_ROOT}/src/aes/rtl/aes_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/aes/rtl/aes_pkg.sv
 ${CALIPTRA_ROOT}/src/aes/rtl/aes_sbox_canright_pkg.sv
-${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
-${CALIPTRA_ROOT}/src/prim_generic/rtl/prim_generic_flop.sv
-${CALIPTRA_ROOT}/src/prim_generic/rtl/prim_generic_buf.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_flop_2sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_lfsr.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_mubi4_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_diff_decode.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sec_anchor_buf.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_slicer.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_count.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sparse_fsm_flop.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_dom_and_2share.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sec_anchor_flop.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_reg_we_check.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_packer_fifo.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_max_tree.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg_arb.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_intr_hw.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_onehot_check.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_mubi8_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_fifo_sync_cnt.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_buf.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_lc_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_alert_receiver.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_flop.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_alert_sender.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_fifo_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_arbiter_ppc.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sum_tree.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg_ext.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_edge_detector.sv
 ${CALIPTRA_ROOT}/src/aes/rtl/aes_sbox_canright.sv
 ${CALIPTRA_ROOT}/src/aes/rtl/aes_sbox_canright_masked.sv
 ${CALIPTRA_ROOT}/src/aes/rtl/aes_cipher_core.sv
@@ -78,4 +88,4 @@ ${CALIPTRA_ROOT}/src/aes/rtl/aes_shift_rows.sv
 ${CALIPTRA_ROOT}/src/aes/rtl/aes_mix_single_column.sv
 ${CALIPTRA_ROOT}/src/aes/rtl/aes_cipher_control.sv
 ${CALIPTRA_ROOT}/src/aes/rtl/aes_prng_masking.sv
-${CALIPTRA_ROOT}/src/aes/rtl/aes_key_expand.sv
\ No newline at end of file
+${CALIPTRA_ROOT}/src/aes/rtl/aes_key_expand.sv
diff --git a/src/aes/config/aes_pkg.vf b/src/aes/config/aes_pkg.vf
index 75b3506c8..5c75eb1af 100644
--- a/src/aes/config/aes_pkg.vf
+++ b/src/aes/config/aes_pkg.vf
@@ -1,6 +1,73 @@
++incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl
++incdir+${CALIPTRA_ROOT}/src/integration/rtl
++incdir+${CALIPTRA_ROOT}/src/libs/rtl
++incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl
++incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl
 +incdir+${CALIPTRA_ROOT}/src/edn/rtl
++incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl
 +incdir+${CALIPTRA_ROOT}/src/aes/rtl
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm_pkg.sv
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_ack_sm_pkg.sv
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_reg_pkg.sv
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_pkg.sv
+${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh
+${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sva.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_macros.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sram.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_defines_pkg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_ahb_srom.sv
+${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv
+${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv
+${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv
+${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv
 ${CALIPTRA_ROOT}/src/edn/rtl/edn_pkg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_en.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cdc_rand_delay.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lfsr.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi4_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_diff_decode.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_slicer.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_count.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_dom_and_2share.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_reg_we_check.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_max_tree.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_arb.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_intr_hw.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_onehot_check.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi8_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync_cnt.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lc_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_receiver.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_sender.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv
 ${CALIPTRA_ROOT}/src/aes/rtl/aes_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/aes/rtl/aes_pkg.sv
 ${CALIPTRA_ROOT}/src/aes/rtl/aes_sbox_canright_pkg.sv
\ No newline at end of file
diff --git a/src/aes/config/compile.yml b/src/aes/config/compile.yml
index b58d3118f..fc4379b07 100644
--- a/src/aes/config/compile.yml
+++ b/src/aes/config/compile.yml
@@ -3,6 +3,7 @@ provides: [aes_pkg]
 schema_version: 2.4.0
 requires:
   - edn_pkg
+  - caliptra_prim
 targets:
   rtl:
     directories: [$COMPILE_ROOT/rtl]
@@ -15,7 +16,6 @@ provides: [aes]
 schema_version: 2.4.0
 requires:
   - aes_pkg
-  - prim
 targets:
   rtl:
     directories: [$COMPILE_ROOT/rtl]
@@ -38,4 +38,4 @@ targets:
       - $COMPILE_ROOT/rtl/aes_cipher_control.sv
       - $COMPILE_ROOT/rtl/aes_prng_masking.sv
       - $COMPILE_ROOT/rtl/aes_key_expand.sv
-    tops: [aes_fixme]
+    tops: [aes_cipher_core]
diff --git a/src/aes/rtl/aes_cipher_control.sv b/src/aes/rtl/aes_cipher_control.sv
index 2e9745d18..ea0c65092 100644
--- a/src/aes/rtl/aes_cipher_control.sv
+++ b/src/aes/rtl/aes_cipher_control.sv
@@ -6,7 +6,7 @@
 //
 // This module controls the AES cipher core including the key expand module.
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
 module aes_cipher_control import aes_pkg::*;
 #(
@@ -400,7 +400,7 @@ module aes_cipher_control import aes_pkg::*;
   // The following primitives are used to place a size-only constraint on the
   // flops in order to prevent optimizations on these status signals.
   logic [Sp2VWidth-1:0] crypt_q_raw;
-  prim_flop #(
+  caliptra_prim_flop #(
     .Width      ( Sp2VWidth            ),
     .ResetValue ( Sp2VWidth'(SP2V_LOW) )
   ) u_crypt_regs (
@@ -411,7 +411,7 @@ module aes_cipher_control import aes_pkg::*;
   );
 
   logic [Sp2VWidth-1:0] dec_key_gen_q_raw;
-  prim_flop #(
+  caliptra_prim_flop #(
     .Width      ( Sp2VWidth            ),
     .ResetValue ( Sp2VWidth'(SP2V_LOW) )
   ) u_dec_key_gen_regs (
diff --git a/src/aes/rtl/aes_cipher_control_fsm.sv b/src/aes/rtl/aes_cipher_control_fsm.sv
index 3bc037086..3d63128fa 100644
--- a/src/aes/rtl/aes_cipher_control_fsm.sv
+++ b/src/aes/rtl/aes_cipher_control_fsm.sv
@@ -6,7 +6,7 @@
 //
 // This module contains the AES cipher core control FSM.
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
 module aes_cipher_control_fsm import aes_pkg::*;
 #(
@@ -445,7 +445,7 @@ module aes_cipher_control_fsm import aes_pkg::*;
   end
 
   // SEC_CM: CIPHER.FSM.SPARSE
-  `PRIM_FLOP_SPARSE_FSM(u_state_regs, aes_cipher_ctrl_ns,
+  `CALIPTRA_PRIM_FLOP_SPARSE_FSM(u_state_regs, aes_cipher_ctrl_ns,
       aes_cipher_ctrl_cs, aes_cipher_ctrl_e, CIPHER_CTRL_IDLE)
 
   always_ff @(posedge clk_i or negedge rst_ni) begin : reg_fsm
diff --git a/src/aes/rtl/aes_cipher_control_fsm_n.sv b/src/aes/rtl/aes_cipher_control_fsm_n.sv
index d862938dd..f56153b3b 100644
--- a/src/aes/rtl/aes_cipher_control_fsm_n.sv
+++ b/src/aes/rtl/aes_cipher_control_fsm_n.sv
@@ -8,7 +8,7 @@
 // values of important control signals. This is achieved by:
 // - instantiating the regular AES cipher core control FSM operating on and producing the positive
 //   values of these signals, and
-// - inverting these signals between the regular FSM and the prim_buf synthesis barriers.
+// - inverting these signals between the regular FSM and the caliptra_prim_buf synthesis barriers.
 // Synthesis tools will then push the inverters into the actual FSM.
 
 module aes_cipher_control_fsm_n import aes_pkg::*;
@@ -142,9 +142,9 @@ module aes_cipher_control_fsm_n import aes_pkg::*;
 
   // This primitive is used to place a size-only constraint on the
   // buffers to act as a synthesis optimization barrier.
-  prim_buf #(
+  caliptra_prim_buf #(
     .Width(NumInBufBits)
-  ) u_prim_buf_in (
+  ) u_caliptra_prim_buf_in (
     .in_i(in),
     .out_o(in_buf)
   );
@@ -233,7 +233,7 @@ module aes_cipher_control_fsm_n import aes_pkg::*;
 
   // The regular FSM operates on and produces the positive values of important control signals.
   // Invert *_n input signals here to get the positive values for the regular FSM. To obtain the
-  // negated outputs, important output signals are inverted further below. Thanks to the prim_buf
+  // negated outputs, important output signals are inverted further below. Thanks to the caliptra_prim_buf
   // synthesis optimization barriers, tools will push the inverters into the regular FSM.
   aes_cipher_control_fsm #(
     .SecMasking  ( SecMasking  ),
@@ -364,9 +364,9 @@ module aes_cipher_control_fsm_n import aes_pkg::*;
 
   // This primitive is used to place a size-only constraint on the
   // buffers to act as a synthesis optimization barrier.
-  prim_buf #(
+  caliptra_prim_buf #(
     .Width(NumOutBufBits)
-  ) u_prim_buf_out (
+  ) u_caliptra_prim_buf_out (
     .in_i(out),
     .out_o(out_buf)
   );
diff --git a/src/aes/rtl/aes_cipher_control_fsm_p.sv b/src/aes/rtl/aes_cipher_control_fsm_p.sv
index ee823b3c1..749eaf2fc 100644
--- a/src/aes/rtl/aes_cipher_control_fsm_p.sv
+++ b/src/aes/rtl/aes_cipher_control_fsm_p.sv
@@ -138,9 +138,9 @@ module aes_cipher_control_fsm_p import aes_pkg::*;
 
   // This primitive is used to place a size-only constraint on the
   // buffers to act as a synthesis optimization barrier.
-  prim_buf #(
+  caliptra_prim_buf #(
     .Width(NumInBufBits)
-  ) u_prim_buf_in (
+  ) u_caliptra_prim_buf_in (
     .in_i(in),
     .out_o(in_buf)
   );
@@ -354,9 +354,9 @@ module aes_cipher_control_fsm_p import aes_pkg::*;
 
   // This primitive is used to place a size-only constraint on the
   // buffers to act as a synthesis optimization barrier.
-  prim_buf #(
+  caliptra_prim_buf #(
     .Width(NumOutBufBits)
-  ) u_prim_buf_out (
+  ) u_caliptra_prim_buf_out (
     .in_i(out),
     .out_o(out_buf)
   );
diff --git a/src/aes/rtl/aes_cipher_core.sv b/src/aes/rtl/aes_cipher_core.sv
index cd8b7fc16..c6754c35a 100644
--- a/src/aes/rtl/aes_cipher_core.sv
+++ b/src/aes/rtl/aes_cipher_core.sv
@@ -90,7 +90,7 @@
 // - KEY_SHARE0_6 32h'{  .    .    .    .  }
 // - KEY_SHARE0_7 32h'{ b31, b30, b29, b28 } .
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
 module aes_cipher_core import aes_pkg::*;
 #(
diff --git a/src/aes/rtl/aes_key_expand.sv b/src/aes/rtl/aes_key_expand.sv
index a90ff804c..230536856 100644
--- a/src/aes/rtl/aes_key_expand.sv
+++ b/src/aes/rtl/aes_key_expand.sv
@@ -4,7 +4,7 @@
 //
 // AES KeyExpand
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
 module aes_key_expand import aes_pkg::*;
 #(
diff --git a/src/aes/rtl/aes_pkg.sv b/src/aes/rtl/aes_pkg.sv
index 6eeb549ae..170be20f2 100644
--- a/src/aes/rtl/aes_pkg.sv
+++ b/src/aes/rtl/aes_pkg.sv
@@ -17,7 +17,7 @@ parameter int unsigned NumSharesKey = 2;
 // Software updates IV in chunks of 32 bits, the counter updates 16 bits at a time.
 parameter int unsigned SliceSizeCtr = 16;
 parameter int unsigned NumSlicesCtr = aes_reg_pkg::NumRegsIv * 32 / SliceSizeCtr;
-parameter int unsigned SliceIdxWidth = prim_util_pkg::vbits(NumSlicesCtr);
+parameter int unsigned SliceIdxWidth = caliptra_prim_util_pkg::vbits(NumSlicesCtr);
 
 // Widths of signals carrying pseudo-random data for clearing
 parameter int unsigned WidthPRDClearing = 64;
diff --git a/src/aes/rtl/aes_prng_masking.sv b/src/aes/rtl/aes_prng_masking.sv
index 011a15acd..455cafebb 100644
--- a/src/aes/rtl/aes_prng_masking.sv
+++ b/src/aes/rtl/aes_prng_masking.sv
@@ -18,7 +18,7 @@
 // for masking purposes.                                                                         //
 ///////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
 module aes_prng_masking import aes_pkg::*;
 #(
@@ -96,7 +96,7 @@ module aes_prng_masking import aes_pkg::*;
   if (ChunkSize == EntropyWidth) begin : gen_counter
     // We can reseed chunk by chunk as we get fresh entropy. Need to keep track of which chunk to
     // reseed next.
-    localparam int unsigned ChunkIdxWidth = prim_util_pkg::vbits(NumChunks);
+    localparam int unsigned ChunkIdxWidth = caliptra_prim_util_pkg::vbits(NumChunks);
     logic [ChunkIdxWidth-1:0] chunk_idx_d, chunk_idx_q;
     logic                     prng_reseed_done;
 
@@ -133,11 +133,11 @@ module aes_prng_masking import aes_pkg::*;
     assign entropy_req_o = SecSkipPRNGReseeding ? 1'b0         : reseed_req_i & ~seed_valid;
     assign reseed_ack_o  = SecSkipPRNGReseeding ? reseed_req_i : seed_valid;
 
-    prim_packer_fifo #(
+    caliptra_prim_packer_fifo #(
       .InW         ( EntropyWidth ),
       .OutW        ( Width        ),
       .ClearOnRead ( 1'b0         )
-    ) u_prim_packer_fifo (
+    ) u_caliptra_prim_packer_fifo (
       .clk_i    ( clk_i         ),
       .rst_ni   ( rst_ni        ),
       .clr_i    ( 1'b0          ), // Not needed.
@@ -163,7 +163,7 @@ module aes_prng_masking import aes_pkg::*;
 
   // We use multiple LFSR instances each having a width of ChunkSize.
   for (genvar c = 0; c < NumChunks; c++) begin : gen_lfsrs
-    prim_lfsr #(
+    caliptra_prim_lfsr #(
       .LfsrType     ( "GAL_XOR"                                   ),
       .LfsrDw       ( ChunkSize                                   ),
       .StateOutDw   ( ChunkSize                                   ),
diff --git a/src/aes/rtl/aes_sbox.sv b/src/aes/rtl/aes_sbox.sv
index a13900c3e..560720c7d 100644
--- a/src/aes/rtl/aes_sbox.sv
+++ b/src/aes/rtl/aes_sbox.sv
@@ -4,7 +4,7 @@
 //
 // AES SBox
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
 module aes_sbox import aes_pkg::*;
 #(
diff --git a/src/aes/rtl/aes_sbox_canright_masked.sv b/src/aes/rtl/aes_sbox_canright_masked.sv
index 45c4ff749..a20001478 100644
--- a/src/aes/rtl/aes_sbox_canright_masked.sv
+++ b/src/aes/rtl/aes_sbox_canright_masked.sv
@@ -24,7 +24,7 @@
 // IMPORTANT NOTE:                                                                               //
 //                            DO NOT USE THIS FOR SYNTHESIS BLINDLY!                             //
 //                                                                                               //
-// This implementation relies on primitive cells like prim_buf/xor2 containing tool-specific     //
+// This implementation relies on primitive cells like caliptra_prim_buf/xor2 containing tool-specific     //
 // synthesis attributes to enforce the correct ordering of operations and avoid aggressive       //
 // optimization. Without the proper primitives, synthesis tools might heavily optimize the       //
 // design. The result is likely insecure. Use with care.                                         //
@@ -59,9 +59,9 @@ module aes_masked_inverse_gf2p4 (
 
   // Avoid aggressive synthesis optimizations.
   logic [1:0] mul_b0_q1_buf, mul_b1_q0_buf, mul_q1_q0_buf;
-  prim_buf #(
+  caliptra_prim_buf #(
     .Width ( 6 )
-  ) u_prim_buf_mul_bq01 (
+  ) u_caliptra_prim_buf_mul_bq01 (
     .in_i  ( {mul_b0_q1,     mul_b1_q0,     mul_q1_q0}     ),
     .out_o ( {mul_b0_q1_buf, mul_b1_q0_buf, mul_q1_q0_buf} )
   );
@@ -85,16 +85,16 @@ module aes_masked_inverse_gf2p4 (
   // These terms are added to other terms that depend on the same inputs.
   // Avoid aggressive synthesis optimizations.
   logic [1:0] scale_omega2_b_buf, scale_omega2_q_buf;
-  prim_buf #(
+  caliptra_prim_buf #(
     .Width ( 4 )
-  ) u_prim_buf_scale_omega2_bq (
+  ) u_caliptra_prim_buf_scale_omega2_bq (
     .in_i  ( {scale_omega2_b,     scale_omega2_q}     ),
     .out_o ( {scale_omega2_b_buf, scale_omega2_q_buf} )
   );
   logic [1:0] mul_b1_b0_buf;
-  prim_buf #(
+  caliptra_prim_buf #(
     .Width ( 2 )
-  ) u_prim_buf_mul_b1_b0 (
+  ) u_caliptra_prim_buf_mul_b1_b0 (
     .in_i  ( mul_b1_b0     ),
     .out_o ( mul_b1_b0_buf )
   );
@@ -111,9 +111,9 @@ module aes_masked_inverse_gf2p4 (
 
   // Avoid aggressive synthesis optimizations.
   for (genvar i = 0; i < 6; i++) begin : gen_c_buf
-    prim_buf #(
+    caliptra_prim_buf #(
       .Width ( 2 )
-    ) u_prim_buf_c_i (
+    ) u_caliptra_prim_buf_c_i (
       .in_i  ( c[i]     ),
       .out_o ( c_buf[i] )
     );
@@ -137,32 +137,32 @@ module aes_masked_inverse_gf2p4 (
 
   // Get intermediate terms.
   logic [1:0] xor_q1_r_sq, xor_q0_q1, c1_inv, c2_inv;
-  prim_xor2 #(
+  caliptra_prim_xor2 #(
     .Width ( 2 )
-  ) u_prim_xor_q1_r_sq (
+  ) u_caliptra_prim_xor_q1_r_sq (
     .in0_i ( q1          ),
     .in1_i ( r_sq        ),
     .out_o ( xor_q1_r_sq )
   );
-  prim_xor2 #(
+  caliptra_prim_xor2 #(
     .Width ( 2 )
-  ) u_prim_xor_q0_q1 (
+  ) u_caliptra_prim_xor_q0_q1 (
     .in0_i ( q0        ),
     .in1_i ( q1        ),
     .out_o ( xor_q0_q1 )
   );
 
   // Generate c1_inv and c2_inv.
-  prim_xor2 #(
+  caliptra_prim_xor2 #(
     .Width ( 2 )
-  ) u_prim_c1_inv (
+  ) u_caliptra_prim_c1_inv (
     .in0_i ( xor_q1_r_sq ),
     .in1_i ( c_inv       ),
     .out_o ( c1_inv      )
   );
-  prim_xor2 #(
+  caliptra_prim_xor2 #(
     .Width ( 2 )
-  ) u_prim_c2_inv (
+  ) u_caliptra_prim_c2_inv (
     .in0_i ( c1_inv    ),
     .in1_i ( xor_q0_q1 ),
     .out_o ( c2_inv    )
@@ -187,9 +187,9 @@ module aes_masked_inverse_gf2p4 (
   // The multiplier outputs are added to terms that depend on the same inputs.
   // Avoid aggressive synthesis optimizations.
   logic [1:0] mul_b0_c1_inv_buf, mul_q0_c1_inv_buf, mul_b1_c2_inv_buf, mul_q1_c2_inv_buf;
-  prim_buf #(
+  caliptra_prim_buf #(
     .Width ( 8 )
-  ) u_prim_buf_mul_bq01_c12_inv (
+  ) u_caliptra_prim_buf_mul_bq01_c12_inv (
     .in_i  ( {mul_b0_c1_inv,     mul_q0_c1_inv,     mul_b1_c2_inv,     mul_q1_c2_inv}     ),
     .out_o ( {mul_b0_c1_inv_buf, mul_q0_c1_inv_buf, mul_b1_c2_inv_buf, mul_q1_c2_inv_buf} )
   );
@@ -210,15 +210,15 @@ module aes_masked_inverse_gf2p4 (
 
   // Avoid aggressive synthesis optimizations.
   for (genvar i = 0; i < 4; i++) begin : gen_a01_inv_buf
-    prim_buf #(
+    caliptra_prim_buf #(
       .Width ( 2 )
-    ) u_prim_buf_b1_inv_i (
+    ) u_caliptra_prim_buf_b1_inv_i (
       .in_i  ( b1_inv[i]     ),
       .out_o ( b1_inv_buf[i] )
     );
-    prim_buf #(
+    caliptra_prim_buf #(
       .Width ( 2 )
-    ) u_prim_buf_b0_inv_i (
+    ) u_caliptra_prim_buf_b0_inv_i (
       .in_i  ( b0_inv[i]     ),
       .out_o ( b0_inv_buf[i] )
     );
@@ -268,9 +268,9 @@ module aes_masked_inverse_gf2p8 (
 
   // Avoid aggressive synthesis optimizations.
   logic [3:0] mul_a0_m1_buf, mul_a1_m0_buf, mul_m0_m1_buf;
-  prim_buf #(
+  caliptra_prim_buf #(
     .Width ( 12 )
-  ) u_prim_buf_mul_bq01 (
+  ) u_caliptra_prim_buf_mul_bq01 (
     .in_i  ( {mul_a0_m1,     mul_a1_m0,     mul_m0_m1}     ),
     .out_o ( {mul_a0_m1_buf, mul_a1_m0_buf, mul_m0_m1_buf} )
   );
@@ -295,9 +295,9 @@ module aes_masked_inverse_gf2p8 (
   // The multiplier output is added to terms that depend on the same inputs.
   // Avoid aggressive synthesis optimizations.
   logic [3:0] mul_a1_a0_buf;
-  prim_buf #(
+  caliptra_prim_buf #(
     .Width ( 4 )
-  ) u_prim_buf_mul_am01 (
+  ) u_caliptra_prim_buf_mul_am01 (
     .in_i  ( mul_a1_a0     ),
     .out_o ( mul_a1_a0_buf )
   );
@@ -314,9 +314,9 @@ module aes_masked_inverse_gf2p8 (
 
   // Avoid aggressive synthesis optimizations.
   for (genvar i = 0; i < 6; i++) begin : gen_b_buf
-    prim_buf #(
+    caliptra_prim_buf #(
       .Width ( 4 )
-    ) u_prim_buf_b_i (
+    ) u_caliptra_prim_buf_b_i (
       .in_i  ( b[i]     ),
       .out_o ( b_buf[i] )
     );
@@ -339,9 +339,9 @@ module aes_masked_inverse_gf2p8 (
   // with inputs to the GF(2^4) inverter. Aggressive synthesis optimizations across the GF(2^4)
   // inverter may result in SCA leakage and should be avoided.
   logic [3:0] b_inv_buf;
-  prim_buf #(
+  caliptra_prim_buf #(
     .Width ( 4 )
-  ) u_prim_buf_b_inv (
+  ) u_caliptra_prim_buf_b_inv (
     .in_i  ( b_inv     ),
     .out_o ( b_inv_buf )
   );
@@ -354,16 +354,16 @@ module aes_masked_inverse_gf2p8 (
 
   // Generate b2_inv step by step.
   logic [3:0] xor_m1_m0, b2_inv;
-  prim_xor2 #(
+  caliptra_prim_xor2 #(
     .Width ( 4 )
-  ) u_prim_xor_m1_m0 (
+  ) u_caliptra_prim_xor_m1_m0 (
     .in0_i ( m1        ),
     .in1_i ( m0        ),
     .out_o ( xor_m1_m0 )
   );
-  prim_xor2 #(
+  caliptra_prim_xor2 #(
     .Width ( 4 )
-  ) u_prim_xor_b2_inv (
+  ) u_caliptra_prim_xor_b2_inv (
     .in0_i ( b_inv_buf ),
     .in1_i ( xor_m1_m0 ),
     .out_o ( b2_inv    )
@@ -388,9 +388,9 @@ module aes_masked_inverse_gf2p8 (
   // The multiplier outputs are added to terms that depend on the same inputs.
   // Avoid aggressive synthesis optimizations.
   logic [3:0] mul_a0_b_inv_buf, mul_m0_b_inv_buf, mul_a1_b2_inv_buf, mul_m1_b2_inv_buf;
-  prim_buf #(
+  caliptra_prim_buf #(
     .Width ( 16 )
-  ) u_prim_buf_mul_bq01_c12_inv (
+  ) u_caliptra_prim_buf_mul_bq01_c12_inv (
     .in_i  ( {mul_a0_b_inv,     mul_m0_b_inv,     mul_a1_b2_inv,     mul_m1_b2_inv}     ),
     .out_o ( {mul_a0_b_inv_buf, mul_m0_b_inv_buf, mul_a1_b2_inv_buf, mul_m1_b2_inv_buf} )
   );
@@ -411,15 +411,15 @@ module aes_masked_inverse_gf2p8 (
 
   // Avoid aggressive synthesis optimizations.
   for (genvar i = 0; i < 4; i++) begin : gen_a01_inv_buf
-    prim_buf #(
+    caliptra_prim_buf #(
       .Width ( 4 )
-    ) u_prim_buf_a1_inv_i (
+    ) u_caliptra_prim_buf_a1_inv_i (
       .in_i  ( a1_inv[i]     ),
       .out_o ( a1_inv_buf[i] )
     );
-    prim_buf #(
+    caliptra_prim_buf #(
       .Width ( 4 )
-    ) u_prim_buf_a0_inv_i (
+    ) u_caliptra_prim_buf_a0_inv_i (
       .in_i  ( a0_inv[i]     ),
       .out_o ( a0_inv_buf[i] )
     );
diff --git a/src/aes/rtl/aes_sbox_canright_masked_noreuse.sv b/src/aes/rtl/aes_sbox_canright_masked_noreuse.sv
index 983a692d5..b4e8631e6 100644
--- a/src/aes/rtl/aes_sbox_canright_masked_noreuse.sv
+++ b/src/aes/rtl/aes_sbox_canright_masked_noreuse.sv
@@ -23,7 +23,7 @@
 // IMPORTANT NOTE:                                                                               //
 //                            DO NOT USE THIS FOR SYNTHESIS BLINDLY!                             //
 //                                                                                               //
-// This implementation relies on primitive cells like prim_buf containing tool-specific          //
+// This implementation relies on primitive cells like caliptra_prim_buf containing tool-specific          //
 // synthesis attributes to enforce the correct ordering of operations and avoid aggressive       //
 // optimization. Without the proper primitives, synthesis tools might heavily optimize the       //
 // design. The result is likely insecure. Use with care.                                         //
@@ -72,16 +72,16 @@ module aes_masked_inverse_gf2p4_noreuse (
   // These terms are added to other terms that depend on the same inputs.
   // Avoid aggressive synthesis optimizations.
   logic [1:0] scale_omega2_b_buf, scale_omega2_q_buf;
-  prim_buf #(
+  caliptra_prim_buf #(
     .Width ( 4 )
-  ) u_prim_buf_scale_omega2_bq (
+  ) u_caliptra_prim_buf_scale_omega2_bq (
     .in_i  ( {scale_omega2_b,     scale_omega2_q}     ),
     .out_o ( {scale_omega2_b_buf, scale_omega2_q_buf} )
   );
   logic [1:0] mul_b1_b0_buf, mul_b1_q0_buf, mul_b0_q1_buf, mul_q1_q0_buf;
-  prim_buf #(
+  caliptra_prim_buf #(
     .Width ( 8 )
-  ) u_prim_buf_mul_bq01 (
+  ) u_caliptra_prim_buf_mul_bq01 (
     .in_i  ( {mul_b1_b0,     mul_b1_q0,     mul_b0_q1,     mul_q1_q0}     ),
     .out_o ( {mul_b1_b0_buf, mul_b1_q0_buf, mul_b0_q1_buf, mul_q1_q0_buf} )
   );
@@ -98,9 +98,9 @@ module aes_masked_inverse_gf2p4_noreuse (
 
   // Avoid aggressive synthesis optimizations.
   for (genvar i = 0; i < 6; i++) begin : gen_c_buf
-    prim_buf #(
+    caliptra_prim_buf #(
       .Width ( 2 )
-    ) u_prim_buf_c_i (
+    ) u_caliptra_prim_buf_c_i (
       .in_i  ( c[i]     ),
       .out_o ( c_buf[i] )
     );
@@ -136,16 +136,16 @@ module aes_masked_inverse_gf2p4_noreuse (
   // The multiplier outputs are added to terms that depend on the same inputs.
   // Avoid aggressive synthesis optimizations.
   logic [1:0] mul_b0_r_sq_buf, mul_q0_c_inv_buf, mul_q0_r_sq_buf;
-  prim_buf #(
+  caliptra_prim_buf #(
     .Width ( 6 )
-  ) u_prim_buf_mul_bq0 (
+  ) u_caliptra_prim_buf_mul_bq0 (
     .in_i  ( {mul_b0_r_sq,     mul_q0_c_inv,     mul_q0_r_sq}     ),
     .out_o ( {mul_b0_r_sq_buf, mul_q0_c_inv_buf, mul_q0_r_sq_buf} )
   );
   logic [1:0] mul_b1_r_sq_buf, mul_q1_c_inv_buf, mul_q1_r_sq_buf;
-  prim_buf #(
+  caliptra_prim_buf #(
     .Width ( 6 )
-  ) u_prim_buf_mul_bq1 (
+  ) u_caliptra_prim_buf_mul_bq1 (
     .in_i  ( {mul_b1_r_sq,     mul_q1_c_inv,     mul_q1_r_sq}     ),
     .out_o ( {mul_b1_r_sq_buf, mul_q1_c_inv_buf, mul_q1_r_sq_buf} )
   );
@@ -166,15 +166,15 @@ module aes_masked_inverse_gf2p4_noreuse (
 
   // Avoid aggressive synthesis optimizations.
   for (genvar i = 0; i < 4; i++) begin : gen_a01_inv_buf
-    prim_buf #(
+    caliptra_prim_buf #(
       .Width ( 2 )
-    ) u_prim_buf_b1_inv_i (
+    ) u_caliptra_prim_buf_b1_inv_i (
       .in_i  ( b1_inv[i]     ),
       .out_o ( b1_inv_buf[i] )
     );
-    prim_buf #(
+    caliptra_prim_buf #(
       .Width ( 2 )
-    ) u_prim_buf_b0_inv_i (
+    ) u_caliptra_prim_buf_b0_inv_i (
       .in_i  ( b0_inv[i]     ),
       .out_o ( b0_inv_buf[i] )
     );
@@ -264,9 +264,9 @@ module aes_masked_inverse_gf2p8_noreuse (
   // The multiplier outputs are added to terms that depend on the same inputs.
   // Avoid aggressive synthesis optimizations.
   logic [3:0] mul_a1_a0_buf, mul_a1_m0_buf, mul_a0_m1_buf, mul_m0_m1_buf;
-  prim_buf #(
+  caliptra_prim_buf #(
     .Width ( 16 )
-  ) u_prim_buf_mul_am01 (
+  ) u_caliptra_prim_buf_mul_am01 (
     .in_i  ( {mul_a1_a0,     mul_a1_m0,     mul_a0_m1,     mul_m0_m1}     ),
     .out_o ( {mul_a1_a0_buf, mul_a1_m0_buf, mul_a0_m1_buf, mul_m0_m1_buf} )
   );
@@ -283,9 +283,9 @@ module aes_masked_inverse_gf2p8_noreuse (
 
   // Avoid aggressive synthesis optimizations.
   for (genvar i = 0; i < 6; i++) begin : gen_b_buf
-    prim_buf #(
+    caliptra_prim_buf #(
       .Width ( 4 )
-    ) u_prim_buf_b_i (
+    ) u_caliptra_prim_buf_b_i (
       .in_i  ( b[i]     ),
       .out_o ( b_buf[i] )
     );
@@ -308,9 +308,9 @@ module aes_masked_inverse_gf2p8_noreuse (
   // with inputs to the GF(2^4) inverter. Aggressive synthesis optimizations across the GF(2^4)
   // inverter may result in SCA leakage and should be avoided.
   logic [3:0] b_inv_buf;
-  prim_buf #(
+  caliptra_prim_buf #(
     .Width ( 4 )
-  ) u_prim_buf_b_inv (
+  ) u_caliptra_prim_buf_b_inv (
     .in_i  ( b_inv     ),
     .out_o ( b_inv_buf )
   );
@@ -339,16 +339,16 @@ module aes_masked_inverse_gf2p8_noreuse (
   // The multiplier outputs are added to terms that depend on the same inputs.
   // Avoid aggressive synthesis optimizations.
   logic [3:0] mul_a0_b_inv_buf, mul_a0_t_buf, mul_m0_b_inv_buf, mul_m0_t_buf;
-  prim_buf #(
+  caliptra_prim_buf #(
     .Width ( 16 )
-  ) u_prim_buf_mul_am0 (
+  ) u_caliptra_prim_buf_mul_am0 (
     .in_i  ( {mul_a0_b_inv,     mul_a0_t,     mul_m0_b_inv,     mul_m0_t}     ),
     .out_o ( {mul_a0_b_inv_buf, mul_a0_t_buf, mul_m0_b_inv_buf, mul_m0_t_buf} )
   );
   logic [3:0] mul_a1_b_inv_buf, mul_a1_t_buf, mul_m1_b_inv_buf, mul_m1_t_buf;
-  prim_buf #(
+  caliptra_prim_buf #(
     .Width ( 16 )
-  ) u_prim_buf_mul_am1 (
+  ) u_caliptra_prim_buf_mul_am1 (
     .in_i  ( {mul_a1_b_inv,     mul_a1_t,     mul_m1_b_inv,     mul_m1_t}     ),
     .out_o ( {mul_a1_b_inv_buf, mul_a1_t_buf, mul_m1_b_inv_buf, mul_m1_t_buf} )
   );
@@ -369,15 +369,15 @@ module aes_masked_inverse_gf2p8_noreuse (
 
   // Avoid aggressive synthesis optimizations.
   for (genvar i = 0; i < 4; i++) begin : gen_a01_inv_buf
-    prim_buf #(
+    caliptra_prim_buf #(
       .Width ( 4 )
-    ) u_prim_buf_a1_inv_i (
+    ) u_caliptra_prim_buf_a1_inv_i (
       .in_i  ( a1_inv[i]     ),
       .out_o ( a1_inv_buf[i] )
     );
-    prim_buf #(
+    caliptra_prim_buf #(
       .Width ( 4 )
-    ) u_prim_buf_a0_inv_i (
+    ) u_caliptra_prim_buf_a0_inv_i (
       .in_i  ( a0_inv[i]     ),
       .out_o ( a0_inv_buf[i] )
     );
diff --git a/src/aes/rtl/aes_sbox_dom.sv b/src/aes/rtl/aes_sbox_dom.sv
index c3519b3d4..6eedae7ef 100644
--- a/src/aes/rtl/aes_sbox_dom.sv
+++ b/src/aes/rtl/aes_sbox_dom.sv
@@ -32,13 +32,13 @@
 // IMPORTANT NOTE:                                                                               //
 //                            DO NOT USE THIS FOR SYNTHESIS BLINDLY!                             //
 //                                                                                               //
-// This implementation relies on primitive cells like prim_buf/flop_en containing tool-specific  //
+// This implementation relies on primitive cells like caliptra_prim_buf/flop_en containing tool-specific  //
 // synthesis attributes to prevent the synthesis tool from optimizing away/re-ordering registers //
 // and to enforce the correct ordering of operations. Without the proper primitives, synthesis   //
 // tools might heavily optimize the design. The result is likely insecure. Use with care.        //
 ///////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
 // Packed struct for pseudo-random data (PRD) input. Stages 1, 3 and 4 require 8 bits each. Stage 2
 // requires just 4 bits.
@@ -115,10 +115,10 @@ module aes_dom_indep_mul_gf2pn #(
   assign bq_z0_d = z_0 ^ mul_ay_bx;
 
   // Registers
-  prim_flop_en #(
+  caliptra_prim_flop_en #(
     .Width      ( 2*NPower ),
     .ResetValue ( '0       )
-  ) u_prim_flop_abq_z0 (
+  ) u_caliptra_prim_flop_abq_z0 (
     .clk_i  ( clk_i              ),
     .rst_ni ( rst_ni             ),
     .en_i   ( we_i               ),
@@ -137,10 +137,10 @@ module aes_dom_indep_mul_gf2pn #(
     // reshared cross-domain terms with inner-domain terms derived from different input data.
 
     logic [NPower-1:0] mul_ax_ay_q, mul_bx_by_q;
-    prim_flop_en #(
+    caliptra_prim_flop_en #(
       .Width      ( 2*NPower ),
       .ResetValue ( '0       )
-    ) u_prim_flop_mul_abx_aby (
+    ) u_caliptra_prim_flop_mul_abx_aby (
       .clk_i  ( clk_i                      ),
       .rst_ni ( rst_ni                     ),
       .en_i   ( we_i                       ),
@@ -159,9 +159,9 @@ module aes_dom_indep_mul_gf2pn #(
 
     // Avoid aggressive synthesis optimizations.
     logic [NPower-1:0] mul_ax_ay_buf, mul_bx_by_buf;
-    prim_buf #(
+    caliptra_prim_buf #(
       .Width  ( 2*NPower )
-    ) u_prim_buf_mul_abx_aby (
+    ) u_caliptra_prim_buf_mul_abx_aby (
       .in_i  ( {mul_ax_ay_d,   mul_bx_by_d}   ),
       .out_o ( {mul_ax_ay_buf, mul_bx_by_buf} )
     );
@@ -217,10 +217,10 @@ module aes_dom_dep_mul_gf2pn_unopt #(
   assign b_yz_d = b_y ^ b_z;
 
   // Registers
-  prim_flop_en #(
+  caliptra_prim_flop_en #(
     .Width      ( 2*NPower ),
     .ResetValue ( '0       )
-  ) u_prim_flop_ab_yz (
+  ) u_caliptra_prim_flop_ab_yz (
     .clk_i  ( clk_i            ),
     .rst_ni ( rst_ni           ),
     .en_i   ( we_i             ),
@@ -259,10 +259,10 @@ module aes_dom_dep_mul_gf2pn_unopt #(
     // different clock cycles.
 
     logic [NPower-1:0] a_x_q, b_x_q;
-    prim_flop_en #(
+    caliptra_prim_flop_en #(
       .Width      ( 2*NPower ),
       .ResetValue ( '0       )
-    ) u_prim_flop_ab_x (
+    ) u_caliptra_prim_flop_ab_x (
       .clk_i  ( clk_i          ),
       .rst_ni ( rst_ni         ),
       .en_i   ( we_i           ),
@@ -357,10 +357,10 @@ module aes_dom_dep_mul_gf2pn #(
   assign b_yz0_d = b_y ^ z_0;
 
   // Registers
-  prim_flop_en #(
+  caliptra_prim_flop_en #(
     .Width      ( 2*NPower ),
     .ResetValue ( '0       )
-  ) u_prim_flop_ab_yz0 (
+  ) u_caliptra_prim_flop_ab_yz0 (
     .clk_i  ( clk_i              ),
     .rst_ni ( rst_ni             ),
     .en_i   ( we_i               ),
@@ -389,9 +389,9 @@ module aes_dom_dep_mul_gf2pn #(
 
   // Avoid aggressive synthesis optimizations.
   logic [NPower-1:0] mul_ax_z0_buf, mul_bx_z0_buf;
-  prim_buf #(
+  caliptra_prim_buf #(
     .Width ( 2*NPower )
-  ) u_prim_buf_mul_abx_z0 (
+  ) u_caliptra_prim_buf_mul_abx_z0 (
     .in_i  ( {mul_ax_z0,     mul_bx_z0}     ),
     .out_o ( {mul_ax_z0_buf, mul_bx_z0_buf} )
   );
@@ -403,10 +403,10 @@ module aes_dom_dep_mul_gf2pn #(
   assign bxz0_z1_d = mul_bx_z0_buf ^ z_1;
 
   // Registers
-  prim_flop_en #(
+  caliptra_prim_flop_en #(
     .Width      ( 2*NPower ),
     .ResetValue ( '0       )
-  ) u_prim_flop_abxz0_z1 (
+  ) u_caliptra_prim_flop_abxz0_z1 (
     .clk_i  ( clk_i                  ),
     .rst_ni ( rst_ni                 ),
     .en_i   ( we_i                   ),
@@ -493,10 +493,10 @@ module aes_dom_dep_mul_gf2pn #(
     end
 
     // Registers
-    prim_flop_en #(
+    caliptra_prim_flop_en #(
       .Width      ( 2*NPower ),
       .ResetValue ( '0       )
-    ) u_prim_flop_mul_abx_aby (
+    ) u_caliptra_prim_flop_mul_abx_aby (
       .clk_i  ( clk_i                      ),
       .rst_ni ( rst_ni                     ),
       .en_i   ( we_i                       ),
@@ -518,9 +518,9 @@ module aes_dom_dep_mul_gf2pn #(
 
     // Avoid aggressive synthesis optimizations.
     logic [NPower-1:0] mul_ax_byz0_buf, mul_bx_ayz0_buf;
-    prim_buf #(
+    caliptra_prim_buf #(
       .Width ( 2*NPower )
-    ) u_prim_buf_mul_abx_bayz0 (
+    ) u_caliptra_prim_buf_mul_abx_bayz0 (
       .in_i  ( {mul_ax_byz0,     mul_bx_ayz0}     ),
       .out_o ( {mul_ax_byz0_buf, mul_bx_ayz0_buf} )
     );
@@ -541,9 +541,9 @@ module aes_dom_dep_mul_gf2pn #(
 
     // Avoid aggressive synthesis optimizations.
     logic [NPower-1:0] a_b_buf, b_b_buf;
-    prim_buf #(
+    caliptra_prim_buf #(
       .Width ( 2*NPower )
-    ) u_prim_buf_ab_b (
+    ) u_caliptra_prim_buf_ab_b (
       .in_i  ( {a_b,     b_b}     ),
       .out_o ( {a_b_buf, b_b_buf} )
     );
@@ -560,9 +560,9 @@ module aes_dom_dep_mul_gf2pn #(
 
     // Avoid aggressive synthesis optimizations.
     logic [NPower-1:0] a_mul_ax_b_buf, b_mul_bx_b_buf;
-    prim_buf #(
+    caliptra_prim_buf #(
       .Width ( 2*NPower )
-    ) u_prim_buf_ab_mul_abx_b (
+    ) u_caliptra_prim_buf_ab_mul_abx_b (
       .in_i  ( {a_mul_ax_b,     b_mul_bx_b}     ),
       .out_o ( {a_mul_ax_b_buf, b_mul_bx_b_buf} )
     );
@@ -612,10 +612,10 @@ module aes_dom_inverse_gf2p4 #(
   logic [1:0] a_gamma_ss_q, b_gamma_ss_q;
   assign a_gamma_ss_d = aes_scale_omega2_gf2p2(aes_square_gf2p2(a_gamma1 ^ a_gamma0));
   assign b_gamma_ss_d = aes_scale_omega2_gf2p2(aes_square_gf2p2(b_gamma1 ^ b_gamma0));
-  prim_flop_en #(
+  caliptra_prim_flop_en #(
     .Width      ( 4  ),
     .ResetValue ( '0 )
-  ) u_prim_flop_ab_gamma_ss (
+  ) u_caliptra_prim_flop_ab_gamma_ss (
     .clk_i  ( clk_i                        ),
     .rst_ni ( rst_ni                       ),
     .en_i   ( we_i[0]                      ),
@@ -624,10 +624,10 @@ module aes_dom_inverse_gf2p4 #(
   );
 
   logic [1:0] a_gamma1_q, a_gamma0_q, b_gamma1_q, b_gamma0_q;
-  prim_flop_en #(
+  caliptra_prim_flop_en #(
     .Width      ( 8  ),
     .ResetValue ( '0 )
-  ) u_prim_flop_ab_gamma10 (
+  ) u_caliptra_prim_flop_ab_gamma10 (
     .clk_i  ( clk_i                                            ),
     .rst_ni ( rst_ni                                           ),
     .en_i   ( we_i[0]                                          ),
@@ -684,23 +684,23 @@ module aes_dom_inverse_gf2p4 #(
 
   // Avoid aggressive synthesis optimizations.
   logic [1:0] a_omega_buf, b_omega_buf;
-  prim_buf #(
+  caliptra_prim_buf #(
     .Width ( 4 )
-  ) u_prim_buf_ab_omega (
+  ) u_caliptra_prim_buf_ab_omega (
     .in_i  ( {a_omega,     b_omega}     ),
     .out_o ( {a_omega_buf, b_omega_buf} )
   );
 
   // Pipeline registers
   logic [1:0] a_gamma1_qq, a_gamma0_qq, b_gamma1_qq, b_gamma0_qq, a_omega_buf_q, b_omega_buf_q;
-  if (PipelineMul == 1'b1) begin: gen_prim_flop_omega_gamma10
+  if (PipelineMul == 1'b1) begin: gen_caliptra_prim_flop_omega_gamma10
     // We instantiate the input pipeline registers for the DOM-dep multiplier outside of the
     // multiplier to enable sharing of pipeline registers where applicable.
 
-    prim_flop_en #(
+    caliptra_prim_flop_en #(
       .Width      ( 8  ),
       .ResetValue ( '0 )
-    ) u_prim_flop_ab_gamma10_q (
+    ) u_caliptra_prim_flop_ab_gamma10_q (
       .clk_i  ( clk_i                                                ),
       .rst_ni ( rst_ni                                               ),
       .en_i   ( we_i[1]                                              ),
@@ -709,10 +709,10 @@ module aes_dom_inverse_gf2p4 #(
     );
 
     // These inputs are used by both DOM-dep multipliers below.
-    prim_flop_en #(
+    caliptra_prim_flop_en #(
       .Width      ( 4  ),
       .ResetValue ( '0 )
-    ) u_prim_flop_ab_omega_buf (
+    ) u_caliptra_prim_flop_ab_omega_buf (
       .clk_i  ( clk_i                          ),
       .rst_ni ( rst_ni                         ),
       .en_i   ( we_i[1]                        ),
@@ -720,7 +720,7 @@ module aes_dom_inverse_gf2p4 #(
       .q_o    ( {a_omega_buf_q, b_omega_buf_q} )
     );
 
-  end else begin : gen_no_prim_flop_ab_y10
+  end else begin : gen_no_caliptra_prim_flop_ab_y10
     // When using un-pipelined multipliers, there is no need to insert additional registers.
     // We drive the corresponding inputs to 0 to make sure the functionality isn't correct in case
     // the pipeliend inputs are erroneously used.
@@ -823,10 +823,10 @@ module aes_dom_inverse_gf2p8 #(
   logic [3:0] a_y_ss_q, b_y_ss_q;
   assign a_y_ss_d = aes_square_scale_gf2p4_gf2p2(a_y1 ^ a_y0);
   assign b_y_ss_d = aes_square_scale_gf2p4_gf2p2(b_y1 ^ b_y0);
-  prim_flop_en #(
+  caliptra_prim_flop_en #(
     .Width      ( 8  ),
     .ResetValue ( '0 )
-  ) u_prim_flop_ab_y_ss (
+  ) u_caliptra_prim_flop_ab_y_ss (
     .clk_i  ( clk_i                ),
     .rst_ni ( rst_ni               ),
     .en_i   ( we_i[0]              ),
@@ -835,14 +835,14 @@ module aes_dom_inverse_gf2p8 #(
   );
 
   logic [3:0] a_y1_q, a_y0_q, b_y1_q, b_y0_q;
-  if (PipelineMul == 1'b1) begin: gen_prim_flop_ab_y10
+  if (PipelineMul == 1'b1) begin: gen_caliptra_prim_flop_ab_y10
     // We instantiate the input pipeline registers for the DOM-dep multiplier outside of the
     // multiplier to enable sharing of pipeline registers where applicable.
 
-    prim_flop_en #(
+    caliptra_prim_flop_en #(
       .Width      ( 16  ),
       .ResetValue ( '0  )
-    ) u_prim_flop_ab_y10 (
+    ) u_caliptra_prim_flop_ab_y10 (
       .clk_i  ( clk_i                            ),
       .rst_ni ( rst_ni                           ),
       .en_i   ( we_i[0]                          ),
@@ -850,7 +850,7 @@ module aes_dom_inverse_gf2p8 #(
       .q_o    ( {a_y1_q, a_y0_q, b_y1_q, b_y0_q} )
     );
 
-  end else begin : gen_no_prim_flop_ab_y10
+  end else begin : gen_no_caliptra_prim_flop_ab_y10
     // When using un-pipelined multipliers, there is no need to insert additional registers.
     // We drive the corresponding inputs to 0 to make sure the functionality isn't correct in case
     // the pipeliend inputs are erroneously used.
@@ -891,9 +891,9 @@ module aes_dom_inverse_gf2p8 #(
 
   // Avoid aggressive synthesis optimizations.
   logic [3:0] a_gamma_buf, b_gamma_buf;
-  prim_buf #(
+  caliptra_prim_buf #(
     .Width ( 8 )
-  ) u_prim_buf_ab_gamma (
+  ) u_caliptra_prim_buf_ab_gamma (
     .in_i  ( {a_gamma,     b_gamma}     ),
     .out_o ( {a_gamma_buf, b_gamma_buf} )
   );
@@ -935,10 +935,10 @@ module aes_dom_inverse_gf2p8 #(
   // Formulas 18 and 19 in [2].
 
   logic [3:0] a_y1_qqq, a_y0_qqq, b_y1_qqq, b_y0_qqq;
-  prim_flop_en #(
+  caliptra_prim_flop_en #(
     .Width      ( 16 ),
     .ResetValue ( '0 )
-  ) u_prim_flop_ab_y10_qqq (
+  ) u_caliptra_prim_flop_ab_y10_qqq (
     .clk_i  ( clk_i                                    ),
     .rst_ni ( rst_ni                                   ),
     .en_i   ( we_i[2]                                  ),
@@ -1070,10 +1070,10 @@ module aes_sbox_dom
   // Buffer and forward PRD for the individual stages. We get 8 bits from the PRNG for usage in the
   // first cycle. Stages 2, 3 and 4 are driven by other S-Box instances.
   assign prd1_d = we[0] ? prd_i[7:0] : prd1_q;
-  prim_flop #(
+  caliptra_prim_flop #(
     .Width      ( 8  ),
     .ResetValue ( '0 )
-  ) u_prim_flop_prd1_q (
+  ) u_caliptra_prim_flop_prd1_q (
     .clk_i  ( clk_i  ),
     .rst_ni ( rst_ni ),
     .d_i    ( prd1_d ),
diff --git a/src/aes/rtl/aes_sel_buf_chk.sv b/src/aes/rtl/aes_sel_buf_chk.sv
index 5bee783b2..b6cb03cfd 100644
--- a/src/aes/rtl/aes_sel_buf_chk.sv
+++ b/src/aes/rtl/aes_sel_buf_chk.sv
@@ -9,7 +9,7 @@
 // 2. to check that the selector signal is valid, i.e., doesn't take on invalid values.
 // Whenever the selector signal takes on an invalid value, an error is signaled.
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
 module aes_sel_buf_chk #(
   parameter int Num      = 2,
@@ -36,16 +36,16 @@ module aes_sel_buf_chk #(
   ////////////
 
   if (EnSecBuf) begin : gen_sec_buf
-    prim_sec_anchor_buf #(
+    caliptra_prim_sec_anchor_buf #(
       .Width ( Width )
-    ) u_prim_buf_sel_i (
+    ) u_caliptra_prim_buf_sel_i (
       .in_i  ( sel_i ),
       .out_o ( sel_o )
     );
   end else begin : gen_buf
-    prim_buf  #(
+    caliptra_prim_buf  #(
       .Width ( Width )
-    ) u_prim_buf_sel_i (
+    ) u_caliptra_prim_buf_sel_i (
       .in_i  ( sel_i ),
       .out_o ( sel_o )
     );
diff --git a/src/ahb_lite_bus/config/ahb_lite_bus.vf b/src/ahb_lite_bus/config/ahb_lite_bus.vf
index 27ca1516c..86fbbb2e2 100644
--- a/src/ahb_lite_bus/config/ahb_lite_bus.vf
+++ b/src/ahb_lite_bus/config/ahb_lite_bus.vf
@@ -1,4 +1,19 @@
++incdir+${CALIPTRA_ROOT}/src/integration/rtl
++incdir+${CALIPTRA_ROOT}/src/libs/rtl
 +incdir+${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl
+${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh
+${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sva.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_macros.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sram.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_defines_pkg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_ahb_srom.sv
+${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
 ${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_lite_bus_inf.sv
 ${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_lite_address_decoder.sv
 ${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_lite_bus.sv
diff --git a/src/ahb_lite_bus/config/ahb_node_wrap.vf b/src/ahb_lite_bus/config/ahb_node_wrap.vf
deleted file mode 100644
index fb670ea20..000000000
--- a/src/ahb_lite_bus/config/ahb_node_wrap.vf
+++ /dev/null
@@ -1,4 +0,0 @@
-+incdir+${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl
-${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_bus.sv
-${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_node.sv
-${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_node_wrap.sv
diff --git a/src/ahb_lite_bus/config/compile.yml b/src/ahb_lite_bus/config/compile.yml
index 38bba9e49..2529a1177 100755
--- a/src/ahb_lite_bus/config/compile.yml
+++ b/src/ahb_lite_bus/config/compile.yml
@@ -1,5 +1,7 @@
 ---
 provides: [ahb_lite_bus]
+requires:
+  - libs
 schema_version: 2.4.0
 targets:
   rtl:
diff --git a/src/ahb_lite_bus/rtl/ahb_lite_2to1_mux.sv b/src/ahb_lite_bus/rtl/ahb_lite_2to1_mux.sv
index 5d5641522..017539252 100644
--- a/src/ahb_lite_bus/rtl/ahb_lite_2to1_mux.sv
+++ b/src/ahb_lite_bus/rtl/ahb_lite_2to1_mux.sv
@@ -21,13 +21,15 @@
 
 module ahb_lite_2to1_mux #(
     parameter AHB_LITE_ADDR_WIDTH   = 32,
-    parameter AHB_LITE_DATA_WIDTH   = 32
+    parameter AHB_LITE_DATA_WIDTH   = 32,
+    parameter AHB_NO_OPT = 0
 ) (
     // ---------------------------------------
     // Global clock/reset
     // ---------------------------------------
     input logic     hclk,
     input logic     hreset_n,
+    input logic     force_bus_idle,
 
     // ---------------------------------------
     // From Initiator 0
@@ -80,7 +82,9 @@ module ahb_lite_2to1_mux #(
 //Initiator 0 always takes priority
 
 logic initiator0_address_ph, initiator1_address_ph;
+logic initiator0_data_ph_nq, initiator1_data_ph_nq;
 logic initiator0_data_ph, initiator1_data_ph;
+logic initiator0_pend_addr_ph_nq, initiator1_pend_addr_ph_nq;
 logic initiator0_pend_addr_ph, initiator1_pend_addr_ph;
 logic initiator0_gnt, initiator1_gnt;
 logic [AHB_LITE_ADDR_WIDTH-1:0] initiator0_pend_haddr, initiator1_pend_haddr;
@@ -93,8 +97,8 @@ logic initiator0_pend_hwrite, initiator1_pend_hwrite;
 logic initiator0_hwrite, initiator1_hwrite;
 
 //Detect address phase
-always_comb initiator0_address_ph = hsel_i_0 & hready_i_0 & htrans_i_0 inside {2'b10, 2'b11};
-always_comb initiator1_address_ph = hsel_i_1 & hready_i_1 & htrans_i_1 inside {2'b10, 2'b11};
+always_comb initiator0_address_ph = hsel_i_0 & hready_i_0 & htrans_i_0 inside {2'b10, 2'b11} & ~force_bus_idle;
+always_comb initiator1_address_ph = hsel_i_1 & hready_i_1 & htrans_i_1 inside {2'b10, 2'b11} & ~force_bus_idle;
 
 always_ff @(posedge hclk or negedge hreset_n) begin
     if (~hreset_n) begin
@@ -106,10 +110,10 @@ always_ff @(posedge hclk or negedge hreset_n) begin
         initiator1_pend_hsize <= '0;
         initiator0_pend_hwrite <= '0;
         initiator1_pend_hwrite <= '0;
-        initiator0_pend_addr_ph <= '0;
-        initiator1_pend_addr_ph <= '0;
-        initiator0_data_ph <= '0;
-        initiator1_data_ph <= '0;
+        initiator0_pend_addr_ph_nq <= '0;
+        initiator1_pend_addr_ph_nq <= '0;
+        initiator0_data_ph_nq <= '0;
+        initiator1_data_ph_nq <= '0;
     end
     else begin
         //Capture the address during the address phase for each initiator
@@ -123,15 +127,20 @@ always_ff @(posedge hclk or negedge hreset_n) begin
         initiator1_pend_hwrite <= initiator1_address_ph & ~initiator1_pend_addr_ph ? hwrite_i_1 : initiator1_pend_hwrite;
 
         //Capture pending address phase when initiators collide
-        initiator0_pend_addr_ph <= (initiator0_address_ph | initiator0_pend_addr_ph) & ~initiator0_gnt;
-        initiator1_pend_addr_ph <= (initiator1_address_ph | initiator1_pend_addr_ph) & ~initiator1_gnt; 
+        initiator0_pend_addr_ph_nq <= (initiator0_address_ph | initiator0_pend_addr_ph) & ~(hreadyout_i & initiator0_gnt);
+        initiator1_pend_addr_ph_nq <= (initiator1_address_ph | initiator1_pend_addr_ph) & ~(hreadyout_i & initiator1_gnt); 
 
         //Transition to data phase when endpoint accepts address phase, hold when not ready
-        initiator0_data_ph <= (initiator0_gnt) | (initiator0_data_ph & ~hreadyout_i);
-        initiator1_data_ph <= (initiator1_gnt) | (initiator1_data_ph & ~hreadyout_i);
+        initiator0_data_ph_nq <= (initiator0_gnt) | (initiator0_data_ph & ~hreadyout_i);
+        initiator1_data_ph_nq <= (initiator1_gnt) | (initiator1_data_ph & ~hreadyout_i);
     end
 end
 
+always_comb initiator0_data_ph = initiator0_data_ph_nq & ~force_bus_idle;
+always_comb initiator1_data_ph = initiator1_data_ph_nq & ~force_bus_idle;
+always_comb initiator0_pend_addr_ph = initiator0_pend_addr_ph_nq & ~force_bus_idle;
+always_comb initiator1_pend_addr_ph = initiator1_pend_addr_ph_nq & ~force_bus_idle;
+
 always_comb initiator0_haddr = initiator0_pend_addr_ph ? initiator0_pend_haddr : haddr_i_0;
 always_comb initiator0_htrans = initiator0_pend_addr_ph ? initiator0_pend_htrans : htrans_i_0;
 always_comb initiator0_hsize = initiator0_pend_addr_ph ? initiator0_pend_hsize : hsize_i_0;
@@ -143,12 +152,29 @@ always_comb initiator1_hsize = initiator1_pend_addr_ph ? initiator1_pend_hsize :
 always_comb initiator1_hwrite = initiator1_pend_addr_ph ? initiator1_pend_hwrite : hwrite_i_1;
 
 //Select the appropriate initiator
-//Initiator 0 gets priority
-//Stall the grant if initiator 1 is processing a data phase and address phase b2b
-always_comb initiator0_gnt = (initiator0_address_ph | initiator0_pend_addr_ph) & hreadyout_i;
-
-//Initiator 1 gets through only if initiator 0 isn't getting granted
-always_comb initiator1_gnt = (initiator1_address_ph | initiator1_pend_addr_ph) & hreadyout_i & ~initiator0_gnt;
+generate
+    if (AHB_NO_OPT) begin
+        //no optimization, data phase must complete before driving new address phase
+        //Initiator 0 gets priority
+        //Stall the grant only if initiator 1 is on its data phase
+        always_comb initiator0_gnt = (initiator0_address_ph | initiator0_pend_addr_ph) & ~initiator1_data_ph;
+
+        //Initiator 1 gets through only if initiator 0 address phase isn't getting gnt, or in data phase
+        always_comb initiator1_gnt = (initiator1_address_ph | initiator1_pend_addr_ph) & ~initiator0_data_ph & ~initiator0_gnt;
+    end else begin
+        //optimized to allow addr phase to overlap data phase, assumes no stalls
+        //Initiator 0 gets priority
+        //Stall the grant if initiator 1 is processing a data phase and address phase b2b
+        always_comb initiator0_gnt = (initiator0_address_ph | initiator0_pend_addr_ph);
+
+        //Initiator 1 gets through only if initiator 0 isn't getting granted
+        always_comb initiator1_gnt = (initiator1_address_ph | initiator1_pend_addr_ph) & ~initiator0_gnt;
+
+        //optimized path doesn't look at stall
+        //only time this stalls is on error condition
+        `CALIPTRA_ASSERT_NEVER(ERR_2TO1MUX_STALL, ~hreadyout_i & (hresp_i == 1'b0), hclk, hreset_n)
+    end
+endgenerate
 
 //Mux the appropriate initiator and send out
 //Keep driving initiator 1 controls on data phase if init0 isn't getting a grant in that cycle
@@ -165,14 +191,52 @@ always_comb hready_o = initiator1_gnt | (initiator1_data_ph & ~initiator0_gnt) ?
 //Send the data coming from responder when selected
 always_comb hresp_o_0  = initiator0_data_ph ? hresp_i : '0;
 always_comb hrdata_o_0 = initiator0_data_ph ? hrdata_i : '0;
-always_comb hready_o_0 = initiator0_pend_addr_ph ? '0 : 
-                         initiator0_data_ph ? hreadyout_i : '1;
+always_comb hready_o_0 = initiator0_data_ph ? hreadyout_i :
+                         initiator0_pend_addr_ph ? '0 : '1;
 
 always_comb hresp_o_1  = initiator1_data_ph? hresp_i: '0;
 always_comb hrdata_o_1 = initiator1_data_ph ? hrdata_i: '0;
-always_comb hready_o_1 = initiator1_pend_addr_ph ? '0 : 
-                         initiator1_data_ph ? hreadyout_i : '1;
+always_comb hready_o_1 = initiator1_data_ph ? hreadyout_i :
+                         initiator1_pend_addr_ph ? '0 :  '1;
 
 `CALIPTRA_ASSERT_MUTEX(ERR_2TO1MUX_MUTEX_DATA_PH, {initiator0_data_ph,initiator1_data_ph}, hclk, hreset_n)
 `CALIPTRA_ASSERT_NEVER(ERR_2TO1MUX_BAD_HTRANS, (htrans_o == 2'b01), hclk, hreset_n)
+
+//Coverage
+`ifndef VERILATOR
+`ifdef FCOV
+
+covergroup ahb_lite_2to1_mux_cov_grp @(posedge hclk iff hreset_n);
+    option.per_instance = 1;
+    
+    init0_addr_cp: coverpoint initiator0_address_ph;
+    init0_pend_addr_cp: coverpoint initiator0_pend_addr_ph;
+    init0_data_cp: coverpoint initiator0_data_ph;
+    init0_gnt_cp : coverpoint initiator0_gnt;
+
+    init1_addr_cp: coverpoint initiator1_address_ph;
+    init1_pend_addr_cp: coverpoint initiator1_pend_addr_ph;
+    init1_data_cp: coverpoint initiator1_data_ph;
+    init1_gnt_cp : coverpoint initiator1_gnt;
+
+    init0_pend_addr_not_ready: coverpoint initiator0_pend_addr_ph & ~hreadyout_i;
+    init1_pend_addr_not_ready: coverpoint initiator1_pend_addr_ph & ~hreadyout_i;
+
+    init0_data_not_ready: coverpoint initiator0_data_ph & ~hreadyout_i;
+    init1_data_not_ready: coverpoint initiator1_data_ph & ~hreadyout_i;
+
+    init0_dataXinit1_gnt: cross  init0_data_cp, init1_gnt_cp;
+    init1_dataXinit0_gnt: cross  init1_data_cp, init0_gnt_cp;
+
+    init0_addrXpend: cross init0_addr_cp, init0_pend_addr_cp;
+    init1_addrXpend: cross init1_addr_cp, init1_pend_addr_cp;
+    init0Xinit1_addr: cross init0_addr_cp, init1_addr_cp;
+    init0Xinit1_pend_addr: cross init0_pend_addr_cp, init1_pend_addr_cp;
+
+endgroup
+
+    ahb_lite_2to1_mux_cov_grp ahb_lite_2to1_mux_cov_grp1 = new();
+
+`endif
+`endif              
 endmodule
diff --git a/src/ahb_lite_bus/rtl/ahb_lite_address_decoder.sv b/src/ahb_lite_bus/rtl/ahb_lite_address_decoder.sv
index 9b87d0fbd..918529300 100644
--- a/src/ahb_lite_bus/rtl/ahb_lite_address_decoder.sv
+++ b/src/ahb_lite_bus/rtl/ahb_lite_address_decoder.sv
@@ -27,7 +27,7 @@ module ahb_lite_address_decoder #(
     // ---------------------------------------
     input logic     hclk,
     input logic     hreset_n,
-
+    input logic     force_bus_idle,
     // ---------------------------------------
     // From Initiator Interface Port
     // ---------------------------------------
@@ -57,7 +57,7 @@ module ahb_lite_address_decoder #(
     output logic    [NUM_RESPONDERS-1:0][2:0]                       hsize_o,
 
     // ----------------------------------------------
-    // Respnder Disable
+    // Responder Disable
     // ----------------------------------------------
     input logic     [NUM_RESPONDERS-1:0]                            responder_disable_i,
     output logic    [NUM_RESPONDERS-1:0]                            access_blocked_o,
@@ -78,19 +78,23 @@ module ahb_lite_address_decoder #(
     logic [NUM_RESPONDERS-1:0]                          pending_hsel;
     logic                                               hinitiator_ready_default;
     logic                                               hinitiator_ready_int;
+    logic                                               hinitiator_ready_int_q;
     logic [NUM_RESPONDERS-1:0]                          hsel_o_int_pre;
     logic [NUM_RESPONDERS-1:0]                          hsel_blocked;
     logic [NUM_RESPONDERS-1:0]                          hsel_o_int;
     logic                                               hresp_error;
     logic                                               hresp_error_r;
 
+    logic [1:0]                                         htrans_q;
+
 
+    always_comb htrans_q = force_bus_idle ? AHB_XFER_IDLE : htrans_i;
 
     // Decode the address to appropriate Responder HSEL
     genvar resp_num;
     generate
         for (resp_num = 0; resp_num < NUM_RESPONDERS; resp_num++) begin: gen_responder_hsel
-            assign hsel_o_int_pre[resp_num] = (haddr_i >= responder_start_addr_i[resp_num]) && (haddr_i <= responder_end_addr_i[resp_num]);
+            assign hsel_o_int_pre[resp_num] = ~force_bus_idle && (haddr_i >= responder_start_addr_i[resp_num]) && (haddr_i <= responder_end_addr_i[resp_num]);
             assign hsel_blocked  [resp_num] = hsel_o_int_pre[resp_num] &&  responder_disable_i[resp_num];
             assign hsel_o_int    [resp_num] = hsel_o_int_pre[resp_num] && !responder_disable_i[resp_num];
         end
@@ -100,7 +104,7 @@ module ahb_lite_address_decoder #(
     always @(posedge hclk or negedge hreset_n) begin
         if (!hreset_n)
             access_blocked_o <= '0;
-        else if (|htrans_i && hinitiator_ready_int && |hsel_blocked)
+        else if (|htrans_q && hinitiator_ready_int_q && |hsel_blocked)
             access_blocked_o <= hsel_blocked;
         else
             access_blocked_o <= '0;
@@ -109,16 +113,16 @@ module ahb_lite_address_decoder #(
     always @(posedge hclk or negedge hreset_n) begin
         if (!hreset_n)
             pending_hsel    <= '0;
-        else if (|htrans_i && hinitiator_ready_int)
+        else if (|htrans_q && hinitiator_ready_int_q)
             pending_hsel    <= hsel_o_int;
-        else if (hinitiator_ready_int)
+        else if (hinitiator_ready_int_q)
             pending_hsel    <= '0;
     end
 
     always_comb begin
         // Only flag errors for NONSEQ or SEQ type transfers
         // (BUSY transfers require OKAY response)
-        hresp_error = htrans_i inside {AHB_XFER_NONSEQ, AHB_XFER_SEQ} && hinitiator_ready_int && ~|hsel_o_int;
+        hresp_error = htrans_q inside {AHB_XFER_NONSEQ, AHB_XFER_SEQ} && hinitiator_ready_int_q && ~|hsel_o_int;
     end
 
     always @(posedge hclk or negedge hreset_n) begin
@@ -133,18 +137,19 @@ module ahb_lite_address_decoder #(
             hresp_error_r <= 1'b0;
         else if (hresp_error)
             hresp_error_r <= 1'b1;
-        else if (hinitiator_ready_int)
+        else if (hinitiator_ready_int_q)
             hresp_error_r <= 1'b0;
         else
             hresp_error_r <= hresp_error_r;
     end
 
     // Drive the address phase of the AHB Lite Transaction
+    // For RDC force ready signal when we force the bus idle
     always_comb begin
         for (int rr = 0; rr < NUM_RESPONDERS; rr++) begin
-            hresponderready_o[rr]    = hinitiator_ready_int;
+            hresponderready_o[rr]    = hinitiator_ready_int_q;
             hwrite_o[rr]             = hwrite_i;
-            htrans_o[rr]             = htrans_i;
+            htrans_o[rr]             = htrans_q;
             hsize_o[rr]              = hsize_i;
             haddr_o[rr]              = haddr_i;
             hwdata_o[rr]             = hwdata_i;
@@ -171,9 +176,27 @@ module ahb_lite_address_decoder #(
                 hinitiator_ready_int    = hreadyout_i[rr];
             end
         end
+        hinitiator_ready_int_q = hinitiator_ready_int | force_bus_idle;
     end
 
     assign hsel_o               = hsel_o_int;
-    assign hinitiatorready_o    = hinitiator_ready_int;
+    assign hinitiatorready_o    = hinitiator_ready_int_q;
+
+//Coverage
+`ifndef VERILATOR
+`ifdef FCOV
+
+covergroup ahb_lite_address_decode_cov_grp @(posedge hclk iff hreset_n);
+    option.per_instance = 1;
+
+    access_blocked_cp: coverpoint |access_blocked_o {option.comment = "Received a transaction to a locked memory region";}
+    oob_access_cp: coverpoint |htrans_i && ~|hsel_o_int_pre {option.comment = "Received a transaction to an unmapped memory region";}
+    hresp_cp: coverpoint hresp_o {option.comment = "AHB Response - can be ERROR or OKAY";}
+endgroup
+
+    ahb_lite_address_decode_cov_grp ahb_lite_address_decode_cov_grp1 = new();
 
+`endif
+`endif  
+    
 endmodule
diff --git a/src/ahb_lite_bus/rtl/ahb_lite_bus.sv b/src/ahb_lite_bus/rtl/ahb_lite_bus.sv
index 0294c0d06..4cc2cc372 100644
--- a/src/ahb_lite_bus/rtl/ahb_lite_bus.sv
+++ b/src/ahb_lite_bus/rtl/ahb_lite_bus.sv
@@ -45,10 +45,15 @@ module ahb_lite_bus #(
     output logic [NUM_RESPONDERS-1:0]                         ahb_lite_resp_access_blocked_o,
 
     // ----------------------------------------------
-    // Respnder Address Map (Start and End addresses)
+    // Responder Address Map (Start and End addresses)
     // ----------------------------------------------
     input logic [NUM_RESPONDERS-1:0][AHB_LITE_ADDR_WIDTH-1:0] ahb_lite_start_addr_i,
-    input logic [NUM_RESPONDERS-1:0][AHB_LITE_ADDR_WIDTH-1:0] ahb_lite_end_addr_i
+    input logic [NUM_RESPONDERS-1:0][AHB_LITE_ADDR_WIDTH-1:0] ahb_lite_end_addr_i,
+
+    // ----------------------------------------------
+    // Force bus idle during uc reset to prevent RDC violations
+    // ----------------------------------------------
+    input logic force_bus_idle
 );
 
     logic   [NUM_RESPONDERS-1:0][AHB_LITE_ADDR_WIDTH-1:0]   haddr;
@@ -105,7 +110,7 @@ module ahb_lite_bus #(
         .hsize_i            (ahb_lite_initiator.hsize),
         // Outputs
         .hresp_o            (ahb_lite_initiator.hresp),
-        .hinitiatorready_o  (ahb_lite_initiator.hready),
+        .hinitiatorready_o  (ahb_lite_initiator.hreadyout),
         .hrdata_o           (ahb_lite_initiator.hrdata),
 
         // --------------------------------------
@@ -125,8 +130,10 @@ module ahb_lite_bus #(
         .htrans_o           (htrans),
         .hsize_o            (hsize),
 
+        .force_bus_idle     (force_bus_idle),
+
         // ----------------------------------------------
-        // Respnder Disable
+        // Responder Disable
         // ----------------------------------------------
         .responder_disable_i          (ahb_lite_resp_disable_i),
         .access_blocked_o             (ahb_lite_resp_access_blocked_o),
diff --git a/src/ahb_lite_bus/rtl/ahb_lite_bus_inf.sv b/src/ahb_lite_bus/rtl/ahb_lite_bus_inf.sv
index 74b00cb9c..d21c78be4 100644
--- a/src/ahb_lite_bus/rtl/ahb_lite_bus_inf.sv
+++ b/src/ahb_lite_bus/rtl/ahb_lite_bus_inf.sv
@@ -43,7 +43,7 @@ interface CALIPTRA_AHB_LITE_BUS_INF
 
     modport Initiator_Interface_Ports (
         input    haddr, hwdata, hwrite, hsize, htrans, // from AHB Initiator to AHB Responder
-        output   hresp, hrdata, hready                       // from AHB Responder to AHB Initiator
+        output   hresp, hrdata, hreadyout                    // from AHB Responder to AHB Initiator
     );
 
     // -------------------------------------------
diff --git a/src/caliptra_prim/config/caliptra_prim.vf b/src/caliptra_prim/config/caliptra_prim.vf
new file mode 100644
index 000000000..59740aec8
--- /dev/null
+++ b/src/caliptra_prim/config/caliptra_prim.vf
@@ -0,0 +1,62 @@
++incdir+${CALIPTRA_ROOT}/src/integration/rtl
++incdir+${CALIPTRA_ROOT}/src/libs/rtl
++incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl
++incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl
++incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl
+${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh
+${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sva.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_macros.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sram.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_defines_pkg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_ahb_srom.sv
+${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv
+${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv
+${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv
+${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_en.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cdc_rand_delay.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lfsr.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi4_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_diff_decode.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_slicer.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_count.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_dom_and_2share.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_reg_we_check.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_max_tree.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_arb.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_intr_hw.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_onehot_check.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi8_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync_cnt.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lc_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_receiver.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_sender.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv
diff --git a/src/caliptra_prim/config/caliptra_prim_pkg.vf b/src/caliptra_prim/config/caliptra_prim_pkg.vf
new file mode 100644
index 000000000..dfed9ddd5
--- /dev/null
+++ b/src/caliptra_prim/config/caliptra_prim_pkg.vf
@@ -0,0 +1,9 @@
++incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv
diff --git a/src/caliptra_prim/config/compile.yml b/src/caliptra_prim/config/compile.yml
new file mode 100644
index 000000000..70fac1887
--- /dev/null
+++ b/src/caliptra_prim/config/compile.yml
@@ -0,0 +1,74 @@
+---
+provides: [caliptra_prim_pkg]
+schema_version: 2.4.0
+targets:
+  rtl:
+    directories: [$COMPILE_ROOT/rtl]
+    files:
+      - $COMPILE_ROOT/rtl/caliptra_prim_util_pkg.sv
+      - $COMPILE_ROOT/rtl/caliptra_prim_alert_pkg.sv
+      - $COMPILE_ROOT/rtl/caliptra_prim_subreg_pkg.sv
+      - $COMPILE_ROOT/rtl/caliptra_prim_mubi_pkg.sv
+      - $COMPILE_ROOT/rtl/caliptra_prim_cipher_pkg.sv
+      - $COMPILE_ROOT/rtl/caliptra_prim_pkg.sv
+      - $COMPILE_ROOT/rtl/caliptra_prim_sparse_fsm_pkg.sv
+  tb:
+    directories: [$COMPILE_ROOT/rtl]
+    files:
+      - $COMPILE_ROOT/rtl/caliptra_prim_util_pkg.sv
+      - $COMPILE_ROOT/rtl/caliptra_prim_alert_pkg.sv
+      - $COMPILE_ROOT/rtl/caliptra_prim_subreg_pkg.sv
+      - $COMPILE_ROOT/rtl/caliptra_prim_mubi_pkg.sv
+      - $COMPILE_ROOT/rtl/caliptra_prim_cipher_pkg.sv
+      - $COMPILE_ROOT/rtl/caliptra_prim_pkg.sv
+      - $COMPILE_ROOT/rtl/caliptra_prim_sparse_fsm_pkg.sv
+---
+provides: [caliptra_prim]
+schema_version: 2.4.0
+requires:
+  - libs
+  - lc_ctrl_pkg
+  - caliptra_prim_pkg
+  - caliptra_prim_generic
+targets:
+  rtl:
+    directories: [$COMPILE_ROOT/rtl]
+    files:
+#      - $COMPILE_ROOT/rtl/caliptra_prim_flop_macros.sv
+      - $COMPILE_ROOT/rtl/caliptra_prim_flop_en.sv
+      - $COMPILE_ROOT/rtl/caliptra_prim_cdc_rand_delay.sv
+      - $COMPILE_ROOT/rtl/caliptra_prim_flop_2sync.sv
+      - $COMPILE_ROOT/rtl/caliptra_prim_lfsr.sv
+      - $COMPILE_ROOT/rtl/caliptra_prim_mubi4_sync.sv
+      - $COMPILE_ROOT/rtl/caliptra_prim_diff_decode.sv
+      - $COMPILE_ROOT/rtl/caliptra_prim_sec_anchor_buf.sv
+      - $COMPILE_ROOT/rtl/caliptra_prim_slicer.sv
+#      - $COMPILE_ROOT/rtl/caliptra_prim_assert_dummy_macros.svh
+      - $COMPILE_ROOT/rtl/caliptra_prim_count.sv
+#      - $COMPILE_ROOT/rtl/caliptra_prim_assert_yosys_macros.svh
+      - $COMPILE_ROOT/rtl/caliptra_prim_sparse_fsm_flop.sv
+      - $COMPILE_ROOT/rtl/caliptra_prim_dom_and_2share.sv
+      - $COMPILE_ROOT/rtl/caliptra_prim_sec_anchor_flop.sv
+      - $COMPILE_ROOT/rtl/caliptra_prim_reg_we_check.sv
+      - $COMPILE_ROOT/rtl/caliptra_prim_packer_fifo.sv
+      - $COMPILE_ROOT/rtl/caliptra_prim_max_tree.sv
+      - $COMPILE_ROOT/rtl/caliptra_prim_subreg_arb.sv
+      - $COMPILE_ROOT/rtl/caliptra_prim_subreg.sv
+      - $COMPILE_ROOT/rtl/caliptra_prim_intr_hw.sv
+      - $COMPILE_ROOT/rtl/caliptra_prim_onehot_check.sv
+      - $COMPILE_ROOT/rtl/caliptra_prim_mubi8_sync.sv
+      - $COMPILE_ROOT/rtl/caliptra_prim_fifo_sync_cnt.sv
+      - $COMPILE_ROOT/rtl/caliptra_prim_buf.sv
+      - $COMPILE_ROOT/rtl/caliptra_prim_lc_sync.sv
+      - $COMPILE_ROOT/rtl/caliptra_prim_alert_receiver.sv
+#      - $COMPILE_ROOT/rtl/caliptra_prim_assert_standard_macros.svh
+      - $COMPILE_ROOT/rtl/caliptra_prim_flop.sv
+      - $COMPILE_ROOT/rtl/caliptra_prim_alert_sender.sv
+      - $COMPILE_ROOT/rtl/caliptra_prim_fifo_sync.sv
+      - $COMPILE_ROOT/rtl/caliptra_prim_arbiter_ppc.sv
+#      - $COMPILE_ROOT/rtl/caliptra_prim_assert.sv
+#      - $COMPILE_ROOT/rtl/caliptra_prim_assert_sec_cm.svh
+      - $COMPILE_ROOT/rtl/caliptra_prim_sum_tree.sv
+      - $COMPILE_ROOT/rtl/caliptra_prim_subreg_ext.sv
+      - $COMPILE_ROOT/rtl/caliptra_prim_edge_detector.sv
+    tops: [caliptra_prim]
diff --git a/src/caliptra_prim/lint/caliptra_prim_arbiter.vlt b/src/caliptra_prim/lint/caliptra_prim_arbiter.vlt
new file mode 100644
index 000000000..414c503fa
--- /dev/null
+++ b/src/caliptra_prim/lint/caliptra_prim_arbiter.vlt
@@ -0,0 +1,45 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+`verilator_config
+
+// Tell the Verilator scheduler to split up these variables into
+// separate pieces when it's figuring out process scheduling. This
+// avoids spurious UNOPTFLAT warnings caused by the fact that the
+// arrays feed into themselves (with different bits for different
+// positions in the tree).
+split_var -module "caliptra_prim_arbiter_fixed" -var "data_tree"
+split_var -module "caliptra_prim_arbiter_fixed" -var "gnt_tree"
+split_var -module "caliptra_prim_arbiter_fixed" -var "idx_tree"
+split_var -module "caliptra_prim_arbiter_fixed" -var "req_tree"
+
+split_var -module "caliptra_prim_arbiter_tree" -var "req_tree"
+split_var -module "caliptra_prim_arbiter_tree" -var "prio_tree"
+split_var -module "caliptra_prim_arbiter_tree" -var "sel_tree"
+split_var -module "caliptra_prim_arbiter_tree" -var "mask_tree"
+split_var -module "caliptra_prim_arbiter_tree" -var "idx_tree"
+split_var -module "caliptra_prim_arbiter_tree" -var "data_tree"
+
+// Waive ALWCOMBORDER warnings about the tree variables. We've got
+// lines like "req_tree[Pa] = req_tree[C0] | req_tree[C1];" and it
+// seems that the ALWCOMBORDER warning isn't affected by the split_var
+// rules above.
+lint_off -rule ALWCOMBORDER -file "*/rtl/caliptra_prim_arbiter_fixed.sv" -match "*data_tree*"
+lint_off -rule ALWCOMBORDER -file "*/rtl/caliptra_prim_arbiter_fixed.sv" -match "*gnt_tree*"
+lint_off -rule ALWCOMBORDER -file "*/rtl/caliptra_prim_arbiter_fixed.sv" -match "*idx_tree*"
+lint_off -rule ALWCOMBORDER -file "*/rtl/caliptra_prim_arbiter_fixed.sv" -match "*req_tree*"
+
+lint_off -rule ALWCOMBORDER -file "*/rtl/caliptra_prim_arbiter_tree.sv" -match "*req_tree*"
+lint_off -rule ALWCOMBORDER -file "*/rtl/caliptra_prim_arbiter_tree.sv" -match "*prio_tree*"
+lint_off -rule ALWCOMBORDER -file "*/rtl/caliptra_prim_arbiter_tree.sv" -match "*sel_tree*"
+lint_off -rule ALWCOMBORDER -file "*/rtl/caliptra_prim_arbiter_tree.sv" -match "*mask_tree*"
+lint_off -rule ALWCOMBORDER -file "*/rtl/caliptra_prim_arbiter_tree.sv" -match "*idx_tree*"
+lint_off -rule ALWCOMBORDER -file "*/rtl/caliptra_prim_arbiter_tree.sv" -match "*data_tree*"
+
+lint_off -rule ALWCOMBORDER -file "*/rtl/caliptra_prim_arbiter_ppc.sv" -match "*ppc_out*"
+
+// Waive unused clk and reset signals: they're just used for
+// assertions (which Verilator doesn't see)
+lint_off -rule UNUSED -file "*/rtl/caliptra_prim_arbiter_fixed.sv" -match "*clk_i*"
+lint_off -rule UNUSED -file "*/rtl/caliptra_prim_arbiter_fixed.sv" -match "*rst_ni*"
diff --git a/src/caliptra_prim/lint/caliptra_prim_arbiter.waiver b/src/caliptra_prim/lint/caliptra_prim_arbiter.waiver
new file mode 100644
index 000000000..038288027
--- /dev/null
+++ b/src/caliptra_prim/lint/caliptra_prim_arbiter.waiver
@@ -0,0 +1,13 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# waiver file for caliptra_prim_arbiter
+
+waive -rules PARTIAL_CONST_ASSIGN -location {caliptra_prim_arbiter_*.sv} -regexp {'mask.0.' is conditionally assigned a constant} \
+      -comment "makes the code more readable"
+waive -rules CONST_FF -location {caliptra_prim_arbiter_*.sv} -regexp {Flip-flop 'mask.0.' is driven by constant} \
+      -comment "makes the code more readable"
+
+waive -rules {HIER_BRANCH_NOT_READ INPUT_NOT_READ} -location {caliptra_prim_arbiter_fixed.sv} -regexp {.*'(clk_i|rst_ni)' is not read from in module 'caliptra_prim_arbiter_fixed'.*} \
+      -comment "clk_ and rst_ni are only used for assertions in this module."
diff --git a/src/prim/lint/prim_max_tree.vlt b/src/caliptra_prim/lint/caliptra_prim_max_tree.vlt
similarity index 58%
rename from src/prim/lint/prim_max_tree.vlt
rename to src/caliptra_prim/lint/caliptra_prim_max_tree.vlt
index fe2485c89..c26d4121b 100644
--- a/src/prim/lint/prim_max_tree.vlt
+++ b/src/caliptra_prim/lint/caliptra_prim_max_tree.vlt
@@ -9,10 +9,10 @@
 // avoids spurious UNOPTFLAT warnings caused by the fact that the
 // arrays feed into themselves (with different bits for different
 // positions in the tree).
-split_var -module "prim_max_tree" -var "max_tree"
-split_var -module "prim_max_tree" -var "vld_tree"
-split_var -module "prim_max_tree" -var "idx_tree"
+split_var -module "caliptra_prim_max_tree" -var "max_tree"
+split_var -module "caliptra_prim_max_tree" -var "vld_tree"
+split_var -module "caliptra_prim_max_tree" -var "idx_tree"
 
 // The clock and reset are only used for assertions in this module.
-lint_off -rule UNUSED -file "*/rtl/prim_max_tree.sv" -match "Signal is not used: 'clk_i'"
-lint_off -rule UNUSED -file "*/rtl/prim_max_tree.sv" -match "Signal is not used: 'rst_ni'"
+lint_off -rule UNUSED -file "*/rtl/caliptra_prim_max_tree.sv" -match "Signal is not used: 'clk_i'"
+lint_off -rule UNUSED -file "*/rtl/caliptra_prim_max_tree.sv" -match "Signal is not used: 'rst_ni'"
diff --git a/src/prim/lint/prim_sum_tree.waiver b/src/caliptra_prim/lint/caliptra_prim_max_tree.waiver
similarity index 51%
rename from src/prim/lint/prim_sum_tree.waiver
rename to src/caliptra_prim/lint/caliptra_prim_max_tree.waiver
index 7f2fa7c93..64e911834 100644
--- a/src/prim/lint/prim_sum_tree.waiver
+++ b/src/caliptra_prim/lint/caliptra_prim_max_tree.waiver
@@ -2,7 +2,7 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
-# waiver file for prim_arbiter
+# waiver file for caliptra_prim_arbiter
 
-waive -rules {HIER_BRANCH_NOT_READ INPUT_NOT_READ} -location {prim_sum_tree.sv} -regexp {.*'(clk_i|rst_ni)' is not read from in module 'prim_sum_tree'.*} \
+waive -rules {HIER_BRANCH_NOT_READ INPUT_NOT_READ} -location {caliptra_prim_max_tree.sv} -regexp {.*'(clk_i|rst_ni)' is not read from in module 'caliptra_prim_max_tree'.*} \
       -comment "clk_ and rst_ni are only used for assertions in this module."
diff --git a/src/prim/lint/prim_onehot_check.vlt b/src/caliptra_prim/lint/caliptra_prim_onehot_check.vlt
similarity index 57%
rename from src/prim/lint/prim_onehot_check.vlt
rename to src/caliptra_prim/lint/caliptra_prim_onehot_check.vlt
index d7d927bae..26796713c 100644
--- a/src/prim/lint/prim_onehot_check.vlt
+++ b/src/caliptra_prim/lint/caliptra_prim_onehot_check.vlt
@@ -9,14 +9,14 @@
 // avoids spurious UNOPTFLAT warnings caused by the fact that the
 // arrays feed into themselves (with different bits for different
 // positions in the tree).
-split_var -module "prim_onehot_check" -var "or_tree"
-split_var -module "prim_onehot_check" -var "and_tree"
-split_var -module "prim_onehot_check" -var "err_tree"
+split_var -module "caliptra_prim_onehot_check" -var "or_tree"
+split_var -module "caliptra_prim_onehot_check" -var "and_tree"
+split_var -module "caliptra_prim_onehot_check" -var "err_tree"
 
 // The clock and reset are only used for assertions in this module.
-lint_off -rule UNUSED -file "*/rtl/prim_onehot_check.sv" -match "Signal is not used: 'clk_i'"
-lint_off -rule UNUSED -file "*/rtl/prim_onehot_check.sv" -match "Signal is not used: 'rst_ni'"
+lint_off -rule UNUSED -file "*/rtl/caliptra_prim_onehot_check.sv" -match "Signal is not used: 'clk_i'"
+lint_off -rule UNUSED -file "*/rtl/caliptra_prim_onehot_check.sv" -match "Signal is not used: 'rst_ni'"
 
 // The EnableAlertTriggerSVA parameter is only used by modules bound
 // in for DV testing. Waive the warning that we don't read it.
-lint_off -rule UNUSED -file "*/rtl/prim_onehot_check.sv" -match "*EnableAlertTriggerSVA*"
+lint_off -rule UNUSED -file "*/rtl/caliptra_prim_onehot_check.sv" -match "*EnableAlertTriggerSVA*"
diff --git a/src/caliptra_prim/lint/caliptra_prim_onehot_check.waiver b/src/caliptra_prim/lint/caliptra_prim_onehot_check.waiver
new file mode 100644
index 000000000..15ca76824
--- /dev/null
+++ b/src/caliptra_prim/lint/caliptra_prim_onehot_check.waiver
@@ -0,0 +1,11 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# waiver file for caliptra_prim_onehot_check
+
+waive -rules {HIER_BRANCH_NOT_READ INPUT_NOT_READ} -location {caliptra_prim_onehot_check.sv} -regexp {.*'(clk_i|rst_ni)' is not read from in module 'caliptra_prim_onehot_check'.*} \
+      -comment "clk_ and rst_ni are only used for assertions in this module."
+
+waive -rules {PARAM_NOT_USED} -location {caliptra_prim_onehot_check.sv} -regexp {.*EnableAlertTriggerSVA.*} \
+      -comment "The disable parameter is used only during DV / FPV."
diff --git a/src/prim/lint/prim_sum_tree.vlt b/src/caliptra_prim/lint/caliptra_prim_sum_tree.vlt
similarity index 62%
rename from src/prim/lint/prim_sum_tree.vlt
rename to src/caliptra_prim/lint/caliptra_prim_sum_tree.vlt
index bb990bd78..bc0ec8f77 100644
--- a/src/prim/lint/prim_sum_tree.vlt
+++ b/src/caliptra_prim/lint/caliptra_prim_sum_tree.vlt
@@ -9,9 +9,9 @@
 // avoids spurious UNOPTFLAT warnings caused by the fact that the
 // arrays feed into themselves (with different bits for different
 // positions in the tree).
-split_var -module "prim_sum_tree" -var "sum_tree"
-split_var -module "prim_sum_tree" -var "vld_tree"
+split_var -module "caliptra_prim_sum_tree" -var "sum_tree"
+split_var -module "caliptra_prim_sum_tree" -var "vld_tree"
 
 // The clock and reset are only used for assertions in this module.
-lint_off -rule UNUSED -file "*/rtl/prim_sum_tree.sv" -match "Signal is not used: 'clk_i'"
-lint_off -rule UNUSED -file "*/rtl/prim_sum_tree.sv" -match "Signal is not used: 'rst_ni'"
+lint_off -rule UNUSED -file "*/rtl/caliptra_prim_sum_tree.sv" -match "Signal is not used: 'clk_i'"
+lint_off -rule UNUSED -file "*/rtl/caliptra_prim_sum_tree.sv" -match "Signal is not used: 'rst_ni'"
diff --git a/src/prim/lint/prim_max_tree.waiver b/src/caliptra_prim/lint/caliptra_prim_sum_tree.waiver
similarity index 51%
rename from src/prim/lint/prim_max_tree.waiver
rename to src/caliptra_prim/lint/caliptra_prim_sum_tree.waiver
index 870802010..987be5cd1 100644
--- a/src/prim/lint/prim_max_tree.waiver
+++ b/src/caliptra_prim/lint/caliptra_prim_sum_tree.waiver
@@ -2,7 +2,7 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
-# waiver file for prim_arbiter
+# waiver file for caliptra_prim_arbiter
 
-waive -rules {HIER_BRANCH_NOT_READ INPUT_NOT_READ} -location {prim_max_tree.sv} -regexp {.*'(clk_i|rst_ni)' is not read from in module 'prim_max_tree'.*} \
+waive -rules {HIER_BRANCH_NOT_READ INPUT_NOT_READ} -location {caliptra_prim_sum_tree.sv} -regexp {.*'(clk_i|rst_ni)' is not read from in module 'caliptra_prim_sum_tree'.*} \
       -comment "clk_ and rst_ni are only used for assertions in this module."
diff --git a/src/prim/rtl/prim_alert_pkg.sv b/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv
similarity index 90%
rename from src/prim/rtl/prim_alert_pkg.sv
rename to src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv
index a3594b619..1f9935a4c 100644
--- a/src/prim/rtl/prim_alert_pkg.sv
+++ b/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv
@@ -2,7 +2,7 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
-package prim_alert_pkg;
+package caliptra_prim_alert_pkg;
 
   typedef struct packed {
     logic alert_p;
@@ -24,4 +24,4 @@ package prim_alert_pkg;
                                             ack_p: 1'b0,
                                             ack_n: 1'b1};
 
-endpackage : prim_alert_pkg
+endpackage : caliptra_prim_alert_pkg
diff --git a/src/prim/rtl/prim_alert_receiver.sv b/src/caliptra_prim/rtl/caliptra_prim_alert_receiver.sv
similarity index 95%
rename from src/prim/rtl/prim_alert_receiver.sv
rename to src/caliptra_prim/rtl/caliptra_prim_alert_receiver.sv
index dc0632267..0421cb953 100644
--- a/src/prim/rtl/prim_alert_receiver.sv
+++ b/src/caliptra_prim/rtl/caliptra_prim_alert_receiver.sv
@@ -25,13 +25,13 @@
 // Note that in case of synchronous operation, alerts on the diffpair are
 // decoded combinationally and forwarded on alert_o within the same cycle.
 //
-// See also: prim_alert_sender, prim_diff_decode, alert_handler
+// See also: caliptra_prim_alert_sender, caliptra_prim_diff_decode, alert_handler
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
-module prim_alert_receiver
-  import prim_alert_pkg::*;
-  import prim_mubi_pkg::mubi4_t;
+module caliptra_prim_alert_receiver
+  import caliptra_prim_alert_pkg::*;
+  import caliptra_prim_mubi_pkg::mubi4_t;
 #(
   // enables additional synchronization logic
   parameter bit AsyncOn = 1'b0
@@ -56,7 +56,7 @@ module prim_alert_receiver
   input alert_tx_t  alert_tx_i
 );
 
-  import prim_mubi_pkg::mubi4_test_true_strict;
+  import caliptra_prim_mubi_pkg::mubi4_test_true_strict;
 
   /////////////////////////////////
   // decode differential signals //
@@ -64,16 +64,16 @@ module prim_alert_receiver
   logic alert_level, alert_sigint, alert_p, alert_n;
 
   // This prevents further tool optimizations of the differential signal.
-  prim_sec_anchor_buf #(
+  caliptra_prim_sec_anchor_buf #(
     .Width(2)
-  ) u_prim_buf_in (
+  ) u_caliptra_prim_buf_in (
     .in_i({alert_tx_i.alert_n,
            alert_tx_i.alert_p}),
     .out_o({alert_n,
             alert_p})
   );
 
-  prim_diff_decode #(
+  caliptra_prim_diff_decode #(
     .AsyncOn(AsyncOn)
   ) u_decode_alert (
     .clk_i,
@@ -112,10 +112,10 @@ module prim_alert_receiver
   assign ping_tog_dn = ~ping_tog_pd;
 
   // This prevents further tool optimizations of the differential signal.
-  prim_sec_anchor_flop #(
+  caliptra_prim_sec_anchor_flop #(
     .Width     (2),
     .ResetValue(2'b10)
-  ) u_prim_generic_flop_ack (
+  ) u_caliptra_prim_generic_flop_ack (
     .clk_i,
     .rst_ni,
     .d_i({ack_dn,
@@ -124,10 +124,10 @@ module prim_alert_receiver
           ack_pq})
   );
 
-  prim_sec_anchor_flop #(
+  caliptra_prim_sec_anchor_flop #(
     .Width     (2),
     .ResetValue(2'b10)
-  ) u_prim_generic_flop_ping (
+  ) u_caliptra_prim_generic_flop_ping (
     .clk_i,
     .rst_ni,
     .d_i({ping_tog_dn,
@@ -268,8 +268,8 @@ module prim_alert_receiver
   // assertions //
   ////////////////
 
-`ifdef INC_ASSERT
-  import prim_mubi_pkg::mubi4_test_false_loose;
+`ifdef CALIPTRA_INC_ASSERT
+  import caliptra_prim_mubi_pkg::mubi4_test_false_loose;
 `endif
 
   // check whether all outputs have a good known state after reset
@@ -383,4 +383,4 @@ module prim_alert_receiver
       |->
       ping_ok_o)
 
-endmodule : prim_alert_receiver
+endmodule : caliptra_prim_alert_receiver
diff --git a/src/prim/rtl/prim_alert_sender.sv b/src/caliptra_prim/rtl/caliptra_prim_alert_sender.sv
similarity index 94%
rename from src/prim/rtl/prim_alert_sender.sv
rename to src/caliptra_prim/rtl/caliptra_prim_alert_sender.sv
index e945482e9..b2f0ad09e 100644
--- a/src/prim/rtl/prim_alert_sender.sv
+++ b/src/caliptra_prim/rtl/caliptra_prim_alert_sender.sv
@@ -3,7 +3,7 @@
 // SPDX-License-Identifier: Apache-2.0
 //
 // The alert sender primitive module differentially encodes and transmits an
-// alert signal to the prim_alert_receiver module. An alert will be signalled
+// alert signal to the caliptra_prim_alert_receiver module. An alert will be signalled
 // by a full handshake on alert_p/n and ack_p/n. The alert_req_i signal may
 // be continuously asserted, in which case the alert signalling handshake
 // will be repeatedly initiated.
@@ -37,12 +37,12 @@
 // to the receiver by placing an inconsistent diff value on the differential
 // output (and continuously toggling it).
 //
-// See also: prim_alert_receiver, prim_diff_decode, alert_handler
+// See also: caliptra_prim_alert_receiver, caliptra_prim_diff_decode, alert_handler
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
-module prim_alert_sender
-  import prim_alert_pkg::*;
+module caliptra_prim_alert_sender
+  import caliptra_prim_alert_pkg::*;
 #(
   // enables additional synchronization logic
   parameter bit AsyncOn = 1'b1,
@@ -72,16 +72,16 @@ module prim_alert_sender
   logic ping_sigint, ping_event, ping_n, ping_p;
 
   // This prevents further tool optimizations of the differential signal.
-  prim_sec_anchor_buf #(
+  caliptra_prim_sec_anchor_buf #(
     .Width(2)
-  ) u_prim_buf_ping (
+  ) u_caliptra_prim_buf_ping (
     .in_i({alert_rx_i.ping_n,
            alert_rx_i.ping_p}),
     .out_o({ping_n,
             ping_p})
   );
 
-  prim_diff_decode #(
+  caliptra_prim_diff_decode #(
     .AsyncOn(AsyncOn)
   ) u_decode_ping (
     .clk_i,
@@ -98,16 +98,16 @@ module prim_alert_sender
   logic ack_sigint, ack_level, ack_n, ack_p;
 
   // This prevents further tool optimizations of the differential signal.
-  prim_sec_anchor_buf #(
+  caliptra_prim_sec_anchor_buf #(
     .Width(2)
-  ) u_prim_buf_ack (
+  ) u_caliptra_prim_buf_ack (
     .in_i({alert_rx_i.ack_n,
            alert_rx_i.ack_p}),
     .out_o({ack_n,
             ack_p})
   );
 
-  prim_diff_decode #(
+  caliptra_prim_diff_decode #(
     .AsyncOn(AsyncOn)
   ) u_decode_ack (
     .clk_i,
@@ -153,9 +153,9 @@ module prim_alert_sender
 
   // if handshake is ongoing, capture additional alert requests.
   logic alert_req;
-  prim_sec_anchor_buf #(
+  caliptra_prim_sec_anchor_buf #(
     .Width(1)
-  ) u_prim_buf_in_req (
+  ) u_caliptra_prim_buf_in_req (
     .in_i(alert_req_i),
     .out_o(alert_req)
   );
@@ -262,10 +262,10 @@ module prim_alert_sender
   end
 
   // This prevents further tool optimizations of the differential signal.
-  prim_sec_anchor_flop #(
+  caliptra_prim_sec_anchor_flop #(
     .Width     (2),
     .ResetValue(2'b10)
-  ) u_prim_flop_alert (
+  ) u_caliptra_prim_flop_alert (
     .clk_i,
     .rst_ni,
     .d_i({alert_nd, alert_pd}),
@@ -292,8 +292,8 @@ module prim_alert_sender
   ////////////////
 
 // however, since we use sequence constructs below, we need to wrap the entire block again.
-// typically, the CALIPTRA_ASSERT macros already contain this INC_ASSERT macro.
-`ifdef INC_ASSERT
+// typically, the CALIPTRA_ASSERT macros already contain this CALIPTRA_INC_ASSERT macro.
+`ifdef CALIPTRA_INC_ASSERT
   // check whether all outputs have a good known state after reset
   `CALIPTRA_ASSERT_KNOWN(AlertPKnownO_A, alert_tx_o)
 
@@ -389,4 +389,4 @@ module prim_alert_sender
   `CALIPTRA_ASSUME_FPV(TriggerAlertInit_S, $stable(rst_ni) == 0 |=> alert_rx_i.ping_p == alert_rx_i.ping_n)
   `CALIPTRA_ASSUME_FPV(PingDiffPair_S, ##2 alert_rx_i.ping_p != alert_rx_i.ping_n)
 `endif
-endmodule : prim_alert_sender
+endmodule : caliptra_prim_alert_sender
diff --git a/src/prim/rtl/prim_arbiter_ppc.sv b/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv
similarity index 98%
rename from src/prim/rtl/prim_arbiter_ppc.sv
rename to src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv
index cb160116c..f3275abd5 100644
--- a/src/prim/rtl/prim_arbiter_ppc.sv
+++ b/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv
@@ -20,11 +20,11 @@
 // until they have been served. This assertion can be gated by driving the req_chk_i low. This is
 // a non-functional input and does not affect the designs behavior.
 //
-// See also: prim_arbiter_tree
+// See also: caliptra_prim_arbiter_tree
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
-module prim_arbiter_ppc #(
+module caliptra_prim_arbiter_ppc #(
   parameter int unsigned N  = 8,
   parameter int unsigned DW = 32,
 
@@ -222,4 +222,4 @@ end
       req_i[k], clk_i, !rst_ni || !req_chk_i)
 `endif
 
-endmodule : prim_arbiter_ppc
+endmodule : caliptra_prim_arbiter_ppc
diff --git a/src/prim/rtl/prim_assert.sv b/src/caliptra_prim/rtl/caliptra_prim_assert.sv
similarity index 91%
rename from src/prim/rtl/prim_assert.sv
rename to src/caliptra_prim/rtl/caliptra_prim_assert.sv
index 77539d3f2..7a91601a9 100644
--- a/src/prim/rtl/prim_assert.sv
+++ b/src/caliptra_prim/rtl/caliptra_prim_assert.sv
@@ -7,7 +7,7 @@
 //  - Provides boiler plate template for common assertions
 
 `ifndef PRIM_ASSERT_SV
-`define PRIM_ASSERT_SV
+`define CALIPTRA_PRIM_ASSERT_SV
 
 ///////////////////
 // Helper macros //
@@ -21,7 +21,7 @@
 `endif
 
 // Converts an arbitrary block of code into a Verilog string
-`define PRIM_STRINGIFY(__x) `"__x`"
+`define CALIPTRA_PRIM_STRINGIFY(__x) `"__x`"
 
 // CALIPTRA_ASSERT_ERROR logs an error message with either `uvm_error or with $error.
 //
@@ -29,11 +29,11 @@
 // for redefining it here is to avoid creating a dependency.
 `define CALIPTRA_ASSERT_ERROR(__name)                                                             \
 `ifdef UVM                                                                                        \
-  uvm_pkg::uvm_report_error("CALIPTRA_ASSERT FAILED", `PRIM_STRINGIFY(__name), uvm_pkg::UVM_NONE, \
+  uvm_pkg::uvm_report_error("CALIPTRA_ASSERT FAILED", `CALIPTRA_PRIM_STRINGIFY(__name), uvm_pkg::UVM_NONE, \
                             `__FILE__, `__LINE__, "", 1);                                         \
 `else                                                                                             \
   $error("%0t: (%0s:%0d) [%m] [CALIPTRA_ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         \
-         `PRIM_STRINGIFY(__name));                                                                \
+         `CALIPTRA_PRIM_STRINGIFY(__name));                                                                \
 `endif
 
 // This macro is suitable for conditionally triggering lint errors, e.g., if a Sec parameter takes
@@ -59,8 +59,8 @@
 // the same thing in each case (except for the dummy flavour), but in a way that the respective
 // tools support.
 //
-// If the tool supports assertions in some form, we also define INC_ASSERT (which can be used to
-// hide signal definitions that are only used for assertions).
+// If the tool supports assertions in some form, we also define CALIPTRA_INC_ASSERT (which can be 
+// used to hide signal definitions that are only used for assertions).
 //
 // The list of basic macros supported is:
 //
@@ -94,15 +94,15 @@
 //  CALIPTRA_ASSUME_I:     Assume an immediate property
 
 `ifdef VERILATOR
- `include "prim_assert_dummy_macros.svh"
+ `include "caliptra_prim_assert_dummy_macros.svh"
 `elsif SYNTHESIS
- `include "prim_assert_dummy_macros.svh"
+ `include "caliptra_prim_assert_dummy_macros.svh"
 `elsif YOSYS
- `include "prim_assert_yosys_macros.svh"
- `define INC_ASSERT
+ `include "caliptra_prim_assert_yosys_macros.svh"
+ `define CALIPTRA_INC_ASSERT
 `else
- `include "prim_assert_standard_macros.svh"
- `define INC_ASSERT
+ `include "caliptra_prim_assert_standard_macros.svh"
+ `define CALIPTRA_INC_ASSERT
 `endif
 
 //////////////////////////////
@@ -159,7 +159,7 @@
 // Create a small "gray" window beyond the usual rst time to avoid
 // checking.
 `define CALIPTRA_ASSERT_FPV_LINEAR_FSM(__name, __state, __type, __clk = `CALIPTRA_ASSERT_DEFAULT_CLK, __rst = `CALIPTRA_ASSERT_DEFAULT_RST) \
-  `ifdef INC_ASSERT                                                                                              \
+  `ifdef CALIPTRA_INC_ASSERT                                                                                              \
      bit __name``_cond;                                                                                          \
      always_ff @(posedge __clk or posedge __rst) begin                                                           \
        if (__rst) begin                                                                                          \
@@ -176,7 +176,7 @@
    `CALIPTRA_ASSERT(__name, __name``_p, __clk, __rst)                                                                     \
   `endif
 
-`include "prim_assert_sec_cm.svh"
-`include "prim_flop_macros.sv"
+`include "caliptra_prim_assert_sec_cm.svh"
+`include "caliptra_prim_flop_macros.sv"
 
 `endif // PRIM_ASSERT_SV
diff --git a/src/prim/rtl/prim_assert_dummy_macros.svh b/src/caliptra_prim/rtl/caliptra_prim_assert_dummy_macros.svh
similarity index 85%
rename from src/prim/rtl/prim_assert_dummy_macros.svh
rename to src/caliptra_prim/rtl/caliptra_prim_assert_dummy_macros.svh
index a868a9a29..047bb9a58 100644
--- a/src/prim/rtl/prim_assert_dummy_macros.svh
+++ b/src/caliptra_prim/rtl/caliptra_prim_assert_dummy_macros.svh
@@ -2,8 +2,8 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
-// Macro bodies included by prim_assert.sv for tools that don't support assertions. See
-// prim_assert.sv for documentation for each of the macros.
+// Macro bodies included by caliptra_prim_assert.sv for tools that don't support assertions. See
+// caliptra_prim_assert.sv for documentation for each of the macros.
 
 `define CALIPTRA_ASSERT_I(__name, __prop)
 `define CALIPTRA_ASSERT_INIT(__name, __prop)
diff --git a/src/caliptra_prim/rtl/caliptra_prim_assert_sec_cm.svh b/src/caliptra_prim/rtl/caliptra_prim_assert_sec_cm.svh
new file mode 100644
index 000000000..096b7b61f
--- /dev/null
+++ b/src/caliptra_prim/rtl/caliptra_prim_assert_sec_cm.svh
@@ -0,0 +1,48 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// // Macros and helper code for security countermeasures.
+
+`ifndef PRIM_ASSERT_SEC_CM_SVH
+`define CALIPTRA_PRIM_ASSERT_SEC_CM_SVH
+
+`define _CALIPTRA_SEC_CM_ALERT_MAX_CYC 30
+
+// Helper macros
+`define CALIPTRA_ASSERT_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, GATE_, MAX_CYCLES_, ERR_NAME_) \
+  `CALIPTRA_ASSERT(FpvSecCm``NAME_``, \
+          $rose(PRIM_HIER_.ERR_NAME_) && !(GATE_) \
+          |-> ##[0:MAX_CYCLES_] (ALERT_.alert_p)) \
+  `ifdef CALIPTRA_INC_ASSERT \
+  assign PRIM_HIER_.unused_assert_connected = 1'b1; \
+  `endif \
+  `CALIPTRA_ASSUME_FPV(``NAME_``TriggerAfterAlertInit_S, $stable(rst_ni) == 0 |-> \
+                       PRIM_HIER_.ERR_NAME_ == 0 [*10])
+
+`define CALIPTRA_ASSERT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_, MAX_CYCLES_, ERR_NAME_, CLK_, RST_) \
+  `CALIPTRA_ASSERT(FpvSecCm``NAME_``, \
+          $rose(PRIM_HIER_.ERR_NAME_) && !(GATE_) \
+          |-> ##[0:MAX_CYCLES_] (ERR_), CLK_, RST_) \
+  `ifdef CALIPTRA_INC_ASSERT \
+  assign PRIM_HIER_.unused_assert_connected = 1'b1; \
+  `endif
+
+// macros for security countermeasures that will trigger alert
+`define CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, GATE_ = 0, MAX_CYCLES_ = `_CALIPTRA_SEC_CM_ALERT_MAX_CYC) \
+  `CALIPTRA_ASSERT_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, GATE_, MAX_CYCLES_, err_o)
+
+`define CALIPTRA_ASSERT_PRIM_DOUBLE_LFSR_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, GATE_ = 0, MAX_CYCLES_ = `_CALIPTRA_SEC_CM_ALERT_MAX_CYC) \
+  `CALIPTRA_ASSERT_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, GATE_, MAX_CYCLES_, err_o)
+
+`define CALIPTRA_ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, GATE_ = 0, MAX_CYCLES_ = `_CALIPTRA_SEC_CM_ALERT_MAX_CYC) \
+  `CALIPTRA_ASSERT_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, GATE_, MAX_CYCLES_, unused_err_o)
+
+`define CALIPTRA_ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, GATE_ = 0, MAX_CYCLES_ = `_CALIPTRA_SEC_CM_ALERT_MAX_CYC) \
+  `CALIPTRA_ASSERT_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, GATE_, MAX_CYCLES_, err_o)
+
+`define CALIPTRA_ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(NAME_, REG_TOP_HIER_, ALERT_, GATE_ = 0, MAX_CYCLES_ = `_CALIPTRA_SEC_CM_ALERT_MAX_CYC) \
+  `CALIPTRA_ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ALERT(NAME_, \
+    REG_TOP_HIER_.u_caliptra_prim_reg_we_check.u_caliptra_prim_onehot_check, ALERT_, GATE_, MAX_CYCLES_)
+
+`endif // PRIM_ASSERT_SEC_CM_SVH
diff --git a/src/prim/rtl/prim_assert_standard_macros.svh b/src/caliptra_prim/rtl/caliptra_prim_assert_standard_macros.svh
similarity index 96%
rename from src/prim/rtl/prim_assert_standard_macros.svh
rename to src/caliptra_prim/rtl/caliptra_prim_assert_standard_macros.svh
index 611cd366d..966906340 100644
--- a/src/prim/rtl/prim_assert_standard_macros.svh
+++ b/src/caliptra_prim/rtl/caliptra_prim_assert_standard_macros.svh
@@ -2,8 +2,8 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
-// Macro bodies included by prim_assert.sv for tools that support full SystemVerilog and SVA syntax.
-// See prim_assert.sv for documentation for each of the macros.
+// Macro bodies included by caliptra_prim_assert.sv for tools that support full SystemVerilog and SVA syntax.
+// See caliptra_prim_assert.sv for documentation for each of the macros.
 
 `define CALIPTRA_ASSERT_I(__name, __prop) \
   __name: assert (__prop)        \
diff --git a/src/prim/rtl/prim_assert_yosys_macros.svh b/src/caliptra_prim/rtl/caliptra_prim_assert_yosys_macros.svh
similarity index 95%
rename from src/prim/rtl/prim_assert_yosys_macros.svh
rename to src/caliptra_prim/rtl/caliptra_prim_assert_yosys_macros.svh
index c5d237c8a..f47b5b796 100644
--- a/src/prim/rtl/prim_assert_yosys_macros.svh
+++ b/src/caliptra_prim/rtl/caliptra_prim_assert_yosys_macros.svh
@@ -2,7 +2,7 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
-// Macro bodies included by prim_assert.sv for formal verification with Yosys. See prim_assert.sv
+// Macro bodies included by caliptra_prim_assert.sv for formal verification with Yosys. See caliptra_prim_assert.sv
 // for documentation for each of the macros.
 
 `define CALIPTRA_ASSERT_I(__name, __prop)    \
diff --git a/src/prim/rtl/prim_buf.sv b/src/caliptra_prim/rtl/caliptra_prim_buf.sv
similarity index 75%
rename from src/prim/rtl/prim_buf.sv
rename to src/caliptra_prim/rtl/caliptra_prim_buf.sv
index d0e5839fb..5567894bc 100755
--- a/src/prim/rtl/prim_buf.sv
+++ b/src/caliptra_prim/rtl/caliptra_prim_buf.sv
@@ -6,7 +6,7 @@
 // Used parser: Verible
 
 `ifndef PRIM_DEFAULT_IMPL
-  `define PRIM_DEFAULT_IMPL prim_pkg::ImplGeneric
+  `define CALIPTRA_PRIM_DEFAULT_IMPL caliptra_prim_pkg::ImplGeneric
 `endif
 
 // This is to prevent AscentLint warnings in the generated
@@ -14,7 +14,7 @@
 // use. TODO: we may want to move these inline waivers
 // into a separate, generated waiver file for consistency.
 //ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ HIER_BRANCH_NOT_READ
-module prim_buf
+module caliptra_prim_buf
 
 #(
 parameter int Width = 1
@@ -22,16 +22,16 @@ parameter int Width = 1
   input        [Width-1:0] in_i,
   output logic [Width-1:0] out_o
 );
-  parameter prim_pkg::impl_e Impl = `PRIM_DEFAULT_IMPL;
+  parameter caliptra_prim_pkg::impl_e Impl = `CALIPTRA_PRIM_DEFAULT_IMPL;
 
-if (Impl == prim_pkg::ImplXilinx) begin : gen_xilinx
-    prim_xilinx_buf #(
+if (Impl == caliptra_prim_pkg::ImplXilinx) begin : gen_xilinx
+    caliptra_prim_xilinx_buf #(
       .Width(Width)
     ) u_impl_xilinx (
       .*
     );
 end else begin : gen_generic
-    prim_generic_buf #(
+    caliptra_prim_generic_buf #(
       .Width(Width)
     ) u_impl_generic (
       .*
diff --git a/src/caliptra_prim/rtl/caliptra_prim_cdc_rand_delay.sv b/src/caliptra_prim/rtl/caliptra_prim_cdc_rand_delay.sv
new file mode 100644
index 000000000..8b63739c3
--- /dev/null
+++ b/src/caliptra_prim/rtl/caliptra_prim_cdc_rand_delay.sv
@@ -0,0 +1,63 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// This module should be instantiated within flops of CDC synchronization primitives,
+// and allows DV to model real CDC delays within simulations, especially useful at the chip level
+// or in IPs that communicate across clock domains.
+//
+// The instrumentation is very simple: when this is enabled the input into the first
+// synchronizer flop has a mux where the select is randomly set. One of the mux inputs is the input
+// of this module, and the other is the output of the first flop: selecting the latter models the
+// effect of the first flop missing the input transition.
+//
+// Notice the delay should cause the input to be skipped by at most a single cycle. As a perhaps
+// unnecessary precaution, the select will only be allowed to be random when the input changes.
+
+module caliptra_prim_cdc_rand_delay #(
+    parameter int DataWidth = 1,
+    parameter bit Enable = 1
+) (
+    input logic                   clk_i,
+    input logic                   rst_ni,
+    input logic [DataWidth-1:0]   prev_data_i,
+    input logic [DataWidth-1:0]   src_data_i,
+    output logic [DataWidth-1:0]  dst_data_o
+);
+`ifdef CALIPTRA_SIMULATION
+  if (Enable) begin : gen_enable
+
+    // This controls dst_data_o: any bit with its data_sel set uses prev_data_i, others use
+    // src_data_i.
+    bit [DataWidth-1:0] data_sel;
+    bit                 cdc_instrumentation_enabled;
+
+    function automatic bit [DataWidth-1:0] fast_randomize();
+      bit [DataWidth-1:0] data;
+      bit [31:0]          urandom_result;
+      for (int i = 0; i < DataWidth; i += 32) begin
+        data = data << 32;
+        urandom_result = $urandom();
+        data = data | urandom_result;
+      end
+      return data;
+    endfunction
+
+    initial begin
+      void'($value$plusargs("cdc_instrumentation_enabled=%d", cdc_instrumentation_enabled));
+      data_sel = '0;
+    end
+
+    // Set data_sel at random combinationally when the input changes.
+    always @(src_data_i) begin
+      data_sel = cdc_instrumentation_enabled ? fast_randomize() : 0;
+    end
+
+    always_comb dst_data_o = (prev_data_i & data_sel) | (src_data_i & ~data_sel);
+  end else begin : gen_no_enable
+    assign dst_data_o = src_data_i;
+  end
+`else  // CALIPTRA_SIMULATION
+    assign dst_data_o = src_data_i;
+`endif  // CALIPTRA_SIMULATION
+endmodule
diff --git a/src/prim/rtl/prim_cipher_pkg.sv b/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv
similarity index 99%
rename from src/prim/rtl/prim_cipher_pkg.sv
rename to src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv
index 742c92536..a9f9532a2 100644
--- a/src/prim/rtl/prim_cipher_pkg.sv
+++ b/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv
@@ -5,7 +5,7 @@
 // This package holds common constants and functions for PRESENT- and
 // PRINCE-based scrambling devices.
 //
-// See also: prim_present, prim_prince
+// See also: caliptra_prim_present, caliptra_prim_prince
 //
 // References: - https://en.wikipedia.org/wiki/PRESENT
 //             - https://en.wikipedia.org/wiki/Prince_(cipher)
@@ -14,7 +14,7 @@
 //             - https://eprint.iacr.org/2015/372.pdf
 //             - https://eprint.iacr.org/2014/656.pdf
 
-package prim_cipher_pkg;
+package caliptra_prim_cipher_pkg;
 
   ///////////////////
   // PRINCE Cipher //
@@ -394,4 +394,4 @@ package prim_cipher_pkg;
     return state_out;
   endfunction : perm_64bit
 
-endpackage : prim_cipher_pkg
+endpackage : caliptra_prim_cipher_pkg
diff --git a/src/prim/rtl/prim_count.sv b/src/caliptra_prim/rtl/caliptra_prim_count.sv
similarity index 97%
rename from src/prim/rtl/prim_count.sv
rename to src/caliptra_prim/rtl/caliptra_prim_count.sv
index 257a574f1..1e8dc7465 100644
--- a/src/prim/rtl/prim_count.sv
+++ b/src/caliptra_prim/rtl/caliptra_prim_count.sv
@@ -20,9 +20,9 @@
 // Note that if both incr_en_i and decr_en_i are asserted at the same time, the counter remains
 // unchanged. The counter is also protected against under- and overflows.
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
-module prim_count #(
+module caliptra_prim_count #(
   parameter int Width = 2,
   // Can be used to reset the counter to a different value than 0, for example when
   // the counter is used as a down-counter.
@@ -101,7 +101,7 @@ module prim_count #(
                       (cnt_en) ? cnt_sat        : cnt_q[k];
 
     logic [Width-1:0] cnt_unforced_q;
-    prim_flop #(
+    caliptra_prim_flop #(
       .Width(Width),
       .ResetValue(ResetValues[k])
     ) u_cnt_flop (
@@ -127,7 +127,7 @@ module prim_count #(
   ////////////////
   // Assertions //
   ////////////////
-`ifdef INC_ASSERT
+`ifdef CALIPTRA_INC_ASSERT
   //VCS coverage off
   // pragma coverage off
 
@@ -251,11 +251,11 @@ module prim_count #(
       (cnt_q[1] + cnt_q[0]) != {Width{1'b1}})
 
   // This logic that will be assign to one, when user adds macro
-  // CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT to check the error with alert, in case that prim_count
+  // CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT to check the error with alert, in case that caliptra_prim_count
   // is used in design without adding this assertion check.
   logic unused_assert_connected;
 
   `CALIPTRA_ASSERT_INIT_NET(AssertConnected_A, unused_assert_connected === 1'b1 || !EnableAlertTriggerSVA)
 `endif
 
-endmodule // prim_count
+endmodule // caliptra_prim_count
diff --git a/src/prim/rtl/prim_diff_decode.sv b/src/caliptra_prim/rtl/caliptra_prim_diff_decode.sv
similarity index 97%
rename from src/prim/rtl/prim_diff_decode.sv
rename to src/caliptra_prim/rtl/caliptra_prim_diff_decode.sv
index 3c0818b8e..40450d7e6 100644
--- a/src/prim/rtl/prim_diff_decode.sv
+++ b/src/caliptra_prim/rtl/caliptra_prim_diff_decode.sv
@@ -13,11 +13,11 @@
 // the differential pair (i.e., when level changes on the diff pair are
 // sampled one cycle apart due to a timing skew between the two wires).
 //
-// See also: prim_alert_sender, prim_alert_receiver, alert_handler
+// See also: caliptra_prim_alert_sender, caliptra_prim_alert_receiver, alert_handler
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
-module prim_diff_decode #(
+module caliptra_prim_diff_decode #(
   // enables additional synchronization logic
   parameter bit AsyncOn = 1'b0
 ) (
@@ -51,7 +51,7 @@ module prim_diff_decode #(
     // 2 sync regs, one reg for edge detection
     logic diff_pq, diff_nq, diff_pd, diff_nd;
 
-    prim_flop_2sync #(
+    caliptra_prim_flop_2sync #(
       .Width(1),
       .ResetValue('0)
     ) i_sync_p (
@@ -61,7 +61,7 @@ module prim_diff_decode #(
       .q_o(diff_pd)
     );
 
-    prim_flop_2sync #(
+    caliptra_prim_flop_2sync #(
       .Width(1),
       .ResetValue(1'b1)
     ) i_sync_n (
@@ -219,7 +219,7 @@ module prim_diff_decode #(
 
   if (AsyncOn) begin : gen_async_assert
     // assertions for asynchronous case
-`ifdef INC_ASSERT
+`ifdef CALIPTRA_INC_ASSERT
   `ifndef FPV_ALERT_NO_SIGINT_ERR
     // correctly detect sigint issue (only one transition cycle of permissible due to skew)
     `CALIPTRA_ASSERT(SigintCheck0_A, gen_async.diff_pd == gen_async.diff_nd [*2] |-> sigint_o)
@@ -282,4 +282,4 @@ module prim_diff_decode #(
     `CALIPTRA_ASSERT(LevelCheck_A, (diff_pi ^ diff_ni) |-> diff_pi == level_o)
   end
 
-endmodule : prim_diff_decode
+endmodule : caliptra_prim_diff_decode
diff --git a/src/prim/rtl/prim_dom_and_2share.sv b/src/caliptra_prim/rtl/caliptra_prim_dom_and_2share.sv
similarity index 94%
rename from src/prim/rtl/prim_dom_and_2share.sv
rename to src/caliptra_prim/rtl/caliptra_prim_dom_and_2share.sv
index f81994301..3ed0e0dd1 100644
--- a/src/prim/rtl/prim_dom_and_2share.sv
+++ b/src/caliptra_prim/rtl/caliptra_prim_dom_and_2share.sv
@@ -23,9 +23,9 @@
 // Q1 = t{1,1} + sig(j>1,1)(...) + sig(j<1,1)(t{1,j} + Z{j})
 //    = a1&b1  + (0              + a1&b0 + z0)
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
-module prim_dom_and_2share #(
+module caliptra_prim_dom_and_2share #(
   parameter int DW = 64, // Input width
   parameter bit Pipeline = 1'b0 // Enable full pipelining
 ) (
@@ -66,19 +66,19 @@ module prim_dom_and_2share #(
   // Resharing of cross-domain terms
 
   // Preserve the logic sequence for XOR not to proceed cross-domain AND.
-  prim_xor2 #(
+  caliptra_prim_xor2 #(
     .Width ( DW*2 )
-  ) u_prim_xor_t01 (
+  ) u_caliptra_prim_xor_t01 (
     .in0_i ( {t_a0b1, t_a1b0} ),
     .in1_i ( {z_i,    z_i}    ),
     .out_o ( {t0_d,   t1_d}   )
   );
 
   // Register stage
-  prim_flop_en #(
+  caliptra_prim_flop_en #(
     .Width      ( DW*2 ),
     .ResetValue ( '0   )
-  ) u_prim_flop_t01 (
+  ) u_caliptra_prim_flop_t01 (
     .clk_i  ( clk_i        ),
     .rst_ni ( rst_ni       ),
     .en_i   ( z_valid_i    ),
@@ -96,10 +96,10 @@ module prim_dom_and_2share #(
     // reshared cross-domain terms with inner-domain terms derived from different input data.
 
     logic [DW-1:0] t_a0b0_q, t_a1b1_q;
-    prim_flop_en #(
+    caliptra_prim_flop_en #(
       .Width      ( DW*2 ),
       .ResetValue ( '0   )
-    ) u_prim_flop_tab01 (
+    ) u_caliptra_prim_flop_tab01 (
       .clk_i  ( clk_i                ),
       .rst_ni ( rst_ni               ),
       .en_i   ( z_valid_i            ),
@@ -125,9 +125,9 @@ module prim_dom_and_2share #(
   /////////////////
 
   // Preserve the logic sequence for XOR not to proceed the inner-domain AND.
-  prim_xor2 #(
+  caliptra_prim_xor2 #(
     .Width ( DW*2 )
-  ) u_prim_xor_q01 (
+  ) u_caliptra_prim_xor_q01 (
     .in0_i ( {t_a0b0, t_a1b1} ),
     .in1_i ( {t0_q,   t1_q}   ),
     .out_o ( {q0_o,   q1_o}   )
diff --git a/src/prim/rtl/prim_edge_detector.sv b/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv
similarity index 91%
rename from src/prim/rtl/prim_edge_detector.sv
rename to src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv
index 2b0a92fb7..98b93624e 100644
--- a/src/prim/rtl/prim_edge_detector.sv
+++ b/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv
@@ -4,7 +4,7 @@
 //
 // Edge Detector
 
-module prim_edge_detector #(
+module caliptra_prim_edge_detector #(
   parameter int unsigned Width = 1,
 
   parameter logic [Width-1:0] ResetValue = '0,
@@ -28,7 +28,7 @@ module prim_edge_detector #(
   logic [Width-1:0] q_sync_d, q_sync_q;
 
   if (EnSync) begin : g_sync
-    prim_flop_2sync #(
+    caliptra_prim_flop_2sync #(
       .Width (Width),
       .ResetValue (ResetValue)
     ) u_sync (
@@ -52,4 +52,4 @@ module prim_edge_detector #(
   assign q_posedge_pulse_o = q_sync_d & ~q_sync_q;
   assign q_negedge_pulse_o = ~q_sync_d & q_sync_q;
 
-endmodule : prim_edge_detector
+endmodule : caliptra_prim_edge_detector
diff --git a/src/prim/rtl/prim_fifo_sync.sv b/src/caliptra_prim/rtl/caliptra_prim_fifo_sync.sv
similarity index 95%
rename from src/prim/rtl/prim_fifo_sync.sv
rename to src/caliptra_prim/rtl/caliptra_prim_fifo_sync.sv
index d45db0ff1..a9713b85d 100644
--- a/src/prim/rtl/prim_fifo_sync.sv
+++ b/src/caliptra_prim/rtl/caliptra_prim_fifo_sync.sv
@@ -4,16 +4,16 @@
 //
 // Generic synchronous fifo for use in a variety of devices.
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
-module prim_fifo_sync #(
+module caliptra_prim_fifo_sync #(
   parameter int unsigned Width       = 16,
   parameter bit Pass                 = 1'b1, // if == 1 allow requests to pass through empty FIFO
   parameter int unsigned Depth       = 4,
   parameter bit OutputZeroIfEmpty    = 1'b1, // if == 1 always output 0 when FIFO is empty
   parameter bit Secure               = 1'b0, // use prim count for pointers
   // derived parameter
-  localparam int          DepthW     = prim_util_pkg::vbits(Depth+1)
+  localparam int          DepthW     = caliptra_prim_util_pkg::vbits(Depth+1)
 ) (
   input                   clk_i,
   input                   rst_ni,
@@ -58,7 +58,7 @@ module prim_fifo_sync #(
   // Normal FIFO construction
   end else begin : gen_normal_fifo
 
-    localparam int unsigned PTRV_W    = prim_util_pkg::vbits(Depth);
+    localparam int unsigned PTRV_W    = caliptra_prim_util_pkg::vbits(Depth);
     localparam int unsigned PTR_WIDTH = PTRV_W+1;
 
     logic [PTR_WIDTH-1:0] fifo_wptr, fifo_rptr;
@@ -99,7 +99,7 @@ module prim_fifo_sync #(
     assign full_o   = full;
     assign rvalid_o = ~empty & ~under_rst;
 
-    prim_fifo_sync_cnt #(
+    caliptra_prim_fifo_sync_cnt #(
       .Width(PTR_WIDTH),
       .Depth(Depth),
       .Secure(Secure)
diff --git a/src/prim/rtl/prim_fifo_sync_cnt.sv b/src/caliptra_prim/rtl/caliptra_prim_fifo_sync_cnt.sv
similarity index 93%
rename from src/prim/rtl/prim_fifo_sync_cnt.sv
rename to src/caliptra_prim/rtl/caliptra_prim_fifo_sync_cnt.sv
index ec69515b0..02f05b823 100644
--- a/src/prim/rtl/prim_fifo_sync_cnt.sv
+++ b/src/caliptra_prim/rtl/caliptra_prim_fifo_sync_cnt.sv
@@ -4,9 +4,9 @@
 //
 // Generic synchronous fifo for use in a variety of devices.
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
-module prim_fifo_sync_cnt #(
+module caliptra_prim_fifo_sync_cnt #(
   parameter int Depth = 4,
   parameter int Width = 16,
   parameter bit Secure = 1'b0
@@ -34,7 +34,7 @@ module prim_fifo_sync_cnt #(
 
   if (Secure) begin : gen_secure_ptrs
     logic wptr_err;
-    prim_count #(
+    caliptra_prim_count #(
       .Width(Width)
     ) u_wptr (
       .clk_i,
@@ -51,7 +51,7 @@ module prim_fifo_sync_cnt #(
     );
 
     logic rptr_err;
-    prim_count #(
+    caliptra_prim_count #(
       .Width(Width)
     ) u_rptr (
       .clk_i,
@@ -99,4 +99,4 @@ module prim_fifo_sync_cnt #(
 
 
 
-endmodule // prim_fifo_sync_cnt
+endmodule // caliptra_prim_fifo_sync_cnt
diff --git a/src/prim/rtl/prim_flop.sv b/src/caliptra_prim/rtl/caliptra_prim_flop.sv
similarity index 78%
rename from src/prim/rtl/prim_flop.sv
rename to src/caliptra_prim/rtl/caliptra_prim_flop.sv
index 3c4667512..395a53c68 100755
--- a/src/prim/rtl/prim_flop.sv
+++ b/src/caliptra_prim/rtl/caliptra_prim_flop.sv
@@ -6,7 +6,7 @@
 // Used parser: Fallback (regex)
 
 `ifndef PRIM_DEFAULT_IMPL
-  `define PRIM_DEFAULT_IMPL prim_pkg::ImplGeneric
+  `define CALIPTRA_PRIM_DEFAULT_IMPL caliptra_prim_pkg::ImplGeneric
 `endif
 
 // This is to prevent AscentLint warnings in the generated
@@ -14,7 +14,7 @@
 // use. TODO: we may want to move these inline waivers
 // into a separate, generated waiver file for consistency.
 //ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ HIER_BRANCH_NOT_READ
-module prim_flop
+module caliptra_prim_flop
 
 #(
 
@@ -27,17 +27,17 @@ module prim_flop
   input        [Width-1:0] d_i,
   output logic [Width-1:0] q_o
 );
-  parameter prim_pkg::impl_e Impl = `PRIM_DEFAULT_IMPL;
+  parameter caliptra_prim_pkg::impl_e Impl = `CALIPTRA_PRIM_DEFAULT_IMPL;
 
-if (Impl == prim_pkg::ImplXilinx) begin : gen_xilinx
-    prim_xilinx_flop #(
+if (Impl == caliptra_prim_pkg::ImplXilinx) begin : gen_xilinx
+    caliptra_prim_xilinx_flop #(
       .ResetValue(ResetValue),
       .Width(Width)
     ) u_impl_xilinx (
       .*
     );
 end else begin : gen_generic
-    prim_generic_flop #(
+    caliptra_prim_generic_flop #(
       .ResetValue(ResetValue),
       .Width(Width)
     ) u_impl_generic (
diff --git a/src/prim/rtl/prim_flop_2sync.sv b/src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv
similarity index 73%
rename from src/prim/rtl/prim_flop_2sync.sv
rename to src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv
index 7ff3c76ae..4c8b929a7 100644
--- a/src/prim/rtl/prim_flop_2sync.sv
+++ b/src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv
@@ -3,10 +3,10 @@
 // SPDX-License-Identifier: Apache-2.0
 //
 // Generic double-synchronizer flop
-// This may need to be moved to prim_generic if libraries have a specific cell
+// This may need to be moved to caliptra_prim_generic if libraries have a specific cell
 // for synchronization
 
-module prim_flop_2sync #(
+module caliptra_prim_flop_2sync #(
   parameter int               Width      = 16,
   parameter logic [Width-1:0] ResetValue = '0,
   parameter bit               EnablePrimCdcRand = 1
@@ -20,25 +20,25 @@ module prim_flop_2sync #(
   logic [Width-1:0] d_o;
   logic [Width-1:0] intq;
 
-`ifdef SIMULATION
+`ifdef CALIPTRA_SIMULATION
 
-  prim_cdc_rand_delay #(
+  caliptra_prim_cdc_rand_delay #(
     .DataWidth(Width),
     .Enable(EnablePrimCdcRand)
-  ) u_prim_cdc_rand_delay (
+  ) u_caliptra_prim_cdc_rand_delay (
     .clk_i,
     .rst_ni,
     .src_data_i(d_i),
     .prev_data_i(intq),
     .dst_data_o(d_o)
   );
-`else // !`ifdef SIMULATION
+`else // !`ifdef CALIPTRA_SIMULATION
   logic unused_sig;
   assign unused_sig = EnablePrimCdcRand;
   always_comb d_o = d_i;
-`endif // !`ifdef SIMULATION
+`endif // !`ifdef CALIPTRA_SIMULATION
 
-  prim_flop #(
+  caliptra_prim_flop #(
     .Width(Width),
     .ResetValue(ResetValue)
   ) u_sync_1 (
@@ -48,7 +48,7 @@ module prim_flop_2sync #(
     .q_o(intq)
   );
 
-  prim_flop #(
+  caliptra_prim_flop #(
     .Width(Width),
     .ResetValue(ResetValue)
   ) u_sync_2 (
@@ -58,4 +58,4 @@ module prim_flop_2sync #(
     .q_o
   );
 
-endmodule : prim_flop_2sync
+endmodule : caliptra_prim_flop_2sync
diff --git a/src/prim/rtl/prim_flop_en.sv b/src/caliptra_prim/rtl/caliptra_prim_flop_en.sv
similarity index 80%
rename from src/prim/rtl/prim_flop_en.sv
rename to src/caliptra_prim/rtl/caliptra_prim_flop_en.sv
index 8f9ba1a10..f7b073e33 100644
--- a/src/prim/rtl/prim_flop_en.sv
+++ b/src/caliptra_prim/rtl/caliptra_prim_flop_en.sv
@@ -6,7 +6,7 @@
 // Used parser: Fallback (regex)
 
 `ifndef PRIM_DEFAULT_IMPL
-  `define PRIM_DEFAULT_IMPL prim_pkg::ImplGeneric
+  `define CALIPTRA_PRIM_DEFAULT_IMPL caliptra_prim_pkg::ImplGeneric
 `endif
 
 // This is to prevent AscentLint warnings in the generated
@@ -14,7 +14,7 @@
 // use. TODO: we may want to move these inline waivers
 // into a separate, generated waiver file for consistency.
 //ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ HIER_BRANCH_NOT_READ
-module prim_flop_en
+module caliptra_prim_flop_en
 
 #(
 
@@ -29,10 +29,10 @@ module prim_flop_en
   input        [Width-1:0] d_i,
   output logic [Width-1:0] q_o
 );
-  parameter prim_pkg::impl_e Impl = `PRIM_DEFAULT_IMPL;
+  parameter caliptra_prim_pkg::impl_e Impl = `CALIPTRA_PRIM_DEFAULT_IMPL;
 
-if (Impl == prim_pkg::ImplXilinx) begin : gen_xilinx
-    prim_xilinx_flop_en #(
+if (Impl == caliptra_prim_pkg::ImplXilinx) begin : gen_xilinx
+    caliptra_prim_xilinx_flop_en #(
       .EnSecBuf(EnSecBuf),
       .ResetValue(ResetValue),
       .Width(Width)
@@ -40,7 +40,7 @@ if (Impl == prim_pkg::ImplXilinx) begin : gen_xilinx
       .*
     );
 end else begin : gen_generic
-    prim_generic_flop_en #(
+    caliptra_prim_generic_flop_en #(
       .EnSecBuf(EnSecBuf),
       .ResetValue(ResetValue),
       .Width(Width)
diff --git a/src/prim/rtl/prim_flop_macros.sv b/src/caliptra_prim/rtl/caliptra_prim_flop_macros.sv
similarity index 74%
rename from src/prim/rtl/prim_flop_macros.sv
rename to src/caliptra_prim/rtl/caliptra_prim_flop_macros.sv
index 5d5945866..7c72af795 100644
--- a/src/prim/rtl/prim_flop_macros.sv
+++ b/src/caliptra_prim/rtl/caliptra_prim_flop_macros.sv
@@ -3,15 +3,15 @@
 // SPDX-License-Identifier: Apache-2.0
 
 `ifndef PRIM_FLOP_MACROS_SV
-`define PRIM_FLOP_MACROS_SV
+`define CALIPTRA_PRIM_FLOP_MACROS_SV
 
 /////////////////////////////////////
 // Default Values for Macros below //
 /////////////////////////////////////
 
-`define PRIM_FLOP_CLK clk_i
-`define PRIM_FLOP_RST rst_ni
-`define PRIM_FLOP_RESVAL '0
+`define CALIPTRA_PRIM_FLOP_CLK clk_i
+`define CALIPTRA_PRIM_FLOP_RST rst_ni
+`define CALIPTRA_PRIM_FLOP_RESVAL '0
 
 /////////////////////
 // Register Macros //
@@ -21,7 +21,7 @@
 // to make the code more concise.
 
 // Register with asynchronous reset.
-`define PRIM_FLOP_A(__d, __q, __resval = `PRIM_FLOP_RESVAL, __clk = `PRIM_FLOP_CLK, __rst_n = `PRIM_FLOP_RST) \
+`define CALIPTRA_PRIM_FLOP_A(__d, __q, __resval = `CALIPTRA_PRIM_FLOP_RESVAL, __clk = `CALIPTRA_PRIM_FLOP_CLK, __rst_n = `CALIPTRA_PRIM_FLOP_RST) \
   always_ff @(posedge __clk or negedge __rst_n) begin \
     if (!__rst_n) begin                               \
       __q <= __resval;                                \
@@ -38,27 +38,27 @@
 // like Xcelium and VCS seem to have problems inferring FSMs if the state register is not coded in
 // a behavioral always_ff block in the same hierarchy. To that end, this uses a modified variant
 // with a second behavioral register definition for RTL simulations so that FSMs can be inferred.
-// Note that in this variant, the __q output is disconnected from prim_sparse_fsm_flop and attached
+// Note that in this variant, the __q output is disconnected from caliptra_prim_sparse_fsm_flop and attached
 // to the behavioral flop. An assertion is added to ensure equivalence between the
-// prim_sparse_fsm_flop output and the behavioral flop output in that case.
-`define PRIM_FLOP_SPARSE_FSM(__name, __d, __q, __type, __resval = `PRIM_FLOP_RESVAL, __clk = `PRIM_FLOP_CLK, __rst_n = `PRIM_FLOP_RST, __alert_trigger_sva_en = 1) \
-  `ifdef SIMULATION                                   \
-    prim_sparse_fsm_flop #(                           \
+// caliptra_prim_sparse_fsm_flop output and the behavioral flop output in that case.
+`define CALIPTRA_PRIM_FLOP_SPARSE_FSM(__name, __d, __q, __type, __resval = `CALIPTRA_PRIM_FLOP_RESVAL, __clk = `CALIPTRA_PRIM_FLOP_CLK, __rst_n = `CALIPTRA_PRIM_FLOP_RST, __alert_trigger_sva_en = 1) \
+  `ifdef CALIPTRA_SIMULATION                                   \
+    caliptra_prim_sparse_fsm_flop #(                           \
       .StateEnumT(__type),                            \
       .Width($bits(__type)),                          \
       .ResetValue($bits(__type)'(__resval)),          \
       .EnableAlertTriggerSVA(__alert_trigger_sva_en), \
-      .CustomForceName(`PRIM_STRINGIFY(__q))          \
+      .CustomForceName(`CALIPTRA_PRIM_STRINGIFY(__q))          \
     ) __name (                                        \
       .clk_i   ( __clk   ),                           \
       .rst_ni  ( __rst_n ),                           \
       .state_i ( __d     ),                           \
       .state_o (         )                            \
     );                                                \
-    `PRIM_FLOP_A(__d, __q, __resval, __clk, __rst_n)  \
+    `CALIPTRA_PRIM_FLOP_A(__d, __q, __resval, __clk, __rst_n)  \
     `CALIPTRA_ASSERT(``__name``_A, __q === ``__name``.state_o) \
   `else                                               \
-    prim_sparse_fsm_flop #(                           \
+    caliptra_prim_sparse_fsm_flop #(                           \
       .StateEnumT(__type),                            \
       .Width($bits(__type)),                          \
       .ResetValue($bits(__type)'(__resval)),          \
diff --git a/src/prim/rtl/prim_intr_hw.sv b/src/caliptra_prim/rtl/caliptra_prim_intr_hw.sv
similarity index 99%
rename from src/prim/rtl/prim_intr_hw.sv
rename to src/caliptra_prim/rtl/caliptra_prim_intr_hw.sv
index 15aae5eb2..f9a8fdbc8 100644
--- a/src/prim/rtl/prim_intr_hw.sv
+++ b/src/caliptra_prim/rtl/caliptra_prim_intr_hw.sv
@@ -7,7 +7,7 @@
 // This module can be instantiated once per interrupt field, or
 // "bussified" with all fields of the interrupt vector.
 
-module prim_intr_hw # (
+module caliptra_prim_intr_hw # (
   parameter int unsigned Width = 1,
   parameter bit FlopOutput = 1,
 
diff --git a/src/prim/rtl/prim_lc_sync.sv b/src/caliptra_prim/rtl/caliptra_prim_lc_sync.sv
similarity index 94%
rename from src/prim/rtl/prim_lc_sync.sv
rename to src/caliptra_prim/rtl/caliptra_prim_lc_sync.sv
index b33600d25..5f83c11e6 100644
--- a/src/prim/rtl/prim_lc_sync.sv
+++ b/src/caliptra_prim/rtl/caliptra_prim_lc_sync.sv
@@ -8,9 +8,9 @@
 // Should be used exactly as recommended in the life cycle controller spec:
 // https://docs.opentitan.org/hw/ip/lc_ctrl/doc/index.html#control-signal-propagation
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
-module prim_lc_sync #(
+module caliptra_prim_lc_sync #(
   // Number of separately buffered output signals.
   // The buffer cells have a don't touch constraint
   // on them such that synthesis tools won't collapse
@@ -37,10 +37,10 @@ module prim_lc_sync #(
 
   logic [lc_ctrl_pkg::TxWidth-1:0] lc_en;
   if (AsyncOn) begin : gen_flops
-    prim_flop_2sync #(
+    caliptra_prim_flop_2sync #(
       .Width(lc_ctrl_pkg::TxWidth),
       .ResetValue(lc_ctrl_pkg::TxWidth'(LcResetValue))
-    ) u_prim_flop_2sync (
+    ) u_caliptra_prim_flop_2sync (
       .clk_i,
       .rst_ni,
       .d_i(lc_en_i),
@@ -62,7 +62,7 @@ module prim_lc_sync #(
 // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
 // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
 // sampling mismatches.
-`ifdef INC_ASSERT
+`ifdef CALIPTRA_INC_ASSERT
       lc_ctrl_pkg::lc_tx_t lc_en_in_sva_q;
       always_ff @(posedge clk_i) begin
         lc_en_in_sva_q <= lc_en_i;
@@ -99,7 +99,7 @@ module prim_lc_sync #(
   for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
     logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
     for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
-      prim_sec_anchor_buf u_prim_buf (
+      caliptra_prim_sec_anchor_buf u_caliptra_prim_buf (
         .in_i(lc_en[k]),
         .out_o(lc_en_out[k])
       );
@@ -114,4 +114,4 @@ module prim_lc_sync #(
   // The outputs should be known at all times.
   `CALIPTRA_ASSERT_KNOWN(OutputsKnown_A, lc_en_o)
 
-endmodule : prim_lc_sync
+endmodule : caliptra_prim_lc_sync
diff --git a/src/prim/rtl/prim_lfsr.sv b/src/caliptra_prim/rtl/caliptra_prim_lfsr.sv
similarity index 97%
rename from src/prim/rtl/prim_lfsr.sv
rename to src/caliptra_prim/rtl/caliptra_prim_lfsr.sv
index 1b6e11278..8801ef48f 100644
--- a/src/prim/rtl/prim_lfsr.sv
+++ b/src/caliptra_prim/rtl/caliptra_prim_lfsr.sv
@@ -24,9 +24,9 @@
 //       [2] https://users.ece.cmu.edu/~koopman/lfsr/
 //       [3] https://www.xilinx.com/support/documentation/application_notes/xapp052.pdf
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
-module prim_lfsr #(
+module caliptra_prim_lfsr #(
   // Lfsr Type, can be FIB_XNOR or GAL_XOR
   parameter                    LfsrType     = "GAL_XOR",
   // Lfsr width
@@ -312,21 +312,21 @@ module prim_lfsr #(
   logic [LfsrDw-1:0] next_lfsr_state, coeffs;
 
   // Enable the randomization of DefaultSeed using DefaultSeedLocal in DV simulations.
-  `ifdef SIMULATION
+  `ifdef CALIPTRA_SIMULATION
   `ifdef VERILATOR
       localparam logic [LfsrDw-1:0] DefaultSeedLocal = DefaultSeed;
 
   `else
     logic [LfsrDw-1:0] DefaultSeedLocal;
-    logic prim_lfsr_use_default_seed;
+    logic caliptra_prim_lfsr_use_default_seed;
 
     initial begin : p_randomize_default_seed
-      if (!$value$plusargs("prim_lfsr_use_default_seed=%0d", prim_lfsr_use_default_seed)) begin
+      if (!$value$plusargs("caliptra_prim_lfsr_use_default_seed=%0d", caliptra_prim_lfsr_use_default_seed)) begin
         // 30% of the time, use the DefaultSeed parameter; 70% of the time, randomize it.
-        `CALIPTRA_ASSERT_I(UseDefaultSeedRandomizeCheck_A, std::randomize(prim_lfsr_use_default_seed) with {
-                                                  prim_lfsr_use_default_seed dist {0:/7, 1:/3};})
+        `CALIPTRA_ASSERT_I(UseDefaultSeedRandomizeCheck_A, std::randomize(caliptra_prim_lfsr_use_default_seed) with {
+                                                  caliptra_prim_lfsr_use_default_seed dist {0:/7, 1:/3};})
       end
-      if (prim_lfsr_use_default_seed) begin
+      if (caliptra_prim_lfsr_use_default_seed) begin
         DefaultSeedLocal = DefaultSeed;
       end else begin
         // Randomize the DefaultSeedLocal ensuring its not all 0s or all 1s.
@@ -340,7 +340,7 @@ module prim_lfsr #(
   `else
     localparam logic [LfsrDw-1:0] DefaultSeedLocal = DefaultSeed;
 
-  `endif  // ifdef SIMULATION
+  `endif  // ifdef CALIPTRA_SIMULATION
 
   ////////////////
   // Galois XOR //
@@ -524,7 +524,7 @@ module prim_lfsr #(
                         lfsr_q[sbox_in_indices[k*4 + 2]],
                         lfsr_q[sbox_in_indices[k*4 + 1]],
                         lfsr_q[sbox_in_indices[k*4 + 0]]};
-      assign sbox_out[k*4 +: 4] = prim_cipher_pkg::PRINCE_SBOX4[sbox_in];
+      assign sbox_out[k*4 +: 4] = caliptra_prim_cipher_pkg::PRINCE_SBOX4[sbox_in];
     end
   end else begin : gen_out_passthru
     assign sbox_out = lfsr_q;
diff --git a/src/prim/rtl/prim_max_tree.sv b/src/caliptra_prim/rtl/caliptra_prim_max_tree.sv
similarity index 97%
rename from src/prim/rtl/prim_max_tree.sv
rename to src/caliptra_prim/rtl/caliptra_prim_max_tree.sv
index f218626ab..3b0f9b086 100644
--- a/src/prim/rtl/prim_max_tree.sv
+++ b/src/caliptra_prim/rtl/caliptra_prim_max_tree.sv
@@ -14,9 +14,9 @@
 // be equal to the input value at index 0.
 
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
-module prim_max_tree #(
+module caliptra_prim_max_tree #(
   parameter int NumSrc = 32,
   parameter int Width = 8,
   // Derived parameters
@@ -104,7 +104,7 @@ module prim_max_tree #(
   // Assertions //
   ////////////////
 
-`ifdef INC_ASSERT
+`ifdef CALIPTRA_INC_ASSERT
   //VCS coverage off
   // pragma coverage off
 
@@ -149,4 +149,4 @@ module prim_max_tree #(
   `CALIPTRA_ASSERT(MaxIndexComputationInvalid_A, !max_valid_o |-> max_idx_o == '0)
 `endif
 
-endmodule : prim_max_tree
+endmodule : caliptra_prim_max_tree
diff --git a/src/prim/rtl/prim_mubi4_sync.sv b/src/caliptra_prim/rtl/caliptra_prim_mubi4_sync.sv
similarity index 93%
rename from src/prim/rtl/prim_mubi4_sync.sv
rename to src/caliptra_prim/rtl/caliptra_prim_mubi4_sync.sv
index f0bfb06b5..572219fac 100644
--- a/src/prim/rtl/prim_mubi4_sync.sv
+++ b/src/caliptra_prim/rtl/caliptra_prim_mubi4_sync.sv
@@ -9,10 +9,10 @@
 //
 // Double-synchronizer flop for multibit signals with additional output buffers.
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
-module prim_mubi4_sync
-  import prim_mubi_pkg::*;
+module caliptra_prim_mubi4_sync
+  import caliptra_prim_mubi_pkg::*;
 #(
   // Number of separately buffered output signals.
   // The buffer cells have a don't touch constraint
@@ -43,10 +43,10 @@ module prim_mubi4_sync
   logic [MuBi4Width-1:0] mubi;
   if (AsyncOn) begin : gen_flops
     logic [MuBi4Width-1:0] mubi_sync;
-    prim_flop_2sync #(
+    caliptra_prim_flop_2sync #(
       .Width(MuBi4Width),
       .ResetValue(MuBi4Width'(ResetValue))
-    ) u_prim_flop_2sync (
+    ) u_caliptra_prim_flop_2sync (
       .clk_i,
       .rst_ni,
       .d_i(MuBi4Width'(mubi_i)),
@@ -55,10 +55,10 @@ module prim_mubi4_sync
 
     if (StabilityCheck) begin : gen_stable_chks
       logic [MuBi4Width-1:0] mubi_q;
-      prim_flop #(
+      caliptra_prim_flop #(
         .Width(MuBi4Width),
         .ResetValue(MuBi4Width'(ResetValue))
-      ) u_prim_flop_3rd_stage (
+      ) u_caliptra_prim_flop_3rd_stage (
         .clk_i,
         .rst_ni,
         .d_i(mubi_sync),
@@ -66,7 +66,7 @@ module prim_mubi4_sync
       );
 
       logic [MuBi4Width-1:0] sig_unstable;
-      prim_xor2 #(
+      caliptra_prim_xor2 #(
         .Width(MuBi4Width)
       ) u_mubi_xor (
         .in0_i(mubi_sync),
@@ -82,7 +82,7 @@ module prim_mubi4_sync
 
         // each mux gets its own buffered output, this ensures the OR-ing
         // cannot be defeated in one place.
-        prim_sec_anchor_buf #(
+        caliptra_prim_sec_anchor_buf #(
           .Width(MuBi4Width)
         ) u_sig_unstable_buf (
           .in_i(sig_unstable),
@@ -111,7 +111,7 @@ module prim_mubi4_sync
 // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
 // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
 // sampling mismatches.
-`ifdef INC_ASSERT
+`ifdef CALIPTRA_INC_ASSERT
       mubi4_t mubi_in_sva_q;
       always_ff @(posedge clk_i) begin
         mubi_in_sva_q <= mubi_i;
@@ -122,7 +122,7 @@ module prim_mubi4_sync
 `endif
     end else begin : gen_no_stable_chks
       assign mubi = mubi_sync;
-`ifdef INC_ASSERT
+`ifdef CALIPTRA_INC_ASSERT
       mubi4_t mubi_in_sva_q;
       always_ff @(posedge clk_i) begin
         mubi_in_sva_q <= mubi_i;
@@ -160,7 +160,7 @@ module prim_mubi4_sync
   for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
     logic [MuBi4Width-1:0] mubi_out;
     for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
-      prim_buf u_prim_buf (
+      caliptra_prim_buf u_caliptra_prim_buf (
         .in_i(mubi[k]),
         .out_o(mubi_out[k])
       );
@@ -175,4 +175,4 @@ module prim_mubi4_sync
   // The outputs should be known at all times.
   `CALIPTRA_ASSERT_KNOWN(OutputsKnown_A, mubi_o)
 
-endmodule : prim_mubi4_sync
+endmodule : caliptra_prim_mubi4_sync
diff --git a/src/prim/rtl/prim_mubi8_sync.sv b/src/caliptra_prim/rtl/caliptra_prim_mubi8_sync.sv
similarity index 93%
rename from src/prim/rtl/prim_mubi8_sync.sv
rename to src/caliptra_prim/rtl/caliptra_prim_mubi8_sync.sv
index f5696db62..dcc04fa90 100644
--- a/src/prim/rtl/prim_mubi8_sync.sv
+++ b/src/caliptra_prim/rtl/caliptra_prim_mubi8_sync.sv
@@ -9,10 +9,10 @@
 //
 // Double-synchronizer flop for multibit signals with additional output buffers.
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
-module prim_mubi8_sync
-  import prim_mubi_pkg::*;
+module caliptra_prim_mubi8_sync
+  import caliptra_prim_mubi_pkg::*;
 #(
   // Number of separately buffered output signals.
   // The buffer cells have a don't touch constraint
@@ -43,10 +43,10 @@ module prim_mubi8_sync
   logic [MuBi8Width-1:0] mubi;
   if (AsyncOn) begin : gen_flops
     logic [MuBi8Width-1:0] mubi_sync;
-    prim_flop_2sync #(
+    caliptra_prim_flop_2sync #(
       .Width(MuBi8Width),
       .ResetValue(MuBi8Width'(ResetValue))
-    ) u_prim_flop_2sync (
+    ) u_caliptra_prim_flop_2sync (
       .clk_i,
       .rst_ni,
       .d_i(MuBi8Width'(mubi_i)),
@@ -55,10 +55,10 @@ module prim_mubi8_sync
 
     if (StabilityCheck) begin : gen_stable_chks
       logic [MuBi8Width-1:0] mubi_q;
-      prim_flop #(
+      caliptra_prim_flop #(
         .Width(MuBi8Width),
         .ResetValue(MuBi8Width'(ResetValue))
-      ) u_prim_flop_3rd_stage (
+      ) u_caliptra_prim_flop_3rd_stage (
         .clk_i,
         .rst_ni,
         .d_i(mubi_sync),
@@ -66,7 +66,7 @@ module prim_mubi8_sync
       );
 
       logic [MuBi8Width-1:0] sig_unstable;
-      prim_xor2 #(
+      caliptra_prim_xor2 #(
         .Width(MuBi8Width)
       ) u_mubi_xor (
         .in0_i(mubi_sync),
@@ -82,7 +82,7 @@ module prim_mubi8_sync
 
         // each mux gets its own buffered output, this ensures the OR-ing
         // cannot be defeated in one place.
-        prim_sec_anchor_buf #(
+        caliptra_prim_sec_anchor_buf #(
           .Width(MuBi8Width)
         ) u_sig_unstable_buf (
           .in_i(sig_unstable),
@@ -111,7 +111,7 @@ module prim_mubi8_sync
 // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
 // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
 // sampling mismatches.
-`ifdef INC_ASSERT
+`ifdef CALIPTRA_INC_ASSERT
       mubi8_t mubi_in_sva_q;
       always_ff @(posedge clk_i) begin
         mubi_in_sva_q <= mubi_i;
@@ -122,7 +122,7 @@ module prim_mubi8_sync
 `endif
     end else begin : gen_no_stable_chks
       assign mubi = mubi_sync;
-`ifdef INC_ASSERT
+`ifdef CALIPTRA_INC_ASSERT
       mubi8_t mubi_in_sva_q;
       always_ff @(posedge clk_i) begin
         mubi_in_sva_q <= mubi_i;
@@ -161,7 +161,7 @@ module prim_mubi8_sync
   for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
     logic [MuBi8Width-1:0] mubi_out;
     for (genvar k = 0; k < MuBi8Width; k++) begin : gen_bits
-      prim_buf u_prim_buf (
+      caliptra_prim_buf u_caliptra_prim_buf (
         .in_i(mubi[k]),
         .out_o(mubi_out[k])
       );
@@ -176,4 +176,4 @@ module prim_mubi8_sync
   // The outputs should be known at all times.
   `CALIPTRA_ASSERT_KNOWN(OutputsKnown_A, mubi_o)
 
-endmodule : prim_mubi8_sync
+endmodule : caliptra_prim_mubi8_sync
diff --git a/src/prim/rtl/prim_mubi_pkg.sv b/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv
similarity index 99%
rename from src/prim/rtl/prim_mubi_pkg.sv
rename to src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv
index 118f9ad60..cc474c97d 100644
--- a/src/prim/rtl/prim_mubi_pkg.sv
+++ b/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv
@@ -10,9 +10,9 @@
 // This package defines common multibit signal types, active high and active low values and
 // the corresponding functions to test whether the values are set or not.
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
-package prim_mubi_pkg;
+package caliptra_prim_mubi_pkg;
 
   //////////////////////////////////////////////
   // 4 Bit Multibit Type and Functions //
@@ -542,4 +542,4 @@ package prim_mubi_pkg;
     return mubi16_and(a, b, MuBi16False);
   endfunction : mubi16_and_lo
 
-endpackage : prim_mubi_pkg
+endpackage : caliptra_prim_mubi_pkg
diff --git a/src/prim/rtl/prim_onehot_check.sv b/src/caliptra_prim/rtl/caliptra_prim_onehot_check.sv
similarity index 93%
rename from src/prim/rtl/prim_onehot_check.sv
rename to src/caliptra_prim/rtl/caliptra_prim_onehot_check.sv
index 47d5ff4e3..e5bfcb450 100644
--- a/src/prim/rtl/prim_onehot_check.sv
+++ b/src/caliptra_prim/rtl/caliptra_prim_onehot_check.sv
@@ -16,9 +16,9 @@
 // All checks make use of an explicit binary tree implementation in order to minimize the delay.
 //
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
-module prim_onehot_check #(
+module caliptra_prim_onehot_check #(
   parameter int unsigned AddrWidth   = 5,
   // The onehot width can be <= 2**AddrWidth and does not have to be a power of two.
   parameter int unsigned OneHotWidth = 2**AddrWidth,
@@ -139,17 +139,17 @@ module prim_onehot_check #(
 
   // This logic that will be assign to one, when user adds macro
   // CALIPTRA_ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ALERT to check the error with alert, in case that
-  // prim_onehot_check is used in design without adding this assertion check.
-  `ifdef INC_ASSERT
+  // caliptra_prim_onehot_check is used in design without adding this assertion check.
+  `ifdef CALIPTRA_INC_ASSERT
   `ifndef PRIM_DEFAULT_IMPL
-    `define PRIM_DEFAULT_IMPL prim_pkg::ImplGeneric
+    `define CALIPTRA_PRIM_DEFAULT_IMPL caliptra_prim_pkg::ImplGeneric
   `endif
-  parameter prim_pkg::impl_e Impl = `PRIM_DEFAULT_IMPL;
+  parameter caliptra_prim_pkg::impl_e Impl = `CALIPTRA_PRIM_DEFAULT_IMPL;
 
   logic unused_assert_connected;
   // TODO(#13337): only check generic for now. The path of this prim in other Impl may differ
-  if (Impl == prim_pkg::ImplGeneric) begin : gen_generic
+  if (Impl == caliptra_prim_pkg::ImplGeneric) begin : gen_generic
     `CALIPTRA_ASSERT_INIT_NET(AssertConnected_A, unused_assert_connected === 1'b1 || !EnableAlertTriggerSVA)
   end
   `endif
-endmodule : prim_onehot_check
+endmodule : caliptra_prim_onehot_check
diff --git a/src/prim/rtl/prim_packer_fifo.sv b/src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv
similarity index 98%
rename from src/prim/rtl/prim_packer_fifo.sv
rename to src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv
index 095635ea3..24fdd1429 100644
--- a/src/prim/rtl/prim_packer_fifo.sv
+++ b/src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv
@@ -39,9 +39,9 @@
 // depth_o    0000000000|1111111111|00000000000000000000000000000000000000000
 
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
-module prim_packer_fifo #(
+module caliptra_prim_packer_fifo #(
   parameter int InW  = 32,
   parameter int OutW = 8,
   parameter bit ClearOnRead = 1'b1, // if == 1 always output 0 after read
diff --git a/src/prim/rtl/prim_pkg.sv b/src/caliptra_prim/rtl/caliptra_prim_pkg.sv
similarity index 85%
rename from src/prim/rtl/prim_pkg.sv
rename to src/caliptra_prim/rtl/caliptra_prim_pkg.sv
index 938bf7390..97242c359 100755
--- a/src/prim/rtl/prim_pkg.sv
+++ b/src/caliptra_prim/rtl/caliptra_prim_pkg.sv
@@ -6,7 +6,7 @@
 
 // This file is auto-generated.
 
-package prim_pkg;
+package caliptra_prim_pkg;
 
   // Implementation target specialization
   typedef enum integer {
@@ -14,4 +14,4 @@ package prim_pkg;
     ImplXilinx,
     ImplBadbit
   } impl_e;
-endpackage : prim_pkg
+endpackage : caliptra_prim_pkg
diff --git a/src/prim/rtl/prim_reg_we_check.sv b/src/caliptra_prim/rtl/caliptra_prim_reg_we_check.sv
similarity index 82%
rename from src/prim/rtl/prim_reg_we_check.sv
rename to src/caliptra_prim/rtl/caliptra_prim_reg_we_check.sv
index 51373ca37..a55c2fea9 100644
--- a/src/prim/rtl/prim_reg_we_check.sv
+++ b/src/caliptra_prim/rtl/caliptra_prim_reg_we_check.sv
@@ -5,9 +5,9 @@
 // Spurious write-enable checker for autogenerated CSR node.
 // This module has additional simulation features for error injection testing.
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
-module prim_reg_we_check #(
+module caliptra_prim_reg_we_check #(
   parameter int unsigned OneHotWidth  = 32
 ) (
   // The module is combinational - the clock and reset are only used for assertions.
@@ -22,16 +22,16 @@ module prim_reg_we_check #(
 
   // Prevent optimization of the onehot input buffer.
   logic [OneHotWidth-1:0] oh_buf;
-  prim_buf #(
+  caliptra_prim_buf #(
     .Width(OneHotWidth)
-  ) u_prim_buf (
+  ) u_caliptra_prim_buf (
     .in_i(oh_i),
     .out_o(oh_buf)
   );
 
-  prim_onehot_check #(
+  caliptra_prim_onehot_check #(
     .OneHotWidth(OneHotWidth),
-    .AddrWidth  (prim_util_pkg::vbits(OneHotWidth)),
+    .AddrWidth  (caliptra_prim_util_pkg::vbits(OneHotWidth)),
     .EnableCheck(1),
     // Since certain peripherals may have a very large address space
     // (e.g. > 20bit), the inverse address decoding check (which is
@@ -42,7 +42,7 @@ module prim_reg_we_check #(
     // we do not perform strict checks. I.e., we allow cases
     // where en_i is set to 1, but the oh_i vector is all-zeroes.
     .StrictCheck(0)
-  ) u_prim_onehot_check (
+  ) u_caliptra_prim_onehot_check (
     .clk_i,
     .rst_ni,
     .oh_i(oh_buf),
@@ -51,4 +51,4 @@ module prim_reg_we_check #(
     .err_o
   );
 
-endmodule : prim_reg_we_check
+endmodule : caliptra_prim_reg_we_check
diff --git a/src/prim/rtl/prim_sec_anchor_buf.sv b/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_buf.sv
similarity index 77%
rename from src/prim/rtl/prim_sec_anchor_buf.sv
rename to src/caliptra_prim/rtl/caliptra_prim_sec_anchor_buf.sv
index 1ea71841a..ae8753ad4 100644
--- a/src/prim/rtl/prim_sec_anchor_buf.sv
+++ b/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_buf.sv
@@ -2,16 +2,16 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
-module prim_sec_anchor_buf #(
+module caliptra_prim_sec_anchor_buf #(
   parameter int Width = 1
 ) (
   input        [Width-1:0] in_i,
   output logic [Width-1:0] out_o
 );
 
-  prim_buf #(
+  caliptra_prim_buf #(
     .Width(Width)
   ) u_secure_anchor_buf (
     .in_i,
diff --git a/src/prim/rtl/prim_sec_anchor_flop.sv b/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_flop.sv
similarity index 83%
rename from src/prim/rtl/prim_sec_anchor_flop.sv
rename to src/caliptra_prim/rtl/caliptra_prim_sec_anchor_flop.sv
index ce18b47d4..c475864b6 100644
--- a/src/prim/rtl/prim_sec_anchor_flop.sv
+++ b/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_flop.sv
@@ -2,9 +2,9 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
-module prim_sec_anchor_flop #(
+module caliptra_prim_sec_anchor_flop #(
   parameter int               Width      = 1,
   parameter logic [Width-1:0] ResetValue = 0
 ) (
@@ -14,7 +14,7 @@ module prim_sec_anchor_flop #(
   output logic [Width-1:0] q_o
 );
 
-  prim_flop #(
+  caliptra_prim_flop #(
     .Width(Width),
     .ResetValue(ResetValue)
   ) u_secure_anchor_flop (
diff --git a/src/prim/rtl/prim_slicer.sv b/src/caliptra_prim/rtl/caliptra_prim_slicer.sv
similarity index 91%
rename from src/prim/rtl/prim_slicer.sv
rename to src/caliptra_prim/rtl/caliptra_prim_slicer.sv
index 370158858..33493f03b 100644
--- a/src/prim/rtl/prim_slicer.sv
+++ b/src/caliptra_prim/rtl/caliptra_prim_slicer.sv
@@ -5,9 +5,9 @@
 // Slicer chops the incoming bitstring into OutW granularity.
 // It supports fractional InW/OutW which fills 0 at the end of message.
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
-module prim_slicer #(
+module caliptra_prim_slicer #(
   parameter int InW = 64,
   parameter int OutW = 8,
 
diff --git a/src/prim/rtl/prim_sparse_fsm_flop.sv b/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_flop.sv
similarity index 80%
rename from src/prim/rtl/prim_sparse_fsm_flop.sv
rename to src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_flop.sv
index 846eb9665..b0483a7a5 100644
--- a/src/prim/rtl/prim_sparse_fsm_flop.sv
+++ b/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_flop.sv
@@ -2,20 +2,22 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
-module prim_sparse_fsm_flop #(
+module caliptra_prim_sparse_fsm_flop
+  import caliptra_prim_sparse_fsm_pkg::*;
+#(
   parameter int               Width      = 1,
-  parameter type              StateEnumT = logic [Width-1:0],
+  parameter type              StateEnumT = state_t,
   parameter logic [Width-1:0] ResetValue = '0,
   // This should only be disabled in special circumstances, for example
   // in non-comportable IPs where an error does not trigger an alert.
   parameter bit               EnableAlertTriggerSVA = 1
-`ifdef SIMULATION
+`ifdef CALIPTRA_SIMULATION
   ,
   // In case this parameter is set to a non-empty string, the
-  // prim_sparse_fsm_flop_if will also force the signal with this name
-  // in the parent module that instantiates prim_sparse_fsm_flop.
+  // caliptra_prim_sparse_fsm_flop_if will also force the signal with this name
+  // in the parent module that instantiates caliptra_prim_sparse_fsm_flop.
   parameter string            CustomForceName = ""
 `endif
 ) (
@@ -28,7 +30,7 @@ module prim_sparse_fsm_flop #(
   logic unused_err_o;
 
   logic [Width-1:0] state_raw;
-  prim_flop #(
+  caliptra_prim_flop #(
     .Width(Width),
     .ResetValue(ResetValue)
   ) u_state_flop (
@@ -39,7 +41,7 @@ module prim_sparse_fsm_flop #(
   );
   assign state_o = StateEnumT'(state_raw);
 
-  `ifdef INC_ASSERT
+  `ifdef CALIPTRA_INC_ASSERT
   assign unused_err_o = is_undefined_state(state_o);
 
   function automatic logic is_undefined_state(StateEnumT sig);
@@ -58,7 +60,7 @@ module prim_sparse_fsm_flop #(
   // If CALIPTRA_ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT is declared, the unused_assert_connected signal will
   // be set to 1 and the below check will pass.
   // If the assertion is not declared however, the statement below will fail.
-  `ifdef INC_ASSERT
+  `ifdef CALIPTRA_INC_ASSERT
   logic unused_assert_connected;
 
   `CALIPTRA_ASSERT_INIT_NET(AssertConnected_A, unused_assert_connected === 1'b1 || !EnableAlertTriggerSVA)
diff --git a/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv b/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv
new file mode 100644
index 000000000..5f0b716c4
--- /dev/null
+++ b/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv
@@ -0,0 +1,7 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+package caliptra_prim_sparse_fsm_pkg;
+  typedef enum logic {Idle, Done} state_t;
+endpackage : caliptra_prim_sparse_fsm_pkg
diff --git a/src/prim/rtl/prim_subreg.sv b/src/caliptra_prim/rtl/caliptra_prim_subreg.sv
similarity index 93%
rename from src/prim/rtl/prim_subreg.sv
rename to src/caliptra_prim/rtl/caliptra_prim_subreg.sv
index 1215e430f..8bb91d955 100644
--- a/src/prim/rtl/prim_subreg.sv
+++ b/src/caliptra_prim/rtl/caliptra_prim_subreg.sv
@@ -4,8 +4,8 @@
 //
 // Register slice conforming to Comportibility guide.
 
-module prim_subreg
-  import prim_subreg_pkg::*;
+module caliptra_prim_subreg
+  import caliptra_prim_subreg_pkg::*;
 #(
   parameter int            DW       = 32,
   parameter sw_access_e    SwAccess = SwAccessRW,
@@ -37,7 +37,7 @@ module prim_subreg
   logic          wr_en;
   logic [DW-1:0] wr_data;
 
-  prim_subreg_arb #(
+  caliptra_prim_subreg_arb #(
     .DW       ( DW       ),
     .SwAccess ( SwAccess )
   ) wr_en_data_arb (
diff --git a/src/prim/rtl/prim_subreg_arb.sv b/src/caliptra_prim/rtl/caliptra_prim_subreg_arb.sv
similarity index 97%
rename from src/prim/rtl/prim_subreg_arb.sv
rename to src/caliptra_prim/rtl/caliptra_prim_subreg_arb.sv
index 80033366c..d660a5465 100644
--- a/src/prim/rtl/prim_subreg_arb.sv
+++ b/src/caliptra_prim/rtl/caliptra_prim_subreg_arb.sv
@@ -4,8 +4,8 @@
 //
 // Write enable and data arbitration logic for register slice conforming to Comportibility guide.
 
-module prim_subreg_arb
-  import prim_subreg_pkg::*;
+module caliptra_prim_subreg_arb
+  import caliptra_prim_subreg_pkg::*;
 #(
   parameter int         DW       = 32,
   parameter sw_access_e SwAccess = SwAccessRW
diff --git a/src/prim/rtl/prim_subreg_ext.sv b/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv
similarity index 95%
rename from src/prim/rtl/prim_subreg_ext.sv
rename to src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv
index 30a40c60c..217d11c66 100644
--- a/src/prim/rtl/prim_subreg_ext.sv
+++ b/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv
@@ -4,7 +4,7 @@
 //
 // Register slice conforming to Comportibility guide.
 
-module prim_subreg_ext #(
+module caliptra_prim_subreg_ext #(
   parameter int unsigned DW = 32
 ) (
   input          re,
diff --git a/src/prim/rtl/prim_subreg_pkg.sv b/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv
similarity index 94%
rename from src/prim/rtl/prim_subreg_pkg.sv
rename to src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv
index 6e1da0436..7e374d1b1 100644
--- a/src/prim/rtl/prim_subreg_pkg.sv
+++ b/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv
@@ -2,7 +2,7 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
-package prim_subreg_pkg;
+package caliptra_prim_subreg_pkg;
 
   // Register access specifier
   typedef enum logic [2:0] {
diff --git a/src/prim/rtl/prim_sum_tree.sv b/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv
similarity index 95%
rename from src/prim/rtl/prim_sum_tree.sv
rename to src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv
index 8961d1f83..be17bc1b0 100644
--- a/src/prim/rtl/prim_sum_tree.sv
+++ b/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv
@@ -2,7 +2,7 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
-// Based on prim_max_tree, this module implements an explicit binary tree to find the
+// Based on caliptra_prim_max_tree, this module implements an explicit binary tree to find the
 // sum of this inputs. The solution has O(N) area and O(log(N)) delay complexity, and
 // thus scales well with many input sources.
 //
@@ -10,9 +10,9 @@
 // Invalid values are treated as 0.
 //
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
-module prim_sum_tree #(
+module caliptra_prim_sum_tree #(
   parameter int NumSrc = 32,
   parameter int Width = 8
 ) (
@@ -95,7 +95,7 @@ module prim_sum_tree #(
   // Assertions //
   ////////////////
 
-`ifdef INC_ASSERT
+`ifdef CALIPTRA_INC_ASSERT
   //VCS coverage off
   // pragma coverage off
 
@@ -121,4 +121,4 @@ module prim_sum_tree #(
   `CALIPTRA_ASSERT(SumComputationInvalid_A, !sum_valid_o |-> sum_value_o == '0)
 `endif
 
-endmodule : prim_sum_tree
+endmodule : caliptra_prim_sum_tree
diff --git a/src/prim/rtl/prim_util_pkg.sv b/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv
similarity index 98%
rename from src/prim/rtl/prim_util_pkg.sv
rename to src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv
index f5e3c92af..4a6f7c7a9 100644
--- a/src/prim/rtl/prim_util_pkg.sv
+++ b/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv
@@ -6,7 +6,7 @@
 /**
  * Utility functions
  */
-package prim_util_pkg;
+package caliptra_prim_util_pkg;
   /**
    * Math function: $clog2 as specified in Verilog-2005
    *
@@ -86,7 +86,7 @@ package prim_util_pkg;
 `endif
   endfunction
 
-`ifdef INC_ASSERT
+`ifdef CALIPTRA_INC_ASSERT
   // Package-scoped variable to detect the end of simulation.
   //
   // Used only in DV simulations. The bit will be used by assertions in RTL to perform end-of-test
diff --git a/src/caliptra_prim_generic/config/caliptra_prim_generic.vf b/src/caliptra_prim_generic/config/caliptra_prim_generic.vf
new file mode 100644
index 000000000..38af67734
--- /dev/null
+++ b/src/caliptra_prim_generic/config/caliptra_prim_generic.vf
@@ -0,0 +1,4 @@
++incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv
diff --git a/src/caliptra_prim_generic/config/compile.yml b/src/caliptra_prim_generic/config/compile.yml
new file mode 100644
index 000000000..f18389093
--- /dev/null
+++ b/src/caliptra_prim_generic/config/compile.yml
@@ -0,0 +1,10 @@
+---
+provides: [caliptra_prim_generic]
+schema_version: 2.4.0
+targets:
+  rtl:
+    directories: [$COMPILE_ROOT/rtl]
+    files:
+      - $COMPILE_ROOT/rtl/caliptra_prim_generic_flop_en.sv
+      - $COMPILE_ROOT/rtl/caliptra_prim_generic_flop.sv
+      - $COMPILE_ROOT/rtl/caliptra_prim_generic_buf.sv
diff --git a/src/prim_generic/rtl/prim_generic_buf.sv b/src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv
similarity index 82%
rename from src/prim_generic/rtl/prim_generic_buf.sv
rename to src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv
index 1b2fbffad..02d5b7da7 100644
--- a/src/prim_generic/rtl/prim_generic_buf.sv
+++ b/src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv
@@ -2,9 +2,9 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
-module prim_generic_buf #(
+module caliptra_prim_generic_buf #(
   parameter int Width = 1
 ) (
   input        [Width-1:0] in_i,
diff --git a/src/prim_generic/rtl/prim_generic_flop.sv b/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv
similarity index 88%
rename from src/prim_generic/rtl/prim_generic_flop.sv
rename to src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv
index 67b6e8906..4bce14585 100644
--- a/src/prim_generic/rtl/prim_generic_flop.sv
+++ b/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv
@@ -2,9 +2,9 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
-module prim_generic_flop #(
+module caliptra_prim_generic_flop #(
   parameter int               Width      = 1,
   parameter logic [Width-1:0] ResetValue = 0
 ) (
diff --git a/src/prim_generic/rtl/prim_generic_flop_en.sv b/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv
similarity index 88%
rename from src/prim_generic/rtl/prim_generic_flop_en.sv
rename to src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv
index 3c367b735..0a6ffba17 100644
--- a/src/prim_generic/rtl/prim_generic_flop_en.sv
+++ b/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv
@@ -2,9 +2,9 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
-module prim_generic_flop_en #(
+module caliptra_prim_generic_flop_en #(
   parameter int               Width      = 1,
   parameter bit               EnSecBuf   = 0,
   parameter logic [Width-1:0] ResetValue = 0
@@ -18,7 +18,7 @@ module prim_generic_flop_en #(
 
   logic en;
   if (EnSecBuf) begin : gen_en_sec_buf
-    prim_sec_anchor_buf #(
+    caliptra_prim_sec_anchor_buf #(
       .Width(1)
     ) u_en_buf (
       .in_i(en_i),
diff --git a/src/csrng/config/compile.yml b/src/csrng/config/compile.yml
index 2c4db93c2..146c5653c 100644
--- a/src/csrng/config/compile.yml
+++ b/src/csrng/config/compile.yml
@@ -1,6 +1,8 @@
 ---
 provides: [csrng_pkg]
 schema_version: 2.4.0
+requires:
+  - entropy_src_pkg
 targets:
   rtl:
     directories: [$COMPILE_ROOT/rtl]
@@ -17,8 +19,8 @@ provides: [csrng]
 schema_version: 2.4.0
 requires:
   - libs
-  - prim_generic
-  - prim
+  - caliptra_prim_generic
+  - caliptra_prim
   - lc_ctrl_pkg
   - entropy_src_pkg
   - edn_pkg
diff --git a/src/csrng/config/csrng.vf b/src/csrng/config/csrng.vf
index 70811b6d7..ef06dd886 100644
--- a/src/csrng/config/csrng.vf
+++ b/src/csrng/config/csrng.vf
@@ -1,10 +1,10 @@
 +incdir+${CALIPTRA_ROOT}/src/integration/rtl
 +incdir+${CALIPTRA_ROOT}/src/libs/rtl
-+incdir+${CALIPTRA_ROOT}/src/prim/rtl
++incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl
 +incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl
 +incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl
 +incdir+${CALIPTRA_ROOT}/src/csrng/rtl
-+incdir+${CALIPTRA_ROOT}/src/prim_generic/rtl
++incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl
 +incdir+${CALIPTRA_ROOT}/src/edn/rtl
 +incdir+${CALIPTRA_ROOT}/src/aes/rtl
 ${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh
@@ -18,12 +18,14 @@ ${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_util_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_alert_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_mubi_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_cipher_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_pkg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv
 ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv
 ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv
@@ -34,37 +36,40 @@ ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_pkg.sv
 ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_pkg.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
-${CALIPTRA_ROOT}/src/prim_generic/rtl/prim_generic_flop.sv
-${CALIPTRA_ROOT}/src/prim_generic/rtl/prim_generic_buf.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_flop_2sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_lfsr.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_mubi4_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_diff_decode.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sec_anchor_buf.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_slicer.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_count.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sparse_fsm_flop.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_dom_and_2share.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sec_anchor_flop.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_reg_we_check.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_packer_fifo.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_max_tree.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg_arb.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_intr_hw.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_onehot_check.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_mubi8_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_fifo_sync_cnt.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_buf.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_lc_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_alert_receiver.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_flop.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_alert_sender.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_fifo_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_arbiter_ppc.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sum_tree.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg_ext.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_edge_detector.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_en.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cdc_rand_delay.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lfsr.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi4_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_diff_decode.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_slicer.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_count.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_dom_and_2share.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_reg_we_check.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_max_tree.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_arb.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_intr_hw.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_onehot_check.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi8_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync_cnt.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lc_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_receiver.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_sender.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv
 ${CALIPTRA_ROOT}/src/edn/rtl/edn_pkg.sv
 ${CALIPTRA_ROOT}/src/aes/rtl/aes_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/aes/rtl/aes_pkg.sv
@@ -96,4 +101,5 @@ ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_ctr_drbg_gen.sv
 ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_block_encrypt.sv
 ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_state_db.sv
 ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_cmd_stage.sv
-${CALIPTRA_ROOT}/src/csrng/rtl/csrng.sv
\ No newline at end of file
+${CALIPTRA_ROOT}/src/csrng/rtl/csrng.sv
+${CALIPTRA_ROOT}/src/csrng/tb/csrng_tb.sv
diff --git a/src/csrng/config/csrng.vlt b/src/csrng/config/csrng.vlt
index 9aba1faef..7ef75610e 100644
--- a/src/csrng/config/csrng.vlt
+++ b/src/csrng/config/csrng.vlt
@@ -1,6 +1,6 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
-${CALIPTRA_ROOT}/src/prim/lint/prim_onehot_check.vlt
-${CALIPTRA_ROOT}/src/prim/lint/prim_arbiter.vlt
+${CALIPTRA_ROOT}/src/caliptra_prim/lint/caliptra_prim_onehot_check.vlt
+${CALIPTRA_ROOT}/src/caliptra_prim/lint/caliptra_prim_arbiter.vlt
 ${CALIPTRA_ROOT}/src/csrng/lint/csrng.vlt
diff --git a/src/csrng/config/csrng_pkg.vf b/src/csrng/config/csrng_pkg.vf
index 5c3f2e165..6badfdba1 100644
--- a/src/csrng/config/csrng_pkg.vf
+++ b/src/csrng/config/csrng_pkg.vf
@@ -1,4 +1,9 @@
++incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl
 +incdir+${CALIPTRA_ROOT}/src/csrng/rtl
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm_pkg.sv
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_ack_sm_pkg.sv
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_reg_pkg.sv
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_pkg.sv
 ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_pkg.sv
 ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_pkg.sv
\ No newline at end of file
diff --git a/src/csrng/config/csrng_tb.vf b/src/csrng/config/csrng_tb.vf
index 71bd1fab4..4793e52ec 100644
--- a/src/csrng/config/csrng_tb.vf
+++ b/src/csrng/config/csrng_tb.vf
@@ -1,10 +1,10 @@
 +incdir+${CALIPTRA_ROOT}/src/integration/rtl
 +incdir+${CALIPTRA_ROOT}/src/libs/rtl
-+incdir+${CALIPTRA_ROOT}/src/prim/rtl
++incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl
 +incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl
 +incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl
 +incdir+${CALIPTRA_ROOT}/src/csrng/rtl
-+incdir+${CALIPTRA_ROOT}/src/prim_generic/rtl
++incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl
 +incdir+${CALIPTRA_ROOT}/src/edn/rtl
 +incdir+${CALIPTRA_ROOT}/src/aes/rtl
 +incdir+${CALIPTRA_ROOT}/src/csrng/tb
@@ -19,12 +19,14 @@ ${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_util_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_alert_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_mubi_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_cipher_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_pkg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv
 ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv
 ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv
@@ -35,37 +37,40 @@ ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_pkg.sv
 ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_pkg.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
-${CALIPTRA_ROOT}/src/prim_generic/rtl/prim_generic_flop.sv
-${CALIPTRA_ROOT}/src/prim_generic/rtl/prim_generic_buf.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_flop_2sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_lfsr.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_mubi4_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_diff_decode.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sec_anchor_buf.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_slicer.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_count.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sparse_fsm_flop.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_dom_and_2share.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sec_anchor_flop.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_reg_we_check.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_packer_fifo.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_max_tree.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg_arb.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_intr_hw.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_onehot_check.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_mubi8_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_fifo_sync_cnt.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_buf.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_lc_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_alert_receiver.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_flop.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_alert_sender.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_fifo_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_arbiter_ppc.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sum_tree.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg_ext.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_edge_detector.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_en.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cdc_rand_delay.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lfsr.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi4_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_diff_decode.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_slicer.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_count.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_dom_and_2share.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_reg_we_check.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_max_tree.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_arb.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_intr_hw.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_onehot_check.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi8_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync_cnt.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lc_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_receiver.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_sender.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv
 ${CALIPTRA_ROOT}/src/edn/rtl/edn_pkg.sv
 ${CALIPTRA_ROOT}/src/aes/rtl/aes_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/aes/rtl/aes_pkg.sv
@@ -98,4 +103,4 @@ ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_block_encrypt.sv
 ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_state_db.sv
 ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_cmd_stage.sv
 ${CALIPTRA_ROOT}/src/csrng/rtl/csrng.sv
-${CALIPTRA_ROOT}/src/csrng/tb/csrng_tb.sv
\ No newline at end of file
+${CALIPTRA_ROOT}/src/csrng/tb/csrng_tb.sv
diff --git a/src/csrng/data/csrng.hjson b/src/csrng/data/csrng.hjson
index 0c6c911f9..1748549ed 100644
--- a/src/csrng/data/csrng.hjson
+++ b/src/csrng/data/csrng.hjson
@@ -75,7 +75,7 @@
       type:    "uni"
       name:    "otp_en_csrng_sw_app_read"
       act:     "rcv"
-      package: "prim_mubi_pkg"
+      package: "caliptra_prim_mubi_pkg"
     }
     { struct:  "lc_tx"
       type:    "uni"
diff --git a/src/csrng/data/csrng.json b/src/csrng/data/csrng.json
index b25e5c086..d9c035aed 100644
--- a/src/csrng/data/csrng.json
+++ b/src/csrng/data/csrng.json
@@ -92,7 +92,7 @@
       "type": "uni",
       "name": "otp_en_csrng_sw_app_read",
       "act": "rcv",
-      "package": "prim_mubi_pkg"
+      "package": "caliptra_prim_mubi_pkg"
     },
     {
       "struct": "lc_tx",
diff --git a/src/csrng/lint/csrng.waiver b/src/csrng/lint/csrng.waiver
index 75a4e51a7..2c9b4c8a3 100644
--- a/src/csrng/lint/csrng.waiver
+++ b/src/csrng/lint/csrng.waiver
@@ -4,7 +4,7 @@
 #
 # waiver file for csrng
 
-waive -rules {ONE_BIT_MEM_WIDTH} -location {prim_arbiter_ppc.sv} -regexp {.*has word width which is single bit wide.*} \
+waive -rules {ONE_BIT_MEM_WIDTH} -location {caliptra_prim_arbiter_ppc.sv} -regexp {.*has word width which is single bit wide.*} \
       -comment "Usage case specific to CSRNG and how the arbiter is used."
 waive -rules {LHS_TOO_SHORT} -location {aes_cipher_control_fsm.sv aes_cipher_core.sv aes_key_expand.sv aes_sbox.sv} -regexp {Bitlength mismatch between 'unused_assert_static_lint_error' length 1 and.*} \
       -comment "CSRNG intentionally uses an unmasked AES implementation."
diff --git a/src/csrng/rtl/csrng.sv b/src/csrng/rtl/csrng.sv
index 70350a1f4..8aed50dba 100644
--- a/src/csrng/rtl/csrng.sv
+++ b/src/csrng/rtl/csrng.sv
@@ -4,7 +4,7 @@
 //
 // Description: csrng top level wrapper file
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
 module csrng
  import csrng_pkg::*;
@@ -38,7 +38,7 @@ module csrng
 
    // OTP Interface
   // SEC_CM: INTERSIG.MUBI
-  input  prim_mubi_pkg::mubi8_t otp_en_csrng_sw_app_read_i,
+  input  caliptra_prim_mubi_pkg::mubi8_t otp_en_csrng_sw_app_read_i,
 
   // Lifecycle broadcast inputs
   input  lc_ctrl_pkg::lc_tx_t  lc_hw_debug_en_i,
@@ -56,8 +56,8 @@ module csrng
   output csrng_rsp_t  [NHwApps-1:0] csrng_cmd_o,
 
   // Alerts
-  input  prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i,
-  output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o,
+  input  caliptra_prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i,
+  output caliptra_prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o,
 
   // Interrupts
   output logic    intr_cs_cmd_req_done_o,
@@ -144,10 +144,10 @@ module csrng
   // Alert generation
   ///////////////////////////
   for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx
-    prim_alert_sender #(
+    caliptra_prim_alert_sender #(
       .AsyncOn(AlertAsyncOn[i]),
       .IsFatal(i)
-    ) u_prim_alert_sender (
+    ) u_caliptra_prim_alert_sender (
       .clk_i,
       .rst_ni,
       .alert_test_i  (alert_test[i]                 ),
@@ -185,16 +185,16 @@ module csrng
   `CALIPTRA_ASSERT_KNOWN(IntrCsFatalErrKnownO_A, intr_cs_fatal_err_o)
 
   `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CtrDrbgUpdAlertCheck_A,
-    u_csrng_core.u_csrng_ctr_drbg_upd.u_prim_count_ctr_drbg,
+    u_csrng_core.u_csrng_ctr_drbg_upd.u_caliptra_prim_count_ctr_drbg,
     alert_tx_o[1])
 
   `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CtrDrbgGenAlertCheck_A,
-    u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_count_ctr_drbg,
+    u_csrng_core.u_csrng_ctr_drbg_gen.u_caliptra_prim_count_ctr_drbg,
     alert_tx_o[1])
 
   for (genvar i = 0; i < NHwApps + 1; i++) begin : gen_cnt_asserts
     `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntAlertCheck_A,
-      u_csrng_core.gen_cmd_stage[i].u_csrng_cmd_stage.u_prim_count_cmd_gen_cntr,
+      u_csrng_core.gen_cmd_stage[i].u_csrng_cmd_stage.u_caliptra_prim_count_cmd_gen_cntr,
       alert_tx_o[1])
 
     `CALIPTRA_ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(DrbgCmdFsmCheck_A,
diff --git a/src/csrng/rtl/csrng_block_encrypt.sv b/src/csrng/rtl/csrng_block_encrypt.sv
index 853e566f5..a05152b65 100644
--- a/src/csrng/rtl/csrng_block_encrypt.sv
+++ b/src/csrng/rtl/csrng_block_encrypt.sv
@@ -137,11 +137,11 @@ module csrng_block_encrypt import csrng_pkg::*; #(
   // cmd / id tracking fifo
   //--------------------------------------------
 
-  prim_fifo_sync #(
+  caliptra_prim_fifo_sync #(
     .Width(BlkEncFifoWidth),
     .Pass(0),
     .Depth(BlkEncFifoDepth)
-  ) u_prim_fifo_sync_blkenc (
+  ) u_caliptra_prim_fifo_sync_blkenc (
     .clk_i    (clk_i),
     .rst_ni   (rst_ni),
     .clr_i    (!block_encrypt_enable_i),
diff --git a/src/csrng/rtl/csrng_cmd_stage.sv b/src/csrng/rtl/csrng_cmd_stage.sv
index a8d1eae76..f62311e79 100644
--- a/src/csrng/rtl/csrng_cmd_stage.sv
+++ b/src/csrng/rtl/csrng_cmd_stage.sv
@@ -116,12 +116,12 @@ module csrng_cmd_stage import csrng_pkg::*; #(
   // Capture the transfer length of data behind the command.
   //---------------------------------------------------------
 
-  prim_fifo_sync #(
+  caliptra_prim_fifo_sync #(
     .Width(CmdFifoWidth),
     .Pass(0),
     .Depth(CmdFifoDepth),
     .OutputZeroIfEmpty(1'b0)
-  ) u_prim_fifo_cmd (
+  ) u_caliptra_prim_fifo_cmd (
     .clk_i          (clk_i),
     .rst_ni         (rst_ni),
     .clr_i          (!cs_enable_i),
@@ -180,10 +180,10 @@ module csrng_cmd_stage import csrng_pkg::*; #(
          cmd_gen_cmd_q;
 
   // SEC_CM: GEN_CMD.CTR.REDUN
-  prim_count #(
+  caliptra_prim_count #(
     .Width(GenBitsCntrWidth),
     .ResetValue({GenBitsCntrWidth{1'b1}})
-  ) u_prim_count_cmd_gen_cntr (
+  ) u_caliptra_prim_count_cmd_gen_cntr (
     .clk_i,
     .rst_ni,
     .clr_i(!cs_enable_i),
@@ -239,7 +239,7 @@ module csrng_cmd_stage import csrng_pkg::*; #(
   } state_e;
 
   state_e state_d, state_q;
-  `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Idle)
+  `CALIPTRA_PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Idle)
 
   always_comb begin
     state_d = state_q;
@@ -367,12 +367,12 @@ module csrng_cmd_stage import csrng_pkg::*; #(
   // Genbits FIFO.
   //---------------------------------------------------------
 
-  prim_fifo_sync #(
+  caliptra_prim_fifo_sync #(
     .Width(GenBitsFifoWidth),
     .Pass(0),
     .Depth(GenBitsFifoDepth),
     .OutputZeroIfEmpty(0) // Set to 0, and let last data drive out.
-  ) u_prim_fifo_genbits (
+  ) u_caliptra_prim_fifo_genbits (
     .clk_i          (clk_i),
     .rst_ni         (rst_ni),
     .clr_i          (!cs_enable_i),
diff --git a/src/csrng/rtl/csrng_core.sv b/src/csrng/rtl/csrng_core.sv
index 9aa6bf678..8fc153a01 100644
--- a/src/csrng/rtl/csrng_core.sv
+++ b/src/csrng/rtl/csrng_core.sv
@@ -19,7 +19,7 @@ module csrng_core import csrng_pkg::*; #(
   output csrng_reg_pkg::csrng_hw2reg_t            hw2reg,
 
   // Efuse Interface
-  input  prim_mubi_pkg::mubi8_t                   otp_en_csrng_sw_app_read_i,
+  input  caliptra_prim_mubi_pkg::mubi8_t                   otp_en_csrng_sw_app_read_i,
 
   // Lifecycle broadcast inputs
   input  lc_ctrl_pkg::lc_tx_t                     lc_hw_debug_en_i,
@@ -51,9 +51,9 @@ module csrng_core import csrng_pkg::*; #(
 
   import csrng_reg_pkg::*;
 
-  import prim_mubi_pkg::mubi4_t;
-  import prim_mubi_pkg::mubi4_test_true_strict;
-  import prim_mubi_pkg::mubi4_test_invalid;
+  import caliptra_prim_mubi_pkg::mubi4_t;
+  import caliptra_prim_mubi_pkg::mubi4_test_true_strict;
+  import caliptra_prim_mubi_pkg::mubi4_test_invalid;
 
   localparam int NApps = NHwApps + 1;
   localparam int AppCmdWidth = 32;
@@ -353,9 +353,9 @@ module csrng_core import csrng_pkg::*; #(
   logic                      unused_reg2hw_genbits;
   logic                      unused_int_state_val;
 
-  prim_mubi_pkg::mubi8_t [1:0] en_csrng_sw_app_read;
-  prim_mubi_pkg::mubi4_t [CsEnableCopies-1:0] mubi_cs_enable_fanout;
-  prim_mubi_pkg::mubi4_t [Flag0Copies-1:0] mubi_flag0_fanout;
+  caliptra_prim_mubi_pkg::mubi8_t [1:0] en_csrng_sw_app_read;
+  caliptra_prim_mubi_pkg::mubi4_t [CsEnableCopies-1:0] mubi_cs_enable_fanout;
+  caliptra_prim_mubi_pkg::mubi4_t [Flag0Copies-1:0] mubi_flag0_fanout;
 
   // flops
   logic [2:0]                acmd_q, acmd_d;
@@ -379,7 +379,7 @@ module csrng_core import csrng_pkg::*; #(
       acmd_q                  <= '0;
       shid_q                  <= '0;
       gen_last_q              <= '0;
-      flag0_q                 <= prim_mubi_pkg::MuBi4False;
+      flag0_q                 <= caliptra_prim_mubi_pkg::MuBi4False;
       cmd_arb_idx_q           <= '0;
       statedb_wr_select_q     <= '0;
       genbits_stage_fips_sw_q <= '0;
@@ -414,7 +414,7 @@ module csrng_core import csrng_pkg::*; #(
   //--------------------------------------------
   // All TLUL interrupts are collect in the section.
 
-  prim_intr_hw #(
+  caliptra_prim_intr_hw #(
     .Width(1)
   ) u_intr_hw_cs_cmd_req_done (
     .clk_i                  (clk_i),
@@ -429,7 +429,7 @@ module csrng_core import csrng_pkg::*; #(
     .intr_o                 (intr_cs_cmd_req_done_o)
   );
 
-  prim_intr_hw #(
+  caliptra_prim_intr_hw #(
     .Width(1)
   ) u_intr_hw_cs_entropy_req (
     .clk_i                  (clk_i),
@@ -445,7 +445,7 @@ module csrng_core import csrng_pkg::*; #(
   );
 
 
-  prim_intr_hw #(
+  caliptra_prim_intr_hw #(
     .Width(1)
   ) u_intr_hw_cs_hw_inst_exc (
     .clk_i                  (clk_i),
@@ -461,7 +461,7 @@ module csrng_core import csrng_pkg::*; #(
   );
 
 
-  prim_intr_hw #(
+  caliptra_prim_intr_hw #(
     .Width(1)
   ) u_intr_hw_cs_fatal_err (
     .clk_i                  (clk_i),
@@ -734,11 +734,11 @@ module csrng_core import csrng_pkg::*; #(
          cs_bus_cmp_alert;
 
 
-  prim_edge_detector #(
+  caliptra_prim_edge_detector #(
     .Width(1),
     .ResetValue(0),
     .EnSync(0)
-  ) u_prim_edge_detector_recov_alert (
+  ) u_caliptra_prim_edge_detector_recov_alert (
     .clk_i,
     .rst_ni,
     .d_i(recov_alert_event),
@@ -761,10 +761,10 @@ module csrng_core import csrng_pkg::*; #(
     assign cs_enable_fo[i] = mubi4_test_true_strict(mubi_cs_enable_fanout[i]);
   end : gen_mubi_en_copies
 
-  prim_mubi4_sync #(
+  caliptra_prim_mubi4_sync #(
     .NumCopies(CsEnableCopies),
     .AsyncOn(0)
-  ) u_prim_mubi4_sync_cs_enable (
+  ) u_caliptra_prim_mubi4_sync_cs_enable (
     .clk_i,
     .rst_ni,
     .mubi_i(mubi_cs_enable),
@@ -780,10 +780,10 @@ module csrng_core import csrng_pkg::*; #(
   assign hw2reg.recov_alert_sts.sw_app_enable_field_alert.de = sw_app_enable_pfa;
   assign hw2reg.recov_alert_sts.sw_app_enable_field_alert.d  = sw_app_enable_pfa;
 
-  prim_mubi4_sync #(
+  caliptra_prim_mubi4_sync #(
     .NumCopies(2),
     .AsyncOn(0)
-  ) u_prim_mubi4_sync_sw_app_enable (
+  ) u_caliptra_prim_mubi4_sync_sw_app_enable (
     .clk_i,
     .rst_ni,
     .mubi_i(mubi_sw_app_enable),
@@ -799,10 +799,10 @@ module csrng_core import csrng_pkg::*; #(
   assign hw2reg.recov_alert_sts.read_int_state_field_alert.de = read_int_state_pfa;
   assign hw2reg.recov_alert_sts.read_int_state_field_alert.d  = read_int_state_pfa;
 
-  prim_mubi4_sync #(
+  caliptra_prim_mubi4_sync #(
     .NumCopies(2),
     .AsyncOn(0)
-  ) u_prim_mubi4_sync_read_int_state (
+  ) u_caliptra_prim_mubi4_sync_read_int_state (
     .clk_i,
     .rst_ni,
     .mubi_i(mubi_read_int_state),
@@ -885,13 +885,13 @@ module csrng_core import csrng_pkg::*; #(
   assign hw2reg.genbits.d = (sw_app_enable && efuse_sw_app_enable[0]) ? genbits_stage_bus_sw : '0;
   assign genbits_stage_bus_rd_sw = reg2hw.genbits.re;
 
-  assign efuse_sw_app_enable[0] = prim_mubi_pkg::mubi8_test_true_strict(en_csrng_sw_app_read[0]);
-  assign efuse_sw_app_enable[1] = prim_mubi_pkg::mubi8_test_true_strict(en_csrng_sw_app_read[1]);
+  assign efuse_sw_app_enable[0] = caliptra_prim_mubi_pkg::mubi8_test_true_strict(en_csrng_sw_app_read[0]);
+  assign efuse_sw_app_enable[1] = caliptra_prim_mubi_pkg::mubi8_test_true_strict(en_csrng_sw_app_read[1]);
 
-  prim_mubi8_sync #(
+  caliptra_prim_mubi8_sync #(
     .NumCopies(2),
     .AsyncOn(1)
-  ) u_prim_mubi8_sync_sw_app_read (
+  ) u_caliptra_prim_mubi8_sync_sw_app_read (
     .clk_i,
     .rst_ni,
     .mubi_i(otp_en_csrng_sw_app_read_i),
@@ -900,11 +900,11 @@ module csrng_core import csrng_pkg::*; #(
 
   // pack the gen bits into a 32 bit register sized word
 
-  prim_packer_fifo #(
+  caliptra_prim_packer_fifo #(
     .InW(BlkLen),
     .OutW(32),
     .ClearOnRead(1'b0)
-  ) u_prim_packer_fifo_sw_genbits (
+  ) u_caliptra_prim_packer_fifo_sw_genbits (
     .clk_i    (clk_i),
     .rst_ni   (rst_ni),
     .clr_i    (!cs_enable_fo[29]),
@@ -1015,11 +1015,11 @@ module csrng_core import csrng_pkg::*; #(
   // Can't be fed directly to port-list per Synthesis failure
   assign cmd_arb_di = '{1'b0, 1'b0, 1'b0};
 
-  prim_arbiter_ppc #(
+  caliptra_prim_arbiter_ppc #(
     .EnDataPort(0),    // Ignore data port
     .N(NApps),  // Number of request ports
     .DW(1) // Data width
-  ) u_prim_arbiter_ppc_acmd (
+  ) u_caliptra_prim_arbiter_ppc_acmd (
     .clk_i    (clk_i),
     .rst_ni   (rst_ni),
     .req_chk_i(cs_enable_fo[1]),
@@ -1060,7 +1060,7 @@ module csrng_core import csrng_pkg::*; #(
          gen_last_q;
 
   assign flag0_d =
-         (!cs_enable_fo[35]) ? prim_mubi_pkg::MuBi4False :
+         (!cs_enable_fo[35]) ? caliptra_prim_mubi_pkg::MuBi4False :
          (acmd_sop && ((acmd_bus[2:0] == INS) || (acmd_bus[2:0] == RES))) ? flag0 :
          flag0_q;
 
@@ -1072,10 +1072,10 @@ module csrng_core import csrng_pkg::*; #(
     assign flag0_fo[i] = mubi4_test_true_strict(mubi_flag0_fanout[i]);
   end : gen_mubi_flag0_copies
 
-  prim_mubi4_sync #(
+  caliptra_prim_mubi4_sync #(
     .NumCopies(Flag0Copies),
     .AsyncOn(0)
-  ) u_prim_mubi4_sync_flag0 (
+  ) u_caliptra_prim_mubi4_sync_flag0 (
     .clk_i,
     .rst_ni,
     .mubi_i(mubi_flag0),
@@ -1131,11 +1131,11 @@ module csrng_core import csrng_pkg::*; #(
   end : gen_cmd_ack
 
 
-  prim_packer_fifo #(
+  caliptra_prim_packer_fifo #(
     .InW(32),
     .OutW(SeedLen),
     .ClearOnRead(1'b1)
-  ) u_prim_packer_fifo_adata (
+  ) u_caliptra_prim_packer_fifo_adata (
     .clk_i      (clk_i),
     .rst_ni     (rst_ni),
     .clr_i      (!cs_enable_fo[37] || packer_adata_clr),
@@ -1422,10 +1422,10 @@ module csrng_core import csrng_pkg::*; #(
 
   // update block  arbiter
 
-  prim_arbiter_ppc #(
+  caliptra_prim_arbiter_ppc #(
     .N(NUpdateArbReqs), // (cmd req and gen req)
     .DW(UpdateArbWidth) // Data width
-  ) u_prim_arbiter_ppc_updblk_arb (
+  ) u_caliptra_prim_arbiter_ppc_updblk_arb (
     .clk_i(clk_i),
     .rst_ni(rst_ni),
     .req_chk_i(cs_enable_fo[1]),
@@ -1464,9 +1464,9 @@ module csrng_core import csrng_pkg::*; #(
 
   lc_ctrl_pkg::lc_tx_t [LcHwDebugCopies-1:0] lc_hw_debug_en_out;
 
-  prim_lc_sync #(
+  caliptra_prim_lc_sync #(
     .NumCopies(LcHwDebugCopies)
-  ) u_prim_lc_sync (
+  ) u_caliptra_prim_lc_sync (
     .clk_i,
     .rst_ni,
     .lc_en_i(lc_hw_debug_en_i),
@@ -1515,10 +1515,10 @@ module csrng_core import csrng_pkg::*; #(
   );
 
 
-  prim_arbiter_ppc #(
+  caliptra_prim_arbiter_ppc #(
     .N(NBlkEncArbReqs), // (upd req and gen req)
     .DW(BlkEncArbWidth) // Data width
-  ) u_prim_arbiter_ppc_benblk_arb (
+  ) u_caliptra_prim_arbiter_ppc_benblk_arb (
     .clk_i(clk_i),
     .rst_ni(rst_ni),
     .req_chk_i(cs_enable_fo[1]),
diff --git a/src/csrng/rtl/csrng_ctr_drbg_cmd.sv b/src/csrng/rtl/csrng_ctr_drbg_cmd.sv
index d4df09ade..567cbbf24 100644
--- a/src/csrng/rtl/csrng_ctr_drbg_cmd.sv
+++ b/src/csrng/rtl/csrng_ctr_drbg_cmd.sv
@@ -138,12 +138,12 @@ module csrng_ctr_drbg_cmd import csrng_pkg::*; #(
   // input request fifo for staging cmd request
   //--------------------------------------------
 
-  prim_fifo_sync #(
+  caliptra_prim_fifo_sync #(
     .Width(CmdreqFifoWidth),
     .Pass(0),
     .Depth(CmdreqFifoDepth),
     .OutputZeroIfEmpty(1'b0)
-  ) u_prim_fifo_sync_cmdreq (
+  ) u_caliptra_prim_fifo_sync_cmdreq (
     .clk_i          (clk_i),
     .rst_ni         (rst_ni),
     .clr_i          (!ctr_drbg_cmd_enable_i),
@@ -235,12 +235,12 @@ module csrng_ctr_drbg_cmd import csrng_pkg::*; #(
   // fifo to stage rc and command, waiting for update block to ack
   //--------------------------------------------
 
-  prim_fifo_sync #(
+  caliptra_prim_fifo_sync #(
     .Width(RCStageFifoWidth),
     .Pass(0),
     .Depth(RCStageFifoDepth),
     .OutputZeroIfEmpty(1'b0)
-  ) u_prim_fifo_sync_rcstage (
+  ) u_caliptra_prim_fifo_sync_rcstage (
     .clk_i          (clk_i),
     .rst_ni         (rst_ni),
     .clr_i          (!ctr_drbg_cmd_enable_i),
@@ -274,12 +274,12 @@ module csrng_ctr_drbg_cmd import csrng_pkg::*; #(
   // final cmd block processing
   //--------------------------------------------
 
-  prim_fifo_sync #(
+  caliptra_prim_fifo_sync #(
     .Width(KeyVRCFifoWidth),
     .Pass(0),
     .Depth(KeyVRCFifoDepth),
     .OutputZeroIfEmpty(1'b0)
-  ) u_prim_fifo_sync_keyvrc (
+  ) u_caliptra_prim_fifo_sync_keyvrc (
     .clk_i          (clk_i),
     .rst_ni         (rst_ni),
     .clr_i          (!ctr_drbg_cmd_enable_i),
diff --git a/src/csrng/rtl/csrng_ctr_drbg_gen.sv b/src/csrng/rtl/csrng_ctr_drbg_gen.sv
index 2b2adfd3f..66aed6132 100644
--- a/src/csrng/rtl/csrng_ctr_drbg_gen.sv
+++ b/src/csrng/rtl/csrng_ctr_drbg_gen.sv
@@ -216,7 +216,7 @@ module csrng_ctr_drbg_gen import csrng_pkg::*; #(
   state_e state_d, state_q;
 
   // SEC_CM: UPDATE.FSM.SPARSE
-  `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ReqIdle)
+  `CALIPTRA_PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ReqIdle)
 
   always_ff @(posedge clk_i or negedge rst_ni)
     if (!rst_ni) begin
@@ -235,12 +235,12 @@ module csrng_ctr_drbg_gen import csrng_pkg::*; #(
   // input request fifo for staging gen request
   //--------------------------------------------
 
-  prim_fifo_sync #(
+  caliptra_prim_fifo_sync #(
     .Width(GenreqFifoWidth),
     .Pass(0),
     .Depth(GenreqFifoDepth),
     .OutputZeroIfEmpty(1'b0)
-  ) u_prim_fifo_sync_genreq (
+  ) u_caliptra_prim_fifo_sync_genreq (
     .clk_i          (clk_i),
     .rst_ni         (rst_ni),
     .clr_i          (!ctr_drbg_gen_enable_i),
@@ -289,9 +289,9 @@ module csrng_ctr_drbg_gen import csrng_pkg::*; #(
   end
 
   // SEC_CM: DRBG_GEN.CTR.REDUN
-  prim_count #(
+  caliptra_prim_count #(
     .Width(CtrLen)
-  ) u_prim_count_ctr_drbg (
+  ) u_caliptra_prim_count_ctr_drbg (
     .clk_i,
     .rst_ni,
     .clr_i(!ctr_drbg_gen_enable_i),
@@ -386,12 +386,12 @@ module csrng_ctr_drbg_gen import csrng_pkg::*; #(
   // fifo to stage key, v, rc, and adata, waiting for update block to ack
   //--------------------------------------------
 
-  prim_fifo_sync #(
+  caliptra_prim_fifo_sync #(
     .Width(AdstageFifoWidth),
     .Pass(0),
     .Depth(AdstageFifoDepth),
     .OutputZeroIfEmpty(1'b0)
-  ) u_prim_fifo_sync_adstage (
+  ) u_caliptra_prim_fifo_sync_adstage (
     .clk_i          (clk_i),
     .rst_ni         (rst_ni),
     .clr_i          (!ctr_drbg_gen_enable_i),
@@ -446,12 +446,12 @@ module csrng_ctr_drbg_gen import csrng_pkg::*; #(
   // block_encrypt response fifo from block encrypt
   //--------------------------------------------
 
-  prim_fifo_sync #(
+  caliptra_prim_fifo_sync #(
     .Width(BlkEncAckFifoWidth),
     .Pass(0),
     .Depth(BlkEncAckFifoDepth),
     .OutputZeroIfEmpty(1'b0)
-  ) u_prim_fifo_sync_bencack (
+  ) u_caliptra_prim_fifo_sync_bencack (
     .clk_i    (clk_i),
     .rst_ni   (rst_ni),
     .clr_i    (!ctr_drbg_gen_enable_i),
@@ -501,12 +501,12 @@ module csrng_ctr_drbg_gen import csrng_pkg::*; #(
   // fifo to stage rc, waiting for update block to ack
   //--------------------------------------------
 
-  prim_fifo_sync #(
+  caliptra_prim_fifo_sync #(
     .Width(RCStageFifoWidth),
     .Pass(0),
     .Depth(RCStageFifoDepth),
     .OutputZeroIfEmpty(1'b0)
-  ) u_prim_fifo_sync_rcstage (
+  ) u_caliptra_prim_fifo_sync_rcstage (
     .clk_i          (clk_i),
     .rst_ni         (rst_ni),
     .clr_i          (!ctr_drbg_gen_enable_i),
@@ -544,12 +544,12 @@ module csrng_ctr_drbg_gen import csrng_pkg::*; #(
   // final cmd block processing
   //--------------------------------------------
 
-  prim_fifo_sync #(
+  caliptra_prim_fifo_sync #(
     .Width(GenbitsFifoWidth),
     .Pass(0),
     .Depth(GenbitsFifoDepth),
     .OutputZeroIfEmpty(1'b0)
-  ) u_prim_fifo_sync_genbits (
+  ) u_caliptra_prim_fifo_sync_genbits (
     .clk_i          (clk_i),
     .rst_ni         (rst_ni),
     .clr_i          (!ctr_drbg_gen_enable_i),
diff --git a/src/csrng/rtl/csrng_ctr_drbg_upd.sv b/src/csrng/rtl/csrng_ctr_drbg_upd.sv
index 232ad994c..8e5320b4a 100644
--- a/src/csrng/rtl/csrng_ctr_drbg_upd.sv
+++ b/src/csrng/rtl/csrng_ctr_drbg_upd.sv
@@ -184,7 +184,7 @@ module csrng_ctr_drbg_upd #(
   blk_enc_state_e blk_enc_state_d, blk_enc_state_q;
 
   // SEC_CM: BLK_ENC.FSM.SPARSE
-  `PRIM_FLOP_SPARSE_FSM(u_blk_enc_state_regs, blk_enc_state_d,
+  `CALIPTRA_PRIM_FLOP_SPARSE_FSM(u_blk_enc_state_regs, blk_enc_state_d,
       blk_enc_state_q, blk_enc_state_e, ReqIdle)
 
 // Encoding generated with:
@@ -218,7 +218,7 @@ module csrng_ctr_drbg_upd #(
   outblk_state_e outblk_state_d, outblk_state_q;
 
   // SEC_CM: OUTBLK.FSM.SPARSE
-  `PRIM_FLOP_SPARSE_FSM(u_outblk_state_regs, outblk_state_d,
+  `CALIPTRA_PRIM_FLOP_SPARSE_FSM(u_outblk_state_regs, outblk_state_d,
       outblk_state_q, outblk_state_e, AckIdle)
 
   always_ff @(posedge clk_i or negedge rst_ni)
@@ -241,12 +241,12 @@ module csrng_ctr_drbg_upd #(
   // input request fifo for staging update requests
   //--------------------------------------------
 
-  prim_fifo_sync #(
+  caliptra_prim_fifo_sync #(
     .Width(UpdReqFifoWidth),
     .Pass(0),
     .Depth(UpdReqFifoDepth),
     .OutputZeroIfEmpty(1'b0)
-  ) u_prim_fifo_sync_updreq (
+  ) u_caliptra_prim_fifo_sync_updreq (
     .clk_i    (clk_i),
     .rst_ni   (rst_ni),
     .clr_i    (!ctr_drbg_upd_enable_i),
@@ -287,9 +287,9 @@ module csrng_ctr_drbg_upd #(
   end
 
   // SEC_CM: DRBG_UPD.CTR.REDUN
-  prim_count #(
+  caliptra_prim_count #(
     .Width(CtrLen)
-  ) u_prim_count_ctr_drbg (
+  ) u_caliptra_prim_count_ctr_drbg (
     .clk_i,
     .rst_ni,
     .clr_i(!ctr_drbg_upd_enable_i),
@@ -377,12 +377,12 @@ module csrng_ctr_drbg_upd #(
   // block_encrypt request fifo for staging aes requests
   //--------------------------------------------
 
-  prim_fifo_sync #(
+  caliptra_prim_fifo_sync #(
     .Width(BlkEncReqFifoWidth),
     .Pass(0),
     .Depth(BlkEncReqFifoDepth),
     .OutputZeroIfEmpty(1'b0)
-  ) u_prim_fifo_sync_bencreq (
+  ) u_caliptra_prim_fifo_sync_bencreq (
     .clk_i    (clk_i),
     .rst_ni   (rst_ni),
     .clr_i    (!ctr_drbg_upd_enable_i),
@@ -420,12 +420,12 @@ module csrng_ctr_drbg_upd #(
   // block_encrypt response fifo from block encrypt
   //--------------------------------------------
 
-  prim_fifo_sync #(
+  caliptra_prim_fifo_sync #(
     .Width(BlkEncAckFifoWidth),
     .Pass(0),
     .Depth(BlkEncAckFifoDepth),
     .OutputZeroIfEmpty(1'b0)
-  ) u_prim_fifo_sync_bencack (
+  ) u_caliptra_prim_fifo_sync_bencack (
     .clk_i    (clk_i),
     .rst_ni   (rst_ni),
     .clr_i    (!ctr_drbg_upd_enable_i),
@@ -455,12 +455,12 @@ module csrng_ctr_drbg_upd #(
   // fifo to stage provided_data, waiting for blk_encrypt to ack
   //--------------------------------------------
 
-  prim_fifo_sync #(
+  caliptra_prim_fifo_sync #(
     .Width(PDataFifoWidth),
     .Pass(0),
     .Depth(PDataFifoDepth),
     .OutputZeroIfEmpty(1'b0)
-  ) u_prim_fifo_sync_pdata (
+  ) u_caliptra_prim_fifo_sync_pdata (
     .clk_i    (clk_i),
     .rst_ni   (rst_ni),
     .clr_i    (!ctr_drbg_upd_enable_i),
@@ -579,12 +579,12 @@ module csrng_ctr_drbg_upd #(
   // XOR the additional data with the new key and value from block encryption
   assign updated_key_and_v = concat_outblk_q ^ sfifo_pdata_v;
 
-  prim_fifo_sync #(
+  caliptra_prim_fifo_sync #(
     .Width(FinalFifoWidth),
     .Pass(0),
     .Depth(FinalFifoDepth),
     .OutputZeroIfEmpty(1'b0)
-  ) u_prim_fifo_sync_final (
+  ) u_caliptra_prim_fifo_sync_final (
     .clk_i    (clk_i),
     .rst_ni   (rst_ni),
     .clr_i    (!ctr_drbg_upd_enable_i),
diff --git a/src/csrng/rtl/csrng_main_sm.sv b/src/csrng/rtl/csrng_main_sm.sv
index d494ad225..625fb7b7c 100644
--- a/src/csrng/rtl/csrng_main_sm.sv
+++ b/src/csrng/rtl/csrng_main_sm.sv
@@ -33,7 +33,7 @@ module csrng_main_sm import csrng_pkg::*; #() (
 );
 
   main_sm_state_e state_d, state_q;
-  `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, main_sm_state_e, MainSmIdle)
+  `CALIPTRA_PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, main_sm_state_e, MainSmIdle)
 
   assign main_sm_state_o = {state_q};
 
diff --git a/src/csrng/rtl/csrng_reg_top.sv b/src/csrng/rtl/csrng_reg_top.sv
index 021ad65f0..70a8d0056 100644
--- a/src/csrng/rtl/csrng_reg_top.sv
+++ b/src/csrng/rtl/csrng_reg_top.sv
@@ -4,7 +4,7 @@
 //
 // Register Top module auto-generated by `reggen`
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
 module csrng_reg_top #(
     parameter AHBDataWidth = 64,
@@ -67,9 +67,9 @@ module csrng_reg_top #(
   // also check for spurious write enables
   logic reg_we_err;
   logic [16:0] reg_we_check;
-  prim_reg_we_check #(
+  caliptra_prim_reg_we_check #(
     .OneHotWidth(17)
-  ) u_prim_reg_we_check (
+  ) u_caliptra_prim_reg_we_check (
     .clk_i(clk_i),
     .rst_ni(rst_ni),
     .oh_i  (reg_we_check),
@@ -249,9 +249,9 @@ module csrng_reg_top #(
   // Register instances
   // R[intr_state]: V(False)
   //   F[cs_cmd_req_done]: 0:0
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW1C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_intr_state_cs_cmd_req_done (
     .clk_i   (clk_i),
@@ -275,9 +275,9 @@ module csrng_reg_top #(
   );
 
   //   F[cs_entropy_req]: 1:1
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW1C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_intr_state_cs_entropy_req (
     .clk_i   (clk_i),
@@ -301,9 +301,9 @@ module csrng_reg_top #(
   );
 
   //   F[cs_hw_inst_exc]: 2:2
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW1C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_intr_state_cs_hw_inst_exc (
     .clk_i   (clk_i),
@@ -327,9 +327,9 @@ module csrng_reg_top #(
   );
 
   //   F[cs_fatal_err]: 3:3
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW1C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_intr_state_cs_fatal_err (
     .clk_i   (clk_i),
@@ -355,9 +355,9 @@ module csrng_reg_top #(
 
   // R[intr_enable]: V(False)
   //   F[cs_cmd_req_done]: 0:0
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_intr_enable_cs_cmd_req_done (
     .clk_i   (clk_i),
@@ -381,9 +381,9 @@ module csrng_reg_top #(
   );
 
   //   F[cs_entropy_req]: 1:1
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_intr_enable_cs_entropy_req (
     .clk_i   (clk_i),
@@ -407,9 +407,9 @@ module csrng_reg_top #(
   );
 
   //   F[cs_hw_inst_exc]: 2:2
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_intr_enable_cs_hw_inst_exc (
     .clk_i   (clk_i),
@@ -433,9 +433,9 @@ module csrng_reg_top #(
   );
 
   //   F[cs_fatal_err]: 3:3
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_intr_enable_cs_fatal_err (
     .clk_i   (clk_i),
@@ -464,7 +464,7 @@ module csrng_reg_top #(
   logic [3:0] intr_test_flds_we;
   assign intr_test_qe = &intr_test_flds_we;
   //   F[cs_cmd_req_done]: 0:0
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (1)
   ) u_intr_test_cs_cmd_req_done (
     .re     (1'b0),
@@ -480,7 +480,7 @@ module csrng_reg_top #(
   assign reg2hw.intr_test.cs_cmd_req_done.qe = intr_test_qe;
 
   //   F[cs_entropy_req]: 1:1
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (1)
   ) u_intr_test_cs_entropy_req (
     .re     (1'b0),
@@ -496,7 +496,7 @@ module csrng_reg_top #(
   assign reg2hw.intr_test.cs_entropy_req.qe = intr_test_qe;
 
   //   F[cs_hw_inst_exc]: 2:2
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (1)
   ) u_intr_test_cs_hw_inst_exc (
     .re     (1'b0),
@@ -512,7 +512,7 @@ module csrng_reg_top #(
   assign reg2hw.intr_test.cs_hw_inst_exc.qe = intr_test_qe;
 
   //   F[cs_fatal_err]: 3:3
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (1)
   ) u_intr_test_cs_fatal_err (
     .re     (1'b0),
@@ -533,7 +533,7 @@ module csrng_reg_top #(
   logic [1:0] alert_test_flds_we;
   assign alert_test_qe = &alert_test_flds_we;
   //   F[recov_alert]: 0:0
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (1)
   ) u_alert_test_recov_alert (
     .re     (1'b0),
@@ -549,7 +549,7 @@ module csrng_reg_top #(
   assign reg2hw.alert_test.recov_alert.qe = alert_test_qe;
 
   //   F[fatal_alert]: 1:1
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (1)
   ) u_alert_test_fatal_alert (
     .re     (1'b0),
@@ -566,9 +566,9 @@ module csrng_reg_top #(
 
 
   // R[regwen]: V(False)
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW0C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW0C),
     .RESVAL  (1'h1)
   ) u_regwen (
     .clk_i   (clk_i),
@@ -597,9 +597,9 @@ module csrng_reg_top #(
   logic ctrl_gated_we;
   assign ctrl_gated_we = ctrl_we & regwen_qs;
   //   F[enable]: 3:0
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (4),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (4'h9)
   ) u_ctrl_enable (
     .clk_i   (clk_i),
@@ -623,9 +623,9 @@ module csrng_reg_top #(
   );
 
   //   F[sw_app_enable]: 7:4
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (4),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (4'h9)
   ) u_ctrl_sw_app_enable (
     .clk_i   (clk_i),
@@ -649,9 +649,9 @@ module csrng_reg_top #(
   );
 
   //   F[read_int_state]: 11:8
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (4),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (4'h9)
   ) u_ctrl_read_int_state (
     .clk_i   (clk_i),
@@ -678,7 +678,7 @@ module csrng_reg_top #(
   // R[cmd_req]: V(False)
   logic cmd_req_qe;
   logic [0:0] cmd_req_flds_we;
-  prim_flop #(
+  caliptra_prim_flop #(
     .Width(1),
     .ResetValue(0)
   ) u_cmd_req0_qe (
@@ -687,9 +687,9 @@ module csrng_reg_top #(
     .d_i(&cmd_req_flds_we),
     .q_o(cmd_req_qe)
   );
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (32),
-    .SwAccess(prim_subreg_pkg::SwAccessWO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessWO),
     .RESVAL  (32'h0)
   ) u_cmd_req (
     .clk_i   (clk_i),
@@ -716,9 +716,9 @@ module csrng_reg_top #(
 
   // R[sw_cmd_sts]: V(False)
   //   F[cmd_rdy]: 0:0
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h1)
   ) u_sw_cmd_sts_cmd_rdy (
     .clk_i   (clk_i),
@@ -742,9 +742,9 @@ module csrng_reg_top #(
   );
 
   //   F[cmd_sts]: 1:1
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_sw_cmd_sts_cmd_sts (
     .clk_i   (clk_i),
@@ -770,7 +770,7 @@ module csrng_reg_top #(
 
   // R[genbits_vld]: V(True)
   //   F[genbits_vld]: 0:0
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (1)
   ) u_genbits_vld_genbits_vld (
     .re     (genbits_vld_re),
@@ -785,7 +785,7 @@ module csrng_reg_top #(
   );
 
   //   F[genbits_fips]: 1:1
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (1)
   ) u_genbits_vld_genbits_fips (
     .re     (genbits_vld_re),
@@ -801,7 +801,7 @@ module csrng_reg_top #(
 
 
   // R[genbits]: V(True)
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (32)
   ) u_genbits (
     .re     (genbits_re),
@@ -819,7 +819,7 @@ module csrng_reg_top #(
   // R[int_state_num]: V(False)
   logic int_state_num_qe;
   logic [0:0] int_state_num_flds_we;
-  prim_flop #(
+  caliptra_prim_flop #(
     .Width(1),
     .ResetValue(0)
   ) u_int_state_num0_qe (
@@ -828,9 +828,9 @@ module csrng_reg_top #(
     .d_i(&int_state_num_flds_we),
     .q_o(int_state_num_qe)
   );
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (4),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (4'h0)
   ) u_int_state_num (
     .clk_i   (clk_i),
@@ -856,7 +856,7 @@ module csrng_reg_top #(
 
 
   // R[int_state_val]: V(True)
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (32)
   ) u_int_state_val (
     .re     (int_state_val_re),
@@ -872,9 +872,9 @@ module csrng_reg_top #(
 
 
   // R[hw_exc_sts]: V(False)
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (16),
-    .SwAccess(prim_subreg_pkg::SwAccessW0C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW0C),
     .RESVAL  (16'h0)
   ) u_hw_exc_sts (
     .clk_i   (clk_i),
@@ -900,9 +900,9 @@ module csrng_reg_top #(
 
   // R[recov_alert_sts]: V(False)
   //   F[enable_field_alert]: 0:0
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW0C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW0C),
     .RESVAL  (1'h0)
   ) u_recov_alert_sts_enable_field_alert (
     .clk_i   (clk_i),
@@ -926,9 +926,9 @@ module csrng_reg_top #(
   );
 
   //   F[sw_app_enable_field_alert]: 1:1
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW0C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW0C),
     .RESVAL  (1'h0)
   ) u_recov_alert_sts_sw_app_enable_field_alert (
     .clk_i   (clk_i),
@@ -952,9 +952,9 @@ module csrng_reg_top #(
   );
 
   //   F[read_int_state_field_alert]: 2:2
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW0C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW0C),
     .RESVAL  (1'h0)
   ) u_recov_alert_sts_read_int_state_field_alert (
     .clk_i   (clk_i),
@@ -978,9 +978,9 @@ module csrng_reg_top #(
   );
 
   //   F[acmd_flag0_field_alert]: 3:3
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW0C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW0C),
     .RESVAL  (1'h0)
   ) u_recov_alert_sts_acmd_flag0_field_alert (
     .clk_i   (clk_i),
@@ -1004,9 +1004,9 @@ module csrng_reg_top #(
   );
 
   //   F[cs_bus_cmp_alert]: 12:12
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW0C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW0C),
     .RESVAL  (1'h0)
   ) u_recov_alert_sts_cs_bus_cmp_alert (
     .clk_i   (clk_i),
@@ -1030,9 +1030,9 @@ module csrng_reg_top #(
   );
 
   //   F[cs_main_sm_alert]: 13:13
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW0C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW0C),
     .RESVAL  (1'h0)
   ) u_recov_alert_sts_cs_main_sm_alert (
     .clk_i   (clk_i),
@@ -1058,9 +1058,9 @@ module csrng_reg_top #(
 
   // R[err_code]: V(False)
   //   F[sfifo_cmd_err]: 0:0
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_err_code_sfifo_cmd_err (
     .clk_i   (clk_i),
@@ -1084,9 +1084,9 @@ module csrng_reg_top #(
   );
 
   //   F[sfifo_genbits_err]: 1:1
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_err_code_sfifo_genbits_err (
     .clk_i   (clk_i),
@@ -1110,9 +1110,9 @@ module csrng_reg_top #(
   );
 
   //   F[sfifo_cmdreq_err]: 2:2
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_err_code_sfifo_cmdreq_err (
     .clk_i   (clk_i),
@@ -1136,9 +1136,9 @@ module csrng_reg_top #(
   );
 
   //   F[sfifo_rcstage_err]: 3:3
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_err_code_sfifo_rcstage_err (
     .clk_i   (clk_i),
@@ -1162,9 +1162,9 @@ module csrng_reg_top #(
   );
 
   //   F[sfifo_keyvrc_err]: 4:4
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_err_code_sfifo_keyvrc_err (
     .clk_i   (clk_i),
@@ -1188,9 +1188,9 @@ module csrng_reg_top #(
   );
 
   //   F[sfifo_updreq_err]: 5:5
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_err_code_sfifo_updreq_err (
     .clk_i   (clk_i),
@@ -1214,9 +1214,9 @@ module csrng_reg_top #(
   );
 
   //   F[sfifo_bencreq_err]: 6:6
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_err_code_sfifo_bencreq_err (
     .clk_i   (clk_i),
@@ -1240,9 +1240,9 @@ module csrng_reg_top #(
   );
 
   //   F[sfifo_bencack_err]: 7:7
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_err_code_sfifo_bencack_err (
     .clk_i   (clk_i),
@@ -1266,9 +1266,9 @@ module csrng_reg_top #(
   );
 
   //   F[sfifo_pdata_err]: 8:8
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_err_code_sfifo_pdata_err (
     .clk_i   (clk_i),
@@ -1292,9 +1292,9 @@ module csrng_reg_top #(
   );
 
   //   F[sfifo_final_err]: 9:9
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_err_code_sfifo_final_err (
     .clk_i   (clk_i),
@@ -1318,9 +1318,9 @@ module csrng_reg_top #(
   );
 
   //   F[sfifo_gbencack_err]: 10:10
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_err_code_sfifo_gbencack_err (
     .clk_i   (clk_i),
@@ -1344,9 +1344,9 @@ module csrng_reg_top #(
   );
 
   //   F[sfifo_grcstage_err]: 11:11
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_err_code_sfifo_grcstage_err (
     .clk_i   (clk_i),
@@ -1370,9 +1370,9 @@ module csrng_reg_top #(
   );
 
   //   F[sfifo_ggenreq_err]: 12:12
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_err_code_sfifo_ggenreq_err (
     .clk_i   (clk_i),
@@ -1396,9 +1396,9 @@ module csrng_reg_top #(
   );
 
   //   F[sfifo_gadstage_err]: 13:13
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_err_code_sfifo_gadstage_err (
     .clk_i   (clk_i),
@@ -1422,9 +1422,9 @@ module csrng_reg_top #(
   );
 
   //   F[sfifo_ggenbits_err]: 14:14
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_err_code_sfifo_ggenbits_err (
     .clk_i   (clk_i),
@@ -1448,9 +1448,9 @@ module csrng_reg_top #(
   );
 
   //   F[sfifo_blkenc_err]: 15:15
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_err_code_sfifo_blkenc_err (
     .clk_i   (clk_i),
@@ -1474,9 +1474,9 @@ module csrng_reg_top #(
   );
 
   //   F[cmd_stage_sm_err]: 20:20
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_err_code_cmd_stage_sm_err (
     .clk_i   (clk_i),
@@ -1500,9 +1500,9 @@ module csrng_reg_top #(
   );
 
   //   F[main_sm_err]: 21:21
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_err_code_main_sm_err (
     .clk_i   (clk_i),
@@ -1526,9 +1526,9 @@ module csrng_reg_top #(
   );
 
   //   F[drbg_gen_sm_err]: 22:22
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_err_code_drbg_gen_sm_err (
     .clk_i   (clk_i),
@@ -1552,9 +1552,9 @@ module csrng_reg_top #(
   );
 
   //   F[drbg_updbe_sm_err]: 23:23
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_err_code_drbg_updbe_sm_err (
     .clk_i   (clk_i),
@@ -1578,9 +1578,9 @@ module csrng_reg_top #(
   );
 
   //   F[drbg_updob_sm_err]: 24:24
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_err_code_drbg_updob_sm_err (
     .clk_i   (clk_i),
@@ -1604,9 +1604,9 @@ module csrng_reg_top #(
   );
 
   //   F[aes_cipher_sm_err]: 25:25
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_err_code_aes_cipher_sm_err (
     .clk_i   (clk_i),
@@ -1630,9 +1630,9 @@ module csrng_reg_top #(
   );
 
   //   F[cmd_gen_cnt_err]: 26:26
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_err_code_cmd_gen_cnt_err (
     .clk_i   (clk_i),
@@ -1656,9 +1656,9 @@ module csrng_reg_top #(
   );
 
   //   F[fifo_write_err]: 28:28
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_err_code_fifo_write_err (
     .clk_i   (clk_i),
@@ -1682,9 +1682,9 @@ module csrng_reg_top #(
   );
 
   //   F[fifo_read_err]: 29:29
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_err_code_fifo_read_err (
     .clk_i   (clk_i),
@@ -1708,9 +1708,9 @@ module csrng_reg_top #(
   );
 
   //   F[fifo_state_err]: 30:30
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_err_code_fifo_state_err (
     .clk_i   (clk_i),
@@ -1737,7 +1737,7 @@ module csrng_reg_top #(
   // R[err_code_test]: V(False)
   logic err_code_test_qe;
   logic [0:0] err_code_test_flds_we;
-  prim_flop #(
+  caliptra_prim_flop #(
     .Width(1),
     .ResetValue(0)
   ) u_err_code_test0_qe (
@@ -1749,9 +1749,9 @@ module csrng_reg_top #(
   // Create REGWEN-gated WE signal
   logic err_code_test_gated_we;
   assign err_code_test_gated_we = err_code_test_we & regwen_qs;
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (5),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (5'h0)
   ) u_err_code_test (
     .clk_i   (clk_i),
@@ -1777,9 +1777,9 @@ module csrng_reg_top #(
 
 
   // R[main_sm_state]: V(False)
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (8),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (8'h4e)
   ) u_main_sm_state (
     .clk_i   (clk_i),
@@ -2059,10 +2059,6 @@ module csrng_reg_top #(
       addr_hit[16]: begin
         reg_rdata_next[7:0] = main_sm_state_qs;
       end
-
-      default: begin
-        reg_rdata_next = '1;
-      end
     endcase
   end
 
diff --git a/src/csrng/rtl/csrng_state_db.sv b/src/csrng/rtl/csrng_state_db.sv
index 0716b3f2e..034304bba 100644
--- a/src/csrng/rtl/csrng_state_db.sv
+++ b/src/csrng/rtl/csrng_state_db.sv
@@ -7,7 +7,7 @@
 // This is the container for accessing the current
 //    working state for a given drbg instance.
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
 module csrng_state_db import csrng_pkg::*; #(
   parameter int NApps = 4,
diff --git a/src/csrng/tb/Makefile b/src/csrng/tb/Makefile
index 1ab01e91a..4c29d9279 100644
--- a/src/csrng/tb/Makefile
+++ b/src/csrng/tb/Makefile
@@ -44,10 +44,10 @@ verilator-build: $(TBFILES) $(VERILATOR_LINT_FILES) test_$(IPNAME)_tb.cpp
 	$(VERILATOR) --cc \
 		--timing \
 		--timescale 1ns/1ps \
-		-f $(CONFIGDIR)/$(IPNAME).vf --top-module $(IPNAME)_tb \
+		-f $(CONFIGDIR)/$(IPNAME)_tb.vf --top-module $(IPNAME)_tb \
     -f $(VERILATOR_LINT_FILES) \
 		-exe test_$(IPNAME)_tb.cpp \
-		--trace
+		--trace --trace-structs
 	cp test_$(IPNAME)_tb.cpp obj_dir/
 	$(MAKE) -j -e -C obj_dir/ -f V$(IPNAME)_tb.mk $(VERILATOR_MAKE_FLAGS) VM_PARALLEL_BUILDS=1
 	touch verilator-build
diff --git a/src/csrng/tb/csrng_tb.sv b/src/csrng/tb/csrng_tb.sv
index 9666eece9..726aab0f4 100644
--- a/src/csrng/tb/csrng_tb.sv
+++ b/src/csrng/tb/csrng_tb.sv
@@ -27,7 +27,7 @@ module csrng_tb
   import entropy_src_pkg::*;
   import entropy_src_reg_pkg::*;
   import lc_ctrl_pkg::*;
-  import prim_mubi_pkg::mubi8_t;
+  import caliptra_prim_mubi_pkg::mubi8_t;
 (
 `ifdef VERILATOR
   input bit clk_tb
@@ -126,7 +126,7 @@ module csrng_tb
       .hreadyout_o (hreadyout_o_tb),
       .hrdata_o    (hrdata_o_tb),
        // OTP Interface
-      .otp_en_csrng_sw_app_read_i(prim_mubi_pkg::MuBi8True),
+      .otp_en_csrng_sw_app_read_i(caliptra_prim_mubi_pkg::MuBi8True),
       // Lifecycle broadcast inputs
       .lc_hw_debug_en_i(lc_ctrl_pkg::On),
       // Entropy Interface
@@ -167,7 +167,7 @@ module csrng_tb
   // the dut as needed.
   //----------------------------------------------------------------
   always @(posedge clk_tb) begin : sys_monitor
-      cycle_ctr = cycle_ctr + 1;
+      cycle_ctr = (!reset_n_tb) ? 32'h0 : cycle_ctr + 1;
     end
 
 
@@ -199,7 +199,6 @@ module csrng_tb
   //----------------------------------------------------------------
   task init_sim;
     begin
-      cycle_ctr = '0;
       error_ctr = '0;
       tc_ctr    = '0;
 `ifndef VERILATOR
@@ -254,6 +253,7 @@ module csrng_tb
       $display("[%t] write_single_word(addr=0x%x, word=0x%x)", $time, address, word);
       hsel_i_tb       = 1;
       haddr_i_tb      = address;
+      hwdata_i_tb     = word;
       hwrite_i_tb     = 1;
       hready_i_tb     = 1;
       htrans_i_tb     = AHB_HTRANS_NONSEQ;
@@ -261,7 +261,6 @@ module csrng_tb
 
       @(posedge clk_tb);
       haddr_i_tb      = 'Z;
-      hwdata_i_tb     = word;
       hwrite_i_tb     = 0;
       htrans_i_tb     = AHB_HTRANS_IDLE;
       wait(hreadyout_o_tb == 1'b1);
diff --git a/src/datavault/config/datavault.vf b/src/datavault/config/datavault.vf
index 26a98c56a..829d888e8 100644
--- a/src/datavault/config/datavault.vf
+++ b/src/datavault/config/datavault.vf
@@ -12,6 +12,7 @@ ${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
 ${CALIPTRA_ROOT}/src/datavault/rtl/dv_defines_pkg.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
 ${CALIPTRA_ROOT}/src/datavault/rtl/dv_reg_pkg.sv
diff --git a/src/datavault/rtl/dv.sv b/src/datavault/rtl/dv.sv
index b725b9e11..a4f2e459f 100644
--- a/src/datavault/rtl/dv.sv
+++ b/src/datavault/rtl/dv.sv
@@ -104,17 +104,17 @@ always_comb begin: datavault
     end
  
     //Non-Sticky Data Vault Regs & Controls
-    for (int entry = 0; entry < NONSTICKY_DV_NUM_ENTRIES; entry++) begin
-       dv_reg_hwif_in.NonStickyDataVaultCtrl[entry].lock_entry.swwel = dv_reg_hwif_out.NonStickyDataVaultCtrl[entry].lock_entry.value;
+    for (int entry = 0; entry < DV_NUM_ENTRIES; entry++) begin
+       dv_reg_hwif_in.DataVaultCtrl[entry].lock_entry.swwel = dv_reg_hwif_out.DataVaultCtrl[entry].lock_entry.value;
        for (int dword = 0; dword < DV_NUM_DWORDS; dword++) begin
-           dv_reg_hwif_in.NONSTICKY_DATA_VAULT_ENTRY[entry][dword].data.swwel = dv_reg_hwif_out.NonStickyDataVaultCtrl[entry].lock_entry.value;
+           dv_reg_hwif_in.DATA_VAULT_ENTRY[entry][dword].data.swwel = dv_reg_hwif_out.DataVaultCtrl[entry].lock_entry.value;
        end
     end
  
     //Non-Sticky Generic Lockable Registers in the Data Vault
-    for (int entry = 0; entry < NONSTICKY_LOCK_SCRATCH_NUM_ENTRIES; entry++) begin
-       dv_reg_hwif_in.NonStickyLockableScratchRegCtrl[entry].lock_entry.swwel = dv_reg_hwif_out.NonStickyLockableScratchRegCtrl[entry].lock_entry.value;
-       dv_reg_hwif_in.NonStickyLockableScratchReg[entry].data.swwel  = dv_reg_hwif_out.NonStickyLockableScratchRegCtrl[entry].lock_entry.value;
+    for (int entry = 0; entry < LOCK_SCRATCH_NUM_ENTRIES; entry++) begin
+       dv_reg_hwif_in.LockableScratchRegCtrl[entry].lock_entry.swwel = dv_reg_hwif_out.LockableScratchRegCtrl[entry].lock_entry.value;
+       dv_reg_hwif_in.LockableScratchReg[entry].data.swwel  = dv_reg_hwif_out.LockableScratchRegCtrl[entry].lock_entry.value;
     end
  
     //Sticky Generic Lockable Registers in the Data Vault
diff --git a/src/datavault/rtl/dv_defines_pkg.sv b/src/datavault/rtl/dv_defines_pkg.sv
index 0883025e3..7ff199f1d 100644
--- a/src/datavault/rtl/dv_defines_pkg.sv
+++ b/src/datavault/rtl/dv_defines_pkg.sv
@@ -21,8 +21,8 @@ package dv_defines_pkg;
     parameter DV_DATA_W = 32;
 
     parameter STICKY_DV_NUM_ENTRIES = 10;
-    parameter NONSTICKY_DV_NUM_ENTRIES = 10;
-    parameter NONSTICKY_LOCK_SCRATCH_NUM_ENTRIES = 10;
+    parameter DV_NUM_ENTRIES = 10;
+    parameter LOCK_SCRATCH_NUM_ENTRIES = 10;
     parameter STICKY_LOCK_SCRATCH_NUM_ENTRIES = 8;
     parameter NONSTICKY_SCRATCH_NUM_ENTRIES = 8;
     parameter DV_NUM_DWORDS = 12;
diff --git a/src/datavault/rtl/dv_reg.rdl b/src/datavault/rtl/dv_reg.rdl
index 27d6e59db..6e4d57a51 100644
--- a/src/datavault/rtl/dv_reg.rdl
+++ b/src/datavault/rtl/dv_reg.rdl
@@ -19,51 +19,53 @@ addrmap dv_reg {
     signal {activelow; async;} hard_reset_b;
 
     // Sticky DataVault registers
-    field StickyDataVaultEntry    {desc="DataVault Entry"; sw=rw; hw=na; swwel=true; resetsignal = hard_reset_b;};
+    field StickyDataVaultEntry    {desc="DataVault Entry (cleared on hard reset)"; sw=rw; hw=na; swwel=true; resetsignal = hard_reset_b;};
     reg StickyDataVaultReg    {StickyDataVaultEntry data[32]=0;}; //generic reg for DataVault
 
-    // NonSticky DataVault registers (reset on warm reset)
-    field NonStickyDataVaultEntry {desc="DataVault Entry"; sw=rw; hw=na; swwel=true; resetsignal = reset_b;};
-    reg NonStickyDataVaultReg {NonStickyDataVaultEntry data[32]=0;}; //generic reg for DataVault
+    // Sticky DataVault registers (reset on hard reset)
+    field DataVaultEntry {desc="DataVault Entry (cleared on hard reset)"; sw=rw; hw=na; swwel=true; resetsignal = hard_reset_b;};
+    reg DataVaultReg {DataVaultEntry data[32]=0;}; //generic reg for DataVault
 
     // ============== Data Vault Registers ===========================
     reg {
-        desc="Controls for the Sticky Data Vault Entries";
+        desc="Controls for the Sticky Data Vault Entries (cleared on hard reset)";
         field {desc="Lock writes to this entry. Writes will be suppressed when locked.";
-               sw=rw; swwel=true; hw=r; resetsignal=hard_reset_b;} lock_entry=0; //Shoud reflect NONSTICKY_DV_NUM_ENTRIES from kv_defines_pkg.sv
+               sw=rw; swwel=true; hw=r; resetsignal=hard_reset_b;} lock_entry=0; //Shoud reflect STICKY_DV_NUM_ENTRIES from dv_defines_pkg.sv
     } StickyDataVaultCtrl[10];
 
-    StickyDataVaultReg     STICKY_DATA_VAULT_ENTRY[10][12];//Shoud reflect STICKY_DV_NUM_ENTRIES and DV_NUM_DWORDS from kv_defines_pkg.sv
+    StickyDataVaultReg     STICKY_DATA_VAULT_ENTRY[10][12];//Shoud reflect STICKY_DV_NUM_ENTRIES and DV_NUM_DWORDS from dv_defines_pkg.sv
 
     reg {
-        desc="Controls for the Non-Sticky Data Vault Entries";
+        desc="Controls for the Data Vault Entries (cleared on warm reset)";
         field {desc="Lock writes to this entry. Writes will be suppressed when locked.";
-               sw=rw; swwel=true; hw=r; resetsignal=core_only_rst_b;} lock_entry=0; //Shoud reflect STICKY_DV_NUM_ENTRIES and DV_NUM_DWORDS from kv_defines_pkg.sv
-    } NonStickyDataVaultCtrl[10];// CAREFUL with the address extensions
+               sw=rw; swwel=true; hw=r; resetsignal=core_only_rst_b;} lock_entry=0; //Shoud reflect DV_NUM_ENTRIES and DV_NUM_DWORDS from dv_defines_pkg.sv
+    } DataVaultCtrl[10];// CAREFUL with the address extensions
 
-    NonStickyDataVaultReg  NONSTICKY_DATA_VAULT_ENTRY[10][12];//Shoud reflect NONSTICKY_DV_NUM_ENTRIES and DV_NUM_DWORDS from kv_defines_pkg.sv
+    DataVaultReg  DATA_VAULT_ENTRY[10][12];//Shoud reflect DV_NUM_ENTRIES and DV_NUM_DWORDS from dv_defines_pkg.sv
 
     reg {
-        desc="Non-Sticky Scratch Register Controls";
+        desc="Scratch Register Controls (cleared on warm reset)";
         field {desc="Lock writes to the Scratch registers. Writes will be suppressed when locked.";
                sw=rw; swwel=true; hw=r; resetsignal=core_only_rst_b;} lock_entry=0;
-    } NonStickyLockableScratchRegCtrl[10]; //Shoud reflect NONSTICKY_SCRATCH_NUM_ENTRIES from kv_defines_pkg.sv & CAREFUL with the address extensions
+    } LockableScratchRegCtrl[10]; //Shoud reflect LOCK_SCRATCH_NUM_ENTRIES from dv_defines_pkg.sv & CAREFUL with the address extensions
 
     reg {
-       field {sw=rw; swwel=true; hw=na; resetsignal=reset_b;} data[32]=0;
-    } NonStickyLockableScratchReg[10]; //Shoud reflect NONSTICKY_LOCKQ_SCRATCH_NUM_ENTRIES from kv_defines_pkg.sv
+       desc="Scratch Register Entrie (cleared on hard reset)";
+       field {sw=rw; swwel=true; hw=na; resetsignal=hard_reset_b;} data[32]=0;
+    } LockableScratchReg[10]; //Shoud reflect LOCK_SCRATCH_NUM_ENTRIES from dv_defines_pkg.sv
 
     reg {
        field {sw=rw; hw=na; resetsignal=reset_b;} data[32]=0;
-    } NonStickyGenericScratchReg[8]; //Shoud reflect NONSTICKY_SCRATCH_NUM_ENTRIES from kv_defines_pkg.sv & CAREFUL with the address extensions
+    } NonStickyGenericScratchReg[8]; //Shoud reflect NONSTICKY_SCRATCH_NUM_ENTRIES from dv_defines_pkg.sv & CAREFUL with the address extensions
 
     reg {
-        desc="Sticky Scratch Register Controls";
+        desc="Sticky Scratch Register Controls (cleared on hard reset)";
         field {desc="Lock writes to the Scratch registers. Writes will be suppressed when locked.";
                sw=rw; swwel=true; hw=r; resetsignal=hard_reset_b;} lock_entry=0;
     } StickyLockableScratchRegCtrl[8]; //should reflect STICKY_LOCKQ_SCRATCH_NUM_ENTRIES
 
     reg {
+       desc="Sticky Scratch Register Entries (cleared on hard reset)";
        field {sw=rw; swwel=true; hw=na; resetsignal=hard_reset_b;} data[32]=0;
     } StickyLockableScratchReg[8]; //should reflect STICKY_LOCKQ_SCRATCH_NUM_ENTRIES
 
diff --git a/src/datavault/rtl/dv_reg.sv b/src/datavault/rtl/dv_reg.sv
index 5eec7ce22..ded8e5d15 100644
--- a/src/datavault/rtl/dv_reg.sv
+++ b/src/datavault/rtl/dv_reg.sv
@@ -66,10 +66,10 @@ module dv_reg (
     typedef struct packed{
         logic [10-1:0]StickyDataVaultCtrl;
         logic [10-1:0][12-1:0]STICKY_DATA_VAULT_ENTRY;
-        logic [10-1:0]NonStickyDataVaultCtrl;
-        logic [10-1:0][12-1:0]NONSTICKY_DATA_VAULT_ENTRY;
-        logic [10-1:0]NonStickyLockableScratchRegCtrl;
-        logic [10-1:0]NonStickyLockableScratchReg;
+        logic [10-1:0]DataVaultCtrl;
+        logic [10-1:0][12-1:0]DATA_VAULT_ENTRY;
+        logic [10-1:0]LockableScratchRegCtrl;
+        logic [10-1:0]LockableScratchReg;
         logic [8-1:0]NonStickyGenericScratchReg;
         logic [8-1:0]StickyLockableScratchRegCtrl;
         logic [8-1:0]StickyLockableScratchReg;
@@ -90,18 +90,18 @@ module dv_reg (
             end
         end
         for(int i0=0; i0<10; i0++) begin
-            decoded_reg_strb.NonStickyDataVaultCtrl[i0] = cpuif_req_masked & (cpuif_addr == 'h208 + i0*'h4);
+            decoded_reg_strb.DataVaultCtrl[i0] = cpuif_req_masked & (cpuif_addr == 'h208 + i0*'h4);
         end
         for(int i0=0; i0<10; i0++) begin
             for(int i1=0; i1<12; i1++) begin
-                decoded_reg_strb.NONSTICKY_DATA_VAULT_ENTRY[i0][i1] = cpuif_req_masked & (cpuif_addr == 'h230 + i0*'h30 + i1*'h4);
+                decoded_reg_strb.DATA_VAULT_ENTRY[i0][i1] = cpuif_req_masked & (cpuif_addr == 'h230 + i0*'h30 + i1*'h4);
             end
         end
         for(int i0=0; i0<10; i0++) begin
-            decoded_reg_strb.NonStickyLockableScratchRegCtrl[i0] = cpuif_req_masked & (cpuif_addr == 'h410 + i0*'h4);
+            decoded_reg_strb.LockableScratchRegCtrl[i0] = cpuif_req_masked & (cpuif_addr == 'h410 + i0*'h4);
         end
         for(int i0=0; i0<10; i0++) begin
-            decoded_reg_strb.NonStickyLockableScratchReg[i0] = cpuif_req_masked & (cpuif_addr == 'h438 + i0*'h4);
+            decoded_reg_strb.LockableScratchReg[i0] = cpuif_req_masked & (cpuif_addr == 'h438 + i0*'h4);
         end
         for(int i0=0; i0<8; i0++) begin
             decoded_reg_strb.NonStickyGenericScratchReg[i0] = cpuif_req_masked & (cpuif_addr == 'h460 + i0*'h4);
@@ -145,25 +145,25 @@ module dv_reg (
                 logic next;
                 logic load_next;
             } lock_entry;
-        } [10-1:0]NonStickyDataVaultCtrl;
+        } [10-1:0]DataVaultCtrl;
         struct packed{
             struct packed{
                 logic [31:0] next;
                 logic load_next;
             } data;
-        } [10-1:0][12-1:0]NONSTICKY_DATA_VAULT_ENTRY;
+        } [10-1:0][12-1:0]DATA_VAULT_ENTRY;
         struct packed{
             struct packed{
                 logic next;
                 logic load_next;
             } lock_entry;
-        } [10-1:0]NonStickyLockableScratchRegCtrl;
+        } [10-1:0]LockableScratchRegCtrl;
         struct packed{
             struct packed{
                 logic [31:0] next;
                 logic load_next;
             } data;
-        } [10-1:0]NonStickyLockableScratchReg;
+        } [10-1:0]LockableScratchReg;
         struct packed{
             struct packed{
                 logic [31:0] next;
@@ -200,22 +200,22 @@ module dv_reg (
             struct packed{
                 logic value;
             } lock_entry;
-        } [10-1:0]NonStickyDataVaultCtrl;
+        } [10-1:0]DataVaultCtrl;
         struct packed{
             struct packed{
                 logic [31:0] value;
             } data;
-        } [10-1:0][12-1:0]NONSTICKY_DATA_VAULT_ENTRY;
+        } [10-1:0][12-1:0]DATA_VAULT_ENTRY;
         struct packed{
             struct packed{
                 logic value;
             } lock_entry;
-        } [10-1:0]NonStickyLockableScratchRegCtrl;
+        } [10-1:0]LockableScratchRegCtrl;
         struct packed{
             struct packed{
                 logic [31:0] value;
             } data;
-        } [10-1:0]NonStickyLockableScratchReg;
+        } [10-1:0]LockableScratchReg;
         struct packed{
             struct packed{
                 logic [31:0] value;
@@ -278,86 +278,86 @@ module dv_reg (
         end
     end
     for(genvar i0=0; i0<10; i0++) begin
-        // Field: dv_reg.NonStickyDataVaultCtrl[].lock_entry
+        // Field: dv_reg.DataVaultCtrl[].lock_entry
         always_comb begin
-            automatic logic [0:0] next_c = field_storage.NonStickyDataVaultCtrl[i0].lock_entry.value;
+            automatic logic [0:0] next_c = field_storage.DataVaultCtrl[i0].lock_entry.value;
             automatic logic load_next_c = '0;
-            if(decoded_reg_strb.NonStickyDataVaultCtrl[i0] && decoded_req_is_wr && !(hwif_in.NonStickyDataVaultCtrl[i0].lock_entry.swwel)) begin // SW write
-                next_c = (field_storage.NonStickyDataVaultCtrl[i0].lock_entry.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
+            if(decoded_reg_strb.DataVaultCtrl[i0] && decoded_req_is_wr && !(hwif_in.DataVaultCtrl[i0].lock_entry.swwel)) begin // SW write
+                next_c = (field_storage.DataVaultCtrl[i0].lock_entry.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
                 load_next_c = '1;
             end
-            field_combo.NonStickyDataVaultCtrl[i0].lock_entry.next = next_c;
-            field_combo.NonStickyDataVaultCtrl[i0].lock_entry.load_next = load_next_c;
+            field_combo.DataVaultCtrl[i0].lock_entry.next = next_c;
+            field_combo.DataVaultCtrl[i0].lock_entry.load_next = load_next_c;
         end
         always_ff @(posedge clk or negedge hwif_in.core_only_rst_b) begin
             if(~hwif_in.core_only_rst_b) begin
-                field_storage.NonStickyDataVaultCtrl[i0].lock_entry.value <= 'h0;
-            end else if(field_combo.NonStickyDataVaultCtrl[i0].lock_entry.load_next) begin
-                field_storage.NonStickyDataVaultCtrl[i0].lock_entry.value <= field_combo.NonStickyDataVaultCtrl[i0].lock_entry.next;
+                field_storage.DataVaultCtrl[i0].lock_entry.value <= 'h0;
+            end else if(field_combo.DataVaultCtrl[i0].lock_entry.load_next) begin
+                field_storage.DataVaultCtrl[i0].lock_entry.value <= field_combo.DataVaultCtrl[i0].lock_entry.next;
             end
         end
-        assign hwif_out.NonStickyDataVaultCtrl[i0].lock_entry.value = field_storage.NonStickyDataVaultCtrl[i0].lock_entry.value;
+        assign hwif_out.DataVaultCtrl[i0].lock_entry.value = field_storage.DataVaultCtrl[i0].lock_entry.value;
     end
     for(genvar i0=0; i0<10; i0++) begin
         for(genvar i1=0; i1<12; i1++) begin
-            // Field: dv_reg.NONSTICKY_DATA_VAULT_ENTRY[][].data
+            // Field: dv_reg.DATA_VAULT_ENTRY[][].data
             always_comb begin
-                automatic logic [31:0] next_c = field_storage.NONSTICKY_DATA_VAULT_ENTRY[i0][i1].data.value;
+                automatic logic [31:0] next_c = field_storage.DATA_VAULT_ENTRY[i0][i1].data.value;
                 automatic logic load_next_c = '0;
-                if(decoded_reg_strb.NONSTICKY_DATA_VAULT_ENTRY[i0][i1] && decoded_req_is_wr && !(hwif_in.NONSTICKY_DATA_VAULT_ENTRY[i0][i1].data.swwel)) begin // SW write
-                    next_c = (field_storage.NONSTICKY_DATA_VAULT_ENTRY[i0][i1].data.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+                if(decoded_reg_strb.DATA_VAULT_ENTRY[i0][i1] && decoded_req_is_wr && !(hwif_in.DATA_VAULT_ENTRY[i0][i1].data.swwel)) begin // SW write
+                    next_c = (field_storage.DATA_VAULT_ENTRY[i0][i1].data.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
                     load_next_c = '1;
                 end
-                field_combo.NONSTICKY_DATA_VAULT_ENTRY[i0][i1].data.next = next_c;
-                field_combo.NONSTICKY_DATA_VAULT_ENTRY[i0][i1].data.load_next = load_next_c;
+                field_combo.DATA_VAULT_ENTRY[i0][i1].data.next = next_c;
+                field_combo.DATA_VAULT_ENTRY[i0][i1].data.load_next = load_next_c;
             end
-            always_ff @(posedge clk or negedge hwif_in.reset_b) begin
-                if(~hwif_in.reset_b) begin
-                    field_storage.NONSTICKY_DATA_VAULT_ENTRY[i0][i1].data.value <= 'h0;
-                end else if(field_combo.NONSTICKY_DATA_VAULT_ENTRY[i0][i1].data.load_next) begin
-                    field_storage.NONSTICKY_DATA_VAULT_ENTRY[i0][i1].data.value <= field_combo.NONSTICKY_DATA_VAULT_ENTRY[i0][i1].data.next;
+            always_ff @(posedge clk or negedge hwif_in.hard_reset_b) begin
+                if(~hwif_in.hard_reset_b) begin
+                    field_storage.DATA_VAULT_ENTRY[i0][i1].data.value <= 'h0;
+                end else if(field_combo.DATA_VAULT_ENTRY[i0][i1].data.load_next) begin
+                    field_storage.DATA_VAULT_ENTRY[i0][i1].data.value <= field_combo.DATA_VAULT_ENTRY[i0][i1].data.next;
                 end
             end
         end
     end
     for(genvar i0=0; i0<10; i0++) begin
-        // Field: dv_reg.NonStickyLockableScratchRegCtrl[].lock_entry
+        // Field: dv_reg.LockableScratchRegCtrl[].lock_entry
         always_comb begin
-            automatic logic [0:0] next_c = field_storage.NonStickyLockableScratchRegCtrl[i0].lock_entry.value;
+            automatic logic [0:0] next_c = field_storage.LockableScratchRegCtrl[i0].lock_entry.value;
             automatic logic load_next_c = '0;
-            if(decoded_reg_strb.NonStickyLockableScratchRegCtrl[i0] && decoded_req_is_wr && !(hwif_in.NonStickyLockableScratchRegCtrl[i0].lock_entry.swwel)) begin // SW write
-                next_c = (field_storage.NonStickyLockableScratchRegCtrl[i0].lock_entry.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
+            if(decoded_reg_strb.LockableScratchRegCtrl[i0] && decoded_req_is_wr && !(hwif_in.LockableScratchRegCtrl[i0].lock_entry.swwel)) begin // SW write
+                next_c = (field_storage.LockableScratchRegCtrl[i0].lock_entry.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
                 load_next_c = '1;
             end
-            field_combo.NonStickyLockableScratchRegCtrl[i0].lock_entry.next = next_c;
-            field_combo.NonStickyLockableScratchRegCtrl[i0].lock_entry.load_next = load_next_c;
+            field_combo.LockableScratchRegCtrl[i0].lock_entry.next = next_c;
+            field_combo.LockableScratchRegCtrl[i0].lock_entry.load_next = load_next_c;
         end
         always_ff @(posedge clk or negedge hwif_in.core_only_rst_b) begin
             if(~hwif_in.core_only_rst_b) begin
-                field_storage.NonStickyLockableScratchRegCtrl[i0].lock_entry.value <= 'h0;
-            end else if(field_combo.NonStickyLockableScratchRegCtrl[i0].lock_entry.load_next) begin
-                field_storage.NonStickyLockableScratchRegCtrl[i0].lock_entry.value <= field_combo.NonStickyLockableScratchRegCtrl[i0].lock_entry.next;
+                field_storage.LockableScratchRegCtrl[i0].lock_entry.value <= 'h0;
+            end else if(field_combo.LockableScratchRegCtrl[i0].lock_entry.load_next) begin
+                field_storage.LockableScratchRegCtrl[i0].lock_entry.value <= field_combo.LockableScratchRegCtrl[i0].lock_entry.next;
             end
         end
-        assign hwif_out.NonStickyLockableScratchRegCtrl[i0].lock_entry.value = field_storage.NonStickyLockableScratchRegCtrl[i0].lock_entry.value;
+        assign hwif_out.LockableScratchRegCtrl[i0].lock_entry.value = field_storage.LockableScratchRegCtrl[i0].lock_entry.value;
     end
     for(genvar i0=0; i0<10; i0++) begin
-        // Field: dv_reg.NonStickyLockableScratchReg[].data
+        // Field: dv_reg.LockableScratchReg[].data
         always_comb begin
-            automatic logic [31:0] next_c = field_storage.NonStickyLockableScratchReg[i0].data.value;
+            automatic logic [31:0] next_c = field_storage.LockableScratchReg[i0].data.value;
             automatic logic load_next_c = '0;
-            if(decoded_reg_strb.NonStickyLockableScratchReg[i0] && decoded_req_is_wr && !(hwif_in.NonStickyLockableScratchReg[i0].data.swwel)) begin // SW write
-                next_c = (field_storage.NonStickyLockableScratchReg[i0].data.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+            if(decoded_reg_strb.LockableScratchReg[i0] && decoded_req_is_wr && !(hwif_in.LockableScratchReg[i0].data.swwel)) begin // SW write
+                next_c = (field_storage.LockableScratchReg[i0].data.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
                 load_next_c = '1;
             end
-            field_combo.NonStickyLockableScratchReg[i0].data.next = next_c;
-            field_combo.NonStickyLockableScratchReg[i0].data.load_next = load_next_c;
+            field_combo.LockableScratchReg[i0].data.next = next_c;
+            field_combo.LockableScratchReg[i0].data.load_next = load_next_c;
         end
-        always_ff @(posedge clk or negedge hwif_in.reset_b) begin
-            if(~hwif_in.reset_b) begin
-                field_storage.NonStickyLockableScratchReg[i0].data.value <= 'h0;
-            end else if(field_combo.NonStickyLockableScratchReg[i0].data.load_next) begin
-                field_storage.NonStickyLockableScratchReg[i0].data.value <= field_combo.NonStickyLockableScratchReg[i0].data.next;
+        always_ff @(posedge clk or negedge hwif_in.hard_reset_b) begin
+            if(~hwif_in.hard_reset_b) begin
+                field_storage.LockableScratchReg[i0].data.value <= 'h0;
+            end else if(field_combo.LockableScratchReg[i0].data.load_next) begin
+                field_storage.LockableScratchReg[i0].data.value <= field_combo.LockableScratchReg[i0].data.next;
             end
         end
     end
@@ -441,20 +441,20 @@ module dv_reg (
         end
     end
     for(genvar i0=0; i0<10; i0++) begin
-        assign readback_array[i0*1 + 130][0:0] = (decoded_reg_strb.NonStickyDataVaultCtrl[i0] && !decoded_req_is_wr) ? field_storage.NonStickyDataVaultCtrl[i0].lock_entry.value : '0;
+        assign readback_array[i0*1 + 130][0:0] = (decoded_reg_strb.DataVaultCtrl[i0] && !decoded_req_is_wr) ? field_storage.DataVaultCtrl[i0].lock_entry.value : '0;
         assign readback_array[i0*1 + 130][31:1] = '0;
     end
     for(genvar i0=0; i0<10; i0++) begin
         for(genvar i1=0; i1<12; i1++) begin
-            assign readback_array[i0*12 + i1*1 + 140][31:0] = (decoded_reg_strb.NONSTICKY_DATA_VAULT_ENTRY[i0][i1] && !decoded_req_is_wr) ? field_storage.NONSTICKY_DATA_VAULT_ENTRY[i0][i1].data.value : '0;
+            assign readback_array[i0*12 + i1*1 + 140][31:0] = (decoded_reg_strb.DATA_VAULT_ENTRY[i0][i1] && !decoded_req_is_wr) ? field_storage.DATA_VAULT_ENTRY[i0][i1].data.value : '0;
         end
     end
     for(genvar i0=0; i0<10; i0++) begin
-        assign readback_array[i0*1 + 260][0:0] = (decoded_reg_strb.NonStickyLockableScratchRegCtrl[i0] && !decoded_req_is_wr) ? field_storage.NonStickyLockableScratchRegCtrl[i0].lock_entry.value : '0;
+        assign readback_array[i0*1 + 260][0:0] = (decoded_reg_strb.LockableScratchRegCtrl[i0] && !decoded_req_is_wr) ? field_storage.LockableScratchRegCtrl[i0].lock_entry.value : '0;
         assign readback_array[i0*1 + 260][31:1] = '0;
     end
     for(genvar i0=0; i0<10; i0++) begin
-        assign readback_array[i0*1 + 270][31:0] = (decoded_reg_strb.NonStickyLockableScratchReg[i0] && !decoded_req_is_wr) ? field_storage.NonStickyLockableScratchReg[i0].data.value : '0;
+        assign readback_array[i0*1 + 270][31:0] = (decoded_reg_strb.LockableScratchReg[i0] && !decoded_req_is_wr) ? field_storage.LockableScratchReg[i0].data.value : '0;
     end
     for(genvar i0=0; i0<8; i0++) begin
         assign readback_array[i0*1 + 280][31:0] = (decoded_reg_strb.NonStickyGenericScratchReg[i0] && !decoded_req_is_wr) ? field_storage.NonStickyGenericScratchReg[i0].data.value : '0;
diff --git a/src/datavault/rtl/dv_reg_pkg.sv b/src/datavault/rtl/dv_reg_pkg.sv
index 465927a3b..ee3801467 100644
--- a/src/datavault/rtl/dv_reg_pkg.sv
+++ b/src/datavault/rtl/dv_reg_pkg.sv
@@ -20,35 +20,35 @@ package dv_reg_pkg;
 
     typedef struct packed{
         logic swwel;
-    } dv_reg__NonStickyDataVaultCtrl__lock_entry__in_t;
+    } dv_reg__DataVaultCtrl__lock_entry__in_t;
 
     typedef struct packed{
-        dv_reg__NonStickyDataVaultCtrl__lock_entry__in_t lock_entry;
-    } dv_reg__NonStickyDataVaultCtrl__in_t;
+        dv_reg__DataVaultCtrl__lock_entry__in_t lock_entry;
+    } dv_reg__DataVaultCtrl__in_t;
 
     typedef struct packed{
         logic swwel;
-    } dv_reg__NonStickyDataVaultEntry_w32__in_t;
+    } dv_reg__DataVaultEntry_w32__in_t;
 
     typedef struct packed{
-        dv_reg__NonStickyDataVaultEntry_w32__in_t data;
-    } dv_reg__NonStickyDataVaultReg__in_t;
+        dv_reg__DataVaultEntry_w32__in_t data;
+    } dv_reg__DataVaultReg__in_t;
 
     typedef struct packed{
         logic swwel;
-    } dv_reg__NonStickyLockableScratchRegCtrl__lock_entry__in_t;
+    } dv_reg__LockableScratchRegCtrl__lock_entry__in_t;
 
     typedef struct packed{
-        dv_reg__NonStickyLockableScratchRegCtrl__lock_entry__in_t lock_entry;
-    } dv_reg__NonStickyLockableScratchRegCtrl__in_t;
+        dv_reg__LockableScratchRegCtrl__lock_entry__in_t lock_entry;
+    } dv_reg__LockableScratchRegCtrl__in_t;
 
     typedef struct packed{
         logic swwel;
-    } dv_reg__NonStickyLockableScratchReg__data__in_t;
+    } dv_reg__LockableScratchReg__data__in_t;
 
     typedef struct packed{
-        dv_reg__NonStickyLockableScratchReg__data__in_t data;
-    } dv_reg__NonStickyLockableScratchReg__in_t;
+        dv_reg__LockableScratchReg__data__in_t data;
+    } dv_reg__LockableScratchReg__in_t;
 
     typedef struct packed{
         logic swwel;
@@ -72,10 +72,10 @@ package dv_reg_pkg;
         logic hard_reset_b;
         dv_reg__StickyDataVaultCtrl__in_t [10-1:0]StickyDataVaultCtrl;
         dv_reg__StickyDataVaultReg__in_t [10-1:0][12-1:0]STICKY_DATA_VAULT_ENTRY;
-        dv_reg__NonStickyDataVaultCtrl__in_t [10-1:0]NonStickyDataVaultCtrl;
-        dv_reg__NonStickyDataVaultReg__in_t [10-1:0][12-1:0]NONSTICKY_DATA_VAULT_ENTRY;
-        dv_reg__NonStickyLockableScratchRegCtrl__in_t [10-1:0]NonStickyLockableScratchRegCtrl;
-        dv_reg__NonStickyLockableScratchReg__in_t [10-1:0]NonStickyLockableScratchReg;
+        dv_reg__DataVaultCtrl__in_t [10-1:0]DataVaultCtrl;
+        dv_reg__DataVaultReg__in_t [10-1:0][12-1:0]DATA_VAULT_ENTRY;
+        dv_reg__LockableScratchRegCtrl__in_t [10-1:0]LockableScratchRegCtrl;
+        dv_reg__LockableScratchReg__in_t [10-1:0]LockableScratchReg;
         dv_reg__StickyLockableScratchRegCtrl__in_t [8-1:0]StickyLockableScratchRegCtrl;
         dv_reg__StickyLockableScratchReg__in_t [8-1:0]StickyLockableScratchReg;
     } dv_reg__in_t;
@@ -90,19 +90,19 @@ package dv_reg_pkg;
 
     typedef struct packed{
         logic value;
-    } dv_reg__NonStickyDataVaultCtrl__lock_entry__out_t;
+    } dv_reg__DataVaultCtrl__lock_entry__out_t;
 
     typedef struct packed{
-        dv_reg__NonStickyDataVaultCtrl__lock_entry__out_t lock_entry;
-    } dv_reg__NonStickyDataVaultCtrl__out_t;
+        dv_reg__DataVaultCtrl__lock_entry__out_t lock_entry;
+    } dv_reg__DataVaultCtrl__out_t;
 
     typedef struct packed{
         logic value;
-    } dv_reg__NonStickyLockableScratchRegCtrl__lock_entry__out_t;
+    } dv_reg__LockableScratchRegCtrl__lock_entry__out_t;
 
     typedef struct packed{
-        dv_reg__NonStickyLockableScratchRegCtrl__lock_entry__out_t lock_entry;
-    } dv_reg__NonStickyLockableScratchRegCtrl__out_t;
+        dv_reg__LockableScratchRegCtrl__lock_entry__out_t lock_entry;
+    } dv_reg__LockableScratchRegCtrl__out_t;
 
     typedef struct packed{
         logic value;
@@ -114,8 +114,8 @@ package dv_reg_pkg;
 
     typedef struct packed{
         dv_reg__StickyDataVaultCtrl__out_t [10-1:0]StickyDataVaultCtrl;
-        dv_reg__NonStickyDataVaultCtrl__out_t [10-1:0]NonStickyDataVaultCtrl;
-        dv_reg__NonStickyLockableScratchRegCtrl__out_t [10-1:0]NonStickyLockableScratchRegCtrl;
+        dv_reg__DataVaultCtrl__out_t [10-1:0]DataVaultCtrl;
+        dv_reg__LockableScratchRegCtrl__out_t [10-1:0]LockableScratchRegCtrl;
         dv_reg__StickyLockableScratchRegCtrl__out_t [8-1:0]StickyLockableScratchRegCtrl;
     } dv_reg__out_t;
 
diff --git a/src/datavault/rtl/dv_reg_uvm.sv b/src/datavault/rtl/dv_reg_uvm.sv
index 4c4ac0719..9517e8221 100644
--- a/src/datavault/rtl/dv_reg_uvm.sv
+++ b/src/datavault/rtl/dv_reg_uvm.sv
@@ -3,130 +3,274 @@
 package dv_reg_uvm;
     `include "uvm_macros.svh"
     import uvm_pkg::*;
-    
+    `include "dv_reg_covergroups.svh"
     // Reg - dv_reg::StickyDataVaultCtrl
     class dv_reg__StickyDataVaultCtrl extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        dv_reg__StickyDataVaultCtrl_bit_cg lock_entry_bit_cg[1];
+        dv_reg__StickyDataVaultCtrl_fld_cg fld_cg;
         rand uvm_reg_field lock_entry;
 
         function new(string name = "dv_reg__StickyDataVaultCtrl");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.lock_entry = new("lock_entry");
             this.lock_entry.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(lock_entry_bit_cg[bt]) lock_entry_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : dv_reg__StickyDataVaultCtrl
 
     // Reg - dv_reg::StickyDataVaultReg
     class dv_reg__StickyDataVaultReg extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        dv_reg__StickyDataVaultReg_bit_cg data_bit_cg[32];
+        dv_reg__StickyDataVaultReg_fld_cg fld_cg;
         rand uvm_reg_field data;
 
         function new(string name = "dv_reg__StickyDataVaultReg");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.data = new("data");
             this.data.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(data_bit_cg[bt]) data_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : dv_reg__StickyDataVaultReg
 
-    // Reg - dv_reg::NonStickyDataVaultCtrl
-    class dv_reg__NonStickyDataVaultCtrl extends uvm_reg;
+    // Reg - dv_reg::DataVaultCtrl
+    class dv_reg__DataVaultCtrl extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        dv_reg__DataVaultCtrl_bit_cg lock_entry_bit_cg[1];
+        dv_reg__DataVaultCtrl_fld_cg fld_cg;
         rand uvm_reg_field lock_entry;
 
-        function new(string name = "dv_reg__NonStickyDataVaultCtrl");
-            super.new(name, 32, UVM_NO_COVERAGE);
+        function new(string name = "dv_reg__DataVaultCtrl");
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.lock_entry = new("lock_entry");
             this.lock_entry.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(lock_entry_bit_cg[bt]) lock_entry_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
-    endclass : dv_reg__NonStickyDataVaultCtrl
+    endclass : dv_reg__DataVaultCtrl
+
+    // Reg - dv_reg::DataVaultReg
+    class dv_reg__DataVaultReg extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
 
-    // Reg - dv_reg::NonStickyDataVaultReg
-    class dv_reg__NonStickyDataVaultReg extends uvm_reg;
+        dv_reg__DataVaultReg_bit_cg data_bit_cg[32];
+        dv_reg__DataVaultReg_fld_cg fld_cg;
         rand uvm_reg_field data;
 
-        function new(string name = "dv_reg__NonStickyDataVaultReg");
-            super.new(name, 32, UVM_NO_COVERAGE);
+        function new(string name = "dv_reg__DataVaultReg");
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.data = new("data");
             this.data.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(data_bit_cg[bt]) data_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
-    endclass : dv_reg__NonStickyDataVaultReg
+    endclass : dv_reg__DataVaultReg
+
+    // Reg - dv_reg::LockableScratchRegCtrl
+    class dv_reg__LockableScratchRegCtrl extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
 
-    // Reg - dv_reg::NonStickyLockableScratchRegCtrl
-    class dv_reg__NonStickyLockableScratchRegCtrl extends uvm_reg;
+        dv_reg__LockableScratchRegCtrl_bit_cg lock_entry_bit_cg[1];
+        dv_reg__LockableScratchRegCtrl_fld_cg fld_cg;
         rand uvm_reg_field lock_entry;
 
-        function new(string name = "dv_reg__NonStickyLockableScratchRegCtrl");
-            super.new(name, 32, UVM_NO_COVERAGE);
+        function new(string name = "dv_reg__LockableScratchRegCtrl");
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.lock_entry = new("lock_entry");
             this.lock_entry.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(lock_entry_bit_cg[bt]) lock_entry_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
-    endclass : dv_reg__NonStickyLockableScratchRegCtrl
+    endclass : dv_reg__LockableScratchRegCtrl
+
+    // Reg - dv_reg::LockableScratchReg
+    class dv_reg__LockableScratchReg extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
 
-    // Reg - dv_reg::NonStickyLockableScratchReg
-    class dv_reg__NonStickyLockableScratchReg extends uvm_reg;
+        dv_reg__LockableScratchReg_bit_cg data_bit_cg[32];
+        dv_reg__LockableScratchReg_fld_cg fld_cg;
         rand uvm_reg_field data;
 
-        function new(string name = "dv_reg__NonStickyLockableScratchReg");
-            super.new(name, 32, UVM_NO_COVERAGE);
+        function new(string name = "dv_reg__LockableScratchReg");
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.data = new("data");
             this.data.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(data_bit_cg[bt]) data_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
-    endclass : dv_reg__NonStickyLockableScratchReg
+    endclass : dv_reg__LockableScratchReg
 
     // Reg - dv_reg::NonStickyGenericScratchReg
     class dv_reg__NonStickyGenericScratchReg extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        dv_reg__NonStickyGenericScratchReg_bit_cg data_bit_cg[32];
+        dv_reg__NonStickyGenericScratchReg_fld_cg fld_cg;
         rand uvm_reg_field data;
 
         function new(string name = "dv_reg__NonStickyGenericScratchReg");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.data = new("data");
             this.data.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(data_bit_cg[bt]) data_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : dv_reg__NonStickyGenericScratchReg
 
     // Reg - dv_reg::StickyLockableScratchRegCtrl
     class dv_reg__StickyLockableScratchRegCtrl extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        dv_reg__StickyLockableScratchRegCtrl_bit_cg lock_entry_bit_cg[1];
+        dv_reg__StickyLockableScratchRegCtrl_fld_cg fld_cg;
         rand uvm_reg_field lock_entry;
 
         function new(string name = "dv_reg__StickyLockableScratchRegCtrl");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.lock_entry = new("lock_entry");
             this.lock_entry.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(lock_entry_bit_cg[bt]) lock_entry_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : dv_reg__StickyLockableScratchRegCtrl
 
     // Reg - dv_reg::StickyLockableScratchReg
     class dv_reg__StickyLockableScratchReg extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        dv_reg__StickyLockableScratchReg_bit_cg data_bit_cg[32];
+        dv_reg__StickyLockableScratchReg_fld_cg fld_cg;
         rand uvm_reg_field data;
 
         function new(string name = "dv_reg__StickyLockableScratchReg");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.data = new("data");
             this.data.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(data_bit_cg[bt]) data_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : dv_reg__StickyLockableScratchReg
 
@@ -134,10 +278,10 @@ package dv_reg_uvm;
     class dv_reg extends uvm_reg_block;
         rand dv_reg__StickyDataVaultCtrl StickyDataVaultCtrl[10];
         rand dv_reg__StickyDataVaultReg STICKY_DATA_VAULT_ENTRY[10][12];
-        rand dv_reg__NonStickyDataVaultCtrl NonStickyDataVaultCtrl[10];
-        rand dv_reg__NonStickyDataVaultReg NONSTICKY_DATA_VAULT_ENTRY[10][12];
-        rand dv_reg__NonStickyLockableScratchRegCtrl NonStickyLockableScratchRegCtrl[10];
-        rand dv_reg__NonStickyLockableScratchReg NonStickyLockableScratchReg[10];
+        rand dv_reg__DataVaultCtrl DataVaultCtrl[10];
+        rand dv_reg__DataVaultReg DATA_VAULT_ENTRY[10][12];
+        rand dv_reg__LockableScratchRegCtrl LockableScratchRegCtrl[10];
+        rand dv_reg__LockableScratchReg LockableScratchReg[10];
         rand dv_reg__NonStickyGenericScratchReg NonStickyGenericScratchReg[8];
         rand dv_reg__StickyLockableScratchRegCtrl StickyLockableScratchRegCtrl[8];
         rand dv_reg__StickyLockableScratchReg StickyLockableScratchReg[8];
@@ -162,33 +306,33 @@ package dv_reg_uvm;
                 this.STICKY_DATA_VAULT_ENTRY[i0][i1].build();
                 this.default_map.add_reg(this.STICKY_DATA_VAULT_ENTRY[i0][i1], 'h28 + i0*'h30 + i1*'h4);
             end
-            foreach(this.NonStickyDataVaultCtrl[i0]) begin
-                this.NonStickyDataVaultCtrl[i0] = new($sformatf("NonStickyDataVaultCtrl[%0d]", i0));
-                this.NonStickyDataVaultCtrl[i0].configure(this);
+            foreach(this.DataVaultCtrl[i0]) begin
+                this.DataVaultCtrl[i0] = new($sformatf("DataVaultCtrl[%0d]", i0));
+                this.DataVaultCtrl[i0].configure(this);
                 
-                this.NonStickyDataVaultCtrl[i0].build();
-                this.default_map.add_reg(this.NonStickyDataVaultCtrl[i0], 'h208 + i0*'h4);
+                this.DataVaultCtrl[i0].build();
+                this.default_map.add_reg(this.DataVaultCtrl[i0], 'h208 + i0*'h4);
             end
-            foreach(this.NONSTICKY_DATA_VAULT_ENTRY[i0, i1]) begin
-                this.NONSTICKY_DATA_VAULT_ENTRY[i0][i1] = new($sformatf("NONSTICKY_DATA_VAULT_ENTRY[%0d][%0d]", i0, i1));
-                this.NONSTICKY_DATA_VAULT_ENTRY[i0][i1].configure(this);
+            foreach(this.DATA_VAULT_ENTRY[i0, i1]) begin
+                this.DATA_VAULT_ENTRY[i0][i1] = new($sformatf("DATA_VAULT_ENTRY[%0d][%0d]", i0, i1));
+                this.DATA_VAULT_ENTRY[i0][i1].configure(this);
                 
-                this.NONSTICKY_DATA_VAULT_ENTRY[i0][i1].build();
-                this.default_map.add_reg(this.NONSTICKY_DATA_VAULT_ENTRY[i0][i1], 'h230 + i0*'h30 + i1*'h4);
+                this.DATA_VAULT_ENTRY[i0][i1].build();
+                this.default_map.add_reg(this.DATA_VAULT_ENTRY[i0][i1], 'h230 + i0*'h30 + i1*'h4);
             end
-            foreach(this.NonStickyLockableScratchRegCtrl[i0]) begin
-                this.NonStickyLockableScratchRegCtrl[i0] = new($sformatf("NonStickyLockableScratchRegCtrl[%0d]", i0));
-                this.NonStickyLockableScratchRegCtrl[i0].configure(this);
+            foreach(this.LockableScratchRegCtrl[i0]) begin
+                this.LockableScratchRegCtrl[i0] = new($sformatf("LockableScratchRegCtrl[%0d]", i0));
+                this.LockableScratchRegCtrl[i0].configure(this);
                 
-                this.NonStickyLockableScratchRegCtrl[i0].build();
-                this.default_map.add_reg(this.NonStickyLockableScratchRegCtrl[i0], 'h410 + i0*'h4);
+                this.LockableScratchRegCtrl[i0].build();
+                this.default_map.add_reg(this.LockableScratchRegCtrl[i0], 'h410 + i0*'h4);
             end
-            foreach(this.NonStickyLockableScratchReg[i0]) begin
-                this.NonStickyLockableScratchReg[i0] = new($sformatf("NonStickyLockableScratchReg[%0d]", i0));
-                this.NonStickyLockableScratchReg[i0].configure(this);
+            foreach(this.LockableScratchReg[i0]) begin
+                this.LockableScratchReg[i0] = new($sformatf("LockableScratchReg[%0d]", i0));
+                this.LockableScratchReg[i0].configure(this);
                 
-                this.NonStickyLockableScratchReg[i0].build();
-                this.default_map.add_reg(this.NonStickyLockableScratchReg[i0], 'h438 + i0*'h4);
+                this.LockableScratchReg[i0].build();
+                this.default_map.add_reg(this.LockableScratchReg[i0], 'h438 + i0*'h4);
             end
             foreach(this.NonStickyGenericScratchReg[i0]) begin
                 this.NonStickyGenericScratchReg[i0] = new($sformatf("NonStickyGenericScratchReg[%0d]", i0));
@@ -214,4 +358,5 @@ package dv_reg_uvm;
         endfunction : build
     endclass : dv_reg
 
+    `include "dv_reg_sample.svh"
 endpackage: dv_reg_uvm
diff --git a/src/doe/config/compile.yml b/src/doe/config/compile.yml
index 7b1815664..39c70d8c4 100755
--- a/src/doe/config/compile.yml
+++ b/src/doe/config/compile.yml
@@ -53,6 +53,18 @@ targets:
     files:
       - $COMPILE_ROOT/tb/doe_cbc_tb.sv
     tops: [doe_cbc_tb]
+---
+provides: [doe_core_cbc_tb]  
+schema_version: 2.4.0
+requires: 
+  - doe_ctrl
+targets:
+  tb:
+    directories: 
+      - $COMPILE_ROOT/tb
+    files:
+      - $COMPILE_ROOT/tb/doe_core_cbc_tb.sv
+    tops: [doe_core_cbc_tb]    
 global:
   tool:
     vcs:
diff --git a/src/doe/config/doe_cbc_tb.vf b/src/doe/config/doe_cbc_tb.vf
index 6feae6b6b..343b1bc45 100644
--- a/src/doe/config/doe_cbc_tb.vf
+++ b/src/doe/config/doe_cbc_tb.vf
@@ -14,6 +14,7 @@ ${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
 ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_defines_pkg.sv
 ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_macros.svh
 ${CALIPTRA_ROOT}/src/doe/rtl/doe_defines_pkg.sv
diff --git a/src/doe/config/doe_core_cbc_tb.vf b/src/doe/config/doe_core_cbc_tb.vf
new file mode 100644
index 000000000..be61bb115
--- /dev/null
+++ b/src/doe/config/doe_core_cbc_tb.vf
@@ -0,0 +1,39 @@
++incdir+${CALIPTRA_ROOT}/src/integration/rtl
++incdir+${CALIPTRA_ROOT}/src/libs/rtl
++incdir+${CALIPTRA_ROOT}/src/keyvault/rtl
++incdir+${CALIPTRA_ROOT}/src/doe/rtl
++incdir+${CALIPTRA_ROOT}/src/doe/tb
+${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh
+${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sva.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_macros.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sram.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_defines_pkg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_ahb_srom.sv
+${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
+${CALIPTRA_ROOT}/src/keyvault/rtl/kv_defines_pkg.sv
+${CALIPTRA_ROOT}/src/keyvault/rtl/kv_macros.svh
+${CALIPTRA_ROOT}/src/doe/rtl/doe_defines_pkg.sv
+${CALIPTRA_ROOT}/src/doe/tb/doe_core_cbc_tb.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
+${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg_pkg.sv
+${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg.sv
+${CALIPTRA_ROOT}/src/keyvault/rtl/kv.sv
+${CALIPTRA_ROOT}/src/keyvault/rtl/kv_fsm.sv
+${CALIPTRA_ROOT}/src/keyvault/rtl/kv_read_client.sv
+${CALIPTRA_ROOT}/src/keyvault/rtl/kv_write_client.sv
+${CALIPTRA_ROOT}/src/doe/rtl/doe_reg_pkg.sv
+${CALIPTRA_ROOT}/src/doe/rtl/doe_ctrl.sv
+${CALIPTRA_ROOT}/src/doe/rtl/doe_decipher_block.sv
+${CALIPTRA_ROOT}/src/doe/rtl/doe_encipher_block.sv
+${CALIPTRA_ROOT}/src/doe/rtl/doe_inv_sbox.sv
+${CALIPTRA_ROOT}/src/doe/rtl/doe_key_mem.sv
+${CALIPTRA_ROOT}/src/doe/rtl/doe_sbox.sv
+${CALIPTRA_ROOT}/src/doe/rtl/doe_cbc.sv
+${CALIPTRA_ROOT}/src/doe/rtl/doe_core_cbc.sv
+${CALIPTRA_ROOT}/src/doe/rtl/doe_reg.sv
+${CALIPTRA_ROOT}/src/doe/rtl/doe_fsm.sv
\ No newline at end of file
diff --git a/src/doe/config/doe_ctrl.vf b/src/doe/config/doe_ctrl.vf
index e4141e256..09ff0b298 100644
--- a/src/doe/config/doe_ctrl.vf
+++ b/src/doe/config/doe_ctrl.vf
@@ -13,6 +13,7 @@ ${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
 ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_defines_pkg.sv
 ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_macros.svh
 ${CALIPTRA_ROOT}/src/doe/rtl/doe_defines_pkg.sv
diff --git a/src/doe/coverage/config/doe_cm_hier.cfg b/src/doe/coverage/config/doe_cm_hier.cfg
new file mode 100644
index 000000000..bcd0cda31
--- /dev/null
+++ b/src/doe/coverage/config/doe_cm_hier.cfg
@@ -0,0 +1,3 @@
+begin line+tgl+fsm+cond+branch
+    +tree doe_core_cbc_tb.dut 0
+end
\ No newline at end of file
diff --git a/src/doe/rtl/doe_cbc.sv b/src/doe/rtl/doe_cbc.sv
index 68f15f0d4..70dec5840 100644
--- a/src/doe/rtl/doe_cbc.sv
+++ b/src/doe/rtl/doe_cbc.sv
@@ -67,7 +67,8 @@ module doe_cbc
    output logic clear_obf_secrets,
 
    //interface with kv
-   output kv_write_t kv_write
+   output kv_write_t kv_write,
+   input  logic debugUnlock_or_scan_mode_switch
   );
 
   //----------------------------------------------------------------
@@ -106,6 +107,7 @@ module doe_cbc
 
   logic doe_init;
   logic doe_next;
+  logic zeroize;
 
   logic flow_done;
   logic flow_in_progress, lock_fe_flow, lock_uds_flow;
@@ -133,6 +135,7 @@ module doe_cbc
   doe_core_cbc i_doe_core_cbc(
                 .clk(clk),
                 .reset_n(reset_n),
+                .zeroize(zeroize),
 
                 .encdec(core_encdec),
                 .init_cmd(core_init),
@@ -163,6 +166,11 @@ module doe_cbc
           ready_reg <= '0;
           kv_result_reg <= '0;
       end
+      else if (zeroize) begin
+          block_reg <= '0;
+          ready_reg <= '0;
+          kv_result_reg <= '0;
+      end
       else begin
           ready_reg  <= core_ready;
           kv_result_reg <= core_result;
@@ -191,7 +199,8 @@ assign doe_cmd_reg.dest_sel = hwif_out.DOE_CTRL.DEST.value;
 
 //FW can do this to clear the obfuscation related secrets
 //the Obfuscated UDS, FE, and OBF KEY
-always_comb clear_obf_secrets = (doe_cmd_reg.cmd == DOE_CLEAR);
+always_comb clear_obf_secrets = (doe_cmd_reg.cmd == DOE_CLEAR) || debugUnlock_or_scan_mode_switch;
+always_comb zeroize = clear_obf_secrets;
 
 always_comb begin
   IV_updated = '0;
@@ -201,6 +210,13 @@ always_comb begin
   end
 end
 
+//TODO: flow_done also?
+always_comb begin
+  for (int dword = 0; dword < IV_NO; dword++) begin
+    hwif_in.DOE_IV[dword].IV.hwclr = zeroize;
+  end
+end
+
 doe_fsm
 doe_fsm1 
 (
@@ -231,7 +247,8 @@ doe_fsm1
   .flow_done(flow_done),
   .flow_in_progress(flow_in_progress),
   .lock_uds_flow(lock_uds_flow),
-  .lock_fe_flow(lock_fe_flow)
+  .lock_fe_flow(lock_fe_flow),
+  .zeroize(zeroize)
 
 );
 
diff --git a/src/doe/rtl/doe_core_cbc.sv b/src/doe/rtl/doe_core_cbc.sv
index 69f473122..213fe2d80 100644
--- a/src/doe/rtl/doe_core_cbc.sv
+++ b/src/doe/rtl/doe_core_cbc.sv
@@ -47,6 +47,7 @@ module doe_core_cbc(
                 // Clock and reset.
                 input wire            clk,
                 input wire            reset_n,
+                input wire            zeroize,
 
                 // Control.
                 input wire            encdec,
@@ -143,6 +144,7 @@ module doe_core_cbc(
   doe_encipher_block enc_block(
                                .clk(clk),
                                .reset_n(reset_n),
+                               .zeroize(zeroize),
 
                                .next_cmd(enc_next),
 
@@ -162,6 +164,7 @@ module doe_core_cbc(
   doe_decipher_block dec_block(
                                .clk(clk),
                                .reset_n(reset_n),
+                               .zeroize(zeroize),
 
                                .next_cmd(dec_next),
 
@@ -178,6 +181,7 @@ module doe_core_cbc(
   doe_key_mem keymem(
                      .clk(clk),
                      .reset_n(reset_n),
+                     .zeroize(zeroize),
 
                      .key(key),
                      .keylen(keylen),
@@ -215,6 +219,15 @@ module doe_core_cbc(
           IV_dec_state        <= st_IV_engine_idle;
           IV_updated_delayed  <= 1'b0;
         end
+      else if (zeroize)
+        begin
+          IV_encry            <= 128'h0;
+          IV_decry            <= 128'h0;
+          IV_decry_next       <= 128'h0;
+          IV_enc_state        <= st_IV_engine_idle;
+          IV_dec_state        <= st_IV_engine_idle;
+          IV_updated_delayed  <= 1'b0;
+        end
       else
         begin
             
@@ -325,6 +338,12 @@ module doe_core_cbc(
           ready_reg         <= 1'b1;
           doe_core_ctrl_reg <= CTRL_IDLE;
         end
+      else if (zeroize)
+        begin
+          result_valid_reg  <= 1'b0;
+          ready_reg         <= 1'b1;
+          doe_core_ctrl_reg <= CTRL_IDLE;
+        end
       else
         begin
           if (result_valid_we)
diff --git a/src/doe/rtl/doe_ctrl.sv b/src/doe/rtl/doe_ctrl.sv
index bcf05c9fa..03fb1306f 100644
--- a/src/doe/rtl/doe_ctrl.sv
+++ b/src/doe/rtl/doe_ctrl.sv
@@ -61,7 +61,8 @@ module doe_ctrl
 
     // Interrupt
     output logic error_intr,
-    output logic notif_intr
+    output logic notif_intr,
+    input  logic debugUnlock_or_scan_mode_switch
 );
 
     //----------------------------------------------------------------
@@ -91,7 +92,8 @@ module doe_ctrl
         .error_intr(error_intr),
         .notif_intr(notif_intr),
         .clear_obf_secrets(clear_obf_secrets),
-        .kv_write(kv_write)
+        .kv_write(kv_write),
+        .debugUnlock_or_scan_mode_switch(debugUnlock_or_scan_mode_switch)
     );
 
 
diff --git a/src/doe/rtl/doe_decipher_block.sv b/src/doe/rtl/doe_decipher_block.sv
index 236b7a8d6..3fef11af7 100644
--- a/src/doe/rtl/doe_decipher_block.sv
+++ b/src/doe/rtl/doe_decipher_block.sv
@@ -42,6 +42,7 @@ module doe_decipher_block(
                           //Clock and reset.
                           input wire            clk,
                           input wire            reset_n,
+                          input wire            zeroize,
 
                           //Control
                           input wire            next_cmd,
@@ -265,6 +266,17 @@ module doe_decipher_block(
           ready_reg     <= 1'b1;
           dec_ctrl_reg  <= CTRL_IDLE;
         end
+      else if (zeroize)
+        begin
+          block_w0_reg  <= 32'h0;
+          block_w1_reg  <= 32'h0;
+          block_w2_reg  <= 32'h0;
+          block_w3_reg  <= 32'h0;
+          sword_ctr_reg <= 2'h0;
+          round_ctr_reg <= 4'h0;
+          ready_reg     <= 1'b1;
+          dec_ctrl_reg  <= CTRL_IDLE;
+        end
       else
         begin
           if (block_w0_we)
diff --git a/src/doe/rtl/doe_defines_pkg.sv b/src/doe/rtl/doe_defines_pkg.sv
index 1f9dc1cbf..b5032b3fe 100644
--- a/src/doe/rtl/doe_defines_pkg.sv
+++ b/src/doe/rtl/doe_defines_pkg.sv
@@ -22,39 +22,6 @@ package doe_defines_pkg;
   //----------------------------------------------------------------
   // Internal constant and parameter definitions.
   //----------------------------------------------------------------
-  localparam DOE_ADDR_NAME0        = 32'h00000000;
-  localparam DOE_ADDR_NAME1        = 32'h00000004;
-  localparam DOE_ADDR_VERSION0     = 32'h00000008;
-  localparam DOE_ADDR_VERSION1     = 32'h0000000c;
-
-  localparam DOE_ADDR_CTRL        = 32'h00000010;
-  localparam DOE_CTRL_INIT_BIT    = 0;
-  localparam DOE_CTRL_NEXT_BIT    = 1;
-
-  localparam DOE_ADDR_STATUS      = 32'h00000018;
-  localparam DOE_STATUS_READY_BIT = 0;
-  localparam DOE_STATUS_VALID_BIT = 1;
-
-  localparam DOE_ADDR_CONFIG      = 32'h00000020;
-  localparam DOE_CTRL_ENCDEC_BIT  = 0;
-  localparam DOE_CTRL_KEYLEN_BIT  = 1;
-
-  localparam DOE_ADDR_KEY_START   = 32'h00000040;
-  localparam DOE_ADDR_KEY_END     = 32'h0000005c;
-
-  localparam DOE_ADDR_BLOCK_START = 32'h00000080;
-  localparam DOE_ADDR_BLOCK_END   = 32'h0000008c;
-
-  localparam DOE_ADDR_RESULT_START= 32'h00000100;
-  localparam DOE_ADDR_RESULT_END  = 32'h0000010c;
-
-  localparam DOE_ADDR_IV_START = 32'h00000110;
-  localparam DOE_ADDR_IV_END   = 32'h0000011c;
-
-  localparam DOE_ADDR_KV_CTRL  = 32'h00000200;
-
-  localparam DOE_ADDR_INTR_START = 32'h00000800; // span = 0x400; 0x800 base offset matches mailbox for fw ease
-  localparam DOE_ADDR_INTR_END   = 32'h00000BFC;
 
   localparam DOE_CORE_NAME        = 64'h20202020_73206165; // "doe "
   localparam DOE_CORE_VERSION     = 64'h00000000_3630302e; // "0.60"
diff --git a/src/doe/rtl/doe_encipher_block.sv b/src/doe/rtl/doe_encipher_block.sv
index 2249d4419..faf9347b4 100644
--- a/src/doe/rtl/doe_encipher_block.sv
+++ b/src/doe/rtl/doe_encipher_block.sv
@@ -41,6 +41,7 @@
 module doe_encipher_block(
                           input wire            clk,
                           input wire            reset_n,
+                          input wire            zeroize,
 
                           input wire            next_cmd,
 
@@ -224,6 +225,17 @@ module doe_encipher_block(
           ready_reg     <= 1'b1;
           enc_ctrl_reg  <= CTRL_IDLE;
         end
+      else if (zeroize)
+        begin
+          block_w0_reg  <= 32'h0;
+          block_w1_reg  <= 32'h0;
+          block_w2_reg  <= 32'h0;
+          block_w3_reg  <= 32'h0;
+          sword_ctr_reg <= 2'h0;
+          round_ctr_reg <= 4'h0;
+          ready_reg     <= 1'b1;
+          enc_ctrl_reg  <= CTRL_IDLE;
+        end
       else
         begin
           if (block_w0_we)
diff --git a/src/doe/rtl/doe_fsm.sv b/src/doe/rtl/doe_fsm.sv
index 32717e4ab..f6f1a934f 100644
--- a/src/doe/rtl/doe_fsm.sv
+++ b/src/doe/rtl/doe_fsm.sv
@@ -57,7 +57,8 @@ module doe_fsm
     output logic flow_done,
     output logic flow_in_progress,
     output logic lock_uds_flow,
-    output logic lock_fe_flow
+    output logic lock_fe_flow,
+    input  logic zeroize
 );
 localparam UDS_BLOCK_OFFSET_W = $clog2(UDS_NUM_BLOCKS);
 localparam FE_BLOCK_OFFSET_W = $clog2(FE_NUM_BLOCKS);
@@ -87,7 +88,7 @@ logic dest_write_done;
 logic [BLOCK_OFFSET_W-1:0] block_offset, block_offset_nxt;
 logic block_offset_en;
 logic block_done;
-
+logic zeroize_reg;
 
 kv_doe_fsm_state_e kv_doe_fsm_ps, kv_doe_fsm_ns;
 logic arc_DOE_IDLE_DOE_INIT;
@@ -96,6 +97,22 @@ logic arc_DOE_WAIT_DOE_WRITE;
 logic arc_DOE_WRITE_DOE_BLOCK;
 logic arc_DOE_WRITE_DOE_DONE;
 
+//zeroize input is a single pulse. However, when we detect zeroize, we'd like the fsm
+//to remain in IDLE until next DOE_CMD is issued. To avoid other arcs moving the fsm
+//to other states, extending zeroize to a level so we can keep the fsm in IDLE. When the
+//next command is issued, this extended signal is reset and fsm advances.
+always_ff @(posedge clk or negedge rst_b) begin
+    if (~rst_b) begin
+        zeroize_reg <= 0;
+    end
+    else if (zeroize) begin
+        zeroize_reg <= 1;
+    end
+    else if (running_uds || running_fe) begin
+        zeroize_reg <= 0;
+    end
+end
+
 always_comb running_uds = (doe_cmd_reg.cmd == DOE_UDS);
 always_comb running_fe = (doe_cmd_reg.cmd == DOE_FE);
 always_comb block_done = running_uds ? (block_offset == (UDS_NUM_BLOCKS-1)) :
@@ -157,6 +174,7 @@ always_comb begin : kv_doe_fsm
             //increment dest offset each clock, clear when done
             dest_write_offset_en = '1;
             dest_write_offset_nxt = (dest_write_offset == 'hb) ? 'h0 : dest_write_offset + 'd1;
+
             //go back to idle if dest done, and done with blocks
             if (arc_DOE_WRITE_DOE_DONE) kv_doe_fsm_ns = DOE_DONE;
             //go back to block stage for next block if not done with blocks
@@ -215,6 +233,12 @@ always_ff @(posedge clk or negedge rst_b) begin
         block_offset <= '0;
         dest_addr <= '0;
     end
+    else if (zeroize_reg) begin
+        kv_doe_fsm_ps <= DOE_IDLE;
+        dest_write_offset <= '0;
+        block_offset <= '0;
+        dest_addr <= '0;
+    end
     else begin
         kv_doe_fsm_ps <= kv_doe_fsm_ns;
         dest_write_offset <= dest_write_offset_en ? dest_write_offset_nxt : dest_write_offset;
diff --git a/src/doe/rtl/doe_key_mem.sv b/src/doe/rtl/doe_key_mem.sv
index 5c4b6d007..7b2100e06 100644
--- a/src/doe/rtl/doe_key_mem.sv
+++ b/src/doe/rtl/doe_key_mem.sv
@@ -39,6 +39,7 @@
 module doe_key_mem(
                    input wire            clk,
                    input wire            reset_n,
+                   input wire            zeroize,
 
                    input wire [255 : 0]  key,
                    input wire            keylen,
@@ -144,6 +145,18 @@ module doe_key_mem(
           prev_key1_reg    <= 128'h0;
           key_mem_ctrl_reg <= CTRL_IDLE;
         end
+      else if (zeroize)
+        begin
+          for (ii = 0 ; ii <= DOE_256_NUM_ROUNDS ; ii = ii + 1)
+            key_mem [ii] <= 128'h0;
+
+          ready_reg        <= 1'b0;
+          rcon_reg         <= 8'h0;
+          round_ctr_reg    <= 4'h0;
+          prev_key0_reg    <= 128'h0;
+          prev_key1_reg    <= 128'h0;
+          key_mem_ctrl_reg <= CTRL_IDLE;
+        end
       else
         begin
           if (ready_we)
diff --git a/src/doe/rtl/doe_reg.rdl b/src/doe/rtl/doe_reg.rdl
index 8c2012b30..b969aaa0f 100644
--- a/src/doe/rtl/doe_reg.rdl
+++ b/src/doe/rtl/doe_reg.rdl
@@ -50,7 +50,7 @@ addrmap doe_reg {
         default sw = rw;
         default hw = r;
         default resetsignal = reset_b;
-        field {desc = "IV input field"; swmod;} IV[32] = 32'b0;
+        field {desc = "IV input field"; swmod; hwclr;} IV[32] = 32'b0;
     
     } DOE_IV[4];
 
diff --git a/src/doe/rtl/doe_reg.sv b/src/doe/rtl/doe_reg.sv
index 9d333e5f5..2f567cc7f 100644
--- a/src/doe/rtl/doe_reg.sv
+++ b/src/doe/rtl/doe_reg.sv
@@ -508,6 +508,9 @@ module doe_reg (
             if(decoded_reg_strb.DOE_IV[i0] && decoded_req_is_wr) begin // SW write
                 next_c = (field_storage.DOE_IV[i0].IV.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
                 load_next_c = '1;
+            end else if(hwif_in.DOE_IV[i0].IV.hwclr) begin // HW Clear
+                next_c = '0;
+                load_next_c = '1;
             end
             field_combo.DOE_IV[i0].IV.next = next_c;
             field_combo.DOE_IV[i0].IV.load_next = load_next_c;
diff --git a/src/doe/rtl/doe_reg_pkg.sv b/src/doe/rtl/doe_reg_pkg.sv
index 6571ce468..e8d318c07 100644
--- a/src/doe/rtl/doe_reg_pkg.sv
+++ b/src/doe/rtl/doe_reg_pkg.sv
@@ -2,6 +2,14 @@
 //  https://github.com/SystemRDL/PeakRDL-regblock
 
 package doe_reg_pkg;
+    typedef struct packed{
+        logic hwclr;
+    } doe_reg__DOE_IV__IV__in_t;
+
+    typedef struct packed{
+        doe_reg__DOE_IV__IV__in_t IV;
+    } doe_reg__DOE_IV__in_t;
+
     typedef struct packed{
         logic hwclr;
     } doe_reg__DOE_CTRL__CMD__in_t;
@@ -79,6 +87,7 @@ package doe_reg_pkg;
     typedef struct packed{
         logic reset_b;
         logic cptra_pwrgood;
+        doe_reg__DOE_IV__in_t [4-1:0]DOE_IV;
         doe_reg__DOE_CTRL__in_t DOE_CTRL;
         doe_reg__DOE_STATUS__in_t DOE_STATUS;
         doe_reg__intr_block_t__in_t intr_block_rf;
diff --git a/src/doe/rtl/doe_reg_uvm.sv b/src/doe/rtl/doe_reg_uvm.sv
index 02a5da800..c6613d480 100644
--- a/src/doe/rtl/doe_reg_uvm.sv
+++ b/src/doe/rtl/doe_reg_uvm.sv
@@ -3,40 +3,84 @@
 package doe_reg_uvm;
     `include "uvm_macros.svh"
     import uvm_pkg::*;
-    
+    `include "doe_reg_covergroups.svh"
     // Reg - doe_reg::DOE_IV
     class doe_reg__DOE_IV extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        doe_reg__DOE_IV_bit_cg IV_bit_cg[32];
+        doe_reg__DOE_IV_fld_cg fld_cg;
         rand uvm_reg_field IV;
 
         function new(string name = "doe_reg__DOE_IV");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.IV = new("IV");
-            this.IV.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+            this.IV.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(IV_bit_cg[bt]) IV_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : doe_reg__DOE_IV
 
     // Reg - doe_reg::DOE_CTRL
     class doe_reg__DOE_CTRL extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        doe_reg__DOE_CTRL_bit_cg CMD_bit_cg[2];
+        doe_reg__DOE_CTRL_bit_cg DEST_bit_cg[5];
+        doe_reg__DOE_CTRL_fld_cg fld_cg;
         rand uvm_reg_field CMD;
         rand uvm_reg_field DEST;
 
         function new(string name = "doe_reg__DOE_CTRL");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.CMD = new("CMD");
             this.CMD.configure(this, 2, 0, "RW", 1, 'h0, 1, 1, 0);
             this.DEST = new("DEST");
             this.DEST.configure(this, 5, 2, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(CMD_bit_cg[bt]) CMD_bit_cg[bt] = new();
+                foreach(DEST_bit_cg[bt]) DEST_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : doe_reg__DOE_CTRL
 
     // Reg - doe_reg::DOE_STATUS
     class doe_reg__DOE_STATUS extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        doe_reg__DOE_STATUS_bit_cg READY_bit_cg[1];
+        doe_reg__DOE_STATUS_bit_cg VALID_bit_cg[1];
+        doe_reg__DOE_STATUS_bit_cg UDS_FLOW_DONE_bit_cg[1];
+        doe_reg__DOE_STATUS_bit_cg FE_FLOW_DONE_bit_cg[1];
+        doe_reg__DOE_STATUS_bit_cg DEOBF_SECRETS_CLEARED_bit_cg[1];
+        doe_reg__DOE_STATUS_fld_cg fld_cg;
         rand uvm_reg_field READY;
         rand uvm_reg_field VALID;
         rand uvm_reg_field UDS_FLOW_DONE;
@@ -44,8 +88,13 @@ package doe_reg_uvm;
         rand uvm_reg_field DEOBF_SECRETS_CLEARED;
 
         function new(string name = "doe_reg__DOE_STATUS");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.READY = new("READY");
@@ -58,36 +107,77 @@ package doe_reg_uvm;
             this.FE_FLOW_DONE.configure(this, 1, 3, "RO", 1, 'h0, 1, 1, 0);
             this.DEOBF_SECRETS_CLEARED = new("DEOBF_SECRETS_CLEARED");
             this.DEOBF_SECRETS_CLEARED.configure(this, 1, 4, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(READY_bit_cg[bt]) READY_bit_cg[bt] = new();
+                foreach(VALID_bit_cg[bt]) VALID_bit_cg[bt] = new();
+                foreach(UDS_FLOW_DONE_bit_cg[bt]) UDS_FLOW_DONE_bit_cg[bt] = new();
+                foreach(FE_FLOW_DONE_bit_cg[bt]) FE_FLOW_DONE_bit_cg[bt] = new();
+                foreach(DEOBF_SECRETS_CLEARED_bit_cg[bt]) DEOBF_SECRETS_CLEARED_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : doe_reg__DOE_STATUS
 
     // Reg - doe_reg::global_intr_en_t
     class doe_reg__global_intr_en_t extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        doe_reg__global_intr_en_t_bit_cg error_en_bit_cg[1];
+        doe_reg__global_intr_en_t_bit_cg notif_en_bit_cg[1];
+        doe_reg__global_intr_en_t_fld_cg fld_cg;
         rand uvm_reg_field error_en;
         rand uvm_reg_field notif_en;
 
         function new(string name = "doe_reg__global_intr_en_t");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.error_en = new("error_en");
             this.error_en.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
             this.notif_en = new("notif_en");
             this.notif_en.configure(this, 1, 1, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(error_en_bit_cg[bt]) error_en_bit_cg[bt] = new();
+                foreach(notif_en_bit_cg[bt]) notif_en_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : doe_reg__global_intr_en_t
 
     // Reg - doe_reg::error_intr_en_t
     class doe_reg__error_intr_en_t extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        doe_reg__error_intr_en_t_bit_cg error0_en_bit_cg[1];
+        doe_reg__error_intr_en_t_bit_cg error1_en_bit_cg[1];
+        doe_reg__error_intr_en_t_bit_cg error2_en_bit_cg[1];
+        doe_reg__error_intr_en_t_bit_cg error3_en_bit_cg[1];
+        doe_reg__error_intr_en_t_fld_cg fld_cg;
         rand uvm_reg_field error0_en;
         rand uvm_reg_field error1_en;
         rand uvm_reg_field error2_en;
         rand uvm_reg_field error3_en;
 
         function new(string name = "doe_reg__error_intr_en_t");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.error0_en = new("error0_en");
@@ -98,61 +188,131 @@ package doe_reg_uvm;
             this.error2_en.configure(this, 1, 2, "RW", 0, 'h0, 1, 1, 0);
             this.error3_en = new("error3_en");
             this.error3_en.configure(this, 1, 3, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(error0_en_bit_cg[bt]) error0_en_bit_cg[bt] = new();
+                foreach(error1_en_bit_cg[bt]) error1_en_bit_cg[bt] = new();
+                foreach(error2_en_bit_cg[bt]) error2_en_bit_cg[bt] = new();
+                foreach(error3_en_bit_cg[bt]) error3_en_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : doe_reg__error_intr_en_t
 
     // Reg - doe_reg::notif_intr_en_t
     class doe_reg__notif_intr_en_t extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        doe_reg__notif_intr_en_t_bit_cg notif_cmd_done_en_bit_cg[1];
+        doe_reg__notif_intr_en_t_fld_cg fld_cg;
         rand uvm_reg_field notif_cmd_done_en;
 
         function new(string name = "doe_reg__notif_intr_en_t");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.notif_cmd_done_en = new("notif_cmd_done_en");
             this.notif_cmd_done_en.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(notif_cmd_done_en_bit_cg[bt]) notif_cmd_done_en_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : doe_reg__notif_intr_en_t
 
     // Reg - doe_reg::global_intr_t_agg_sts_dd3dcf0a
     class doe_reg__global_intr_t_agg_sts_dd3dcf0a extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        doe_reg__global_intr_t_agg_sts_dd3dcf0a_bit_cg agg_sts_bit_cg[1];
+        doe_reg__global_intr_t_agg_sts_dd3dcf0a_fld_cg fld_cg;
         rand uvm_reg_field agg_sts;
 
         function new(string name = "doe_reg__global_intr_t_agg_sts_dd3dcf0a");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.agg_sts = new("agg_sts");
             this.agg_sts.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(agg_sts_bit_cg[bt]) agg_sts_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : doe_reg__global_intr_t_agg_sts_dd3dcf0a
 
     // Reg - doe_reg::global_intr_t_agg_sts_e6399b4a
     class doe_reg__global_intr_t_agg_sts_e6399b4a extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        doe_reg__global_intr_t_agg_sts_e6399b4a_bit_cg agg_sts_bit_cg[1];
+        doe_reg__global_intr_t_agg_sts_e6399b4a_fld_cg fld_cg;
         rand uvm_reg_field agg_sts;
 
         function new(string name = "doe_reg__global_intr_t_agg_sts_e6399b4a");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.agg_sts = new("agg_sts");
             this.agg_sts.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(agg_sts_bit_cg[bt]) agg_sts_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : doe_reg__global_intr_t_agg_sts_e6399b4a
 
     // Reg - doe_reg::error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba
     class doe_reg__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        doe_reg__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba_bit_cg error0_sts_bit_cg[1];
+        doe_reg__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba_bit_cg error1_sts_bit_cg[1];
+        doe_reg__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba_bit_cg error2_sts_bit_cg[1];
+        doe_reg__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba_bit_cg error3_sts_bit_cg[1];
+        doe_reg__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba_fld_cg fld_cg;
         rand uvm_reg_field error0_sts;
         rand uvm_reg_field error1_sts;
         rand uvm_reg_field error2_sts;
         rand uvm_reg_field error3_sts;
 
         function new(string name = "doe_reg__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.error0_sts = new("error0_sts");
@@ -163,33 +323,71 @@ package doe_reg_uvm;
             this.error2_sts.configure(this, 1, 2, "W1C", 1, 'h0, 1, 1, 0);
             this.error3_sts = new("error3_sts");
             this.error3_sts.configure(this, 1, 3, "W1C", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(error0_sts_bit_cg[bt]) error0_sts_bit_cg[bt] = new();
+                foreach(error1_sts_bit_cg[bt]) error1_sts_bit_cg[bt] = new();
+                foreach(error2_sts_bit_cg[bt]) error2_sts_bit_cg[bt] = new();
+                foreach(error3_sts_bit_cg[bt]) error3_sts_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : doe_reg__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba
 
     // Reg - doe_reg::notif_intr_t_notif_cmd_done_sts_1c68637e
     class doe_reg__notif_intr_t_notif_cmd_done_sts_1c68637e extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        doe_reg__notif_intr_t_notif_cmd_done_sts_1c68637e_bit_cg notif_cmd_done_sts_bit_cg[1];
+        doe_reg__notif_intr_t_notif_cmd_done_sts_1c68637e_fld_cg fld_cg;
         rand uvm_reg_field notif_cmd_done_sts;
 
         function new(string name = "doe_reg__notif_intr_t_notif_cmd_done_sts_1c68637e");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.notif_cmd_done_sts = new("notif_cmd_done_sts");
             this.notif_cmd_done_sts.configure(this, 1, 0, "W1C", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(notif_cmd_done_sts_bit_cg[bt]) notif_cmd_done_sts_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : doe_reg__notif_intr_t_notif_cmd_done_sts_1c68637e
 
     // Reg - doe_reg::error_intr_trig_t
     class doe_reg__error_intr_trig_t extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        doe_reg__error_intr_trig_t_bit_cg error0_trig_bit_cg[1];
+        doe_reg__error_intr_trig_t_bit_cg error1_trig_bit_cg[1];
+        doe_reg__error_intr_trig_t_bit_cg error2_trig_bit_cg[1];
+        doe_reg__error_intr_trig_t_bit_cg error3_trig_bit_cg[1];
+        doe_reg__error_intr_trig_t_fld_cg fld_cg;
         rand uvm_reg_field error0_trig;
         rand uvm_reg_field error1_trig;
         rand uvm_reg_field error2_trig;
         rand uvm_reg_field error3_trig;
 
         function new(string name = "doe_reg__error_intr_trig_t");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.error0_trig = new("error0_trig");
@@ -200,160 +398,344 @@ package doe_reg_uvm;
             this.error2_trig.configure(this, 1, 2, "W1S", 0, 'h0, 1, 1, 0);
             this.error3_trig = new("error3_trig");
             this.error3_trig.configure(this, 1, 3, "W1S", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(error0_trig_bit_cg[bt]) error0_trig_bit_cg[bt] = new();
+                foreach(error1_trig_bit_cg[bt]) error1_trig_bit_cg[bt] = new();
+                foreach(error2_trig_bit_cg[bt]) error2_trig_bit_cg[bt] = new();
+                foreach(error3_trig_bit_cg[bt]) error3_trig_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : doe_reg__error_intr_trig_t
 
     // Reg - doe_reg::notif_intr_trig_t
     class doe_reg__notif_intr_trig_t extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        doe_reg__notif_intr_trig_t_bit_cg notif_cmd_done_trig_bit_cg[1];
+        doe_reg__notif_intr_trig_t_fld_cg fld_cg;
         rand uvm_reg_field notif_cmd_done_trig;
 
         function new(string name = "doe_reg__notif_intr_trig_t");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.notif_cmd_done_trig = new("notif_cmd_done_trig");
             this.notif_cmd_done_trig.configure(this, 1, 0, "W1S", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(notif_cmd_done_trig_bit_cg[bt]) notif_cmd_done_trig_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : doe_reg__notif_intr_trig_t
 
     // Reg - doe_reg::intr_count_t_cnt_130ab269
     class doe_reg__intr_count_t_cnt_130ab269 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        doe_reg__intr_count_t_cnt_130ab269_bit_cg cnt_bit_cg[32];
+        doe_reg__intr_count_t_cnt_130ab269_fld_cg fld_cg;
         rand uvm_reg_field cnt;
 
         function new(string name = "doe_reg__intr_count_t_cnt_130ab269");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.cnt = new("cnt");
             this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : doe_reg__intr_count_t_cnt_130ab269
 
     // Reg - doe_reg::intr_count_t_cnt_324dfc53
     class doe_reg__intr_count_t_cnt_324dfc53 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        doe_reg__intr_count_t_cnt_324dfc53_bit_cg cnt_bit_cg[32];
+        doe_reg__intr_count_t_cnt_324dfc53_fld_cg fld_cg;
         rand uvm_reg_field cnt;
 
         function new(string name = "doe_reg__intr_count_t_cnt_324dfc53");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.cnt = new("cnt");
             this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : doe_reg__intr_count_t_cnt_324dfc53
 
     // Reg - doe_reg::intr_count_t_cnt_791a4799
     class doe_reg__intr_count_t_cnt_791a4799 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        doe_reg__intr_count_t_cnt_791a4799_bit_cg cnt_bit_cg[32];
+        doe_reg__intr_count_t_cnt_791a4799_fld_cg fld_cg;
         rand uvm_reg_field cnt;
 
         function new(string name = "doe_reg__intr_count_t_cnt_791a4799");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.cnt = new("cnt");
             this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : doe_reg__intr_count_t_cnt_791a4799
 
     // Reg - doe_reg::intr_count_t_cnt_e9de7334
     class doe_reg__intr_count_t_cnt_e9de7334 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        doe_reg__intr_count_t_cnt_e9de7334_bit_cg cnt_bit_cg[32];
+        doe_reg__intr_count_t_cnt_e9de7334_fld_cg fld_cg;
         rand uvm_reg_field cnt;
 
         function new(string name = "doe_reg__intr_count_t_cnt_e9de7334");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.cnt = new("cnt");
             this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : doe_reg__intr_count_t_cnt_e9de7334
 
     // Reg - doe_reg::intr_count_t_cnt_be67d6d5
     class doe_reg__intr_count_t_cnt_be67d6d5 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        doe_reg__intr_count_t_cnt_be67d6d5_bit_cg cnt_bit_cg[32];
+        doe_reg__intr_count_t_cnt_be67d6d5_fld_cg fld_cg;
         rand uvm_reg_field cnt;
 
         function new(string name = "doe_reg__intr_count_t_cnt_be67d6d5");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.cnt = new("cnt");
             this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : doe_reg__intr_count_t_cnt_be67d6d5
 
     // Reg - doe_reg::intr_count_incr_t_pulse_37026c97
     class doe_reg__intr_count_incr_t_pulse_37026c97 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        doe_reg__intr_count_incr_t_pulse_37026c97_bit_cg pulse_bit_cg[1];
+        doe_reg__intr_count_incr_t_pulse_37026c97_fld_cg fld_cg;
         rand uvm_reg_field pulse;
 
         function new(string name = "doe_reg__intr_count_incr_t_pulse_37026c97");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.pulse = new("pulse");
             this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : doe_reg__intr_count_incr_t_pulse_37026c97
 
     // Reg - doe_reg::intr_count_incr_t_pulse_d860d977
     class doe_reg__intr_count_incr_t_pulse_d860d977 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        doe_reg__intr_count_incr_t_pulse_d860d977_bit_cg pulse_bit_cg[1];
+        doe_reg__intr_count_incr_t_pulse_d860d977_fld_cg fld_cg;
         rand uvm_reg_field pulse;
 
         function new(string name = "doe_reg__intr_count_incr_t_pulse_d860d977");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.pulse = new("pulse");
             this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : doe_reg__intr_count_incr_t_pulse_d860d977
 
     // Reg - doe_reg::intr_count_incr_t_pulse_87b45fe7
     class doe_reg__intr_count_incr_t_pulse_87b45fe7 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        doe_reg__intr_count_incr_t_pulse_87b45fe7_bit_cg pulse_bit_cg[1];
+        doe_reg__intr_count_incr_t_pulse_87b45fe7_fld_cg fld_cg;
         rand uvm_reg_field pulse;
 
         function new(string name = "doe_reg__intr_count_incr_t_pulse_87b45fe7");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.pulse = new("pulse");
             this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : doe_reg__intr_count_incr_t_pulse_87b45fe7
 
     // Reg - doe_reg::intr_count_incr_t_pulse_c1689ee6
     class doe_reg__intr_count_incr_t_pulse_c1689ee6 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        doe_reg__intr_count_incr_t_pulse_c1689ee6_bit_cg pulse_bit_cg[1];
+        doe_reg__intr_count_incr_t_pulse_c1689ee6_fld_cg fld_cg;
         rand uvm_reg_field pulse;
 
         function new(string name = "doe_reg__intr_count_incr_t_pulse_c1689ee6");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.pulse = new("pulse");
             this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : doe_reg__intr_count_incr_t_pulse_c1689ee6
 
     // Reg - doe_reg::intr_count_incr_t_pulse_6173128e
     class doe_reg__intr_count_incr_t_pulse_6173128e extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        doe_reg__intr_count_incr_t_pulse_6173128e_bit_cg pulse_bit_cg[1];
+        doe_reg__intr_count_incr_t_pulse_6173128e_fld_cg fld_cg;
         rand uvm_reg_field pulse;
 
         function new(string name = "doe_reg__intr_count_incr_t_pulse_6173128e");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.pulse = new("pulse");
             this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : doe_reg__intr_count_incr_t_pulse_6173128e
 
@@ -520,4 +902,5 @@ package doe_reg_uvm;
         endfunction : build
     endclass : doe_reg
 
+    `include "doe_reg_sample.svh"
 endpackage: doe_reg_uvm
diff --git a/src/doe/stimulus/tests/directed/doe_cbc_nist_test.yml b/src/doe/stimulus/tests/directed/doe_cbc_nist_test.yml
new file mode 100644
index 000000000..8005b2f5c
--- /dev/null
+++ b/src/doe/stimulus/tests/directed/doe_cbc_nist_test.yml
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+---
+testname: doe_cbc_nist_test
+seed: 1
\ No newline at end of file
diff --git a/src/doe/stimulus/testsuites/doe_nightly_directed_regression.yml b/src/doe/stimulus/testsuites/doe_nightly_directed_regression.yml
new file mode 100644
index 000000000..1af388109
--- /dev/null
+++ b/src/doe/stimulus/testsuites/doe_nightly_directed_regression.yml
@@ -0,0 +1,8 @@
+document:
+  schema: 1.0
+
+contents:
+  - tests:
+      tags: ["L0", "directed", "nightly", "DOE"]
+      paths:
+        - ${CALIPTRA_ROOT}/src/doe/stimulus/tests/directed/doe_cbc_nist_test.yml
diff --git a/src/doe/tb/doe_core_cbc_tb.sv b/src/doe/tb/doe_core_cbc_tb.sv
new file mode 100644
index 000000000..bd5bcfa55
--- /dev/null
+++ b/src/doe/tb/doe_core_cbc_tb.sv
@@ -0,0 +1,671 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//======================================================================
+//
+// doe_core_cbc_tb.sv
+// --------
+// DOE testbench for the DOE core CBC.
+//
+//
+//======================================================================
+
+module doe_core_cbc_tb();
+
+//----------------------------------------------------------------
+  // Internal constant and parameter definitions.
+  //----------------------------------------------------------------
+  parameter DEBUG     = 0;
+
+  parameter CLK_HALF_PERIOD = 1;
+  parameter CLK_PERIOD      = 2 * CLK_HALF_PERIOD;
+
+
+  parameter DOE_128_BIT_KEY = 0;
+  parameter DOE_256_BIT_KEY = 1;
+
+  parameter DOE_DECIPHER = 1'b0;
+  parameter DOE_ENCIPHER = 1'b1;
+
+  //----------------------------------------------------------------
+  // Register and Wire declarations.
+  //----------------------------------------------------------------
+  reg [63 : 0]  cycle_ctr;
+  reg [63 : 0]  error_ctr;
+  reg [63 : 0]  tc_ctr;
+  reg [63 : 0]  temp_ctr;
+
+  reg           clk_tb;
+  reg           reset_n_tb;
+  reg           zeroize_tb;
+  
+  logic         core_encdec_tb;
+  logic         core_init_tb;
+  logic         core_next_tb;
+  logic         core_ready_tb;
+  logic [255:0] core_key_tb;
+  logic         core_keylen_tb;
+  logic [127:0] core_IV_tb;
+  logic         IV_updated_tb;
+  logic [127:0] core_block_tb;
+  logic [127:0] core_result_tb;
+  logic         core_valid_tb;
+
+
+  //----------------------------------------------------------------
+  // Device Under Test.
+  //----------------------------------------------------------------
+  doe_core_cbc dut (
+              .clk(clk_tb),
+              .reset_n(reset_n_tb),
+              .zeroize(zeroize_tb),
+
+              .encdec(core_encdec_tb),
+              .init_cmd(core_init_tb),
+              .next_cmd(core_next_tb),
+              .ready(core_ready_tb),
+
+              .key(core_key_tb),
+              .keylen(core_keylen_tb),
+
+              .IV(core_IV_tb),
+              .IV_updated(IV_updated_tb),
+
+              .block_msg(core_block_tb),
+              .result(core_result_tb),
+              .result_valid(core_valid_tb)
+            );
+
+
+  //----------------------------------------------------------------
+  // clk_gen
+  //
+  // Always running clock generator process.
+  //----------------------------------------------------------------
+  always
+    begin : clk_gen
+      #CLK_HALF_PERIOD;
+      clk_tb = !clk_tb;
+    end // clk_gen
+
+
+  //----------------------------------------------------------------
+  // sys_monitor()
+  //
+  // An always running process that creates a cycle counter and
+  // conditionally displays information about the DUT.
+  //----------------------------------------------------------------
+  always
+    begin : sys_monitor
+      #(CLK_PERIOD);
+      cycle_ctr = cycle_ctr + 1;
+    end
+
+
+  //----------------------------------------------------------------
+  // reset_dut()
+  //
+  // Toggle reset to put the DUT into a well known state.
+  //----------------------------------------------------------------
+  task reset_dut;
+    begin
+      $display("*** Toggle reset.");
+      reset_n_tb = 0;
+
+      #(2 * CLK_PERIOD);
+      reset_n_tb = 1;
+      $display("");
+    end
+  endtask // reset_dut
+
+
+  //----------------------------------------------------------------
+  // display_test_results()
+  //
+  // Display the accumulated test results.
+  //----------------------------------------------------------------
+  task display_test_results;
+    begin
+      if (error_ctr == 0)
+        begin
+          $display("*** All %02d test cases completed successfully", tc_ctr);
+          $display("* TESTCASE PASSED");
+        end
+      else
+        begin
+          $display("*** %02d tests completed - %02d test cases did not complete successfully.",
+                   tc_ctr, error_ctr);
+          $display("* TESTCASE FAILED");
+        end
+    end
+  endtask // display_test_results
+
+  //----------------------------------------------------------------
+  // init_sim()
+  //
+  // Initialize all counters and testbed functionality as well
+  // as setting the DUT inputs to defined values.
+  //----------------------------------------------------------------
+  task init_sim;
+    begin
+      cycle_ctr     = 0;
+      error_ctr     = 0;
+      tc_ctr        = 0;
+      temp_ctr      = 0;
+
+      clk_tb        = 0;
+      reset_n_tb    = 0;
+      zeroize_tb    = 0;
+
+      core_encdec_tb  = 0;
+      core_init_tb    = 0;
+      core_next_tb    = 0;
+      core_key_tb     = 0;
+      core_keylen_tb  = 0;
+      core_IV_tb      = 0;
+      IV_updated_tb   = 0;
+      core_block_tb   = 0;
+    end
+  endtask // init_sim
+
+
+  //----------------------------------------------------------------
+  // wait_ready()
+  //
+  // Wait for the ready flag in the dut to be set.
+  // (Actually we wait for either ready or valid to be set.)
+  //
+  // Note: It is the callers responsibility to call the function
+  // when the dut is actively processing and will in fact at some
+  // point set the flag.
+  //----------------------------------------------------------------
+  task wait_ready;
+    begin
+      #(CLK_PERIOD);
+      while (core_ready_tb == 0)
+        begin
+          #(CLK_PERIOD);
+        end
+    end
+  endtask // wait_ready
+
+
+
+  //----------------------------------------------------------------
+  // init_key()
+  //
+  // init the key in the dut by writing the given key and
+  // key length and then trigger init processing.
+  //----------------------------------------------------------------
+  task init_key(input [255 : 0] key, input key_length);
+    begin
+      core_key_tb = key;
+      core_keylen_tb = key_length;
+      core_init_tb = 1'b1;
+      
+      #CLK_PERIOD;
+      core_init_tb       = 0;
+
+      wait_ready();
+      
+    end
+  endtask // init_key
+
+
+  //----------------------------------------------------------------
+  // cbc_mode_single_block_test()
+  //
+  // Perform CBC mode encryption or decryption single block test.
+  //----------------------------------------------------------------
+  task cbc_mode_single_block_test(input [7 : 0]   tc_number,
+                                  input           encdec,
+                                  input [255 : 0] key,
+                                  input           key_length,
+                                  input [127 : 0] IV,
+                                  input [127 : 0] block,
+                                  input [127 : 0] expected);
+    reg [31  : 0] start_time;
+    reg [31 : 0] end_time;
+    
+    begin
+      $display("*** TC %0d CBC mode test started.", tc_number);
+      if (encdec==0)
+        $display("*** DECRYPTION *** ");
+      else
+        $display("*** ENCRYPTION *** ");
+      tc_ctr = tc_ctr + 1;
+
+      start_time = cycle_ctr;
+      init_key(key, key_length);
+      
+      core_IV_tb = IV;
+      IV_updated_tb = 1'b1;      
+      
+      #(CLK_PERIOD);
+      IV_updated_tb = 0;
+      core_block_tb = block;
+      core_encdec_tb = encdec;
+      core_next_tb       = 1'b1;
+
+      #(CLK_PERIOD);
+      core_next_tb       = 0;
+      wait_ready();
+      end_time = cycle_ctr - start_time;
+      $display("*** Single block test processing time = %01d cycles", end_time);
+
+      if (core_result_tb == expected)
+        begin
+          $display("*** TC %0d successful.", tc_number);
+          $display("");
+        end
+      else
+        begin
+          $display("*** ERROR: TC %0d NOT successful.", tc_number);
+          $display("Expected: 0x%032x", expected);
+          $display("Got:      0x%032x", core_result_tb);
+          $display("");
+
+          error_ctr = error_ctr + 1;
+        end
+    end
+  endtask // cbc_mode_single_block_test
+
+
+  //----------------------------------------------------------------
+  // cbc_mode_double_block_test()
+  //
+  // Perform CBC mode encryption or decryption double block test.
+  //----------------------------------------------------------------
+  task cbc_mode_double_block_test(input [7 : 0]   tc_number,
+                                  input           encdec,
+                                  input [255 : 0] key,
+                                  input           key_length,
+                                  input [127 : 0] IV,
+                                  input [127 : 0] block1,
+                                  input [127 : 0] block2,
+                                  input [127 : 0] expected1,
+                                  input [127 : 0] expected2
+                                  );
+    reg [31  : 0] start_time;
+    reg [31 : 0] end_time;
+    
+    begin
+      $display("*** TC %0d CBC mode DOUBLE BLOCK test started.", tc_number);
+      tc_ctr = tc_ctr + 1;
+
+      if (encdec==0)
+        $display("*** DECRYPTION *** ");
+      else
+        $display("*** ENCRYPTION *** ");
+
+      start_time = cycle_ctr;
+      init_key(key, key_length);
+      
+      core_IV_tb = IV;
+      IV_updated_tb = 1'b1;
+      
+      #CLK_PERIOD;
+      IV_updated_tb = 0;
+      // first block
+      core_block_tb = block1;
+      core_encdec_tb = encdec;
+      core_next_tb       = 1'b1;
+      
+      #(CLK_PERIOD);
+      core_next_tb       = 0;
+      wait_ready();
+
+      if (core_result_tb == expected1)
+        begin
+          $display("*** TC %0d first block successful.", tc_number);
+          $display("");
+        end
+      else
+        begin
+          $display("*** ERROR: TC %0d first block NOT successful.", tc_number);
+          $display("Expected: 0x%032x", expected1);
+          $display("Got:      0x%032x", core_result_tb);
+          $display("");
+
+          error_ctr = error_ctr + 1;
+        end
+
+      // second block
+      core_block_tb = block2;
+      core_next_tb       = 1'b1;
+      
+      #(CLK_PERIOD);
+      core_next_tb       = 0;
+      wait_ready();
+      
+      if (core_result_tb == expected2)
+        begin
+          $display("*** TC %0d second block successful.", tc_number);
+          $display("");
+        end
+      else
+        begin
+          $display("*** ERROR: TC %0d second block NOT successful.", tc_number);
+          $display("Expected: 0x%032x", expected2);
+          $display("Got:      0x%032x", core_result_tb);
+          $display("");
+
+          error_ctr = error_ctr + 1;
+        end
+    end
+  endtask // cbc_mode_dual_block_test
+
+
+
+
+  //----------------------------------------------------------------
+  // cbc_mode_quadratic_block_test()
+  //
+  // Perform CBC mode encryption or decryption quadratic block test.
+  //----------------------------------------------------------------
+  task cbc_mode_quadratic_block_test(input [7 : 0]   tc_number,
+                                  input           encdec,
+                                  input [255 : 0] key,
+                                  input           key_length,
+                                  input [127 : 0] IV,
+                                  input [127 : 0] block1,
+                                  input [127 : 0] block2,
+                                  input [127 : 0] block3,
+                                  input [127 : 0] block4,
+                                  input [127 : 0] expected1,
+                                  input [127 : 0] expected2,
+                                  input [127 : 0] expected3,
+                                  input [127 : 0] expected4
+                                  );
+    reg [31  : 0] start_time;
+    reg [31 : 0] end_time;
+    
+    begin
+      $display("*** TC %0d CBC mode FOUR BLOCK test started.", tc_number);
+      tc_ctr = tc_ctr + 1;
+
+
+      if (encdec==0)
+        $display("*** DECRYPTION *** ");
+      else
+        $display("*** ENCRYPTION *** ");
+
+      start_time = cycle_ctr;
+      init_key(key, key_length);
+      
+      core_IV_tb = IV;
+      IV_updated_tb = 1'b1;
+      
+      #CLK_PERIOD;
+      IV_updated_tb = 0;
+      // first block
+      core_block_tb = block1;
+      core_encdec_tb = encdec;
+      core_next_tb       = 1'b1;
+      
+      #(CLK_PERIOD);
+      core_next_tb       = 0;
+      wait_ready();
+
+      if (core_result_tb == expected1)
+        begin
+          $display("*** TC %0d first block successful.", tc_number);
+          $display("");
+        end
+      else
+        begin
+          $display("*** ERROR: TC %0d first block NOT successful.", tc_number);
+          $display("Expected: 0x%032x", expected1);
+          $display("Got:      0x%032x", core_result_tb);
+          $display("");
+
+          error_ctr = error_ctr + 1;
+        end
+
+      // second block
+      core_block_tb = block2;
+      core_next_tb       = 1'b1;
+      
+      #(CLK_PERIOD);
+      core_next_tb       = 0;
+      wait_ready();
+      
+      if (core_result_tb == expected2)
+        begin
+          $display("*** TC %0d second block successful.", tc_number);
+          $display("");
+        end
+      else
+        begin
+          $display("*** ERROR: TC %0d second block NOT successful.", tc_number);
+          $display("Expected: 0x%032x", expected2);
+          $display("Got:      0x%032x", core_result_tb);
+          $display("");
+
+          error_ctr = error_ctr + 1;
+        end
+
+      // third block
+      core_block_tb = block3;
+      core_next_tb       = 1'b1;
+      
+      #(CLK_PERIOD);
+      core_next_tb       = 0;
+      wait_ready();
+      
+      if (core_result_tb == expected3)
+        begin
+          $display("*** TC %0d third block successful.", tc_number);
+          $display("");
+        end
+      else
+        begin
+          $display("*** ERROR: TC %0d third block NOT successful.", tc_number);
+          $display("Expected: 0x%032x", expected3);
+          $display("Got:      0x%032x", core_result_tb);
+          $display("");
+
+          error_ctr = error_ctr + 1;
+        end
+
+      // final block
+      core_block_tb = block4;
+      core_next_tb       = 1'b1;
+      
+      #(CLK_PERIOD);
+      core_next_tb       = 0;
+      wait_ready();
+      
+      if (core_result_tb == expected4)
+        begin
+          $display("*** TC %0d fourth block successful.", tc_number);
+          $display("");
+        end
+      else
+        begin
+          $display("*** ERROR: TC %0d fourth block NOT successful.", tc_number);
+          $display("Expected: 0x%032x", expected4);
+          $display("Got:      0x%032x", core_result_tb);
+          $display("");
+
+          error_ctr = error_ctr + 1;
+        end
+      
+      end_time = cycle_ctr - start_time;
+
+    end
+  endtask // cbc_mode_quat_block_test
+
+  
+  //----------------------------------------------------------------
+  // doe_cbc_test()
+  //
+  //
+  // Main test task will perform complete test of DOE.
+  // Test vectors copied from the follwing documents.
+  //
+  // https://datatracker.ietf.org/doc/html/rfc3602
+  // 
+  //
+  //----------------------------------------------------------------
+  task doe_cbc_test;
+    reg [255 : 0] nist_doe_key    ;
+    
+
+    reg [127 : 0] nist_IV0;
+
+    reg [127 : 0] nist_plaintext0;
+
+    reg [127 : 0] nist_plaintext1;
+
+    reg [127 : 0] nist_plaintext2;
+
+    reg [127 : 0] nist_plaintext3;
+
+    reg [127 : 0] nist_cbc_128_enc_expected0;
+
+    reg [127 : 0] nist_cbc_128_enc_expected1;
+
+    reg [127 : 0] nist_cbc_128_enc_expected2;
+
+    reg [127 : 0] nist_cbc_128_enc_expected3;
+
+    reg [127 : 0] nist_cbc_256_enc_expected0;
+
+    reg [127 : 0] nist_cbc_256_enc_expected1;
+
+    reg [127 : 0] nist_cbc_256_enc_expected2;
+
+    reg [127 : 0] nist_cbc_256_enc_expected3;
+
+    begin
+      nist_doe_key               = 256'hc286696d887c9aa0611bbb3e2025a45a00000000000000000000000000000000;
+      nist_IV0                   = 128'h562e17996d093d28ddb3ba695a2e6f58;
+      nist_plaintext0            = 128'h000102030405060708090a0b0c0d0e0f;
+      nist_cbc_128_enc_expected0 = 128'hd296cd94c2cccf8a3a863028b5e1dc0a;
+
+      $display("CBC 128 bit key single block tests");
+      $display("---------------------");
+      cbc_mode_single_block_test(8'h01, DOE_ENCIPHER, nist_doe_key    , DOE_128_BIT_KEY, nist_IV0,
+                                 nist_plaintext0, nist_cbc_128_enc_expected0);
+      $display("---------------------");
+      cbc_mode_single_block_test(8'h01, DOE_DECIPHER, nist_doe_key    , DOE_128_BIT_KEY, nist_IV0,
+                                 nist_cbc_128_enc_expected0, nist_plaintext0);
+
+      $display("---------------------");
+      
+      nist_doe_key               = 256'h56e47a38c5598974bc46903dba29034900000000000000000000000000000000;
+      nist_IV0                   = 128'h8ce82eefbea0da3c44699ed7db51b7d9;
+      nist_plaintext0            = 128'ha0a1a2a3a4a5a6a7a8a9aaabacadaeaf;
+      nist_cbc_128_enc_expected0 = 128'hc30e32ffedc0774e6aff6af0869f71aa;
+
+      cbc_mode_single_block_test(8'h02, DOE_ENCIPHER, nist_doe_key    , DOE_128_BIT_KEY, nist_IV0,
+                                 nist_plaintext0, nist_cbc_128_enc_expected0);
+      $display("---------------------");
+      cbc_mode_single_block_test(8'h03, DOE_DECIPHER, nist_doe_key    , DOE_128_BIT_KEY, nist_IV0,
+                                 nist_cbc_128_enc_expected0, nist_plaintext0);
+      $display("---------------------");
+      
+      nist_doe_key               = 256'hc286696d887c9aa0611bbb3e2025a45a00000000000000000000000000000000;
+      nist_IV0                   = 128'h562e17996d093d28ddb3ba695a2e6f58;
+      nist_plaintext0            = 128'h000102030405060708090a0b0c0d0e0f;
+      nist_plaintext1            = 128'h101112131415161718191a1b1c1d1e1f;
+      nist_cbc_128_enc_expected0 = 128'hd296cd94c2cccf8a3a863028b5e1dc0a;
+      nist_cbc_128_enc_expected1 = 128'h7586602d253cfff91b8266bea6d61ab1;
+      $display("---------------------");
+      cbc_mode_double_block_test(8'h04, DOE_ENCIPHER, nist_doe_key    , DOE_128_BIT_KEY, nist_IV0,
+                                 nist_plaintext0,
+                                 nist_plaintext1,
+                                 nist_cbc_128_enc_expected0,
+                                 nist_cbc_128_enc_expected1);
+
+      $display("---------------------");
+      cbc_mode_double_block_test(8'h05, DOE_DECIPHER, nist_doe_key    , DOE_128_BIT_KEY, nist_IV0,
+                                 nist_cbc_128_enc_expected0,
+                                 nist_cbc_128_enc_expected1,
+                                 nist_plaintext0,
+                                 nist_plaintext1);
+      $display("---------------------");      
+      nist_doe_key               = 256'h56e47a38c5598974bc46903dba29034900000000000000000000000000000000;
+      nist_IV0                   = 128'h8ce82eefbea0da3c44699ed7db51b7d9;
+      nist_plaintext0            = 128'ha0a1a2a3a4a5a6a7a8a9aaabacadaeaf;
+      nist_plaintext1            = 128'hb0b1b2b3b4b5b6b7b8b9babbbcbdbebf;
+      nist_plaintext2            = 128'hc0c1c2c3c4c5c6c7c8c9cacbcccdcecf;
+      nist_plaintext3            = 128'hd0d1d2d3d4d5d6d7d8d9dadbdcdddedf;
+      nist_cbc_128_enc_expected0 = 128'hc30e32ffedc0774e6aff6af0869f71aa;
+      nist_cbc_128_enc_expected1 = 128'h0f3af07a9a31a9c684db207eb0ef8e4e;
+      nist_cbc_128_enc_expected2 = 128'h35907aa632c3ffdf868bb7b29d3d46ad;
+      nist_cbc_128_enc_expected3 = 128'h83ce9f9a102ee99d49a53e87f4c3da55;
+
+      cbc_mode_quadratic_block_test(8'h06, DOE_ENCIPHER, nist_doe_key    , DOE_128_BIT_KEY, nist_IV0,
+                                 nist_plaintext0,
+                                 nist_plaintext1,
+                                 nist_plaintext2,
+                                 nist_plaintext3,
+                                 nist_cbc_128_enc_expected0,
+                                 nist_cbc_128_enc_expected1,
+                                 nist_cbc_128_enc_expected2,
+                                 nist_cbc_128_enc_expected3);
+      $display("---------------------");
+      cbc_mode_quadratic_block_test(8'h07, DOE_DECIPHER, nist_doe_key    , DOE_128_BIT_KEY, nist_IV0,
+                                 nist_cbc_128_enc_expected0,
+                                 nist_cbc_128_enc_expected1,
+                                 nist_cbc_128_enc_expected2,
+                                 nist_cbc_128_enc_expected3,
+                                 nist_plaintext0,
+                                 nist_plaintext1,
+                                 nist_plaintext2,
+                                 nist_plaintext3);
+
+      $display("---------------------");
+
+      nist_doe_key               = 256'h603deb1015ca71be2b73aef0857d77811f352c073b6108d72d9810a30914dff4;
+      nist_IV0                   = 128'h000102030405060708090A0B0C0D0E0F;
+      nist_plaintext0            = 128'h6bc1bee22e409f96e93d7e117393172a;
+      nist_cbc_128_enc_expected0 = 128'hf58c4c04d6e5f1ba779eabfb5f7bfbd6;
+
+      $display("CBC 256 bit key single block tests");
+      
+      cbc_mode_single_block_test(8'h08, DOE_ENCIPHER, nist_doe_key, DOE_256_BIT_KEY, nist_IV0,
+                                 nist_plaintext0, nist_cbc_128_enc_expected0);
+
+      $display("---------------------");
+
+    end
+  endtask // doe_cbc_test
+
+  //----------------------------------------------------------------
+  // main
+  //
+  // The main test functionality.
+  //----------------------------------------------------------------
+  initial
+    begin : main
+      $display("   -= Testbench for DOE CBC started =-");
+      $display("    ==============================");
+      $display("");
+
+      init_sim();
+      reset_dut();
+
+      doe_cbc_test();
+
+      display_test_results();
+      
+      $display("");
+      $display("*** DOE simulation done. ***");
+      $finish;
+    end // main
+
+endmodule // doe_tb
diff --git a/src/doe/tb/doe_test_gen.py b/src/doe/tb/doe_test_gen.py
new file mode 100644
index 000000000..9040b73fa
--- /dev/null
+++ b/src/doe/tb/doe_test_gen.py
@@ -0,0 +1,139 @@
+#usr/local/bin/python3
+#********************************************************************************
+# SPDX-License-Identifier: Apache-2.0
+# Copyright 2020 Western Digital Corporation or its affiliates.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#********************************************************************************
+#
+# This script generates:
+# UDS, key, IV, ciphertext
+# FE, key, IV, ciphertext
+#********************************************************************************
+import os
+import subprocess
+import re
+import random
+import secrets
+from pathlib import Path
+
+def encrypt(plaintext_filename, key_str, iv_str):
+    #Encrypt UDS (to be used to drive DOE)
+    command = 'cat '+ plaintext_filename +' | xxd -r -ps | openssl enc -aes-256-cbc -e -out temp -K ' + key_str + ' -iv ' + iv_str + ' -nopad'
+    subprocess.run(command, shell=True)
+    command = 'xxd -p -c 1000 temp'
+    encrypted = subprocess.check_output(command, shell=True)
+    cipher_str = str(encrypted)[2:-3] #Chomp extra chars and convert to string
+    return cipher_str
+
+def decrypt_and_compare(ciphertext_filename, key_str, iv_str, plain_str, flow):
+    #Decrypt previous (this step is only to make sure openssl command is working)
+    command = 'cat ' + ciphertext_filename + ' | xxd -r -ps | openssl enc -aes-256-cbc -d -out temp -K ' + key_str + ' -iv ' + iv_str + ' -nopad'
+    subprocess.run(command, shell=True)
+    command = 'xxd -p -c 1000 temp'
+    decrypted = subprocess.check_output(command, shell=True)
+    decrypted_str = str(decrypted)[2:-3]
+
+    #Compare decrypted and plaintext to make sure they're matching
+    if decrypted_str != plain_str:
+        print(decrypted_str+'\n'+plain_str)
+        print("Plaintext mismatch when decrypting " + flow + "! Check openssl command\n")
+
+def generate_rand_bytes(num_bytes): #(key_bytes, iv_bytes, plaintext_bytes):
+    #Generate 256-bit OBF KEY - UDS
+    #key_str = str(secrets.token_hex(key_bytes)) #OBF KEY - 256 bit
+
+    #Generate 128-bit IV
+    #iv_str = str(secrets.token_hex(iv_bytes)) #IV - 128 bit
+
+    #Generate 384-bit UDS (plaintext)
+    #plain_str = str(secrets.token_hex(plaintext_bytes)) #UDS - 384 bit (12 dwords)
+    #return key_str, iv_str, plain_str
+    rand_str = str(secrets.token_hex(num_bytes))
+    return rand_str
+
+
+def generate_doe_testvector():
+    f = open("doe_test_vector.txt", "w")
+    g = open("doe_test_vectors_all.txt", "a")
+    
+    #-------------------------------------
+    #UDS
+    #-------------------------------------
+    p = open("uds", "w")
+    c = open("ciphertext", "w")
+
+    #key_str, iv_str, plain_str = generate_rand_bytes(32, 16, 48)
+    key_str     = generate_rand_bytes(32)
+    iv_str      = generate_rand_bytes(16)
+    plain_str   = generate_rand_bytes(48)
+    # key_str = "002ec695b21f27581a745c72e5b9f484865bc95eb10a13d584f57062166838d6"
+    # iv_str = "a07b6cf2c26e78194b698f30ed0f5bdb"
+    # plain_str = "754e68e5bdb5df41fca420e77655c76fe8ac8e4bc55727b2132bfdf9419a3b21b0dcc413c6f3f64a9b2d6cc1d861065b"
+    p.write(plain_str)
+    p.close()
+
+    #Encrypt plaintext
+    cipher_str = encrypt("uds", key_str, iv_str)
+    c.write(cipher_str)
+    c.close()
+
+    #Decrypt ciphertext and make sure it matches with generated plaintext
+    decrypt_and_compare("ciphertext", key_str, iv_str, plain_str, "UDS")
+    
+
+    #Write all values to a file to be used in test
+    f.write(key_str+'\n'+iv_str+'\n'+plain_str+'\n'+cipher_str+'\n')
+    g.write("OBF UDS key: "+key_str+'\n'+ "IV: "+iv_str+'\n'+ "UDS plaintext: "+plain_str+'\n'+ "UDS ciphertext: "+cipher_str+'\n')
+
+    #-------------------------------------
+    #FE
+    #-------------------------------------
+    p = open("fe", "w")
+    c = open("ciphertext", "w")
+    
+    plain_str = "" #Clear out plain str
+    #iv_str, plain_str = generate_rand_bytes(16, 32) #Use same key as UDS
+    iv_str      = generate_rand_bytes(16)
+    plain_str   = generate_rand_bytes(32)
+    p.write(plain_str)
+    p.close()
+
+    #Encrypt plaintext
+    cipher_str = encrypt("fe", key_str, iv_str)
+    c.write(cipher_str)
+    c.close()
+
+    #Decrypt ciphertext and make sure it matches with generated plaintext
+    decrypt_and_compare("ciphertext", key_str, iv_str, plain_str, "FE")
+    
+
+    #Write all values to a file to be used in test
+    f.write(key_str+'\n'+iv_str+'\n'+plain_str+'\n'+cipher_str+'\n')
+    g.write("OBF FE key: "+key_str+'\n'+"IV: "+iv_str+'\n'+"FE plaintext: "+plain_str+'\n'+"FE ciphertext: "+cipher_str+'\n')
+
+    g.write('---------------------------------\n')
+    f.close()
+    g.close()
+
+    #Temp file clean up
+    os.remove("uds")
+    os.remove("fe")
+    os.remove("ciphertext")
+    os.remove("temp")
+
+def main():
+    generate_doe_testvector()
+
+main()
+    
\ No newline at end of file
diff --git a/src/ecc/config/compile.yml b/src/ecc/config/compile.yml
index d8fd3ced7..369d1ed2c 100755
--- a/src/ecc/config/compile.yml
+++ b/src/ecc/config/compile.yml
@@ -50,14 +50,40 @@ requires:
   - ecc_top
   - keyvault
   - caliptra_top_defines
+  - ecc_coverage
 targets:
   tb:
     directories: 
       - $COMPILE_ROOT/tb
     files:
       - $COMPILE_ROOT/tb/ecc_top_tb.sv
-
     tops: [ecc_top_tb]
+---
+provides: [ecc_montgomerymultiplier_tb]  
+schema_version: 2.4.0
+requires: 
+  - ecc_top
+targets:
+  tb:
+    directories: 
+      - $COMPILE_ROOT/tb
+    files:
+      - $COMPILE_ROOT/tb/ecc_montgomerymultiplier_tb.sv
+    tops: [ecc_montgomerymultiplier_tb]
+  sim:
+    pre_exec: 'echo "[PRE-EXEC] Copying Mont multiplication test vector to $PWD" && cp $COMPILE_ROOT/tb/test_vectors/mm_test_vectors*.hex .'
+---
+provides: [ecc_coverage]  
+schema_version: 2.4.0
+requires: 
+  - ecc_top
+targets:
+  tb:
+    directories: 
+      - $COMPILE_ROOT/coverage
+    files:
+      - $COMPILE_ROOT/coverage/ecc_top_cov_if.sv
+      - $COMPILE_ROOT/coverage/ecc_top_cov_bind.sv
 global:
   tool:
     vcs:
diff --git a/src/ecc/config/ecc_montgomerymultiplier_tb.vf b/src/ecc/config/ecc_montgomerymultiplier_tb.vf
new file mode 100644
index 000000000..0754d8f22
--- /dev/null
+++ b/src/ecc/config/ecc_montgomerymultiplier_tb.vf
@@ -0,0 +1,81 @@
++incdir+${CALIPTRA_ROOT}/src/integration/rtl
++incdir+${CALIPTRA_ROOT}/src/libs/rtl
++incdir+${CALIPTRA_ROOT}/src/keyvault/rtl
++incdir+${CALIPTRA_ROOT}/src/pcrvault/rtl
++incdir+${CALIPTRA_ROOT}/src/ecc/tb
++incdir+${CALIPTRA_ROOT}/src/sha512/rtl
++incdir+${CALIPTRA_ROOT}/src/sha512_masked/rtl
++incdir+${CALIPTRA_ROOT}/src/hmac/rtl
++incdir+${CALIPTRA_ROOT}/src/hmac_drbg/rtl
++incdir+${CALIPTRA_ROOT}/src/ecc/rtl
+${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh
+${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sva.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_macros.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sram.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_defines_pkg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_ahb_srom.sv
+${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
+${CALIPTRA_ROOT}/src/keyvault/rtl/kv_defines_pkg.sv
+${CALIPTRA_ROOT}/src/keyvault/rtl/kv_macros.svh
+${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_defines_pkg.sv
+${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_macros.svh
+${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_gen_hash.sv
+${CALIPTRA_ROOT}/src/ecc/tb/ecc_montgomerymultiplier_tb.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
+${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg_pkg.sv
+${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg.sv
+${CALIPTRA_ROOT}/src/keyvault/rtl/kv.sv
+${CALIPTRA_ROOT}/src/keyvault/rtl/kv_fsm.sv
+${CALIPTRA_ROOT}/src/keyvault/rtl/kv_read_client.sv
+${CALIPTRA_ROOT}/src/keyvault/rtl/kv_write_client.sv
+${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg_pkg.sv
+${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg.sv
+${CALIPTRA_ROOT}/src/pcrvault/rtl/pv.sv
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg_pkg.sv
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_params_pkg.sv
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_ctrl.sv
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512.sv
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_core.v
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_h_constants.v
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_k_constants.v
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_w_mem.v
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg.sv
+${CALIPTRA_ROOT}/src/sha512_masked/rtl/sha512_masked_defines_pkg.sv
+${CALIPTRA_ROOT}/src/sha512_masked/rtl/sha512_masked_core.sv
+${CALIPTRA_ROOT}/src/sha512_masked/rtl/sha512_masked_lfsr.sv
+${CALIPTRA_ROOT}/src/hmac/rtl/hmac_param_pkg.sv
+${CALIPTRA_ROOT}/src/hmac/rtl/hmac_reg_pkg.sv
+${CALIPTRA_ROOT}/src/hmac/rtl/hmac_ctrl.sv
+${CALIPTRA_ROOT}/src/hmac/rtl/hmac.sv
+${CALIPTRA_ROOT}/src/hmac/rtl/hmac_core.v
+${CALIPTRA_ROOT}/src/hmac/rtl/hmac_reg.sv
+${CALIPTRA_ROOT}/src/hmac_drbg/rtl/hmac_drbg.sv
+${CALIPTRA_ROOT}/src/hmac_drbg/rtl/hmac_drbg_lfsr.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_reg_pkg.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_defines_pkg.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_params_pkg.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_dsa_uop_pkg.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_pm_uop_pkg.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_top.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_reg.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_dsa_ctrl.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_dsa_sequencer.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_scalar_blinding.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_hmac_drbg_interface.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_arith_unit.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_pm_ctrl.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_pm_sequencer.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_ram_tdp_file.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_fau.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_montgomerymultiplier.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_pe_first.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_pe.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_pe_final.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_mult_dsp.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_add_sub_mod_alter.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_adder.sv
\ No newline at end of file
diff --git a/src/ecc/config/ecc_top.vf b/src/ecc/config/ecc_top.vf
index ad7987f01..51e02138b 100644
--- a/src/ecc/config/ecc_top.vf
+++ b/src/ecc/config/ecc_top.vf
@@ -18,6 +18,7 @@ ${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
 ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_defines_pkg.sv
 ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_macros.svh
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_defines_pkg.sv
@@ -34,9 +35,9 @@ ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg.sv
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg_pkg.sv
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_params_pkg.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_ctrl.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512.sv
-${CALIPTRA_ROOT}/src/sha512/rtl/sha512_param.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_core.v
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_h_constants.v
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_k_constants.v
diff --git a/src/ecc/config/ecc_top_tb.vf b/src/ecc/config/ecc_top_tb.vf
index ab0098841..ea081512c 100644
--- a/src/ecc/config/ecc_top_tb.vf
+++ b/src/ecc/config/ecc_top_tb.vf
@@ -2,6 +2,7 @@
 +incdir+${CALIPTRA_ROOT}/src/libs/rtl
 +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl
 +incdir+${CALIPTRA_ROOT}/src/pcrvault/rtl
++incdir+${CALIPTRA_ROOT}/src/ecc/coverage
 +incdir+${CALIPTRA_ROOT}/src/ecc/tb
 +incdir+${CALIPTRA_ROOT}/src/sha512/rtl
 +incdir+${CALIPTRA_ROOT}/src/sha512_masked/rtl
@@ -19,11 +20,14 @@ ${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
 ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_defines_pkg.sv
 ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_macros.svh
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_defines_pkg.sv
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_macros.svh
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_gen_hash.sv
+${CALIPTRA_ROOT}/src/ecc/coverage/ecc_top_cov_if.sv
+${CALIPTRA_ROOT}/src/ecc/coverage/ecc_top_cov_bind.sv
 ${CALIPTRA_ROOT}/src/ecc/tb/ecc_top_tb.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
 ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg_pkg.sv
@@ -36,9 +40,9 @@ ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg.sv
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg_pkg.sv
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_params_pkg.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_ctrl.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512.sv
-${CALIPTRA_ROOT}/src/sha512/rtl/sha512_param.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_core.v
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_h_constants.v
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_k_constants.v
diff --git a/src/ecc/coverage/ecc_top_cov_bind.sv b/src/ecc/coverage/ecc_top_cov_bind.sv
new file mode 100644
index 000000000..a04dc5097
--- /dev/null
+++ b/src/ecc/coverage/ecc_top_cov_bind.sv
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+module ecc_top_cov_bind;
+    `ifdef FCOV
+    bind ecc_top ecc_top_cov_if i_ecc_top_cov_if(.*);
+    `endif
+endmodule
diff --git a/src/ecc/coverage/ecc_top_cov_if.sv b/src/ecc/coverage/ecc_top_cov_if.sv
new file mode 100644
index 000000000..97f1a8cac
--- /dev/null
+++ b/src/ecc/coverage/ecc_top_cov_if.sv
@@ -0,0 +1,155 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+`ifndef VERILATOR
+
+interface ecc_top_cov_if     
+    (
+    input logic           clk,
+    input logic           reset_n,
+    input logic           cptra_pwrgood
+
+);
+
+    logic [1 : 0] ecc_cmd;
+    logic [1 : 0] ecc_sw_cmd;
+    logic zeroize;
+    logic pcr_sign_mode;
+    logic ready;
+    logic valid;
+
+    logic dest_keyvault;
+
+    logic error_flag;
+    logic privkey_input_outofrange;
+    logic r_output_outofrange;
+    logic r_input_outofrange;
+    logic s_input_outofrange;
+    logic pubkeyx_input_outofrange;
+    logic pubkeyy_input_outofrange;
+    logic pubkey_input_invalid;
+    logic pcr_sign_input_invalid;
+    logic keygen_process;
+    logic signing_process;
+    logic verifying_process;
+
+
+    logic mod_p_q;
+    logic add_en;
+    logic add_sub_i;
+    logic [383 : 0] add_res0;
+    logic add_cout0;
+    logic add_cout1;
+    logic add_res_less_than_prime;
+    logic add_res_greater_than_prime;
+    logic add_res_greater_than_384_bit;
+
+    logic mult_ready;
+    logic mult_last_reduction;
+    logic mult_final_subtraction;
+
+    assign mod_p_q = ecc_top.ecc_dsa_ctrl_i.ecc_arith_unit_i.mod_p_q;
+    assign add_en = ecc_top.ecc_dsa_ctrl_i.ecc_arith_unit_i.ecc_fau_i.add_en_i;
+    assign add_sub_i = ecc_top.ecc_dsa_ctrl_i.ecc_arith_unit_i.ecc_fau_i.sub_i;
+    assign add_res0 = ecc_top.ecc_dsa_ctrl_i.ecc_arith_unit_i.ecc_fau_i.i_ADDER_SUBTRACTOR.r0_reg;
+    assign add_cout0 = ecc_top.ecc_dsa_ctrl_i.ecc_arith_unit_i.ecc_fau_i.i_ADDER_SUBTRACTOR.carry0_reg;
+    assign add_cout1 = ecc_top.ecc_dsa_ctrl_i.ecc_arith_unit_i.ecc_fau_i.i_ADDER_SUBTRACTOR.carry1;
+    assign add_res_less_than_prime = ((add_cout0 == 1'b0) & (add_res0 < ecc_top.ecc_dsa_ctrl_i.ecc_arith_unit_i.ecc_fau_i.prime_i));
+    assign add_res_greater_than_prime = ((add_cout0 == 1'b0) & (add_res0 >= ecc_top.ecc_dsa_ctrl_i.ecc_arith_unit_i.ecc_fau_i.prime_i));
+    assign add_res_greater_than_384_bit = (add_cout0 == 1'b1);
+    
+    assign mult_ready = ecc_top.ecc_dsa_ctrl_i.ecc_arith_unit_i.ecc_fau_i.i_MULTIPLIER.ready_o;
+    assign mult_last_reduction = ecc_top.ecc_dsa_ctrl_i.ecc_arith_unit_i.ecc_fau_i.i_MULTIPLIER.last_reduction;
+    assign mult_final_subtraction = mult_ready & mult_last_reduction;
+    
+    assign ecc_cmd = ecc_top.ecc_dsa_ctrl_i.cmd_reg;
+    assign pcr_sign_mode = ecc_top.ecc_dsa_ctrl_i.pcr_sign_mode;
+    assign zeroize = ecc_top.ecc_dsa_ctrl_i.zeroize_reg;
+    assign ready = ecc_top.ecc_dsa_ctrl_i.dsa_ready_reg;
+    assign valid = ecc_top.ecc_dsa_ctrl_i.dsa_valid_reg;
+
+    always_ff @(posedge clk) begin
+        if (!reset_n) begin
+            ecc_sw_cmd <= '0;
+        end
+        else if (ecc_top.ecc_reg1.decoded_reg_strb.ECC_CTRL && ecc_top.ecc_reg1.decoded_req_is_wr) begin // SW write
+            ecc_sw_cmd <= (ecc_top.ecc_reg1.field_storage.ECC_CTRL.CTRL.value & ~ecc_top.ecc_reg1.decoded_wr_biten[1:0]) | (ecc_top.ecc_reg1.decoded_wr_data[1:0] & ecc_top.ecc_reg1.decoded_wr_biten[1:0]);
+        end
+    end
+
+    assign dest_keyvault = ecc_top.ecc_dsa_ctrl_i.dest_keyvault;
+
+    assign error_flag = ecc_top.ecc_dsa_ctrl_i.error_flag;
+    assign privkey_input_outofrange = ecc_top.ecc_dsa_ctrl_i.privkey_input_outofrange;
+    assign r_output_outofrange = ecc_top.ecc_dsa_ctrl_i.r_output_outofrange;
+    assign r_input_outofrange = ecc_top.ecc_dsa_ctrl_i.r_input_outofrange;
+    assign s_input_outofrange = ecc_top.ecc_dsa_ctrl_i.s_input_outofrange;
+    assign pubkeyx_input_outofrange = ecc_top.ecc_dsa_ctrl_i.pubkeyx_input_outofrange;
+    assign pubkeyy_input_outofrange = ecc_top.ecc_dsa_ctrl_i.pubkeyy_input_outofrange;
+    assign pubkey_input_invalid = ecc_top.ecc_dsa_ctrl_i.pubkey_input_invalid;
+    assign pcr_sign_input_invalid = ecc_top.ecc_dsa_ctrl_i.pcr_sign_input_invalid;
+    assign keygen_process = ecc_top.ecc_dsa_ctrl_i.keygen_process;
+    assign signing_process = ecc_top.ecc_dsa_ctrl_i.signing_process;
+    assign verifying_process = ecc_top.ecc_dsa_ctrl_i.verifying_process;
+
+    covergroup ecc_top_cov_grp @(posedge clk);
+        reset_cp: coverpoint reset_n;
+        cptra_pwrgood_cp: coverpoint cptra_pwrgood;
+
+        ecc_cmd_cp: coverpoint ecc_cmd;
+        pcr_sign_cp: coverpoint pcr_sign_mode;
+        zeroize_cp: coverpoint zeroize;
+        ready_cp: coverpoint ready;
+        valid_cp: coverpoint valid;
+
+        dest_keyvault_cp: coverpoint dest_keyvault;
+
+        error_flag_cp: coverpoint error_flag;
+        privkey_input_outofrange_cp: coverpoint privkey_input_outofrange;
+        r_output_outofrange_cp: coverpoint r_output_outofrange;
+        r_input_outofrange_cp: coverpoint r_input_outofrange;
+        s_input_outofrange_cp: coverpoint s_input_outofrange;
+        pubkeyx_input_outofrange_cp: coverpoint pubkeyx_input_outofrange;
+        pubkeyy_input_outofrange_cp: coverpoint pubkeyy_input_outofrange;
+        pubkey_input_invalid_cp: coverpoint pubkey_input_invalid;
+        pcr_sign_input_invalid_cp: coverpoint pcr_sign_input_invalid;
+
+        cmd_ready_cp: cross ecc_sw_cmd, ready;
+        cmd_kv_cp: cross ecc_cmd, dest_keyvault;
+        pcr_ready_cp: cross ready, pcr_sign_mode;
+        pcr_cmd_cp: cross pcr_sign_mode, ecc_cmd;
+        zeroize_pcr_cp: cross zeroize, pcr_sign_mode;
+        zeroize_cmd_cp: cross zeroize, ecc_cmd;
+        zeroize_error_cp: cross zeroize, error_flag;
+        zeroize_ready_cp: cross ready, zeroize;
+        pcr_sign_input_invalid_cmd_cp: cross error_flag, ecc_cmd;
+        error_keygen_cp: cross error_flag, keygen_process;
+        error_signing_cp: cross error_flag, signing_process;
+        error_verifying_cp: cross error_flag, verifying_process;
+
+        // modular operation
+        mult_final_subtraction_cp: coverpoint mult_final_subtraction;
+        add_carry_cp: cross mod_p_q, add_sub_i, add_cout0, add_cout1;
+        add_result_less_than_prime_cp: cross mod_p_q, add_sub_i, add_res_less_than_prime;
+        add_result_greater_than_prime_cp: cross mod_p_q, add_sub_i, add_res_greater_than_prime;
+        add_result_greater_than_384_bit_cp: cross mod_p_q, add_sub_i, add_res_greater_than_384_bit;
+        
+
+    endgroup
+
+    ecc_top_cov_grp ecc_top_cov_grp1 = new();
+
+endinterface
+
+`endif
\ No newline at end of file
diff --git a/src/ecc/rtl/ecc_add_sub_mod_alter.sv b/src/ecc/rtl/ecc_add_sub_mod_alter.sv
index c335d368c..2bf3eb332 100644
--- a/src/ecc/rtl/ecc_add_sub_mod_alter.sv
+++ b/src/ecc/rtl/ecc_add_sub_mod_alter.sv
@@ -50,7 +50,8 @@ module ecc_add_sub_mod_alter #(
     logic [REG_SIZE-1 : 0] r0_reg;
     logic                  carry0_reg;
 
-    logic                   carry_garbage_bit;
+    logic                  carry1;
+    logic [1 : 0]          push_result_reg;
 
     ecc_adder #(
         .RADIX(REG_SIZE)
@@ -71,7 +72,7 @@ module ecc_add_sub_mod_alter #(
         .b_i(opb1),
         .cin_i(sub_n),
         .s_o(r1),
-        .cout_o(carry_garbage_bit)
+        .cout_o(carry1)
     );
 
 
@@ -84,22 +85,31 @@ module ecc_add_sub_mod_alter #(
         if(!reset_n) begin
             r0_reg <= '0;
             carry0_reg <= '0;
-            ready_o <= 1'b0;
         end
         else if (zeroize) begin
             r0_reg <= '0;
             carry0_reg <= '0;
-            ready_o <= 1'b0;
         end
         else if (add_en_i) begin 
             r0_reg <= r0;
             carry0_reg <= carry0;
-            ready_o <= 1'b0;
         end
-        else
-            ready_o <= 1'b1;
     end
 
-    assign res_o = (sub_n ^ carry0_reg)? r0 : r1;
+    // Determines when results are ready
+    always_ff @(posedge clk or negedge reset_n) begin
+        if (!reset_n)
+            push_result_reg <= 2'b0;
+        else if (zeroize)
+            push_result_reg <= 2'b0;
+        else if (add_en_i)
+            push_result_reg <= 2'b10;
+        else // one shift to right
+            push_result_reg <= (push_result_reg >> 1);
+    end
+
+    assign ready_o = push_result_reg[0];
+
+    assign res_o = sub_n ? (carry0_reg ^ carry1)? r1 : r0 : (carry0_reg) ? r0 : r1;
     
 endmodule
diff --git a/src/ecc/rtl/ecc_dsa_ctrl.sv b/src/ecc/rtl/ecc_dsa_ctrl.sv
index 058d6ad0d..48eb05af2 100644
--- a/src/ecc/rtl/ecc_dsa_ctrl.sv
+++ b/src/ecc/rtl/ecc_dsa_ctrl.sv
@@ -81,7 +81,8 @@ module ecc_dsa_ctrl
 
     // Interrupts (from ecc_reg)
     output logic error_intr,
-    output logic notif_intr
+    output logic notif_intr,
+    input  logic debugUnlock_or_scan_mode_switch
     );
 
     //----------------------------------------------------------------
@@ -116,6 +117,7 @@ module ecc_dsa_ctrl
     logic hw_scalar_G_we;
     logic hw_scalar_PK_we;
     logic hw_verify_r_we;
+    logic hw_pk_chk_we;
     logic scalar_G_sel;
 
     logic dsa_valid_reg;
@@ -140,6 +142,7 @@ module ecc_dsa_ctrl
     logic [REG_SIZE-1 : 0]  lambda_reg;
     logic [REG_SIZE-1 : 0]  masking_rnd;
     logic [REG_SIZE-1 : 0]  masking_rnd_reg;
+    logic [REG_SIZE-1 : 0]  pk_chk_reg;
 
     logic [REG_SIZE-1 : 0]  scalar_G_reg;
     logic [REG_SIZE-1 : 0]  scalar_PK_reg;
@@ -174,7 +177,10 @@ module ecc_dsa_ctrl
     logic kv_privkey_ready, kv_privkey_done;
     logic kv_seed_ready, kv_seed_done ;
     logic kv_write_ready, kv_write_done;
-  
+    //KV Read Data Present
+    logic kv_read_data_present;
+    logic kv_read_data_present_set, kv_read_data_present_reset;
+    
     kv_read_ctrl_reg_t kv_privkey_read_ctrl_reg;
     kv_read_ctrl_reg_t kv_seed_read_ctrl_reg;
     kv_write_ctrl_reg_t kv_write_ctrl_reg;
@@ -182,6 +188,25 @@ module ecc_dsa_ctrl
     logic pcr_sign_mode;
     
     instr_struct_t prog_instr;
+    
+    // ERROR
+    logic keygen_process;
+    logic signing_process;
+    logic verifying_process;
+
+    logic privkey_input_outofrange;
+    logic r_output_outofrange;
+    logic r_input_outofrange;
+    logic s_input_outofrange;
+    logic pubkeyx_input_outofrange;
+    logic pubkeyy_input_outofrange;
+    logic pubkey_input_invalid;
+    logic pcr_sign_input_invalid;
+
+    logic error_flag;
+    logic error_flag_reg;
+    logic error_flag_edge;
+
     //----------------------------------------------------------------
     // Module instantiantions.
     //----------------------------------------------------------------
@@ -283,7 +308,7 @@ module ecc_dsa_ctrl
     // read the registers written by sw
     always_comb begin
         cmd_reg = hwif_out.ECC_CTRL.CTRL.value;
-        zeroize_reg = hwif_out.ECC_CTRL.ZEROIZE.value;
+        zeroize_reg = hwif_out.ECC_CTRL.ZEROIZE.value || debugUnlock_or_scan_mode_switch;
         
         sca_point_rnd_en  = 1'b1;
         sca_mask_sign_en  = 1'b1;
@@ -297,18 +322,23 @@ module ecc_dsa_ctrl
             privkey_we_reg      <= '0;
             privkey_we_reg_ff   <= '0;
             kv_reg    <= '0;
+            kv_read_data_present <= '0;
         end
         else if (zeroize_reg) begin
             privkey_we_reg      <= '0;
             privkey_we_reg_ff   <= '0;
             kv_reg    <= '0;
+            kv_read_data_present <= '0;
         end
         //Store private key here before pushing to keyvault
         else begin
             privkey_we_reg <= hw_privkey_we;
             privkey_we_reg_ff <= privkey_we_reg;
-            if (privkey_out_we & dest_keyvault)
+            if (privkey_out_we & (dest_keyvault | kv_read_data_present))
                 kv_reg <= read_reg;
+
+            kv_read_data_present <= kv_read_data_present_set ? '1 :
+                                    kv_read_data_present_reset ? '0 : kv_read_data_present;
         end
     end
 
@@ -335,23 +365,23 @@ module ecc_dsa_ctrl
             //Key Vault has priority if enabled to drive these registers
             //don't store the private key generated in sw accessible register if it's going to keyvault
             privkey_reg[dword] = hwif_out.ECC_PRIVKEY_IN[11-dword].PRIVKEY_IN.value;
-            hwif_in.ECC_PRIVKEY_IN[dword].PRIVKEY_IN.we = pcr_sign_mode | (kv_privkey_write_en & (kv_privkey_write_offset == dword));
+            hwif_in.ECC_PRIVKEY_IN[dword].PRIVKEY_IN.we = (pcr_sign_mode | (kv_privkey_write_en & (kv_privkey_write_offset == dword))) & !zeroize_reg;
             hwif_in.ECC_PRIVKEY_IN[dword].PRIVKEY_IN.next = pcr_sign_mode ? pcr_signing_data.pcr_signing_privkey[dword] : kv_privkey_write_en? kv_privkey_write_data : read_reg[11-dword];
             hwif_in.ECC_PRIVKEY_IN[dword].PRIVKEY_IN.hwclr = zeroize_reg;
         end 
 
         for (int dword=0; dword < 12; dword++)begin
             //If keyvault is not enabled, grab the sw value as usual
-            hwif_in.ECC_PRIVKEY_OUT[dword].PRIVKEY_OUT.we = privkey_out_we & ~dest_keyvault;
+            hwif_in.ECC_PRIVKEY_OUT[dword].PRIVKEY_OUT.we = (privkey_out_we & ~(dest_keyvault | kv_read_data_present)) & !zeroize_reg;
             hwif_in.ECC_PRIVKEY_OUT[dword].PRIVKEY_OUT.next = read_reg[11-dword];
             hwif_in.ECC_PRIVKEY_OUT[dword].PRIVKEY_OUT.hwclr = zeroize_reg;
         end
 
         for (int dword=0; dword < 12; dword++)begin
             seed_reg[dword] = hwif_out.ECC_SEED[11-dword].SEED.value;
-            hwif_in.ECC_SEED[dword].SEED.we = kv_seed_write_en & (kv_seed_write_offset == dword);
+            hwif_in.ECC_SEED[dword].SEED.we = (kv_seed_write_en & (kv_seed_write_offset == dword)) & !zeroize_reg;
             hwif_in.ECC_SEED[dword].SEED.next = kv_seed_write_data;
-            hwif_in.ECC_SEED[dword].SEED.hwclr = zeroize_reg;
+            hwif_in.ECC_SEED[dword].SEED.hwclr = zeroize_reg | kv_read_data_present_reset;
         end
 
         for (int dword=0; dword < 12; dword++)begin
@@ -361,41 +391,41 @@ module ecc_dsa_ctrl
 
         for (int dword=0; dword < 12; dword++)begin
             msg_reg[dword] = hwif_out.ECC_MSG[11-dword].MSG.value;
-            hwif_in.ECC_MSG[dword].MSG.we = pcr_sign_mode;
+            hwif_in.ECC_MSG[dword].MSG.we = pcr_sign_mode & !zeroize_reg;
             hwif_in.ECC_MSG[dword].MSG.next = pcr_signing_data.pcr_hash[dword];
             hwif_in.ECC_MSG[dword].MSG.hwclr = zeroize_reg;
         end
 
         for (int dword=0; dword < 12; dword++)begin
             pubkeyx_reg[dword] = hwif_out.ECC_PUBKEY_X[11-dword].PUBKEY_X.value;
-            hwif_in.ECC_PUBKEY_X[dword].PUBKEY_X.we = hw_pubkeyx_we;
+            hwif_in.ECC_PUBKEY_X[dword].PUBKEY_X.we = hw_pubkeyx_we & !zeroize_reg;
             hwif_in.ECC_PUBKEY_X[dword].PUBKEY_X.next = read_reg[11-dword];  
             hwif_in.ECC_PUBKEY_X[dword].PUBKEY_X.hwclr = zeroize_reg;
         end
 
         for (int dword=0; dword < 12; dword++)begin
             pubkeyy_reg[dword] = hwif_out.ECC_PUBKEY_Y[11-dword].PUBKEY_Y.value;
-            hwif_in.ECC_PUBKEY_Y[dword].PUBKEY_Y.we = hw_pubkeyy_we;
+            hwif_in.ECC_PUBKEY_Y[dword].PUBKEY_Y.we = hw_pubkeyy_we & !zeroize_reg;
             hwif_in.ECC_PUBKEY_Y[dword].PUBKEY_Y.next = read_reg[11-dword];
             hwif_in.ECC_PUBKEY_Y[dword].PUBKEY_Y.hwclr = zeroize_reg;
         end
 
         for (int dword=0; dword < 12; dword++)begin
             r_reg[dword] = hwif_out.ECC_SIGN_R[11-dword].SIGN_R.value;
-            hwif_in.ECC_SIGN_R[dword].SIGN_R.we = hw_r_we;
+            hwif_in.ECC_SIGN_R[dword].SIGN_R.we = hw_r_we & !zeroize_reg;
             hwif_in.ECC_SIGN_R[dword].SIGN_R.next = read_reg[11-dword];
             hwif_in.ECC_SIGN_R[dword].SIGN_R.hwclr = zeroize_reg;
         end
 
         for (int dword=0; dword < 12; dword++)begin
             s_reg[dword] = hwif_out.ECC_SIGN_S[11-dword].SIGN_S.value;
-            hwif_in.ECC_SIGN_S[dword].SIGN_S.we = hw_s_we;
+            hwif_in.ECC_SIGN_S[dword].SIGN_S.we = hw_s_we & !zeroize_reg;
             hwif_in.ECC_SIGN_S[dword].SIGN_S.next = read_reg[11-dword];
             hwif_in.ECC_SIGN_S[dword].SIGN_S.hwclr = zeroize_reg;
         end
 
         for (int dword=0; dword < 12; dword++)begin 
-            hwif_in.ECC_VERIFY_R[dword].VERIFY_R.we = hw_verify_r_we;       
+            hwif_in.ECC_VERIFY_R[dword].VERIFY_R.we = hw_verify_r_we & !zeroize_reg;       
             hwif_in.ECC_VERIFY_R[dword].VERIFY_R.next = read_reg[11-dword];
             hwif_in.ECC_VERIFY_R[dword].VERIFY_R.hwclr = zeroize_reg;
         end
@@ -411,7 +441,7 @@ module ecc_dsa_ctrl
     always_comb hwif_in.ECC_CTRL.PCR_SIGN.hwclr = hwif_out.ECC_CTRL.PCR_SIGN.value;
     
     // TODO add other interrupt hwset signals (errors)
-    always_comb hwif_in.intr_block_rf.error_internal_intr_r.error_internal_sts.hwset = 1'b0;
+    always_comb hwif_in.intr_block_rf.error_internal_intr_r.error_internal_sts.hwset = error_flag_reg;
     always_comb hwif_in.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.hwset = ecc_status_done_p;
 
 
@@ -443,6 +473,10 @@ module ecc_dsa_ctrl
     `CALIPTRA_KV_READ_CTRL_REG2STRUCT(kv_seed_read_ctrl_reg, ecc_kv_rd_seed_ctrl)
     `CALIPTRA_KV_WRITE_CTRL_REG2STRUCT(kv_write_ctrl_reg, ecc_kv_wr_pkey_ctrl)
 
+    //Force result into KV reg whenever source came from KV
+    always_comb kv_read_data_present_set = kv_seed_read_ctrl_reg.read_en;
+    always_comb kv_read_data_present_reset = kv_read_data_present & privkey_out_we;
+
     always_comb pcr_sign_mode = hwif_out.ECC_CTRL.PCR_SIGN.value;
 
     //----------------------------------------------------------------
@@ -483,7 +517,8 @@ module ecc_dsa_ctrl
         hw_scalar_G_we = 0;
         hw_scalar_PK_we = 0;
         hw_verify_r_we = 0;
-        if (prog_instr.opcode == DSA_UOP_RD_CORE)begin
+        hw_pk_chk_we = 0;
+        if ((prog_instr.opcode == DSA_UOP_RD_CORE) & (cycle_cnt == 0)) begin
             unique casez (prog_instr.reg_id)
                 PRIVKEY_ID      : hw_privkey_we = 1;
                 PUBKEYX_ID      : hw_pubkeyx_we = 1;
@@ -493,6 +528,7 @@ module ecc_dsa_ctrl
                 SCALAR_G_ID     : hw_scalar_G_we = 1;
                 SCALAR_PK_ID    : hw_scalar_PK_we = 1;
                 VERIFY_R_ID     : hw_verify_r_we = 1;
+                PK_VALID_ID     : hw_pk_chk_we = 1;
                 default         : 
                     begin 
                         hw_privkey_we = 0;
@@ -503,6 +539,7 @@ module ecc_dsa_ctrl
                         hw_scalar_G_we = 0;
                         hw_scalar_PK_we = 0;
                         hw_verify_r_we = 0;
+                        hw_pk_chk_we = 0;
                     end
             endcase
         end
@@ -519,6 +556,7 @@ module ecc_dsa_ctrl
                 CONST_ZERO_ID         : write_reg = {zero_pad, ZERO_CONST};
                 CONST_ONE_ID          : write_reg = {zero_pad, ONE_CONST};
                 CONST_E_a_MONT_ID     : write_reg = {zero_pad, E_a_MONT};
+                CONST_E_b_MONT_ID     : write_reg = {zero_pad, E_b_MONT};
                 CONST_E_3b_MONT_ID    : write_reg = {zero_pad, E_3b_MONT};
                 CONST_ONE_p_MONT_ID   : write_reg = {zero_pad, ONE_p_MONT};
                 CONST_R2_p_MONT_ID    : write_reg = {zero_pad, R2_p_MONT};
@@ -567,6 +605,55 @@ module ecc_dsa_ctrl
     assign hmac_busy = ~hmac_ready;
     assign subcomponent_busy = pm_busy_o | hmac_busy | scalar_sca_busy_o;
 
+
+    //----------------------------------------------------------------
+    // ERROR detection
+    //
+    // bound check for different input/output registers.
+    //----------------------------------------------------------------   
+    always_ff @(posedge clk or negedge reset_n) 
+    begin : pk_chk
+        if(!reset_n) begin
+            pk_chk_reg <= '0;
+        end
+        else if(zeroize_reg) begin
+            pk_chk_reg <= '0;
+        end
+        else begin
+            if (hw_pk_chk_we) begin
+                pk_chk_reg <= read_reg;
+            end
+        end
+    end // pk_chk
+
+    always_ff @(posedge clk or negedge reset_n) 
+    begin : error_detection
+        if(!reset_n) begin
+            error_flag_reg <= '0;
+        end
+        else if(zeroize_reg) begin
+            error_flag_reg <= '0;
+        end
+        else begin
+            error_flag_reg  <= error_flag;
+        end
+    end // error_detection
+
+    assign error_flag_edge = error_flag & (!error_flag_reg);
+    
+    assign privkey_input_outofrange = signing_process & ((privkey_reg == 0) | (privkey_reg >= GROUP_ORDER));
+    assign r_output_outofrange      = signing_process & (hw_r_we & (read_reg == 0));
+
+    assign r_input_outofrange       = verifying_process & ((r_reg == 0) | (r_reg >= GROUP_ORDER));
+    assign s_input_outofrange       = verifying_process & ((s_reg == 0) | (s_reg >= GROUP_ORDER));
+    assign pubkeyx_input_outofrange = verifying_process & (pubkeyx_reg >= PRIME);
+    assign pubkeyy_input_outofrange = verifying_process & (pubkeyy_reg >= PRIME);
+    assign pubkey_input_invalid     = verifying_process & (pk_chk_reg != 0);
+
+    assign pcr_sign_input_invalid   = ((cmd_reg == KEYGEN) | (cmd_reg == VERIFY)) & pcr_sign_mode;
+
+    assign error_flag = privkey_input_outofrange | r_output_outofrange | r_input_outofrange | s_input_outofrange | pubkeyx_input_outofrange | pubkeyy_input_outofrange | pubkey_input_invalid | pcr_sign_input_invalid;
+
     //----------------------------------------------------------------
     // ECDSA_FSM_flow
     //
@@ -577,27 +664,40 @@ module ecc_dsa_ctrl
     always_ff @(posedge clk or negedge reset_n) 
     begin : ECDSA_FSM
         if(!reset_n) begin
-            prog_cntr       <= DSA_RESET;
-            cycle_cnt       <= '0;
-            pm_cmd_reg      <= '0;
-            dsa_valid_reg   <= 0;
-            scalar_G_sel    <= 0;
-            hmac_mode       <= 0;
-            hmac_init       <= 0;
-            scalar_sca_en   <= 0;
+            prog_cntr           <= DSA_RESET;
+            cycle_cnt           <= '0;
+            pm_cmd_reg          <= '0;
+            dsa_valid_reg       <= 0;
+            scalar_G_sel        <= 0;
+            hmac_mode           <= 0;
+            hmac_init           <= 0;
+            scalar_sca_en       <= 0;
+            keygen_process      <= 0;
+            signing_process     <= 0;
+            verifying_process   <= 0;
         end
         else if(zeroize_reg) begin
-            prog_cntr       <= DSA_RESET;
-            cycle_cnt       <= '0;
-            pm_cmd_reg      <= '0;
-            dsa_valid_reg   <= 0;
-            scalar_G_sel    <= 0;
-            hmac_mode       <= 0;
-            hmac_init       <= 0;
-            scalar_sca_en   <= 0;
+            prog_cntr           <= DSA_RESET;
+            cycle_cnt           <= '0;
+            pm_cmd_reg          <= '0;
+            dsa_valid_reg       <= 0;
+            scalar_G_sel        <= 0;
+            hmac_mode           <= 0;
+            hmac_init           <= 0;
+            scalar_sca_en       <= 0;
+            keygen_process      <= 0;
+            signing_process     <= 0;
+            verifying_process   <= 0;
         end
         else begin
-            if (subcomponent_busy) begin //Stalled until sub-component is done
+            if (error_flag_edge) begin
+                prog_cntr       <= DSA_NOP;
+                cycle_cnt       <= 2'd3;
+                pm_cmd_reg      <= '0;
+                scalar_sca_en   <= 0;
+                hmac_init       <= 0;
+            end
+            else if (subcomponent_busy) begin //Stalled until sub-component is done
                 prog_cntr       <= prog_cntr;
                 cycle_cnt       <= 2'd3;
                 pm_cmd_reg      <= '0;
@@ -611,6 +711,9 @@ module ecc_dsa_ctrl
                 cycle_cnt <= '0;
                 unique casez (prog_cntr)
                     DSA_NOP : begin 
+                        keygen_process      <= 0;
+                        signing_process     <= 0;
+                        verifying_process   <= 0;
                         // Waiting for new valid command 
                         unique casez (cmd_reg)
                             KEYGEN : begin  // keygen
@@ -618,6 +721,7 @@ module ecc_dsa_ctrl
                                 dsa_valid_reg <= 0;
                                 scalar_G_sel <= 0;
                                 hmac_mode <= 0;
+                                keygen_process <= 1;
                             end   
 
                             SIGN : begin  // signing
@@ -625,12 +729,14 @@ module ecc_dsa_ctrl
                                 dsa_valid_reg <= 0;
                                 scalar_G_sel <= 0;
                                 hmac_mode <= 1;
+                                signing_process <= 1;
                             end                                   
 
                             VERIFY : begin  // verifying
                                 prog_cntr <= DSA_VER_S;
                                 dsa_valid_reg <= 0;
                                 scalar_G_sel <= 1;
+                                verifying_process <= 1;
                             end
 
                             default : begin
@@ -702,6 +808,7 @@ module ecc_dsa_ctrl
     (
         .clk(clk),
         .rst_b(reset_n),
+        .zeroize(zeroize_reg),
 
         //client control register
         .read_ctrl_reg(kv_privkey_read_ctrl_reg),
@@ -729,6 +836,7 @@ module ecc_dsa_ctrl
     (
         .clk(clk),
         .rst_b(reset_n),
+        .zeroize(zeroize_reg),
 
         //client control register
         .read_ctrl_reg(kv_seed_read_ctrl_reg),
@@ -755,6 +863,7 @@ module ecc_dsa_ctrl
     (
         .clk(clk),
         .rst_b(reset_n),
+        .zeroize(zeroize_reg),
 
         //client control register
         .write_ctrl_reg(kv_write_ctrl_reg),
diff --git a/src/ecc/rtl/ecc_dsa_sequencer.sv b/src/ecc/rtl/ecc_dsa_sequencer.sv
index 6c5ce3398..a41c080cb 100644
--- a/src/ecc/rtl/ecc_dsa_sequencer.sv
+++ b/src/ecc/rtl/ecc_dsa_sequencer.sv
@@ -112,24 +112,30 @@ module ecc_dsa_sequencer
                     DSA_SGN_S+ 14  : douta <= {DSA_UOP_NOP,           NOP_ID,             UOP_OPR_DONTCARE};
 
                     //VERIFY
-                    DSA_VER_S     : douta <= {DSA_UOP_WR_CORE,        MSG_ID,             UOP_OPR_HASH_MSG};
-                    DSA_VER_S+ 1  : douta <= {DSA_UOP_WR_CORE,        R_ID,               UOP_OPR_SIGN_R};
-                    DSA_VER_S+ 2  : douta <= {DSA_UOP_WR_CORE,        S_ID,               UOP_OPR_SIGN_S};
-                    DSA_VER_S+ 3  : douta <= {DSA_UOP_WR_CORE,        CONST_ONE_ID,       UOP_OPR_LAMBDA};
-                    DSA_VER_S+ 4  : douta <= {DSA_UOP_VERIFY0,        NOP_ID,             UOP_OPR_DONTCARE};
-                    DSA_VER_S+ 5  : douta <= {DSA_UOP_NOP,            NOP_ID,             UOP_OPR_DONTCARE};
-                    DSA_VER_S+ 6  : douta <= {DSA_UOP_RD_CORE,        SCALAR_G_ID,        UOP_OPR_SCALAR_G};
-                    DSA_VER_S+ 7  : douta <= {DSA_UOP_RD_CORE,        SCALAR_PK_ID,       UOP_OPR_SCALAR_PK};
-                    DSA_VER_S+ 8  : douta <= {DSA_UOP_WR_SCALAR,      SCALAR_G_ID,        UOP_OPR_DONTCARE};
-                    DSA_VER_S+ 9  : douta <= {DSA_UOP_VERIFY1,        NOP_ID,             UOP_OPR_DONTCARE};
-                    DSA_VER_S+ 10 : douta <= {DSA_UOP_NOP,            NOP_ID,             UOP_OPR_DONTCARE};
-                    DSA_VER_S+ 11 : douta <= {DSA_UOP_WR_CORE,        PUBKEYX_ID,         UOP_OPR_Qx_AFFN};
-                    DSA_VER_S+ 12 : douta <= {DSA_UOP_WR_CORE,        PUBKEYY_ID,         UOP_OPR_Qy_AFFN};
-                    DSA_VER_S+ 13 : douta <= {DSA_UOP_WR_SCALAR,      SCALAR_PK_ID,       UOP_OPR_DONTCARE};
-                    DSA_VER_S+ 14 : douta <= {DSA_UOP_VERIFY2,        NOP_ID,             UOP_OPR_DONTCARE};
-                    DSA_VER_S+ 15 : douta <= {DSA_UOP_NOP,            NOP_ID,             UOP_OPR_DONTCARE};
-                    DSA_VER_S+ 16 : douta <= {DSA_UOP_RD_CORE,        VERIFY_R_ID,        UOP_OPR_Qx_AFFN};
-                    DSA_VER_S+ 17 : douta <= {DSA_UOP_NOP,            NOP_ID,             UOP_OPR_DONTCARE};
+                    DSA_VER_S     : douta <= {DSA_UOP_WR_CORE,        CONST_E_b_MONT_ID,  UOP_OPR_CONST_E_b};
+                    DSA_VER_S+ 1  : douta <= {DSA_UOP_WR_CORE,        PUBKEYX_ID,         UOP_OPR_Qx_AFFN};
+                    DSA_VER_S+ 2  : douta <= {DSA_UOP_WR_CORE,        PUBKEYY_ID,         UOP_OPR_Qy_AFFN};
+                    DSA_VER_S+ 3  : douta <= {DSA_UOP_PK_CHK,         NOP_ID,             UOP_OPR_DONTCARE};
+                    DSA_VER_S+ 4  : douta <= {DSA_UOP_NOP,            NOP_ID,             UOP_OPR_DONTCARE};
+                    DSA_VER_S+ 5  : douta <= {DSA_UOP_RD_CORE,        PK_VALID_ID,        UOP_OPR_PK_VALID};
+                    DSA_VER_S+ 6  : douta <= {DSA_UOP_WR_CORE,        MSG_ID,             UOP_OPR_HASH_MSG};
+                    DSA_VER_S+ 7  : douta <= {DSA_UOP_WR_CORE,        R_ID,               UOP_OPR_SIGN_R};
+                    DSA_VER_S+ 8  : douta <= {DSA_UOP_WR_CORE,        S_ID,               UOP_OPR_SIGN_S};
+                    DSA_VER_S+ 9  : douta <= {DSA_UOP_WR_CORE,        CONST_ONE_ID,       UOP_OPR_LAMBDA};
+                    DSA_VER_S+ 10 : douta <= {DSA_UOP_VERIFY0,        NOP_ID,             UOP_OPR_DONTCARE};
+                    DSA_VER_S+ 11 : douta <= {DSA_UOP_NOP,            NOP_ID,             UOP_OPR_DONTCARE};
+                    DSA_VER_S+ 12 : douta <= {DSA_UOP_RD_CORE,        SCALAR_G_ID,        UOP_OPR_SCALAR_G};
+                    DSA_VER_S+ 13 : douta <= {DSA_UOP_RD_CORE,        SCALAR_PK_ID,       UOP_OPR_SCALAR_PK};
+                    DSA_VER_S+ 14 : douta <= {DSA_UOP_WR_SCALAR,      SCALAR_G_ID,        UOP_OPR_DONTCARE};
+                    DSA_VER_S+ 15 : douta <= {DSA_UOP_VERIFY1,        NOP_ID,             UOP_OPR_DONTCARE};
+                    DSA_VER_S+ 16 : douta <= {DSA_UOP_NOP,            NOP_ID,             UOP_OPR_DONTCARE};
+                    DSA_VER_S+ 17 : douta <= {DSA_UOP_WR_CORE,        PUBKEYX_ID,         UOP_OPR_Qx_AFFN};
+                    DSA_VER_S+ 18 : douta <= {DSA_UOP_WR_CORE,        PUBKEYY_ID,         UOP_OPR_Qy_AFFN};
+                    DSA_VER_S+ 19 : douta <= {DSA_UOP_WR_SCALAR,      SCALAR_PK_ID,       UOP_OPR_DONTCARE};
+                    DSA_VER_S+ 20 : douta <= {DSA_UOP_VERIFY2,        NOP_ID,             UOP_OPR_DONTCARE};
+                    DSA_VER_S+ 21 : douta <= {DSA_UOP_NOP,            NOP_ID,             UOP_OPR_DONTCARE};
+                    DSA_VER_S+ 22 : douta <= {DSA_UOP_RD_CORE,        VERIFY_R_ID,        UOP_OPR_Qx_AFFN};
+                    DSA_VER_S+ 23 : douta <= {DSA_UOP_NOP,            NOP_ID,             UOP_OPR_DONTCARE};
 
                     default :       douta <= {DSA_UOP_NOP,            NOP_ID,             UOP_OPR_DONTCARE};
                 endcase 
diff --git a/src/ecc/rtl/ecc_dsa_uop_pkg.sv b/src/ecc/rtl/ecc_dsa_uop_pkg.sv
index 822814317..02439063c 100644
--- a/src/ecc/rtl/ecc_dsa_uop_pkg.sv
+++ b/src/ecc/rtl/ecc_dsa_uop_pkg.sv
@@ -30,7 +30,7 @@ package ecc_dsa_uop_pkg;
 localparam integer DSA_UOP_ADDR_WIDTH       = 8;
 localparam integer DSA_OPR_ADDR_WIDTH       = 6;
 
-localparam DSA_PROG_ADDR_W                  = 6; //$clog2(DSA_VER_E+2);
+localparam DSA_PROG_ADDR_W                  = 7; //$clog2(DSA_VER_E+2);
 localparam DSA_INSTRUCTION_LENGTH           = DSA_UOP_ADDR_WIDTH + (2*DSA_OPR_ADDR_WIDTH);    // opcode + 2 * operand
 
 typedef enum logic[2 : 0]
@@ -40,7 +40,8 @@ typedef enum logic[2 : 0]
     sign_cmd    = 3'b010,
     verify0_cmd = 3'b100,
     verify1_cmd = 3'b101,
-    verify2_cmd = 3'b110
+    verify2_cmd = 3'b110,
+    pk_chk_cmd  = 3'b111
 } cmd_t;
 
 typedef struct packed
@@ -70,6 +71,7 @@ localparam opcode_t DSA_UOP_SIGN          = '{op_sel:1'b0,   wr_en:1'b0, rd_en:1
 localparam opcode_t DSA_UOP_VERIFY0       = '{op_sel:1'b0,   wr_en:1'b0, rd_en:1'b0, pm_cmd:verify0_cmd, hmac_drbg_en:1'b0, sca_en:1'b0}; // = 8'b0010_0000;
 localparam opcode_t DSA_UOP_VERIFY1       = '{op_sel:1'b0,   wr_en:1'b0, rd_en:1'b0, pm_cmd:verify1_cmd, hmac_drbg_en:1'b0, sca_en:1'b0}; // = 8'b0010_1000;
 localparam opcode_t DSA_UOP_VERIFY2       = '{op_sel:1'b0,   wr_en:1'b0, rd_en:1'b0, pm_cmd:verify2_cmd, hmac_drbg_en:1'b0, sca_en:1'b0}; // = 8'b0011_0000;
+localparam opcode_t DSA_UOP_PK_CHK        = '{op_sel:1'b0,   wr_en:1'b0, rd_en:1'b0, pm_cmd:pk_chk_cmd,  hmac_drbg_en:1'b0, sca_en:1'b0}; // = 8'b0011_1000;
 localparam opcode_t DSA_UOP_HMAC_DRBG     = '{op_sel:1'b0,   wr_en:1'b0, rd_en:1'b0, pm_cmd:no_cmd,      hmac_drbg_en:1'b1, sca_en:1'b0}; // = 8'b0100_0000;
 localparam opcode_t DSA_UOP_SCALAR_SCA    = '{op_sel:1'b0,   wr_en:1'b0, rd_en:1'b0, pm_cmd:no_cmd,      hmac_drbg_en:1'b0, sca_en:1'b1}; // = 8'b1000_0000;
 
@@ -85,6 +87,7 @@ localparam [DSA_OPR_ADDR_WIDTH-1 : 0] CONST_G_X_MONT_ID        = 6'd7;
 localparam [DSA_OPR_ADDR_WIDTH-1 : 0] CONST_G_Y_MONT_ID        = 6'd8;
 localparam [DSA_OPR_ADDR_WIDTH-1 : 0] CONST_R2_q_MONT_ID       = 6'd9;
 localparam [DSA_OPR_ADDR_WIDTH-1 : 0] CONST_ONE_q_MONT_ID      = 6'd10;
+localparam [DSA_OPR_ADDR_WIDTH-1 : 0] CONST_E_b_MONT_ID        = 6'd11;
 
 localparam [DSA_OPR_ADDR_WIDTH-1 : 0] SEED_ID                  = 6'd16;
 localparam [DSA_OPR_ADDR_WIDTH-1 : 0] MSG_ID                   = 6'd17;
@@ -99,6 +102,7 @@ localparam [DSA_OPR_ADDR_WIDTH-1 : 0] SCALAR_PK_ID             = 6'd25;
 localparam [DSA_OPR_ADDR_WIDTH-1 : 0] VERIFY_R_ID              = 6'd26;
 localparam [DSA_OPR_ADDR_WIDTH-1 : 0] LAMBDA_ID                = 6'd27;
 localparam [DSA_OPR_ADDR_WIDTH-1 : 0] MASKING_ID               = 6'd28;
+localparam [DSA_OPR_ADDR_WIDTH-1 : 0] PK_VALID_ID              = 6'd29;
 
 // DSA Subroutine listing
 localparam [DSA_PROG_ADDR_W-1 : 0] DSA_RESET                    = 6'd0;
@@ -108,7 +112,7 @@ localparam [DSA_PROG_ADDR_W-1 : 0] DSA_KG_E                     = DSA_KG_S + 12;
 localparam [DSA_PROG_ADDR_W-1 : 0] DSA_SGN_S                    = DSA_KG_E + 2; 
 localparam [DSA_PROG_ADDR_W-1 : 0] DSA_SGN_E                    = DSA_SGN_S + 14; 
 localparam [DSA_PROG_ADDR_W-1 : 0] DSA_VER_S                    = DSA_SGN_E + 2; 
-localparam [DSA_PROG_ADDR_W-1 : 0] DSA_VER_E                    = DSA_VER_S + 17;
+localparam [DSA_PROG_ADDR_W-1 : 0] DSA_VER_E                    = DSA_VER_S + 23;
 
 
 endpackage
diff --git a/src/ecc/rtl/ecc_fau.sv b/src/ecc/rtl/ecc_fau.sv
index b729cec65..56b82a6ec 100644
--- a/src/ecc/rtl/ecc_fau.sv
+++ b/src/ecc/rtl/ecc_fau.sv
@@ -51,7 +51,9 @@ module ecc_fau #(
     reg                     mult_start;
     reg                     mult_start_dly;
     wire                    mult_start_edge;
-    reg                     add_en;   
+    logic                   add_start;
+    logic                   add_start_dly;
+    logic                   add_start_edge;   
     reg                     sub;
 
     logic                   add_ready_o;
@@ -97,7 +99,7 @@ module ecc_fau #(
         .reset_n(reset_n),
         .zeroize(zeroize),
 
-        .add_en_i(add_en),
+        .add_en_i(add_start_edge),
         .sub_i(sub),
         .opa_i(opa_i),
         .opb_i(opb_i),
@@ -114,34 +116,41 @@ module ecc_fau #(
     begin
         if (!reset_n) begin
             mult_start <= '0;
-            add_en <= '0;
+            add_start <= '0;
             sub <= '0;
         end
         else if (zeroize) begin
             mult_start <= '0;
-            add_en <= '0;
+            add_start <= '0;
             sub <= '0;
         end
         else begin
             mult_start <= mult_en_i;
-            add_en <= add_en_i;
+            add_start <= add_en_i;
             sub <= sub_i;
         end
     end
 
     always_ff @(posedge clk or negedge reset_n) begin
-        if (!reset_n)
+        if (!reset_n) begin
             mult_start_dly <= '0;
-        else if (zeroize)
+            add_start_dly  <= '0;
+        end
+        else if (zeroize) begin
             mult_start_dly <= '0;
-        else
+            add_start_dly  <= '0;
+        end
+        else begin
             mult_start_dly <= mult_start;
+            add_start_dly  <= add_start;
+        end
     end
     
     assign ready_garbage_bit = add_ready_o & mult_ready_o;
     
     // generate a pulse enable for mult
     assign mult_start_edge = mult_start & ~mult_start_dly;
+    assign add_start_edge  = add_start  & ~add_start_dly;
 
     //----------------------------------------------------------------
     // Concurrent connectivity for ports etc.
diff --git a/src/ecc/rtl/ecc_montgomerymultiplier.sv b/src/ecc/rtl/ecc_montgomerymultiplier.sv
index df0fb79a2..db767af83 100644
--- a/src/ecc/rtl/ecc_montgomerymultiplier.sv
+++ b/src/ecc/rtl/ecc_montgomerymultiplier.sv
@@ -100,6 +100,7 @@ module ecc_montgomerymultiplier #(
     logic   [RADIX-1 : 0]             last_s_reg;
     logic   [FULL_REG_SIZE-1:0]       p_internal;
     logic   [FULL_REG_SIZE-1:0]       p_subtracted_internal;
+    logic                             last_reduction;
 
     //----------------------------------------------------------------
     // Processing elements (PEs)
@@ -291,8 +292,15 @@ module ecc_montgomerymultiplier #(
                 always_comb sub_b_i[t1] = 1;
             else
                 always_comb sub_b_i[t1] = sub_b_o[t1 - 1];
-                
-            always_comb sub_b_o[t1] = sub_res[t1][RADIX];
+            
+            always_ff @(posedge clk or negedge reset_n) begin
+                if (~reset_n)
+                    sub_b_o[t1] <= '0;
+                else if (zeroize)
+                    sub_b_o[t1] <= '0;
+                else
+                    sub_b_o[t1] <= sub_res[t1][RADIX];
+            end
         end
     endgenerate
 
@@ -337,7 +345,8 @@ module ecc_montgomerymultiplier #(
         end
     endgenerate
 
-    assign p_o = (sub_b_o[2*(PE_UNITS+1)])? p_subtracted_internal[REG_SIZE-1:0] : p_internal[REG_SIZE-1:0];
+    always_comb last_reduction = (sub_b_o[2*(PE_UNITS+1)]);
+    assign p_o = (last_reduction)? p_subtracted_internal[REG_SIZE-1:0] : p_internal[REG_SIZE-1:0];
 
     // Determines when results are ready based on S_NUM
     always_ff @(posedge clk or negedge reset_n) begin
diff --git a/src/ecc/rtl/ecc_params_pkg.sv b/src/ecc/rtl/ecc_params_pkg.sv
index 04112fed8..4838971af 100644
--- a/src/ecc/rtl/ecc_params_pkg.sv
+++ b/src/ecc/rtl/ecc_params_pkg.sv
@@ -53,6 +53,7 @@ package ecc_params_pkg;
   parameter [REG_SIZE-1 : 0] ZERO_CONST  = 384'h0;
   parameter [REG_SIZE-1 : 0] ONE_CONST   = 384'h1;
   parameter [REG_SIZE-1 : 0] E_a_MONT    = 384'hfffffffffffffffffffffffffffffffffffffffffffffffffffffffcfffffffbffffffff00000002fffffffdffffffff;
+  parameter [REG_SIZE-1 : 0] E_b_MONT    = 384'h604fbff9b62b21f41f022094e3374bee94938ae277f2209b1920022fc431bf244754443708118870d0391c81cd08114b;
   parameter [REG_SIZE-1 : 0] E_3b_MONT   = 384'h20ef3fed228165dc5d0661bea9a5e3cbbdbaa0a767d661d14b60068f4c953d6dd5fccca61834995270ab5584671833e2;
   parameter [REG_SIZE-1 : 0] ONE_p_MONT  = 384'h100000000ffffffffffffffff0000000100000000;
   parameter [REG_SIZE-1 : 0] R2_p_MONT   = 384'h10000000200000000fffffffe000000000000000200000000fffffffe000000010000000000000000;
diff --git a/src/ecc/rtl/ecc_pm_ctrl.sv b/src/ecc/rtl/ecc_pm_ctrl.sv
index 94776280f..0593c5f65 100644
--- a/src/ecc/rtl/ecc_pm_ctrl.sv
+++ b/src/ecc/rtl/ecc_pm_ctrl.sv
@@ -65,7 +65,7 @@ module ecc_pm_ctrl
     //----------------------------------------------------------------
     // Internal constant and parameter definitions.
     //----------------------------------------------------------------
-    localparam [7 : 0] MULT_DELAY          = 8'd38; //39 -1;
+    localparam [7 : 0] MULT_DELAY          = 8'd39; //40 -1;
     localparam [7 : 0] ADD_DELAY           = 8'd1;  // 2 -1;
     
     localparam [9 : 0] Secp384_SCA_MONT_COUNT   = REG_SIZE[9 : 0] + RND_SIZE[9 : 0];
@@ -189,6 +189,10 @@ module ecc_pm_ctrl
                                 prog_cntr <= VER1_ST_S;
                             end
 
+                            CHK_PK_CMD : begin
+                                prog_cntr <= CHK_PK_S;
+                            end
+
                             default : 
                                 prog_cntr <= NOP;
                         endcase
@@ -269,6 +273,10 @@ module ecc_pm_ctrl
                         prog_cntr <= NOP;
                     end
 
+                    CHK_PK_E: begin // End of public key validation before verifying process
+                        prog_cntr <= NOP;
+                    end
+
                     VER0_P0_E : begin // End of verfying part 0 to convert inputs to Mont domain
                         prog_cntr <= INVq_S;
                     end
diff --git a/src/ecc/rtl/ecc_pm_sequencer.sv b/src/ecc/rtl/ecc_pm_sequencer.sv
index c9f178158..d4d758d9e 100644
--- a/src/ecc/rtl/ecc_pm_sequencer.sv
+++ b/src/ecc/rtl/ecc_pm_sequencer.sv
@@ -26,7 +26,8 @@
 // 3) All modular operations are performed in Montgomery domain.
 //    mod p are modular operation respect to PRIME of SECP384 curve.
 //    mod q are modular operation respect to GROUP ORDER of SECP384 curve.
-// 
+// 4) To validate the given public key, we compare YY = Y^2 with 
+//    RHS = X^3 + A X + B.
 //
 //======================================================================
 
@@ -2397,6 +2398,30 @@ module ecc_pm_sequencer
                     SIGN1_S+ 10   : douta <= {UOP_NOP,        UOP_OPR_DONTCARE,   UOP_OPR_DONTCARE};
                     SIGN1_S+ 11   : douta <= {UOP_NOP,        UOP_OPR_DONTCARE,   UOP_OPR_DONTCARE};
 
+                    // check the given public key is a valid curve point
+                    CHK_PK_S       : douta <= {UOP_DO_MUL_p,   UOP_OPR_Qy_AFFN,   UOP_OPR_CONST_R2_p};  // A = mm(Qy, R2) % q
+                    CHK_PK_S+ 1    : douta <= {UOP_ST_MUL_p,   UOP_OPR_DONTCARE,  UOP_OPR_A};
+                    CHK_PK_S+ 2    : douta <= {UOP_DO_MUL_p,   UOP_OPR_A,         UOP_OPR_A};           // A = A*A % q
+                    CHK_PK_S+ 3    : douta <= {UOP_ST_MUL_p,   UOP_OPR_DONTCARE,  UOP_OPR_A};
+                    CHK_PK_S+ 4    : douta <= {UOP_DO_MUL_p,   UOP_OPR_Qx_AFFN,   UOP_OPR_CONST_R2_p};  // B = mm(Qx, R2) % q
+                    CHK_PK_S+ 5    : douta <= {UOP_ST_MUL_p,   UOP_OPR_DONTCARE,  UOP_OPR_B};
+                    CHK_PK_S+ 6    : douta <= {UOP_DO_MUL_p,   UOP_OPR_B,         UOP_OPR_B};           // C = B*B % q
+                    CHK_PK_S+ 7    : douta <= {UOP_ST_MUL_p,   UOP_OPR_DONTCARE,  UOP_OPR_C};
+                    CHK_PK_S+ 8    : douta <= {UOP_DO_MUL_p,   UOP_OPR_C,         UOP_OPR_B};           // C = C*B % q
+                    CHK_PK_S+ 9    : douta <= {UOP_ST_MUL_p,   UOP_OPR_DONTCARE,  UOP_OPR_C};
+                    CHK_PK_S+ 10   : douta <= {UOP_DO_MUL_p,   UOP_OPR_CONST_E_a, UOP_OPR_B};           // D = ECC.a*B % q
+                    CHK_PK_S+ 11   : douta <= {UOP_ST_MUL_p,   UOP_OPR_DONTCARE,  UOP_OPR_D};
+                    CHK_PK_S+ 12   : douta <= {UOP_DO_ADD_p,   UOP_OPR_C,         UOP_OPR_D};           // C = C + D % q
+                    CHK_PK_S+ 13   : douta <= {UOP_ST_ADD_p,   UOP_OPR_C,         UOP_OPR_DONTCARE};
+                    CHK_PK_S+ 14   : douta <= {UOP_DO_ADD_p,   UOP_OPR_C,         UOP_OPR_CONST_E_b};   // C = C + ECC.b % q
+                    CHK_PK_S+ 15   : douta <= {UOP_ST_ADD_p,   UOP_OPR_C,         UOP_OPR_DONTCARE};
+                    CHK_PK_S+ 16   : douta <= {UOP_DO_SUB_p,   UOP_OPR_A,         UOP_OPR_C};           // C = C + ECC.b % q
+                    CHK_PK_S+ 17   : douta <= {UOP_ST_ADD_p,   UOP_OPR_PK_VALID,  UOP_OPR_DONTCARE};
+                    CHK_PK_S+ 18   : douta <= {UOP_NOP,        UOP_OPR_DONTCARE,  UOP_OPR_DONTCARE};
+                    CHK_PK_S+ 19   : douta <= {UOP_NOP,        UOP_OPR_DONTCARE,  UOP_OPR_DONTCARE};
+                    CHK_PK_S+ 20   : douta <= {UOP_NOP,        UOP_OPR_DONTCARE,  UOP_OPR_DONTCARE};
+                    CHK_PK_S+ 21   : douta <= {UOP_NOP,        UOP_OPR_DONTCARE,  UOP_OPR_DONTCARE};
+    
                     // VERIFY0 SCALAR part0 to convert inputs to Mont domain
                     VER0_P0_S     : douta <= {UOP_DO_MUL_q,   UOP_OPR_HASH_MSG,   UOP_OPR_CONST_R2_q};    // A = mm(h, R2) % q
                     VER0_P0_S+ 1  : douta <= {UOP_ST_MUL_q,   UOP_OPR_DONTCARE,   UOP_OPR_A};
diff --git a/src/ecc/rtl/ecc_pm_uop_pkg.sv b/src/ecc/rtl/ecc_pm_uop_pkg.sv
index c006f33c1..7f8646c4a 100644
--- a/src/ecc/rtl/ecc_pm_uop_pkg.sv
+++ b/src/ecc/rtl/ecc_pm_uop_pkg.sv
@@ -75,8 +75,8 @@ localparam [OPR_ADDR_WIDTH-1 : 0] UOP_OPR_CONST_R2_p        = 6'd5;
 localparam [OPR_ADDR_WIDTH-1 : 0] UOP_OPR_CONST_GX_MONT     = 6'd6;
 localparam [OPR_ADDR_WIDTH-1 : 0] UOP_OPR_CONST_GY_MONT     = 6'd7;
 
-localparam [OPR_ADDR_WIDTH-1 : 0] UOP_OPR_R0_X              = 6'd8;  // 8'b0000_1000;
-localparam [OPR_ADDR_WIDTH-1 : 0] UOP_OPR_R0_Y              = 6'd9;  // 8'b0000_1001;
+localparam [OPR_ADDR_WIDTH-1 : 0] UOP_OPR_R0_X              = 6'd8;   // 8'b0000_1000;
+localparam [OPR_ADDR_WIDTH-1 : 0] UOP_OPR_R0_Y              = 6'd9;   // 8'b0000_1001;
 localparam [OPR_ADDR_WIDTH-1 : 0] UOP_OPR_R0_Z              = 6'd10;  // 8'b0000_1010;
 
 localparam [OPR_ADDR_WIDTH-1 : 0] UOP_OPR_R1_X              = 6'd12;  // 8'b0000_1100;
@@ -129,12 +129,16 @@ localparam [OPR_ADDR_WIDTH-1 : 0] UOP_OPR_P1_X_MONT         = 6'd53;
 localparam [OPR_ADDR_WIDTH-1 : 0] UOP_OPR_P1_Y_MONT         = 6'd54;
 localparam [OPR_ADDR_WIDTH-1 : 0] UOP_OPR_P1_Z_MONT         = 6'd55;
 
+localparam [OPR_ADDR_WIDTH-1 : 0] UOP_OPR_CONST_E_b         = 6'd56;
+localparam [OPR_ADDR_WIDTH-1 : 0] UOP_OPR_PK_VALID          = 6'd57;
+
 //PM command listing
 localparam [2 : 0] KEYGEN_CMD           = 3'b001;
 localparam [2 : 0] SIGN_CMD             = 3'b010;
 localparam [2 : 0] VER_PART0_CMD        = 3'b100;    
 localparam [2 : 0] VER_PART1_CMD        = 3'b101;    
-localparam [2 : 0] VER_PART2_CMD        = 3'b110;    
+localparam [2 : 0] VER_PART2_CMD        = 3'b110;
+localparam [2 : 0] CHK_PK_CMD           = 3'b111;
 
 //PM Subroutine listing
 localparam [PROG_ADDR_W-1 : 0] NOP                  = 12'd0;
@@ -158,7 +162,9 @@ localparam [PROG_ADDR_W-1 : 0] INVq_E               = INVq_S + 1043;
 localparam [PROG_ADDR_W-1 : 0] SIGN1_S              = INVq_E + 2;     // signing proof r part1
 localparam [PROG_ADDR_W-1 : 0] SIGN1_E              = SIGN1_S + 11;
 
-localparam [PROG_ADDR_W-1 : 0] VER0_P0_S            = SIGN1_E + 2;    // verifying0 part0 to convert inputs to Mont domain
+localparam [PROG_ADDR_W-1 : 0] CHK_PK_S             = SIGN1_E + 2;    // check the given public key is a valid curve point
+localparam [PROG_ADDR_W-1 : 0] CHK_PK_E             = CHK_PK_S + 21;
+localparam [PROG_ADDR_W-1 : 0] VER0_P0_S            = CHK_PK_E + 2;   // verifying0 part0 to convert inputs to Mont domain
 localparam [PROG_ADDR_W-1 : 0] VER0_P0_E            = VER0_P0_S + 9;
 localparam [PROG_ADDR_W-1 : 0] VER0_P1_S            = VER0_P0_E + 2;  // verifying0 part1 to compute (h*s_inv) and (r*s_inv)
 localparam [PROG_ADDR_W-1 : 0] VER0_P1_E            = VER0_P1_S + 11;
diff --git a/src/ecc/rtl/ecc_reg.rdl b/src/ecc/rtl/ecc_reg.rdl
index 09332d1b1..4446bf8fa 100644
--- a/src/ecc/rtl/ecc_reg.rdl
+++ b/src/ecc/rtl/ecc_reg.rdl
@@ -81,7 +81,7 @@ addrmap ecc_reg {
         default hw = r;
         default resetsignal = reset_b;
         field {desc = "Control command field"; swwe = ecc_ready; hwclr;} CTRL[2] = 2'b0;
-        field {desc = "Zeroize all internal registers"; swwe = ecc_ready; singlepulse;} ZEROIZE = 1'b0;
+        field {desc = "Zeroize all internal registers"; singlepulse;} ZEROIZE = 1'b0;
         field {desc = "Run PCR Signing flow"; swwe = ecc_ready; hwclr;} PCR_SIGN = 1'b0;
     
     } ECC_CTRL @0x00000010;
diff --git a/src/ecc/rtl/ecc_reg.sv b/src/ecc/rtl/ecc_reg.sv
index d40d0106d..212ad6d15 100644
--- a/src/ecc/rtl/ecc_reg.sv
+++ b/src/ecc/rtl/ecc_reg.sv
@@ -682,7 +682,7 @@ module ecc_reg (
     always_comb begin
         automatic logic [0:0] next_c = field_storage.ECC_CTRL.ZEROIZE.value;
         automatic logic load_next_c = '0;
-        if(decoded_reg_strb.ECC_CTRL && decoded_req_is_wr && hwif_in.ecc_ready) begin // SW write
+        if(decoded_reg_strb.ECC_CTRL && decoded_req_is_wr) begin // SW write
             next_c = (field_storage.ECC_CTRL.ZEROIZE.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]);
             load_next_c = '1;
         end else if(1) begin // singlepulse clears back to 0
diff --git a/src/ecc/rtl/ecc_reg_uvm.sv b/src/ecc/rtl/ecc_reg_uvm.sv
index 4f037836b..2e574c8c6 100644
--- a/src/ecc/rtl/ecc_reg_uvm.sv
+++ b/src/ecc/rtl/ecc_reg_uvm.sv
@@ -3,44 +3,89 @@
 package ecc_reg_uvm;
     `include "uvm_macros.svh"
     import uvm_pkg::*;
-    
+    `include "ecc_reg_covergroups.svh"
     // Reg - ecc_reg::ECC_NAME
     class ecc_reg__ECC_NAME extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        ecc_reg__ECC_NAME_bit_cg NAME_bit_cg[32];
+        ecc_reg__ECC_NAME_fld_cg fld_cg;
         rand uvm_reg_field NAME;
 
         function new(string name = "ecc_reg__ECC_NAME");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.NAME = new("NAME");
             this.NAME.configure(this, 32, 0, "RO", 1, 'h0, 0, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(NAME_bit_cg[bt]) NAME_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : ecc_reg__ECC_NAME
 
     // Reg - ecc_reg::ECC_VERSION
     class ecc_reg__ECC_VERSION extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        ecc_reg__ECC_VERSION_bit_cg VERSION_bit_cg[32];
+        ecc_reg__ECC_VERSION_fld_cg fld_cg;
         rand uvm_reg_field VERSION;
 
         function new(string name = "ecc_reg__ECC_VERSION");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.VERSION = new("VERSION");
             this.VERSION.configure(this, 32, 0, "RO", 1, 'h0, 0, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(VERSION_bit_cg[bt]) VERSION_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : ecc_reg__ECC_VERSION
 
     // Reg - ecc_reg::ECC_CTRL
     class ecc_reg__ECC_CTRL extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        ecc_reg__ECC_CTRL_bit_cg CTRL_bit_cg[2];
+        ecc_reg__ECC_CTRL_bit_cg ZEROIZE_bit_cg[1];
+        ecc_reg__ECC_CTRL_bit_cg PCR_SIGN_bit_cg[1];
+        ecc_reg__ECC_CTRL_fld_cg fld_cg;
         rand uvm_reg_field CTRL;
         rand uvm_reg_field ZEROIZE;
         rand uvm_reg_field PCR_SIGN;
 
         function new(string name = "ecc_reg__ECC_CTRL");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.CTRL = new("CTRL");
@@ -49,190 +94,405 @@ package ecc_reg_uvm;
             this.ZEROIZE.configure(this, 1, 2, "WO", 0, 'h0, 1, 1, 0);
             this.PCR_SIGN = new("PCR_SIGN");
             this.PCR_SIGN.configure(this, 1, 3, "WO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(CTRL_bit_cg[bt]) CTRL_bit_cg[bt] = new();
+                foreach(ZEROIZE_bit_cg[bt]) ZEROIZE_bit_cg[bt] = new();
+                foreach(PCR_SIGN_bit_cg[bt]) PCR_SIGN_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : ecc_reg__ECC_CTRL
 
     // Reg - ecc_reg::ECC_STATUS
     class ecc_reg__ECC_STATUS extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        ecc_reg__ECC_STATUS_bit_cg READY_bit_cg[1];
+        ecc_reg__ECC_STATUS_bit_cg VALID_bit_cg[1];
+        ecc_reg__ECC_STATUS_fld_cg fld_cg;
         rand uvm_reg_field READY;
         rand uvm_reg_field VALID;
 
         function new(string name = "ecc_reg__ECC_STATUS");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.READY = new("READY");
             this.READY.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
             this.VALID = new("VALID");
             this.VALID.configure(this, 1, 1, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(READY_bit_cg[bt]) READY_bit_cg[bt] = new();
+                foreach(VALID_bit_cg[bt]) VALID_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : ecc_reg__ECC_STATUS
 
     // Reg - ecc_reg::ECC_SEED
     class ecc_reg__ECC_SEED extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        ecc_reg__ECC_SEED_bit_cg SEED_bit_cg[32];
+        ecc_reg__ECC_SEED_fld_cg fld_cg;
         rand uvm_reg_field SEED;
 
         function new(string name = "ecc_reg__ECC_SEED");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.SEED = new("SEED");
             this.SEED.configure(this, 32, 0, "WO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(SEED_bit_cg[bt]) SEED_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : ecc_reg__ECC_SEED
 
     // Reg - ecc_reg::ECC_MSG
     class ecc_reg__ECC_MSG extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        ecc_reg__ECC_MSG_bit_cg MSG_bit_cg[32];
+        ecc_reg__ECC_MSG_fld_cg fld_cg;
         rand uvm_reg_field MSG;
 
         function new(string name = "ecc_reg__ECC_MSG");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.MSG = new("MSG");
             this.MSG.configure(this, 32, 0, "WO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(MSG_bit_cg[bt]) MSG_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : ecc_reg__ECC_MSG
 
     // Reg - ecc_reg::ECC_PRIVKEY_OUT
     class ecc_reg__ECC_PRIVKEY_OUT extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        ecc_reg__ECC_PRIVKEY_OUT_bit_cg PRIVKEY_OUT_bit_cg[32];
+        ecc_reg__ECC_PRIVKEY_OUT_fld_cg fld_cg;
         rand uvm_reg_field PRIVKEY_OUT;
 
         function new(string name = "ecc_reg__ECC_PRIVKEY_OUT");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.PRIVKEY_OUT = new("PRIVKEY_OUT");
             this.PRIVKEY_OUT.configure(this, 32, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(PRIVKEY_OUT_bit_cg[bt]) PRIVKEY_OUT_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : ecc_reg__ECC_PRIVKEY_OUT
 
     // Reg - ecc_reg::ECC_PUBKEY_X
     class ecc_reg__ECC_PUBKEY_X extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        ecc_reg__ECC_PUBKEY_X_bit_cg PUBKEY_X_bit_cg[32];
+        ecc_reg__ECC_PUBKEY_X_fld_cg fld_cg;
         rand uvm_reg_field PUBKEY_X;
 
         function new(string name = "ecc_reg__ECC_PUBKEY_X");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.PUBKEY_X = new("PUBKEY_X");
             this.PUBKEY_X.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(PUBKEY_X_bit_cg[bt]) PUBKEY_X_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : ecc_reg__ECC_PUBKEY_X
 
     // Reg - ecc_reg::ECC_PUBKEY_Y
     class ecc_reg__ECC_PUBKEY_Y extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        ecc_reg__ECC_PUBKEY_Y_bit_cg PUBKEY_Y_bit_cg[32];
+        ecc_reg__ECC_PUBKEY_Y_fld_cg fld_cg;
         rand uvm_reg_field PUBKEY_Y;
 
         function new(string name = "ecc_reg__ECC_PUBKEY_Y");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.PUBKEY_Y = new("PUBKEY_Y");
             this.PUBKEY_Y.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(PUBKEY_Y_bit_cg[bt]) PUBKEY_Y_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : ecc_reg__ECC_PUBKEY_Y
 
     // Reg - ecc_reg::ECC_SIGN_R
     class ecc_reg__ECC_SIGN_R extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        ecc_reg__ECC_SIGN_R_bit_cg SIGN_R_bit_cg[32];
+        ecc_reg__ECC_SIGN_R_fld_cg fld_cg;
         rand uvm_reg_field SIGN_R;
 
         function new(string name = "ecc_reg__ECC_SIGN_R");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.SIGN_R = new("SIGN_R");
             this.SIGN_R.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(SIGN_R_bit_cg[bt]) SIGN_R_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : ecc_reg__ECC_SIGN_R
 
     // Reg - ecc_reg::ECC_SIGN_S
     class ecc_reg__ECC_SIGN_S extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        ecc_reg__ECC_SIGN_S_bit_cg SIGN_S_bit_cg[32];
+        ecc_reg__ECC_SIGN_S_fld_cg fld_cg;
         rand uvm_reg_field SIGN_S;
 
         function new(string name = "ecc_reg__ECC_SIGN_S");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.SIGN_S = new("SIGN_S");
             this.SIGN_S.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(SIGN_S_bit_cg[bt]) SIGN_S_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : ecc_reg__ECC_SIGN_S
 
     // Reg - ecc_reg::ECC_VERIFY_R
     class ecc_reg__ECC_VERIFY_R extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        ecc_reg__ECC_VERIFY_R_bit_cg VERIFY_R_bit_cg[32];
+        ecc_reg__ECC_VERIFY_R_fld_cg fld_cg;
         rand uvm_reg_field VERIFY_R;
 
         function new(string name = "ecc_reg__ECC_VERIFY_R");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.VERIFY_R = new("VERIFY_R");
             this.VERIFY_R.configure(this, 32, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(VERIFY_R_bit_cg[bt]) VERIFY_R_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : ecc_reg__ECC_VERIFY_R
 
     // Reg - ecc_reg::ECC_IV
     class ecc_reg__ECC_IV extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        ecc_reg__ECC_IV_bit_cg IV_bit_cg[32];
+        ecc_reg__ECC_IV_fld_cg fld_cg;
         rand uvm_reg_field IV;
 
         function new(string name = "ecc_reg__ECC_IV");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.IV = new("IV");
             this.IV.configure(this, 32, 0, "WO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(IV_bit_cg[bt]) IV_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : ecc_reg__ECC_IV
 
     // Reg - ecc_reg::ECC_NONCE
     class ecc_reg__ECC_NONCE extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        ecc_reg__ECC_NONCE_bit_cg NONCE_bit_cg[32];
+        ecc_reg__ECC_NONCE_fld_cg fld_cg;
         rand uvm_reg_field NONCE;
 
         function new(string name = "ecc_reg__ECC_NONCE");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.NONCE = new("NONCE");
             this.NONCE.configure(this, 32, 0, "WO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(NONCE_bit_cg[bt]) NONCE_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : ecc_reg__ECC_NONCE
 
     // Reg - ecc_reg::ECC_PRIVKEY_IN
     class ecc_reg__ECC_PRIVKEY_IN extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        ecc_reg__ECC_PRIVKEY_IN_bit_cg PRIVKEY_IN_bit_cg[32];
+        ecc_reg__ECC_PRIVKEY_IN_fld_cg fld_cg;
         rand uvm_reg_field PRIVKEY_IN;
 
         function new(string name = "ecc_reg__ECC_PRIVKEY_IN");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.PRIVKEY_IN = new("PRIVKEY_IN");
             this.PRIVKEY_IN.configure(this, 32, 0, "WO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(PRIVKEY_IN_bit_cg[bt]) PRIVKEY_IN_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : ecc_reg__ECC_PRIVKEY_IN
 
     // Reg - kv_read_ctrl_reg
     class kv_read_ctrl_reg extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        kv_read_ctrl_reg_bit_cg read_en_bit_cg[1];
+        kv_read_ctrl_reg_bit_cg read_entry_bit_cg[5];
+        kv_read_ctrl_reg_bit_cg pcr_hash_extend_bit_cg[1];
+        kv_read_ctrl_reg_bit_cg rsvd_bit_cg[25];
+        kv_read_ctrl_reg_fld_cg fld_cg;
         rand uvm_reg_field read_en;
         rand uvm_reg_field read_entry;
         rand uvm_reg_field pcr_hash_extend;
         rand uvm_reg_field rsvd;
 
         function new(string name = "kv_read_ctrl_reg");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.read_en = new("read_en");
@@ -243,18 +503,39 @@ package ecc_reg_uvm;
             this.pcr_hash_extend.configure(this, 1, 6, "RW", 0, 'h0, 1, 1, 0);
             this.rsvd = new("rsvd");
             this.rsvd.configure(this, 25, 7, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(read_en_bit_cg[bt]) read_en_bit_cg[bt] = new();
+                foreach(read_entry_bit_cg[bt]) read_entry_bit_cg[bt] = new();
+                foreach(pcr_hash_extend_bit_cg[bt]) pcr_hash_extend_bit_cg[bt] = new();
+                foreach(rsvd_bit_cg[bt]) rsvd_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : kv_read_ctrl_reg
 
     // Reg - kv_status_reg
     class kv_status_reg extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        kv_status_reg_bit_cg READY_bit_cg[1];
+        kv_status_reg_bit_cg VALID_bit_cg[1];
+        kv_status_reg_bit_cg ERROR_bit_cg[8];
+        kv_status_reg_fld_cg fld_cg;
         rand uvm_reg_field READY;
         rand uvm_reg_field VALID;
         rand uvm_reg_field ERROR;
 
         function new(string name = "kv_status_reg");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.READY = new("READY");
@@ -263,11 +544,31 @@ package ecc_reg_uvm;
             this.VALID.configure(this, 1, 1, "RO", 1, 'h0, 1, 1, 0);
             this.ERROR = new("ERROR");
             this.ERROR.configure(this, 8, 2, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(READY_bit_cg[bt]) READY_bit_cg[bt] = new();
+                foreach(VALID_bit_cg[bt]) VALID_bit_cg[bt] = new();
+                foreach(ERROR_bit_cg[bt]) ERROR_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : kv_status_reg
 
     // Reg - kv_write_ctrl_reg
     class kv_write_ctrl_reg extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        kv_write_ctrl_reg_bit_cg write_en_bit_cg[1];
+        kv_write_ctrl_reg_bit_cg write_entry_bit_cg[5];
+        kv_write_ctrl_reg_bit_cg hmac_key_dest_valid_bit_cg[1];
+        kv_write_ctrl_reg_bit_cg hmac_block_dest_valid_bit_cg[1];
+        kv_write_ctrl_reg_bit_cg sha_block_dest_valid_bit_cg[1];
+        kv_write_ctrl_reg_bit_cg ecc_pkey_dest_valid_bit_cg[1];
+        kv_write_ctrl_reg_bit_cg ecc_seed_dest_valid_bit_cg[1];
+        kv_write_ctrl_reg_bit_cg rsvd_bit_cg[21];
+        kv_write_ctrl_reg_fld_cg fld_cg;
         rand uvm_reg_field write_en;
         rand uvm_reg_field write_entry;
         rand uvm_reg_field hmac_key_dest_valid;
@@ -278,8 +579,13 @@ package ecc_reg_uvm;
         rand uvm_reg_field rsvd;
 
         function new(string name = "kv_write_ctrl_reg");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.write_en = new("write_en");
@@ -298,191 +604,413 @@ package ecc_reg_uvm;
             this.ecc_seed_dest_valid.configure(this, 1, 10, "RW", 0, 'h0, 1, 1, 0);
             this.rsvd = new("rsvd");
             this.rsvd.configure(this, 21, 11, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(write_en_bit_cg[bt]) write_en_bit_cg[bt] = new();
+                foreach(write_entry_bit_cg[bt]) write_entry_bit_cg[bt] = new();
+                foreach(hmac_key_dest_valid_bit_cg[bt]) hmac_key_dest_valid_bit_cg[bt] = new();
+                foreach(hmac_block_dest_valid_bit_cg[bt]) hmac_block_dest_valid_bit_cg[bt] = new();
+                foreach(sha_block_dest_valid_bit_cg[bt]) sha_block_dest_valid_bit_cg[bt] = new();
+                foreach(ecc_pkey_dest_valid_bit_cg[bt]) ecc_pkey_dest_valid_bit_cg[bt] = new();
+                foreach(ecc_seed_dest_valid_bit_cg[bt]) ecc_seed_dest_valid_bit_cg[bt] = new();
+                foreach(rsvd_bit_cg[bt]) rsvd_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : kv_write_ctrl_reg
 
     // Reg - ecc_reg::intr_block_t::global_intr_en_t
     class ecc_reg__intr_block_t__global_intr_en_t extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        ecc_reg__intr_block_t__global_intr_en_t_bit_cg error_en_bit_cg[1];
+        ecc_reg__intr_block_t__global_intr_en_t_bit_cg notif_en_bit_cg[1];
+        ecc_reg__intr_block_t__global_intr_en_t_fld_cg fld_cg;
         rand uvm_reg_field error_en;
         rand uvm_reg_field notif_en;
 
         function new(string name = "ecc_reg__intr_block_t__global_intr_en_t");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.error_en = new("error_en");
             this.error_en.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
             this.notif_en = new("notif_en");
             this.notif_en.configure(this, 1, 1, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(error_en_bit_cg[bt]) error_en_bit_cg[bt] = new();
+                foreach(notif_en_bit_cg[bt]) notif_en_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : ecc_reg__intr_block_t__global_intr_en_t
 
     // Reg - ecc_reg::intr_block_t::error_intr_en_t
     class ecc_reg__intr_block_t__error_intr_en_t extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        ecc_reg__intr_block_t__error_intr_en_t_bit_cg error_internal_en_bit_cg[1];
+        ecc_reg__intr_block_t__error_intr_en_t_fld_cg fld_cg;
         rand uvm_reg_field error_internal_en;
 
         function new(string name = "ecc_reg__intr_block_t__error_intr_en_t");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.error_internal_en = new("error_internal_en");
             this.error_internal_en.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(error_internal_en_bit_cg[bt]) error_internal_en_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : ecc_reg__intr_block_t__error_intr_en_t
 
     // Reg - ecc_reg::intr_block_t::notif_intr_en_t
     class ecc_reg__intr_block_t__notif_intr_en_t extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        ecc_reg__intr_block_t__notif_intr_en_t_bit_cg notif_cmd_done_en_bit_cg[1];
+        ecc_reg__intr_block_t__notif_intr_en_t_fld_cg fld_cg;
         rand uvm_reg_field notif_cmd_done_en;
 
         function new(string name = "ecc_reg__intr_block_t__notif_intr_en_t");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.notif_cmd_done_en = new("notif_cmd_done_en");
             this.notif_cmd_done_en.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(notif_cmd_done_en_bit_cg[bt]) notif_cmd_done_en_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : ecc_reg__intr_block_t__notif_intr_en_t
 
     // Reg - ecc_reg::intr_block_t::global_intr_t_agg_sts_dd3dcf0a
     class ecc_reg__intr_block_t__global_intr_t_agg_sts_dd3dcf0a extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        ecc_reg__intr_block_t__global_intr_t_agg_sts_dd3dcf0a_bit_cg agg_sts_bit_cg[1];
+        ecc_reg__intr_block_t__global_intr_t_agg_sts_dd3dcf0a_fld_cg fld_cg;
         rand uvm_reg_field agg_sts;
 
         function new(string name = "ecc_reg__intr_block_t__global_intr_t_agg_sts_dd3dcf0a");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.agg_sts = new("agg_sts");
             this.agg_sts.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(agg_sts_bit_cg[bt]) agg_sts_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : ecc_reg__intr_block_t__global_intr_t_agg_sts_dd3dcf0a
 
     // Reg - ecc_reg::intr_block_t::global_intr_t_agg_sts_e6399b4a
     class ecc_reg__intr_block_t__global_intr_t_agg_sts_e6399b4a extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        ecc_reg__intr_block_t__global_intr_t_agg_sts_e6399b4a_bit_cg agg_sts_bit_cg[1];
+        ecc_reg__intr_block_t__global_intr_t_agg_sts_e6399b4a_fld_cg fld_cg;
         rand uvm_reg_field agg_sts;
 
         function new(string name = "ecc_reg__intr_block_t__global_intr_t_agg_sts_e6399b4a");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.agg_sts = new("agg_sts");
             this.agg_sts.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(agg_sts_bit_cg[bt]) agg_sts_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : ecc_reg__intr_block_t__global_intr_t_agg_sts_e6399b4a
 
     // Reg - ecc_reg::intr_block_t::error_intr_t_error_internal_sts_83adab02
     class ecc_reg__intr_block_t__error_intr_t_error_internal_sts_83adab02 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        ecc_reg__intr_block_t__error_intr_t_error_internal_sts_83adab02_bit_cg error_internal_sts_bit_cg[1];
+        ecc_reg__intr_block_t__error_intr_t_error_internal_sts_83adab02_fld_cg fld_cg;
         rand uvm_reg_field error_internal_sts;
 
         function new(string name = "ecc_reg__intr_block_t__error_intr_t_error_internal_sts_83adab02");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.error_internal_sts = new("error_internal_sts");
             this.error_internal_sts.configure(this, 1, 0, "W1C", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(error_internal_sts_bit_cg[bt]) error_internal_sts_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : ecc_reg__intr_block_t__error_intr_t_error_internal_sts_83adab02
 
     // Reg - ecc_reg::intr_block_t::notif_intr_t_notif_cmd_done_sts_1c68637e
     class ecc_reg__intr_block_t__notif_intr_t_notif_cmd_done_sts_1c68637e extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        ecc_reg__intr_block_t__notif_intr_t_notif_cmd_done_sts_1c68637e_bit_cg notif_cmd_done_sts_bit_cg[1];
+        ecc_reg__intr_block_t__notif_intr_t_notif_cmd_done_sts_1c68637e_fld_cg fld_cg;
         rand uvm_reg_field notif_cmd_done_sts;
 
         function new(string name = "ecc_reg__intr_block_t__notif_intr_t_notif_cmd_done_sts_1c68637e");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.notif_cmd_done_sts = new("notif_cmd_done_sts");
             this.notif_cmd_done_sts.configure(this, 1, 0, "W1C", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(notif_cmd_done_sts_bit_cg[bt]) notif_cmd_done_sts_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : ecc_reg__intr_block_t__notif_intr_t_notif_cmd_done_sts_1c68637e
 
     // Reg - ecc_reg::intr_block_t::error_intr_trig_t
     class ecc_reg__intr_block_t__error_intr_trig_t extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        ecc_reg__intr_block_t__error_intr_trig_t_bit_cg error_internal_trig_bit_cg[1];
+        ecc_reg__intr_block_t__error_intr_trig_t_fld_cg fld_cg;
         rand uvm_reg_field error_internal_trig;
 
         function new(string name = "ecc_reg__intr_block_t__error_intr_trig_t");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.error_internal_trig = new("error_internal_trig");
             this.error_internal_trig.configure(this, 1, 0, "W1S", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(error_internal_trig_bit_cg[bt]) error_internal_trig_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : ecc_reg__intr_block_t__error_intr_trig_t
 
     // Reg - ecc_reg::intr_block_t::notif_intr_trig_t
     class ecc_reg__intr_block_t__notif_intr_trig_t extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        ecc_reg__intr_block_t__notif_intr_trig_t_bit_cg notif_cmd_done_trig_bit_cg[1];
+        ecc_reg__intr_block_t__notif_intr_trig_t_fld_cg fld_cg;
         rand uvm_reg_field notif_cmd_done_trig;
 
         function new(string name = "ecc_reg__intr_block_t__notif_intr_trig_t");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.notif_cmd_done_trig = new("notif_cmd_done_trig");
             this.notif_cmd_done_trig.configure(this, 1, 0, "W1S", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(notif_cmd_done_trig_bit_cg[bt]) notif_cmd_done_trig_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : ecc_reg__intr_block_t__notif_intr_trig_t
 
     // Reg - ecc_reg::intr_block_t::intr_count_t_cnt_60ddff93
     class ecc_reg__intr_block_t__intr_count_t_cnt_60ddff93 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        ecc_reg__intr_block_t__intr_count_t_cnt_60ddff93_bit_cg cnt_bit_cg[32];
+        ecc_reg__intr_block_t__intr_count_t_cnt_60ddff93_fld_cg fld_cg;
         rand uvm_reg_field cnt;
 
         function new(string name = "ecc_reg__intr_block_t__intr_count_t_cnt_60ddff93");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.cnt = new("cnt");
             this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : ecc_reg__intr_block_t__intr_count_t_cnt_60ddff93
 
     // Reg - ecc_reg::intr_block_t::intr_count_t_cnt_be67d6d5
     class ecc_reg__intr_block_t__intr_count_t_cnt_be67d6d5 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        ecc_reg__intr_block_t__intr_count_t_cnt_be67d6d5_bit_cg cnt_bit_cg[32];
+        ecc_reg__intr_block_t__intr_count_t_cnt_be67d6d5_fld_cg fld_cg;
         rand uvm_reg_field cnt;
 
         function new(string name = "ecc_reg__intr_block_t__intr_count_t_cnt_be67d6d5");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.cnt = new("cnt");
             this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : ecc_reg__intr_block_t__intr_count_t_cnt_be67d6d5
 
     // Reg - ecc_reg::intr_block_t::intr_count_incr_t_pulse_15e6ed7e
     class ecc_reg__intr_block_t__intr_count_incr_t_pulse_15e6ed7e extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        ecc_reg__intr_block_t__intr_count_incr_t_pulse_15e6ed7e_bit_cg pulse_bit_cg[1];
+        ecc_reg__intr_block_t__intr_count_incr_t_pulse_15e6ed7e_fld_cg fld_cg;
         rand uvm_reg_field pulse;
 
         function new(string name = "ecc_reg__intr_block_t__intr_count_incr_t_pulse_15e6ed7e");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.pulse = new("pulse");
             this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : ecc_reg__intr_block_t__intr_count_incr_t_pulse_15e6ed7e
 
     // Reg - ecc_reg::intr_block_t::intr_count_incr_t_pulse_6173128e
     class ecc_reg__intr_block_t__intr_count_incr_t_pulse_6173128e extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        ecc_reg__intr_block_t__intr_count_incr_t_pulse_6173128e_bit_cg pulse_bit_cg[1];
+        ecc_reg__intr_block_t__intr_count_incr_t_pulse_6173128e_fld_cg fld_cg;
         rand uvm_reg_field pulse;
 
         function new(string name = "ecc_reg__intr_block_t__intr_count_incr_t_pulse_6173128e");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.pulse = new("pulse");
             this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : ecc_reg__intr_block_t__intr_count_incr_t_pulse_6173128e
 
@@ -745,4 +1273,5 @@ package ecc_reg_uvm;
         endfunction : build
     endclass : ecc_reg
 
+    `include "ecc_reg_sample.svh"
 endpackage: ecc_reg_uvm
diff --git a/src/ecc/rtl/ecc_top.sv b/src/ecc/rtl/ecc_top.sv
index a3333e100..b78ae1535 100644
--- a/src/ecc/rtl/ecc_top.sv
+++ b/src/ecc/rtl/ecc_top.sv
@@ -57,7 +57,8 @@ module ecc_top
     input pcr_signing_t pcr_signing_data,
 
     output logic error_intr,
-    output logic notif_intr
+    output logic notif_intr,
+    input  logic debugUnlock_or_scan_mode_switch
 );
 
     //gasket to assemble ecc request
@@ -148,7 +149,8 @@ module ecc_top
         .pcr_signing_data(pcr_signing_data),
         
         .error_intr(error_intr),
-        .notif_intr(notif_intr)
+        .notif_intr(notif_intr),
+        .debugUnlock_or_scan_mode_switch(debugUnlock_or_scan_mode_switch)
     );
 
 endmodule
diff --git a/src/ecc/tb/ecc_montgomerymultiplier_tb.sv b/src/ecc/tb/ecc_montgomerymultiplier_tb.sv
index eb11056c5..5fef6665d 100644
--- a/src/ecc/tb/ecc_montgomerymultiplier_tb.sv
+++ b/src/ecc/tb/ecc_montgomerymultiplier_tb.sv
@@ -22,9 +22,9 @@
 //======================================================================
 
 module ecc_montgomerymultiplier_tb #(
-    parameter   OPERAND_WIDTH = 384,
-    parameter   WORD_WIDTH = 32,
-    parameter   TEST_VECTOR_NUM = 102
+    parameter   OPERAND_WIDTH = 16,
+    parameter   WORD_WIDTH = 4,
+    parameter   TEST_VECTOR_NUM = 5
   )
   ();
 
@@ -91,6 +91,7 @@ module ecc_montgomerymultiplier_tb #(
   mm_dut (
       .clk        (clk_tb),
       .reset_n    (reset_n_tb),
+      .zeroize    (1'b0),
 
       .start_i    (start_i_tb),
       .opa_i      (opa_i_tb),
@@ -317,7 +318,8 @@ module ecc_montgomerymultiplier_tb #(
       $display("   -= Testbench for mm started =-");
       $display("    ==============================\n");
 
-      fname = $sformatf("/home/mojtabab/workspace_aha_poc/ws1/Caliptra/src/ecc/tb/test_vectors/mm_test_vectors_%0d_key_%0d_word_%0d.hex", TEST_VECTOR_NUM, OPERAND_WIDTH, WORD_WIDTH);
+      fname = $sformatf("mm_test_vectors_%0d_key_%0d_word_%0d.hex", TEST_VECTOR_NUM, OPERAND_WIDTH, WORD_WIDTH);
+
       read_test_vectors(fname);
 
       init_sim();
diff --git a/src/ecc/tb/ecc_top_tb.sv b/src/ecc/tb/ecc_top_tb.sv
index 9333b7610..9112a4718 100644
--- a/src/ecc/tb/ecc_top_tb.sv
+++ b/src/ecc/tb/ecc_top_tb.sv
@@ -138,6 +138,9 @@ module ecc_top_tb
     end
   end
 
+  //bind coverage file
+  ecc_top_cov_bind i_ecc_top_cov_bind();
+
   //----------------------------------------------------------------
   // Device Under Test.
   //----------------------------------------------------------------
@@ -169,7 +172,8 @@ module ecc_top_tb
              .pcr_signing_data(pcr_signing_data_tb),
 
              .error_intr(error_intr_tb),
-             .notif_intr(notif_intr_tb)
+             .notif_intr(notif_intr_tb),
+             .debugUnlock_or_scan_mode_switch('0)
             );
 
 
@@ -206,18 +210,15 @@ module ecc_top_tb
   task reset_dut;
     begin
       $display("*** Toggle reset.");
+      cptra_pwrgood_tb = '0;
       reset_n_tb = 0;
-      cptra_pwrgood_tb = 0;
 
       #(2 * CLK_PERIOD);
-
-      @(posedge clk_tb);
-      reset_n_tb = 1;
       cptra_pwrgood_tb = 1;
 
       #(2 * CLK_PERIOD);
+      reset_n_tb = 1;
 
-      @(posedge clk_tb);
       $display("");
     end
   endtask // reset_dut
@@ -307,22 +308,18 @@ module ecc_top_tb
   task write_single_word(input [31 : 0]  address,
                   input [31 : 0] word);
     begin
-      hsel_i_tb       <= 1;
-      haddr_i_tb      <= address;
-      hwrite_i_tb     <= 1;
-      hready_i_tb     <= 1;
-      htrans_i_tb     <= AHB_HTRANS_NONSEQ;
-      hsize_i_tb      <= 3'b010;
-      
-      @(posedge clk_tb);
-      haddr_i_tb      <= 'Z;
-      hwdata_i_tb     <= word;
-      hwrite_i_tb     <= 0;
-      htrans_i_tb     <= AHB_HTRANS_IDLE;
-      wait(hreadyout_o_tb == 1'b1);
-
-      @(posedge clk_tb);
-      hsel_i_tb       <= 0;
+      hsel_i_tb       = 1;
+      haddr_i_tb      = address;
+      hwrite_i_tb     = 1;
+      hready_i_tb     = 1;
+      htrans_i_tb     = AHB_HTRANS_NONSEQ;
+      hsize_i_tb      = 3'b010;
+      #(CLK_PERIOD);
+
+      haddr_i_tb      = 'Z;
+      hwdata_i_tb     = word;
+      hwrite_i_tb     = 0;
+      htrans_i_tb     = AHB_HTRANS_IDLE;
     end
   endtask // write_single_word
 
@@ -359,21 +356,17 @@ module ecc_top_tb
   //----------------------------------------------------------------
   task read_single_word(input [31 : 0]  address);
     begin
-      hsel_i_tb       <= 1;
-      haddr_i_tb      <= address;
-      hwrite_i_tb     <= 0;
-      hready_i_tb     <= 1;
-      htrans_i_tb     <= AHB_HTRANS_NONSEQ;
-      hsize_i_tb      <= 3'b010;
+      hsel_i_tb       = 1;
+      haddr_i_tb      = address;
+      hwrite_i_tb     = 0;
+      hready_i_tb     = 1;
+      htrans_i_tb     = AHB_HTRANS_NONSEQ;
+      hsize_i_tb      = 3'b010;
+      #(CLK_PERIOD);
       
-      @(posedge clk_tb);
-      hwdata_i_tb     <= 0;
-      haddr_i_tb      <= 'Z;
-      htrans_i_tb     <= AHB_HTRANS_IDLE;
-      wait(hreadyout_o_tb == 1'b1);
-
-      @(posedge clk_tb);
-      hsel_i_tb       <= 0;      
+      hwdata_i_tb     = 0;
+      haddr_i_tb      = 'Z;
+      htrans_i_tb     = AHB_HTRANS_IDLE;
     end
   endtask // read_word
 
@@ -455,7 +448,10 @@ module ecc_top_tb
   //----------------------------------------------------------------
   task trig_ECC(input [2 : 0] cmd);
     begin
-      write_single_word(`ECC_REG_ECC_CTRL  , cmd);
+      write_single_word(`ECC_REG_ECC_CTRL, cmd);
+      #(CLK_PERIOD);
+      hsel_i_tb       = 0;
+      #(CLK_PERIOD);
     end
   endtask // trig_ECC
 
@@ -469,7 +465,7 @@ module ecc_top_tb
                        input test_vector_t test_vector);
     reg [31  : 0]   start_time;
     reg [31  : 0]   end_time;
-    reg [383 : 0]   privkey;
+    operand_t       privkey;
     affn_point_t    pubkey;
     begin
       wait_ready();
@@ -488,7 +484,6 @@ module ecc_top_tb
 
       $display("*** TC %0d starting ECC keygen flow", tc_number);
       trig_ECC(ECC_CMD_KEYGEN);
-      #(CLK_PERIOD);
       
       wait_ready();
 
@@ -504,6 +499,8 @@ module ecc_top_tb
       read_block(`ECC_REG_ECC_PUBKEY_Y_0);
       pubkey.y = reg_read_data;
       
+      trig_ECC(`ECC_REG_ECC_CTRL_ZEROIZE_MASK); //zeroize
+
       end_time = cycle_ctr - start_time;
       $display("*** keygen test processing time = %01d cycles.", end_time);
       $display("privkey    : 0x%96x", privkey);
@@ -539,8 +536,8 @@ module ecc_top_tb
                         input test_vector_t test_vector);
     reg [31  : 0]   start_time;
     reg [31  : 0]   end_time;
-    reg [383 : 0]   R;
-    reg [383 : 0]   S;
+    operand_t       R;
+    operand_t       S;
     
     begin
       wait_ready();
@@ -559,7 +556,6 @@ module ecc_top_tb
 
       $display("*** TC %0d starting ECC signing flow", tc_number);
       trig_ECC(ECC_CMD_SIGNING);
-      #(CLK_PERIOD);
 
       wait_ready();
 
@@ -571,6 +567,8 @@ module ecc_top_tb
       read_block(`ECC_REG_ECC_SIGN_S_0);
       S = reg_read_data;
       
+      trig_ECC(`ECC_REG_ECC_CTRL_ZEROIZE_MASK); //zeroize
+
       end_time = cycle_ctr - start_time;
       $display("*** signing test processing time = %01d cycles.", end_time);
       $display("privkey    : 0x%96x", test_vector.privkey);
@@ -604,7 +602,7 @@ module ecc_top_tb
                         input test_vector_t test_vector);
     reg [31  : 0]   start_time;
     reg [31  : 0]   end_time;
-    reg [383 : 0]   verify_r;
+    operand_t       verify_r;
     
     begin
       wait_ready();
@@ -627,7 +625,6 @@ module ecc_top_tb
 
       $display("*** TC %0d starting ECC verify flow", tc_number);
       trig_ECC(ECC_CMD_VERIFYING);
-      #(CLK_PERIOD);
 
       wait_ready();
 
@@ -635,6 +632,8 @@ module ecc_top_tb
       read_block(`ECC_REG_ECC_VERIFY_R_0);
       verify_r = reg_read_data;
       
+      trig_ECC(`ECC_REG_ECC_CTRL_ZEROIZE_MASK); //zeroize
+
       end_time = cycle_ctr - start_time;
       $display("*** verifying test processing time = %01d cycles.", end_time);
       $display("privkey    : 0x%96x", test_vector.privkey);
@@ -657,6 +656,304 @@ module ecc_top_tb
   endtask // ecc_verifying_test
 
 
+
+  //----------------------------------------------------------------
+  // continuous_cmd_test()
+  //
+  //
+  // Perform test of chaning the command during the process.
+  //----------------------------------------------------------------
+  task continuous_cmd_test(input test_vector_t test_vector);
+    operand_t     privkey;
+    affn_point_t  pubkey;
+    operand_t     R;
+    operand_t     S;
+    operand_t     verify_r;
+
+    begin
+
+      $display("*** continuous_cmd_test started.");
+
+      $display("*** starting ECC keygen flow");
+      wait_ready();
+      tc_ctr = tc_ctr + 1;
+    
+      write_block(`ECC_REG_ECC_SEED_0, test_vector.seed);
+      write_block(`ECC_REG_ECC_NONCE_0, test_vector.nonce);
+      write_block(`ECC_REG_ECC_IV_0, test_vector.IV);
+
+      trig_ECC(ECC_CMD_KEYGEN);
+      
+      for (int i=0; i<10; i++)
+        begin
+          trig_ECC(ECC_CMD_SIGNING);
+          #(10*CLK_PERIOD);
+          trig_ECC(ECC_CMD_KEYGEN);
+          #(10*CLK_PERIOD);
+          trig_ECC(ECC_CMD_VERIFYING);
+          #(10*CLK_PERIOD);
+        end
+
+      wait_ready();
+
+      read_block(`ECC_REG_ECC_PRIVKEY_OUT_0);
+      privkey = reg_read_data;
+      read_block(`ECC_REG_ECC_PUBKEY_X_0);
+      pubkey.x = reg_read_data;
+      read_block(`ECC_REG_ECC_PUBKEY_Y_0);
+      pubkey.y = reg_read_data;
+      
+      trig_ECC(`ECC_REG_ECC_CTRL_ZEROIZE_MASK); //zeroize
+
+      if ((privkey == test_vector.privkey) & (pubkey == test_vector.pubkey))
+        begin
+          $display("*** TC %0d keygen successful.", tc_ctr);
+          $display("");
+        end
+      else
+        begin
+          $display("*** ERROR: TC %0d keygen NOT successful.", tc_ctr);
+          $display("Expected_x: 0x%96x", test_vector.pubkey.x);
+          $display("Got:        0x%96x", pubkey.x);
+          $display("Expected_y: 0x%96x", test_vector.pubkey.y);
+          $display("Got:        0x%96x", pubkey.y);
+          $display("");
+
+          error_ctr = error_ctr + 1;
+        end
+
+
+      $display("*** signing test started.");
+      wait_ready();
+      tc_ctr = tc_ctr + 1;
+
+      write_block(`ECC_REG_ECC_MSG_0, test_vector.hashed_msg);
+      write_block(`ECC_REG_ECC_PRIVKEY_IN_0, test_vector.privkey);
+      write_block(`ECC_REG_ECC_IV_0, test_vector.IV);
+
+      trig_ECC(ECC_CMD_SIGNING);
+
+      for (int i=0; i<10; i++)
+        begin
+          trig_ECC(ECC_CMD_SIGNING);
+          #(10*CLK_PERIOD);
+          trig_ECC(ECC_CMD_KEYGEN);
+          #(10*CLK_PERIOD);
+          trig_ECC(ECC_CMD_VERIFYING);
+          #(10*CLK_PERIOD);
+        end
+
+      wait_ready();
+
+      read_block(`ECC_REG_ECC_SIGN_R_0);
+      R = reg_read_data;
+      read_block(`ECC_REG_ECC_SIGN_S_0);
+      S = reg_read_data;
+      
+      trig_ECC(`ECC_REG_ECC_CTRL_ZEROIZE_MASK); //zeroize
+
+      if (R == test_vector.R & S == test_vector.S)
+        begin
+          $display("*** TC %0d signing successful.", tc_ctr);
+          $display("");
+        end
+      else
+        begin
+          $display("*** ERROR: TC %0d signing NOT successful.", tc_ctr);
+          $display("Expected_R: 0x%96x", test_vector.R);
+          $display("Got:        0x%96x", R);
+          $display("Expected_S: 0x%96x", test_vector.S);
+          $display("Got:        0x%96x", S);
+          $display("");
+
+          error_ctr = error_ctr + 1;
+        end
+
+      
+      $display("*** verifying test started.");
+      wait_ready();
+      tc_ctr = tc_ctr + 1;
+
+      write_block(`ECC_REG_ECC_MSG_0, test_vector.hashed_msg);
+      write_block(`ECC_REG_ECC_PUBKEY_X_0, test_vector.pubkey.x);
+      write_block(`ECC_REG_ECC_PUBKEY_Y_0, test_vector.pubkey.y);
+      write_block(`ECC_REG_ECC_SIGN_R_0, test_vector.R);
+      write_block(`ECC_REG_ECC_SIGN_S_0, test_vector.S);
+
+      trig_ECC(ECC_CMD_VERIFYING);
+
+      for (int i=0; i<10; i++)
+        begin
+          trig_ECC(ECC_CMD_SIGNING);
+          #(10*CLK_PERIOD);
+          trig_ECC(ECC_CMD_KEYGEN);
+          #(10*CLK_PERIOD);
+          trig_ECC(ECC_CMD_VERIFYING);
+          #(10*CLK_PERIOD);
+        end
+
+      wait_ready();
+
+      read_block(`ECC_REG_ECC_VERIFY_R_0);
+      verify_r = reg_read_data;
+      
+      trig_ECC(`ECC_REG_ECC_CTRL_ZEROIZE_MASK); //zeroize
+
+      if (verify_r == test_vector.R)
+        begin
+          $display("*** TC %0d verifying successful.", tc_ctr);
+          $display("");
+        end
+      else
+        begin
+          $display("*** ERROR: TC %0d verifying NOT successful.", tc_ctr);
+          $display("Expected_R: 0x%96x", test_vector.R);
+          $display("Got:        0x%96x", verify_r);
+          $display("");
+
+          error_ctr = error_ctr + 1;
+        end
+    end
+  endtask // continuous_cmd_test
+
+
+  //----------------------------------------------------------------
+  // zeroize_test()
+  //
+  //----------------------------------------------------------------
+  task zeroize_test(input test_vector_t test_vector);
+    operand_t     privkey;
+    affn_point_t  pubkey;
+    operand_t     R;
+    operand_t     S;
+    operand_t     verify_r;
+
+    begin
+
+      $display("*** zeroize test started.");
+      
+      for (int i=0; i<2; i++) begin
+        // First test: assert zeroize with KEYGEN
+        wait_ready();
+        write_block(`ECC_REG_ECC_SEED_0, test_vector.seed);
+        write_block(`ECC_REG_ECC_NONCE_0, test_vector.nonce);
+        write_block(`ECC_REG_ECC_IV_0, test_vector.IV);
+
+        if (i==0) begin
+          trig_ECC(ECC_CMD_KEYGEN);
+          #(100 * CLK_PERIOD);
+          trig_ECC(`ECC_REG_ECC_CTRL_ZEROIZE_MASK); //zeroize
+          #(CLK_PERIOD);
+        end
+        else begin
+          trig_ECC(`ECC_REG_ECC_CTRL_ZEROIZE_MASK | ECC_CMD_KEYGEN); //zeroize
+        end
+
+        wait_ready();
+
+        read_block(`ECC_REG_ECC_PRIVKEY_OUT_0);
+        privkey = reg_read_data;
+        read_block(`ECC_REG_ECC_PUBKEY_X_0);
+        pubkey.x = reg_read_data;
+        read_block(`ECC_REG_ECC_PUBKEY_Y_0);
+        pubkey.y = reg_read_data;
+        
+        if ((privkey == 0) & (pubkey == 0))
+          begin
+            $display("*** TC %0d keygen successful.", tc_ctr);
+            $display("");
+          end
+        else
+          begin
+            $display("*** ERROR: TC %0d keygen NOT successful.", tc_ctr);
+            $display("Got:        0x%96x", pubkey.x);
+            $display("Got:        0x%96x", pubkey.y);
+            $display("");
+
+            error_ctr = error_ctr + 1;
+          end
+        tc_ctr = tc_ctr + 1;
+
+        // Second test: assert zeroize with Signing
+        wait_ready();
+        write_block(`ECC_REG_ECC_MSG_0, test_vector.hashed_msg);
+        write_block(`ECC_REG_ECC_PRIVKEY_IN_0, test_vector.privkey);
+        write_block(`ECC_REG_ECC_IV_0, test_vector.IV);
+
+        if (i==0) begin
+          trig_ECC(ECC_CMD_SIGNING);
+          #(100 * CLK_PERIOD);
+          trig_ECC(`ECC_REG_ECC_CTRL_ZEROIZE_MASK); //zeroize
+        end
+        else begin
+          trig_ECC(`ECC_REG_ECC_CTRL_ZEROIZE_MASK | ECC_CMD_SIGNING); //zeroize
+        end
+
+        wait_ready();
+
+        read_block(`ECC_REG_ECC_SIGN_R_0);
+        R = reg_read_data;
+        read_block(`ECC_REG_ECC_SIGN_S_0);
+        S = reg_read_data;
+        
+        if (R == 0 & S == 0)
+          begin
+            $display("*** TC %0d signing successful.", tc_ctr);
+            $display("");
+          end
+        else
+          begin
+            $display("*** ERROR: TC %0d signing NOT successful.", tc_ctr);
+            $display("Got:        0x%96x", R);
+            $display("Got:        0x%96x", S);
+            $display("");
+
+            error_ctr = error_ctr + 1;
+          end
+        tc_ctr = tc_ctr + 1;
+
+        // Third test: assert zeroize when Verifying is working
+        wait_ready();
+        write_block(`ECC_REG_ECC_MSG_0, test_vector.hashed_msg);
+        write_block(`ECC_REG_ECC_PUBKEY_X_0, test_vector.pubkey.x);
+        write_block(`ECC_REG_ECC_PUBKEY_Y_0, test_vector.pubkey.y);
+        write_block(`ECC_REG_ECC_SIGN_R_0, test_vector.R);
+        write_block(`ECC_REG_ECC_SIGN_S_0, test_vector.S);
+
+        if (i==0) begin
+          trig_ECC(ECC_CMD_VERIFYING);
+          #(100 * CLK_PERIOD);
+          trig_ECC(`ECC_REG_ECC_CTRL_ZEROIZE_MASK); //zeroize
+        end
+        else begin
+          trig_ECC(`ECC_REG_ECC_CTRL_ZEROIZE_MASK | ECC_CMD_VERIFYING); //zeroize
+        end
+
+        wait_ready();
+
+        read_block(`ECC_REG_ECC_VERIFY_R_0);
+        verify_r = reg_read_data;
+        
+        if (verify_r == 0)
+          begin
+            $display("*** TC %0d verifying successful.", tc_ctr);
+            $display("");
+          end
+        else
+          begin
+            $display("*** ERROR: TC %0d verifying NOT successful.", tc_ctr);
+            $display("Got:        0x%96x", verify_r);
+            $display("");
+
+            error_ctr = error_ctr + 1;
+          end
+        tc_ctr = tc_ctr + 1;
+      end
+
+      $display("*** TC%01d - zeroize test done.", tc_ctr);
+    end
+  endtask // zeroize_test
+
   //----------------------------------------------------------------
   // ecc_openssl_keygen_test()
   //
@@ -732,6 +1029,9 @@ module ecc_top_tb
           ecc_onthefly_reset_test(i, test_vectors[i]);
         end
       end
+      
+      continuous_cmd_test(test_vectors[0]);
+      zeroize_test(test_vectors[1]);
     end
   endtask // ecc_test
 
diff --git a/src/ecc/tb/test_vectors/mm_test_vectors_5_key_16_word_4.hex b/src/ecc/tb/test_vectors/mm_test_vectors_5_key_16_word_4.hex
new file mode 100644
index 000000000..56ea6deda
--- /dev/null
+++ b/src/ecc/tb/test_vectors/mm_test_vectors_5_key_16_word_4.hex
@@ -0,0 +1,30 @@
+0013
+0d79
+fffb
+0d
+0000
+0
+0015
+00ff
+fff1
+0f
+b00c
+1
+0026
+e509
+fffb
+0d
+0000
+2
+c15f
+5445
+fff1
+0f
+0006
+3
+bfff
+2fff
+fff1
+0f
+002f
+4
\ No newline at end of file
diff --git a/src/ecc/uvmf_ecc/config/compile.yml b/src/ecc/uvmf_ecc/config/compile.yml
index 2b821a758..991c25a93 100644
--- a/src/ecc/uvmf_ecc/config/compile.yml
+++ b/src/ecc/uvmf_ecc/config/compile.yml
@@ -4,6 +4,7 @@ schema_version: 2.4.0
 requires:
   - uvmf_lib
   - ecc_top
+  - ecc_coverage
 targets:
   tb:
     directories:
diff --git a/src/ecc/uvmf_ecc/uvmf_template_output/project_benches/ECC/tb/testbench/hdl_top.sv b/src/ecc/uvmf_ecc/uvmf_template_output/project_benches/ECC/tb/testbench/hdl_top.sv
index 13891f689..d9d9209bb 100644
--- a/src/ecc/uvmf_ecc/uvmf_template_output/project_benches/ECC/tb/testbench/hdl_top.sv
+++ b/src/ecc/uvmf_ecc/uvmf_template_output/project_benches/ECC/tb/testbench/hdl_top.sv
@@ -116,7 +116,8 @@ import uvmf_base_pkg_hdl::*;
       .hrdata_o         (ECC_out_agent_bus.hrdata), 
 
       .error_intr       (),
-      .notif_intr       ()
+      .notif_intr       (),
+      .debugUnlock_or_scan_mode_switch('0)
   );
 
   // pragma uvmf custom dut_instantiation end
diff --git a/src/edn/config/compile.yml b/src/edn/config/compile.yml
index 9f1b4fa4f..569411ae1 100644
--- a/src/edn/config/compile.yml
+++ b/src/edn/config/compile.yml
@@ -1,5 +1,7 @@
 ---
 provides: [edn_pkg]
+requires:
+  - entropy_src_pkg
 schema_version: 2.4.0
 targets:
   rtl:
diff --git a/src/edn/config/edn_pkg.vf b/src/edn/config/edn_pkg.vf
index e90a6984a..cc750fdb6 100644
--- a/src/edn/config/edn_pkg.vf
+++ b/src/edn/config/edn_pkg.vf
@@ -1,2 +1,7 @@
++incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl
 +incdir+${CALIPTRA_ROOT}/src/edn/rtl
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm_pkg.sv
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_ack_sm_pkg.sv
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_reg_pkg.sv
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_pkg.sv
 ${CALIPTRA_ROOT}/src/edn/rtl/edn_pkg.sv
\ No newline at end of file
diff --git a/src/entropy_src/config/compile.yml b/src/entropy_src/config/compile.yml
index 99b8c9449..9cdb9c50a 100644
--- a/src/entropy_src/config/compile.yml
+++ b/src/entropy_src/config/compile.yml
@@ -23,8 +23,8 @@ requires:
   - entropy_src_pkg
   - libs
   - kmac
-  - prim_generic
-  - prim
+  - caliptra_prim_generic
+  - caliptra_prim
 targets:
   rtl:
     directories: [$COMPILE_ROOT/rtl]
@@ -56,6 +56,7 @@ targets:
   rtl:
     directories: [$COMPILE_ROOT/tb]
     files:
+      - $COMPILE_ROOT/tb/physical_rng.sv
       - $COMPILE_ROOT/tb/entropy_src_tb.sv
     tops: [entropy_src_tb]
 global:
diff --git a/src/entropy_src/config/entropy_src.vf b/src/entropy_src/config/entropy_src.vf
index 535b9751a..f8a916e71 100644
--- a/src/entropy_src/config/entropy_src.vf
+++ b/src/entropy_src/config/entropy_src.vf
@@ -1,11 +1,11 @@
 +incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl
 +incdir+${CALIPTRA_ROOT}/src/integration/rtl
 +incdir+${CALIPTRA_ROOT}/src/libs/rtl
-+incdir+${CALIPTRA_ROOT}/src/prim/rtl
++incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl
 +incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl
 +incdir+${CALIPTRA_ROOT}/src/entropy_src/tb
 +incdir+${CALIPTRA_ROOT}/src/kmac/rtl
-+incdir+${CALIPTRA_ROOT}/src/prim_generic/rtl
++incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm_pkg.sv
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_ack_sm_pkg.sv
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_reg_pkg.sv
@@ -21,12 +21,14 @@ ${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_util_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_alert_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_mubi_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_cipher_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_pkg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv
 ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv
 ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv
@@ -37,37 +39,40 @@ ${CALIPTRA_ROOT}/src/kmac/rtl/keccak_round.sv
 ${CALIPTRA_ROOT}/src/kmac/rtl/keccak_2share.sv
 ${CALIPTRA_ROOT}/src/kmac/rtl/sha3pad.sv
 ${CALIPTRA_ROOT}/src/kmac/rtl/sha3.sv
-${CALIPTRA_ROOT}/src/prim_generic/rtl/prim_generic_flop.sv
-${CALIPTRA_ROOT}/src/prim_generic/rtl/prim_generic_buf.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_flop_2sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_lfsr.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_mubi4_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_diff_decode.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sec_anchor_buf.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_slicer.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_count.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sparse_fsm_flop.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_dom_and_2share.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sec_anchor_flop.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_reg_we_check.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_packer_fifo.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_max_tree.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg_arb.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_intr_hw.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_onehot_check.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_mubi8_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_fifo_sync_cnt.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_buf.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_lc_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_alert_receiver.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_flop.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_alert_sender.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_fifo_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_arbiter_ppc.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sum_tree.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg_ext.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_edge_detector.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_en.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cdc_rand_delay.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lfsr.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi4_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_diff_decode.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_slicer.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_count.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_dom_and_2share.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_reg_we_check.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_max_tree.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_arb.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_intr_hw.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_onehot_check.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi8_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync_cnt.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lc_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_receiver.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_sender.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_reg_top.sv
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_bucket_ht.sv
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_cntr_reg.sv
@@ -80,4 +85,4 @@ ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_adaptp_ht.sv
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_core.sv
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_repcnt_ht.sv
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_ack_sm.sv
-${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src.sv
\ No newline at end of file
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src.sv
diff --git a/src/entropy_src/config/entropy_src.vlt b/src/entropy_src/config/entropy_src.vlt
index 21794084e..5e03da9c1 100644
--- a/src/entropy_src/config/entropy_src.vlt
+++ b/src/entropy_src/config/entropy_src.vlt
@@ -1,6 +1,6 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
-${CALIPTRA_ROOT}/src/prim/lint/prim_max_tree.vlt
-${CALIPTRA_ROOT}/src/prim/lint/prim_sum_tree.vlt
-${CALIPTRA_ROOT}/src/prim/lint/prim_onehot_check.vlt
+${CALIPTRA_ROOT}/src/caliptra_prim/lint/caliptra_prim_max_tree.vlt
+${CALIPTRA_ROOT}/src/caliptra_prim/lint/caliptra_prim_sum_tree.vlt
+${CALIPTRA_ROOT}/src/caliptra_prim/lint/caliptra_prim_onehot_check.vlt
diff --git a/src/entropy_src/config/entropy_src_tb.vf b/src/entropy_src/config/entropy_src_tb.vf
index 95547b682..f0f720b91 100644
--- a/src/entropy_src/config/entropy_src_tb.vf
+++ b/src/entropy_src/config/entropy_src_tb.vf
@@ -1,11 +1,11 @@
 +incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl
 +incdir+${CALIPTRA_ROOT}/src/integration/rtl
 +incdir+${CALIPTRA_ROOT}/src/libs/rtl
-+incdir+${CALIPTRA_ROOT}/src/prim/rtl
++incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl
 +incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl
 +incdir+${CALIPTRA_ROOT}/src/entropy_src/tb
 +incdir+${CALIPTRA_ROOT}/src/kmac/rtl
-+incdir+${CALIPTRA_ROOT}/src/prim_generic/rtl
++incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm_pkg.sv
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_ack_sm_pkg.sv
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_reg_pkg.sv
@@ -21,12 +21,14 @@ ${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_util_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_alert_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_mubi_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_cipher_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_pkg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv
 ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv
 ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv
@@ -37,37 +39,40 @@ ${CALIPTRA_ROOT}/src/kmac/rtl/keccak_round.sv
 ${CALIPTRA_ROOT}/src/kmac/rtl/keccak_2share.sv
 ${CALIPTRA_ROOT}/src/kmac/rtl/sha3pad.sv
 ${CALIPTRA_ROOT}/src/kmac/rtl/sha3.sv
-${CALIPTRA_ROOT}/src/prim_generic/rtl/prim_generic_flop.sv
-${CALIPTRA_ROOT}/src/prim_generic/rtl/prim_generic_buf.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_flop_2sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_lfsr.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_mubi4_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_diff_decode.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sec_anchor_buf.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_slicer.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_count.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sparse_fsm_flop.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_dom_and_2share.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sec_anchor_flop.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_reg_we_check.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_packer_fifo.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_max_tree.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg_arb.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_intr_hw.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_onehot_check.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_mubi8_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_fifo_sync_cnt.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_buf.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_lc_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_alert_receiver.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_flop.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_alert_sender.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_fifo_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_arbiter_ppc.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sum_tree.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg_ext.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_edge_detector.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_en.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cdc_rand_delay.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lfsr.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi4_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_diff_decode.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_slicer.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_count.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_dom_and_2share.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_reg_we_check.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_max_tree.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_arb.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_intr_hw.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_onehot_check.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi8_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync_cnt.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lc_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_receiver.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_sender.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_reg_top.sv
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_bucket_ht.sv
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_cntr_reg.sv
@@ -81,4 +86,4 @@ ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_core.sv
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_repcnt_ht.sv
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_ack_sm.sv
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src.sv
-${CALIPTRA_ROOT}/src/entropy_src/tb/entropy_src_tb.sv
\ No newline at end of file
+${CALIPTRA_ROOT}/src/entropy_src/tb/entropy_src_tb.sv
diff --git a/src/entropy_src/data/entropy_src.hjson b/src/entropy_src/data/entropy_src.hjson
index 74a76233d..65202bab5 100644
--- a/src/entropy_src/data/entropy_src.hjson
+++ b/src/entropy_src/data/entropy_src.hjson
@@ -45,13 +45,13 @@
       type:    "uni"
       name:    "otp_en_entropy_src_fw_read"
       act:     "rcv"
-      package: "prim_mubi_pkg"
+      package: "caliptra_prim_mubi_pkg"
     }
     { struct:  "mubi8"
       type:    "uni"
       name:    "otp_en_entropy_src_fw_over"
       act:     "rcv"
-      package: "prim_mubi_pkg"
+      package: "caliptra_prim_mubi_pkg"
     }
     { struct:  "logic"
       type:    "uni"
diff --git a/src/entropy_src/data/entropy_src.json b/src/entropy_src/data/entropy_src.json
index 6cdd99c15..522b3403e 100644
--- a/src/entropy_src/data/entropy_src.json
+++ b/src/entropy_src/data/entropy_src.json
@@ -64,14 +64,14 @@
       "type": "uni",
       "name": "otp_en_entropy_src_fw_read",
       "act": "rcv",
-      "package": "prim_mubi_pkg"
+      "package": "caliptra_prim_mubi_pkg"
     },
     {
       "struct": "mubi8",
       "type": "uni",
       "name": "otp_en_entropy_src_fw_over",
       "act": "rcv",
-      "package": "prim_mubi_pkg"
+      "package": "caliptra_prim_mubi_pkg"
     },
     {
       "struct": "logic",
diff --git a/src/entropy_src/rtl/entropy_src.sv b/src/entropy_src/rtl/entropy_src.sv
index ece5b8e40..d4af6c202 100644
--- a/src/entropy_src/rtl/entropy_src.sv
+++ b/src/entropy_src/rtl/entropy_src.sv
@@ -4,13 +4,13 @@
 //
 // Description: entropy_src top level wrapper file
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
 
 module entropy_src
   import entropy_src_pkg::*;
   import entropy_src_reg_pkg::*;
-  import prim_mubi_pkg::mubi8_t;
+  import caliptra_prim_mubi_pkg::mubi8_t;
 #(
   parameter bit Stub = 1'b0,
   parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}},
@@ -60,8 +60,8 @@ module entropy_src
   input  entropy_src_xht_rsp_t entropy_src_xht_i,
 
   // Alerts
-  input  prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i,
-  output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o,
+  input  caliptra_prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i,
+  output caliptra_prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o,
 
   // Interrupts
   output logic    intr_es_entropy_valid_o,
@@ -203,18 +203,18 @@ module entropy_src
   };
   // once enabled, stub entropy is always available
 
-  import prim_mubi_pkg::mubi4_t;
-  import prim_mubi_pkg::mubi4_test_true_strict;
+  import caliptra_prim_mubi_pkg::mubi4_t;
+  import caliptra_prim_mubi_pkg::mubi4_test_true_strict;
 
   mubi4_t mubi_module_en;
   assign mubi_module_en  = mubi4_t'(reg2hw.module_enable.q);
   assign stub_es_valid = mubi4_test_true_strict(mubi_module_en);
 
   if (Stub) begin : gen_stub_entropy_src
-    prim_lfsr #(
+    caliptra_prim_lfsr #(
       .LfsrDw(StubLfsrWidth),
       .StateOutDw(StubLfsrWidth)
-    ) u_prim_lfsr (
+    ) u_caliptra_prim_lfsr (
       .clk_i          (clk_i),
       .rst_ni         (rst_ni),
       .seed_en_i      ('0),
@@ -248,10 +248,10 @@ module entropy_src
   // Alert generation
   ///////////////////////////
   for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx
-    prim_alert_sender #(
+    caliptra_prim_alert_sender #(
       .AsyncOn(AlertAsyncOn[i]),
       .IsFatal(i)
-    ) u_prim_alert_sender (
+    ) u_caliptra_prim_alert_sender (
       .clk_i,
       .rst_ni,
       .alert_test_i  ( alert_test[i]                 ),
@@ -292,37 +292,37 @@ module entropy_src
   `CALIPTRA_ASSERT_KNOWN(IntrEsHealthTestFailedKnownO_A, intr_es_health_test_failed_o)
   `CALIPTRA_ASSERT_KNOWN(IntrEsFifoErrKnownO_A, intr_es_fatal_err_o)
 
-  // prim_count alerts
+  // caliptra_prim_count alerts
   `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntAlertCheck0_A,
-    u_entropy_src_core.u_prim_count_window_cntr,
+    u_entropy_src_core.u_caliptra_prim_count_window_cntr,
     alert_tx_o[1])
 
   for (genvar sh = 0; sh < RngBusWidth; sh = sh+1) begin : gen_bit_cntrs
     `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntAlertCheck1_A,
-      u_entropy_src_core.u_entropy_src_adaptp_ht.gen_cntrs[sh].u_prim_count_test_cnt,
+      u_entropy_src_core.u_entropy_src_adaptp_ht.gen_cntrs[sh].u_caliptra_prim_count_test_cnt,
       alert_tx_o[1])
   end : gen_bit_cntrs
 
   for (genvar i = 0; i < NumBins; i = i + 1) begin : gen_symbol_match
    `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntAlertCheck_A,
-     u_entropy_src_core.u_entropy_src_bucket_ht.gen_symbol_match[i].u_prim_count_bin_cntr,
+     u_entropy_src_core.u_entropy_src_bucket_ht.gen_symbol_match[i].u_caliptra_prim_count_bin_cntr,
      alert_tx_o[1])
   end : gen_symbol_match
 
   for (genvar sh = 0; sh < RngBusWidth; sh = sh+1) begin : gen_pair_cntrs
    `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntAlertCheck_A,
-     u_entropy_src_core.u_entropy_src_markov_ht.gen_cntrs[sh].u_prim_count_pair_cntr,
+     u_entropy_src_core.u_entropy_src_markov_ht.gen_cntrs[sh].u_caliptra_prim_count_pair_cntr,
      alert_tx_o[1])
   end : gen_pair_cntrs
 
   for (genvar sh = 0; sh < RngBusWidth; sh = sh+1) begin : gen_rep_cntrs
    `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntAlertCheck_A,
-     u_entropy_src_core.u_entropy_src_repcnt_ht.gen_cntrs[sh].u_prim_count_rep_cntr,
+     u_entropy_src_core.u_entropy_src_repcnt_ht.gen_cntrs[sh].u_caliptra_prim_count_rep_cntr,
      alert_tx_o[1])
   end : gen_rep_cntrs
 
   `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntAlertCheck7_A,
-    u_entropy_src_core.u_entropy_src_repcnts_ht.u_prim_count_rep_cntr,
+    u_entropy_src_core.u_entropy_src_repcnts_ht.u_caliptra_prim_count_rep_cntr,
     alert_tx_o[1])
 
   `CALIPTRA_ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(CtrlMainFsmCheck_A,
@@ -350,79 +350,79 @@ module entropy_src
     u_entropy_src_core.u_sha3.u_keccak.u_round_count, alert_tx_o[1])
 
   `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntAlertCheck8_A,
-    u_entropy_src_core.u_entropy_src_cntr_reg_repcnt.u_prim_count_cntr_reg,
+    u_entropy_src_core.u_entropy_src_cntr_reg_repcnt.u_caliptra_prim_count_cntr_reg,
     alert_tx_o[1])
 
   `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntAlertCheck9_A,
-    u_entropy_src_core.u_entropy_src_cntr_reg_repcnts.u_prim_count_cntr_reg,
+    u_entropy_src_core.u_entropy_src_cntr_reg_repcnts.u_caliptra_prim_count_cntr_reg,
     alert_tx_o[1])
 
   `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntAlertCheck10_A,
-    u_entropy_src_core.u_entropy_src_cntr_reg_adaptp_hi.u_prim_count_cntr_reg,
+    u_entropy_src_core.u_entropy_src_cntr_reg_adaptp_hi.u_caliptra_prim_count_cntr_reg,
     alert_tx_o[1])
 
   `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntAlertCheck11_A,
-    u_entropy_src_core.u_entropy_src_cntr_reg_adaptp_lo.u_prim_count_cntr_reg,
+    u_entropy_src_core.u_entropy_src_cntr_reg_adaptp_lo.u_caliptra_prim_count_cntr_reg,
     alert_tx_o[1])
 
   `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntAlertCheck12_A,
-    u_entropy_src_core.u_entropy_src_cntr_reg_bucket.u_prim_count_cntr_reg,
+    u_entropy_src_core.u_entropy_src_cntr_reg_bucket.u_caliptra_prim_count_cntr_reg,
     alert_tx_o[1])
 
   `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntAlertCheck13_A,
-    u_entropy_src_core.u_entropy_src_cntr_reg_markov_hi.u_prim_count_cntr_reg,
+    u_entropy_src_core.u_entropy_src_cntr_reg_markov_hi.u_caliptra_prim_count_cntr_reg,
     alert_tx_o[1])
 
   `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntAlertCheck14_A,
-    u_entropy_src_core.u_entropy_src_cntr_reg_markov_lo.u_prim_count_cntr_reg,
+    u_entropy_src_core.u_entropy_src_cntr_reg_markov_lo.u_caliptra_prim_count_cntr_reg,
     alert_tx_o[1])
 
   `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntAlertCheck15_A,
-    u_entropy_src_core.u_entropy_src_cntr_reg_extht_hi.u_prim_count_cntr_reg,
+    u_entropy_src_core.u_entropy_src_cntr_reg_extht_hi.u_caliptra_prim_count_cntr_reg,
     alert_tx_o[1])
 
   `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntAlertCheck16_A,
-    u_entropy_src_core.u_entropy_src_cntr_reg_extht_lo.u_prim_count_cntr_reg,
+    u_entropy_src_core.u_entropy_src_cntr_reg_extht_lo.u_caliptra_prim_count_cntr_reg,
     alert_tx_o[1])
 
   `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntAlertCheck17_A,
-    u_entropy_src_core.u_entropy_src_cntr_reg_any_alert_fails.u_prim_count_cntr_reg,
+    u_entropy_src_core.u_entropy_src_cntr_reg_any_alert_fails.u_caliptra_prim_count_cntr_reg,
     alert_tx_o[1])
 
   `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntAlertCheck18_A,
-    u_entropy_src_core.u_entropy_src_cntr_reg_repcnt_alert_fails.u_prim_count_cntr_reg,
+    u_entropy_src_core.u_entropy_src_cntr_reg_repcnt_alert_fails.u_caliptra_prim_count_cntr_reg,
     alert_tx_o[1])
 
   `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntAlertCheck19_A,
-    u_entropy_src_core.u_entropy_src_cntr_reg_repcnts_alert_fails.u_prim_count_cntr_reg,
+    u_entropy_src_core.u_entropy_src_cntr_reg_repcnts_alert_fails.u_caliptra_prim_count_cntr_reg,
     alert_tx_o[1])
 
   `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntAlertCheck20_A,
-    u_entropy_src_core.u_entropy_src_cntr_reg_adaptp_hi_alert_fails.u_prim_count_cntr_reg,
+    u_entropy_src_core.u_entropy_src_cntr_reg_adaptp_hi_alert_fails.u_caliptra_prim_count_cntr_reg,
     alert_tx_o[1])
 
   `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntAlertCheck21_A,
-    u_entropy_src_core.u_entropy_src_cntr_reg_adaptp_lo_alert_fails.u_prim_count_cntr_reg,
+    u_entropy_src_core.u_entropy_src_cntr_reg_adaptp_lo_alert_fails.u_caliptra_prim_count_cntr_reg,
     alert_tx_o[1])
 
   `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntAlertCheck22_A,
-    u_entropy_src_core.u_entropy_src_cntr_reg_bucket_alert_fails.u_prim_count_cntr_reg,
+    u_entropy_src_core.u_entropy_src_cntr_reg_bucket_alert_fails.u_caliptra_prim_count_cntr_reg,
     alert_tx_o[1])
 
   `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntAlertCheck23_A,
-    u_entropy_src_core.u_entropy_src_cntr_reg_markov_hi_alert_fails.u_prim_count_cntr_reg,
+    u_entropy_src_core.u_entropy_src_cntr_reg_markov_hi_alert_fails.u_caliptra_prim_count_cntr_reg,
     alert_tx_o[1])
 
   `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntAlertCheck24_A,
-    u_entropy_src_core.u_entropy_src_cntr_reg_markov_lo_alert_fails.u_prim_count_cntr_reg,
+    u_entropy_src_core.u_entropy_src_cntr_reg_markov_lo_alert_fails.u_caliptra_prim_count_cntr_reg,
     alert_tx_o[1])
 
   `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntAlertCheck25_A,
-    u_entropy_src_core.u_entropy_src_cntr_reg_extht_hi_alert_fails.u_prim_count_cntr_reg,
+    u_entropy_src_core.u_entropy_src_cntr_reg_extht_hi_alert_fails.u_caliptra_prim_count_cntr_reg,
     alert_tx_o[1])
 
   `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntAlertCheck26_A,
-    u_entropy_src_core.u_entropy_src_cntr_reg_extht_lo_alert_fails.u_prim_count_cntr_reg,
+    u_entropy_src_core.u_entropy_src_cntr_reg_extht_lo_alert_fails.u_caliptra_prim_count_cntr_reg,
     alert_tx_o[1])
 
   // Alert assertions for reg_we onehot check
diff --git a/src/entropy_src/rtl/entropy_src_ack_sm.sv b/src/entropy_src/rtl/entropy_src_ack_sm.sv
index a5d12e750..6fda7f6ce 100644
--- a/src/entropy_src/rtl/entropy_src_ack_sm.sv
+++ b/src/entropy_src/rtl/entropy_src_ack_sm.sv
@@ -22,7 +22,7 @@ module entropy_src_ack_sm (
 
   state_e state_d, state_q;
 
-  `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Idle)
+  `CALIPTRA_PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Idle)
 
   always_comb begin
     state_d = state_q;
diff --git a/src/entropy_src/rtl/entropy_src_adaptp_ht.sv b/src/entropy_src/rtl/entropy_src_adaptp_ht.sv
index 1ef799702..4c58bbc33 100644
--- a/src/entropy_src/rtl/entropy_src_adaptp_ht.sv
+++ b/src/entropy_src/rtl/entropy_src_adaptp_ht.sv
@@ -47,9 +47,9 @@ module entropy_src_adaptp_ht #(
 
     // cumulative ones counter
     // SEC_CM: CTR.REDUN
-    prim_count #(
+    caliptra_prim_count #(
       .Width(RegWidth)
-    ) u_prim_count_test_cnt (
+    ) u_caliptra_prim_count_test_cnt (
       .clk_i,
       .rst_ni,
       .clr_i(window_wrap_pulse_i),
@@ -65,7 +65,7 @@ module entropy_src_adaptp_ht #(
   end : gen_cntrs
 
   // determine the highest counter counter value
-  prim_max_tree #(
+  caliptra_prim_max_tree #(
     .NumSrc(RngBusWidth),
     .Width(RegWidth)
   ) u_max (
@@ -79,9 +79,9 @@ module entropy_src_adaptp_ht #(
   );
 
   // determine the lowest counter value
-  // Negate the inputs and outputs of prim_max_tree to find the minimum
+  // Negate the inputs and outputs of caliptra_prim_max_tree to find the minimum
   // For this unsigned application, one's complement negation (i.e. logical inversion) is fine.
-  prim_max_tree #(
+  caliptra_prim_max_tree #(
     .NumSrc(RngBusWidth),
     .Width(RegWidth)
   ) u_min (
@@ -96,7 +96,7 @@ module entropy_src_adaptp_ht #(
 
   assign test_cnt_min = ~test_cnt_min_tmp;
 
-  prim_sum_tree #(
+  caliptra_prim_sum_tree #(
     .NumSrc(RngBusWidth),
     .Width(RegWidth)
   ) u_sum (
diff --git a/src/entropy_src/rtl/entropy_src_bucket_ht.sv b/src/entropy_src/rtl/entropy_src_bucket_ht.sv
index ecf2e9ba9..a59e62f46 100644
--- a/src/entropy_src/rtl/entropy_src_bucket_ht.sv
+++ b/src/entropy_src/rtl/entropy_src_bucket_ht.sv
@@ -49,9 +49,9 @@ module entropy_src_bucket_ht #(
     assign bin_incr[i] = entropy_bit_vld_i && (entropy_bit_i == i);
     // use the bin incrementer to increase the bin total count
     // SEC_CM: CTR.REDUN
-    prim_count #(
+    caliptra_prim_count #(
       .Width(RegWidth)
-    ) u_prim_count_bin_cntr (
+    ) u_caliptra_prim_count_bin_cntr (
       .clk_i,
       .rst_ni,
       .clr_i(window_wrap_pulse_i),
@@ -67,10 +67,10 @@ module entropy_src_bucket_ht #(
     assign bin_cnt_exceeds_thresh[i] = (bin_cntr[i] > thresh_i);
   end : gen_symbol_match
 
-  prim_max_tree #(
+  caliptra_prim_max_tree #(
     .NumSrc(NUM_BINS),
     .Width(RegWidth)
-  ) u_prim_max_tree_bin_cntr_max (
+  ) u_caliptra_prim_max_tree_bin_cntr_max (
     .clk_i,
     .rst_ni,
     .values_i   (bin_cntr),
diff --git a/src/entropy_src/rtl/entropy_src_cntr_reg.sv b/src/entropy_src/rtl/entropy_src_cntr_reg.sv
index fbb5c3425..65c1a506d 100644
--- a/src/entropy_src/rtl/entropy_src_cntr_reg.sv
+++ b/src/entropy_src/rtl/entropy_src_cntr_reg.sv
@@ -22,9 +22,9 @@ module entropy_src_cntr_reg #(
   logic [RegWidth-1:0] counter_value;
 
   // counter will not wrap when full value is reached
-  prim_count #(
+  caliptra_prim_count #(
     .Width(RegWidth)
-  ) u_prim_count_cntr_reg (
+  ) u_caliptra_prim_count_cntr_reg (
     .clk_i,
     .rst_ni,
     .clr_i(clear_i),
diff --git a/src/entropy_src/rtl/entropy_src_core.sv b/src/entropy_src/rtl/entropy_src_core.sv
index 6c5bcaeb5..cb58c0e4d 100644
--- a/src/entropy_src/rtl/entropy_src_core.sv
+++ b/src/entropy_src/rtl/entropy_src_core.sv
@@ -15,8 +15,8 @@ module entropy_src_core import entropy_src_pkg::*; #(
   output entropy_src_reg_pkg::entropy_src_hw2reg_t hw2reg,
 
   // Efuse Interface
-  input prim_mubi_pkg::mubi8_t otp_en_entropy_src_fw_read_i,
-  input prim_mubi_pkg::mubi8_t otp_en_entropy_src_fw_over_i,
+  input caliptra_prim_mubi_pkg::mubi8_t otp_en_entropy_src_fw_read_i,
+  input caliptra_prim_mubi_pkg::mubi8_t otp_en_entropy_src_fw_over_i,
 
   // RNG Interface
   output logic rng_fips_o,
@@ -49,11 +49,11 @@ module entropy_src_core import entropy_src_pkg::*; #(
 );
 
   import entropy_src_reg_pkg::*;
-  import prim_mubi_pkg::mubi4_t;
-  import prim_mubi_pkg::mubi4_test_true_strict;
-  import prim_mubi_pkg::mubi4_and_hi;
-  import prim_mubi_pkg::mubi4_test_false_loose;
-  import prim_mubi_pkg::mubi4_test_invalid;
+  import caliptra_prim_mubi_pkg::mubi4_t;
+  import caliptra_prim_mubi_pkg::mubi4_test_true_strict;
+  import caliptra_prim_mubi_pkg::mubi4_and_hi;
+  import caliptra_prim_mubi_pkg::mubi4_test_false_loose;
+  import caliptra_prim_mubi_pkg::mubi4_test_invalid;
 
   localparam int Clog2EsFifoDepth = $clog2(EsFifoDepth);
   localparam int PostHTWidth = 32;
@@ -406,8 +406,8 @@ module entropy_src_core import entropy_src_pkg::*; #(
   logic                     sha3_msg_end;
   logic                     sha3_msg_rdy_mask;
   logic                     sha3_block_processed;
-  prim_mubi_pkg::mubi4_t    sha3_done;
-  prim_mubi_pkg::mubi4_t    sha3_absorbed;
+  caliptra_prim_mubi_pkg::mubi4_t    sha3_done;
+  caliptra_prim_mubi_pkg::mubi4_t    sha3_absorbed;
   logic                     sha3_squeezing;
   logic [2:0]               sha3_fsm;
   logic [32:0]              sha3_err;
@@ -448,8 +448,8 @@ module entropy_src_core import entropy_src_pkg::*; #(
   logic                    unused_entropy_data;
   logic                    unused_fw_ov_rd_data;
 
-  prim_mubi_pkg::mubi8_t en_entropy_src_fw_read;
-  prim_mubi_pkg::mubi8_t en_entropy_src_fw_over;
+  caliptra_prim_mubi_pkg::mubi8_t en_entropy_src_fw_read;
+  caliptra_prim_mubi_pkg::mubi8_t en_entropy_src_fw_over;
 
   mubi4_t mubi_es_enable;
   mubi4_t mubi_module_en_pulse;
@@ -495,7 +495,7 @@ module entropy_src_core import entropy_src_pkg::*; #(
       es_rdata_capt_vld_q    <= '0;
       fw_ov_sha3_start_pfe_q <= '0;
       sha3_msg_rdy_mask_q    <= '0;
-      mubi_mod_en_dly_q      <= prim_mubi_pkg::MuBi4False;
+      mubi_mod_en_dly_q      <= caliptra_prim_mubi_pkg::MuBi4False;
       sha3_flush_q           <= '0;
       sha3_start_mask_q      <= '0;
       fw_ov_corrupted_q      <= 2'b00;
@@ -544,10 +544,10 @@ module entropy_src_core import entropy_src_pkg::*; #(
   assign hw2reg.recov_alert_sts.module_enable_field_alert.de = es_enable_pfa;
   assign hw2reg.recov_alert_sts.module_enable_field_alert.d  = es_enable_pfa;
 
-  prim_mubi4_sync #(
+  caliptra_prim_mubi4_sync #(
     .NumCopies(3),
     .AsyncOn(0)
-  ) u_prim_mubi4_sync_entropy_module_en (
+  ) u_caliptra_prim_mubi4_sync_entropy_module_en (
     .clk_i,
     .rst_ni,
     .mubi_i(mubi_module_en_raw),
@@ -580,10 +580,10 @@ module entropy_src_core import entropy_src_pkg::*; #(
     assign es_enable_fo[i] = mubi4_test_true_strict(mubi_es_enable_fanout[i]);
   end : gen_mubi_en_copies
 
-  prim_mubi4_sync #(
+  caliptra_prim_mubi4_sync #(
     .NumCopies(EsEnableCopies),
     .AsyncOn(0)
-  ) u_prim_mubi4_sync_es_enable (
+  ) u_caliptra_prim_mubi4_sync_es_enable (
     .clk_i,
     .rst_ni,
     .mubi_i(mubi_es_enable),
@@ -594,10 +594,10 @@ module entropy_src_core import entropy_src_pkg::*; #(
     assign module_en_pulse_fo[i] = mubi4_test_true_strict(mubi_module_en_pulse_fanout[i]);
   end : gen_mubi_en_pulse_copies
 
-  prim_mubi4_sync #(
+  caliptra_prim_mubi4_sync #(
     .NumCopies(EsEnPulseCopies),
     .AsyncOn(0)
-  ) u_prim_mubi4_sync_es_enable_pulse (
+  ) u_caliptra_prim_mubi4_sync_es_enable_pulse (
     .clk_i,
     .rst_ni,
     .mubi_i(mubi_module_en_pulse),
@@ -625,10 +625,10 @@ module entropy_src_core import entropy_src_pkg::*; #(
   assign hw2reg.recov_alert_sts.fips_enable_field_alert.de = fips_enable_pfa;
   assign hw2reg.recov_alert_sts.fips_enable_field_alert.d  = fips_enable_pfa;
 
-  prim_mubi4_sync #(
+  caliptra_prim_mubi4_sync #(
     .NumCopies(2),
     .AsyncOn(0)
-  ) u_prim_mubi4_sync_entropy_fips_en (
+  ) u_caliptra_prim_mubi4_sync_entropy_fips_en (
     .clk_i,
     .rst_ni,
     .mubi_i(mubi_fips_en),
@@ -644,10 +644,10 @@ module entropy_src_core import entropy_src_pkg::*; #(
   assign hw2reg.recov_alert_sts.entropy_data_reg_en_field_alert.de = entropy_data_reg_en_pfa;
   assign hw2reg.recov_alert_sts.entropy_data_reg_en_field_alert.d =  entropy_data_reg_en_pfa;
 
-  prim_mubi4_sync #(
+  caliptra_prim_mubi4_sync #(
     .NumCopies(2),
     .AsyncOn(0)
-  ) u_prim_mubi4_sync_entropy_data_reg_en (
+  ) u_caliptra_prim_mubi4_sync_entropy_data_reg_en (
     .clk_i,
     .rst_ni,
     .mubi_i(mubi_entropy_reg_en),
@@ -665,10 +665,10 @@ module entropy_src_core import entropy_src_pkg::*; #(
   assign hw2reg.recov_alert_sts.fw_ov_mode_field_alert.de = fw_ov_mode_pfa;
   assign hw2reg.recov_alert_sts.fw_ov_mode_field_alert.d  = fw_ov_mode_pfa;
 
-  prim_mubi4_sync #(
+  caliptra_prim_mubi4_sync #(
     .NumCopies(2),
     .AsyncOn(0)
-  ) u_prim_mubi4_sync_fw_ov_mode (
+  ) u_caliptra_prim_mubi4_sync_fw_ov_mode (
     .clk_i,
     .rst_ni,
     .mubi_i(mubi_fw_ov_mode),
@@ -684,10 +684,10 @@ module entropy_src_core import entropy_src_pkg::*; #(
   assign hw2reg.recov_alert_sts.fw_ov_entropy_insert_field_alert.de = fw_ov_entropy_insert_pfa;
   assign hw2reg.recov_alert_sts.fw_ov_entropy_insert_field_alert.d  = fw_ov_entropy_insert_pfa;
 
-  prim_mubi4_sync #(
+  caliptra_prim_mubi4_sync #(
     .NumCopies(2),
     .AsyncOn(0)
-  ) u_prim_mubi4_sync_fw_ov_entropy_insert (
+  ) u_caliptra_prim_mubi4_sync_fw_ov_entropy_insert (
     .clk_i,
     .rst_ni,
     .mubi_i(mubi_fw_ov_entropy_insert),
@@ -703,10 +703,10 @@ module entropy_src_core import entropy_src_pkg::*; #(
   assign hw2reg.recov_alert_sts.fw_ov_sha3_start_field_alert.de = fw_ov_sha3_start_pfa;
   assign hw2reg.recov_alert_sts.fw_ov_sha3_start_field_alert.d  = fw_ov_sha3_start_pfa;
 
-  prim_mubi4_sync #(
+  caliptra_prim_mubi4_sync #(
     .NumCopies(2),
     .AsyncOn(0)
-  ) u_prim_mubi4_sync_fw_ov_sha3_start (
+  ) u_caliptra_prim_mubi4_sync_fw_ov_sha3_start (
     .clk_i,
     .rst_ni,
     .mubi_i(mubi_fw_ov_sha3_start),
@@ -721,12 +721,12 @@ module entropy_src_core import entropy_src_pkg::*; #(
   assign fw_ov_fifo_wr_pulse = reg2hw.fw_ov_wr_data.qe;
   assign fw_ov_wr_data = reg2hw.fw_ov_wr_data.q;
 
-  assign efuse_es_sw_ov_en = prim_mubi_pkg::mubi8_test_true_strict(en_entropy_src_fw_over);
+  assign efuse_es_sw_ov_en = caliptra_prim_mubi_pkg::mubi8_test_true_strict(en_entropy_src_fw_over);
 
-  prim_mubi8_sync #(
+  caliptra_prim_mubi8_sync #(
     .NumCopies(1),
     .AsyncOn(1) // must be set to one, see note below
-  ) u_prim_mubi8_sync_es_fw_over (
+  ) u_caliptra_prim_mubi8_sync_es_fw_over (
     .clk_i,
     .rst_ni,
     .mubi_i(otp_en_entropy_src_fw_over_i),
@@ -749,7 +749,7 @@ module entropy_src_core import entropy_src_pkg::*; #(
   // instantiate interrupt hardware primitives
   //--------------------------------------------
 
-  prim_intr_hw #(
+  caliptra_prim_intr_hw #(
     .Width(1)
   ) u_intr_hw_es_entropy_valid (
     .clk_i                  (clk_i),
@@ -764,7 +764,7 @@ module entropy_src_core import entropy_src_pkg::*; #(
     .intr_o                 (intr_es_entropy_valid_o)
   );
 
-  prim_intr_hw #(
+  caliptra_prim_intr_hw #(
     .Width(1)
   ) u_intr_hw_es_health_test_failed (
     .clk_i                  (clk_i),
@@ -780,7 +780,7 @@ module entropy_src_core import entropy_src_pkg::*; #(
   );
 
 
-  prim_intr_hw #(
+  caliptra_prim_intr_hw #(
     .Width(1)
   ) u_intr_hw_es_observe_fifo_ready (
     .clk_i                  (clk_i),
@@ -795,7 +795,7 @@ module entropy_src_core import entropy_src_pkg::*; #(
     .intr_o                 (intr_es_observe_fifo_ready_o)
   );
 
-  prim_intr_hw #(
+  caliptra_prim_intr_hw #(
     .Width(1)
   ) u_intr_hw_es_fatal_err (
     .clk_i                  (clk_i),
@@ -827,7 +827,7 @@ module entropy_src_core import entropy_src_pkg::*; #(
                                   sfifo_test_err_sum) ) ||
                               es_ack_sm_err_sum ||
                               es_main_sm_err_sum ||
-                              es_cntr_err_sum || // prim_count err is always active
+                              es_cntr_err_sum || // caliptra_prim_count err is always active
                               sha3_rst_storage_err_sum ||
                               sha3_state_error_sum;
 
@@ -935,7 +935,7 @@ module entropy_src_core import entropy_src_pkg::*; #(
   assign hw2reg.debug_status.sha3_block_pr.d = sha3_block_processed;
   assign hw2reg.debug_status.sha3_squeezing.d = sha3_squeezing;
   assign hw2reg.debug_status.sha3_absorbed.d =
-    prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) ? 1'b 1 : 1'b 0;
+    caliptra_prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) ? 1'b 1 : 1'b 0;
   assign hw2reg.debug_status.sha3_err.d = sha3_err_q;
 
   assign sha3_err_d =
@@ -961,11 +961,11 @@ module entropy_src_core import entropy_src_pkg::*; #(
   //--------------------------------------------
 
 
-  prim_fifo_sync #(
+  caliptra_prim_fifo_sync #(
     .Width(RngBusWidth),
     .Pass(0),
     .Depth(2)
-  ) u_prim_fifo_sync_esrng (
+  ) u_caliptra_prim_fifo_sync_esrng (
     .clk_i      (clk_i),
     .rst_ni     (rst_ni),
     .clr_i      (sfifo_esrng_clr),
@@ -989,7 +989,7 @@ module entropy_src_core import entropy_src_pkg::*; #(
                                                                    pfifo_postht_not_full );
 
   // fifo err
-  // Note: for prim_fifo_sync is not an error to push to a fifo that is full.  In fact, the
+  // Note: for caliptra_prim_fifo_sync is not an error to push to a fifo that is full.  In fact, the
   // backpressure mechanism applied to the RNG inputs counts on this.
   assign sfifo_esrng_err =
          {1'b0,
@@ -1006,10 +1006,10 @@ module entropy_src_core import entropy_src_pkg::*; #(
   assign hw2reg.recov_alert_sts.rng_bit_enable_field_alert.de = rng_bit_enable_pfa;
   assign hw2reg.recov_alert_sts.rng_bit_enable_field_alert.d  = rng_bit_enable_pfa;
 
-  prim_mubi4_sync #(
+  caliptra_prim_mubi4_sync #(
     .NumCopies(2),
     .AsyncOn(0)
-  ) u_prim_mubi4_sync_rng_bit_en (
+  ) u_caliptra_prim_mubi4_sync_rng_bit_en (
     .clk_i,
     .rst_ni,
     .mubi_i(mubi_rng_bit_en),
@@ -1020,11 +1020,11 @@ module entropy_src_core import entropy_src_pkg::*; #(
   assign rng_bit_en = rng_bit_enable_pfe;
   assign rng_bit_sel = reg2hw.conf.rng_bit_sel.q;
 
-  prim_packer_fifo #(
+  caliptra_prim_packer_fifo #(
     .InW(1),
     .OutW(RngBusWidth),
     .ClearOnRead(1'b0)
-  ) u_prim_packer_fifo_esbit (
+  ) u_caliptra_prim_packer_fifo_esbit (
     .clk_i      (clk_i),
     .rst_ni     (rst_ni),
     .clr_i      (pfifo_esbit_clr),
@@ -1422,10 +1422,10 @@ module entropy_src_core import entropy_src_pkg::*; #(
   assign hw2reg.recov_alert_sts.es_route_field_alert.de = es_route_pfa;
   assign hw2reg.recov_alert_sts.es_route_field_alert.d  = es_route_pfa;
 
-  prim_mubi4_sync #(
+  caliptra_prim_mubi4_sync #(
     .NumCopies(2),
     .AsyncOn(0)
-  ) u_prim_mubi4_sync_es_route (
+  ) u_caliptra_prim_mubi4_sync_es_route (
     .clk_i,
     .rst_ni,
     .mubi_i(mubi_es_route),
@@ -1441,10 +1441,10 @@ module entropy_src_core import entropy_src_pkg::*; #(
   assign hw2reg.recov_alert_sts.es_type_field_alert.de = es_type_pfa;
   assign hw2reg.recov_alert_sts.es_type_field_alert.d  = es_type_pfa;
 
-  prim_mubi4_sync #(
+  caliptra_prim_mubi4_sync #(
     .NumCopies(2),
     .AsyncOn(0)
-  ) u_prim_mubi4_sync_es_type (
+  ) u_caliptra_prim_mubi4_sync_es_type (
     .clk_i,
     .rst_ni,
     .mubi_i(mubi_es_type),
@@ -1474,9 +1474,9 @@ module entropy_src_core import entropy_src_pkg::*; #(
 
   // Window counter
   // SEC_CM: CTR.REDUN
-  prim_count #(
+  caliptra_prim_count #(
     .Width(HalfRegWidth)
-  ) u_prim_count_window_cntr (
+  ) u_caliptra_prim_count_window_cntr (
     .clk_i,
     .rst_ni,
     .clr_i(!es_delayed_enable),
@@ -2079,11 +2079,11 @@ module entropy_src_core import entropy_src_pkg::*; #(
          (any_fail_count >= alert_threshold) && (alert_threshold != '0);
 
 
-  prim_edge_detector #(
+  caliptra_prim_edge_detector #(
     .Width(1),
     .ResetValue(0),
     .EnSync(0)
-  ) u_prim_edge_detector_recov_alert (
+  ) u_caliptra_prim_edge_detector_recov_alert (
     .clk_i,
     .rst_ni,
     .d_i(recov_alert_state),
@@ -2262,11 +2262,11 @@ module entropy_src_core import entropy_src_pkg::*; #(
   // pack tested entropy into 32 bit packer
   //--------------------------------------------
 
-  prim_packer_fifo #(
+  caliptra_prim_packer_fifo #(
     .InW(RngBusWidth),
     .OutW(PostHTWidth),
     .ClearOnRead(1'b0)
-  ) u_prim_packer_fifo_postht (
+  ) u_caliptra_prim_packer_fifo_postht (
     .clk_i      (clk_i),
     .rst_ni     (rst_ni),
     .clr_i      (pfifo_postht_clr),
@@ -2305,11 +2305,11 @@ module entropy_src_core import entropy_src_pkg::*; #(
   // store entropy into a 64 entry deep FIFO
   //--------------------------------------------
 
-  prim_fifo_sync #(
+  caliptra_prim_fifo_sync #(
     .Width(ObserveFifoWidth),
     .Pass(0),
     .Depth(ObserveFifoDepth)
-  ) u_prim_fifo_sync_observe (
+  ) u_caliptra_prim_fifo_sync_observe (
     .clk_i      (clk_i),
     .rst_ni     (rst_ni),
     .clr_i      (sfifo_observe_clr),
@@ -2373,11 +2373,11 @@ module entropy_src_core import entropy_src_pkg::*; #(
   // pack entropy into 64 bit packer
   //--------------------------------------------
 
-  prim_packer_fifo #(
+  caliptra_prim_packer_fifo #(
     .InW(ObserveFifoWidth),
     .OutW(PreCondWidth),
     .ClearOnRead(1'b0)
-  ) u_prim_packer_fifo_precon (
+  ) u_caliptra_prim_packer_fifo_precon (
     .clk_i      (clk_i),
     .rst_ni     (rst_ni),
     .clr_i      (pfifo_precon_clr),
@@ -2512,11 +2512,11 @@ module entropy_src_core import entropy_src_pkg::*; #(
   // bypass SHA conditioner path
   //--------------------------------------------
 
-  prim_packer_fifo #(
+  caliptra_prim_packer_fifo #(
      .InW(PostHTWidth),
      .OutW(SeedLen),
      .ClearOnRead(1'b0)
-  ) u_prim_packer_fifo_bypass (
+  ) u_caliptra_prim_packer_fifo_bypass (
     .clk_i      (clk_i),
     .rst_ni     (rst_ni),
     .clr_i      (pfifo_bypass_clr),
@@ -2645,11 +2645,11 @@ module entropy_src_core import entropy_src_pkg::*; #(
   // send processed entropy to final fifo
   //--------------------------------------------
 
-  prim_fifo_sync #(
+  caliptra_prim_fifo_sync #(
     .Width(1+SeedLen),
     .Pass(0),
     .Depth(EsFifoDepth)
-  ) u_prim_fifo_sync_esfinal (
+  ) u_caliptra_prim_fifo_sync_esfinal (
     .clk_i          (clk_i),
     .rst_ni         (rst_ni),
     .clr_i          (sfifo_esfinal_clr),
@@ -2679,7 +2679,7 @@ module entropy_src_core import entropy_src_pkg::*; #(
   assign {esfinal_fips_flag,esfinal_data} = sfifo_esfinal_rdata;
 
   // fifo err
-  // Note: for prim_fifo_sync is not an error to push to a fifo that is full.  In fact, the
+  // Note: for caliptra_prim_fifo_sync is not an error to push to a fifo that is full.  In fact, the
   // backpressure mechanism applied to the previous FIFO counts on this.
   assign sfifo_esfinal_err =
          {1'b0,
@@ -2733,11 +2733,11 @@ module entropy_src_core import entropy_src_pkg::*; #(
   // software es read path
   //--------------------------------------------
 
-  prim_packer_fifo #(
+  caliptra_prim_packer_fifo #(
     .InW(SeedLen),
     .OutW(FullRegWidth),
     .ClearOnRead(1'b0)
-  ) u_prim_packer_fifo_swread (
+  ) u_caliptra_prim_packer_fifo_swread (
     .clk_i      (clk_i),
     .rst_ni     (rst_ni),
     .clr_i      (pfifo_swread_clr),
@@ -2761,12 +2761,12 @@ module entropy_src_core import entropy_src_pkg::*; #(
   assign hw2reg.entropy_data.d = es_data_reg_rd_en ? pfifo_swread_rdata : '0;
   assign sw_es_rd_pulse = es_data_reg_rd_en && reg2hw.entropy_data.re;
 
-  assign efuse_es_sw_reg_en = prim_mubi_pkg::mubi8_test_true_strict(en_entropy_src_fw_read);
+  assign efuse_es_sw_reg_en = caliptra_prim_mubi_pkg::mubi8_test_true_strict(en_entropy_src_fw_read);
 
-  prim_mubi8_sync #(
+  caliptra_prim_mubi8_sync #(
     .NumCopies(1),
     .AsyncOn(1) // must be set to one, see note below
-  ) u_prim_mubi8_sync_es_fw_read (
+  ) u_caliptra_prim_mubi8_sync_es_fw_read (
     .clk_i,
     .rst_ni,
     .mubi_i(otp_en_entropy_src_fw_read_i),
diff --git a/src/entropy_src/rtl/entropy_src_enable_delay.sv b/src/entropy_src/rtl/entropy_src_enable_delay.sv
index dc23fbc45..aab25ab79 100644
--- a/src/entropy_src/rtl/entropy_src_enable_delay.sv
+++ b/src/entropy_src/rtl/entropy_src_enable_delay.sv
@@ -30,7 +30,7 @@
 //    2b. One clock after the SHA engine completes,
 //    Whichever comes later.
 
-module entropy_src_enable_delay import prim_mubi_pkg::*; (
+module entropy_src_enable_delay import caliptra_prim_mubi_pkg::*; (
   input logic  clk_i,
   input logic  rst_ni,
 
@@ -70,7 +70,7 @@ module entropy_src_enable_delay import prim_mubi_pkg::*; (
     if (!rst_ni) begin
       sha3_active_post_en_q   <= 1'b0;
       fifo_timer_q            <= '0;
-      sha3_done_q             <= prim_mubi_pkg::MuBi4False;
+      sha3_done_q             <= caliptra_prim_mubi_pkg::MuBi4False;
       extend_enable_q         <= 1'b0;
     end else begin
       sha3_active_post_en_q   <= sha3_active_post_en_d;
diff --git a/src/entropy_src/rtl/entropy_src_main_sm.sv b/src/entropy_src/rtl/entropy_src_main_sm.sv
index 23f397ebe..fd223f1bb 100644
--- a/src/entropy_src/rtl/entropy_src_main_sm.sv
+++ b/src/entropy_src/rtl/entropy_src_main_sm.sv
@@ -28,7 +28,7 @@ module entropy_src_main_sm
   output logic                  boot_phase_done_o,
   output logic                  sha3_start_o,
   output logic                  sha3_process_o,
-  output prim_mubi_pkg::mubi4_t sha3_done_o,
+  output caliptra_prim_mubi_pkg::mubi4_t sha3_done_o,
   output logic                  cs_aes_halt_req_o,
   input logic                   cs_aes_halt_ack_i,
   input logic                   local_escalate_i,
@@ -41,7 +41,7 @@ module entropy_src_main_sm
   // The definition of state_e, the sparse FSM state enum, is in entropy_src_main_sm_pkg.sv
   state_e state_d, state_q;
 
-  `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Idle)
+  `CALIPTRA_PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Idle)
 
   assign main_sm_state_o = state_q;
 
@@ -53,7 +53,7 @@ module entropy_src_main_sm
     boot_phase_done_o = 1'b0;
     sha3_start_o = 1'b0;
     sha3_process_o = 1'b0;
-    sha3_done_o = prim_mubi_pkg::MuBi4False;
+    sha3_done_o = caliptra_prim_mubi_pkg::MuBi4False;
     cs_aes_halt_req_o = 1'b0;
     main_sm_alert_o = 1'b0;
     main_sm_idle_o = 1'b0;
@@ -240,11 +240,11 @@ module entropy_src_main_sm
       end
       Sha3Done: begin
         if (!enable_i) begin
-          sha3_done_o = prim_mubi_pkg::MuBi4True;
+          sha3_done_o = caliptra_prim_mubi_pkg::MuBi4True;
           state_d = Sha3MsgDone;
         end else begin
           if (main_stage_rdy_i) begin
-            sha3_done_o = prim_mubi_pkg::MuBi4True;
+            sha3_done_o = caliptra_prim_mubi_pkg::MuBi4True;
             main_stage_push_o = 1'b1;
             state_d = Sha3MsgDone;
           end
diff --git a/src/entropy_src/rtl/entropy_src_markov_ht.sv b/src/entropy_src/rtl/entropy_src_markov_ht.sv
index 647669380..dd9ebfb01 100644
--- a/src/entropy_src/rtl/entropy_src_markov_ht.sv
+++ b/src/entropy_src/rtl/entropy_src_markov_ht.sv
@@ -70,9 +70,9 @@ module entropy_src_markov_ht #(
            (prev_sample_q[sh] == !entropy_bit_i[sh]);
 
     // pair counter
-    prim_count #(
+    caliptra_prim_count #(
       .Width(RegWidth)
-    ) u_prim_count_pair_cntr (
+    ) u_caliptra_prim_count_pair_cntr (
       .clk_i,
       .rst_ni,
       .clr_i(window_wrap_pulse_i),
@@ -94,7 +94,7 @@ module entropy_src_markov_ht #(
                     toggle_q;
 
   // determine the highest counter pair counter value
-  prim_max_tree #(
+  caliptra_prim_max_tree #(
     .NumSrc(RngBusWidth),
     .Width(RegWidth)
   ) u_max (
@@ -108,9 +108,9 @@ module entropy_src_markov_ht #(
   );
 
   // determine the lowest counter pair counter value
-  // Negate the inputs and outputs of prim_max_tree to find the minimum
+  // Negate the inputs and outputs of caliptra_prim_max_tree to find the minimum
   // For this unsigned application, one's complement negation (i.e. logical inversion) is fine.
-  prim_max_tree #(
+  caliptra_prim_max_tree #(
     .NumSrc(RngBusWidth),
     .Width(RegWidth)
   ) u_min (
@@ -126,7 +126,7 @@ module entropy_src_markov_ht #(
   // Invert the output back.
   assign pair_cntr_min = ~pair_cntr_min_tmp;
 
-  prim_sum_tree #(
+  caliptra_prim_sum_tree #(
     .NumSrc(RngBusWidth),
     .Width(RegWidth)
   ) u_sum (
diff --git a/src/entropy_src/rtl/entropy_src_reg_top.sv b/src/entropy_src/rtl/entropy_src_reg_top.sv
index e50577687..e443608a4 100644
--- a/src/entropy_src/rtl/entropy_src_reg_top.sv
+++ b/src/entropy_src/rtl/entropy_src_reg_top.sv
@@ -4,7 +4,7 @@
 //
 // Register Top module auto-generated by `reggen`
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
 module entropy_src_reg_top #(
     parameter AHBDataWidth = 64,
@@ -67,9 +67,9 @@ module entropy_src_reg_top #(
   // also check for spurious write enables
   logic reg_we_err;
   logic [56:0] reg_we_check;
-  prim_reg_we_check #(
+  caliptra_prim_reg_we_check #(
     .OneHotWidth(57)
-  ) u_prim_reg_we_check (
+  ) u_caliptra_prim_reg_we_check (
     .clk_i(clk_i),
     .rst_ni(rst_ni),
     .oh_i  (reg_we_check),
@@ -409,9 +409,9 @@ module entropy_src_reg_top #(
   // Register instances
   // R[intr_state]: V(False)
   //   F[es_entropy_valid]: 0:0
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW1C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_intr_state_es_entropy_valid (
     .clk_i   (clk_i),
@@ -435,9 +435,9 @@ module entropy_src_reg_top #(
   );
 
   //   F[es_health_test_failed]: 1:1
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW1C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_intr_state_es_health_test_failed (
     .clk_i   (clk_i),
@@ -461,9 +461,9 @@ module entropy_src_reg_top #(
   );
 
   //   F[es_observe_fifo_ready]: 2:2
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW1C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_intr_state_es_observe_fifo_ready (
     .clk_i   (clk_i),
@@ -487,9 +487,9 @@ module entropy_src_reg_top #(
   );
 
   //   F[es_fatal_err]: 3:3
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW1C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_intr_state_es_fatal_err (
     .clk_i   (clk_i),
@@ -515,9 +515,9 @@ module entropy_src_reg_top #(
 
   // R[intr_enable]: V(False)
   //   F[es_entropy_valid]: 0:0
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_intr_enable_es_entropy_valid (
     .clk_i   (clk_i),
@@ -541,9 +541,9 @@ module entropy_src_reg_top #(
   );
 
   //   F[es_health_test_failed]: 1:1
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_intr_enable_es_health_test_failed (
     .clk_i   (clk_i),
@@ -567,9 +567,9 @@ module entropy_src_reg_top #(
   );
 
   //   F[es_observe_fifo_ready]: 2:2
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_intr_enable_es_observe_fifo_ready (
     .clk_i   (clk_i),
@@ -593,9 +593,9 @@ module entropy_src_reg_top #(
   );
 
   //   F[es_fatal_err]: 3:3
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_intr_enable_es_fatal_err (
     .clk_i   (clk_i),
@@ -624,7 +624,7 @@ module entropy_src_reg_top #(
   logic [3:0] intr_test_flds_we;
   assign intr_test_qe = &intr_test_flds_we;
   //   F[es_entropy_valid]: 0:0
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (1)
   ) u_intr_test_es_entropy_valid (
     .re     (1'b0),
@@ -640,7 +640,7 @@ module entropy_src_reg_top #(
   assign reg2hw.intr_test.es_entropy_valid.qe = intr_test_qe;
 
   //   F[es_health_test_failed]: 1:1
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (1)
   ) u_intr_test_es_health_test_failed (
     .re     (1'b0),
@@ -656,7 +656,7 @@ module entropy_src_reg_top #(
   assign reg2hw.intr_test.es_health_test_failed.qe = intr_test_qe;
 
   //   F[es_observe_fifo_ready]: 2:2
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (1)
   ) u_intr_test_es_observe_fifo_ready (
     .re     (1'b0),
@@ -672,7 +672,7 @@ module entropy_src_reg_top #(
   assign reg2hw.intr_test.es_observe_fifo_ready.qe = intr_test_qe;
 
   //   F[es_fatal_err]: 3:3
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (1)
   ) u_intr_test_es_fatal_err (
     .re     (1'b0),
@@ -693,7 +693,7 @@ module entropy_src_reg_top #(
   logic [1:0] alert_test_flds_we;
   assign alert_test_qe = &alert_test_flds_we;
   //   F[recov_alert]: 0:0
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (1)
   ) u_alert_test_recov_alert (
     .re     (1'b0),
@@ -709,7 +709,7 @@ module entropy_src_reg_top #(
   assign reg2hw.alert_test.recov_alert.qe = alert_test_qe;
 
   //   F[fatal_alert]: 1:1
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (1)
   ) u_alert_test_fatal_alert (
     .re     (1'b0),
@@ -726,9 +726,9 @@ module entropy_src_reg_top #(
 
 
   // R[me_regwen]: V(False)
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW0C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW0C),
     .RESVAL  (1'h1)
   ) u_me_regwen (
     .clk_i   (clk_i),
@@ -753,9 +753,9 @@ module entropy_src_reg_top #(
 
 
   // R[sw_regupd]: V(False)
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW0C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW0C),
     .RESVAL  (1'h1)
   ) u_sw_regupd (
     .clk_i   (clk_i),
@@ -780,9 +780,9 @@ module entropy_src_reg_top #(
 
 
   // R[regwen]: V(False)
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h1)
   ) u_regwen (
     .clk_i   (clk_i),
@@ -824,9 +824,9 @@ module entropy_src_reg_top #(
   // Create REGWEN-gated WE signal
   logic module_enable_gated_we;
   assign module_enable_gated_we = module_enable_we & me_regwen_qs;
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (4),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (4'h9)
   ) u_module_enable (
     .clk_i   (clk_i),
@@ -855,9 +855,9 @@ module entropy_src_reg_top #(
   logic conf_gated_we;
   assign conf_gated_we = conf_we & regwen_qs;
   //   F[fips_enable]: 3:0
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (4),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (4'h9)
   ) u_conf_fips_enable (
     .clk_i   (clk_i),
@@ -881,9 +881,9 @@ module entropy_src_reg_top #(
   );
 
   //   F[entropy_data_reg_enable]: 7:4
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (4),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (4'h9)
   ) u_conf_entropy_data_reg_enable (
     .clk_i   (clk_i),
@@ -907,9 +907,9 @@ module entropy_src_reg_top #(
   );
 
   //   F[threshold_scope]: 15:12
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (4),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (4'h9)
   ) u_conf_threshold_scope (
     .clk_i   (clk_i),
@@ -933,9 +933,9 @@ module entropy_src_reg_top #(
   );
 
   //   F[rng_bit_enable]: 23:20
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (4),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (4'h9)
   ) u_conf_rng_bit_enable (
     .clk_i   (clk_i),
@@ -959,9 +959,9 @@ module entropy_src_reg_top #(
   );
 
   //   F[rng_bit_sel]: 25:24
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (2),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (2'h0)
   ) u_conf_rng_bit_sel (
     .clk_i   (clk_i),
@@ -990,9 +990,9 @@ module entropy_src_reg_top #(
   logic entropy_control_gated_we;
   assign entropy_control_gated_we = entropy_control_we & regwen_qs;
   //   F[es_route]: 3:0
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (4),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (4'h9)
   ) u_entropy_control_es_route (
     .clk_i   (clk_i),
@@ -1016,9 +1016,9 @@ module entropy_src_reg_top #(
   );
 
   //   F[es_type]: 7:4
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (4),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (4'h9)
   ) u_entropy_control_es_type (
     .clk_i   (clk_i),
@@ -1043,7 +1043,7 @@ module entropy_src_reg_top #(
 
 
   // R[entropy_data]: V(True)
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (32)
   ) u_entropy_data (
     .re     (entropy_data_re),
@@ -1063,9 +1063,9 @@ module entropy_src_reg_top #(
   logic health_test_windows_gated_we;
   assign health_test_windows_gated_we = health_test_windows_we & regwen_qs;
   //   F[fips_window]: 15:0
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (16),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (16'h200)
   ) u_health_test_windows_fips_window (
     .clk_i   (clk_i),
@@ -1089,9 +1089,9 @@ module entropy_src_reg_top #(
   );
 
   //   F[bypass_window]: 31:16
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (16),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (16'h60)
   ) u_health_test_windows_bypass_window (
     .clk_i   (clk_i),
@@ -1123,7 +1123,7 @@ module entropy_src_reg_top #(
   logic repcnt_thresholds_gated_we;
   assign repcnt_thresholds_gated_we = repcnt_thresholds_we & regwen_qs;
   //   F[fips_thresh]: 15:0
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (16)
   ) u_repcnt_thresholds_fips_thresh (
     .re     (repcnt_thresholds_re),
@@ -1139,7 +1139,7 @@ module entropy_src_reg_top #(
   assign reg2hw.repcnt_thresholds.fips_thresh.qe = repcnt_thresholds_qe;
 
   //   F[bypass_thresh]: 31:16
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (16)
   ) u_repcnt_thresholds_bypass_thresh (
     .re     (repcnt_thresholds_re),
@@ -1163,7 +1163,7 @@ module entropy_src_reg_top #(
   logic repcnts_thresholds_gated_we;
   assign repcnts_thresholds_gated_we = repcnts_thresholds_we & regwen_qs;
   //   F[fips_thresh]: 15:0
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (16)
   ) u_repcnts_thresholds_fips_thresh (
     .re     (repcnts_thresholds_re),
@@ -1179,7 +1179,7 @@ module entropy_src_reg_top #(
   assign reg2hw.repcnts_thresholds.fips_thresh.qe = repcnts_thresholds_qe;
 
   //   F[bypass_thresh]: 31:16
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (16)
   ) u_repcnts_thresholds_bypass_thresh (
     .re     (repcnts_thresholds_re),
@@ -1203,7 +1203,7 @@ module entropy_src_reg_top #(
   logic adaptp_hi_thresholds_gated_we;
   assign adaptp_hi_thresholds_gated_we = adaptp_hi_thresholds_we & regwen_qs;
   //   F[fips_thresh]: 15:0
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (16)
   ) u_adaptp_hi_thresholds_fips_thresh (
     .re     (adaptp_hi_thresholds_re),
@@ -1219,7 +1219,7 @@ module entropy_src_reg_top #(
   assign reg2hw.adaptp_hi_thresholds.fips_thresh.qe = adaptp_hi_thresholds_qe;
 
   //   F[bypass_thresh]: 31:16
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (16)
   ) u_adaptp_hi_thresholds_bypass_thresh (
     .re     (adaptp_hi_thresholds_re),
@@ -1243,7 +1243,7 @@ module entropy_src_reg_top #(
   logic adaptp_lo_thresholds_gated_we;
   assign adaptp_lo_thresholds_gated_we = adaptp_lo_thresholds_we & regwen_qs;
   //   F[fips_thresh]: 15:0
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (16)
   ) u_adaptp_lo_thresholds_fips_thresh (
     .re     (adaptp_lo_thresholds_re),
@@ -1259,7 +1259,7 @@ module entropy_src_reg_top #(
   assign reg2hw.adaptp_lo_thresholds.fips_thresh.qe = adaptp_lo_thresholds_qe;
 
   //   F[bypass_thresh]: 31:16
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (16)
   ) u_adaptp_lo_thresholds_bypass_thresh (
     .re     (adaptp_lo_thresholds_re),
@@ -1283,7 +1283,7 @@ module entropy_src_reg_top #(
   logic bucket_thresholds_gated_we;
   assign bucket_thresholds_gated_we = bucket_thresholds_we & regwen_qs;
   //   F[fips_thresh]: 15:0
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (16)
   ) u_bucket_thresholds_fips_thresh (
     .re     (bucket_thresholds_re),
@@ -1299,7 +1299,7 @@ module entropy_src_reg_top #(
   assign reg2hw.bucket_thresholds.fips_thresh.qe = bucket_thresholds_qe;
 
   //   F[bypass_thresh]: 31:16
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (16)
   ) u_bucket_thresholds_bypass_thresh (
     .re     (bucket_thresholds_re),
@@ -1323,7 +1323,7 @@ module entropy_src_reg_top #(
   logic markov_hi_thresholds_gated_we;
   assign markov_hi_thresholds_gated_we = markov_hi_thresholds_we & regwen_qs;
   //   F[fips_thresh]: 15:0
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (16)
   ) u_markov_hi_thresholds_fips_thresh (
     .re     (markov_hi_thresholds_re),
@@ -1339,7 +1339,7 @@ module entropy_src_reg_top #(
   assign reg2hw.markov_hi_thresholds.fips_thresh.qe = markov_hi_thresholds_qe;
 
   //   F[bypass_thresh]: 31:16
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (16)
   ) u_markov_hi_thresholds_bypass_thresh (
     .re     (markov_hi_thresholds_re),
@@ -1363,7 +1363,7 @@ module entropy_src_reg_top #(
   logic markov_lo_thresholds_gated_we;
   assign markov_lo_thresholds_gated_we = markov_lo_thresholds_we & regwen_qs;
   //   F[fips_thresh]: 15:0
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (16)
   ) u_markov_lo_thresholds_fips_thresh (
     .re     (markov_lo_thresholds_re),
@@ -1379,7 +1379,7 @@ module entropy_src_reg_top #(
   assign reg2hw.markov_lo_thresholds.fips_thresh.qe = markov_lo_thresholds_qe;
 
   //   F[bypass_thresh]: 31:16
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (16)
   ) u_markov_lo_thresholds_bypass_thresh (
     .re     (markov_lo_thresholds_re),
@@ -1403,7 +1403,7 @@ module entropy_src_reg_top #(
   logic extht_hi_thresholds_gated_we;
   assign extht_hi_thresholds_gated_we = extht_hi_thresholds_we & regwen_qs;
   //   F[fips_thresh]: 15:0
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (16)
   ) u_extht_hi_thresholds_fips_thresh (
     .re     (extht_hi_thresholds_re),
@@ -1419,7 +1419,7 @@ module entropy_src_reg_top #(
   assign reg2hw.extht_hi_thresholds.fips_thresh.qe = extht_hi_thresholds_qe;
 
   //   F[bypass_thresh]: 31:16
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (16)
   ) u_extht_hi_thresholds_bypass_thresh (
     .re     (extht_hi_thresholds_re),
@@ -1443,7 +1443,7 @@ module entropy_src_reg_top #(
   logic extht_lo_thresholds_gated_we;
   assign extht_lo_thresholds_gated_we = extht_lo_thresholds_we & regwen_qs;
   //   F[fips_thresh]: 15:0
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (16)
   ) u_extht_lo_thresholds_fips_thresh (
     .re     (extht_lo_thresholds_re),
@@ -1459,7 +1459,7 @@ module entropy_src_reg_top #(
   assign reg2hw.extht_lo_thresholds.fips_thresh.qe = extht_lo_thresholds_qe;
 
   //   F[bypass_thresh]: 31:16
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (16)
   ) u_extht_lo_thresholds_bypass_thresh (
     .re     (extht_lo_thresholds_re),
@@ -1477,7 +1477,7 @@ module entropy_src_reg_top #(
 
   // R[repcnt_hi_watermarks]: V(True)
   //   F[fips_watermark]: 15:0
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (16)
   ) u_repcnt_hi_watermarks_fips_watermark (
     .re     (repcnt_hi_watermarks_re),
@@ -1492,7 +1492,7 @@ module entropy_src_reg_top #(
   );
 
   //   F[bypass_watermark]: 31:16
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (16)
   ) u_repcnt_hi_watermarks_bypass_watermark (
     .re     (repcnt_hi_watermarks_re),
@@ -1509,7 +1509,7 @@ module entropy_src_reg_top #(
 
   // R[repcnts_hi_watermarks]: V(True)
   //   F[fips_watermark]: 15:0
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (16)
   ) u_repcnts_hi_watermarks_fips_watermark (
     .re     (repcnts_hi_watermarks_re),
@@ -1524,7 +1524,7 @@ module entropy_src_reg_top #(
   );
 
   //   F[bypass_watermark]: 31:16
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (16)
   ) u_repcnts_hi_watermarks_bypass_watermark (
     .re     (repcnts_hi_watermarks_re),
@@ -1541,7 +1541,7 @@ module entropy_src_reg_top #(
 
   // R[adaptp_hi_watermarks]: V(True)
   //   F[fips_watermark]: 15:0
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (16)
   ) u_adaptp_hi_watermarks_fips_watermark (
     .re     (adaptp_hi_watermarks_re),
@@ -1556,7 +1556,7 @@ module entropy_src_reg_top #(
   );
 
   //   F[bypass_watermark]: 31:16
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (16)
   ) u_adaptp_hi_watermarks_bypass_watermark (
     .re     (adaptp_hi_watermarks_re),
@@ -1573,7 +1573,7 @@ module entropy_src_reg_top #(
 
   // R[adaptp_lo_watermarks]: V(True)
   //   F[fips_watermark]: 15:0
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (16)
   ) u_adaptp_lo_watermarks_fips_watermark (
     .re     (adaptp_lo_watermarks_re),
@@ -1588,7 +1588,7 @@ module entropy_src_reg_top #(
   );
 
   //   F[bypass_watermark]: 31:16
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (16)
   ) u_adaptp_lo_watermarks_bypass_watermark (
     .re     (adaptp_lo_watermarks_re),
@@ -1605,7 +1605,7 @@ module entropy_src_reg_top #(
 
   // R[extht_hi_watermarks]: V(True)
   //   F[fips_watermark]: 15:0
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (16)
   ) u_extht_hi_watermarks_fips_watermark (
     .re     (extht_hi_watermarks_re),
@@ -1620,7 +1620,7 @@ module entropy_src_reg_top #(
   );
 
   //   F[bypass_watermark]: 31:16
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (16)
   ) u_extht_hi_watermarks_bypass_watermark (
     .re     (extht_hi_watermarks_re),
@@ -1637,7 +1637,7 @@ module entropy_src_reg_top #(
 
   // R[extht_lo_watermarks]: V(True)
   //   F[fips_watermark]: 15:0
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (16)
   ) u_extht_lo_watermarks_fips_watermark (
     .re     (extht_lo_watermarks_re),
@@ -1652,7 +1652,7 @@ module entropy_src_reg_top #(
   );
 
   //   F[bypass_watermark]: 31:16
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (16)
   ) u_extht_lo_watermarks_bypass_watermark (
     .re     (extht_lo_watermarks_re),
@@ -1669,7 +1669,7 @@ module entropy_src_reg_top #(
 
   // R[bucket_hi_watermarks]: V(True)
   //   F[fips_watermark]: 15:0
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (16)
   ) u_bucket_hi_watermarks_fips_watermark (
     .re     (bucket_hi_watermarks_re),
@@ -1684,7 +1684,7 @@ module entropy_src_reg_top #(
   );
 
   //   F[bypass_watermark]: 31:16
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (16)
   ) u_bucket_hi_watermarks_bypass_watermark (
     .re     (bucket_hi_watermarks_re),
@@ -1701,7 +1701,7 @@ module entropy_src_reg_top #(
 
   // R[markov_hi_watermarks]: V(True)
   //   F[fips_watermark]: 15:0
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (16)
   ) u_markov_hi_watermarks_fips_watermark (
     .re     (markov_hi_watermarks_re),
@@ -1716,7 +1716,7 @@ module entropy_src_reg_top #(
   );
 
   //   F[bypass_watermark]: 31:16
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (16)
   ) u_markov_hi_watermarks_bypass_watermark (
     .re     (markov_hi_watermarks_re),
@@ -1733,7 +1733,7 @@ module entropy_src_reg_top #(
 
   // R[markov_lo_watermarks]: V(True)
   //   F[fips_watermark]: 15:0
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (16)
   ) u_markov_lo_watermarks_fips_watermark (
     .re     (markov_lo_watermarks_re),
@@ -1748,7 +1748,7 @@ module entropy_src_reg_top #(
   );
 
   //   F[bypass_watermark]: 31:16
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (16)
   ) u_markov_lo_watermarks_bypass_watermark (
     .re     (markov_lo_watermarks_re),
@@ -1764,7 +1764,7 @@ module entropy_src_reg_top #(
 
 
   // R[repcnt_total_fails]: V(True)
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (32)
   ) u_repcnt_total_fails (
     .re     (repcnt_total_fails_re),
@@ -1780,7 +1780,7 @@ module entropy_src_reg_top #(
 
 
   // R[repcnts_total_fails]: V(True)
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (32)
   ) u_repcnts_total_fails (
     .re     (repcnts_total_fails_re),
@@ -1796,7 +1796,7 @@ module entropy_src_reg_top #(
 
 
   // R[adaptp_hi_total_fails]: V(True)
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (32)
   ) u_adaptp_hi_total_fails (
     .re     (adaptp_hi_total_fails_re),
@@ -1812,7 +1812,7 @@ module entropy_src_reg_top #(
 
 
   // R[adaptp_lo_total_fails]: V(True)
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (32)
   ) u_adaptp_lo_total_fails (
     .re     (adaptp_lo_total_fails_re),
@@ -1828,7 +1828,7 @@ module entropy_src_reg_top #(
 
 
   // R[bucket_total_fails]: V(True)
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (32)
   ) u_bucket_total_fails (
     .re     (bucket_total_fails_re),
@@ -1844,7 +1844,7 @@ module entropy_src_reg_top #(
 
 
   // R[markov_hi_total_fails]: V(True)
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (32)
   ) u_markov_hi_total_fails (
     .re     (markov_hi_total_fails_re),
@@ -1860,7 +1860,7 @@ module entropy_src_reg_top #(
 
 
   // R[markov_lo_total_fails]: V(True)
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (32)
   ) u_markov_lo_total_fails (
     .re     (markov_lo_total_fails_re),
@@ -1876,7 +1876,7 @@ module entropy_src_reg_top #(
 
 
   // R[extht_hi_total_fails]: V(True)
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (32)
   ) u_extht_hi_total_fails (
     .re     (extht_hi_total_fails_re),
@@ -1892,7 +1892,7 @@ module entropy_src_reg_top #(
 
 
   // R[extht_lo_total_fails]: V(True)
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (32)
   ) u_extht_lo_total_fails (
     .re     (extht_lo_total_fails_re),
@@ -1912,9 +1912,9 @@ module entropy_src_reg_top #(
   logic alert_threshold_gated_we;
   assign alert_threshold_gated_we = alert_threshold_we & regwen_qs;
   //   F[alert_threshold]: 15:0
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (16),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (16'h2)
   ) u_alert_threshold_alert_threshold (
     .clk_i   (clk_i),
@@ -1938,9 +1938,9 @@ module entropy_src_reg_top #(
   );
 
   //   F[alert_threshold_inv]: 31:16
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (16),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (16'hfffd)
   ) u_alert_threshold_alert_threshold_inv (
     .clk_i   (clk_i),
@@ -1965,7 +1965,7 @@ module entropy_src_reg_top #(
 
 
   // R[alert_summary_fail_counts]: V(True)
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (16)
   ) u_alert_summary_fail_counts (
     .re     (alert_summary_fail_counts_re),
@@ -1982,7 +1982,7 @@ module entropy_src_reg_top #(
 
   // R[alert_fail_counts]: V(True)
   //   F[repcnt_fail_count]: 7:4
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (4)
   ) u_alert_fail_counts_repcnt_fail_count (
     .re     (alert_fail_counts_re),
@@ -1997,7 +1997,7 @@ module entropy_src_reg_top #(
   );
 
   //   F[adaptp_hi_fail_count]: 11:8
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (4)
   ) u_alert_fail_counts_adaptp_hi_fail_count (
     .re     (alert_fail_counts_re),
@@ -2012,7 +2012,7 @@ module entropy_src_reg_top #(
   );
 
   //   F[adaptp_lo_fail_count]: 15:12
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (4)
   ) u_alert_fail_counts_adaptp_lo_fail_count (
     .re     (alert_fail_counts_re),
@@ -2027,7 +2027,7 @@ module entropy_src_reg_top #(
   );
 
   //   F[bucket_fail_count]: 19:16
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (4)
   ) u_alert_fail_counts_bucket_fail_count (
     .re     (alert_fail_counts_re),
@@ -2042,7 +2042,7 @@ module entropy_src_reg_top #(
   );
 
   //   F[markov_hi_fail_count]: 23:20
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (4)
   ) u_alert_fail_counts_markov_hi_fail_count (
     .re     (alert_fail_counts_re),
@@ -2057,7 +2057,7 @@ module entropy_src_reg_top #(
   );
 
   //   F[markov_lo_fail_count]: 27:24
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (4)
   ) u_alert_fail_counts_markov_lo_fail_count (
     .re     (alert_fail_counts_re),
@@ -2072,7 +2072,7 @@ module entropy_src_reg_top #(
   );
 
   //   F[repcnts_fail_count]: 31:28
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (4)
   ) u_alert_fail_counts_repcnts_fail_count (
     .re     (alert_fail_counts_re),
@@ -2089,7 +2089,7 @@ module entropy_src_reg_top #(
 
   // R[extht_fail_counts]: V(True)
   //   F[extht_hi_fail_count]: 3:0
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (4)
   ) u_extht_fail_counts_extht_hi_fail_count (
     .re     (extht_fail_counts_re),
@@ -2104,7 +2104,7 @@ module entropy_src_reg_top #(
   );
 
   //   F[extht_lo_fail_count]: 7:4
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (4)
   ) u_extht_fail_counts_extht_lo_fail_count (
     .re     (extht_fail_counts_re),
@@ -2124,9 +2124,9 @@ module entropy_src_reg_top #(
   logic fw_ov_control_gated_we;
   assign fw_ov_control_gated_we = fw_ov_control_we & regwen_qs;
   //   F[fw_ov_mode]: 3:0
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (4),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (4'h9)
   ) u_fw_ov_control_fw_ov_mode (
     .clk_i   (clk_i),
@@ -2150,9 +2150,9 @@ module entropy_src_reg_top #(
   );
 
   //   F[fw_ov_entropy_insert]: 7:4
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (4),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (4'h9)
   ) u_fw_ov_control_fw_ov_entropy_insert (
     .clk_i   (clk_i),
@@ -2177,9 +2177,9 @@ module entropy_src_reg_top #(
 
 
   // R[fw_ov_sha3_start]: V(False)
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (4),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (4'h9)
   ) u_fw_ov_sha3_start (
     .clk_i   (clk_i),
@@ -2204,7 +2204,7 @@ module entropy_src_reg_top #(
 
 
   // R[fw_ov_wr_fifo_full]: V(True)
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (1)
   ) u_fw_ov_wr_fifo_full (
     .re     (fw_ov_wr_fifo_full_re),
@@ -2220,9 +2220,9 @@ module entropy_src_reg_top #(
 
 
   // R[fw_ov_rd_fifo_overflow]: V(False)
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW0C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW0C),
     .RESVAL  (1'h0)
   ) u_fw_ov_rd_fifo_overflow (
     .clk_i   (clk_i),
@@ -2247,7 +2247,7 @@ module entropy_src_reg_top #(
 
 
   // R[fw_ov_rd_data]: V(True)
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (32)
   ) u_fw_ov_rd_data (
     .re     (fw_ov_rd_data_re),
@@ -2266,7 +2266,7 @@ module entropy_src_reg_top #(
   logic fw_ov_wr_data_qe;
   logic [0:0] fw_ov_wr_data_flds_we;
   assign fw_ov_wr_data_qe = &fw_ov_wr_data_flds_we;
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (32)
   ) u_fw_ov_wr_data (
     .re     (1'b0),
@@ -2286,9 +2286,9 @@ module entropy_src_reg_top #(
   // Create REGWEN-gated WE signal
   logic observe_fifo_thresh_gated_we;
   assign observe_fifo_thresh_gated_we = observe_fifo_thresh_we & regwen_qs;
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (7),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (7'h20)
   ) u_observe_fifo_thresh (
     .clk_i   (clk_i),
@@ -2313,7 +2313,7 @@ module entropy_src_reg_top #(
 
 
   // R[observe_fifo_depth]: V(True)
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (7)
   ) u_observe_fifo_depth (
     .re     (observe_fifo_depth_re),
@@ -2330,7 +2330,7 @@ module entropy_src_reg_top #(
 
   // R[debug_status]: V(True)
   //   F[entropy_fifo_depth]: 2:0
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (3)
   ) u_debug_status_entropy_fifo_depth (
     .re     (debug_status_re),
@@ -2345,7 +2345,7 @@ module entropy_src_reg_top #(
   );
 
   //   F[sha3_fsm]: 5:3
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (3)
   ) u_debug_status_sha3_fsm (
     .re     (debug_status_re),
@@ -2360,7 +2360,7 @@ module entropy_src_reg_top #(
   );
 
   //   F[sha3_block_pr]: 6:6
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (1)
   ) u_debug_status_sha3_block_pr (
     .re     (debug_status_re),
@@ -2375,7 +2375,7 @@ module entropy_src_reg_top #(
   );
 
   //   F[sha3_squeezing]: 7:7
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (1)
   ) u_debug_status_sha3_squeezing (
     .re     (debug_status_re),
@@ -2390,7 +2390,7 @@ module entropy_src_reg_top #(
   );
 
   //   F[sha3_absorbed]: 8:8
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (1)
   ) u_debug_status_sha3_absorbed (
     .re     (debug_status_re),
@@ -2405,7 +2405,7 @@ module entropy_src_reg_top #(
   );
 
   //   F[sha3_err]: 9:9
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (1)
   ) u_debug_status_sha3_err (
     .re     (debug_status_re),
@@ -2420,7 +2420,7 @@ module entropy_src_reg_top #(
   );
 
   //   F[main_sm_idle]: 16:16
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (1)
   ) u_debug_status_main_sm_idle (
     .re     (debug_status_re),
@@ -2435,7 +2435,7 @@ module entropy_src_reg_top #(
   );
 
   //   F[main_sm_boot_done]: 17:17
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (1)
   ) u_debug_status_main_sm_boot_done (
     .re     (debug_status_re),
@@ -2452,9 +2452,9 @@ module entropy_src_reg_top #(
 
   // R[recov_alert_sts]: V(False)
   //   F[fips_enable_field_alert]: 0:0
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW0C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW0C),
     .RESVAL  (1'h0)
   ) u_recov_alert_sts_fips_enable_field_alert (
     .clk_i   (clk_i),
@@ -2478,9 +2478,9 @@ module entropy_src_reg_top #(
   );
 
   //   F[entropy_data_reg_en_field_alert]: 1:1
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW0C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW0C),
     .RESVAL  (1'h0)
   ) u_recov_alert_sts_entropy_data_reg_en_field_alert (
     .clk_i   (clk_i),
@@ -2504,9 +2504,9 @@ module entropy_src_reg_top #(
   );
 
   //   F[module_enable_field_alert]: 2:2
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW0C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW0C),
     .RESVAL  (1'h0)
   ) u_recov_alert_sts_module_enable_field_alert (
     .clk_i   (clk_i),
@@ -2530,9 +2530,9 @@ module entropy_src_reg_top #(
   );
 
   //   F[threshold_scope_field_alert]: 3:3
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW0C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW0C),
     .RESVAL  (1'h0)
   ) u_recov_alert_sts_threshold_scope_field_alert (
     .clk_i   (clk_i),
@@ -2556,9 +2556,9 @@ module entropy_src_reg_top #(
   );
 
   //   F[rng_bit_enable_field_alert]: 5:5
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW0C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW0C),
     .RESVAL  (1'h0)
   ) u_recov_alert_sts_rng_bit_enable_field_alert (
     .clk_i   (clk_i),
@@ -2582,9 +2582,9 @@ module entropy_src_reg_top #(
   );
 
   //   F[fw_ov_sha3_start_field_alert]: 7:7
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW0C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW0C),
     .RESVAL  (1'h0)
   ) u_recov_alert_sts_fw_ov_sha3_start_field_alert (
     .clk_i   (clk_i),
@@ -2608,9 +2608,9 @@ module entropy_src_reg_top #(
   );
 
   //   F[fw_ov_mode_field_alert]: 8:8
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW0C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW0C),
     .RESVAL  (1'h0)
   ) u_recov_alert_sts_fw_ov_mode_field_alert (
     .clk_i   (clk_i),
@@ -2634,9 +2634,9 @@ module entropy_src_reg_top #(
   );
 
   //   F[fw_ov_entropy_insert_field_alert]: 9:9
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW0C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW0C),
     .RESVAL  (1'h0)
   ) u_recov_alert_sts_fw_ov_entropy_insert_field_alert (
     .clk_i   (clk_i),
@@ -2660,9 +2660,9 @@ module entropy_src_reg_top #(
   );
 
   //   F[es_route_field_alert]: 10:10
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW0C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW0C),
     .RESVAL  (1'h0)
   ) u_recov_alert_sts_es_route_field_alert (
     .clk_i   (clk_i),
@@ -2686,9 +2686,9 @@ module entropy_src_reg_top #(
   );
 
   //   F[es_type_field_alert]: 11:11
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW0C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW0C),
     .RESVAL  (1'h0)
   ) u_recov_alert_sts_es_type_field_alert (
     .clk_i   (clk_i),
@@ -2712,9 +2712,9 @@ module entropy_src_reg_top #(
   );
 
   //   F[es_main_sm_alert]: 12:12
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW0C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW0C),
     .RESVAL  (1'h0)
   ) u_recov_alert_sts_es_main_sm_alert (
     .clk_i   (clk_i),
@@ -2738,9 +2738,9 @@ module entropy_src_reg_top #(
   );
 
   //   F[es_bus_cmp_alert]: 13:13
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW0C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW0C),
     .RESVAL  (1'h0)
   ) u_recov_alert_sts_es_bus_cmp_alert (
     .clk_i   (clk_i),
@@ -2764,9 +2764,9 @@ module entropy_src_reg_top #(
   );
 
   //   F[es_thresh_cfg_alert]: 14:14
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW0C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW0C),
     .RESVAL  (1'h0)
   ) u_recov_alert_sts_es_thresh_cfg_alert (
     .clk_i   (clk_i),
@@ -2790,9 +2790,9 @@ module entropy_src_reg_top #(
   );
 
   //   F[es_fw_ov_wr_alert]: 15:15
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW0C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW0C),
     .RESVAL  (1'h0)
   ) u_recov_alert_sts_es_fw_ov_wr_alert (
     .clk_i   (clk_i),
@@ -2816,9 +2816,9 @@ module entropy_src_reg_top #(
   );
 
   //   F[es_fw_ov_disable_alert]: 16:16
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW0C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW0C),
     .RESVAL  (1'h0)
   ) u_recov_alert_sts_es_fw_ov_disable_alert (
     .clk_i   (clk_i),
@@ -2844,9 +2844,9 @@ module entropy_src_reg_top #(
 
   // R[err_code]: V(False)
   //   F[sfifo_esrng_err]: 0:0
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_err_code_sfifo_esrng_err (
     .clk_i   (clk_i),
@@ -2870,9 +2870,9 @@ module entropy_src_reg_top #(
   );
 
   //   F[sfifo_observe_err]: 1:1
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_err_code_sfifo_observe_err (
     .clk_i   (clk_i),
@@ -2896,9 +2896,9 @@ module entropy_src_reg_top #(
   );
 
   //   F[sfifo_esfinal_err]: 2:2
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_err_code_sfifo_esfinal_err (
     .clk_i   (clk_i),
@@ -2922,9 +2922,9 @@ module entropy_src_reg_top #(
   );
 
   //   F[es_ack_sm_err]: 20:20
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_err_code_es_ack_sm_err (
     .clk_i   (clk_i),
@@ -2948,9 +2948,9 @@ module entropy_src_reg_top #(
   );
 
   //   F[es_main_sm_err]: 21:21
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_err_code_es_main_sm_err (
     .clk_i   (clk_i),
@@ -2974,9 +2974,9 @@ module entropy_src_reg_top #(
   );
 
   //   F[es_cntr_err]: 22:22
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_err_code_es_cntr_err (
     .clk_i   (clk_i),
@@ -3000,9 +3000,9 @@ module entropy_src_reg_top #(
   );
 
   //   F[sha3_state_err]: 23:23
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_err_code_sha3_state_err (
     .clk_i   (clk_i),
@@ -3026,9 +3026,9 @@ module entropy_src_reg_top #(
   );
 
   //   F[sha3_rst_storage_err]: 24:24
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_err_code_sha3_rst_storage_err (
     .clk_i   (clk_i),
@@ -3052,9 +3052,9 @@ module entropy_src_reg_top #(
   );
 
   //   F[fifo_write_err]: 28:28
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_err_code_fifo_write_err (
     .clk_i   (clk_i),
@@ -3078,9 +3078,9 @@ module entropy_src_reg_top #(
   );
 
   //   F[fifo_read_err]: 29:29
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_err_code_fifo_read_err (
     .clk_i   (clk_i),
@@ -3104,9 +3104,9 @@ module entropy_src_reg_top #(
   );
 
   //   F[fifo_state_err]: 30:30
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_err_code_fifo_state_err (
     .clk_i   (clk_i),
@@ -3133,7 +3133,7 @@ module entropy_src_reg_top #(
   // R[err_code_test]: V(False)
   logic err_code_test_qe;
   logic [0:0] err_code_test_flds_we;
-  prim_flop #(
+  caliptra_prim_flop #(
     .Width(1),
     .ResetValue(0)
   ) u_err_code_test0_qe (
@@ -3142,9 +3142,9 @@ module entropy_src_reg_top #(
     .d_i(&err_code_test_flds_we),
     .q_o(err_code_test_qe)
   );
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (5),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (5'h0)
   ) u_err_code_test (
     .clk_i   (clk_i),
@@ -3170,9 +3170,9 @@ module entropy_src_reg_top #(
 
 
   // R[main_sm_state]: V(False)
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (9),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (9'hf5)
   ) u_main_sm_state (
     .clk_i   (clk_i),
@@ -3892,10 +3892,6 @@ module entropy_src_reg_top #(
       addr_hit[56]: begin
         reg_rdata_next[8:0] = main_sm_state_qs;
       end
-
-      default: begin
-        reg_rdata_next = '1;
-      end
     endcase
   end
 
diff --git a/src/entropy_src/rtl/entropy_src_repcnt_ht.sv b/src/entropy_src/rtl/entropy_src_repcnt_ht.sv
index 99999a839..847aef3b6 100644
--- a/src/entropy_src/rtl/entropy_src_repcnt_ht.sv
+++ b/src/entropy_src/rtl/entropy_src_repcnt_ht.sv
@@ -68,9 +68,9 @@ module entropy_src_repcnt_ht #(
 
     // NIST B counter
     // SEC_CM: CTR.REDUN
-    prim_count #(
+    caliptra_prim_count #(
       .Width(RegWidth)
-    ) u_prim_count_rep_cntr (
+    ) u_caliptra_prim_count_rep_cntr (
       .clk_i,
       .rst_ni,
       .clr_i(1'b0),
@@ -88,10 +88,10 @@ module entropy_src_repcnt_ht #(
 
   end : gen_cntrs
 
-  prim_max_tree #(
+  caliptra_prim_max_tree #(
     .NumSrc(RngBusWidth),
     .Width(RegWidth)
-  ) u_prim_max_tree_rep_cntr_max (
+  ) u_caliptra_prim_max_tree_rep_cntr_max (
     .clk_i,
     .rst_ni,
     .values_i   (rep_cntr),
diff --git a/src/entropy_src/rtl/entropy_src_repcnts_ht.sv b/src/entropy_src/rtl/entropy_src_repcnts_ht.sv
index 561a4da07..26ff0df79 100644
--- a/src/entropy_src/rtl/entropy_src_repcnts_ht.sv
+++ b/src/entropy_src/rtl/entropy_src_repcnts_ht.sv
@@ -64,9 +64,9 @@ module entropy_src_repcnts_ht #(
 
   // NIST B counter
   // SEC_CM: CTR.REDUN
-  prim_count #(
+  caliptra_prim_count #(
     .Width(RegWidth)
-  ) u_prim_count_rep_cntr (
+  ) u_caliptra_prim_count_rep_cntr (
     .clk_i,
     .rst_ni,
     .clr_i(1'b0),
diff --git a/src/entropy_src/tb/Makefile b/src/entropy_src/tb/Makefile
index f7387c682..7fc2f8cc5 100644
--- a/src/entropy_src/tb/Makefile
+++ b/src/entropy_src/tb/Makefile
@@ -44,7 +44,7 @@ verilator-build: $(TBFILES) $(VERILATOR_LINT_FILES) test_$(IPNAME)_tb.cpp
 	$(VERILATOR) --cc \
 		--timing \
 		--timescale 1ns/1ps \
-		-f $(CONFIGDIR)/$(IPNAME).vf --top-module $(IPNAME)_tb \
+		-f $(CONFIGDIR)/$(IPNAME)_tb.vf --top-module $(IPNAME)_tb \
     -f $(VERILATOR_LINT_FILES) \
 		-exe test_$(IPNAME)_tb.cpp \
 		--trace
diff --git a/src/entropy_src/tb/entropy_src_tb.sv b/src/entropy_src/tb/entropy_src_tb.sv
index 8c6bf6c09..c01cb59b4 100644
--- a/src/entropy_src/tb/entropy_src_tb.sv
+++ b/src/entropy_src/tb/entropy_src_tb.sv
@@ -24,7 +24,7 @@
 module entropy_src_tb
   import entropy_src_pkg::*;
   import entropy_src_reg_pkg::*;
-  import prim_mubi_pkg::mubi8_t;
+  import caliptra_prim_mubi_pkg::mubi8_t;
 (
 `ifdef VERILATOR
   input bit clk_tb
@@ -160,8 +160,8 @@ module entropy_src_tb
     .hreadyout_o (hreadyout_o_tb),
     .hrdata_o    (hrdata_o_tb),
     // OTP Interface
-    .otp_en_entropy_src_fw_read_i (prim_mubi_pkg::MuBi8True),
-    .otp_en_entropy_src_fw_over_i (prim_mubi_pkg::MuBi8True),
+    .otp_en_entropy_src_fw_read_i (caliptra_prim_mubi_pkg::MuBi8True),
+    .otp_en_entropy_src_fw_over_i (caliptra_prim_mubi_pkg::MuBi8True),
     // RNG Interface
     .rng_fips_o          (),
     // Entropy Interface
@@ -213,7 +213,7 @@ module entropy_src_tb
   // the dut as needed.
   //----------------------------------------------------------------
   always @(posedge clk_tb) begin : sys_monitor
-      cycle_ctr = cycle_ctr + 1;
+      cycle_ctr = (!reset_n_tb) ? 32'h0 : cycle_ctr + 1;
     end
 
 
@@ -246,7 +246,6 @@ module entropy_src_tb
   task init_sim;
     begin
       generate_rng = '0;
-      cycle_ctr    = '0;
       error_ctr    = '0;
       tc_ctr       = '0;
 `ifndef VERILATOR
@@ -297,6 +296,7 @@ module entropy_src_tb
       $display("[%t] write_single_word(addr=0x%x, word=0x%x)", $time, address, word);
       hsel_i_tb       = 1;
       haddr_i_tb      = address;
+      hwdata_i_tb     = word;
       hwrite_i_tb     = 1;
       hready_i_tb     = 1;
       htrans_i_tb     = AHB_HTRANS_NONSEQ;
@@ -304,7 +304,6 @@ module entropy_src_tb
 
       @(posedge clk_tb);
       haddr_i_tb      = 'Z;
-      hwdata_i_tb     = word;
       hwrite_i_tb     = 0;
       htrans_i_tb     = AHB_HTRANS_IDLE;
       wait(hreadyout_o_tb == 1'b1);
diff --git a/src/hmac/config/compile.yml b/src/hmac/config/compile.yml
index fe54fef0c..181ae1ce8 100755
--- a/src/hmac/config/compile.yml
+++ b/src/hmac/config/compile.yml
@@ -27,6 +27,7 @@ provides: [hmac_ctrl_tb]
 schema_version: 2.4.0
 requires: 
   - hmac_ctrl
+  - hmac_coverage
 targets:
   tb:
     directories: 
@@ -34,6 +35,18 @@ targets:
     files:
       - $COMPILE_ROOT/tb/hmac_ctrl_tb.sv
     tops: [hmac_ctrl_tb]
+---
+provides: [hmac_coverage]  
+schema_version: 2.4.0
+requires: 
+  - hmac_ctrl
+targets:
+  tb:
+    directories: 
+      - $COMPILE_ROOT/coverage
+    files:
+      - $COMPILE_ROOT/coverage/hmac_ctrl_cov_if.sv
+      - $COMPILE_ROOT/coverage/hmac_ctrl_cov_bind.sv
 global:
   tool:
     vcs:
diff --git a/src/hmac/config/hmac_coverage.vf b/src/hmac/config/hmac_coverage.vf
new file mode 100644
index 000000000..f74b96944
--- /dev/null
+++ b/src/hmac/config/hmac_coverage.vf
@@ -0,0 +1,54 @@
++incdir+${CALIPTRA_ROOT}/src/integration/rtl
++incdir+${CALIPTRA_ROOT}/src/libs/rtl
++incdir+${CALIPTRA_ROOT}/src/keyvault/rtl
++incdir+${CALIPTRA_ROOT}/src/pcrvault/rtl
++incdir+${CALIPTRA_ROOT}/src/hmac/coverage
++incdir+${CALIPTRA_ROOT}/src/sha512/rtl
++incdir+${CALIPTRA_ROOT}/src/sha512_masked/rtl
++incdir+${CALIPTRA_ROOT}/src/hmac/rtl
+${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh
+${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sva.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_macros.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sram.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_defines_pkg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_ahb_srom.sv
+${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
+${CALIPTRA_ROOT}/src/keyvault/rtl/kv_defines_pkg.sv
+${CALIPTRA_ROOT}/src/keyvault/rtl/kv_macros.svh
+${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_defines_pkg.sv
+${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_macros.svh
+${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_gen_hash.sv
+${CALIPTRA_ROOT}/src/hmac/coverage/hmac_ctrl_cov_if.sv
+${CALIPTRA_ROOT}/src/hmac/coverage/hmac_ctrl_cov_bind.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
+${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg_pkg.sv
+${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg.sv
+${CALIPTRA_ROOT}/src/keyvault/rtl/kv.sv
+${CALIPTRA_ROOT}/src/keyvault/rtl/kv_fsm.sv
+${CALIPTRA_ROOT}/src/keyvault/rtl/kv_read_client.sv
+${CALIPTRA_ROOT}/src/keyvault/rtl/kv_write_client.sv
+${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg_pkg.sv
+${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg.sv
+${CALIPTRA_ROOT}/src/pcrvault/rtl/pv.sv
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg_pkg.sv
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_params_pkg.sv
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_ctrl.sv
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512.sv
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_core.v
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_h_constants.v
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_k_constants.v
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_w_mem.v
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg.sv
+${CALIPTRA_ROOT}/src/sha512_masked/rtl/sha512_masked_defines_pkg.sv
+${CALIPTRA_ROOT}/src/sha512_masked/rtl/sha512_masked_core.sv
+${CALIPTRA_ROOT}/src/sha512_masked/rtl/sha512_masked_lfsr.sv
+${CALIPTRA_ROOT}/src/hmac/rtl/hmac_param_pkg.sv
+${CALIPTRA_ROOT}/src/hmac/rtl/hmac_reg_pkg.sv
+${CALIPTRA_ROOT}/src/hmac/rtl/hmac_ctrl.sv
+${CALIPTRA_ROOT}/src/hmac/rtl/hmac.sv
+${CALIPTRA_ROOT}/src/hmac/rtl/hmac_core.v
+${CALIPTRA_ROOT}/src/hmac/rtl/hmac_reg.sv
\ No newline at end of file
diff --git a/src/hmac/config/hmac_ctrl.vf b/src/hmac/config/hmac_ctrl.vf
index 87401410d..666c3371f 100644
--- a/src/hmac/config/hmac_ctrl.vf
+++ b/src/hmac/config/hmac_ctrl.vf
@@ -16,6 +16,7 @@ ${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
 ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_defines_pkg.sv
 ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_macros.svh
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_defines_pkg.sv
@@ -32,9 +33,9 @@ ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg.sv
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg_pkg.sv
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_params_pkg.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_ctrl.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512.sv
-${CALIPTRA_ROOT}/src/sha512/rtl/sha512_param.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_core.v
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_h_constants.v
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_k_constants.v
diff --git a/src/hmac/config/hmac_ctrl_tb.vf b/src/hmac/config/hmac_ctrl_tb.vf
index 1cb35069c..1ca5eaa69 100644
--- a/src/hmac/config/hmac_ctrl_tb.vf
+++ b/src/hmac/config/hmac_ctrl_tb.vf
@@ -2,6 +2,7 @@
 +incdir+${CALIPTRA_ROOT}/src/libs/rtl
 +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl
 +incdir+${CALIPTRA_ROOT}/src/pcrvault/rtl
++incdir+${CALIPTRA_ROOT}/src/hmac/coverage
 +incdir+${CALIPTRA_ROOT}/src/hmac/tb
 +incdir+${CALIPTRA_ROOT}/src/sha512/rtl
 +incdir+${CALIPTRA_ROOT}/src/sha512_masked/rtl
@@ -17,11 +18,14 @@ ${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
 ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_defines_pkg.sv
 ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_macros.svh
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_defines_pkg.sv
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_macros.svh
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_gen_hash.sv
+${CALIPTRA_ROOT}/src/hmac/coverage/hmac_ctrl_cov_if.sv
+${CALIPTRA_ROOT}/src/hmac/coverage/hmac_ctrl_cov_bind.sv
 ${CALIPTRA_ROOT}/src/hmac/tb/hmac_ctrl_tb.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
 ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg_pkg.sv
@@ -34,9 +38,9 @@ ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg.sv
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg_pkg.sv
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_params_pkg.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_ctrl.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512.sv
-${CALIPTRA_ROOT}/src/sha512/rtl/sha512_param.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_core.v
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_h_constants.v
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_k_constants.v
diff --git a/src/hmac/coverage/hmac_ctrl_cov_bind.sv b/src/hmac/coverage/hmac_ctrl_cov_bind.sv
new file mode 100644
index 000000000..7d731b056
--- /dev/null
+++ b/src/hmac/coverage/hmac_ctrl_cov_bind.sv
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+module hmac_ctrl_cov_bind;
+    `ifdef FCOV
+    bind hmac_ctrl hmac_ctrl_cov_if i_hmac_ctrl_cov_if(.*);
+    `endif
+endmodule
diff --git a/src/hmac/coverage/hmac_ctrl_cov_if.sv b/src/hmac/coverage/hmac_ctrl_cov_if.sv
new file mode 100644
index 000000000..231213b0b
--- /dev/null
+++ b/src/hmac/coverage/hmac_ctrl_cov_if.sv
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+`ifndef VERILATOR
+
+interface hmac_ctrl_cov_if     
+    (
+    input logic           clk,
+    input logic           reset_n,
+    input logic           cptra_pwrgood
+
+);
+
+    logic init;
+    logic next;
+    logic zeroize;
+    logic ready;
+    logic valid;
+    
+    logic core_tag_we;
+
+    logic [1 : 0] hmac_cmd;
+    
+    assign init = hmac_ctrl.hmac_inst.init_reg;
+    assign next = hmac_ctrl.hmac_inst.next_reg;
+    assign zeroize = hmac_ctrl.hmac_inst.zeroize_reg;
+    assign ready = hmac_ctrl.hmac_inst.ready_reg;
+    assign valid = hmac_ctrl.hmac_inst.tag_valid_reg;
+
+    assign core_tag_we = hmac_ctrl.hmac_inst.core_tag_we;
+
+    assign hmac_cmd = {next, init};
+
+    covergroup hmac_ctrl_cov_grp @(posedge clk);
+        reset_cp: coverpoint reset_n;
+        cptra_pwrgood_cp: coverpoint cptra_pwrgood;
+
+        init_cp: coverpoint init;
+        next_cp: coverpoint next;
+        zeroize_cp: coverpoint zeroize;
+        ready_cp: coverpoint ready;
+        valid_cp: coverpoint valid;
+
+        core_tag_we_cp: coverpoint core_tag_we;
+
+        hmac_cmd_cp: coverpoint hmac_cmd  {bins cmd[]   = (0, 0 => 1, 2 => 0, 0);}
+
+        init_ready_cp: cross ready, init;
+        next_ready_cp: cross ready, next;
+        zeroize_ready_cp: cross ready, zeroize;
+        zeroize_init_cp: cross zeroize, init;
+        zeroize_next_cp: cross zeroize, next;
+
+    endgroup
+
+    hmac_ctrl_cov_grp hmac_ctrl_cov_grp1 = new();
+
+endinterface
+
+`endif
\ No newline at end of file
diff --git a/src/hmac/rtl/hmac.sv b/src/hmac/rtl/hmac.sv
index 81f9810f4..a9d0114c4 100644
--- a/src/hmac/rtl/hmac.sv
+++ b/src/hmac/rtl/hmac.sv
@@ -50,7 +50,8 @@ module hmac
         input kv_wr_resp_t kv_wr_resp,
 
         output wire error_intr,
-        output wire notif_intr
+        output wire notif_intr,
+        input logic debugUnlock_or_scan_mode_switch
       );
 
   //----------------------------------------------------------------
@@ -102,6 +103,9 @@ module hmac
   logic kv_block_write_en;
   logic [4:0] kv_block_write_offset;
   logic [31:0] kv_block_write_data;
+  //KV Read Data Present
+  logic kv_read_data_present;
+  logic kv_read_data_present_set, kv_read_data_present_reset;
 
   logic dest_keyvault;
   kv_error_code_e kv_key_error, kv_block_error, kv_write_error;
@@ -113,7 +117,6 @@ module hmac
   kv_read_ctrl_reg_t kv_block_read_ctrl_reg;
   kv_write_ctrl_reg_t kv_write_ctrl_reg;
   logic core_tag_we;
-  logic core_ready_reg;
   //----------------------------------------------------------------
   // Concurrent connectivity for ports etc.
   //----------------------------------------------------------------
@@ -173,26 +176,30 @@ module hmac
           kv_reg          <= '0;
           tag_reg         <= '0;
           tag_valid_reg   <= '0;
-          core_ready_reg  <= '0;
+          ready_reg       <= '0;
+          kv_read_data_present <= '0;
         end
       else if (zeroize_reg)
         begin
           kv_reg          <= '0;
           tag_reg         <= '0;
           tag_valid_reg   <= '0;
-          core_ready_reg  <= '0;
+          ready_reg       <= '0;
+          kv_read_data_present <= '0;
         end
       else
         begin
           tag_valid_reg <= core_tag_valid;
-          core_ready_reg <= core_ready; 
+          ready_reg     <= core_ready; 
 
           //write to sw register
-          if (core_tag_we & ~dest_keyvault)
+          if (core_tag_we & ~(dest_keyvault | kv_read_data_present))
             tag_reg <= core_tag;
-          if (core_tag_we & dest_keyvault)
+          if (core_tag_we & (dest_keyvault | kv_read_data_present))
             kv_reg <= core_tag;
 
+          kv_read_data_present <= kv_read_data_present_set ? '1 :
+                                  kv_read_data_present_reset ? '0 : kv_read_data_present;
         end
     end // reg_update
 
@@ -210,10 +217,10 @@ always_comb begin
   //assign hardware readable registers to drive hmac core
   init_reg = hwif_out.HMAC384_CTRL.INIT.value;
   next_reg = hwif_out.HMAC384_CTRL.NEXT.value;
-  zeroize_reg = hwif_out.HMAC384_CTRL.ZEROIZE.value;
+  zeroize_reg = hwif_out.HMAC384_CTRL.ZEROIZE.value || debugUnlock_or_scan_mode_switch;
 
   //drive hardware writeable registers from hmac core
-  hwif_in.HMAC384_STATUS.READY.next = core_ready_reg;
+  hwif_in.HMAC384_STATUS.READY.next = ready_reg;
   hwif_in.HMAC384_STATUS.VALID.next = tag_valid_reg;
   for (int dword=0; dword < TAG_NUM_DWORDS; dword++) begin
     hwif_in.HMAC384_TAG[dword].TAG.next = tag_reg[(TAG_NUM_DWORDS - 1)-dword];
@@ -221,14 +228,14 @@ always_comb begin
   end
   //drive hardware writable registers from key vault
   for (int dword=0; dword < BLOCK_NUM_DWORDS; dword++)begin
-    hwif_in.HMAC384_BLOCK[dword].BLOCK.we = kv_block_write_en & (kv_block_write_offset == dword);
+    hwif_in.HMAC384_BLOCK[dword].BLOCK.we = (kv_block_write_en & (kv_block_write_offset == dword)) & !(zeroize_reg | kv_read_data_present_reset);
     hwif_in.HMAC384_BLOCK[dword].BLOCK.next = kv_block_write_data;
-    hwif_in.HMAC384_BLOCK[dword].BLOCK.hwclr = zeroize_reg;
+    hwif_in.HMAC384_BLOCK[dword].BLOCK.hwclr = zeroize_reg | kv_read_data_present_reset;
   end
   for (int dword=0; dword < KEY_NUM_DWORDS; dword++)begin
-    hwif_in.HMAC384_KEY[dword].KEY.we = kv_key_write_en & (kv_key_write_offset == dword);
+    hwif_in.HMAC384_KEY[dword].KEY.we = (kv_key_write_en & (kv_key_write_offset == dword)) & !(zeroize_reg | kv_read_data_present_reset);
     hwif_in.HMAC384_KEY[dword].KEY.next = kv_key_write_data;
-    hwif_in.HMAC384_KEY[dword].KEY.hwclr = zeroize_reg;
+    hwif_in.HMAC384_KEY[dword].KEY.hwclr = zeroize_reg | kv_read_data_present_reset;
   end
   //set ready when keyvault isn't busy
   hwif_in.HMAC384_KV_RD_KEY_STATUS.READY.next = kv_key_ready;
@@ -268,6 +275,10 @@ end
 `CALIPTRA_KV_READ_CTRL_REG2STRUCT(kv_block_read_ctrl_reg, HMAC384_KV_RD_BLOCK_CTRL)
 `CALIPTRA_KV_WRITE_CTRL_REG2STRUCT(kv_write_ctrl_reg, HMAC384_KV_WR_CTRL)
 
+//Force result into KV reg whenever source came from KV
+always_comb kv_read_data_present_set = kv_key_read_ctrl_reg.read_en | kv_block_read_ctrl_reg.read_en;
+always_comb kv_read_data_present_reset = kv_read_data_present & core_tag_we;
+
 // Register block
 hmac_reg i_hmac_reg (
     .clk(clk),
@@ -309,6 +320,7 @@ hmac_key_kv_read
 (
     .clk(clk),
     .rst_b(reset_n),
+    .zeroize(zeroize_reg),
 
     //client control register
     .read_ctrl_reg(kv_key_read_ctrl_reg),
@@ -337,6 +349,7 @@ hmac_block_kv_read
 (
     .clk(clk),
     .rst_b(reset_n),
+    .zeroize(zeroize_reg),
 
     //client control register
     .read_ctrl_reg(kv_block_read_ctrl_reg),
@@ -363,6 +376,7 @@ hmac_result_kv_write
 (
   .clk(clk),
   .rst_b(reset_n),
+  .zeroize(zeroize_reg),
 
   //client control register
   .write_ctrl_reg(kv_write_ctrl_reg),
diff --git a/src/hmac/rtl/hmac_ctrl.sv b/src/hmac/rtl/hmac_ctrl.sv
index f26c00284..b9c5482f6 100644
--- a/src/hmac/rtl/hmac_ctrl.sv
+++ b/src/hmac/rtl/hmac_ctrl.sv
@@ -58,7 +58,8 @@ module hmac_ctrl
 
     // Interrupt
     output logic error_intr,
-    output logic notif_intr
+    output logic notif_intr,
+    input  logic debugUnlock_or_scan_mode_switch
 );
 
     //----------------------------------------------------------------
@@ -88,7 +89,8 @@ module hmac_ctrl
         .kv_rd_resp(kv_rd_resp),
         .kv_wr_resp(kv_wr_resp),
         .error_intr(error_intr),
-        .notif_intr(notif_intr)
+        .notif_intr(notif_intr),
+        .debugUnlock_or_scan_mode_switch(debugUnlock_or_scan_mode_switch)
     );
 
     //instantiate ahb lite module
diff --git a/src/hmac/rtl/hmac_reg_uvm.sv b/src/hmac/rtl/hmac_reg_uvm.sv
index 06f298f7c..f8259d2d8 100644
--- a/src/hmac/rtl/hmac_reg_uvm.sv
+++ b/src/hmac/rtl/hmac_reg_uvm.sv
@@ -3,44 +3,89 @@
 package hmac_reg_uvm;
     `include "uvm_macros.svh"
     import uvm_pkg::*;
-    
+    `include "hmac_reg_covergroups.svh"
     // Reg - hmac_reg::HMAC384_NAME
     class hmac_reg__HMAC384_NAME extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        hmac_reg__HMAC384_NAME_bit_cg NAME_bit_cg[32];
+        hmac_reg__HMAC384_NAME_fld_cg fld_cg;
         rand uvm_reg_field NAME;
 
         function new(string name = "hmac_reg__HMAC384_NAME");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.NAME = new("NAME");
             this.NAME.configure(this, 32, 0, "RO", 1, 'h0, 0, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(NAME_bit_cg[bt]) NAME_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : hmac_reg__HMAC384_NAME
 
     // Reg - hmac_reg::HMAC384_VERSION
     class hmac_reg__HMAC384_VERSION extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        hmac_reg__HMAC384_VERSION_bit_cg VERSION_bit_cg[32];
+        hmac_reg__HMAC384_VERSION_fld_cg fld_cg;
         rand uvm_reg_field VERSION;
 
         function new(string name = "hmac_reg__HMAC384_VERSION");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.VERSION = new("VERSION");
             this.VERSION.configure(this, 32, 0, "RO", 1, 'h0, 0, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(VERSION_bit_cg[bt]) VERSION_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : hmac_reg__HMAC384_VERSION
 
     // Reg - hmac_reg::HMAC384_CTRL
     class hmac_reg__HMAC384_CTRL extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        hmac_reg__HMAC384_CTRL_bit_cg INIT_bit_cg[1];
+        hmac_reg__HMAC384_CTRL_bit_cg NEXT_bit_cg[1];
+        hmac_reg__HMAC384_CTRL_bit_cg ZEROIZE_bit_cg[1];
+        hmac_reg__HMAC384_CTRL_fld_cg fld_cg;
         rand uvm_reg_field INIT;
         rand uvm_reg_field NEXT;
         rand uvm_reg_field ZEROIZE;
 
         function new(string name = "hmac_reg__HMAC384_CTRL");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.INIT = new("INIT");
@@ -49,92 +94,195 @@ package hmac_reg_uvm;
             this.NEXT.configure(this, 1, 1, "WO", 0, 'h0, 1, 1, 0);
             this.ZEROIZE = new("ZEROIZE");
             this.ZEROIZE.configure(this, 1, 2, "WO", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(INIT_bit_cg[bt]) INIT_bit_cg[bt] = new();
+                foreach(NEXT_bit_cg[bt]) NEXT_bit_cg[bt] = new();
+                foreach(ZEROIZE_bit_cg[bt]) ZEROIZE_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : hmac_reg__HMAC384_CTRL
 
     // Reg - hmac_reg::HMAC384_STATUS
     class hmac_reg__HMAC384_STATUS extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        hmac_reg__HMAC384_STATUS_bit_cg READY_bit_cg[1];
+        hmac_reg__HMAC384_STATUS_bit_cg VALID_bit_cg[1];
+        hmac_reg__HMAC384_STATUS_fld_cg fld_cg;
         rand uvm_reg_field READY;
         rand uvm_reg_field VALID;
 
         function new(string name = "hmac_reg__HMAC384_STATUS");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.READY = new("READY");
             this.READY.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
             this.VALID = new("VALID");
             this.VALID.configure(this, 1, 1, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(READY_bit_cg[bt]) READY_bit_cg[bt] = new();
+                foreach(VALID_bit_cg[bt]) VALID_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : hmac_reg__HMAC384_STATUS
 
     // Reg - hmac_reg::HMAC384_KEY
     class hmac_reg__HMAC384_KEY extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        hmac_reg__HMAC384_KEY_bit_cg KEY_bit_cg[32];
+        hmac_reg__HMAC384_KEY_fld_cg fld_cg;
         rand uvm_reg_field KEY;
 
         function new(string name = "hmac_reg__HMAC384_KEY");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.KEY = new("KEY");
             this.KEY.configure(this, 32, 0, "WO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(KEY_bit_cg[bt]) KEY_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : hmac_reg__HMAC384_KEY
 
     // Reg - hmac_reg::HMAC384_BLOCK
     class hmac_reg__HMAC384_BLOCK extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        hmac_reg__HMAC384_BLOCK_bit_cg BLOCK_bit_cg[32];
+        hmac_reg__HMAC384_BLOCK_fld_cg fld_cg;
         rand uvm_reg_field BLOCK;
 
         function new(string name = "hmac_reg__HMAC384_BLOCK");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.BLOCK = new("BLOCK");
             this.BLOCK.configure(this, 32, 0, "WO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(BLOCK_bit_cg[bt]) BLOCK_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : hmac_reg__HMAC384_BLOCK
 
     // Reg - hmac_reg::HMAC384_TAG
     class hmac_reg__HMAC384_TAG extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        hmac_reg__HMAC384_TAG_bit_cg TAG_bit_cg[32];
+        hmac_reg__HMAC384_TAG_fld_cg fld_cg;
         rand uvm_reg_field TAG;
 
         function new(string name = "hmac_reg__HMAC384_TAG");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.TAG = new("TAG");
             this.TAG.configure(this, 32, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(TAG_bit_cg[bt]) TAG_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : hmac_reg__HMAC384_TAG
 
     // Reg - hmac_reg::HMAC384_LFSR_SEED
     class hmac_reg__HMAC384_LFSR_SEED extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        hmac_reg__HMAC384_LFSR_SEED_bit_cg LFSR_SEED_bit_cg[32];
+        hmac_reg__HMAC384_LFSR_SEED_fld_cg fld_cg;
         rand uvm_reg_field LFSR_SEED;
 
         function new(string name = "hmac_reg__HMAC384_LFSR_SEED");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.LFSR_SEED = new("LFSR_SEED");
             this.LFSR_SEED.configure(this, 32, 0, "WO", 0, 'h3cabffb0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(LFSR_SEED_bit_cg[bt]) LFSR_SEED_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : hmac_reg__HMAC384_LFSR_SEED
 
     // Reg - kv_read_ctrl_reg
     class kv_read_ctrl_reg extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        kv_read_ctrl_reg_bit_cg read_en_bit_cg[1];
+        kv_read_ctrl_reg_bit_cg read_entry_bit_cg[5];
+        kv_read_ctrl_reg_bit_cg pcr_hash_extend_bit_cg[1];
+        kv_read_ctrl_reg_bit_cg rsvd_bit_cg[25];
+        kv_read_ctrl_reg_fld_cg fld_cg;
         rand uvm_reg_field read_en;
         rand uvm_reg_field read_entry;
         rand uvm_reg_field pcr_hash_extend;
         rand uvm_reg_field rsvd;
 
         function new(string name = "kv_read_ctrl_reg");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.read_en = new("read_en");
@@ -145,18 +293,39 @@ package hmac_reg_uvm;
             this.pcr_hash_extend.configure(this, 1, 6, "RW", 0, 'h0, 1, 1, 0);
             this.rsvd = new("rsvd");
             this.rsvd.configure(this, 25, 7, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(read_en_bit_cg[bt]) read_en_bit_cg[bt] = new();
+                foreach(read_entry_bit_cg[bt]) read_entry_bit_cg[bt] = new();
+                foreach(pcr_hash_extend_bit_cg[bt]) pcr_hash_extend_bit_cg[bt] = new();
+                foreach(rsvd_bit_cg[bt]) rsvd_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : kv_read_ctrl_reg
 
     // Reg - kv_status_reg
     class kv_status_reg extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        kv_status_reg_bit_cg READY_bit_cg[1];
+        kv_status_reg_bit_cg VALID_bit_cg[1];
+        kv_status_reg_bit_cg ERROR_bit_cg[8];
+        kv_status_reg_fld_cg fld_cg;
         rand uvm_reg_field READY;
         rand uvm_reg_field VALID;
         rand uvm_reg_field ERROR;
 
         function new(string name = "kv_status_reg");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.READY = new("READY");
@@ -165,11 +334,31 @@ package hmac_reg_uvm;
             this.VALID.configure(this, 1, 1, "RO", 1, 'h0, 1, 1, 0);
             this.ERROR = new("ERROR");
             this.ERROR.configure(this, 8, 2, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(READY_bit_cg[bt]) READY_bit_cg[bt] = new();
+                foreach(VALID_bit_cg[bt]) VALID_bit_cg[bt] = new();
+                foreach(ERROR_bit_cg[bt]) ERROR_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : kv_status_reg
 
     // Reg - kv_write_ctrl_reg
     class kv_write_ctrl_reg extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        kv_write_ctrl_reg_bit_cg write_en_bit_cg[1];
+        kv_write_ctrl_reg_bit_cg write_entry_bit_cg[5];
+        kv_write_ctrl_reg_bit_cg hmac_key_dest_valid_bit_cg[1];
+        kv_write_ctrl_reg_bit_cg hmac_block_dest_valid_bit_cg[1];
+        kv_write_ctrl_reg_bit_cg sha_block_dest_valid_bit_cg[1];
+        kv_write_ctrl_reg_bit_cg ecc_pkey_dest_valid_bit_cg[1];
+        kv_write_ctrl_reg_bit_cg ecc_seed_dest_valid_bit_cg[1];
+        kv_write_ctrl_reg_bit_cg rsvd_bit_cg[21];
+        kv_write_ctrl_reg_fld_cg fld_cg;
         rand uvm_reg_field write_en;
         rand uvm_reg_field write_entry;
         rand uvm_reg_field hmac_key_dest_valid;
@@ -180,8 +369,13 @@ package hmac_reg_uvm;
         rand uvm_reg_field rsvd;
 
         function new(string name = "kv_write_ctrl_reg");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.write_en = new("write_en");
@@ -200,36 +394,80 @@ package hmac_reg_uvm;
             this.ecc_seed_dest_valid.configure(this, 1, 10, "RW", 0, 'h0, 1, 1, 0);
             this.rsvd = new("rsvd");
             this.rsvd.configure(this, 21, 11, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(write_en_bit_cg[bt]) write_en_bit_cg[bt] = new();
+                foreach(write_entry_bit_cg[bt]) write_entry_bit_cg[bt] = new();
+                foreach(hmac_key_dest_valid_bit_cg[bt]) hmac_key_dest_valid_bit_cg[bt] = new();
+                foreach(hmac_block_dest_valid_bit_cg[bt]) hmac_block_dest_valid_bit_cg[bt] = new();
+                foreach(sha_block_dest_valid_bit_cg[bt]) sha_block_dest_valid_bit_cg[bt] = new();
+                foreach(ecc_pkey_dest_valid_bit_cg[bt]) ecc_pkey_dest_valid_bit_cg[bt] = new();
+                foreach(ecc_seed_dest_valid_bit_cg[bt]) ecc_seed_dest_valid_bit_cg[bt] = new();
+                foreach(rsvd_bit_cg[bt]) rsvd_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : kv_write_ctrl_reg
 
     // Reg - hmac_reg::global_intr_en_t
     class hmac_reg__global_intr_en_t extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        hmac_reg__global_intr_en_t_bit_cg error_en_bit_cg[1];
+        hmac_reg__global_intr_en_t_bit_cg notif_en_bit_cg[1];
+        hmac_reg__global_intr_en_t_fld_cg fld_cg;
         rand uvm_reg_field error_en;
         rand uvm_reg_field notif_en;
 
         function new(string name = "hmac_reg__global_intr_en_t");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.error_en = new("error_en");
             this.error_en.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
             this.notif_en = new("notif_en");
             this.notif_en.configure(this, 1, 1, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(error_en_bit_cg[bt]) error_en_bit_cg[bt] = new();
+                foreach(notif_en_bit_cg[bt]) notif_en_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : hmac_reg__global_intr_en_t
 
     // Reg - hmac_reg::error_intr_en_t
     class hmac_reg__error_intr_en_t extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        hmac_reg__error_intr_en_t_bit_cg error0_en_bit_cg[1];
+        hmac_reg__error_intr_en_t_bit_cg error1_en_bit_cg[1];
+        hmac_reg__error_intr_en_t_bit_cg error2_en_bit_cg[1];
+        hmac_reg__error_intr_en_t_bit_cg error3_en_bit_cg[1];
+        hmac_reg__error_intr_en_t_fld_cg fld_cg;
         rand uvm_reg_field error0_en;
         rand uvm_reg_field error1_en;
         rand uvm_reg_field error2_en;
         rand uvm_reg_field error3_en;
 
         function new(string name = "hmac_reg__error_intr_en_t");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.error0_en = new("error0_en");
@@ -240,61 +478,131 @@ package hmac_reg_uvm;
             this.error2_en.configure(this, 1, 2, "RW", 0, 'h0, 1, 1, 0);
             this.error3_en = new("error3_en");
             this.error3_en.configure(this, 1, 3, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(error0_en_bit_cg[bt]) error0_en_bit_cg[bt] = new();
+                foreach(error1_en_bit_cg[bt]) error1_en_bit_cg[bt] = new();
+                foreach(error2_en_bit_cg[bt]) error2_en_bit_cg[bt] = new();
+                foreach(error3_en_bit_cg[bt]) error3_en_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : hmac_reg__error_intr_en_t
 
     // Reg - hmac_reg::notif_intr_en_t
     class hmac_reg__notif_intr_en_t extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        hmac_reg__notif_intr_en_t_bit_cg notif_cmd_done_en_bit_cg[1];
+        hmac_reg__notif_intr_en_t_fld_cg fld_cg;
         rand uvm_reg_field notif_cmd_done_en;
 
         function new(string name = "hmac_reg__notif_intr_en_t");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.notif_cmd_done_en = new("notif_cmd_done_en");
             this.notif_cmd_done_en.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(notif_cmd_done_en_bit_cg[bt]) notif_cmd_done_en_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : hmac_reg__notif_intr_en_t
 
     // Reg - hmac_reg::global_intr_t_agg_sts_dd3dcf0a
     class hmac_reg__global_intr_t_agg_sts_dd3dcf0a extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        hmac_reg__global_intr_t_agg_sts_dd3dcf0a_bit_cg agg_sts_bit_cg[1];
+        hmac_reg__global_intr_t_agg_sts_dd3dcf0a_fld_cg fld_cg;
         rand uvm_reg_field agg_sts;
 
         function new(string name = "hmac_reg__global_intr_t_agg_sts_dd3dcf0a");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.agg_sts = new("agg_sts");
             this.agg_sts.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(agg_sts_bit_cg[bt]) agg_sts_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : hmac_reg__global_intr_t_agg_sts_dd3dcf0a
 
     // Reg - hmac_reg::global_intr_t_agg_sts_e6399b4a
     class hmac_reg__global_intr_t_agg_sts_e6399b4a extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        hmac_reg__global_intr_t_agg_sts_e6399b4a_bit_cg agg_sts_bit_cg[1];
+        hmac_reg__global_intr_t_agg_sts_e6399b4a_fld_cg fld_cg;
         rand uvm_reg_field agg_sts;
 
         function new(string name = "hmac_reg__global_intr_t_agg_sts_e6399b4a");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.agg_sts = new("agg_sts");
             this.agg_sts.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(agg_sts_bit_cg[bt]) agg_sts_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : hmac_reg__global_intr_t_agg_sts_e6399b4a
 
     // Reg - hmac_reg::error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378
     class hmac_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        hmac_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378_bit_cg error0_sts_bit_cg[1];
+        hmac_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378_bit_cg error1_sts_bit_cg[1];
+        hmac_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378_bit_cg error2_sts_bit_cg[1];
+        hmac_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378_bit_cg error3_sts_bit_cg[1];
+        hmac_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378_fld_cg fld_cg;
         rand uvm_reg_field error0_sts;
         rand uvm_reg_field error1_sts;
         rand uvm_reg_field error2_sts;
         rand uvm_reg_field error3_sts;
 
         function new(string name = "hmac_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.error0_sts = new("error0_sts");
@@ -305,33 +613,71 @@ package hmac_reg_uvm;
             this.error2_sts.configure(this, 1, 2, "W1C", 1, 'h0, 1, 1, 0);
             this.error3_sts = new("error3_sts");
             this.error3_sts.configure(this, 1, 3, "W1C", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(error0_sts_bit_cg[bt]) error0_sts_bit_cg[bt] = new();
+                foreach(error1_sts_bit_cg[bt]) error1_sts_bit_cg[bt] = new();
+                foreach(error2_sts_bit_cg[bt]) error2_sts_bit_cg[bt] = new();
+                foreach(error3_sts_bit_cg[bt]) error3_sts_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : hmac_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378
 
     // Reg - hmac_reg::notif_intr_t_notif_cmd_done_sts_1c68637e
     class hmac_reg__notif_intr_t_notif_cmd_done_sts_1c68637e extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        hmac_reg__notif_intr_t_notif_cmd_done_sts_1c68637e_bit_cg notif_cmd_done_sts_bit_cg[1];
+        hmac_reg__notif_intr_t_notif_cmd_done_sts_1c68637e_fld_cg fld_cg;
         rand uvm_reg_field notif_cmd_done_sts;
 
         function new(string name = "hmac_reg__notif_intr_t_notif_cmd_done_sts_1c68637e");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.notif_cmd_done_sts = new("notif_cmd_done_sts");
             this.notif_cmd_done_sts.configure(this, 1, 0, "W1C", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(notif_cmd_done_sts_bit_cg[bt]) notif_cmd_done_sts_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : hmac_reg__notif_intr_t_notif_cmd_done_sts_1c68637e
 
     // Reg - hmac_reg::error_intr_trig_t
     class hmac_reg__error_intr_trig_t extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        hmac_reg__error_intr_trig_t_bit_cg error0_trig_bit_cg[1];
+        hmac_reg__error_intr_trig_t_bit_cg error1_trig_bit_cg[1];
+        hmac_reg__error_intr_trig_t_bit_cg error2_trig_bit_cg[1];
+        hmac_reg__error_intr_trig_t_bit_cg error3_trig_bit_cg[1];
+        hmac_reg__error_intr_trig_t_fld_cg fld_cg;
         rand uvm_reg_field error0_trig;
         rand uvm_reg_field error1_trig;
         rand uvm_reg_field error2_trig;
         rand uvm_reg_field error3_trig;
 
         function new(string name = "hmac_reg__error_intr_trig_t");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.error0_trig = new("error0_trig");
@@ -342,160 +688,344 @@ package hmac_reg_uvm;
             this.error2_trig.configure(this, 1, 2, "W1S", 0, 'h0, 1, 1, 0);
             this.error3_trig = new("error3_trig");
             this.error3_trig.configure(this, 1, 3, "W1S", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(error0_trig_bit_cg[bt]) error0_trig_bit_cg[bt] = new();
+                foreach(error1_trig_bit_cg[bt]) error1_trig_bit_cg[bt] = new();
+                foreach(error2_trig_bit_cg[bt]) error2_trig_bit_cg[bt] = new();
+                foreach(error3_trig_bit_cg[bt]) error3_trig_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : hmac_reg__error_intr_trig_t
 
     // Reg - hmac_reg::notif_intr_trig_t
     class hmac_reg__notif_intr_trig_t extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        hmac_reg__notif_intr_trig_t_bit_cg notif_cmd_done_trig_bit_cg[1];
+        hmac_reg__notif_intr_trig_t_fld_cg fld_cg;
         rand uvm_reg_field notif_cmd_done_trig;
 
         function new(string name = "hmac_reg__notif_intr_trig_t");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.notif_cmd_done_trig = new("notif_cmd_done_trig");
             this.notif_cmd_done_trig.configure(this, 1, 0, "W1S", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(notif_cmd_done_trig_bit_cg[bt]) notif_cmd_done_trig_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : hmac_reg__notif_intr_trig_t
 
     // Reg - hmac_reg::intr_count_t_cnt_35ace267
     class hmac_reg__intr_count_t_cnt_35ace267 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        hmac_reg__intr_count_t_cnt_35ace267_bit_cg cnt_bit_cg[32];
+        hmac_reg__intr_count_t_cnt_35ace267_fld_cg fld_cg;
         rand uvm_reg_field cnt;
 
         function new(string name = "hmac_reg__intr_count_t_cnt_35ace267");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.cnt = new("cnt");
             this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : hmac_reg__intr_count_t_cnt_35ace267
 
     // Reg - hmac_reg::intr_count_t_cnt_73c42c28
     class hmac_reg__intr_count_t_cnt_73c42c28 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        hmac_reg__intr_count_t_cnt_73c42c28_bit_cg cnt_bit_cg[32];
+        hmac_reg__intr_count_t_cnt_73c42c28_fld_cg fld_cg;
         rand uvm_reg_field cnt;
 
         function new(string name = "hmac_reg__intr_count_t_cnt_73c42c28");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.cnt = new("cnt");
             this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : hmac_reg__intr_count_t_cnt_73c42c28
 
     // Reg - hmac_reg::intr_count_t_cnt_d8af96ff
     class hmac_reg__intr_count_t_cnt_d8af96ff extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        hmac_reg__intr_count_t_cnt_d8af96ff_bit_cg cnt_bit_cg[32];
+        hmac_reg__intr_count_t_cnt_d8af96ff_fld_cg fld_cg;
         rand uvm_reg_field cnt;
 
         function new(string name = "hmac_reg__intr_count_t_cnt_d8af96ff");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.cnt = new("cnt");
             this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : hmac_reg__intr_count_t_cnt_d8af96ff
 
     // Reg - hmac_reg::intr_count_t_cnt_9bd7f809
     class hmac_reg__intr_count_t_cnt_9bd7f809 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        hmac_reg__intr_count_t_cnt_9bd7f809_bit_cg cnt_bit_cg[32];
+        hmac_reg__intr_count_t_cnt_9bd7f809_fld_cg fld_cg;
         rand uvm_reg_field cnt;
 
         function new(string name = "hmac_reg__intr_count_t_cnt_9bd7f809");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.cnt = new("cnt");
             this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : hmac_reg__intr_count_t_cnt_9bd7f809
 
     // Reg - hmac_reg::intr_count_t_cnt_be67d6d5
     class hmac_reg__intr_count_t_cnt_be67d6d5 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        hmac_reg__intr_count_t_cnt_be67d6d5_bit_cg cnt_bit_cg[32];
+        hmac_reg__intr_count_t_cnt_be67d6d5_fld_cg fld_cg;
         rand uvm_reg_field cnt;
 
         function new(string name = "hmac_reg__intr_count_t_cnt_be67d6d5");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.cnt = new("cnt");
             this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : hmac_reg__intr_count_t_cnt_be67d6d5
 
     // Reg - hmac_reg::intr_count_incr_t_pulse_37026c97
     class hmac_reg__intr_count_incr_t_pulse_37026c97 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        hmac_reg__intr_count_incr_t_pulse_37026c97_bit_cg pulse_bit_cg[1];
+        hmac_reg__intr_count_incr_t_pulse_37026c97_fld_cg fld_cg;
         rand uvm_reg_field pulse;
 
         function new(string name = "hmac_reg__intr_count_incr_t_pulse_37026c97");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.pulse = new("pulse");
             this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : hmac_reg__intr_count_incr_t_pulse_37026c97
 
     // Reg - hmac_reg::intr_count_incr_t_pulse_d860d977
     class hmac_reg__intr_count_incr_t_pulse_d860d977 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        hmac_reg__intr_count_incr_t_pulse_d860d977_bit_cg pulse_bit_cg[1];
+        hmac_reg__intr_count_incr_t_pulse_d860d977_fld_cg fld_cg;
         rand uvm_reg_field pulse;
 
         function new(string name = "hmac_reg__intr_count_incr_t_pulse_d860d977");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.pulse = new("pulse");
             this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : hmac_reg__intr_count_incr_t_pulse_d860d977
 
     // Reg - hmac_reg::intr_count_incr_t_pulse_87b45fe7
     class hmac_reg__intr_count_incr_t_pulse_87b45fe7 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        hmac_reg__intr_count_incr_t_pulse_87b45fe7_bit_cg pulse_bit_cg[1];
+        hmac_reg__intr_count_incr_t_pulse_87b45fe7_fld_cg fld_cg;
         rand uvm_reg_field pulse;
 
         function new(string name = "hmac_reg__intr_count_incr_t_pulse_87b45fe7");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.pulse = new("pulse");
             this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : hmac_reg__intr_count_incr_t_pulse_87b45fe7
 
     // Reg - hmac_reg::intr_count_incr_t_pulse_c1689ee6
     class hmac_reg__intr_count_incr_t_pulse_c1689ee6 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        hmac_reg__intr_count_incr_t_pulse_c1689ee6_bit_cg pulse_bit_cg[1];
+        hmac_reg__intr_count_incr_t_pulse_c1689ee6_fld_cg fld_cg;
         rand uvm_reg_field pulse;
 
         function new(string name = "hmac_reg__intr_count_incr_t_pulse_c1689ee6");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.pulse = new("pulse");
             this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : hmac_reg__intr_count_incr_t_pulse_c1689ee6
 
     // Reg - hmac_reg::intr_count_incr_t_pulse_6173128e
     class hmac_reg__intr_count_incr_t_pulse_6173128e extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        hmac_reg__intr_count_incr_t_pulse_6173128e_bit_cg pulse_bit_cg[1];
+        hmac_reg__intr_count_incr_t_pulse_6173128e_fld_cg fld_cg;
         rand uvm_reg_field pulse;
 
         function new(string name = "hmac_reg__intr_count_incr_t_pulse_6173128e");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.pulse = new("pulse");
             this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : hmac_reg__intr_count_incr_t_pulse_6173128e
 
@@ -738,4 +1268,5 @@ package hmac_reg_uvm;
         endfunction : build
     endclass : hmac_reg
 
+    `include "hmac_reg_sample.svh"
 endpackage: hmac_reg_uvm
diff --git a/src/hmac/tb/hmac_ctrl_tb.sv b/src/hmac/tb/hmac_ctrl_tb.sv
index 3b9658f7b..c070ed310 100644
--- a/src/hmac/tb/hmac_ctrl_tb.sv
+++ b/src/hmac/tb/hmac_ctrl_tb.sv
@@ -39,9 +39,8 @@ module hmac_ctrl_tb();
   parameter ADDR_VERSION     = BASE_ADDR + 32'h00000008;
 
   parameter ADDR_CTRL        = BASE_ADDR + 32'h00000010;
-  parameter CTRL_INIT_VALUE  = 8'h01;
-  parameter CTRL_NEXT_VALUE  = 8'h02;
-  parameter CTRL_MODE_VALUE  = 8'h04;
+  parameter CTRL_INIT_VALUE  = 2'h1;
+  parameter CTRL_NEXT_VALUE  = 2'h2;
 
   parameter ADDR_STATUS      = BASE_ADDR + 32'h00000018;
   parameter STATUS_READY_BIT = 0;
@@ -146,6 +145,9 @@ module hmac_ctrl_tb();
   reg [63 : 0]  read_data;
   reg [383 : 0] digest_data;
 
+  //bind coverage file
+  hmac_ctrl_cov_bind i_hmac_ctrl_cov_bind();
+
   //----------------------------------------------------------------
   // Device Under Test.
   //----------------------------------------------------------------
@@ -176,7 +178,8 @@ module hmac_ctrl_tb();
              .kv_wr_resp('x),
 
              .error_intr(),
-             .notif_intr()
+             .notif_intr(),
+             .debugUnlock_or_scan_mode_switch('0)
             );
 
 
@@ -537,6 +540,9 @@ module hmac_ctrl_tb();
       wait_ready();
       data_in_time = cycle_ctr;
       read_digest();
+
+      write_single_word(ADDR_CTRL, {29'h0, 1'b1, 2'b0}); //zeroize
+
       data_in_time = cycle_ctr - data_in_time;
       $display("***       DATA OUT processing time = %01d cycles", data_in_time);
       end_time = cycle_ctr - start_time;
@@ -549,8 +555,8 @@ module hmac_ctrl_tb();
       else
         begin
           $display("TC%01d: ERROR.", tc_ctr);
-          $display("TC%01d: Expected: 0x%064x", tc_ctr, expected);
-          $display("TC%01d: Got:      0x%064x", tc_ctr, digest_data);
+          $display("TC%01d: Expected: 0x%096x", tc_ctr, expected);
+          $display("TC%01d: Got:      0x%096x", tc_ctr, digest_data);
           error_ctr = error_ctr + 1;
         end
       $display("*** TC%01d - Single block test done.", tc_ctr);
@@ -604,6 +610,8 @@ module hmac_ctrl_tb();
       wait_ready();
       read_digest();
 
+      write_single_word(ADDR_CTRL, {29'h0, 1'b1, 2'b0}); //zeroize
+
       end_time = cycle_ctr - start_time;
       $display("*** Double block test processing time = %01d cycles", end_time);
 
@@ -614,8 +622,8 @@ module hmac_ctrl_tb();
       else
         begin
           $display("TC%01d: ERROR in final digest", tc_ctr);
-          $display("TC%01d: Expected: 0x%064x", tc_ctr, expected);
-          $display("TC%01d: Got:      0x%064x", tc_ctr, digest_data);
+          $display("TC%01d: Expected: 0x%096x", tc_ctr, expected);
+          $display("TC%01d: Got:      0x%096x", tc_ctr, digest_data);
           error_ctr = error_ctr + 1;
         end
 
@@ -625,6 +633,230 @@ module hmac_ctrl_tb();
   endtask // double_block_test
 
 
+  //----------------------------------------------------------------
+  // continuous_cmd_test()
+  //
+  //
+  // Perform test of a double block digest.
+  //----------------------------------------------------------------
+  task continuous_cmd_test(input [383 : 0] key,
+                         input [1023: 0] block0,
+                         input [1023: 0] block1,
+                         input [159: 0]  seed,
+                         input [383 : 0] expected
+                        );
+    begin
+      reg [31  : 0] start_time;
+      reg [31 : 0] end_time;
+
+      start_time = cycle_ctr;
+      $display("*** TC%01d - continuous_cmd_test started.", tc_ctr);
+
+      write_key(key);
+
+      // First block
+      write_block(block0);
+
+      write_seed(seed);
+
+      write_single_word(ADDR_CTRL, CTRL_INIT_VALUE);
+      #CLK_PERIOD;
+      hsel_i_tb       = 0;
+
+      #(CLK_PERIOD);
+
+      for (int i=0; i<10; i++)
+        begin
+          write_single_word(ADDR_CTRL, CTRL_INIT_VALUE);
+          #CLK_PERIOD;
+          write_single_word(ADDR_CTRL, CTRL_NEXT_VALUE);
+          #CLK_PERIOD;
+        end
+
+      #(CLK_PERIOD);
+      wait_ready();
+
+      // Final block
+      write_block(block1);
+
+      write_single_word(ADDR_CTRL, CTRL_NEXT_VALUE);
+      #CLK_PERIOD;
+      hsel_i_tb       = 0;
+
+      #(CLK_PERIOD);
+
+      for (int i=0; i<10; i++)
+        begin
+          write_single_word(ADDR_CTRL, CTRL_INIT_VALUE);
+          #CLK_PERIOD;
+          write_single_word(ADDR_CTRL, CTRL_NEXT_VALUE);
+          #CLK_PERIOD;
+        end
+
+      #(CLK_PERIOD);
+      wait_ready();
+      read_digest();
+
+      write_single_word(ADDR_CTRL, {29'h0, 1'b1, 2'b0}); //zeroize
+
+      end_time = cycle_ctr - start_time;
+      $display("*** continuous_cmd_test processing time = %01d cycles", end_time);
+
+      if (digest_data == expected)
+        begin
+          $display("TC%01d final block: OK.", tc_ctr);
+        end
+      else
+        begin
+          $display("TC%01d: ERROR in final digest", tc_ctr);
+          $display("TC%01d: Expected: 0x%096x", tc_ctr, expected);
+          $display("TC%01d: Got:      0x%096x", tc_ctr, digest_data);
+          error_ctr = error_ctr + 1;
+        end
+
+      $display("*** TC%01d - continuous_cmd_test done.", tc_ctr);
+      tc_ctr = tc_ctr + 1;
+    end
+  endtask // continuous_cmd_test
+
+  //----------------------------------------------------------------
+  // zeroize_test()
+  //
+  //----------------------------------------------------------------
+  task zeroize_test(input [383 : 0] key,
+                    input [1023: 0] block0,
+                    input [1023: 0] block1,
+                    input [159: 0]  seed,
+                    input [383 : 0] expected
+                  );
+    begin
+
+      $display("*** TC%01d - zeroize test started.", tc_ctr);
+
+      // First test: assert zeroize when engine is working
+      write_key(key);
+      
+      write_block(block0);
+
+      write_seed(seed);
+
+      write_single_word(ADDR_CTRL, CTRL_INIT_VALUE);
+      #CLK_PERIOD;
+      hsel_i_tb       = 0;
+
+      for (int i=0; i<10; i++)
+        begin
+          #(CLK_PERIOD);
+        end
+
+      write_single_word(ADDR_CTRL, {29'h0, 1'b1, 2'b0}); //zeroize
+
+      wait_ready();
+      read_digest();
+      if (digest_data == 0)
+        begin
+          $display("TC%01d final block: OK.", tc_ctr);
+        end
+      else
+        begin
+          $display("TC%01d: ERROR in final digest", tc_ctr);
+          $display("TC%01d: Expected: 0x%096x", tc_ctr, 0);
+          $display("TC%01d: Got:      0x%096x", tc_ctr, digest_data);
+          error_ctr = error_ctr + 1;
+        end
+      tc_ctr = tc_ctr + 1;
+
+      // Second test: assert zeroize with INIT
+      write_key(key);
+      
+      write_block(block0);
+
+      write_seed(seed);
+
+      write_single_word(ADDR_CTRL, {29'h0, 1'b1, CTRL_INIT_VALUE}); //zeroize
+      #CLK_PERIOD;
+      hsel_i_tb       = 0;
+      #(CLK_PERIOD);
+
+      wait_ready();
+      read_digest();
+      if (digest_data == 0)
+        begin
+          $display("TC%01d final block: OK.", tc_ctr);
+        end
+      else
+        begin
+          $display("TC%01d: ERROR in final digest", tc_ctr);
+          $display("TC%01d: Expected: 0x%096x", tc_ctr, 0);
+          $display("TC%01d: Got:      0x%096x", tc_ctr, digest_data);
+          error_ctr = error_ctr + 1;
+        end
+      tc_ctr = tc_ctr + 1;
+
+      // Third test: assert zeroize with NEXT
+      write_key(key);
+      
+      write_block(block0);
+
+      write_seed(seed);
+
+      write_single_word(ADDR_CTRL, {29'h0, 1'b1, CTRL_NEXT_VALUE}); //zeroize
+      #CLK_PERIOD;
+      hsel_i_tb       = 0;
+      #(CLK_PERIOD);
+
+      wait_ready();
+      read_digest();
+      if (digest_data == 0)
+        begin
+          $display("TC%01d final block: OK.", tc_ctr);
+        end
+      else
+        begin
+          $display("TC%01d: ERROR in final digest", tc_ctr);
+          $display("TC%01d: Expected: 0x%096x", tc_ctr, 0);
+          $display("TC%01d: Got:      0x%096x", tc_ctr, digest_data);
+          error_ctr = error_ctr + 1;
+        end
+      tc_ctr = tc_ctr + 1;
+
+      // Forth test: assert zeroize after NEXT
+      write_key(key);
+      
+      write_block(block0);
+
+      write_seed(seed);
+
+      write_single_word(ADDR_CTRL, CTRL_NEXT_VALUE);
+      #CLK_PERIOD;
+      hsel_i_tb       = 0;
+
+      for (int i=0; i<10; i++)
+        begin
+          #(CLK_PERIOD);
+        end
+
+      write_single_word(ADDR_CTRL, {29'h0, 1'b1, 2'b0}); //zeroize
+
+      wait_ready();
+      read_digest();
+      if (digest_data == 0)
+        begin
+          $display("TC%01d final block: OK.", tc_ctr);
+        end
+      else
+        begin
+          $display("TC%01d: ERROR in final digest", tc_ctr);
+          $display("TC%01d: Expected: 0x%096x", tc_ctr, 0);
+          $display("TC%01d: Got:      0x%096x", tc_ctr, digest_data);
+          error_ctr = error_ctr + 1;
+        end
+
+      $display("*** TC%01d - zeroize test done.", tc_ctr);
+      tc_ctr = tc_ctr + 1;
+    end
+  endtask // zeroize_test
+
   //----------------------------------------------------------------
   // hmac_tests()
   //
@@ -699,6 +931,10 @@ module hmac_ctrl_tb();
       seed4 = random_gen();
 
       double_block_test(key4, data40, data41, seed4, expected4);
+
+      continuous_cmd_test(key4, data40, data41, seed4, expected4);
+
+      zeroize_test(key4, data40, data41, seed4, expected4);
       
       $display("*** Testcases for PRF-HMAC-SHA-384 functionality completed.");
     end
diff --git a/src/hmac/uvmf_2022/config/compile.yml b/src/hmac/uvmf_2022/config/compile.yml
index 46d7a406a..1fc2a84f7 100644
--- a/src/hmac/uvmf_2022/config/compile.yml
+++ b/src/hmac/uvmf_2022/config/compile.yml
@@ -4,6 +4,7 @@ schema_version: 2.4.0
 requires:
   - uvmf_lib
   - hmac_ctrl
+  - hmac_coverage
 targets:
   tb:
     directories:
diff --git a/src/hmac/uvmf_2022/uvmf_template_output/project_benches/HMAC/tb/testbench/hdl_top.sv b/src/hmac/uvmf_2022/uvmf_template_output/project_benches/HMAC/tb/testbench/hdl_top.sv
index 9758dbce2..feeda3abe 100644
--- a/src/hmac/uvmf_2022/uvmf_template_output/project_benches/HMAC/tb/testbench/hdl_top.sv
+++ b/src/hmac/uvmf_2022/uvmf_template_output/project_benches/HMAC/tb/testbench/hdl_top.sv
@@ -98,7 +98,14 @@ hmac_ctrl #(
      .hsize_i       (HMAC_in_agent_bus.hsize),
      .hresp_o       (HMAC_out_agent_bus.hresp),
      .hreadyout_o   (HMAC_out_agent_bus.hreadyout),
-     .hrdata_o      (HMAC_out_agent_bus.hrdata)
+     .hrdata_o      (HMAC_out_agent_bus.hrdata),
+     .kv_read    (),
+     .kv_write   (),
+     .kv_rd_resp (),
+     .kv_wr_resp (),
+     .error_intr (),
+     .notif_intr (),
+     .debugUnlock_or_scan_mode_switch('0)
 );
  
   // pragma uvmf custom dut_instantiation end
diff --git a/src/hmac_drbg/config/hmac_drbg.vf b/src/hmac_drbg/config/hmac_drbg.vf
index 8e31d11fa..2e7367213 100644
--- a/src/hmac_drbg/config/hmac_drbg.vf
+++ b/src/hmac_drbg/config/hmac_drbg.vf
@@ -17,6 +17,7 @@ ${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
 ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_defines_pkg.sv
 ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_macros.svh
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_defines_pkg.sv
@@ -33,9 +34,9 @@ ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg.sv
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg_pkg.sv
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_params_pkg.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_ctrl.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512.sv
-${CALIPTRA_ROOT}/src/sha512/rtl/sha512_param.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_core.v
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_h_constants.v
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_k_constants.v
diff --git a/src/hmac_drbg/config/hmac_drbg_tb.vf b/src/hmac_drbg/config/hmac_drbg_tb.vf
index ab917c28f..9754c6784 100644
--- a/src/hmac_drbg/config/hmac_drbg_tb.vf
+++ b/src/hmac_drbg/config/hmac_drbg_tb.vf
@@ -18,6 +18,7 @@ ${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
 ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_defines_pkg.sv
 ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_macros.svh
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_defines_pkg.sv
@@ -35,9 +36,9 @@ ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg.sv
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg_pkg.sv
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_params_pkg.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_ctrl.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512.sv
-${CALIPTRA_ROOT}/src/sha512/rtl/sha512_param.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_core.v
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_h_constants.v
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_k_constants.v
diff --git a/src/integration/asserts/caliptra_top_sva.sv b/src/integration/asserts/caliptra_top_sva.sv
index ad44256df..8da8234aa 100644
--- a/src/integration/asserts/caliptra_top_sva.sv
+++ b/src/integration/asserts/caliptra_top_sva.sv
@@ -20,17 +20,23 @@
 //`include "kv_defines_pkg.sv"
 //`include "doe_defines_pkg.sv"
 `define CPTRA_TOP_PATH  caliptra_top_tb.caliptra_top_dut
-`define KEYVAULT_PATH   caliptra_top_tb.caliptra_top_dut.key_vault1
-`define DOE_PATH        caliptra_top_tb.caliptra_top_dut.doe.doe_inst.doe_fsm1
-`define DOE_REG_PATH    caliptra_top_tb.caliptra_top_dut.doe.doe_inst.i_doe_reg
+`define KEYVAULT_PATH   `CPTRA_TOP_PATH.key_vault1
+`define DOE_INST_PATH   `CPTRA_TOP_PATH.doe.doe_inst
+`define DOE_PATH        `DOE_INST_PATH.doe_fsm1
+`define DOE_REG_PATH    `DOE_INST_PATH.i_doe_reg
 `define SERVICES_PATH   caliptra_top_tb.tb_services_i
-`define SHA512_PATH     caliptra_top_tb.caliptra_top_dut.sha512.sha512_inst
-`define HMAC_PATH       caliptra_top_tb.caliptra_top_dut.hmac.hmac_inst
-`define ECC_PATH        caliptra_top_tb.caliptra_top_dut.ecc_top1.ecc_dsa_ctrl_i
-`define ECC_REG_PATH    caliptra_top_tb.caliptra_top_dut.ecc_top1.ecc_reg1
-`define SHA256_PATH     caliptra_top_tb.caliptra_top_dut.sha256.sha256_inst
-`define SHA512_MASKED_PATH caliptra_top_tb.caliptra_top_dut.ecc_top1.ecc_dsa_ctrl_i.ecc_hmac_drbg_interface_i.hmac_drbg_i.HMAC_K.u_sha512_core_h1
-
+`define SHA512_PATH     `CPTRA_TOP_PATH.sha512.sha512_inst
+`define HMAC_PATH       `CPTRA_TOP_PATH.hmac.hmac_inst
+`define ECC_PATH        `CPTRA_TOP_PATH.ecc_top1.ecc_dsa_ctrl_i
+`define ECC_REG_PATH    `CPTRA_TOP_PATH.ecc_top1.ecc_reg1
+`define SHA256_PATH     `CPTRA_TOP_PATH.sha256.sha256_inst
+`define SHA512_MASKED_PATH `CPTRA_TOP_PATH.ecc_top1.ecc_dsa_ctrl_i.ecc_hmac_drbg_interface_i.hmac_drbg_i.HMAC_K.u_sha512_core_h1
+`define SOC_IFC_TOP_PATH   `CPTRA_TOP_PATH.soc_ifc_top1
+`define WDT_PATH        `SOC_IFC_TOP_PATH.i_wdt
+
+`define SVA_RDC_CLK `CPTRA_TOP_PATH.rdc_clk_cg
+`define SVA_CLK caliptra_top_tb.core_clk
+`define SVA_RST caliptra_top_tb.cptra_rst_b
 
 module caliptra_top_sva
   import doe_defines_pkg::*;
@@ -47,54 +53,63 @@ module caliptra_top_sva
   localparam ECC_MEM_ADDR             = 2**6; //'ECC_PATH.ecc_arith_unit_i.ram_tdp_file_i.mem.ADDR_LENGTH
   localparam SHA256_DIG_NUM_DWORDS    = 8;    //`SHA256_PATH.DIG_NUM_DWORDS;
   localparam SHA256_BLOCK_NUM_DWORDS  = 16;   //`SHA256_PATH.BLOCK_NUM_DWORDS;
+  localparam DOE_256_NUM_ROUNDS       = 14;   //`DOE_INST_PATH.i_doe_core_cbc.keymem.DOE_256_NUM_ROUNDS
 
   //TODO: add disable condition based on doe cmd reg
   DOE_lock_uds_set:        assert property (
-                                            @(posedge `DOE_PATH.clk)
+                                            @(posedge `SVA_RDC_CLK)
+                                            disable iff (~`SVA_RST)
                                             $rose(`DOE_PATH.flow_done) && $past(doe_cmd_reg_t'(`DOE_PATH.doe_cmd_reg.cmd) == DOE_UDS) |=> `DOE_PATH.lock_uds_flow
                                           )
                             else $display("SVA ERROR: lock_uds_flow was not set after UDS flow");
 
+  //Note: lock + reset checks will use ungated clock. Using RDC clk throws the SVA off in the very first cycle where lock was 0
+  //but there's no $past value to compare against. This problem doesn't exist when using ungated clk because in the first cycle,
+  //pwrgood is also 0, so SVA is disabled.
   DOE_lock_uds_cold_reset: assert property (
-                                            @(posedge `DOE_PATH.clk)
+                                            @(posedge `SVA_CLK)
                                             ~`DOE_PATH.hard_rst_b |-> (`DOE_PATH.lock_uds_flow == 0)
                                           )
                             else $display("SVA ERROR: lock_uds_flow was not reset on hard reset");
 
   DOE_lock_uds_warm_reset: assert property (
-                                            @(posedge `DOE_PATH.clk)
+                                            @(posedge `SVA_CLK)
                                             disable iff (~`DOE_PATH.rst_b && ~`DOE_PATH.hard_rst_b)
                                             ~`DOE_PATH.rst_b |-> $past(`DOE_PATH.lock_uds_flow) == `DOE_PATH.lock_uds_flow
                                           )
                             else $display("SVA ERROR: lock_uds_flow toggled after warm reset");
-
   DOE_lock_fe_set:         assert property (
-                                            @(posedge `DOE_PATH.clk)
+                                            @(posedge `SVA_RDC_CLK)
+                                            disable iff (~`SVA_RST)
                                             $rose(`DOE_PATH.flow_done) && $past(doe_cmd_reg_t'(`DOE_PATH.doe_cmd_reg.cmd) == DOE_FE) |=> `DOE_PATH.lock_fe_flow
                                           )
                             else $display("SVA ERROR: lock_fe_flow was not set after FE flow");
 
   DOE_lock_fe_cold_reset:    assert property (
-                                            @(posedge `DOE_PATH.clk)
+                                            @(posedge `SVA_CLK)
                                             ~`DOE_PATH.hard_rst_b |-> (`DOE_PATH.lock_fe_flow == 0)
                                           )
                             else $display("SVA ERROR: lock_fe_flow was not reset on hard reset");
 
   DOE_lock_fe_warm_reset:    assert property (
-                                            @(posedge `DOE_PATH.clk)
+                                            @(posedge `SVA_CLK)
                                             disable iff (~`DOE_PATH.rst_b && ~`DOE_PATH.hard_rst_b)
                                             ~`DOE_PATH.rst_b |-> $past(`DOE_PATH.lock_fe_flow) == `DOE_PATH.lock_fe_flow
                                           )
                             else $display("SVA ERROR: lock_fe_flow toggled after warm reset");
 
+  //Corner case: when clear_obf_secrets and reset events happen in the same cycle, reset deassertion will cause SVA to start checking
+  //But if clear_obf_secrets was already 1 (not a pulse), it expects to see status valid in the next clk, but in design, it takes an extra
+  //cycle to update status. Adding a 1 cycle delay to avoid this case by starting the check when reset is deasserted
   DOE_clear_obf_status_valid: assert property (
-                                            @(posedge `CPTRA_TOP_PATH.clk)
-                                            `CPTRA_TOP_PATH.clear_obf_secrets |=> (`DOE_REG_PATH.field_storage.DOE_STATUS.VALID.value && `DOE_REG_PATH.field_storage.DOE_STATUS.DEOBF_SECRETS_CLEARED.value)
+                                            @(posedge `SVA_RDC_CLK)
+                                            disable iff (~`DOE_PATH.rst_b)
+                                            `CPTRA_TOP_PATH.clear_obf_secrets && `DOE_PATH.rst_b |=> (`DOE_REG_PATH.field_storage.DOE_STATUS.VALID.value && `DOE_REG_PATH.field_storage.DOE_STATUS.DEOBF_SECRETS_CLEARED.value)
                                           )
                             else $display("SVA ERROR: DOE STATUS valid bit not set after clear obf secrets cmd");
 
   KV_haddr_valid:          assert property (
-                                            @(posedge `CPTRA_TOP_PATH.clk)
+                                            @(posedge `SVA_RDC_CLK)
                                             disable iff (~`KEYVAULT_PATH.hsel_i)
                                             `KEYVAULT_PATH.hsel_i |-> !$isunknown(`KEYVAULT_PATH.haddr_i)
                                           )
@@ -104,16 +119,16 @@ module caliptra_top_sva
     for(genvar entry=0; entry < KV_NUM_KEYS; entry++) begin
       for(genvar dword = 0; dword < KV_NUM_DWORDS; dword++) begin
         KV_debug_value0:         assert property (
-                                                  @(posedge `KEYVAULT_PATH.clk)
+                                                  @(posedge `SVA_RDC_CLK)
                                                   disable iff(!`KEYVAULT_PATH.cptra_pwrgood)
-                                                  `KEYVAULT_PATH.flush_keyvault && (`KEYVAULT_PATH.kv_reg_hwif_out.CLEAR_SECRETS.sel_debug_value.value == 0) && `KEYVAULT_PATH.cptra_pwrgood |=> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[entry][dword] == CLP_DEBUG_MODE_KV_0)
+                                                  $rose(~`CPTRA_TOP_PATH.cptra_security_state_Latched.debug_locked || `SOC_IFC_TOP_PATH.cptra_error_fatal || `CPTRA_TOP_PATH.cptra_scan_mode_Latched) && (`KEYVAULT_PATH.kv_reg_hwif_out.CLEAR_SECRETS.sel_debug_value.value == 0) && `KEYVAULT_PATH.cptra_pwrgood |=> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[entry][dword] == CLP_DEBUG_MODE_KV_0)
                                                 )
                                   else $display("SVA ERROR: KV not flushed with correct debug values");
 
         KV_debug_value1:         assert property (
-                                                  @(posedge `KEYVAULT_PATH.clk)
+                                                  @(posedge `SVA_RDC_CLK)
                                                   disable iff(!`KEYVAULT_PATH.cptra_pwrgood)
-                                                  `KEYVAULT_PATH.flush_keyvault && (`KEYVAULT_PATH.kv_reg_hwif_out.CLEAR_SECRETS.sel_debug_value.value == 1) && `KEYVAULT_PATH.cptra_pwrgood |=> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[entry][dword] == CLP_DEBUG_MODE_KV_1)
+                                                  $rose(~`CPTRA_TOP_PATH.cptra_security_state_Latched.debug_locked || `SOC_IFC_TOP_PATH.cptra_error_fatal || `CPTRA_TOP_PATH.cptra_scan_mode_Latched) && (`KEYVAULT_PATH.kv_reg_hwif_out.CLEAR_SECRETS.sel_debug_value.value == 1) && `KEYVAULT_PATH.cptra_pwrgood |=> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[entry][dword] == CLP_DEBUG_MODE_KV_1)
                                                 )
                                   else $display("SVA ERROR: KV not flushed with correct debug values");
       end
@@ -124,7 +139,7 @@ module caliptra_top_sva
     for(genvar dword = 0; dword < KV_NUM_DWORDS; dword++) begin
       //sha512 block read
       kv_sha512_block_r_flow:   assert property (
-                                            @(posedge `KEYVAULT_PATH.clk)
+                                            @(posedge `SVA_RDC_CLK)
                                             $rose(`SHA512_PATH.kv_src_done & ~`SHA512_PATH.pcr_hash_extend_ip) && (dword < (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_CTRL[`SHA512_PATH.kv_read.read_entry].last_dword + 1)) |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`SHA512_PATH.kv_read.read_entry][dword] == `SHA512_PATH.block_reg[dword])
                                             )
                                 else $display("SVA ERROR: SHA384 block mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`SHA512_PATH.kv_read.read_entry][dword], `SHA512_PATH.block_reg[dword]);
@@ -132,7 +147,7 @@ module caliptra_top_sva
       //sha512 digest write
       if (dword < SHA512_DIG_NUM_DWORDS) begin
         kv_sha512_digest_w_flow:  assert property (
-                                              @(posedge `KEYVAULT_PATH.clk)
+                                              @(posedge `SVA_RDC_CLK)
                                               `SHA512_PATH.kv_dest_done & ~`SHA512_PATH.pcr_hash_extend_ip |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`SHA512_PATH.kv_write_ctrl_reg.write_entry][dword] == `SHA512_PATH.kv_reg[(KV_NUM_DWORDS-1) - dword])
                                               )
                                   else $display("SVA ERROR: SHA384 digest mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`SHA512_PATH.kv_write_ctrl_reg.write_entry][dword], `SHA512_PATH.kv_reg[(KV_NUM_DWORDS-1) - dword]);
@@ -140,7 +155,7 @@ module caliptra_top_sva
 
       //hmac block read
       kv_hmac_block_r_flow:     assert property (
-                                            @(posedge `KEYVAULT_PATH.clk)
+                                            @(posedge `SVA_RDC_CLK)
                                             $rose(`HMAC_PATH.kv_block_done) && (dword < (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_CTRL[`HMAC_PATH.kv_read[1].read_entry].last_dword + 1)) |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`HMAC_PATH.kv_read[1].read_entry][dword] == `HMAC_PATH.block_reg[dword])
                                             )
                                 else $display("SVA ERROR: HMAC384 block mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`HMAC_PATH.kv_read[1].read_entry][dword], `HMAC_PATH.block_reg[dword]);
@@ -148,7 +163,7 @@ module caliptra_top_sva
       //hmac key read
       if (dword < HMAC_KEY_NUM_DWORDS) begin
         kv_hmac_key_r_flow:       assert property (
-                                              @(posedge `KEYVAULT_PATH.clk)
+                                              @(posedge `SVA_RDC_CLK)
                                               $fell(`HMAC_PATH.kv_key_write_en) |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`HMAC_PATH.kv_read[0].read_entry][dword] == `HMAC_PATH.key_reg[dword])
                                               )
                                   else $display("SVA ERROR: HMAC384 key mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`HMAC_PATH.kv_read[0].read_entry][dword], `HMAC_PATH.key_reg[dword]);
@@ -157,7 +172,7 @@ module caliptra_top_sva
       //hmac tag write
       if (dword < HMAC_TAG_NUM_DWORDS) begin
         kv_hmac_tag_w_flow:       assert property (
-                                              @(posedge `KEYVAULT_PATH.clk)
+                                              @(posedge `SVA_RDC_CLK)
                                               `HMAC_PATH.kv_write_done |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`HMAC_PATH.kv_write_ctrl_reg.write_entry][dword] == `HMAC_PATH.kv_reg[(`HMAC_PATH.TAG_NUM_DWORDS-1) - dword])
                                               )
                                   else $display("SVA ERROR: HMAC384 tag mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`HMAC_PATH.kv_write_ctrl_reg.write_entry][dword], `HMAC_PATH.kv_reg[(`HMAC_PATH.TAG_NUM_DWORDS-1) - dword]);                    
@@ -167,46 +182,124 @@ module caliptra_top_sva
       if (dword < ECC_REG_NUM_DWORDS) begin
         //ecc privkey read
         kv_ecc_privkey_r_flow:    assert property (
-                                              @(posedge `KEYVAULT_PATH.clk)
+                                              @(posedge `SVA_RDC_CLK)
                                               $fell(`ECC_PATH.kv_privkey_write_en) |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`ECC_PATH.kv_read[0].read_entry][dword] == `ECC_PATH.privkey_reg[(`ECC_PATH.REG_NUM_DWORDS-1) - dword])
                                               )
                                   else $display("SVA ERROR: ECC privkey read mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`ECC_PATH.kv_read[0].read_entry][dword], `ECC_PATH.privkey_reg[(`ECC_PATH.REG_NUM_DWORDS-1) - dword]);
         kv_ecc_seed_r_flow:       assert property (
-                                              @(posedge `KEYVAULT_PATH.clk)
+                                              @(posedge `SVA_RDC_CLK)
                                               $fell(`ECC_PATH.kv_seed_write_en) |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`ECC_PATH.kv_read[1].read_entry][dword] == `ECC_PATH.seed_reg[(`ECC_PATH.REG_NUM_DWORDS-1) - dword])
                                               )
                                   else $display("SVA ERROR: ECC seed mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`ECC_PATH.kv_read[1].read_entry][dword], `ECC_PATH.seed_reg[(`ECC_PATH.REG_NUM_DWORDS-1) - dword]);
         //ecc privkey write
         kv_ecc_privkey_w_flow:    assert property (
-                                              @(posedge `KEYVAULT_PATH.clk)
+                                              @(posedge `SVA_RDC_CLK)
                                               `ECC_PATH.kv_write_done |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`ECC_PATH.kv_write_ctrl_reg.write_entry][dword] == `ECC_PATH.kv_reg[(`ECC_PATH.REG_NUM_DWORDS-1) - dword])
                                               )
                                   else $display("SVA ERROR: ECC privkey write mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`ECC_PATH.kv_write_ctrl_reg.write_entry][dword], `ECC_PATH.kv_reg[(`ECC_PATH.REG_NUM_DWORDS-1) - dword]);
 
         //ecc sign r
         pcr_ecc_sign_r:    assert property (
-                                              @(posedge `SERVICES_PATH.clk)
+                                              @(posedge `SVA_RDC_CLK)
                                               `SERVICES_PATH.check_pcr_signing |-> (`SERVICES_PATH.test_vector.R[dword] == `ECC_PATH.hwif_out.ECC_SIGN_R[dword].SIGN_R.value)
                                               )
                                   else $display("SVA ERROR: PCR SIGNING SIGN_R mismatch!, 0x%04x, 0x%04x", `SERVICES_PATH.test_vector.R[dword], `ECC_PATH.hwif_out.ECC_SIGN_R[dword].SIGN_R.value);                     
         
         //ecc sign s
         pcr_ecc_sign_s:    assert property (
-                                              @(posedge `SERVICES_PATH.clk)
+                                              @(posedge `SVA_RDC_CLK)
                                               `SERVICES_PATH.check_pcr_signing |-> (`SERVICES_PATH.test_vector.S[dword] == `ECC_PATH.hwif_out.ECC_SIGN_S[dword].SIGN_S.value)
                                               )
                                   else $display("SVA ERROR: PCR SIGNING SIGN_S mismatch!, 0x%04x, 0x%04x", `SERVICES_PATH.test_vector.S[dword], `ECC_PATH.hwif_out.ECC_SIGN_S[dword].SIGN_S.value); 
       end
+    end
+  endgenerate
 
+  `ifndef VERILATOR
+  generate
+    begin: UDS_data_check
+    for(genvar dword = 0; dword < `CLP_OBF_UDS_DWORDS; dword++) begin
+      DOE_UDS_data_check:  assert property (
+                                            @(posedge `SVA_RDC_CLK)
+                                            disable iff (`CPTRA_TOP_PATH.scan_mode || !`CPTRA_TOP_PATH.security_state.debug_locked)
+                                            (`SERVICES_PATH.WriteData == 'hEC && `SERVICES_PATH.mailbox_write) |=> ##[1:$] $rose(`DOE_PATH.lock_uds_flow) |=> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`DOE_REG_PATH.hwif_out.DOE_CTRL.DEST.value][dword] == `SERVICES_PATH.doe_test_vector.uds_plaintext[dword])
+                                
+                                          )
+                                  else $display("SVA ERROR: DOE UDS output %h does not match plaintext %h!", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`DOE_REG_PATH.hwif_out.DOE_CTRL.DEST.value][dword], `SERVICES_PATH.doe_test_vector.uds_plaintext[dword]);
+    end
+    end
+  endgenerate
+  generate
+    begin: FE_data_check
+    for(genvar dword = 0; dword < `CLP_OBF_FE_DWORDS; dword++) begin
+  
+      DOE_FE_data_check:   assert property (
+                                            @(posedge `SVA_RDC_CLK)
+                                            disable iff (`CPTRA_TOP_PATH.scan_mode || !`CPTRA_TOP_PATH.security_state.debug_locked)
+                                            (`SERVICES_PATH.WriteData == 'hED && `SERVICES_PATH.mailbox_write) |=> ##[1:$] $rose(`DOE_PATH.lock_fe_flow) |=> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`DOE_REG_PATH.hwif_out.DOE_CTRL.DEST.value][dword] == `SERVICES_PATH.doe_test_vector.fe_plaintext[dword])
+                                          )
+                                  else $display("SVA ERROR: DOE FE output %h does not match plaintext %h!", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`DOE_REG_PATH.hwif_out.DOE_CTRL.DEST.value][dword], `SERVICES_PATH.doe_test_vector.fe_plaintext[dword]);
 
     end
+    end
   endgenerate
+  `endif
+
+  //Generate disable signal for fuse_wr_check sva when hwclr is asserted. The disable needs to be for 3 clks in order to ignore the fuses being cleared
+  logic clear_obf_secrets_f;
+  logic clear_obf_secrets_ff;
+  logic clear_obf_secrets_int;
+
+  logic cptra_in_debug_scan_mode_f;
+  logic cptra_in_debug_scan_mode_fall_trans;
+  logic cptra_in_debug_scan_mode_fall_trans_f;
+  logic cptra_in_debug_scan_mode_int;
+
+  always@(posedge `SVA_RDC_CLK or negedge `CPTRA_TOP_PATH.cptra_rst_b) begin
+    if(!`CPTRA_TOP_PATH.cptra_rst_b) begin
+      clear_obf_secrets_f <= 'b0;
+      clear_obf_secrets_ff <= 'b0;
+    end
+    else begin
+      clear_obf_secrets_f <= `SOC_IFC_TOP_PATH.clear_obf_secrets;
+      clear_obf_secrets_ff <= clear_obf_secrets_f;
+    end
+  end
+
+  always@(posedge `SVA_RDC_CLK or negedge `CPTRA_TOP_PATH.cptra_rst_b) begin
+    if(!`CPTRA_TOP_PATH.cptra_rst_b) begin
+      cptra_in_debug_scan_mode_f <= 'b0;
+      cptra_in_debug_scan_mode_fall_trans_f <= 'b0;
+    end
+    else begin
+      cptra_in_debug_scan_mode_f <= `CPTRA_TOP_PATH.cptra_in_debug_scan_mode;
+      cptra_in_debug_scan_mode_fall_trans_f <= cptra_in_debug_scan_mode_fall_trans;
+    end
+  end
+
+  assign clear_obf_secrets_int = `SOC_IFC_TOP_PATH.clear_obf_secrets | clear_obf_secrets_f | clear_obf_secrets_ff;
+  assign cptra_in_debug_scan_mode_fall_trans = !`CPTRA_TOP_PATH.cptra_in_debug_scan_mode && cptra_in_debug_scan_mode_f;
+  assign cptra_in_debug_scan_mode_int = cptra_in_debug_scan_mode_fall_trans | cptra_in_debug_scan_mode_fall_trans_f;
+
+  UDS_fuse_wr_check: assert property (
+                                  @(posedge `SVA_RDC_CLK)
+                                  disable iff(`CPTRA_TOP_PATH.cptra_in_debug_scan_mode || clear_obf_secrets_int || cptra_in_debug_scan_mode_int)
+                                  (`SOC_IFC_TOP_PATH.soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value) |-> `CPTRA_TOP_PATH.obf_uds_seed == $past(`CPTRA_TOP_PATH.obf_uds_seed)
+  )
+  else $display("SVA ERROR: Unexpected write to obf uds seed!");
+
+  FE_fuse_wr_check: assert property (
+                                  @(posedge `SVA_RDC_CLK)
+                                  disable iff(`CPTRA_TOP_PATH.cptra_in_debug_scan_mode || clear_obf_secrets_int || cptra_in_debug_scan_mode_int)
+                                  (`SOC_IFC_TOP_PATH.soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value) |-> `CPTRA_TOP_PATH.obf_field_entropy == $past(`CPTRA_TOP_PATH.obf_field_entropy)
+  )
+  else $display("SVA ERROR: Unexpected write to obf field entropy!");
 
   //ZEROIZE SVA
   generate
     for(genvar dword = 0; dword < SHA256_BLOCK_NUM_DWORDS; dword++) begin
         sha256_block_zeroize:       assert property (
-                                              @(posedge `SHA256_PATH.clk)
+                                              @(posedge `SVA_RDC_CLK)
                                               `SHA256_PATH.hwif_out.SHA256_CTRL.ZEROIZE.value |=> (`SHA256_PATH.hwif_out.SHA256_BLOCK[dword].BLOCK.value == 0)
                                               )
                                   else $display("SVA ERROR: SHA256 block zeroize mismatch!");
@@ -214,7 +307,7 @@ module caliptra_top_sva
 
     for(genvar dword = 0; dword < SHA256_DIG_NUM_DWORDS; dword++) begin
         sha256_digest_zeroize:       assert property (
-                                              @(posedge `SHA256_PATH.clk)
+                                              @(posedge `SVA_RDC_CLK)
                                               `SHA256_PATH.hwif_out.SHA256_CTRL.ZEROIZE.value |=> (`SHA256_PATH.digest_reg[dword] == 0) & (`SHA256_PATH.i_sha256_reg.decoded_reg_strb.SHA256_DIGEST[dword] == 0)
                                               )
                                   else $display("SVA ERROR: SHA256 digest zeroize mismatch!");                                
@@ -222,7 +315,7 @@ module caliptra_top_sva
 
     for(genvar dword = 0; dword < SHA512_BLOCK_NUM_DWORDS; dword++) begin
         sha512_block_zeroize:       assert property (
-                                              @(posedge `SHA512_PATH.clk)
+                                              @(posedge `SVA_RDC_CLK)
                                               `SHA512_PATH.hwif_out.SHA512_CTRL.ZEROIZE.value |=> (`SHA512_PATH.hwif_out.SHA512_BLOCK[dword].BLOCK.value == 0)
                                               )
                                   else $display("SVA ERROR: SHA512 block zeroize mismatch!");
@@ -230,7 +323,7 @@ module caliptra_top_sva
 
     for(genvar dword = 0; dword < SHA512_DIG_NUM_DWORDS; dword++) begin
         sha512_digest_zeroize:       assert property (
-                                              @(posedge `SHA512_PATH.clk)
+                                              @(posedge `SVA_RDC_CLK)
                                               `SHA512_PATH.hwif_out.SHA512_CTRL.ZEROIZE.value |=> (`SHA512_PATH.digest_reg[dword] == 0) & (`SHA512_PATH.i_sha512_reg.decoded_reg_strb.SHA512_DIGEST[dword] == 0)
                                               )
                                   else $display("SVA ERROR: SHA512 digest zeroize mismatch!");                                
@@ -238,7 +331,7 @@ module caliptra_top_sva
 
     for(genvar dword = 0; dword < HMAC_KEY_NUM_DWORDS; dword++) begin
         hmac_key_zeroize:       assert property (
-                                              @(posedge `HMAC_PATH.clk)
+                                              @(posedge `SVA_RDC_CLK)
                                               `HMAC_PATH.hwif_out.HMAC384_CTRL.ZEROIZE.value |=> (`HMAC_PATH.hwif_out.HMAC384_KEY[dword].KEY.value == 0)
                                               )
                                   else $display("SVA ERROR: HMAC384 key zeroize mismatch!");
@@ -246,7 +339,7 @@ module caliptra_top_sva
     
     for(genvar dword = 0; dword < HMAC_BLOCK_NUM_DWORDS; dword++) begin
         hmac_block_zeroize:       assert property (
-                                              @(posedge `HMAC_PATH.clk)
+                                              @(posedge `SVA_RDC_CLK)
                                               `HMAC_PATH.hwif_out.HMAC384_CTRL.ZEROIZE.value |=> (`HMAC_PATH.hwif_out.HMAC384_BLOCK[dword].BLOCK.value == 0)
                                               )
                                   else $display("SVA ERROR: HMAC384 block zeroize mismatch!");
@@ -254,7 +347,7 @@ module caliptra_top_sva
 
     for(genvar dword = 0; dword < HMAC_TAG_NUM_DWORDS; dword++) begin
         hmac_tag_zeroize:       assert property (
-                                              @(posedge `HMAC_PATH.clk)
+                                              @(posedge `SVA_RDC_CLK)
                                               `HMAC_PATH.hwif_out.HMAC384_CTRL.ZEROIZE.value |=> (`HMAC_PATH.tag_reg[dword] == 0) & (`HMAC_PATH.i_hmac_reg.decoded_reg_strb.HMAC384_TAG[dword] == 0)
                                               )
                                   else $display("SVA ERROR: HMAC384 tag zeroize mismatch!");                      
@@ -263,36 +356,62 @@ module caliptra_top_sva
 
     for(genvar dword = 0; dword < ECC_REG_NUM_DWORDS; dword++) begin
         ecc_reg_zeroize:        assert property (
-                                              @(posedge `ECC_PATH.clk)
+                                              @(posedge `SVA_RDC_CLK)
                                               `ECC_PATH.hwif_out.ECC_CTRL.ZEROIZE.value |=> (`ECC_PATH.hwif_out.ECC_SEED[dword].SEED.value == 0) & (`ECC_PATH.hwif_out.ECC_NONCE[dword].NONCE.value == 0) & (`ECC_PATH.hwif_out.ECC_PRIVKEY_IN[dword].PRIVKEY_IN.value == 0) &
                                               (`ECC_PATH.hwif_out.ECC_MSG[dword].MSG.value == 0) & (`ECC_PATH.hwif_out.ECC_PUBKEY_X[dword].PUBKEY_X.value == 0) & (`ECC_PATH.hwif_out.ECC_PUBKEY_Y[dword].PUBKEY_Y.value == 0) &
                                               (`ECC_PATH.hwif_out.ECC_SIGN_R[dword].SIGN_R.value == 0) & (`ECC_PATH.hwif_out.ECC_SIGN_S[dword].SIGN_S.value == 0) & (`ECC_PATH.hwif_out.ECC_VERIFY_R[dword].VERIFY_R.value == 0) & (`ECC_PATH.hwif_out.ECC_IV[dword].IV.value == 0) &
                                               (`ECC_REG_PATH.decoded_reg_strb.ECC_PRIVKEY_OUT[dword] == 0)
                                               )
                                   else $display("SVA ERROR: ECC reg zeroize mismatch!"); 
-      end
+    end
     
     for(genvar addr = 0; addr < ECC_MEM_ADDR; addr++) begin
         ecc_mem_zeroize:        assert property (
-                                              @(posedge `ECC_PATH.clk)
+                                              @(posedge `SVA_RDC_CLK)
                                               `ECC_PATH.hwif_out.ECC_CTRL.ZEROIZE.value |=> (`ECC_PATH.ecc_arith_unit_i.ram_tdp_file_i.mem[addr] == 0)
                                               )
                                   else $display("SVA ERROR: ECC mem zeroize mismatch!"); 
-      end
+    end
+
+    for(genvar addr = 0; addr < DOE_256_NUM_ROUNDS; addr++) begin
+        doe_mem_zeroize:        assert property (
+                                              @(posedge `DOE_INST_PATH.clk)
+                                              `DOE_INST_PATH.zeroize |=> (`DOE_INST_PATH.i_doe_core_cbc.keymem.key_mem[addr] == 0)
+                                              )
+                                  else $display("SVA ERROR: DOE mem zeroize mismatch!"); 
+    end
   endgenerate
 
   sha512_masked_core_digest_zeroize:       assert property (
-                                      @(posedge `ECC_PATH.clk)
+                                      @(posedge `SVA_RDC_CLK)
                                       `ECC_PATH.hwif_out.ECC_CTRL.ZEROIZE.value |=> (`SHA512_MASKED_PATH.digest == 0) & (`SHA512_MASKED_PATH.a_reg == 0) & (`SHA512_MASKED_PATH.b_reg == 0) & (`SHA512_MASKED_PATH.c_reg == 0) & (`SHA512_MASKED_PATH.d_reg == 0) & (`SHA512_MASKED_PATH.e_reg == 0) & (`SHA512_MASKED_PATH.f_reg == 0) & (`SHA512_MASKED_PATH.g_reg == 0) & (`SHA512_MASKED_PATH.h_reg == 0)
                                       )
                           else $display("SVA ERROR: SHA512_masked_core digest zeroize mismatch!");  
+  
+  doe_block_zeroize:      assert property (
+                                      @(posedge `DOE_INST_PATH.clk)
+                                      `DOE_INST_PATH.zeroize |=> (`DOE_INST_PATH.i_doe_core_cbc.enc_block.new_block == 0) & (`DOE_INST_PATH.i_doe_core_cbc.dec_block.new_block == 0)
+                                      )
+                          else $display("SVA ERROR: DOE block zeroize mismatch!"); 
 
+  doe_reg_zeroize:      assert property (
+                                      @(posedge `DOE_INST_PATH.clk)
+                                      `DOE_INST_PATH.zeroize |=> (`DOE_INST_PATH.core_block == 0) & (`DOE_INST_PATH.core_IV == 0)
+                                      )
+                          else $display("SVA ERROR: DOE reg zeroize mismatch!"); 
+
+  doe_key_clear:      assert property (
+                                      @(posedge `DOE_INST_PATH.clk)
+                                      disable iff(`CPTRA_TOP_PATH.cptra_in_debug_scan_mode)
+                                      `DOE_INST_PATH.zeroize |=> (`DOE_INST_PATH.core_key == 0)
+                                      )
+                          else $display("SVA ERROR: DOE key clear mismatch!"); 
 
   genvar client;
   generate
     for(client = 0; client < KV_NUM_WRITE; client++) begin
       KV_client_wrdata_not_unknown: assert property (
-                                                    @(posedge `KEYVAULT_PATH.clk)
+                                                    @(posedge `SVA_RDC_CLK)
                                                     disable iff (!`KEYVAULT_PATH.kv_write[client].write_en || !`KEYVAULT_PATH.rst_b)
                                                     `KEYVAULT_PATH.kv_write[client].write_en |-> !$isunknown(`KEYVAULT_PATH.kv_write[client].write_data)
                                                   )
@@ -301,14 +420,113 @@ module caliptra_top_sva
 
     for(client = 0; client < KV_NUM_READ; client++) begin
       KV_client_rddata_not_unknown: assert property (
-                                                    @(posedge `KEYVAULT_PATH.clk)
+                                                    @(posedge `SVA_RDC_CLK)
                                                     disable iff (!`KEYVAULT_PATH.rst_b)
                                                     !$isunknown(`KEYVAULT_PATH.kv_rd_resp[client].read_data)
                                                   )
                                     else $display("SVA ERROR: KV client %0d data is unknown", client);
     end
   endgenerate
-    
+  
+  //WDT checks:
+  cascade_wdt_t1_pet: assert property (
+    @(posedge `WDT_PATH.clk)
+    (`WDT_PATH.timer1_restart && !`WDT_PATH.timer2_en) |=> (`WDT_PATH.timer1_count == 'h0)
+  )
+  else $display("SVA ERROR: [Cascade] WDT Timer1 did not restart on pet");
+
+  cascade_wdt_t2_pet: assert property (
+    @(posedge `WDT_PATH.clk)
+    (`WDT_PATH.timer2_restart && !`WDT_PATH.timer2_en) |=> (`WDT_PATH.timer2_count == 'h0)
+  )
+  else $display("SVA ERROR: [Cascade] WDT Timer2 did not restart on pet");
+
+  cascade_wdt_t1_service: assert property (
+    @(posedge `WDT_PATH.clk)
+    (`WDT_PATH.wdt_timer1_timeout_serviced && !`WDT_PATH.timer2_en && !`WDT_PATH.t2_timeout) |=> (`WDT_PATH.timer1_count == 'h0)
+  )
+  else $display("SVA ERROR: [Cascade] WDT Timer1 did not restart after interrupt service");
+
+  cascade_wdt_t2_service: assert property (
+    @(posedge `WDT_PATH.clk)
+    (`WDT_PATH.wdt_timer2_timeout_serviced && !`WDT_PATH.timer2_en) |=> (`WDT_PATH.timer2_count == 'h0)
+  )
+  else $display("SVA ERROR: [Cascade] WDT Timer2 did not restart after interrupt service");
+
+  independent_wdt_t1_pet: assert property (
+    @(posedge `WDT_PATH.clk)
+    (`WDT_PATH.timer1_restart && `WDT_PATH.timer2_en) |=> (`WDT_PATH.timer1_count == 'h0)
+  )
+  else $display("SVA ERROR: [Independent] WDT Timer1 did not restart on pet");
+
+  independent_wdt_t2_pet: assert property (
+    @(posedge `WDT_PATH.clk)
+    (`WDT_PATH.timer2_restart && `WDT_PATH.timer2_en) |=> (`WDT_PATH.timer2_count == 'h0)
+  )
+  else $display("SVA ERROR: [Independent] WDT Timer2 did not restart on pet");
+
+  independent_wdt_t1_service: assert property (
+    @(posedge `WDT_PATH.clk)
+    (`WDT_PATH.wdt_timer1_timeout_serviced && `WDT_PATH.timer2_en && !`WDT_PATH.t2_timeout) |=> (`WDT_PATH.timer1_count == 'h0)
+  )
+  else $display("SVA ERROR: [Independent] WDT Timer1 did not restart after interrupt service");
+
+  independent_wdt_t2_service: assert property (
+    @(posedge `WDT_PATH.clk)
+    (`WDT_PATH.wdt_timer2_timeout_serviced && `WDT_PATH.timer2_en) |=> (`WDT_PATH.timer2_count == 'h0)
+  )
+  else $display("SVA ERROR: [Independent] WDT Timer2 did not restart after interrupt service");
+
+
+
+  //VALID flag SVA
+  sha512_valid_flag:        assert property (
+                                    @(posedge `SVA_RDC_CLK)
+                                    `SHA512_PATH.digest_valid_reg |-> `SHA512_PATH.ready_reg
+                                    )
+                        else $display("SVA ERROR: SHA512 VALID flag mismatch!");
+                          
+  sha256_valid_flag:        assert property (
+                                        @(posedge `SVA_RDC_CLK)
+                                        `SHA256_PATH.digest_valid_reg |-> `SHA256_PATH.ready_reg
+                                        )
+                            else $display("SVA ERROR: SHA256 VALID flag mismatch!");
+
+  HMAC_valid_flag:      assert property (
+                                    @(posedge `SVA_RDC_CLK)
+                                    `HMAC_PATH.tag_valid_reg |-> `HMAC_PATH.ready_reg
+                                    )
+                        else $display("SVA ERROR: HMAC VALID flag mismatch!"); 
+
+  ECC_valid_flag:       assert property (
+                                    @(posedge `SVA_RDC_CLK)
+                                    `ECC_PATH.dsa_valid_reg |-> `ECC_PATH.dsa_ready_reg 
+                                    )
+                        else $display("SVA ERROR: ECC VALID flag mismatch!");      
+
+  //SVA for modular operations
+  ecc_opa_input:        assert property (
+                                      @(posedge `SVA_RDC_CLK)
+                                      (`ECC_PATH.ecc_arith_unit_i.ecc_fau_i.add_en_i | `ECC_PATH.ecc_arith_unit_i.ecc_fau_i.mult_en_i) |-> (`ECC_PATH.ecc_arith_unit_i.ecc_fau_i.opa_i < `ECC_PATH.ecc_arith_unit_i.ecc_fau_i.prime_i)
+                                      )
+                          else $display("SVA ERROR: ECC opa input is not valid!"); 
+
+  ecc_opb_input:        assert property (
+                                      @(posedge `SVA_RDC_CLK)
+                                      (`ECC_PATH.ecc_arith_unit_i.ecc_fau_i.add_en_i | `ECC_PATH.ecc_arith_unit_i.ecc_fau_i.mult_en_i) |-> (`ECC_PATH.ecc_arith_unit_i.ecc_fau_i.opb_i < `ECC_PATH.ecc_arith_unit_i.ecc_fau_i.prime_i)
+                                      )
+                          else $display("SVA ERROR: ECC opb input is not valid!"); 
+
+  ecc_add_result:       assert property (
+                                      @(posedge `SVA_RDC_CLK)
+                                      `ECC_PATH.ecc_arith_unit_i.ecc_instr_s.opcode.add_we |-> (`ECC_PATH.ecc_arith_unit_i.add_res_s < `ECC_PATH.ecc_arith_unit_i.adder_prime)
+                                      )
+                          else $display("SVA ERROR: ECC adder result is not valid!"); 
 
+  ecc_mult_result:       assert property (
+                                      @(posedge `SVA_RDC_CLK)
+                                      `ECC_PATH.ecc_arith_unit_i.ecc_instr_s.opcode.mult_we |-> (`ECC_PATH.ecc_arith_unit_i.mult_res_s < `ECC_PATH.ecc_arith_unit_i.adder_prime)
+                                      )
+                          else $display("SVA ERROR: ECC multiplier result is not valid!"); 
 endmodule
 
diff --git a/src/integration/config/caliptra_top.vf b/src/integration/config/caliptra_top.vf
index cfe8a2c30..44074db29 100644
--- a/src/integration/config/caliptra_top.vf
+++ b/src/integration/config/caliptra_top.vf
@@ -4,14 +4,15 @@
 +incdir+${CALIPTRA_ROOT}/src/pcrvault/rtl
 +incdir+${CALIPTRA_ROOT}/src/datavault/rtl
 +incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl
-+incdir+${CALIPTRA_ROOT}/src/soc_ifc/coverage
 +incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl
 +incdir+${CALIPTRA_ROOT}/src/doe/rtl
 +incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl
-+incdir+${CALIPTRA_ROOT}/src/prim/rtl
++incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl
 +incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl
 +incdir+${CALIPTRA_ROOT}/src/entropy_src/tb
 +incdir+${CALIPTRA_ROOT}/src/csrng/rtl
++incdir+${CALIPTRA_ROOT}/src/spi_host/rtl
++incdir+${CALIPTRA_ROOT}/src/uart/rtl
 +incdir+${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl
 +incdir+${CALIPTRA_ROOT}/src/sha512/rtl
 +incdir+${CALIPTRA_ROOT}/src/sha256/rtl
@@ -20,7 +21,7 @@
 +incdir+${CALIPTRA_ROOT}/src/hmac_drbg/rtl
 +incdir+${CALIPTRA_ROOT}/src/ecc/rtl
 +incdir+${CALIPTRA_ROOT}/src/kmac/rtl
-+incdir+${CALIPTRA_ROOT}/src/prim_generic/rtl
++incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl
 +incdir+${CALIPTRA_ROOT}/src/edn/rtl
 +incdir+${CALIPTRA_ROOT}/src/aes/rtl
 ${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh
@@ -34,6 +35,7 @@ ${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
 ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_defines_pkg.sv
 ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_macros.svh
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_defines_pkg.sv
@@ -42,8 +44,6 @@ ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_gen_hash.sv
 ${CALIPTRA_ROOT}/src/datavault/rtl/dv_defines_pkg.sv
 ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv
 ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv
-${CALIPTRA_ROOT}/src/soc_ifc/coverage/soc_ifc_cov_if.sv
-${CALIPTRA_ROOT}/src/soc_ifc/coverage/soc_ifc_cov_bind.sv
 ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pdef.vh
 ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/include/el2_def.sv
 ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/common_defines.sv
@@ -52,18 +52,22 @@ ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm_pkg.sv
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_ack_sm_pkg.sv
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_util_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_alert_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_mubi_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_cipher_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv
 ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv
 ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv
 ${CALIPTRA_ROOT}/src/entropy_src/tb/physical_rng.sv
 ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_pkg.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_reg_pkg.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_cmd_pkg.sv
+${CALIPTRA_ROOT}/src/uart/rtl/uart_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
 ${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_pkg.sv
 ${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv
@@ -125,18 +129,18 @@ ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg.sv
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg_pkg.sv
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_params_pkg.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_ctrl.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512.sv
-${CALIPTRA_ROOT}/src/sha512/rtl/sha512_param.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_core.v
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_h_constants.v
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_k_constants.v
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_w_mem.v
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg.sv
 ${CALIPTRA_ROOT}/src/sha256/rtl/sha256_reg_pkg.sv
+${CALIPTRA_ROOT}/src/sha256/rtl/sha256_params_pkg.sv
 ${CALIPTRA_ROOT}/src/sha256/rtl/sha256_ctrl.sv
 ${CALIPTRA_ROOT}/src/sha256/rtl/sha256.sv
-${CALIPTRA_ROOT}/src/sha256/rtl/sha256_param.sv
 ${CALIPTRA_ROOT}/src/sha256/rtl/sha256_core.v
 ${CALIPTRA_ROOT}/src/sha256/rtl/sha256_k_constants.v
 ${CALIPTRA_ROOT}/src/sha256/rtl/sha256_w_mem.v
@@ -203,37 +207,40 @@ ${CALIPTRA_ROOT}/src/kmac/rtl/keccak_round.sv
 ${CALIPTRA_ROOT}/src/kmac/rtl/keccak_2share.sv
 ${CALIPTRA_ROOT}/src/kmac/rtl/sha3pad.sv
 ${CALIPTRA_ROOT}/src/kmac/rtl/sha3.sv
-${CALIPTRA_ROOT}/src/prim_generic/rtl/prim_generic_flop.sv
-${CALIPTRA_ROOT}/src/prim_generic/rtl/prim_generic_buf.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_flop_2sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_lfsr.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_mubi4_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_diff_decode.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sec_anchor_buf.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_slicer.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_count.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sparse_fsm_flop.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_dom_and_2share.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sec_anchor_flop.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_reg_we_check.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_packer_fifo.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_max_tree.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg_arb.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_intr_hw.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_onehot_check.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_mubi8_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_fifo_sync_cnt.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_buf.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_lc_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_alert_receiver.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_flop.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_alert_sender.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_fifo_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_arbiter_ppc.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sum_tree.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg_ext.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_edge_detector.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_en.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cdc_rand_delay.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lfsr.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi4_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_diff_decode.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_slicer.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_count.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_dom_and_2share.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_reg_we_check.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_max_tree.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_arb.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_intr_hw.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_onehot_check.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi8_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync_cnt.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lc_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_receiver.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_sender.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_reg_top.sv
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_bucket_ht.sv
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_cntr_reg.sv
@@ -279,4 +286,18 @@ ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_block_encrypt.sv
 ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_state_db.sv
 ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_cmd_stage.sv
 ${CALIPTRA_ROOT}/src/csrng/rtl/csrng.sv
-${CALIPTRA_ROOT}/src/integration/rtl/caliptra_top.sv
\ No newline at end of file
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_byte_merge.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_byte_select.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_command_queue.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_core.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_data_fifos.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_fsm.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_reg_top.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_shift_register.sv
+${CALIPTRA_ROOT}/src/uart/rtl/uart_tx.sv
+${CALIPTRA_ROOT}/src/uart/rtl/uart_reg_top.sv
+${CALIPTRA_ROOT}/src/uart/rtl/uart_rx.sv
+${CALIPTRA_ROOT}/src/uart/rtl/uart.sv
+${CALIPTRA_ROOT}/src/uart/rtl/uart_core.sv
+${CALIPTRA_ROOT}/src/integration/rtl/caliptra_top.sv
diff --git a/src/integration/config/caliptra_top_tb.vf b/src/integration/config/caliptra_top_tb.vf
index 3760bc2f3..836578fd2 100644
--- a/src/integration/config/caliptra_top_tb.vf
+++ b/src/integration/config/caliptra_top_tb.vf
@@ -3,17 +3,26 @@
 +incdir+${CALIPTRA_ROOT}/src/integration/asserts
 +incdir+${CALIPTRA_ROOT}/src/integration/rtl
 +incdir+${CALIPTRA_ROOT}/src/libs/rtl
++incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl
++incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl
++incdir+${CALIPTRA_ROOT}/src/spi_host/rtl
++incdir+${CALIPTRA_ROOT}/src/spi_host/tb
 +incdir+${CALIPTRA_ROOT}/src/pcrvault/rtl
 +incdir+${CALIPTRA_ROOT}/src/datavault/rtl
 +incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl
-+incdir+${CALIPTRA_ROOT}/src/soc_ifc/coverage
 +incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl
 +incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl
-+incdir+${CALIPTRA_ROOT}/src/prim/rtl
-+incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl
 +incdir+${CALIPTRA_ROOT}/src/entropy_src/tb
 +incdir+${CALIPTRA_ROOT}/src/csrng/rtl
++incdir+${CALIPTRA_ROOT}/src/uart/rtl
++incdir+${CALIPTRA_ROOT}/src/sha512/coverage
++incdir+${CALIPTRA_ROOT}/src/sha256/coverage
++incdir+${CALIPTRA_ROOT}/src/hmac/coverage
++incdir+${CALIPTRA_ROOT}/src/ecc/coverage
++incdir+${CALIPTRA_ROOT}/src/soc_ifc/coverage
 +incdir+${CALIPTRA_ROOT}/src/integration/tb
++incdir+${CALIPTRA_ROOT}/src/integration/coverage
++incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl
 +incdir+${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl
 +incdir+${CALIPTRA_ROOT}/src/sha512/rtl
 +incdir+${CALIPTRA_ROOT}/src/sha256/rtl
@@ -22,7 +31,6 @@
 +incdir+${CALIPTRA_ROOT}/src/hmac_drbg/rtl
 +incdir+${CALIPTRA_ROOT}/src/ecc/rtl
 +incdir+${CALIPTRA_ROOT}/src/kmac/rtl
-+incdir+${CALIPTRA_ROOT}/src/prim_generic/rtl
 +incdir+${CALIPTRA_ROOT}/src/edn/rtl
 +incdir+${CALIPTRA_ROOT}/src/aes/rtl
 ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_defines_pkg.sv
@@ -40,14 +48,27 @@ ${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv
+${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv
+${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv
+${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_reg_pkg.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_cmd_pkg.sv
+${CALIPTRA_ROOT}/src/spi_host/tb/spi_device_pkg.sv
+${CALIPTRA_ROOT}/src/spi_host/tb/spiflash.sv
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_defines_pkg.sv
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_macros.svh
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_gen_hash.sv
 ${CALIPTRA_ROOT}/src/datavault/rtl/dv_defines_pkg.sv
 ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv
 ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv
-${CALIPTRA_ROOT}/src/soc_ifc/coverage/soc_ifc_cov_if.sv
-${CALIPTRA_ROOT}/src/soc_ifc/coverage/soc_ifc_cov_bind.sv
 ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pdef.vh
 ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/include/el2_def.sv
 ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/common_defines.sv
@@ -55,23 +76,71 @@ ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm_pkg.sv
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_ack_sm_pkg.sv
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_util_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_alert_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_mubi_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_cipher_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_pkg.sv
-${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv
-${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv
-${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv
 ${CALIPTRA_ROOT}/src/entropy_src/tb/physical_rng.sv
 ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_pkg.sv
-${CALIPTRA_ROOT}/src/integration/tb/caliptra_veer_sram_export.sv
+${CALIPTRA_ROOT}/src/uart/rtl/uart_reg_pkg.sv
+${CALIPTRA_ROOT}/src/sha512/coverage/sha512_ctrl_cov_if.sv
+${CALIPTRA_ROOT}/src/sha512/coverage/sha512_ctrl_cov_bind.sv
+${CALIPTRA_ROOT}/src/sha256/coverage/sha256_ctrl_cov_if.sv
+${CALIPTRA_ROOT}/src/sha256/coverage/sha256_ctrl_cov_bind.sv
+${CALIPTRA_ROOT}/src/hmac/coverage/hmac_ctrl_cov_if.sv
+${CALIPTRA_ROOT}/src/hmac/coverage/hmac_ctrl_cov_bind.sv
+${CALIPTRA_ROOT}/src/ecc/coverage/ecc_top_cov_if.sv
+${CALIPTRA_ROOT}/src/ecc/coverage/ecc_top_cov_bind.sv
+${CALIPTRA_ROOT}/src/soc_ifc/coverage/soc_ifc_cov_if.sv
+${CALIPTRA_ROOT}/src/soc_ifc/coverage/soc_ifc_cov_bind.sv
 ${CALIPTRA_ROOT}/src/integration/tb/caliptra_top_tb_pkg.sv
+${CALIPTRA_ROOT}/src/integration/tb/caliptra_veer_sram_export.sv
 ${CALIPTRA_ROOT}/src/integration/tb/caliptra_top_tb_services.sv
+${CALIPTRA_ROOT}/src/integration/coverage/caliptra_top_cov_if.sv
+${CALIPTRA_ROOT}/src/integration/coverage/caliptra_top_cov_bind.sv
+${CALIPTRA_ROOT}/src/integration/test_suites/libs/jtagdpi/jtagdpi.sv
 ${CALIPTRA_ROOT}/src/integration/tb/caliptra_top_tb.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_en.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cdc_rand_delay.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lfsr.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi4_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_diff_decode.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_slicer.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_count.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_dom_and_2share.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_reg_we_check.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_max_tree.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_arb.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_intr_hw.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_onehot_check.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi8_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync_cnt.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lc_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_receiver.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_sender.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_byte_merge.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_byte_select.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_command_queue.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_core.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_data_fifos.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_fsm.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_reg_top.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_shift_register.sv
 ${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_pkg.sv
 ${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv
 ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv
@@ -132,18 +201,18 @@ ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg.sv
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg_pkg.sv
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_params_pkg.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_ctrl.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512.sv
-${CALIPTRA_ROOT}/src/sha512/rtl/sha512_param.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_core.v
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_h_constants.v
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_k_constants.v
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_w_mem.v
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg.sv
 ${CALIPTRA_ROOT}/src/sha256/rtl/sha256_reg_pkg.sv
+${CALIPTRA_ROOT}/src/sha256/rtl/sha256_params_pkg.sv
 ${CALIPTRA_ROOT}/src/sha256/rtl/sha256_ctrl.sv
 ${CALIPTRA_ROOT}/src/sha256/rtl/sha256.sv
-${CALIPTRA_ROOT}/src/sha256/rtl/sha256_param.sv
 ${CALIPTRA_ROOT}/src/sha256/rtl/sha256_core.v
 ${CALIPTRA_ROOT}/src/sha256/rtl/sha256_k_constants.v
 ${CALIPTRA_ROOT}/src/sha256/rtl/sha256_w_mem.v
@@ -210,39 +279,6 @@ ${CALIPTRA_ROOT}/src/kmac/rtl/keccak_round.sv
 ${CALIPTRA_ROOT}/src/kmac/rtl/keccak_2share.sv
 ${CALIPTRA_ROOT}/src/kmac/rtl/sha3pad.sv
 ${CALIPTRA_ROOT}/src/kmac/rtl/sha3.sv
-${CALIPTRA_ROOT}/src/prim_generic/rtl/prim_generic_flop_en.sv
-${CALIPTRA_ROOT}/src/prim_generic/rtl/prim_generic_flop.sv
-${CALIPTRA_ROOT}/src/prim_generic/rtl/prim_generic_buf.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_flop_en.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_flop_2sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_lfsr.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_mubi4_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_diff_decode.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sec_anchor_buf.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_slicer.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_count.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sparse_fsm_flop.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_dom_and_2share.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sec_anchor_flop.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_reg_we_check.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_packer_fifo.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_max_tree.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg_arb.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_intr_hw.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_onehot_check.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_mubi8_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_fifo_sync_cnt.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_buf.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_lc_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_alert_receiver.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_flop.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_alert_sender.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_fifo_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_arbiter_ppc.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sum_tree.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg_ext.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_edge_detector.sv
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_reg_top.sv
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_bucket_ht.sv
 ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_cntr_reg.sv
@@ -288,21 +324,7 @@ ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_block_encrypt.sv
 ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_state_db.sv
 ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_cmd_stage.sv
 ${CALIPTRA_ROOT}/src/csrng/rtl/csrng.sv
-${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_reg_pkg.sv
-${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_cmd_pkg.sv
-${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host.sv
-${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_byte_merge.sv
-${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_byte_select.sv
-${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_command_queue.sv
-${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_core.sv
-${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_data_fifos.sv
-${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_fsm.sv
-${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_reg_top.sv
-${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_shift_register.sv
-${CALIPTRA_ROOT}/src/spi_host/tb/spi_device_pkg.sv
-${CALIPTRA_ROOT}/src/spi_host/tb/spiflash.sv
 ${CALIPTRA_ROOT}/src/uart/rtl/uart_tx.sv
-${CALIPTRA_ROOT}/src/uart/rtl/uart_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/uart/rtl/uart_reg_top.sv
 ${CALIPTRA_ROOT}/src/uart/rtl/uart_rx.sv
 ${CALIPTRA_ROOT}/src/uart/rtl/uart.sv
diff --git a/src/integration/config/caliptra_top_tb.vlt b/src/integration/config/caliptra_top_tb.vlt
index c56aba880..0aad893c5 100644
--- a/src/integration/config/caliptra_top_tb.vlt
+++ b/src/integration/config/caliptra_top_tb.vlt
@@ -1,9 +1,9 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
-${CALIPTRA_ROOT}/src/prim/lint/prim_onehot_check.vlt
-${CALIPTRA_ROOT}/src/prim/lint/prim_arbiter.vlt
+${CALIPTRA_ROOT}/src/caliptra_prim/lint/caliptra_prim_onehot_check.vlt
+${CALIPTRA_ROOT}/src/caliptra_prim/lint/caliptra_prim_arbiter.vlt
 ${CALIPTRA_ROOT}/src/csrng/lint/csrng.vlt
-${CALIPTRA_ROOT}/src/prim/lint/prim_max_tree.vlt
-${CALIPTRA_ROOT}/src/prim/lint/prim_sum_tree.vlt
-${CALIPTRA_ROOT}/src/prim/lint/prim_onehot_check.vlt
+${CALIPTRA_ROOT}/src/caliptra_prim/lint/caliptra_prim_max_tree.vlt
+${CALIPTRA_ROOT}/src/caliptra_prim/lint/caliptra_prim_sum_tree.vlt
+${CALIPTRA_ROOT}/src/caliptra_prim/lint/caliptra_prim_onehot_check.vlt
diff --git a/src/integration/config/caliptra_top_trng_tb.vf b/src/integration/config/caliptra_top_trng_tb.vf
new file mode 100644
index 000000000..6e8b39584
--- /dev/null
+++ b/src/integration/config/caliptra_top_trng_tb.vf
@@ -0,0 +1,332 @@
++incdir+${CALIPTRA_ROOT}/src/keyvault/rtl
++incdir+${CALIPTRA_ROOT}/src/doe/rtl
++incdir+${CALIPTRA_ROOT}/src/integration/asserts
++incdir+${CALIPTRA_ROOT}/src/integration/rtl
++incdir+${CALIPTRA_ROOT}/src/libs/rtl
++incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl
++incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl
++incdir+${CALIPTRA_ROOT}/src/spi_host/rtl
++incdir+${CALIPTRA_ROOT}/src/spi_host/tb
++incdir+${CALIPTRA_ROOT}/src/pcrvault/rtl
++incdir+${CALIPTRA_ROOT}/src/datavault/rtl
++incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl
++incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl
++incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl
++incdir+${CALIPTRA_ROOT}/src/entropy_src/tb
++incdir+${CALIPTRA_ROOT}/src/csrng/rtl
++incdir+${CALIPTRA_ROOT}/src/uart/rtl
++incdir+${CALIPTRA_ROOT}/src/sha512/coverage
++incdir+${CALIPTRA_ROOT}/src/sha256/coverage
++incdir+${CALIPTRA_ROOT}/src/hmac/coverage
++incdir+${CALIPTRA_ROOT}/src/ecc/coverage
++incdir+${CALIPTRA_ROOT}/src/soc_ifc/coverage
++incdir+${CALIPTRA_ROOT}/src/integration/tb
++incdir+${CALIPTRA_ROOT}/src/integration/coverage
++incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl
++incdir+${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl
++incdir+${CALIPTRA_ROOT}/src/sha512/rtl
++incdir+${CALIPTRA_ROOT}/src/sha256/rtl
++incdir+${CALIPTRA_ROOT}/src/sha512_masked/rtl
++incdir+${CALIPTRA_ROOT}/src/hmac/rtl
++incdir+${CALIPTRA_ROOT}/src/hmac_drbg/rtl
++incdir+${CALIPTRA_ROOT}/src/ecc/rtl
++incdir+${CALIPTRA_ROOT}/src/kmac/rtl
++incdir+${CALIPTRA_ROOT}/src/edn/rtl
++incdir+${CALIPTRA_ROOT}/src/aes/rtl
+${CALIPTRA_ROOT}/src/keyvault/rtl/kv_defines_pkg.sv
+${CALIPTRA_ROOT}/src/keyvault/rtl/kv_macros.svh
+${CALIPTRA_ROOT}/src/doe/rtl/doe_defines_pkg.sv
+${CALIPTRA_ROOT}/src/integration/asserts/caliptra_top_sva.sv
+${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh
+${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sva.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_macros.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sram.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_defines_pkg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_ahb_srom.sv
+${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv
+${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv
+${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv
+${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_reg_pkg.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_cmd_pkg.sv
+${CALIPTRA_ROOT}/src/spi_host/tb/spi_device_pkg.sv
+${CALIPTRA_ROOT}/src/spi_host/tb/spiflash.sv
+${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_defines_pkg.sv
+${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_macros.svh
+${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_gen_hash.sv
+${CALIPTRA_ROOT}/src/datavault/rtl/dv_defines_pkg.sv
+${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv
+${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pdef.vh
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/include/el2_def.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/common_defines.sv
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm_pkg.sv
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_ack_sm_pkg.sv
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_reg_pkg.sv
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_pkg.sv
+${CALIPTRA_ROOT}/src/entropy_src/tb/physical_rng.sv
+${CALIPTRA_ROOT}/src/csrng/rtl/csrng_reg_pkg.sv
+${CALIPTRA_ROOT}/src/csrng/rtl/csrng_pkg.sv
+${CALIPTRA_ROOT}/src/uart/rtl/uart_reg_pkg.sv
+${CALIPTRA_ROOT}/src/sha512/coverage/sha512_ctrl_cov_if.sv
+${CALIPTRA_ROOT}/src/sha512/coverage/sha512_ctrl_cov_bind.sv
+${CALIPTRA_ROOT}/src/sha256/coverage/sha256_ctrl_cov_if.sv
+${CALIPTRA_ROOT}/src/sha256/coverage/sha256_ctrl_cov_bind.sv
+${CALIPTRA_ROOT}/src/hmac/coverage/hmac_ctrl_cov_if.sv
+${CALIPTRA_ROOT}/src/hmac/coverage/hmac_ctrl_cov_bind.sv
+${CALIPTRA_ROOT}/src/ecc/coverage/ecc_top_cov_if.sv
+${CALIPTRA_ROOT}/src/ecc/coverage/ecc_top_cov_bind.sv
+${CALIPTRA_ROOT}/src/soc_ifc/coverage/soc_ifc_cov_if.sv
+${CALIPTRA_ROOT}/src/soc_ifc/coverage/soc_ifc_cov_bind.sv
+${CALIPTRA_ROOT}/src/integration/tb/caliptra_top_tb_pkg.sv
+${CALIPTRA_ROOT}/src/integration/tb/caliptra_veer_sram_export.sv
+${CALIPTRA_ROOT}/src/integration/tb/caliptra_top_tb_services.sv
+${CALIPTRA_ROOT}/src/integration/coverage/caliptra_top_cov_if.sv
+${CALIPTRA_ROOT}/src/integration/coverage/caliptra_top_cov_bind.sv
+${CALIPTRA_ROOT}/src/integration/test_suites/libs/jtagdpi/jtagdpi.sv
+${CALIPTRA_ROOT}/src/integration/tb/caliptra_top_tb.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_en.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cdc_rand_delay.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lfsr.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi4_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_diff_decode.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_slicer.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_count.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_dom_and_2share.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_reg_we_check.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_max_tree.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_arb.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_intr_hw.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_onehot_check.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi8_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync_cnt.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lc_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_receiver.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_sender.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_byte_merge.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_byte_select.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_command_queue.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_core.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_data_fifos.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_fsm.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_reg_top.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_shift_register.sv
+${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_pkg.sv
+${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_mem.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_dma_ctrl.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pic_ctrl.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dbg/el2_dbg.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_decode_ctl.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_gpr_ctl.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_ib_ctl.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_tlu_ctl.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dec/el2_dec_trigger.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dmi/dmi_jtag_to_core_sync.v
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dmi/dmi_wrapper.v
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/dmi/rvjtag_tap.v
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/exu/el2_exu_alu_ctl.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/exu/el2_exu_div_ctl.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/exu/el2_exu_mul_ctl.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/exu/el2_exu.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_aln_ctl.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_bp_ctl.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_compress_ctl.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_iccm_mem.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_ic_mem.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_ifc_ctl.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_mem_ctl.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/ifu/el2_ifu.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/ahb_to_axi4.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/axi4_to_ahb.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/el2_lib.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/mem_lib.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/el2_mem_if.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_addrcheck.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_buffer.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_intf.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_clkdomain.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_dccm_ctl.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_dccm_mem.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_ecc.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_lsc_ctl.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_stbuf.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_trigger.sv
+${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_lite_bus_inf.sv
+${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_lite_address_decoder.sv
+${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_lite_bus.sv
+${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_lite_2to1_mux.sv
+${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg_pkg.sv
+${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg.sv
+${CALIPTRA_ROOT}/src/keyvault/rtl/kv.sv
+${CALIPTRA_ROOT}/src/keyvault/rtl/kv_fsm.sv
+${CALIPTRA_ROOT}/src/keyvault/rtl/kv_read_client.sv
+${CALIPTRA_ROOT}/src/keyvault/rtl/kv_write_client.sv
+${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg_pkg.sv
+${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg.sv
+${CALIPTRA_ROOT}/src/pcrvault/rtl/pv.sv
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg_pkg.sv
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_params_pkg.sv
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_ctrl.sv
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512.sv
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_core.v
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_h_constants.v
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_k_constants.v
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_w_mem.v
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg.sv
+${CALIPTRA_ROOT}/src/sha256/rtl/sha256_reg_pkg.sv
+${CALIPTRA_ROOT}/src/sha256/rtl/sha256_params_pkg.sv
+${CALIPTRA_ROOT}/src/sha256/rtl/sha256_ctrl.sv
+${CALIPTRA_ROOT}/src/sha256/rtl/sha256.sv
+${CALIPTRA_ROOT}/src/sha256/rtl/sha256_core.v
+${CALIPTRA_ROOT}/src/sha256/rtl/sha256_k_constants.v
+${CALIPTRA_ROOT}/src/sha256/rtl/sha256_w_mem.v
+${CALIPTRA_ROOT}/src/sha256/rtl/sha256_reg.sv
+${CALIPTRA_ROOT}/src/doe/rtl/doe_reg_pkg.sv
+${CALIPTRA_ROOT}/src/doe/rtl/doe_ctrl.sv
+${CALIPTRA_ROOT}/src/doe/rtl/doe_decipher_block.sv
+${CALIPTRA_ROOT}/src/doe/rtl/doe_encipher_block.sv
+${CALIPTRA_ROOT}/src/doe/rtl/doe_inv_sbox.sv
+${CALIPTRA_ROOT}/src/doe/rtl/doe_key_mem.sv
+${CALIPTRA_ROOT}/src/doe/rtl/doe_sbox.sv
+${CALIPTRA_ROOT}/src/doe/rtl/doe_cbc.sv
+${CALIPTRA_ROOT}/src/doe/rtl/doe_core_cbc.sv
+${CALIPTRA_ROOT}/src/doe/rtl/doe_reg.sv
+${CALIPTRA_ROOT}/src/doe/rtl/doe_fsm.sv
+${CALIPTRA_ROOT}/src/sha512_masked/rtl/sha512_masked_defines_pkg.sv
+${CALIPTRA_ROOT}/src/sha512_masked/rtl/sha512_masked_core.sv
+${CALIPTRA_ROOT}/src/sha512_masked/rtl/sha512_masked_lfsr.sv
+${CALIPTRA_ROOT}/src/hmac/rtl/hmac_param_pkg.sv
+${CALIPTRA_ROOT}/src/hmac/rtl/hmac_reg_pkg.sv
+${CALIPTRA_ROOT}/src/hmac/rtl/hmac_ctrl.sv
+${CALIPTRA_ROOT}/src/hmac/rtl/hmac.sv
+${CALIPTRA_ROOT}/src/hmac/rtl/hmac_core.v
+${CALIPTRA_ROOT}/src/hmac/rtl/hmac_reg.sv
+${CALIPTRA_ROOT}/src/hmac_drbg/rtl/hmac_drbg.sv
+${CALIPTRA_ROOT}/src/hmac_drbg/rtl/hmac_drbg_lfsr.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_reg_pkg.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_defines_pkg.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_params_pkg.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_dsa_uop_pkg.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_pm_uop_pkg.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_top.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_reg.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_dsa_ctrl.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_dsa_sequencer.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_scalar_blinding.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_hmac_drbg_interface.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_arith_unit.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_pm_ctrl.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_pm_sequencer.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_ram_tdp_file.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_fau.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_montgomerymultiplier.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_pe_first.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_pe.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_pe_final.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_mult_dsp.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_add_sub_mod_alter.sv
+${CALIPTRA_ROOT}/src/ecc/rtl/ecc_adder.sv
+${CALIPTRA_ROOT}/src/datavault/rtl/dv_reg_pkg.sv
+${CALIPTRA_ROOT}/src/datavault/rtl/dv_reg.sv
+${CALIPTRA_ROOT}/src/datavault/rtl/dv.sv
+${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_top.sv
+${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_boot_fsm.sv
+${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_arb.sv
+${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg.sv
+${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox.sv
+${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr.sv
+${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_top.sv
+${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr.sv
+${CALIPTRA_ROOT}/src/soc_ifc/rtl/wdt.sv
+${CALIPTRA_ROOT}/src/kmac/rtl/sha3_pkg.sv
+${CALIPTRA_ROOT}/src/kmac/rtl/keccak_round.sv
+${CALIPTRA_ROOT}/src/kmac/rtl/keccak_2share.sv
+${CALIPTRA_ROOT}/src/kmac/rtl/sha3pad.sv
+${CALIPTRA_ROOT}/src/kmac/rtl/sha3.sv
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_reg_top.sv
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_bucket_ht.sv
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_cntr_reg.sv
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_enable_delay.sv
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_markov_ht.sv
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_watermark_reg.sv
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm.sv
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_repcnts_ht.sv
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_adaptp_ht.sv
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_core.sv
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_repcnt_ht.sv
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_ack_sm.sv
+${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src.sv
+${CALIPTRA_ROOT}/src/edn/rtl/edn_pkg.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_reg_pkg.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_pkg.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_sbox_canright_pkg.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_sbox_canright.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_sbox_canright_masked.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_cipher_core.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_sbox.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_cipher_control_fsm_n.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_cipher_control_fsm_p.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_sbox_lut.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_mix_columns.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_sbox_dom.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_sub_bytes.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_sbox_canright_masked_noreuse.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_sel_buf_chk.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_cipher_control_fsm.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_shift_rows.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_mix_single_column.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_cipher_control.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_prng_masking.sv
+${CALIPTRA_ROOT}/src/aes/rtl/aes_key_expand.sv
+${CALIPTRA_ROOT}/src/csrng/rtl/csrng_core.sv
+${CALIPTRA_ROOT}/src/csrng/rtl/csrng_main_sm.sv
+${CALIPTRA_ROOT}/src/csrng/rtl/csrng_ctr_drbg_upd.sv
+${CALIPTRA_ROOT}/src/csrng/rtl/csrng_ctr_drbg_cmd.sv
+${CALIPTRA_ROOT}/src/csrng/rtl/csrng_reg_top.sv
+${CALIPTRA_ROOT}/src/csrng/rtl/csrng_ctr_drbg_gen.sv
+${CALIPTRA_ROOT}/src/csrng/rtl/csrng_block_encrypt.sv
+${CALIPTRA_ROOT}/src/csrng/rtl/csrng_state_db.sv
+${CALIPTRA_ROOT}/src/csrng/rtl/csrng_cmd_stage.sv
+${CALIPTRA_ROOT}/src/csrng/rtl/csrng.sv
+${CALIPTRA_ROOT}/src/uart/rtl/uart_tx.sv
+${CALIPTRA_ROOT}/src/uart/rtl/uart_reg_top.sv
+${CALIPTRA_ROOT}/src/uart/rtl/uart_rx.sv
+${CALIPTRA_ROOT}/src/uart/rtl/uart.sv
+${CALIPTRA_ROOT}/src/uart/rtl/uart_core.sv
+${CALIPTRA_ROOT}/src/integration/rtl/caliptra_top.sv
\ No newline at end of file
diff --git a/src/integration/config/compile.yml b/src/integration/config/compile.yml
index b1aa6e888..564ce173c 100644
--- a/src/integration/config/compile.yml
+++ b/src/integration/config/compile.yml
@@ -65,20 +65,49 @@ schema_version: 2.4.0
 requires:
   - asserts
   - libs
+  - spiflash
   - caliptra_top
   - el2_veer_pkg
   - el2_veer_wrapper
+  - sha512_coverage
+  - sha256_coverage
+  - hmac_coverage
+  - ecc_coverage
+  - soc_ifc_coverage
 targets:
+  dpi_compile:
+    directories:
+      - $COMPILE_ROOT/test_suites/libs/tcp_server
+      - $COMPILE_ROOT/test_suites/libs/jtagdpi
+    files:
+      - $COMPILE_ROOT/test_suites/libs/tcp_server/tcp_server.h
+      - $COMPILE_ROOT/test_suites/libs/tcp_server/tcp_server.c
+      - $COMPILE_ROOT/test_suites/libs/jtagdpi/jtagdpi.h
+      - $COMPILE_ROOT/test_suites/libs/jtagdpi/jtagdpi.c
+    options:
+      - '-Wno-unused-variable'
+      - '-Wno-unused-function'
+      - tool:
+          vcs:
+            - '-DVCS'
+          ius:
+            - '-DXCELIUM'
   tb:
-    directories: [$COMPILE_ROOT/tb]
+    directories: #[$COMPILE_ROOT/tb]
+      - $COMPILE_ROOT/tb
+      - $COMPILE_ROOT/coverage
     files:
-      - $COMPILE_ROOT/tb/caliptra_veer_sram_export.sv
       - $COMPILE_ROOT/tb/caliptra_top_tb_pkg.sv
+      - $COMPILE_ROOT/tb/caliptra_veer_sram_export.sv
       - $COMPILE_ROOT/tb/caliptra_top_tb_services.sv
+      - $COMPILE_ROOT/coverage/caliptra_top_cov_if.sv
+      - $COMPILE_ROOT/coverage/caliptra_top_cov_bind.sv
+      - $COMPILE_ROOT/test_suites/libs/jtagdpi/jtagdpi.sv
       - $COMPILE_ROOT/tb/caliptra_top_tb.sv
     tops: [caliptra_top_tb]
   sim:
-    pre_exec: '$MSFT_TOOLS/scripts/run_test_makefile && echo "[PRE-EXEC] Copying ECC vector generator to $(pwd)" && cp $COMPILE_ROOT/../ecc/tb/ecdsa_secp384r1.exe .'
+    pre_exec: '$MSFT_TOOLS/scripts/run_test_makefile && echo "[PRE-EXEC] Copying ECC vector generator to ${pwd}" && cp $COMPILE_ROOT/../ecc/tb/ecdsa_secp384r1.exe . 
+                && echo "[PRE-EXEC] Copying DOE vector generator to ${pwd}" && cp $COMPILE_ROOT/../doe/tb/doe_test_gen.py .'
 global:
   tool:
     vcs:
@@ -93,3 +122,22 @@ global:
       #sim:
         #- '-ucli -i dump.ucli'
 
+---
+provides: [caliptra_top_trng_tb]
+schema_version: 2.4.0
+requires:
+  - caliptra_top_tb
+targets:
+  tb:
+    tops: [caliptra_top_tb]
+  sim:
+    pre_exec: '$MSFT_TOOLS/scripts/run_test_makefile && echo "[PRE-EXEC] Copying ECC vector generator to ${pwd}" && cp $COMPILE_ROOT/../ecc/tb/ecdsa_secp384r1.exe . 
+                && echo "[PRE-EXEC] Copying DOE vector generator to ${pwd}" && cp $COMPILE_ROOT/../doe/tb/doe_test_gen.py .'
+global:
+  tool:
+    vcs:
+      default:
+        - '-assert svaext'
+        - +define+CLP_ASSERT_ON
+        - '-noinherit_timescale=1ns/1ps'
+        - '+define+CALIPTRA_INTERNAL_TRNG'
diff --git a/src/integration/coverage/caliptra_top_cov_bind.sv b/src/integration/coverage/caliptra_top_cov_bind.sv
new file mode 100644
index 000000000..7f7903840
--- /dev/null
+++ b/src/integration/coverage/caliptra_top_cov_bind.sv
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+module caliptra_top_cov_bind;
+    `ifdef FCOV
+    bind caliptra_top caliptra_top_cov_if i_caliptra_top_cov_if(.*);
+    `endif
+endmodule
diff --git a/src/integration/coverage/caliptra_top_cov_if.sv b/src/integration/coverage/caliptra_top_cov_if.sv
new file mode 100644
index 000000000..fe5ff93b3
--- /dev/null
+++ b/src/integration/coverage/caliptra_top_cov_if.sv
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+`ifndef VERILATOR
+
+interface caliptra_top_cov_if   
+    import soc_ifc_pkg::*;  
+    (
+    input logic clk,
+    input logic PSEL,
+    input logic [63:0] generic_input_wires,
+    input logic cptra_rst_b,
+    input logic cptra_pwrgood,
+    input logic scan_mode,
+    input security_state_t security_state,
+    input logic cptra_error_fatal
+);
+    
+    logic clk_gating_en;
+    logic cpu_halt_status;
+    logic wdt_timer1_en;
+    logic wdt_timer2_en;
+    logic nmi_int;
+
+    assign clk_gating_en = caliptra_top.cg.clk_gate_en;
+    assign cpu_halt_status = caliptra_top.cg.cpu_halt_status;
+    assign wdt_timer1_en = caliptra_top.soc_ifc_top1.i_wdt.timer1_en;
+    assign wdt_timer2_en = caliptra_top.soc_ifc_top1.i_wdt.timer2_en;
+    assign nmi_int = caliptra_top.nmi_int;
+    
+
+    covergroup caliptra_top_cov_grp @(posedge clk);
+        option.per_instance = 1;
+
+        //-----------------------------------------
+        //WDT coverpoints
+        //-----------------------------------------
+        wdt_t1: coverpoint wdt_timer1_en;
+        wdt_t2: coverpoint wdt_timer2_en;
+        wdt_t1Xt2: cross wdt_t1, wdt_t2;
+        wdt_t1t2Xwarmrst: cross wdt_t1Xt2, cptra_rst_b;
+        wdt_t1t2Xcoldrst: cross wdt_t1Xt2, cptra_pwrgood;
+
+        //-----------------------------------------
+        //CLK GATING coverpoints
+        //-----------------------------------------
+        apb_txn:            coverpoint PSEL {
+            bins single_apb_txn = (0 => 1 => 0);
+            bins b2b_apb_txn = (1 [*5]); //5 txns in a row
+        }
+        cg_en:              coverpoint clk_gating_en;
+        core_asleep_value:  coverpoint cpu_halt_status;
+        core_asleep_trans:  coverpoint cpu_halt_status {
+            bins bin01 = (0 => 1);
+            bins bin10 = (1 => 0);
+        }
+        warm_rst:           coverpoint cptra_rst_b;
+
+        scan:               coverpoint scan_mode;
+        debug:              coverpoint security_state.debug_locked;
+        fatal_error:        coverpoint cptra_error_fatal;
+        nmi:                coverpoint nmi_int;
+        generic:            coverpoint generic_input_wires;
+
+        enXcore_asleep:             cross cg_en, core_asleep_value {
+            ignore_bins b0 = enXcore_asleep with ((cg_en == 0) && (core_asleep_value == 1));
+        }
+        enXcore_asleepXwarm_rst:    cross enXcore_asleep, warm_rst;
+        enXcore_asleepXcold_rst:    cross enXcore_asleep, cptra_pwrgood;
+        // {
+        //     ignore_bins b0 = enXcore_asleepXwarm_rst with ((cg_en == 1) && (core_asleep_value == 1) && (warm_rst == 0));
+        // }
+        enXcore_asleepXwdt1:        cross enXcore_asleep, wdt_t1;
+        enXcore_asleepXwdt2:        cross enXcore_asleep, wdt_t2;
+
+        enXcore_asleepXscan:        cross enXcore_asleep, scan;
+        enXcore_asleepXdebug:       cross enXcore_asleep, debug;
+        enXcore_asleepXfatalerr:    cross enXcore_asleep, fatal_error;
+        enXcore_asleepXnmi:         cross enXcore_asleep, nmi;
+        enXcore_asleepXapb:         cross enXcore_asleep, apb_txn;
+        enXcore_asleepXgeneric:     cross enXcore_asleep, generic;
+    endgroup
+
+    covergroup generic_input_wires_cg(input logic generic_bit) @(posedge clk);
+        option.per_instance = 1;
+        value:      coverpoint generic_bit;
+        transition: coverpoint generic_bit {
+            bins bin01 = (0 => 1);
+            bins bin10 = (1 => 0);
+        }
+    endgroup
+
+    // CLK_GATING_cov_grp CLK_GATING_cov_grp1 = new();
+    // WDT_cov_grp WDT_cov_grp1 = new();
+    caliptra_top_cov_grp caliptra_top_cov_grp1 = new();
+    
+    generic_input_wires_cg giw_cg[64];
+    //foreach(giw_cg[i]) giw_cg[i] = new(generic_input_wires[i]);
+    initial begin
+        for(int i = 0; i < 64; i++) begin
+            giw_cg[i] = new(generic_input_wires[i]);
+        end
+    end
+
+endinterface
+
+`endif
\ No newline at end of file
diff --git a/src/integration/rtl/caliptra_reg.h b/src/integration/rtl/caliptra_reg.h
index 82028a21e..eb10fd96d 100644
--- a/src/integration/rtl/caliptra_reg.h
+++ b/src/integration/rtl/caliptra_reg.h
@@ -15,6 +15,7 @@
 #ifndef CALIPTRA_REG_HEADER
 #define CALIPTRA_REG_HEADER
 
+
 #define CLP_BASE_ADDR                                                                               (0x0)
 #define CLP_DOE_REG_BASE_ADDR                                                                       (0x10000000)
 #define CLP_DOE_REG_DOE_IV_0                                                                        (0x10000000)
@@ -3481,346 +3482,346 @@
 #define DV_REG_STICKY_DATA_VAULT_ENTRY_9_10                                                         (0x200)
 #define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_9_11                                                     (0x1001c204)
 #define DV_REG_STICKY_DATA_VAULT_ENTRY_9_11                                                         (0x204)
-#define CLP_DV_REG_NONSTICKYDATAVAULTCTRL_0                                                         (0x1001c208)
-#define DV_REG_NONSTICKYDATAVAULTCTRL_0                                                             (0x208)
-#define DV_REG_NONSTICKYDATAVAULTCTRL_0_LOCK_ENTRY_LOW                                              (0)
-#define DV_REG_NONSTICKYDATAVAULTCTRL_0_LOCK_ENTRY_MASK                                             (0x1)
-#define CLP_DV_REG_NONSTICKYDATAVAULTCTRL_1                                                         (0x1001c20c)
-#define DV_REG_NONSTICKYDATAVAULTCTRL_1                                                             (0x20c)
-#define DV_REG_NONSTICKYDATAVAULTCTRL_1_LOCK_ENTRY_LOW                                              (0)
-#define DV_REG_NONSTICKYDATAVAULTCTRL_1_LOCK_ENTRY_MASK                                             (0x1)
-#define CLP_DV_REG_NONSTICKYDATAVAULTCTRL_2                                                         (0x1001c210)
-#define DV_REG_NONSTICKYDATAVAULTCTRL_2                                                             (0x210)
-#define DV_REG_NONSTICKYDATAVAULTCTRL_2_LOCK_ENTRY_LOW                                              (0)
-#define DV_REG_NONSTICKYDATAVAULTCTRL_2_LOCK_ENTRY_MASK                                             (0x1)
-#define CLP_DV_REG_NONSTICKYDATAVAULTCTRL_3                                                         (0x1001c214)
-#define DV_REG_NONSTICKYDATAVAULTCTRL_3                                                             (0x214)
-#define DV_REG_NONSTICKYDATAVAULTCTRL_3_LOCK_ENTRY_LOW                                              (0)
-#define DV_REG_NONSTICKYDATAVAULTCTRL_3_LOCK_ENTRY_MASK                                             (0x1)
-#define CLP_DV_REG_NONSTICKYDATAVAULTCTRL_4                                                         (0x1001c218)
-#define DV_REG_NONSTICKYDATAVAULTCTRL_4                                                             (0x218)
-#define DV_REG_NONSTICKYDATAVAULTCTRL_4_LOCK_ENTRY_LOW                                              (0)
-#define DV_REG_NONSTICKYDATAVAULTCTRL_4_LOCK_ENTRY_MASK                                             (0x1)
-#define CLP_DV_REG_NONSTICKYDATAVAULTCTRL_5                                                         (0x1001c21c)
-#define DV_REG_NONSTICKYDATAVAULTCTRL_5                                                             (0x21c)
-#define DV_REG_NONSTICKYDATAVAULTCTRL_5_LOCK_ENTRY_LOW                                              (0)
-#define DV_REG_NONSTICKYDATAVAULTCTRL_5_LOCK_ENTRY_MASK                                             (0x1)
-#define CLP_DV_REG_NONSTICKYDATAVAULTCTRL_6                                                         (0x1001c220)
-#define DV_REG_NONSTICKYDATAVAULTCTRL_6                                                             (0x220)
-#define DV_REG_NONSTICKYDATAVAULTCTRL_6_LOCK_ENTRY_LOW                                              (0)
-#define DV_REG_NONSTICKYDATAVAULTCTRL_6_LOCK_ENTRY_MASK                                             (0x1)
-#define CLP_DV_REG_NONSTICKYDATAVAULTCTRL_7                                                         (0x1001c224)
-#define DV_REG_NONSTICKYDATAVAULTCTRL_7                                                             (0x224)
-#define DV_REG_NONSTICKYDATAVAULTCTRL_7_LOCK_ENTRY_LOW                                              (0)
-#define DV_REG_NONSTICKYDATAVAULTCTRL_7_LOCK_ENTRY_MASK                                             (0x1)
-#define CLP_DV_REG_NONSTICKYDATAVAULTCTRL_8                                                         (0x1001c228)
-#define DV_REG_NONSTICKYDATAVAULTCTRL_8                                                             (0x228)
-#define DV_REG_NONSTICKYDATAVAULTCTRL_8_LOCK_ENTRY_LOW                                              (0)
-#define DV_REG_NONSTICKYDATAVAULTCTRL_8_LOCK_ENTRY_MASK                                             (0x1)
-#define CLP_DV_REG_NONSTICKYDATAVAULTCTRL_9                                                         (0x1001c22c)
-#define DV_REG_NONSTICKYDATAVAULTCTRL_9                                                             (0x22c)
-#define DV_REG_NONSTICKYDATAVAULTCTRL_9_LOCK_ENTRY_LOW                                              (0)
-#define DV_REG_NONSTICKYDATAVAULTCTRL_9_LOCK_ENTRY_MASK                                             (0x1)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_0                                                   (0x1001c230)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_0                                                       (0x230)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_1                                                   (0x1001c234)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_1                                                       (0x234)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_2                                                   (0x1001c238)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_2                                                       (0x238)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_3                                                   (0x1001c23c)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_3                                                       (0x23c)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_4                                                   (0x1001c240)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_4                                                       (0x240)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_5                                                   (0x1001c244)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_5                                                       (0x244)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_6                                                   (0x1001c248)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_6                                                       (0x248)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_7                                                   (0x1001c24c)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_7                                                       (0x24c)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_8                                                   (0x1001c250)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_8                                                       (0x250)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_9                                                   (0x1001c254)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_9                                                       (0x254)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_10                                                  (0x1001c258)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_10                                                      (0x258)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_11                                                  (0x1001c25c)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_11                                                      (0x25c)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_0                                                   (0x1001c260)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_0                                                       (0x260)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_1                                                   (0x1001c264)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_1                                                       (0x264)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_2                                                   (0x1001c268)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_2                                                       (0x268)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_3                                                   (0x1001c26c)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_3                                                       (0x26c)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_4                                                   (0x1001c270)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_4                                                       (0x270)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_5                                                   (0x1001c274)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_5                                                       (0x274)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_6                                                   (0x1001c278)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_6                                                       (0x278)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_7                                                   (0x1001c27c)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_7                                                       (0x27c)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_8                                                   (0x1001c280)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_8                                                       (0x280)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_9                                                   (0x1001c284)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_9                                                       (0x284)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_10                                                  (0x1001c288)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_10                                                      (0x288)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_11                                                  (0x1001c28c)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_11                                                      (0x28c)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_0                                                   (0x1001c290)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_0                                                       (0x290)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_1                                                   (0x1001c294)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_1                                                       (0x294)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_2                                                   (0x1001c298)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_2                                                       (0x298)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_3                                                   (0x1001c29c)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_3                                                       (0x29c)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_4                                                   (0x1001c2a0)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_4                                                       (0x2a0)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_5                                                   (0x1001c2a4)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_5                                                       (0x2a4)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_6                                                   (0x1001c2a8)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_6                                                       (0x2a8)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_7                                                   (0x1001c2ac)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_7                                                       (0x2ac)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_8                                                   (0x1001c2b0)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_8                                                       (0x2b0)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_9                                                   (0x1001c2b4)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_9                                                       (0x2b4)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_10                                                  (0x1001c2b8)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_10                                                      (0x2b8)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_11                                                  (0x1001c2bc)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_11                                                      (0x2bc)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_0                                                   (0x1001c2c0)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_0                                                       (0x2c0)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_1                                                   (0x1001c2c4)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_1                                                       (0x2c4)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_2                                                   (0x1001c2c8)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_2                                                       (0x2c8)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_3                                                   (0x1001c2cc)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_3                                                       (0x2cc)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_4                                                   (0x1001c2d0)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_4                                                       (0x2d0)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_5                                                   (0x1001c2d4)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_5                                                       (0x2d4)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_6                                                   (0x1001c2d8)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_6                                                       (0x2d8)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_7                                                   (0x1001c2dc)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_7                                                       (0x2dc)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_8                                                   (0x1001c2e0)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_8                                                       (0x2e0)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_9                                                   (0x1001c2e4)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_9                                                       (0x2e4)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_10                                                  (0x1001c2e8)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_10                                                      (0x2e8)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_11                                                  (0x1001c2ec)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_11                                                      (0x2ec)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_0                                                   (0x1001c2f0)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_0                                                       (0x2f0)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_1                                                   (0x1001c2f4)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_1                                                       (0x2f4)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_2                                                   (0x1001c2f8)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_2                                                       (0x2f8)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_3                                                   (0x1001c2fc)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_3                                                       (0x2fc)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_4                                                   (0x1001c300)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_4                                                       (0x300)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_5                                                   (0x1001c304)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_5                                                       (0x304)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_6                                                   (0x1001c308)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_6                                                       (0x308)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_7                                                   (0x1001c30c)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_7                                                       (0x30c)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_8                                                   (0x1001c310)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_8                                                       (0x310)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_9                                                   (0x1001c314)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_9                                                       (0x314)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_10                                                  (0x1001c318)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_10                                                      (0x318)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_11                                                  (0x1001c31c)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_11                                                      (0x31c)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_0                                                   (0x1001c320)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_0                                                       (0x320)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_1                                                   (0x1001c324)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_1                                                       (0x324)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_2                                                   (0x1001c328)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_2                                                       (0x328)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_3                                                   (0x1001c32c)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_3                                                       (0x32c)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_4                                                   (0x1001c330)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_4                                                       (0x330)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_5                                                   (0x1001c334)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_5                                                       (0x334)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_6                                                   (0x1001c338)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_6                                                       (0x338)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_7                                                   (0x1001c33c)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_7                                                       (0x33c)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_8                                                   (0x1001c340)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_8                                                       (0x340)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_9                                                   (0x1001c344)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_9                                                       (0x344)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_10                                                  (0x1001c348)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_10                                                      (0x348)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_11                                                  (0x1001c34c)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_11                                                      (0x34c)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_0                                                   (0x1001c350)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_0                                                       (0x350)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_1                                                   (0x1001c354)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_1                                                       (0x354)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_2                                                   (0x1001c358)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_2                                                       (0x358)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_3                                                   (0x1001c35c)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_3                                                       (0x35c)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_4                                                   (0x1001c360)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_4                                                       (0x360)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_5                                                   (0x1001c364)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_5                                                       (0x364)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_6                                                   (0x1001c368)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_6                                                       (0x368)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_7                                                   (0x1001c36c)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_7                                                       (0x36c)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_8                                                   (0x1001c370)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_8                                                       (0x370)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_9                                                   (0x1001c374)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_9                                                       (0x374)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_10                                                  (0x1001c378)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_10                                                      (0x378)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_11                                                  (0x1001c37c)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_11                                                      (0x37c)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_0                                                   (0x1001c380)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_0                                                       (0x380)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_1                                                   (0x1001c384)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_1                                                       (0x384)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_2                                                   (0x1001c388)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_2                                                       (0x388)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_3                                                   (0x1001c38c)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_3                                                       (0x38c)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_4                                                   (0x1001c390)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_4                                                       (0x390)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_5                                                   (0x1001c394)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_5                                                       (0x394)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_6                                                   (0x1001c398)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_6                                                       (0x398)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_7                                                   (0x1001c39c)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_7                                                       (0x39c)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_8                                                   (0x1001c3a0)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_8                                                       (0x3a0)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_9                                                   (0x1001c3a4)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_9                                                       (0x3a4)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_10                                                  (0x1001c3a8)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_10                                                      (0x3a8)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_11                                                  (0x1001c3ac)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_11                                                      (0x3ac)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_0                                                   (0x1001c3b0)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_0                                                       (0x3b0)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_1                                                   (0x1001c3b4)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_1                                                       (0x3b4)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_2                                                   (0x1001c3b8)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_2                                                       (0x3b8)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_3                                                   (0x1001c3bc)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_3                                                       (0x3bc)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_4                                                   (0x1001c3c0)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_4                                                       (0x3c0)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_5                                                   (0x1001c3c4)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_5                                                       (0x3c4)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_6                                                   (0x1001c3c8)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_6                                                       (0x3c8)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_7                                                   (0x1001c3cc)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_7                                                       (0x3cc)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_8                                                   (0x1001c3d0)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_8                                                       (0x3d0)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_9                                                   (0x1001c3d4)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_9                                                       (0x3d4)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_10                                                  (0x1001c3d8)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_10                                                      (0x3d8)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_11                                                  (0x1001c3dc)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_11                                                      (0x3dc)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_0                                                   (0x1001c3e0)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_0                                                       (0x3e0)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_1                                                   (0x1001c3e4)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_1                                                       (0x3e4)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_2                                                   (0x1001c3e8)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_2                                                       (0x3e8)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_3                                                   (0x1001c3ec)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_3                                                       (0x3ec)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_4                                                   (0x1001c3f0)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_4                                                       (0x3f0)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_5                                                   (0x1001c3f4)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_5                                                       (0x3f4)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_6                                                   (0x1001c3f8)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_6                                                       (0x3f8)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_7                                                   (0x1001c3fc)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_7                                                       (0x3fc)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_8                                                   (0x1001c400)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_8                                                       (0x400)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_9                                                   (0x1001c404)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_9                                                       (0x404)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_10                                                  (0x1001c408)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_10                                                      (0x408)
-#define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_11                                                  (0x1001c40c)
-#define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_11                                                      (0x40c)
-#define CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_0                                                (0x1001c410)
-#define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_0                                                    (0x410)
-#define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_0_LOCK_ENTRY_LOW                                     (0)
-#define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_0_LOCK_ENTRY_MASK                                    (0x1)
-#define CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_1                                                (0x1001c414)
-#define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_1                                                    (0x414)
-#define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_1_LOCK_ENTRY_LOW                                     (0)
-#define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_1_LOCK_ENTRY_MASK                                    (0x1)
-#define CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_2                                                (0x1001c418)
-#define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_2                                                    (0x418)
-#define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_2_LOCK_ENTRY_LOW                                     (0)
-#define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_2_LOCK_ENTRY_MASK                                    (0x1)
-#define CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_3                                                (0x1001c41c)
-#define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_3                                                    (0x41c)
-#define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_3_LOCK_ENTRY_LOW                                     (0)
-#define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_3_LOCK_ENTRY_MASK                                    (0x1)
-#define CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_4                                                (0x1001c420)
-#define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_4                                                    (0x420)
-#define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_4_LOCK_ENTRY_LOW                                     (0)
-#define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_4_LOCK_ENTRY_MASK                                    (0x1)
-#define CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_5                                                (0x1001c424)
-#define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_5                                                    (0x424)
-#define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_5_LOCK_ENTRY_LOW                                     (0)
-#define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_5_LOCK_ENTRY_MASK                                    (0x1)
-#define CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_6                                                (0x1001c428)
-#define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_6                                                    (0x428)
-#define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_6_LOCK_ENTRY_LOW                                     (0)
-#define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_6_LOCK_ENTRY_MASK                                    (0x1)
-#define CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_7                                                (0x1001c42c)
-#define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_7                                                    (0x42c)
-#define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_7_LOCK_ENTRY_LOW                                     (0)
-#define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_7_LOCK_ENTRY_MASK                                    (0x1)
-#define CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_8                                                (0x1001c430)
-#define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_8                                                    (0x430)
-#define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_8_LOCK_ENTRY_LOW                                     (0)
-#define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_8_LOCK_ENTRY_MASK                                    (0x1)
-#define CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_9                                                (0x1001c434)
-#define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_9                                                    (0x434)
-#define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_9_LOCK_ENTRY_LOW                                     (0)
-#define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_9_LOCK_ENTRY_MASK                                    (0x1)
-#define CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREG_0                                                    (0x1001c438)
-#define DV_REG_NONSTICKYLOCKABLESCRATCHREG_0                                                        (0x438)
-#define CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREG_1                                                    (0x1001c43c)
-#define DV_REG_NONSTICKYLOCKABLESCRATCHREG_1                                                        (0x43c)
-#define CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREG_2                                                    (0x1001c440)
-#define DV_REG_NONSTICKYLOCKABLESCRATCHREG_2                                                        (0x440)
-#define CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREG_3                                                    (0x1001c444)
-#define DV_REG_NONSTICKYLOCKABLESCRATCHREG_3                                                        (0x444)
-#define CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREG_4                                                    (0x1001c448)
-#define DV_REG_NONSTICKYLOCKABLESCRATCHREG_4                                                        (0x448)
-#define CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREG_5                                                    (0x1001c44c)
-#define DV_REG_NONSTICKYLOCKABLESCRATCHREG_5                                                        (0x44c)
-#define CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREG_6                                                    (0x1001c450)
-#define DV_REG_NONSTICKYLOCKABLESCRATCHREG_6                                                        (0x450)
-#define CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREG_7                                                    (0x1001c454)
-#define DV_REG_NONSTICKYLOCKABLESCRATCHREG_7                                                        (0x454)
-#define CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREG_8                                                    (0x1001c458)
-#define DV_REG_NONSTICKYLOCKABLESCRATCHREG_8                                                        (0x458)
-#define CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREG_9                                                    (0x1001c45c)
-#define DV_REG_NONSTICKYLOCKABLESCRATCHREG_9                                                        (0x45c)
+#define CLP_DV_REG_DATAVAULTCTRL_0                                                                  (0x1001c208)
+#define DV_REG_DATAVAULTCTRL_0                                                                      (0x208)
+#define DV_REG_DATAVAULTCTRL_0_LOCK_ENTRY_LOW                                                       (0)
+#define DV_REG_DATAVAULTCTRL_0_LOCK_ENTRY_MASK                                                      (0x1)
+#define CLP_DV_REG_DATAVAULTCTRL_1                                                                  (0x1001c20c)
+#define DV_REG_DATAVAULTCTRL_1                                                                      (0x20c)
+#define DV_REG_DATAVAULTCTRL_1_LOCK_ENTRY_LOW                                                       (0)
+#define DV_REG_DATAVAULTCTRL_1_LOCK_ENTRY_MASK                                                      (0x1)
+#define CLP_DV_REG_DATAVAULTCTRL_2                                                                  (0x1001c210)
+#define DV_REG_DATAVAULTCTRL_2                                                                      (0x210)
+#define DV_REG_DATAVAULTCTRL_2_LOCK_ENTRY_LOW                                                       (0)
+#define DV_REG_DATAVAULTCTRL_2_LOCK_ENTRY_MASK                                                      (0x1)
+#define CLP_DV_REG_DATAVAULTCTRL_3                                                                  (0x1001c214)
+#define DV_REG_DATAVAULTCTRL_3                                                                      (0x214)
+#define DV_REG_DATAVAULTCTRL_3_LOCK_ENTRY_LOW                                                       (0)
+#define DV_REG_DATAVAULTCTRL_3_LOCK_ENTRY_MASK                                                      (0x1)
+#define CLP_DV_REG_DATAVAULTCTRL_4                                                                  (0x1001c218)
+#define DV_REG_DATAVAULTCTRL_4                                                                      (0x218)
+#define DV_REG_DATAVAULTCTRL_4_LOCK_ENTRY_LOW                                                       (0)
+#define DV_REG_DATAVAULTCTRL_4_LOCK_ENTRY_MASK                                                      (0x1)
+#define CLP_DV_REG_DATAVAULTCTRL_5                                                                  (0x1001c21c)
+#define DV_REG_DATAVAULTCTRL_5                                                                      (0x21c)
+#define DV_REG_DATAVAULTCTRL_5_LOCK_ENTRY_LOW                                                       (0)
+#define DV_REG_DATAVAULTCTRL_5_LOCK_ENTRY_MASK                                                      (0x1)
+#define CLP_DV_REG_DATAVAULTCTRL_6                                                                  (0x1001c220)
+#define DV_REG_DATAVAULTCTRL_6                                                                      (0x220)
+#define DV_REG_DATAVAULTCTRL_6_LOCK_ENTRY_LOW                                                       (0)
+#define DV_REG_DATAVAULTCTRL_6_LOCK_ENTRY_MASK                                                      (0x1)
+#define CLP_DV_REG_DATAVAULTCTRL_7                                                                  (0x1001c224)
+#define DV_REG_DATAVAULTCTRL_7                                                                      (0x224)
+#define DV_REG_DATAVAULTCTRL_7_LOCK_ENTRY_LOW                                                       (0)
+#define DV_REG_DATAVAULTCTRL_7_LOCK_ENTRY_MASK                                                      (0x1)
+#define CLP_DV_REG_DATAVAULTCTRL_8                                                                  (0x1001c228)
+#define DV_REG_DATAVAULTCTRL_8                                                                      (0x228)
+#define DV_REG_DATAVAULTCTRL_8_LOCK_ENTRY_LOW                                                       (0)
+#define DV_REG_DATAVAULTCTRL_8_LOCK_ENTRY_MASK                                                      (0x1)
+#define CLP_DV_REG_DATAVAULTCTRL_9                                                                  (0x1001c22c)
+#define DV_REG_DATAVAULTCTRL_9                                                                      (0x22c)
+#define DV_REG_DATAVAULTCTRL_9_LOCK_ENTRY_LOW                                                       (0)
+#define DV_REG_DATAVAULTCTRL_9_LOCK_ENTRY_MASK                                                      (0x1)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_0_0                                                             (0x1001c230)
+#define DV_REG_DATA_VAULT_ENTRY_0_0                                                                 (0x230)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_0_1                                                             (0x1001c234)
+#define DV_REG_DATA_VAULT_ENTRY_0_1                                                                 (0x234)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_0_2                                                             (0x1001c238)
+#define DV_REG_DATA_VAULT_ENTRY_0_2                                                                 (0x238)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_0_3                                                             (0x1001c23c)
+#define DV_REG_DATA_VAULT_ENTRY_0_3                                                                 (0x23c)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_0_4                                                             (0x1001c240)
+#define DV_REG_DATA_VAULT_ENTRY_0_4                                                                 (0x240)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_0_5                                                             (0x1001c244)
+#define DV_REG_DATA_VAULT_ENTRY_0_5                                                                 (0x244)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_0_6                                                             (0x1001c248)
+#define DV_REG_DATA_VAULT_ENTRY_0_6                                                                 (0x248)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_0_7                                                             (0x1001c24c)
+#define DV_REG_DATA_VAULT_ENTRY_0_7                                                                 (0x24c)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_0_8                                                             (0x1001c250)
+#define DV_REG_DATA_VAULT_ENTRY_0_8                                                                 (0x250)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_0_9                                                             (0x1001c254)
+#define DV_REG_DATA_VAULT_ENTRY_0_9                                                                 (0x254)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_0_10                                                            (0x1001c258)
+#define DV_REG_DATA_VAULT_ENTRY_0_10                                                                (0x258)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_0_11                                                            (0x1001c25c)
+#define DV_REG_DATA_VAULT_ENTRY_0_11                                                                (0x25c)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_1_0                                                             (0x1001c260)
+#define DV_REG_DATA_VAULT_ENTRY_1_0                                                                 (0x260)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_1_1                                                             (0x1001c264)
+#define DV_REG_DATA_VAULT_ENTRY_1_1                                                                 (0x264)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_1_2                                                             (0x1001c268)
+#define DV_REG_DATA_VAULT_ENTRY_1_2                                                                 (0x268)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_1_3                                                             (0x1001c26c)
+#define DV_REG_DATA_VAULT_ENTRY_1_3                                                                 (0x26c)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_1_4                                                             (0x1001c270)
+#define DV_REG_DATA_VAULT_ENTRY_1_4                                                                 (0x270)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_1_5                                                             (0x1001c274)
+#define DV_REG_DATA_VAULT_ENTRY_1_5                                                                 (0x274)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_1_6                                                             (0x1001c278)
+#define DV_REG_DATA_VAULT_ENTRY_1_6                                                                 (0x278)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_1_7                                                             (0x1001c27c)
+#define DV_REG_DATA_VAULT_ENTRY_1_7                                                                 (0x27c)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_1_8                                                             (0x1001c280)
+#define DV_REG_DATA_VAULT_ENTRY_1_8                                                                 (0x280)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_1_9                                                             (0x1001c284)
+#define DV_REG_DATA_VAULT_ENTRY_1_9                                                                 (0x284)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_1_10                                                            (0x1001c288)
+#define DV_REG_DATA_VAULT_ENTRY_1_10                                                                (0x288)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_1_11                                                            (0x1001c28c)
+#define DV_REG_DATA_VAULT_ENTRY_1_11                                                                (0x28c)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_2_0                                                             (0x1001c290)
+#define DV_REG_DATA_VAULT_ENTRY_2_0                                                                 (0x290)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_2_1                                                             (0x1001c294)
+#define DV_REG_DATA_VAULT_ENTRY_2_1                                                                 (0x294)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_2_2                                                             (0x1001c298)
+#define DV_REG_DATA_VAULT_ENTRY_2_2                                                                 (0x298)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_2_3                                                             (0x1001c29c)
+#define DV_REG_DATA_VAULT_ENTRY_2_3                                                                 (0x29c)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_2_4                                                             (0x1001c2a0)
+#define DV_REG_DATA_VAULT_ENTRY_2_4                                                                 (0x2a0)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_2_5                                                             (0x1001c2a4)
+#define DV_REG_DATA_VAULT_ENTRY_2_5                                                                 (0x2a4)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_2_6                                                             (0x1001c2a8)
+#define DV_REG_DATA_VAULT_ENTRY_2_6                                                                 (0x2a8)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_2_7                                                             (0x1001c2ac)
+#define DV_REG_DATA_VAULT_ENTRY_2_7                                                                 (0x2ac)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_2_8                                                             (0x1001c2b0)
+#define DV_REG_DATA_VAULT_ENTRY_2_8                                                                 (0x2b0)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_2_9                                                             (0x1001c2b4)
+#define DV_REG_DATA_VAULT_ENTRY_2_9                                                                 (0x2b4)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_2_10                                                            (0x1001c2b8)
+#define DV_REG_DATA_VAULT_ENTRY_2_10                                                                (0x2b8)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_2_11                                                            (0x1001c2bc)
+#define DV_REG_DATA_VAULT_ENTRY_2_11                                                                (0x2bc)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_3_0                                                             (0x1001c2c0)
+#define DV_REG_DATA_VAULT_ENTRY_3_0                                                                 (0x2c0)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_3_1                                                             (0x1001c2c4)
+#define DV_REG_DATA_VAULT_ENTRY_3_1                                                                 (0x2c4)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_3_2                                                             (0x1001c2c8)
+#define DV_REG_DATA_VAULT_ENTRY_3_2                                                                 (0x2c8)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_3_3                                                             (0x1001c2cc)
+#define DV_REG_DATA_VAULT_ENTRY_3_3                                                                 (0x2cc)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_3_4                                                             (0x1001c2d0)
+#define DV_REG_DATA_VAULT_ENTRY_3_4                                                                 (0x2d0)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_3_5                                                             (0x1001c2d4)
+#define DV_REG_DATA_VAULT_ENTRY_3_5                                                                 (0x2d4)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_3_6                                                             (0x1001c2d8)
+#define DV_REG_DATA_VAULT_ENTRY_3_6                                                                 (0x2d8)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_3_7                                                             (0x1001c2dc)
+#define DV_REG_DATA_VAULT_ENTRY_3_7                                                                 (0x2dc)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_3_8                                                             (0x1001c2e0)
+#define DV_REG_DATA_VAULT_ENTRY_3_8                                                                 (0x2e0)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_3_9                                                             (0x1001c2e4)
+#define DV_REG_DATA_VAULT_ENTRY_3_9                                                                 (0x2e4)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_3_10                                                            (0x1001c2e8)
+#define DV_REG_DATA_VAULT_ENTRY_3_10                                                                (0x2e8)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_3_11                                                            (0x1001c2ec)
+#define DV_REG_DATA_VAULT_ENTRY_3_11                                                                (0x2ec)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_4_0                                                             (0x1001c2f0)
+#define DV_REG_DATA_VAULT_ENTRY_4_0                                                                 (0x2f0)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_4_1                                                             (0x1001c2f4)
+#define DV_REG_DATA_VAULT_ENTRY_4_1                                                                 (0x2f4)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_4_2                                                             (0x1001c2f8)
+#define DV_REG_DATA_VAULT_ENTRY_4_2                                                                 (0x2f8)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_4_3                                                             (0x1001c2fc)
+#define DV_REG_DATA_VAULT_ENTRY_4_3                                                                 (0x2fc)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_4_4                                                             (0x1001c300)
+#define DV_REG_DATA_VAULT_ENTRY_4_4                                                                 (0x300)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_4_5                                                             (0x1001c304)
+#define DV_REG_DATA_VAULT_ENTRY_4_5                                                                 (0x304)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_4_6                                                             (0x1001c308)
+#define DV_REG_DATA_VAULT_ENTRY_4_6                                                                 (0x308)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_4_7                                                             (0x1001c30c)
+#define DV_REG_DATA_VAULT_ENTRY_4_7                                                                 (0x30c)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_4_8                                                             (0x1001c310)
+#define DV_REG_DATA_VAULT_ENTRY_4_8                                                                 (0x310)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_4_9                                                             (0x1001c314)
+#define DV_REG_DATA_VAULT_ENTRY_4_9                                                                 (0x314)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_4_10                                                            (0x1001c318)
+#define DV_REG_DATA_VAULT_ENTRY_4_10                                                                (0x318)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_4_11                                                            (0x1001c31c)
+#define DV_REG_DATA_VAULT_ENTRY_4_11                                                                (0x31c)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_5_0                                                             (0x1001c320)
+#define DV_REG_DATA_VAULT_ENTRY_5_0                                                                 (0x320)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_5_1                                                             (0x1001c324)
+#define DV_REG_DATA_VAULT_ENTRY_5_1                                                                 (0x324)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_5_2                                                             (0x1001c328)
+#define DV_REG_DATA_VAULT_ENTRY_5_2                                                                 (0x328)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_5_3                                                             (0x1001c32c)
+#define DV_REG_DATA_VAULT_ENTRY_5_3                                                                 (0x32c)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_5_4                                                             (0x1001c330)
+#define DV_REG_DATA_VAULT_ENTRY_5_4                                                                 (0x330)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_5_5                                                             (0x1001c334)
+#define DV_REG_DATA_VAULT_ENTRY_5_5                                                                 (0x334)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_5_6                                                             (0x1001c338)
+#define DV_REG_DATA_VAULT_ENTRY_5_6                                                                 (0x338)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_5_7                                                             (0x1001c33c)
+#define DV_REG_DATA_VAULT_ENTRY_5_7                                                                 (0x33c)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_5_8                                                             (0x1001c340)
+#define DV_REG_DATA_VAULT_ENTRY_5_8                                                                 (0x340)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_5_9                                                             (0x1001c344)
+#define DV_REG_DATA_VAULT_ENTRY_5_9                                                                 (0x344)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_5_10                                                            (0x1001c348)
+#define DV_REG_DATA_VAULT_ENTRY_5_10                                                                (0x348)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_5_11                                                            (0x1001c34c)
+#define DV_REG_DATA_VAULT_ENTRY_5_11                                                                (0x34c)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_6_0                                                             (0x1001c350)
+#define DV_REG_DATA_VAULT_ENTRY_6_0                                                                 (0x350)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_6_1                                                             (0x1001c354)
+#define DV_REG_DATA_VAULT_ENTRY_6_1                                                                 (0x354)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_6_2                                                             (0x1001c358)
+#define DV_REG_DATA_VAULT_ENTRY_6_2                                                                 (0x358)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_6_3                                                             (0x1001c35c)
+#define DV_REG_DATA_VAULT_ENTRY_6_3                                                                 (0x35c)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_6_4                                                             (0x1001c360)
+#define DV_REG_DATA_VAULT_ENTRY_6_4                                                                 (0x360)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_6_5                                                             (0x1001c364)
+#define DV_REG_DATA_VAULT_ENTRY_6_5                                                                 (0x364)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_6_6                                                             (0x1001c368)
+#define DV_REG_DATA_VAULT_ENTRY_6_6                                                                 (0x368)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_6_7                                                             (0x1001c36c)
+#define DV_REG_DATA_VAULT_ENTRY_6_7                                                                 (0x36c)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_6_8                                                             (0x1001c370)
+#define DV_REG_DATA_VAULT_ENTRY_6_8                                                                 (0x370)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_6_9                                                             (0x1001c374)
+#define DV_REG_DATA_VAULT_ENTRY_6_9                                                                 (0x374)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_6_10                                                            (0x1001c378)
+#define DV_REG_DATA_VAULT_ENTRY_6_10                                                                (0x378)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_6_11                                                            (0x1001c37c)
+#define DV_REG_DATA_VAULT_ENTRY_6_11                                                                (0x37c)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_7_0                                                             (0x1001c380)
+#define DV_REG_DATA_VAULT_ENTRY_7_0                                                                 (0x380)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_7_1                                                             (0x1001c384)
+#define DV_REG_DATA_VAULT_ENTRY_7_1                                                                 (0x384)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_7_2                                                             (0x1001c388)
+#define DV_REG_DATA_VAULT_ENTRY_7_2                                                                 (0x388)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_7_3                                                             (0x1001c38c)
+#define DV_REG_DATA_VAULT_ENTRY_7_3                                                                 (0x38c)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_7_4                                                             (0x1001c390)
+#define DV_REG_DATA_VAULT_ENTRY_7_4                                                                 (0x390)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_7_5                                                             (0x1001c394)
+#define DV_REG_DATA_VAULT_ENTRY_7_5                                                                 (0x394)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_7_6                                                             (0x1001c398)
+#define DV_REG_DATA_VAULT_ENTRY_7_6                                                                 (0x398)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_7_7                                                             (0x1001c39c)
+#define DV_REG_DATA_VAULT_ENTRY_7_7                                                                 (0x39c)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_7_8                                                             (0x1001c3a0)
+#define DV_REG_DATA_VAULT_ENTRY_7_8                                                                 (0x3a0)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_7_9                                                             (0x1001c3a4)
+#define DV_REG_DATA_VAULT_ENTRY_7_9                                                                 (0x3a4)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_7_10                                                            (0x1001c3a8)
+#define DV_REG_DATA_VAULT_ENTRY_7_10                                                                (0x3a8)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_7_11                                                            (0x1001c3ac)
+#define DV_REG_DATA_VAULT_ENTRY_7_11                                                                (0x3ac)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_8_0                                                             (0x1001c3b0)
+#define DV_REG_DATA_VAULT_ENTRY_8_0                                                                 (0x3b0)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_8_1                                                             (0x1001c3b4)
+#define DV_REG_DATA_VAULT_ENTRY_8_1                                                                 (0x3b4)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_8_2                                                             (0x1001c3b8)
+#define DV_REG_DATA_VAULT_ENTRY_8_2                                                                 (0x3b8)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_8_3                                                             (0x1001c3bc)
+#define DV_REG_DATA_VAULT_ENTRY_8_3                                                                 (0x3bc)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_8_4                                                             (0x1001c3c0)
+#define DV_REG_DATA_VAULT_ENTRY_8_4                                                                 (0x3c0)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_8_5                                                             (0x1001c3c4)
+#define DV_REG_DATA_VAULT_ENTRY_8_5                                                                 (0x3c4)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_8_6                                                             (0x1001c3c8)
+#define DV_REG_DATA_VAULT_ENTRY_8_6                                                                 (0x3c8)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_8_7                                                             (0x1001c3cc)
+#define DV_REG_DATA_VAULT_ENTRY_8_7                                                                 (0x3cc)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_8_8                                                             (0x1001c3d0)
+#define DV_REG_DATA_VAULT_ENTRY_8_8                                                                 (0x3d0)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_8_9                                                             (0x1001c3d4)
+#define DV_REG_DATA_VAULT_ENTRY_8_9                                                                 (0x3d4)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_8_10                                                            (0x1001c3d8)
+#define DV_REG_DATA_VAULT_ENTRY_8_10                                                                (0x3d8)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_8_11                                                            (0x1001c3dc)
+#define DV_REG_DATA_VAULT_ENTRY_8_11                                                                (0x3dc)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_9_0                                                             (0x1001c3e0)
+#define DV_REG_DATA_VAULT_ENTRY_9_0                                                                 (0x3e0)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_9_1                                                             (0x1001c3e4)
+#define DV_REG_DATA_VAULT_ENTRY_9_1                                                                 (0x3e4)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_9_2                                                             (0x1001c3e8)
+#define DV_REG_DATA_VAULT_ENTRY_9_2                                                                 (0x3e8)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_9_3                                                             (0x1001c3ec)
+#define DV_REG_DATA_VAULT_ENTRY_9_3                                                                 (0x3ec)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_9_4                                                             (0x1001c3f0)
+#define DV_REG_DATA_VAULT_ENTRY_9_4                                                                 (0x3f0)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_9_5                                                             (0x1001c3f4)
+#define DV_REG_DATA_VAULT_ENTRY_9_5                                                                 (0x3f4)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_9_6                                                             (0x1001c3f8)
+#define DV_REG_DATA_VAULT_ENTRY_9_6                                                                 (0x3f8)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_9_7                                                             (0x1001c3fc)
+#define DV_REG_DATA_VAULT_ENTRY_9_7                                                                 (0x3fc)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_9_8                                                             (0x1001c400)
+#define DV_REG_DATA_VAULT_ENTRY_9_8                                                                 (0x400)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_9_9                                                             (0x1001c404)
+#define DV_REG_DATA_VAULT_ENTRY_9_9                                                                 (0x404)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_9_10                                                            (0x1001c408)
+#define DV_REG_DATA_VAULT_ENTRY_9_10                                                                (0x408)
+#define CLP_DV_REG_DATA_VAULT_ENTRY_9_11                                                            (0x1001c40c)
+#define DV_REG_DATA_VAULT_ENTRY_9_11                                                                (0x40c)
+#define CLP_DV_REG_LOCKABLESCRATCHREGCTRL_0                                                         (0x1001c410)
+#define DV_REG_LOCKABLESCRATCHREGCTRL_0                                                             (0x410)
+#define DV_REG_LOCKABLESCRATCHREGCTRL_0_LOCK_ENTRY_LOW                                              (0)
+#define DV_REG_LOCKABLESCRATCHREGCTRL_0_LOCK_ENTRY_MASK                                             (0x1)
+#define CLP_DV_REG_LOCKABLESCRATCHREGCTRL_1                                                         (0x1001c414)
+#define DV_REG_LOCKABLESCRATCHREGCTRL_1                                                             (0x414)
+#define DV_REG_LOCKABLESCRATCHREGCTRL_1_LOCK_ENTRY_LOW                                              (0)
+#define DV_REG_LOCKABLESCRATCHREGCTRL_1_LOCK_ENTRY_MASK                                             (0x1)
+#define CLP_DV_REG_LOCKABLESCRATCHREGCTRL_2                                                         (0x1001c418)
+#define DV_REG_LOCKABLESCRATCHREGCTRL_2                                                             (0x418)
+#define DV_REG_LOCKABLESCRATCHREGCTRL_2_LOCK_ENTRY_LOW                                              (0)
+#define DV_REG_LOCKABLESCRATCHREGCTRL_2_LOCK_ENTRY_MASK                                             (0x1)
+#define CLP_DV_REG_LOCKABLESCRATCHREGCTRL_3                                                         (0x1001c41c)
+#define DV_REG_LOCKABLESCRATCHREGCTRL_3                                                             (0x41c)
+#define DV_REG_LOCKABLESCRATCHREGCTRL_3_LOCK_ENTRY_LOW                                              (0)
+#define DV_REG_LOCKABLESCRATCHREGCTRL_3_LOCK_ENTRY_MASK                                             (0x1)
+#define CLP_DV_REG_LOCKABLESCRATCHREGCTRL_4                                                         (0x1001c420)
+#define DV_REG_LOCKABLESCRATCHREGCTRL_4                                                             (0x420)
+#define DV_REG_LOCKABLESCRATCHREGCTRL_4_LOCK_ENTRY_LOW                                              (0)
+#define DV_REG_LOCKABLESCRATCHREGCTRL_4_LOCK_ENTRY_MASK                                             (0x1)
+#define CLP_DV_REG_LOCKABLESCRATCHREGCTRL_5                                                         (0x1001c424)
+#define DV_REG_LOCKABLESCRATCHREGCTRL_5                                                             (0x424)
+#define DV_REG_LOCKABLESCRATCHREGCTRL_5_LOCK_ENTRY_LOW                                              (0)
+#define DV_REG_LOCKABLESCRATCHREGCTRL_5_LOCK_ENTRY_MASK                                             (0x1)
+#define CLP_DV_REG_LOCKABLESCRATCHREGCTRL_6                                                         (0x1001c428)
+#define DV_REG_LOCKABLESCRATCHREGCTRL_6                                                             (0x428)
+#define DV_REG_LOCKABLESCRATCHREGCTRL_6_LOCK_ENTRY_LOW                                              (0)
+#define DV_REG_LOCKABLESCRATCHREGCTRL_6_LOCK_ENTRY_MASK                                             (0x1)
+#define CLP_DV_REG_LOCKABLESCRATCHREGCTRL_7                                                         (0x1001c42c)
+#define DV_REG_LOCKABLESCRATCHREGCTRL_7                                                             (0x42c)
+#define DV_REG_LOCKABLESCRATCHREGCTRL_7_LOCK_ENTRY_LOW                                              (0)
+#define DV_REG_LOCKABLESCRATCHREGCTRL_7_LOCK_ENTRY_MASK                                             (0x1)
+#define CLP_DV_REG_LOCKABLESCRATCHREGCTRL_8                                                         (0x1001c430)
+#define DV_REG_LOCKABLESCRATCHREGCTRL_8                                                             (0x430)
+#define DV_REG_LOCKABLESCRATCHREGCTRL_8_LOCK_ENTRY_LOW                                              (0)
+#define DV_REG_LOCKABLESCRATCHREGCTRL_8_LOCK_ENTRY_MASK                                             (0x1)
+#define CLP_DV_REG_LOCKABLESCRATCHREGCTRL_9                                                         (0x1001c434)
+#define DV_REG_LOCKABLESCRATCHREGCTRL_9                                                             (0x434)
+#define DV_REG_LOCKABLESCRATCHREGCTRL_9_LOCK_ENTRY_LOW                                              (0)
+#define DV_REG_LOCKABLESCRATCHREGCTRL_9_LOCK_ENTRY_MASK                                             (0x1)
+#define CLP_DV_REG_LOCKABLESCRATCHREG_0                                                             (0x1001c438)
+#define DV_REG_LOCKABLESCRATCHREG_0                                                                 (0x438)
+#define CLP_DV_REG_LOCKABLESCRATCHREG_1                                                             (0x1001c43c)
+#define DV_REG_LOCKABLESCRATCHREG_1                                                                 (0x43c)
+#define CLP_DV_REG_LOCKABLESCRATCHREG_2                                                             (0x1001c440)
+#define DV_REG_LOCKABLESCRATCHREG_2                                                                 (0x440)
+#define CLP_DV_REG_LOCKABLESCRATCHREG_3                                                             (0x1001c444)
+#define DV_REG_LOCKABLESCRATCHREG_3                                                                 (0x444)
+#define CLP_DV_REG_LOCKABLESCRATCHREG_4                                                             (0x1001c448)
+#define DV_REG_LOCKABLESCRATCHREG_4                                                                 (0x448)
+#define CLP_DV_REG_LOCKABLESCRATCHREG_5                                                             (0x1001c44c)
+#define DV_REG_LOCKABLESCRATCHREG_5                                                                 (0x44c)
+#define CLP_DV_REG_LOCKABLESCRATCHREG_6                                                             (0x1001c450)
+#define DV_REG_LOCKABLESCRATCHREG_6                                                                 (0x450)
+#define CLP_DV_REG_LOCKABLESCRATCHREG_7                                                             (0x1001c454)
+#define DV_REG_LOCKABLESCRATCHREG_7                                                                 (0x454)
+#define CLP_DV_REG_LOCKABLESCRATCHREG_8                                                             (0x1001c458)
+#define DV_REG_LOCKABLESCRATCHREG_8                                                                 (0x458)
+#define CLP_DV_REG_LOCKABLESCRATCHREG_9                                                             (0x1001c45c)
+#define DV_REG_LOCKABLESCRATCHREG_9                                                                 (0x45c)
 #define CLP_DV_REG_NONSTICKYGENERICSCRATCHREG_0                                                     (0x1001c460)
 #define DV_REG_NONSTICKYGENERICSCRATCHREG_0                                                         (0x460)
 #define CLP_DV_REG_NONSTICKYGENERICSCRATCHREG_1                                                     (0x1001c464)
@@ -4052,42 +4053,56 @@
 #define SHA512_REG_SHA512_KV_WR_STATUS_VALID_MASK                                                   (0x2)
 #define SHA512_REG_SHA512_KV_WR_STATUS_ERROR_LOW                                                    (2)
 #define SHA512_REG_SHA512_KV_WR_STATUS_ERROR_MASK                                                   (0x3fc)
-#define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_NONCE                                                    (0x10020610)
-#define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE                                                        (0x610)
-#define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_CTRL                                                     (0x10020614)
-#define SHA512_REG_SHA512_GEN_PCR_HASH_CTRL                                                         (0x614)
+#define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_0                                                  (0x10020610)
+#define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_0                                                      (0x610)
+#define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_1                                                  (0x10020614)
+#define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_1                                                      (0x614)
+#define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_2                                                  (0x10020618)
+#define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_2                                                      (0x618)
+#define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_3                                                  (0x1002061c)
+#define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_3                                                      (0x61c)
+#define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_4                                                  (0x10020620)
+#define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_4                                                      (0x620)
+#define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_5                                                  (0x10020624)
+#define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_5                                                      (0x624)
+#define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_6                                                  (0x10020628)
+#define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_6                                                      (0x628)
+#define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_7                                                  (0x1002062c)
+#define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_7                                                      (0x62c)
+#define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_CTRL                                                     (0x10020630)
+#define SHA512_REG_SHA512_GEN_PCR_HASH_CTRL                                                         (0x630)
 #define SHA512_REG_SHA512_GEN_PCR_HASH_CTRL_START_LOW                                               (0)
 #define SHA512_REG_SHA512_GEN_PCR_HASH_CTRL_START_MASK                                              (0x1)
-#define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_STATUS                                                   (0x10020618)
-#define SHA512_REG_SHA512_GEN_PCR_HASH_STATUS                                                       (0x618)
+#define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_STATUS                                                   (0x10020634)
+#define SHA512_REG_SHA512_GEN_PCR_HASH_STATUS                                                       (0x634)
 #define SHA512_REG_SHA512_GEN_PCR_HASH_STATUS_READY_LOW                                             (0)
 #define SHA512_REG_SHA512_GEN_PCR_HASH_STATUS_READY_MASK                                            (0x1)
 #define SHA512_REG_SHA512_GEN_PCR_HASH_STATUS_VALID_LOW                                             (1)
 #define SHA512_REG_SHA512_GEN_PCR_HASH_STATUS_VALID_MASK                                            (0x2)
-#define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_0                                                 (0x1002061c)
-#define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_0                                                     (0x61c)
-#define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_1                                                 (0x10020620)
-#define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_1                                                     (0x620)
-#define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_2                                                 (0x10020624)
-#define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_2                                                     (0x624)
-#define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_3                                                 (0x10020628)
-#define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_3                                                     (0x628)
-#define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_4                                                 (0x1002062c)
-#define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_4                                                     (0x62c)
-#define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_5                                                 (0x10020630)
-#define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_5                                                     (0x630)
-#define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_6                                                 (0x10020634)
-#define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_6                                                     (0x634)
-#define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_7                                                 (0x10020638)
-#define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_7                                                     (0x638)
-#define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_8                                                 (0x1002063c)
-#define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_8                                                     (0x63c)
-#define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_9                                                 (0x10020640)
-#define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_9                                                     (0x640)
-#define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_10                                                (0x10020644)
-#define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_10                                                    (0x644)
-#define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_11                                                (0x10020648)
-#define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_11                                                    (0x648)
+#define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_0                                                 (0x10020638)
+#define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_0                                                     (0x638)
+#define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_1                                                 (0x1002063c)
+#define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_1                                                     (0x63c)
+#define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_2                                                 (0x10020640)
+#define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_2                                                     (0x640)
+#define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_3                                                 (0x10020644)
+#define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_3                                                     (0x644)
+#define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_4                                                 (0x10020648)
+#define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_4                                                     (0x648)
+#define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_5                                                 (0x1002064c)
+#define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_5                                                     (0x64c)
+#define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_6                                                 (0x10020650)
+#define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_6                                                     (0x650)
+#define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_7                                                 (0x10020654)
+#define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_7                                                     (0x654)
+#define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_8                                                 (0x10020658)
+#define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_8                                                     (0x658)
+#define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_9                                                 (0x1002065c)
+#define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_9                                                     (0x65c)
+#define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_10                                                (0x10020660)
+#define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_10                                                    (0x660)
+#define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_11                                                (0x10020664)
+#define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_11                                                    (0x664)
 #define CLP_SHA512_REG_INTR_BLOCK_RF_START                                                          (0x10020800)
 #define CLP_SHA512_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R                                               (0x10020800)
 #define SHA512_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R                                                   (0x800)
@@ -4335,6 +4350,292 @@
 #define SHA256_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R                                   (0xa10)
 #define SHA256_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_LOW                         (0)
 #define SHA256_REG_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_MASK                        (0x1)
+#define CLP_SPI_HOST_REG_BASE_ADDR                                                                  (0x20000000)
+#define CLP_SPI_HOST_REG_INTERRUPT_STATE                                                            (0x20000000)
+#define SPI_HOST_REG_INTERRUPT_STATE                                                                (0x0)
+#define SPI_HOST_REG_INTERRUPT_STATE_ERROR_LOW                                                      (0)
+#define SPI_HOST_REG_INTERRUPT_STATE_ERROR_MASK                                                     (0x1)
+#define SPI_HOST_REG_INTERRUPT_STATE_SPI_EVENT_LOW                                                  (1)
+#define SPI_HOST_REG_INTERRUPT_STATE_SPI_EVENT_MASK                                                 (0x2)
+#define CLP_SPI_HOST_REG_INTERRUPT_ENABLE                                                           (0x20000004)
+#define SPI_HOST_REG_INTERRUPT_ENABLE                                                               (0x4)
+#define SPI_HOST_REG_INTERRUPT_ENABLE_ERROR_LOW                                                     (0)
+#define SPI_HOST_REG_INTERRUPT_ENABLE_ERROR_MASK                                                    (0x1)
+#define SPI_HOST_REG_INTERRUPT_ENABLE_SPI_EVENT_LOW                                                 (1)
+#define SPI_HOST_REG_INTERRUPT_ENABLE_SPI_EVENT_MASK                                                (0x2)
+#define CLP_SPI_HOST_REG_INTERRUPT_TEST                                                             (0x20000008)
+#define SPI_HOST_REG_INTERRUPT_TEST                                                                 (0x8)
+#define SPI_HOST_REG_INTERRUPT_TEST_ERROR_LOW                                                       (0)
+#define SPI_HOST_REG_INTERRUPT_TEST_ERROR_MASK                                                      (0x1)
+#define SPI_HOST_REG_INTERRUPT_TEST_SPI_EVENT_LOW                                                   (1)
+#define SPI_HOST_REG_INTERRUPT_TEST_SPI_EVENT_MASK                                                  (0x2)
+#define CLP_SPI_HOST_REG_ALERT_TEST                                                                 (0x2000000c)
+#define SPI_HOST_REG_ALERT_TEST                                                                     (0xc)
+#define SPI_HOST_REG_ALERT_TEST_FATAL_FAULT_LOW                                                     (0)
+#define SPI_HOST_REG_ALERT_TEST_FATAL_FAULT_MASK                                                    (0x1)
+#define CLP_SPI_HOST_REG_CONTROL                                                                    (0x20000010)
+#define SPI_HOST_REG_CONTROL                                                                        (0x10)
+#define SPI_HOST_REG_CONTROL_RX_WATERMARK_LOW                                                       (0)
+#define SPI_HOST_REG_CONTROL_RX_WATERMARK_MASK                                                      (0xff)
+#define SPI_HOST_REG_CONTROL_TX_WATERMARK_LOW                                                       (8)
+#define SPI_HOST_REG_CONTROL_TX_WATERMARK_MASK                                                      (0xff00)
+#define SPI_HOST_REG_CONTROL_OUTPUT_EN_LOW                                                          (29)
+#define SPI_HOST_REG_CONTROL_OUTPUT_EN_MASK                                                         (0x20000000)
+#define SPI_HOST_REG_CONTROL_SW_RST_LOW                                                             (30)
+#define SPI_HOST_REG_CONTROL_SW_RST_MASK                                                            (0x40000000)
+#define SPI_HOST_REG_CONTROL_SPIEN_LOW                                                              (31)
+#define SPI_HOST_REG_CONTROL_SPIEN_MASK                                                             (0x80000000)
+#define CLP_SPI_HOST_REG_STATUS                                                                     (0x20000014)
+#define SPI_HOST_REG_STATUS                                                                         (0x14)
+#define SPI_HOST_REG_STATUS_TXQD_LOW                                                                (0)
+#define SPI_HOST_REG_STATUS_TXQD_MASK                                                               (0xff)
+#define SPI_HOST_REG_STATUS_RXQD_LOW                                                                (8)
+#define SPI_HOST_REG_STATUS_RXQD_MASK                                                               (0xff00)
+#define SPI_HOST_REG_STATUS_CMDQD_LOW                                                               (16)
+#define SPI_HOST_REG_STATUS_CMDQD_MASK                                                              (0xf0000)
+#define SPI_HOST_REG_STATUS_RXWM_LOW                                                                (20)
+#define SPI_HOST_REG_STATUS_RXWM_MASK                                                               (0x100000)
+#define SPI_HOST_REG_STATUS_BYTEORDER_LOW                                                           (22)
+#define SPI_HOST_REG_STATUS_BYTEORDER_MASK                                                          (0x400000)
+#define SPI_HOST_REG_STATUS_RXSTALL_LOW                                                             (23)
+#define SPI_HOST_REG_STATUS_RXSTALL_MASK                                                            (0x800000)
+#define SPI_HOST_REG_STATUS_RXEMPTY_LOW                                                             (24)
+#define SPI_HOST_REG_STATUS_RXEMPTY_MASK                                                            (0x1000000)
+#define SPI_HOST_REG_STATUS_RXFULL_LOW                                                              (25)
+#define SPI_HOST_REG_STATUS_RXFULL_MASK                                                             (0x2000000)
+#define SPI_HOST_REG_STATUS_TXWM_LOW                                                                (26)
+#define SPI_HOST_REG_STATUS_TXWM_MASK                                                               (0x4000000)
+#define SPI_HOST_REG_STATUS_TXSTALL_LOW                                                             (27)
+#define SPI_HOST_REG_STATUS_TXSTALL_MASK                                                            (0x8000000)
+#define SPI_HOST_REG_STATUS_TXEMPTY_LOW                                                             (28)
+#define SPI_HOST_REG_STATUS_TXEMPTY_MASK                                                            (0x10000000)
+#define SPI_HOST_REG_STATUS_TXFULL_LOW                                                              (29)
+#define SPI_HOST_REG_STATUS_TXFULL_MASK                                                             (0x20000000)
+#define SPI_HOST_REG_STATUS_ACTIVE_LOW                                                              (30)
+#define SPI_HOST_REG_STATUS_ACTIVE_MASK                                                             (0x40000000)
+#define SPI_HOST_REG_STATUS_READY_LOW                                                               (31)
+#define SPI_HOST_REG_STATUS_READY_MASK                                                              (0x80000000)
+#define CLP_SPI_HOST_REG_CONFIGOPTS_0                                                               (0x20000018)
+#define SPI_HOST_REG_CONFIGOPTS_0                                                                   (0x18)
+#define SPI_HOST_REG_CONFIGOPTS_0_CLKDIV_LOW                                                        (0)
+#define SPI_HOST_REG_CONFIGOPTS_0_CLKDIV_MASK                                                       (0xffff)
+#define SPI_HOST_REG_CONFIGOPTS_0_CSNIDLE_LOW                                                       (16)
+#define SPI_HOST_REG_CONFIGOPTS_0_CSNIDLE_MASK                                                      (0xf0000)
+#define SPI_HOST_REG_CONFIGOPTS_0_CSNTRAIL_LOW                                                      (20)
+#define SPI_HOST_REG_CONFIGOPTS_0_CSNTRAIL_MASK                                                     (0xf00000)
+#define SPI_HOST_REG_CONFIGOPTS_0_CSNLEAD_LOW                                                       (24)
+#define SPI_HOST_REG_CONFIGOPTS_0_CSNLEAD_MASK                                                      (0xf000000)
+#define SPI_HOST_REG_CONFIGOPTS_0_FULLCYC_LOW                                                       (29)
+#define SPI_HOST_REG_CONFIGOPTS_0_FULLCYC_MASK                                                      (0x20000000)
+#define SPI_HOST_REG_CONFIGOPTS_0_CPHA_LOW                                                          (30)
+#define SPI_HOST_REG_CONFIGOPTS_0_CPHA_MASK                                                         (0x40000000)
+#define SPI_HOST_REG_CONFIGOPTS_0_CPOL_LOW                                                          (31)
+#define SPI_HOST_REG_CONFIGOPTS_0_CPOL_MASK                                                         (0x80000000)
+#define CLP_SPI_HOST_REG_CONFIGOPTS_1                                                               (0x2000001c)
+#define SPI_HOST_REG_CONFIGOPTS_1                                                                   (0x1c)
+#define SPI_HOST_REG_CONFIGOPTS_1_CLKDIV_LOW                                                        (0)
+#define SPI_HOST_REG_CONFIGOPTS_1_CLKDIV_MASK                                                       (0xffff)
+#define SPI_HOST_REG_CONFIGOPTS_1_CSNIDLE_LOW                                                       (16)
+#define SPI_HOST_REG_CONFIGOPTS_1_CSNIDLE_MASK                                                      (0xf0000)
+#define SPI_HOST_REG_CONFIGOPTS_1_CSNTRAIL_LOW                                                      (20)
+#define SPI_HOST_REG_CONFIGOPTS_1_CSNTRAIL_MASK                                                     (0xf00000)
+#define SPI_HOST_REG_CONFIGOPTS_1_CSNLEAD_LOW                                                       (24)
+#define SPI_HOST_REG_CONFIGOPTS_1_CSNLEAD_MASK                                                      (0xf000000)
+#define SPI_HOST_REG_CONFIGOPTS_1_FULLCYC_LOW                                                       (29)
+#define SPI_HOST_REG_CONFIGOPTS_1_FULLCYC_MASK                                                      (0x20000000)
+#define SPI_HOST_REG_CONFIGOPTS_1_CPHA_LOW                                                          (30)
+#define SPI_HOST_REG_CONFIGOPTS_1_CPHA_MASK                                                         (0x40000000)
+#define SPI_HOST_REG_CONFIGOPTS_1_CPOL_LOW                                                          (31)
+#define SPI_HOST_REG_CONFIGOPTS_1_CPOL_MASK                                                         (0x80000000)
+#define CLP_SPI_HOST_REG_CSID                                                                       (0x20000020)
+#define SPI_HOST_REG_CSID                                                                           (0x20)
+#define CLP_SPI_HOST_REG_COMMAND                                                                    (0x20000024)
+#define SPI_HOST_REG_COMMAND                                                                        (0x24)
+#define SPI_HOST_REG_COMMAND_LEN_LOW                                                                (0)
+#define SPI_HOST_REG_COMMAND_LEN_MASK                                                               (0x1ff)
+#define SPI_HOST_REG_COMMAND_CSAAT_LOW                                                              (9)
+#define SPI_HOST_REG_COMMAND_CSAAT_MASK                                                             (0x200)
+#define SPI_HOST_REG_COMMAND_SPEED_LOW                                                              (10)
+#define SPI_HOST_REG_COMMAND_SPEED_MASK                                                             (0xc00)
+#define SPI_HOST_REG_COMMAND_DIRECTION_LOW                                                          (12)
+#define SPI_HOST_REG_COMMAND_DIRECTION_MASK                                                         (0x3000)
+#define CLP_SPI_HOST_REG_RXDATA                                                                     (0x20000028)
+#define SPI_HOST_REG_RXDATA                                                                         (0x28)
+#define CLP_SPI_HOST_REG_TXDATA                                                                     (0x2000002c)
+#define SPI_HOST_REG_TXDATA                                                                         (0x2c)
+#define CLP_SPI_HOST_REG_ERROR_ENABLE                                                               (0x20000030)
+#define SPI_HOST_REG_ERROR_ENABLE                                                                   (0x30)
+#define SPI_HOST_REG_ERROR_ENABLE_CMDBUSY_LOW                                                       (0)
+#define SPI_HOST_REG_ERROR_ENABLE_CMDBUSY_MASK                                                      (0x1)
+#define SPI_HOST_REG_ERROR_ENABLE_OVERFLOW_LOW                                                      (1)
+#define SPI_HOST_REG_ERROR_ENABLE_OVERFLOW_MASK                                                     (0x2)
+#define SPI_HOST_REG_ERROR_ENABLE_UNDERFLOW_LOW                                                     (2)
+#define SPI_HOST_REG_ERROR_ENABLE_UNDERFLOW_MASK                                                    (0x4)
+#define SPI_HOST_REG_ERROR_ENABLE_CMDINVAL_LOW                                                      (3)
+#define SPI_HOST_REG_ERROR_ENABLE_CMDINVAL_MASK                                                     (0x8)
+#define SPI_HOST_REG_ERROR_ENABLE_CSIDINVAL_LOW                                                     (4)
+#define SPI_HOST_REG_ERROR_ENABLE_CSIDINVAL_MASK                                                    (0x10)
+#define CLP_SPI_HOST_REG_ERROR_STATUS                                                               (0x20000034)
+#define SPI_HOST_REG_ERROR_STATUS                                                                   (0x34)
+#define SPI_HOST_REG_ERROR_STATUS_CMDBUSY_LOW                                                       (0)
+#define SPI_HOST_REG_ERROR_STATUS_CMDBUSY_MASK                                                      (0x1)
+#define SPI_HOST_REG_ERROR_STATUS_OVERFLOW_LOW                                                      (1)
+#define SPI_HOST_REG_ERROR_STATUS_OVERFLOW_MASK                                                     (0x2)
+#define SPI_HOST_REG_ERROR_STATUS_UNDERFLOW_LOW                                                     (2)
+#define SPI_HOST_REG_ERROR_STATUS_UNDERFLOW_MASK                                                    (0x4)
+#define SPI_HOST_REG_ERROR_STATUS_CMDINVAL_LOW                                                      (3)
+#define SPI_HOST_REG_ERROR_STATUS_CMDINVAL_MASK                                                     (0x8)
+#define SPI_HOST_REG_ERROR_STATUS_CSIDINVAL_LOW                                                     (4)
+#define SPI_HOST_REG_ERROR_STATUS_CSIDINVAL_MASK                                                    (0x10)
+#define SPI_HOST_REG_ERROR_STATUS_ACCESSINVAL_LOW                                                   (5)
+#define SPI_HOST_REG_ERROR_STATUS_ACCESSINVAL_MASK                                                  (0x20)
+#define CLP_SPI_HOST_REG_EVENT_ENABLE                                                               (0x20000038)
+#define SPI_HOST_REG_EVENT_ENABLE                                                                   (0x38)
+#define SPI_HOST_REG_EVENT_ENABLE_RXFULL_LOW                                                        (0)
+#define SPI_HOST_REG_EVENT_ENABLE_RXFULL_MASK                                                       (0x1)
+#define SPI_HOST_REG_EVENT_ENABLE_TXEMPTY_LOW                                                       (1)
+#define SPI_HOST_REG_EVENT_ENABLE_TXEMPTY_MASK                                                      (0x2)
+#define SPI_HOST_REG_EVENT_ENABLE_RXWM_LOW                                                          (2)
+#define SPI_HOST_REG_EVENT_ENABLE_RXWM_MASK                                                         (0x4)
+#define SPI_HOST_REG_EVENT_ENABLE_TXWM_LOW                                                          (3)
+#define SPI_HOST_REG_EVENT_ENABLE_TXWM_MASK                                                         (0x8)
+#define SPI_HOST_REG_EVENT_ENABLE_READY_LOW                                                         (4)
+#define SPI_HOST_REG_EVENT_ENABLE_READY_MASK                                                        (0x10)
+#define SPI_HOST_REG_EVENT_ENABLE_IDLE_LOW                                                          (5)
+#define SPI_HOST_REG_EVENT_ENABLE_IDLE_MASK                                                         (0x20)
+#define CLP_UART_BASE_ADDR                                                                          (0x20001000)
+#define CLP_UART_INTERRUPT_STATE                                                                    (0x20001000)
+#define UART_INTERRUPT_STATE                                                                        (0x0)
+#define UART_INTERRUPT_STATE_TX_WATERMARK_LOW                                                       (0)
+#define UART_INTERRUPT_STATE_TX_WATERMARK_MASK                                                      (0x1)
+#define UART_INTERRUPT_STATE_RX_WATERMARK_LOW                                                       (1)
+#define UART_INTERRUPT_STATE_RX_WATERMARK_MASK                                                      (0x2)
+#define UART_INTERRUPT_STATE_TX_EMPTY_LOW                                                           (2)
+#define UART_INTERRUPT_STATE_TX_EMPTY_MASK                                                          (0x4)
+#define UART_INTERRUPT_STATE_RX_OVERFLOW_LOW                                                        (3)
+#define UART_INTERRUPT_STATE_RX_OVERFLOW_MASK                                                       (0x8)
+#define UART_INTERRUPT_STATE_RX_FRAME_ERR_LOW                                                       (4)
+#define UART_INTERRUPT_STATE_RX_FRAME_ERR_MASK                                                      (0x10)
+#define UART_INTERRUPT_STATE_RX_BREAK_ERR_LOW                                                       (5)
+#define UART_INTERRUPT_STATE_RX_BREAK_ERR_MASK                                                      (0x20)
+#define UART_INTERRUPT_STATE_RX_TIMEOUT_LOW                                                         (6)
+#define UART_INTERRUPT_STATE_RX_TIMEOUT_MASK                                                        (0x40)
+#define UART_INTERRUPT_STATE_RX_PARITY_ERR_LOW                                                      (7)
+#define UART_INTERRUPT_STATE_RX_PARITY_ERR_MASK                                                     (0x80)
+#define CLP_UART_INTERRUPT_ENABLE                                                                   (0x20001004)
+#define UART_INTERRUPT_ENABLE                                                                       (0x4)
+#define UART_INTERRUPT_ENABLE_TX_WATERMARK_LOW                                                      (0)
+#define UART_INTERRUPT_ENABLE_TX_WATERMARK_MASK                                                     (0x1)
+#define UART_INTERRUPT_ENABLE_RX_WATERMARK_LOW                                                      (1)
+#define UART_INTERRUPT_ENABLE_RX_WATERMARK_MASK                                                     (0x2)
+#define UART_INTERRUPT_ENABLE_TX_EMPTY_LOW                                                          (2)
+#define UART_INTERRUPT_ENABLE_TX_EMPTY_MASK                                                         (0x4)
+#define UART_INTERRUPT_ENABLE_RX_OVERFLOW_LOW                                                       (3)
+#define UART_INTERRUPT_ENABLE_RX_OVERFLOW_MASK                                                      (0x8)
+#define UART_INTERRUPT_ENABLE_RX_FRAME_ERR_LOW                                                      (4)
+#define UART_INTERRUPT_ENABLE_RX_FRAME_ERR_MASK                                                     (0x10)
+#define UART_INTERRUPT_ENABLE_RX_BREAK_ERR_LOW                                                      (5)
+#define UART_INTERRUPT_ENABLE_RX_BREAK_ERR_MASK                                                     (0x20)
+#define UART_INTERRUPT_ENABLE_RX_TIMEOUT_LOW                                                        (6)
+#define UART_INTERRUPT_ENABLE_RX_TIMEOUT_MASK                                                       (0x40)
+#define UART_INTERRUPT_ENABLE_RX_PARITY_ERR_LOW                                                     (7)
+#define UART_INTERRUPT_ENABLE_RX_PARITY_ERR_MASK                                                    (0x80)
+#define CLP_UART_INTERRUPT_TEST                                                                     (0x20001008)
+#define UART_INTERRUPT_TEST                                                                         (0x8)
+#define UART_INTERRUPT_TEST_TX_WATERMARK_LOW                                                        (0)
+#define UART_INTERRUPT_TEST_TX_WATERMARK_MASK                                                       (0x1)
+#define UART_INTERRUPT_TEST_RX_WATERMARK_LOW                                                        (1)
+#define UART_INTERRUPT_TEST_RX_WATERMARK_MASK                                                       (0x2)
+#define UART_INTERRUPT_TEST_TX_EMPTY_LOW                                                            (2)
+#define UART_INTERRUPT_TEST_TX_EMPTY_MASK                                                           (0x4)
+#define UART_INTERRUPT_TEST_RX_OVERFLOW_LOW                                                         (3)
+#define UART_INTERRUPT_TEST_RX_OVERFLOW_MASK                                                        (0x8)
+#define UART_INTERRUPT_TEST_RX_FRAME_ERR_LOW                                                        (4)
+#define UART_INTERRUPT_TEST_RX_FRAME_ERR_MASK                                                       (0x10)
+#define UART_INTERRUPT_TEST_RX_BREAK_ERR_LOW                                                        (5)
+#define UART_INTERRUPT_TEST_RX_BREAK_ERR_MASK                                                       (0x20)
+#define UART_INTERRUPT_TEST_RX_TIMEOUT_LOW                                                          (6)
+#define UART_INTERRUPT_TEST_RX_TIMEOUT_MASK                                                         (0x40)
+#define UART_INTERRUPT_TEST_RX_PARITY_ERR_LOW                                                       (7)
+#define UART_INTERRUPT_TEST_RX_PARITY_ERR_MASK                                                      (0x80)
+#define CLP_UART_ALERT_TEST                                                                         (0x2000100c)
+#define UART_ALERT_TEST                                                                             (0xc)
+#define UART_ALERT_TEST_FATAL_FAULT_LOW                                                             (0)
+#define UART_ALERT_TEST_FATAL_FAULT_MASK                                                            (0x1)
+#define CLP_UART_CTRL                                                                               (0x20001010)
+#define UART_CTRL                                                                                   (0x10)
+#define UART_CTRL_TX_LOW                                                                            (0)
+#define UART_CTRL_TX_MASK                                                                           (0x1)
+#define UART_CTRL_RX_LOW                                                                            (1)
+#define UART_CTRL_RX_MASK                                                                           (0x2)
+#define UART_CTRL_NF_LOW                                                                            (2)
+#define UART_CTRL_NF_MASK                                                                           (0x4)
+#define UART_CTRL_SLPBK_LOW                                                                         (4)
+#define UART_CTRL_SLPBK_MASK                                                                        (0x10)
+#define UART_CTRL_LLPBK_LOW                                                                         (5)
+#define UART_CTRL_LLPBK_MASK                                                                        (0x20)
+#define UART_CTRL_PARITY_EN_LOW                                                                     (6)
+#define UART_CTRL_PARITY_EN_MASK                                                                    (0x40)
+#define UART_CTRL_PARITY_ODD_LOW                                                                    (7)
+#define UART_CTRL_PARITY_ODD_MASK                                                                   (0x80)
+#define UART_CTRL_RXBLVL_LOW                                                                        (8)
+#define UART_CTRL_RXBLVL_MASK                                                                       (0x300)
+#define UART_CTRL_NCO_LOW                                                                           (16)
+#define UART_CTRL_NCO_MASK                                                                          (0xffff0000)
+#define CLP_UART_STATUS                                                                             (0x20001014)
+#define UART_STATUS                                                                                 (0x14)
+#define UART_STATUS_TXFULL_LOW                                                                      (0)
+#define UART_STATUS_TXFULL_MASK                                                                     (0x1)
+#define UART_STATUS_RXFULL_LOW                                                                      (1)
+#define UART_STATUS_RXFULL_MASK                                                                     (0x2)
+#define UART_STATUS_TXEMPTY_LOW                                                                     (2)
+#define UART_STATUS_TXEMPTY_MASK                                                                    (0x4)
+#define UART_STATUS_TXIDLE_LOW                                                                      (3)
+#define UART_STATUS_TXIDLE_MASK                                                                     (0x8)
+#define UART_STATUS_RXIDLE_LOW                                                                      (4)
+#define UART_STATUS_RXIDLE_MASK                                                                     (0x10)
+#define UART_STATUS_RXEMPTY_LOW                                                                     (5)
+#define UART_STATUS_RXEMPTY_MASK                                                                    (0x20)
+#define CLP_UART_RDATA                                                                              (0x20001018)
+#define UART_RDATA                                                                                  (0x18)
+#define UART_RDATA_RDATA_LOW                                                                        (0)
+#define UART_RDATA_RDATA_MASK                                                                       (0xff)
+#define CLP_UART_WDATA                                                                              (0x2000101c)
+#define UART_WDATA                                                                                  (0x1c)
+#define UART_WDATA_WDATA_LOW                                                                        (0)
+#define UART_WDATA_WDATA_MASK                                                                       (0xff)
+#define CLP_UART_FIFO_CTRL                                                                          (0x20001020)
+#define UART_FIFO_CTRL                                                                              (0x20)
+#define UART_FIFO_CTRL_RXRST_LOW                                                                    (0)
+#define UART_FIFO_CTRL_RXRST_MASK                                                                   (0x1)
+#define UART_FIFO_CTRL_TXRST_LOW                                                                    (1)
+#define UART_FIFO_CTRL_TXRST_MASK                                                                   (0x2)
+#define UART_FIFO_CTRL_RXILVL_LOW                                                                   (2)
+#define UART_FIFO_CTRL_RXILVL_MASK                                                                  (0x1c)
+#define UART_FIFO_CTRL_TXILVL_LOW                                                                   (5)
+#define UART_FIFO_CTRL_TXILVL_MASK                                                                  (0x60)
+#define CLP_UART_FIFO_STATUS                                                                        (0x20001024)
+#define UART_FIFO_STATUS                                                                            (0x24)
+#define UART_FIFO_STATUS_TXLVL_LOW                                                                  (0)
+#define UART_FIFO_STATUS_TXLVL_MASK                                                                 (0x3f)
+#define UART_FIFO_STATUS_RXLVL_LOW                                                                  (16)
+#define UART_FIFO_STATUS_RXLVL_MASK                                                                 (0x3f0000)
+#define CLP_UART_OVRD                                                                               (0x20001028)
+#define UART_OVRD                                                                                   (0x28)
+#define UART_OVRD_TXEN_LOW                                                                          (0)
+#define UART_OVRD_TXEN_MASK                                                                         (0x1)
+#define UART_OVRD_TXVAL_LOW                                                                         (1)
+#define UART_OVRD_TXVAL_MASK                                                                        (0x2)
+#define CLP_UART_VAL                                                                                (0x2000102c)
+#define UART_VAL                                                                                    (0x2c)
+#define UART_VAL_RX_LOW                                                                             (0)
+#define UART_VAL_RX_MASK                                                                            (0xffff)
+#define CLP_UART_TIMEOUT_CTRL                                                                       (0x20001030)
+#define UART_TIMEOUT_CTRL                                                                           (0x30)
+#define UART_TIMEOUT_CTRL_VAL_LOW                                                                   (0)
+#define UART_TIMEOUT_CTRL_VAL_MASK                                                                  (0xffffff)
+#define UART_TIMEOUT_CTRL_EN_LOW                                                                    (31)
+#define UART_TIMEOUT_CTRL_EN_MASK                                                                   (0x80000000)
 #define CLP_CSRNG_REG_BASE_ADDR                                                                     (0x20002000)
 #define CLP_CSRNG_REG_INTERRUPT_STATE                                                               (0x20002000)
 #define CSRNG_REG_INTERRUPT_STATE                                                                   (0x0)
@@ -4386,6 +4687,14 @@
 #define CSRNG_REG_CTRL_READ_INT_STATE_MASK                                                          (0xf00)
 #define CLP_CSRNG_REG_CMD_REQ                                                                       (0x20002018)
 #define CSRNG_REG_CMD_REQ                                                                           (0x18)
+#define CSRNG_REG_CMD_REQ_ACMD_LOW                                                                  (0)
+#define CSRNG_REG_CMD_REQ_ACMD_MASK                                                                 (0xf)
+#define CSRNG_REG_CMD_REQ_CLEN_LOW                                                                  (4)
+#define CSRNG_REG_CMD_REQ_CLEN_MASK                                                                 (0xf0)
+#define CSRNG_REG_CMD_REQ_FLAG0_LOW                                                                 (8)
+#define CSRNG_REG_CMD_REQ_FLAG0_MASK                                                                (0xf00)
+#define CSRNG_REG_CMD_REQ_GLEN_LOW                                                                  (12)
+#define CSRNG_REG_CMD_REQ_GLEN_MASK                                                                 (0x1fff000)
 #define CLP_CSRNG_REG_SW_CMD_STS                                                                    (0x2000201c)
 #define CSRNG_REG_SW_CMD_STS                                                                        (0x1c)
 #define CSRNG_REG_SW_CMD_STS_CMD_RDY_LOW                                                            (0)
@@ -4874,6 +5183,8 @@
 #define MBOX_CSR_MBOX_STATUS_MBOX_FSM_PS_MASK                                                       (0x1c0)
 #define MBOX_CSR_MBOX_STATUS_SOC_HAS_LOCK_LOW                                                       (9)
 #define MBOX_CSR_MBOX_STATUS_SOC_HAS_LOCK_MASK                                                      (0x200)
+#define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_LOW                                                         (10)
+#define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_MASK                                                        (0x1fffc00)
 #define CLP_MBOX_CSR_MBOX_UNLOCK                                                                    (0x30020020)
 #define MBOX_CSR_MBOX_UNLOCK                                                                        (0x20)
 #define MBOX_CSR_MBOX_UNLOCK_UNLOCK_LOW                                                             (0)
@@ -4905,6 +5216,8 @@
 #define SHA512_ACC_CSR_STATUS                                                                       (0x1c)
 #define SHA512_ACC_CSR_STATUS_VALID_LOW                                                             (0)
 #define SHA512_ACC_CSR_STATUS_VALID_MASK                                                            (0x1)
+#define SHA512_ACC_CSR_STATUS_SOC_HAS_LOCK_LOW                                                      (1)
+#define SHA512_ACC_CSR_STATUS_SOC_HAS_LOCK_MASK                                                     (0x2)
 #define CLP_SHA512_ACC_CSR_DIGEST_0                                                                 (0x30021020)
 #define SHA512_ACC_CSR_DIGEST_0                                                                     (0x20)
 #define CLP_SHA512_ACC_CSR_DIGEST_1                                                                 (0x30021024)
@@ -5031,8 +5344,20 @@
 #define CLP_SOC_IFC_REG_BASE_ADDR                                                                   (0x30030000)
 #define CLP_SOC_IFC_REG_CPTRA_HW_ERROR_FATAL                                                        (0x30030000)
 #define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL                                                            (0x0)
+#define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_ICCM_ECC_UNC_LOW                                           (0)
+#define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_ICCM_ECC_UNC_MASK                                          (0x1)
+#define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_DCCM_ECC_UNC_LOW                                           (1)
+#define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_DCCM_ECC_UNC_MASK                                          (0x2)
+#define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_NMI_PIN_LOW                                                (2)
+#define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_NMI_PIN_MASK                                               (0x4)
 #define CLP_SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL                                                    (0x30030004)
 #define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL                                                        (0x4)
+#define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_NO_LOCK_LOW                                  (0)
+#define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_NO_LOCK_MASK                                 (0x1)
+#define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_OOO_LOW                                      (1)
+#define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_OOO_MASK                                     (0x2)
+#define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_ECC_UNC_LOW                                       (2)
+#define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_ECC_UNC_MASK                                      (0x4)
 #define CLP_SOC_IFC_REG_CPTRA_FW_ERROR_FATAL                                                        (0x30030008)
 #define SOC_IFC_REG_CPTRA_FW_ERROR_FATAL                                                            (0x8)
 #define CLP_SOC_IFC_REG_CPTRA_FW_ERROR_NON_FATAL                                                    (0x3003000c)
@@ -5062,7 +5387,11 @@
 #define CLP_SOC_IFC_REG_CPTRA_FLOW_STATUS                                                           (0x3003003c)
 #define SOC_IFC_REG_CPTRA_FLOW_STATUS                                                               (0x3c)
 #define SOC_IFC_REG_CPTRA_FLOW_STATUS_STATUS_LOW                                                    (0)
-#define SOC_IFC_REG_CPTRA_FLOW_STATUS_STATUS_MASK                                                   (0xfffffff)
+#define SOC_IFC_REG_CPTRA_FLOW_STATUS_STATUS_MASK                                                   (0xffffff)
+#define SOC_IFC_REG_CPTRA_FLOW_STATUS_IDEVID_CSR_READY_LOW                                          (24)
+#define SOC_IFC_REG_CPTRA_FLOW_STATUS_IDEVID_CSR_READY_MASK                                         (0x1000000)
+#define SOC_IFC_REG_CPTRA_FLOW_STATUS_BOOT_FSM_PS_LOW                                               (25)
+#define SOC_IFC_REG_CPTRA_FLOW_STATUS_BOOT_FSM_PS_MASK                                              (0xe000000)
 #define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_LOW                                              (28)
 #define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_MASK                                             (0x10000000)
 #define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_RUNTIME_LOW                                         (29)
@@ -5147,80 +5476,116 @@
 #define SOC_IFC_REG_CPTRA_TRNG_DATA_10                                                              (0xa0)
 #define CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_11                                                          (0x300300a4)
 #define SOC_IFC_REG_CPTRA_TRNG_DATA_11                                                              (0xa4)
-#define CLP_SOC_IFC_REG_CPTRA_TRNG_STATUS                                                           (0x300300a8)
-#define SOC_IFC_REG_CPTRA_TRNG_STATUS                                                               (0xa8)
+#define CLP_SOC_IFC_REG_CPTRA_TRNG_CTRL                                                             (0x300300a8)
+#define SOC_IFC_REG_CPTRA_TRNG_CTRL                                                                 (0xa8)
+#define SOC_IFC_REG_CPTRA_TRNG_CTRL_CLEAR_LOW                                                       (0)
+#define SOC_IFC_REG_CPTRA_TRNG_CTRL_CLEAR_MASK                                                      (0x1)
+#define CLP_SOC_IFC_REG_CPTRA_TRNG_STATUS                                                           (0x300300ac)
+#define SOC_IFC_REG_CPTRA_TRNG_STATUS                                                               (0xac)
 #define SOC_IFC_REG_CPTRA_TRNG_STATUS_DATA_REQ_LOW                                                  (0)
 #define SOC_IFC_REG_CPTRA_TRNG_STATUS_DATA_REQ_MASK                                                 (0x1)
 #define SOC_IFC_REG_CPTRA_TRNG_STATUS_DATA_WR_DONE_LOW                                              (1)
 #define SOC_IFC_REG_CPTRA_TRNG_STATUS_DATA_WR_DONE_MASK                                             (0x2)
-#define CLP_SOC_IFC_REG_CPTRA_FUSE_WR_DONE                                                          (0x300300ac)
-#define SOC_IFC_REG_CPTRA_FUSE_WR_DONE                                                              (0xac)
+#define CLP_SOC_IFC_REG_CPTRA_FUSE_WR_DONE                                                          (0x300300b0)
+#define SOC_IFC_REG_CPTRA_FUSE_WR_DONE                                                              (0xb0)
 #define SOC_IFC_REG_CPTRA_FUSE_WR_DONE_DONE_LOW                                                     (0)
 #define SOC_IFC_REG_CPTRA_FUSE_WR_DONE_DONE_MASK                                                    (0x1)
-#define CLP_SOC_IFC_REG_CPTRA_TIMER_CONFIG                                                          (0x300300b0)
-#define SOC_IFC_REG_CPTRA_TIMER_CONFIG                                                              (0xb0)
-#define CLP_SOC_IFC_REG_CPTRA_BOOTFSM_GO                                                            (0x300300b4)
-#define SOC_IFC_REG_CPTRA_BOOTFSM_GO                                                                (0xb4)
+#define CLP_SOC_IFC_REG_CPTRA_TIMER_CONFIG                                                          (0x300300b4)
+#define SOC_IFC_REG_CPTRA_TIMER_CONFIG                                                              (0xb4)
+#define CLP_SOC_IFC_REG_CPTRA_BOOTFSM_GO                                                            (0x300300b8)
+#define SOC_IFC_REG_CPTRA_BOOTFSM_GO                                                                (0xb8)
 #define SOC_IFC_REG_CPTRA_BOOTFSM_GO_GO_LOW                                                         (0)
 #define SOC_IFC_REG_CPTRA_BOOTFSM_GO_GO_MASK                                                        (0x1)
-#define CLP_SOC_IFC_REG_CPTRA_DBG_MANUF_SERVICE_REG                                                 (0x300300b8)
-#define SOC_IFC_REG_CPTRA_DBG_MANUF_SERVICE_REG                                                     (0xb8)
-#define CLP_SOC_IFC_REG_CPTRA_CLK_GATING_EN                                                         (0x300300bc)
-#define SOC_IFC_REG_CPTRA_CLK_GATING_EN                                                             (0xbc)
+#define CLP_SOC_IFC_REG_CPTRA_DBG_MANUF_SERVICE_REG                                                 (0x300300bc)
+#define SOC_IFC_REG_CPTRA_DBG_MANUF_SERVICE_REG                                                     (0xbc)
+#define CLP_SOC_IFC_REG_CPTRA_CLK_GATING_EN                                                         (0x300300c0)
+#define SOC_IFC_REG_CPTRA_CLK_GATING_EN                                                             (0xc0)
 #define SOC_IFC_REG_CPTRA_CLK_GATING_EN_CLK_GATING_EN_LOW                                           (0)
 #define SOC_IFC_REG_CPTRA_CLK_GATING_EN_CLK_GATING_EN_MASK                                          (0x1)
-#define CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0                                                 (0x300300c0)
-#define SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0                                                     (0xc0)
-#define CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_1                                                 (0x300300c4)
-#define SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_1                                                     (0xc4)
-#define CLP_SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_0                                                (0x300300c8)
-#define SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_0                                                    (0xc8)
-#define CLP_SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_1                                                (0x300300cc)
-#define SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_1                                                    (0xcc)
-#define CLP_SOC_IFC_REG_CPTRA_HW_REV_ID                                                             (0x300300d0)
-#define SOC_IFC_REG_CPTRA_HW_REV_ID                                                                 (0xd0)
-#define CLP_SOC_IFC_REG_CPTRA_FW_REV_ID_0                                                           (0x300300d4)
-#define SOC_IFC_REG_CPTRA_FW_REV_ID_0                                                               (0xd4)
-#define CLP_SOC_IFC_REG_CPTRA_FW_REV_ID_1                                                           (0x300300d8)
-#define SOC_IFC_REG_CPTRA_FW_REV_ID_1                                                               (0xd8)
-#define CLP_SOC_IFC_REG_CPTRA_HW_CONFIG                                                             (0x300300dc)
-#define SOC_IFC_REG_CPTRA_HW_CONFIG                                                                 (0xdc)
+#define CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0                                                 (0x300300c4)
+#define SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0                                                     (0xc4)
+#define CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_1                                                 (0x300300c8)
+#define SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_1                                                     (0xc8)
+#define CLP_SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_0                                                (0x300300cc)
+#define SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_0                                                    (0xcc)
+#define CLP_SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_1                                                (0x300300d0)
+#define SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_1                                                    (0xd0)
+#define CLP_SOC_IFC_REG_CPTRA_HW_REV_ID                                                             (0x300300d4)
+#define SOC_IFC_REG_CPTRA_HW_REV_ID                                                                 (0xd4)
+#define SOC_IFC_REG_CPTRA_HW_REV_ID_CPTRA_GENERATION_LOW                                            (0)
+#define SOC_IFC_REG_CPTRA_HW_REV_ID_CPTRA_GENERATION_MASK                                           (0xffff)
+#define SOC_IFC_REG_CPTRA_HW_REV_ID_SOC_STEPPING_ID_LOW                                             (16)
+#define SOC_IFC_REG_CPTRA_HW_REV_ID_SOC_STEPPING_ID_MASK                                            (0xffff0000)
+#define CLP_SOC_IFC_REG_CPTRA_FW_REV_ID_0                                                           (0x300300d8)
+#define SOC_IFC_REG_CPTRA_FW_REV_ID_0                                                               (0xd8)
+#define CLP_SOC_IFC_REG_CPTRA_FW_REV_ID_1                                                           (0x300300dc)
+#define SOC_IFC_REG_CPTRA_FW_REV_ID_1                                                               (0xdc)
+#define CLP_SOC_IFC_REG_CPTRA_HW_CONFIG                                                             (0x300300e0)
+#define SOC_IFC_REG_CPTRA_HW_CONFIG                                                                 (0xe0)
 #define SOC_IFC_REG_CPTRA_HW_CONFIG_ITRNG_EN_LOW                                                    (0)
 #define SOC_IFC_REG_CPTRA_HW_CONFIG_ITRNG_EN_MASK                                                   (0x1)
 #define SOC_IFC_REG_CPTRA_HW_CONFIG_QSPI_EN_LOW                                                     (1)
 #define SOC_IFC_REG_CPTRA_HW_CONFIG_QSPI_EN_MASK                                                    (0x2)
 #define SOC_IFC_REG_CPTRA_HW_CONFIG_I3C_EN_LOW                                                      (2)
 #define SOC_IFC_REG_CPTRA_HW_CONFIG_I3C_EN_MASK                                                     (0x4)
-#define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_EN                                                         (0x300300e0)
-#define SOC_IFC_REG_CPTRA_WDT_TIMER1_EN                                                             (0xe0)
+#define SOC_IFC_REG_CPTRA_HW_CONFIG_UART_EN_LOW                                                     (3)
+#define SOC_IFC_REG_CPTRA_HW_CONFIG_UART_EN_MASK                                                    (0x8)
+#define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_EN                                                         (0x300300e4)
+#define SOC_IFC_REG_CPTRA_WDT_TIMER1_EN                                                             (0xe4)
 #define SOC_IFC_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_LOW                                               (0)
 #define SOC_IFC_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_MASK                                              (0x1)
-#define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL                                                       (0x300300e4)
-#define SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL                                                           (0xe4)
+#define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL                                                       (0x300300e8)
+#define SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL                                                           (0xe8)
 #define SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART_LOW                                        (0)
 #define SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART_MASK                                       (0x1)
-#define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0                                           (0x300300e8)
-#define SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0                                               (0xe8)
-#define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1                                           (0x300300ec)
-#define SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1                                               (0xec)
-#define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_EN                                                         (0x300300f0)
-#define SOC_IFC_REG_CPTRA_WDT_TIMER2_EN                                                             (0xf0)
+#define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0                                           (0x300300ec)
+#define SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0                                               (0xec)
+#define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1                                           (0x300300f0)
+#define SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1                                               (0xf0)
+#define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_EN                                                         (0x300300f4)
+#define SOC_IFC_REG_CPTRA_WDT_TIMER2_EN                                                             (0xf4)
 #define SOC_IFC_REG_CPTRA_WDT_TIMER2_EN_TIMER2_EN_LOW                                               (0)
 #define SOC_IFC_REG_CPTRA_WDT_TIMER2_EN_TIMER2_EN_MASK                                              (0x1)
-#define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL                                                       (0x300300f4)
-#define SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL                                                           (0xf4)
+#define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL                                                       (0x300300f8)
+#define SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL                                                           (0xf8)
 #define SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART_LOW                                        (0)
 #define SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART_MASK                                       (0x1)
-#define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0                                           (0x300300f8)
-#define SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0                                               (0xf8)
-#define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1                                           (0x300300fc)
-#define SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1                                               (0xfc)
-#define CLP_SOC_IFC_REG_CPTRA_WDT_STATUS                                                            (0x30030100)
-#define SOC_IFC_REG_CPTRA_WDT_STATUS                                                                (0x100)
+#define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0                                           (0x300300fc)
+#define SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0                                               (0xfc)
+#define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1                                           (0x30030100)
+#define SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1                                               (0x100)
+#define CLP_SOC_IFC_REG_CPTRA_WDT_STATUS                                                            (0x30030104)
+#define SOC_IFC_REG_CPTRA_WDT_STATUS                                                                (0x104)
 #define SOC_IFC_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_LOW                                                 (0)
 #define SOC_IFC_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_MASK                                                (0x1)
 #define SOC_IFC_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_LOW                                                 (1)
 #define SOC_IFC_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_MASK                                                (0x2)
+#define CLP_SOC_IFC_REG_CPTRA_FUSE_VALID_PAUSER                                                     (0x30030108)
+#define SOC_IFC_REG_CPTRA_FUSE_VALID_PAUSER                                                         (0x108)
+#define CLP_SOC_IFC_REG_CPTRA_FUSE_PAUSER_LOCK                                                      (0x3003010c)
+#define SOC_IFC_REG_CPTRA_FUSE_PAUSER_LOCK                                                          (0x10c)
+#define SOC_IFC_REG_CPTRA_FUSE_PAUSER_LOCK_LOCK_LOW                                                 (0)
+#define SOC_IFC_REG_CPTRA_FUSE_PAUSER_LOCK_LOCK_MASK                                                (0x1)
+#define CLP_SOC_IFC_REG_CPTRA_WDT_CFG_0                                                             (0x30030110)
+#define SOC_IFC_REG_CPTRA_WDT_CFG_0                                                                 (0x110)
+#define CLP_SOC_IFC_REG_CPTRA_WDT_CFG_1                                                             (0x30030114)
+#define SOC_IFC_REG_CPTRA_WDT_CFG_1                                                                 (0x114)
+#define CLP_SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0                                                (0x30030118)
+#define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0                                                    (0x118)
+#define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_LOW_THRESHOLD_LOW                                  (0)
+#define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_LOW_THRESHOLD_MASK                                 (0xffff)
+#define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_HIGH_THRESHOLD_LOW                                 (16)
+#define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_HIGH_THRESHOLD_MASK                                (0xffff0000)
+#define CLP_SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1                                                (0x3003011c)
+#define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1                                                    (0x11c)
+#define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_REPETITION_COUNT_LOW                               (0)
+#define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_REPETITION_COUNT_MASK                              (0xffff)
+#define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_RSVD_LOW                                           (16)
+#define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_RSVD_MASK                                          (0xffff0000)
+#define CLP_SOC_IFC_REG_CPTRA_RSVD_REG_0                                                            (0x30030120)
+#define SOC_IFC_REG_CPTRA_RSVD_REG_0                                                                (0x120)
+#define CLP_SOC_IFC_REG_CPTRA_RSVD_REG_1                                                            (0x30030124)
+#define SOC_IFC_REG_CPTRA_RSVD_REG_1                                                                (0x124)
 #define CLP_SOC_IFC_REG_FUSE_UDS_SEED_0                                                             (0x30030200)
 #define SOC_IFC_REG_FUSE_UDS_SEED_0                                                                 (0x200)
 #define CLP_SOC_IFC_REG_FUSE_UDS_SEED_1                                                             (0x30030204)
@@ -5387,6 +5752,16 @@
 #define SOC_IFC_REG_FUSE_LIFE_CYCLE                                                                 (0x33c)
 #define SOC_IFC_REG_FUSE_LIFE_CYCLE_LIFE_CYCLE_LOW                                                  (0)
 #define SOC_IFC_REG_FUSE_LIFE_CYCLE_LIFE_CYCLE_MASK                                                 (0x3)
+#define CLP_SOC_IFC_REG_FUSE_LMS_VERIFY                                                             (0x30030340)
+#define SOC_IFC_REG_FUSE_LMS_VERIFY                                                                 (0x340)
+#define SOC_IFC_REG_FUSE_LMS_VERIFY_LMS_VERIFY_LOW                                                  (0)
+#define SOC_IFC_REG_FUSE_LMS_VERIFY_LMS_VERIFY_MASK                                                 (0x1)
+#define CLP_SOC_IFC_REG_FUSE_LMS_REVOCATION                                                         (0x30030344)
+#define SOC_IFC_REG_FUSE_LMS_REVOCATION                                                             (0x344)
+#define CLP_SOC_IFC_REG_FUSE_SOC_STEPPING_ID                                                        (0x30030348)
+#define SOC_IFC_REG_FUSE_SOC_STEPPING_ID                                                            (0x348)
+#define SOC_IFC_REG_FUSE_SOC_STEPPING_ID_SOC_STEPPING_ID_LOW                                        (0)
+#define SOC_IFC_REG_FUSE_SOC_STEPPING_ID_SOC_STEPPING_ID_MASK                                       (0xffff)
 #define CLP_SOC_IFC_REG_INTERNAL_OBF_KEY_0                                                          (0x30030600)
 #define SOC_IFC_REG_INTERNAL_OBF_KEY_0                                                              (0x600)
 #define CLP_SOC_IFC_REG_INTERNAL_OBF_KEY_1                                                          (0x30030604)
@@ -5417,6 +5792,34 @@
 #define SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES_WAIT_CYCLES_MASK                           (0xff)
 #define CLP_SOC_IFC_REG_INTERNAL_NMI_VECTOR                                                         (0x3003062c)
 #define SOC_IFC_REG_INTERNAL_NMI_VECTOR                                                             (0x62c)
+#define CLP_SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK                                                (0x30030630)
+#define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK                                                    (0x630)
+#define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_ICCM_ECC_UNC_LOW                              (0)
+#define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_ICCM_ECC_UNC_MASK                             (0x1)
+#define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_DCCM_ECC_UNC_LOW                              (1)
+#define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_DCCM_ECC_UNC_MASK                             (0x2)
+#define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_NMI_PIN_LOW                                   (2)
+#define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_NMI_PIN_MASK                                  (0x4)
+#define CLP_SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK                                            (0x30030634)
+#define SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK                                                (0x634)
+#define SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK_MASK_MBOX_PROT_NO_LOCK_LOW                     (0)
+#define SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK_MASK_MBOX_PROT_NO_LOCK_MASK                    (0x1)
+#define SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK_MASK_MBOX_PROT_OOO_LOW                         (1)
+#define SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK_MASK_MBOX_PROT_OOO_MASK                        (0x2)
+#define SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK_MASK_MBOX_ECC_UNC_LOW                          (2)
+#define SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK_MASK_MBOX_ECC_UNC_MASK                         (0x4)
+#define CLP_SOC_IFC_REG_INTERNAL_FW_ERROR_FATAL_MASK                                                (0x30030638)
+#define SOC_IFC_REG_INTERNAL_FW_ERROR_FATAL_MASK                                                    (0x638)
+#define CLP_SOC_IFC_REG_INTERNAL_FW_ERROR_NON_FATAL_MASK                                            (0x3003063c)
+#define SOC_IFC_REG_INTERNAL_FW_ERROR_NON_FATAL_MASK                                                (0x63c)
+#define CLP_SOC_IFC_REG_INTERNAL_RV_MTIME_L                                                         (0x30030640)
+#define SOC_IFC_REG_INTERNAL_RV_MTIME_L                                                             (0x640)
+#define CLP_SOC_IFC_REG_INTERNAL_RV_MTIME_H                                                         (0x30030644)
+#define SOC_IFC_REG_INTERNAL_RV_MTIME_H                                                             (0x644)
+#define CLP_SOC_IFC_REG_INTERNAL_RV_MTIMECMP_L                                                      (0x30030648)
+#define SOC_IFC_REG_INTERNAL_RV_MTIMECMP_L                                                          (0x648)
+#define CLP_SOC_IFC_REG_INTERNAL_RV_MTIMECMP_H                                                      (0x3003064c)
+#define SOC_IFC_REG_INTERNAL_RV_MTIMECMP_H                                                          (0x64c)
 #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_START                                                         (0x30030800)
 #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R                                              (0x30030800)
 #define SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R                                                  (0x800)
@@ -5450,8 +5853,12 @@
 #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_MBOX_ECC_COR_EN_MASK                        (0x2)
 #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_DEBUG_LOCKED_EN_LOW                         (2)
 #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_DEBUG_LOCKED_EN_MASK                        (0x4)
-#define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_SOC_REQ_LOCK_EN_LOW                         (3)
-#define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_SOC_REQ_LOCK_EN_MASK                        (0x8)
+#define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_SCAN_MODE_EN_LOW                            (3)
+#define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_SCAN_MODE_EN_MASK                           (0x8)
+#define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_SOC_REQ_LOCK_EN_LOW                         (4)
+#define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_SOC_REQ_LOCK_EN_MASK                        (0x10)
+#define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_GEN_IN_TOGGLE_EN_LOW                        (5)
+#define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_GEN_IN_TOGGLE_EN_MASK                       (0x20)
 #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R                                           (0x3003080c)
 #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R                                               (0x80c)
 #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW                                   (0)
@@ -5486,8 +5893,12 @@
 #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK                 (0x2)
 #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_LOW                  (2)
 #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK                 (0x4)
-#define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_LOW                  (3)
-#define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK                 (0x8)
+#define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_LOW                     (3)
+#define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK                    (0x8)
+#define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_LOW                  (4)
+#define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK                 (0x10)
+#define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_LOW                 (5)
+#define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK                (0x20)
 #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R                                             (0x3003081c)
 #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R                                                 (0x81c)
 #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_INTERNAL_TRIG_LOW                         (0)
@@ -5514,8 +5925,12 @@
 #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_MBOX_ECC_COR_TRIG_MASK                    (0x2)
 #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_DEBUG_LOCKED_TRIG_LOW                     (2)
 #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_DEBUG_LOCKED_TRIG_MASK                    (0x4)
-#define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_SOC_REQ_LOCK_TRIG_LOW                     (3)
-#define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_SOC_REQ_LOCK_TRIG_MASK                    (0x8)
+#define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_SCAN_MODE_TRIG_LOW                        (3)
+#define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_SCAN_MODE_TRIG_MASK                       (0x8)
+#define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_SOC_REQ_LOCK_TRIG_LOW                     (4)
+#define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_SOC_REQ_LOCK_TRIG_MASK                    (0x10)
+#define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_GEN_IN_TOGGLE_TRIG_LOW                    (5)
+#define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_GEN_IN_TOGGLE_TRIG_MASK                   (0x20)
 #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_R                                   (0x30030900)
 #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_R                                       (0x900)
 #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INV_DEV_INTR_COUNT_R                                    (0x30030904)
@@ -5538,8 +5953,12 @@
 #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_R                                   (0x984)
 #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_R                               (0x30030988)
 #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_R                                   (0x988)
-#define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_R                               (0x3003098c)
-#define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_R                                   (0x98c)
+#define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_R                                  (0x3003098c)
+#define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_R                                      (0x98c)
+#define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_R                               (0x30030990)
+#define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_R                                   (0x990)
+#define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_R                              (0x30030994)
+#define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_R                                  (0x994)
 #define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R                              (0x30030a00)
 #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R                                  (0xa00)
 #define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R_PULSE_LOW                        (0)
@@ -5584,10 +6003,18 @@
 #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_INCR_R                              (0xa28)
 #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_INCR_R_PULSE_LOW                    (0)
 #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_INCR_R_PULSE_MASK                   (0x1)
-#define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R                          (0x30030a2c)
-#define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R                              (0xa2c)
+#define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_INCR_R                             (0x30030a2c)
+#define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_INCR_R                                 (0xa2c)
+#define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_INCR_R_PULSE_LOW                       (0)
+#define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_INCR_R_PULSE_MASK                      (0x1)
+#define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R                          (0x30030a30)
+#define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R                              (0xa30)
 #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R_PULSE_LOW                    (0)
 #define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R_PULSE_MASK                   (0x1)
+#define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_INCR_R                         (0x30030a34)
+#define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_INCR_R                             (0xa34)
+#define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_INCR_R_PULSE_LOW                   (0)
+#define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_INCR_R_PULSE_MASK                  (0x1)
 
 
-#endif
+#endif
\ No newline at end of file
diff --git a/src/integration/rtl/caliptra_reg_defines.svh b/src/integration/rtl/caliptra_reg_defines.svh
index 8b7c2851e..c7af5ea04 100644
--- a/src/integration/rtl/caliptra_reg_defines.svh
+++ b/src/integration/rtl/caliptra_reg_defines.svh
@@ -3482,346 +3482,346 @@
 `define DV_REG_STICKY_DATA_VAULT_ENTRY_9_10                                                         (32'h200)
 `define CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_9_11                                                     (32'h1001c204)
 `define DV_REG_STICKY_DATA_VAULT_ENTRY_9_11                                                         (32'h204)
-`define CLP_DV_REG_NONSTICKYDATAVAULTCTRL_0                                                         (32'h1001c208)
-`define DV_REG_NONSTICKYDATAVAULTCTRL_0                                                             (32'h208)
-`define DV_REG_NONSTICKYDATAVAULTCTRL_0_LOCK_ENTRY_LOW                                              (0)
-`define DV_REG_NONSTICKYDATAVAULTCTRL_0_LOCK_ENTRY_MASK                                             (32'h1)
-`define CLP_DV_REG_NONSTICKYDATAVAULTCTRL_1                                                         (32'h1001c20c)
-`define DV_REG_NONSTICKYDATAVAULTCTRL_1                                                             (32'h20c)
-`define DV_REG_NONSTICKYDATAVAULTCTRL_1_LOCK_ENTRY_LOW                                              (0)
-`define DV_REG_NONSTICKYDATAVAULTCTRL_1_LOCK_ENTRY_MASK                                             (32'h1)
-`define CLP_DV_REG_NONSTICKYDATAVAULTCTRL_2                                                         (32'h1001c210)
-`define DV_REG_NONSTICKYDATAVAULTCTRL_2                                                             (32'h210)
-`define DV_REG_NONSTICKYDATAVAULTCTRL_2_LOCK_ENTRY_LOW                                              (0)
-`define DV_REG_NONSTICKYDATAVAULTCTRL_2_LOCK_ENTRY_MASK                                             (32'h1)
-`define CLP_DV_REG_NONSTICKYDATAVAULTCTRL_3                                                         (32'h1001c214)
-`define DV_REG_NONSTICKYDATAVAULTCTRL_3                                                             (32'h214)
-`define DV_REG_NONSTICKYDATAVAULTCTRL_3_LOCK_ENTRY_LOW                                              (0)
-`define DV_REG_NONSTICKYDATAVAULTCTRL_3_LOCK_ENTRY_MASK                                             (32'h1)
-`define CLP_DV_REG_NONSTICKYDATAVAULTCTRL_4                                                         (32'h1001c218)
-`define DV_REG_NONSTICKYDATAVAULTCTRL_4                                                             (32'h218)
-`define DV_REG_NONSTICKYDATAVAULTCTRL_4_LOCK_ENTRY_LOW                                              (0)
-`define DV_REG_NONSTICKYDATAVAULTCTRL_4_LOCK_ENTRY_MASK                                             (32'h1)
-`define CLP_DV_REG_NONSTICKYDATAVAULTCTRL_5                                                         (32'h1001c21c)
-`define DV_REG_NONSTICKYDATAVAULTCTRL_5                                                             (32'h21c)
-`define DV_REG_NONSTICKYDATAVAULTCTRL_5_LOCK_ENTRY_LOW                                              (0)
-`define DV_REG_NONSTICKYDATAVAULTCTRL_5_LOCK_ENTRY_MASK                                             (32'h1)
-`define CLP_DV_REG_NONSTICKYDATAVAULTCTRL_6                                                         (32'h1001c220)
-`define DV_REG_NONSTICKYDATAVAULTCTRL_6                                                             (32'h220)
-`define DV_REG_NONSTICKYDATAVAULTCTRL_6_LOCK_ENTRY_LOW                                              (0)
-`define DV_REG_NONSTICKYDATAVAULTCTRL_6_LOCK_ENTRY_MASK                                             (32'h1)
-`define CLP_DV_REG_NONSTICKYDATAVAULTCTRL_7                                                         (32'h1001c224)
-`define DV_REG_NONSTICKYDATAVAULTCTRL_7                                                             (32'h224)
-`define DV_REG_NONSTICKYDATAVAULTCTRL_7_LOCK_ENTRY_LOW                                              (0)
-`define DV_REG_NONSTICKYDATAVAULTCTRL_7_LOCK_ENTRY_MASK                                             (32'h1)
-`define CLP_DV_REG_NONSTICKYDATAVAULTCTRL_8                                                         (32'h1001c228)
-`define DV_REG_NONSTICKYDATAVAULTCTRL_8                                                             (32'h228)
-`define DV_REG_NONSTICKYDATAVAULTCTRL_8_LOCK_ENTRY_LOW                                              (0)
-`define DV_REG_NONSTICKYDATAVAULTCTRL_8_LOCK_ENTRY_MASK                                             (32'h1)
-`define CLP_DV_REG_NONSTICKYDATAVAULTCTRL_9                                                         (32'h1001c22c)
-`define DV_REG_NONSTICKYDATAVAULTCTRL_9                                                             (32'h22c)
-`define DV_REG_NONSTICKYDATAVAULTCTRL_9_LOCK_ENTRY_LOW                                              (0)
-`define DV_REG_NONSTICKYDATAVAULTCTRL_9_LOCK_ENTRY_MASK                                             (32'h1)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_0                                                   (32'h1001c230)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_0                                                       (32'h230)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_1                                                   (32'h1001c234)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_1                                                       (32'h234)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_2                                                   (32'h1001c238)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_2                                                       (32'h238)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_3                                                   (32'h1001c23c)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_3                                                       (32'h23c)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_4                                                   (32'h1001c240)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_4                                                       (32'h240)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_5                                                   (32'h1001c244)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_5                                                       (32'h244)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_6                                                   (32'h1001c248)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_6                                                       (32'h248)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_7                                                   (32'h1001c24c)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_7                                                       (32'h24c)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_8                                                   (32'h1001c250)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_8                                                       (32'h250)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_9                                                   (32'h1001c254)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_9                                                       (32'h254)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_10                                                  (32'h1001c258)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_10                                                      (32'h258)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_11                                                  (32'h1001c25c)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_11                                                      (32'h25c)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_0                                                   (32'h1001c260)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_0                                                       (32'h260)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_1                                                   (32'h1001c264)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_1                                                       (32'h264)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_2                                                   (32'h1001c268)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_2                                                       (32'h268)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_3                                                   (32'h1001c26c)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_3                                                       (32'h26c)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_4                                                   (32'h1001c270)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_4                                                       (32'h270)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_5                                                   (32'h1001c274)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_5                                                       (32'h274)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_6                                                   (32'h1001c278)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_6                                                       (32'h278)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_7                                                   (32'h1001c27c)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_7                                                       (32'h27c)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_8                                                   (32'h1001c280)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_8                                                       (32'h280)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_9                                                   (32'h1001c284)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_9                                                       (32'h284)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_10                                                  (32'h1001c288)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_10                                                      (32'h288)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_11                                                  (32'h1001c28c)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_11                                                      (32'h28c)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_0                                                   (32'h1001c290)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_0                                                       (32'h290)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_1                                                   (32'h1001c294)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_1                                                       (32'h294)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_2                                                   (32'h1001c298)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_2                                                       (32'h298)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_3                                                   (32'h1001c29c)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_3                                                       (32'h29c)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_4                                                   (32'h1001c2a0)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_4                                                       (32'h2a0)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_5                                                   (32'h1001c2a4)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_5                                                       (32'h2a4)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_6                                                   (32'h1001c2a8)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_6                                                       (32'h2a8)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_7                                                   (32'h1001c2ac)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_7                                                       (32'h2ac)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_8                                                   (32'h1001c2b0)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_8                                                       (32'h2b0)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_9                                                   (32'h1001c2b4)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_9                                                       (32'h2b4)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_10                                                  (32'h1001c2b8)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_10                                                      (32'h2b8)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_11                                                  (32'h1001c2bc)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_11                                                      (32'h2bc)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_0                                                   (32'h1001c2c0)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_0                                                       (32'h2c0)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_1                                                   (32'h1001c2c4)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_1                                                       (32'h2c4)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_2                                                   (32'h1001c2c8)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_2                                                       (32'h2c8)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_3                                                   (32'h1001c2cc)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_3                                                       (32'h2cc)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_4                                                   (32'h1001c2d0)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_4                                                       (32'h2d0)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_5                                                   (32'h1001c2d4)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_5                                                       (32'h2d4)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_6                                                   (32'h1001c2d8)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_6                                                       (32'h2d8)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_7                                                   (32'h1001c2dc)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_7                                                       (32'h2dc)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_8                                                   (32'h1001c2e0)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_8                                                       (32'h2e0)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_9                                                   (32'h1001c2e4)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_9                                                       (32'h2e4)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_10                                                  (32'h1001c2e8)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_10                                                      (32'h2e8)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_11                                                  (32'h1001c2ec)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_11                                                      (32'h2ec)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_0                                                   (32'h1001c2f0)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_0                                                       (32'h2f0)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_1                                                   (32'h1001c2f4)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_1                                                       (32'h2f4)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_2                                                   (32'h1001c2f8)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_2                                                       (32'h2f8)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_3                                                   (32'h1001c2fc)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_3                                                       (32'h2fc)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_4                                                   (32'h1001c300)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_4                                                       (32'h300)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_5                                                   (32'h1001c304)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_5                                                       (32'h304)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_6                                                   (32'h1001c308)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_6                                                       (32'h308)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_7                                                   (32'h1001c30c)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_7                                                       (32'h30c)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_8                                                   (32'h1001c310)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_8                                                       (32'h310)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_9                                                   (32'h1001c314)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_9                                                       (32'h314)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_10                                                  (32'h1001c318)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_10                                                      (32'h318)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_11                                                  (32'h1001c31c)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_11                                                      (32'h31c)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_0                                                   (32'h1001c320)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_0                                                       (32'h320)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_1                                                   (32'h1001c324)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_1                                                       (32'h324)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_2                                                   (32'h1001c328)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_2                                                       (32'h328)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_3                                                   (32'h1001c32c)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_3                                                       (32'h32c)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_4                                                   (32'h1001c330)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_4                                                       (32'h330)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_5                                                   (32'h1001c334)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_5                                                       (32'h334)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_6                                                   (32'h1001c338)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_6                                                       (32'h338)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_7                                                   (32'h1001c33c)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_7                                                       (32'h33c)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_8                                                   (32'h1001c340)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_8                                                       (32'h340)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_9                                                   (32'h1001c344)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_9                                                       (32'h344)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_10                                                  (32'h1001c348)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_10                                                      (32'h348)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_11                                                  (32'h1001c34c)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_11                                                      (32'h34c)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_0                                                   (32'h1001c350)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_0                                                       (32'h350)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_1                                                   (32'h1001c354)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_1                                                       (32'h354)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_2                                                   (32'h1001c358)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_2                                                       (32'h358)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_3                                                   (32'h1001c35c)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_3                                                       (32'h35c)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_4                                                   (32'h1001c360)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_4                                                       (32'h360)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_5                                                   (32'h1001c364)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_5                                                       (32'h364)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_6                                                   (32'h1001c368)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_6                                                       (32'h368)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_7                                                   (32'h1001c36c)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_7                                                       (32'h36c)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_8                                                   (32'h1001c370)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_8                                                       (32'h370)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_9                                                   (32'h1001c374)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_9                                                       (32'h374)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_10                                                  (32'h1001c378)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_10                                                      (32'h378)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_11                                                  (32'h1001c37c)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_11                                                      (32'h37c)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_0                                                   (32'h1001c380)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_0                                                       (32'h380)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_1                                                   (32'h1001c384)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_1                                                       (32'h384)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_2                                                   (32'h1001c388)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_2                                                       (32'h388)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_3                                                   (32'h1001c38c)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_3                                                       (32'h38c)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_4                                                   (32'h1001c390)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_4                                                       (32'h390)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_5                                                   (32'h1001c394)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_5                                                       (32'h394)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_6                                                   (32'h1001c398)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_6                                                       (32'h398)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_7                                                   (32'h1001c39c)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_7                                                       (32'h39c)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_8                                                   (32'h1001c3a0)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_8                                                       (32'h3a0)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_9                                                   (32'h1001c3a4)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_9                                                       (32'h3a4)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_10                                                  (32'h1001c3a8)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_10                                                      (32'h3a8)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_11                                                  (32'h1001c3ac)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_11                                                      (32'h3ac)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_0                                                   (32'h1001c3b0)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_0                                                       (32'h3b0)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_1                                                   (32'h1001c3b4)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_1                                                       (32'h3b4)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_2                                                   (32'h1001c3b8)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_2                                                       (32'h3b8)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_3                                                   (32'h1001c3bc)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_3                                                       (32'h3bc)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_4                                                   (32'h1001c3c0)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_4                                                       (32'h3c0)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_5                                                   (32'h1001c3c4)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_5                                                       (32'h3c4)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_6                                                   (32'h1001c3c8)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_6                                                       (32'h3c8)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_7                                                   (32'h1001c3cc)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_7                                                       (32'h3cc)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_8                                                   (32'h1001c3d0)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_8                                                       (32'h3d0)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_9                                                   (32'h1001c3d4)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_9                                                       (32'h3d4)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_10                                                  (32'h1001c3d8)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_10                                                      (32'h3d8)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_11                                                  (32'h1001c3dc)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_11                                                      (32'h3dc)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_0                                                   (32'h1001c3e0)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_0                                                       (32'h3e0)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_1                                                   (32'h1001c3e4)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_1                                                       (32'h3e4)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_2                                                   (32'h1001c3e8)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_2                                                       (32'h3e8)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_3                                                   (32'h1001c3ec)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_3                                                       (32'h3ec)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_4                                                   (32'h1001c3f0)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_4                                                       (32'h3f0)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_5                                                   (32'h1001c3f4)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_5                                                       (32'h3f4)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_6                                                   (32'h1001c3f8)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_6                                                       (32'h3f8)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_7                                                   (32'h1001c3fc)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_7                                                       (32'h3fc)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_8                                                   (32'h1001c400)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_8                                                       (32'h400)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_9                                                   (32'h1001c404)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_9                                                       (32'h404)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_10                                                  (32'h1001c408)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_10                                                      (32'h408)
-`define CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_11                                                  (32'h1001c40c)
-`define DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_11                                                      (32'h40c)
-`define CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_0                                                (32'h1001c410)
-`define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_0                                                    (32'h410)
-`define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_0_LOCK_ENTRY_LOW                                     (0)
-`define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_0_LOCK_ENTRY_MASK                                    (32'h1)
-`define CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_1                                                (32'h1001c414)
-`define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_1                                                    (32'h414)
-`define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_1_LOCK_ENTRY_LOW                                     (0)
-`define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_1_LOCK_ENTRY_MASK                                    (32'h1)
-`define CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_2                                                (32'h1001c418)
-`define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_2                                                    (32'h418)
-`define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_2_LOCK_ENTRY_LOW                                     (0)
-`define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_2_LOCK_ENTRY_MASK                                    (32'h1)
-`define CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_3                                                (32'h1001c41c)
-`define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_3                                                    (32'h41c)
-`define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_3_LOCK_ENTRY_LOW                                     (0)
-`define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_3_LOCK_ENTRY_MASK                                    (32'h1)
-`define CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_4                                                (32'h1001c420)
-`define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_4                                                    (32'h420)
-`define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_4_LOCK_ENTRY_LOW                                     (0)
-`define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_4_LOCK_ENTRY_MASK                                    (32'h1)
-`define CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_5                                                (32'h1001c424)
-`define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_5                                                    (32'h424)
-`define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_5_LOCK_ENTRY_LOW                                     (0)
-`define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_5_LOCK_ENTRY_MASK                                    (32'h1)
-`define CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_6                                                (32'h1001c428)
-`define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_6                                                    (32'h428)
-`define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_6_LOCK_ENTRY_LOW                                     (0)
-`define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_6_LOCK_ENTRY_MASK                                    (32'h1)
-`define CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_7                                                (32'h1001c42c)
-`define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_7                                                    (32'h42c)
-`define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_7_LOCK_ENTRY_LOW                                     (0)
-`define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_7_LOCK_ENTRY_MASK                                    (32'h1)
-`define CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_8                                                (32'h1001c430)
-`define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_8                                                    (32'h430)
-`define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_8_LOCK_ENTRY_LOW                                     (0)
-`define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_8_LOCK_ENTRY_MASK                                    (32'h1)
-`define CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_9                                                (32'h1001c434)
-`define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_9                                                    (32'h434)
-`define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_9_LOCK_ENTRY_LOW                                     (0)
-`define DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_9_LOCK_ENTRY_MASK                                    (32'h1)
-`define CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREG_0                                                    (32'h1001c438)
-`define DV_REG_NONSTICKYLOCKABLESCRATCHREG_0                                                        (32'h438)
-`define CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREG_1                                                    (32'h1001c43c)
-`define DV_REG_NONSTICKYLOCKABLESCRATCHREG_1                                                        (32'h43c)
-`define CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREG_2                                                    (32'h1001c440)
-`define DV_REG_NONSTICKYLOCKABLESCRATCHREG_2                                                        (32'h440)
-`define CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREG_3                                                    (32'h1001c444)
-`define DV_REG_NONSTICKYLOCKABLESCRATCHREG_3                                                        (32'h444)
-`define CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREG_4                                                    (32'h1001c448)
-`define DV_REG_NONSTICKYLOCKABLESCRATCHREG_4                                                        (32'h448)
-`define CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREG_5                                                    (32'h1001c44c)
-`define DV_REG_NONSTICKYLOCKABLESCRATCHREG_5                                                        (32'h44c)
-`define CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREG_6                                                    (32'h1001c450)
-`define DV_REG_NONSTICKYLOCKABLESCRATCHREG_6                                                        (32'h450)
-`define CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREG_7                                                    (32'h1001c454)
-`define DV_REG_NONSTICKYLOCKABLESCRATCHREG_7                                                        (32'h454)
-`define CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREG_8                                                    (32'h1001c458)
-`define DV_REG_NONSTICKYLOCKABLESCRATCHREG_8                                                        (32'h458)
-`define CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREG_9                                                    (32'h1001c45c)
-`define DV_REG_NONSTICKYLOCKABLESCRATCHREG_9                                                        (32'h45c)
+`define CLP_DV_REG_DATAVAULTCTRL_0                                                                  (32'h1001c208)
+`define DV_REG_DATAVAULTCTRL_0                                                                      (32'h208)
+`define DV_REG_DATAVAULTCTRL_0_LOCK_ENTRY_LOW                                                       (0)
+`define DV_REG_DATAVAULTCTRL_0_LOCK_ENTRY_MASK                                                      (32'h1)
+`define CLP_DV_REG_DATAVAULTCTRL_1                                                                  (32'h1001c20c)
+`define DV_REG_DATAVAULTCTRL_1                                                                      (32'h20c)
+`define DV_REG_DATAVAULTCTRL_1_LOCK_ENTRY_LOW                                                       (0)
+`define DV_REG_DATAVAULTCTRL_1_LOCK_ENTRY_MASK                                                      (32'h1)
+`define CLP_DV_REG_DATAVAULTCTRL_2                                                                  (32'h1001c210)
+`define DV_REG_DATAVAULTCTRL_2                                                                      (32'h210)
+`define DV_REG_DATAVAULTCTRL_2_LOCK_ENTRY_LOW                                                       (0)
+`define DV_REG_DATAVAULTCTRL_2_LOCK_ENTRY_MASK                                                      (32'h1)
+`define CLP_DV_REG_DATAVAULTCTRL_3                                                                  (32'h1001c214)
+`define DV_REG_DATAVAULTCTRL_3                                                                      (32'h214)
+`define DV_REG_DATAVAULTCTRL_3_LOCK_ENTRY_LOW                                                       (0)
+`define DV_REG_DATAVAULTCTRL_3_LOCK_ENTRY_MASK                                                      (32'h1)
+`define CLP_DV_REG_DATAVAULTCTRL_4                                                                  (32'h1001c218)
+`define DV_REG_DATAVAULTCTRL_4                                                                      (32'h218)
+`define DV_REG_DATAVAULTCTRL_4_LOCK_ENTRY_LOW                                                       (0)
+`define DV_REG_DATAVAULTCTRL_4_LOCK_ENTRY_MASK                                                      (32'h1)
+`define CLP_DV_REG_DATAVAULTCTRL_5                                                                  (32'h1001c21c)
+`define DV_REG_DATAVAULTCTRL_5                                                                      (32'h21c)
+`define DV_REG_DATAVAULTCTRL_5_LOCK_ENTRY_LOW                                                       (0)
+`define DV_REG_DATAVAULTCTRL_5_LOCK_ENTRY_MASK                                                      (32'h1)
+`define CLP_DV_REG_DATAVAULTCTRL_6                                                                  (32'h1001c220)
+`define DV_REG_DATAVAULTCTRL_6                                                                      (32'h220)
+`define DV_REG_DATAVAULTCTRL_6_LOCK_ENTRY_LOW                                                       (0)
+`define DV_REG_DATAVAULTCTRL_6_LOCK_ENTRY_MASK                                                      (32'h1)
+`define CLP_DV_REG_DATAVAULTCTRL_7                                                                  (32'h1001c224)
+`define DV_REG_DATAVAULTCTRL_7                                                                      (32'h224)
+`define DV_REG_DATAVAULTCTRL_7_LOCK_ENTRY_LOW                                                       (0)
+`define DV_REG_DATAVAULTCTRL_7_LOCK_ENTRY_MASK                                                      (32'h1)
+`define CLP_DV_REG_DATAVAULTCTRL_8                                                                  (32'h1001c228)
+`define DV_REG_DATAVAULTCTRL_8                                                                      (32'h228)
+`define DV_REG_DATAVAULTCTRL_8_LOCK_ENTRY_LOW                                                       (0)
+`define DV_REG_DATAVAULTCTRL_8_LOCK_ENTRY_MASK                                                      (32'h1)
+`define CLP_DV_REG_DATAVAULTCTRL_9                                                                  (32'h1001c22c)
+`define DV_REG_DATAVAULTCTRL_9                                                                      (32'h22c)
+`define DV_REG_DATAVAULTCTRL_9_LOCK_ENTRY_LOW                                                       (0)
+`define DV_REG_DATAVAULTCTRL_9_LOCK_ENTRY_MASK                                                      (32'h1)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_0_0                                                             (32'h1001c230)
+`define DV_REG_DATA_VAULT_ENTRY_0_0                                                                 (32'h230)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_0_1                                                             (32'h1001c234)
+`define DV_REG_DATA_VAULT_ENTRY_0_1                                                                 (32'h234)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_0_2                                                             (32'h1001c238)
+`define DV_REG_DATA_VAULT_ENTRY_0_2                                                                 (32'h238)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_0_3                                                             (32'h1001c23c)
+`define DV_REG_DATA_VAULT_ENTRY_0_3                                                                 (32'h23c)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_0_4                                                             (32'h1001c240)
+`define DV_REG_DATA_VAULT_ENTRY_0_4                                                                 (32'h240)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_0_5                                                             (32'h1001c244)
+`define DV_REG_DATA_VAULT_ENTRY_0_5                                                                 (32'h244)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_0_6                                                             (32'h1001c248)
+`define DV_REG_DATA_VAULT_ENTRY_0_6                                                                 (32'h248)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_0_7                                                             (32'h1001c24c)
+`define DV_REG_DATA_VAULT_ENTRY_0_7                                                                 (32'h24c)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_0_8                                                             (32'h1001c250)
+`define DV_REG_DATA_VAULT_ENTRY_0_8                                                                 (32'h250)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_0_9                                                             (32'h1001c254)
+`define DV_REG_DATA_VAULT_ENTRY_0_9                                                                 (32'h254)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_0_10                                                            (32'h1001c258)
+`define DV_REG_DATA_VAULT_ENTRY_0_10                                                                (32'h258)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_0_11                                                            (32'h1001c25c)
+`define DV_REG_DATA_VAULT_ENTRY_0_11                                                                (32'h25c)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_1_0                                                             (32'h1001c260)
+`define DV_REG_DATA_VAULT_ENTRY_1_0                                                                 (32'h260)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_1_1                                                             (32'h1001c264)
+`define DV_REG_DATA_VAULT_ENTRY_1_1                                                                 (32'h264)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_1_2                                                             (32'h1001c268)
+`define DV_REG_DATA_VAULT_ENTRY_1_2                                                                 (32'h268)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_1_3                                                             (32'h1001c26c)
+`define DV_REG_DATA_VAULT_ENTRY_1_3                                                                 (32'h26c)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_1_4                                                             (32'h1001c270)
+`define DV_REG_DATA_VAULT_ENTRY_1_4                                                                 (32'h270)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_1_5                                                             (32'h1001c274)
+`define DV_REG_DATA_VAULT_ENTRY_1_5                                                                 (32'h274)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_1_6                                                             (32'h1001c278)
+`define DV_REG_DATA_VAULT_ENTRY_1_6                                                                 (32'h278)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_1_7                                                             (32'h1001c27c)
+`define DV_REG_DATA_VAULT_ENTRY_1_7                                                                 (32'h27c)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_1_8                                                             (32'h1001c280)
+`define DV_REG_DATA_VAULT_ENTRY_1_8                                                                 (32'h280)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_1_9                                                             (32'h1001c284)
+`define DV_REG_DATA_VAULT_ENTRY_1_9                                                                 (32'h284)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_1_10                                                            (32'h1001c288)
+`define DV_REG_DATA_VAULT_ENTRY_1_10                                                                (32'h288)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_1_11                                                            (32'h1001c28c)
+`define DV_REG_DATA_VAULT_ENTRY_1_11                                                                (32'h28c)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_2_0                                                             (32'h1001c290)
+`define DV_REG_DATA_VAULT_ENTRY_2_0                                                                 (32'h290)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_2_1                                                             (32'h1001c294)
+`define DV_REG_DATA_VAULT_ENTRY_2_1                                                                 (32'h294)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_2_2                                                             (32'h1001c298)
+`define DV_REG_DATA_VAULT_ENTRY_2_2                                                                 (32'h298)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_2_3                                                             (32'h1001c29c)
+`define DV_REG_DATA_VAULT_ENTRY_2_3                                                                 (32'h29c)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_2_4                                                             (32'h1001c2a0)
+`define DV_REG_DATA_VAULT_ENTRY_2_4                                                                 (32'h2a0)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_2_5                                                             (32'h1001c2a4)
+`define DV_REG_DATA_VAULT_ENTRY_2_5                                                                 (32'h2a4)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_2_6                                                             (32'h1001c2a8)
+`define DV_REG_DATA_VAULT_ENTRY_2_6                                                                 (32'h2a8)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_2_7                                                             (32'h1001c2ac)
+`define DV_REG_DATA_VAULT_ENTRY_2_7                                                                 (32'h2ac)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_2_8                                                             (32'h1001c2b0)
+`define DV_REG_DATA_VAULT_ENTRY_2_8                                                                 (32'h2b0)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_2_9                                                             (32'h1001c2b4)
+`define DV_REG_DATA_VAULT_ENTRY_2_9                                                                 (32'h2b4)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_2_10                                                            (32'h1001c2b8)
+`define DV_REG_DATA_VAULT_ENTRY_2_10                                                                (32'h2b8)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_2_11                                                            (32'h1001c2bc)
+`define DV_REG_DATA_VAULT_ENTRY_2_11                                                                (32'h2bc)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_3_0                                                             (32'h1001c2c0)
+`define DV_REG_DATA_VAULT_ENTRY_3_0                                                                 (32'h2c0)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_3_1                                                             (32'h1001c2c4)
+`define DV_REG_DATA_VAULT_ENTRY_3_1                                                                 (32'h2c4)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_3_2                                                             (32'h1001c2c8)
+`define DV_REG_DATA_VAULT_ENTRY_3_2                                                                 (32'h2c8)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_3_3                                                             (32'h1001c2cc)
+`define DV_REG_DATA_VAULT_ENTRY_3_3                                                                 (32'h2cc)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_3_4                                                             (32'h1001c2d0)
+`define DV_REG_DATA_VAULT_ENTRY_3_4                                                                 (32'h2d0)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_3_5                                                             (32'h1001c2d4)
+`define DV_REG_DATA_VAULT_ENTRY_3_5                                                                 (32'h2d4)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_3_6                                                             (32'h1001c2d8)
+`define DV_REG_DATA_VAULT_ENTRY_3_6                                                                 (32'h2d8)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_3_7                                                             (32'h1001c2dc)
+`define DV_REG_DATA_VAULT_ENTRY_3_7                                                                 (32'h2dc)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_3_8                                                             (32'h1001c2e0)
+`define DV_REG_DATA_VAULT_ENTRY_3_8                                                                 (32'h2e0)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_3_9                                                             (32'h1001c2e4)
+`define DV_REG_DATA_VAULT_ENTRY_3_9                                                                 (32'h2e4)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_3_10                                                            (32'h1001c2e8)
+`define DV_REG_DATA_VAULT_ENTRY_3_10                                                                (32'h2e8)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_3_11                                                            (32'h1001c2ec)
+`define DV_REG_DATA_VAULT_ENTRY_3_11                                                                (32'h2ec)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_4_0                                                             (32'h1001c2f0)
+`define DV_REG_DATA_VAULT_ENTRY_4_0                                                                 (32'h2f0)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_4_1                                                             (32'h1001c2f4)
+`define DV_REG_DATA_VAULT_ENTRY_4_1                                                                 (32'h2f4)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_4_2                                                             (32'h1001c2f8)
+`define DV_REG_DATA_VAULT_ENTRY_4_2                                                                 (32'h2f8)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_4_3                                                             (32'h1001c2fc)
+`define DV_REG_DATA_VAULT_ENTRY_4_3                                                                 (32'h2fc)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_4_4                                                             (32'h1001c300)
+`define DV_REG_DATA_VAULT_ENTRY_4_4                                                                 (32'h300)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_4_5                                                             (32'h1001c304)
+`define DV_REG_DATA_VAULT_ENTRY_4_5                                                                 (32'h304)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_4_6                                                             (32'h1001c308)
+`define DV_REG_DATA_VAULT_ENTRY_4_6                                                                 (32'h308)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_4_7                                                             (32'h1001c30c)
+`define DV_REG_DATA_VAULT_ENTRY_4_7                                                                 (32'h30c)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_4_8                                                             (32'h1001c310)
+`define DV_REG_DATA_VAULT_ENTRY_4_8                                                                 (32'h310)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_4_9                                                             (32'h1001c314)
+`define DV_REG_DATA_VAULT_ENTRY_4_9                                                                 (32'h314)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_4_10                                                            (32'h1001c318)
+`define DV_REG_DATA_VAULT_ENTRY_4_10                                                                (32'h318)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_4_11                                                            (32'h1001c31c)
+`define DV_REG_DATA_VAULT_ENTRY_4_11                                                                (32'h31c)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_5_0                                                             (32'h1001c320)
+`define DV_REG_DATA_VAULT_ENTRY_5_0                                                                 (32'h320)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_5_1                                                             (32'h1001c324)
+`define DV_REG_DATA_VAULT_ENTRY_5_1                                                                 (32'h324)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_5_2                                                             (32'h1001c328)
+`define DV_REG_DATA_VAULT_ENTRY_5_2                                                                 (32'h328)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_5_3                                                             (32'h1001c32c)
+`define DV_REG_DATA_VAULT_ENTRY_5_3                                                                 (32'h32c)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_5_4                                                             (32'h1001c330)
+`define DV_REG_DATA_VAULT_ENTRY_5_4                                                                 (32'h330)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_5_5                                                             (32'h1001c334)
+`define DV_REG_DATA_VAULT_ENTRY_5_5                                                                 (32'h334)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_5_6                                                             (32'h1001c338)
+`define DV_REG_DATA_VAULT_ENTRY_5_6                                                                 (32'h338)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_5_7                                                             (32'h1001c33c)
+`define DV_REG_DATA_VAULT_ENTRY_5_7                                                                 (32'h33c)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_5_8                                                             (32'h1001c340)
+`define DV_REG_DATA_VAULT_ENTRY_5_8                                                                 (32'h340)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_5_9                                                             (32'h1001c344)
+`define DV_REG_DATA_VAULT_ENTRY_5_9                                                                 (32'h344)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_5_10                                                            (32'h1001c348)
+`define DV_REG_DATA_VAULT_ENTRY_5_10                                                                (32'h348)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_5_11                                                            (32'h1001c34c)
+`define DV_REG_DATA_VAULT_ENTRY_5_11                                                                (32'h34c)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_6_0                                                             (32'h1001c350)
+`define DV_REG_DATA_VAULT_ENTRY_6_0                                                                 (32'h350)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_6_1                                                             (32'h1001c354)
+`define DV_REG_DATA_VAULT_ENTRY_6_1                                                                 (32'h354)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_6_2                                                             (32'h1001c358)
+`define DV_REG_DATA_VAULT_ENTRY_6_2                                                                 (32'h358)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_6_3                                                             (32'h1001c35c)
+`define DV_REG_DATA_VAULT_ENTRY_6_3                                                                 (32'h35c)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_6_4                                                             (32'h1001c360)
+`define DV_REG_DATA_VAULT_ENTRY_6_4                                                                 (32'h360)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_6_5                                                             (32'h1001c364)
+`define DV_REG_DATA_VAULT_ENTRY_6_5                                                                 (32'h364)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_6_6                                                             (32'h1001c368)
+`define DV_REG_DATA_VAULT_ENTRY_6_6                                                                 (32'h368)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_6_7                                                             (32'h1001c36c)
+`define DV_REG_DATA_VAULT_ENTRY_6_7                                                                 (32'h36c)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_6_8                                                             (32'h1001c370)
+`define DV_REG_DATA_VAULT_ENTRY_6_8                                                                 (32'h370)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_6_9                                                             (32'h1001c374)
+`define DV_REG_DATA_VAULT_ENTRY_6_9                                                                 (32'h374)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_6_10                                                            (32'h1001c378)
+`define DV_REG_DATA_VAULT_ENTRY_6_10                                                                (32'h378)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_6_11                                                            (32'h1001c37c)
+`define DV_REG_DATA_VAULT_ENTRY_6_11                                                                (32'h37c)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_7_0                                                             (32'h1001c380)
+`define DV_REG_DATA_VAULT_ENTRY_7_0                                                                 (32'h380)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_7_1                                                             (32'h1001c384)
+`define DV_REG_DATA_VAULT_ENTRY_7_1                                                                 (32'h384)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_7_2                                                             (32'h1001c388)
+`define DV_REG_DATA_VAULT_ENTRY_7_2                                                                 (32'h388)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_7_3                                                             (32'h1001c38c)
+`define DV_REG_DATA_VAULT_ENTRY_7_3                                                                 (32'h38c)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_7_4                                                             (32'h1001c390)
+`define DV_REG_DATA_VAULT_ENTRY_7_4                                                                 (32'h390)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_7_5                                                             (32'h1001c394)
+`define DV_REG_DATA_VAULT_ENTRY_7_5                                                                 (32'h394)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_7_6                                                             (32'h1001c398)
+`define DV_REG_DATA_VAULT_ENTRY_7_6                                                                 (32'h398)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_7_7                                                             (32'h1001c39c)
+`define DV_REG_DATA_VAULT_ENTRY_7_7                                                                 (32'h39c)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_7_8                                                             (32'h1001c3a0)
+`define DV_REG_DATA_VAULT_ENTRY_7_8                                                                 (32'h3a0)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_7_9                                                             (32'h1001c3a4)
+`define DV_REG_DATA_VAULT_ENTRY_7_9                                                                 (32'h3a4)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_7_10                                                            (32'h1001c3a8)
+`define DV_REG_DATA_VAULT_ENTRY_7_10                                                                (32'h3a8)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_7_11                                                            (32'h1001c3ac)
+`define DV_REG_DATA_VAULT_ENTRY_7_11                                                                (32'h3ac)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_8_0                                                             (32'h1001c3b0)
+`define DV_REG_DATA_VAULT_ENTRY_8_0                                                                 (32'h3b0)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_8_1                                                             (32'h1001c3b4)
+`define DV_REG_DATA_VAULT_ENTRY_8_1                                                                 (32'h3b4)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_8_2                                                             (32'h1001c3b8)
+`define DV_REG_DATA_VAULT_ENTRY_8_2                                                                 (32'h3b8)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_8_3                                                             (32'h1001c3bc)
+`define DV_REG_DATA_VAULT_ENTRY_8_3                                                                 (32'h3bc)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_8_4                                                             (32'h1001c3c0)
+`define DV_REG_DATA_VAULT_ENTRY_8_4                                                                 (32'h3c0)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_8_5                                                             (32'h1001c3c4)
+`define DV_REG_DATA_VAULT_ENTRY_8_5                                                                 (32'h3c4)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_8_6                                                             (32'h1001c3c8)
+`define DV_REG_DATA_VAULT_ENTRY_8_6                                                                 (32'h3c8)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_8_7                                                             (32'h1001c3cc)
+`define DV_REG_DATA_VAULT_ENTRY_8_7                                                                 (32'h3cc)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_8_8                                                             (32'h1001c3d0)
+`define DV_REG_DATA_VAULT_ENTRY_8_8                                                                 (32'h3d0)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_8_9                                                             (32'h1001c3d4)
+`define DV_REG_DATA_VAULT_ENTRY_8_9                                                                 (32'h3d4)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_8_10                                                            (32'h1001c3d8)
+`define DV_REG_DATA_VAULT_ENTRY_8_10                                                                (32'h3d8)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_8_11                                                            (32'h1001c3dc)
+`define DV_REG_DATA_VAULT_ENTRY_8_11                                                                (32'h3dc)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_9_0                                                             (32'h1001c3e0)
+`define DV_REG_DATA_VAULT_ENTRY_9_0                                                                 (32'h3e0)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_9_1                                                             (32'h1001c3e4)
+`define DV_REG_DATA_VAULT_ENTRY_9_1                                                                 (32'h3e4)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_9_2                                                             (32'h1001c3e8)
+`define DV_REG_DATA_VAULT_ENTRY_9_2                                                                 (32'h3e8)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_9_3                                                             (32'h1001c3ec)
+`define DV_REG_DATA_VAULT_ENTRY_9_3                                                                 (32'h3ec)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_9_4                                                             (32'h1001c3f0)
+`define DV_REG_DATA_VAULT_ENTRY_9_4                                                                 (32'h3f0)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_9_5                                                             (32'h1001c3f4)
+`define DV_REG_DATA_VAULT_ENTRY_9_5                                                                 (32'h3f4)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_9_6                                                             (32'h1001c3f8)
+`define DV_REG_DATA_VAULT_ENTRY_9_6                                                                 (32'h3f8)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_9_7                                                             (32'h1001c3fc)
+`define DV_REG_DATA_VAULT_ENTRY_9_7                                                                 (32'h3fc)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_9_8                                                             (32'h1001c400)
+`define DV_REG_DATA_VAULT_ENTRY_9_8                                                                 (32'h400)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_9_9                                                             (32'h1001c404)
+`define DV_REG_DATA_VAULT_ENTRY_9_9                                                                 (32'h404)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_9_10                                                            (32'h1001c408)
+`define DV_REG_DATA_VAULT_ENTRY_9_10                                                                (32'h408)
+`define CLP_DV_REG_DATA_VAULT_ENTRY_9_11                                                            (32'h1001c40c)
+`define DV_REG_DATA_VAULT_ENTRY_9_11                                                                (32'h40c)
+`define CLP_DV_REG_LOCKABLESCRATCHREGCTRL_0                                                         (32'h1001c410)
+`define DV_REG_LOCKABLESCRATCHREGCTRL_0                                                             (32'h410)
+`define DV_REG_LOCKABLESCRATCHREGCTRL_0_LOCK_ENTRY_LOW                                              (0)
+`define DV_REG_LOCKABLESCRATCHREGCTRL_0_LOCK_ENTRY_MASK                                             (32'h1)
+`define CLP_DV_REG_LOCKABLESCRATCHREGCTRL_1                                                         (32'h1001c414)
+`define DV_REG_LOCKABLESCRATCHREGCTRL_1                                                             (32'h414)
+`define DV_REG_LOCKABLESCRATCHREGCTRL_1_LOCK_ENTRY_LOW                                              (0)
+`define DV_REG_LOCKABLESCRATCHREGCTRL_1_LOCK_ENTRY_MASK                                             (32'h1)
+`define CLP_DV_REG_LOCKABLESCRATCHREGCTRL_2                                                         (32'h1001c418)
+`define DV_REG_LOCKABLESCRATCHREGCTRL_2                                                             (32'h418)
+`define DV_REG_LOCKABLESCRATCHREGCTRL_2_LOCK_ENTRY_LOW                                              (0)
+`define DV_REG_LOCKABLESCRATCHREGCTRL_2_LOCK_ENTRY_MASK                                             (32'h1)
+`define CLP_DV_REG_LOCKABLESCRATCHREGCTRL_3                                                         (32'h1001c41c)
+`define DV_REG_LOCKABLESCRATCHREGCTRL_3                                                             (32'h41c)
+`define DV_REG_LOCKABLESCRATCHREGCTRL_3_LOCK_ENTRY_LOW                                              (0)
+`define DV_REG_LOCKABLESCRATCHREGCTRL_3_LOCK_ENTRY_MASK                                             (32'h1)
+`define CLP_DV_REG_LOCKABLESCRATCHREGCTRL_4                                                         (32'h1001c420)
+`define DV_REG_LOCKABLESCRATCHREGCTRL_4                                                             (32'h420)
+`define DV_REG_LOCKABLESCRATCHREGCTRL_4_LOCK_ENTRY_LOW                                              (0)
+`define DV_REG_LOCKABLESCRATCHREGCTRL_4_LOCK_ENTRY_MASK                                             (32'h1)
+`define CLP_DV_REG_LOCKABLESCRATCHREGCTRL_5                                                         (32'h1001c424)
+`define DV_REG_LOCKABLESCRATCHREGCTRL_5                                                             (32'h424)
+`define DV_REG_LOCKABLESCRATCHREGCTRL_5_LOCK_ENTRY_LOW                                              (0)
+`define DV_REG_LOCKABLESCRATCHREGCTRL_5_LOCK_ENTRY_MASK                                             (32'h1)
+`define CLP_DV_REG_LOCKABLESCRATCHREGCTRL_6                                                         (32'h1001c428)
+`define DV_REG_LOCKABLESCRATCHREGCTRL_6                                                             (32'h428)
+`define DV_REG_LOCKABLESCRATCHREGCTRL_6_LOCK_ENTRY_LOW                                              (0)
+`define DV_REG_LOCKABLESCRATCHREGCTRL_6_LOCK_ENTRY_MASK                                             (32'h1)
+`define CLP_DV_REG_LOCKABLESCRATCHREGCTRL_7                                                         (32'h1001c42c)
+`define DV_REG_LOCKABLESCRATCHREGCTRL_7                                                             (32'h42c)
+`define DV_REG_LOCKABLESCRATCHREGCTRL_7_LOCK_ENTRY_LOW                                              (0)
+`define DV_REG_LOCKABLESCRATCHREGCTRL_7_LOCK_ENTRY_MASK                                             (32'h1)
+`define CLP_DV_REG_LOCKABLESCRATCHREGCTRL_8                                                         (32'h1001c430)
+`define DV_REG_LOCKABLESCRATCHREGCTRL_8                                                             (32'h430)
+`define DV_REG_LOCKABLESCRATCHREGCTRL_8_LOCK_ENTRY_LOW                                              (0)
+`define DV_REG_LOCKABLESCRATCHREGCTRL_8_LOCK_ENTRY_MASK                                             (32'h1)
+`define CLP_DV_REG_LOCKABLESCRATCHREGCTRL_9                                                         (32'h1001c434)
+`define DV_REG_LOCKABLESCRATCHREGCTRL_9                                                             (32'h434)
+`define DV_REG_LOCKABLESCRATCHREGCTRL_9_LOCK_ENTRY_LOW                                              (0)
+`define DV_REG_LOCKABLESCRATCHREGCTRL_9_LOCK_ENTRY_MASK                                             (32'h1)
+`define CLP_DV_REG_LOCKABLESCRATCHREG_0                                                             (32'h1001c438)
+`define DV_REG_LOCKABLESCRATCHREG_0                                                                 (32'h438)
+`define CLP_DV_REG_LOCKABLESCRATCHREG_1                                                             (32'h1001c43c)
+`define DV_REG_LOCKABLESCRATCHREG_1                                                                 (32'h43c)
+`define CLP_DV_REG_LOCKABLESCRATCHREG_2                                                             (32'h1001c440)
+`define DV_REG_LOCKABLESCRATCHREG_2                                                                 (32'h440)
+`define CLP_DV_REG_LOCKABLESCRATCHREG_3                                                             (32'h1001c444)
+`define DV_REG_LOCKABLESCRATCHREG_3                                                                 (32'h444)
+`define CLP_DV_REG_LOCKABLESCRATCHREG_4                                                             (32'h1001c448)
+`define DV_REG_LOCKABLESCRATCHREG_4                                                                 (32'h448)
+`define CLP_DV_REG_LOCKABLESCRATCHREG_5                                                             (32'h1001c44c)
+`define DV_REG_LOCKABLESCRATCHREG_5                                                                 (32'h44c)
+`define CLP_DV_REG_LOCKABLESCRATCHREG_6                                                             (32'h1001c450)
+`define DV_REG_LOCKABLESCRATCHREG_6                                                                 (32'h450)
+`define CLP_DV_REG_LOCKABLESCRATCHREG_7                                                             (32'h1001c454)
+`define DV_REG_LOCKABLESCRATCHREG_7                                                                 (32'h454)
+`define CLP_DV_REG_LOCKABLESCRATCHREG_8                                                             (32'h1001c458)
+`define DV_REG_LOCKABLESCRATCHREG_8                                                                 (32'h458)
+`define CLP_DV_REG_LOCKABLESCRATCHREG_9                                                             (32'h1001c45c)
+`define DV_REG_LOCKABLESCRATCHREG_9                                                                 (32'h45c)
 `define CLP_DV_REG_NONSTICKYGENERICSCRATCHREG_0                                                     (32'h1001c460)
 `define DV_REG_NONSTICKYGENERICSCRATCHREG_0                                                         (32'h460)
 `define CLP_DV_REG_NONSTICKYGENERICSCRATCHREG_1                                                     (32'h1001c464)
@@ -4053,42 +4053,56 @@
 `define SHA512_REG_SHA512_KV_WR_STATUS_VALID_MASK                                                   (32'h2)
 `define SHA512_REG_SHA512_KV_WR_STATUS_ERROR_LOW                                                    (2)
 `define SHA512_REG_SHA512_KV_WR_STATUS_ERROR_MASK                                                   (32'h3fc)
-`define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_NONCE                                                    (32'h10020610)
-`define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE                                                        (32'h610)
-`define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_CTRL                                                     (32'h10020614)
-`define SHA512_REG_SHA512_GEN_PCR_HASH_CTRL                                                         (32'h614)
+`define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_0                                                  (32'h10020610)
+`define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_0                                                      (32'h610)
+`define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_1                                                  (32'h10020614)
+`define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_1                                                      (32'h614)
+`define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_2                                                  (32'h10020618)
+`define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_2                                                      (32'h618)
+`define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_3                                                  (32'h1002061c)
+`define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_3                                                      (32'h61c)
+`define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_4                                                  (32'h10020620)
+`define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_4                                                      (32'h620)
+`define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_5                                                  (32'h10020624)
+`define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_5                                                      (32'h624)
+`define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_6                                                  (32'h10020628)
+`define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_6                                                      (32'h628)
+`define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_7                                                  (32'h1002062c)
+`define SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_7                                                      (32'h62c)
+`define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_CTRL                                                     (32'h10020630)
+`define SHA512_REG_SHA512_GEN_PCR_HASH_CTRL                                                         (32'h630)
 `define SHA512_REG_SHA512_GEN_PCR_HASH_CTRL_START_LOW                                               (0)
 `define SHA512_REG_SHA512_GEN_PCR_HASH_CTRL_START_MASK                                              (32'h1)
-`define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_STATUS                                                   (32'h10020618)
-`define SHA512_REG_SHA512_GEN_PCR_HASH_STATUS                                                       (32'h618)
+`define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_STATUS                                                   (32'h10020634)
+`define SHA512_REG_SHA512_GEN_PCR_HASH_STATUS                                                       (32'h634)
 `define SHA512_REG_SHA512_GEN_PCR_HASH_STATUS_READY_LOW                                             (0)
 `define SHA512_REG_SHA512_GEN_PCR_HASH_STATUS_READY_MASK                                            (32'h1)
 `define SHA512_REG_SHA512_GEN_PCR_HASH_STATUS_VALID_LOW                                             (1)
 `define SHA512_REG_SHA512_GEN_PCR_HASH_STATUS_VALID_MASK                                            (32'h2)
-`define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_0                                                 (32'h1002061c)
-`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_0                                                     (32'h61c)
-`define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_1                                                 (32'h10020620)
-`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_1                                                     (32'h620)
-`define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_2                                                 (32'h10020624)
-`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_2                                                     (32'h624)
-`define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_3                                                 (32'h10020628)
-`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_3                                                     (32'h628)
-`define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_4                                                 (32'h1002062c)
-`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_4                                                     (32'h62c)
-`define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_5                                                 (32'h10020630)
-`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_5                                                     (32'h630)
-`define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_6                                                 (32'h10020634)
-`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_6                                                     (32'h634)
-`define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_7                                                 (32'h10020638)
-`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_7                                                     (32'h638)
-`define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_8                                                 (32'h1002063c)
-`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_8                                                     (32'h63c)
-`define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_9                                                 (32'h10020640)
-`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_9                                                     (32'h640)
-`define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_10                                                (32'h10020644)
-`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_10                                                    (32'h644)
-`define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_11                                                (32'h10020648)
-`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_11                                                    (32'h648)
+`define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_0                                                 (32'h10020638)
+`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_0                                                     (32'h638)
+`define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_1                                                 (32'h1002063c)
+`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_1                                                     (32'h63c)
+`define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_2                                                 (32'h10020640)
+`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_2                                                     (32'h640)
+`define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_3                                                 (32'h10020644)
+`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_3                                                     (32'h644)
+`define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_4                                                 (32'h10020648)
+`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_4                                                     (32'h648)
+`define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_5                                                 (32'h1002064c)
+`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_5                                                     (32'h64c)
+`define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_6                                                 (32'h10020650)
+`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_6                                                     (32'h650)
+`define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_7                                                 (32'h10020654)
+`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_7                                                     (32'h654)
+`define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_8                                                 (32'h10020658)
+`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_8                                                     (32'h658)
+`define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_9                                                 (32'h1002065c)
+`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_9                                                     (32'h65c)
+`define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_10                                                (32'h10020660)
+`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_10                                                    (32'h660)
+`define CLP_SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_11                                                (32'h10020664)
+`define SHA512_REG_SHA512_GEN_PCR_HASH_DIGEST_11                                                    (32'h664)
 `define CLP_SHA512_REG_INTR_BLOCK_RF_START                                                          (32'h10020800)
 `define CLP_SHA512_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R                                               (32'h10020800)
 `define SHA512_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R                                                   (32'h800)
@@ -5169,6 +5183,8 @@
 `define MBOX_CSR_MBOX_STATUS_MBOX_FSM_PS_MASK                                                       (32'h1c0)
 `define MBOX_CSR_MBOX_STATUS_SOC_HAS_LOCK_LOW                                                       (9)
 `define MBOX_CSR_MBOX_STATUS_SOC_HAS_LOCK_MASK                                                      (32'h200)
+`define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_LOW                                                         (10)
+`define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_MASK                                                        (32'h1fffc00)
 `define CLP_MBOX_CSR_MBOX_UNLOCK                                                                    (32'h30020020)
 `define MBOX_CSR_MBOX_UNLOCK                                                                        (32'h20)
 `define MBOX_CSR_MBOX_UNLOCK_UNLOCK_LOW                                                             (0)
@@ -5200,6 +5216,8 @@
 `define SHA512_ACC_CSR_STATUS                                                                       (32'h1c)
 `define SHA512_ACC_CSR_STATUS_VALID_LOW                                                             (0)
 `define SHA512_ACC_CSR_STATUS_VALID_MASK                                                            (32'h1)
+`define SHA512_ACC_CSR_STATUS_SOC_HAS_LOCK_LOW                                                      (1)
+`define SHA512_ACC_CSR_STATUS_SOC_HAS_LOCK_MASK                                                     (32'h2)
 `define CLP_SHA512_ACC_CSR_DIGEST_0                                                                 (32'h30021020)
 `define SHA512_ACC_CSR_DIGEST_0                                                                     (32'h20)
 `define CLP_SHA512_ACC_CSR_DIGEST_1                                                                 (32'h30021024)
@@ -5326,8 +5344,20 @@
 `define CLP_SOC_IFC_REG_BASE_ADDR                                                                   (32'h30030000)
 `define CLP_SOC_IFC_REG_CPTRA_HW_ERROR_FATAL                                                        (32'h30030000)
 `define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL                                                            (32'h0)
+`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_ICCM_ECC_UNC_LOW                                           (0)
+`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_ICCM_ECC_UNC_MASK                                          (32'h1)
+`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_DCCM_ECC_UNC_LOW                                           (1)
+`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_DCCM_ECC_UNC_MASK                                          (32'h2)
+`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_NMI_PIN_LOW                                                (2)
+`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_NMI_PIN_MASK                                               (32'h4)
 `define CLP_SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL                                                    (32'h30030004)
 `define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL                                                        (32'h4)
+`define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_NO_LOCK_LOW                                  (0)
+`define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_NO_LOCK_MASK                                 (32'h1)
+`define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_OOO_LOW                                      (1)
+`define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_OOO_MASK                                     (32'h2)
+`define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_ECC_UNC_LOW                                       (2)
+`define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_ECC_UNC_MASK                                      (32'h4)
 `define CLP_SOC_IFC_REG_CPTRA_FW_ERROR_FATAL                                                        (32'h30030008)
 `define SOC_IFC_REG_CPTRA_FW_ERROR_FATAL                                                            (32'h8)
 `define CLP_SOC_IFC_REG_CPTRA_FW_ERROR_NON_FATAL                                                    (32'h3003000c)
@@ -5357,7 +5387,11 @@
 `define CLP_SOC_IFC_REG_CPTRA_FLOW_STATUS                                                           (32'h3003003c)
 `define SOC_IFC_REG_CPTRA_FLOW_STATUS                                                               (32'h3c)
 `define SOC_IFC_REG_CPTRA_FLOW_STATUS_STATUS_LOW                                                    (0)
-`define SOC_IFC_REG_CPTRA_FLOW_STATUS_STATUS_MASK                                                   (32'hfffffff)
+`define SOC_IFC_REG_CPTRA_FLOW_STATUS_STATUS_MASK                                                   (32'hffffff)
+`define SOC_IFC_REG_CPTRA_FLOW_STATUS_IDEVID_CSR_READY_LOW                                          (24)
+`define SOC_IFC_REG_CPTRA_FLOW_STATUS_IDEVID_CSR_READY_MASK                                         (32'h1000000)
+`define SOC_IFC_REG_CPTRA_FLOW_STATUS_BOOT_FSM_PS_LOW                                               (25)
+`define SOC_IFC_REG_CPTRA_FLOW_STATUS_BOOT_FSM_PS_MASK                                              (32'he000000)
 `define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_LOW                                              (28)
 `define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_MASK                                             (32'h10000000)
 `define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_RUNTIME_LOW                                         (29)
@@ -5442,44 +5476,52 @@
 `define SOC_IFC_REG_CPTRA_TRNG_DATA_10                                                              (32'ha0)
 `define CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_11                                                          (32'h300300a4)
 `define SOC_IFC_REG_CPTRA_TRNG_DATA_11                                                              (32'ha4)
-`define CLP_SOC_IFC_REG_CPTRA_TRNG_STATUS                                                           (32'h300300a8)
-`define SOC_IFC_REG_CPTRA_TRNG_STATUS                                                               (32'ha8)
+`define CLP_SOC_IFC_REG_CPTRA_TRNG_CTRL                                                             (32'h300300a8)
+`define SOC_IFC_REG_CPTRA_TRNG_CTRL                                                                 (32'ha8)
+`define SOC_IFC_REG_CPTRA_TRNG_CTRL_CLEAR_LOW                                                       (0)
+`define SOC_IFC_REG_CPTRA_TRNG_CTRL_CLEAR_MASK                                                      (32'h1)
+`define CLP_SOC_IFC_REG_CPTRA_TRNG_STATUS                                                           (32'h300300ac)
+`define SOC_IFC_REG_CPTRA_TRNG_STATUS                                                               (32'hac)
 `define SOC_IFC_REG_CPTRA_TRNG_STATUS_DATA_REQ_LOW                                                  (0)
 `define SOC_IFC_REG_CPTRA_TRNG_STATUS_DATA_REQ_MASK                                                 (32'h1)
 `define SOC_IFC_REG_CPTRA_TRNG_STATUS_DATA_WR_DONE_LOW                                              (1)
 `define SOC_IFC_REG_CPTRA_TRNG_STATUS_DATA_WR_DONE_MASK                                             (32'h2)
-`define CLP_SOC_IFC_REG_CPTRA_FUSE_WR_DONE                                                          (32'h300300ac)
-`define SOC_IFC_REG_CPTRA_FUSE_WR_DONE                                                              (32'hac)
+`define CLP_SOC_IFC_REG_CPTRA_FUSE_WR_DONE                                                          (32'h300300b0)
+`define SOC_IFC_REG_CPTRA_FUSE_WR_DONE                                                              (32'hb0)
 `define SOC_IFC_REG_CPTRA_FUSE_WR_DONE_DONE_LOW                                                     (0)
 `define SOC_IFC_REG_CPTRA_FUSE_WR_DONE_DONE_MASK                                                    (32'h1)
-`define CLP_SOC_IFC_REG_CPTRA_TIMER_CONFIG                                                          (32'h300300b0)
-`define SOC_IFC_REG_CPTRA_TIMER_CONFIG                                                              (32'hb0)
-`define CLP_SOC_IFC_REG_CPTRA_BOOTFSM_GO                                                            (32'h300300b4)
-`define SOC_IFC_REG_CPTRA_BOOTFSM_GO                                                                (32'hb4)
+`define CLP_SOC_IFC_REG_CPTRA_TIMER_CONFIG                                                          (32'h300300b4)
+`define SOC_IFC_REG_CPTRA_TIMER_CONFIG                                                              (32'hb4)
+`define CLP_SOC_IFC_REG_CPTRA_BOOTFSM_GO                                                            (32'h300300b8)
+`define SOC_IFC_REG_CPTRA_BOOTFSM_GO                                                                (32'hb8)
 `define SOC_IFC_REG_CPTRA_BOOTFSM_GO_GO_LOW                                                         (0)
 `define SOC_IFC_REG_CPTRA_BOOTFSM_GO_GO_MASK                                                        (32'h1)
-`define CLP_SOC_IFC_REG_CPTRA_DBG_MANUF_SERVICE_REG                                                 (32'h300300b8)
-`define SOC_IFC_REG_CPTRA_DBG_MANUF_SERVICE_REG                                                     (32'hb8)
-`define CLP_SOC_IFC_REG_CPTRA_CLK_GATING_EN                                                         (32'h300300bc)
-`define SOC_IFC_REG_CPTRA_CLK_GATING_EN                                                             (32'hbc)
+`define CLP_SOC_IFC_REG_CPTRA_DBG_MANUF_SERVICE_REG                                                 (32'h300300bc)
+`define SOC_IFC_REG_CPTRA_DBG_MANUF_SERVICE_REG                                                     (32'hbc)
+`define CLP_SOC_IFC_REG_CPTRA_CLK_GATING_EN                                                         (32'h300300c0)
+`define SOC_IFC_REG_CPTRA_CLK_GATING_EN                                                             (32'hc0)
 `define SOC_IFC_REG_CPTRA_CLK_GATING_EN_CLK_GATING_EN_LOW                                           (0)
 `define SOC_IFC_REG_CPTRA_CLK_GATING_EN_CLK_GATING_EN_MASK                                          (32'h1)
-`define CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0                                                 (32'h300300c0)
-`define SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0                                                     (32'hc0)
-`define CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_1                                                 (32'h300300c4)
-`define SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_1                                                     (32'hc4)
-`define CLP_SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_0                                                (32'h300300c8)
-`define SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_0                                                    (32'hc8)
-`define CLP_SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_1                                                (32'h300300cc)
-`define SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_1                                                    (32'hcc)
-`define CLP_SOC_IFC_REG_CPTRA_HW_REV_ID                                                             (32'h300300d0)
-`define SOC_IFC_REG_CPTRA_HW_REV_ID                                                                 (32'hd0)
-`define CLP_SOC_IFC_REG_CPTRA_FW_REV_ID_0                                                           (32'h300300d4)
-`define SOC_IFC_REG_CPTRA_FW_REV_ID_0                                                               (32'hd4)
-`define CLP_SOC_IFC_REG_CPTRA_FW_REV_ID_1                                                           (32'h300300d8)
-`define SOC_IFC_REG_CPTRA_FW_REV_ID_1                                                               (32'hd8)
-`define CLP_SOC_IFC_REG_CPTRA_HW_CONFIG                                                             (32'h300300dc)
-`define SOC_IFC_REG_CPTRA_HW_CONFIG                                                                 (32'hdc)
+`define CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0                                                 (32'h300300c4)
+`define SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0                                                     (32'hc4)
+`define CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_1                                                 (32'h300300c8)
+`define SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_1                                                     (32'hc8)
+`define CLP_SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_0                                                (32'h300300cc)
+`define SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_0                                                    (32'hcc)
+`define CLP_SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_1                                                (32'h300300d0)
+`define SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_1                                                    (32'hd0)
+`define CLP_SOC_IFC_REG_CPTRA_HW_REV_ID                                                             (32'h300300d4)
+`define SOC_IFC_REG_CPTRA_HW_REV_ID                                                                 (32'hd4)
+`define SOC_IFC_REG_CPTRA_HW_REV_ID_CPTRA_GENERATION_LOW                                            (0)
+`define SOC_IFC_REG_CPTRA_HW_REV_ID_CPTRA_GENERATION_MASK                                           (32'hffff)
+`define SOC_IFC_REG_CPTRA_HW_REV_ID_SOC_STEPPING_ID_LOW                                             (16)
+`define SOC_IFC_REG_CPTRA_HW_REV_ID_SOC_STEPPING_ID_MASK                                            (32'hffff0000)
+`define CLP_SOC_IFC_REG_CPTRA_FW_REV_ID_0                                                           (32'h300300d8)
+`define SOC_IFC_REG_CPTRA_FW_REV_ID_0                                                               (32'hd8)
+`define CLP_SOC_IFC_REG_CPTRA_FW_REV_ID_1                                                           (32'h300300dc)
+`define SOC_IFC_REG_CPTRA_FW_REV_ID_1                                                               (32'hdc)
+`define CLP_SOC_IFC_REG_CPTRA_HW_CONFIG                                                             (32'h300300e0)
+`define SOC_IFC_REG_CPTRA_HW_CONFIG                                                                 (32'he0)
 `define SOC_IFC_REG_CPTRA_HW_CONFIG_ITRNG_EN_LOW                                                    (0)
 `define SOC_IFC_REG_CPTRA_HW_CONFIG_ITRNG_EN_MASK                                                   (32'h1)
 `define SOC_IFC_REG_CPTRA_HW_CONFIG_QSPI_EN_LOW                                                     (1)
@@ -5488,36 +5530,62 @@
 `define SOC_IFC_REG_CPTRA_HW_CONFIG_I3C_EN_MASK                                                     (32'h4)
 `define SOC_IFC_REG_CPTRA_HW_CONFIG_UART_EN_LOW                                                     (3)
 `define SOC_IFC_REG_CPTRA_HW_CONFIG_UART_EN_MASK                                                    (32'h8)
-`define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_EN                                                         (32'h300300e0)
-`define SOC_IFC_REG_CPTRA_WDT_TIMER1_EN                                                             (32'he0)
+`define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_EN                                                         (32'h300300e4)
+`define SOC_IFC_REG_CPTRA_WDT_TIMER1_EN                                                             (32'he4)
 `define SOC_IFC_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_LOW                                               (0)
 `define SOC_IFC_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_MASK                                              (32'h1)
-`define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL                                                       (32'h300300e4)
-`define SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL                                                           (32'he4)
+`define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL                                                       (32'h300300e8)
+`define SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL                                                           (32'he8)
 `define SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART_LOW                                        (0)
 `define SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART_MASK                                       (32'h1)
-`define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0                                           (32'h300300e8)
-`define SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0                                               (32'he8)
-`define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1                                           (32'h300300ec)
-`define SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1                                               (32'hec)
-`define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_EN                                                         (32'h300300f0)
-`define SOC_IFC_REG_CPTRA_WDT_TIMER2_EN                                                             (32'hf0)
+`define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0                                           (32'h300300ec)
+`define SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0                                               (32'hec)
+`define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1                                           (32'h300300f0)
+`define SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1                                               (32'hf0)
+`define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_EN                                                         (32'h300300f4)
+`define SOC_IFC_REG_CPTRA_WDT_TIMER2_EN                                                             (32'hf4)
 `define SOC_IFC_REG_CPTRA_WDT_TIMER2_EN_TIMER2_EN_LOW                                               (0)
 `define SOC_IFC_REG_CPTRA_WDT_TIMER2_EN_TIMER2_EN_MASK                                              (32'h1)
-`define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL                                                       (32'h300300f4)
-`define SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL                                                           (32'hf4)
+`define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL                                                       (32'h300300f8)
+`define SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL                                                           (32'hf8)
 `define SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART_LOW                                        (0)
 `define SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART_MASK                                       (32'h1)
-`define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0                                           (32'h300300f8)
-`define SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0                                               (32'hf8)
-`define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1                                           (32'h300300fc)
-`define SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1                                               (32'hfc)
-`define CLP_SOC_IFC_REG_CPTRA_WDT_STATUS                                                            (32'h30030100)
-`define SOC_IFC_REG_CPTRA_WDT_STATUS                                                                (32'h100)
+`define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0                                           (32'h300300fc)
+`define SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0                                               (32'hfc)
+`define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1                                           (32'h30030100)
+`define SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1                                               (32'h100)
+`define CLP_SOC_IFC_REG_CPTRA_WDT_STATUS                                                            (32'h30030104)
+`define SOC_IFC_REG_CPTRA_WDT_STATUS                                                                (32'h104)
 `define SOC_IFC_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_LOW                                                 (0)
 `define SOC_IFC_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_MASK                                                (32'h1)
 `define SOC_IFC_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_LOW                                                 (1)
 `define SOC_IFC_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_MASK                                                (32'h2)
+`define CLP_SOC_IFC_REG_CPTRA_FUSE_VALID_PAUSER                                                     (32'h30030108)
+`define SOC_IFC_REG_CPTRA_FUSE_VALID_PAUSER                                                         (32'h108)
+`define CLP_SOC_IFC_REG_CPTRA_FUSE_PAUSER_LOCK                                                      (32'h3003010c)
+`define SOC_IFC_REG_CPTRA_FUSE_PAUSER_LOCK                                                          (32'h10c)
+`define SOC_IFC_REG_CPTRA_FUSE_PAUSER_LOCK_LOCK_LOW                                                 (0)
+`define SOC_IFC_REG_CPTRA_FUSE_PAUSER_LOCK_LOCK_MASK                                                (32'h1)
+`define CLP_SOC_IFC_REG_CPTRA_WDT_CFG_0                                                             (32'h30030110)
+`define SOC_IFC_REG_CPTRA_WDT_CFG_0                                                                 (32'h110)
+`define CLP_SOC_IFC_REG_CPTRA_WDT_CFG_1                                                             (32'h30030114)
+`define SOC_IFC_REG_CPTRA_WDT_CFG_1                                                                 (32'h114)
+`define CLP_SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0                                                (32'h30030118)
+`define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0                                                    (32'h118)
+`define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_LOW_THRESHOLD_LOW                                  (0)
+`define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_LOW_THRESHOLD_MASK                                 (32'hffff)
+`define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_HIGH_THRESHOLD_LOW                                 (16)
+`define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_HIGH_THRESHOLD_MASK                                (32'hffff0000)
+`define CLP_SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1                                                (32'h3003011c)
+`define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1                                                    (32'h11c)
+`define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_REPETITION_COUNT_LOW                               (0)
+`define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_REPETITION_COUNT_MASK                              (32'hffff)
+`define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_RSVD_LOW                                           (16)
+`define SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_RSVD_MASK                                          (32'hffff0000)
+`define CLP_SOC_IFC_REG_CPTRA_RSVD_REG_0                                                            (32'h30030120)
+`define SOC_IFC_REG_CPTRA_RSVD_REG_0                                                                (32'h120)
+`define CLP_SOC_IFC_REG_CPTRA_RSVD_REG_1                                                            (32'h30030124)
+`define SOC_IFC_REG_CPTRA_RSVD_REG_1                                                                (32'h124)
 `define CLP_SOC_IFC_REG_FUSE_UDS_SEED_0                                                             (32'h30030200)
 `define SOC_IFC_REG_FUSE_UDS_SEED_0                                                                 (32'h200)
 `define CLP_SOC_IFC_REG_FUSE_UDS_SEED_1                                                             (32'h30030204)
@@ -5684,6 +5752,16 @@
 `define SOC_IFC_REG_FUSE_LIFE_CYCLE                                                                 (32'h33c)
 `define SOC_IFC_REG_FUSE_LIFE_CYCLE_LIFE_CYCLE_LOW                                                  (0)
 `define SOC_IFC_REG_FUSE_LIFE_CYCLE_LIFE_CYCLE_MASK                                                 (32'h3)
+`define CLP_SOC_IFC_REG_FUSE_LMS_VERIFY                                                             (32'h30030340)
+`define SOC_IFC_REG_FUSE_LMS_VERIFY                                                                 (32'h340)
+`define SOC_IFC_REG_FUSE_LMS_VERIFY_LMS_VERIFY_LOW                                                  (0)
+`define SOC_IFC_REG_FUSE_LMS_VERIFY_LMS_VERIFY_MASK                                                 (32'h1)
+`define CLP_SOC_IFC_REG_FUSE_LMS_REVOCATION                                                         (32'h30030344)
+`define SOC_IFC_REG_FUSE_LMS_REVOCATION                                                             (32'h344)
+`define CLP_SOC_IFC_REG_FUSE_SOC_STEPPING_ID                                                        (32'h30030348)
+`define SOC_IFC_REG_FUSE_SOC_STEPPING_ID                                                            (32'h348)
+`define SOC_IFC_REG_FUSE_SOC_STEPPING_ID_SOC_STEPPING_ID_LOW                                        (0)
+`define SOC_IFC_REG_FUSE_SOC_STEPPING_ID_SOC_STEPPING_ID_MASK                                       (32'hffff)
 `define CLP_SOC_IFC_REG_INTERNAL_OBF_KEY_0                                                          (32'h30030600)
 `define SOC_IFC_REG_INTERNAL_OBF_KEY_0                                                              (32'h600)
 `define CLP_SOC_IFC_REG_INTERNAL_OBF_KEY_1                                                          (32'h30030604)
@@ -5714,6 +5792,34 @@
 `define SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES_WAIT_CYCLES_MASK                           (32'hff)
 `define CLP_SOC_IFC_REG_INTERNAL_NMI_VECTOR                                                         (32'h3003062c)
 `define SOC_IFC_REG_INTERNAL_NMI_VECTOR                                                             (32'h62c)
+`define CLP_SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK                                                (32'h30030630)
+`define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK                                                    (32'h630)
+`define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_ICCM_ECC_UNC_LOW                              (0)
+`define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_ICCM_ECC_UNC_MASK                             (32'h1)
+`define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_DCCM_ECC_UNC_LOW                              (1)
+`define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_DCCM_ECC_UNC_MASK                             (32'h2)
+`define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_NMI_PIN_LOW                                   (2)
+`define SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_NMI_PIN_MASK                                  (32'h4)
+`define CLP_SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK                                            (32'h30030634)
+`define SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK                                                (32'h634)
+`define SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK_MASK_MBOX_PROT_NO_LOCK_LOW                     (0)
+`define SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK_MASK_MBOX_PROT_NO_LOCK_MASK                    (32'h1)
+`define SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK_MASK_MBOX_PROT_OOO_LOW                         (1)
+`define SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK_MASK_MBOX_PROT_OOO_MASK                        (32'h2)
+`define SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK_MASK_MBOX_ECC_UNC_LOW                          (2)
+`define SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK_MASK_MBOX_ECC_UNC_MASK                         (32'h4)
+`define CLP_SOC_IFC_REG_INTERNAL_FW_ERROR_FATAL_MASK                                                (32'h30030638)
+`define SOC_IFC_REG_INTERNAL_FW_ERROR_FATAL_MASK                                                    (32'h638)
+`define CLP_SOC_IFC_REG_INTERNAL_FW_ERROR_NON_FATAL_MASK                                            (32'h3003063c)
+`define SOC_IFC_REG_INTERNAL_FW_ERROR_NON_FATAL_MASK                                                (32'h63c)
+`define CLP_SOC_IFC_REG_INTERNAL_RV_MTIME_L                                                         (32'h30030640)
+`define SOC_IFC_REG_INTERNAL_RV_MTIME_L                                                             (32'h640)
+`define CLP_SOC_IFC_REG_INTERNAL_RV_MTIME_H                                                         (32'h30030644)
+`define SOC_IFC_REG_INTERNAL_RV_MTIME_H                                                             (32'h644)
+`define CLP_SOC_IFC_REG_INTERNAL_RV_MTIMECMP_L                                                      (32'h30030648)
+`define SOC_IFC_REG_INTERNAL_RV_MTIMECMP_L                                                          (32'h648)
+`define CLP_SOC_IFC_REG_INTERNAL_RV_MTIMECMP_H                                                      (32'h3003064c)
+`define SOC_IFC_REG_INTERNAL_RV_MTIMECMP_H                                                          (32'h64c)
 `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_START                                                         (32'h30030800)
 `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R                                              (32'h30030800)
 `define SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R                                                  (32'h800)
@@ -5747,8 +5853,12 @@
 `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_MBOX_ECC_COR_EN_MASK                        (32'h2)
 `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_DEBUG_LOCKED_EN_LOW                         (2)
 `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_DEBUG_LOCKED_EN_MASK                        (32'h4)
-`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_SOC_REQ_LOCK_EN_LOW                         (3)
-`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_SOC_REQ_LOCK_EN_MASK                        (32'h8)
+`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_SCAN_MODE_EN_LOW                            (3)
+`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_SCAN_MODE_EN_MASK                           (32'h8)
+`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_SOC_REQ_LOCK_EN_LOW                         (4)
+`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_SOC_REQ_LOCK_EN_MASK                        (32'h10)
+`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_GEN_IN_TOGGLE_EN_LOW                        (5)
+`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_GEN_IN_TOGGLE_EN_MASK                       (32'h20)
 `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R                                           (32'h3003080c)
 `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R                                               (32'h80c)
 `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_LOW                                   (0)
@@ -5783,8 +5893,12 @@
 `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK                 (32'h2)
 `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_LOW                  (2)
 `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK                 (32'h4)
-`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_LOW                  (3)
-`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK                 (32'h8)
+`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_LOW                     (3)
+`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK                    (32'h8)
+`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_LOW                  (4)
+`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK                 (32'h10)
+`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_LOW                 (5)
+`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK                (32'h20)
 `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R                                             (32'h3003081c)
 `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R                                                 (32'h81c)
 `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_INTERNAL_TRIG_LOW                         (0)
@@ -5811,8 +5925,12 @@
 `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_MBOX_ECC_COR_TRIG_MASK                    (32'h2)
 `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_DEBUG_LOCKED_TRIG_LOW                     (2)
 `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_DEBUG_LOCKED_TRIG_MASK                    (32'h4)
-`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_SOC_REQ_LOCK_TRIG_LOW                     (3)
-`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_SOC_REQ_LOCK_TRIG_MASK                    (32'h8)
+`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_SCAN_MODE_TRIG_LOW                        (3)
+`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_SCAN_MODE_TRIG_MASK                       (32'h8)
+`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_SOC_REQ_LOCK_TRIG_LOW                     (4)
+`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_SOC_REQ_LOCK_TRIG_MASK                    (32'h10)
+`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_GEN_IN_TOGGLE_TRIG_LOW                    (5)
+`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_GEN_IN_TOGGLE_TRIG_MASK                   (32'h20)
 `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_R                                   (32'h30030900)
 `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_R                                       (32'h900)
 `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INV_DEV_INTR_COUNT_R                                    (32'h30030904)
@@ -5835,8 +5953,12 @@
 `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_R                                   (32'h984)
 `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_R                               (32'h30030988)
 `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_R                                   (32'h988)
-`define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_R                               (32'h3003098c)
-`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_R                                   (32'h98c)
+`define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_R                                  (32'h3003098c)
+`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_R                                      (32'h98c)
+`define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_R                               (32'h30030990)
+`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_R                                   (32'h990)
+`define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_R                              (32'h30030994)
+`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_R                                  (32'h994)
 `define CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R                              (32'h30030a00)
 `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R                                  (32'ha00)
 `define SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R_PULSE_LOW                        (0)
@@ -5881,10 +6003,18 @@
 `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_INCR_R                              (32'ha28)
 `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_INCR_R_PULSE_LOW                    (0)
 `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_INCR_R_PULSE_MASK                   (32'h1)
-`define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R                          (32'h30030a2c)
-`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R                              (32'ha2c)
+`define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_INCR_R                             (32'h30030a2c)
+`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_INCR_R                                 (32'ha2c)
+`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_INCR_R_PULSE_LOW                       (0)
+`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_INCR_R_PULSE_MASK                      (32'h1)
+`define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R                          (32'h30030a30)
+`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R                              (32'ha30)
 `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R_PULSE_LOW                    (0)
 `define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R_PULSE_MASK                   (32'h1)
+`define CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_INCR_R                         (32'h30030a34)
+`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_INCR_R                             (32'ha34)
+`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_INCR_R_PULSE_LOW                   (0)
+`define SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_INCR_R_PULSE_MASK                  (32'h1)
 
 
 `endif
\ No newline at end of file
diff --git a/src/integration/rtl/caliptra_top.sv b/src/integration/rtl/caliptra_top.sv
index 1dcd23645..3937626d9 100755
--- a/src/integration/rtl/caliptra_top.sv
+++ b/src/integration/rtl/caliptra_top.sv
@@ -56,7 +56,9 @@ module caliptra_top
     //QSPI Interface
     output logic                                qspi_clk_o,
     output logic [`CALIPTRA_QSPI_CS_WIDTH-1:0]  qspi_cs_no,
-    inout  wire  [`CALIPTRA_QSPI_IO_WIDTH-1:0]  qspi_d_io,
+    input  wire  [`CALIPTRA_QSPI_IO_WIDTH-1:0]  qspi_d_i,
+    output logic [`CALIPTRA_QSPI_IO_WIDTH-1:0]  qspi_d_o,
+    output logic [`CALIPTRA_QSPI_IO_WIDTH-1:0]  qspi_d_en_o,
 
     //UART Interface
     // TODO: Determine if this should be set behind a ifdef
@@ -69,7 +71,7 @@ module caliptra_top
     //TODO update with I3C interface signals
 
     // Caliptra Memory Export Interface
-    el2_mem_if                         el2_mem_export,
+    el2_mem_if.veer_sram_src           el2_mem_export,
 
     //SRAM interface for mbox
     output logic mbox_sram_cs,
@@ -121,8 +123,11 @@ module caliptra_top
 
     //clock gating signals
     logic                       clk_gating_en   ;
+    logic                       rdc_clk_dis     ;
     logic                       clk_cg          ;
     logic                       soc_ifc_clk_cg  ;
+    logic                       rdc_clk_cg      ;
+    logic                       uc_clk_cg       ;
 
     logic        [31:0]         ic_haddr        ;
     logic        [2:0]          ic_hburst       ;
@@ -184,7 +189,15 @@ module caliptra_top
     logic [6:0]                 cptra_uncore_dmi_reg_addr;
     logic [31:0]                cptra_uncore_dmi_reg_wdata;
     security_state_t            cptra_security_state_Latched;
+    security_state_t            cptra_security_state_Latched_d;
+    security_state_t            cptra_security_state_Latched_f;
+    logic                       cptra_dmi_reg_en_preQ;
     
+    logic                       fw_update_rst_window;
+
+    // Caliptra ECC status signals
+    rv_ecc_sts_t rv_ecc_sts;
+
 
     logic iccm_lock;
 
@@ -233,10 +246,11 @@ module caliptra_top
     logic clear_obf_secrets;
     logic clear_secrets;
     
-    logic cptra_security_state_captured, scan_mode_f, scan_mode_switch;
-    logic debugUnlock_or_scan_mode_switch, clear_obf_secrets_debugScanQ, cptra_scan_mode_Latched, debug_lock_to_unlock_switch;
-    var security_state_t security_state_f;
-    
+    logic cptra_security_state_captured;
+    logic scan_mode_switch;
+    logic debug_lock_or_scan_mode_switch, clear_obf_secrets_debugScanQ, debug_lock_switch;
+    logic cptra_scan_mode_Latched, cptra_scan_mode_Latched_d, cptra_scan_mode_Latched_f;
+
     logic [TOTAL_OBF_KEY_BITS-1:0]        cptra_obf_key_dbg;
     logic [`CLP_OBF_FE_DWORDS-1 :0][31:0] obf_field_entropy_dbg;
     logic [`CLP_OBF_UDS_DWORDS-1:0][31:0] obf_uds_seed_dbg;
@@ -276,6 +290,17 @@ end
     //========================================================================
     // AHB Master ports
     //========================================================================
+    CALIPTRA_AHB_LITE_BUS_INF #(
+        .AHB_LITE_ADDR_WIDTH(`CALIPTRA_AHB_HADDR_SIZE),
+        .AHB_LITE_DATA_WIDTH(`CALIPTRA_AHB_HDATA_SIZE)
+    )
+    sb_ahb();
+    CALIPTRA_AHB_LITE_BUS_INF #(
+        .AHB_LITE_ADDR_WIDTH(`CALIPTRA_AHB_HADDR_SIZE),
+        .AHB_LITE_DATA_WIDTH(`CALIPTRA_AHB_HDATA_SIZE)
+    )
+    lsu_ahb();
+
     CALIPTRA_AHB_LITE_BUS_INF #(
         .AHB_LITE_ADDR_WIDTH(`CALIPTRA_AHB_HADDR_SIZE),
         .AHB_LITE_DATA_WIDTH(`CALIPTRA_AHB_HDATA_SIZE)
@@ -299,6 +324,7 @@ end
     ahb_lite_bus_i (
         .hclk                          ( clk_cg                      ),
         .hreset_n                      ( cptra_noncore_rst_b         ),
+        .force_bus_idle                ( fw_update_rst_window        ),
         .ahb_lite_responders           ( responder_inst              ),
         .ahb_lite_initiator            ( initiator_inst              ),
         .ahb_lite_resp_disable_i       ( ahb_lite_resp_disable       ),
@@ -340,7 +366,6 @@ assign jtag_id[27:12] = '0;
 assign jtag_id[11:1]  = 11'h45;
 assign reset_vector = `RV_RESET_VEC;
 assign soft_int     = 1'b0;
-assign timer_int    = 1'b0;
 
 assign kv_error_intr = 1'b0; // TODO
 assign kv_notif_intr = 1'b0; // TODO
@@ -380,9 +405,13 @@ always_comb begin
 end
 
 el2_veer_wrapper rvtop (
+`ifdef CALIPTRA_FORCE_CPU_RESET
+    .rst_l                  ( 1'b0 ),
+`else
     .rst_l                  ( cptra_uc_rst_b),
+`endif
     .dbg_rst_l              ( cptra_pwrgood), 
-    .clk                    ( clk      ),
+    .clk                    ( uc_clk_cg    ),
     .rst_vec                ( reset_vector[31:1]),
     .nmi_int                ( nmi_int       ),
     .nmi_vec                ( nmi_vector[31:1]),
@@ -403,34 +432,34 @@ el2_veer_wrapper rvtop (
     //---------------------------------------------------------------
     // Debug AHB Master
     //---------------------------------------------------------------
-    .sb_haddr               (),
-    .sb_hburst              (),
-    .sb_hmastlock           (),
-    .sb_hprot               (),
-    .sb_hsize               (),
-    .sb_htrans              (),
-    .sb_hwrite              (),
-    .sb_hwdata              (),
-
-    .sb_hrdata              ('0),
-    .sb_hready              ('0),
-    .sb_hresp               ('0),
+    .sb_haddr               ( sb_ahb.haddr   ),
+    .sb_hburst              (                ),
+    .sb_hmastlock           (                ),
+    .sb_hprot               (                ),
+    .sb_hsize               ( sb_ahb.hsize   ),
+    .sb_htrans              ( sb_ahb.htrans  ),
+    .sb_hwrite              ( sb_ahb.hwrite  ),
+    .sb_hwdata              ( sb_ahb.hwdata  ),
+
+    .sb_hrdata              ( sb_ahb.hrdata  ),
+    .sb_hready              ( sb_ahb.hready  ),
+    .sb_hresp               ( sb_ahb.hresp   ),
 
     //---------------------------------------------------------------
     // LSU AHB Master
     //---------------------------------------------------------------
-    .lsu_haddr              ( initiator_inst.haddr       ),
-    .lsu_hburst             (                       ),
-    .lsu_hmastlock          (                       ),
-    .lsu_hprot              (                       ),
-    .lsu_hsize              ( initiator_inst.hsize       ),
-    .lsu_htrans             ( initiator_inst.htrans      ),
-    .lsu_hwrite             ( initiator_inst.hwrite      ),
-    .lsu_hwdata             ( initiator_inst.hwdata      ),
-
-    .lsu_hrdata             ( initiator_inst.hrdata[63:0]),
-    .lsu_hready             ( initiator_inst.hready      ),
-    .lsu_hresp              ( initiator_inst.hresp       ),
+    .lsu_haddr              ( lsu_ahb.haddr  ),
+    .lsu_hburst             (                ),
+    .lsu_hmastlock          (                ),
+    .lsu_hprot              (                ),
+    .lsu_hsize              ( lsu_ahb.hsize  ),
+    .lsu_htrans             ( lsu_ahb.htrans ),
+    .lsu_hwrite             ( lsu_ahb.hwrite ),
+    .lsu_hwdata             ( lsu_ahb.hwdata ),
+
+    .lsu_hrdata             ( lsu_ahb.hrdata ),
+    .lsu_hready             ( lsu_ahb.hready ),
+    .lsu_hresp              ( lsu_ahb.hresp  ),
 
     //---------------------------------------------------------------
     // DMA Slave
@@ -479,6 +508,7 @@ el2_veer_wrapper rvtop (
    .cptra_uncore_dmi_reg_addr    ( cptra_uncore_dmi_reg_addr ),
    .cptra_uncore_dmi_reg_wdata   ( cptra_uncore_dmi_reg_wdata ),
    .cptra_security_state_Latched ( cptra_security_state_Latched),
+   .cptra_dmi_reg_en_preQ        ( cptra_dmi_reg_en_preQ ),
 
     .mpc_debug_halt_ack     ( mpc_debug_halt_ack),
     .mpc_debug_halt_req     ( 1'b0),
@@ -502,6 +532,12 @@ el2_veer_wrapper rvtop (
     // Caliptra Memory Export Interface
     .el2_mem_export         (el2_mem_export),
 
+    // Caliptra ECC status signals
+    .cptra_iccm_ecc_single_error(rv_ecc_sts.cptra_iccm_ecc_single_error),
+    .cptra_iccm_ecc_double_error(rv_ecc_sts.cptra_iccm_ecc_double_error),
+    .cptra_dccm_ecc_single_error(rv_ecc_sts.cptra_dccm_ecc_single_error),
+    .cptra_dccm_ecc_double_error(rv_ecc_sts.cptra_dccm_ecc_double_error),
+
     .soft_int               (soft_int),
     .core_id                ('0),
     .scan_mode              ( cptra_scan_mode_Latched ), // To enable scan mode
@@ -513,38 +549,96 @@ el2_veer_wrapper rvtop (
     always_comb responder_inst[`CALIPTRA_SLAVE_SEL_IDMA].hresp     = responder_inst[`CALIPTRA_SLAVE_SEL_DDMA].hresp;
     always_comb responder_inst[`CALIPTRA_SLAVE_SEL_IDMA].hreadyout = responder_inst[`CALIPTRA_SLAVE_SEL_DDMA].hreadyout;
 
+    // SB and LSU AHB master mux
+    ahb_lite_2to1_mux #(
+        .AHB_LITE_ADDR_WIDTH (`CALIPTRA_AHB_HADDR_SIZE),
+        .AHB_LITE_DATA_WIDTH (`CALIPTRA_AHB_HDATA_SIZE),
+        .AHB_NO_OPT(1) //Prevent address and data phase overlap between initiators
+    ) u_sb_lsu_ahb_mux (
+        .hclk                (clk_cg),
+        .hreset_n            (cptra_noncore_rst_b),
+        .force_bus_idle      (fw_update_rst_window),
+        // Initiator 0
+        .hsel_i_0            (1'b1          ),
+        .haddr_i_0           (lsu_ahb.haddr ),
+        .hwdata_i_0          (lsu_ahb.hwdata),
+        .hwrite_i_0          (lsu_ahb.hwrite),
+        .htrans_i_0          (lsu_ahb.htrans),
+        .hsize_i_0           (lsu_ahb.hsize ),
+        .hready_i_0          (1'b1          ),
+        .hresp_o_0           (lsu_ahb.hresp ),
+        .hready_o_0          (lsu_ahb.hready),
+        .hrdata_o_0          (lsu_ahb.hrdata),
+
+        // Initiator 1
+        .hsel_i_1            (1'b1          ),
+        .haddr_i_1           (sb_ahb.haddr  ),
+        .hwdata_i_1          (sb_ahb.hwdata ),
+        .hwrite_i_1          (sb_ahb.hwrite ),
+        .htrans_i_1          (sb_ahb.htrans ),
+        .hsize_i_1           (sb_ahb.hsize  ),
+        .hready_i_1          (1'b1          ),
+        .hresp_o_1           (sb_ahb.hresp  ),
+        .hready_o_1          (sb_ahb.hready ),
+        .hrdata_o_1          (sb_ahb.hrdata ),
+
+        // Responder
+        .hsel_o              (initiator_inst.hsel  ),
+        .haddr_o             (initiator_inst.haddr ),
+        .hwdata_o            (initiator_inst.hwdata),
+        .hwrite_o            (initiator_inst.hwrite),
+        .htrans_o            (initiator_inst.htrans),
+        .hsize_o             (initiator_inst.hsize ),
+        .hready_o            (initiator_inst.hready),
+        .hresp_i             (initiator_inst.hresp ),
+        .hreadyout_i         (initiator_inst.hreadyout),
+        .hrdata_i            (initiator_inst.hrdata)
+    );
+
     // Security State value captured on a Caliptra reset deassertion (0->1 signal transition)
-    always_ff @(posedge clk or negedge cptra_rst_b) begin
-        if (~cptra_rst_b) begin
-            cptra_security_state_Latched <= '{device_lifecycle: DEVICE_PRODUCTION, debug_locked: 1'b1}; //Setting the default value to be debug locked and in production mode
-            security_state_f <= '{device_lifecycle: DEVICE_PRODUCTION, debug_locked: 1'b1}; //Setting the default value to be debug locked and in production mode
+    always_ff @(posedge clk or negedge cptra_noncore_rst_b) begin
+        if (~cptra_noncore_rst_b) begin
+            cptra_security_state_Latched_d <= '{device_lifecycle: DEVICE_PRODUCTION, debug_locked: 1'b1}; //Setting the default value to be debug locked and in production mode
+            cptra_security_state_Latched_f <= '{device_lifecycle: DEVICE_PRODUCTION, debug_locked: 1'b1};
+
             cptra_security_state_captured <= 0;
-            scan_mode_f <= 0;
         end
         else if(!cptra_security_state_captured) begin
-            cptra_security_state_Latched <= security_state;
-            cptra_scan_mode_Latched <= scan_mode;
+            cptra_security_state_Latched_d <= security_state;
             cptra_security_state_captured <= 1;
         end
         else begin
-            // Latched State is different than flopped value of security state
-            // Latched State is used if we want to open the JTAG and is
-            // determined to do so only at reset exit time
-            // Asset flushing happens 'anytime' switch happens for safe side
-            //security_state_f  <= security_state;
-            security_state_f  <= security_state;
-            scan_mode_f  <= scan_mode;
+            cptra_security_state_Latched_f <= cptra_security_state_Latched_d;
+        end
+    end
+
+    always_ff @(posedge clk or negedge cptra_pwrgood) begin
+        if (~cptra_pwrgood) begin
+            cptra_scan_mode_Latched_d <= '0;
+            cptra_scan_mode_Latched_f <= '0;
+        end
+        else begin
+            cptra_scan_mode_Latched_d <= scan_mode;
+            cptra_scan_mode_Latched_f <= cptra_scan_mode_Latched_d;
         end
     end
 
+    //Lock debug unless both flops are unlocked
+    assign cptra_security_state_Latched.debug_locked = cptra_security_state_Latched_d.debug_locked | cptra_security_state_Latched_f.debug_locked;
+    //Pass on the latched value of device lifecycle
+    assign cptra_security_state_Latched.device_lifecycle = cptra_security_state_Latched_d.device_lifecycle;
+    //Only assert scan mode once both flops have set
+    assign cptra_scan_mode_Latched = cptra_scan_mode_Latched_d & cptra_scan_mode_Latched_f;
+    
     // When scan mode goes from 0->1, generate a pulse to clear the assets
     // Note that when scan goes to '1, Caliptra state as well as SOC state
     // gets messed up. So switch to scan is destructive (obvious! Duh!)
-    assign scan_mode_switch = ~scan_mode_f & scan_mode;
-    // 1->0 transition (Debug locked to unlocked)
-    assign debug_lock_to_unlock_switch = security_state_f.debug_locked & ~security_state.debug_locked;
-    assign debugUnlock_or_scan_mode_switch = debug_lock_to_unlock_switch | scan_mode_switch;
-    assign clear_obf_secrets_debugScanQ = clear_obf_secrets | debugUnlock_or_scan_mode_switch;
+    assign scan_mode_switch = cptra_scan_mode_Latched_d & ~cptra_scan_mode_Latched_f;
+    // Detect transition of debug mode
+    assign debug_lock_switch = cptra_security_state_Latched_d.debug_locked ^ cptra_security_state_Latched_f.debug_locked;
+    assign debug_lock_or_scan_mode_switch = debug_lock_switch | scan_mode_switch | cptra_error_fatal;
+
+    assign clear_obf_secrets_debugScanQ = clear_obf_secrets | cptra_in_debug_scan_mode | cptra_error_fatal;
 
 //=========================================================================-
 // Clock gating instance
@@ -555,9 +649,16 @@ clk_gate cg (
     .psel(PSEL),
     .clk_gate_en(clk_gating_en),
     .cpu_halt_status(o_cpu_halt_status),
+    .rdc_clk_dis(rdc_clk_dis),
+    .rdc_clk_dis_uc (fw_update_rst_window),
     .clk_cg (clk_cg),
     .soc_ifc_clk_cg (soc_ifc_clk_cg),
-    .generic_input_wires(generic_input_wires)
+    .rdc_clk_cg (rdc_clk_cg),
+    .uc_clk_cg (uc_clk_cg),
+    .generic_input_wires(generic_input_wires),
+    .cptra_error_fatal(cptra_error_fatal),
+    .cptra_in_debug_scan_mode(cptra_in_debug_scan_mode),
+    .cptra_dmi_reg_en_preQ(cptra_dmi_reg_en_preQ)
 );
 //=========================================================================-
 // AHB I$ instance
@@ -569,7 +670,8 @@ ahb_lite_2to1_mux #(
     .AHB_LITE_DATA_WIDTH(`CALIPTRA_IMEM_DATA_WIDTH)
 ) u_ahb_lite_2to1_mux (
     .hclk           (clk_cg),
-    .hreset_n       (cptra_noncore_rst_b),
+    .hreset_n       (cptra_uc_rst_b),
+    .force_bus_idle (fw_update_rst_window),
     // From Initiator 0
     // Inputs
     .hsel_i_0             (responder_inst[`CALIPTRA_SLAVE_SEL_IMEM].hsel),
@@ -619,7 +721,7 @@ caliptra_ahb_srom #(
 
     //AMBA AHB Lite INF
     .hclk       (clk_cg),
-    .hreset_n   (cptra_noncore_rst_b),
+    .hreset_n   (cptra_uc_rst_b),
     .haddr_i    (imem_haddr[`CALIPTRA_IMEM_BYTE_ADDR_W-1:0]),
     .hwdata_i   (`CALIPTRA_IMEM_DATA_WIDTH'(0)             ),
     .hsel_i     (imem_hsel),
@@ -668,7 +770,8 @@ sha512_ctrl #(
     .pcr_signing_hash(pcr_signing_data.pcr_hash),
 
     .error_intr(sha512_error_intr),
-    .notif_intr(sha512_notif_intr)
+    .notif_intr(sha512_notif_intr),
+    .debugUnlock_or_scan_mode_switch(debug_lock_or_scan_mode_switch)
 );
 
 sha256_ctrl #(
@@ -690,11 +793,12 @@ sha256_ctrl #(
     .hrdata_o       (responder_inst[`CALIPTRA_SLAVE_SEL_SHA256].hrdata),
 
     .error_intr(sha256_error_intr),
-    .notif_intr(sha256_notif_intr)
+    .notif_intr(sha256_notif_intr),
+    .debugUnlock_or_scan_mode_switch(debug_lock_or_scan_mode_switch)
 );
 
 //override device secrets with debug values in Debug or Scan Mode
-always_comb cptra_in_debug_scan_mode = ~security_state.debug_locked | scan_mode;
+always_comb cptra_in_debug_scan_mode = ~cptra_security_state_Latched.debug_locked | cptra_scan_mode_Latched;
 always_comb cptra_obf_key_dbg     = cptra_in_debug_scan_mode ? `CLP_DEBUG_MODE_OBF_KEY : cptra_obf_key_reg;
 always_comb obf_uds_seed_dbg      = cptra_in_debug_scan_mode ? `CLP_DEBUG_MODE_UDS_SEED : obf_uds_seed;
 always_comb obf_field_entropy_dbg = cptra_in_debug_scan_mode ? `CLP_DEBUG_MODE_FIELD_ENTROPY : obf_field_entropy;
@@ -724,8 +828,8 @@ doe_ctrl #(
     .notif_intr(doe_notif_intr),
     .clear_obf_secrets(clear_obf_secrets), //Output
     .kv_write (kv_write[KV_NUM_WRITE-1]),
-    .kv_wr_resp (kv_wr_resp[KV_NUM_WRITE-1])
-
+    .kv_wr_resp (kv_wr_resp[KV_NUM_WRITE-1]),
+    .debugUnlock_or_scan_mode_switch(debug_lock_or_scan_mode_switch)
     
 );
 
@@ -756,7 +860,8 @@ ecc_top1
     .pcr_signing_data(pcr_signing_data),
 
     .error_intr      (ecc_error_intr),
-    .notif_intr      (ecc_notif_intr)
+    .notif_intr      (ecc_notif_intr),
+    .debugUnlock_or_scan_mode_switch(debug_lock_or_scan_mode_switch)
 );
 
 hmac_ctrl #(
@@ -782,7 +887,8 @@ hmac_ctrl #(
      .kv_wr_resp    (kv_wr_resp[0]),
 
      .error_intr(hmac_error_intr),
-     .notif_intr(hmac_notif_intr)
+     .notif_intr(hmac_notif_intr),
+     .debugUnlock_or_scan_mode_switch(debug_lock_or_scan_mode_switch)
 
 );
 
@@ -792,28 +898,30 @@ kv #(
 )
 key_vault1
 (
-    .clk              (clk_cg),
-    .rst_b            (cptra_noncore_rst_b),
-    .core_only_rst_b  (cptra_uc_rst_b),
-    .cptra_pwrgood    (cptra_pwrgood),
-    .haddr_i          (responder_inst[`CALIPTRA_SLAVE_SEL_KV].haddr[`CALIPTRA_SLAVE_ADDR_WIDTH(`CALIPTRA_SLAVE_SEL_KV)-1:0]),
-    .hwdata_i         (responder_inst[`CALIPTRA_SLAVE_SEL_KV].hwdata),
-    .hsel_i           (responder_inst[`CALIPTRA_SLAVE_SEL_KV].hsel),
-    .hwrite_i         (responder_inst[`CALIPTRA_SLAVE_SEL_KV].hwrite),
-    .hready_i         (responder_inst[`CALIPTRA_SLAVE_SEL_KV].hready),
-    .htrans_i         (responder_inst[`CALIPTRA_SLAVE_SEL_KV].htrans),
-    .hsize_i          (responder_inst[`CALIPTRA_SLAVE_SEL_KV].hsize),
-    .hresp_o          (responder_inst[`CALIPTRA_SLAVE_SEL_KV].hresp),
-    .hreadyout_o      (responder_inst[`CALIPTRA_SLAVE_SEL_KV].hreadyout),
-    .hrdata_o         (responder_inst[`CALIPTRA_SLAVE_SEL_KV].hrdata),
-
-    .debugUnlock_or_scan_mode_switch (debugUnlock_or_scan_mode_switch),
-
-    .kv_read          (kv_read),
-    .kv_write         (kv_write),
-    .kv_rd_resp       (kv_rd_resp),
-    .kv_wr_resp       (kv_wr_resp),
-    .pcr_signing_key  (pcr_signing_data.pcr_signing_privkey)
+    .clk                  (clk_cg),
+    .rst_b                (cptra_noncore_rst_b),
+    .core_only_rst_b      (cptra_uc_rst_b),
+    .cptra_pwrgood        (cptra_pwrgood),
+    .fw_update_rst_window (fw_update_rst_window),
+    .haddr_i              (responder_inst[`CALIPTRA_SLAVE_SEL_KV].haddr[`CALIPTRA_SLAVE_ADDR_WIDTH(`CALIPTRA_SLAVE_SEL_KV)-1:0]),
+    .hwdata_i             (responder_inst[`CALIPTRA_SLAVE_SEL_KV].hwdata),
+    .hsel_i               (responder_inst[`CALIPTRA_SLAVE_SEL_KV].hsel),
+    .hwrite_i             (responder_inst[`CALIPTRA_SLAVE_SEL_KV].hwrite),
+    .hready_i             (responder_inst[`CALIPTRA_SLAVE_SEL_KV].hready),
+    .htrans_i             (responder_inst[`CALIPTRA_SLAVE_SEL_KV].htrans),
+    .hsize_i              (responder_inst[`CALIPTRA_SLAVE_SEL_KV].hsize),
+    .hresp_o              (responder_inst[`CALIPTRA_SLAVE_SEL_KV].hresp),
+    .hreadyout_o          (responder_inst[`CALIPTRA_SLAVE_SEL_KV].hreadyout),
+    .hrdata_o             (responder_inst[`CALIPTRA_SLAVE_SEL_KV].hrdata),
+
+    .cptra_in_debug_scan_mode(cptra_in_debug_scan_mode),
+    .debugUnlock_or_scan_mode_switch (debug_lock_or_scan_mode_switch),
+
+    .kv_read              (kv_read),
+    .kv_write             (kv_write),
+    .kv_rd_resp           (kv_rd_resp),
+    .kv_wr_resp           (kv_wr_resp),
+    .pcr_signing_key      (pcr_signing_data.pcr_signing_privkey)
 );
 
 pv #(
@@ -822,24 +930,26 @@ pv #(
 )
 pcr_vault1
 (
-    .clk           (clk_cg),
-    .rst_b         (cptra_noncore_rst_b),
-    .cptra_pwrgood (cptra_pwrgood),
-    .haddr_i       (responder_inst[`CALIPTRA_SLAVE_SEL_PV].haddr[`CALIPTRA_SLAVE_ADDR_WIDTH(`CALIPTRA_SLAVE_SEL_PV)-1:0]),
-    .hwdata_i      (responder_inst[`CALIPTRA_SLAVE_SEL_PV].hwdata),
-    .hsel_i        (responder_inst[`CALIPTRA_SLAVE_SEL_PV].hsel),
-    .hwrite_i      (responder_inst[`CALIPTRA_SLAVE_SEL_PV].hwrite),
-    .hready_i      (responder_inst[`CALIPTRA_SLAVE_SEL_PV].hready),
-    .htrans_i      (responder_inst[`CALIPTRA_SLAVE_SEL_PV].htrans),
-    .hsize_i       (responder_inst[`CALIPTRA_SLAVE_SEL_PV].hsize),
-    .hresp_o       (responder_inst[`CALIPTRA_SLAVE_SEL_PV].hresp),
-    .hreadyout_o   (responder_inst[`CALIPTRA_SLAVE_SEL_PV].hreadyout),
-    .hrdata_o      (responder_inst[`CALIPTRA_SLAVE_SEL_PV].hrdata),
-
-    .pv_read       (pv_read),
-    .pv_write      (pv_write),
-    .pv_rd_resp    (pv_rd_resp),
-    .pv_wr_resp    (pv_wr_resp)
+    .clk                  (clk_cg),
+    .rst_b                (cptra_noncore_rst_b),
+    .core_only_rst_b      (cptra_uc_rst_b),
+    .cptra_pwrgood        (cptra_pwrgood),
+    .fw_update_rst_window (fw_update_rst_window),
+    .haddr_i              (responder_inst[`CALIPTRA_SLAVE_SEL_PV].haddr[`CALIPTRA_SLAVE_ADDR_WIDTH(`CALIPTRA_SLAVE_SEL_PV)-1:0]),
+    .hwdata_i             (responder_inst[`CALIPTRA_SLAVE_SEL_PV].hwdata),
+    .hsel_i               (responder_inst[`CALIPTRA_SLAVE_SEL_PV].hsel),
+    .hwrite_i             (responder_inst[`CALIPTRA_SLAVE_SEL_PV].hwrite),
+    .hready_i             (responder_inst[`CALIPTRA_SLAVE_SEL_PV].hready),
+    .htrans_i             (responder_inst[`CALIPTRA_SLAVE_SEL_PV].htrans),
+    .hsize_i              (responder_inst[`CALIPTRA_SLAVE_SEL_PV].hsize),
+    .hresp_o              (responder_inst[`CALIPTRA_SLAVE_SEL_PV].hresp),
+    .hreadyout_o          (responder_inst[`CALIPTRA_SLAVE_SEL_PV].hreadyout),
+    .hrdata_o             (responder_inst[`CALIPTRA_SLAVE_SEL_PV].hrdata),
+
+    .pv_read              (pv_read),
+    .pv_write             (pv_write),
+    .pv_rd_resp           (pv_rd_resp),
+    .pv_wr_resp           (pv_wr_resp)
 );
 
 dv #(
@@ -897,7 +1007,7 @@ csrng #(
     .hreadyout_o            (responder_inst[`CALIPTRA_SLAVE_SEL_CSRNG].hreadyout),
     .hrdata_o               (responder_inst[`CALIPTRA_SLAVE_SEL_CSRNG].hrdata),
      // OTP Interface
-    .otp_en_csrng_sw_app_read_i(prim_mubi_pkg::MuBi8True),
+    .otp_en_csrng_sw_app_read_i(caliptra_prim_mubi_pkg::MuBi8True),
     // Lifecycle broadcast inputs
     .lc_hw_debug_en_i       (lc_ctrl_pkg::On),
     // Entropy Interface
@@ -910,7 +1020,7 @@ csrng #(
     .csrng_cmd_o            (),
     // Alerts
     .alert_tx_o             (),
-    .alert_rx_i             ({prim_alert_pkg::ALERT_RX_DEFAULT, prim_alert_pkg::ALERT_RX_DEFAULT}),
+    .alert_rx_i             ({caliptra_prim_alert_pkg::ALERT_RX_DEFAULT, caliptra_prim_alert_pkg::ALERT_RX_DEFAULT}),
     // Interrupt
     .intr_cs_cmd_req_done_o (),
     .intr_cs_entropy_req_o  (),
@@ -936,8 +1046,8 @@ entropy_src #(
     .hreadyout_o            (responder_inst[`CALIPTRA_SLAVE_SEL_ENTROPY_SRC].hreadyout),
     .hrdata_o               (responder_inst[`CALIPTRA_SLAVE_SEL_ENTROPY_SRC].hrdata),
     // OTP Interface
-    .otp_en_entropy_src_fw_read_i(prim_mubi_pkg::MuBi8True),
-    .otp_en_entropy_src_fw_over_i(prim_mubi_pkg::MuBi8True),
+    .otp_en_entropy_src_fw_read_i(caliptra_prim_mubi_pkg::MuBi8True),
+    .otp_en_entropy_src_fw_over_i(caliptra_prim_mubi_pkg::MuBi8True),
     // RNG Interface
     .rng_fips_o                       (),
     // Entropy Interface
@@ -953,7 +1063,7 @@ entropy_src #(
     .entropy_src_xht_o                (),
     .entropy_src_xht_i                (entropy_src_xht_rsp_t'('0)),
     // Alerts
-    .alert_rx_i                       ({prim_alert_pkg::ALERT_RX_DEFAULT, prim_alert_pkg::ALERT_RX_DEFAULT}),
+    .alert_rx_i                       ({caliptra_prim_alert_pkg::ALERT_RX_DEFAULT, caliptra_prim_alert_pkg::ALERT_RX_DEFAULT}),
     .alert_tx_o                       (),
     // Interrupts
     .intr_es_entropy_valid_o          (),
@@ -971,22 +1081,15 @@ entropy_src #(
   logic                               cio_sck_en_o;
   logic [`CALIPTRA_QSPI_CS_WIDTH-1:0] cio_csb_o;
   logic [`CALIPTRA_QSPI_CS_WIDTH-1:0] cio_csb_en_o;
-  logic [`CALIPTRA_QSPI_IO_WIDTH-1:0] cio_sd_o;
-  logic [`CALIPTRA_QSPI_IO_WIDTH-1:0] cio_sd_en_o;
-  logic [`CALIPTRA_QSPI_IO_WIDTH-1:0] cio_sd_i;
 
   assign qspi_clk_o = cio_sck_en_o ? cio_sck_o : 1'b0;
   for (genvar ii = 0; ii < `CALIPTRA_QSPI_CS_WIDTH; ii += 1) begin : gen_qspi_cs
     assign qspi_cs_no[ii] = cio_csb_en_o[ii] ? cio_csb_o[ii] : 1'b1;
   end
-  for (genvar ii = 0; ii < `CALIPTRA_QSPI_IO_WIDTH; ii += 1) begin : gen_qspi_io
-    assign qspi_d_io[ii] = cio_sd_en_o[ii] ? cio_sd_o[ii] : 1'bz;
-    assign cio_sd_i[ii]  = cio_sd_en_o[ii] ? 1'bz : qspi_d_io[ii];
-  end
 
 spi_host #(
     .AHBDataWidth(`CALIPTRA_AHB_HDATA_SIZE),
-    .AHBAddrWidth(`CALIPTRA_SLAVE_ADDR_WIDTH(`CALIPTRA_SLAVE_SEL_CSRNG))
+    .AHBAddrWidth(`CALIPTRA_SLAVE_ADDR_WIDTH(`CALIPTRA_SLAVE_SEL_QSPI))
 ) spi_host (
     // Clock and reset connections
     .clk_i                  (clk_cg),
@@ -1003,16 +1106,16 @@ spi_host #(
     .hreadyout_o            (responder_inst[`CALIPTRA_SLAVE_SEL_QSPI].hreadyout),
     .hrdata_o               (responder_inst[`CALIPTRA_SLAVE_SEL_QSPI].hrdata),
     // Alerts
-    .alert_rx_i(prim_alert_pkg::ALERT_RX_DEFAULT),
+    .alert_rx_i(caliptra_prim_alert_pkg::ALERT_RX_DEFAULT),
     .alert_tx_o(),
     // SPI Interface
     .cio_sck_o    (cio_sck_o),
     .cio_sck_en_o (cio_sck_en_o),
     .cio_csb_o    (cio_csb_o),
     .cio_csb_en_o (cio_csb_en_o),
-    .cio_sd_o     (cio_sd_o),
-    .cio_sd_en_o  (cio_sd_en_o),
-    .cio_sd_i     (cio_sd_i),
+    .cio_sd_o     (qspi_d_o),
+    .cio_sd_en_o  (qspi_d_en_o),
+    .cio_sd_i     (qspi_d_i),
     .intr_error_o(),
     .intr_spi_event_o()
   );
@@ -1020,7 +1123,8 @@ spi_host #(
 //QSPI Tie Off
 assign qspi_clk_o = '0;
 assign qspi_cs_no = '0;
-assign qspi_d_io = '0;
+assign qspi_d_o = '0;
+assign qspi_d_en_o = '0;
 `endif
 
 `ifdef CALIPTRA_INTERNAL_UART
@@ -1072,6 +1176,7 @@ soc_ifc_top1
     .clk(clk),
     .clk_cg(clk_cg),
     .soc_ifc_clk_cg(soc_ifc_clk_cg),
+    .rdc_clk_cg(rdc_clk_cg),
     .cptra_pwrgood(cptra_pwrgood), 
     .cptra_rst_b(cptra_rst_b),
     .ready_for_fuses(ready_for_fuses),
@@ -1080,7 +1185,7 @@ soc_ifc_top1
     .mailbox_data_avail(mailbox_data_avail),
     .mailbox_flow_done(mailbox_flow_done),
 
-    .security_state(security_state),
+    .security_state(cptra_security_state_Latched),
     
     .BootFSM_BrkPoint (BootFSM_BrkPoint),
     
@@ -1091,6 +1196,9 @@ soc_ifc_top1
     .mbox_sram_req(mbox_sram_req),
     .mbox_sram_resp(mbox_sram_resp),
 
+    // RV ECC Status Interface
+    .rv_ecc_sts(rv_ecc_sts),
+
     //APB Interface with SoC
     .paddr_i(PADDR[`CALIPTRA_SLAVE_ADDR_WIDTH(`CALIPTRA_SLAVE_SEL_SOC_IFC)-1:0]),
     .psel_i(PSEL),
@@ -1125,9 +1233,10 @@ soc_ifc_top1
     .soc_ifc_notif_intr(soc_ifc_notif_intr),
     .sha_error_intr(sha_error_intr),
     .sha_notif_intr(sha_notif_intr),
+    .timer_intr(timer_int),
     //Obfuscated UDS and FE
     .clear_obf_secrets(clear_obf_secrets_debugScanQ), //input - includes debug & scan modes to do the register clearing
-    .scan_mode_f(scan_mode_f),
+    .scan_mode_f(cptra_scan_mode_Latched),
     .cptra_obf_key(cptra_obf_key),
     .cptra_obf_key_reg(cptra_obf_key_reg),
     .obf_field_entropy(obf_field_entropy),
@@ -1143,6 +1252,8 @@ soc_ifc_top1
     .cptra_uc_rst_b (cptra_uc_rst_b),
     //Clock gating en
     .clk_gating_en(clk_gating_en),
+    .rdc_clk_dis(rdc_clk_dis),
+    .fw_update_rst_window(fw_update_rst_window),
 
     //caliptra uncore jtag ports
     .cptra_uncore_dmi_reg_en   ( cptra_uncore_dmi_reg_en ),
diff --git a/src/integration/rtl/config_defines.svh b/src/integration/rtl/config_defines.svh
index 44d5230b8..1a52b4002 100755
--- a/src/integration/rtl/config_defines.svh
+++ b/src/integration/rtl/config_defines.svh
@@ -32,7 +32,7 @@
   // AHB Address Map
   `define CALIPTRA_SLAVE_NAMES         {"ENTROPY_SRC", "CSRNG"      , "IMEM"       , "SHA256"     , "VEER_ICCM_DMA" , "VEER_DCCM_DMA"  , "SOC_IFC"    , "I3C"        , "UART"       , "QSPI"       , "SHA512"     , "DATAVAULT"  , "PCRVAULT"   , "KEYVAULT"   , "HMAC"       , "ECC"        , "DOE_CTRL"   } /* Array of names for peripherals */
   `define CALIPTRA_SLAVE_BASE_ADDR     {32'h2000_3000, 32'h2000_2000, 32'h0000_0000, 32'h1002_8000, 32'h4000_0000   , 32'h5000_0000    , 32'h3000_0000, 32'hFFFF_FFFF, 32'h2000_1000, 32'h2000_0000, 32'h1002_0000, 32'h1001_C000, 32'h1001_A000, 32'h1001_8000, 32'h1001_0000, 32'h1000_8000, 32'h1000_0000} /* Array with slave base address */
-  `define CALIPTRA_SLAVE_MASK_ADDR     {32'h2000_3FFF, 32'h2000_2FFF, 32'h0000_8000, 32'h1002_FFFF, 32'h4001_FFFF   , 32'h5001_FFFF    , 32'h3003_FFFF, 32'hFFFF_FFFF, 32'h2000_1FFF, 32'h2000_0FFF, 32'h1002_7FFF, 32'h1001_DFFF, 32'h1001_BFFF, 32'h1001_9FFF, 32'h1001_0FFF, 32'h1000_FFFF, 32'h1000_7FFF} /* Array with slave offset address */
+  `define CALIPTRA_SLAVE_MASK_ADDR     {32'h2000_3FFF, 32'h2000_2FFF, 32'h0000_BFFF, 32'h1002_FFFF, 32'h4001_FFFF   , 32'h5001_FFFF    , 32'h3003_FFFF, 32'hFFFF_FFFF, 32'h2000_1FFF, 32'h2000_0FFF, 32'h1002_7FFF, 32'h1001_DFFF, 32'h1001_BFFF, 32'h1001_9FFF, 32'h1001_0FFF, 32'h1000_FFFF, 32'h1000_7FFF} /* Array with slave offset address */
   `define CALIPTRA_SLAVE_ADDR_MASK     (`CALIPTRA_SLAVE_BASE_ADDR ^ `CALIPTRA_SLAVE_MASK_ADDR) /* Array indicating meaningful address bits for each slave */
   `define CALIPTRA_SLAVE_ADDR_WIDTH(n) $clog2((`CALIPTRA_SLAVE_ADDR_MASK >> (`CALIPTRA_AHB_HADDR_SIZE*n)) & {`CALIPTRA_AHB_HADDR_SIZE{1'b1}}) /* Decode address width for each slave from assigned BASE/MASK address */
   `define CALIPTRA_SLAVE_SEL_DOE         0
@@ -83,7 +83,7 @@
   //`define CALIPTRA_KV_NUM_READ 6
   //`define CALIPTRA_KV_NUM_WRITE 4
 
-  `define CALIPTRA_IMEM_BYTE_SIZE   32768
+  `define CALIPTRA_IMEM_BYTE_SIZE   49152
   `define CALIPTRA_IMEM_DATA_WIDTH  64
   `define CALIPTRA_IMEM_DEPTH       `CALIPTRA_IMEM_BYTE_SIZE / (`CALIPTRA_IMEM_DATA_WIDTH/8)
   `define CALIPTRA_IMEM_BYTE_ADDR_W $clog2(`CALIPTRA_IMEM_BYTE_SIZE)
diff --git a/src/integration/stimulus/L0_regression.yml b/src/integration/stimulus/L0_regression.yml
index 91afa9e8d..e979afb51 100644
--- a/src/integration/stimulus/L0_regression.yml
+++ b/src/integration/stimulus/L0_regression.yml
@@ -9,6 +9,7 @@ contents:
         #add back for aes
         #- ../test_suites/smoke_test_aes/smoke_test_aes.yml
         - ../test_suites/smoke_test_mbox/smoke_test_mbox.yml
+        #- ../test_suites/smoke_test_mbox_cg/smoke_test_mbox_cg.yml
         - ../test_suites/smoke_test_sha512/smoke_test_sha512.yml
         - ../test_suites/smoke_test_sha256/smoke_test_sha256.yml
         - ../test_suites/smoke_test_sha_accel/smoke_test_sha_accel.yml
@@ -21,20 +22,32 @@ contents:
         - ../test_suites/smoke_test_hmac/smoke_test_hmac.yml
         - ../test_suites/smoke_test_kv/smoke_test_kv.yml
         - ../test_suites/smoke_test_sram_ecc/smoke_test_sram_ecc.yml
-        # smoke_test_trng requires Caliptra to be built using the
-        # +define+CALIPTRA_INTERNAL_TRNG argument, which is not the
-        # default build config
-        # It will simply die without running in this L0 regression
+        - ../test_suites/smoke_test_ras/smoke_test_ras.yml
+        # The following tests need defines, which are not in the default build config
+        # smoke_test_trng : +define+CALIPTRA_INTERNAL_TRNG
+        # smoke_test_qspi : +define+CALIPTRA_INTERNAL_QSPI
+        # smoke_test_uart : +define+CALIPTRA_INTERNAL_UART
+        # They will simply die without running in this L0 regression
         - ../test_suites/smoke_test_trng/smoke_test_trng.yml
+        - ../test_suites/smoke_test_qspi/smoke_test_qspi.yml
+        - ../test_suites/smoke_test_uart/smoke_test_uart.yml
         - ../test_suites/smoke_test_kv_uds_reset/smoke_test_kv_uds_reset.yml
         - ../test_suites/smoke_test_kv_securitystate/smoke_test_kv_securitystate.yml
         - ../test_suites/smoke_test_kv_ecc_flow/smoke_test_kv_ecc_flow.yml
         - ../test_suites/smoke_test_kv_hmac_flow/smoke_test_kv_hmac_flow.yml
         - ../test_suites/smoke_test_kv_sha512_flow/smoke_test_kv_sha512_flow.yml
         - ../test_suites/smoke_test_kv_crypto_flow/smoke_test_kv_crypto_flow.yml
+        #- ../test_suites/smoke_test_kv_cg/smoke_test_kv_cg.yml
         - ../test_suites/pv_hash_and_sign/pv_hash_and_sign.yml
         - ../test_suites/smoke_test_pcr_signing/smoke_test_pcr_signing.yml
+        - ../test_suites/smoke_test_fw_kv_backtoback_hmac/smoke_test_fw_kv_backtoback_hmac.yml
+        - ../test_suites/smoke_test_ecc_errortrigger/smoke_test_ecc_errortrigger.yml
+        - ../test_suites/smoke_test_pcr_zeroize/smoke_test_pcr_zeroize.yml
         - ../test_suites/smoke_test_ahb_mux/smoke_test_ahb_mux.yml
+        - ../test_suites/smoke_test_doe_rand/smoke_test_doe_rand.yml
+        - ../test_suites/smoke_test_doe_scan/smoke_test_doe_scan.yml
+        - ../test_suites/smoke_test_zeroize_crypto/smoke_test_zeroize_crypto.yml
+        #- ../test_suites/smoke_test_doe_cg/smoke_test_doe_cg.yml
         # data vault tests
         - ../test_suites/smoke_test_datavault_basic/smoke_test_datavault_basic.yml
         - ../test_suites/smoke_test_datavault_reset/smoke_test_datavault_reset.yml
@@ -44,5 +57,9 @@ contents:
         #smoke test debug state transition
         #smoke test interrupt handling
         #smoke test wd timer expiry and nmi generation
+        - ../test_suites/smoke_test_wdt/smoke_test_wdt.yml
+        - ../test_suites/smoke_test_cg_wdt/smoke_test_cg_wdt.yml
         #smoke test jtag
         #smoke test generic input wire to fw interrupt
+        - ../test_suites/smoke_test_clk_gating/smoke_test_clk_gating.yml
+        - ../test_suites/smoke_test_iccm_reset/smoke_test_iccm_reset.yml
diff --git a/src/integration/stimulus/L0_trng_regression.yml b/src/integration/stimulus/L0_trng_regression.yml
index 0fca213e9..9bf496444 100644
--- a/src/integration/stimulus/L0_trng_regression.yml
+++ b/src/integration/stimulus/L0_trng_regression.yml
@@ -6,32 +6,15 @@ contents:
       tags: ["L0_trng", "Lop_trng_regression", "top_trng_regression"]
       paths:
         - ../test_suites/smoke_test_veer/smoke_test_veer.yml
-        #add back for aes
-        #- ../test_suites/smoke_test_aes/smoke_test_aes.yml
         - ../test_suites/smoke_test_mbox/smoke_test_mbox.yml
-        - ../test_suites/smoke_test_sha512/smoke_test_sha512.yml
-        - ../test_suites/smoke_test_sha256/smoke_test_sha256.yml
         - ../test_suites/smoke_test_sha_accel/smoke_test_sha_accel.yml
-        - ../test_suites/memCpy_ROM_to_dccm/memCpy_ROM_to_dccm.yml
         - ../test_suites/memCpy_dccm_to_iccm/memCpy_dccm_to_iccm.yml
         - ../test_suites/hello_world_iccm/hello_world_iccm.yml
         - ../test_suites/iccm_lock/iccm_lock.yml
         - ../test_suites/c_intr_handler/c_intr_handler.yml
-        #- ../test_suites/smoke_test_ecc/smoke_test_ecc.yml
-        - ../test_suites/smoke_test_hmac/smoke_test_hmac.yml
-        - ../test_suites/smoke_test_kv/smoke_test_kv.yml
         - ../test_suites/smoke_test_sram_ecc/smoke_test_sram_ecc.yml
         - ../test_suites/smoke_test_trng/smoke_test_trng.yml
         - ../test_suites/smoke_test_kv_uds_reset/smoke_test_kv_uds_reset.yml
-        - ../test_suites/smoke_test_kv_securitystate/smoke_test_kv_securitystate.yml
-        - ../test_suites/smoke_test_kv_ecc_flow/smoke_test_kv_ecc_flow.yml
-        - ../test_suites/smoke_test_kv_hmac_flow/smoke_test_kv_hmac_flow.yml
-        - ../test_suites/smoke_test_kv_sha512_flow/smoke_test_kv_sha512_flow.yml
-        - ../test_suites/pv_hash_and_sign/pv_hash_and_sign.yml
-        #smoke test icc locking
-        #smoke test impactles reset
-        #smoke test debug state transition
-        #smoke test interrupt handling
-        #smoke test wd timer expiry and nmi generation
-        #smoke test jtag
-        #smoke test generic input wire to fw interrupt
+        - ../test_suites/smoke_test_wdt/smoke_test_wdt.yml
+        - ../test_suites/smoke_test_cg_wdt/smoke_test_cg_wdt.yml
+        - ../test_suites/smoke_test_clk_gating/smoke_test_clk_gating.yml
diff --git a/src/integration/stimulus/testsuites/caliptra_top_nightly_random_regression.yml b/src/integration/stimulus/testsuites/caliptra_top_nightly_random_regression.yml
index 116a6c0fd..70c33e93e 100644
--- a/src/integration/stimulus/testsuites/caliptra_top_nightly_random_regression.yml
+++ b/src/integration/stimulus/testsuites/caliptra_top_nightly_random_regression.yml
@@ -5,10 +5,16 @@ contents:
   - generator:
       tags: ["L1", "CALIPTRA_TOP",  "random"]
       path: ""
+      config:
+        params:
+          # 12 hours to accommodate certain longer-running tests
+          timeout: 720
       weight: 100
-      generations: 100
+      generations: 500
       formats: 
         generate: "reseed {template}.yml -seed {seed}"
         path: "{template_basename}__{seed}.yml"
       templates:
         $CALIPTRA_ROOT/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_rand_test   : { weight 100 }
+        $CALIPTRA_ROOT/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_wdt_test    : { weight 100 }
+        $CALIPTRA_ROOT/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_wdt_independent_test   : { weight 100 }
diff --git a/src/integration/stimulus/testsuites/uvmf_caliptra_top_nightly_directed_regression.yml b/src/integration/stimulus/testsuites/uvmf_caliptra_top_nightly_directed_regression.yml
new file mode 100644
index 000000000..5baa312a8
--- /dev/null
+++ b/src/integration/stimulus/testsuites/uvmf_caliptra_top_nightly_directed_regression.yml
@@ -0,0 +1,18 @@
+document:
+  schema: 1.0
+
+contents:
+  - generator:
+      tags: ["L1", "CALIPTRA_TOP",  "directed", "ROM"]
+      path: ""
+      config:
+        params:
+          # 12 hours
+          timeout: 720
+      weight: 100
+      generations: 1
+      formats: 
+        generate: "reseed {template}.yml -seed {seed}"
+        path: "{template_basename}__{seed}.yml"
+      templates:
+        $CALIPTRA_ROOT/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_rom_test   : { weight 100 }
diff --git a/src/integration/stimulus/testsuites/uvmf_caliptra_top_promote_regression.yml b/src/integration/stimulus/testsuites/uvmf_caliptra_top_promote_regression.yml
new file mode 100644
index 000000000..77fcfc323
--- /dev/null
+++ b/src/integration/stimulus/testsuites/uvmf_caliptra_top_promote_regression.yml
@@ -0,0 +1,15 @@
+document:
+  schema: 1.0
+
+contents:
+  - generator:
+      tags: ["L0", "CALIPTRA_TOP",  "directed", "smoke_test"]
+      path: ""
+      weight: 100
+      generations: 1
+      formats: 
+        generate: "reseed {template}.yml -seed 1"
+        path: "{template_basename}__1.yml"
+      templates:
+        $CALIPTRA_ROOT/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_cmdline_test   : { weight 100 }
+        #$CALIPTRA_ROOT/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_rand_test      : { weight 500 }
diff --git a/src/integration/tb/caliptra_top_tb.sv b/src/integration/tb/caliptra_top_tb.sv
index ad0f48c12..ca7f5e21e 100755
--- a/src/integration/tb/caliptra_top_tb.sv
+++ b/src/integration/tb/caliptra_top_tb.sv
@@ -28,8 +28,8 @@ module caliptra_top_tb (
     );
 `endif
 
-    import caliptra_top_tb_pkg::*;
     import soc_ifc_pkg::*;
+    import caliptra_top_tb_pkg::*;
 
 `ifndef VERILATOR
     // Time formatting for %t in display tasks
@@ -53,11 +53,19 @@ module caliptra_top_tb (
     logic                       BootFSM_BrkPoint;
     logic                       scan_mode;
 
-    logic [7:0][31:0]           cptra_obf_key;
-    logic [0:7][31:0]           cptra_obf_key_uds, cptra_obf_key_fe;
+    logic [`CLP_OBF_KEY_DWORDS-1:0][31:0]          cptra_obf_key;
+    logic [0:`CLP_OBF_KEY_DWORDS-1][31:0]          cptra_obf_key_uds, cptra_obf_key_fe;
     
-    logic [0:11][31:0]          cptra_uds_tb;
-    logic [0:31][31:0]          cptra_fe_tb;
+    // logic [11:0][31:0]          cptra_uds_tb;
+    // logic [7:0][31:0]           cptra_fe_tb;
+    logic [0:`CLP_OBF_UDS_DWORDS-1][31:0]          cptra_uds_tb;
+    logic [0:`CLP_OBF_FE_DWORDS-1][31:0]           cptra_fe_tb;
+
+    // logic [11:0][31:0]          cptra_uds_rand;
+    // logic [7:0][31:0]           cptra_fe_rand;
+    logic [0:`CLP_OBF_UDS_DWORDS-1][31:0]          cptra_uds_rand;
+    logic [0:`CLP_OBF_FE_DWORDS-1][31:0]           cptra_fe_rand;
+    logic [0:`CLP_OBF_KEY_DWORDS-1][31:0]          cptra_obf_key_tb;
 
     logic                       start_apb_fuse_sequence;
 
@@ -65,9 +73,11 @@ module caliptra_top_tb (
         S_APB_IDLE,
         S_APB_WR_UDS,
         S_APB_WR_FE,
+        S_APB_WR_SOC_STEPPING_ID,
         S_APB_WR_FUSE_DONE,
+        S_APB_POLL_FLOW_ST,
         S_APB_WR_BOOT_GO,
-        S_APB_WAIT_FW_READY,
+        S_APB_WAIT_FW_TEST,
         S_APB_POLL_LOCK,
         S_APB_PRE_WR_CMD,
         S_APB_WR_CMD,
@@ -75,13 +85,25 @@ module caliptra_top_tb (
         S_APB_WR_DATAIN,
         S_APB_WR_STATUS,
         S_APB_WR_EXEC,
+        S_APB_WAIT_ERROR_AXS,
+        S_APB_RD_HW_ERROR_FATAL,
+        S_APB_WR_HW_ERROR_FATAL,
+        S_APB_RD_HW_ERROR_NON_FATAL,
+        S_APB_WR_HW_ERROR_NON_FATAL,
         S_APB_DONE,
+        S_APB_RD_DLEN,
+        S_APB_RD_DATAOUT,
+        S_APB_RST_EXEC,
         S_APB_ERROR
     } n_state_apb, c_state_apb;
 
+    parameter FW_NUM_DWORDS         = 256;
+
     logic [$clog2(FW_NUM_DWORDS)-1:0] apb_wr_count, apb_wr_count_nxt;
+    logic [31:0] apb_rd_count, apb_rd_count_nxt, dlen;
     logic apb_enable_ph;
     logic apb_xfer_end;
+    logic execute_mbox_rx_protocol;
 
     //jtag interface
     logic                       jtag_tck;    // JTAG clk
@@ -106,6 +128,8 @@ module caliptra_top_tb (
     logic                                qspi_clk;
     logic [`CALIPTRA_QSPI_CS_WIDTH-1:0]  qspi_cs_n;
     wire  [`CALIPTRA_QSPI_IO_WIDTH-1:0]  qspi_data;
+    logic [`CALIPTRA_QSPI_IO_WIDTH-1:0]  qspi_data_host_to_device, qspi_data_device_to_host;
+    logic [`CALIPTRA_QSPI_IO_WIDTH-1:0]  qspi_data_host_to_device_en;
 
 `ifdef CALIPTRA_INTERNAL_UART
     logic uart_loopback;
@@ -128,11 +152,26 @@ module caliptra_top_tb (
     //device lifecycle
     security_state_t security_state;
 
+    ras_test_ctrl_t ras_test_ctrl;
     logic [63:0] generic_input_wires;
     logic        etrng_req;
     logic  [3:0] itrng_data;
     logic        itrng_valid;
 
+    logic cptra_error_fatal;
+    logic cptra_error_non_fatal;
+    logic [15:0] cptra_error_fatal_counter;
+    logic [15:0] cptra_error_non_fatal_counter;
+    logic cptra_error_fatal_dly_p;
+    logic cptra_error_non_fatal_dly_p;
+
+    logic mbox_apb_dataout_read_ooo;
+    logic mbox_ooo_read_done;
+    logic mbox_apb_dataout_read_no_lock;
+    logic mbox_no_lock_read_done;
+
+    logic [`CALIPTRA_APB_DATA_WIDTH-1:0] soc_ifc_hw_error_wdata;
+
     //Interrupt flags
     //logic nmi_int;
     //logic soft_int;
@@ -144,13 +183,16 @@ module caliptra_top_tb (
     //Reset flags
     logic assert_hard_rst_flag;
     logic deassert_hard_rst_flag;
+    logic assert_rst_flag_from_service;
+    logic assert_rst_flag_from_fatal;
     logic assert_rst_flag;
+    logic deassert_rst_flag_from_service;
+    int   count_deassert_rst_flag_from_fatal;
+    logic deassert_rst_flag_from_fatal;
     logic deassert_rst_flag;
 
     el2_mem_if el2_mem_export ();
 
-    parameter FW_NUM_DWORDS         = 256;
-
     logic [FW_NUM_DWORDS-1:0][31:0] fw_blob;
 
 `ifndef VERILATOR
@@ -176,31 +218,177 @@ module caliptra_top_tb (
         
         else if((c_state_apb == S_APB_WR_EXEC) && apb_xfer_end && int_flag) begin
             //Wait for APB flow to be done before toggling generic_input_wires
-            generic_input_wires <= 'h4001; //Toggle wires
+            generic_input_wires <= {$urandom, $urandom}; //Toggle wires
         end
         
         else if((cycleCnt == cycleCnt_ff + 15000) && int_flag) begin
             force caliptra_top_dut.soft_int = 'b1;
         end
         
-        else begin
+        else if (!ras_test_ctrl.error_injection_seen) begin
             release caliptra_top_dut.soft_int;
             release caliptra_top_dut.timer_int;
             generic_input_wires <= 'h0;
         end
+
+        else if (ras_test_ctrl.reset_generic_input_wires) begin
+            generic_input_wires <= {32'h0, ERROR_NONE_SET};
+        end
+
+        else if (c_state_apb == S_APB_RD_HW_ERROR_FATAL && apb_xfer_end) begin
+            if (PRDATA[`SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_ICCM_ECC_UNC_LOW]) begin
+                generic_input_wires <= {32'h0, ICCM_FATAL_OBSERVED};
+            end
+            else if (PRDATA[`SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_DCCM_ECC_UNC_LOW]) begin
+                generic_input_wires <= {32'h0, DCCM_FATAL_OBSERVED};
+            end
+            else if (PRDATA[`SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_NMI_PIN_LOW]) begin
+                generic_input_wires <= {32'h0, NMI_FATAL_OBSERVED};
+            end
+            else begin
+                generic_input_wires <= {32'h0, ERROR_NONE_SET};
+            end
+        end
+
+        else if (c_state_apb == S_APB_RD_HW_ERROR_NON_FATAL && apb_xfer_end) begin
+            if (PRDATA[`SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_NO_LOCK_LOW]) begin
+                generic_input_wires <= {32'h0, PROT_NO_LOCK_NON_FATAL_OBSERVED};
+            end
+            else if (PRDATA[`SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_OOO_LOW]) begin
+                generic_input_wires <= {32'h0, PROT_OOO_NON_FATAL_OBSERVED};
+            end
+            else if (PRDATA[`SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_ECC_UNC_LOW]) begin
+                generic_input_wires <= {32'h0, MBOX_NON_FATAL_OBSERVED};
+            end
+            else begin
+                generic_input_wires <= {32'h0, ERROR_NONE_SET};
+            end
+        end
+
+    end
+
+    always@(negedge core_clk or negedge cptra_pwrgood) begin
+        // This persists across soft reset
+        if (!cptra_pwrgood) begin
+            soc_ifc_hw_error_wdata <= '0;
+        end
+        else if (c_state_apb inside {S_APB_RD_HW_ERROR_FATAL, S_APB_RD_HW_ERROR_NON_FATAL} && apb_xfer_end) begin
+            // HW ERROR registers are W1C, capture the set bits
+            soc_ifc_hw_error_wdata <= PRDATA;
+        end
+        else if (c_state_apb inside {S_APB_WR_HW_ERROR_FATAL, S_APB_WR_HW_ERROR_NON_FATAL} && apb_xfer_end) begin
+            // Clear after completing the write
+            soc_ifc_hw_error_wdata <= 0;
+        end
+    end
+
+    always@(negedge core_clk or negedge cptra_rst_b) begin
+        if (!cptra_rst_b) begin
+            cptra_error_fatal_counter     <= 16'h0;
+            cptra_error_non_fatal_counter <= 16'h0;
+        end
+        else begin
+            cptra_error_fatal_counter     <= cptra_error_fatal     ? (cptra_error_fatal_counter     + 16'h1) : 16'h0;
+            cptra_error_non_fatal_counter <= cptra_error_non_fatal ? (cptra_error_non_fatal_counter + 16'h1) : 16'h0;
+        end
+    end
+    // Pulse fires about 640ns after the original error interrupt occurs
+    always_comb cptra_error_fatal_dly_p     = cptra_error_fatal_counter     == 16'h0040;
+    always_comb cptra_error_non_fatal_dly_p = cptra_error_non_fatal_counter == 16'h0040;
+
+    always_comb assert_rst_flag_from_fatal = c_state_apb == S_APB_ERROR;
+    always@(negedge core_clk) begin
+        if (!cptra_pwrgood) begin
+            count_deassert_rst_flag_from_fatal <= 0;
+        end
+        // Start counting after the fatal flag asserts reset, and continue
+        // counting until the reset is deasserted
+        else if (assert_rst_flag_from_fatal || (!cptra_rst_b && |count_deassert_rst_flag_from_fatal)) begin
+            count_deassert_rst_flag_from_fatal <= count_deassert_rst_flag_from_fatal + 1;
+        end
+        else begin
+            count_deassert_rst_flag_from_fatal <= 0;
+        end
     end
+    // Leave reset asserted for 32 clock cycles
+    always_comb deassert_rst_flag_from_fatal = count_deassert_rst_flag_from_fatal == 31;
 
+    assert property (@(posedge core_clk) c_state_apb == S_APB_WR_FUSE_DONE |-> !cptra_error_non_fatal) else begin
+        $error("cptra_error_non_fatal observed during boot up");
+        $finish;
+    end
+    assert property (@(posedge core_clk) c_state_apb == S_APB_WR_FUSE_DONE |-> !cptra_error_fatal) else begin
+        $error("cptra_error_fatal observed during boot up");
+        $finish;
+    end
+
+    always@(negedge core_clk or negedge cptra_rst_b) begin
+        if(!cptra_rst_b) begin
+            mbox_apb_dataout_read_ooo <= 1'b0;
+        end
+        else if(ras_test_ctrl.do_ooo_access) begin
+            mbox_apb_dataout_read_ooo <= 1'b1;
+        end
+        else if (mbox_apb_dataout_read_ooo && (c_state_apb == S_APB_RD_DATAOUT) && (apb_rd_count == dlen)) begin
+            mbox_apb_dataout_read_ooo <= 1'b0;
+        end
+    end
+
+    always@(negedge core_clk or negedge cptra_rst_b) begin
+        if(!cptra_rst_b) begin
+            mbox_apb_dataout_read_no_lock <= 1'b0;
+        end
+        else if(ras_test_ctrl.do_no_lock_access) begin
+            mbox_apb_dataout_read_no_lock <= 1'b1;
+        end
+        else if (mbox_apb_dataout_read_no_lock && (c_state_apb == S_APB_RD_DATAOUT) && (apb_rd_count == dlen)) begin
+            mbox_apb_dataout_read_no_lock <= 1'b0;
+        end
+    end
+
+    always@(negedge core_clk or negedge cptra_rst_b) begin
+        if (!cptra_rst_b) begin
+            mbox_ooo_read_done <= 1'b0;
+        end
+        else if (mbox_apb_dataout_read_ooo && (c_state_apb == S_APB_RD_DATAOUT) && (apb_rd_count == dlen)) begin
+            mbox_ooo_read_done <= 1'b1;
+        end
+        else if (c_state_apb == S_APB_WR_HW_ERROR_NON_FATAL)
+            mbox_ooo_read_done <= 1'b0;
+        else if (ras_test_ctrl.reset_ooo_done_flag)
+            mbox_ooo_read_done <= 1'b0;
+    end
+
+    always@(negedge core_clk or negedge cptra_rst_b) begin
+        if (!cptra_rst_b) begin
+            mbox_no_lock_read_done <= 1'b0;
+        end
+        else if (mbox_apb_dataout_read_no_lock && (c_state_apb == S_APB_RD_DATAOUT) && (apb_rd_count == dlen)) begin
+            mbox_no_lock_read_done <= 1'b1;
+        end
+        else if (c_state_apb == S_APB_WR_HW_ERROR_NON_FATAL)
+            mbox_no_lock_read_done <= 1'b0;
+        else if (ras_test_ctrl.reset_no_lock_done_flag)
+            mbox_no_lock_read_done <= 1'b0;
+    end
+
+    always@(negedge core_clk or negedge cptra_rst_b) begin
+        if (!cptra_rst_b) begin
+            execute_mbox_rx_protocol <= 'b0;
+        end
+        else if (c_state_apb == S_APB_WR_EXEC) begin
+            execute_mbox_rx_protocol <= 'b1;
+        end
+        else if (execute_mbox_rx_protocol && ((c_state_apb == S_APB_RST_EXEC) && apb_xfer_end)) begin
+            execute_mbox_rx_protocol <= 'b0;
+        end
+    end
 
     initial begin
         cptra_pwrgood = 1'b0;
         BootFSM_BrkPoint = 1'b1; //Set to 1 even before anything starts
         cptra_rst_b = 1'b0;
         start_apb_fuse_sequence = 1'b0;
-        //tie offs
-        jtag_tck = 1'b0;    // JTAG clk
-        jtag_tms = 1'b0;    // JTAG TMS
-        jtag_tdi = 1'b0;    // JTAG tdi
-        jtag_trst_n = 1'b0; // JTAG Reset
         //TIE-OFF
         PPROT = '0;
 
@@ -208,25 +396,39 @@ module caliptra_top_tb (
         if($test$plusargs("dumpon")) $dumpvars;
 `endif
 
-        //Key for UDS 
-        cptra_obf_key_uds = 256'h54682728db5035eb04b79645c64a95606abb6ba392b6633d79173c027c5acf77;
-        cptra_uds_tb = 384'he4046d05385ab789c6a72866e08350f93f583e2a005ca0faecc32b5cfc323d461c76c107307654db5566a5bd693e227c;
-
-        //Key for FE
-        cptra_obf_key_fe = 256'h31358e8af34d6ac31c958bbd5c8fb33c334714bffb41700d28b07f11cfe891e7;
-        cptra_fe_tb = {256'hb32e2b171b63827034ebb0d1909f7ef1d51c5f82c1bb9bc26bc4ac4dccdee835,
-                       256'h7dca6154c2510ae1c87b1b422b02b621bb06cac280023894fcff3406af08ee9b,
-                       256'he1dd72419beccddff77c722d992cdcc87e9c7486f56ab406ea608d8c6aeb060c,
-                       256'h64cf2785ad1a159147567e39e303370da445247526d95942bf4d7e88057178b0};
+        if($test$plusargs("RAND_DOE_VALUES")) begin
+            //cptra_obf_key = cptra_obf_key_tb;
+            for (int dword = 0; dword < $bits(cptra_obf_key/32); dword++) begin
+                cptra_obf_key[dword] = cptra_obf_key_tb[dword];
+            end
 
-        //swizzle the key so it matches the endianness of AES block
-        //used for visual inspection of uds/fe flow, manually switching keys and checking both
-        for (int dword = 0; dword < $bits(cptra_obf_key/32); dword++) begin
-            //cptra_obf_key[dword] = cptra_obf_key_uds[dword];
-            cptra_obf_key[dword] = cptra_obf_key_fe[dword];
+            cptra_uds_tb = cptra_uds_rand;
+            cptra_fe_tb = cptra_fe_rand;
+        end
+        else begin
+            //Key for UDS
+            cptra_obf_key_uds = 256'h54682728db5035eb04b79645c64a95606abb6ba392b6633d79173c027c5acf77;
+            cptra_uds_tb = 384'he4046d05385ab789c6a72866e08350f93f583e2a005ca0faecc32b5cfc323d461c76c107307654db5566a5bd693e227c;
+
+            //Key for FE
+            cptra_obf_key_fe = 256'h31358e8af34d6ac31c958bbd5c8fb33c334714bffb41700d28b07f11cfe891e7;
+            cptra_fe_tb = 256'hb32e2b171b63827034ebb0d1909f7ef1d51c5f82c1bb9bc26bc4ac4dccdee835;
+                           /*256'h7dca6154c2510ae1c87b1b422b02b621bb06cac280023894fcff3406af08ee9b,
+                           256'he1dd72419beccddff77c722d992cdcc87e9c7486f56ab406ea608d8c6aeb060c,
+                           256'h64cf2785ad1a159147567e39e303370da445247526d95942bf4d7e88057178b0};*/
+
+            //swizzle the key so it matches the endianness of AES block
+            //used for visual inspection of uds/fe flow, manually switching keys and checking both
+            for (int dword = 0; dword < $bits(cptra_obf_key/32); dword++) begin
+                //cptra_obf_key[dword] = cptra_obf_key_uds[dword];
+                cptra_obf_key[dword] = cptra_obf_key_fe[dword];
+            end
         end
+        
     end
 
+    assign assert_rst_flag   =   assert_rst_flag_from_service ||   assert_rst_flag_from_fatal;
+    assign deassert_rst_flag = deassert_rst_flag_from_service || deassert_rst_flag_from_fatal;
     always @(posedge core_clk) begin
         //Reset/pwrgood assertion during runtime
         if (cycleCnt == 15 || deassert_hard_rst_flag) begin
@@ -244,9 +446,11 @@ module caliptra_top_tb (
         else if (assert_hard_rst_flag) begin
             cptra_pwrgood <= 'b0;
             cptra_rst_b <= 'b0;
+            start_apb_fuse_sequence <= 1'b0;
         end
         else if (assert_rst_flag) begin
             cptra_rst_b <= 'b0;
+            start_apb_fuse_sequence <= 1'b0;
         end
         //wait for fuse indication
         else if (ready_for_fuses == 1'b0) begin
@@ -258,15 +462,26 @@ module caliptra_top_tb (
         end
     end
 
+    always@(negedge core_clk or negedge cptra_rst_b) begin
+        if (!cptra_rst_b) begin
+            dlen <= '0;
+        end
+        else if ((c_state_apb == S_APB_RD_DLEN) && apb_xfer_end) begin
+            dlen <= PRDATA;
+        end
+    end
+
     always@(posedge core_clk or negedge cptra_rst_b) begin
         if (!cptra_rst_b) begin
             c_state_apb  <= S_APB_IDLE;
             apb_wr_count <= '0;
+            apb_rd_count <= '0;
             apb_enable_ph <= 0;
         end
         else begin
             c_state_apb  <= n_state_apb;
             apb_wr_count <= apb_wr_count_nxt;
+            apb_rd_count <= apb_rd_count_nxt;
             //next phase is an access phase if this is setup phase OR it's access and responder isn't ready
             apb_enable_ph <= (PSEL & ~PENABLE) | (PSEL & PENABLE & ~PREADY);
         end
@@ -279,13 +494,19 @@ module caliptra_top_tb (
                 S_APB_WR_FE: begin
                     $display ("SoC: Writing obfuscated Field Entropy to fuse bank\n");
                 end
+                S_APB_WR_SOC_STEPPING_ID: begin
+                    $display ("SoC: Writing SOC Stepping ID to fuse bank\n");
+                end
                 S_APB_WR_FUSE_DONE: begin
                     $display ("SoC: Writing fuse done register\n");
                 end
+                S_APB_POLL_FLOW_ST: begin
+                    $display ("SoC: Polling Flow Status\n");
+                end
                 S_APB_WR_BOOT_GO: begin
                     $display ("SoC: Writing BootGo register\n");
                 end
-                S_APB_WAIT_FW_READY: begin
+                S_APB_WAIT_FW_TEST: begin
                     $display ("CLP: ROM Flow in progress...\n");
                 end
                 S_APB_POLL_LOCK: begin
@@ -310,8 +531,32 @@ module caliptra_top_tb (
                 S_APB_WR_STATUS: begin
                     $display ("SoC: Writing the Mbox Status Register\n");
                 end
+                S_APB_WAIT_ERROR_AXS: begin
+                    $display("SoC: Waiting to see cptra_error_fatal/non_fatal\n");
+                end
+                S_APB_RD_HW_ERROR_FATAL: begin
+                    $display("SoC: Observed cptra_error_fatal; reading Caliptra register\n");
+                end
+                S_APB_WR_HW_ERROR_FATAL: begin
+                    $display("SoC: Observed cptra_error_fatal; writing to clear Caliptra register\n");
+                end
+                S_APB_RD_HW_ERROR_NON_FATAL: begin
+                    $display("SoC: Observed cptra_error_non_fatal; reading Caliptra register\n");
+                end
+                S_APB_WR_HW_ERROR_NON_FATAL: begin
+                    $display("SoC: Observed cptra_error_non_fatal; writing to clear Caliptra register\n");
+                end
                 S_APB_DONE: begin
                 end
+                S_APB_RD_DLEN: begin
+                    $display("SoC: Reading the Data Length Register\n");
+                end
+                S_APB_RD_DATAOUT: begin
+                    $display("SoC: Reading the Data Out Register\n");
+                end
+                S_APB_RST_EXEC: begin
+                    $display("SoC: Resetting the Execute Register\n");
+                end
                 default: begin
                     $display("Entering unexpected APB state: %p", n_state_apb);
                 end
@@ -321,6 +566,7 @@ module caliptra_top_tb (
 
     always_comb begin
         apb_wr_count_nxt = 0;
+        apb_rd_count_nxt = 0;
         case (c_state_apb) inside
             S_APB_IDLE: begin
                 if (start_apb_fuse_sequence)
@@ -330,7 +576,7 @@ module caliptra_top_tb (
             end
             //load fuses
             S_APB_WR_UDS: begin
-                if (apb_xfer_end && apb_wr_count == 11) begin
+                if (apb_xfer_end && apb_wr_count == (`CLP_OBF_UDS_DWORDS-1)) begin
                     n_state_apb = S_APB_WR_FE;
                     apb_wr_count_nxt = '0;
                 end
@@ -344,8 +590,8 @@ module caliptra_top_tb (
                 end
             end
             S_APB_WR_FE: begin
-                if (apb_xfer_end && apb_wr_count == 31) begin
-                    n_state_apb = S_APB_WR_FUSE_DONE;
+                if (apb_xfer_end && apb_wr_count == (`CLP_OBF_FE_DWORDS-1)) begin
+                    n_state_apb = S_APB_WR_SOC_STEPPING_ID;
                     apb_wr_count_nxt = '0;
                 end
                 else if (apb_xfer_end) begin
@@ -357,24 +603,40 @@ module caliptra_top_tb (
                     apb_wr_count_nxt = apb_wr_count;
                 end
             end
+            S_APB_WR_SOC_STEPPING_ID: begin
+                if (apb_xfer_end) begin
+                    n_state_apb = S_APB_WR_FUSE_DONE;
+                end
+                else begin
+                    n_state_apb = S_APB_WR_SOC_STEPPING_ID;
+                end
+            end
             //set fuse done
             S_APB_WR_FUSE_DONE: begin
                 if (apb_xfer_end) begin
                     if(BootFSM_BrkPoint) begin
-                       n_state_apb = S_APB_WR_BOOT_GO;
+                       n_state_apb = S_APB_POLL_FLOW_ST;
                     end
                     else begin
-                       n_state_apb = S_APB_WAIT_FW_READY;
+                       n_state_apb = S_APB_WAIT_FW_TEST;
                     end
                 end
                 else begin
                     n_state_apb = S_APB_WR_FUSE_DONE;
                 end
             end
+            S_APB_POLL_FLOW_ST: begin
+                if (apb_xfer_end && (PRDATA[`SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FUSES_LOW] == 0)) begin
+                    n_state_apb = S_APB_WR_BOOT_GO;
+                end
+                else begin
+                    n_state_apb = S_APB_POLL_FLOW_ST;
+                end
+            end
             //Write BootGo register
             S_APB_WR_BOOT_GO: begin
                 if(apb_xfer_end) begin
-                   n_state_apb = S_APB_WAIT_FW_READY;
+                   n_state_apb = S_APB_WAIT_FW_TEST;
                 end
                 else begin
                    n_state_apb = S_APB_WR_BOOT_GO;
@@ -383,24 +645,27 @@ module caliptra_top_tb (
         
             //This is for Caliptra Demo, smoke tests will stop here since they don't set ready for fw
             //wait for fw req
-            S_APB_WAIT_FW_READY: begin
+            S_APB_WAIT_FW_TEST: begin
                 if (ready_for_fw_push & (apb_wr_count == 5)) begin
                     n_state_apb = S_APB_POLL_LOCK;
                     apb_wr_count_nxt = 0;
                 end
                 else if (ready_for_fw_push) begin
-                    n_state_apb = S_APB_WAIT_FW_READY;
+                    n_state_apb = S_APB_WAIT_FW_TEST;
                     apb_wr_count_nxt = apb_wr_count + 1;
                 end
+                else if (ras_test_ctrl.error_injection_seen) begin
+                    n_state_apb = S_APB_WAIT_ERROR_AXS;
+                end
                 else begin
-                    n_state_apb = S_APB_WAIT_FW_READY;
+                    n_state_apb = S_APB_WAIT_FW_TEST;
                     apb_wr_count_nxt = 0;
                 end
             end
             // poll for lock register
             S_APB_POLL_LOCK: begin
                 if (apb_xfer_end && (PRDATA != 0)) begin
-                    n_state_apb = S_APB_WR_CMD;
+                    n_state_apb = mbox_apb_dataout_read_ooo ? S_APB_RD_DLEN : S_APB_WR_CMD;
                 end
                 else begin
                     n_state_apb = S_APB_POLL_LOCK;
@@ -459,15 +724,98 @@ module caliptra_top_tb (
                 else
                     n_state_apb = S_APB_WR_STATUS;
             end
+            S_APB_WAIT_ERROR_AXS: begin
+                if (cptra_error_fatal_dly_p) begin
+                    n_state_apb = S_APB_RD_HW_ERROR_FATAL;
+                end
+                else if (cptra_error_non_fatal_dly_p) begin
+                    n_state_apb = S_APB_RD_HW_ERROR_NON_FATAL;
+                end
+                else if (soc_ifc_hw_error_wdata) begin
+                    n_state_apb = S_APB_WR_HW_ERROR_FATAL;
+                end
+                else if (ras_test_ctrl.do_no_lock_access) begin
+                    n_state_apb = S_APB_RD_DLEN;
+                end
+                else if (mbox_apb_dataout_read_ooo && !mbox_ooo_read_done) begin
+                    n_state_apb = S_APB_POLL_LOCK;
+                end
+                else begin
+                    n_state_apb = S_APB_WAIT_ERROR_AXS;
+                end
+            end
+            S_APB_RD_HW_ERROR_FATAL: begin
+                // Go to ERROR state to wait for cptra_rst_b to assert
+                if (apb_xfer_end) begin
+                    n_state_apb = S_APB_ERROR;
+                end
+                else begin
+                    n_state_apb = S_APB_RD_HW_ERROR_FATAL;
+                end
+            end
+            S_APB_WR_HW_ERROR_FATAL: begin
+                if (apb_xfer_end) begin
+                    n_state_apb = S_APB_WAIT_ERROR_AXS;
+                end
+                else begin
+                    n_state_apb = S_APB_WR_HW_ERROR_FATAL;
+                end
+            end
+            S_APB_RD_HW_ERROR_NON_FATAL: begin
+                if (apb_xfer_end) begin
+                    n_state_apb = S_APB_WR_HW_ERROR_NON_FATAL;
+                end
+                else begin
+                    n_state_apb = S_APB_RD_HW_ERROR_NON_FATAL;
+                end
+            end
+            S_APB_WR_HW_ERROR_NON_FATAL: begin
+                if (apb_xfer_end) begin
+                    n_state_apb = S_APB_WAIT_ERROR_AXS;
+                end
+                else begin
+                    n_state_apb = S_APB_WR_HW_ERROR_NON_FATAL;
+                end
+            end
             S_APB_DONE: begin
                 apb_wr_count_nxt = '0;
-                if (mailbox_data_avail & ~status_set)
+                apb_rd_count_nxt = '0;
+                if (mailbox_data_avail && execute_mbox_rx_protocol)
+                    n_state_apb = S_APB_RD_DLEN;
+                else if (mailbox_data_avail && ~status_set && ~execute_mbox_rx_protocol)
                     n_state_apb = S_APB_WR_STATUS;
                 else
-                n_state_apb = S_APB_DONE;
+                    n_state_apb = S_APB_DONE;
+            end
+            S_APB_RD_DLEN: begin
+                if (apb_xfer_end)
+                    n_state_apb = S_APB_RD_DATAOUT;
+                else
+                    n_state_apb = S_APB_RD_DLEN;
+            end
+            S_APB_RD_DATAOUT: begin
+                if (apb_xfer_end && (apb_rd_count == dlen)) begin
+                    n_state_apb = (mbox_no_lock_read_done || mbox_ooo_read_done) ? S_APB_WAIT_ERROR_AXS : S_APB_RST_EXEC;
+                    apb_rd_count_nxt = '0;
+                end
+                else if (apb_xfer_end) begin
+                    n_state_apb = S_APB_RD_DATAOUT;
+                    apb_rd_count_nxt = apb_rd_count + 1;
+                end
+                else begin
+                    n_state_apb = S_APB_RD_DATAOUT;
+                    apb_rd_count_nxt = apb_rd_count;
+                end
+            end
+            S_APB_RST_EXEC: begin
+                if (apb_xfer_end)
+                    n_state_apb = S_APB_DONE;
+                else
+                    n_state_apb = S_APB_RST_EXEC;
             end
             default: begin
                 apb_wr_count_nxt = apb_wr_count;
+                apb_rd_count_nxt = apb_rd_count;
                 n_state_apb = S_APB_ERROR;
             end
         endcase
@@ -497,10 +845,18 @@ module caliptra_top_tb (
                 PADDR      = `CLP_SOC_IFC_REG_FUSE_FIELD_ENTROPY_0 + 4 * apb_wr_count;
                 PWDATA     = cptra_fe_tb[apb_wr_count];
             end
+            S_APB_WR_SOC_STEPPING_ID: begin
+                PADDR      = `CLP_SOC_IFC_REG_FUSE_SOC_STEPPING_ID;
+                PWDATA     = $urandom();
+            end
             S_APB_WR_FUSE_DONE: begin
                 PADDR      = `CLP_SOC_IFC_REG_CPTRA_FUSE_WR_DONE;
                 PWDATA     = 32'h00000001;
             end
+            S_APB_POLL_FLOW_ST: begin
+                PADDR      = `CLP_SOC_IFC_REG_CPTRA_FLOW_STATUS; 
+                PWDATA     = '0;
+            end
             S_APB_WR_BOOT_GO: begin
                 PADDR      = `CLP_SOC_IFC_REG_CPTRA_BOOTFSM_GO; 
                 PWDATA     = 32'h00000001;
@@ -529,10 +885,38 @@ module caliptra_top_tb (
                 PADDR      = `CLP_MBOX_CSR_MBOX_STATUS;
                 PWDATA     = 32'h00000001;
             end
+            S_APB_RD_HW_ERROR_FATAL: begin
+                PADDR      = `CLP_SOC_IFC_REG_CPTRA_HW_ERROR_FATAL;
+                PWDATA     = soc_ifc_hw_error_wdata;
+            end
+            S_APB_WR_HW_ERROR_FATAL: begin
+                PADDR      = `CLP_SOC_IFC_REG_CPTRA_HW_ERROR_FATAL;
+                PWDATA     = soc_ifc_hw_error_wdata;
+            end
+            S_APB_RD_HW_ERROR_NON_FATAL: begin
+                PADDR      = `CLP_SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL;
+                PWDATA     = soc_ifc_hw_error_wdata;
+            end
+            S_APB_WR_HW_ERROR_NON_FATAL: begin
+                PADDR      = `CLP_SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL;
+                PWDATA     = soc_ifc_hw_error_wdata;
+            end
             S_APB_DONE: begin
                 PADDR      = '0;
                 PWDATA     = '0;
             end
+            S_APB_RD_DLEN: begin
+                PADDR      = `CLP_MBOX_CSR_MBOX_DLEN;
+                PWDATA     = dlen;
+            end
+            S_APB_RD_DATAOUT: begin
+                PADDR      = `CLP_MBOX_CSR_MBOX_DATAOUT;
+                PWDATA     = '0;
+            end
+            S_APB_RST_EXEC: begin
+                PADDR      = `CLP_MBOX_CSR_MBOX_EXECUTE;
+                PWDATA     = '0;
+            end
             default: begin
                 PADDR      = '0;
                 PWDATA     = '0;
@@ -557,11 +941,21 @@ module caliptra_top_tb (
                 PWRITE     = 1;
                 PAUSER     = 0;
             end
+            S_APB_WR_SOC_STEPPING_ID: begin
+                PSEL       = 1;
+                PWRITE     = 1;
+                PAUSER     = 0;
+            end
             S_APB_WR_FUSE_DONE: begin
                 PSEL       = 1;
                 PWRITE     = 1;
                 PAUSER     = 0;
             end
+            S_APB_POLL_FLOW_ST: begin
+                PSEL       = 1;
+                PWRITE     = 0;
+                PAUSER     = 0;
+            end
             S_APB_WR_BOOT_GO: begin
                 PSEL       = 1;
                 PWRITE     = 1;
@@ -597,11 +991,46 @@ module caliptra_top_tb (
                 PWRITE     = 1;
                 PAUSER     = '1;
             end
+            S_APB_RD_HW_ERROR_FATAL: begin
+                PSEL       = 1;
+                PWRITE     = 0;
+                PAUSER     = '1;
+            end
+            S_APB_WR_HW_ERROR_FATAL: begin
+                PSEL       = 1;
+                PWRITE     = 1;
+                PAUSER     = '1;
+            end
+            S_APB_RD_HW_ERROR_NON_FATAL: begin
+                PSEL       = 1;
+                PWRITE     = 0;
+                PAUSER     = '1;
+            end
+            S_APB_WR_HW_ERROR_NON_FATAL: begin
+                PSEL       = 1;
+                PWRITE     = 1;
+                PAUSER     = '1;
+            end
             S_APB_DONE: begin
                 PSEL       = 0;
                 PWRITE     = 0;
                 PAUSER     = 0;
             end
+            S_APB_RD_DLEN: begin
+                PSEL       = 1;
+                PWRITE     = 0;
+                PAUSER     = '1; //TODO - which value?
+            end
+            S_APB_RD_DATAOUT: begin
+                PSEL       = 1;
+                PWRITE     = 0;
+                PAUSER     = '1;
+            end
+            S_APB_RST_EXEC: begin
+                PSEL       = 1;
+                PWRITE     = 1;
+                PAUSER     = '1;
+            end
             default: begin
                 PSEL       = 0;
                 PWRITE     = 0;
@@ -610,6 +1039,20 @@ module caliptra_top_tb (
         endcase
     end
 
+// JTAG DPI
+jtagdpi #(
+    .Name           ("jtag0"),
+    .ListenPort     (5000)
+) jtagdpi (
+    .clk_i          (core_clk),
+    .rst_ni         (cptra_rst_b),
+    .jtag_tck       (jtag_tck),
+    .jtag_tms       (jtag_tms),
+    .jtag_tdi       (jtag_tdi),
+    .jtag_tdo       (jtag_tdo),
+    .jtag_trst_n    (jtag_trst_n),
+    .jtag_srst_n    ()
+);
 
    //=========================================================================-
    // DUT instance
@@ -638,16 +1081,18 @@ caliptra_top caliptra_top_dut (
     .PWDATA(PWDATA),
     .PWRITE(PWRITE),
 
-    .qspi_clk_o(qspi_clk),
-    .qspi_cs_no(qspi_cs_n),
-    .qspi_d_io(qspi_data),
+    .qspi_clk_o (qspi_clk),
+    .qspi_cs_no (qspi_cs_n),
+    .qspi_d_i   (qspi_data_device_to_host),
+    .qspi_d_o   (qspi_data_host_to_device),
+    .qspi_d_en_o(qspi_data_host_to_device_en),
 
 `ifdef CALIPTRA_INTERNAL_UART
     .uart_tx(uart_loopback),
     .uart_rx(uart_loopback),
 `endif
 
-    .el2_mem_export(el2_mem_export),
+    .el2_mem_export(el2_mem_export.veer_sram_src),
 
     .ready_for_fuses(ready_for_fuses),
     .ready_for_fw_push(ready_for_fw_push),
@@ -668,8 +1113,8 @@ caliptra_top caliptra_top_dut (
     .BootFSM_BrkPoint(BootFSM_BrkPoint),
 
     //SoC Interrupts
-    .cptra_error_fatal    (),
-    .cptra_error_non_fatal(),
+    .cptra_error_fatal    (cptra_error_fatal    ),
+    .cptra_error_non_fatal(cptra_error_non_fatal),
 
 `ifdef CALIPTRA_INTERNAL_TRNG
     .etrng_req             (etrng_req),
@@ -684,8 +1129,8 @@ caliptra_top caliptra_top_dut (
     .generic_input_wires(generic_input_wires),
     .generic_output_wires(),
 
-    .security_state(security_state), //FIXME TIE-OFF
-    .scan_mode     (scan_mode) //FIXME TIE-OFF
+    .security_state(security_state),
+    .scan_mode     (scan_mode)
 );
 
 
@@ -705,6 +1150,15 @@ physical_rng physical_rng (
     //=========================================================================-
     // SPI Flash
     //=========================================================================-
+for (genvar ii = 0; ii < `CALIPTRA_QSPI_IO_WIDTH; ii += 1) begin: gen_qspi_io
+  assign qspi_data[ii] = qspi_data_host_to_device_en[ii]
+      ? qspi_data_host_to_device[ii]
+      : 1'bz;
+  assign qspi_data_device_to_host[ii] = qspi_data_host_to_device_en[ii]
+      ? 1'bz
+      : qspi_data[ii];
+end
+
 localparam logic [15:0] DeviceId0 = 16'hF10A;
 localparam logic [15:0] DeviceId1 = 16'hF10B;
 
@@ -739,7 +1193,7 @@ caliptra_top_tb_services #(
     .cptra_rst_b(cptra_rst_b),
 
     // Caliptra Memory Export Interface
-    .el2_mem_export (el2_mem_export),
+    .el2_mem_export (el2_mem_export.veer_sram_sink),
 
     //SRAM interface for mbox
     .mbox_sram_cs   (mbox_sram_cs   ),
@@ -760,6 +1214,7 @@ caliptra_top_tb_services #(
     .scan_mode(scan_mode),
 
     // TB Controls
+    .ras_test_ctrl(ras_test_ctrl),
     .cycleCnt(cycleCnt),
 
     //Interrupt flags
@@ -769,15 +1224,16 @@ caliptra_top_tb_services #(
     //Reset flags
     .assert_hard_rst_flag(assert_hard_rst_flag),
     .deassert_hard_rst_flag(deassert_hard_rst_flag),
-    .assert_rst_flag(assert_rst_flag),
-    .deassert_rst_flag(deassert_rst_flag)
+
+    .assert_rst_flag(assert_rst_flag_from_service),
+    .deassert_rst_flag(deassert_rst_flag_from_service),
+    
+    .cptra_uds_tb(cptra_uds_rand),
+    .cptra_fe_tb(cptra_fe_rand),
+    .cptra_obf_key_tb(cptra_obf_key_tb)
 
 );
 
 caliptra_top_sva sva();
 
-`ifndef VERILATOR
-soc_ifc_cov_bind i_soc_ifc_cov_bind();
-`endif
-
 endmodule
diff --git a/src/integration/tb/caliptra_top_tb_pkg.sv b/src/integration/tb/caliptra_top_tb_pkg.sv
index d29a48268..8a14afeb7 100644
--- a/src/integration/tb/caliptra_top_tb_pkg.sv
+++ b/src/integration/tb/caliptra_top_tb_pkg.sv
@@ -41,9 +41,38 @@ class bitflip_mask_generator #(int MBOX_DATA_AND_ECC_W = 39);
 
 endclass
 `else
-function logic [soc_ifc_pkg::MBOX_DATA_AND_ECC_W-1:0] get_bitflip_mask(bit do_double_bit = 1'b0);
+function static logic [soc_ifc_pkg::MBOX_DATA_AND_ECC_W-1:0] get_bitflip_mask(bit do_double_bit = 1'b0);
     return 2<<($urandom%(soc_ifc_pkg::MBOX_DATA_AND_ECC_W-2)) | soc_ifc_pkg::MBOX_DATA_AND_ECC_W'(do_double_bit);
 endfunction
 `endif
 
+typedef struct packed {
+    //  [3] - Double bit, DCCM Error Injection
+    //  [2] - Single bit, DCCM Error Injection
+    //  [1] - Double bit, ICCM Error Injection
+    //  [0] - Single bit, ICCM Error Injection
+    logic dccm_double_bit_error;
+    logic dccm_single_bit_error;
+    logic iccm_double_bit_error;
+    logic iccm_single_bit_error;
+} veer_sram_error_injection_mode_t;
+
+typedef struct packed {
+    logic error_injection_seen;
+    logic reset_generic_input_wires;
+    logic do_no_lock_access;
+    logic do_ooo_access;
+    logic reset_ooo_done_flag;
+    logic reset_no_lock_done_flag;
+} ras_test_ctrl_t;
+
+// Values to drive onto GENERIC INPUT WIRES in response to RAS testing
+localparam MBOX_NON_FATAL_OBSERVED         = 32'h600dab1e;
+localparam PROT_NO_LOCK_NON_FATAL_OBSERVED = 32'h600dbabe;
+localparam PROT_OOO_NON_FATAL_OBSERVED     = 32'h600dcafe;
+localparam ICCM_FATAL_OBSERVED             = 32'hdeadaca1;
+localparam DCCM_FATAL_OBSERVED             = 32'hdeadbeef;
+localparam NMI_FATAL_OBSERVED              = 32'hdeadc0a7;
+localparam ERROR_NONE_SET                  = 32'hba5eba11; /* default value for a test with no activity observed by TB */
+
 endpackage
diff --git a/src/integration/tb/caliptra_top_tb_services.sv b/src/integration/tb/caliptra_top_tb_services.sv
index dcc39632b..e274b6565 100644
--- a/src/integration/tb/caliptra_top_tb_services.sv
+++ b/src/integration/tb/caliptra_top_tb_services.sv
@@ -36,26 +36,27 @@
 module caliptra_top_tb_services 
     import soc_ifc_pkg::*; 
     import kv_defines_pkg::*;
+    import caliptra_top_tb_pkg::*;
 #(
     parameter UVM_TB = 0
 ) (
-    input logic                        clk,
+    input wire logic                   clk,
 
-    input logic                        cptra_rst_b,
+    input wire logic                   cptra_rst_b,
 
     // Caliptra Memory Export Interface
-    el2_mem_if.top                     el2_mem_export,
+    el2_mem_if.veer_sram_sink          el2_mem_export,
 
     //SRAM interface for mbox
-    input  logic mbox_sram_cs,
-    input  logic mbox_sram_we,
-    input  logic [MBOX_ADDR_W-1:0] mbox_sram_addr,
-    input  logic [MBOX_DATA_AND_ECC_W-1:0] mbox_sram_wdata,
-    output logic [MBOX_DATA_AND_ECC_W-1:0] mbox_sram_rdata,
+    input  wire logic mbox_sram_cs,
+    input  wire logic mbox_sram_we,
+    input  wire logic [MBOX_ADDR_W-1:0] mbox_sram_addr,
+    input  wire logic [MBOX_DATA_AND_ECC_W-1:0] mbox_sram_wdata,
+    output wire logic [MBOX_DATA_AND_ECC_W-1:0] mbox_sram_rdata,
 
     //SRAM interface for imem
-    input  logic imem_cs,
-    input  logic [`CALIPTRA_IMEM_ADDR_WIDTH-1:0] imem_addr,
+    input  wire logic imem_cs,
+    input  wire logic [`CALIPTRA_IMEM_ADDR_WIDTH-1:0] imem_addr,
     output logic [`CALIPTRA_IMEM_DATA_WIDTH-1:0] imem_rdata,
 
     // Security State
@@ -65,6 +66,7 @@ module caliptra_top_tb_services
     output logic scan_mode,
 
     // TB Controls
+    output var   ras_test_ctrl_t ras_test_ctrl,
     output int   cycleCnt,
 
     //Interrupt flags
@@ -75,14 +77,17 @@ module caliptra_top_tb_services
     output logic assert_hard_rst_flag,
     output logic assert_rst_flag,
     output logic deassert_hard_rst_flag,
-    output logic deassert_rst_flag
+    output logic deassert_rst_flag,
+
+    output logic [0:`CLP_OBF_UDS_DWORDS-1][31:0] cptra_uds_tb,
+    output logic [0:`CLP_OBF_FE_DWORDS-1] [31:0] cptra_fe_tb,
+    output logic [0:`CLP_OBF_KEY_DWORDS-1][31:0] cptra_obf_key_tb
 
 );
 
    //=========================================================================-
    // Imports
    //=========================================================================-
-    import caliptra_top_tb_pkg::*;
 
    //=========================================================================-
    // Parameters
@@ -107,6 +112,8 @@ module caliptra_top_tb_services
     parameter MEMTYPE_LMEM = 3'h1;
     parameter MEMTYPE_DCCM = 3'h2;
     parameter MEMTYPE_ICCM = 3'h3;
+    parameter DATA_WIDTH = 32;
+    localparam IV_NO = 128 / DATA_WIDTH;
 
    //=========================================================================-
    // Signals
@@ -128,6 +135,7 @@ module caliptra_top_tb_services
     logic [MBOX_DATA_AND_ECC_W-1:0] mbox_sram_wdata_bitflip;
     int cycleCntKillReq;
 
+    int                         cycleCnt_ff;
     int                         rst_cyclecnt = 0;
     int                         wait_time_to_rst;
 
@@ -144,10 +152,26 @@ module caliptra_top_tb_services
     logic                       inject_random_data;
     logic                       check_pcr_signing;
 
+    // Decode:
+    //  [0] - Single bit, ICCM Error Injection
+    //  [1] - Double bit, ICCM Error Injection
+    //  [2] - Single bit, DCCM Error Injection
+    //  [3] - Double bit, DCCM Error Injection
+    veer_sram_error_injection_mode_t sram_error_injection_mode;
+    // Decode:
+    //  [0] - Single bit, Mailbox Error Injection
+    //  [1] - Double bit, Mailbox Error Injection
+    logic [1:0]                 inject_mbox_sram_error = 2'b0;
+
     logic                       set_wdt_timer1_period;
     logic                       set_wdt_timer2_period;
     logic                       reset_wdt_timer_period;
 
+    logic                       inject_zero_sign_r;
+    logic                       inject_zero_sign_r_needs_release;
+
+    logic                       en_jtag_access;
+
     typedef bit  [0:11][31:0]   operand_t;
 
     typedef struct packed {
@@ -174,6 +198,20 @@ module caliptra_top_tb_services
 
     test_vector_t test_vector;
 
+    typedef struct packed {
+          logic [0:`CLP_OBF_KEY_DWORDS-1][31:0] obf_key_uds;
+          logic [0:IV_NO-1][31:0] iv_uds;
+          logic [0:`CLP_OBF_UDS_DWORDS-1][31:0] uds_plaintext;
+          logic [0:`CLP_OBF_UDS_DWORDS-1][31:0] uds_ciphertext;
+
+          logic [0:`CLP_OBF_KEY_DWORDS-1][31:0] obf_key_fe;
+          logic [0:IV_NO-1][31:0] iv_fe;
+          logic [0:`CLP_OBF_FE_DWORDS-1] [31:0] fe_plaintext;
+          logic [0:`CLP_OBF_FE_DWORDS-1] [31:0] fe_ciphertext;
+    } doe_test_vector_t;
+
+    doe_test_vector_t doe_test_vector;
+
 // Upwards name referencing per 23.8 of IEEE 1800-2017
 `define DEC caliptra_top_dut.rvtop.veer.dec
 
@@ -195,14 +233,30 @@ module caliptra_top_tb_services
     //         8'h90        - Issue PCR singing with fixed vector   
     //         8'h91        - Issue PCR singing with randomized vector
     //         8'h92        - Check PCR singing with randomized vector   
+    //         8'h98        - Inject invalid zero sign_r into ECC 
+    //         8'h99        - Inject zeroize into HMAC
     //         8'ha0: 8'ha7 - Inject HMAC_KEY to kv_key register
     //         8'hc0: 8'hc7 - Inject SHA_BLOCK to kv_key register
+    //         8'he0        - Set random ICCM SRAM single bit error injection
+    //         8'he1        - Set random ICCM SRAM double bit error injection
+    //         8'he2        - Set random DCCM SRAM single bit error injection
+    //         8'he3        - Set random DCCM SRAM double bit error injection
+    //         8'he4        - Disable all SRAM error injection (Mailbox, ICCM, DCCM)
+    //         8'he5        - Request TB to initiate Mailbox flow without lock (violation)
+    //         8'he6        - Request TB to initiate Mailbox flow with out-of-order accesses (violation)
+    //         8'he7        - Reset mailbox out-of-order flag when non-fatal error is masked (allows the test to continue)
+    //         8'he8        - Enable scan mode when DOE fsm transitions to done state
+    //         8'he9        - Force dmi_reg_en input to clk gate to emulate JTAG accesses
+    //         8'hea        - Set random values to WDT timer1 and timer2
+    //         8'heb        - Inject fatal error
+    //         8'hec        - Inject randomized UDS test vector
+    //         8'hed        - Inject randomized FE test vector
     //         8'hee        - Issue random warm reset
     //         8'hef        - Enable scan mode
     //         8'hf0        - Disable scan mode
     //         8'hf1        - Release WDT timer periods so they can be set by the test
     //         8'hf2        - Force clk_gating_en (to use in smoke_test only)
-    //         8'hf3        - Make two clients write to KV
+    //         8'hf3        - Init PCR slot 31
     //         8'hf4        - Write random data to KV entry0
     //         8'hf5        - Issue cold reset
     //         8'hf6        - Issue warm reset
@@ -212,8 +266,8 @@ module caliptra_top_tb_services
     //         8'hfa        - Unlock debug in security state
     //         8'hfb        - Set the isr_active bit
     //         8'hfc        - Clear the isr_active bit
-    //         8'hfd        - Toggle random SRAM single bit error injection
-    //         8'hfe        - Toggle random SRAM double bit error injection
+    //         8'hfd        - Set random Mailbox SRAM single bit error injection
+    //         8'hfe        - Set random Mailbox SRAM double bit error injection
     //         8'hff        - End the simulation with a Success status
     assign mailbox_write = caliptra_top_dut.soc_ifc_top1.i_soc_ifc_reg.field_combo.CPTRA_GENERIC_OUTPUT_WIRES[0].generic_wires.load_next;
     assign WriteData = caliptra_top_dut.soc_ifc_top1.i_soc_ifc_reg.field_combo.CPTRA_GENERIC_OUTPUT_WIRES[0].generic_wires.next;
@@ -234,16 +288,67 @@ module caliptra_top_tb_services
             isr_active++;
         end
     end
-    logic [1:0] inject_rand_sram_error = 2'b0;
-    always @(negedge clk) begin
-        if ((WriteData[7:0] == 8'hfd) && mailbox_write) begin
-            inject_rand_sram_error ^= 2'b01;
+    always @(negedge clk or negedge cptra_rst_b) begin
+        if      (!cptra_rst_b)                               inject_mbox_sram_error <= 2'b00;
+        else if ((WriteData[7:0] == 8'hfd) && mailbox_write) inject_mbox_sram_error <= 2'b01;
+        else if ((WriteData[7:0] == 8'hfe) && mailbox_write) inject_mbox_sram_error <= 2'b10;
+        else if ((WriteData[7:0] == 8'he4) && mailbox_write) inject_mbox_sram_error <= 2'b00;
+    end
+    always @(negedge clk or negedge cptra_rst_b) begin
+        if      (!cptra_rst_b)                               sram_error_injection_mode                       <= '{default: 1'b0};
+        else if ((WriteData[7:0] == 8'he0) && mailbox_write) sram_error_injection_mode.iccm_single_bit_error <= 1'b1;
+        else if ((WriteData[7:0] == 8'he1) && mailbox_write) sram_error_injection_mode.iccm_double_bit_error <= 1'b1;
+        else if ((WriteData[7:0] == 8'he2) && mailbox_write) sram_error_injection_mode.dccm_single_bit_error <= 1'b1;
+        else if ((WriteData[7:0] == 8'he3) && mailbox_write) sram_error_injection_mode.dccm_double_bit_error <= 1'b1;
+        else if ((WriteData[7:0] == 8'he4) && mailbox_write) sram_error_injection_mode                       <= '{default: 1'b0};
+    end
+
+    always @(negedge clk or negedge cptra_rst_b) begin
+        if (!cptra_rst_b) begin
+            ras_test_ctrl.do_no_lock_access     <= 1'b0;
+            ras_test_ctrl.do_ooo_access         <= 1'b0;
+            ras_test_ctrl.reset_ooo_done_flag   <= 1'b0;
+            ras_test_ctrl.reset_no_lock_done_flag   <= 1'b0;
+        end
+        else if((WriteData == 8'he5) && mailbox_write) begin
+            ras_test_ctrl.do_no_lock_access     <= 1'b1;
+            ras_test_ctrl.do_ooo_access         <= 1'b0;
+            ras_test_ctrl.reset_ooo_done_flag   <= 1'b0;
+            ras_test_ctrl.reset_no_lock_done_flag   <= 1'b0;
         end
-        else if ((WriteData[7:0] == 8'hfe) && mailbox_write) begin
-            inject_rand_sram_error ^= 2'b10;
+        else if((WriteData == 8'he6) && mailbox_write) begin
+            ras_test_ctrl.do_no_lock_access     <= 1'b0;
+            ras_test_ctrl.do_ooo_access         <= 1'b1;
+            ras_test_ctrl.reset_ooo_done_flag   <= 1'b0;
+            ras_test_ctrl.reset_no_lock_done_flag   <= 1'b0;
+        end
+        else if ((WriteData == 8'he7) && mailbox_write) begin
+            ras_test_ctrl.do_no_lock_access     <= 1'b0;
+            ras_test_ctrl.do_ooo_access         <= 1'b0;
+            ras_test_ctrl.reset_ooo_done_flag   <= 1'b1;
+            ras_test_ctrl.reset_no_lock_done_flag   <= 1'b1;
+        end
+        else begin
+            ras_test_ctrl.do_no_lock_access     <= 1'b0;
+            ras_test_ctrl.do_ooo_access         <= 1'b0;
+            ras_test_ctrl.reset_ooo_done_flag   <= 1'b0;
+            ras_test_ctrl.reset_no_lock_done_flag   <= 1'b0;
         end
     end
 
+    initial ras_test_ctrl.error_injection_seen = 1'b0;
+    always @(negedge clk) begin
+        if (mailbox_write && WriteData[7:0] == 8'hfd) begin
+            ras_test_ctrl.error_injection_seen <= 1'b1;
+        end
+    end
+    // When starting a new error injection test, reset generic_input wires to the idle value.
+    // New values will be loaded to reflect the result of the RAS test.
+    initial ras_test_ctrl.reset_generic_input_wires = 1'b0;
+    always@(negedge clk) begin
+        ras_test_ctrl.reset_generic_input_wires <= mailbox_write && (WriteData[7:0] inside {8'he0, 8'he1, 8'he2, 8'he3, 8'hfd, 8'hfe});
+    end
+
     //keyvault injection hooks
     //Inject data to KV key reg
     logic [0:11][31:0]   ecc_seed_tb    = 384'h8FA8541C82A392CA74F23ED1DBFD73541C5966391B97EA73D744B0E34B9DF59ED0158063E39C09A5A055371EDF7A5441;
@@ -341,8 +446,35 @@ module caliptra_top_tb_services
     endgenerate
     
 
+    always@(posedge clk or negedge cptra_rst_b) begin
+        if (~cptra_rst_b) begin
+            inject_zero_sign_r <= 1'b0;
+            inject_zero_sign_r_needs_release <= 1'b0;
+        end
+        else if((WriteData[7:0] == 8'h98) && mailbox_write) begin
+            inject_zero_sign_r <= 1'b1;
+        end
+        else if(inject_zero_sign_r) begin
+            if (caliptra_top_dut.ecc_top1.ecc_dsa_ctrl_i.prog_instr.reg_id == 6'd21) begin //R_ID
+                force caliptra_top_dut.ecc_top1.ecc_dsa_ctrl_i.ecc_arith_unit_i.d_o = '0;
+                inject_zero_sign_r_needs_release <= 1'b1;
+            end
+            else if (inject_zero_sign_r_needs_release) begin
+                inject_zero_sign_r <= 1'b0;
+            end
+        end
+        else begin
+            release caliptra_top_dut.ecc_top1.ecc_dsa_ctrl_i.ecc_arith_unit_i.d_o;
+        end
+    end
+
     //TIE-OFF device lifecycle
-    initial security_state = '{device_lifecycle: DEVICE_PRODUCTION, debug_locked: 1'b1};
+    logic assert_ss_tran;
+`ifdef CALIPTRA_DEBUG_UNLOCKED
+    initial security_state = '{device_lifecycle: DEVICE_PRODUCTION, debug_locked: 1'b0}; // DebugUnlocked & Production
+`else
+    initial security_state = '{device_lifecycle: DEVICE_PRODUCTION, debug_locked: 1'b1}; // DebugLocked & Production
+`endif
     always @(negedge clk) begin
         //lock debug mode
         if ((WriteData[7:0] == 8'hf9) && mailbox_write) begin
@@ -351,15 +483,56 @@ module caliptra_top_tb_services
         end
         //unlock debug mode
         else if ((WriteData[7:0] == 8'hfa) && mailbox_write) begin
-            security_state.debug_locked <= 1'b0;
+            cycleCnt_ff <= cycleCnt;
+            assert_ss_tran <= 'b1;
+            //security_state.debug_locked <= 1'b0;
             if (UVM_TB) $warning("WARNING! Detected FW write to manually clear security_state.debug_locked, but Firmware can't do this in UVM. Use a sequence in the soc_ifc_ctrl_agent to modify this field.");
         end
+        else if(assert_ss_tran && (cycleCnt == cycleCnt_ff + 'd100)) begin
+            security_state.debug_locked <= 1'b0;
+            assert_ss_tran <= 'b0;
+        end
     end
+    
+    generate
+        for(genvar dword = 0; dword < IV_NO; dword++) begin
+    always@(negedge clk) begin
+        if ((WriteData[7:0] == 8'hec) && mailbox_write) begin
+            force caliptra_top_dut.doe.doe_inst.hwif_out.DOE_IV[dword].IV.swmod = 'b1;
+            force caliptra_top_dut.doe.doe_inst.i_doe_reg.field_storage.DOE_IV[dword].IV.value = doe_test_vector.iv_uds[dword];
+        end
+        else if ((WriteData[7:0] == 8'hed) && mailbox_write) begin
+            force caliptra_top_dut.doe.doe_inst.hwif_out.DOE_IV[dword].IV.swmod = 'b1;
+            force caliptra_top_dut.doe.doe_inst.i_doe_reg.field_storage.DOE_IV[dword].IV.value = doe_test_vector.iv_fe[dword];
+        end
+        else begin
+            release caliptra_top_dut.doe.doe_inst.hwif_out.DOE_IV[dword].IV.swmod;
+            release caliptra_top_dut.doe.doe_inst.i_doe_reg.field_storage.DOE_IV[dword].IV.value;
+        end
+    end
+end //for
+endgenerate //IV_NO
 
+    logic assert_scan_mode;
+    logic assert_scan_mode_doe_done;
     always @(negedge clk) begin
         //Enable scan mode
         if ((WriteData[7:0] == 8'hef) && mailbox_write) begin
+            cycleCnt_ff <= cycleCnt;
+            assert_scan_mode <= 'b1;
+            //scan_mode <= 1'b1;
+        end
+        else if ((WriteData[7:0] == 8'he8) && mailbox_write) begin
+            cycleCnt_ff <= cycleCnt;
+            assert_scan_mode_doe_done <= 'b1;
+        end
+        else if(assert_scan_mode && (cycleCnt == cycleCnt_ff + 'd100)) begin
             scan_mode <= 1'b1;
+            assert_scan_mode <= 'b0;
+        end
+        else if (assert_scan_mode_doe_done && (caliptra_top_dut.doe.doe_inst.doe_fsm1.kv_doe_fsm_ps == 'h5)) begin
+            scan_mode <= 1'b1;
+            assert_scan_mode <= 'b0;
         end
         //Disable scan mode
         else if ((WriteData[7:0] == 8'hf0) && mailbox_write) begin
@@ -374,6 +547,70 @@ module caliptra_top_tb_services
         end
     end
 
+    always@(negedge clk) begin
+        if ((WriteData == 'he9) && mailbox_write) begin
+            cycleCnt_ff <= cycleCnt;
+            en_jtag_access <= 'b1;
+        end
+        else if(en_jtag_access && (cycleCnt == (cycleCnt_ff + 'd100))) begin
+            force caliptra_top_dut.cptra_dmi_reg_en_preQ = 1;
+        end
+        else if(en_jtag_access && (cycleCnt == (cycleCnt_ff + 'd150))) begin
+            release caliptra_top_dut.cptra_dmi_reg_en_preQ;
+            en_jtag_access <= 'b0;
+        end
+    end
+    
+    logic inject_zeroize_to_hmac;
+    logic inject_zeroize_to_hmac_cmd;
+    logic [3 : 0] inject_zeroize_to_hmac_cnt;
+    always@(posedge clk or negedge cptra_rst_b) begin
+        if (~cptra_rst_b) begin
+            inject_zeroize_to_hmac_cmd <= 1'b0;
+            inject_zeroize_to_hmac <= 1'b0;
+            inject_zeroize_to_hmac_cnt <= '0;
+        end
+        else if((WriteData == 'h99) && mailbox_write) begin
+            inject_zeroize_to_hmac_cmd <= 1'b1;
+        end
+        else if (inject_zeroize_to_hmac_cmd) begin
+            if (caliptra_top_dut.hmac.hmac_inst.core_tag_we) begin
+                inject_zeroize_to_hmac <= 1'b1;
+            end
+            if (inject_zeroize_to_hmac) begin
+                if (inject_zeroize_to_hmac_cnt < 4'hf) begin
+                    inject_zeroize_to_hmac_cnt <= inject_zeroize_to_hmac_cnt + 1'b1;
+                end
+            end
+        end
+    end
+    always@(negedge clk) begin
+        if (inject_zeroize_to_hmac) begin
+            if (inject_zeroize_to_hmac_cnt == 4'h5) begin
+                force caliptra_top_dut.hmac.hmac_inst.i_hmac_reg.field_storage.HMAC384_CTRL.ZEROIZE.value = 1'b1;
+            end
+            else begin
+                release caliptra_top_dut.hmac.hmac_inst.i_hmac_reg.field_storage.HMAC384_CTRL.ZEROIZE.value;
+            end
+        end
+    end
+
+    //Inject fatal error after a delay
+    logic inject_fatal_error;
+    always@(negedge clk) begin
+        if((WriteData == 'heb) && mailbox_write) begin
+            cycleCnt_ff <= cycleCnt;
+            inject_fatal_error <= 'b1;
+        end
+        else if(inject_fatal_error && (cycleCnt == cycleCnt_ff + 'd100)) begin
+            force caliptra_top_dut.cptra_error_fatal = 'b1;
+        end
+        else if(inject_fatal_error && (cycleCnt == cycleCnt_ff + 'd200)) begin
+            release caliptra_top_dut.cptra_error_fatal;
+            inject_fatal_error <= 'b0;
+        end
+    end
+
     logic [0:11][31:0] pv_hash_value = {32'h11143121,
     32'hbeb365e6,
     32'h3826e7de,
@@ -409,6 +646,41 @@ module caliptra_top_tb_services
         end
     endgenerate
 
+    task doe_testvector_generator();
+        string file_name;
+        int fd_r;
+        string line_read;
+
+        $system("python doe_test_gen.py");
+        file_name = "doe_test_vector.txt";
+        if(!UVM_TB) begin
+            fd_r = $fopen(file_name, "r");
+            if(fd_r == 0) $error("Cannot open file %s for reading", file_name);
+
+            //Get values from file
+            void'($fgets(line_read, fd_r));
+            void'($sscanf(line_read, "%h", doe_test_vector.obf_key_uds));
+            void'($fgets(line_read, fd_r));
+            void'($sscanf(line_read, "%h", doe_test_vector.iv_uds));
+            void'($fgets(line_read, fd_r));
+            void'($sscanf(line_read, "%h", doe_test_vector.uds_plaintext));
+            void'($fgets(line_read, fd_r));
+            void'($sscanf(line_read, "%h", doe_test_vector.uds_ciphertext));
+
+            void'($fgets(line_read, fd_r));
+            void'($sscanf(line_read, "%h", doe_test_vector.obf_key_fe));
+            void'($fgets(line_read, fd_r));
+            void'($sscanf(line_read, "%h", doe_test_vector.iv_fe));
+            void'($fgets(line_read, fd_r));
+            void'($sscanf(line_read, "%h", doe_test_vector.fe_plaintext));
+            void'($fgets(line_read, fd_r));
+            void'($sscanf(line_read, "%h", doe_test_vector.fe_ciphertext));
+
+            $fclose(fd_r);
+        end
+
+    endtask
+
     task ecc_testvector_generator ();
         string    file_name;
         begin
@@ -420,7 +692,7 @@ module caliptra_top_tb_services
         end
     endtask // ecc_test
 
-    task ecc_read_test_vectors (input string fname);
+    task static ecc_read_test_vectors (input string fname);
         integer values_per_test_vector;
         int fd_r;
         string line_read;
@@ -501,7 +773,7 @@ module caliptra_top_tb_services
             timed_warm_rst <= 'b1;
         end
         else if((WriteData == 'hee) && mailbox_write) begin
-            wait_time_to_rst =$urandom_range(5,1000);
+            wait_time_to_rst = $urandom_range(5,100);
             prandom_warm_rst <= 'b1;
             rst_cyclecnt <= cycleCnt;
         end
@@ -596,11 +868,13 @@ module caliptra_top_tb_services
             set_wdt_timer2_period <= 'b0;
         end
         else begin
-            if(caliptra_top_dut.soc_ifc_top1.i_wdt.wdt_timer1_timeout_serviced) begin
-                set_wdt_timer1_period <= 'b1;
-            end
-            if(caliptra_top_dut.soc_ifc_top1.i_wdt.wdt_timer2_timeout_serviced) begin
-                set_wdt_timer2_period <= 'b1;
+            if (!UVM_TB) begin
+                if(caliptra_top_dut.soc_ifc_top1.i_wdt.wdt_timer1_timeout_serviced) begin
+                    set_wdt_timer1_period <= 'b1;
+                end
+                if(caliptra_top_dut.soc_ifc_top1.i_wdt.wdt_timer2_timeout_serviced) begin
+                    set_wdt_timer2_period <= 'b1;
+                end
             end
             if(reset_wdt_timer_period) begin
                 set_wdt_timer1_period <= 'b0;
@@ -613,30 +887,40 @@ module caliptra_top_tb_services
         if(set_wdt_timer1_period) begin
             force caliptra_top_dut.soc_ifc_top1.timer1_timeout_period = 64'hFFFFFFFF_FFFFFFFF;
         end
-        else begin
+        else if(reset_wdt_timer_period) begin
             release caliptra_top_dut.soc_ifc_top1.timer1_timeout_period;
         end
+
         if(set_wdt_timer2_period) begin
             force caliptra_top_dut.soc_ifc_top1.timer2_timeout_period = 64'hFFFFFFFF_FFFFFFFF;
         end
-        else begin
+        else if(reset_wdt_timer_period) begin
             release caliptra_top_dut.soc_ifc_top1.timer2_timeout_period;
         end
+
+    end
+
+    always @(negedge clk) begin
+        if((WriteData[7:0] == 8'hea) && mailbox_write) begin
+            force caliptra_top_dut.soc_ifc_top1.timer1_timeout_period = {32'h0000_0000, $urandom_range(32'h0000_0001,32'h0000_0FFF)};
+            force caliptra_top_dut.soc_ifc_top1.timer2_timeout_period = {32'h0000_0000, $urandom_range(32'h0000_0001,32'h0000_0FFF)};
+        end
+        //Use 'hF1 code to reset these values in the test
     end
 
 
     `ifndef VERILATOR
         initial begin
-            bitflip_mask_generator #(MBOX_DATA_AND_ECC_W) bitflip_gen = new();
+            automatic bitflip_mask_generator #(MBOX_DATA_AND_ECC_W) bitflip_gen = new();
             forever begin
                 @(posedge clk)
-                if (~|inject_rand_sram_error) begin
+                if (~|inject_mbox_sram_error) begin
                     mbox_sram_wdata_bitflip <= '0;
                 end
                 else if (mbox_sram_cs & mbox_sram_we) begin
                     // Corrupt 10% of the writes
                     flip_bit = $urandom_range(0,99) < 10;
-                    mbox_sram_wdata_bitflip <= flip_bit ? bitflip_gen.get_mask(inject_rand_sram_error[1]) : '0;
+                    mbox_sram_wdata_bitflip <= flip_bit ? bitflip_gen.get_mask(inject_mbox_sram_error[1]) : '0;
 //                    if (flip_bit) $display("%t Injecting bit flips", $realtime);
 //                    else          $display("%t No bit flips injected", $realtime);
                 end
@@ -644,13 +928,14 @@ module caliptra_top_tb_services
         end
     `else
         always @(posedge clk) begin
-            // Corrupt 10% of the writes
-            flip_bit <= ($urandom % 100) < 10;
-            if (~|inject_rand_sram_error) begin
+            if (~|inject_mbox_sram_error) begin
+                flip_bit <= 0;
                 mbox_sram_wdata_bitflip <= '0;
             end
             else if (mbox_sram_cs & mbox_sram_we) begin
-                mbox_sram_wdata_bitflip <= flip_bit ? get_bitflip_mask(inject_rand_sram_error[1]) : '0;
+                // Corrupt 10% of the writes
+                flip_bit <= ($urandom % 100) < 10;
+                mbox_sram_wdata_bitflip <= flip_bit ? get_bitflip_mask(inject_mbox_sram_error[1]) : '0;
             end
         end
     `endif
@@ -683,7 +968,7 @@ module caliptra_top_tb_services
         // uvm tests/sequences
         // End Of test monitor
         if(mailbox_write && WriteData[7:0] == 8'hff) begin
-            if (UVM_TB) $warning("WARNING! Detected FW write to manually end the test with SUCCESS, but Firmware can't do this in UVM.");
+            if (UVM_TB) $info("INFO: Detected FW write to manually end the test with SUCCESS; ignoring since the UVM environment will handle this.");
             else if (|cycleCntKillReq) begin
                 $error("ERROR! FW attempted to end the simulation with SUCCESS after previously requesting to end the sim with FAILURE!");
             end
@@ -821,7 +1106,7 @@ module caliptra_top_tb_services
         dummy_dccm_preloader.ram = '{default:8'h0};
         `endif
         hex_file_is_empty = $system("test -s program.hex");
-        if (!hex_file_is_empty) $readmemh("program.hex",  imem_inst1.ram,0,32'h00007FFF);
+        if (!hex_file_is_empty) $readmemh("program.hex",  imem_inst1.ram,0,`CALIPTRA_IMEM_BYTE_SIZE-1);
         hex_file_is_empty = $system("test -s mailbox.hex");
         if (!hex_file_is_empty) $readmemh("mailbox.hex",  dummy_mbox_preloader.ram,0,32'h0001_FFFF);
         hex_file_is_empty = $system("test -s dccm.hex");
@@ -867,9 +1152,26 @@ module caliptra_top_tb_services
         wait_time_to_rst = 0;
 
         set_wdt_timer1_period = 0;
+        assert_ss_tran = 0;
+        en_jtag_access = 0;
 
         `ifndef VERILATOR
-        ecc_testvector_generator();
+        if (!UVM_TB) begin
+            ecc_testvector_generator();
+            doe_testvector_generator();
+            
+            //Note: Both obf_key_uds and obf_key_fe are the same
+            //for(int dword = 0; dword < `CLP_OBF_KEY_DWORDS; dword++) begin
+            //    cptra_obf_key_tb[dword] = doe_test_vector.obf_key_uds[(`CLP_OBF_KEY_DWORDS-1)-dword];
+            //end
+            cptra_obf_key_tb = doe_test_vector.obf_key_uds;
+            for(int dword = 0; dword < `CLP_OBF_UDS_DWORDS; dword++) begin
+                cptra_uds_tb[dword] = doe_test_vector.uds_ciphertext[dword];
+            end
+            for(int dword = 0; dword < `CLP_OBF_FE_DWORDS; dword++) begin
+                cptra_fe_tb[dword] = doe_test_vector.fe_ciphertext[dword];
+            end
+        end
         `endif
     end
 
@@ -877,6 +1179,7 @@ module caliptra_top_tb_services
    // SRAM instances
    //=========================================================================-
 caliptra_veer_sram_export veer_sram_export_inst (
+    .sram_error_injection_mode(sram_error_injection_mode),
     .el2_mem_export(el2_mem_export)
 );
 
@@ -969,7 +1272,7 @@ caliptra_sram #(
    //=========================================================================-
    // SRAM preload services
    //=========================================================================-
-task preload_mbox;
+task static preload_mbox;
     // Variables
     mbox_sram_data_t      ecc_data;
     bit [MBOX_ADDR_W  :0] addr;
@@ -996,7 +1299,7 @@ task preload_mbox;
     $display("MBOX pre-load completed");
 endtask
 
-task preload_iccm;
+task static preload_iccm;
     bit[31:0] data;
     bit[31:0] addr, eaddr, saddr;
 
@@ -1028,7 +1331,7 @@ task preload_iccm;
 endtask
 
 
-task preload_dccm;
+task static preload_dccm;
     bit[31:0] data;
     bit[31:0] addr, saddr, eaddr;
 
@@ -1070,7 +1373,7 @@ endtask
 `endif
 
 
-task slam_dccm_ram(input [31:0] addr, input[38:0] data);
+task static slam_dccm_ram(input [31:0] addr, input[38:0] data);
     int bank, indx;
     bank = get_dccm_bank(addr, indx);
     `ifdef RV_DCCM_ENABLE
@@ -1095,7 +1398,7 @@ task slam_dccm_ram(input [31:0] addr, input[38:0] data);
 endtask
 
 
-task slam_iccm_ram( input[31:0] addr, input[38:0] data);
+task static slam_iccm_ram( input[31:0] addr, input[38:0] data);
     int bank, idx;
 
     bank = get_iccm_bank(addr, idx);
@@ -1136,7 +1439,7 @@ task slam_iccm_ram( input[31:0] addr, input[38:0] data);
     `endif
 endtask
 
-task init_iccm;
+task static init_iccm;
     `ifdef RV_ICCM_ENABLE
         `IRAM(0) = '{default:39'h0};
         `IRAM(1) = '{default:39'h0};
@@ -1168,7 +1471,7 @@ task init_iccm;
     `endif
 endtask
 
-task init_dccm;
+task static init_dccm;
     `ifdef RV_DCCM_ENABLE
         `DRAM(0) = '{default:39'h0};
         `DRAM(1) = '{default:39'h0};
@@ -1185,7 +1488,7 @@ task init_dccm;
     `endif
 endtask
 
-task dump_memory_contents;
+task static dump_memory_contents;
     input [2:0] mem_type;
     input [31:0] start_addr;
     input [31:0] end_addr;
@@ -1350,6 +1653,15 @@ function int get_iccm_bank(input[31:0] addr,  output int bank_idx);
     `endif
 endfunction
 
+`ifndef VERILATOR
+soc_ifc_cov_bind i_soc_ifc_cov_bind();
+caliptra_top_cov_bind i_caliptra_top_cov_bind();
+sha512_ctrl_cov_bind i_sha512_ctrl_cov_bind();
+sha256_ctrl_cov_bind i_sha256_ctrl_cov_bind();
+hmac_ctrl_cov_bind i_hmac_ctrl_cov_bind();
+ecc_top_cov_bind i_ecc_top_cov_bind();
+`endif
+
 /* verilator lint_off CASEINCOMPLETE */
 `include "dasm.svi"
 /* verilator lint_on CASEINCOMPLETE */
diff --git a/src/integration/tb/caliptra_veer_sram_export.sv b/src/integration/tb/caliptra_veer_sram_export.sv
index c1ea5dd4a..04e717840 100644
--- a/src/integration/tb/caliptra_veer_sram_export.sv
+++ b/src/integration/tb/caliptra_veer_sram_export.sv
@@ -14,12 +14,79 @@
 //
 
 import el2_pkg::*;
-module caliptra_veer_sram_export #(
+module caliptra_veer_sram_export import caliptra_top_tb_pkg::*; #(
     `include "el2_param.vh"
 ) (
-    el2_mem_if.top el2_mem_export
+    // Decode:
+    //  [0] - Single bit, ICCM Error Injection
+    //  [1] - Double bit, ICCM Error Injection
+    //  [2] - Single bit, DCCM Error Injection
+    //  [3] - Double bit, DCCM Error Injection
+    input veer_sram_error_injection_mode_t sram_error_injection_mode,
+    el2_mem_if.veer_sram_sink el2_mem_export
 );
 
+//////////////////////////////////////////////////////
+// Sim-only Error Injection for ICCM/DCCM
+//
+    bit   [pt.ICCM_NUM_BANKS-1:0]          iccm_flip_bit;
+    bit   [pt.DCCM_NUM_BANKS-1:0]          dccm_flip_bit;
+    logic [pt.ICCM_NUM_BANKS-1:0] [39-1:0] iccm_sram_wdata_bitflip;
+    logic [pt.DCCM_NUM_BANKS-1:0] [39-1:0] dccm_sram_wdata_bitflip;
+    int ii,jj,kk,ll;
+
+    `ifndef VERILATOR
+        initial begin
+            bitflip_mask_generator #(39) iccm_bitflip_gen = new();
+            bitflip_mask_generator #(39) dccm_bitflip_gen = new();
+            forever begin
+                @(posedge el2_mem_export.clk)
+                if (~sram_error_injection_mode.iccm_single_bit_error && ~sram_error_injection_mode.iccm_double_bit_error) begin
+                    iccm_sram_wdata_bitflip <= '{default:0};
+                end
+                else if (el2_mem_export.iccm_clken & el2_mem_export.iccm_wren_bank) begin
+                    // Corrupt 50% of the writes
+                    for (ii = 0; ii < pt.ICCM_NUM_BANKS; ii++) begin
+                        iccm_flip_bit[ii] = 1'($urandom_range(0,99) < 50);
+                        iccm_sram_wdata_bitflip[ii] <= iccm_flip_bit[ii] ? iccm_bitflip_gen.get_mask(sram_error_injection_mode.iccm_double_bit_error) : '0;
+                    end
+                end
+                if (~sram_error_injection_mode.dccm_single_bit_error && ~sram_error_injection_mode.dccm_double_bit_error) begin
+                    dccm_sram_wdata_bitflip <= '{default:0};
+                end
+                else if (el2_mem_export.dccm_clken & el2_mem_export.dccm_wren_bank) begin
+                    // Corrupt 50% of the writes
+                    for (jj = 0; jj < pt.DCCM_NUM_BANKS; jj++) begin
+                        dccm_flip_bit[jj] = 1'($urandom_range(0,99) < 50);
+                        dccm_sram_wdata_bitflip[jj] <= dccm_flip_bit[jj] ? dccm_bitflip_gen.get_mask(sram_error_injection_mode.dccm_double_bit_error) : '0;
+                    end
+                end
+            end
+        end
+    `else
+        always @(posedge el2_mem_export.clk) begin
+            // Corrupt 50% of the writes
+            if ((~sram_error_injection_mode.iccm_single_bit_error && ~sram_error_injection_mode.iccm_double_bit_error)) begin
+                iccm_sram_wdata_bitflip <= '{default:0};
+            end
+            else if (el2_mem_export.iccm_clken & el2_mem_export.iccm_wren_bank) begin
+                for (kk = 0; kk < pt.ICCM_NUM_BANKS; kk++) begin
+                    iccm_flip_bit[kk] <= ($urandom % 100) < 50;
+                    iccm_sram_wdata_bitflip[kk] <= iccm_flip_bit[kk] ? get_bitflip_mask(sram_error_injection_mode.iccm_double_bit_error) : '0;
+                end
+            end
+            // Corrupt 50% of the writes
+            if ((~sram_error_injection_mode.dccm_single_bit_error && ~sram_error_injection_mode.dccm_double_bit_error)) begin
+                dccm_sram_wdata_bitflip <= '{default:0};
+            end
+            else if (el2_mem_export.dccm_clken & el2_mem_export.dccm_wren_bank) begin
+                for (ll = 0; ll < pt.DCCM_NUM_BANKS; ll++) begin
+                    dccm_flip_bit[ll] <= ($urandom % 100) < 50;
+                    dccm_sram_wdata_bitflip[ll] <= dccm_flip_bit[ll] ? get_bitflip_mask(sram_error_injection_mode.dccm_double_bit_error) : '0;
+                end
+            end
+        end
+    `endif
 
 //////////////////////////////////////////////////////
 // DCCM
@@ -46,7 +113,7 @@ for (genvar i=0; i<pt.DCCM_NUM_BANKS; i++) begin: dccm_loop
                                   .CLK (el2_mem_export.clk                                            ),
                                   .WE  (el2_mem_export.dccm_wren_bank[i]                              ),
                                   .ADR (el2_mem_export.dccm_addr_bank[i]                              ),
-                                  .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ),
+                                  .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ^ dccm_sram_wdata_bitflip[i]),
                                   .Q   (el2_mem_export.dccm_bank_dout[i][pt.DCCM_FDATA_WIDTH-1:0]     ),
                                   .ROP (                                                              ),
                                   // These are used by SoC
@@ -62,7 +129,7 @@ for (genvar i=0; i<pt.DCCM_NUM_BANKS; i++) begin: dccm_loop
                                   .CLK (el2_mem_export.clk                                            ),
                                   .WE  (el2_mem_export.dccm_wren_bank[i]                              ),
                                   .ADR (el2_mem_export.dccm_addr_bank[i]                              ),
-                                  .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ),
+                                  .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ^ dccm_sram_wdata_bitflip[i]),
                                   .Q   (el2_mem_export.dccm_bank_dout[i][pt.DCCM_FDATA_WIDTH-1:0]     ),
                                   .ROP (                                                              ),
                                   // These are used by SoC
@@ -77,7 +144,7 @@ for (genvar i=0; i<pt.DCCM_NUM_BANKS; i++) begin: dccm_loop
                                   .CLK (el2_mem_export.clk                                            ),
                                   .WE  (el2_mem_export.dccm_wren_bank[i]                              ),
                                   .ADR (el2_mem_export.dccm_addr_bank[i]                              ),
-                                  .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ),
+                                  .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ^ dccm_sram_wdata_bitflip[i]),
                                   .Q   (el2_mem_export.dccm_bank_dout[i][pt.DCCM_FDATA_WIDTH-1:0]     ),
                                   .ROP (                                                              ),
                                   // These are used by SoC
@@ -92,7 +159,7 @@ for (genvar i=0; i<pt.DCCM_NUM_BANKS; i++) begin: dccm_loop
                                  .CLK (el2_mem_export.clk                                            ),
                                  .WE  (el2_mem_export.dccm_wren_bank[i]                              ),
                                  .ADR (el2_mem_export.dccm_addr_bank[i]                              ),
-                                 .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ),
+                                 .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ^ dccm_sram_wdata_bitflip[i]),
                                  .Q   (el2_mem_export.dccm_bank_dout[i][pt.DCCM_FDATA_WIDTH-1:0]     ),
                                  .ROP (                                                              ),
                                  // These are used by SoC
@@ -107,7 +174,7 @@ for (genvar i=0; i<pt.DCCM_NUM_BANKS; i++) begin: dccm_loop
                                  .CLK (el2_mem_export.clk                                            ),
                                  .WE  (el2_mem_export.dccm_wren_bank[i]                              ),
                                  .ADR (el2_mem_export.dccm_addr_bank[i]                              ),
-                                 .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ),
+                                 .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ^ dccm_sram_wdata_bitflip[i]),
                                  .Q   (el2_mem_export.dccm_bank_dout[i][pt.DCCM_FDATA_WIDTH-1:0]     ),
                                  .ROP (                                                              ),
                                  // These are used by SoC
@@ -122,7 +189,7 @@ for (genvar i=0; i<pt.DCCM_NUM_BANKS; i++) begin: dccm_loop
                                  .CLK (el2_mem_export.clk                                            ),
                                  .WE  (el2_mem_export.dccm_wren_bank[i]                              ),
                                  .ADR (el2_mem_export.dccm_addr_bank[i]                              ),
-                                 .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ),
+                                 .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ^ dccm_sram_wdata_bitflip[i]),
                                  .Q   (el2_mem_export.dccm_bank_dout[i][pt.DCCM_FDATA_WIDTH-1:0]     ),
                                  .ROP (                                                              ),
                                  // These are used by SoC
@@ -137,7 +204,7 @@ for (genvar i=0; i<pt.DCCM_NUM_BANKS; i++) begin: dccm_loop
                                  .CLK (el2_mem_export.clk                                            ),
                                  .WE  (el2_mem_export.dccm_wren_bank[i]                              ),
                                  .ADR (el2_mem_export.dccm_addr_bank[i]                              ),
-                                 .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ),
+                                 .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ^ dccm_sram_wdata_bitflip[i]),
                                  .Q   (el2_mem_export.dccm_bank_dout[i][pt.DCCM_FDATA_WIDTH-1:0]     ),
                                  .ROP (                                                              ),
                                  // These are used by SoC
@@ -152,7 +219,7 @@ for (genvar i=0; i<pt.DCCM_NUM_BANKS; i++) begin: dccm_loop
                                  .CLK (el2_mem_export.clk                                            ),
                                  .WE  (el2_mem_export.dccm_wren_bank[i]                              ),
                                  .ADR (el2_mem_export.dccm_addr_bank[i]                              ),
-                                 .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ),
+                                 .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ^ dccm_sram_wdata_bitflip[i]),
                                  .Q   (el2_mem_export.dccm_bank_dout[i][pt.DCCM_FDATA_WIDTH-1:0]     ),
                                  .ROP (                                                              ),
                                  // These are used by SoC
@@ -167,7 +234,7 @@ for (genvar i=0; i<pt.DCCM_NUM_BANKS; i++) begin: dccm_loop
                                 .CLK (el2_mem_export.clk                                            ),
                                 .WE  (el2_mem_export.dccm_wren_bank[i]                              ),
                                 .ADR (el2_mem_export.dccm_addr_bank[i]                              ),
-                                .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ),
+                                .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ^ dccm_sram_wdata_bitflip[i]),
                                 .Q   (el2_mem_export.dccm_bank_dout[i][pt.DCCM_FDATA_WIDTH-1:0]     ),
                                 .ROP (                                                              ),
                                 // These are used by SoC
@@ -182,7 +249,7 @@ for (genvar i=0; i<pt.DCCM_NUM_BANKS; i++) begin: dccm_loop
                                 .CLK (el2_mem_export.clk                                            ),
                                 .WE  (el2_mem_export.dccm_wren_bank[i]                              ),
                                 .ADR (el2_mem_export.dccm_addr_bank[i]                              ),
-                                .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ),
+                                .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ^ dccm_sram_wdata_bitflip[i]),
                                 .Q   (el2_mem_export.dccm_bank_dout[i][pt.DCCM_FDATA_WIDTH-1:0]     ),
                                 .ROP (                                                              ),
                                 // These are used by SoC
@@ -197,7 +264,7 @@ for (genvar i=0; i<pt.DCCM_NUM_BANKS; i++) begin: dccm_loop
                                 .CLK (el2_mem_export.clk                                            ),
                                 .WE  (el2_mem_export.dccm_wren_bank[i]                              ),
                                 .ADR (el2_mem_export.dccm_addr_bank[i]                              ),
-                                .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ),
+                                .D   (el2_mem_export.dccm_wr_data_bank[i][pt.DCCM_FDATA_WIDTH-1:0]  ^ dccm_sram_wdata_bitflip[i]),
                                 .Q   (el2_mem_export.dccm_bank_dout[i][pt.DCCM_FDATA_WIDTH-1:0]     ),
                                 .ROP (                                                              ),
                                 // These are used by SoC
@@ -223,7 +290,7 @@ for (genvar i=0; i<pt.ICCM_NUM_BANKS; i++) begin: iccm_loop
                                      .CLK (el2_mem_export.clk                       ),
                                      .WE  (el2_mem_export.iccm_wren_bank[i]         ),
                                      .ADR (el2_mem_export.iccm_addr_bank[i]         ),
-                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0]),
+                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0] ^ iccm_sram_wdata_bitflip[i]),
                                      .Q   (el2_mem_export.iccm_bank_dout[i][38:0]   ),
                                      .ROP (                                         ),
                                      // These are used by SoC
@@ -247,7 +314,7 @@ for (genvar i=0; i<pt.ICCM_NUM_BANKS; i++) begin: iccm_loop
                                      .ME  (el2_mem_export.iccm_clken[i]             ),
                                      .WE  (el2_mem_export.iccm_wren_bank[i]         ),
                                      .ADR (el2_mem_export.iccm_addr_bank[i]         ),
-                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0]),
+                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0] ^ iccm_sram_wdata_bitflip[i]),
                                      .Q   (el2_mem_export.iccm_bank_dout[i][38:0]   ),
                                      .ROP (                                         ),
                                      // These are used by SoC
@@ -271,7 +338,7 @@ for (genvar i=0; i<pt.ICCM_NUM_BANKS; i++) begin: iccm_loop
                                      .ME  (el2_mem_export.iccm_clken[i]             ),
                                      .WE  (el2_mem_export.iccm_wren_bank[i]         ),
                                      .ADR (el2_mem_export.iccm_addr_bank[i]         ),
-                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0]),
+                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0] ^ iccm_sram_wdata_bitflip[i]),
                                      .Q   (el2_mem_export.iccm_bank_dout[i][38:0]   ),
                                      .ROP (                                         ),
                                      // These are used by SoC
@@ -295,7 +362,7 @@ for (genvar i=0; i<pt.ICCM_NUM_BANKS; i++) begin: iccm_loop
                                      .ME  (el2_mem_export.iccm_clken[i]             ),
                                      .WE  (el2_mem_export.iccm_wren_bank[i]         ),
                                      .ADR (el2_mem_export.iccm_addr_bank[i]         ),
-                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0]),
+                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0] ^ iccm_sram_wdata_bitflip[i]),
                                      .Q   (el2_mem_export.iccm_bank_dout[i][38:0]   ),
                                      .ROP (                                         ),
                                      // These are used by SoC
@@ -318,7 +385,7 @@ for (genvar i=0; i<pt.ICCM_NUM_BANKS; i++) begin: iccm_loop
                                      .ME  (el2_mem_export.iccm_clken[i]             ),
                                      .WE  (el2_mem_export.iccm_wren_bank[i]         ),
                                      .ADR (el2_mem_export.iccm_addr_bank[i]         ),
-                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0]),
+                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0] ^ iccm_sram_wdata_bitflip[i]),
                                      .Q   (el2_mem_export.iccm_bank_dout[i][38:0]   ),
                                      .ROP (                                         ),
                                      // These are used by SoC
@@ -341,7 +408,7 @@ for (genvar i=0; i<pt.ICCM_NUM_BANKS; i++) begin: iccm_loop
                                      .ME  (el2_mem_export.iccm_clken[i]             ),
                                      .WE  (el2_mem_export.iccm_wren_bank[i]         ),
                                      .ADR (el2_mem_export.iccm_addr_bank[i]         ),
-                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0]),
+                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0] ^ iccm_sram_wdata_bitflip[i]),
                                      .Q   (el2_mem_export.iccm_bank_dout[i][38:0]   ),
                                      .ROP (                                         ),
                                      // These are used by SoC
@@ -364,7 +431,7 @@ for (genvar i=0; i<pt.ICCM_NUM_BANKS; i++) begin: iccm_loop
                                      .ME  (el2_mem_export.iccm_clken[i]             ),
                                      .WE  (el2_mem_export.iccm_wren_bank[i]         ),
                                      .ADR (el2_mem_export.iccm_addr_bank[i]         ),
-                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0]),
+                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0] ^ iccm_sram_wdata_bitflip[i]),
                                      .Q   (el2_mem_export.iccm_bank_dout[i][38:0]   ),
                                      .ROP (                                         ),
                                      // These are used by SoC
@@ -387,7 +454,7 @@ for (genvar i=0; i<pt.ICCM_NUM_BANKS; i++) begin: iccm_loop
                                      .ME  (el2_mem_export.iccm_clken[i]             ),
                                      .WE  (el2_mem_export.iccm_wren_bank[i]         ),
                                      .ADR (el2_mem_export.iccm_addr_bank[i]         ),
-                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0]),
+                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0] ^ iccm_sram_wdata_bitflip[i]),
                                      .Q   (el2_mem_export.iccm_bank_dout[i][38:0]   ),
                                      .ROP (                                         ),
                                      // These are used by SoC
@@ -410,7 +477,7 @@ for (genvar i=0; i<pt.ICCM_NUM_BANKS; i++) begin: iccm_loop
                                      .ME  (el2_mem_export.iccm_clken[i]             ),
                                      .WE  (el2_mem_export.iccm_wren_bank[i]         ),
                                      .ADR (el2_mem_export.iccm_addr_bank[i]         ),
-                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0]),
+                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0] ^ iccm_sram_wdata_bitflip[i]),
                                      .Q   (el2_mem_export.iccm_bank_dout[i][38:0]   ),
                                      .ROP (                                         ),
                                      // These are used by SoC
@@ -433,7 +500,7 @@ for (genvar i=0; i<pt.ICCM_NUM_BANKS; i++) begin: iccm_loop
                                      .ME  (el2_mem_export.iccm_clken[i]             ),
                                      .WE  (el2_mem_export.iccm_wren_bank[i]         ),
                                      .ADR (el2_mem_export.iccm_addr_bank[i]         ),
-                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0]),
+                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0] ^ iccm_sram_wdata_bitflip[i]),
                                      .Q   (el2_mem_export.iccm_bank_dout[i][38:0]   ),
                                      .ROP (                                         ),
                                      // These are used by SoC
@@ -456,7 +523,7 @@ for (genvar i=0; i<pt.ICCM_NUM_BANKS; i++) begin: iccm_loop
                                      .ME  (el2_mem_export.iccm_clken[i]             ),
                                      .WE  (el2_mem_export.iccm_wren_bank[i]         ),
                                      .ADR (el2_mem_export.iccm_addr_bank[i]         ),
-                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0]),
+                                     .D   (el2_mem_export.iccm_bank_wr_data[i][38:0] ^ iccm_sram_wdata_bitflip[i]),
                                      .Q   (el2_mem_export.iccm_bank_dout[i][38:0]   ),
                                      .ROP (                                         ),
                                      // These are used by SoC
diff --git a/src/integration/tb/dasm.svi b/src/integration/tb/dasm.svi
index ef7017d10..e0ff207ec 100755
--- a/src/integration/tb/dasm.svi
+++ b/src/integration/tb/dasm.svi
@@ -23,7 +23,7 @@
 bit[31:0] [31:0] gpr[`RV_NUM_THREADS];
 
 // main DASM function
-function string dasm(input[31:0] opcode, input[31:0] pc, input[4:0] regn, input[31:0] regv, input tid=0);
+function static string dasm(input[31:0] opcode, input[31:0] pc, input[4:0] regn, input[31:0] regv, input tid=0);
     dasm = (opcode[1:0] == 2'b11) ? dasm32(opcode, pc, tid) : dasm16(opcode, pc, tid);
     if(regn) gpr[tid][regn] = regv;
 endfunction
@@ -31,7 +31,7 @@ endfunction
 
 ///////////////// 16 bits instructions ///////////////////////
 
-function string dasm16( input[31:0] opcode, input[31:0] pc, input tid=0);
+function static string dasm16( input[31:0] opcode, input[31:0] pc, input tid=0);
     case(opcode[1:0])
     0: return dasm16_0(opcode, tid);
     1: return dasm16_1(opcode, pc);
@@ -40,7 +40,7 @@ function string dasm16( input[31:0] opcode, input[31:0] pc, input tid=0);
     return $sformatf(".short 0x%h", opcode[15:0]);
 endfunction
 
-function string dasm16_0( input[31:0] opcode, tid);
+function static string dasm16_0( input[31:0] opcode, tid);
     case(opcode[15:13])
     3'b000: return dasm16_ciw(opcode);
     3'b001: return {"c.fld  ", dasm16_cl(opcode, tid)};
@@ -53,7 +53,7 @@ function string dasm16_0( input[31:0] opcode, tid);
     return $sformatf(".short  0x%h", opcode[15:0]);
 endfunction
 
-function string dasm16_ciw( input[31:0] opcode);
+function static string dasm16_ciw( input[31:0] opcode);
 int imm;
     imm=0;
     if(opcode[15:0] == 0) return ".short  0";
@@ -61,7 +61,7 @@ int imm;
     return $sformatf("c.addi4spn %s,0x%0h", abi_reg[opcode[4:2]+8], imm);
 endfunction
 
-function string dasm16_cl( input[31:0] opcode, input tid=0);
+function static string dasm16_cl( input[31:0] opcode, input tid=0);
 int imm;
     imm=0;
     imm[5:3] = opcode[12:10];
@@ -70,7 +70,7 @@ int imm;
     return $sformatf(" %s,%0d(%s) [%h]", abi_reg[opcode[4:2]+8], imm, abi_reg[opcode[9:7]+8], gpr[tid][opcode[9:7]+8]+imm);
 endfunction
 
-function string dasm16_1( input[31:0] opcode, input[31:0] pc);
+function static string dasm16_1( input[31:0] opcode, input[31:0] pc);
     case(opcode[15:13])
     3'b000: return opcode[11:7]==0 ? "c.nop" : {"c.addi  ",dasm16_ci(opcode)};
     3'b001: return {"c.jal   ", dasm16_cj(opcode, pc)};
@@ -83,7 +83,7 @@ function string dasm16_1( input[31:0] opcode, input[31:0] pc);
     endcase
 endfunction
 
-function string dasm16_ci( input[31:0] opcode);
+function static string dasm16_ci( input[31:0] opcode);
 int imm;
     imm=0;
     imm[4:0] = opcode[6:2];
@@ -91,7 +91,7 @@ int imm;
     return $sformatf("%s,%0d", abi_reg[opcode[11:7]], imm);
 endfunction
 
-function string dasm16_cj( input[31:0] opcode, input[31:0] pc);
+function static string dasm16_cj( input[31:0] opcode, input[31:0] pc);
 bit[31:0] imm;
     imm=0;
     {imm[11],imm[4],imm[9:8],imm[10],imm[6], imm[7],imm[3:1], imm[5]} = opcode[12:2];
@@ -99,7 +99,7 @@ bit[31:0] imm;
     return $sformatf("0x%0h", imm+pc);
 endfunction
 
-function string dasm16_cb( input[31:0] opcode, input[31:0] pc);
+function static string dasm16_cb( input[31:0] opcode, input[31:0] pc);
 bit[31:0] imm;
     imm=0;
     {imm[8],imm[4:3]} = opcode[12:10];
@@ -108,7 +108,7 @@ bit[31:0] imm;
     return $sformatf("%s,0x%0h",abi_reg[opcode[9:7]+8], imm+pc);
 endfunction
 
-function string dasm16_cr( input[31:0] opcode);
+function static string dasm16_cr( input[31:0] opcode);
 bit[31:0] imm;
 
     imm = 0;
@@ -128,7 +128,7 @@ bit[31:0] imm;
     endcase
 endfunction
 
-function string dasm16_1_3( input[31:0] opcode);
+function static string dasm16_1_3( input[31:0] opcode);
 int imm;
 
     imm=0;
@@ -145,7 +145,7 @@ int imm;
     end
 endfunction
 
-function string dasm16_2( input[31:0] opcode, input tid=0);
+function static string dasm16_2( input[31:0] opcode, input tid=0);
     case(opcode[15:13])
     3'b000: return {"c.slli  ", dasm16_ci(opcode)};
     3'b001: return {"c.fldsp ", dasm16_cls(opcode,1,tid)};
@@ -167,7 +167,7 @@ function string dasm16_2( input[31:0] opcode, input tid=0);
 endfunction
 
 
-function string dasm16_cls( input[31:0] opcode, input sh1=0, tid=0);
+function static string dasm16_cls( input[31:0] opcode, input sh1=0, tid=0);
 bit[31:0] imm;
     imm=0;
     if(sh1) {imm[4:3],imm[8:6]} = opcode[6:2];
@@ -176,7 +176,7 @@ bit[31:0] imm;
     return $sformatf("%s,0x%0h [%h]", abi_reg[opcode[11:7]], imm, gpr[tid][2]+imm);
 endfunction
 
-function string dasm16_css( input[31:0] opcode, input sh1=0, tid=0);
+function static string dasm16_css( input[31:0] opcode, input sh1=0, tid=0);
 bit[31:0] imm;
     imm=0;
     if(sh1) {imm[5:3],imm[8:6]} = opcode[12:7];
@@ -186,7 +186,7 @@ endfunction
 
 ///////////////// 32 bit instructions ///////////////////////
 
-function string dasm32( input[31:0] opcode, input[31:0] pc, input tid=0);
+function static string dasm32( input[31:0] opcode, input[31:0] pc, input tid=0);
     case(opcode[6:0])
     7'b0110111: return {"lui     ", dasm32_u(opcode)};
     7'b0010111: return {"auipc   ", dasm32_u(opcode)};
@@ -205,14 +205,14 @@ function string dasm32( input[31:0] opcode, input[31:0] pc, input tid=0);
     return $sformatf(".long   0x%h", opcode);
 endfunction
 
-function string dasm32_u( input[31:0] opcode);
+function static string dasm32_u( input[31:0] opcode);
 bit[31:0] imm;
     imm=0;
     imm[31:12] = opcode[31:12];
     return $sformatf("%s,0x%0h", abi_reg[opcode[11:7]], imm);
 endfunction
 
-function string dasm32_j( input[31:0] opcode, input[31:0] pc);
+function static string dasm32_j( input[31:0] opcode, input[31:0] pc);
 int imm;
     imm=0;
     {imm[20], imm[10:1], imm[11], imm[19:12]} = opcode[31:12];
@@ -220,7 +220,7 @@ int imm;
     return $sformatf("%s,0x%0h",abi_reg[opcode[11:7]], imm+pc);
 endfunction
 
-function string dasm32_jr( input[31:0] opcode, input[31:0] pc);
+function static string dasm32_jr( input[31:0] opcode, input[31:0] pc);
 int imm;
     imm=0;
     imm[11:1] = opcode[31:19];
@@ -228,7 +228,7 @@ int imm;
     return $sformatf("%s,%s,0x%0h",abi_reg[opcode[11:7]], abi_reg[opcode[19:15]], imm+pc);
 endfunction
 
-function string dasm32_b( input[31:0] opcode, input[31:0] pc);
+function static string dasm32_b( input[31:0] opcode, input[31:0] pc);
 int imm;
 string mn;
     imm=0;
@@ -247,7 +247,7 @@ string mn;
     return $sformatf("%s%s,%s,0x%0h", mn, abi_reg[opcode[19:15]], abi_reg[opcode[24:20]], imm+pc);
 endfunction
 
-function string dasm32_l( input[31:0] opcode, input tid=0);
+function static string dasm32_l( input[31:0] opcode, input tid=0);
 int imm;
 string mn;
     imm=0;
@@ -264,7 +264,7 @@ string mn;
     return $sformatf("%s%s,%0d(%s) [%h]", mn, abi_reg[opcode[11:7]], imm, abi_reg[opcode[19:15]], imm+gpr[tid][opcode[19:15]]);
 endfunction
 
-function string dasm32_s( input[31:0] opcode, input tid=0);
+function static string dasm32_s( input[31:0] opcode, input tid=0);
 int imm;
 string mn;
     imm=0;
@@ -280,7 +280,7 @@ string mn;
     return $sformatf("%s%s,%0d(%s) [%h]", mn, abi_reg[opcode[24:20]], imm, abi_reg[opcode[19:15]], imm+gpr[tid][opcode[19:15]]);
 endfunction
 
-function string dasm32_ai( input[31:0] opcode);
+function static string dasm32_ai( input[31:0] opcode);
 int imm;
 string mn;
     imm=0;
@@ -299,7 +299,7 @@ endcase
 return $sformatf("%s%s,%s,%0d", mn, abi_reg[opcode[11:7]], abi_reg[opcode[19:15]], imm);
 endfunction
 
-function string dasm32_si( input[31:0] opcode);
+function static string dasm32_si( input[31:0] opcode);
 int imm;
 string mn;
     imm = opcode[24:20];
@@ -313,7 +313,7 @@ endfunction
 
 
 
-function string dasm32_ar( input[31:0] opcode);
+function static string dasm32_ar( input[31:0] opcode);
 string mn;
     if(opcode[25])
         case(opcode[14:12])
@@ -340,11 +340,11 @@ string mn;
     return $sformatf("%s%s,%s,%s", mn, abi_reg[opcode[11:7]], abi_reg[opcode[19:15]], abi_reg[opcode[24:20]]);
 endfunction
 
-function string dasm32_fence( input[31:0] opcode);
+function static string dasm32_fence( input[31:0] opcode);
     return  opcode[12] ? ".i" : "";
 endfunction
 
-function string dasm32_e(input[31:0] opcode);
+function static string dasm32_e(input[31:0] opcode);
     if(opcode[31:7] == 0) return "ecall";
     else if({opcode[31:21],opcode [19:7]} == 0) return "ebreak";
     else
@@ -360,7 +360,7 @@ function string dasm32_e(input[31:0] opcode);
 endfunction
 
 
-function string dasm32_csr(input[31:0] opcode, input im=0);
+function static string dasm32_csr(input[31:0] opcode, input im=0);
 bit[11:0] csr;
     csr = opcode[31:20];
     if(im) begin
@@ -373,7 +373,7 @@ bit[11:0] csr;
 endfunction
 
 //atomics
-function string dasm32_a(input[31:0] opcode, input tid=0);
+function static string dasm32_a(input[31:0] opcode, input tid=0);
     case(opcode[31:27])
     'b00010: return $sformatf("lr.w    %s,(%s) [%h]",    abi_reg[opcode[11:7]],                         abi_reg[opcode[19:15]], gpr[tid][opcode[19:15]]);
     'b00011: return $sformatf("sc.w    %s,%s,(%s) [%h]", abi_reg[opcode[11:7]], abi_reg[opcode[24:20]], abi_reg[opcode[19:15]], gpr[tid][opcode[19:15]]);
@@ -390,6 +390,6 @@ function string dasm32_a(input[31:0] opcode, input tid=0);
     return $sformatf(".long 0x%h", opcode);
 endfunction
 
-function string dasm32_amo( input[31:0] opcode, input tid=0);
+function static string dasm32_amo( input[31:0] opcode, input tid=0);
     return $sformatf(" %s,%s,(%s) [%h]", abi_reg[opcode[11:7]], abi_reg[opcode[24:20]], abi_reg[opcode[19:15]], gpr[tid][opcode[19:15]]);
 endfunction
diff --git a/src/integration/tb/test_caliptra_top_tb.cpp b/src/integration/tb/test_caliptra_top_tb.cpp
index a838fbd53..05b7f47db 100644
--- a/src/integration/tb/test_caliptra_top_tb.cpp
+++ b/src/integration/tb/test_caliptra_top_tb.cpp
@@ -19,8 +19,11 @@
 #include <string>
 #include "Vcaliptra_top_tb.h"
 #include "verilated.h"
+#if VM_TRACE_VCD
 #include "verilated_vcd_c.h"
-
+#elif VM_TRACE_FST
+#include "verilated_fst_c.h"
+#endif
 
 vluint64_t main_time = 0;
 
@@ -37,13 +40,17 @@ int main(int argc, char** argv) {
   Vcaliptra_top_tb* tb = new Vcaliptra_top_tb;
 
   // init trace dump
-  VerilatedVcdC* tfp = NULL;
-
 #if VM_TRACE
   Verilated::traceEverOn(true);
-  tfp = new VerilatedVcdC;
-  tb->trace (tfp, 24);
-  tfp->open ("sim.vcd");
+  #if VM_TRACE_VCD
+    VerilatedVcdC* tfp = new VerilatedVcdC;
+    tb->trace (tfp, 24);
+    tfp->open ("sim.vcd");
+  #elif VM_TRACE_FST
+    VerilatedFstC* tfp = new VerilatedFstC;
+    tb->trace (tfp, 24);
+    tfp->open ("sim.fst");
+  #endif
 #endif
   // Simulate
   while(!Verilated::gotFinish()){
diff --git a/src/integration/test_suites/c_intr_handler/c_intr_handler.c b/src/integration/test_suites/c_intr_handler/c_intr_handler.c
index 6c488b494..01e11447c 100644
--- a/src/integration/test_suites/c_intr_handler/c_intr_handler.c
+++ b/src/integration/test_suites/c_intr_handler/c_intr_handler.c
@@ -15,6 +15,7 @@
 #include "caliptra_defines.h"
 #include "caliptra_isr.h"
 #include "riscv-csr.h"
+#include "riscv_hw_if.h"
 #include <string.h>
 #include <stdint.h>
 #include "printf.h"
@@ -32,6 +33,31 @@ volatile uint32_t intr_count;
     enum printf_verbosity verbosity_g = LOW;
 #endif
 
+//TODO: Fix this since ISR is not currently populating these variables.
+volatile caliptra_intr_received_s cptra_intr_rcv = {
+    .doe_error        = 0,
+    .doe_notif        = 0,
+    .ecc_error        = 0,
+    .ecc_notif        = 0,
+    .hmac_error       = 0,
+    .hmac_notif       = 0,
+    .kv_error         = 0,
+    .kv_notif         = 0,
+    .sha512_error     = 0,
+    .sha512_notif     = 0,
+    .sha256_error     = 0,
+    .sha256_notif     = 0,
+    .qspi_error       = 0,
+    .qspi_notif       = 0,
+    .uart_error       = 0,
+    .uart_notif       = 0,
+    .i3c_error        = 0,
+    .i3c_notif        = 0,
+    .soc_ifc_error    = 0,
+    .soc_ifc_notif    = 0,
+    .sha512_acc_error = 0,
+    .sha512_acc_notif = 0,
+};
 
 void main(void) {
         int argc=0;
@@ -60,10 +86,12 @@ void main(void) {
         volatile uint32_t * soc_ifc_error_mbox_ecc_unc_ctr = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_MBOX_ECC_UNC_INTR_COUNT_R);
         volatile uint32_t * soc_ifc_error_wdt_timer1_timeout_ctr = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_R);
         volatile uint32_t * soc_ifc_error_wdt_timer2_timeout_ctr = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_R);
-        volatile uint32_t * soc_ifc_notif_cmd_avail_ctr    = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_CMD_AVAIL_INTR_COUNT_R);
-        volatile uint32_t * soc_ifc_notif_mbox_ecc_cor_ctr = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_R);
-        volatile uint32_t * soc_ifc_notif_debug_locked_ctr = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_R);
-        volatile uint32_t * soc_ifc_notif_soc_req_lock_ctr = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_R);
+        volatile uint32_t * soc_ifc_notif_cmd_avail_ctr     = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_CMD_AVAIL_INTR_COUNT_R);
+        volatile uint32_t * soc_ifc_notif_mbox_ecc_cor_ctr  = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_R);
+        volatile uint32_t * soc_ifc_notif_debug_locked_ctr  = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_R);
+        volatile uint32_t * soc_ifc_notif_scan_mode_ctr     = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_R);
+        volatile uint32_t * soc_ifc_notif_soc_req_lock_ctr  = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_R);
+        volatile uint32_t * soc_ifc_notif_gen_in_toggle_ctr = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_R);
 
         uint32_t sha512_intr_count = 0;
         uint32_t sha256_intr_count = 0;
@@ -75,6 +103,7 @@ void main(void) {
         uint32_t soc_ifc_notif_intr_count_hw = 0;
         uint32_t soc_ifc_error_intr_count = 0;
         uint32_t soc_ifc_error_intr_count_hw = 0;
+        uint64_t mtime = 0;
 
         VPRINTF(LOW,"----------------------------------\nCaliptra: Direct ISR Test!!\n----------------------------------\n");
 
@@ -87,26 +116,26 @@ void main(void) {
         // Busy loop
         while (intr_count < 64) {
             // Trigger interrupt manually
-            if ((intr_count % 0x12) >= 0x11) {
+            if ((intr_count % 0x13) >= 0x12) {
                 *sha512_notif_trig = SHA512_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_MASK;
                 sha512_intr_count++;
-            } else if ((intr_count % 0x12) >= 0x10) {
+            } else if ((intr_count % 0x13) >= 0x11) {
                 *sha256_notif_trig = SHA256_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_MASK;
                 sha256_intr_count++;
-            } else if ((intr_count % 0x12) >= 0x0F) {
+            } else if ((intr_count % 0x13) >= 0x10) {
                 *sha512_acc_notif_trig = SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_MASK;
                 sha512_acc_intr_count++;
-            } else if ((intr_count % 0x12) >= 0x0E) {
+            } else if ((intr_count % 0x13) >= 0x0F) {
                 *hmac_notif_trig = HMAC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_MASK;
                 hmac_intr_count++;
-            } else if ((intr_count % 0x12) >= 0x0D) {
+            } else if ((intr_count % 0x13) >= 0x0E) {
                 *ecc_notif_trig = ECC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_MASK;
                 ecc_intr_count++;
-            } else if ((intr_count % 0x12) >= 0x0C) {
+            } else if ((intr_count % 0x13) >= 0x0D) {
                 *doe_notif_trig = DOE_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_MASK;
                 doe_intr_count++;
-            } else if ((intr_count % 0x12) >= 0x08) { //8-B
-                *soc_ifc_notif_trig = 1 << (intr_count % 0x4);
+            } else if ((intr_count % 0x13) >= 0x08) { //8-C
+                *soc_ifc_notif_trig = 1 << (intr_count % 0x5);
                 soc_ifc_notif_intr_count++;
             } else { //0-7
                 *soc_ifc_error_trig = 1 << (intr_count % 0x8);
@@ -192,7 +221,9 @@ void main(void) {
         soc_ifc_notif_intr_count_hw =  *soc_ifc_notif_cmd_avail_ctr +
                                        *soc_ifc_notif_mbox_ecc_cor_ctr +
                                        *soc_ifc_notif_debug_locked_ctr +
-                                       *soc_ifc_notif_soc_req_lock_ctr;
+                                       *soc_ifc_notif_scan_mode_ctr +
+                                       *soc_ifc_notif_soc_req_lock_ctr +
+                                       *soc_ifc_notif_gen_in_toggle_ctr;
         VPRINTF(MEDIUM, "SOC_IFC Notif hw count: %x\n", soc_ifc_notif_intr_count_hw);
         if (soc_ifc_notif_intr_count != soc_ifc_notif_intr_count_hw) {
             VPRINTF(ERROR, "SOC_IFC Notif count mismatch!\n");
@@ -206,6 +237,32 @@ void main(void) {
             SEND_STDOUT_CTRL(0x1); // Kill sim with ERROR
         }
 
+        // Now test timer interrupts
+        mtime = (lsu_read_32(CLP_SOC_IFC_REG_INTERNAL_RV_MTIME_H) << 32) | lsu_read_32(CLP_SOC_IFC_REG_INTERNAL_RV_MTIME_L);
+        // Did we just rollover? Maybe the value read from MTIME_H was stale after reading MTIME_L.
+        // Reread.
+        if ((mtime & 0xFFFFFFFF) < 0x40) {
+            mtime = (lsu_read_32(CLP_SOC_IFC_REG_INTERNAL_RV_MTIME_H) << 32) | lsu_read_32(CLP_SOC_IFC_REG_INTERNAL_RV_MTIME_L);
+        }
+
+        // Setup a wait time of 1000 clock cycles = 10us
+        mtime += 1000;
+        lsu_write_32(CLP_SOC_IFC_REG_INTERNAL_RV_MTIMECMP_L, mtime & 0xFFFFFFFF);
+        lsu_write_32(CLP_SOC_IFC_REG_INTERNAL_RV_MTIMECMP_H, mtime >> 32       );
+
+        // Re-enable interrupts (but not external interrupts)
+        csr_clr_bits_mie(MIE_MEI_BIT_MASK);
+        csr_set_bits_mstatus(MSTATUS_MIE_BIT_MASK);
+
+        // Poll for Timer Interrupt Handler to complete processing.
+        // Timer ISR simply sets mtimecmp back to max values, so poll for that.
+        while (lsu_read_32(CLP_SOC_IFC_REG_INTERNAL_RV_MTIMECMP_H) != 0xFFFFFFFF) {
+            // Sleep in between triggers to allow ISR to execute and show idle time in sims
+            for (uint16_t slp = 0; slp < 100; slp++) {
+                __asm__ volatile ("nop"); // Sleep loop as "nop"
+            }
+        }
+
         return;
 }
 
diff --git a/src/integration/test_suites/c_intr_handler/caliptra_isr.h b/src/integration/test_suites/c_intr_handler/caliptra_isr.h
index a57d5f814..517e72b37 100644
--- a/src/integration/test_suites/c_intr_handler/caliptra_isr.h
+++ b/src/integration/test_suites/c_intr_handler/caliptra_isr.h
@@ -32,6 +32,33 @@
 #include <stdint.h>
 #include "printf.h"
 
+/* --------------- symbols/typedefs --------------- */
+typedef struct {
+    uint32_t doe_error;
+    uint32_t doe_notif;
+    uint32_t ecc_error;
+    uint32_t ecc_notif;
+    uint32_t hmac_error;
+    uint32_t hmac_notif;
+    uint32_t kv_error;
+    uint32_t kv_notif;
+    uint32_t sha512_error;
+    uint32_t sha512_notif;
+    uint32_t sha256_error;
+    uint32_t sha256_notif;
+    uint32_t qspi_error;
+    uint32_t qspi_notif;
+    uint32_t uart_error;
+    uint32_t uart_notif;
+    uint32_t i3c_error;
+    uint32_t i3c_notif;
+    uint32_t soc_ifc_error;
+    uint32_t soc_ifc_notif;
+    uint32_t sha512_acc_error;
+    uint32_t sha512_acc_notif;
+} caliptra_intr_received_s;
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
+
 //////////////////////////////////////////////////////////////////////////////
 // Function Declarations
 //
@@ -166,9 +193,15 @@ inline void service_soc_ifc_notif_intr () {
     if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
         *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
     }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
     if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
         *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
     }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
     if (sts == 0) {
         printf("bad soc_ifc_notif_intr sts:%x\n", sts);
         printf("%c", 0x1);
diff --git a/src/integration/test_suites/caliptra_demo/caliptra_isr.h b/src/integration/test_suites/caliptra_demo/caliptra_isr.h
index e6aa9ee48..983bd1b2b 100644
--- a/src/integration/test_suites/caliptra_demo/caliptra_isr.h
+++ b/src/integration/test_suites/caliptra_demo/caliptra_isr.h
@@ -160,6 +160,9 @@ inline void service_soc_ifc_notif_intr () {
     if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
         *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
     }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
     if (sts == 0) {
         printf("bad soc_ifc_notif_intr sts:%x\n", sts);
         printf("%c", 0x1);
diff --git a/src/integration/test_suites/caliptra_fmc/caliptra_fmc.c b/src/integration/test_suites/caliptra_fmc/caliptra_fmc.c
index 8b2c071c9..cf8bcfbf7 100644
--- a/src/integration/test_suites/caliptra_fmc/caliptra_fmc.c
+++ b/src/integration/test_suites/caliptra_fmc/caliptra_fmc.c
@@ -29,6 +29,7 @@
 #include "sha256.h"
 #include "sha512.h"
 #include "soc_ifc.h"
+#include "caliptra_isr.h"
 #include <string.h>
 #include <stdint.h>
 #include "printf.h"
@@ -37,12 +38,14 @@
 extern uintptr_t STACK;
 
 /* --------------- Global vars --------------- */
-volatile char*                    stdout           = (char *)STDOUT;
+volatile char* stdout = (char *)STDOUT;
 #ifdef CPT_VERBOSITY
-    enum printf_verbosity             verbosity_g = CPT_VERBOSITY;
+    enum printf_verbosity verbosity_g = CPT_VERBOSITY;
 #else
-    enum printf_verbosity             verbosity_g = LOW;
+    enum printf_verbosity verbosity_g = LOW;
 #endif
+volatile caliptra_intr_received_s cptra_intr_rcv;
+volatile uint32_t                 intr_count       = 0;
 
 
 /* --------------- Function Definitions --------------- */
diff --git a/src/integration/test_suites/caliptra_fmc/caliptra_fmc.ld b/src/integration/test_suites/caliptra_fmc/caliptra_fmc.ld
index fad2eeedf..7c093ba27 100644
--- a/src/integration/test_suites/caliptra_fmc/caliptra_fmc.ld
+++ b/src/integration/test_suites/caliptra_fmc/caliptra_fmc.ld
@@ -40,7 +40,7 @@ SECTIONS {
   . = _text_lma_end + 0x10; /* . (location counter) points to 0x0, force it back to next LMA here */
   _data_vma_start = 0x50000000;
   _data_lma_start = .; /* After this, . (location counter) goes back to holding VMA value */
-  .data _data_vma_start :  AT(_data_lma_start) { *(.*data) *(.rodata*) ; . = ALIGN(4); } =0x0000,
+  .data _data_vma_start :  AT(_data_lma_start) { *(.*data) *(.sdata*) *(.rodata*) *(.srodata*) ; . = ALIGN(4); } =0x0000,
   _data_lma_end = _data_lma_start + SIZEOF(.data);
 
   _bss_vma_start = .;
diff --git a/src/integration/test_suites/caliptra_fmc/caliptra_isr.h b/src/integration/test_suites/caliptra_fmc/caliptra_isr.h
new file mode 100644
index 000000000..542d6572b
--- /dev/null
+++ b/src/integration/test_suites/caliptra_fmc/caliptra_isr.h
@@ -0,0 +1,255 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// ---------------------------------------------------------------------
+// File: caliptra_isr.h
+// Description:
+//     Provides function declarations for use by external test files, so
+//     that the ISR functionality may behave like a library.
+//     TODO:
+//     This header file includes inline function definitions for event and
+//     test specific interrupt service behavior, so it should be copied and
+//     modified for each test.
+// ---------------------------------------------------------------------
+
+#ifndef CALIPTRA_ISR_H
+    #define CALIPTRA_ISR_H
+
+#define EN_ISR_PRINTS 1
+
+#include "caliptra_defines.h"
+#include <stdint.h>
+#include "printf.h"
+
+/* --------------- symbols/typedefs --------------- */
+typedef struct {
+    uint32_t doe_error;
+    uint32_t doe_notif;
+    uint32_t ecc_error;
+    uint32_t ecc_notif;
+    uint32_t hmac_error;
+    uint32_t hmac_notif;
+    uint32_t kv_error;
+    uint32_t kv_notif;
+    uint32_t sha512_error;
+    uint32_t sha512_notif;
+    uint32_t sha256_error;
+    uint32_t sha256_notif;
+    uint32_t qspi_error;
+    uint32_t qspi_notif;
+    uint32_t uart_error;
+    uint32_t uart_notif;
+    uint32_t i3c_error;
+    uint32_t i3c_notif;
+    uint32_t soc_ifc_error;
+    uint32_t soc_ifc_notif;
+    uint32_t sha512_acc_error;
+    uint32_t sha512_acc_notif;
+} caliptra_intr_received_s;
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
+
+//////////////////////////////////////////////////////////////////////////////
+// Function Declarations
+//
+
+// Performs all the CSR setup to configure and enable vectored external interrupts
+void init_interrupts(void);
+
+// These inline functions are used to insert event-specific functionality into the
+// otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr"
+inline void service_doe_error_intr() {return;}
+inline void service_doe_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.doe_notif |= DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad doe_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_ecc_error_intr() {return;}
+inline void service_ecc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.ecc_notif |= ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad ecc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_hmac_error_intr() {return;}
+inline void service_hmac_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.hmac_notif |= HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad hmac_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_kv_error_intr() {return;}
+inline void service_kv_notif_intr() {return;}
+inline void service_sha512_error_intr() {return;}
+inline void service_sha512_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_notif |= SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha256_error_intr() {return;}
+inline void service_sha256_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha256_notif |= SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha256_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_qspi_error_intr() {return;}
+inline void service_qspi_notif_intr() {return;}
+inline void service_uart_error_intr() {return;}
+inline void service_uart_notif_intr() {return;}
+inline void service_i3c_error_intr() {return;}
+inline void service_i3c_notif_intr() {return;}
+
+inline void service_soc_ifc_error_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_error_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_soc_ifc_notif_intr () {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha512_acc_error_intr() {return;}
+inline void service_sha512_acc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_acc_notif |= SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_acc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+
+#endif //CALIPTRA_ISR_H
diff --git a/src/integration/test_suites/caliptra_rt/caliptra_isr.h b/src/integration/test_suites/caliptra_rt/caliptra_isr.h
index e7647284a..1f7d023bc 100644
--- a/src/integration/test_suites/caliptra_rt/caliptra_isr.h
+++ b/src/integration/test_suites/caliptra_rt/caliptra_isr.h
@@ -66,7 +66,7 @@ void init_interrupts(void);
 // otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr"
 inline void service_doe_error_intr() {return;}
 inline void service_doe_notif_intr() {
-    uint32_t * reg = (uint32_t *) (CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    volatile uint32_t * reg = (volatile uint32_t *) (CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
     uint32_t sts = *reg;
     /* Write 1 to Clear the pending interrupt */
     if (sts & DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
@@ -82,7 +82,7 @@ inline void service_doe_notif_intr() {
 
 inline void service_ecc_error_intr() {return;}
 inline void service_ecc_notif_intr() {
-    uint32_t * reg = (uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    volatile uint32_t * reg = (volatile uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
     uint32_t sts = *reg;
     /* Write 1 to Clear the pending interrupt */
     if (sts & ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
@@ -98,7 +98,7 @@ inline void service_ecc_notif_intr() {
 
 inline void service_hmac_error_intr() {return;}
 inline void service_hmac_notif_intr() {
-    uint32_t * reg = (uint32_t *) (CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    volatile uint32_t * reg = (volatile uint32_t *) (CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
     uint32_t sts = *reg;
     /* Write 1 to Clear the pending interrupt */
     if (sts & HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
@@ -116,7 +116,7 @@ inline void service_kv_error_intr() {return;}
 inline void service_kv_notif_intr() {return;}
 inline void service_sha512_error_intr() {return;}
 inline void service_sha512_notif_intr() {
-    uint32_t * reg = (uint32_t *) (CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    volatile uint32_t * reg = (volatile uint32_t *) (CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
     uint32_t sts = *reg;
     /* Write 1 to Clear the pending interrupt */
     if (sts & SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
@@ -132,7 +132,7 @@ inline void service_sha512_notif_intr() {
 
 inline void service_sha256_error_intr() {return;}
 inline void service_sha256_notif_intr() {
-    uint32_t * reg = (uint32_t *) (CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    volatile uint32_t * reg = (volatile uint32_t *) (CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
     uint32_t sts = *reg;
     /* Write 1 to Clear the pending interrupt */
     if (sts & SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
@@ -154,7 +154,7 @@ inline void service_i3c_error_intr() {return;}
 inline void service_i3c_notif_intr() {return;}
 
 inline void service_soc_ifc_error_intr() {
-    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+    volatile uint32_t * reg = (volatile uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
     uint32_t sts = *reg;
     /* Write 1 to Clear the pending interrupt */
     if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
@@ -181,14 +181,14 @@ inline void service_soc_ifc_error_intr() {
         *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
         cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
     }
-    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK) {
-        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK;
-        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK;
-    }
-    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK) {
-        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK;
-        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK;
-    }
+    // if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK) {
+    //     *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK;
+    //     cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK;
+    // }
+    // if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK) {
+    //     *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK;
+    //     cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK;
+    // }
     if (sts == 0) {
         VPRINTF(ERROR,"bad soc_ifc_error_intr sts:%x\n", sts);
         SEND_STDOUT_CTRL(0x1);
@@ -197,7 +197,7 @@ inline void service_soc_ifc_error_intr() {
 }
 
 inline void service_soc_ifc_notif_intr () {
-    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    volatile uint32_t * reg = (volatile uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
     uint32_t sts = *reg;
     /* Write 1 to Clear the pending interrupt */
     if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
@@ -208,6 +208,22 @@ inline void service_soc_ifc_notif_intr () {
         *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
         cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
     }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
     if (sts == 0) {
         VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
         SEND_STDOUT_CTRL(0x1);
@@ -217,7 +233,7 @@ inline void service_soc_ifc_notif_intr () {
 
 inline void service_sha512_acc_error_intr() {return;}
 inline void service_sha512_acc_notif_intr() {
-    uint32_t * reg = (uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    volatile uint32_t * reg = (volatile uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
     uint32_t sts = *reg;
     /* Write 1 to Clear the pending interrupt */
     if (sts & SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
diff --git a/src/integration/test_suites/caliptra_rt/caliptra_rt.c b/src/integration/test_suites/caliptra_rt/caliptra_rt.c
index 183814882..5474d3032 100644
--- a/src/integration/test_suites/caliptra_rt/caliptra_rt.c
+++ b/src/integration/test_suites/caliptra_rt/caliptra_rt.c
@@ -72,6 +72,20 @@ volatile caliptra_intr_received_s cptra_intr_rcv = {
     .sha512_acc_error = 0,
     .sha512_acc_notif = 0,
 };
+#define CLEAR_INTR_FLAG_SAFELY(flag, mask) \
+    csr_clr_bits_mstatus(MSTATUS_MIE_BIT_MASK); \
+    flag &= mask; \
+    csr_set_bits_mstatus(MSTATUS_MIE_BIT_MASK);
+
+#ifndef MY_RANDOM_SEED
+#define MY_RANDOM_SEED 17
+#endif // MY_RANDOM_SEED
+
+
+enum gen_in_value {
+    WDT_CASCADE     = 0x0000abab,
+    WDT_INDEPENDENT = 0x0000efef
+};
 
 /* --------------- Function Definitions --------------- */
 void nmi_handler() {
@@ -92,6 +106,12 @@ void nmi_handler() {
             SEND_STDOUT_CTRL(0x1);
         }
     }
+    else {
+        VPRINTF(LOW, "In NMI handler\n");
+        if (lsu_read_32(CLP_SOC_IFC_REG_CPTRA_HW_ERROR_FATAL) & SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_NMI_PIN_MASK)
+            VPRINTF(LOW, "Saw hw_error_fatal.nmi_pin assertion\n");
+        while(1);
+    }
 }
 
 void caliptra_rt() {
@@ -105,8 +125,15 @@ void caliptra_rt() {
     uint32_t reg_addr;
     uint32_t read_data;
     uint32_t loop_iter;
+    uint32_t loop_iter2;
     uint32_t temp; // multi-purpose variable
 
+    //WDT vars
+    int i;
+    int wdt_rand_t1_val;
+    int wdt_rand_t2_val;
+    int mode = 0;
+
     VPRINTF(MEDIUM, "----------------------------------\n");
     VPRINTF(LOW,    "- Caliptra Validation RT!!\n"        );
     VPRINTF(MEDIUM, "----------------------------------\n");
@@ -114,11 +141,89 @@ void caliptra_rt() {
     //set NMI vector
     lsu_write_32((uintptr_t) (CLP_SOC_IFC_REG_INTERNAL_NMI_VECTOR), (uint32_t) (nmi_handler));
 
+    // Initialize rand num generator
+    VPRINTF(LOW,"\nUsing random seed = %d\n\n", MY_RANDOM_SEED);
+    srand((uint32_t) MY_RANDOM_SEED);
+
     // Runtime flow -- set ready for RT
     soc_ifc_set_flow_status_field(SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_RUNTIME_MASK);
 
+#ifdef WDT_TEST
+    VPRINTF(LOW, "Enabling WDT intr\n");
+    lsu_write_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R, SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_WDT_TIMER1_TIMEOUT_EN_MASK | SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_WDT_TIMER2_TIMEOUT_EN_MASK);
+    lsu_write_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R, SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK);
+    
+    //Generate constrained random WDT timer periods
+    wdt_rand_t1_val = rand() % 0xfff;
+    wdt_rand_t2_val = rand() % 0xfff;
+    
+    while (!(lsu_read_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R) & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK));
+    if (lsu_read_32(CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0) == WDT_CASCADE) { //rand() % 2; //0 - independent mode, 1 - cascade mode
+        VPRINTF(LOW, "Restarting WDT in cascade mode\n");
+        //Enable timer1 to start cascade mode
+        lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_EN, SOC_IFC_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_MASK);
+        //Set timer1 period to a small random value, so core can see timer1 timing out
+        lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0, wdt_rand_t1_val);
+        lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1, 0x00000000);
+        //Restart timer1
+        lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL, SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART_MASK);
+
+        while (!(lsu_read_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R) & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK));
+        //Clear timer1 intr
+        lsu_write_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R, SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK);
+
+        //Program timer1 and 2 periods to <= 0x100 to test NMI generation
+        wdt_rand_t1_val = rand() % 0x100;
+        wdt_rand_t2_val = rand() % 0x100;
+        //WDT cascade mode with t2 timeout
+        lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_EN, !SOC_IFC_REG_CPTRA_WDT_TIMER2_EN_TIMER2_EN_MASK);
+        lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0, wdt_rand_t1_val);
+        lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1, 0x00000000);
+        lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0, wdt_rand_t2_val);
+        lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1, 0x00000000);
+        lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL, SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART_MASK);
+        // lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL, SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART_MASK);
+    
+        //Don't service interrupts so it can timeout and cause NMI
+    }
+    else if (lsu_read_32(CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0) == WDT_INDEPENDENT){
+        VPRINTF(LOW, "Restarting WDT in independent mode\n");
+        lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_EN, SOC_IFC_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_MASK);
+        lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0, wdt_rand_t1_val);
+        lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1, 0x00000000);
+
+        lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_EN, SOC_IFC_REG_CPTRA_WDT_TIMER2_EN_TIMER2_EN_MASK);
+        lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0, wdt_rand_t2_val);
+        lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1, 0x00000000);
+
+        lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL, SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART_MASK);
+        lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL, SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART_MASK);
+
+        while (!(lsu_read_32(CLP_SOC_IFC_REG_CPTRA_WDT_STATUS) & SOC_IFC_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_MASK));
+        //Reset timer1 period to avoid hangs in test
+        lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0, 0xffffffff);
+        lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1, 0xffffffff);
+
+        while (!(lsu_read_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R) & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK));
+        //Clear timer1 intr
+        lsu_write_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R, SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK);
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK;
+
+        //Reset timer2 period to avoid hangs in test
+        while (!(lsu_read_32(CLP_SOC_IFC_REG_CPTRA_WDT_STATUS) & SOC_IFC_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_MASK));
+        lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0, 0xffffffff);
+        lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1, 0xffffffff);
+
+        while (!(lsu_read_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R) & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK));
+        //Clear timer2 intr
+        lsu_write_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R, SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK);
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK;
+
+    }
+#endif
     // Initialization
     init_interrupts();
+    lsu_write_32(CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTR_EN_R, 0); // FIXME tmp workaround to UVM issue with predicting SHA accelerator interrupts
 
     while(1) {
         // Service received interrupts
@@ -126,28 +231,38 @@ void caliptra_rt() {
         if (cptra_intr_rcv.soc_ifc_error   ) {
             VPRINTF(ERROR, "Intr received: soc_ifc_error\n");
             if (cptra_intr_rcv.soc_ifc_error & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
-                cptra_intr_rcv.soc_ifc_error &= ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+                CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK)
             }
             if (cptra_intr_rcv.soc_ifc_error & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) {
-                cptra_intr_rcv.soc_ifc_error &= ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+                CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK)
             }
             if (cptra_intr_rcv.soc_ifc_error & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
-                cptra_intr_rcv.soc_ifc_error &= ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+                enum mbox_fsm_e state;
+                CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK)
+                // If we entered the error state, we must use force-unlock to reset the mailbox state
+                state = (lsu_read_32(CLP_MBOX_CSR_MBOX_STATUS) & MBOX_CSR_MBOX_STATUS_MBOX_FSM_PS_MASK) >> MBOX_CSR_MBOX_STATUS_MBOX_FSM_PS_LOW;
+                if (state == MBOX_ERROR) {
+                    // clr command interrupt to avoid attempted re-processing after force-unlock
+                    if (cptra_intr_rcv.soc_ifc_notif & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
+                        CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_notif, ~SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK)
+                    }
+                    lsu_write_32(CLP_MBOX_CSR_MBOX_UNLOCK, MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK);
+                }
             }
             if (cptra_intr_rcv.soc_ifc_error & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK) {
-                cptra_intr_rcv.soc_ifc_error &= ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+                CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK)
             }
             if (cptra_intr_rcv.soc_ifc_error & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK) {
-                cptra_intr_rcv.soc_ifc_error &= ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+                CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK)
             }
             if (cptra_intr_rcv.soc_ifc_error & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) {
-                cptra_intr_rcv.soc_ifc_error &= ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+                CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK)
             }
             if (cptra_intr_rcv.soc_ifc_error & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK) {
-                cptra_intr_rcv.soc_ifc_error &= ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK;
+                CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK)
             }
             if (cptra_intr_rcv.soc_ifc_error & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK) {
-                cptra_intr_rcv.soc_ifc_error &= ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK;
+                CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK)
             }
             if (cptra_intr_rcv.soc_ifc_error & (~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK &
                                                 ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK &
@@ -170,7 +285,7 @@ void caliptra_rt() {
         if (cptra_intr_rcv.ecc_error       ) {
             VPRINTF(ERROR, "Intr received: ecc_error\n");
             if (cptra_intr_rcv.ecc_error & ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
-                cptra_intr_rcv.ecc_error &= ~ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+                CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.ecc_error, ~ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK)
             }
             if (cptra_intr_rcv.ecc_error & ~ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
                 VPRINTF(FATAL, "Intr received: unsupported ecc_error (0x%x)\n", cptra_intr_rcv.ecc_error);
@@ -212,9 +327,24 @@ void caliptra_rt() {
         }
 
         if (cptra_intr_rcv.soc_ifc_notif   ) {
+            uint8_t fsm_chk;
             VPRINTF(LOW, "Intr received: soc_ifc_notif\n");
             if (cptra_intr_rcv.soc_ifc_notif & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
-                cptra_intr_rcv.soc_ifc_notif &= ~SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+                CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_notif, ~SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK)
+                fsm_chk = soc_ifc_chk_execute_uc();
+                if (fsm_chk != 0) {
+                    if (fsm_chk == 0xF) {
+                        if (cptra_intr_rcv.soc_ifc_error & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
+                            CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK)
+                            VPRINTF(LOW, "Clearing FW soc_ifc_error intr bit (cmd fail) after servicing\n");
+                        } else {
+                            VPRINTF(ERROR, "After finding an error and resetting the mailbox with force unlock, RT firmware has not received an soc_ifc_err_intr!\n");
+                            SEND_STDOUT_CTRL(0x1);
+                            while(1);
+                        }
+                    }
+                    continue;
+                }
                 //read the mbox command
                 op = soc_ifc_read_mbox_cmd();
                 if (op.cmd & MBOX_CMD_FIELD_FW_MASK) {
@@ -224,7 +354,7 @@ void caliptra_rt() {
                     }
                     VPRINTF(MEDIUM, "Triggering FW update reset\n");
                     //Trigger firmware update reset, new fw will get copied over from ROM
-                    soc_ifc_set_fw_update_reset();
+                    soc_ifc_set_fw_update_reset((uint8_t) (rand() & 0xFF));
                 }
                 else if (op.cmd & MBOX_CMD_FIELD_RESP_MASK) {
                     VPRINTF(MEDIUM, "Received mailbox command (expecting RESP) from SOC! Got 0x%x\n", op.cmd);
@@ -252,22 +382,26 @@ void caliptra_rt() {
                         mode = (op.cmd == MBOX_CMD_SHA384_REQ) ? SHA_MBOX_384 : SHA_MBOX_512;
                         //First dword contains the start address
                         temp = soc_ifc_mbox_read_dataout_single();
-                        //dlen in bytes
-                        read_data = lsu_read_32(CLP_MBOX_CSR_MBOX_DLEN);
-                        read_data = read_data - temp;
+                        //ignore the bytes used for start address
+                        op.dlen = op.dlen - 4;
+                        //Copy the KAT to the start address using direct access
+                        for (loop_iter = 0; loop_iter<op.dlen; loop_iter+=4) {
+                            read_data = soc_ifc_mbox_read_dataout_single();
+                            soc_ifc_mbox_dir_write_single(temp+loop_iter, read_data);
+                        }
                         //Acquire SHA Accel lock
                         soc_ifc_sha_accel_acquire_lock();
                         soc_ifc_sha_accel_wr_mode(mode);
                         //write start addr in bytes
                         lsu_write_32((uintptr_t) (CLP_SHA512_ACC_CSR_START_ADDRESS), temp);
                         //write dlen in bytes
-                        lsu_write_32((uintptr_t) (CLP_SHA512_ACC_CSR_DLEN), read_data);
+                        lsu_write_32((uintptr_t) (CLP_SHA512_ACC_CSR_DLEN), op.dlen);
                         soc_ifc_sha_accel_execute();
                         soc_ifc_sha_accel_poll_status();
                         lsu_write_32((uintptr_t) (CLP_MBOX_CSR_MBOX_DLEN), (mode == SHA_MBOX_384) ? 48 : 64);
                         //read the digest and write it back to the mailbox
-                        reg_addr = (uint32_t *) CLP_SHA512_ACC_CSR_DIGEST_0;
-                        while (reg_addr <= (uint32_t*) ((mode == SHA_MBOX_384) ? CLP_SHA512_ACC_CSR_DIGEST_11 : CLP_SHA512_ACC_CSR_DIGEST_15)) {
+                        reg_addr = CLP_SHA512_ACC_CSR_DIGEST_0;
+                        while (reg_addr <= ((mode == SHA_MBOX_384) ? CLP_SHA512_ACC_CSR_DIGEST_11 : CLP_SHA512_ACC_CSR_DIGEST_15)) {
                             read_data = lsu_read_32(reg_addr);
                             lsu_write_32((uintptr_t) (CLP_MBOX_CSR_MBOX_DATAIN), read_data);
                             reg_addr = reg_addr + 4;
@@ -276,45 +410,109 @@ void caliptra_rt() {
                     }
                     else {
                         // Read provided data
-                        for (loop_iter = 0; loop_iter<op.dlen; loop_iter+=4) {
+                        read_data = soc_ifc_mbox_read_dataout_single();
+                        temp      = soc_ifc_mbox_read_dataout_single(); // Capture resp dlen
+                        for (loop_iter = 8; loop_iter<op.dlen; loop_iter+=4) {
                             read_data = soc_ifc_mbox_read_dataout_single();
-                            if (loop_iter == 4) {
-                                temp = read_data; // Capture resp dlen
-                            }
                         }
 
                         // Set resp dlen
                         lsu_write_32((uintptr_t) (CLP_MBOX_CSR_MBOX_DLEN), temp);
 
                         // Write response data
-                        srand((uint32_t) (op.cmd ^ read_data)); // Initialize rand num generator
                         for (loop_iter = 0; loop_iter<temp; loop_iter+=4) {
                             lsu_write_32((uintptr_t) (CLP_MBOX_CSR_MBOX_DATAIN), rand());
                         }
 
                     }
 
-                    soc_ifc_set_mbox_status_field(DATA_READY);
+                    fsm_chk = soc_ifc_chk_execute_uc();
+                    if (fsm_chk != 0) {
+                        if (fsm_chk == 0xF) {
+                            if (cptra_intr_rcv.soc_ifc_error & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
+                                CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK)
+                                VPRINTF(LOW, "Clearing FW soc_ifc_error intr bit (cmd fail) after servicing\n");
+                            } else {
+                                VPRINTF(ERROR, "After finding an error and resetting the mailbox with force unlock, RT firmware has not received an soc_ifc_err_intr!\n");
+                                SEND_STDOUT_CTRL(0x1);
+                                while(1);
+                            }
+                        }
+                        continue;
+                    }
+                    if (cptra_intr_rcv.soc_ifc_error & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) {
+                        CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK)
+                        VPRINTF(LOW, "Clearing FW soc_ifc_error intr bit (ECC unc) after servicing\n");
+                        soc_ifc_set_mbox_status_field(CMD_FAILURE);
+                    } else {
+                        soc_ifc_set_mbox_status_field(DATA_READY);
+                    }
                 }
                 else {
                     VPRINTF(MEDIUM, "Received mailbox command (no expected RESP) from SOC! Got 0x%x\n", op.cmd);
+                    VPRINTF(MEDIUM, "Got command with DLEN 0x%x\n", op.dlen);
+                    //Command to exercise direct read path to mailbox
+                    if (op.cmd == MBOX_CMD_DIR_RD) {
+                        // Read provided data through direct path
+                        for (loop_iter = 0; loop_iter<op.dlen; loop_iter+=4) {
+                            read_data = soc_ifc_mbox_dir_read_single(loop_iter);
+                        }
+                    }
+                    //For overrun command, read an extra dword
+                    else {
+                        if (op.cmd == MBOX_CMD_UC_OVERRUN) op.dlen = op.dlen + 4;
+                        // Read provided data
+                        for (loop_iter = 0; loop_iter<op.dlen; loop_iter+=4) {
+                            read_data = soc_ifc_mbox_read_dataout_single();
+                        }
+                    }
                     lsu_write_32((uintptr_t) (CLP_MBOX_CSR_MBOX_DLEN), 0);
-                    soc_ifc_set_mbox_status_field(CMD_COMPLETE);
+                    // Check for an error
+                    fsm_chk = soc_ifc_chk_execute_uc();
+                    if (fsm_chk != 0) {
+                        if (fsm_chk == 0xF) {
+                            if (cptra_intr_rcv.soc_ifc_error & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
+                                CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK)
+                                VPRINTF(LOW, "Clearing FW soc_ifc_error intr bit (cmd fail) after servicing\n");
+                            } else {
+                                VPRINTF(ERROR, "After finding an error and resetting the mailbox with force unlock, RT firmware has not received an soc_ifc_err_intr!\n");
+                                SEND_STDOUT_CTRL(0x1);
+                                while(1);
+                            }
+                        }
+                        continue;
+                    }
+                    //Mark the command complete
+                    if (cptra_intr_rcv.soc_ifc_error & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) {
+                        CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK)
+                        VPRINTF(LOW, "Clearing FW soc_ifc_error intr bit (ECC unc) after servicing\n");
+                        soc_ifc_set_mbox_status_field(CMD_FAILURE);
+                    } else {
+                        soc_ifc_set_mbox_status_field(CMD_COMPLETE);
+                    }
                 }
             }
             if (cptra_intr_rcv.soc_ifc_notif & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK) {
-                cptra_intr_rcv.soc_ifc_notif &= ~SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+                CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_notif, ~SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK)
             }
             if (cptra_intr_rcv.soc_ifc_notif & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
-                cptra_intr_rcv.soc_ifc_notif &= ~SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+                CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_notif, ~SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK)
+            }
+            if (cptra_intr_rcv.soc_ifc_notif & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+                CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_notif, ~SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK)
             }
             if (cptra_intr_rcv.soc_ifc_notif & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
-                cptra_intr_rcv.soc_ifc_notif &= ~SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+                CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_notif, ~SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK)
+            }
+            if (cptra_intr_rcv.soc_ifc_notif & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+                CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_notif, ~SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK)
             }
             if (cptra_intr_rcv.soc_ifc_notif & (~SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK &
                                                 ~SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK &
                                                 ~SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK &
-                                                ~SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK )) {
+                                                ~SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK &
+                                                ~SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK &
+                                                ~SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK )) {
                 VPRINTF(FATAL, "Intr received: unsupported soc_ifc_notif (0x%x)\n", cptra_intr_rcv.soc_ifc_notif);
                 SEND_STDOUT_CTRL(0x1);
                 while(1);
@@ -324,7 +522,7 @@ void caliptra_rt() {
         if (cptra_intr_rcv.doe_notif       ) {
             VPRINTF(LOW, "Intr received: doe_notif\n");
             if (cptra_intr_rcv.doe_notif & DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
-                cptra_intr_rcv.doe_notif &= ~DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+                CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.doe_notif, ~DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK)
             }
             if (cptra_intr_rcv.doe_notif & (~DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK)) {
                 VPRINTF(FATAL, "Intr received: unsupported doe_notif (0x%x)\n", cptra_intr_rcv.doe_notif);
@@ -336,7 +534,7 @@ void caliptra_rt() {
         if (cptra_intr_rcv.ecc_notif       ) {
             VPRINTF(LOW, "Intr received: ecc_notif\n");
             if (cptra_intr_rcv.ecc_notif & ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
-                cptra_intr_rcv.ecc_notif &= ~ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+                CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.ecc_notif, ~ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK)
             }
             if (cptra_intr_rcv.ecc_notif & (~ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK)) {
                 VPRINTF(FATAL, "Intr received: unsupported ecc_notif (0x%x)\n", cptra_intr_rcv.ecc_notif);
@@ -348,7 +546,7 @@ void caliptra_rt() {
         if (cptra_intr_rcv.hmac_notif      ) {
             VPRINTF(LOW, "Intr received: hmac_notif\n");
             if (cptra_intr_rcv.hmac_notif & HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
-                cptra_intr_rcv.hmac_notif &= ~HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+                CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.hmac_notif, ~HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK)
             }
             if (cptra_intr_rcv.hmac_notif & (~HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK)) {
                 VPRINTF(FATAL, "Intr received: unsupported hmac_notif (0x%x)\n", cptra_intr_rcv.hmac_notif);
@@ -364,7 +562,7 @@ void caliptra_rt() {
         if (cptra_intr_rcv.sha512_notif    ) {
             VPRINTF(LOW, "Intr received: sha512_notif\n");
             if (cptra_intr_rcv.sha512_notif & SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
-                cptra_intr_rcv.sha512_notif &= ~SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+                CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.sha512_notif, ~SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK)
             }
             if (cptra_intr_rcv.sha512_notif & (~SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK)) {
                 VPRINTF(FATAL, "Intr received: unsupported sha512_notif (0x%x)\n", cptra_intr_rcv.sha512_notif);
@@ -376,7 +574,7 @@ void caliptra_rt() {
         if (cptra_intr_rcv.sha256_notif    ) {
             VPRINTF(LOW, "Intr received: sha256_notif\n");
             if (cptra_intr_rcv.sha256_notif & SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
-                cptra_intr_rcv.sha256_notif &= ~SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+                CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.sha256_notif, ~SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK)
             }
             if (cptra_intr_rcv.sha256_notif & (~SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK)) {
                 VPRINTF(FATAL, "Intr received: unsupported sha256_notif (0x%x)\n", cptra_intr_rcv.sha256_notif);
@@ -388,7 +586,7 @@ void caliptra_rt() {
         if (cptra_intr_rcv.sha512_acc_notif) {
             VPRINTF(LOW, "Intr received: sha512_acc_notif");
             if (cptra_intr_rcv.sha512_acc_notif & SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
-                cptra_intr_rcv.sha512_acc_notif &= ~SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+                CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.sha512_acc_notif, ~SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK)
             }
             if (cptra_intr_rcv.sha512_acc_notif & (~SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK)) {
                 VPRINTF(FATAL, "Intr received: unsupported sha512_acc_notif (0x%x)\n", cptra_intr_rcv.sha512_acc_notif);
diff --git a/src/integration/test_suites/caliptra_rt/caliptra_rt.ld b/src/integration/test_suites/caliptra_rt/caliptra_rt.ld
index e143785ff..ba2ca5e6e 100644
--- a/src/integration/test_suites/caliptra_rt/caliptra_rt.ld
+++ b/src/integration/test_suites/caliptra_rt/caliptra_rt.ld
@@ -40,7 +40,7 @@ SECTIONS {
   . = _text_lma_end + 0x10; /* . (location counter) points to 0x0, force it back to next LMA here */
   _data_vma_start = 0x50010000;
   _data_lma_start = .; /* After this, . (location counter) goes back to holding VMA value */
-  .data _data_vma_start :  AT(_data_lma_start) { *(.*data) *(.rodata*) ; . = ALIGN(4); } =0x0000,
+  .data _data_vma_start :  AT(_data_lma_start) { *(.*data) *(.sdata*) *(.rodata*) *(.srodata*) ; . = ALIGN(4); } =0x0000,
   _data_lma_end = _data_lma_start + SIZEOF(.data);
 
   _bss_vma_start = ALIGN(4);
diff --git a/src/integration/test_suites/caliptra_top/caliptra_isr.h b/src/integration/test_suites/caliptra_top/caliptra_isr.h
new file mode 100644
index 000000000..3fd30343d
--- /dev/null
+++ b/src/integration/test_suites/caliptra_top/caliptra_isr.h
@@ -0,0 +1,235 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// ---------------------------------------------------------------------
+// File: caliptra_isr.h
+// Description:
+//     Provides function declarations for use by external test files, so
+//     that the ISR functionality may behave like a library.
+//     TODO:
+//     This header file includes inline function definitions for event and
+//     test specific interrupt service behavior, so it should be copied and
+//     modified for each test.
+// ---------------------------------------------------------------------
+
+#ifndef CALIPTRA_ISR_H
+    #define CALIPTRA_ISR_H
+
+#define EN_ISR_PRINTS 1
+
+#include "caliptra_defines.h"
+#include <stdint.h>
+#include "printf.h"
+
+/* --------------- symbols/typedefs --------------- */
+typedef struct {
+    uint32_t doe_error;
+    uint32_t doe_notif;
+    uint32_t ecc_error;
+    uint32_t ecc_notif;
+    uint32_t hmac_error;
+    uint32_t hmac_notif;
+    uint32_t kv_error;
+    uint32_t kv_notif;
+    uint32_t sha512_error;
+    uint32_t sha512_notif;
+    uint32_t sha256_error;
+    uint32_t sha256_notif;
+    uint32_t qspi_error;
+    uint32_t qspi_notif;
+    uint32_t uart_error;
+    uint32_t uart_notif;
+    uint32_t i3c_error;
+    uint32_t i3c_notif;
+    uint32_t soc_ifc_error;
+    uint32_t soc_ifc_notif;
+    uint32_t sha512_acc_error;
+    uint32_t sha512_acc_notif;
+} caliptra_intr_received_s;
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
+
+//////////////////////////////////////////////////////////////////////////////
+// Function Declarations
+//
+
+// Performs all the CSR setup to configure and enable vectored external interrupts
+void init_interrupts(void);
+
+// These inline functions are used to insert event-specific functionality into the
+// otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr"
+inline void service_doe_error_intr() {
+    volatile uint32_t * reg = (volatile uint32_t *) (CLP_DOE_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    if (sts != 0) {
+        cptra_intr_rcv.doe_error = 0xFFFFFFFF;
+        VPRINTF(FATAL,"caliptra_top (ROM) val image does not support interrupts!\n");
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_doe_notif_intr() {
+    volatile uint32_t * reg = (volatile uint32_t *) (CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    if (sts != 0) {
+        cptra_intr_rcv.doe_notif = 0xFFFFFFFF;
+        VPRINTF(FATAL,"caliptra_top (ROM) val image does not support interrupts!\n");
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_ecc_error_intr() {
+    volatile uint32_t * reg = (volatile uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    if (sts != 0) {
+        cptra_intr_rcv.ecc_error = 0xFFFFFFFF;
+        VPRINTF(FATAL,"caliptra_top (ROM) val image does not support interrupts!\n");
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_ecc_notif_intr() {
+    volatile uint32_t * reg = (volatile uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    if (sts != 0) {
+        cptra_intr_rcv.ecc_notif = 0xFFFFFFFF;
+        VPRINTF(FATAL,"caliptra_top (ROM) val image does not support interrupts!\n");
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_hmac_error_intr() {
+    volatile uint32_t * reg = (volatile uint32_t *) (CLP_HMAC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    if (sts != 0) {
+        cptra_intr_rcv.hmac_error = 0xFFFFFFFF;
+        VPRINTF(FATAL,"caliptra_top (ROM) val image does not support interrupts!\n");
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_hmac_notif_intr() {
+    volatile uint32_t * reg = (volatile uint32_t *) (CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    if (sts != 0) {
+        cptra_intr_rcv.hmac_notif = 0xFFFFFFFF;
+        VPRINTF(FATAL,"caliptra_top (ROM) val image does not support interrupts!\n");
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_kv_error_intr() {return;}
+inline void service_kv_notif_intr() {return;}
+inline void service_sha512_error_intr() {
+    volatile uint32_t * reg = (volatile uint32_t *) (CLP_SHA512_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    if (sts != 0) {
+        cptra_intr_rcv.sha512_error = 0xFFFFFFFF;
+        VPRINTF(FATAL,"caliptra_top (ROM) val image does not support interrupts!\n");
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha512_notif_intr() {
+    volatile uint32_t * reg = (volatile uint32_t *) (CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    if (sts != 0) {
+        cptra_intr_rcv.sha512_notif = 0xFFFFFFFF;
+        VPRINTF(FATAL,"caliptra_top (ROM) val image does not support interrupts!\n");
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha256_error_intr() {
+    volatile uint32_t * reg = (volatile uint32_t *) (CLP_SHA256_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    if (sts != 0) {
+        cptra_intr_rcv.sha256_error = 0xFFFFFFFF;
+        VPRINTF(FATAL,"caliptra_top (ROM) val image does not support interrupts!\n");
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha256_notif_intr() {
+    volatile uint32_t * reg = (volatile uint32_t *) (CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    if (sts != 0) {
+        cptra_intr_rcv.sha256_notif = 0xFFFFFFFF;
+        VPRINTF(FATAL,"caliptra_top (ROM) val image does not support interrupts!\n");
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_qspi_error_intr() {return;}
+inline void service_qspi_notif_intr() {return;}
+inline void service_uart_error_intr() {return;}
+inline void service_uart_notif_intr() {return;}
+inline void service_i3c_error_intr() {return;}
+inline void service_i3c_notif_intr() {return;}
+
+inline void service_soc_ifc_error_intr() {
+    volatile uint32_t * reg = (volatile uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    if (sts != 0) {
+        cptra_intr_rcv.soc_ifc_error = 0xFFFFFFFF;
+        VPRINTF(FATAL,"caliptra_top (ROM) val image does not support interrupts!\n");
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_soc_ifc_notif_intr () {
+    volatile uint32_t * reg = (volatile uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    if (sts != 0) {
+        cptra_intr_rcv.soc_ifc_notif = 0xFFFFFFFF;
+        VPRINTF(FATAL,"caliptra_top (ROM) val image does not support interrupts!\n");
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha512_acc_error_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    if (sts != 0) {
+        cptra_intr_rcv.sha512_acc_error = 0xFFFFFFFF;
+        VPRINTF(FATAL,"caliptra_top (ROM) val image does not support interrupts!\n");
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha512_acc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    if (sts != 0) {
+        cptra_intr_rcv.sha512_acc_notif = 0xFFFFFFFF;
+        VPRINTF(FATAL,"caliptra_top (ROM) val image does not support interrupts!\n");
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+
+#endif //CALIPTRA_ISR_H
diff --git a/src/integration/test_suites/caliptra_top/caliptra_top.c b/src/integration/test_suites/caliptra_top/caliptra_top.c
index e2e199fd9..d1ebee1a0 100644
--- a/src/integration/test_suites/caliptra_top/caliptra_top.c
+++ b/src/integration/test_suites/caliptra_top/caliptra_top.c
@@ -24,6 +24,7 @@
 #include "sha256.h"
 #include "sha512.h"
 #include "soc_ifc.h"
+#include "caliptra_isr.h"
 #include <string.h>
 #include <stdint.h>
 #include "printf.h"
@@ -37,6 +38,8 @@ volatile char* stdout = (char *)STDOUT;
 #else
     enum printf_verbosity verbosity_g = LOW;
 #endif
+volatile caliptra_intr_received_s cptra_intr_rcv;
+volatile uint32_t                 intr_count       = 0;
 
 
 /* --------------- Function Prototypes --------------- */
@@ -66,16 +69,25 @@ void main() {
     VPRINTF(MEDIUM, "----------------------------------\n");
 
     // TODO other init tasks? (interrupts later)
+    VPRINTF(LOW, "Starting WDT in cascade mode\n");
+    lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_EN, SOC_IFC_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_MASK);
 
     //Check the reset reason FIXME (as soc_ifc fn)
     reset_reason = lsu_read_32(CLP_SOC_IFC_REG_CPTRA_RESET_REASON);
 
     //Cold Boot, run DOE flows, wait for FW image
     if (reset_reason == 0x0) {
+        VPRINTF(LOW, "Beginning Cold Boot flow\n");
         doe_init(iv_data_uds, iv_data_fe, 0x6); // TODO replace 0x6 with entry indicators
 
+        VPRINTF(LOW, "Setting Flow Status\n");
         soc_ifc_set_flow_status_field(SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_MASK);
 
+        VPRINTF(LOW, "Unlocking SHA512-ACC\n");
+        // Clear SHA accelerator lock (FIPS requirement)
+        soc_ifc_w1clr_sha_lock_field(SHA512_ACC_CSR_LOCK_LOCK_MASK);
+
+        VPRINTF(LOW, "Waiting for FMC FW to be loaded\n");
         // Wait for FW available (FMC)
         do {
             intr_sts = lsu_read_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
@@ -114,6 +126,7 @@ void main() {
         soc_ifc_clr_flow_status_field(SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_MASK);
 
         // Jump to ICCM (this is the FMC image, a.k.a. Section 0)
+        VPRINTF(LOW, "FMC FW loaded into ICCM - jumping there \n");
         iccm_fmc();
     }  
     //FW Update Reset
@@ -139,13 +152,16 @@ void main() {
         // Ready for FW (need to reload the FMC)
         soc_ifc_set_flow_status_field(SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_MASK);
 
+        // Clear SHA accelerator lock (FIPS requirement)
+        soc_ifc_w1clr_sha_lock_field(SHA512_ACC_CSR_LOCK_LOCK_MASK);
+
         // Wait for FW available (FMC)
         do {
-            intr_sts = lsu_read_32( (uint32_t*) CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+            intr_sts = lsu_read_32( (uintptr_t) CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
             intr_sts &= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
         } while (!intr_sts);
         //clear the interrupt
-        lsu_write_32((uint32_t*) CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R, SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK);
+        lsu_write_32((uintptr_t) CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R, SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK);
 
         op = soc_ifc_read_mbox_cmd();
         if (op.cmd != MBOX_CMD_FMC_UPDATE) {
@@ -160,11 +176,11 @@ void main() {
 
         // Wait for FW available (RT)
         do {
-            intr_sts = lsu_read_32( (uint32_t*) CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+            intr_sts = lsu_read_32( (uintptr_t) CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
             intr_sts &= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
         } while (!intr_sts);
         //clear the interrupt
-        lsu_write_32((uint32_t*) CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R, SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK);
+        lsu_write_32((uintptr_t) CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R, SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK);
         //read the mbox command
         op = soc_ifc_read_mbox_cmd();
         if (op.cmd != MBOX_CMD_RT_UPDATE) {
diff --git a/src/integration/test_suites/fw_test_rom/fw_test_rom b/src/integration/test_suites/fw_test_rom/fw_test_rom
new file mode 100644
index 000000000..7bf33b11c
Binary files /dev/null and b/src/integration/test_suites/fw_test_rom/fw_test_rom differ
diff --git a/src/integration/test_suites/fw_test_rom/fw_test_rom.makefile b/src/integration/test_suites/fw_test_rom/fw_test_rom.makefile
new file mode 100644
index 000000000..eabd715f4
--- /dev/null
+++ b/src/integration/test_suites/fw_test_rom/fw_test_rom.makefile
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: Apache-2.0
+# Copyright 2020 Western Digital Corporation or its affiliates.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+GCC_PREFIX = riscv64-unknown-elf
+BUILD_DIR = $(CURDIR)
+
+# Define test name
+TESTNAME ?= fw_test_rom
+TESTNAME_fw = $(TESTNAME)_fw
+TEST_DIR = $(CALIPTRA_ROOT)/src/integration/test_suites/$(TESTNAME)
+
+VPATH = $(TEST_DIR) $(BUILD_DIR)
+
+# Targets
+all: program.hex
+
+clean:
+	rm -rf *.log *.s *.hex *.dis *.size *.tbl .map *.map snapshots \
+	*.exe obj* *.o csrc *.csv work \
+	dataset.asdb  library.cfg vsimsa.cfg \
+	*.h
+
+############ TEST build ###############################
+
+# Build program.hex from RUST executable
+program.hex: fw_update.hex
+	@echo "Building program.hex from $(TESTNAME) using Crypto Test rules for pre-compiled RUST executables"
+	-$(GCC_PREFIX)-objcopy -O verilog --pad-to 0x8000 --gap-fill 0xFF --no-change-warnings $(TEST_DIR)/$(TESTNAME) program.hex
+	$(GCC_PREFIX)-objdump -S  $(TEST_DIR)/$(TESTNAME) > $(TESTNAME).dis
+	$(GCC_PREFIX)-size        $(TEST_DIR)/$(TESTNAME) | tee $(TESTNAME).size
+
+fw_update.hex:
+	@echo "Building fw_update.hex from $(TESTNAME_fw) using simple hexdump on pre-compiled RUST package"
+	-hexdump -v -e '16/1 "%02x " "\n"'  $(TEST_DIR)/$(TESTNAME_fw) > fw_update.hex
+
+
+help:
+	@echo Make sure the environment variable RV_ROOT is set.
+	@echo Possible targets: help clean all program.hex
+
+.PHONY: help clean
diff --git a/src/integration/test_suites/fw_test_rom/fw_test_rom_fw b/src/integration/test_suites/fw_test_rom/fw_test_rom_fw
new file mode 100644
index 000000000..e59e82bd4
Binary files /dev/null and b/src/integration/test_suites/fw_test_rom/fw_test_rom_fw differ
diff --git a/src/integration/test_suites/hello_world_iccm/caliptra_isr.h b/src/integration/test_suites/hello_world_iccm/caliptra_isr.h
new file mode 100644
index 000000000..8f5779e04
--- /dev/null
+++ b/src/integration/test_suites/hello_world_iccm/caliptra_isr.h
@@ -0,0 +1,247 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// ---------------------------------------------------------------------
+// File: caliptra_isr.h
+// Description:
+//     Provides function declarations for use by external test files, so
+//     that the ISR functionality may behave like a library.
+//     TODO:
+//     This header file includes inline function definitions for event and
+//     test specific interrupt service behavior, so it should be copied and
+//     modified for each test.
+// ---------------------------------------------------------------------
+
+#ifndef CALIPTRA_ISR_H
+    #define CALIPTRA_ISR_H
+
+#define EN_ISR_PRINTS 1
+
+#include "caliptra_defines.h"
+#include <stdint.h>
+#include "printf.h"
+
+/* --------------- symbols/typedefs --------------- */
+typedef struct {
+    uint32_t doe_error;
+    uint32_t doe_notif;
+    uint32_t ecc_error;
+    uint32_t ecc_notif;
+    uint32_t hmac_error;
+    uint32_t hmac_notif;
+    uint32_t kv_error;
+    uint32_t kv_notif;
+    uint32_t sha512_error;
+    uint32_t sha512_notif;
+    uint32_t sha256_error;
+    uint32_t sha256_notif;
+    uint32_t qspi_error;
+    uint32_t qspi_notif;
+    uint32_t uart_error;
+    uint32_t uart_notif;
+    uint32_t i3c_error;
+    uint32_t i3c_notif;
+    uint32_t soc_ifc_error;
+    uint32_t soc_ifc_notif;
+    uint32_t sha512_acc_error;
+    uint32_t sha512_acc_notif;
+} caliptra_intr_received_s;
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
+
+//////////////////////////////////////////////////////////////////////////////
+// Function Declarations
+//
+
+// Performs all the CSR setup to configure and enable vectored external interrupts
+void init_interrupts(void);
+
+// These inline functions are used to insert event-specific functionality into the
+// otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr"
+inline void service_doe_error_intr() {return;}
+inline void service_doe_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.doe_notif |= DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad doe_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_ecc_error_intr() {return;}
+inline void service_ecc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.ecc_notif |= ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad ecc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_hmac_error_intr() {return;}
+inline void service_hmac_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.hmac_notif |= HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad hmac_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_kv_error_intr() {return;}
+inline void service_kv_notif_intr() {return;}
+inline void service_sha512_error_intr() {return;}
+inline void service_sha512_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_notif |= SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha256_error_intr() {return;}
+inline void service_sha256_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha256_notif |= SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha256_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_qspi_error_intr() {return;}
+inline void service_qspi_notif_intr() {return;}
+inline void service_uart_error_intr() {return;}
+inline void service_uart_notif_intr() {return;}
+inline void service_i3c_error_intr() {return;}
+inline void service_i3c_notif_intr() {return;}
+
+inline void service_soc_ifc_error_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_error_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_soc_ifc_notif_intr () {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha512_acc_error_intr() {return;}
+inline void service_sha512_acc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_acc_notif |= SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_acc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+
+#endif //CALIPTRA_ISR_H
diff --git a/src/integration/test_suites/hello_world_iccm/hello_world_iccm.s b/src/integration/test_suites/hello_world_iccm/hello_world_iccm.s
index a0d643154..3be592213 100644
--- a/src/integration/test_suites/hello_world_iccm/hello_world_iccm.s
+++ b/src/integration/test_suites/hello_world_iccm/hello_world_iccm.s
@@ -33,6 +33,9 @@ _start:
     li x1, 0xaaaaaaaa
     csrw 0x7c0, x1
 
+    // Call interrupt init
+    call init_interrupts
+
     li  x3, 4
     csrw    mfdc, x3     // disable store merging
     li  x3, RV_ICCM_SADR // desired destination (ICCM) for printf subroutine (i.e. VMA)
@@ -67,6 +70,11 @@ _finish:
 stdout: .word STDOUT
 .global verbosity_g
 verbosity_g: .word 2
+// FW polls this variable for intr
+.global intr_count
+intr_count: .word 0
+.global cptra_intr_rcv
+cptra_intr_rcv: .word 0
 hw_data:
 .ascii "----------------------------------------\n"
 .ascii "Hello World from VeeR EL2 ICCM   !!\n"
diff --git a/src/integration/test_suites/iccm_lock/caliptra_isr.h b/src/integration/test_suites/iccm_lock/caliptra_isr.h
index 06cfbecad..0bdef173f 100644
--- a/src/integration/test_suites/iccm_lock/caliptra_isr.h
+++ b/src/integration/test_suites/iccm_lock/caliptra_isr.h
@@ -26,12 +26,37 @@
 #ifndef CALIPTRA_ISR_H
     #define CALIPTRA_ISR_H
 
-#define EN_ISR_PRINTS 0
-
-#include "caliptra_reg.h"
+#include "caliptra_defines.h"
 #include <stdint.h>
 #include "printf.h"
 
+/* --------------- symbols/typedefs --------------- */
+typedef struct {
+    uint32_t doe_error;
+    uint32_t doe_notif;
+    uint32_t ecc_error;
+    uint32_t ecc_notif;
+    uint32_t hmac_error;
+    uint32_t hmac_notif;
+    uint32_t kv_error;
+    uint32_t kv_notif;
+    uint32_t sha512_error;
+    uint32_t sha512_notif;
+    uint32_t sha256_error;
+    uint32_t sha256_notif;
+    uint32_t qspi_error;
+    uint32_t qspi_notif;
+    uint32_t uart_error;
+    uint32_t uart_notif;
+    uint32_t i3c_error;
+    uint32_t i3c_notif;
+    uint32_t soc_ifc_error;
+    uint32_t soc_ifc_notif;
+    uint32_t sha512_acc_error;
+    uint32_t sha512_acc_notif;
+} caliptra_intr_received_s;
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
+
 //////////////////////////////////////////////////////////////////////////////
 // Function Declarations
 //
@@ -48,10 +73,12 @@ inline void service_doe_notif_intr() {
     /* Write 1 to Clear the pending interrupt */
     if (sts & DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
         *reg = DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.doe_notif |= DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
     }
     if (sts == 0) {
-        printf("bad doe_notif_intr sts:%x\n", sts);
-        printf("%c", 0x1);
+        VPRINTF(ERROR,"bad doe_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
     }
 }
 
@@ -62,10 +89,12 @@ inline void service_ecc_notif_intr() {
     /* Write 1 to Clear the pending interrupt */
     if (sts & ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
         *reg = ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.ecc_notif |= ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
     }
     if (sts == 0) {
-        printf("bad ecc_notif_intr sts:%x\n", sts);
-        printf("%c", 0x1);
+        VPRINTF(ERROR,"bad ecc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
     }
 }
 
@@ -76,10 +105,12 @@ inline void service_hmac_notif_intr() {
     /* Write 1 to Clear the pending interrupt */
     if (sts & HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
         *reg = HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.hmac_notif |= HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
     }
     if (sts == 0) {
-        printf("bad hmac_notif_intr sts:%x\n", sts);
-        printf("%c", 0x1);
+        VPRINTF(ERROR,"bad hmac_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
     }
 }
 
@@ -92,10 +123,12 @@ inline void service_sha512_notif_intr() {
     /* Write 1 to Clear the pending interrupt */
     if (sts & SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
         *reg = SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_notif |= SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
     }
     if (sts == 0) {
-        printf("bad sha512_notif_intr sts:%x\n", sts);
-        printf("%c", 0x1);
+        VPRINTF(ERROR,"bad sha512_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
     }
 }
 
@@ -106,10 +139,12 @@ inline void service_sha256_notif_intr() {
     /* Write 1 to Clear the pending interrupt */
     if (sts & SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
         *reg = SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha256_notif |= SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
     }
     if (sts == 0) {
-        printf("bad sha256_notif_intr sts:%x\n", sts);
-        printf("%c", 0x1);
+        VPRINTF(ERROR,"bad sha256_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
     }
 }
 
@@ -119,31 +154,39 @@ inline void service_uart_error_intr() {return;}
 inline void service_uart_notif_intr() {return;}
 inline void service_i3c_error_intr() {return;}
 inline void service_i3c_notif_intr() {return;}
+
 inline void service_soc_ifc_error_intr() {
     uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
     uint32_t sts = *reg;
     /* Write 1 to Clear the pending interrupt */
     if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
         *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
     }
     if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) {
         *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
     }
     if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
         *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
     }
     if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK) {
         *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
     }
     if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK) {
         *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
     }
     if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) {
         *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
     }
     if (sts == 0) {
-        printf("bad soc_ifc_error_intr sts:%x\n", sts);
-        printf("%c", 0x1);
+        VPRINTF(ERROR,"bad soc_ifc_error_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
     }
 }
 
@@ -153,31 +196,50 @@ inline void service_soc_ifc_notif_intr () {
     /* Write 1 to Clear the pending interrupt */
     if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
         *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
     }
     if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK) {
         *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
     }
     if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
         *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
     }
     if (sts == 0) {
-        printf("bad soc_ifc_notif_intr sts:%x\n", sts);
-        printf("%c", 0x1);
+        VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
     }
 }
 
-inline void service_sha512_acc_error_intr() {printf("ERROR");}
+inline void service_sha512_acc_error_intr() {return;}
 inline void service_sha512_acc_notif_intr() {
     uint32_t * reg = (uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
     uint32_t sts = *reg;
     /* Write 1 to Clear the pending interrupt */
     if (sts & SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
         *reg = SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_acc_notif |= SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
     }
     if (sts == 0) {
-        printf("bad sha512_acc_notif_intr sts:%x\n", sts);
-        printf("%c", 0x1);
+        VPRINTF(ERROR,"bad sha512_acc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
     }
 }
 
+
 #endif //CALIPTRA_ISR_H
diff --git a/src/integration/test_suites/iccm_lock/dccm.hex b/src/integration/test_suites/iccm_lock/dccm.hex
new file mode 100755
index 000000000..5b07d11c4
--- /dev/null
+++ b/src/integration/test_suites/iccm_lock/dccm.hex
@@ -0,0 +1,3608 @@
+@00011F44
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diff --git a/src/integration/test_suites/iccm_lock/iccm_lock.c b/src/integration/test_suites/iccm_lock/iccm_lock.c
index 305c72914..416c449fc 100644
--- a/src/integration/test_suites/iccm_lock/iccm_lock.c
+++ b/src/integration/test_suites/iccm_lock/iccm_lock.c
@@ -34,9 +34,35 @@ volatile uint32_t intr_count;
     enum printf_verbosity verbosity_g = LOW;
 #endif
 
+volatile caliptra_intr_received_s cptra_intr_rcv = {
+    .doe_error        = 0,
+    .doe_notif        = 0,
+    .ecc_error        = 0,
+    .ecc_notif        = 0,
+    .hmac_error       = 0,
+    .hmac_notif       = 0,
+    .kv_error         = 0,
+    .kv_notif         = 0,
+    .sha512_error     = 0,
+    .sha512_notif     = 0,
+    .sha256_error     = 0,
+    .sha256_notif     = 0,
+    .qspi_error       = 0,
+    .qspi_notif       = 0,
+    .uart_error       = 0,
+    .uart_notif       = 0,
+    .i3c_error        = 0,
+    .i3c_notif        = 0,
+    .soc_ifc_error    = 0,
+    .soc_ifc_notif    = 0,
+    .sha512_acc_error = 0,
+    .sha512_acc_notif = 0,
+};
+
 extern uintptr_t iccm_code0_start, iccm_code0_end;
 extern uintptr_t iccm_code1_start, iccm_code1_end;
 extern uintptr_t iccm_code2_start, iccm_code2_end;
+extern uintptr_t STACK;
 static uint32_t persistent_exec_cnt __attribute__ ((section(".dccm.persistent"))) = 0; // Allocate in .dccm
 static uint8_t  persistent_is_second_pass __attribute__ ((section(".dccm.persistent"))) = 0; // Allocate in .dccm
 static uint8_t  persistent_nmi_expected __attribute__ ((section(".dccm.persistent"))) = 0; // Allocate in .dccm
@@ -121,8 +147,33 @@ void main(void) {
             SEND_STDOUT_CTRL(0x1);
         }
 
+        // Try to unlock ICCM Writes (should fail)
+        *soc_ifc_iccm_lock = *soc_ifc_iccm_lock & ~SOC_IFC_REG_INTERNAL_ICCM_LOCK_LOCK_MASK;
+        if (*soc_ifc_iccm_lock & SOC_IFC_REG_INTERNAL_ICCM_LOCK_LOCK_MASK != SOC_IFC_REG_INTERNAL_ICCM_LOCK_LOCK_MASK) {
+            VPRINTF(ERROR, "ERROR: Attempt to clear ICCM_LOCK via reg write succeeded!\n");
+            SEND_STDOUT_CTRL(0x1);
+        }
+
+        // Check that DCCM can still be written/read
+        if ((uint32_t)(&STACK) + 4 <= RV_DCCM_EADR) {
+            uint32_t dccm_test_val = lsu_read_32((uintptr_t)(&STACK)+4);
+            VPRINTF(LOW, "Test DCCM at addr: 0x%x\n", (uintptr_t)(&STACK)+4);
+            dccm_test_val ^= 0xAAAAAAAA;
+            lsu_write_32((uintptr_t)(&STACK)+4, dccm_test_val);
+            if (lsu_read_32((uintptr_t)(&STACK)+4) != dccm_test_val) {
+                VPRINTF(ERROR, "ERROR: Rd data (0x%x) after wr to DCCM does not match exp (0x%x)!\n", lsu_read_32((uintptr_t)(&STACK)+4), dccm_test_val);
+                SEND_STDOUT_CTRL(0x1);
+            } else {
+                VPRINTF(LOW, "Rd data (0x%x) after DCCM wr matches exp (0x%x)!\n", lsu_read_32((uintptr_t)(&STACK)+4), dccm_test_val);
+            }
+        } else {
+            VPRINTF(FATAL, "FATAL: Unable to test DCCM access because there is no unused space in DCCM (above STACK)!\n");
+            SEND_STDOUT_CTRL(0x1);
+        }
 
-         // Read ICCM here to see if there is any error when its being read while ICCM is being locked and that reads are getting expected data
+        // Read ICCM here to check that:
+        //   - reads are getting expected data
+        //   - no error occurs when reading while ICCM is locked
         iccm_dest = ICCM;
         if (persistent_is_second_pass) {
             code_word = (uint32_t *) &iccm_code1_start;
diff --git a/src/integration/test_suites/iccm_lock/iccm_lock.hex b/src/integration/test_suites/iccm_lock/iccm_lock.hex
new file mode 100755
index 000000000..2c5097c3b
--- /dev/null
+++ b/src/integration/test_suites/iccm_lock/iccm_lock.hex
@@ -0,0 +1,2051 @@
+@00000000
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
diff --git a/src/integration/test_suites/infinite_loop/caliptra_isr.h b/src/integration/test_suites/infinite_loop/caliptra_isr.h
new file mode 100644
index 000000000..7bd443326
--- /dev/null
+++ b/src/integration/test_suites/infinite_loop/caliptra_isr.h
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// ---------------------------------------------------------------------
+// File: caliptra_isr.h
+// Description:
+//     Dummy ISRs
+// ---------------------------------------------------------------------
+
+#ifndef CALIPTRA_ISR_H
+#define CALIPTRA_ISR_H
+
+#include "caliptra_defines.h"
+#include <stdint.h>
+
+/* --------------- symbols/typedefs --------------- */
+
+typedef struct {
+    uint32_t doe_error;
+    uint32_t doe_notif;
+    uint32_t ecc_error;
+    uint32_t ecc_notif;
+    uint32_t hmac_error;
+    uint32_t hmac_notif;
+    uint32_t kv_error;
+    uint32_t kv_notif;
+    uint32_t sha512_error;
+    uint32_t sha512_notif;
+    uint32_t sha256_error;
+    uint32_t sha256_notif;
+    uint32_t qspi_error;
+    uint32_t qspi_notif;
+    uint32_t uart_error;
+    uint32_t uart_notif;
+    uint32_t i3c_error;
+    uint32_t i3c_notif;
+    uint32_t soc_ifc_error;
+    uint32_t soc_ifc_notif;
+    uint32_t sha512_acc_error;
+    uint32_t sha512_acc_notif;
+} caliptra_intr_received_s;
+
+//////////////////////////////////////////////////////////////////////////////
+// Function Declarations
+
+inline void service_doe_error_intr() {return;}
+inline void service_doe_notif_intr() {return;}
+
+inline void service_ecc_error_intr() {return;}
+inline void service_ecc_notif_intr() {return;}
+
+inline void service_hmac_error_intr() {return;}
+inline void service_hmac_notif_intr() {return;}
+
+inline void service_kv_error_intr() {return;}
+inline void service_kv_notif_intr() {return;}
+
+inline void service_sha512_error_intr() {return;}
+inline void service_sha512_notif_intr() {return;}
+
+inline void service_sha256_error_intr() {return;}
+inline void service_sha256_notif_intr() {return;}
+
+inline void service_qspi_error_intr() {return;}
+inline void service_qspi_notif_intr() {return;}
+
+inline void service_uart_error_intr() {return;}
+inline void service_uart_notif_intr() {return;}
+
+inline void service_i3c_error_intr() {return;}
+inline void service_i3c_notif_intr() {return;}
+
+inline void service_soc_ifc_error_intr() {return;}
+inline void service_soc_ifc_notif_intr () {return;}
+
+inline void service_sha512_acc_error_intr() {return;}
+inline void service_sha512_acc_notif_intr() {return;}
+
+#endif //CALIPTRA_ISR_H
diff --git a/src/integration/test_suites/infinite_loop/dump_and_compare.sh b/src/integration/test_suites/infinite_loop/dump_and_compare.sh
new file mode 100755
index 000000000..594703ba0
--- /dev/null
+++ b/src/integration/test_suites/infinite_loop/dump_and_compare.sh
@@ -0,0 +1,26 @@
+#!/bin/bash
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+set -ex
+
+# Invoke GDB and dump core registers
+riscv64-unknown-elf-gdb -n --batch -x dump_registers.gdb >gdb.log
+# Parse the log, extract register values. Skip those which change as the
+# program executes since we don't know at which point we tap in.
+cat gdb.log | grep -E '^ra |^sp |^gp |^tp |^t[01256] |^s[0-9]+ |^a[0-9]+ |^\$[0-9]+' >regdump.txt
+
+# Compare the dumps
+diff -E -y regdump_golden.txt regdump.txt
+
diff --git a/src/integration/test_suites/infinite_loop/dump_registers.gdb b/src/integration/test_suites/infinite_loop/dump_registers.gdb
new file mode 100644
index 000000000..6e491afd5
--- /dev/null
+++ b/src/integration/test_suites/infinite_loop/dump_registers.gdb
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+echo Connecting to OpenOCD...\n
+set architecture riscv:rv32
+set remotetimeout 30
+target extended-remote :3333
+
+echo Connected, waiting...\n
+shell sleep 30s
+
+echo Dumping registers...\n
+info registers
diff --git a/src/integration/test_suites/infinite_loop/infinite_loop.s b/src/integration/test_suites/infinite_loop/infinite_loop.s
new file mode 100644
index 000000000..4a3753157
--- /dev/null
+++ b/src/integration/test_suites/infinite_loop/infinite_loop.s
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+
+#include "caliptra_defines.h"
+
+.set    mfdc, 0x7f9
+
+// Code to execute
+.section .text
+.global _start
+_start:
+
+    // Enable Caches in MRAC
+    li      x1, 0xaaaaaaaa
+    csrw    0x7c0, x1
+
+    li      x3, 4
+    csrw    mfdc, x3        // disable store merging
+
+    // Set some register values
+    li      x1,  0x12345678
+    li      x2,  0xABCDEF00
+    li      x3,  0xCAFEBABA
+    li      x4,  0xDEADBEEF
+    li      x5,  0x05050505
+    li      x6,  0xA0A0A0A0
+    li      x7,  0x00FF00FF
+    li      x8,  0xCC00CC00
+
+    // Simple infinite loop program with inner and outer loop
+    li      t3,  0
+outer:
+    addi    t3, t3, 1
+    li      t4, 123
+inner:
+    addi    t4, t4, -1
+    bne     t4, zero, inner
+    jal     x0, outer
+
+.section .dccm
+.global stdout
+stdout: .word STDOUT
+.global verbosity_g
+verbosity_g: .word 2
+
+.global intr_count
+intr_count: .word 0
+.global cptra_intr_rcv
+cptra_intr_rcv: .word 0
diff --git a/src/integration/test_suites/infinite_loop/infinite_loop.yml b/src/integration/test_suites/infinite_loop/infinite_loop.yml
new file mode 100755
index 000000000..89d86fb13
--- /dev/null
+++ b/src/integration/test_suites/infinite_loop/infinite_loop.yml
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+---
+seed: 1
+testname: infinite_loop
diff --git a/src/integration/test_suites/infinite_loop/mem_access.gdb b/src/integration/test_suites/infinite_loop/mem_access.gdb
new file mode 100644
index 000000000..9c72da922
--- /dev/null
+++ b/src/integration/test_suites/infinite_loop/mem_access.gdb
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+echo Connecting to OpenOCD...\n
+set architecture riscv:rv32
+set remotetimeout 30
+target extended-remote :3333
+
+echo Connected, waiting...\n
+shell sleep 5s
+
+echo Accessing DCCM...\n
+set *(0x50000000) = 0xCAFEBABA
+set *(0x50000004) = 0xDEADBEEF
+set *(0x50000008) = 0xFEEDBACA
+set *(0x5000000C) = 0xA5A5A5A5
+print/x *0x50000000@4
+
+echo Accessing ICCM...\n
+set *(0x40000100) = 0x01234567
+set *(0x40000104) = 0x89ABCDEF
+set *(0x40000108) = 0x55555555
+set *(0x4000010C) = 0xAAAAAAAA
+print/x *0x40000100@4
+
+echo Accessing ROM...\n
+print/x *0x00000000@8
diff --git a/src/integration/test_suites/infinite_loop/mem_access.sh b/src/integration/test_suites/infinite_loop/mem_access.sh
new file mode 100755
index 000000000..d800cc099
--- /dev/null
+++ b/src/integration/test_suites/infinite_loop/mem_access.sh
@@ -0,0 +1,25 @@
+#!/bin/bash
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+set -ex
+
+# Invoke GDB
+riscv64-unknown-elf-gdb -n --batch -x mem_access.gdb >gdb.log
+# Parse the log
+cat gdb.log | grep -E '^\$[0-9]+' >out.txt
+
+# Compare the dumps
+diff -E -y mem_access_golden.txt out.txt
+
diff --git a/src/integration/test_suites/infinite_loop/mem_access_golden.txt b/src/integration/test_suites/infinite_loop/mem_access_golden.txt
new file mode 100644
index 000000000..1f6b00925
--- /dev/null
+++ b/src/integration/test_suites/infinite_loop/mem_access_golden.txt
@@ -0,0 +1,3 @@
+$1 = {0xcafebaba, 0xdeadbeef, 0xfeedbaca, 0xa5a5a5a5}
+$2 = {0x1234567, 0x89abcdef, 0x55555555, 0xaaaaaaaa}
+$3 = {0xaaaab0b7, 0xaaa08093, 0x7c009073, 0x90734191, 0x50b77f91, 0x80931234, 0xf1376780, 0x7111abcd}
diff --git a/src/integration/test_suites/infinite_loop/peripheral_access.gdb b/src/integration/test_suites/infinite_loop/peripheral_access.gdb
new file mode 100644
index 000000000..473466eeb
--- /dev/null
+++ b/src/integration/test_suites/infinite_loop/peripheral_access.gdb
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+echo Connecting to OpenOCD...\n
+set architecture riscv:rv32
+set remotetimeout 30
+target extended-remote :3333
+
+echo Connected, waiting...\n
+shell sleep 5s
+
+echo Accessing ECC...\n
+print/x *0x10008000@2
+print/x *0x10008008@2
+
+echo Accessing HMAC...\n
+print/x *0x10010000@2
+print/x *0x10010008@2
+
+echo Accessing SHA512...\n
+print/x *0x10020000@2
+print/x *0x10020008@2
+
+echo Accessing SHA256...\n
+print/x *0x10028000@2
+print/x *0x10028008@2
+
+echo Writing and reading DOE IV...\n
+set *(0x10000000) = 0xCAFEBABA
+set *(0x10000004) = 0xDEADBEEF
+set *(0x10000008) = 0xD0ED0E00
+print/x *0x10000000@3
+
diff --git a/src/integration/test_suites/infinite_loop/peripheral_access.sh b/src/integration/test_suites/infinite_loop/peripheral_access.sh
new file mode 100755
index 000000000..1f9d83cf5
--- /dev/null
+++ b/src/integration/test_suites/infinite_loop/peripheral_access.sh
@@ -0,0 +1,25 @@
+#!/bin/bash
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+set -ex
+
+# Invoke GDB
+riscv64-unknown-elf-gdb -n --batch -x peripheral_access.gdb >gdb.log
+# Parse the log
+cat gdb.log | grep -E '^\$[0-9]+' >out.txt
+
+# Compare the dumps
+diff -E -y peripheral_access_golden.txt out.txt
+
diff --git a/src/integration/test_suites/infinite_loop/peripheral_access.tcl b/src/integration/test_suites/infinite_loop/peripheral_access.tcl
new file mode 100644
index 000000000..d6bf70d37
--- /dev/null
+++ b/src/integration/test_suites/infinite_loop/peripheral_access.tcl
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+init
+
+proc compare {x y} {
+    puts "'$x' vs. '$y'"
+
+    if {[llength $y] != [llength $y]} {
+        puts "length mismatch!"
+        return -1
+    }
+
+    for {set i 0} {$i < [llength $x]} {incr i} {
+        if {[lindex $x $i] != [lindex $y $i]} {
+            puts "item $i mismatch!"
+            return -1
+        }
+    }
+
+    return 0
+}
+
+# Manually read dmstatus and check if the core is actually held in external
+# reset. In the expected state bits anyunavail allrunning anyrunning allhalted 
+# and anyhalted should be cleared.
+set val [riscv dmi_read 0x11]
+puts "dmstatus: $val"
+
+if { ($val & 0x00000F00) != 0 } {
+    echo "The core is not held in reset!"
+    shutdown error
+}
+
+echo "Accessing ECC..."
+set golden { 0x63707365 0x38342d33 0x3030312e 0x0 }
+set actual [ read_memory 0x10008000 32 4 phys ]
+if {[compare $actual $golden] != 0} {
+    shutdown error
+}
+
+echo "Accessing HMAC..."
+set golden { 0x6163686d 0x61327368 0x3030312e 0x0 }
+set actual [ read_memory 0x10010000 32 4 phys ]
+if {[compare $actual $golden] != 0} {
+    shutdown error
+}
+
+echo "Accessing SHA512..."
+set golden { 0x61327368 0x31322d35 0x3830302e 0x0 }
+set actual [ read_memory 0x10020000 32 4 phys ]
+if {[compare $actual $golden] != 0} {
+    shutdown error
+}
+
+echo "Accessing SHA256..."
+set golden { 0x61327368 0x35362d32 0x3830312e 0x0 }
+set actual [ read_memory 0x10028000 32 4 phys ]
+if {[compare $actual $golden] != 0} {
+    shutdown error
+}
+
+echo "Writing and reading DOE IV..."
+set golden { 0xCAFEBABA 0xDEADBEEF 0xD0ED0E00 }
+write_memory 0x10000000 32 $golden phys
+set actual [ read_memory 0x10000000 32 3 phys ]
+if {[compare $actual $golden] != 0} {
+    shutdown error
+}
+
+# Success
+shutdown
diff --git a/src/integration/test_suites/infinite_loop/peripheral_access_golden.txt b/src/integration/test_suites/infinite_loop/peripheral_access_golden.txt
new file mode 100644
index 000000000..2c9759e24
--- /dev/null
+++ b/src/integration/test_suites/infinite_loop/peripheral_access_golden.txt
@@ -0,0 +1,9 @@
+$1 = {0x63707365, 0x38342d33}
+$2 = {0x3030312e, 0x0}
+$3 = {0x6163686d, 0x61327368}
+$4 = {0x3030312e, 0x0}
+$5 = {0x61327368, 0x31322d35}
+$6 = {0x3830302e, 0x0}
+$7 = {0x61327368, 0x35362d32}
+$8 = {0x3830312e, 0x0}
+$9 = {0xcafebaba, 0xdeadbeef, 0xd0ed0e00}
diff --git a/src/integration/test_suites/infinite_loop/regdump_golden.txt b/src/integration/test_suites/infinite_loop/regdump_golden.txt
new file mode 100644
index 000000000..27196e7d5
--- /dev/null
+++ b/src/integration/test_suites/infinite_loop/regdump_golden.txt
@@ -0,0 +1,28 @@
+ra             0x12345678	0x12345678
+sp             0xabcdef00	0xabcdef00
+gp             0xcafebaba	0xcafebaba
+tp             0xdeadbeef	0xdeadbeef
+t0             0x5050505	84215045
+t1             0xa0a0a0a0	-1600085856
+t2             0xff00ff	16711935
+s1             0x0	0
+a0             0x0	0
+a1             0x0	0
+a2             0x0	0
+a3             0x0	0
+a4             0x0	0
+a5             0x0	0
+a6             0x0	0
+a7             0x0	0
+s2             0x0	0
+s3             0x0	0
+s4             0x0	0
+s5             0x0	0
+s6             0x0	0
+s7             0x0	0
+s8             0x0	0
+s9             0x0	0
+s10            0x0	0
+s11            0x0	0
+t5             0x0	0
+t6             0x0	0
diff --git a/src/integration/test_suites/libs/caliptra_isr/caliptra_isr.c b/src/integration/test_suites/libs/caliptra_isr/caliptra_isr.c
index 9753de607..fe7f4783e 100644
--- a/src/integration/test_suites/libs/caliptra_isr/caliptra_isr.c
+++ b/src/integration/test_suites/libs/caliptra_isr/caliptra_isr.c
@@ -19,9 +19,13 @@
 #include "veer-csr.h"
 #include "riscv-interrupts.h"
 #include "printf.h"
+#include "riscv_hw_if.h"
 
 
 extern volatile uint32_t intr_count;
+#ifdef RV_EXCEPTION_STRUCT
+extern volatile rv_exception_struct_s exc_flag;
+#endif
 
 //////////////////////////////////////////////////////////////////////////////
 // Function Declarations
@@ -38,14 +42,15 @@ void std_rv_mtvec_exception(void) __attribute__ ((interrupt ("machine"), aligned
 // "External Interrupts" are also included in this unimplemented list, just because the
 // std_rv_isr_vector_table should never reroute to External Interrupts -- Fast
 // Redirect takes care of that separately
-void std_rv_nop_machine(void) __attribute__ ((interrupt ("machine"), aligned(4)));
-void std_rv_mtvec_mei(void) __attribute__ ((interrupt ("machine") , aligned(4) , weak, alias("std_rv_nop_machine") ));
-void std_rv_mtvec_msi(void) __attribute__ ((interrupt ("machine") , aligned(4) , weak, alias("std_rv_nop_machine") ));
-void std_rv_mtvec_mti(void) __attribute__ ((interrupt ("machine") , aligned(4) , weak, alias("std_rv_nop_machine") ));
-void std_rv_mtvec_miti0(void) __attribute__ ((interrupt ("machine") , aligned(4) ));
-void std_rv_mtvec_sei(void) __attribute__ ((interrupt ("machine") , aligned(4) , weak, alias("std_rv_nop_machine") ));
-void std_rv_mtvec_ssi(void) __attribute__ ((interrupt ("machine") , aligned(4) , weak, alias("std_rv_nop_machine") ));
-void std_rv_mtvec_sti(void) __attribute__ ((interrupt ("machine") , aligned(4) , weak, alias("std_rv_nop_machine") ));
+void std_rv_nop_machine(void)     __attribute__ ((interrupt ("machine") , aligned(4)));
+void std_rv_mtvec_mei(void)       __attribute__ ((interrupt ("machine") , aligned(4) , weak, alias("std_rv_nop_machine") ));
+void std_rv_mtvec_msi(void)       __attribute__ ((interrupt ("machine") , aligned(4) , weak, alias("std_rv_nop_machine") ));
+void std_rv_mtvec_mti(void)       __attribute__ ((interrupt ("machine") , aligned(4) ));
+void std_rv_mtvec_sei(void)       __attribute__ ((interrupt ("machine") , aligned(4) , weak, alias("std_rv_nop_machine") ));
+void std_rv_mtvec_ssi(void)       __attribute__ ((interrupt ("machine") , aligned(4) , weak, alias("std_rv_nop_machine") ));
+void std_rv_mtvec_sti(void)       __attribute__ ((interrupt ("machine") , aligned(4) , weak, alias("std_rv_nop_machine") ));
+void nonstd_veer_mtvec_miti0(void)__attribute__ ((interrupt ("machine") , aligned(4) ));
+void nonstd_veer_mtvec_mcei(void) __attribute__ ((interrupt ("machine") , aligned(4) ));
 
 
 // VeeR Per-Source Vectored ISR functions
@@ -87,12 +92,12 @@ static void (* const nonstd_veer_isr_9 ) (void) = nonstd_veer_isr_sha512_error;
 static void (* const nonstd_veer_isr_10) (void) = nonstd_veer_isr_sha512_notif;    // from the param'd
 static void (* const nonstd_veer_isr_11) (void) = nonstd_veer_isr_sha256_error;    // macro "nonstd_veer_isr"
 static void (* const nonstd_veer_isr_12) (void) = nonstd_veer_isr_sha256_notif;    // below
-static void (* const nonstd_veer_isr_13) (void) = nonstd_veer_isr_qspi_error  ;    //        |
-static void (* const nonstd_veer_isr_14) (void) = nonstd_veer_isr_qspi_notif  ;    //        |
-static void (* const nonstd_veer_isr_15) (void) = nonstd_veer_isr_uart_error  ;    //        |
-static void (* const nonstd_veer_isr_16) (void) = nonstd_veer_isr_uart_notif  ;    //        |
-static void (* const nonstd_veer_isr_17) (void) = nonstd_veer_isr_i3c_error   ;    //        |
-static void (* const nonstd_veer_isr_18) (void) = nonstd_veer_isr_i3c_notif   ;    //        |
+static void (* const nonstd_veer_isr_13) (void) = std_rv_nop_machine          ;    //        |    nonstd_veer_isr_qspi_error ---.
+static void (* const nonstd_veer_isr_14) (void) = std_rv_nop_machine          ;    //        |    nonstd_veer_isr_qspi_notif    |
+static void (* const nonstd_veer_isr_15) (void) = std_rv_nop_machine          ;    //        |    nonstd_veer_isr_uart_error    | Unimplemented to
+static void (* const nonstd_veer_isr_16) (void) = std_rv_nop_machine          ;    //        |    nonstd_veer_isr_uart_notif    | save code space
+static void (* const nonstd_veer_isr_17) (void) = std_rv_nop_machine          ;    //        |    nonstd_veer_isr_i3c_error     |
+static void (* const nonstd_veer_isr_18) (void) = std_rv_nop_machine          ;    //        |    nonstd_veer_isr_i3c_notif  ---'
 static void (* const nonstd_veer_isr_19) (void) = nonstd_veer_isr_soc_ifc_error;   //        |
 static void (* const nonstd_veer_isr_20) (void) = nonstd_veer_isr_soc_ifc_notif;   //        |
 static void (* const nonstd_veer_isr_21) (void) = nonstd_veer_isr_sha512_acc_error;//        |
@@ -172,6 +177,10 @@ void init_interrupts(void) {
     volatile uint32_t * const sha512_reg     = (uint32_t*) CLP_SHA512_REG_BASE_ADDR;
     volatile uint32_t * const sha256_reg     = (uint32_t*) CLP_SHA256_REG_BASE_ADDR;
     volatile uint32_t * const sha512_acc_csr = (uint32_t*) CLP_SHA512_ACC_CSR_BASE_ADDR;
+    volatile uint32_t * const mtime_l        = (uint32_t*) CLP_SOC_IFC_REG_INTERNAL_RV_MTIME_L;
+    volatile uint32_t * const mtime_h        = (uint32_t*) CLP_SOC_IFC_REG_INTERNAL_RV_MTIME_H;
+    volatile uint32_t * const mtimecmp_l     = (uint32_t*) CLP_SOC_IFC_REG_INTERNAL_RV_MTIMECMP_L;
+    volatile uint32_t * const mtimecmp_h     = (uint32_t*) CLP_SOC_IFC_REG_INTERNAL_RV_MTIMECMP_H;
     char* DCCM = (char *) RV_DCCM_SADR;
     uint32_t value;
 
@@ -271,7 +280,7 @@ void init_interrupts(void) {
                                                                        DOE_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK;
 
     // ECC
-    // TODO error interrupt enables
+    ecc_reg[ECC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R /sizeof(uint32_t)] = ECC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_INTERNAL_EN_MASK;
     ecc_reg[ECC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R /sizeof(uint32_t)] = ECC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_MASK;
     ecc_reg[ECC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R/sizeof(uint32_t)] = ECC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK |
                                                                        ECC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK;
@@ -297,8 +306,10 @@ void init_interrupts(void) {
     // Mailbox
     // Clear DEBUG locked, which is always set on reset deassertion due to rst_val != TB input val
     soc_ifc_reg[SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R /sizeof(uint32_t)] = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    soc_ifc_reg[SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R /sizeof(uint32_t)] = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
     // Also clear the statistics counter for DEBUG locked
     soc_ifc_reg[SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_R /sizeof(uint32_t)] = 0;
+    soc_ifc_reg[SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_R /sizeof(uint32_t)] = 0;
     soc_ifc_reg[SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R /sizeof(uint32_t)] = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_INTERNAL_EN_MASK |
                                                                                SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_INV_DEV_EN_MASK  |
                                                                                SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_CMD_FAIL_EN_MASK |
@@ -311,7 +322,9 @@ void init_interrupts(void) {
     soc_ifc_reg[SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R /sizeof(uint32_t)] = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_AVAIL_EN_MASK |
                                                                                SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_MBOX_ECC_COR_EN_MASK |
                                                                                SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_DEBUG_LOCKED_EN_MASK |
-                                                                               SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_SOC_REQ_LOCK_EN_MASK;
+                                                                               SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_SCAN_MODE_EN_MASK |
+                                                                               SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_SOC_REQ_LOCK_EN_MASK |
+                                                                               SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_GEN_IN_TOGGLE_EN_MASK;
     soc_ifc_reg[SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R/sizeof(uint32_t)] = SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK |
                                                                                SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK;
 
@@ -321,10 +334,31 @@ void init_interrupts(void) {
     sha512_acc_csr[SHA512_ACC_CSR_INTR_BLOCK_RF_GLOBAL_INTR_EN_R/sizeof(uint32_t)] = SHA512_ACC_CSR_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK |
                                                                                      SHA512_ACC_CSR_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK;
 
+    // Set mtimecmp to max value to avoid spurious timer interrupts
+    *mtimecmp_l = 0xFFFFFFFF;
+    *mtimecmp_h = 0xFFFFFFFF;
+
+    // Set threshold for Correctable Error Local Interrupts
+    value = 0xd0000000;
+    __asm__ volatile ("csrw    %0, %1"
+                      : /* output: none */
+                      : "i" (VEER_CSR_MICECT),   "r" (value) /* input : immediate, register */
+                      : /* clobbers: none */);
+    __asm__ volatile ("csrw    %0, %1"
+                      : /* output: none */
+                      : "i" (VEER_CSR_MICCMECT), "r" (value) /* input : immediate, register */
+                      : /* clobbers: none */);
+    __asm__ volatile ("csrw    %0, %1"
+                      : /* output: none */
+                      : "i" (VEER_CSR_MDCCMECT), "r" (value) /* input : immediate, register */
+                      : /* clobbers: none */);
+
     // MIE
     // Enable MIE.MEI (External Interrupts)
-    // Do not enable Timer or SW Interrupts
-    csr_set_bits_mie(MIE_MEI_BIT_MASK);
+    // Enable MIE.MTI (Timer Interrupts)
+    // Enable MIE.MCEI (Correctable Error Interrupt)
+    // Do not enable SW Interrupts
+    csr_set_bits_mie(MIE_MEI_BIT_MASK | MIE_MTI_BIT_MASK | MIE_MCEI_BIT_MASK);
 
     // Global interrupt enable
     csr_set_bits_mstatus(MSTATUS_MIE_BIT_MASK);
@@ -333,11 +367,22 @@ void init_interrupts(void) {
 
 void std_rv_nop_machine(void)  {
     // Nop machine mode interrupt.
-    VPRINTF(HIGH,"nop\n");
+    VPRINTF(HIGH,"mcause:%x\n", csr_read_mcause());
     return;
 }
 
-void std_rv_mtvec_miti0(void) {
+void std_rv_mtvec_mti(void) {
+    volatile uint32_t * const mtimecmp_l     = (uint32_t*) CLP_SOC_IFC_REG_INTERNAL_RV_MTIMECMP_L;
+    volatile uint32_t * const mtimecmp_h     = (uint32_t*) CLP_SOC_IFC_REG_INTERNAL_RV_MTIMECMP_H;
+
+    // Set mtimecmp to max value to avoid further timer interrupts
+    *mtimecmp_l = 0xFFFFFFFF;
+    *mtimecmp_h = 0xFFFFFFFF;
+
+    VPRINTF(MEDIUM, "Done handling machine-mode TIMER interrupt\n");
+}
+
+void nonstd_veer_mtvec_miti0(void) {
     uint_xlen_t value;
     //Disable internal timer 0 count en to service intr
     __asm__ volatile ("csrwi %0, %1" \
@@ -347,6 +392,23 @@ void std_rv_mtvec_miti0(void) {
 
 }
 
+void nonstd_veer_mtvec_mcei(void) {
+    uint32_t mask = 0x07FFFFFF;
+    VPRINTF(HIGH,"Cor Error Local ISR\n");
+    __asm__ volatile ("csrc    %0, %1"
+                      : /* output: none */
+                      : "i" (VEER_CSR_MICECT),   "r" (mask) /* input : immediate, register */
+                      : /* clobbers: none */);
+    __asm__ volatile ("csrc    %0, %1"
+                      : /* output: none */
+                      : "i" (VEER_CSR_MICCMECT), "r" (mask) /* input : immediate, register */
+                      : /* clobbers: none */);
+    __asm__ volatile ("csrc    %0, %1"
+                      : /* output: none */
+                      : "i" (VEER_CSR_MDCCMECT), "r" (mask) /* input : immediate, register */
+                      : /* clobbers: none */);
+}
+
 static void std_rv_isr(void) {
     void (* isr) (void); // Function pointer to source-specific ISR
     SEND_STDOUT_CTRL(0xfb); //FIXME
@@ -381,7 +443,7 @@ static void std_rv_isr(void) {
                                   : "i" (VEER_CSR_MEIHAP) /* input : immediate */
                                   : /* clobbers: none */);
                 // Call the ID-specific handler
-                isr(); // ISR here is a function pointer indexed into the mtvec table
+                isr(); // ISR here is a function pointer indexed into the meivt table
                     // For Interrupt NESTING support, the handler should:
                     //  * Save meicurpl
                     //  * Read meicidpl
@@ -400,9 +462,9 @@ static void std_rv_isr(void) {
         switch (this_cause) {
         case RISCV_EXCP_LOAD_ACCESS_FAULT :
             // mscause
-            __asm__ volatile ("csrr    %0, 0x7ff"
+            __asm__ volatile ("csrr    %0, %1"
                               : "=r" (this_cause)  /* output : register */
-                              : /* input : none */
+                              : "i" (VEER_CSR_MSCAUSE) /* input : immediate */
                               : /* clobbers: none */);
             VPRINTF(LOW,"mscause:%x\n",this_cause);
             // mepc
@@ -440,7 +502,9 @@ static void std_rv_isr_vector_table(void) {
         ".org  std_rv_isr_vector_table + 11*4;"
         "jal   zero,std_rv_mtvec_mei;"  /* 11 */
         ".org  std_rv_isr_vector_table + 29*4;"
-        "jal   zero,std_rv_mtvec_miti0;" /* 29 */
+        "jal   zero,nonstd_veer_mtvec_miti0;" /* 29 */
+        ".org  std_rv_isr_vector_table + 30*4;"
+        "jal   zero,nonstd_veer_mtvec_mcei;" /* 30 */
 //        #ifndef VECTOR_TABLE_MTVEC_PLATFORM_INTS
 //        ".org  std_rv_isr_vector_table + 16*4;"
 //        "jal   std_rv_mtvec_platform_irq0;"
@@ -473,40 +537,84 @@ void std_rv_mtvec_exception(void) {
     VPRINTF(WARNING,"In:Std Excptn\nmcause:%x\n", this_cause);
     if (this_cause &  MCAUSE_INTERRUPT_BIT_MASK) {
         VPRINTF(ERROR,"Unexpected Intr bit:%x\n", 0xFFFFFFFF);
+        SEND_STDOUT_CTRL(0x1); // KILL THE SIMULATION with "ERROR"
     } else {
+        uint_xlen_t tmp_reg;
+
+        // mscause
+        __asm__ volatile ("csrr    %0, %1"
+                          : "=r" (tmp_reg)  /* output : register */
+                          : "i" (VEER_CSR_MSCAUSE) /* input : immediate */
+                          : /* clobbers: none */);
+        VPRINTF(LOW,"mscause:%x\n",tmp_reg);
+        #ifdef RV_EXCEPTION_STRUCT
+        SEND_STDOUT_CTRL(0xe4); // Disable ECC Error injection, if enabled, to allow exc_flag writes (which may be in DCCM) without corruption
+        __asm__ volatile ("fence.i");
+        exc_flag.exception_hit = 1;
+        exc_flag.mcause = this_cause;
+        exc_flag.mscause = tmp_reg;
+        #endif
+        // mepc
+        tmp_reg = csr_read_mepc();
+        VPRINTF(LOW,"mepc:%x\n",tmp_reg);
+        // mtval
+        tmp_reg = csr_read_mtval();
+        VPRINTF(LOW,"mtval:%x\n",tmp_reg);
+
         switch (this_cause) {
         case RISCV_EXCP_LOAD_ACCESS_FAULT :
-            // mscause
-            __asm__ volatile ("csrr    %0, 0x7ff"
-                              : "=r" (this_cause)  /* output : register */
-                              : /* input : none */
-                              : /* clobbers: none */);
-            VPRINTF(LOW,"mscause:%x\n",this_cause);
-            // mepc
-            this_cause = csr_read_mepc();
-            VPRINTF(LOW,"mepc:%x\n",this_cause);
-            // mtval
-            this_cause = csr_read_mtval();
-            VPRINTF(LOW,"mtval:%x\n",this_cause);
+            #ifdef RV_EXCEPTION_STRUCT
+            if (exc_flag.mscause == RISC_EXCP_MSCAUSE_DCCM_LOAD_UNC_ECC_ERR) {
+                // Increment mepc before returning, because repeating the previously
+                // failing command will cause an infinite loop back to this ISR.
+                tmp_reg = csr_read_mepc();
+                csr_write_mepc(tmp_reg + 4); // FIXME this has no guarantee of working. E.g. Compressed instructions are 2, not 4, bytes...
+
+                // Bail immediately instead of killing the sim.
+                // Caliptra RESET is expected due to FATAL Error, but if it's
+                // masked the originating test should decide what to do.
+                SEND_STDOUT_CTRL(0xfc); //FIXME
+                return;
+            }
+            #endif
+            break;
+        case RISCV_EXCP_STORE_AMO_ACCESS_FAULT :
+            #ifdef RV_EXCEPTION_STRUCT
+            if (exc_flag.mscause == RISC_EXCP_MSCAUSE_DCCM_STOR_UNC_ECC_ERR) {
+                // Bail immediately instead of killing the sim.
+                // Caliptra RESET is expected due to FATAL Error, but if it's
+                // masked the originating test should decide what to do.
+                SEND_STDOUT_CTRL(0xfc); //FIXME
+                return;
+            }
+            #endif
+            break;
+        case RISCV_EXCP_INSTRUCTION_ACCESS_FAULT :
+            #ifdef RV_EXCEPTION_STRUCT
+            if (exc_flag.mscause == RISC_EXCP_MSCAUSE_ICCM_INST_UNC_ECC_ERR) {
+                SEND_STDOUT_CTRL(0xfc); //FIXME
+
+                // Reset uC instead of killing the sim.
+                // Caliptra RESET is expected due to FATAL Error, but if it's
+                // masked the originating test won't be able to make progress
+                // after this routine returns.
+
+                // If the FATAL Error bit for ICCM ECC Error is masked, manually trigger firmware reset
+                if (lsu_read_32(CLP_SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK) & SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_ICCM_ECC_UNC_MASK) {
+                    VPRINTF(LOW, "ICCM ECC FATAL_ERROR bit is masked, no reset expected from TB: resetting the core manually!\n");
+                    lsu_write_32(CLP_SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET, SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_CORE_RST_MASK);
+                // Otherwise, wait for core reset
+                } else {
+                    VPRINTF(LOW, "ICCM ECC FATAL_ERROR bit is not masked, waiting for reset from TB!\n");
+                    while(1);
+                }
+
+            }
+            #endif
             break;
         case RISCV_EXCP_ILLEGAL_INSTRUCTION :
-            // mscause
-            __asm__ volatile ("csrr    %0, 0x7ff"
-                              : "=r" (this_cause)  /* output : register */
-                              : /* input : none */
-                              : /* clobbers: none */);
-            VPRINTF(LOW,"mscause:%x\n",this_cause);
-            // mepc
-            this_cause = csr_read_mepc();
-            VPRINTF(LOW,"mepc:%x\n",this_cause);
-            // mtval
-            this_cause = csr_read_mtval();
-            VPRINTF(LOW,"mtval:%x\n",this_cause);
             break;
         default :
-            // mepc
-            this_cause = csr_read_mepc();
-            VPRINTF(LOW,"mepc:%x\n",this_cause);
             break;
         }
     }
@@ -642,18 +750,20 @@ nonstd_veer_isr(sha512_notif)
 nonstd_veer_isr(sha256_error)
 // Non-Standard Vectored Interrupt Handler (SHA256 Notification = vector 12)
 nonstd_veer_isr(sha256_notif)
-// Non-Standard Vectored Interrupt Handler (QSPI Error = vector 13)
-nonstd_veer_isr(qspi_error)
-// Non-Standard Vectored Interrupt Handler (QSPI Notification = vector 14)
-nonstd_veer_isr(qspi_notif)
-// Non-Standard Vectored Interrupt Handler (UART Error = vector 15)
-nonstd_veer_isr(uart_error)
-// Non-Standard Vectored Interrupt Handler (UART Notification = vector 16)
-nonstd_veer_isr(uart_notif)
-// Non-Standard Vectored Interrupt Handler (I3C Error = vector 17)
-nonstd_veer_isr(i3c_error)
-// Non-Standard Vectored Interrupt Handler (I3C Notification = vector 18)
-nonstd_veer_isr(i3c_notif)
+/********************** Save FW image space by omitting these unused ISR ******
+ * // Non-Standard Vectored Interrupt Handler (QSPI Error = vector 13)          //
+ * nonstd_veer_isr(qspi_error)                                                  //
+ * // Non-Standard Vectored Interrupt Handler (QSPI Notification = vector 14)   //
+ * nonstd_veer_isr(qspi_notif)                                                  //
+ * // Non-Standard Vectored Interrupt Handler (UART Error = vector 15)          //
+ * nonstd_veer_isr(uart_error)                                                  //
+ * // Non-Standard Vectored Interrupt Handler (UART Notification = vector 16)   //
+ * nonstd_veer_isr(uart_notif)                                                  //
+ * // Non-Standard Vectored Interrupt Handler (I3C Error = vector 17)           //
+ * nonstd_veer_isr(i3c_error)                                                   //
+ * // Non-Standard Vectored Interrupt Handler (I3C Notification = vector 18)    //
+ * nonstd_veer_isr(i3c_notif)                                                   //
+******************************************************************************/
 // Non-Standard Vectored Interrupt Handler (SOC_IFC Error = vector 19)
 nonstd_veer_isr(soc_ifc_error)
 // Non-Standard Vectored Interrupt Handler (SOC_IFC Notification = vector 20)
diff --git a/src/integration/test_suites/libs/caliptra_isr/veer-csr.h b/src/integration/test_suites/libs/caliptra_isr/veer-csr.h
index a5d5c67f3..553d4b4e1 100644
--- a/src/integration/test_suites/libs/caliptra_isr/veer-csr.h
+++ b/src/integration/test_suites/libs/caliptra_isr/veer-csr.h
@@ -23,6 +23,10 @@
 //////////////////////////////////////////////////////////////////////////////
 // Non-Standard VeeR CSR offset macros
 //
+#define VEER_CSR_MICECT   0x7F0
+#define VEER_CSR_MICCMECT 0x7F1
+#define VEER_CSR_MDCCMECT 0x7F2
+#define VEER_CSR_MSCAUSE  0x7FF
 #define VEER_CSR_MEIVT    0xBC8
 #define VEER_CSR_MEIPT    0xBC9
 #define VEER_CSR_MEICPCT  0xBCA
@@ -31,6 +35,17 @@
 #define VEER_CSR_MEIHAP   0xFC8
 
 
+//////////////////////////////////////////////////////////////////////////////
+// VeeR MSCAUSE encoding
+//
+// From Table 2-10, VeeR EL2 PRM, Rev 1.4
+enum {
+    RISC_EXCP_MSCAUSE_ICCM_INST_UNC_ECC_ERR = 0x1,
+    RISC_EXCP_MSCAUSE_DCCM_LOAD_UNC_ECC_ERR = 0x1,
+    RISC_EXCP_MSCAUSE_DCCM_STOR_UNC_ECC_ERR = 0x1,
+};
+
+
 //////////////////////////////////////////////////////////////////////////////
 // VeeR PIC Memory Mapped register offset macros
 //
@@ -100,4 +115,15 @@ static inline uint_xlen_t csr_read_write_mdeau(uint_xlen_t new_value) {
 }
 
 
+//////////////////////////////////////////////////////////////////////////////
+// VeeR Core-Specific MIE/MIP values
+//
+#define MIE_MCEI_BIT_OFFSET   30
+#define MIE_MCEI_BIT_WIDTH    1
+#define MIE_MCEI_BIT_MASK     0x40000000
+#define MIP_MCEI_BIT_OFFSET   30
+#define MIP_MCEI_BIT_WIDTH    1
+#define MIP_MCEI_BIT_MASK     0x40000000
+
+
 #endif // #define VEER_CSR_H
diff --git a/src/integration/test_suites/libs/clk_gate/clk_gate.c b/src/integration/test_suites/libs/clk_gate/clk_gate.c
new file mode 100644
index 000000000..ad724e6e6
--- /dev/null
+++ b/src/integration/test_suites/libs/clk_gate/clk_gate.c
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+
+#include "clk_gate.h"
+#include "riscv_hw_if.h"
+#include "caliptra_defines.h"
+#include "printf.h"
+
+void set_mit0_and_halt_core(uint32_t mitb0, uint32_t mie_en) {
+    VPRINTF(LOW, "Enabling internal timer0 and halting core\n");
+    //Enable internal timer0
+        __asm__ volatile ("csrwi    %0, %1" \
+                        : /* output: none */        \
+                        : "i" (0x7d2), "i" (0x00)  /* input : immediate  */ \
+                        : /* clobbers: none */);
+
+        //Set internal timer0 upper bound
+        __asm__ volatile ("csrw    %0, %1" \
+                        : /* output: none */        \
+                        : "i" (0x7d3), "r" (mitb0)   /* input : immediate  */ \
+                        : /* clobbers: none */);
+
+        //Set internal timer0 control (halt_en = 1, enable = 1)
+        __asm__ volatile ("csrwi    %0, %1" \
+                        : /* output: none */        \
+                        : "i" (0x7d4), "i" (0x03)  /* input : immediate  */ \
+                        : /* clobbers: none */);
+            
+        //Set machine intr enable reg (mie) - enable internal timer0 intr
+        __asm__ volatile ("csrw    %0, %1" \
+                        : /* output: none */        \
+                        : "i" (0x304), "r" (mie_en)  /* input : immediate  */ \
+                        : /* clobbers: none */);
+
+        //Set mstatus reg - enable mie
+        __asm__ volatile ("csrwi    %0, %1" \
+                        : /* output: none */        \
+                        : "i" (0x300), "i" (0x08)  /* input : immediate  */ \
+                        : /* clobbers: none */);
+
+
+        //Halt the core
+        __asm__ volatile ("csrwi    %0, %1" \
+                    : /* output: none */        \
+                    : "i" (0x7c6), "i" (0x03)  /* input : immediate  */ \
+                    : /* clobbers: none */);
+}
+
+void set_mit0(uint32_t mitb0, uint32_t mie_en) {
+    //Enable internal timer0
+        __asm__ volatile ("csrwi    %0, %1" \
+                        : /* output: none */        \
+                        : "i" (0x7d2), "i" (0x00)  /* input : immediate  */ \
+                        : /* clobbers: none */);
+
+        //Set internal timer0 upper bound
+        __asm__ volatile ("csrw    %0, %1" \
+                        : /* output: none */        \
+                        : "i" (0x7d3), "r" (mitb0)   /* input : immediate  */ \
+                        : /* clobbers: none */);
+
+        //Set internal timer0 control (halt_en = 1, enable = 1)
+        __asm__ volatile ("csrwi    %0, %1" \
+                        : /* output: none */        \
+                        : "i" (0x7d4), "i" (0x03)  /* input : immediate  */ \
+                        : /* clobbers: none */);
+            
+        //Set machine intr enable reg (mie) - enable internal timer0 intr
+        __asm__ volatile ("csrw    %0, %1" \
+                        : /* output: none */        \
+                        : "i" (0x304), "r" (mie_en)  /* input : immediate  */ \
+                        : /* clobbers: none */);
+
+        //Set mstatus reg - enable mie
+        __asm__ volatile ("csrwi    %0, %1" \
+                        : /* output: none */        \
+                        : "i" (0x300), "i" (0x08)  /* input : immediate  */ \
+                        : /* clobbers: none */);
+}
+
+void halt_core() {
+    //Halt the core
+        __asm__ volatile ("csrwi    %0, %1" \
+                    : /* output: none */        \
+                    : "i" (0x7c6), "i" (0x03)  /* input : immediate  */ \
+                    : /* clobbers: none */);
+}
\ No newline at end of file
diff --git a/src/integration/test_suites/libs/clk_gate/clk_gate.h b/src/integration/test_suites/libs/clk_gate/clk_gate.h
new file mode 100644
index 000000000..05e45236e
--- /dev/null
+++ b/src/integration/test_suites/libs/clk_gate/clk_gate.h
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+
+#ifndef CLK_GATE_H
+    #define CLK_GATE_H
+
+#include "caliptra_defines.h"
+#include "caliptra_reg.h"
+#include "riscv_hw_if.h"
+
+/* --------------- symbols/typedefs --------------- */
+
+/* --------------- Function Prototypes --------------- */
+void set_mit0_and_halt_core(uint32_t mitb0, uint32_t mie_en);
+void set_mit0(uint32_t mitb0, uint32_t mie_en);
+void halt_core();
+
+#endif
\ No newline at end of file
diff --git a/src/integration/test_suites/libs/datavault/datavault.c b/src/integration/test_suites/libs/datavault/datavault.c
index 11cc90207..c9646e6ff 100644
--- a/src/integration/test_suites/libs/datavault/datavault.c
+++ b/src/integration/test_suites/libs/datavault/datavault.c
@@ -22,11 +22,11 @@ widereg_t dv_regs [DV_PFX_COUNT] = {
     { "STICKYDATAVAULTCTRL",                 (uint32_t *) CLP_DV_REG_STICKYDATAVAULTCTRL_0,             2,  0x1,     0x0 }, //  0. (0x1001c000) 
     { "STICKY_DATA_VAULT_ENTRY_0",           (uint32_t *) CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_0_0,       3,  DV_ONES, 0x0 }, //  1. (0x1001c028) 
     { "STICKY_DATA_VAULT_ENTRY_1",           (uint32_t *) CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_1_0,       3,  DV_ONES, 0x0 }, //  2. (0x1001c058) 
-    { "NONSTICKYDATAVAULTCTRL",              (uint32_t *) CLP_DV_REG_NONSTICKYDATAVAULTCTRL_0,          2,  0x0,     0x0 }, //  3. (0x1001c208) 
-    { "NONSTICKY_DATA_VAULT_ENTRY_0",        (uint32_t *) CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_0,    3,  0x0,     0x0 }, //  4. (0x1001c230) 
-    { "NONSTICKY_DATA_VAULT_ENTRY_1",        (uint32_t *) CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_0,    3,  0x0,     0x0 }, //  5. (0x1001c260) 
-    { "NONSTICKY_LOCKABLE_SCRATCHREG_CTRL",  (uint32_t *) CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_0, 2,  0x0,     0x0 }, //  6. (0x1001c410)
-    { "NONSTICKY_LOCKABLE_SCRATCHREG",       (uint32_t *) CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREG_0,     2,  0x0,     0x0 }, //  7. (0x1001c438) 
+    { "DATAVAULTCTRL",                       (uint32_t *) CLP_DV_REG_DATAVAULTCTRL_0,                   2,  0x0,     0x0 }, //  3. (0x1001c208) 
+    { "DATA_VAULT_ENTRY_0",                  (uint32_t *) CLP_DV_REG_DATA_VAULT_ENTRY_0_0,              3,  DV_ONES, 0x0 }, //  4. (0x1001c230) 
+    { "DATA_VAULT_ENTRY_1",                  (uint32_t *) CLP_DV_REG_DATA_VAULT_ENTRY_1_0,              3,  DV_ONES, 0x0 }, //  5. (0x1001c260) 
+    { "LOCKABLE_SCRATCHREG_CTRL",            (uint32_t *) CLP_DV_REG_LOCKABLESCRATCHREGCTRL_0,          2,  0x0,     0x0 }, //  6. (0x1001c410)
+    { "LOCKABLE_SCRATCHREG",                 (uint32_t *) CLP_DV_REG_LOCKABLESCRATCHREG_0,              2,  DV_ONES, 0x0 }, //  7. (0x1001c438) 
     { "STICKY_LOCKABLE_SCRATCHREGCTRL",      (uint32_t *) CLP_DV_REG_STICKYLOCKABLESCRATCHREGCTRL_0,    2,  0x1,     0x0 }, //  8. (0x1001c480) 
     { "STICKY_LOCKABLE_SCRATCHREG",          (uint32_t *) CLP_DV_REG_STICKYLOCKABLESCRATCHREG_0,        2,  DV_ONES, 0x0 }  //  9. (0x1001c4a0) 
 };
@@ -61,21 +61,21 @@ int lock_status_bitmap [DV_PFX_COUNT] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };  // ea
         STICKY_DATA_VAULT_ENTRY_1[1]
         STICKY_DATA_VAULT_ENTRY_1[2]
     --------------------------------------------------------------
-    NONSTICKYDATAVAULTCTRL[0] locks:       
-        NONSTICKY_DATA_VAULT_ENTRY_0[0]
-        NONSTICKY_DATA_VAULT_ENTRY_0[1]
-        NONSTICKY_DATA_VAULT_ENTRY_0[2]
-
-    NONSTICKYDATAVAULTCTRL[1] locks:       
-        NONSTICKY_DATA_VAULT_ENTRY_1[0]
-        NONSTICKY_DATA_VAULT_ENTRY_1[1]
-        NONSTICKY_DATA_VAULT_ENTRY_1[2]
+    DATAVAULTCTRL[0] locks:       
+        DATA_VAULT_ENTRY_0[0]
+        DATA_VAULT_ENTRY_0[1]
+        DATA_VAULT_ENTRY_0[2]
+
+    DATAVAULTCTRL[1] locks:       
+        DATA_VAULT_ENTRY_1[0]
+        DATA_VAULT_ENTRY_1[1]
+        DATA_VAULT_ENTRY_1[2]
     --------------------------------------------------------------
-    NONSTICKY_LOCKABLE_SCRATCHREG_CTRL[0] locks:  
-        NONSTICKY_LOCKABLE_SCRATCHREG[0]
+    LOCKABLE_SCRATCHREG_CTRL[0] locks:  
+        LOCKABLE_SCRATCHREG[0]
 
-    NONSTICKY_LOCKABLE_SCRATCHREG_CTRL[1] locks:  
-        NONSTICKY_LOCKABLE_SCRATCHREG[1]
+    LOCKABLE_SCRATCHREG_CTRL[1] locks:  
+        LOCKABLE_SCRATCHREG[1]
     --------------------------------------------------------------
     STICKY_LOCKABLE_SCRATCHREG_CTRL[0] locks:
         STICKY_LOCKABLE_SCRATCHREG[0]
@@ -99,19 +99,19 @@ widereg_t dv_regs [DV_PFX_COUNT] = {
     { "STICKY_DATA_VAULT_ENTRY_7",           (uint32_t *) CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_7_0,       12,  DV_ONES, 0x0 }, //  8. (0x1001c178) 
     { "STICKY_DATA_VAULT_ENTRY_8",           (uint32_t *) CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_8_0,       12,  DV_ONES, 0x0 }, //  9. (0x1001c1a8) 
     { "STICKY_DATA_VAULT_ENTRY_9",           (uint32_t *) CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_9_0,       12,  DV_ONES, 0x0 }, // 10. (0x1001c1d8) 
-    { "NONSTICKYDATAVAULTCTRL",              (uint32_t *) CLP_DV_REG_NONSTICKYDATAVAULTCTRL_0,          10,  0x0,     0x0 }, // 11. (0x1001c208) 
-    { "NONSTICKY_DATA_VAULT_ENTRY_0",        (uint32_t *) CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_0,    12,  0x0,     0x0 }, // 12. (0x1001c230) 
-    { "NONSTICKY_DATA_VAULT_ENTRY_1",        (uint32_t *) CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_0,    12,  0x0,     0x0 }, // 13. (0x1001c260) 
-    { "NONSTICKY_DATA_VAULT_ENTRY_2",        (uint32_t *) CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_2_0,    12,  0x0,     0x0 }, // 14. (0x1001c290) 
-    { "NONSTICKY_DATA_VAULT_ENTRY_3",        (uint32_t *) CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_3_0,    12,  0x0,     0x0 }, // 15. (0x1001c2c0) 
-    { "NONSTICKY_DATA_VAULT_ENTRY_4",        (uint32_t *) CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_4_0,    12,  0x0,     0x0 }, // 16. (0x1001c2f0) 
-    { "NONSTICKY_DATA_VAULT_ENTRY_5",        (uint32_t *) CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_5_0,    12,  0x0,     0x0 }, // 17. (0x1001c320) 
-    { "NONSTICKY_DATA_VAULT_ENTRY_6",        (uint32_t *) CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_6_0,    12,  0x0,     0x0 }, // 18. (0x1001c350) 
-    { "NONSTICKY_DATA_VAULT_ENTRY_7",        (uint32_t *) CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_7_0,    12,  0x0,     0x0 }, // 19. (0x1001c380) 
-    { "NONSTICKY_DATA_VAULT_ENTRY_8",        (uint32_t *) CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_8_0,    12,  0x0,     0x0 }, // 20. (0x1001c3b0) 
-    { "NONSTICKY_DATA_VAULT_ENTRY_9",        (uint32_t *) CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_9_0,    12,  0x0,     0x0 }, // 21. (0x1001c3e0) 
-    { "NONSTICKY_LOCKABLE_SCRATCHREG_CTRL",  (uint32_t *) CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_0, 10,  0x0,     0x0 }, // 22. (0x1001c410)
-    { "NONSTICKY_LOCKABLE_SCRATCHREG",       (uint32_t *) CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREG_0,     10,  0x0,     0x0 }, // 23. (0x1001c438) 
+    { "DATAVAULTCTRL",                       (uint32_t *) CLP_DV_REG_DATAVAULTCTRL_0,                   10,  0x0,     0x0 }, // 11. (0x1001c208) 
+    { "DATA_VAULT_ENTRY_0",                  (uint32_t *) CLP_DV_REG_DATA_VAULT_ENTRY_0_0,              12,  DV_ONES, 0x0 }, // 12. (0x1001c230) 
+    { "DATA_VAULT_ENTRY_1",                  (uint32_t *) CLP_DV_REG_DATA_VAULT_ENTRY_1_0,              12,  DV_ONES, 0x0 }, // 13. (0x1001c260) 
+    { "DATA_VAULT_ENTRY_2",                  (uint32_t *) CLP_DV_REG_DATA_VAULT_ENTRY_2_0,              12,  DV_ONES, 0x0 }, // 14. (0x1001c290) 
+    { "DATA_VAULT_ENTRY_3",                  (uint32_t *) CLP_DV_REG_DATA_VAULT_ENTRY_3_0,              12,  DV_ONES, 0x0 }, // 15. (0x1001c2c0) 
+    { "DATA_VAULT_ENTRY_4",                  (uint32_t *) CLP_DV_REG_DATA_VAULT_ENTRY_4_0,              12,  DV_ONES, 0x0 }, // 16. (0x1001c2f0) 
+    { "DATA_VAULT_ENTRY_5",                  (uint32_t *) CLP_DV_REG_DATA_VAULT_ENTRY_5_0,              12,  DV_ONES, 0x0 }, // 17. (0x1001c320) 
+    { "DATA_VAULT_ENTRY_6",                  (uint32_t *) CLP_DV_REG_DATA_VAULT_ENTRY_6_0,              12,  DV_ONES, 0x0 }, // 18. (0x1001c350) 
+    { "DATA_VAULT_ENTRY_7",                  (uint32_t *) CLP_DV_REG_DATA_VAULT_ENTRY_7_0,              12,  DV_ONES, 0x0 }, // 19. (0x1001c380) 
+    { "DATA_VAULT_ENTRY_8",                  (uint32_t *) CLP_DV_REG_DATA_VAULT_ENTRY_8_0,              12,  DV_ONES, 0x0 }, // 20. (0x1001c3b0) 
+    { "DATA_VAULT_ENTRY_9",                  (uint32_t *) CLP_DV_REG_DATA_VAULT_ENTRY_9_0,              12,  DV_ONES, 0x0 }, // 21. (0x1001c3e0) 
+    { "LOCKABLE_SCRATCHREG_CTRL",            (uint32_t *) CLP_DV_REG_LOCKABLESCRATCHREGCTRL_0,          10,  0x0,     0x0 }, // 22. (0x1001c410)
+    { "LOCKABLE_SCRATCHREG",                 (uint32_t *) CLP_DV_REG_LOCKABLESCRATCHREG_0,              10,  DV_ONES, 0x0 }, // 23. (0x1001c438) 
     { "NONSTICKY_GENERIC_SCRATCHREG",        (uint32_t *) CLP_DV_REG_NONSTICKYGENERICSCRATCHREG_0,      8 ,  0x0,     0x0 }, // 24. (0x1001c460) 
     { "STICKY_LOCKABLE_SCRATCHREG_CTRL",     (uint32_t *) CLP_DV_REG_STICKYLOCKABLESCRATCHREGCTRL_0,    8 ,  0x1,     0x0 }, // 25. (0x1001c480) 
     { "STICKY_LOCKABLE_SCRATCHREG",          (uint32_t *) CLP_DV_REG_STICKYLOCKABLESCRATCHREG_0,        8 ,  DV_ONES, 0x0 }  // 26. (0x1001c4a0) 
diff --git a/src/integration/test_suites/libs/ecc/ecc.c b/src/integration/test_suites/libs/ecc/ecc.c
index 12c1d2c28..5f97375f0 100644
--- a/src/integration/test_suites/libs/ecc/ecc.c
+++ b/src/integration/test_suites/libs/ecc/ecc.c
@@ -14,35 +14,26 @@
 //
 
 #include "caliptra_defines.h"
-#include "riscv_hw_if.h"
-#include <string.h>
-#include <stdint.h>
+//#include "riscv_hw_if.h"
+//#include <string.h>
+//#include <stdint.h>
 #include "printf.h"
 #include "ecc.h"
+#include "caliptra_isr.h"
 
-
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
 
 void wait_for_ecc_intr(){
     printf("ECC flow in progress...\n");
-    while((lsu_read_32(CLP_ECC_REG_ECC_STATUS) & ECC_REG_ECC_STATUS_VALID_MASK) == 0){
-        __asm__ volatile ("wfi"); // "Wait for interrupt"
-        // Sleep during ECC operation to allow ISR to execute and show idle time in sims
-        for (uint16_t slp = 0; slp < 100; slp++) {
-            __asm__ volatile ("nop"); // Sleep loop as "nop"
-        }
-    };
-    /* TODO
-    printf("ECC flow in progress...\n");
-    while(ecc_intr_status == 0){
+    while((cptra_intr_rcv.ecc_error == 0) & (cptra_intr_rcv.ecc_notif == 0)){
         __asm__ volatile ("wfi"); // "Wait for interrupt"
         // Sleep during ECC operation to allow ISR to execute and show idle time in sims
         for (uint16_t slp = 0; slp < 100; slp++) {
             __asm__ volatile ("nop"); // Sleep loop as "nop"
         }
     };
-    printf("Received ECC intr with status = %x\n", ecc_intr_status);
-    ecc_intr_status = 0;
-    */
+    //printf("Received ECC error intr with status = %d\n", cptra_intr_rcv.ecc_error);
+    printf("Received ECC notif/ err intr with status = %d/ %d\n", cptra_intr_rcv.ecc_notif, cptra_intr_rcv.ecc_error);
 }
 
 void ecc_zeroize(){
diff --git a/src/integration/test_suites/libs/ecc/ecc.h b/src/integration/test_suites/libs/ecc/ecc.h
index f193e9d57..041ead072 100644
--- a/src/integration/test_suites/libs/ecc/ecc.h
+++ b/src/integration/test_suites/libs/ecc/ecc.h
@@ -35,5 +35,6 @@ void ecc_signing_flow(ecc_io privkey, ecc_io msg, ecc_io iv, ecc_io sign_r, ecc_
 void ecc_verifying_flow(ecc_io msg, ecc_io pubkey_x, ecc_io pubkey_y, ecc_io sign_r, ecc_io sign_s);
 void ecc_pcr_signing_flow(ecc_io iv, ecc_io sign_r, ecc_io sign_s);
 void ecc_zeroize();
+void wait_for_ecc_intr();
 
 #endif
diff --git a/src/integration/test_suites/libs/hmac/hmac.c b/src/integration/test_suites/libs/hmac/hmac.c
index b7810c3e4..7d6f28e46 100644
--- a/src/integration/test_suites/libs/hmac/hmac.c
+++ b/src/integration/test_suites/libs/hmac/hmac.c
@@ -16,6 +16,22 @@
 #include "caliptra_defines.h"
 #include "printf.h"
 #include "hmac.h"
+#include "caliptra_isr.h"
+
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
+
+void wait_for_hmac_intr(){
+    printf("HMAC flow in progress...\n");
+    while((cptra_intr_rcv.hmac_error == 0) & (cptra_intr_rcv.hmac_notif == 0)){
+        __asm__ volatile ("wfi"); // "Wait for interrupt"
+        // Sleep during HMAC operation to allow ISR to execute and show idle time in sims
+        for (uint16_t slp = 0; slp < 100; slp++) {
+            __asm__ volatile ("nop"); // Sleep loop as "nop"
+        }
+    };
+    //printf("Received HMAC error intr with status = %d\n", cptra_intr_rcv.hmac_error);
+    printf("Received HMAC notif intr with status = %d\n", cptra_intr_rcv.hmac_notif);
+}
 
 void hmac_zeroize(){
     printf("HMAC zeroize flow.\n");
@@ -92,6 +108,8 @@ void hmac_flow(hmac_io key, hmac_io block, hmac_io lfsr_seed, hmac_io tag){
     lsu_write_32(CLP_HMAC_REG_HMAC384_CTRL, HMAC_REG_HMAC384_CTRL_INIT_MASK);
 
     // wait for HMAC process to be done
+    wait_for_hmac_intr();
+
     if (tag.kv_intf){
         // wait for HMAC process - check dest done
         printf("Load TAG data from HMAC to KV\n");
diff --git a/src/integration/test_suites/libs/jtagdpi/README.md b/src/integration/test_suites/libs/jtagdpi/README.md
new file mode 100644
index 000000000..54750ef1f
--- /dev/null
+++ b/src/integration/test_suites/libs/jtagdpi/README.md
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: Apache-2.0
+# 
+# # Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+# # http://www.apache.org/licenses/LICENSE-2.0 
+# # Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+JTAG DPI module for OpenOCD remote_bitbang driver
+=================================================
+
+This DPI module provides a "virtual" JTAG connection between a simulated chip
+and [OpenOCD](http://openocd.org/). It makes use of the `remote_bitbang` JTAG
+driver shipped with OpenOCD, which forwards JTAG requests over TCP to a remote
+server. The `jtagdpi` module is instantiated in the hardware simulation to
+receive the JTAG requests from OpenOCD and drive the JTAG pins (TCK, TMS, TDI,
+etc.) from it.
+
+The `remote_bitbang` protocol is documented in the OpenOCD source tree at
+`doc/manual/jtag/drivers/remote_bitbang.txt`, or online at
+https://repo.or.cz/openocd.git/blob/HEAD:/doc/manual/jtag/drivers/remote_bitbang.txt
diff --git a/src/integration/test_suites/libs/jtagdpi/jtagdpi.c b/src/integration/test_suites/libs/jtagdpi/jtagdpi.c
new file mode 100644
index 000000000..e0b270874
--- /dev/null
+++ b/src/integration/test_suites/libs/jtagdpi/jtagdpi.c
@@ -0,0 +1,210 @@
+// Copyright lowRISC contributors.
+// Copyright 2023 Antmicro.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#include "jtagdpi.h"
+
+#include <assert.h>
+#include <stdbool.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "tcp_server.h"
+
+// Uncomment to enable JTAG DPI debugging. The code will print vertically
+// oriented waveform for all JTAG signals.
+//#define JTAGDPI_DEBUG
+
+struct jtagdpi_signals {
+  uint8_t tck;
+  uint8_t tms;
+  uint8_t tdi;
+  uint8_t tdo;
+  uint8_t trst_n;
+  uint8_t srst_n;
+};
+
+struct jtagdpi_ctx {
+  // Server context
+  struct tcp_server_ctx *sock;
+  // Signals
+  struct jtagdpi_signals curr;
+#ifdef JTAGDPI_DEBUG
+  struct jtagdpi_signals prev;
+  uint8_t init;
+#endif
+};
+
+/**
+ * Reset the JTAG signals to a "dongle unplugged" state
+ */
+static void reset_jtag_signals(struct jtagdpi_ctx *ctx) {
+  assert(ctx);
+
+  // Set all to zero
+  memset(&ctx->curr, 0, sizeof(struct jtagdpi_signals));
+#ifdef JTAGDPI_DEBUG
+  memset(&ctx->prev, 0, sizeof(struct jtagdpi_signals));
+#endif
+
+  // trst_n is pulled down (reset active) by default
+  // srst_n is pulled up (reset not active) by default
+  ctx->curr.srst_n = 1;
+#ifdef JTAGDPI_DEBUG
+  ctx->prev.srst_n = 1;
+#endif
+}
+
+/**
+ * Update the JTAG signals in the context structure
+ */
+static void update_jtag_signals(struct jtagdpi_ctx *ctx) {
+  assert(ctx);
+
+  /*
+   * Documentation pointer:
+   * The remote_bitbang protocol implemented below is documented in the OpenOCD
+   * source tree at doc/manual/jtag/drivers/remote_bitbang.txt, or online at
+   * https://repo.or.cz/openocd.git/blob/HEAD:/doc/manual/jtag/drivers/remote_bitbang.txt
+   */
+
+  // read a command byte
+  char cmd;
+  if (!tcp_server_read(ctx->sock, &cmd)) {
+    return;
+  }
+
+  bool act_send_resp = false;
+  bool act_quit = false;
+
+  // parse received command byte
+  if (cmd >= '0' && cmd <= '7') {
+    // JTAG write
+    char cmd_bit = cmd - '0';
+    ctx->curr.tdi = (cmd_bit >> 0) & 0x1;
+    ctx->curr.tms = (cmd_bit >> 1) & 0x1;
+    ctx->curr.tck = (cmd_bit >> 2) & 0x1;
+  } else if (cmd >= 'r' && cmd <= 'u') {
+    // JTAG reset (active high from OpenOCD)
+    char cmd_bit = cmd - 'r';
+    ctx->curr.srst_n = !((cmd_bit >> 0) & 0x1);
+    ctx->curr.trst_n = !((cmd_bit >> 1) & 0x1);
+  } else if (cmd == 'R') {
+    // JTAG read
+    act_send_resp = true;
+  } else if (cmd == 'B') {
+    // printf("%s: BLINK ON!\n", ctx->display_name);
+  } else if (cmd == 'b') {
+    // printf("%s: BLINK OFF!\n", ctx->display_name);
+  } else if (cmd == 'Q') {
+    // quit (client disconnect)
+    act_quit = true;
+  } else {
+    fprintf(stderr,
+            "JTAG DPI Protocol violation detected: unsupported command %c\n",
+            cmd);
+    exit(1);
+  }
+
+  // send tdo as response
+  if (act_send_resp) {
+    char tdo_ascii = ctx->curr.tdo + '0';
+    tcp_server_write(ctx->sock, tdo_ascii);
+  }
+
+  if (act_quit) {
+    printf("JTAG DPI: Remote disconnected.\n");
+    tcp_server_client_close(ctx->sock);
+  }
+}
+
+void *jtagdpi_create(const char *display_name, int listen_port) {
+  struct jtagdpi_ctx *ctx =
+      (struct jtagdpi_ctx *)calloc(1, sizeof(struct jtagdpi_ctx));
+  assert(ctx);
+
+  // Create socket
+  ctx->sock = tcp_server_create(display_name, listen_port);
+#ifdef JTAGDPI_DEBUG
+  ctx->init = 1;
+#endif
+
+  reset_jtag_signals(ctx);
+
+  printf(
+      "\n"
+      "JTAG: Virtual JTAG interface %s is listening on port %d. Use\n"
+      "OpenOCD and the following configuration to connect:\n"
+      "  interface remote_bitbang\n"
+      "  remote_bitbang_host localhost\n"
+      "  remote_bitbang_port %d\n",
+      display_name, listen_port, listen_port);
+
+  return (void *)ctx;
+}
+
+void jtagdpi_close(void *ctx_void) {
+  struct jtagdpi_ctx *ctx = (struct jtagdpi_ctx *)ctx_void;
+  if (!ctx) {
+    return;
+  }
+  tcp_server_close(ctx->sock);
+  free(ctx);
+}
+
+#ifdef JTAGDPI_DEBUG
+static void jtagdpi_dbg(struct jtagdpi_ctx *ctx) {
+
+    uint8_t* curr = (uint8_t*)&ctx->curr;
+    uint8_t* prev = (uint8_t*)&ctx->prev;
+
+    if (ctx->init) {
+        fprintf(stderr, "tck  tms  tdi  tdo trst srst\n");
+        ctx->init = 0;
+    }
+
+    for (int i=0; i<6; ++i) {
+        if (!prev[i] &&  curr[i]) {
+            fprintf(stderr, "\\    ");
+        }
+        if ( prev[i] &&  curr[i]) {
+            fprintf(stderr, " |   ");
+        }
+        if ( prev[i] && !curr[i]) {
+            fprintf(stderr, "/    ");
+        }
+        if (!prev[i] && !curr[i]) {
+            fprintf(stderr, "|    ");
+        }
+    }
+    fprintf(stderr, "\n");
+}
+#endif
+
+void jtagdpi_tick(void *ctx_void, svBit *tck, svBit *tms, svBit *tdi,
+                  svBit *trst_n, svBit *srst_n, const svBit tdo) {
+  struct jtagdpi_ctx *ctx = (struct jtagdpi_ctx *)ctx_void;
+
+  // Get TDO
+  ctx->curr.tdo = tdo;
+
+  // TODO: Evaluate moving this functionality into a separate thread
+  if (ctx) {
+    update_jtag_signals(ctx);
+  }
+
+#ifdef JTAGDPI_DEBUG
+  if (memcmp(&ctx->curr, &ctx->prev, sizeof(struct jtagdpi_signals))) {
+    jtagdpi_dbg(ctx);
+    memcpy(&ctx->prev, &ctx->curr, sizeof(struct jtagdpi_signals));
+  }
+#endif
+
+  *tdi = ctx->curr.tdi;
+  *tms = ctx->curr.tms;
+  *tck = ctx->curr.tck;
+  *srst_n = ctx->curr.srst_n;
+  *trst_n = ctx->curr.trst_n;
+}
diff --git a/src/integration/test_suites/libs/jtagdpi/jtagdpi.h b/src/integration/test_suites/libs/jtagdpi/jtagdpi.h
new file mode 100644
index 000000000..9ecb2a104
--- /dev/null
+++ b/src/integration/test_suites/libs/jtagdpi/jtagdpi.h
@@ -0,0 +1,56 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#ifndef OPENTITAN_HW_DV_DPI_JTAGDPI_JTAGDPI_H_
+#define OPENTITAN_HW_DV_DPI_JTAGDPI_JTAGDPI_H_
+
+#include <svdpi.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct jtagdpi_ctx;
+
+/**
+ * Constructor: Create and initialize jtagdpi context object
+ *
+ * Call from a initial block.
+ *
+ * @param display_name Name of the JTAG interface (for display purposes only)
+ * @param listen_port Port to listen on
+ * @return an initialized struct jtagdpi_ctx context object
+ */
+void *jtagdpi_create(const char *display_name, int listen_port);
+
+/**
+ * Destructor: Close all connections and free all resources
+ *
+ * Call from a finish block.
+ *
+ * @param ctx_void  a struct jtagdpi_ctx context object
+ */
+void jtagdpi_close(void *ctx_void);
+
+/**
+ * Drive JTAG signals
+ *
+ * Call this function from the simulation at every clock tick to read/write
+ * from/to the JTAG signals.
+ *
+ * @param ctx_void  a struct jtagdpi_ctx context object
+ * @param tck       JTAG test clock signal
+ * @param tms       JTAG test mode select signal
+ * @param tdi       JTAG test data input signal
+ * @param trst_n    JTAG test reset signal (active low)
+ * @param srst_n    JTAG system reset signal (active low)
+ * @param tdo       JTAG test data out
+ */
+void jtagdpi_tick(void *ctx_void, svBit *tck, svBit *tms, svBit *tdi,
+                  svBit *trst_n, svBit *srst_n, const svBit tdo);
+
+#ifdef __cplusplus
+}  // extern "C"
+#endif
+#endif  // OPENTITAN_HW_DV_DPI_JTAGDPI_JTAGDPI_H_
diff --git a/src/integration/test_suites/libs/jtagdpi/jtagdpi.sv b/src/integration/test_suites/libs/jtagdpi/jtagdpi.sv
new file mode 100644
index 000000000..e69d719b5
--- /dev/null
+++ b/src/integration/test_suites/libs/jtagdpi/jtagdpi.sv
@@ -0,0 +1,47 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+module jtagdpi #(
+  parameter string Name = "jtag0", // name of the JTAG interface (display only)
+  parameter int ListenPort = 44853 // TCP port to listen on
+)(
+  input  logic clk_i,
+  input  logic rst_ni,
+
+  output logic jtag_tck,
+  output logic jtag_tms,
+  output logic jtag_tdi,
+  input  logic jtag_tdo,
+  output logic jtag_trst_n,
+  output logic jtag_srst_n
+);
+
+  import "DPI-C"
+  function chandle jtagdpi_create(input string name, input int listen_port);
+
+  import "DPI-C"
+  function void jtagdpi_tick(input chandle ctx, output bit tck, output bit tms,
+                             output bit tdi, output bit trst_n,
+                             output bit srst_n, input bit tdo);
+
+  import "DPI-C"
+  function void jtagdpi_close(input chandle ctx);
+
+  chandle ctx;
+
+  initial begin
+    ctx = jtagdpi_create(Name, ListenPort);
+  end
+
+  final begin
+    jtagdpi_close(ctx);
+    ctx = null;
+  end
+
+  always_ff @(posedge clk_i, negedge rst_ni) begin
+    jtagdpi_tick(ctx, jtag_tck, jtag_tms, jtag_tdi, jtag_trst_n, jtag_srst_n,
+                 jtag_tdo);
+  end
+
+endmodule
diff --git a/src/integration/test_suites/libs/printf/printf.c b/src/integration/test_suites/libs/printf/printf.c
index a2c8161de..367fe3a1d 100644
--- a/src/integration/test_suites/libs/printf/printf.c
+++ b/src/integration/test_suites/libs/printf/printf.c
@@ -164,6 +164,7 @@ whisperPrintfImpl(const char* format, va_list ap)
 
   for (const char* fp = format; *fp; fp++)
     {
+      char* s;
       char pad = ' ';
       int width = 0;  // Field width
 
@@ -232,7 +233,12 @@ whisperPrintfImpl(const char* format, va_list ap)
           break;
 
         case 's':
-          count += whisperPuts(va_arg(ap, char*));
+          s = va_arg(ap, char*);
+          while(*s) {
+            whisperPutc(*s++);
+            ++count;
+          }
+//          count += whisperPuts(va_arg(ap, char*));
           break;
 /*
         case 'g':
diff --git a/src/integration/test_suites/libs/riscv_hw_if/link.ld b/src/integration/test_suites/libs/riscv_hw_if/link.ld
index 9e9fd868b..b4edd0b42 100644
--- a/src/integration/test_suites/libs/riscv_hw_if/link.ld
+++ b/src/integration/test_suites/libs/riscv_hw_if/link.ld
@@ -39,7 +39,7 @@ SECTIONS {
   _bss_vma_end = _bss_vma_start + SIZEOF(.bss);
 
   _end = _bss_lma_end;
-  ASSERT( _end < 0x00008000, "ERROR: ROM size exceeds 32KiB")
+  ASSERT( _end < 0x0000C000, "ERROR: ROM size exceeds 48KiB")
 
   /* DCCM as VMA and LMA */
   . = _bss_vma_end;
diff --git a/src/integration/test_suites/libs/sha256/sha256.c b/src/integration/test_suites/libs/sha256/sha256.c
index 71040cf7f..3d3940d72 100644
--- a/src/integration/test_suites/libs/sha256/sha256.c
+++ b/src/integration/test_suites/libs/sha256/sha256.c
@@ -16,6 +16,22 @@
 #include "caliptra_defines.h"
 #include "printf.h"
 #include "sha256.h"
+#include "caliptra_isr.h"
+
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
+
+void wait_for_sha256_intr(){
+    printf("SHA256 flow in progress...\n");
+    while((cptra_intr_rcv.sha256_error == 0) & (cptra_intr_rcv.sha256_notif == 0)){
+        __asm__ volatile ("wfi"); // "Wait for interrupt"
+        // Sleep during SHA256 operation to allow ISR to execute and show idle time in sims
+        for (uint16_t slp = 0; slp < 100; slp++) {
+            __asm__ volatile ("nop"); // Sleep loop as "nop"
+        }
+    };
+    //printf("Received SHA256 error intr with status = %d\n", cptra_intr_rcv.sha256_error);
+    printf("Received SHA256 notif intr with status = %d\n", cptra_intr_rcv.sha256_notif);
+}
 
 void sha256_zeroize(){
     printf("SHA256 zeroize flow.\n");
@@ -44,7 +60,7 @@ void sha256_flow(sha256_io block, uint8_t mode, sha256_io digest){
                                             (mode << SHA256_REG_SHA256_CTRL_MODE_LOW) & SHA256_REG_SHA256_CTRL_MODE_MASK);
     
     // wait for SHA to be valid
-    while((lsu_read_32(CLP_SHA256_REG_SHA256_STATUS) & SHA256_REG_SHA256_STATUS_VALID_MASK) == 0);
+    wait_for_sha256_intr();
 
     reg_ptr = (uint32_t *) CLP_SHA256_REG_SHA256_DIGEST_0;
     printf("Load DIGEST data from SHA256\n");
diff --git a/src/integration/test_suites/libs/sha512/sha512.c b/src/integration/test_suites/libs/sha512/sha512.c
index 3e3a79137..ed6f07dd4 100644
--- a/src/integration/test_suites/libs/sha512/sha512.c
+++ b/src/integration/test_suites/libs/sha512/sha512.c
@@ -17,6 +17,22 @@
 #include "sha512.h"
 #include "printf.h"
 #include "riscv_hw_if.h"
+#include "caliptra_isr.h"
+
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
+
+void wait_for_sha512_intr(){
+    printf("SHA512 flow in progress...\n");
+    while((cptra_intr_rcv.sha512_error == 0) & (cptra_intr_rcv.sha512_notif == 0)){
+        __asm__ volatile ("wfi"); // "Wait for interrupt"
+        // Sleep during SHA512 operation to allow ISR to execute and show idle time in sims
+        for (uint16_t slp = 0; slp < 100; slp++) {
+            __asm__ volatile ("nop"); // Sleep loop as "nop"
+        }
+    };
+    //printf("Received SHA512 error intr with status = %d\n", cptra_intr_rcv.sha512_error);
+    printf("Received SHA512 notif intr with status = %d\n", cptra_intr_rcv.sha512_notif);
+}
 
 void sha_init(enum sha512_mode_e mode) {
     VPRINTF(MEDIUM,"SHA512: Set mode: 0x%x and init\n", mode);
@@ -101,7 +117,7 @@ void sha384_kvflow(uint8_t sha_kv_id, uint8_t store_to_kv, uint8_t digest_kv_id,
                                              SHA512_REG_SHA512_CTRL_LAST_MASK);
 
     // wait for SHA to be valid
-    while((lsu_read_32(CLP_SHA512_REG_SHA512_STATUS) & SHA512_REG_SHA512_STATUS_VALID_MASK) == 0);
+    wait_for_sha512_intr();
 
     // if we want to store the results into kv
     printf("check digest\n");
@@ -132,4 +148,46 @@ void sha384_kvflow(uint8_t sha_kv_id, uint8_t store_to_kv, uint8_t digest_kv_id,
 void sha512_zeroize(){
     printf("SHA512 zeroize flow.\n");
     lsu_write_32(CLP_SHA512_REG_SHA512_CTRL, (1 << SHA512_REG_SHA512_CTRL_ZEROIZE_LOW) & SHA512_REG_SHA512_CTRL_ZEROIZE_MASK);
+}
+
+void sha512_flow(sha512_io block, uint8_t mode, sha512_io digest){
+    volatile uint32_t * reg_ptr;
+    uint8_t offset;
+    uint8_t fail_cmd = 0x1;
+    uint32_t sha512_digest [16];
+
+    // wait for SHA to be ready
+    while((lsu_read_32(CLP_SHA512_REG_SHA512_STATUS) & SHA512_REG_SHA512_STATUS_READY_MASK) == 0);
+
+    // Write SHA512 block
+    reg_ptr = (uint32_t*) CLP_SHA512_REG_SHA512_BLOCK_0;
+    offset = 0;
+    while (reg_ptr <= (uint32_t*) CLP_SHA512_REG_SHA512_BLOCK_31) {
+        *reg_ptr++ = block.data[offset++];
+    }
+
+    // Enable SHA512 core 
+    VPRINTF(LOW, "Enable SHA512\n");
+    lsu_write_32(CLP_SHA512_REG_SHA512_CTRL, SHA512_REG_SHA512_CTRL_INIT_MASK | 
+                                            (mode << SHA512_REG_SHA512_CTRL_MODE_LOW) & SHA512_REG_SHA512_CTRL_MODE_MASK);
+    
+    // wait for SHA to be valid
+    wait_for_sha512_intr();
+
+    reg_ptr = (uint32_t *) CLP_SHA512_REG_SHA512_DIGEST_0;
+    printf("Load DIGEST data from SHA512\n");
+    offset = 0;
+    while (reg_ptr <= (uint32_t*) CLP_SHA512_REG_SHA512_DIGEST_15) {
+        sha512_digest[offset] = *reg_ptr;
+        if (sha512_digest[offset] != digest.data[offset]) {
+            printf("At offset [%d], sha_digest data mismatch!\n", offset);
+            printf("Actual   data: 0x%x\n", sha512_digest[offset]);
+            printf("Expected data: 0x%x\n", digest.data[offset]);
+            printf("%c", fail_cmd);
+            while(1);
+        }
+        reg_ptr++;
+        offset++;
+    }
+
 }
\ No newline at end of file
diff --git a/src/integration/test_suites/libs/sha512/sha512.h b/src/integration/test_suites/libs/sha512/sha512.h
index 5dd27980f..c485f4222 100644
--- a/src/integration/test_suites/libs/sha512/sha512.h
+++ b/src/integration/test_suites/libs/sha512/sha512.h
@@ -28,6 +28,11 @@ enum sha512_mode_e {
     SHA512_512_MODE = 0x3
 };
 
+typedef struct {
+    uint8_t   data_size;
+    uint32_t  data[32];
+}sha512_io;
+
 /* --------------- Function Prototypes --------------- */
 void sha_init(enum sha512_mode_e mode);
 void sha_next(enum sha512_mode_e mode);
@@ -36,6 +41,7 @@ void sha_next_last(enum sha512_mode_e mode);
 
 void sha384_kvflow(uint8_t sha_kv_id, uint8_t store_to_kv, uint8_t digest_kv_id, uint32_t expected_digest[12]);
 void sha512_zeroize();
+void sha512_flow(sha512_io block, uint8_t mode, sha512_io digest);
 
 //polls until sha512 is ready to be used
 inline void sha512_poll_ready() {
diff --git a/src/integration/test_suites/libs/soc_ifc/soc_ifc.c b/src/integration/test_suites/libs/soc_ifc/soc_ifc.c
index 564957843..7d23f2006 100644
--- a/src/integration/test_suites/libs/soc_ifc/soc_ifc.c
+++ b/src/integration/test_suites/libs/soc_ifc/soc_ifc.c
@@ -25,6 +25,30 @@ void soc_ifc_clear_execute_reg() {
     lsu_write_32(CLP_MBOX_CSR_MBOX_EXECUTE,reg);
 }
 
+// Return 0 if the MBOX_FSM_PS field reports MBOX_EXECUTE_UC, as expected
+// Return 1 if the MBOX_FSM_PS field reports MBOX_IDLE, indicating mailbox was already force-unlocked (after receiving a cmd_avail interrupt)
+// Return F if the MBOX_FSM_PS field reports MBOX_ERROR (to which this routine responds with a force-unlock)
+// Return FF if the MBOX_FSM_PS field reports any other state, which should never happen when this is called
+uint8_t soc_ifc_chk_execute_uc() {
+    enum mbox_fsm_e state;
+    VPRINTF(HIGH,"SOC_IFC: Check mbox_status.mbox_fsm_ps\n");
+    state = (lsu_read_32(CLP_MBOX_CSR_MBOX_STATUS) & MBOX_CSR_MBOX_STATUS_MBOX_FSM_PS_MASK) >> MBOX_CSR_MBOX_STATUS_MBOX_FSM_PS_LOW;
+    if (state == MBOX_EXECUTE_UC) {
+        VPRINTF(HIGH,"SOC_IFC: Check mbox_status.mbox_fsm_ps found MBOX_EXECUTE_UC\n");
+        return 0;
+    } else if (state == MBOX_IDLE) {
+        VPRINTF(WARNING,"SOC_IFC: Check mbox_status.mbox_fsm_ps found MBOX_IDLE\n");
+        return 1;
+    } else if (state == MBOX_ERROR) {
+        VPRINTF(ERROR,"SOC_IFC: Check mbox_status.mbox_fsm_ps found MBOX_ERROR, executing mailbox force-unlock\n");
+        lsu_write_32(CLP_MBOX_CSR_MBOX_UNLOCK, MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK);
+        return 0xF;
+    } else {
+        VPRINTF(FATAL,"SOC_IFC: Check mbox_status.mbox_fsm_ps found unexpected state 0x%x\n", state);
+        return 0xFF;
+    }
+}
+
 void soc_ifc_set_mbox_status_field(enum mbox_status_e field) {
     VPRINTF(MEDIUM,"SOC_IFC: Set mbox_status field: 0x%x\n", field);
     uint32_t reg;
@@ -45,6 +69,29 @@ void soc_ifc_set_flow_status_field(uint32_t field) {
     lsu_write_32(CLP_SOC_IFC_REG_CPTRA_FLOW_STATUS,reg);
 }
 
+// This function as implemented will clear all the bits in the register on writing '1; 
+// In future, if this register has additional bits that cannot be cleared on writing '1, 
+// then this function also needs an update in addition to the RTL itself
+void soc_ifc_w1clr_sha_lock_field(uint32_t field) {
+    VPRINTF(MEDIUM,"SOC_IFC: Clear SHA accelerator lock by writing '1: 0x%x\n", field);
+    uint32_t reg;
+    reg = lsu_read_32(CLP_SHA512_ACC_CSR_LOCK);
+    if (field & ~SHA512_ACC_CSR_LOCK_LOCK_MASK) {
+       VPRINTF(FATAL, "SOC_IFC: Bad field value");
+       SEND_STDOUT_CTRL(0x1); 
+    } 
+    else if (reg & ~SHA512_ACC_CSR_LOCK_LOCK_MASK) {
+       VPRINTF(FATAL, "SOC_IFC: Bad field value");
+       SEND_STDOUT_CTRL(0x1); 
+    }
+    if (field & SHA512_ACC_CSR_LOCK_LOCK_MASK) {
+        reg = (reg & ~SHA512_ACC_CSR_LOCK_LOCK_MASK) | field;
+    } else {
+        reg |= field;
+    }
+    lsu_write_32(CLP_SHA512_ACC_CSR_LOCK,reg);
+}
+
 void soc_ifc_clr_flow_status_field(uint32_t field) {
     VPRINTF(MEDIUM,"SOC_IFC: Clear flow_status field: 0x%x\n", field);
     uint32_t reg;
@@ -180,9 +227,18 @@ void soc_ifc_fw_update(mbox_op_s op) {
         }
 }
 
-void soc_ifc_set_fw_update_reset() {
-    VPRINTF(MEDIUM,"SOC_IFC: Set fw update reset\n");
+void soc_ifc_set_fw_update_reset(uint8_t wait_cycles) {
     uint32_t reg;
+    VPRINTF(MEDIUM,"SOC_IFC: Set fw update reset with wait_cycles [%d] (%s)\n", wait_cycles, wait_cycles > 5 ? "will override" : wait_cycles > 0 ? "will use default 5" : "won't override");
+    // A 0-value argument means don't override the current value
+    if (wait_cycles) {
+        // Enforce minimum wait_cycles of 5
+        if (wait_cycles > 5) {
+            lsu_write_32(CLP_SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES, wait_cycles);
+        } else {
+            lsu_write_32(CLP_SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES, 5);
+        }
+    }
     reg = lsu_read_32(CLP_SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET);
     reg = (reg | SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_CORE_RST_MASK);
     lsu_write_32(CLP_SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET,reg);
@@ -207,4 +263,4 @@ void soc_ifc_sha_accel_poll_status() {
 void soc_ifc_sha_accel_clr_lock() {
     //Write one to clear
     lsu_write_32((CLP_SHA512_ACC_CSR_LOCK), SHA512_ACC_CSR_LOCK_LOCK_MASK);
-}   
\ No newline at end of file
+}   
diff --git a/src/integration/test_suites/libs/soc_ifc/soc_ifc.h b/src/integration/test_suites/libs/soc_ifc/soc_ifc.h
index f1f235aa9..99fd2a28e 100644
--- a/src/integration/test_suites/libs/soc_ifc/soc_ifc.h
+++ b/src/integration/test_suites/libs/soc_ifc/soc_ifc.h
@@ -34,26 +34,32 @@ enum mbox_fsm_e {
     MBOX_RDY_FOR_DATA = 0x2,
     MBOX_RDY_FOR_DLEN = 0x3,
     MBOX_EXECUTE_UC   = 0x6,
-    MBOX_EXECUTE_SOC  = 0x4
+    MBOX_EXECUTE_SOC  = 0x4,
+    MBOX_ERROR        = 0x7
 };
 
 /**
 * Decode:
 *   [31]: Firmware command
 *   [30]: Response required (if set)
+*   [29]: uC to SOC Mailbox command
 */
 enum {
-    MBOX_CMD_FIELD_FW_LOW   = 31,
-    MBOX_CMD_FIELD_RESP_LOW = 30
+    MBOX_CMD_FIELD_FW_LOW        = 31,
+    MBOX_CMD_FIELD_RESP_LOW      = 30,
+    MBOX_CMD_FIELD_UC_TO_SOC_LOW = 29
 };
 
 enum {
-    MBOX_CMD_FIELD_FW_MASK   = 1 << MBOX_CMD_FIELD_FW_LOW  ,
-    MBOX_CMD_FIELD_RESP_MASK = 1 << MBOX_CMD_FIELD_RESP_LOW
+    MBOX_CMD_FIELD_FW_MASK        = 1 << MBOX_CMD_FIELD_FW_LOW  ,
+    MBOX_CMD_FIELD_RESP_MASK      = 1 << MBOX_CMD_FIELD_RESP_LOW,
+    MBOX_CMD_FIELD_UC_TO_SOC_MASK = 1 << MBOX_CMD_FIELD_UC_TO_SOC_LOW
 };
 
 enum mbox_cmd_e {
+    MBOX_CMD_DIR_RD     = 0x01000000,
     MBOX_CMD_UC_BASIC   = 0x20000000,
+    MBOX_CMD_UC_OVERRUN = 0x20000001,
     MBOX_CMD_RESP_BASIC = 0x40000000,
     MBOX_CMD_REG_ACCESS = 0x40000001,
     MBOX_CMD_OOB_ACCESS = 0x40000002,
@@ -88,11 +94,18 @@ enum sha_accel_mode_e {
 inline uint32_t soc_ifc_mbox_read_dataout_single() {
     return lsu_read_32(CLP_MBOX_CSR_MBOX_DATAOUT);
 }
+inline uint32_t soc_ifc_mbox_dir_read_single(uint32_t rdptr) {
+    return lsu_read_32(0x30000000 + rdptr);
+}
+inline uint32_t soc_ifc_mbox_dir_write_single(uint32_t wrptr, uint32_t wrdata) {
+    lsu_write_32(0x30000000 + wrptr, wrdata);
+}
 void soc_ifc_clear_execute_reg();
+uint8_t soc_ifc_chk_execute_uc();
 void soc_ifc_set_mbox_status_field(enum mbox_status_e field);
 void soc_ifc_set_flow_status_field(uint32_t field);
 void soc_ifc_clr_flow_status_field(uint32_t field);
-void soc_ifc_set_fw_update_reset();
+void soc_ifc_set_fw_update_reset(uint8_t wait_cycles);
 inline void soc_ifc_set_iccm_lock() {
     lsu_write_32((CLP_SOC_IFC_REG_INTERNAL_ICCM_LOCK), SOC_IFC_REG_INTERNAL_ICCM_LOCK_LOCK_MASK);
 }
@@ -109,5 +122,6 @@ inline void soc_ifc_sha_accel_execute() {
 }
 void soc_ifc_sha_accel_poll_status();
 void soc_ifc_sha_accel_clr_lock();
+void soc_ifc_w1clr_sha_lock_field();
 
 #endif
diff --git a/src/integration/test_suites/libs/tcp_server/tcp_server.c b/src/integration/test_suites/libs/tcp_server/tcp_server.c
new file mode 100644
index 000000000..c0abb95c0
--- /dev/null
+++ b/src/integration/test_suites/libs/tcp_server/tcp_server.c
@@ -0,0 +1,439 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#include "tcp_server.h"
+
+#include <assert.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <netinet/in.h>
+#include <netinet/tcp.h>
+#include <pthread.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/socket.h>
+#include <sys/time.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+/**
+ * Simple buffer for passing data between TCP sockets and DPI modules
+ */
+#define BUFSIZE_BYTE 1024 // FIXME: This must be larger than the remote_bitbang
+                          // buffer in OpenOCD. Otherwise deadlock occurs.
+
+struct tcp_buf {
+  unsigned int rptr;
+  unsigned int wptr;
+  char buf[BUFSIZE_BYTE];
+};
+
+/**
+ * TCP Server thread context structure
+ */
+struct tcp_server_ctx {
+  // Writeable by the host thread
+  char *display_name;
+  uint16_t listen_port;
+  volatile bool socket_run;
+  // Writeable by the server thread
+  struct tcp_buf *buf_in;
+  struct tcp_buf *buf_out;
+  int sfd;  // socket fd
+  int cfd;  // client fd
+  pthread_t sock_thread;
+};
+
+static bool tcp_buffer_is_full(struct tcp_buf *buf) {
+  if (buf->wptr >= buf->rptr) {
+    return (buf->wptr - buf->rptr) == (BUFSIZE_BYTE - 1);
+  } else {
+    return (buf->rptr - buf->wptr) == 1;
+  }
+}
+
+static bool tcp_buffer_is_empty(struct tcp_buf *buf) {
+  return (buf->wptr == buf->rptr);
+}
+
+static void tcp_buffer_put_byte(struct tcp_buf *buf, char dat) {
+  bool done = false;
+  while (!done) {
+    if (!tcp_buffer_is_full(buf)) {
+      buf->buf[buf->wptr++] = dat;
+      buf->wptr %= BUFSIZE_BYTE;
+      done = true;
+    }
+  }
+}
+
+static bool tcp_buffer_get_byte(struct tcp_buf *buf, char *dat) {
+  if (tcp_buffer_is_empty(buf)) {
+    return false;
+  }
+  *dat = buf->buf[buf->rptr++];
+  buf->rptr %= BUFSIZE_BYTE;
+  return true;
+}
+
+static struct tcp_buf *tcp_buffer_new(void) {
+  struct tcp_buf *buf_new;
+  buf_new = (struct tcp_buf *)malloc(sizeof(struct tcp_buf));
+  buf_new->rptr = 0;
+  buf_new->wptr = 0;
+  return buf_new;
+}
+
+static void tcp_buffer_free(struct tcp_buf **buf) {
+  free(*buf);
+  *buf = NULL;
+}
+
+/**
+ * Start a TCP server
+ *
+ * This function creates attempts to create a new TCP socket instance. The
+ * socket is a non-blocking stream socket, with buffering disabled.
+ *
+ * @param ctx context object
+ * @return 0 on success, -1 in case of an error
+ */
+static int start(struct tcp_server_ctx *ctx) {
+  int rv;
+
+  assert(ctx->sfd == 0 && "Server already started.");
+
+  // create socket
+  int sfd = socket(AF_INET, SOCK_STREAM, 0);
+  if (sfd == -1) {
+    fprintf(stderr, "%s: Unable to create socket: %s (%d)\n", ctx->display_name,
+            strerror(errno), errno);
+    return -1;
+  }
+
+  rv = fcntl(sfd, F_SETFL, O_NONBLOCK);
+  if (rv != 0) {
+    fprintf(stderr, "%s: Unable to make socket non-blocking: %s (%d)\n",
+            ctx->display_name, strerror(errno), errno);
+    return -1;
+  }
+
+  // reuse existing socket (if existing)
+  int reuse_socket = 1;
+  rv = setsockopt(sfd, SOL_SOCKET, SO_REUSEADDR, &reuse_socket, sizeof(int));
+  if (rv != 0) {
+    fprintf(stderr, "%s: Unable to set socket options: %s (%d)\n",
+            ctx->display_name, strerror(errno), errno);
+    return -1;
+  }
+
+  // stop tcp socket from buffering (buffering prevents timely responses to
+  // OpenOCD which severly limits debugging performance)
+  int tcp_nodelay = 1;
+  rv = setsockopt(sfd, IPPROTO_TCP, TCP_NODELAY, &tcp_nodelay, sizeof(int));
+  if (rv != 0) {
+    fprintf(stderr, "%s: Unable to set socket nodelay: %s (%d)\n",
+            ctx->display_name, strerror(errno), errno);
+    return -1;
+  }
+
+  // bind server
+  struct sockaddr_in addr;
+  memset(&addr, 0, sizeof(addr));
+  addr.sin_family = AF_INET;
+  addr.sin_addr.s_addr = htonl(INADDR_ANY);
+  addr.sin_port = htons(ctx->listen_port);
+
+  rv = bind(sfd, (struct sockaddr *)&addr, sizeof(addr));
+  if (rv != 0) {
+    fprintf(stderr, "%s: Failed to bind socket: %s (%d)\n", ctx->display_name,
+            strerror(errno), errno);
+    return -1;
+  }
+
+  // listen for incoming connections
+  rv = listen(sfd, 1);
+  if (rv != 0) {
+    fprintf(stderr, "%s: Failed to listen on socket: %s (%d)\n",
+            ctx->display_name, strerror(errno), errno);
+    return -1;
+  }
+
+  ctx->sfd = sfd;
+  assert(ctx->sfd > 0);
+
+  return 0;
+}
+
+/**
+ * Accept an incoming connection from a client (nonblocking)
+ *
+ * The resulting client fd is made non-blocking.
+ *
+ * @param ctx context object
+ * @return 0 on success, any other value indicates an error
+ */
+static int client_tryaccept(struct tcp_server_ctx *ctx) {
+  int rv;
+
+  assert(ctx->sfd > 0);
+  assert(ctx->cfd == 0);
+
+  int cfd = accept(ctx->sfd, NULL, NULL);
+
+  if (cfd == -1 && errno == EAGAIN) {
+    return -EAGAIN;
+  }
+
+  if (cfd == -1) {
+    fprintf(stderr, "%s: Unable to accept incoming connection: %s (%d)\n",
+            ctx->display_name, strerror(errno), errno);
+    return -1;
+  }
+
+  rv = fcntl(cfd, F_SETFL, O_NONBLOCK);
+  if (rv != 0) {
+    fprintf(stderr, "%s: Unable to make client socket non-blocking: %s (%d)\n",
+            ctx->display_name, strerror(errno), errno);
+    return -1;
+  }
+
+  ctx->cfd = cfd;
+  assert(ctx->cfd > 0);
+
+  printf("%s: Accepted client connection\n", ctx->display_name);
+
+  return 0;
+}
+
+/**
+ * Stop the TCP server
+ *
+ * @param ctx context object
+ */
+static void stop(struct tcp_server_ctx *ctx) {
+  assert(ctx);
+  if (!ctx->sfd) {
+    return;
+  }
+  close(ctx->sfd);
+  ctx->sfd = 0;
+}
+
+/**
+ * Receive a byte from a connected client
+ *
+ * @param ctx context object
+ * @param cmd byte received
+ * @return true if a byte was read
+ */
+static bool get_byte(struct tcp_server_ctx *ctx, char *cmd) {
+  assert(ctx);
+
+  ssize_t num_read = read(ctx->cfd, cmd, 1);
+
+  if (num_read == 0) {
+    return false;
+  }
+  if (num_read == -1) {
+    if (errno == EAGAIN || errno == EWOULDBLOCK) {
+      return false;
+    } else if (errno == EBADF) {
+      // Possibly client went away? Accept a new connection.
+      fprintf(stderr, "%s: Client disappeared.\n", ctx->display_name);
+      tcp_server_client_close(ctx);
+      return false;
+    } else {
+      fprintf(stderr, "%s: Error while reading from client: %s (%d)\n",
+              ctx->display_name, strerror(errno), errno);
+      assert(0 && "Error reading from client");
+    }
+  }
+  assert(num_read == 1);
+  return true;
+}
+
+/**
+ * Send a byte to a connected client
+ *
+ * @param ctx context object
+ * @param cmd byte to send
+ */
+static void put_byte(struct tcp_server_ctx *ctx, char cmd) {
+  while (1) {
+    ssize_t num_written = send(ctx->cfd, &cmd, sizeof(cmd), MSG_NOSIGNAL);
+    if (num_written == -1) {
+      if (errno == EAGAIN || errno == EWOULDBLOCK) {
+        continue;
+      } else if (errno == EPIPE) {
+        printf("%s: Remote disconnected.\n", ctx->display_name);
+        tcp_server_client_close(ctx);
+        break;
+      } else {
+        fprintf(stderr, "%s: Error while writing to client: %s (%d)\n",
+                ctx->display_name, strerror(errno), errno);
+        assert(0 && "Error writing to client.");
+      }
+    }
+    if (num_written >= 1) {
+      break;
+    }
+  }
+}
+
+/**
+ * Cleanup server context
+ *
+ * @param ctx context object
+ */
+static void ctx_free(struct tcp_server_ctx *ctx) {
+  // Free the buffers
+  tcp_buffer_free(&ctx->buf_in);
+  tcp_buffer_free(&ctx->buf_out);
+  // Free the display name
+  free(ctx->display_name);
+  // Free the ctx
+  free(ctx);
+  ctx = NULL;
+}
+
+/**
+ * Thread function to create a new server instance
+ *
+ * @param ctx_void context object
+ * @return Always returns NULL
+ */
+static void *server_create(void *ctx_void) {
+  // Cast to a server struct
+  struct tcp_server_ctx *ctx = (struct tcp_server_ctx *)ctx_void;
+  struct timeval timeout;
+
+  // Start the server
+  int rv = start(ctx);
+  if (rv != 0) {
+    fprintf(stderr, "%s: Unable to create TCP server on port %d\n",
+            ctx->display_name, ctx->listen_port);
+    goto err_cleanup_return;
+  }
+
+  // Initialise timeout
+  timeout.tv_sec = 0;
+
+  // Initialise fd_set
+
+  // Start waiting for connection / data
+  char xfer_data;
+  while (ctx->socket_run) {
+    // Initialise structure of fds
+    fd_set read_fds;
+    FD_ZERO(&read_fds);
+    if (ctx->sfd) {
+      FD_SET(ctx->sfd, &read_fds);
+    }
+    if (ctx->cfd) {
+      FD_SET(ctx->cfd, &read_fds);
+    }
+    // max fd num
+    int mfd = (ctx->cfd > ctx->sfd) ? ctx->cfd : ctx->sfd;
+
+    // Set timeout - 50us gives good performance
+    timeout.tv_usec = 50;
+
+    // Wait for socket activity or timeout
+    rv = select(mfd + 1, &read_fds, NULL, NULL, &timeout);
+
+    if (rv < 0) {
+      printf("%s: Socket read failed, port: %d\n", ctx->display_name,
+             ctx->listen_port);
+      tcp_server_client_close(ctx);
+    }
+
+    // New connection
+    if (FD_ISSET(ctx->sfd, &read_fds)) {
+      client_tryaccept(ctx);
+    }
+
+    // New client data
+    if (FD_ISSET(ctx->cfd, &read_fds)) {
+      while (get_byte(ctx, &xfer_data)) {
+        tcp_buffer_put_byte(ctx->buf_in, xfer_data);
+      }
+    }
+
+    if (ctx->cfd != 0) {
+      while (tcp_buffer_get_byte(ctx->buf_out, &xfer_data)) {
+        put_byte(ctx, xfer_data);
+      }
+    }
+  }
+
+err_cleanup_return:
+
+  // Simulation done - clean up
+  tcp_server_client_close(ctx);
+  stop(ctx);
+
+  return NULL;
+}
+
+// Abstract interface functions
+struct tcp_server_ctx *tcp_server_create(const char *display_name,
+                                         int listen_port) {
+  struct tcp_server_ctx *ctx =
+      (struct tcp_server_ctx *)calloc(1, sizeof(struct tcp_server_ctx));
+  assert(ctx);
+
+  // Create the buffers
+  struct tcp_buf *buf_in = tcp_buffer_new();
+  struct tcp_buf *buf_out = tcp_buffer_new();
+  assert(buf_in);
+  assert(buf_out);
+
+  // Populate the struct with buffer pointers
+  ctx->buf_in = buf_in;
+  ctx->buf_out = buf_out;
+
+  // Set up socket details
+  ctx->socket_run = true;
+  ctx->listen_port = listen_port;
+  ctx->display_name = strdup(display_name);
+  assert(ctx->display_name);
+
+  if (pthread_create(&ctx->sock_thread, NULL, server_create, (void *)ctx) !=
+      0) {
+    fprintf(stderr, "%s: Unable to create TCP socket thread\n",
+            ctx->display_name);
+    ctx_free(ctx);
+    free(ctx);
+    return NULL;
+  }
+  return ctx;
+}
+
+bool tcp_server_read(struct tcp_server_ctx *ctx, char *dat) {
+  return tcp_buffer_get_byte(ctx->buf_in, dat);
+}
+
+void tcp_server_write(struct tcp_server_ctx *ctx, char dat) {
+  tcp_buffer_put_byte(ctx->buf_out, dat);
+}
+
+void tcp_server_close(struct tcp_server_ctx *ctx) {
+  // Shut down the socket thread
+  ctx->socket_run = false;
+  pthread_join(ctx->sock_thread, NULL);
+  ctx_free(ctx);
+}
+
+void tcp_server_client_close(struct tcp_server_ctx *ctx) {
+  assert(ctx);
+
+  if (!ctx->cfd) {
+    return;
+  }
+
+  close(ctx->cfd);
+  ctx->cfd = 0;
+}
diff --git a/src/integration/test_suites/libs/tcp_server/tcp_server.h b/src/integration/test_suites/libs/tcp_server/tcp_server.h
new file mode 100644
index 000000000..5226322f9
--- /dev/null
+++ b/src/integration/test_suites/libs/tcp_server/tcp_server.h
@@ -0,0 +1,71 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#ifndef OPENTITAN_HW_DV_DPI_COMMON_TCP_SERVER_TCP_SERVER_H_
+#define OPENTITAN_HW_DV_DPI_COMMON_TCP_SERVER_TCP_SERVER_H_
+
+/**
+ * Functions to create and interact with a threaded TCP server
+ *
+ * This is intended to be used by simulation add-on DPI modules to provide
+ * basic TCP socket communication between a host and simulated peripherals.
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+
+struct tcp_server_ctx;
+
+/**
+ * Non-blocking read of a byte from a connected client
+ *
+ * @param ctx tcp server context object
+ * @param dat byte received
+ * @return true if a byte was read
+ */
+bool tcp_server_read(struct tcp_server_ctx *ctx, char *dat);
+
+/**
+ * Write a byte to a connected client
+ *
+ * The write is internally buffered and so does not block if the client is not
+ * ready to accept data, but does block if the buffer is full.
+ *
+ * @param ctx tcp server context object
+ * @param dat byte to send
+ */
+void tcp_server_write(struct tcp_server_ctx *ctx, char dat);
+
+/**
+ * Create a new TCP server instance
+ *
+ * @param display_name C string description of server
+ * @param listen_port On which port the server should listen
+ * @return A pointer to the created context struct
+ */
+struct tcp_server_ctx *tcp_server_create(const char *display_name,
+                                         int listen_port);
+
+/**
+ * Shut down the server and free all reserved memory
+ *
+ * @param ctx tcp server context object
+ */
+void tcp_server_close(struct tcp_server_ctx *ctx);
+
+/**
+ * Instruct the server to disconnect a client
+ *
+ * @param ctx tcp server context object
+ */
+void tcp_server_client_close(struct tcp_server_ctx *ctx);
+
+#ifdef __cplusplus
+}  // extern "C"
+#endif
+#endif  // OPENTITAN_HW_DV_DPI_COMMON_TCP_SERVER_TCP_SERVER_H_
diff --git a/src/integration/test_suites/memCpy_ROM_to_dccm/caliptra_isr.h b/src/integration/test_suites/memCpy_ROM_to_dccm/caliptra_isr.h
new file mode 100644
index 000000000..8f5779e04
--- /dev/null
+++ b/src/integration/test_suites/memCpy_ROM_to_dccm/caliptra_isr.h
@@ -0,0 +1,247 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// ---------------------------------------------------------------------
+// File: caliptra_isr.h
+// Description:
+//     Provides function declarations for use by external test files, so
+//     that the ISR functionality may behave like a library.
+//     TODO:
+//     This header file includes inline function definitions for event and
+//     test specific interrupt service behavior, so it should be copied and
+//     modified for each test.
+// ---------------------------------------------------------------------
+
+#ifndef CALIPTRA_ISR_H
+    #define CALIPTRA_ISR_H
+
+#define EN_ISR_PRINTS 1
+
+#include "caliptra_defines.h"
+#include <stdint.h>
+#include "printf.h"
+
+/* --------------- symbols/typedefs --------------- */
+typedef struct {
+    uint32_t doe_error;
+    uint32_t doe_notif;
+    uint32_t ecc_error;
+    uint32_t ecc_notif;
+    uint32_t hmac_error;
+    uint32_t hmac_notif;
+    uint32_t kv_error;
+    uint32_t kv_notif;
+    uint32_t sha512_error;
+    uint32_t sha512_notif;
+    uint32_t sha256_error;
+    uint32_t sha256_notif;
+    uint32_t qspi_error;
+    uint32_t qspi_notif;
+    uint32_t uart_error;
+    uint32_t uart_notif;
+    uint32_t i3c_error;
+    uint32_t i3c_notif;
+    uint32_t soc_ifc_error;
+    uint32_t soc_ifc_notif;
+    uint32_t sha512_acc_error;
+    uint32_t sha512_acc_notif;
+} caliptra_intr_received_s;
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
+
+//////////////////////////////////////////////////////////////////////////////
+// Function Declarations
+//
+
+// Performs all the CSR setup to configure and enable vectored external interrupts
+void init_interrupts(void);
+
+// These inline functions are used to insert event-specific functionality into the
+// otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr"
+inline void service_doe_error_intr() {return;}
+inline void service_doe_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.doe_notif |= DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad doe_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_ecc_error_intr() {return;}
+inline void service_ecc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.ecc_notif |= ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad ecc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_hmac_error_intr() {return;}
+inline void service_hmac_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.hmac_notif |= HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad hmac_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_kv_error_intr() {return;}
+inline void service_kv_notif_intr() {return;}
+inline void service_sha512_error_intr() {return;}
+inline void service_sha512_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_notif |= SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha256_error_intr() {return;}
+inline void service_sha256_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha256_notif |= SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha256_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_qspi_error_intr() {return;}
+inline void service_qspi_notif_intr() {return;}
+inline void service_uart_error_intr() {return;}
+inline void service_uart_notif_intr() {return;}
+inline void service_i3c_error_intr() {return;}
+inline void service_i3c_notif_intr() {return;}
+
+inline void service_soc_ifc_error_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_error_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_soc_ifc_notif_intr () {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha512_acc_error_intr() {return;}
+inline void service_sha512_acc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_acc_notif |= SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_acc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+
+#endif //CALIPTRA_ISR_H
diff --git a/src/integration/test_suites/memCpy_ROM_to_dccm/memCpy_ROM_to_dccm.s b/src/integration/test_suites/memCpy_ROM_to_dccm/memCpy_ROM_to_dccm.s
index ed6178674..600a467d6 100644
--- a/src/integration/test_suites/memCpy_ROM_to_dccm/memCpy_ROM_to_dccm.s
+++ b/src/integration/test_suites/memCpy_ROM_to_dccm/memCpy_ROM_to_dccm.s
@@ -39,6 +39,9 @@ _start:
     li x1, 0xaaaaaaaa
     csrw 0x7c0, x1
 
+    // Call interrupt init
+    call init_interrupts
+
     // Load string from hw_data
     // and write to DCCM
 
@@ -67,6 +70,11 @@ _finish:
 stdout: .word STDOUT
 .global verbosity_g
 verbosity_g: .word 2
+// FW polls this variable for intr
+.global intr_count
+intr_count: .word 0
+.global cptra_intr_rcv
+cptra_intr_rcv: .word 0
 hw_data:
 .ascii "----------------------------------\n"
 .ascii "Hello World from VeeR EL2  !!\n"
diff --git a/src/integration/test_suites/memCpy_dccm_to_iccm/caliptra_isr.h b/src/integration/test_suites/memCpy_dccm_to_iccm/caliptra_isr.h
new file mode 100644
index 000000000..8f5779e04
--- /dev/null
+++ b/src/integration/test_suites/memCpy_dccm_to_iccm/caliptra_isr.h
@@ -0,0 +1,247 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// ---------------------------------------------------------------------
+// File: caliptra_isr.h
+// Description:
+//     Provides function declarations for use by external test files, so
+//     that the ISR functionality may behave like a library.
+//     TODO:
+//     This header file includes inline function definitions for event and
+//     test specific interrupt service behavior, so it should be copied and
+//     modified for each test.
+// ---------------------------------------------------------------------
+
+#ifndef CALIPTRA_ISR_H
+    #define CALIPTRA_ISR_H
+
+#define EN_ISR_PRINTS 1
+
+#include "caliptra_defines.h"
+#include <stdint.h>
+#include "printf.h"
+
+/* --------------- symbols/typedefs --------------- */
+typedef struct {
+    uint32_t doe_error;
+    uint32_t doe_notif;
+    uint32_t ecc_error;
+    uint32_t ecc_notif;
+    uint32_t hmac_error;
+    uint32_t hmac_notif;
+    uint32_t kv_error;
+    uint32_t kv_notif;
+    uint32_t sha512_error;
+    uint32_t sha512_notif;
+    uint32_t sha256_error;
+    uint32_t sha256_notif;
+    uint32_t qspi_error;
+    uint32_t qspi_notif;
+    uint32_t uart_error;
+    uint32_t uart_notif;
+    uint32_t i3c_error;
+    uint32_t i3c_notif;
+    uint32_t soc_ifc_error;
+    uint32_t soc_ifc_notif;
+    uint32_t sha512_acc_error;
+    uint32_t sha512_acc_notif;
+} caliptra_intr_received_s;
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
+
+//////////////////////////////////////////////////////////////////////////////
+// Function Declarations
+//
+
+// Performs all the CSR setup to configure and enable vectored external interrupts
+void init_interrupts(void);
+
+// These inline functions are used to insert event-specific functionality into the
+// otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr"
+inline void service_doe_error_intr() {return;}
+inline void service_doe_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.doe_notif |= DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad doe_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_ecc_error_intr() {return;}
+inline void service_ecc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.ecc_notif |= ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad ecc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_hmac_error_intr() {return;}
+inline void service_hmac_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.hmac_notif |= HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad hmac_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_kv_error_intr() {return;}
+inline void service_kv_notif_intr() {return;}
+inline void service_sha512_error_intr() {return;}
+inline void service_sha512_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_notif |= SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha256_error_intr() {return;}
+inline void service_sha256_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha256_notif |= SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha256_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_qspi_error_intr() {return;}
+inline void service_qspi_notif_intr() {return;}
+inline void service_uart_error_intr() {return;}
+inline void service_uart_notif_intr() {return;}
+inline void service_i3c_error_intr() {return;}
+inline void service_i3c_notif_intr() {return;}
+
+inline void service_soc_ifc_error_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_error_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_soc_ifc_notif_intr () {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha512_acc_error_intr() {return;}
+inline void service_sha512_acc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_acc_notif |= SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_acc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+
+#endif //CALIPTRA_ISR_H
diff --git a/src/integration/test_suites/memCpy_dccm_to_iccm/memCpy_dccm_to_iccm.s b/src/integration/test_suites/memCpy_dccm_to_iccm/memCpy_dccm_to_iccm.s
index fb168535b..75005058b 100644
--- a/src/integration/test_suites/memCpy_dccm_to_iccm/memCpy_dccm_to_iccm.s
+++ b/src/integration/test_suites/memCpy_dccm_to_iccm/memCpy_dccm_to_iccm.s
@@ -38,6 +38,9 @@ _start:
     li x1, 0xaaaaaaaa
     csrw 0x7c0, x1
 
+    // Call interrupt init
+    call init_interrupts
+
     // Load string from hw_data
     // and write to ICCM address
 
@@ -66,6 +69,11 @@ _finish:
 stdout: .word STDOUT
 .global verbosity_g
 verbosity_g: .word 2
+// FW polls this variable for intr
+.global intr_count
+intr_count: .word 0
+.global cptra_intr_rcv
+cptra_intr_rcv: .word 0
 hw_data:
 .ascii "----------------------------------\n"
 .ascii "Hello World from VeeR EL2  !!\n"
diff --git a/src/integration/test_suites/pv_hash_and_sign/caliptra_isr.h b/src/integration/test_suites/pv_hash_and_sign/caliptra_isr.h
index 23b511c4b..8f5779e04 100644
--- a/src/integration/test_suites/pv_hash_and_sign/caliptra_isr.h
+++ b/src/integration/test_suites/pv_hash_and_sign/caliptra_isr.h
@@ -32,39 +32,216 @@
 #include <stdint.h>
 #include "printf.h"
 
-//extern volatile uint32_t hmac_intr_status;
+/* --------------- symbols/typedefs --------------- */
+typedef struct {
+    uint32_t doe_error;
+    uint32_t doe_notif;
+    uint32_t ecc_error;
+    uint32_t ecc_notif;
+    uint32_t hmac_error;
+    uint32_t hmac_notif;
+    uint32_t kv_error;
+    uint32_t kv_notif;
+    uint32_t sha512_error;
+    uint32_t sha512_notif;
+    uint32_t sha256_error;
+    uint32_t sha256_notif;
+    uint32_t qspi_error;
+    uint32_t qspi_notif;
+    uint32_t uart_error;
+    uint32_t uart_notif;
+    uint32_t i3c_error;
+    uint32_t i3c_notif;
+    uint32_t soc_ifc_error;
+    uint32_t soc_ifc_notif;
+    uint32_t sha512_acc_error;
+    uint32_t sha512_acc_notif;
+} caliptra_intr_received_s;
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
 
 //////////////////////////////////////////////////////////////////////////////
 // Function Declarations
 //
+
 // Performs all the CSR setup to configure and enable vectored external interrupts
 void init_interrupts(void);
 
 // These inline functions are used to insert event-specific functionality into the
-// otherwise generic ISR that gets laid down by the parameterized macro "nonstd_swerv_isr"
-inline void service_doe_error_intr() {printf("ERROR");}
-inline void service_doe_notif_intr() {printf("ERROR");}
-inline void service_ecc_error_intr   () {printf("ERROR");}
-inline void service_ecc_notif_intr   () {printf("ERROR");}
-inline void service_hmac_error_intr  () {printf("ERROR");}
-inline void service_hmac_notif_intr  () {printf("ERROR");}
-
-inline void service_kv_error_intr    () {printf("ERROR");}
-inline void service_kv_notif_intr    () {printf("ERROR");}
-inline void service_sha512_error_intr() {printf("ERROR");}
-inline void service_sha512_notif_intr() {printf("ERROR");}
-inline void service_sha256_error_intr() {printf("ERROR");}
-inline void service_sha256_notif_intr() {printf("ERROR");}
-inline void service_qspi_error_intr  () {printf("ERROR");}
-inline void service_qspi_notif_intr  () {printf("ERROR");}
-inline void service_uart_error_intr  () {printf("ERROR");}
-inline void service_uart_notif_intr  () {printf("ERROR");}
-inline void service_i3c_error_intr   () {printf("ERROR");}
-inline void service_i3c_notif_intr   () {printf("ERROR");}
-inline void service_soc_ifc_error_intr  () {printf("ERROR");}
-inline void service_soc_ifc_notif_intr  () {printf("ERROR");}
-inline void service_sha512_acc_error_intr() {printf("ERROR");}
-inline void service_sha512_acc_notif_intr() {printf("ERROR");}
+// otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr"
+inline void service_doe_error_intr() {return;}
+inline void service_doe_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.doe_notif |= DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad doe_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_ecc_error_intr() {return;}
+inline void service_ecc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.ecc_notif |= ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad ecc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_hmac_error_intr() {return;}
+inline void service_hmac_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.hmac_notif |= HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad hmac_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_kv_error_intr() {return;}
+inline void service_kv_notif_intr() {return;}
+inline void service_sha512_error_intr() {return;}
+inline void service_sha512_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_notif |= SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha256_error_intr() {return;}
+inline void service_sha256_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha256_notif |= SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha256_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_qspi_error_intr() {return;}
+inline void service_qspi_notif_intr() {return;}
+inline void service_uart_error_intr() {return;}
+inline void service_uart_notif_intr() {return;}
+inline void service_i3c_error_intr() {return;}
+inline void service_i3c_notif_intr() {return;}
+
+inline void service_soc_ifc_error_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_error_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_soc_ifc_notif_intr () {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha512_acc_error_intr() {return;}
+inline void service_sha512_acc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_acc_notif |= SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_acc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
 
 
 #endif //CALIPTRA_ISR_H
diff --git a/src/integration/test_suites/pv_hash_and_sign/pv_hash_and_sign.c b/src/integration/test_suites/pv_hash_and_sign/pv_hash_and_sign.c
index a2239924e..f23b86f12 100644
--- a/src/integration/test_suites/pv_hash_and_sign/pv_hash_and_sign.c
+++ b/src/integration/test_suites/pv_hash_and_sign/pv_hash_and_sign.c
@@ -31,6 +31,31 @@ volatile uint32_t intr_count = 0;
     enum printf_verbosity verbosity_g = MEDIUM;
 #endif
 
+volatile caliptra_intr_received_s cptra_intr_rcv = {
+    .doe_error        = 0,
+    .doe_notif        = 0,
+    .ecc_error        = 0,
+    .ecc_notif        = 0,
+    .hmac_error       = 0,
+    .hmac_notif       = 0,
+    .kv_error         = 0,
+    .kv_notif         = 0,
+    .sha512_error     = 0,
+    .sha512_notif     = 0,
+    .sha256_error     = 0,
+    .sha256_notif     = 0,
+    .qspi_error       = 0,
+    .qspi_notif       = 0,
+    .uart_error       = 0,
+    .uart_notif       = 0,
+    .i3c_error        = 0,
+    .i3c_notif        = 0,
+    .soc_ifc_error    = 0,
+    .soc_ifc_notif    = 0,
+    .sha512_acc_error = 0,
+    .sha512_acc_notif = 0,
+};
+
 void main() {
     VPRINTF(LOW,"---------------------------\n");
     VPRINTF(LOW," KV PCR Hash Extend Test !!\n");
@@ -75,44 +100,53 @@ void main() {
                        0xa0b43fbf,
                        0x49897978};
 
-    uint32_t exp3[] = {0x9bad51d7,
-                       0x287c2244,
-                       0x154b6f2d,
-                       0x77bd52ea,
-                       0x0213d314,
-                       0x6f4cb39f,
-                       0xe27a6d42,
-                       0x8886bf0e,
-                       0xaab4310a,
-                       0x53946e9b,
-                       0x70cbd1e7,
-                       0xfb158bab};
-
-    uint32_t exp_sign_r[] = {0x4783887c, 
-                             0xe3e20caa, 
-                             0x4a10c8ef, 
-                             0x929fdc23, 
-                             0x1c389ab7, 
-                             0x72cf8b35, 
-                             0xfc1647a5, 
-                             0xf1205a1e, 
-                             0x50d92ac9, 
-                             0x1b5a549a, 
-                             0x3944f5aa, 
-                             0x52f32b23};
-
-    uint32_t exp_sign_s[] = {0x44bd1e3b, 
-                             0x6cb57584, 
-                             0x304f77b9, 
-                             0xee4a6599, 
-                             0x38e3b614, 
-                             0x00db744e, 
-                             0x6227cbb3, 
-                             0x6bbfbbbd, 
-                             0xbe1d0815, 
-                             0x71fba315, 
-                             0xeb049b1e, 
-                             0x437af8aa};
+    uint32_t exp3[] = {0x2ab50775,
+                       0xdab80928,
+                       0xb8de848c,
+                       0xabbdfa56,
+                       0x897ed7b1,
+                       0x45be930e,
+                       0x1e340ce0,
+                       0x8c5bfc73,
+                       0x1d997144,
+                       0x0c43f5a5,
+                       0xaa48ac99,
+                       0x8dbe6bb9};
+
+    uint32_t exp_sign_r[] = {0x871e6ea4, 
+                             0xddc5432c, 
+                             0xddaa60fd, 
+                             0x7f055472, 
+                             0xd3c4dd41, 
+                             0xa5bfb267, 
+                             0x09e88c31, 
+                             0x1a970935, 
+                             0x99a7c8f5, 
+                             0x5b3974c1, 
+                             0x9e4f5a7b, 
+                             0xfc1dd2ac};
+
+    uint32_t exp_sign_s[] = {0x3e5552de, 
+                             0x6403350e, 
+                             0xe70ad74e, 
+                             0x4b854d2d, 
+                             0xc4126bbf, 
+                             0x9c153a5d, 
+                             0x7a07bd4b, 
+                             0x85d06e45, 
+                             0xf850920e, 
+                             0x898fb7d3, 
+                             0x4f80796d, 
+                             0xae29365c};
+
+    uint32_t nonce[] = {0x01234567,
+                        0x11111111,
+                        0x22222222,
+                        0x33333333,
+                        0x44444444,
+                        0x55555555,
+                        0x66666666,
+                        0x77777777};
 
     volatile uint32_t* reg_ptr;
     uint8_t offset;
@@ -259,7 +293,11 @@ void main() {
     }
 
     sha_poll_gen_hash_ready();
-    lsu_write_32(CLP_SHA512_REG_SHA512_GEN_PCR_HASH_NONCE,0x12345678);
+    reg_ptr = (uint32_t*) CLP_SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_0;
+    offset = 0;
+    while (reg_ptr <= (uint32_t*) CLP_SHA512_REG_SHA512_GEN_PCR_HASH_NONCE_7) {
+        *reg_ptr++ = nonce[offset++];
+    }
     sha_gen_hash_start();
     sha_poll_gen_hash_valid();
 
@@ -275,6 +313,11 @@ void main() {
         offset++;
     }
 
+    //inject seed to kv key reg (in RTL)
+    printf("ECC: Inject PRIVKEY into KV slot 7\n");
+    printf("ECC: Inject MSG into msg_reg\n");
+    printf("%c", 0x90);
+
     VPRINTF(MEDIUM,"ECC: Running PCR Sign Function\n");
     //run ECC signing on PCR
     reg = ((1 << ECC_REG_ECC_CTRL_PCR_SIGN_LOW) & ECC_REG_ECC_CTRL_PCR_SIGN_MASK) |
@@ -284,7 +327,7 @@ void main() {
 
     VPRINTF(MEDIUM,"ECC: Polling for PCR Sign to be complete\n");
     // wait for ECC SIGNING process to be done
-    while((lsu_read_32(CLP_ECC_REG_ECC_STATUS) & ECC_REG_ECC_STATUS_VALID_MASK) == 0);
+    while((lsu_read_32(CLP_ECC_REG_ECC_STATUS) & ECC_REG_ECC_STATUS_READY_MASK) == 0);
 
     //check expected output from sign r
     reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_SIGN_R_0;
diff --git a/src/integration/test_suites/randomized_pcr_signing/caliptra_isr.h b/src/integration/test_suites/randomized_pcr_signing/caliptra_isr.h
index 6ffd71c0a..8f5779e04 100644
--- a/src/integration/test_suites/randomized_pcr_signing/caliptra_isr.h
+++ b/src/integration/test_suites/randomized_pcr_signing/caliptra_isr.h
@@ -204,6 +204,22 @@ inline void service_soc_ifc_notif_intr () {
         *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
         cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
     }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
     if (sts == 0) {
         VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
         SEND_STDOUT_CTRL(0x1);
diff --git a/src/integration/test_suites/smoke_test_ahb_mux/caliptra_isr.h b/src/integration/test_suites/smoke_test_ahb_mux/caliptra_isr.h
new file mode 100644
index 000000000..8f5779e04
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_ahb_mux/caliptra_isr.h
@@ -0,0 +1,247 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// ---------------------------------------------------------------------
+// File: caliptra_isr.h
+// Description:
+//     Provides function declarations for use by external test files, so
+//     that the ISR functionality may behave like a library.
+//     TODO:
+//     This header file includes inline function definitions for event and
+//     test specific interrupt service behavior, so it should be copied and
+//     modified for each test.
+// ---------------------------------------------------------------------
+
+#ifndef CALIPTRA_ISR_H
+    #define CALIPTRA_ISR_H
+
+#define EN_ISR_PRINTS 1
+
+#include "caliptra_defines.h"
+#include <stdint.h>
+#include "printf.h"
+
+/* --------------- symbols/typedefs --------------- */
+typedef struct {
+    uint32_t doe_error;
+    uint32_t doe_notif;
+    uint32_t ecc_error;
+    uint32_t ecc_notif;
+    uint32_t hmac_error;
+    uint32_t hmac_notif;
+    uint32_t kv_error;
+    uint32_t kv_notif;
+    uint32_t sha512_error;
+    uint32_t sha512_notif;
+    uint32_t sha256_error;
+    uint32_t sha256_notif;
+    uint32_t qspi_error;
+    uint32_t qspi_notif;
+    uint32_t uart_error;
+    uint32_t uart_notif;
+    uint32_t i3c_error;
+    uint32_t i3c_notif;
+    uint32_t soc_ifc_error;
+    uint32_t soc_ifc_notif;
+    uint32_t sha512_acc_error;
+    uint32_t sha512_acc_notif;
+} caliptra_intr_received_s;
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
+
+//////////////////////////////////////////////////////////////////////////////
+// Function Declarations
+//
+
+// Performs all the CSR setup to configure and enable vectored external interrupts
+void init_interrupts(void);
+
+// These inline functions are used to insert event-specific functionality into the
+// otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr"
+inline void service_doe_error_intr() {return;}
+inline void service_doe_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.doe_notif |= DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad doe_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_ecc_error_intr() {return;}
+inline void service_ecc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.ecc_notif |= ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad ecc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_hmac_error_intr() {return;}
+inline void service_hmac_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.hmac_notif |= HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad hmac_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_kv_error_intr() {return;}
+inline void service_kv_notif_intr() {return;}
+inline void service_sha512_error_intr() {return;}
+inline void service_sha512_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_notif |= SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha256_error_intr() {return;}
+inline void service_sha256_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha256_notif |= SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha256_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_qspi_error_intr() {return;}
+inline void service_qspi_notif_intr() {return;}
+inline void service_uart_error_intr() {return;}
+inline void service_uart_notif_intr() {return;}
+inline void service_i3c_error_intr() {return;}
+inline void service_i3c_notif_intr() {return;}
+
+inline void service_soc_ifc_error_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_error_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_soc_ifc_notif_intr () {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha512_acc_error_intr() {return;}
+inline void service_sha512_acc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_acc_notif |= SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_acc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+
+#endif //CALIPTRA_ISR_H
diff --git a/src/integration/test_suites/smoke_test_ahb_mux/smoke_test_ahb_mux.s b/src/integration/test_suites/smoke_test_ahb_mux/smoke_test_ahb_mux.s
index 41b0ecd44..7a19659ba 100644
--- a/src/integration/test_suites/smoke_test_ahb_mux/smoke_test_ahb_mux.s
+++ b/src/integration/test_suites/smoke_test_ahb_mux/smoke_test_ahb_mux.s
@@ -195,8 +195,11 @@ my_print:
 .section .dccm
 .global stdout
 stdout: .word STDOUT
+// FW polls this variable for intr
 .global intr_count
 intr_count: .word 0
+.global cptra_intr_rcv
+cptra_intr_rcv: .word 0
 .global verbosity_g
 verbosity_g: .word 2
 print_data:
diff --git a/src/integration/test_suites/smoke_test_cg_wdt/caliptra_isr.h b/src/integration/test_suites/smoke_test_cg_wdt/caliptra_isr.h
new file mode 100644
index 000000000..6f27a6427
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_cg_wdt/caliptra_isr.h
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// ---------------------------------------------------------------------
+// File: caliptra_isr.h
+// Description:
+//     Provides function declarations for use by external test files, so
+//     that the ISR functionality may behave like a library.
+//     TODO:
+//     This header file includes inline function definitions for event and
+//     test specific interrupt service behavior, so it should be copied and
+//     modified for each test.
+// ---------------------------------------------------------------------
+
+#ifndef CALIPTRA_ISR_H
+    #define CALIPTRA_ISR_H
+
+#define EN_ISR_PRINTS 1
+
+#include "caliptra_defines.h"
+#include <stdint.h>
+#include "printf.h"
+
+extern volatile uint32_t hmac_intr_status;
+
+/* --------------- symbols/typedefs --------------- */
+typedef struct {
+    uint32_t doe_error;
+    uint32_t doe_notif;
+    uint32_t ecc_error;
+    uint32_t ecc_notif;
+    uint32_t hmac_error;
+    uint32_t hmac_notif;
+    uint32_t kv_error;
+    uint32_t kv_notif;
+    uint32_t sha512_error;
+    uint32_t sha512_notif;
+    uint32_t sha256_error;
+    uint32_t sha256_notif;
+    uint32_t qspi_error;
+    uint32_t qspi_notif;
+    uint32_t uart_error;
+    uint32_t uart_notif;
+    uint32_t i3c_error;
+    uint32_t i3c_notif;
+    uint32_t soc_ifc_error;
+    uint32_t soc_ifc_notif;
+    uint32_t sha512_acc_error;
+    uint32_t sha512_acc_notif;
+} caliptra_intr_received_s;
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
+
+//////////////////////////////////////////////////////////////////////////////
+// Function Declarations
+//
+// Performs all the CSR setup to configure and enable vectored external interrupts
+void init_interrupts(void);
+
+// These inline functions are used to insert event-specific functionality into the
+// otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr"
+inline void service_doe_error_intr() {printf("ERROR");}
+inline void service_doe_notif_intr() {printf("ERROR");}
+inline void service_ecc_error_intr   () {printf("ERROR");}
+inline void service_ecc_notif_intr   () {printf("ERROR");}
+inline void service_hmac_error_intr  () {printf("ERROR");}
+inline void service_hmac_notif_intr  () {
+    uint32_t * reg = (uint32_t *) (CLP_HMAC_REG_BASE_ADDR + HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        printf("bad hmac_notif_intr sts:%x\n", sts);
+    } else {
+        reg = (uint32_t *) (CLP_HMAC_REG_HMAC384_STATUS);
+        hmac_intr_status = *reg;
+    }
+}
+
+inline void service_kv_error_intr    () {printf("ERROR");}
+inline void service_kv_notif_intr    () {printf("ERROR");}
+inline void service_sha512_error_intr() {printf("ERROR");}
+inline void service_sha512_notif_intr() {printf("ERROR");}
+inline void service_sha256_error_intr() {printf("ERROR");}
+inline void service_sha256_notif_intr() {printf("ERROR");}
+inline void service_qspi_error_intr  () {printf("ERROR");}
+inline void service_qspi_notif_intr  () {printf("ERROR");}
+inline void service_uart_error_intr  () {printf("ERROR");}
+inline void service_uart_notif_intr  () {printf("ERROR");}
+inline void service_i3c_error_intr   () {printf("ERROR");}
+inline void service_i3c_notif_intr   () {printf("ERROR");}
+inline void service_soc_ifc_error_intr  () {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    //Write 1 to clear pending interrupt
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK;
+    }
+    //Write 1 to clear pending interrupt
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK;
+    }
+}
+inline void service_soc_ifc_notif_intr  () {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+
+    if(sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+
+    if(sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
+}
+inline void service_sha512_acc_error_intr() {printf("ERROR");}
+inline void service_sha512_acc_notif_intr() {printf("ERROR");}
+
+
+#endif //CALIPTRA_ISR_H
diff --git a/src/integration/test_suites/smoke_test_cg_wdt/smoke_test_cg_wdt.c b/src/integration/test_suites/smoke_test_cg_wdt/smoke_test_cg_wdt.c
new file mode 100644
index 000000000..ecbc2b28d
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_cg_wdt/smoke_test_cg_wdt.c
@@ -0,0 +1,243 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+#include "caliptra_defines.h"
+#include "caliptra_isr.h"
+#include "riscv-csr.h"
+#include <string.h>
+#include <stdint.h>
+#include "printf.h"
+#include "clk_gate.h"
+
+volatile char*    stdout           = (char *)STDOUT;
+volatile uint32_t intr_count       = 0;
+volatile uint32_t hmac_intr_status;
+volatile uint32_t rst_count __attribute__((section(".dccm.persistent"))) = 0;
+
+#ifdef CPT_VERBOSITY
+    enum printf_verbosity verbosity_g = CPT_VERBOSITY;
+#else
+    enum printf_verbosity verbosity_g = LOW;
+#endif
+
+volatile uint32_t * wdt_timer1_en       = (uint32_t *) CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_EN;
+volatile uint32_t * wdt_timer1_ctrl     = (uint32_t *) CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL;
+volatile uint32_t * wdt_timer1_period_0 = (uint32_t *) CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0;
+volatile uint32_t * wdt_timer1_period_1 = (uint32_t *) CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1;
+volatile uint32_t * soc_intr_en         = (uint32_t *) CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R;
+
+volatile uint32_t * wdt_timer2_en       = (uint32_t *) CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_EN;
+volatile uint32_t * wdt_timer2_ctrl     = (uint32_t *) CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL;
+volatile uint32_t * wdt_timer2_period_0 = (uint32_t *) CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0;
+volatile uint32_t * wdt_timer2_period_1 = (uint32_t *) CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1;
+
+volatile uint32_t * hw_error_fatal      = (uint32_t *) CLP_SOC_IFC_REG_CPTRA_HW_ERROR_FATAL;
+
+volatile uint32_t * soc_ifc_error_status = (uint32_t *) CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R;
+volatile uint32_t soc_error_status_int;
+
+volatile uint32_t * clear_secrets = (uint32_t *) CLP_KV_REG_CLEAR_SECRETS;
+
+volatile caliptra_intr_received_s cptra_intr_rcv = {
+    .doe_error        = 0,
+    .doe_notif        = 0,
+    .ecc_error        = 0,
+    .ecc_notif        = 0,
+    .hmac_error       = 0,
+    .hmac_notif       = 0,
+    .kv_error         = 0,
+    .kv_notif         = 0,
+    .sha512_error     = 0,
+    .sha512_notif     = 0,
+    .sha256_error     = 0,
+    .sha256_notif     = 0,
+    .qspi_error       = 0,
+    .qspi_notif       = 0,
+    .uart_error       = 0,
+    .uart_notif       = 0,
+    .i3c_error        = 0,
+    .i3c_notif        = 0,
+    .soc_ifc_error    = 0,
+    .soc_ifc_notif    = 0,
+    .sha512_acc_error = 0,
+    .sha512_acc_notif = 0,
+};
+
+void main() {
+    
+    volatile uint32_t * soc_ifc_flow_status = (uint32_t *) CLP_SOC_IFC_REG_CPTRA_FLOW_STATUS;
+    volatile uint32_t * soc_ifc_clk_gating_en = (uint32_t *) CLP_SOC_IFC_REG_CPTRA_CLK_GATING_EN;
+    uint32_t mitb0 = 0x00000500;
+    uint32_t mie_timer0_ext_int_en = 0x20000800;
+    //uint32_t mie_machinetimer_en = 0x00000080;
+    //uint32_t mie_external_int_en = 0x00000800;
+
+    printf("----------------------------------\n");
+    printf(" CLK GATING + WDT smoke test !!\n"   );
+    printf("----------------------------------\n");
+
+    // Call interrupt init
+    init_interrupts();
+
+    //----------------------------------------------------
+    //Clks shut off, core asleep, WDT running
+    //1. soc_ifc_error_intr triggered. Core wakes up after internal timer0 expires and services intr
+    //2. Fatal error is injected - check that clks are enabled again
+    //3. Core asleep, scan mode enabled - check that KV regs are flushed
+    //----------------------------------------------------
+    
+    //Enable clk gating
+    VPRINTF(LOW, "Enabling clk gating\n====================\n");
+    SEND_STDOUT_CTRL(0xf2); 
+
+    if (rst_count == 0) {
+
+        //Enable SOC notif interrupt
+        *soc_intr_en = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_WDT_TIMER1_TIMEOUT_EN_MASK | SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_WDT_TIMER2_TIMEOUT_EN_MASK;
+
+        //Enable WDT timer1
+        *wdt_timer1_en = SOC_IFC_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_MASK;
+        *wdt_timer1_period_0 = 0x00000100;
+        *wdt_timer1_period_1 = 0x00000000;
+        // *wdt_timer2_period_0 = 0x0000FFFF;
+        // *wdt_timer2_period_1 = 0x00000000;
+
+        //============= Case 1 ================
+        VPRINTF(LOW, "WDT t1 intr\n");
+        set_mit0_and_halt_core(mitb0, mie_timer0_ext_int_en);
+
+        //Core wakes up and services timer1 intr
+        VPRINTF(LOW, "Core is awake\n====================\n");
+
+        //while ((*soc_ifc_error_status & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK) == 1);
+        soc_error_status_int = *soc_ifc_error_status;
+        while (soc_error_status_int == SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK) {
+            soc_error_status_int = *soc_ifc_error_status;
+        }
+
+        //============= Case 2 ================
+        //Inject fatal error (after some delay)
+        VPRINTF(LOW, "Cptra_f_err injection\n====================\n");
+        SEND_STDOUT_CTRL(0xeb);
+
+        set_mit0_and_halt_core(mitb0, mie_timer0_ext_int_en);
+
+        //Check that clks wake up and core wakes up later due to internal timer0
+
+        //============= Case 3 ================
+        //Enable scan mode (after some delay)
+        VPRINTF(LOW, "Scan mode enabled\n====================\n");
+        SEND_STDOUT_CTRL(0xef);
+
+        set_mit0_and_halt_core(mitb0, mie_timer0_ext_int_en);
+        
+        // //KV regs should be flushed
+
+        //Disable scan mode
+        VPRINTF(LOW, "Scan mode disabled\n====================\n");
+        SEND_STDOUT_CTRL(0xf0);
+
+        //============= Case 4 ================
+        //Set debug mode value to 1
+        *clear_secrets = 0x00000002;
+
+        //Enable ss tran after some delay
+        VPRINTF(LOW, "Debug mode unlocked\n====================\n");
+        SEND_STDOUT_CTRL(0xfa);
+
+        for (int i = 0; i < 1000; i++); //sleep
+
+        //Issue warm reset to capture debug mode
+        rst_count++;
+        SEND_STDOUT_CTRL(0xf6);
+    }
+    else if (rst_count == 1) {
+
+        rst_count++;
+        SEND_STDOUT_CTRL(0xf6);
+    }
+    else if (rst_count == 2) {
+
+        set_mit0_and_halt_core(mitb0, mie_timer0_ext_int_en);
+
+        //Disable ss tran
+        VPRINTF(LOW, "Debug mode locked\n====================\n");
+        SEND_STDOUT_CTRL(0xf9); 
+
+        //============= Case 5 ================  
+        //cg enabled, issue warm reset
+        VPRINTF(LOW, "Issue warm reset\n====================\n");
+        rst_count++;
+        SEND_STDOUT_CTRL(0xf6);
+    }
+    else if(rst_count == 3) {
+        //Enable internal timer0
+        __asm__ volatile ("csrwi    %0, %1" \
+                        : /* output: none */        \
+                        : "i" (0x7d2), "i" (0x00)  /* input : immediate  */ \
+                        : /* clobbers: none */);
+
+        //Set internal timer0 upper bound
+        __asm__ volatile ("csrw    %0, %1" \
+                        : /* output: none */        \
+                        : "i" (0x7d3), "r" (mitb0)   /* input : immediate  */ \
+                        : /* clobbers: none */);
+
+        //Set internal timer0 control (halt_en = 1, enable = 1)
+        __asm__ volatile ("csrwi    %0, %1" \
+                        : /* output: none */        \
+                        : "i" (0x7d4), "i" (0x03)  /* input : immediate  */ \
+                        : /* clobbers: none */);
+            
+        //Set machine intr enable reg (mie) - enable internal timer0 intr
+        __asm__ volatile ("csrw    %0, %1" \
+                        : /* output: none */        \
+                        : "i" (0x304), "r" (mie_timer0_ext_int_en)  /* input : immediate  */ \
+                        : /* clobbers: none */);
+
+        //Set mstatus reg - enable mie
+        __asm__ volatile ("csrwi    %0, %1" \
+                        : /* output: none */        \
+                        : "i" (0x300), "i" (0x08)  /* input : immediate  */ \
+                        : /* clobbers: none */);
+
+        VPRINTF(LOW, "Issue random warm reset while core is asleep\n====================\n");
+        rst_count++;
+        SEND_STDOUT_CTRL(0xee);
+
+        //Halt the core
+        __asm__ volatile ("csrwi    %0, %1" \
+                    : /* output: none */        \
+                    : "i" (0x7c6), "i" (0x03)  /* input : immediate  */ \
+                    : /* clobbers: none */);
+
+    
+
+    }
+    else {
+        //WDT independent mode:
+        //Enable WDT timer1
+        *wdt_timer1_en = SOC_IFC_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_MASK;
+        *wdt_timer1_period_0 = 0x00000100;
+        *wdt_timer1_period_1 = 0x00000000;
+        //Enable WDT timer2
+        *wdt_timer2_en = SOC_IFC_REG_CPTRA_WDT_TIMER2_EN_TIMER2_EN_MASK;
+        *wdt_timer2_period_0 = 0x00000100;
+        *wdt_timer2_period_1 = 0x00000000;
+
+        //============= Case 6 ================
+        VPRINTF(LOW, "WDT independent mode and core is halted\n====================\n");
+        set_mit0_and_halt_core(mitb0, mie_timer0_ext_int_en);
+    }
+}
\ No newline at end of file
diff --git a/src/integration/test_suites/smoke_test_cg_wdt/smoke_test_cg_wdt.yml b/src/integration/test_suites/smoke_test_cg_wdt/smoke_test_cg_wdt.yml
new file mode 100644
index 000000000..fcdaa7754
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_cg_wdt/smoke_test_cg_wdt.yml
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+---
+seed: 1
+testname: smoke_test_cg_wdt
\ No newline at end of file
diff --git a/src/integration/test_suites/smoke_test_clk_gating/caliptra_isr.h b/src/integration/test_suites/smoke_test_clk_gating/caliptra_isr.h
new file mode 100644
index 000000000..2eb00407e
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_clk_gating/caliptra_isr.h
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// ---------------------------------------------------------------------
+// File: caliptra_isr.h
+// Description:
+//     Provides function declarations for use by external test files, so
+//     that the ISR functionality may behave like a library.
+//     TODO:
+//     This header file includes inline function definitions for event and
+//     test specific interrupt service behavior, so it should be copied and
+//     modified for each test.
+// ---------------------------------------------------------------------
+
+#ifndef CALIPTRA_ISR_H
+    #define CALIPTRA_ISR_H
+
+#define EN_ISR_PRINTS 1
+
+#include "caliptra_defines.h"
+#include <stdint.h>
+#include "printf.h"
+
+extern volatile uint32_t hmac_intr_status;
+
+/* --------------- symbols/typedefs --------------- */
+typedef struct {
+    uint32_t doe_error;
+    uint32_t doe_notif;
+    uint32_t ecc_error;
+    uint32_t ecc_notif;
+    uint32_t hmac_error;
+    uint32_t hmac_notif;
+    uint32_t kv_error;
+    uint32_t kv_notif;
+    uint32_t sha512_error;
+    uint32_t sha512_notif;
+    uint32_t sha256_error;
+    uint32_t sha256_notif;
+    uint32_t qspi_error;
+    uint32_t qspi_notif;
+    uint32_t uart_error;
+    uint32_t uart_notif;
+    uint32_t i3c_error;
+    uint32_t i3c_notif;
+    uint32_t soc_ifc_error;
+    uint32_t soc_ifc_notif;
+    uint32_t sha512_acc_error;
+    uint32_t sha512_acc_notif;
+} caliptra_intr_received_s;
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
+
+//////////////////////////////////////////////////////////////////////////////
+// Function Declarations
+//
+// Performs all the CSR setup to configure and enable vectored external interrupts
+void init_interrupts(void);
+
+// These inline functions are used to insert event-specific functionality into the
+// otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr"
+inline void service_doe_error_intr() {printf("ERROR");}
+inline void service_doe_notif_intr() {printf("ERROR");}
+inline void service_ecc_error_intr   () {printf("ERROR");}
+inline void service_ecc_notif_intr   () {printf("ERROR");}
+inline void service_hmac_error_intr  () {printf("ERROR");}
+inline void service_hmac_notif_intr  () {
+    uint32_t * reg = (uint32_t *) (CLP_HMAC_REG_BASE_ADDR + HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        printf("bad hmac_notif_intr sts:%x\n", sts);
+    } else {
+        reg = (uint32_t *) (CLP_HMAC_REG_HMAC384_STATUS);
+        hmac_intr_status = *reg;
+    }
+}
+
+inline void service_kv_error_intr    () {printf("ERROR");}
+inline void service_kv_notif_intr    () {printf("ERROR");}
+inline void service_sha512_error_intr() {printf("ERROR");}
+inline void service_sha512_notif_intr() {printf("ERROR");}
+inline void service_sha256_error_intr() {printf("ERROR");}
+inline void service_sha256_notif_intr() {printf("ERROR");}
+inline void service_qspi_error_intr  () {printf("ERROR");}
+inline void service_qspi_notif_intr  () {printf("ERROR");}
+inline void service_uart_error_intr  () {printf("ERROR");}
+inline void service_uart_notif_intr  () {printf("ERROR");}
+inline void service_i3c_error_intr   () {printf("ERROR");}
+inline void service_i3c_notif_intr   () {printf("ERROR");}
+inline void service_soc_ifc_error_intr  () {printf("ERROR");}
+inline void service_soc_ifc_notif_intr () {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
+        VPRINTF(HIGH, "cmd_avail\n");
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK) {
+        VPRINTF(HIGH, "mbox_ecc_cor\n");
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        VPRINTF(HIGH, "debug_locked\n");
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        VPRINTF(HIGH, "scan mode\n");
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        VPRINTF(HIGH, "soc_req_lock\n");
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        VPRINTF(HIGH, "gen_in_toggle\n");
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+inline void service_sha512_acc_error_intr() {printf("ERROR");}
+inline void service_sha512_acc_notif_intr() {printf("ERROR");}
+
+
+#endif //CALIPTRA_ISR_H
diff --git a/src/integration/test_suites/smoke_test_clk_gating/smoke_test_clk_gating.c b/src/integration/test_suites/smoke_test_clk_gating/smoke_test_clk_gating.c
new file mode 100644
index 000000000..114abc7d3
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_clk_gating/smoke_test_clk_gating.c
@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+#include "caliptra_defines.h"
+#include "caliptra_isr.h"
+#include "riscv-csr.h"
+#include <string.h>
+#include <stdint.h>
+#include "printf.h"
+#include "clk_gate.h"
+
+volatile char*    stdout           = (char *)STDOUT;
+volatile uint32_t intr_count       = 0;
+volatile uint32_t hmac_intr_status = 0;
+
+#ifdef CPT_VERBOSITY
+    enum printf_verbosity verbosity_g = CPT_VERBOSITY;
+#else
+    enum printf_verbosity verbosity_g = LOW;
+#endif
+
+volatile caliptra_intr_received_s cptra_intr_rcv = {
+    .doe_error        = 0,
+    .doe_notif        = 0,
+    .ecc_error        = 0,
+    .ecc_notif        = 0,
+    .hmac_error       = 0,
+    .hmac_notif       = 0,
+    .kv_error         = 0,
+    .kv_notif         = 0,
+    .sha512_error     = 0,
+    .sha512_notif     = 0,
+    .sha256_error     = 0,
+    .sha256_notif     = 0,
+    .qspi_error       = 0,
+    .qspi_notif       = 0,
+    .uart_error       = 0,
+    .uart_notif       = 0,
+    .i3c_error        = 0,
+    .i3c_notif        = 0,
+    .soc_ifc_error    = 0,
+    .soc_ifc_notif    = 0,
+    .sha512_acc_error = 0,
+    .sha512_acc_notif = 0,
+};
+
+void main() {
+    
+    volatile uint32_t * soc_ifc_flow_status = (uint32_t *) CLP_SOC_IFC_REG_CPTRA_FLOW_STATUS;
+    volatile uint32_t * soc_ifc_clk_gating_en = (uint32_t *) CLP_SOC_IFC_REG_CPTRA_CLK_GATING_EN;
+    uint32_t mitb0 = 0x00000020;
+    uint32_t mitb0_1 = 0x00000500;
+    uint32_t mie_timer0_en = 0x20000000;
+    uint32_t mie_machinetimer_en = 0x00000080;
+    uint32_t mie_external_int_en = 0x00000800;
+    uint32_t mie_timer0_ext_int_en = 0x20000800;
+
+    printf("----------------------------------\n");
+    printf(" CLK GATING smoke test !!\n"         );
+    printf("----------------------------------\n");
+
+    // Call interrupt init
+    init_interrupts();
+
+    //----------------------------------------------------
+    //Wake up using internal timer0
+    //----------------------------------------------------
+        SEND_STDOUT_CTRL(0xf2); 
+        //Set internal timer0 counter to 0
+        printf("Wake up core using internal timer0\n");
+        __asm__ volatile ("csrwi    %0, %1" \
+                      : /* output: none */        \
+                      : "i" (0x7d2), "i" (0x00)  /* input : immediate  */ \
+                      : /* clobbers: none */);
+
+        //Set internal timer0 upper bound
+        __asm__ volatile ("csrw    %0, %1" \
+                      : /* output: none */        \
+                      : "i" (0x7d3), "r" (mitb0)   /* input : immediate  */ \
+                      : /* clobbers: none */);
+
+        //Set internal timer0 control (halt_en = 1, enable = 1)
+        __asm__ volatile ("csrwi    %0, %1" \
+                      : /* output: none */        \
+                      : "i" (0x7d4), "i" (0x03)  /* input : immediate  */ \
+                      : /* clobbers: none */);
+        
+        //Set machine intr enable reg (mie) - enable internal timer0 intr
+        __asm__ volatile ("csrw    %0, %1" \
+                      : /* output: none */        \
+                      : "i" (0x304), "r" (mie_timer0_en)  /* input : immediate  */ \
+                      : /* clobbers: none */);
+
+        //Set mstatus reg - enable mie
+        __asm__ volatile ("csrwi    %0, %1" \
+                      : /* output: none */        \
+                      : "i" (0x300), "i" (0x08)  /* input : immediate  */ \
+                      : /* clobbers: none */);
+
+        //Halt the core
+        __asm__ volatile ("csrwi    %0, %1" \
+                      : /* output: none */        \
+                      : "i" (0x7c6), "i" (0x03)  /* input : immediate  */ \
+                      : /* clobbers: none */);
+
+    //------------------------------------------------------
+    //Set STDOUT to F8 until all cases below finish running.
+    //This is to assert interrupts to the core for testing
+    //------------------------------------------------------
+        SEND_STDOUT_CTRL(0xf8); 
+
+    //------------------------------------------------------
+    //Wake up using software int
+    //------------------------------------------------------
+        printf("Wake up core using software interrupt\n");
+        //Set machine intr enable reg (mie) - enable soft intr
+        __asm__ volatile ("csrwi    %0, %1" \
+                      : /* output: none */        \
+                      : "i" (0x304), "i" (0x08)  /* input : immediate  */ \
+                      : /* clobbers: none */);
+
+        //Halt the core
+        __asm__ volatile ("csrwi    %0, %1" \
+                      : /* output: none */        \
+                      : "i" (0x7c6), "i" (0x03)  /* input : immediate  */ \
+                      : /* clobbers: none */);
+
+    //------------------------------------------------------
+    //Wake SOC up for APB tx and core using timer int later
+    //------------------------------------------------------
+        printf("Wake up SOC clk on APB txns and later wake up core using timer interrupt\n");
+        //Machine intr enable reg (mie) - enable timer int 
+        __asm__ volatile ("csrw    %0, %1" \
+                      : /* output: none */        \
+                      : "i" (0x304), "r" (mie_machinetimer_en)  /* input : immediate  */ \
+                      : /* clobbers: none */);
+
+        *soc_ifc_flow_status = SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_MASK;
+
+        //Halt the core
+        __asm__ volatile ("csrwi    %0, %1" \
+                      : /* output: none */        \
+                      : "i" (0x7c6), "i" (0x03)  /* input : immediate  */ \
+                      : /* clobbers: none */);
+
+    //------------------------------------------------------
+    //Wake up using generic input wires and then soft intr
+    //------------------------------------------------------
+        printf("Wake up clks on change in generic_input_wires and later wake up core using software interrupt\n");
+        //Set machine intr enable reg (mie) - enable soft intr
+        __asm__ volatile ("csrwi    %0, %1" \
+                      : /* output: none */        \
+                      : "i" (0x304), "i" (0x08)  /* input : immediate  */ \
+                      : /* clobbers: none */);
+
+        //Halt the core
+        __asm__ volatile ("csrwi    %0, %1" \
+                      : /* output: none */        \
+                      : "i" (0x7c6), "i" (0x03)  /* input : immediate  */ \
+                      : /* clobbers: none */);
+
+    //------------------------------------------------------
+    //Wake up using JTAG accesses and then mit0 timer intr
+    //------------------------------------------------------
+        printf("Wake up clks on JTAG accesses and later wake up core on t0 timer intr\n");
+        set_mit0(mitb0_1, mie_timer0_en);
+        SEND_STDOUT_CTRL(0xe9); //Force dmi_reg_en input to clk_gate after a delay
+        halt_core();
+
+}
+
diff --git a/src/integration/test_suites/smoke_test_datavault_basic/caliptra_isr.h b/src/integration/test_suites/smoke_test_datavault_basic/caliptra_isr.h
index 48879dc68..8f5779e04 100644
--- a/src/integration/test_suites/smoke_test_datavault_basic/caliptra_isr.h
+++ b/src/integration/test_suites/smoke_test_datavault_basic/caliptra_isr.h
@@ -32,39 +32,216 @@
 #include <stdint.h>
 #include "printf.h"
 
-//extern volatile uint32_t hmac_intr_status;
+/* --------------- symbols/typedefs --------------- */
+typedef struct {
+    uint32_t doe_error;
+    uint32_t doe_notif;
+    uint32_t ecc_error;
+    uint32_t ecc_notif;
+    uint32_t hmac_error;
+    uint32_t hmac_notif;
+    uint32_t kv_error;
+    uint32_t kv_notif;
+    uint32_t sha512_error;
+    uint32_t sha512_notif;
+    uint32_t sha256_error;
+    uint32_t sha256_notif;
+    uint32_t qspi_error;
+    uint32_t qspi_notif;
+    uint32_t uart_error;
+    uint32_t uart_notif;
+    uint32_t i3c_error;
+    uint32_t i3c_notif;
+    uint32_t soc_ifc_error;
+    uint32_t soc_ifc_notif;
+    uint32_t sha512_acc_error;
+    uint32_t sha512_acc_notif;
+} caliptra_intr_received_s;
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
 
 //////////////////////////////////////////////////////////////////////////////
 // Function Declarations
 //
+
 // Performs all the CSR setup to configure and enable vectored external interrupts
 void init_interrupts(void);
 
 // These inline functions are used to insert event-specific functionality into the
 // otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr"
-inline void service_doe_error_intr() {printf("ERROR");}
-inline void service_doe_notif_intr() {printf("ERROR");}
-inline void service_ecc_error_intr   () {printf("ERROR");}
-inline void service_ecc_notif_intr   () {printf("ERROR");}
-inline void service_hmac_error_intr  () {printf("ERROR");}
-inline void service_hmac_notif_intr  () {printf("ERROR");}
-
-inline void service_kv_error_intr    () {printf("ERROR");}
-inline void service_kv_notif_intr    () {printf("ERROR");}
-inline void service_sha512_error_intr() {printf("ERROR");}
-inline void service_sha512_notif_intr() {printf("ERROR");}
-inline void service_sha256_error_intr() {printf("ERROR");}
-inline void service_sha256_notif_intr() {printf("ERROR");}
-inline void service_qspi_error_intr  () {printf("ERROR");}
-inline void service_qspi_notif_intr  () {printf("ERROR");}
-inline void service_uart_error_intr  () {printf("ERROR");}
-inline void service_uart_notif_intr  () {printf("ERROR");}
-inline void service_i3c_error_intr   () {printf("ERROR");}
-inline void service_i3c_notif_intr   () {printf("ERROR");}
-inline void service_soc_ifc_error_intr  () {printf("ERROR");}
-inline void service_soc_ifc_notif_intr  () {printf("ERROR");}
-inline void service_sha512_acc_error_intr() {printf("ERROR");}
-inline void service_sha512_acc_notif_intr() {printf("ERROR");}
+inline void service_doe_error_intr() {return;}
+inline void service_doe_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.doe_notif |= DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad doe_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_ecc_error_intr() {return;}
+inline void service_ecc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.ecc_notif |= ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad ecc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_hmac_error_intr() {return;}
+inline void service_hmac_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.hmac_notif |= HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad hmac_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_kv_error_intr() {return;}
+inline void service_kv_notif_intr() {return;}
+inline void service_sha512_error_intr() {return;}
+inline void service_sha512_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_notif |= SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha256_error_intr() {return;}
+inline void service_sha256_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha256_notif |= SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha256_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_qspi_error_intr() {return;}
+inline void service_qspi_notif_intr() {return;}
+inline void service_uart_error_intr() {return;}
+inline void service_uart_notif_intr() {return;}
+inline void service_i3c_error_intr() {return;}
+inline void service_i3c_notif_intr() {return;}
+
+inline void service_soc_ifc_error_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_error_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_soc_ifc_notif_intr () {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha512_acc_error_intr() {return;}
+inline void service_sha512_acc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_acc_notif |= SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_acc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
 
 
 #endif //CALIPTRA_ISR_H
diff --git a/src/integration/test_suites/smoke_test_datavault_basic/smoke_test_datavault_basic.c b/src/integration/test_suites/smoke_test_datavault_basic/smoke_test_datavault_basic.c
index b7d0a5b01..78f5a809f 100644
--- a/src/integration/test_suites/smoke_test_datavault_basic/smoke_test_datavault_basic.c
+++ b/src/integration/test_suites/smoke_test_datavault_basic/smoke_test_datavault_basic.c
@@ -35,6 +35,30 @@ volatile uint32_t err_count __attribute__((section(".dccm.persistent"))) = 0;
     enum printf_verbosity verbosity_g = LOW;
 #endif
 
+volatile caliptra_intr_received_s cptra_intr_rcv = {
+    .doe_error        = 0,
+    .doe_notif        = 0,
+    .ecc_error        = 0,
+    .ecc_notif        = 0,
+    .hmac_error       = 0,
+    .hmac_notif       = 0,
+    .kv_error         = 0,
+    .kv_notif         = 0,
+    .sha512_error     = 0,
+    .sha512_notif     = 0,
+    .sha256_error     = 0,
+    .sha256_notif     = 0,
+    .qspi_error       = 0,
+    .qspi_notif       = 0,
+    .uart_error       = 0,
+    .uart_notif       = 0,
+    .i3c_error        = 0,
+    .i3c_notif        = 0,
+    .soc_ifc_error    = 0,
+    .soc_ifc_notif    = 0,
+    .sha512_acc_error = 0,
+    .sha512_acc_notif = 0,
+};
 
 #ifndef MY_RANDOM_SEED
 #define MY_RANDOM_SEED 17
diff --git a/src/integration/test_suites/smoke_test_datavault_lock/caliptra_isr.h b/src/integration/test_suites/smoke_test_datavault_lock/caliptra_isr.h
index 48879dc68..8f5779e04 100644
--- a/src/integration/test_suites/smoke_test_datavault_lock/caliptra_isr.h
+++ b/src/integration/test_suites/smoke_test_datavault_lock/caliptra_isr.h
@@ -32,39 +32,216 @@
 #include <stdint.h>
 #include "printf.h"
 
-//extern volatile uint32_t hmac_intr_status;
+/* --------------- symbols/typedefs --------------- */
+typedef struct {
+    uint32_t doe_error;
+    uint32_t doe_notif;
+    uint32_t ecc_error;
+    uint32_t ecc_notif;
+    uint32_t hmac_error;
+    uint32_t hmac_notif;
+    uint32_t kv_error;
+    uint32_t kv_notif;
+    uint32_t sha512_error;
+    uint32_t sha512_notif;
+    uint32_t sha256_error;
+    uint32_t sha256_notif;
+    uint32_t qspi_error;
+    uint32_t qspi_notif;
+    uint32_t uart_error;
+    uint32_t uart_notif;
+    uint32_t i3c_error;
+    uint32_t i3c_notif;
+    uint32_t soc_ifc_error;
+    uint32_t soc_ifc_notif;
+    uint32_t sha512_acc_error;
+    uint32_t sha512_acc_notif;
+} caliptra_intr_received_s;
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
 
 //////////////////////////////////////////////////////////////////////////////
 // Function Declarations
 //
+
 // Performs all the CSR setup to configure and enable vectored external interrupts
 void init_interrupts(void);
 
 // These inline functions are used to insert event-specific functionality into the
 // otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr"
-inline void service_doe_error_intr() {printf("ERROR");}
-inline void service_doe_notif_intr() {printf("ERROR");}
-inline void service_ecc_error_intr   () {printf("ERROR");}
-inline void service_ecc_notif_intr   () {printf("ERROR");}
-inline void service_hmac_error_intr  () {printf("ERROR");}
-inline void service_hmac_notif_intr  () {printf("ERROR");}
-
-inline void service_kv_error_intr    () {printf("ERROR");}
-inline void service_kv_notif_intr    () {printf("ERROR");}
-inline void service_sha512_error_intr() {printf("ERROR");}
-inline void service_sha512_notif_intr() {printf("ERROR");}
-inline void service_sha256_error_intr() {printf("ERROR");}
-inline void service_sha256_notif_intr() {printf("ERROR");}
-inline void service_qspi_error_intr  () {printf("ERROR");}
-inline void service_qspi_notif_intr  () {printf("ERROR");}
-inline void service_uart_error_intr  () {printf("ERROR");}
-inline void service_uart_notif_intr  () {printf("ERROR");}
-inline void service_i3c_error_intr   () {printf("ERROR");}
-inline void service_i3c_notif_intr   () {printf("ERROR");}
-inline void service_soc_ifc_error_intr  () {printf("ERROR");}
-inline void service_soc_ifc_notif_intr  () {printf("ERROR");}
-inline void service_sha512_acc_error_intr() {printf("ERROR");}
-inline void service_sha512_acc_notif_intr() {printf("ERROR");}
+inline void service_doe_error_intr() {return;}
+inline void service_doe_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.doe_notif |= DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad doe_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_ecc_error_intr() {return;}
+inline void service_ecc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.ecc_notif |= ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad ecc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_hmac_error_intr() {return;}
+inline void service_hmac_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.hmac_notif |= HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad hmac_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_kv_error_intr() {return;}
+inline void service_kv_notif_intr() {return;}
+inline void service_sha512_error_intr() {return;}
+inline void service_sha512_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_notif |= SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha256_error_intr() {return;}
+inline void service_sha256_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha256_notif |= SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha256_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_qspi_error_intr() {return;}
+inline void service_qspi_notif_intr() {return;}
+inline void service_uart_error_intr() {return;}
+inline void service_uart_notif_intr() {return;}
+inline void service_i3c_error_intr() {return;}
+inline void service_i3c_notif_intr() {return;}
+
+inline void service_soc_ifc_error_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_error_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_soc_ifc_notif_intr () {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha512_acc_error_intr() {return;}
+inline void service_sha512_acc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_acc_notif |= SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_acc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
 
 
 #endif //CALIPTRA_ISR_H
diff --git a/src/integration/test_suites/smoke_test_datavault_lock/smoke_test_datavault_lock.c b/src/integration/test_suites/smoke_test_datavault_lock/smoke_test_datavault_lock.c
index 1998304fb..1a995fc73 100644
--- a/src/integration/test_suites/smoke_test_datavault_lock/smoke_test_datavault_lock.c
+++ b/src/integration/test_suites/smoke_test_datavault_lock/smoke_test_datavault_lock.c
@@ -35,6 +35,31 @@ volatile uint32_t err_count __attribute__((section(".dccm.persistent"))) = 0;
     enum printf_verbosity verbosity_g = LOW;
 #endif
 
+volatile caliptra_intr_received_s cptra_intr_rcv = {
+    .doe_error        = 0,
+    .doe_notif        = 0,
+    .ecc_error        = 0,
+    .ecc_notif        = 0,
+    .hmac_error       = 0,
+    .hmac_notif       = 0,
+    .kv_error         = 0,
+    .kv_notif         = 0,
+    .sha512_error     = 0,
+    .sha512_notif     = 0,
+    .sha256_error     = 0,
+    .sha256_notif     = 0,
+    .qspi_error       = 0,
+    .qspi_notif       = 0,
+    .uart_error       = 0,
+    .uart_notif       = 0,
+    .i3c_error        = 0,
+    .i3c_notif        = 0,
+    .soc_ifc_error    = 0,
+    .soc_ifc_notif    = 0,
+    .sha512_acc_error = 0,
+    .sha512_acc_notif = 0,
+};
+
 #ifndef MY_RANDOM_SEED
 #define MY_RANDOM_SEED 17
 #endif // MY_RANDOM_SEED
diff --git a/src/integration/test_suites/smoke_test_datavault_mini/caliptra_isr.h b/src/integration/test_suites/smoke_test_datavault_mini/caliptra_isr.h
index 48879dc68..8f5779e04 100644
--- a/src/integration/test_suites/smoke_test_datavault_mini/caliptra_isr.h
+++ b/src/integration/test_suites/smoke_test_datavault_mini/caliptra_isr.h
@@ -32,39 +32,216 @@
 #include <stdint.h>
 #include "printf.h"
 
-//extern volatile uint32_t hmac_intr_status;
+/* --------------- symbols/typedefs --------------- */
+typedef struct {
+    uint32_t doe_error;
+    uint32_t doe_notif;
+    uint32_t ecc_error;
+    uint32_t ecc_notif;
+    uint32_t hmac_error;
+    uint32_t hmac_notif;
+    uint32_t kv_error;
+    uint32_t kv_notif;
+    uint32_t sha512_error;
+    uint32_t sha512_notif;
+    uint32_t sha256_error;
+    uint32_t sha256_notif;
+    uint32_t qspi_error;
+    uint32_t qspi_notif;
+    uint32_t uart_error;
+    uint32_t uart_notif;
+    uint32_t i3c_error;
+    uint32_t i3c_notif;
+    uint32_t soc_ifc_error;
+    uint32_t soc_ifc_notif;
+    uint32_t sha512_acc_error;
+    uint32_t sha512_acc_notif;
+} caliptra_intr_received_s;
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
 
 //////////////////////////////////////////////////////////////////////////////
 // Function Declarations
 //
+
 // Performs all the CSR setup to configure and enable vectored external interrupts
 void init_interrupts(void);
 
 // These inline functions are used to insert event-specific functionality into the
 // otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr"
-inline void service_doe_error_intr() {printf("ERROR");}
-inline void service_doe_notif_intr() {printf("ERROR");}
-inline void service_ecc_error_intr   () {printf("ERROR");}
-inline void service_ecc_notif_intr   () {printf("ERROR");}
-inline void service_hmac_error_intr  () {printf("ERROR");}
-inline void service_hmac_notif_intr  () {printf("ERROR");}
-
-inline void service_kv_error_intr    () {printf("ERROR");}
-inline void service_kv_notif_intr    () {printf("ERROR");}
-inline void service_sha512_error_intr() {printf("ERROR");}
-inline void service_sha512_notif_intr() {printf("ERROR");}
-inline void service_sha256_error_intr() {printf("ERROR");}
-inline void service_sha256_notif_intr() {printf("ERROR");}
-inline void service_qspi_error_intr  () {printf("ERROR");}
-inline void service_qspi_notif_intr  () {printf("ERROR");}
-inline void service_uart_error_intr  () {printf("ERROR");}
-inline void service_uart_notif_intr  () {printf("ERROR");}
-inline void service_i3c_error_intr   () {printf("ERROR");}
-inline void service_i3c_notif_intr   () {printf("ERROR");}
-inline void service_soc_ifc_error_intr  () {printf("ERROR");}
-inline void service_soc_ifc_notif_intr  () {printf("ERROR");}
-inline void service_sha512_acc_error_intr() {printf("ERROR");}
-inline void service_sha512_acc_notif_intr() {printf("ERROR");}
+inline void service_doe_error_intr() {return;}
+inline void service_doe_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.doe_notif |= DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad doe_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_ecc_error_intr() {return;}
+inline void service_ecc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.ecc_notif |= ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad ecc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_hmac_error_intr() {return;}
+inline void service_hmac_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.hmac_notif |= HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad hmac_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_kv_error_intr() {return;}
+inline void service_kv_notif_intr() {return;}
+inline void service_sha512_error_intr() {return;}
+inline void service_sha512_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_notif |= SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha256_error_intr() {return;}
+inline void service_sha256_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha256_notif |= SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha256_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_qspi_error_intr() {return;}
+inline void service_qspi_notif_intr() {return;}
+inline void service_uart_error_intr() {return;}
+inline void service_uart_notif_intr() {return;}
+inline void service_i3c_error_intr() {return;}
+inline void service_i3c_notif_intr() {return;}
+
+inline void service_soc_ifc_error_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_error_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_soc_ifc_notif_intr () {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha512_acc_error_intr() {return;}
+inline void service_sha512_acc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_acc_notif |= SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_acc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
 
 
 #endif //CALIPTRA_ISR_H
diff --git a/src/integration/test_suites/smoke_test_datavault_mini/smoke_test_datavault_mini.c b/src/integration/test_suites/smoke_test_datavault_mini/smoke_test_datavault_mini.c
index 7f7f64f12..b402e7a68 100644
--- a/src/integration/test_suites/smoke_test_datavault_mini/smoke_test_datavault_mini.c
+++ b/src/integration/test_suites/smoke_test_datavault_mini/smoke_test_datavault_mini.c
@@ -42,6 +42,32 @@ volatile uint32_t err_count __attribute__((section(".dccm.persistent"))) = 0;
     enum printf_verbosity verbosity_g = LOW;
 #endif
 
+volatile caliptra_intr_received_s cptra_intr_rcv = {
+    .doe_error        = 0,
+    .doe_notif        = 0,
+    .ecc_error        = 0,
+    .ecc_notif        = 0,
+    .hmac_error       = 0,
+    .hmac_notif       = 0,
+    .kv_error         = 0,
+    .kv_notif         = 0,
+    .sha512_error     = 0,
+    .sha512_notif     = 0,
+    .sha256_error     = 0,
+    .sha256_notif     = 0,
+    .qspi_error       = 0,
+    .qspi_notif       = 0,
+    .uart_error       = 0,
+    .uart_notif       = 0,
+    .i3c_error        = 0,
+    .i3c_notif        = 0,
+    .soc_ifc_error    = 0,
+    .soc_ifc_notif    = 0,
+    .sha512_acc_error = 0,
+    .sha512_acc_notif = 0,
+};
+
+
 #ifndef MY_RANDOM_SEED
 #define MY_RANDOM_SEED 17
 #endif // MY_RANDOM_SEED
@@ -63,11 +89,11 @@ widereg_t sm_dv_regs [SM_DV_PFX_COUNT] = {
     { "STICKYDATAVAULTCTRL",                 (uint32_t *) CLP_DV_REG_STICKYDATAVAULTCTRL_0,             2,  0x1,     0x0 }, //  0. (0x1001c000) 
     { "STICKY_DATA_VAULT_ENTRY_0",           (uint32_t *) CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_0_0,       3,  DV_ONES, 0x0 }, //  1. (0x1001c028) 
     { "STICKY_DATA_VAULT_ENTRY_1",           (uint32_t *) CLP_DV_REG_STICKY_DATA_VAULT_ENTRY_1_0,       3,  DV_ONES, 0x0 }, //  2. (0x1001c058) 
-    { "NONSTICKYDATAVAULTCTRL",              (uint32_t *) CLP_DV_REG_NONSTICKYDATAVAULTCTRL_0,          2,  0x0,     0x0 }, //  3. (0x1001c208) 
-    { "NONSTICKY_DATA_VAULT_ENTRY_0",        (uint32_t *) CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_0_0,    3,  0x0,     0x0 }, //  4. (0x1001c230) 
-    { "NONSTICKY_DATA_VAULT_ENTRY_1",        (uint32_t *) CLP_DV_REG_NONSTICKY_DATA_VAULT_ENTRY_1_0,    3,  0x0,     0x0 }, //  5. (0x1001c260) 
-    { "NONSTICKY_LOCKABLE_SCRATCHREG_CTRL",  (uint32_t *) CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREGCTRL_0, 2,  0x0,     0x0 }, //  6. (0x1001c410)
-    { "NONSTICKY_LOCKABLE_SCRATCHREG",       (uint32_t *) CLP_DV_REG_NONSTICKYLOCKABLESCRATCHREG_0,     2,  0x0,     0x0 }, //  7. (0x1001c438) 
+    { "DATAVAULTCTRL",                       (uint32_t *) CLP_DV_REG_DATAVAULTCTRL_0,                   2,  0x0,     0x0 }, //  3. (0x1001c208) 
+    { "DATA_VAULT_ENTRY_0",                  (uint32_t *) CLP_DV_REG_DATA_VAULT_ENTRY_0_0,              3,  DV_ONES, 0x0 }, //  4. (0x1001c230) 
+    { "DATA_VAULT_ENTRY_1",                  (uint32_t *) CLP_DV_REG_DATA_VAULT_ENTRY_1_0,              3,  DV_ONES, 0x0 }, //  5. (0x1001c260) 
+    { "LOCKABLE_SCRATCHREG_CTRL",            (uint32_t *) CLP_DV_REG_LOCKABLESCRATCHREGCTRL_0,          2,  0x0,     0x0 }, //  6. (0x1001c410)
+    { "LOCKABLE_SCRATCHREG",                 (uint32_t *) CLP_DV_REG_LOCKABLESCRATCHREG_0,              2,  DV_ONES, 0x0 }, //  7. (0x1001c438) 
     { "STICKY_LOCKABLE_SCRATCHREGCTRL",      (uint32_t *) CLP_DV_REG_STICKYLOCKABLESCRATCHREGCTRL_0,    2,  0x1,     0x0 }, //  8. (0x1001c480) 
     { "STICKY_LOCKABLE_SCRATCHREG",          (uint32_t *) CLP_DV_REG_STICKYLOCKABLESCRATCHREG_0,        2,  DV_ONES, 0x0 }  //  9. (0x1001c4a0) 
 };
diff --git a/src/integration/test_suites/smoke_test_datavault_reset/caliptra_isr.h b/src/integration/test_suites/smoke_test_datavault_reset/caliptra_isr.h
index 48879dc68..8f5779e04 100644
--- a/src/integration/test_suites/smoke_test_datavault_reset/caliptra_isr.h
+++ b/src/integration/test_suites/smoke_test_datavault_reset/caliptra_isr.h
@@ -32,39 +32,216 @@
 #include <stdint.h>
 #include "printf.h"
 
-//extern volatile uint32_t hmac_intr_status;
+/* --------------- symbols/typedefs --------------- */
+typedef struct {
+    uint32_t doe_error;
+    uint32_t doe_notif;
+    uint32_t ecc_error;
+    uint32_t ecc_notif;
+    uint32_t hmac_error;
+    uint32_t hmac_notif;
+    uint32_t kv_error;
+    uint32_t kv_notif;
+    uint32_t sha512_error;
+    uint32_t sha512_notif;
+    uint32_t sha256_error;
+    uint32_t sha256_notif;
+    uint32_t qspi_error;
+    uint32_t qspi_notif;
+    uint32_t uart_error;
+    uint32_t uart_notif;
+    uint32_t i3c_error;
+    uint32_t i3c_notif;
+    uint32_t soc_ifc_error;
+    uint32_t soc_ifc_notif;
+    uint32_t sha512_acc_error;
+    uint32_t sha512_acc_notif;
+} caliptra_intr_received_s;
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
 
 //////////////////////////////////////////////////////////////////////////////
 // Function Declarations
 //
+
 // Performs all the CSR setup to configure and enable vectored external interrupts
 void init_interrupts(void);
 
 // These inline functions are used to insert event-specific functionality into the
 // otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr"
-inline void service_doe_error_intr() {printf("ERROR");}
-inline void service_doe_notif_intr() {printf("ERROR");}
-inline void service_ecc_error_intr   () {printf("ERROR");}
-inline void service_ecc_notif_intr   () {printf("ERROR");}
-inline void service_hmac_error_intr  () {printf("ERROR");}
-inline void service_hmac_notif_intr  () {printf("ERROR");}
-
-inline void service_kv_error_intr    () {printf("ERROR");}
-inline void service_kv_notif_intr    () {printf("ERROR");}
-inline void service_sha512_error_intr() {printf("ERROR");}
-inline void service_sha512_notif_intr() {printf("ERROR");}
-inline void service_sha256_error_intr() {printf("ERROR");}
-inline void service_sha256_notif_intr() {printf("ERROR");}
-inline void service_qspi_error_intr  () {printf("ERROR");}
-inline void service_qspi_notif_intr  () {printf("ERROR");}
-inline void service_uart_error_intr  () {printf("ERROR");}
-inline void service_uart_notif_intr  () {printf("ERROR");}
-inline void service_i3c_error_intr   () {printf("ERROR");}
-inline void service_i3c_notif_intr   () {printf("ERROR");}
-inline void service_soc_ifc_error_intr  () {printf("ERROR");}
-inline void service_soc_ifc_notif_intr  () {printf("ERROR");}
-inline void service_sha512_acc_error_intr() {printf("ERROR");}
-inline void service_sha512_acc_notif_intr() {printf("ERROR");}
+inline void service_doe_error_intr() {return;}
+inline void service_doe_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.doe_notif |= DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad doe_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_ecc_error_intr() {return;}
+inline void service_ecc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.ecc_notif |= ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad ecc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_hmac_error_intr() {return;}
+inline void service_hmac_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.hmac_notif |= HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad hmac_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_kv_error_intr() {return;}
+inline void service_kv_notif_intr() {return;}
+inline void service_sha512_error_intr() {return;}
+inline void service_sha512_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_notif |= SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha256_error_intr() {return;}
+inline void service_sha256_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha256_notif |= SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha256_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_qspi_error_intr() {return;}
+inline void service_qspi_notif_intr() {return;}
+inline void service_uart_error_intr() {return;}
+inline void service_uart_notif_intr() {return;}
+inline void service_i3c_error_intr() {return;}
+inline void service_i3c_notif_intr() {return;}
+
+inline void service_soc_ifc_error_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_error_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_soc_ifc_notif_intr () {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha512_acc_error_intr() {return;}
+inline void service_sha512_acc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_acc_notif |= SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_acc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
 
 
 #endif //CALIPTRA_ISR_H
diff --git a/src/integration/test_suites/smoke_test_datavault_reset/smoke_test_datavault_reset.c b/src/integration/test_suites/smoke_test_datavault_reset/smoke_test_datavault_reset.c
index 68813734f..c0a40a93d 100644
--- a/src/integration/test_suites/smoke_test_datavault_reset/smoke_test_datavault_reset.c
+++ b/src/integration/test_suites/smoke_test_datavault_reset/smoke_test_datavault_reset.c
@@ -34,6 +34,30 @@ volatile uint32_t err_count __attribute__((section(".dccm.persistent"))) = 0;
     enum printf_verbosity verbosity_g = LOW;
 #endif
 
+volatile caliptra_intr_received_s cptra_intr_rcv = {
+    .doe_error        = 0,
+    .doe_notif        = 0,
+    .ecc_error        = 0,
+    .ecc_notif        = 0,
+    .hmac_error       = 0,
+    .hmac_notif       = 0,
+    .kv_error         = 0,
+    .kv_notif         = 0,
+    .sha512_error     = 0,
+    .sha512_notif     = 0,
+    .sha256_error     = 0,
+    .sha256_notif     = 0,
+    .qspi_error       = 0,
+    .qspi_notif       = 0,
+    .uart_error       = 0,
+    .uart_notif       = 0,
+    .i3c_error        = 0,
+    .i3c_notif        = 0,
+    .soc_ifc_error    = 0,
+    .soc_ifc_notif    = 0,
+    .sha512_acc_error = 0,
+    .sha512_acc_notif = 0,
+};
 
 #ifndef MY_RANDOM_SEED
 #define MY_RANDOM_SEED 17
diff --git a/src/integration/test_suites/smoke_test_doe_cg/caliptra_isr.h b/src/integration/test_suites/smoke_test_doe_cg/caliptra_isr.h
new file mode 100644
index 000000000..8f5779e04
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_doe_cg/caliptra_isr.h
@@ -0,0 +1,247 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// ---------------------------------------------------------------------
+// File: caliptra_isr.h
+// Description:
+//     Provides function declarations for use by external test files, so
+//     that the ISR functionality may behave like a library.
+//     TODO:
+//     This header file includes inline function definitions for event and
+//     test specific interrupt service behavior, so it should be copied and
+//     modified for each test.
+// ---------------------------------------------------------------------
+
+#ifndef CALIPTRA_ISR_H
+    #define CALIPTRA_ISR_H
+
+#define EN_ISR_PRINTS 1
+
+#include "caliptra_defines.h"
+#include <stdint.h>
+#include "printf.h"
+
+/* --------------- symbols/typedefs --------------- */
+typedef struct {
+    uint32_t doe_error;
+    uint32_t doe_notif;
+    uint32_t ecc_error;
+    uint32_t ecc_notif;
+    uint32_t hmac_error;
+    uint32_t hmac_notif;
+    uint32_t kv_error;
+    uint32_t kv_notif;
+    uint32_t sha512_error;
+    uint32_t sha512_notif;
+    uint32_t sha256_error;
+    uint32_t sha256_notif;
+    uint32_t qspi_error;
+    uint32_t qspi_notif;
+    uint32_t uart_error;
+    uint32_t uart_notif;
+    uint32_t i3c_error;
+    uint32_t i3c_notif;
+    uint32_t soc_ifc_error;
+    uint32_t soc_ifc_notif;
+    uint32_t sha512_acc_error;
+    uint32_t sha512_acc_notif;
+} caliptra_intr_received_s;
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
+
+//////////////////////////////////////////////////////////////////////////////
+// Function Declarations
+//
+
+// Performs all the CSR setup to configure and enable vectored external interrupts
+void init_interrupts(void);
+
+// These inline functions are used to insert event-specific functionality into the
+// otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr"
+inline void service_doe_error_intr() {return;}
+inline void service_doe_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.doe_notif |= DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad doe_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_ecc_error_intr() {return;}
+inline void service_ecc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.ecc_notif |= ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad ecc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_hmac_error_intr() {return;}
+inline void service_hmac_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.hmac_notif |= HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad hmac_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_kv_error_intr() {return;}
+inline void service_kv_notif_intr() {return;}
+inline void service_sha512_error_intr() {return;}
+inline void service_sha512_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_notif |= SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha256_error_intr() {return;}
+inline void service_sha256_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha256_notif |= SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha256_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_qspi_error_intr() {return;}
+inline void service_qspi_notif_intr() {return;}
+inline void service_uart_error_intr() {return;}
+inline void service_uart_notif_intr() {return;}
+inline void service_i3c_error_intr() {return;}
+inline void service_i3c_notif_intr() {return;}
+
+inline void service_soc_ifc_error_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_error_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_soc_ifc_notif_intr () {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha512_acc_error_intr() {return;}
+inline void service_sha512_acc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_acc_notif |= SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_acc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+
+#endif //CALIPTRA_ISR_H
diff --git a/src/integration/test_suites/smoke_test_doe_cg/smoke_test_doe_cg.c b/src/integration/test_suites/smoke_test_doe_cg/smoke_test_doe_cg.c
new file mode 100644
index 000000000..abab48c5c
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_doe_cg/smoke_test_doe_cg.c
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+
+#include "caliptra_defines.h"
+#include "caliptra_isr.h"
+#include "riscv-csr.h"
+#include <string.h>
+#include <stdint.h>
+#include "printf.h"
+#include "clk_gate.h"
+
+volatile char*    stdout           = (char *)STDOUT;
+volatile uint32_t intr_count = 0;
+volatile uint32_t rst_count __attribute__((section(".dccm.persistent"))) = 0;
+#ifdef CPT_VERBOSITY
+    enum printf_verbosity verbosity_g = CPT_VERBOSITY;
+#else
+    enum printf_verbosity verbosity_g = LOW;
+#endif
+
+uint32_t IV_DATA_UDS0 = 0x2eb94297;
+uint32_t IV_DATA_UDS1 = 0x77285196;
+uint32_t IV_DATA_UDS2 = 0x3dd39a1e;
+uint32_t IV_DATA_UDS3 = 0xb95d438f;
+
+volatile uint32_t * doe_iv_0 = (uint32_t *) CLP_DOE_REG_DOE_IV_0;
+volatile uint32_t * doe_iv_1 = (uint32_t *) CLP_DOE_REG_DOE_IV_1;
+volatile uint32_t * doe_iv_2 = (uint32_t *) CLP_DOE_REG_DOE_IV_2;
+volatile uint32_t * doe_iv_3 = (uint32_t *) CLP_DOE_REG_DOE_IV_3;
+
+volatile uint32_t * doe_ctrl = (uint32_t *) CLP_DOE_REG_DOE_CTRL;
+volatile uint32_t * doe_status = (uint32_t *) CLP_DOE_REG_DOE_STATUS;
+
+volatile uint32_t * soc_ifc_fw_update_reset = (uint32_t *) (CLP_SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET);
+
+volatile uint32_t * pcr_ctrl0 = (uint32_t *) CLP_PV_REG_PCR_CTRL_0;
+volatile uint32_t * pcr_ctrl2 = (uint32_t *) CLP_PV_REG_PCR_CTRL_2;
+volatile uint32_t * pcr_ctrl5 = (uint32_t *) CLP_PV_REG_PCR_CTRL_5;
+
+volatile uint32_t * key_ctrl1 = (uint32_t *) CLP_KV_REG_KEY_CTRL_1;
+volatile uint32_t * key_ctrl4 = (uint32_t *) CLP_KV_REG_KEY_CTRL_4;
+volatile uint32_t * key_ctrl7 = (uint32_t *) CLP_KV_REG_KEY_CTRL_7;
+
+volatile uint32_t doe_status_int;
+
+volatile caliptra_intr_received_s cptra_intr_rcv = {
+    .doe_error        = 0,
+    .doe_notif        = 0,
+    .ecc_error        = 0,
+    .ecc_notif        = 0,
+    .hmac_error       = 0,
+    .hmac_notif       = 0,
+    .kv_error         = 0,
+    .kv_notif         = 0,
+    .sha512_error     = 0,
+    .sha512_notif     = 0,
+    .sha256_error     = 0,
+    .sha256_notif     = 0,
+    .qspi_error       = 0,
+    .qspi_notif       = 0,
+    .uart_error       = 0,
+    .uart_notif       = 0,
+    .i3c_error        = 0,
+    .i3c_notif        = 0,
+    .soc_ifc_error    = 0,
+    .soc_ifc_notif    = 0,
+    .sha512_acc_error = 0,
+    .sha512_acc_notif = 0,
+};
+
+void main() {
+    volatile uint32_t mitb0 = 0x00000400;
+    volatile uint32_t mitb1 = 0x00000500;
+    volatile uint32_t mie_timer0_en = 0x20000000;
+
+    rst_count++;
+
+    VPRINTF(LOW,"---------------------------\n");
+    VPRINTF(LOW," DOE Smoke Test With Rand UDS/FE !!\n");
+    VPRINTF(LOW,"---------------------------\n");
+
+    //Call interrupt init
+    init_interrupts();
+
+    if (rst_count == 1) {
+    //Enable clk gating and halt core
+    SEND_STDOUT_CTRL(0xf2);
+    set_mit0(mitb0, mie_timer0_en);
+    
+    //VPRINTF(LOW,"Rand UDS\n");
+    printf("Rand UDS\n");
+
+    //Start UDS and store in KV3
+    SEND_STDOUT_CTRL(0xec);
+    *doe_ctrl = 0x0000000D;
+
+    printf("Dummy\n");
+    __asm__ volatile ("csrwi    %0, %1" \
+                    : /* output: none */        \
+                    : "i" (0x7c6), "i" (0x03)  /* input : immediate  */ \
+                    : /* clobbers: none */);
+
+    // //Poll for DOE status
+    while(doe_status_int != (DOE_REG_DOE_STATUS_VALID_MASK | DOE_REG_DOE_STATUS_READY_MASK)) {
+        doe_status_int = *doe_status;
+        doe_status_int = doe_status_int & (DOE_REG_DOE_STATUS_VALID_MASK | DOE_REG_DOE_STATUS_READY_MASK) ;
+    }
+
+    //Clear doe_status_int
+    doe_status_int = 0;
+
+}
diff --git a/src/integration/test_suites/smoke_test_doe_cg/smoke_test_doe_cg.yml b/src/integration/test_suites/smoke_test_doe_cg/smoke_test_doe_cg.yml
new file mode 100644
index 000000000..1566a41b1
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_doe_cg/smoke_test_doe_cg.yml
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+---
+plusargs:
+  - +RAND_DOE_VALUES
+seed: 1
+testname: smoke_test_doe_cg
\ No newline at end of file
diff --git a/src/integration/test_suites/smoke_test_doe_rand/caliptra_isr.h b/src/integration/test_suites/smoke_test_doe_rand/caliptra_isr.h
new file mode 100644
index 000000000..8f5779e04
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_doe_rand/caliptra_isr.h
@@ -0,0 +1,247 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// ---------------------------------------------------------------------
+// File: caliptra_isr.h
+// Description:
+//     Provides function declarations for use by external test files, so
+//     that the ISR functionality may behave like a library.
+//     TODO:
+//     This header file includes inline function definitions for event and
+//     test specific interrupt service behavior, so it should be copied and
+//     modified for each test.
+// ---------------------------------------------------------------------
+
+#ifndef CALIPTRA_ISR_H
+    #define CALIPTRA_ISR_H
+
+#define EN_ISR_PRINTS 1
+
+#include "caliptra_defines.h"
+#include <stdint.h>
+#include "printf.h"
+
+/* --------------- symbols/typedefs --------------- */
+typedef struct {
+    uint32_t doe_error;
+    uint32_t doe_notif;
+    uint32_t ecc_error;
+    uint32_t ecc_notif;
+    uint32_t hmac_error;
+    uint32_t hmac_notif;
+    uint32_t kv_error;
+    uint32_t kv_notif;
+    uint32_t sha512_error;
+    uint32_t sha512_notif;
+    uint32_t sha256_error;
+    uint32_t sha256_notif;
+    uint32_t qspi_error;
+    uint32_t qspi_notif;
+    uint32_t uart_error;
+    uint32_t uart_notif;
+    uint32_t i3c_error;
+    uint32_t i3c_notif;
+    uint32_t soc_ifc_error;
+    uint32_t soc_ifc_notif;
+    uint32_t sha512_acc_error;
+    uint32_t sha512_acc_notif;
+} caliptra_intr_received_s;
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
+
+//////////////////////////////////////////////////////////////////////////////
+// Function Declarations
+//
+
+// Performs all the CSR setup to configure and enable vectored external interrupts
+void init_interrupts(void);
+
+// These inline functions are used to insert event-specific functionality into the
+// otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr"
+inline void service_doe_error_intr() {return;}
+inline void service_doe_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.doe_notif |= DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad doe_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_ecc_error_intr() {return;}
+inline void service_ecc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.ecc_notif |= ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad ecc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_hmac_error_intr() {return;}
+inline void service_hmac_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.hmac_notif |= HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad hmac_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_kv_error_intr() {return;}
+inline void service_kv_notif_intr() {return;}
+inline void service_sha512_error_intr() {return;}
+inline void service_sha512_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_notif |= SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha256_error_intr() {return;}
+inline void service_sha256_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha256_notif |= SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha256_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_qspi_error_intr() {return;}
+inline void service_qspi_notif_intr() {return;}
+inline void service_uart_error_intr() {return;}
+inline void service_uart_notif_intr() {return;}
+inline void service_i3c_error_intr() {return;}
+inline void service_i3c_notif_intr() {return;}
+
+inline void service_soc_ifc_error_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_error_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_soc_ifc_notif_intr () {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha512_acc_error_intr() {return;}
+inline void service_sha512_acc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_acc_notif |= SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_acc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+
+#endif //CALIPTRA_ISR_H
diff --git a/src/integration/test_suites/smoke_test_doe_rand/smoke_test_doe_rand.c b/src/integration/test_suites/smoke_test_doe_rand/smoke_test_doe_rand.c
new file mode 100644
index 000000000..4609650e4
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_doe_rand/smoke_test_doe_rand.c
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+
+#include "caliptra_defines.h"
+#include "caliptra_isr.h"
+#include "riscv-csr.h"
+#include <string.h>
+#include <stdint.h>
+#include "printf.h"
+
+volatile char*    stdout           = (char *)STDOUT;
+volatile uint32_t intr_count = 0;
+volatile uint32_t rst_count __attribute__((section(".dccm.persistent"))) = 0;
+#ifdef CPT_VERBOSITY
+    enum printf_verbosity verbosity_g = CPT_VERBOSITY;
+#else
+    enum printf_verbosity verbosity_g = LOW;
+#endif
+
+uint32_t IV_DATA_UDS0 = 0x2eb94297;
+uint32_t IV_DATA_UDS1 = 0x77285196;
+uint32_t IV_DATA_UDS2 = 0x3dd39a1e;
+uint32_t IV_DATA_UDS3 = 0xb95d438f;
+
+volatile uint32_t * doe_iv_0 = (uint32_t *) CLP_DOE_REG_DOE_IV_0;
+volatile uint32_t * doe_iv_1 = (uint32_t *) CLP_DOE_REG_DOE_IV_1;
+volatile uint32_t * doe_iv_2 = (uint32_t *) CLP_DOE_REG_DOE_IV_2;
+volatile uint32_t * doe_iv_3 = (uint32_t *) CLP_DOE_REG_DOE_IV_3;
+
+volatile uint32_t * doe_ctrl = (uint32_t *) CLP_DOE_REG_DOE_CTRL;
+volatile uint32_t * doe_status = (uint32_t *) CLP_DOE_REG_DOE_STATUS;
+
+volatile uint32_t * soc_ifc_fw_update_reset = (uint32_t *) (CLP_SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET);
+
+volatile uint32_t * pcr_ctrl0 = (uint32_t *) CLP_PV_REG_PCR_CTRL_0;
+volatile uint32_t * pcr_ctrl2 = (uint32_t *) CLP_PV_REG_PCR_CTRL_2;
+volatile uint32_t * pcr_ctrl5 = (uint32_t *) CLP_PV_REG_PCR_CTRL_5;
+
+volatile uint32_t * key_ctrl1 = (uint32_t *) CLP_KV_REG_KEY_CTRL_1;
+volatile uint32_t * key_ctrl4 = (uint32_t *) CLP_KV_REG_KEY_CTRL_4;
+volatile uint32_t * key_ctrl7 = (uint32_t *) CLP_KV_REG_KEY_CTRL_7;
+
+volatile uint32_t doe_status_int;
+
+volatile caliptra_intr_received_s cptra_intr_rcv = {
+    .doe_error        = 0,
+    .doe_notif        = 0,
+    .ecc_error        = 0,
+    .ecc_notif        = 0,
+    .hmac_error       = 0,
+    .hmac_notif       = 0,
+    .kv_error         = 0,
+    .kv_notif         = 0,
+    .sha512_error     = 0,
+    .sha512_notif     = 0,
+    .sha256_error     = 0,
+    .sha256_notif     = 0,
+    .qspi_error       = 0,
+    .qspi_notif       = 0,
+    .uart_error       = 0,
+    .uart_notif       = 0,
+    .i3c_error        = 0,
+    .i3c_notif        = 0,
+    .soc_ifc_error    = 0,
+    .soc_ifc_notif    = 0,
+    .sha512_acc_error = 0,
+    .sha512_acc_notif = 0,
+};
+
+void main() {
+    VPRINTF(LOW,"---------------------------\n");
+    VPRINTF(LOW," DOE Smoke Test With Rand UDS/FE !!\n");
+    VPRINTF(LOW,"---------------------------\n");
+
+    //Call interrupt init
+    //init_interrupts();
+    
+    VPRINTF(LOW,"Rand UDS\n");
+
+    //Start UDS and store in KV3
+    SEND_STDOUT_CTRL(0xec);
+    *doe_ctrl = 0x0000000D;
+
+    // //Poll for DOE status
+    while(doe_status_int != (DOE_REG_DOE_STATUS_VALID_MASK | DOE_REG_DOE_STATUS_READY_MASK)) {
+        doe_status_int = *doe_status;
+        doe_status_int = doe_status_int & (DOE_REG_DOE_STATUS_VALID_MASK | DOE_REG_DOE_STATUS_READY_MASK) ;
+    }
+
+    //Clear doe_status_int
+    doe_status_int = 0;
+
+    //Start FE and store in KV15
+    SEND_STDOUT_CTRL(0xed);
+    *doe_ctrl = 0x00000062; //30;
+
+    // //Poll for DOE status
+    while(doe_status_int != (DOE_REG_DOE_STATUS_VALID_MASK | DOE_REG_DOE_STATUS_READY_MASK)) {
+        doe_status_int = *doe_status;
+        doe_status_int = doe_status_int & (DOE_REG_DOE_STATUS_VALID_MASK | DOE_REG_DOE_STATUS_READY_MASK) ;
+    }
+}
diff --git a/src/integration/test_suites/smoke_test_doe_rand/smoke_test_doe_rand.yml b/src/integration/test_suites/smoke_test_doe_rand/smoke_test_doe_rand.yml
new file mode 100644
index 000000000..001bbe8a3
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_doe_rand/smoke_test_doe_rand.yml
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+---
+plusargs:
+  - +RAND_DOE_VALUES
+seed: 1
+testname: smoke_test_doe_rand
\ No newline at end of file
diff --git a/src/integration/test_suites/smoke_test_doe_scan/caliptra_isr.h b/src/integration/test_suites/smoke_test_doe_scan/caliptra_isr.h
new file mode 100644
index 000000000..8f5779e04
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_doe_scan/caliptra_isr.h
@@ -0,0 +1,247 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// ---------------------------------------------------------------------
+// File: caliptra_isr.h
+// Description:
+//     Provides function declarations for use by external test files, so
+//     that the ISR functionality may behave like a library.
+//     TODO:
+//     This header file includes inline function definitions for event and
+//     test specific interrupt service behavior, so it should be copied and
+//     modified for each test.
+// ---------------------------------------------------------------------
+
+#ifndef CALIPTRA_ISR_H
+    #define CALIPTRA_ISR_H
+
+#define EN_ISR_PRINTS 1
+
+#include "caliptra_defines.h"
+#include <stdint.h>
+#include "printf.h"
+
+/* --------------- symbols/typedefs --------------- */
+typedef struct {
+    uint32_t doe_error;
+    uint32_t doe_notif;
+    uint32_t ecc_error;
+    uint32_t ecc_notif;
+    uint32_t hmac_error;
+    uint32_t hmac_notif;
+    uint32_t kv_error;
+    uint32_t kv_notif;
+    uint32_t sha512_error;
+    uint32_t sha512_notif;
+    uint32_t sha256_error;
+    uint32_t sha256_notif;
+    uint32_t qspi_error;
+    uint32_t qspi_notif;
+    uint32_t uart_error;
+    uint32_t uart_notif;
+    uint32_t i3c_error;
+    uint32_t i3c_notif;
+    uint32_t soc_ifc_error;
+    uint32_t soc_ifc_notif;
+    uint32_t sha512_acc_error;
+    uint32_t sha512_acc_notif;
+} caliptra_intr_received_s;
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
+
+//////////////////////////////////////////////////////////////////////////////
+// Function Declarations
+//
+
+// Performs all the CSR setup to configure and enable vectored external interrupts
+void init_interrupts(void);
+
+// These inline functions are used to insert event-specific functionality into the
+// otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr"
+inline void service_doe_error_intr() {return;}
+inline void service_doe_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.doe_notif |= DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad doe_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_ecc_error_intr() {return;}
+inline void service_ecc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.ecc_notif |= ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad ecc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_hmac_error_intr() {return;}
+inline void service_hmac_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.hmac_notif |= HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad hmac_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_kv_error_intr() {return;}
+inline void service_kv_notif_intr() {return;}
+inline void service_sha512_error_intr() {return;}
+inline void service_sha512_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_notif |= SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha256_error_intr() {return;}
+inline void service_sha256_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha256_notif |= SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha256_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_qspi_error_intr() {return;}
+inline void service_qspi_notif_intr() {return;}
+inline void service_uart_error_intr() {return;}
+inline void service_uart_notif_intr() {return;}
+inline void service_i3c_error_intr() {return;}
+inline void service_i3c_notif_intr() {return;}
+
+inline void service_soc_ifc_error_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_error_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_soc_ifc_notif_intr () {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha512_acc_error_intr() {return;}
+inline void service_sha512_acc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_acc_notif |= SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_acc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+
+#endif //CALIPTRA_ISR_H
diff --git a/src/integration/test_suites/smoke_test_doe_scan/smoke_test_doe_scan.c b/src/integration/test_suites/smoke_test_doe_scan/smoke_test_doe_scan.c
new file mode 100644
index 000000000..d2966ca31
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_doe_scan/smoke_test_doe_scan.c
@@ -0,0 +1,201 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+
+#include "caliptra_defines.h"
+#include "caliptra_isr.h"
+#include "riscv-csr.h"
+#include <string.h>
+#include <stdint.h>
+#include "printf.h"
+#include "clk_gate.h"
+
+volatile char*    stdout           = (char *)STDOUT;
+volatile uint32_t intr_count = 0;
+volatile uint32_t rst_count __attribute__((section(".dccm.persistent"))) = 0;
+#ifdef CPT_VERBOSITY
+    enum printf_verbosity verbosity_g = CPT_VERBOSITY;
+#else
+    enum printf_verbosity verbosity_g = LOW;
+#endif
+
+uint32_t IV_DATA_UDS0 = 0x2eb94297;
+uint32_t IV_DATA_UDS1 = 0x77285196;
+uint32_t IV_DATA_UDS2 = 0x3dd39a1e;
+uint32_t IV_DATA_UDS3 = 0xb95d438f;
+
+volatile uint32_t * doe_iv_0 = (uint32_t *) CLP_DOE_REG_DOE_IV_0;
+volatile uint32_t * doe_iv_1 = (uint32_t *) CLP_DOE_REG_DOE_IV_1;
+volatile uint32_t * doe_iv_2 = (uint32_t *) CLP_DOE_REG_DOE_IV_2;
+volatile uint32_t * doe_iv_3 = (uint32_t *) CLP_DOE_REG_DOE_IV_3;
+
+volatile uint32_t * doe_ctrl = (uint32_t *) CLP_DOE_REG_DOE_CTRL;
+volatile uint32_t * doe_status = (uint32_t *) CLP_DOE_REG_DOE_STATUS;
+
+volatile uint32_t * soc_ifc_fw_update_reset = (uint32_t *) (CLP_SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET);
+
+volatile uint32_t * pcr_ctrl0 = (uint32_t *) CLP_PV_REG_PCR_CTRL_0;
+volatile uint32_t * pcr_ctrl2 = (uint32_t *) CLP_PV_REG_PCR_CTRL_2;
+volatile uint32_t * pcr_ctrl5 = (uint32_t *) CLP_PV_REG_PCR_CTRL_5;
+
+volatile uint32_t * key_ctrl1 = (uint32_t *) CLP_KV_REG_KEY_CTRL_1;
+volatile uint32_t * key_ctrl4 = (uint32_t *) CLP_KV_REG_KEY_CTRL_4;
+volatile uint32_t * key_ctrl7 = (uint32_t *) CLP_KV_REG_KEY_CTRL_7;
+
+volatile uint32_t doe_status_int;
+
+volatile caliptra_intr_received_s cptra_intr_rcv = {
+    .doe_error        = 0,
+    .doe_notif        = 0,
+    .ecc_error        = 0,
+    .ecc_notif        = 0,
+    .hmac_error       = 0,
+    .hmac_notif       = 0,
+    .kv_error         = 0,
+    .kv_notif         = 0,
+    .sha512_error     = 0,
+    .sha512_notif     = 0,
+    .sha256_error     = 0,
+    .sha256_notif     = 0,
+    .qspi_error       = 0,
+    .qspi_notif       = 0,
+    .uart_error       = 0,
+    .uart_notif       = 0,
+    .i3c_error        = 0,
+    .i3c_notif        = 0,
+    .soc_ifc_error    = 0,
+    .soc_ifc_notif    = 0,
+    .sha512_acc_error = 0,
+    .sha512_acc_notif = 0,
+};
+
+void main() {
+
+    rst_count++;
+
+    VPRINTF(LOW,"---------------------------\n");
+    VPRINTF(LOW," DOE Smoke Test With Rand UDS/FE !!\n");
+    VPRINTF(LOW,"---------------------------\n");
+
+    //Call interrupt init
+    init_interrupts();
+
+    if (rst_count == 1) {
+    
+    //VPRINTF(LOW,"Rand UDS\n");
+    printf("Rand UDS\n");
+
+    //Start UDS and store in KV3
+    SEND_STDOUT_CTRL(0xec);
+    *doe_ctrl = 0x0000000D;
+
+    // //Poll for DOE status
+    while(doe_status_int != (DOE_REG_DOE_STATUS_VALID_MASK | DOE_REG_DOE_STATUS_READY_MASK)) {
+        doe_status_int = *doe_status;
+        doe_status_int = doe_status_int & (DOE_REG_DOE_STATUS_VALID_MASK | DOE_REG_DOE_STATUS_READY_MASK) ;
+    }
+
+    //Clear doe_status_int
+    doe_status_int = 0;
+
+    //Start FE and store in KV15
+    SEND_STDOUT_CTRL(0xed);
+    *doe_ctrl = 0x00000062; //30;
+
+    // //Poll for DOE status
+    while(doe_status_int != (DOE_REG_DOE_STATUS_VALID_MASK | DOE_REG_DOE_STATUS_READY_MASK)) {
+        doe_status_int = *doe_status;
+        doe_status_int = doe_status_int & (DOE_REG_DOE_STATUS_VALID_MASK | DOE_REG_DOE_STATUS_READY_MASK) ;
+    }
+
+    //Clear doe_status_int
+    doe_status_int = 0;
+
+    //Issue cold reset - to clear lock_uds/fe so we can test other things
+    SEND_STDOUT_CTRL(0xf5);
+    }
+    else if (rst_count == 2) {
+        //-----------------------------------
+        //UDS flow with scan and debug modes
+
+        SEND_STDOUT_CTRL(0xec); //Generate rand UDS vector
+        SEND_STDOUT_CTRL(0xef); //Enable scan mode after a delay
+        *doe_ctrl = 0x0000000D; //Start UDS flow
+
+        // //Poll for DOE status
+        while(doe_status_int != (DOE_REG_DOE_STATUS_VALID_MASK | DOE_REG_DOE_STATUS_READY_MASK)) {
+            doe_status_int = *doe_status;
+            doe_status_int = doe_status_int & (DOE_REG_DOE_STATUS_VALID_MASK | DOE_REG_DOE_STATUS_READY_MASK) ;
+        }
+
+        //Clear doe_status_int
+        doe_status_int = 0;
+
+        SEND_STDOUT_CTRL(0xf0); //Disable scan mode
+
+        //Issue cold reset
+        SEND_STDOUT_CTRL(0xf5);
+    }
+    else if (rst_count == 3) {
+        SEND_STDOUT_CTRL(0xed); //Generate rand FE vector
+        SEND_STDOUT_CTRL(0xfa); //Debug mode unlocked
+        *doe_ctrl = 0x00000062; //Start FE flow
+
+        // //Poll for DOE status
+        while(doe_status_int != (DOE_REG_DOE_STATUS_VALID_MASK | DOE_REG_DOE_STATUS_READY_MASK)) {
+            doe_status_int = *doe_status;
+            doe_status_int = doe_status_int & (DOE_REG_DOE_STATUS_VALID_MASK | DOE_REG_DOE_STATUS_READY_MASK) ;
+        }
+
+        //Clear doe_status_int
+        doe_status_int = 0;
+
+        SEND_STDOUT_CTRL(0xf9); //Debug mode locked
+
+        //Issue cold reset
+        SEND_STDOUT_CTRL(0xf5);
+    }
+    else if (rst_count == 4) {
+        SEND_STDOUT_CTRL(0xed); //Generate rand FE vector
+        *doe_ctrl = 0x00000062; //Start FE flow
+
+        // //Poll for DOE status
+        while(doe_status_int != (DOE_REG_DOE_STATUS_VALID_MASK | DOE_REG_DOE_STATUS_READY_MASK)) {
+            doe_status_int = *doe_status;
+            doe_status_int = doe_status_int & (DOE_REG_DOE_STATUS_VALID_MASK | DOE_REG_DOE_STATUS_READY_MASK) ;
+        }
+
+        //Clear doe_status_int
+        doe_status_int = 0;
+
+        //-----------------------------------
+        //UDS flow with scan and debug modes
+
+        SEND_STDOUT_CTRL(0xec); //Generate rand UDS vector
+        SEND_STDOUT_CTRL(0xe8); //Enable scan mode when DOE fsm goes to DONE
+        *doe_ctrl = 0x0000000D; //Start UDS flow
+
+        // //Poll for DOE status
+        while(doe_status_int != (DOE_REG_DOE_STATUS_VALID_MASK | DOE_REG_DOE_STATUS_READY_MASK)) {
+            doe_status_int = *doe_status;
+            doe_status_int = doe_status_int & (DOE_REG_DOE_STATUS_VALID_MASK | DOE_REG_DOE_STATUS_READY_MASK) ;
+        }
+
+        //Clear doe_status_int
+        doe_status_int = 0;
+
+        SEND_STDOUT_CTRL(0xf0); //Disable scan mode
+
+    }
+}
diff --git a/src/integration/test_suites/smoke_test_doe_scan/smoke_test_doe_scan.yml b/src/integration/test_suites/smoke_test_doe_scan/smoke_test_doe_scan.yml
new file mode 100644
index 000000000..9dc21a5d7
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_doe_scan/smoke_test_doe_scan.yml
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+---
+plusargs:
+  - +RAND_DOE_VALUES
+seed: 1
+testname: smoke_test_doe_scan
\ No newline at end of file
diff --git a/src/integration/test_suites/smoke_test_ecc/caliptra_isr.h b/src/integration/test_suites/smoke_test_ecc/caliptra_isr.h
index 6ffd71c0a..8f5779e04 100644
--- a/src/integration/test_suites/smoke_test_ecc/caliptra_isr.h
+++ b/src/integration/test_suites/smoke_test_ecc/caliptra_isr.h
@@ -204,6 +204,22 @@ inline void service_soc_ifc_notif_intr () {
         *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
         cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
     }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
     if (sts == 0) {
         VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
         SEND_STDOUT_CTRL(0x1);
diff --git a/src/integration/test_suites/smoke_test_ecc_errortrigger/caliptra_isr.h b/src/integration/test_suites/smoke_test_ecc_errortrigger/caliptra_isr.h
new file mode 100644
index 000000000..d5a7efebb
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_ecc_errortrigger/caliptra_isr.h
@@ -0,0 +1,256 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// ---------------------------------------------------------------------
+// File: caliptra_isr.h
+// Description:
+//     Provides function declarations for use by external test files, so
+//     that the ISR functionality may behave like a library.
+//     TODO:
+//     This header file includes inline function definitions for event and
+//     test specific interrupt service behavior, so it should be copied and
+//     modified for each test.
+// ---------------------------------------------------------------------
+
+#ifndef CALIPTRA_ISR_H
+    #define CALIPTRA_ISR_H
+
+#define EN_ISR_PRINTS 1
+
+#include "caliptra_defines.h"
+#include <stdint.h>
+#include "printf.h"
+
+/* --------------- symbols/typedefs --------------- */
+typedef struct {
+    uint32_t doe_error;
+    uint32_t doe_notif;
+    uint32_t ecc_error;
+    uint32_t ecc_notif;
+    uint32_t hmac_error;
+    uint32_t hmac_notif;
+    uint32_t kv_error;
+    uint32_t kv_notif;
+    uint32_t sha512_error;
+    uint32_t sha512_notif;
+    uint32_t sha256_error;
+    uint32_t sha256_notif;
+    uint32_t qspi_error;
+    uint32_t qspi_notif;
+    uint32_t uart_error;
+    uint32_t uart_notif;
+    uint32_t i3c_error;
+    uint32_t i3c_notif;
+    uint32_t soc_ifc_error;
+    uint32_t soc_ifc_notif;
+    uint32_t sha512_acc_error;
+    uint32_t sha512_acc_notif;
+} caliptra_intr_received_s;
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
+
+//////////////////////////////////////////////////////////////////////////////
+// Function Declarations
+//
+
+// Performs all the CSR setup to configure and enable vectored external interrupts
+void init_interrupts(void);
+
+// These inline functions are used to insert event-specific functionality into the
+// otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr"
+inline void service_doe_error_intr() {return;}
+inline void service_doe_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.doe_notif |= DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad doe_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_ecc_error_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
+        *reg = ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+        cptra_intr_rcv.ecc_error |= ECC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad ecc_error_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+inline void service_ecc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.ecc_notif |= ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad ecc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_hmac_error_intr() {return;}
+inline void service_hmac_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.hmac_notif |= HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad hmac_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_kv_error_intr() {return;}
+inline void service_kv_notif_intr() {return;}
+inline void service_sha512_error_intr() {return;}
+inline void service_sha512_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_notif |= SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha256_error_intr() {return;}
+inline void service_sha256_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha256_notif |= SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha256_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_qspi_error_intr() {return;}
+inline void service_qspi_notif_intr() {return;}
+inline void service_uart_error_intr() {return;}
+inline void service_uart_notif_intr() {return;}
+inline void service_i3c_error_intr() {return;}
+inline void service_i3c_notif_intr() {return;}
+
+inline void service_soc_ifc_error_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_error_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_soc_ifc_notif_intr () {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha512_acc_error_intr() {return;}
+inline void service_sha512_acc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_acc_notif |= SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_acc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+
+#endif //CALIPTRA_ISR_H
diff --git a/src/integration/test_suites/smoke_test_ecc_errortrigger/smoke_test_ecc_errortrigger.c b/src/integration/test_suites/smoke_test_ecc_errortrigger/smoke_test_ecc_errortrigger.c
new file mode 100644
index 000000000..d6d358ca7
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_ecc_errortrigger/smoke_test_ecc_errortrigger.c
@@ -0,0 +1,572 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+
+#include "caliptra_defines.h"
+#include "caliptra_isr.h"
+#include "riscv_hw_if.h"
+#include "riscv-csr.h"
+#include "printf.h"
+#include "ecc.h"
+
+volatile char*    stdout           = (char *)STDOUT;
+volatile uint32_t intr_count = 0;
+volatile uint32_t rst_count __attribute__((section(".dccm.persistent"))) = 0;
+#ifdef CPT_VERBOSITY
+    enum printf_verbosity verbosity_g = CPT_VERBOSITY;
+#else
+    enum printf_verbosity verbosity_g = LOW;
+#endif
+
+volatile caliptra_intr_received_s cptra_intr_rcv = {
+    .doe_error        = 0,
+    .doe_notif        = 0,
+    .ecc_error        = 0,
+    .ecc_notif        = 0,
+    .hmac_error       = 0,
+    .hmac_notif       = 0,
+    .kv_error         = 0,
+    .kv_notif         = 0,
+    .sha512_error     = 0,
+    .sha512_notif     = 0,
+    .sha256_error     = 0,
+    .sha256_notif     = 0,
+    .qspi_error       = 0,
+    .qspi_notif       = 0,
+    .uart_error       = 0,
+    .uart_notif       = 0,
+    .i3c_error        = 0,
+    .i3c_notif        = 0,
+    .soc_ifc_error    = 0,
+    .soc_ifc_notif    = 0,
+    .sha512_acc_error = 0,
+    .sha512_acc_notif = 0,
+};
+
+/* ECC test vector:
+    MSG      = C8F518D4F3AA1BD46ED56C1C3C9E16FB800AF504DB98843548C5F623EE115F73D4C62ABC06D303B5D90D9A175087290D
+    PRIVKEY  = F274F69D163B0C9F1FC3EBF4292AD1C4EB3CEC1C5A7DDE6F80C14292934C2055E087748D0A169C772483ADEE5EE70E17
+    PUBKEY_X = D79C6D972B34A1DFC916A7B6E0A99B6B5387B34DA2187607C1AD0A4D1A8C2E4172AB5FA5D9AB58FE45E43F56BBB66BA4
+    PUBKEY_Y = 5A7363932B06B4F223BEF0B60A6390265112DBBD0AAE67FEF26B465BE935B48E451E68D16F1118F2B32B4C28608749ED
+    SEED     = 8FA8541C82A392CA74F23ED1DBFD73541C5966391B97EA73D744B0E34B9DF59ED0158063E39C09A5A055371EDF7A5441
+    NONCE    = 1B7EC5E548E8AAA92EC77097CA9551C9783CE682CA18FB1EDBD9F1E50BC382DB8AB39496C8EE423F8CA105CBBA7B6588
+    Sign_R   = 871E6EA4DDC5432CDDAA60FD7F055472D3C4DD41A5BFB26709E88C311A97093599A7C8F55B3974C19E4F5A7BFC1DD2AC
+    SIGN_S   = 3E5552DE6403350EE70AD74E4B854D2DC4126BBF9C153A5D7A07BD4B85D06E45F850920E898FB7D34F80796DAE29365C
+    IV       = 3401CEFAE20A737649073AC1A351E32926DB9ED0DB6B1CFFAB0493DAAFB93DDDD83EDEA28A803D0D003B2633B9D0F1BF
+*/
+
+void main() {
+    printf("----------------------------------------\n");
+    printf(" Running ECC Smoke Test error_trigger !!\n");
+    printf("----------------------------------------\n");
+
+    uint32_t ecc_msg[] =           {0xC8F518D4,
+                                    0xF3AA1BD4,
+                                    0x6ED56C1C,
+                                    0x3C9E16FB,
+                                    0x800AF504,
+                                    0xDB988435,
+                                    0x48C5F623,
+                                    0xEE115F73,
+                                    0xD4C62ABC,
+                                    0x06D303B5,
+                                    0xD90D9A17,
+                                    0x5087290D};
+    
+    uint32_t ecc_privkey[] =       {0xF274F69D,
+                                    0x163B0C9F,
+                                    0x1FC3EBF4,
+                                    0x292AD1C4,
+                                    0xEB3CEC1C,
+                                    0x5A7DDE6F,
+                                    0x80C14292,
+                                    0x934C2055,
+                                    0xE087748D,
+                                    0x0A169C77,
+                                    0x2483ADEE,
+                                    0x5EE70E17};
+
+    uint32_t ecc_pubkey_x[] =      {0xD79C6D97,
+                                    0x2B34A1DF,
+                                    0xC916A7B6,
+                                    0xE0A99B6B,
+                                    0x5387B34D,
+                                    0xA2187607,
+                                    0xC1AD0A4D,
+                                    0x1A8C2E41,
+                                    0x72AB5FA5,
+                                    0xD9AB58FE,
+                                    0x45E43F56,
+                                    0xBBB66BA4};
+
+    uint32_t ecc_pubkey_y[] =      {0x5A736393,
+                                    0x2B06B4F2,
+                                    0x23BEF0B6,
+                                    0x0A639026,
+                                    0x5112DBBD,
+                                    0x0AAE67FE,
+                                    0xF26B465B,
+                                    0xE935B48E,
+                                    0x451E68D1,
+                                    0x6F1118F2,
+                                    0xB32B4C28,
+                                    0x608749ED};
+
+    uint32_t ecc_seed[] =          {0x8FA8541C,
+                                    0x82A392CA,
+                                    0x74F23ED1,
+                                    0xDBFD7354,
+                                    0x1C596639,
+                                    0x1B97EA73,
+                                    0xD744B0E3,
+                                    0x4B9DF59E,
+                                    0xD0158063,
+                                    0xE39C09A5,
+                                    0xA055371E,
+                                    0xDF7A5441};
+
+    uint32_t ecc_nonce[] =         {0x1B7EC5E5,
+                                    0x48E8AAA9,
+                                    0x2EC77097,
+                                    0xCA9551C9,
+                                    0x783CE682,
+                                    0xCA18FB1E,
+                                    0xDBD9F1E5,
+                                    0x0BC382DB,
+                                    0x8AB39496,
+                                    0xC8EE423F,
+                                    0x8CA105CB,
+                                    0xBA7B6588};
+
+    uint32_t ecc_sign_r[] =        {0x871E6EA4,
+                                    0xDDC5432C,
+                                    0xDDAA60FD,
+                                    0x7F055472,
+                                    0xD3C4DD41,
+                                    0xA5BFB267,
+                                    0x09E88C31,
+                                    0x1A970935,
+                                    0x99A7C8F5,
+                                    0x5B3974C1,
+                                    0x9E4F5A7B,
+                                    0xFC1DD2AC};
+
+    uint32_t ecc_sign_s[] =        {0x3E5552DE,
+                                    0x6403350E,
+                                    0xE70AD74E,
+                                    0x4B854D2D,
+                                    0xC4126BBF,
+                                    0x9C153A5D,
+                                    0x7A07BD4B,
+                                    0x85D06E45,
+                                    0xF850920E,
+                                    0x898FB7D3,
+                                    0x4F80796D,
+                                    0xAE29365C};
+
+    
+    uint32_t ecc_iv[] =            {0x3401CEFA,
+                                    0xE20A7376,
+                                    0x49073AC1,
+                                    0xA351E329,
+                                    0x26DB9ED0,
+                                    0xDB6B1CFF,
+                                    0xAB0493DA,
+                                    0xAFB93DDD,
+                                    0xD83EDEA2,
+                                    0x8A803D0D,
+                                    0x003B2633,
+                                    0xB9D0F1BF};
+
+    uint32_t value_greater_q[]=    {0xffffffff,
+                                    0xffffffff,
+                                    0xffffffff,
+                                    0xffffffff,
+                                    0xffffffff,
+                                    0xffffffff,
+                                    0xc7634d81,
+                                    0xf4372ddf,
+                                    0x5b1a0db2,  //0x581a0db2,
+                                    0x48b0a77a,
+                                    0xecec196a,
+                                    0xccc52973};
+
+    uint32_t value_greater_p[]=    {0xffffffff,
+                                    0xffffffff,
+                                    0xffffffff,
+                                    0xffffffff,
+                                    0xffffffff,
+                                    0xffffffff,
+                                    0xffffffff,
+                                    0xfffffffe,
+                                    0xffffffff,
+                                    0x0000c000,  //0x00000000
+                                    0x00000000,
+                                    0xffffffff};
+    //Call interrupt init
+    init_interrupts();
+
+    uint8_t offset;
+    volatile uint32_t * reg_ptr;
+    uint8_t privkey_inject_cmd;
+   
+
+    if(rst_count == 0) {
+        // wait for ECC to be ready
+        while((lsu_read_32(CLP_ECC_REG_ECC_STATUS) & ECC_REG_ECC_STATUS_READY_MASK) == 0);
+
+        printf("\n TEST OUT OF RANGE PRIVEKEY ZERO\n");
+        reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_PRIVKEY_IN_0;
+        while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_PRIVKEY_IN_11) {
+            *reg_ptr++ = 0;
+        }
+
+        // Enable ECC SIGNING core
+        printf("\nECC SIGNING\n");
+        lsu_write_32(CLP_ECC_REG_ECC_CTRL, ECC_CMD_SIGNING);
+        
+        // wait for ECC SIGNING process to be done
+        wait_for_ecc_intr();
+        if ((cptra_intr_rcv.ecc_error == 0)){
+            printf("\nECC privkey_input_outofrange 0 error is not detected.\n");
+            printf("%c", 0x1);
+            while(1);
+        }
+
+        ecc_zeroize();
+        //Issue warm reset
+        rst_count++;
+        printf("%c",0xf6);
+    }
+    else if(rst_count == 1) {
+        // wait for ECC to be ready
+        while((lsu_read_32(CLP_ECC_REG_ECC_STATUS) & ECC_REG_ECC_STATUS_READY_MASK) == 0);
+
+        printf("\n TEST OUT OF RANGE PRIVEKEY GREATER q\n");
+        reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_PRIVKEY_IN_0;
+        offset = 0;
+        while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_PRIVKEY_IN_11) {
+            *reg_ptr++ = value_greater_q[offset++];;
+        }
+
+        // Enable ECC SIGNING core
+        printf("\nECC SIGNING\n");
+        lsu_write_32(CLP_ECC_REG_ECC_CTRL, ECC_CMD_SIGNING);
+        
+        // wait for ECC SIGNING process to be done
+        wait_for_ecc_intr();
+        if ((cptra_intr_rcv.ecc_error == 0)){
+            printf("\nECC privkey_input_outofrange 1 error is not detected.\n");
+            printf("%c", 0x1);
+            while(1);
+        }
+
+        ecc_zeroize();
+        //Issue warm reset
+        rst_count++;
+        printf("%c",0xf6);
+    }  
+    else if(rst_count == 2) {
+        // wait for ECC to be ready
+        while((lsu_read_32(CLP_ECC_REG_ECC_STATUS) & ECC_REG_ECC_STATUS_READY_MASK) == 0);
+
+        printf("\n TEST OUT OF RANGE PUBKEY\n");
+        // Program ECC PUBKEY_X
+        reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_PUBKEY_X_0;
+        offset = 0;
+        while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_PUBKEY_X_11) {
+            *reg_ptr++ = value_greater_p[offset++];
+        }
+
+        // Program ECC PUBKEY_Y
+        reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_PUBKEY_Y_0;
+        offset = 0;
+        while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_PUBKEY_Y_11) {
+            *reg_ptr++ = value_greater_p[offset++];
+        }
+
+        // Enable ECC VERIFYING core
+        printf("\nECC VERIFYING\n");
+        lsu_write_32(CLP_ECC_REG_ECC_CTRL, ECC_CMD_VERIFYING);
+        
+        // wait for ECC SIGNING process to be done
+        wait_for_ecc_intr();
+        if ((cptra_intr_rcv.ecc_error == 0)){
+            printf("\nECC pubkey_input_outofrange error is not detected.\n");
+            printf("%c", 0x1);
+            while(1);
+        }
+
+        ecc_zeroize();
+        //Issue warm reset
+        rst_count++;
+        printf("%c",0xf6);
+    }  
+    else if(rst_count == 3) {
+        // wait for ECC to be ready
+        while((lsu_read_32(CLP_ECC_REG_ECC_STATUS) & ECC_REG_ECC_STATUS_READY_MASK) == 0);
+
+        printf("\n TEST INVALID PUBKEY\n");
+        // Program ECC PUBKEY_X
+        reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_PUBKEY_X_0;
+        offset = 0;
+        while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_PUBKEY_X_11) {
+            *reg_ptr++ = ecc_pubkey_y[offset++];
+        }
+
+        // Program ECC PUBKEY_Y
+        reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_PUBKEY_Y_0;
+        offset = 0;
+        while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_PUBKEY_Y_11) {
+            *reg_ptr++ = ecc_pubkey_x[offset++];
+        }
+
+        // Program ECC SIGN_R
+        reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_SIGN_R_0;
+        offset = 0;
+        while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_SIGN_R_11) {
+            *reg_ptr++ = ecc_sign_r[offset++];
+        }
+
+        // Program ECC SIGN_S
+        reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_SIGN_S_0;
+        offset = 0;
+        while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_SIGN_S_11) {
+            *reg_ptr++ = ecc_sign_s[offset++];
+        }
+
+        // Enable ECC VERIFYING core
+        printf("\nECC VERIFYING\n");
+        lsu_write_32(CLP_ECC_REG_ECC_CTRL, ECC_CMD_VERIFYING);
+        
+        // wait for ECC SIGNING process to be done
+        wait_for_ecc_intr();
+        if ((cptra_intr_rcv.ecc_error == 0)){
+            printf("\nECC pubkey_input_invalid error is not detected.\n");
+            printf("%c", 0x1);
+            while(1);
+        }
+
+        ecc_zeroize();
+        //Issue warm reset
+        rst_count++;
+        printf("%c",0xf6);
+    }   
+    else if(rst_count == 4) {
+        // wait for ECC to be ready
+        while((lsu_read_32(CLP_ECC_REG_ECC_STATUS) & ECC_REG_ECC_STATUS_READY_MASK) == 0);
+
+        printf("\n TEST INVALID OUTPUT SIGN_R\n");
+        // Program ECC PRIVKEY
+        reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_PRIVKEY_IN_0;
+        offset = 0;
+        while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_PRIVKEY_IN_11) {
+            *reg_ptr++ = ecc_privkey[offset++];
+        }
+
+        // Program ECC MSG
+        reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_MSG_0;
+        offset = 0;
+        while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_MSG_11) {
+            *reg_ptr++ = ecc_msg[offset++];
+        }
+
+        // Program ECC IV
+        reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_IV_0;
+        offset = 0;
+        while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_IV_11) {
+            *reg_ptr++ = ecc_iv[offset++];
+        }
+
+        //Inject invalid zero sign_r
+        printf("%c",0x98);
+
+        // Enable ECC SIGNING core
+        printf("\nECC SIGNING\n");
+        lsu_write_32(CLP_ECC_REG_ECC_CTRL, ECC_CMD_SIGNING);
+        
+        // wait for ECC SIGNING process to be done
+        wait_for_ecc_intr();
+        if ((cptra_intr_rcv.ecc_error == 0)){
+            printf("\nECC r_output_outofrange error is not detected.\n");
+            printf("%c", 0x1);
+            while(1);
+        }
+
+        ecc_zeroize();
+        //Issue warm reset
+        rst_count++;
+        printf("%c",0xf6);
+    }   
+    else if(rst_count == 5) {
+        // wait for ECC to be ready
+        while((lsu_read_32(CLP_ECC_REG_ECC_STATUS) & ECC_REG_ECC_STATUS_READY_MASK) == 0);
+
+        printf("\n TEST OUT OF RANGE INPUT R/S\n");
+        // Program ECC SIGN_R
+        reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_SIGN_R_0;
+        offset = 0;
+        while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_SIGN_R_11) {
+            *reg_ptr++ = value_greater_q[offset++];
+        }
+
+        // Program ECC SIGN_S
+        reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_SIGN_S_0;
+        while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_SIGN_S_11) {
+            *reg_ptr++ = 0;
+        }
+
+        // Enable ECC VERIFYING core
+        printf("\nECC VERIFYING\n");
+        lsu_write_32(CLP_ECC_REG_ECC_CTRL, ECC_CMD_VERIFYING);
+        
+        // wait for ECC SIGNING process to be done
+        wait_for_ecc_intr();
+        if ((cptra_intr_rcv.ecc_error == 0)){
+            printf("\nECC r/s_input_outofrange error is not detected.\n");
+            printf("%c", 0x1);
+            while(1);
+        }
+
+        ecc_zeroize();
+        //Issue warm reset
+        rst_count++;
+        printf("%c",0xf6);
+    }   
+    else if(rst_count == 6) {
+        // wait for ECC to be ready
+        while((lsu_read_32(CLP_ECC_REG_ECC_STATUS) & ECC_REG_ECC_STATUS_READY_MASK) == 0);
+
+        printf("\n TEST PCR WITH INVALID OUTPUT SIGN_R\n");
+        
+        // Program ECC IV
+        reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_IV_0;
+        offset = 0;
+        while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_IV_11) {
+            *reg_ptr++ = ecc_iv[offset++];
+        }
+
+        //Inject invalid zero sign_r
+        printf("%c",0x98);
+
+        //inject seed to kv key reg (in RTL)
+        printf("Inject PRIVKEY into KV slot 7\n");
+        privkey_inject_cmd = 0x88 + 0x7;
+        printf("%c", privkey_inject_cmd);
+
+        printf("Inject MSG into SHA512 digest\n");
+        printf("%c", 0x90);
+
+        // Enable ECC PCR SIGNING core
+        printf("\nECC PCR SIGNING\n");
+        lsu_write_32(CLP_ECC_REG_ECC_CTRL, ECC_CMD_SIGNING | 
+                ((1 << ECC_REG_ECC_CTRL_PCR_SIGN_LOW) & ECC_REG_ECC_CTRL_PCR_SIGN_MASK));
+    
+        
+        // wait for ECC PCR SIGNING process to be done
+        wait_for_ecc_intr();
+        if ((cptra_intr_rcv.ecc_error == 0)){
+            printf("\nECC PCR r_output_outofrange error is not detected.\n");
+            printf("%c", 0x1);
+            while(1);
+        }
+
+        ecc_zeroize();
+        //Issue warm reset
+        rst_count++;
+        printf("%c",0xf6);
+    }  
+    else if(rst_count == 7) {
+        // wait for ECC to be ready
+        while((lsu_read_32(CLP_ECC_REG_ECC_STATUS) & ECC_REG_ECC_STATUS_READY_MASK) == 0);
+
+        printf("\n TEST PCR WITH INVALID INPUT COMMAND\n");
+        
+        // Program ECC IV
+        reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_IV_0;
+        offset = 0;
+        while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_IV_11) {
+            *reg_ptr++ = ecc_iv[offset++];
+        }
+
+        //inject seed to kv key reg (in RTL)
+        printf("Inject PRIVKEY into KV slot 7\n");
+        privkey_inject_cmd = 0x88 + 0x7;
+        printf("%c", privkey_inject_cmd);
+
+        printf("Inject MSG into SHA512 digest\n");
+        printf("%c", 0x90);
+
+        // Enable ECC PCR KEYGEN core
+        printf("\nECC PCR KEYGEN\n");
+        lsu_write_32(CLP_ECC_REG_ECC_CTRL, ECC_CMD_KEYGEN | 
+                ((1 << ECC_REG_ECC_CTRL_PCR_SIGN_LOW) & ECC_REG_ECC_CTRL_PCR_SIGN_MASK));
+    
+        
+        // wait for ECC KEYGEN process to be done
+        wait_for_ecc_intr();
+        if ((cptra_intr_rcv.ecc_error == 0)){
+            printf("\nECC PCR invalid command error is not detected.\n");
+            printf("%c", 0x1);
+            while(1);
+        }
+
+        ecc_zeroize();
+        //Issue warm reset
+        rst_count++;
+        printf("%c",0xf6);
+    }
+    else if(rst_count == 8) {
+        // wait for ECC to be ready
+        while((lsu_read_32(CLP_ECC_REG_ECC_STATUS) & ECC_REG_ECC_STATUS_READY_MASK) == 0);
+
+        printf("\n TEST PCR WITH INVALID INPUT COMMAND\n");
+        
+        // Program ECC IV
+        reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_IV_0;
+        offset = 0;
+        while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_IV_11) {
+            *reg_ptr++ = ecc_iv[offset++];
+        }
+
+        //inject seed to kv key reg (in RTL)
+        printf("Inject PRIVKEY into KV slot 7\n");
+        privkey_inject_cmd = 0x88 + 0x7;
+        printf("%c", privkey_inject_cmd);
+
+        printf("Inject MSG into SHA512 digest\n");
+        printf("%c", 0x90);
+
+        // Enable ECC PCR VERIFYING core
+        printf("\nECC PCR VERIFYING\n");
+        lsu_write_32(CLP_ECC_REG_ECC_CTRL, ECC_CMD_VERIFYING | 
+                ((1 << ECC_REG_ECC_CTRL_PCR_SIGN_LOW) & ECC_REG_ECC_CTRL_PCR_SIGN_MASK));
+    
+        
+        // wait for ECC VERIFYING process to be done
+        wait_for_ecc_intr();
+        if ((cptra_intr_rcv.ecc_error == 0)){
+            printf("\nECC PCR invalid command error is not detected.\n");
+            printf("%c", 0x1);
+            while(1);
+        }
+
+        ecc_zeroize();
+    }        
+    
+    printf("%c",0xff); //End the test
+    
+}
+
+
diff --git a/src/integration/test_suites/smoke_test_ecc_errortrigger/smoke_test_ecc_errortrigger.yml b/src/integration/test_suites/smoke_test_ecc_errortrigger/smoke_test_ecc_errortrigger.yml
new file mode 100644
index 000000000..f3f9a3a52
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_ecc_errortrigger/smoke_test_ecc_errortrigger.yml
@@ -0,0 +1,3 @@
+---
+seed: 1
+testname: smoke_test_ecc_errortrigger
\ No newline at end of file
diff --git a/src/integration/test_suites/smoke_test_fw_kv_backtoback_hmac/caliptra_isr.h b/src/integration/test_suites/smoke_test_fw_kv_backtoback_hmac/caliptra_isr.h
new file mode 100644
index 000000000..8f5779e04
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_fw_kv_backtoback_hmac/caliptra_isr.h
@@ -0,0 +1,247 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// ---------------------------------------------------------------------
+// File: caliptra_isr.h
+// Description:
+//     Provides function declarations for use by external test files, so
+//     that the ISR functionality may behave like a library.
+//     TODO:
+//     This header file includes inline function definitions for event and
+//     test specific interrupt service behavior, so it should be copied and
+//     modified for each test.
+// ---------------------------------------------------------------------
+
+#ifndef CALIPTRA_ISR_H
+    #define CALIPTRA_ISR_H
+
+#define EN_ISR_PRINTS 1
+
+#include "caliptra_defines.h"
+#include <stdint.h>
+#include "printf.h"
+
+/* --------------- symbols/typedefs --------------- */
+typedef struct {
+    uint32_t doe_error;
+    uint32_t doe_notif;
+    uint32_t ecc_error;
+    uint32_t ecc_notif;
+    uint32_t hmac_error;
+    uint32_t hmac_notif;
+    uint32_t kv_error;
+    uint32_t kv_notif;
+    uint32_t sha512_error;
+    uint32_t sha512_notif;
+    uint32_t sha256_error;
+    uint32_t sha256_notif;
+    uint32_t qspi_error;
+    uint32_t qspi_notif;
+    uint32_t uart_error;
+    uint32_t uart_notif;
+    uint32_t i3c_error;
+    uint32_t i3c_notif;
+    uint32_t soc_ifc_error;
+    uint32_t soc_ifc_notif;
+    uint32_t sha512_acc_error;
+    uint32_t sha512_acc_notif;
+} caliptra_intr_received_s;
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
+
+//////////////////////////////////////////////////////////////////////////////
+// Function Declarations
+//
+
+// Performs all the CSR setup to configure and enable vectored external interrupts
+void init_interrupts(void);
+
+// These inline functions are used to insert event-specific functionality into the
+// otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr"
+inline void service_doe_error_intr() {return;}
+inline void service_doe_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.doe_notif |= DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad doe_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_ecc_error_intr() {return;}
+inline void service_ecc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.ecc_notif |= ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad ecc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_hmac_error_intr() {return;}
+inline void service_hmac_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.hmac_notif |= HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad hmac_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_kv_error_intr() {return;}
+inline void service_kv_notif_intr() {return;}
+inline void service_sha512_error_intr() {return;}
+inline void service_sha512_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_notif |= SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha256_error_intr() {return;}
+inline void service_sha256_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha256_notif |= SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha256_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_qspi_error_intr() {return;}
+inline void service_qspi_notif_intr() {return;}
+inline void service_uart_error_intr() {return;}
+inline void service_uart_notif_intr() {return;}
+inline void service_i3c_error_intr() {return;}
+inline void service_i3c_notif_intr() {return;}
+
+inline void service_soc_ifc_error_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_error_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_soc_ifc_notif_intr () {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha512_acc_error_intr() {return;}
+inline void service_sha512_acc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_acc_notif |= SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_acc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+
+#endif //CALIPTRA_ISR_H
diff --git a/src/integration/test_suites/smoke_test_fw_kv_backtoback_hmac/smoke_test_fw_kv_backtoback_hmac.c b/src/integration/test_suites/smoke_test_fw_kv_backtoback_hmac/smoke_test_fw_kv_backtoback_hmac.c
new file mode 100644
index 000000000..8b2cc5203
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_fw_kv_backtoback_hmac/smoke_test_fw_kv_backtoback_hmac.c
@@ -0,0 +1,221 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+
+#include "caliptra_defines.h"
+#include "caliptra_isr.h"
+#include "riscv_hw_if.h"
+#include "riscv-csr.h"
+#include <string.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include "printf.h"
+#include "hmac.h"
+
+volatile char*    stdout           = (char *)STDOUT;
+volatile uint32_t intr_count = 0;
+
+#ifdef CPT_VERBOSITY
+    enum printf_verbosity verbosity_g = CPT_VERBOSITY;
+#else
+    enum printf_verbosity verbosity_g = LOW;
+#endif
+
+volatile caliptra_intr_received_s cptra_intr_rcv = {
+    .doe_error        = 0,
+    .doe_notif        = 0,
+    .ecc_error        = 0,
+    .ecc_notif        = 0,
+    .hmac_error       = 0,
+    .hmac_notif       = 0,
+    .kv_error         = 0,
+    .kv_notif         = 0,
+    .sha512_error     = 0,
+    .sha512_notif     = 0,
+    .sha256_error     = 0,
+    .sha256_notif     = 0,
+    .qspi_error       = 0,
+    .qspi_notif       = 0,
+    .uart_error       = 0,
+    .uart_notif       = 0,
+    .i3c_error        = 0,
+    .i3c_notif        = 0,
+    .soc_ifc_error    = 0,
+    .soc_ifc_notif    = 0,
+    .sha512_acc_error = 0,
+    .sha512_acc_notif = 0,
+};
+
+
+/* HMAC384 test vector
+    KEY = 0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b
+    BLOCK = 4869205468657265800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000440
+    LFSR_SEED = C8F518D4F3AA1BD46ED56C1C3C9E16FB800AF504
+    TAG = b6a8d5636f5c6a7224f9977dcf7ee6c7fb6d0c48cbdee9737a959796489bddbc4c5df61d5b3297b4fb68dab9f1b582c2
+*/
+
+
+
+
+void main() {
+    printf("----------------------------------\n");
+    printf(" Smoke Test With FW HMAC after KV flow !!\n");
+    printf("----------------------------------\n");
+
+    //Call interrupt init
+    init_interrupts();
+
+    uint8_t offset;
+    volatile uint32_t * reg_ptr;
+
+    uint32_t block[32] =   {0x48692054,
+                            0x68657265,
+                            0x80000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000440};
+
+    //this is a random lfsr_seed 160-bit
+    uint32_t lfsr_seed_data[5] = {0xC8F518D4,
+                                 0xF3AA1BD4,
+                                 0x6ED56C1C,
+                                 0x3C9E16FB,
+                                 0x800AF504}; 
+
+    uint32_t expected_tag[12] =   {0xb6a8d563,
+                                    0x6f5c6a72,
+                                    0x24f9977d,
+                                    0xcf7ee6c7,
+                                    0xfb6d0c48,
+                                    0xcbdee973,
+                                    0x7a959796,
+                                    0x489bddbc,
+                                    0x4c5df61d,
+                                    0x5b3297b4,
+                                    0xfb68dab9,
+                                    0xf1b582c2}; 
+
+    uint32_t tag_zerokey_zeroblock[12] =   
+                                   {0x6E120BA2,
+                                    0x27BF3557,
+                                    0x676B0256,
+                                    0x136302D7,
+                                    0xD544B868,
+                                    0x080BED15,
+                                    0xF7D59AB1,
+                                    0x1185C79F,
+                                    0x44A39E4F,
+                                    0x440810F9,
+                                    0x7F419C17,
+                                    0xD6DB7E92}; 
+
+    uint8_t hmackey_kv_id       = 0x2;
+    uint8_t hmacblock_kv_id     = 0x1;
+    uint8_t store_to_kv         = 0x1;
+    uint8_t tag_kv_id           = 0x0;
+
+    hmac_io hmac_key;
+    hmac_io hmac_block;
+    hmac_io hmac_lfsr_seed;
+    hmac_io hmac_tag;
+
+    hmac_key.kv_intf = TRUE;
+    hmac_key.kv_id = hmackey_kv_id;
+
+    hmac_block.kv_intf = FALSE;
+    hmac_block.kv_id = hmacblock_kv_id;
+    hmac_block.data_size = 32;
+    for (int i = 0; i < hmac_block.data_size; i++)
+        hmac_block.data[i] = block[i];
+
+    hmac_lfsr_seed.kv_intf = FALSE;
+    hmac_lfsr_seed.data_size = 5;
+    for (int i = 0; i < hmac_lfsr_seed.data_size; i++)
+        hmac_lfsr_seed.data[i] = lfsr_seed_data[i];
+
+    hmac_tag.kv_intf = TRUE;
+    hmac_tag.kv_id = tag_kv_id;
+    hmac_tag.data_size = 12;
+    for (int i = 0; i < hmac_tag.data_size; i++)
+        hmac_tag.data[i] = expected_tag[i];
+
+
+    //inject hmac_key to kv key reg (in RTL)
+    uint8_t key_inject_cmd = 0xa0 + (hmac_key.kv_id & 0x7);
+    printf("%c", key_inject_cmd);
+
+    hmac_flow(hmac_key, hmac_block, hmac_lfsr_seed, hmac_tag);
+    
+    printf("KV HMAC flow is completed.\n\n");
+
+    /*
+        Start FW HMAC without injecting the key/block
+
+        The expected result is doing HMAC with zero key 
+        and zero block since all values should be cleared 
+        after KV flow.
+    */
+    printf("Start FW HMAC\n");
+    // Enable HMAC core with next command to avoid changing the key
+    lsu_write_32(CLP_HMAC_REG_HMAC384_CTRL, HMAC_REG_HMAC384_CTRL_NEXT_MASK);
+
+    // wait for HMAC process to be done
+    wait_for_hmac_intr();
+
+    printf("Load TAG from FW HMAC\n");
+    reg_ptr = (uint32_t *) CLP_HMAC_REG_HMAC384_TAG_0;
+    offset = 0;
+    while (reg_ptr <= (uint32_t*) CLP_HMAC_REG_HMAC384_TAG_11) {
+        if (tag_zerokey_zeroblock[offset] != *reg_ptr) {
+            printf("At offset [%d], hmac_tag data mismatch!\n", offset);
+            printf("Actual   data: 0x%x\n", *reg_ptr);
+            printf("Expected data: 0x%x\n", tag_zerokey_zeroblock[offset]);
+            printf("%c", 0x1); //fail_cmd
+            while(1);
+        }
+        reg_ptr++;
+        offset++;
+    }
+
+    hmac_zeroize();
+
+    printf("%c",0xff); //End the test
+    
+}
diff --git a/src/integration/test_suites/smoke_test_fw_kv_backtoback_hmac/smoke_test_fw_kv_backtoback_hmac.yml b/src/integration/test_suites/smoke_test_fw_kv_backtoback_hmac/smoke_test_fw_kv_backtoback_hmac.yml
new file mode 100644
index 000000000..09f5d5322
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_fw_kv_backtoback_hmac/smoke_test_fw_kv_backtoback_hmac.yml
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+---
+seed: 1
+testname: smoke_test_fw_kv_backtoback_hmac
\ No newline at end of file
diff --git a/src/integration/test_suites/smoke_test_hmac/caliptra_isr.h b/src/integration/test_suites/smoke_test_hmac/caliptra_isr.h
index 6ffd71c0a..8f5779e04 100644
--- a/src/integration/test_suites/smoke_test_hmac/caliptra_isr.h
+++ b/src/integration/test_suites/smoke_test_hmac/caliptra_isr.h
@@ -204,6 +204,22 @@ inline void service_soc_ifc_notif_intr () {
         *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
         cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
     }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
     if (sts == 0) {
         VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
         SEND_STDOUT_CTRL(0x1);
diff --git a/src/integration/test_suites/smoke_test_iccm_reset/caliptra_isr.h b/src/integration/test_suites/smoke_test_iccm_reset/caliptra_isr.h
new file mode 100644
index 000000000..8f5779e04
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_iccm_reset/caliptra_isr.h
@@ -0,0 +1,247 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// ---------------------------------------------------------------------
+// File: caliptra_isr.h
+// Description:
+//     Provides function declarations for use by external test files, so
+//     that the ISR functionality may behave like a library.
+//     TODO:
+//     This header file includes inline function definitions for event and
+//     test specific interrupt service behavior, so it should be copied and
+//     modified for each test.
+// ---------------------------------------------------------------------
+
+#ifndef CALIPTRA_ISR_H
+    #define CALIPTRA_ISR_H
+
+#define EN_ISR_PRINTS 1
+
+#include "caliptra_defines.h"
+#include <stdint.h>
+#include "printf.h"
+
+/* --------------- symbols/typedefs --------------- */
+typedef struct {
+    uint32_t doe_error;
+    uint32_t doe_notif;
+    uint32_t ecc_error;
+    uint32_t ecc_notif;
+    uint32_t hmac_error;
+    uint32_t hmac_notif;
+    uint32_t kv_error;
+    uint32_t kv_notif;
+    uint32_t sha512_error;
+    uint32_t sha512_notif;
+    uint32_t sha256_error;
+    uint32_t sha256_notif;
+    uint32_t qspi_error;
+    uint32_t qspi_notif;
+    uint32_t uart_error;
+    uint32_t uart_notif;
+    uint32_t i3c_error;
+    uint32_t i3c_notif;
+    uint32_t soc_ifc_error;
+    uint32_t soc_ifc_notif;
+    uint32_t sha512_acc_error;
+    uint32_t sha512_acc_notif;
+} caliptra_intr_received_s;
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
+
+//////////////////////////////////////////////////////////////////////////////
+// Function Declarations
+//
+
+// Performs all the CSR setup to configure and enable vectored external interrupts
+void init_interrupts(void);
+
+// These inline functions are used to insert event-specific functionality into the
+// otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr"
+inline void service_doe_error_intr() {return;}
+inline void service_doe_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.doe_notif |= DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad doe_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_ecc_error_intr() {return;}
+inline void service_ecc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.ecc_notif |= ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad ecc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_hmac_error_intr() {return;}
+inline void service_hmac_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.hmac_notif |= HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad hmac_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_kv_error_intr() {return;}
+inline void service_kv_notif_intr() {return;}
+inline void service_sha512_error_intr() {return;}
+inline void service_sha512_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_notif |= SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha256_error_intr() {return;}
+inline void service_sha256_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha256_notif |= SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha256_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_qspi_error_intr() {return;}
+inline void service_qspi_notif_intr() {return;}
+inline void service_uart_error_intr() {return;}
+inline void service_uart_notif_intr() {return;}
+inline void service_i3c_error_intr() {return;}
+inline void service_i3c_notif_intr() {return;}
+
+inline void service_soc_ifc_error_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_error_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_soc_ifc_notif_intr () {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha512_acc_error_intr() {return;}
+inline void service_sha512_acc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_acc_notif |= SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_acc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+
+#endif //CALIPTRA_ISR_H
diff --git a/src/integration/test_suites/smoke_test_iccm_reset/smoke_test_iccm_reset.c b/src/integration/test_suites/smoke_test_iccm_reset/smoke_test_iccm_reset.c
new file mode 100644
index 000000000..c1c3ef473
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_iccm_reset/smoke_test_iccm_reset.c
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+
+#include "caliptra_defines.h"
+#include "caliptra_isr.h"
+#include "riscv-csr.h"
+#include <string.h>
+#include <stdint.h>
+#include "printf.h"
+
+volatile char*    stdout           = (char *)STDOUT;
+volatile uint32_t intr_count = 0;
+volatile uint32_t rst_count __attribute__((section(".dccm.persistent"))) = 0;
+volatile uint32_t iter __attribute__((section(".dccm.persistent"))) = 0;
+#ifdef CPT_VERBOSITY
+    enum printf_verbosity verbosity_g = CPT_VERBOSITY;
+#else
+    enum printf_verbosity verbosity_g = LOW;
+#endif
+
+volatile caliptra_intr_received_s cptra_intr_rcv = {
+    .doe_error        = 0,
+    .doe_notif        = 0,
+    .ecc_error        = 0,
+    .ecc_notif        = 0,
+    .hmac_error       = 0,
+    .hmac_notif       = 0,
+    .kv_error         = 0,
+    .kv_notif         = 0,
+    .sha512_error     = 0,
+    .sha512_notif     = 0,
+    .sha256_error     = 0,
+    .sha256_notif     = 0,
+    .qspi_error       = 0,
+    .qspi_notif       = 0,
+    .uart_error       = 0,
+    .uart_notif       = 0,
+    .i3c_error        = 0,
+    .i3c_notif        = 0,
+    .soc_ifc_error    = 0,
+    .soc_ifc_notif    = 0,
+    .sha512_acc_error = 0,
+    .sha512_acc_notif = 0,
+};
+
+extern uintptr_t iccm_code0_start, iccm_code0_end;
+volatile uint32_t * soc_ifc_fw_update_reset = (uint32_t *) (CLP_SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET);
+void exec_iccm (void) __attribute__ ((aligned(4),section (".data_iccm0")));
+
+void main() {
+    uint32_t * ICCM = (uint32_t *) RV_ICCM_SADR;
+    uint32_t * code_word = 0;
+    uint32_t * iccm_dest = ICCM;
+    void (* iccm_fn) (void) = (void*) ICCM;
+    VPRINTF(LOW,"---------------------------\n");
+    VPRINTF(LOW," Smoke test ICCM/DCCM + reset !!\n");
+    VPRINTF(LOW,"---------------------------\n");
+
+    rst_count++;
+
+    //Call interrupt init
+    init_interrupts();
+    if(rst_count == 1) {
+
+        code_word = (uint32_t *) &iccm_code0_start;
+        VPRINTF(LOW, "Copying code from %x [through %x] to %x\n", (uintptr_t) code_word, &iccm_code0_end, (uintptr_t) iccm_dest);
+        while (code_word < (uint32_t *) &iccm_code0_end) {
+            VPRINTF(ALL, "at %x: %x\n", (uintptr_t) code_word, *code_word);
+            *iccm_dest++ = *code_word++;
+        }
+
+        VPRINTF(LOW, "Execute function from ICCM\n");
+        iccm_fn();
+        
+        //Issue warm reset
+        VPRINTF(LOW, "Issue warm reset\n");
+        SEND_STDOUT_CTRL(0xf6);
+    }
+    else if(rst_count == 2) {
+        VPRINTF(LOW, "Execute function from ICCM after warm reset\n");
+        iccm_fn();
+
+        //Issue cold reset
+        VPRINTF(LOW, "Issue cold reset\n");
+         SEND_STDOUT_CTRL(0xf5);
+
+    }
+    else if(rst_count == 3) {
+        VPRINTF(LOW, "Execute function from ICCM after cold reset\n");
+        iccm_fn();
+
+        //Issue fw update reset
+        VPRINTF(LOW, "Issue core only reset\n");
+        *soc_ifc_fw_update_reset = SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_CORE_RST_MASK;
+    }
+    else if (rst_count == 4) {
+        VPRINTF(LOW, "Execute function from ICCM after core reset\n");
+        iccm_fn();
+    }
+
+    return;
+}
+
+void exec_iccm (void) {
+    VPRINTF (LOW, "In exec_iccm function, before incrementing = %d\n", iter);
+    iter++;
+    VPRINTF (LOW, "In exec_iccm function, after incrementing = %d\n", iter);
+}
diff --git a/src/integration/test_suites/smoke_test_iccm_reset/smoke_test_iccm_reset.yml b/src/integration/test_suites/smoke_test_iccm_reset/smoke_test_iccm_reset.yml
new file mode 100644
index 000000000..206f00d19
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_iccm_reset/smoke_test_iccm_reset.yml
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+---
+seed: 1
+testname: smoke_test_iccm_reset
\ No newline at end of file
diff --git a/src/integration/test_suites/smoke_test_kv/caliptra_isr.h b/src/integration/test_suites/smoke_test_kv/caliptra_isr.h
new file mode 100644
index 000000000..8f5779e04
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_kv/caliptra_isr.h
@@ -0,0 +1,247 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// ---------------------------------------------------------------------
+// File: caliptra_isr.h
+// Description:
+//     Provides function declarations for use by external test files, so
+//     that the ISR functionality may behave like a library.
+//     TODO:
+//     This header file includes inline function definitions for event and
+//     test specific interrupt service behavior, so it should be copied and
+//     modified for each test.
+// ---------------------------------------------------------------------
+
+#ifndef CALIPTRA_ISR_H
+    #define CALIPTRA_ISR_H
+
+#define EN_ISR_PRINTS 1
+
+#include "caliptra_defines.h"
+#include <stdint.h>
+#include "printf.h"
+
+/* --------------- symbols/typedefs --------------- */
+typedef struct {
+    uint32_t doe_error;
+    uint32_t doe_notif;
+    uint32_t ecc_error;
+    uint32_t ecc_notif;
+    uint32_t hmac_error;
+    uint32_t hmac_notif;
+    uint32_t kv_error;
+    uint32_t kv_notif;
+    uint32_t sha512_error;
+    uint32_t sha512_notif;
+    uint32_t sha256_error;
+    uint32_t sha256_notif;
+    uint32_t qspi_error;
+    uint32_t qspi_notif;
+    uint32_t uart_error;
+    uint32_t uart_notif;
+    uint32_t i3c_error;
+    uint32_t i3c_notif;
+    uint32_t soc_ifc_error;
+    uint32_t soc_ifc_notif;
+    uint32_t sha512_acc_error;
+    uint32_t sha512_acc_notif;
+} caliptra_intr_received_s;
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
+
+//////////////////////////////////////////////////////////////////////////////
+// Function Declarations
+//
+
+// Performs all the CSR setup to configure and enable vectored external interrupts
+void init_interrupts(void);
+
+// These inline functions are used to insert event-specific functionality into the
+// otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr"
+inline void service_doe_error_intr() {return;}
+inline void service_doe_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.doe_notif |= DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad doe_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_ecc_error_intr() {return;}
+inline void service_ecc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.ecc_notif |= ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad ecc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_hmac_error_intr() {return;}
+inline void service_hmac_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.hmac_notif |= HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad hmac_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_kv_error_intr() {return;}
+inline void service_kv_notif_intr() {return;}
+inline void service_sha512_error_intr() {return;}
+inline void service_sha512_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_notif |= SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha256_error_intr() {return;}
+inline void service_sha256_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha256_notif |= SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha256_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_qspi_error_intr() {return;}
+inline void service_qspi_notif_intr() {return;}
+inline void service_uart_error_intr() {return;}
+inline void service_uart_notif_intr() {return;}
+inline void service_i3c_error_intr() {return;}
+inline void service_i3c_notif_intr() {return;}
+
+inline void service_soc_ifc_error_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_error_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_soc_ifc_notif_intr () {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha512_acc_error_intr() {return;}
+inline void service_sha512_acc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_acc_notif |= SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_acc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+
+#endif //CALIPTRA_ISR_H
diff --git a/src/integration/test_suites/smoke_test_kv/smoke_test_kv.s b/src/integration/test_suites/smoke_test_kv/smoke_test_kv.s
index 9f330c06e..d0261b059 100644
--- a/src/integration/test_suites/smoke_test_kv/smoke_test_kv.s
+++ b/src/integration/test_suites/smoke_test_kv/smoke_test_kv.s
@@ -252,3 +252,8 @@ hello_world:
 verbosity_g: .word 2
 .global stdout
 stdout: .word STDOUT
+// FW polls this variable for intr
+.global intr_count
+intr_count: .word 0
+.global cptra_intr_rcv
+cptra_intr_rcv: .word 0
diff --git a/src/integration/test_suites/smoke_test_kv_cg/caliptra_isr.h b/src/integration/test_suites/smoke_test_kv_cg/caliptra_isr.h
new file mode 100644
index 000000000..8f5779e04
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_kv_cg/caliptra_isr.h
@@ -0,0 +1,247 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// ---------------------------------------------------------------------
+// File: caliptra_isr.h
+// Description:
+//     Provides function declarations for use by external test files, so
+//     that the ISR functionality may behave like a library.
+//     TODO:
+//     This header file includes inline function definitions for event and
+//     test specific interrupt service behavior, so it should be copied and
+//     modified for each test.
+// ---------------------------------------------------------------------
+
+#ifndef CALIPTRA_ISR_H
+    #define CALIPTRA_ISR_H
+
+#define EN_ISR_PRINTS 1
+
+#include "caliptra_defines.h"
+#include <stdint.h>
+#include "printf.h"
+
+/* --------------- symbols/typedefs --------------- */
+typedef struct {
+    uint32_t doe_error;
+    uint32_t doe_notif;
+    uint32_t ecc_error;
+    uint32_t ecc_notif;
+    uint32_t hmac_error;
+    uint32_t hmac_notif;
+    uint32_t kv_error;
+    uint32_t kv_notif;
+    uint32_t sha512_error;
+    uint32_t sha512_notif;
+    uint32_t sha256_error;
+    uint32_t sha256_notif;
+    uint32_t qspi_error;
+    uint32_t qspi_notif;
+    uint32_t uart_error;
+    uint32_t uart_notif;
+    uint32_t i3c_error;
+    uint32_t i3c_notif;
+    uint32_t soc_ifc_error;
+    uint32_t soc_ifc_notif;
+    uint32_t sha512_acc_error;
+    uint32_t sha512_acc_notif;
+} caliptra_intr_received_s;
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
+
+//////////////////////////////////////////////////////////////////////////////
+// Function Declarations
+//
+
+// Performs all the CSR setup to configure and enable vectored external interrupts
+void init_interrupts(void);
+
+// These inline functions are used to insert event-specific functionality into the
+// otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr"
+inline void service_doe_error_intr() {return;}
+inline void service_doe_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.doe_notif |= DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad doe_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_ecc_error_intr() {return;}
+inline void service_ecc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.ecc_notif |= ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad ecc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_hmac_error_intr() {return;}
+inline void service_hmac_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.hmac_notif |= HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad hmac_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_kv_error_intr() {return;}
+inline void service_kv_notif_intr() {return;}
+inline void service_sha512_error_intr() {return;}
+inline void service_sha512_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_notif |= SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha256_error_intr() {return;}
+inline void service_sha256_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha256_notif |= SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha256_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_qspi_error_intr() {return;}
+inline void service_qspi_notif_intr() {return;}
+inline void service_uart_error_intr() {return;}
+inline void service_uart_notif_intr() {return;}
+inline void service_i3c_error_intr() {return;}
+inline void service_i3c_notif_intr() {return;}
+
+inline void service_soc_ifc_error_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_error_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_soc_ifc_notif_intr () {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha512_acc_error_intr() {return;}
+inline void service_sha512_acc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_acc_notif |= SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_acc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+
+#endif //CALIPTRA_ISR_H
diff --git a/src/integration/test_suites/smoke_test_kv_cg/smoke_test_kv_cg.c b/src/integration/test_suites/smoke_test_kv_cg/smoke_test_kv_cg.c
new file mode 100644
index 000000000..c90f3fcf6
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_kv_cg/smoke_test_kv_cg.c
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+
+#include "caliptra_defines.h"
+#include "caliptra_isr.h"
+#include "riscv-csr.h"
+#include <string.h>
+#include <stdint.h>
+#include "printf.h"
+#include "clk_gate.h"
+
+volatile char*    stdout           = (char *)STDOUT;
+volatile uint32_t intr_count = 0;
+volatile uint32_t rst_count __attribute__((section(".dccm.persistent"))) = 0;
+#ifdef CPT_VERBOSITY
+    enum printf_verbosity verbosity_g = CPT_VERBOSITY;
+#else
+    enum printf_verbosity verbosity_g = LOW;
+#endif
+
+volatile caliptra_intr_received_s cptra_intr_rcv = {
+    .doe_error        = 0,
+    .doe_notif        = 0,
+    .ecc_error        = 0,
+    .ecc_notif        = 0,
+    .hmac_error       = 0,
+    .hmac_notif       = 0,
+    .kv_error         = 0,
+    .kv_notif         = 0,
+    .sha512_error     = 0,
+    .sha512_notif     = 0,
+    .sha256_error     = 0,
+    .sha256_notif     = 0,
+    .qspi_error       = 0,
+    .qspi_notif       = 0,
+    .uart_error       = 0,
+    .uart_notif       = 0,
+    .i3c_error        = 0,
+    .i3c_notif        = 0,
+    .soc_ifc_error    = 0,
+    .soc_ifc_notif    = 0,
+    .sha512_acc_error = 0,
+    .sha512_acc_notif = 0,
+};
+
+uint32_t IV_DATA_UDS0 = 0x2eb94297;
+uint32_t IV_DATA_UDS1 = 0x77285196;
+uint32_t IV_DATA_UDS2 = 0x3dd39a1e;
+uint32_t IV_DATA_UDS3 = 0xb95d438f;
+
+volatile uint32_t * doe_iv_0 = (uint32_t *) CLP_DOE_REG_DOE_IV_0;
+volatile uint32_t * doe_iv_1 = (uint32_t *) CLP_DOE_REG_DOE_IV_1;
+volatile uint32_t * doe_iv_2 = (uint32_t *) CLP_DOE_REG_DOE_IV_2;
+volatile uint32_t * doe_iv_3 = (uint32_t *) CLP_DOE_REG_DOE_IV_3;
+
+volatile uint32_t * doe_ctrl = (uint32_t *) CLP_DOE_REG_DOE_CTRL;
+volatile uint32_t * doe_status = (uint32_t *) CLP_DOE_REG_DOE_STATUS;
+
+volatile uint32_t * soc_ifc_fw_update_reset = (uint32_t *) (CLP_SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET);
+
+volatile uint32_t * pcr_ctrl0 = (uint32_t *) CLP_PV_REG_PCR_CTRL_0;
+volatile uint32_t * pcr_ctrl2 = (uint32_t *) CLP_PV_REG_PCR_CTRL_2;
+volatile uint32_t * pcr_ctrl5 = (uint32_t *) CLP_PV_REG_PCR_CTRL_5;
+
+volatile uint32_t * key_ctrl1 = (uint32_t *) CLP_KV_REG_KEY_CTRL_1;
+volatile uint32_t * key_ctrl4 = (uint32_t *) CLP_KV_REG_KEY_CTRL_4;
+volatile uint32_t * key_ctrl7 = (uint32_t *) CLP_KV_REG_KEY_CTRL_7;
+
+volatile uint32_t doe_status_int;
+
+void main() {
+    volatile uint32_t mitb0 = 0x00000400;
+    volatile uint32_t mitb1 = 0x00000500;
+    volatile uint32_t mie_timer0_en = 0x20000000;
+
+    VPRINTF(LOW,"---------------------------\n");
+    VPRINTF(LOW," KV Smoke Test With Warm Reset !!\n");
+    VPRINTF(LOW,"---------------------------\n");
+
+    //Call interrupt init
+    init_interrupts();
+
+    //Enable clk gating and halt core
+    SEND_STDOUT_CTRL(0xf2);
+    set_mit0(mitb0, mie_timer0_en);
+
+    VPRINTF(LOW,"UDS flow\n");
+    //Write UDS IV
+    *doe_iv_0 = IV_DATA_UDS0;
+    *doe_iv_1 = IV_DATA_UDS1;
+    *doe_iv_2 = IV_DATA_UDS2;
+    *doe_iv_3 = IV_DATA_UDS3;
+
+    //Start UDS and store in KV0
+    *doe_ctrl = 0x00000001;
+
+    //Sleep
+    // for (uint16_t i = 0; i < 2; i++){
+    //     printf("%d\n", i);
+    // }
+    printf("Dummy print\n");
+    __asm__ volatile ("csrwi    %0, %1" \
+                    : /* output: none */        \
+                    : "i" (0x7c6), "i" (0x03)  /* input : immediate  */ \
+                    : /* clobbers: none */);
+    // set_mit0_and_halt_core(mitb0, mie_timer0_en);
+    //halt_core();
+    // set_mit0(mitb1, mie_timer0_en);
+    // halt_core();
+
+    // //Poll for DOE status
+    while(doe_status_int != (DOE_REG_DOE_STATUS_VALID_MASK | DOE_REG_DOE_STATUS_READY_MASK)) {
+        doe_status_int = *doe_status;
+        doe_status_int = doe_status_int & (DOE_REG_DOE_STATUS_VALID_MASK | DOE_REG_DOE_STATUS_READY_MASK) ;
+    }
+    
+
+    VPRINTF(LOW, "Core back up\n");
+    //Restart UDS flow after core wakes up - should not go through
+    //Write UDS IV
+    VPRINTF(LOW, "Writing IV a 2nd time\n");
+    *doe_iv_0 = IV_DATA_UDS3;
+    *doe_iv_1 = IV_DATA_UDS2;
+    *doe_iv_2 = IV_DATA_UDS1;
+    *doe_iv_3 = IV_DATA_UDS0;
+
+    //Start UDS and store in KV0
+    VPRINTF(LOW, "Starting UDS again\n");
+    *doe_ctrl = 0x00000001;
+
+    // //Poll for DOE status
+    doe_status_int = 0x00000000;
+        while(doe_status_int != (DOE_REG_DOE_STATUS_VALID_MASK | DOE_REG_DOE_STATUS_READY_MASK)) {
+            doe_status_int = *doe_status;
+            doe_status_int = doe_status_int & (DOE_REG_DOE_STATUS_VALID_MASK | DOE_REG_DOE_STATUS_READY_MASK) ;
+        }
+    
+}
diff --git a/src/integration/test_suites/smoke_test_kv_cg/smoke_test_kv_cg.yml b/src/integration/test_suites/smoke_test_kv_cg/smoke_test_kv_cg.yml
new file mode 100644
index 000000000..41b50850e
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_kv_cg/smoke_test_kv_cg.yml
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+---
+seed: 1
+testname: smoke_test_kv_uds_reset
\ No newline at end of file
diff --git a/src/integration/test_suites/smoke_test_kv_crypto_flow/caliptra_isr.h b/src/integration/test_suites/smoke_test_kv_crypto_flow/caliptra_isr.h
index 6ffd71c0a..8f5779e04 100644
--- a/src/integration/test_suites/smoke_test_kv_crypto_flow/caliptra_isr.h
+++ b/src/integration/test_suites/smoke_test_kv_crypto_flow/caliptra_isr.h
@@ -204,6 +204,22 @@ inline void service_soc_ifc_notif_intr () {
         *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
         cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
     }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
     if (sts == 0) {
         VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
         SEND_STDOUT_CTRL(0x1);
diff --git a/src/integration/test_suites/smoke_test_kv_crypto_flow/smoke_test_kv_crypto_flow.c b/src/integration/test_suites/smoke_test_kv_crypto_flow/smoke_test_kv_crypto_flow.c
index 406450b63..12383a871 100644
--- a/src/integration/test_suites/smoke_test_kv_crypto_flow/smoke_test_kv_crypto_flow.c
+++ b/src/integration/test_suites/smoke_test_kv_crypto_flow/smoke_test_kv_crypto_flow.c
@@ -269,7 +269,7 @@ void main(){
     uint8_t cdi_ldevid_id;
 
     //Call interrupt init
-    //init_interrupts();
+    init_interrupts();
 
     random_generator(&doe_fe_dest_id, &uds_key_id, &idevid_privkey_id, &cdi_ldevid_id);
     printf("%x, %x, %x, %x\n",doe_fe_dest_id, uds_key_id, idevid_privkey_id, cdi_ldevid_id);
diff --git a/src/integration/test_suites/smoke_test_kv_ecc_flow/caliptra_isr.h b/src/integration/test_suites/smoke_test_kv_ecc_flow/caliptra_isr.h
index 6ffd71c0a..8f5779e04 100644
--- a/src/integration/test_suites/smoke_test_kv_ecc_flow/caliptra_isr.h
+++ b/src/integration/test_suites/smoke_test_kv_ecc_flow/caliptra_isr.h
@@ -204,6 +204,22 @@ inline void service_soc_ifc_notif_intr () {
         *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
         cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
     }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
     if (sts == 0) {
         VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
         SEND_STDOUT_CTRL(0x1);
diff --git a/src/integration/test_suites/smoke_test_kv_hmac_flow/caliptra_isr.h b/src/integration/test_suites/smoke_test_kv_hmac_flow/caliptra_isr.h
index 6ffd71c0a..8f5779e04 100644
--- a/src/integration/test_suites/smoke_test_kv_hmac_flow/caliptra_isr.h
+++ b/src/integration/test_suites/smoke_test_kv_hmac_flow/caliptra_isr.h
@@ -204,6 +204,22 @@ inline void service_soc_ifc_notif_intr () {
         *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
         cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
     }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
     if (sts == 0) {
         VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
         SEND_STDOUT_CTRL(0x1);
diff --git a/src/integration/test_suites/smoke_test_kv_hmac_flow/smoke_test_kv_hmac_flow.c b/src/integration/test_suites/smoke_test_kv_hmac_flow/smoke_test_kv_hmac_flow.c
index 0df1dc454..f43580d77 100644
--- a/src/integration/test_suites/smoke_test_kv_hmac_flow/smoke_test_kv_hmac_flow.c
+++ b/src/integration/test_suites/smoke_test_kv_hmac_flow/smoke_test_kv_hmac_flow.c
@@ -153,7 +153,7 @@ void main() {
     for (int i = 0; i < hmac_lfsr_seed.data_size; i++)
         hmac_lfsr_seed.data[i] = lfsr_seed_data[i];
 
-    hmac_tag.kv_intf = FALSE;
+    hmac_tag.kv_intf = TRUE;
     hmac_tag.kv_id = tag_kv_id;
     hmac_tag.data_size = 12;
     for (int i = 0; i < hmac_tag.data_size; i++)
diff --git a/src/integration/test_suites/smoke_test_kv_securitystate/caliptra_isr.h b/src/integration/test_suites/smoke_test_kv_securitystate/caliptra_isr.h
index 48879dc68..8f5779e04 100644
--- a/src/integration/test_suites/smoke_test_kv_securitystate/caliptra_isr.h
+++ b/src/integration/test_suites/smoke_test_kv_securitystate/caliptra_isr.h
@@ -32,39 +32,216 @@
 #include <stdint.h>
 #include "printf.h"
 
-//extern volatile uint32_t hmac_intr_status;
+/* --------------- symbols/typedefs --------------- */
+typedef struct {
+    uint32_t doe_error;
+    uint32_t doe_notif;
+    uint32_t ecc_error;
+    uint32_t ecc_notif;
+    uint32_t hmac_error;
+    uint32_t hmac_notif;
+    uint32_t kv_error;
+    uint32_t kv_notif;
+    uint32_t sha512_error;
+    uint32_t sha512_notif;
+    uint32_t sha256_error;
+    uint32_t sha256_notif;
+    uint32_t qspi_error;
+    uint32_t qspi_notif;
+    uint32_t uart_error;
+    uint32_t uart_notif;
+    uint32_t i3c_error;
+    uint32_t i3c_notif;
+    uint32_t soc_ifc_error;
+    uint32_t soc_ifc_notif;
+    uint32_t sha512_acc_error;
+    uint32_t sha512_acc_notif;
+} caliptra_intr_received_s;
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
 
 //////////////////////////////////////////////////////////////////////////////
 // Function Declarations
 //
+
 // Performs all the CSR setup to configure and enable vectored external interrupts
 void init_interrupts(void);
 
 // These inline functions are used to insert event-specific functionality into the
 // otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr"
-inline void service_doe_error_intr() {printf("ERROR");}
-inline void service_doe_notif_intr() {printf("ERROR");}
-inline void service_ecc_error_intr   () {printf("ERROR");}
-inline void service_ecc_notif_intr   () {printf("ERROR");}
-inline void service_hmac_error_intr  () {printf("ERROR");}
-inline void service_hmac_notif_intr  () {printf("ERROR");}
-
-inline void service_kv_error_intr    () {printf("ERROR");}
-inline void service_kv_notif_intr    () {printf("ERROR");}
-inline void service_sha512_error_intr() {printf("ERROR");}
-inline void service_sha512_notif_intr() {printf("ERROR");}
-inline void service_sha256_error_intr() {printf("ERROR");}
-inline void service_sha256_notif_intr() {printf("ERROR");}
-inline void service_qspi_error_intr  () {printf("ERROR");}
-inline void service_qspi_notif_intr  () {printf("ERROR");}
-inline void service_uart_error_intr  () {printf("ERROR");}
-inline void service_uart_notif_intr  () {printf("ERROR");}
-inline void service_i3c_error_intr   () {printf("ERROR");}
-inline void service_i3c_notif_intr   () {printf("ERROR");}
-inline void service_soc_ifc_error_intr  () {printf("ERROR");}
-inline void service_soc_ifc_notif_intr  () {printf("ERROR");}
-inline void service_sha512_acc_error_intr() {printf("ERROR");}
-inline void service_sha512_acc_notif_intr() {printf("ERROR");}
+inline void service_doe_error_intr() {return;}
+inline void service_doe_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.doe_notif |= DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad doe_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_ecc_error_intr() {return;}
+inline void service_ecc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.ecc_notif |= ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad ecc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_hmac_error_intr() {return;}
+inline void service_hmac_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.hmac_notif |= HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad hmac_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_kv_error_intr() {return;}
+inline void service_kv_notif_intr() {return;}
+inline void service_sha512_error_intr() {return;}
+inline void service_sha512_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_notif |= SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha256_error_intr() {return;}
+inline void service_sha256_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha256_notif |= SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha256_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_qspi_error_intr() {return;}
+inline void service_qspi_notif_intr() {return;}
+inline void service_uart_error_intr() {return;}
+inline void service_uart_notif_intr() {return;}
+inline void service_i3c_error_intr() {return;}
+inline void service_i3c_notif_intr() {return;}
+
+inline void service_soc_ifc_error_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_error_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_soc_ifc_notif_intr () {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha512_acc_error_intr() {return;}
+inline void service_sha512_acc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_acc_notif |= SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_acc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
 
 
 #endif //CALIPTRA_ISR_H
diff --git a/src/integration/test_suites/smoke_test_kv_securitystate/smoke_test_kv_securitystate.c b/src/integration/test_suites/smoke_test_kv_securitystate/smoke_test_kv_securitystate.c
index cee7e0b66..391bc7b62 100644
--- a/src/integration/test_suites/smoke_test_kv_securitystate/smoke_test_kv_securitystate.c
+++ b/src/integration/test_suites/smoke_test_kv_securitystate/smoke_test_kv_securitystate.c
@@ -30,6 +30,31 @@ volatile uint32_t rst_count __attribute__((section(".dccm.persistent"))) = 0;
     enum printf_verbosity verbosity_g = LOW;
 #endif
 
+volatile caliptra_intr_received_s cptra_intr_rcv = {
+    .doe_error        = 0,
+    .doe_notif        = 0,
+    .ecc_error        = 0,
+    .ecc_notif        = 0,
+    .hmac_error       = 0,
+    .hmac_notif       = 0,
+    .kv_error         = 0,
+    .kv_notif         = 0,
+    .sha512_error     = 0,
+    .sha512_notif     = 0,
+    .sha256_error     = 0,
+    .sha256_notif     = 0,
+    .qspi_error       = 0,
+    .qspi_notif       = 0,
+    .uart_error       = 0,
+    .uart_notif       = 0,
+    .i3c_error        = 0,
+    .i3c_notif        = 0,
+    .soc_ifc_error    = 0,
+    .soc_ifc_notif    = 0,
+    .sha512_acc_error = 0,
+    .sha512_acc_notif = 0,
+};
+
 volatile uint32_t * clear_secrets = (uint32_t *) CLP_KV_REG_CLEAR_SECRETS;
 volatile uint32_t * reset_reason  = (uint32_t *) CLP_SOC_IFC_REG_CPTRA_RESET_REASON;
 
diff --git a/src/integration/test_suites/smoke_test_kv_sha512_flow/caliptra_isr.h b/src/integration/test_suites/smoke_test_kv_sha512_flow/caliptra_isr.h
index 48879dc68..8f5779e04 100644
--- a/src/integration/test_suites/smoke_test_kv_sha512_flow/caliptra_isr.h
+++ b/src/integration/test_suites/smoke_test_kv_sha512_flow/caliptra_isr.h
@@ -32,39 +32,216 @@
 #include <stdint.h>
 #include "printf.h"
 
-//extern volatile uint32_t hmac_intr_status;
+/* --------------- symbols/typedefs --------------- */
+typedef struct {
+    uint32_t doe_error;
+    uint32_t doe_notif;
+    uint32_t ecc_error;
+    uint32_t ecc_notif;
+    uint32_t hmac_error;
+    uint32_t hmac_notif;
+    uint32_t kv_error;
+    uint32_t kv_notif;
+    uint32_t sha512_error;
+    uint32_t sha512_notif;
+    uint32_t sha256_error;
+    uint32_t sha256_notif;
+    uint32_t qspi_error;
+    uint32_t qspi_notif;
+    uint32_t uart_error;
+    uint32_t uart_notif;
+    uint32_t i3c_error;
+    uint32_t i3c_notif;
+    uint32_t soc_ifc_error;
+    uint32_t soc_ifc_notif;
+    uint32_t sha512_acc_error;
+    uint32_t sha512_acc_notif;
+} caliptra_intr_received_s;
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
 
 //////////////////////////////////////////////////////////////////////////////
 // Function Declarations
 //
+
 // Performs all the CSR setup to configure and enable vectored external interrupts
 void init_interrupts(void);
 
 // These inline functions are used to insert event-specific functionality into the
 // otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr"
-inline void service_doe_error_intr() {printf("ERROR");}
-inline void service_doe_notif_intr() {printf("ERROR");}
-inline void service_ecc_error_intr   () {printf("ERROR");}
-inline void service_ecc_notif_intr   () {printf("ERROR");}
-inline void service_hmac_error_intr  () {printf("ERROR");}
-inline void service_hmac_notif_intr  () {printf("ERROR");}
-
-inline void service_kv_error_intr    () {printf("ERROR");}
-inline void service_kv_notif_intr    () {printf("ERROR");}
-inline void service_sha512_error_intr() {printf("ERROR");}
-inline void service_sha512_notif_intr() {printf("ERROR");}
-inline void service_sha256_error_intr() {printf("ERROR");}
-inline void service_sha256_notif_intr() {printf("ERROR");}
-inline void service_qspi_error_intr  () {printf("ERROR");}
-inline void service_qspi_notif_intr  () {printf("ERROR");}
-inline void service_uart_error_intr  () {printf("ERROR");}
-inline void service_uart_notif_intr  () {printf("ERROR");}
-inline void service_i3c_error_intr   () {printf("ERROR");}
-inline void service_i3c_notif_intr   () {printf("ERROR");}
-inline void service_soc_ifc_error_intr  () {printf("ERROR");}
-inline void service_soc_ifc_notif_intr  () {printf("ERROR");}
-inline void service_sha512_acc_error_intr() {printf("ERROR");}
-inline void service_sha512_acc_notif_intr() {printf("ERROR");}
+inline void service_doe_error_intr() {return;}
+inline void service_doe_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.doe_notif |= DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad doe_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_ecc_error_intr() {return;}
+inline void service_ecc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.ecc_notif |= ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad ecc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_hmac_error_intr() {return;}
+inline void service_hmac_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.hmac_notif |= HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad hmac_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_kv_error_intr() {return;}
+inline void service_kv_notif_intr() {return;}
+inline void service_sha512_error_intr() {return;}
+inline void service_sha512_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_notif |= SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha256_error_intr() {return;}
+inline void service_sha256_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha256_notif |= SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha256_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_qspi_error_intr() {return;}
+inline void service_qspi_notif_intr() {return;}
+inline void service_uart_error_intr() {return;}
+inline void service_uart_notif_intr() {return;}
+inline void service_i3c_error_intr() {return;}
+inline void service_i3c_notif_intr() {return;}
+
+inline void service_soc_ifc_error_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_error_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_soc_ifc_notif_intr () {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha512_acc_error_intr() {return;}
+inline void service_sha512_acc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_acc_notif |= SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_acc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
 
 
 #endif //CALIPTRA_ISR_H
diff --git a/src/integration/test_suites/smoke_test_kv_sha512_flow/smoke_test_kv_sha512_flow.c b/src/integration/test_suites/smoke_test_kv_sha512_flow/smoke_test_kv_sha512_flow.c
index a46f5e360..54b2b6060 100644
--- a/src/integration/test_suites/smoke_test_kv_sha512_flow/smoke_test_kv_sha512_flow.c
+++ b/src/integration/test_suites/smoke_test_kv_sha512_flow/smoke_test_kv_sha512_flow.c
@@ -32,6 +32,30 @@ volatile uint32_t rst_count = 0;
     enum printf_verbosity verbosity_g = LOW;
 #endif
 
+volatile caliptra_intr_received_s cptra_intr_rcv = {
+    .doe_error        = 0,
+    .doe_notif        = 0,
+    .ecc_error        = 0,
+    .ecc_notif        = 0,
+    .hmac_error       = 0,
+    .hmac_notif       = 0,
+    .kv_error         = 0,
+    .kv_notif         = 0,
+    .sha512_error     = 0,
+    .sha512_notif     = 0,
+    .sha256_error     = 0,
+    .sha256_notif     = 0,
+    .qspi_error       = 0,
+    .qspi_notif       = 0,
+    .uart_error       = 0,
+    .uart_notif       = 0,
+    .i3c_error        = 0,
+    .i3c_notif        = 0,
+    .soc_ifc_error    = 0,
+    .soc_ifc_notif    = 0,
+    .sha512_acc_error = 0,
+    .sha512_acc_notif = 0,
+};
 
 
 /* SHA384 test vector:
@@ -45,7 +69,7 @@ void main() {
     printf("----------------------------------\n");
 
     //Call interrupt init
-    //init_interrupts();
+    init_interrupts();
 
     uint32_t expected_digest[] =   {0x38742d18,
                                     0xbfa6e918,
diff --git a/src/integration/test_suites/smoke_test_kv_uds_reset/caliptra_isr.h b/src/integration/test_suites/smoke_test_kv_uds_reset/caliptra_isr.h
index 48879dc68..8f5779e04 100644
--- a/src/integration/test_suites/smoke_test_kv_uds_reset/caliptra_isr.h
+++ b/src/integration/test_suites/smoke_test_kv_uds_reset/caliptra_isr.h
@@ -32,39 +32,216 @@
 #include <stdint.h>
 #include "printf.h"
 
-//extern volatile uint32_t hmac_intr_status;
+/* --------------- symbols/typedefs --------------- */
+typedef struct {
+    uint32_t doe_error;
+    uint32_t doe_notif;
+    uint32_t ecc_error;
+    uint32_t ecc_notif;
+    uint32_t hmac_error;
+    uint32_t hmac_notif;
+    uint32_t kv_error;
+    uint32_t kv_notif;
+    uint32_t sha512_error;
+    uint32_t sha512_notif;
+    uint32_t sha256_error;
+    uint32_t sha256_notif;
+    uint32_t qspi_error;
+    uint32_t qspi_notif;
+    uint32_t uart_error;
+    uint32_t uart_notif;
+    uint32_t i3c_error;
+    uint32_t i3c_notif;
+    uint32_t soc_ifc_error;
+    uint32_t soc_ifc_notif;
+    uint32_t sha512_acc_error;
+    uint32_t sha512_acc_notif;
+} caliptra_intr_received_s;
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
 
 //////////////////////////////////////////////////////////////////////////////
 // Function Declarations
 //
+
 // Performs all the CSR setup to configure and enable vectored external interrupts
 void init_interrupts(void);
 
 // These inline functions are used to insert event-specific functionality into the
 // otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr"
-inline void service_doe_error_intr() {printf("ERROR");}
-inline void service_doe_notif_intr() {printf("ERROR");}
-inline void service_ecc_error_intr   () {printf("ERROR");}
-inline void service_ecc_notif_intr   () {printf("ERROR");}
-inline void service_hmac_error_intr  () {printf("ERROR");}
-inline void service_hmac_notif_intr  () {printf("ERROR");}
-
-inline void service_kv_error_intr    () {printf("ERROR");}
-inline void service_kv_notif_intr    () {printf("ERROR");}
-inline void service_sha512_error_intr() {printf("ERROR");}
-inline void service_sha512_notif_intr() {printf("ERROR");}
-inline void service_sha256_error_intr() {printf("ERROR");}
-inline void service_sha256_notif_intr() {printf("ERROR");}
-inline void service_qspi_error_intr  () {printf("ERROR");}
-inline void service_qspi_notif_intr  () {printf("ERROR");}
-inline void service_uart_error_intr  () {printf("ERROR");}
-inline void service_uart_notif_intr  () {printf("ERROR");}
-inline void service_i3c_error_intr   () {printf("ERROR");}
-inline void service_i3c_notif_intr   () {printf("ERROR");}
-inline void service_soc_ifc_error_intr  () {printf("ERROR");}
-inline void service_soc_ifc_notif_intr  () {printf("ERROR");}
-inline void service_sha512_acc_error_intr() {printf("ERROR");}
-inline void service_sha512_acc_notif_intr() {printf("ERROR");}
+inline void service_doe_error_intr() {return;}
+inline void service_doe_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.doe_notif |= DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad doe_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_ecc_error_intr() {return;}
+inline void service_ecc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.ecc_notif |= ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad ecc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_hmac_error_intr() {return;}
+inline void service_hmac_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.hmac_notif |= HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad hmac_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_kv_error_intr() {return;}
+inline void service_kv_notif_intr() {return;}
+inline void service_sha512_error_intr() {return;}
+inline void service_sha512_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_notif |= SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha256_error_intr() {return;}
+inline void service_sha256_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha256_notif |= SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha256_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_qspi_error_intr() {return;}
+inline void service_qspi_notif_intr() {return;}
+inline void service_uart_error_intr() {return;}
+inline void service_uart_notif_intr() {return;}
+inline void service_i3c_error_intr() {return;}
+inline void service_i3c_notif_intr() {return;}
+
+inline void service_soc_ifc_error_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_error_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_soc_ifc_notif_intr () {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha512_acc_error_intr() {return;}
+inline void service_sha512_acc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_acc_notif |= SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_acc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
 
 
 #endif //CALIPTRA_ISR_H
diff --git a/src/integration/test_suites/smoke_test_kv_uds_reset/smoke_test_kv_uds_reset.c b/src/integration/test_suites/smoke_test_kv_uds_reset/smoke_test_kv_uds_reset.c
index be5e0646b..829b5a4d0 100644
--- a/src/integration/test_suites/smoke_test_kv_uds_reset/smoke_test_kv_uds_reset.c
+++ b/src/integration/test_suites/smoke_test_kv_uds_reset/smoke_test_kv_uds_reset.c
@@ -29,6 +29,31 @@ volatile uint32_t rst_count __attribute__((section(".dccm.persistent"))) = 0;
     enum printf_verbosity verbosity_g = LOW;
 #endif
 
+volatile caliptra_intr_received_s cptra_intr_rcv = {
+    .doe_error        = 0,
+    .doe_notif        = 0,
+    .ecc_error        = 0,
+    .ecc_notif        = 0,
+    .hmac_error       = 0,
+    .hmac_notif       = 0,
+    .kv_error         = 0,
+    .kv_notif         = 0,
+    .sha512_error     = 0,
+    .sha512_notif     = 0,
+    .sha256_error     = 0,
+    .sha256_notif     = 0,
+    .qspi_error       = 0,
+    .qspi_notif       = 0,
+    .uart_error       = 0,
+    .uart_notif       = 0,
+    .i3c_error        = 0,
+    .i3c_notif        = 0,
+    .soc_ifc_error    = 0,
+    .soc_ifc_notif    = 0,
+    .sha512_acc_error = 0,
+    .sha512_acc_notif = 0,
+};
+
 uint32_t IV_DATA_UDS0 = 0x2eb94297;
 uint32_t IV_DATA_UDS1 = 0x77285196;
 uint32_t IV_DATA_UDS2 = 0x3dd39a1e;
diff --git a/src/integration/test_suites/smoke_test_mbox/caliptra_isr.h b/src/integration/test_suites/smoke_test_mbox/caliptra_isr.h
new file mode 100644
index 000000000..8f5779e04
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_mbox/caliptra_isr.h
@@ -0,0 +1,247 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// ---------------------------------------------------------------------
+// File: caliptra_isr.h
+// Description:
+//     Provides function declarations for use by external test files, so
+//     that the ISR functionality may behave like a library.
+//     TODO:
+//     This header file includes inline function definitions for event and
+//     test specific interrupt service behavior, so it should be copied and
+//     modified for each test.
+// ---------------------------------------------------------------------
+
+#ifndef CALIPTRA_ISR_H
+    #define CALIPTRA_ISR_H
+
+#define EN_ISR_PRINTS 1
+
+#include "caliptra_defines.h"
+#include <stdint.h>
+#include "printf.h"
+
+/* --------------- symbols/typedefs --------------- */
+typedef struct {
+    uint32_t doe_error;
+    uint32_t doe_notif;
+    uint32_t ecc_error;
+    uint32_t ecc_notif;
+    uint32_t hmac_error;
+    uint32_t hmac_notif;
+    uint32_t kv_error;
+    uint32_t kv_notif;
+    uint32_t sha512_error;
+    uint32_t sha512_notif;
+    uint32_t sha256_error;
+    uint32_t sha256_notif;
+    uint32_t qspi_error;
+    uint32_t qspi_notif;
+    uint32_t uart_error;
+    uint32_t uart_notif;
+    uint32_t i3c_error;
+    uint32_t i3c_notif;
+    uint32_t soc_ifc_error;
+    uint32_t soc_ifc_notif;
+    uint32_t sha512_acc_error;
+    uint32_t sha512_acc_notif;
+} caliptra_intr_received_s;
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
+
+//////////////////////////////////////////////////////////////////////////////
+// Function Declarations
+//
+
+// Performs all the CSR setup to configure and enable vectored external interrupts
+void init_interrupts(void);
+
+// These inline functions are used to insert event-specific functionality into the
+// otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr"
+inline void service_doe_error_intr() {return;}
+inline void service_doe_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.doe_notif |= DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad doe_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_ecc_error_intr() {return;}
+inline void service_ecc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.ecc_notif |= ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad ecc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_hmac_error_intr() {return;}
+inline void service_hmac_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.hmac_notif |= HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad hmac_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_kv_error_intr() {return;}
+inline void service_kv_notif_intr() {return;}
+inline void service_sha512_error_intr() {return;}
+inline void service_sha512_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_notif |= SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha256_error_intr() {return;}
+inline void service_sha256_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha256_notif |= SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha256_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_qspi_error_intr() {return;}
+inline void service_qspi_notif_intr() {return;}
+inline void service_uart_error_intr() {return;}
+inline void service_uart_notif_intr() {return;}
+inline void service_i3c_error_intr() {return;}
+inline void service_i3c_notif_intr() {return;}
+
+inline void service_soc_ifc_error_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_error_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_soc_ifc_notif_intr () {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha512_acc_error_intr() {return;}
+inline void service_sha512_acc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_acc_notif |= SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_acc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+
+#endif //CALIPTRA_ISR_H
diff --git a/src/integration/test_suites/smoke_test_mbox/smoke_test_mbox.c b/src/integration/test_suites/smoke_test_mbox/smoke_test_mbox.c
index 5494e5a32..1ad31280c 100644
--- a/src/integration/test_suites/smoke_test_mbox/smoke_test_mbox.c
+++ b/src/integration/test_suites/smoke_test_mbox/smoke_test_mbox.c
@@ -17,6 +17,7 @@
 #include "soc_ifc.h"
 #include <stdint.h>
 #include "printf.h"
+#include "caliptra_isr.h"
 
 volatile char*    stdout           = (char *)STDOUT;
 volatile uint32_t intr_count       = 0;
@@ -28,6 +29,31 @@ volatile uint32_t intr_count       = 0;
 
 #define MBOX_DLEN_VAL             0x00000020
 
+volatile caliptra_intr_received_s cptra_intr_rcv = {
+    .doe_error        = 0,
+    .doe_notif        = 0,
+    .ecc_error        = 0,
+    .ecc_notif        = 0,
+    .hmac_error       = 0,
+    .hmac_notif       = 0,
+    .kv_error         = 0,
+    .kv_notif         = 0,
+    .sha512_error     = 0,
+    .sha512_notif     = 0,
+    .sha256_error     = 0,
+    .sha256_notif     = 0,
+    .qspi_error       = 0,
+    .qspi_notif       = 0,
+    .uart_error       = 0,
+    .uart_notif       = 0,
+    .i3c_error        = 0,
+    .i3c_notif        = 0,
+    .soc_ifc_error    = 0,
+    .soc_ifc_notif    = 0,
+    .sha512_acc_error = 0,
+    .sha512_acc_notif = 0,
+};
+
 void main () {
 
     mbox_op_s op;
@@ -95,6 +121,10 @@ void main () {
         VPRINTF(LOW, "FW: Mailbox in expected state, MBOX_EXECUTE_SOC, ending test with success\n");
     }
 
+    //Wait for SoC to reset execute reg
+    VPRINTF(LOW, "FW: Wait for SoC to reset execute register\n");
+    while((lsu_read_32(CLP_MBOX_CSR_MBOX_EXECUTE) & MBOX_CSR_MBOX_EXECUTE_EXECUTE_MASK) == 1);
+
     //Force unlock
     lsu_write_32(CLP_MBOX_CSR_MBOX_UNLOCK, MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK);
 
diff --git a/src/integration/test_suites/smoke_test_mbox_cg/caliptra_isr.h b/src/integration/test_suites/smoke_test_mbox_cg/caliptra_isr.h
new file mode 100644
index 000000000..8f5779e04
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_mbox_cg/caliptra_isr.h
@@ -0,0 +1,247 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// ---------------------------------------------------------------------
+// File: caliptra_isr.h
+// Description:
+//     Provides function declarations for use by external test files, so
+//     that the ISR functionality may behave like a library.
+//     TODO:
+//     This header file includes inline function definitions for event and
+//     test specific interrupt service behavior, so it should be copied and
+//     modified for each test.
+// ---------------------------------------------------------------------
+
+#ifndef CALIPTRA_ISR_H
+    #define CALIPTRA_ISR_H
+
+#define EN_ISR_PRINTS 1
+
+#include "caliptra_defines.h"
+#include <stdint.h>
+#include "printf.h"
+
+/* --------------- symbols/typedefs --------------- */
+typedef struct {
+    uint32_t doe_error;
+    uint32_t doe_notif;
+    uint32_t ecc_error;
+    uint32_t ecc_notif;
+    uint32_t hmac_error;
+    uint32_t hmac_notif;
+    uint32_t kv_error;
+    uint32_t kv_notif;
+    uint32_t sha512_error;
+    uint32_t sha512_notif;
+    uint32_t sha256_error;
+    uint32_t sha256_notif;
+    uint32_t qspi_error;
+    uint32_t qspi_notif;
+    uint32_t uart_error;
+    uint32_t uart_notif;
+    uint32_t i3c_error;
+    uint32_t i3c_notif;
+    uint32_t soc_ifc_error;
+    uint32_t soc_ifc_notif;
+    uint32_t sha512_acc_error;
+    uint32_t sha512_acc_notif;
+} caliptra_intr_received_s;
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
+
+//////////////////////////////////////////////////////////////////////////////
+// Function Declarations
+//
+
+// Performs all the CSR setup to configure and enable vectored external interrupts
+void init_interrupts(void);
+
+// These inline functions are used to insert event-specific functionality into the
+// otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr"
+inline void service_doe_error_intr() {return;}
+inline void service_doe_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.doe_notif |= DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad doe_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_ecc_error_intr() {return;}
+inline void service_ecc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.ecc_notif |= ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad ecc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_hmac_error_intr() {return;}
+inline void service_hmac_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.hmac_notif |= HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad hmac_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_kv_error_intr() {return;}
+inline void service_kv_notif_intr() {return;}
+inline void service_sha512_error_intr() {return;}
+inline void service_sha512_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_notif |= SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha256_error_intr() {return;}
+inline void service_sha256_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha256_notif |= SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha256_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_qspi_error_intr() {return;}
+inline void service_qspi_notif_intr() {return;}
+inline void service_uart_error_intr() {return;}
+inline void service_uart_notif_intr() {return;}
+inline void service_i3c_error_intr() {return;}
+inline void service_i3c_notif_intr() {return;}
+
+inline void service_soc_ifc_error_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_error_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_soc_ifc_notif_intr () {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha512_acc_error_intr() {return;}
+inline void service_sha512_acc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_acc_notif |= SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_acc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+
+#endif //CALIPTRA_ISR_H
diff --git a/src/integration/test_suites/smoke_test_mbox_cg/smoke_test_mbox_cg.c b/src/integration/test_suites/smoke_test_mbox_cg/smoke_test_mbox_cg.c
new file mode 100644
index 000000000..9697d6e71
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_mbox_cg/smoke_test_mbox_cg.c
@@ -0,0 +1,198 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+#include "caliptra_defines.h"
+#include "riscv_hw_if.h"
+#include "soc_ifc.h"
+#include <stdint.h>
+#include "printf.h"
+#include "caliptra_isr.h"
+#include "clk_gate.h"
+
+volatile char*    stdout           = (char *)STDOUT;
+volatile uint32_t intr_count       = 0;
+#ifdef CPT_VERBOSITY
+    enum printf_verbosity             verbosity_g = CPT_VERBOSITY;
+#else
+    enum printf_verbosity             verbosity_g = LOW;
+#endif
+
+#define MBOX_DLEN_VAL             0x00000020
+
+volatile caliptra_intr_received_s cptra_intr_rcv = {
+    .doe_error        = 0,
+    .doe_notif        = 0,
+    .ecc_error        = 0,
+    .ecc_notif        = 0,
+    .hmac_error       = 0,
+    .hmac_notif       = 0,
+    .kv_error         = 0,
+    .kv_notif         = 0,
+    .sha512_error     = 0,
+    .sha512_notif     = 0,
+    .sha256_error     = 0,
+    .sha256_notif     = 0,
+    .qspi_error       = 0,
+    .qspi_notif       = 0,
+    .uart_error       = 0,
+    .uart_notif       = 0,
+    .i3c_error        = 0,
+    .i3c_notif        = 0,
+    .soc_ifc_error    = 0,
+    .soc_ifc_notif    = 0,
+    .sha512_acc_error = 0,
+    .sha512_acc_notif = 0,
+};
+
+void main () {
+
+    mbox_op_s op;
+    uint32_t ii;
+    uint32_t data;
+    enum mbox_fsm_e state;
+    uint32_t mbox_data[] = { 0x00000000,
+                             0x11111111,
+                             0x22222222,
+                             0x33333333,
+                             0x44444444,
+                             0x55555555,
+                             0x66666666,
+                             0x77777777 };
+    uint32_t read_data;
+
+    uint32_t mitb0 = 0x000000F0;
+    uint32_t mie_timer0_ext_int_en = 0x20000800;
+
+    // Message
+    VPRINTF(LOW, "----------------------------------\n");
+    VPRINTF(LOW, " Caliptra Mailbox Smoke Test!!\n"    );
+    VPRINTF(LOW, "----------------------------------\n");
+
+    // Call interrupt init
+    init_interrupts();
+
+    //Enable clk gating
+    SEND_STDOUT_CTRL(0xf2);
+
+    //set ready for FW so tb will push FW
+    soc_ifc_set_flow_status_field(SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_MASK);
+
+    set_mit0_and_halt_core(mitb0, mie_timer0_ext_int_en);
+
+    //wait for mailbox data avail
+    VPRINTF(LOW, "FW: Wait\n");
+    while((lsu_read_32(CLP_MBOX_CSR_MBOX_EXECUTE) & MBOX_CSR_MBOX_EXECUTE_EXECUTE_MASK) != MBOX_CSR_MBOX_EXECUTE_EXECUTE_MASK);
+
+    set_mit0_and_halt_core(mitb0, mie_timer0_ext_int_en);
+
+    //read mbox command
+    op = soc_ifc_read_mbox_cmd();
+
+    //read from mbox
+    VPRINTF(LOW, "FW: Reading %d bytes from mailbox\n", op.dlen);
+    while(op.dlen) {
+        data = soc_ifc_mbox_read_dataout_single();
+        VPRINTF(HIGH, "  dataout: 0x%x\n", data);
+        if (op.dlen < 4) {
+            op.dlen=0;
+        } else {
+            op.dlen-=4;//sizeof(uint32_t);
+        }
+    }
+
+    //push new data in like a response
+    VPRINTF(LOW, "FW: Writing %d bytes to mailbox\n", MBOX_DLEN_VAL);
+    for (ii = 0; ii < MBOX_DLEN_VAL/4; ii++) {
+        VPRINTF(HIGH, "  datain: 0x%x\n", mbox_data[ii]);
+        lsu_write_32(CLP_MBOX_CSR_MBOX_DATAIN,mbox_data[ii]);
+    }
+
+    //set data ready status
+    VPRINTF(LOW, "FW: Set data ready status\n");
+    lsu_write_32(CLP_MBOX_CSR_MBOX_STATUS,DATA_READY);
+
+    //Halt core while SoC is executing mbox flow
+    set_mit0_and_halt_core(mitb0, mie_timer0_ext_int_en);
+
+    //check FSM state, should be in EXECUTE_SOC
+    state = (lsu_read_32(CLP_MBOX_CSR_MBOX_STATUS) & MBOX_CSR_MBOX_STATUS_MBOX_FSM_PS_MASK) >> MBOX_CSR_MBOX_STATUS_MBOX_FSM_PS_LOW;
+    if (state != MBOX_EXECUTE_SOC) {
+        VPRINTF(ERROR, "ERROR: mailbox in unexpected state (%x) when expecting MBOX_EXECUTE_SOC (0x%x)\n", state, MBOX_EXECUTE_SOC);
+        SEND_STDOUT_CTRL( 0x1);
+        while(1);
+    } else {
+        VPRINTF(LOW, "FW: Mailbox in expected state, MBOX_EXECUTE_SOC, ending test with success\n");
+    }
+
+//--------------------------------------------------------------------------------------------
+    //Wait for SoC to reset execute reg
+    VPRINTF(LOW, "FW: Wait for SoC to reset execute register\n");
+    while((lsu_read_32(CLP_MBOX_CSR_MBOX_EXECUTE) & MBOX_CSR_MBOX_EXECUTE_EXECUTE_MASK) == 1);
+
+    //Force unlock
+    lsu_write_32(CLP_MBOX_CSR_MBOX_UNLOCK, MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK);
+
+    set_mit0_and_halt_core(mitb0, mie_timer0_ext_int_en);
+
+    //poll for mbox lock
+    while((lsu_read_32(CLP_MBOX_CSR_MBOX_LOCK) & MBOX_CSR_MBOX_LOCK_LOCK_MASK) == 1);
+
+    set_mit0_and_halt_core(mitb0, mie_timer0_ext_int_en);
+
+    //write command
+    lsu_write_32(CLP_MBOX_CSR_MBOX_CMD,0x12345678);
+
+    set_mit0_and_halt_core(mitb0, mie_timer0_ext_int_en);
+
+    //write dlen
+    lsu_write_32(CLP_MBOX_CSR_MBOX_DLEN,MBOX_DLEN_VAL);
+
+    set_mit0_and_halt_core(mitb0, mie_timer0_ext_int_en);
+
+    //write datain
+    VPRINTF(LOW, "FW: Writing %d bytes to mailbox\n", MBOX_DLEN_VAL);
+    for (ii = 0; ii < MBOX_DLEN_VAL/4; ii++) {
+        VPRINTF(HIGH, "  datain: 0x%x\n", mbox_data[ii]);
+        lsu_write_32(CLP_MBOX_CSR_MBOX_DATAIN,mbox_data[ii]);
+    }
+
+    set_mit0_and_halt_core(mitb0, mie_timer0_ext_int_en);
+
+    //set execute
+    lsu_write_32(CLP_MBOX_CSR_MBOX_EXECUTE, MBOX_CSR_MBOX_EXECUTE_EXECUTE_MASK);
+
+    set_mit0_and_halt_core(mitb0, mie_timer0_ext_int_en);
+
+    //Poll status until data ready is set
+    while((lsu_read_32(CLP_MBOX_CSR_MBOX_STATUS) & MBOX_CSR_MBOX_STATUS_STATUS_MASK) != DATA_READY);
+
+    set_mit0_and_halt_core(mitb0, mie_timer0_ext_int_en);
+
+    //check data 
+    VPRINTF(LOW, "FW: Checking %d bytes from mailbox as if return data\n", MBOX_DLEN_VAL);
+    for (ii = 0; ii < MBOX_DLEN_VAL/4; ii++) {
+        if (ii % 4 == 0){
+            set_mit0_and_halt_core(mitb0, mie_timer0_ext_int_en);
+        }
+        VPRINTF(HIGH, "  datain: 0x%x\n", mbox_data[ii]);
+        read_data = lsu_read_32(CLP_MBOX_CSR_MBOX_DATAOUT);
+        if (read_data != mbox_data[ii]) {
+            VPRINTF(ERROR, "ERROR: mailbox data mismatch actual (0x%x) expected (0x%x)\n", read_data, mbox_data[ii]);
+            SEND_STDOUT_CTRL( 0x1);
+            while(1);
+        };
+    }
+
+    set_mit0_and_halt_core(mitb0, mie_timer0_ext_int_en);
+}
diff --git a/src/integration/test_suites/smoke_test_mbox_cg/smoke_test_mbox_cg.yml b/src/integration/test_suites/smoke_test_mbox_cg/smoke_test_mbox_cg.yml
new file mode 100755
index 000000000..9d8ef527c
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_mbox_cg/smoke_test_mbox_cg.yml
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+---
+seed: 1
+testname: smoke_test_mbox_cg
diff --git a/src/integration/test_suites/smoke_test_pcr_signing/caliptra_isr.h b/src/integration/test_suites/smoke_test_pcr_signing/caliptra_isr.h
index 6ffd71c0a..8f5779e04 100644
--- a/src/integration/test_suites/smoke_test_pcr_signing/caliptra_isr.h
+++ b/src/integration/test_suites/smoke_test_pcr_signing/caliptra_isr.h
@@ -204,6 +204,22 @@ inline void service_soc_ifc_notif_intr () {
         *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
         cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
     }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
     if (sts == 0) {
         VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
         SEND_STDOUT_CTRL(0x1);
diff --git a/src/integration/test_suites/smoke_test_pcr_zeroize/caliptra_isr.h b/src/integration/test_suites/smoke_test_pcr_zeroize/caliptra_isr.h
new file mode 100644
index 000000000..8f5779e04
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_pcr_zeroize/caliptra_isr.h
@@ -0,0 +1,247 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// ---------------------------------------------------------------------
+// File: caliptra_isr.h
+// Description:
+//     Provides function declarations for use by external test files, so
+//     that the ISR functionality may behave like a library.
+//     TODO:
+//     This header file includes inline function definitions for event and
+//     test specific interrupt service behavior, so it should be copied and
+//     modified for each test.
+// ---------------------------------------------------------------------
+
+#ifndef CALIPTRA_ISR_H
+    #define CALIPTRA_ISR_H
+
+#define EN_ISR_PRINTS 1
+
+#include "caliptra_defines.h"
+#include <stdint.h>
+#include "printf.h"
+
+/* --------------- symbols/typedefs --------------- */
+typedef struct {
+    uint32_t doe_error;
+    uint32_t doe_notif;
+    uint32_t ecc_error;
+    uint32_t ecc_notif;
+    uint32_t hmac_error;
+    uint32_t hmac_notif;
+    uint32_t kv_error;
+    uint32_t kv_notif;
+    uint32_t sha512_error;
+    uint32_t sha512_notif;
+    uint32_t sha256_error;
+    uint32_t sha256_notif;
+    uint32_t qspi_error;
+    uint32_t qspi_notif;
+    uint32_t uart_error;
+    uint32_t uart_notif;
+    uint32_t i3c_error;
+    uint32_t i3c_notif;
+    uint32_t soc_ifc_error;
+    uint32_t soc_ifc_notif;
+    uint32_t sha512_acc_error;
+    uint32_t sha512_acc_notif;
+} caliptra_intr_received_s;
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
+
+//////////////////////////////////////////////////////////////////////////////
+// Function Declarations
+//
+
+// Performs all the CSR setup to configure and enable vectored external interrupts
+void init_interrupts(void);
+
+// These inline functions are used to insert event-specific functionality into the
+// otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr"
+inline void service_doe_error_intr() {return;}
+inline void service_doe_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.doe_notif |= DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad doe_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_ecc_error_intr() {return;}
+inline void service_ecc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.ecc_notif |= ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad ecc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_hmac_error_intr() {return;}
+inline void service_hmac_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.hmac_notif |= HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad hmac_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_kv_error_intr() {return;}
+inline void service_kv_notif_intr() {return;}
+inline void service_sha512_error_intr() {return;}
+inline void service_sha512_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_notif |= SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha256_error_intr() {return;}
+inline void service_sha256_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha256_notif |= SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha256_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_qspi_error_intr() {return;}
+inline void service_qspi_notif_intr() {return;}
+inline void service_uart_error_intr() {return;}
+inline void service_uart_notif_intr() {return;}
+inline void service_i3c_error_intr() {return;}
+inline void service_i3c_notif_intr() {return;}
+
+inline void service_soc_ifc_error_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_error_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_soc_ifc_notif_intr () {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha512_acc_error_intr() {return;}
+inline void service_sha512_acc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_acc_notif |= SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_acc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+
+#endif //CALIPTRA_ISR_H
diff --git a/src/integration/test_suites/smoke_test_pcr_zeroize/smoke_test_pcr_zeroize.c b/src/integration/test_suites/smoke_test_pcr_zeroize/smoke_test_pcr_zeroize.c
new file mode 100644
index 000000000..2ff485ee4
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_pcr_zeroize/smoke_test_pcr_zeroize.c
@@ -0,0 +1,276 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+
+#include "caliptra_defines.h"
+#include "caliptra_isr.h"
+#include "riscv_hw_if.h"
+#include "riscv-csr.h"
+#include "printf.h"
+#include "ecc.h"
+
+volatile char*    stdout           = (char *)STDOUT;
+volatile uint32_t intr_count = 0;
+#ifdef CPT_VERBOSITY
+    enum printf_verbosity verbosity_g = CPT_VERBOSITY;
+#else
+    enum printf_verbosity verbosity_g = LOW;
+#endif
+
+volatile caliptra_intr_received_s cptra_intr_rcv = {
+    .doe_error        = 0,
+    .doe_notif        = 0,
+    .ecc_error        = 0,
+    .ecc_notif        = 0,
+    .hmac_error       = 0,
+    .hmac_notif       = 0,
+    .kv_error         = 0,
+    .kv_notif         = 0,
+    .sha512_error     = 0,
+    .sha512_notif     = 0,
+    .sha256_error     = 0,
+    .sha256_notif     = 0,
+    .qspi_error       = 0,
+    .qspi_notif       = 0,
+    .uart_error       = 0,
+    .uart_notif       = 0,
+    .i3c_error        = 0,
+    .i3c_notif        = 0,
+    .soc_ifc_error    = 0,
+    .soc_ifc_notif    = 0,
+    .sha512_acc_error = 0,
+    .sha512_acc_notif = 0,
+};
+
+/* ECC test vector:
+    MSG      = C8F518D4F3AA1BD46ED56C1C3C9E16FB800AF504DB98843548C5F623EE115F73D4C62ABC06D303B5D90D9A175087290D
+    PRIVKEY  = F274F69D163B0C9F1FC3EBF4292AD1C4EB3CEC1C5A7DDE6F80C14292934C2055E087748D0A169C772483ADEE5EE70E17
+    PUBKEY_X = D79C6D972B34A1DFC916A7B6E0A99B6B5387B34DA2187607C1AD0A4D1A8C2E4172AB5FA5D9AB58FE45E43F56BBB66BA4
+    PUBKEY_Y = 5A7363932B06B4F223BEF0B60A6390265112DBBD0AAE67FEF26B465BE935B48E451E68D16F1118F2B32B4C28608749ED
+    SEED     = 8FA8541C82A392CA74F23ED1DBFD73541C5966391B97EA73D744B0E34B9DF59ED0158063E39C09A5A055371EDF7A5441
+    NONCE    = 1B7EC5E548E8AAA92EC77097CA9551C9783CE682CA18FB1EDBD9F1E50BC382DB8AB39496C8EE423F8CA105CBBA7B6588
+    Sign_R   = 871E6EA4DDC5432CDDAA60FD7F055472D3C4DD41A5BFB26709E88C311A97093599A7C8F55B3974C19E4F5A7BFC1DD2AC
+    SIGN_S   = 3E5552DE6403350EE70AD74E4B854D2DC4126BBF9C153A5D7A07BD4B85D06E45F850920E898FB7D34F80796DAE29365C
+    IV       = 3401CEFAE20A737649073AC1A351E32926DB9ED0DB6B1CFFAB0493DAAFB93DDDD83EDEA28A803D0D003B2633B9D0F1BF
+*/
+
+void main(){
+
+    printf("----------------------------------\n");
+    printf(" Smoke Test With PCR Signing flow !!\n");
+    printf("----------------------------------\n");
+
+    uint32_t ecc_msg[] =           {0xC8F518D4,
+                                    0xF3AA1BD4,
+                                    0x6ED56C1C,
+                                    0x3C9E16FB,
+                                    0x800AF504,
+                                    0xDB988435,
+                                    0x48C5F623,
+                                    0xEE115F73,
+                                    0xD4C62ABC,
+                                    0x06D303B5,
+                                    0xD90D9A17,
+                                    0x5087290D};
+
+    uint32_t expected_pubkey_x[] = {0xD79C6D97,
+                                    0x2B34A1DF,
+                                    0xC916A7B6,
+                                    0xE0A99B6B,
+                                    0x5387B34D,
+                                    0xA2187607,
+                                    0xC1AD0A4D,
+                                    0x1A8C2E41,
+                                    0x72AB5FA5,
+                                    0xD9AB58FE,
+                                    0x45E43F56,
+                                    0xBBB66BA4};
+
+    uint32_t expected_pubkey_y[] = {0x5A736393,
+                                    0x2B06B4F2,
+                                    0x23BEF0B6,
+                                    0x0A639026,
+                                    0x5112DBBD,
+                                    0x0AAE67FE,
+                                    0xF26B465B,
+                                    0xE935B48E,
+                                    0x451E68D1,
+                                    0x6F1118F2,
+                                    0xB32B4C28,
+                                    0x608749ED};
+
+    uint32_t ecc_nonce[] =         {0x1B7EC5E5,
+                                    0x48E8AAA9,
+                                    0x2EC77097,
+                                    0xCA9551C9,
+                                    0x783CE682,
+                                    0xCA18FB1E,
+                                    0xDBD9F1E5,
+                                    0x0BC382DB,
+                                    0x8AB39496,
+                                    0xC8EE423F,
+                                    0x8CA105CB,
+                                    0xBA7B6588};
+
+    uint32_t expected_sign_r[] =   {0x871E6EA4,
+                                    0xDDC5432C,
+                                    0xDDAA60FD,
+                                    0x7F055472,
+                                    0xD3C4DD41,
+                                    0xA5BFB267,
+                                    0x09E88C31,
+                                    0x1A970935,
+                                    0x99A7C8F5,
+                                    0x5B3974C1,
+                                    0x9E4F5A7B,
+                                    0xFC1DD2AC};
+
+    uint32_t expected_sign_s[] =   {0x3E5552DE,
+                                    0x6403350E,
+                                    0xE70AD74E,
+                                    0x4B854D2D,
+                                    0xC4126BBF,
+                                    0x9C153A5D,
+                                    0x7A07BD4B,
+                                    0x85D06E45,
+                                    0xF850920E,
+                                    0x898FB7D3,
+                                    0x4F80796D,
+                                    0xAE29365C};
+
+    
+    uint32_t ecc_iv[] =            {0x3401CEFA,
+                                    0xE20A7376,
+                                    0x49073AC1,
+                                    0xA351E329,
+                                    0x26DB9ED0,
+                                    0xDB6B1CFF,
+                                    0xAB0493DA,
+                                    0xAFB93DDD,
+                                    0xD83EDEA2,
+                                    0x8A803D0D,
+                                    0x003B2633,
+                                    0xB9D0F1BF};
+    //Call interrupt init
+    init_interrupts();
+
+    uint8_t offset;
+    volatile uint32_t * reg_ptr;
+    uint8_t fail_cmd = 0x1;
+
+    // wait for ECC to be ready
+    while((lsu_read_32(CLP_ECC_REG_ECC_STATUS) & ECC_REG_ECC_STATUS_READY_MASK) == 0);
+
+    //inject seed to kv key reg (in RTL)
+    printf("Inject PRIVKEY into KV slot 7\n");
+    uint8_t privkey_inject_cmd = 0x88 + 0x7;
+    printf("%c", privkey_inject_cmd);
+
+    printf("Inject MSG into SHA512 digest\n");
+    printf("%c", 0x90);
+
+    // Program ECC IV
+    reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_IV_0;
+    offset = 0;
+    while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_IV_11) {
+        *reg_ptr++ = ecc_iv[offset++];
+    }
+
+    // Enable ECC PCR SIGNING core
+    printf("\nECC PCR SIGNING\n");
+    lsu_write_32(CLP_ECC_REG_ECC_CTRL, ECC_CMD_SIGNING | 
+                ((1 << ECC_REG_ECC_CTRL_PCR_SIGN_LOW) & ECC_REG_ECC_CTRL_PCR_SIGN_MASK) |
+                ((1 << ECC_REG_ECC_CTRL_ZEROIZE_LOW) & ECC_REG_ECC_CTRL_ZEROIZE_MASK));
+    
+    // wait for ECC to be ready
+    while((lsu_read_32(CLP_ECC_REG_ECC_STATUS) & ECC_REG_ECC_STATUS_READY_MASK) == 0);
+
+
+    printf("Load SIGN_R data from ECC\n");
+    reg_ptr = (uint32_t *) CLP_ECC_REG_ECC_SIGN_R_0;
+    offset = 0;
+    while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_SIGN_R_11) {
+        if (*reg_ptr != 0) {
+            printf("At offset [%d], ecc_sign_r data mismatch!\n", offset);
+            printf("Actual   data: 0x%x\n", *reg_ptr);
+            printf("%c", fail_cmd);
+            while(1);
+        }
+        reg_ptr++;
+        offset++;
+    }
+
+    printf("Load SIGN_S data from ECC\n");
+    reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_SIGN_S_0;
+    offset = 0;
+    while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_SIGN_S_11) {
+        if (*reg_ptr != 0) {
+            printf("At offset [%d], ecc_sign_s data mismatch!\n", offset);
+            printf("Actual   data: 0x%x\n", *reg_ptr);
+            printf("%c", fail_cmd);
+            while(1);
+        } 
+        reg_ptr++;
+        offset++;
+    }
+
+
+
+    // wait for ECC to be ready
+    while((lsu_read_32(CLP_ECC_REG_ECC_STATUS) & ECC_REG_ECC_STATUS_READY_MASK) == 0);
+
+    //inject seed to kv key reg (in RTL)
+    printf("Inject PRIVKEY into KV slot 7\n");
+    printf("%c", privkey_inject_cmd);
+
+    printf("Inject MSG into SHA512 digest\n");
+    printf("%c", 0x90);
+
+    // Program ECC IV
+    reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_IV_0;
+    offset = 0;
+    while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_IV_11) {
+        *reg_ptr++ = ecc_iv[offset++];
+    }
+
+    // Enable ECC PCR SIGNING core
+    printf("\nECC PCR SIGNING\n");
+    lsu_write_32(CLP_ECC_REG_ECC_CTRL, ECC_CMD_SIGNING | 
+                ((1 << ECC_REG_ECC_CTRL_PCR_SIGN_LOW) & ECC_REG_ECC_CTRL_PCR_SIGN_MASK));
+    
+    //delay
+    for (int delay_cnt=0; delay_cnt<10000; delay_cnt++);
+
+    //zeroize
+    lsu_write_32(CLP_ECC_REG_ECC_CTRL, ((1 << ECC_REG_ECC_CTRL_ZEROIZE_LOW) & ECC_REG_ECC_CTRL_ZEROIZE_MASK));
+    
+    // wait for ECC to be ready
+    while((lsu_read_32(CLP_ECC_REG_ECC_STATUS) & ECC_REG_ECC_STATUS_READY_MASK) == 0);
+
+    printf("Load SIGN_R data from ECC\n");
+    reg_ptr = (uint32_t *) CLP_ECC_REG_ECC_SIGN_R_0;
+    offset = 0;
+    while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_SIGN_R_11) {
+        if (*reg_ptr != 0) {
+            printf("At offset [%d], ecc_sign_r data mismatch!\n", offset);
+            printf("Actual   data: 0x%x\n", *reg_ptr);
+            printf("%c", fail_cmd);
+            while(1);
+        }
+        reg_ptr++;
+        offset++;
+    }
+
+    printf("%c",0xff); //End the test
+}
diff --git a/src/integration/test_suites/smoke_test_pcr_zeroize/smoke_test_pcr_zeroize.yml b/src/integration/test_suites/smoke_test_pcr_zeroize/smoke_test_pcr_zeroize.yml
new file mode 100644
index 000000000..553271ac3
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_pcr_zeroize/smoke_test_pcr_zeroize.yml
@@ -0,0 +1,4 @@
+---
+# Random seed desired...
+seed: 1
+testname: smoke_test_pcr_zeroize
\ No newline at end of file
diff --git a/src/integration/test_suites/smoke_test_qspi/caliptra_isr.h b/src/integration/test_suites/smoke_test_qspi/caliptra_isr.h
index 23b511c4b..fca82fef0 100644
--- a/src/integration/test_suites/smoke_test_qspi/caliptra_isr.h
+++ b/src/integration/test_suites/smoke_test_qspi/caliptra_isr.h
@@ -32,39 +32,212 @@
 #include <stdint.h>
 #include "printf.h"
 
-//extern volatile uint32_t hmac_intr_status;
+/* --------------- symbols/typedefs --------------- */
+typedef struct {
+    uint32_t doe_error;
+    uint32_t doe_notif;
+    uint32_t ecc_error;
+    uint32_t ecc_notif;
+    uint32_t hmac_error;
+    uint32_t hmac_notif;
+    uint32_t kv_error;
+    uint32_t kv_notif;
+    uint32_t sha512_error;
+    uint32_t sha512_notif;
+    uint32_t sha256_error;
+    uint32_t sha256_notif;
+    uint32_t qspi_error;
+    uint32_t qspi_notif;
+    uint32_t uart_error;
+    uint32_t uart_notif;
+    uint32_t i3c_error;
+    uint32_t i3c_notif;
+    uint32_t soc_ifc_error;
+    uint32_t soc_ifc_notif;
+    uint32_t sha512_acc_error;
+    uint32_t sha512_acc_notif;
+} caliptra_intr_received_s;
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
 
 //////////////////////////////////////////////////////////////////////////////
 // Function Declarations
 //
+
 // Performs all the CSR setup to configure and enable vectored external interrupts
 void init_interrupts(void);
 
 // These inline functions are used to insert event-specific functionality into the
-// otherwise generic ISR that gets laid down by the parameterized macro "nonstd_swerv_isr"
-inline void service_doe_error_intr() {printf("ERROR");}
-inline void service_doe_notif_intr() {printf("ERROR");}
-inline void service_ecc_error_intr   () {printf("ERROR");}
-inline void service_ecc_notif_intr   () {printf("ERROR");}
-inline void service_hmac_error_intr  () {printf("ERROR");}
-inline void service_hmac_notif_intr  () {printf("ERROR");}
-
-inline void service_kv_error_intr    () {printf("ERROR");}
-inline void service_kv_notif_intr    () {printf("ERROR");}
-inline void service_sha512_error_intr() {printf("ERROR");}
-inline void service_sha512_notif_intr() {printf("ERROR");}
-inline void service_sha256_error_intr() {printf("ERROR");}
-inline void service_sha256_notif_intr() {printf("ERROR");}
-inline void service_qspi_error_intr  () {printf("ERROR");}
-inline void service_qspi_notif_intr  () {printf("ERROR");}
-inline void service_uart_error_intr  () {printf("ERROR");}
-inline void service_uart_notif_intr  () {printf("ERROR");}
-inline void service_i3c_error_intr   () {printf("ERROR");}
-inline void service_i3c_notif_intr   () {printf("ERROR");}
-inline void service_soc_ifc_error_intr  () {printf("ERROR");}
-inline void service_soc_ifc_notif_intr  () {printf("ERROR");}
-inline void service_sha512_acc_error_intr() {printf("ERROR");}
-inline void service_sha512_acc_notif_intr() {printf("ERROR");}
+// otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr"
+inline void service_doe_error_intr() {return;}
+inline void service_doe_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.doe_notif |= DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad doe_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_ecc_error_intr() {return;}
+inline void service_ecc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.ecc_notif |= ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad ecc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_hmac_error_intr() {return;}
+inline void service_hmac_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.hmac_notif |= HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad hmac_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_kv_error_intr() {return;}
+inline void service_kv_notif_intr() {return;}
+inline void service_sha512_error_intr() {return;}
+inline void service_sha512_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_notif |= SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha256_error_intr() {return;}
+inline void service_sha256_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha256_notif |= SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha256_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_qspi_error_intr() {return;}
+inline void service_qspi_notif_intr() {return;}
+inline void service_uart_error_intr() {return;}
+inline void service_uart_notif_intr() {return;}
+inline void service_i3c_error_intr() {return;}
+inline void service_i3c_notif_intr() {return;}
+
+inline void service_soc_ifc_error_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_error_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_soc_ifc_notif_intr () {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha512_acc_error_intr() {return;}
+inline void service_sha512_acc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_acc_notif |= SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_acc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
 
 
 #endif //CALIPTRA_ISR_H
diff --git a/src/integration/test_suites/smoke_test_qspi/smoke_test_qspi.c b/src/integration/test_suites/smoke_test_qspi/smoke_test_qspi.c
index 2ddae7c85..babe4f400 100644
--- a/src/integration/test_suites/smoke_test_qspi/smoke_test_qspi.c
+++ b/src/integration/test_suites/smoke_test_qspi/smoke_test_qspi.c
@@ -31,6 +31,31 @@ enum printf_verbosity verbosity_g = CPT_VERBOSITY;
 enum printf_verbosity verbosity_g = LOW;
 #endif
 
+volatile caliptra_intr_received_s cptra_intr_rcv = {
+    .doe_error        = 0,
+    .doe_notif        = 0,
+    .ecc_error        = 0,
+    .ecc_notif        = 0,
+    .hmac_error       = 0,
+    .hmac_notif       = 0,
+    .kv_error         = 0,
+    .kv_notif         = 0,
+    .sha512_error     = 0,
+    .sha512_notif     = 0,
+    .sha256_error     = 0,
+    .sha256_notif     = 0,
+    .qspi_error       = 0,
+    .qspi_notif       = 0,
+    .uart_error       = 0,
+    .uart_notif       = 0,
+    .i3c_error        = 0,
+    .i3c_notif        = 0,
+    .soc_ifc_error    = 0,
+    .soc_ifc_notif    = 0,
+    .sha512_acc_error = 0,
+    .sha512_acc_notif = 0,
+};
+
 typedef enum { Dummy = 0, RdOnly = 1, WrOnly = 2, BiDir = 3 } direction_t;
 typedef enum { Standard = 0, Dual = 1, Quad = 2 } speed_t;
 typedef enum { CmdJedecId = 0x9f, CmdReadQuad = 0x6b } cmd_spi_t;
diff --git a/src/integration/test_suites/smoke_test_ras/caliptra_isr.h b/src/integration/test_suites/smoke_test_ras/caliptra_isr.h
new file mode 100644
index 000000000..a245e2994
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_ras/caliptra_isr.h
@@ -0,0 +1,199 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// ---------------------------------------------------------------------
+// File: caliptra_isr.h
+// Description:
+//     Provides function declarations for use by external test files, so
+//     that the ISR functionality may behave like a library.
+//     TODO:
+//     This header file includes inline function definitions for event and
+//     test specific interrupt service behavior, so it should be copied and
+//     modified for each test.
+// ---------------------------------------------------------------------
+
+#ifndef CALIPTRA_ISR_H
+    #define CALIPTRA_ISR_H
+
+#include "caliptra_reg.h"
+#include <stdint.h>
+#include "printf.h"
+#include "riscv_hw_if.h"
+
+/* --------------- symbols/typedefs --------------- */
+typedef struct {
+    uint32_t doe_error;
+    uint32_t doe_notif;
+    uint32_t ecc_error;
+    uint32_t ecc_notif;
+    uint32_t hmac_error;
+    uint32_t hmac_notif;
+    uint32_t kv_error;
+    uint32_t kv_notif;
+    uint32_t sha512_error;
+    uint32_t sha512_notif;
+    uint32_t sha256_error;
+    uint32_t sha256_notif;
+    uint32_t qspi_error;
+    uint32_t qspi_notif;
+    uint32_t uart_error;
+    uint32_t uart_notif;
+    uint32_t i3c_error;
+    uint32_t i3c_notif;
+    uint32_t soc_ifc_error;
+    uint32_t soc_ifc_notif;
+    uint32_t sha512_acc_error;
+    uint32_t sha512_acc_notif;
+} caliptra_intr_received_s;
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
+#define RV_EXCEPTION_STRUCT 1
+typedef struct {
+    uint8_t  exception_hit;
+    uint32_t mcause;
+    uint32_t mscause;
+} rv_exception_struct_s;
+
+/* --------------- Function Declarations --------------- */
+
+// Performs all the CSR setup to configure and enable vectored external interrupts
+void init_interrupts(void);
+
+// These inline functions are used to insert event-specific functionality into the
+// otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr"
+inline void service_doe_error_intr() {return;}
+inline void service_doe_notif_intr() {return;}
+
+inline void service_ecc_error_intr() {return;}
+inline void service_ecc_notif_intr() {return;}
+
+inline void service_hmac_error_intr() {return;}
+inline void service_hmac_notif_intr() {return;}
+
+inline void service_kv_error_intr() {return;}
+inline void service_kv_notif_intr() {return;}
+inline void service_sha512_error_intr() {return;}
+inline void service_sha512_notif_intr() {return;}
+
+inline void service_sha256_error_intr() {return;}
+inline void service_sha256_notif_intr() {return;}
+
+inline void service_qspi_error_intr() {return;}
+inline void service_qspi_notif_intr() {return;}
+inline void service_uart_error_intr() {return;}
+inline void service_uart_notif_intr() {return;}
+inline void service_i3c_error_intr() {return;}
+inline void service_i3c_notif_intr() {return;}
+
+inline void service_soc_ifc_error_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_error_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_soc_ifc_notif_intr () {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
+        VPRINTF(HIGH, "cmd_avail\n");
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK) {
+        VPRINTF(HIGH, "mbox_ecc_cor\n");
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        VPRINTF(HIGH, "debug_locked\n");
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        VPRINTF(HIGH, "SCAN_MODE\n");
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        VPRINTF(HIGH, "soc_req_lock\n");
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        VPRINTF(HIGH, "gen_in_toggle\n");
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha512_acc_error_intr() {return;}
+inline void service_sha512_acc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_acc_notif |= SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_acc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+
+#endif //CALIPTRA_ISR_H
diff --git a/src/integration/test_suites/smoke_test_ras/smoke_test_ras.c b/src/integration/test_suites/smoke_test_ras/smoke_test_ras.c
new file mode 100644
index 000000000..593b92d3e
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_ras/smoke_test_ras.c
@@ -0,0 +1,1093 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+
+// DESCRIPTION:
+//   Test Reliability, Availability, Servicability (RAS) features in
+//   Caliptra SOC Interface
+//   Test objectives:
+//     1. Demonstrate all reported events can be properly detected and reported
+//        to uC
+//     2. Demonstrate correct reset behavior for FATAL and NON_FATAL events
+//        (a) FATAL events must result in a Caliptra system reset (by SOC i.e.
+//            the testbench)
+//        (b) Following a reset, no further interrupt observed; SOC manually
+//            clears ERROR reg
+//        (c) NON_FATAL events should be observed and cleared by SOC
+//     3. Demonstrate correct behavior of the error mask registers, which should
+//        prevent error assertion
+//        (a) When masked, ERROR register bits should be set, not generate an
+//            interrupt, and then the uC should reset them
+//
+//   Several of the above features may only be properly validated in concert
+//   with Testbench level code that confirms signal behavior and drives resets
+//   as required.
+//   That behavior is requested by FW via writes to GENERIC_OUTPUT_WIRES (which
+//   currently operates as STDOUT in sims)
+//   The TB may also signal response activity by driving GENERIC_INPUT_WIRES
+//   (resulting in interrupt to uC)
+//
+
+#include "caliptra_defines.h"
+#include "caliptra_isr.h"
+#include "riscv_hw_if.h"
+#include "riscv-interrupts.h"
+#include "riscv-csr.h"
+#include "veer-csr.h"
+#include <string.h>
+#include <stdint.h>
+#include "printf.h"
+
+////////////////////////////////////////////////////////////////////
+// Typedefs
+//
+
+// Matches the STDOUT code value as decoded in caliptra_top_tb_services
+enum ecc_error_mode_type {
+    ERROR_NONE  = 0xe4,
+    ICCM_SINGLE = 0xe0,
+    ICCM_DOUBLE = 0xe1,
+    DCCM_SINGLE = 0xe2,
+    DCCM_DOUBLE = 0xe3,
+    MBOX_SINGLE = 0xfd,
+    MBOX_DOUBLE = 0xfe
+};
+
+// Value driven by TB to GENERIC_INPUT_WIRES
+enum tb_resp_value {
+    MBOX_NON_FATAL_OBSERVED         = 0x600dab1e,
+    PROT_NO_LOCK_NON_FATAL_OBSERVED = 0x600dbabe,
+    PROT_OOO_NON_FATAL_OBSERVED     = 0x600dcafe,
+    ICCM_FATAL_OBSERVED             = 0xdeadaca1,
+    DCCM_FATAL_OBSERVED             = 0xdeadbeef,
+    NMI_FATAL_OBSERVED              = 0xdeadc0a7,
+    ERROR_NONE_SET                  = 0xba5eba11, /* default value for a test with no activity observed by TB */
+};
+
+enum mask_config {
+    WITH_MASK,
+    NO_MASK
+};
+
+enum recovery_config {
+    WARM_RESET,
+    FORCE_UNLOCK
+};
+
+enum test_status {
+    SUCCESS          =       0,
+    INTR_COUNT_0     = 1 <<  0,
+    INTR_COR_COUNT_0 = 1 <<  1,
+    INTR_UNC_COUNT_0 = 1 <<  2,
+    BAD_EXCP_CODE    = 1 <<  3,
+    UNEXP_ARG        = 1 <<  4,
+    BAD_CPTRA_SIG    = 1 <<  5,
+    INV_STATE        = 1 <<  6,
+};
+
+enum test_progress {
+    NOT_STARTED,
+    RUN_NOT_CHECKED,
+    RUN_AND_FAILED,
+    RUN_AND_PASSED
+};
+
+// Used to index into the global array of test progress
+// TODO Test the FW FATAL/NON_FATAL regs
+enum test_list {
+    MBOX_SRAM_ECC_SINGLE_UNMASKED,
+    MBOX_SRAM_ECC_DOUBLE_UNMASKED,
+    MBOX_SRAM_ECC_SINGLE_MASKED  ,
+    MBOX_SRAM_ECC_DOUBLE_MASKED  ,
+    ICCM_SRAM_ECC_SINGLE_UNMASKED,
+    ICCM_SRAM_ECC_DOUBLE_UNMASKED,
+    ICCM_SRAM_ECC_SINGLE_MASKED  ,
+    ICCM_SRAM_ECC_DOUBLE_MASKED  ,
+    DCCM_SRAM_ECC_SINGLE_UNMASKED,
+    DCCM_SRAM_ECC_DOUBLE_UNMASKED,
+    DCCM_SRAM_ECC_SINGLE_MASKED  ,
+    DCCM_SRAM_ECC_DOUBLE_MASKED  ,
+    NMI_UNMASKED                 ,
+    NMI_MASKED                   ,
+    PROT_NO_LOCK_UNMASKED        ,
+    PROT_NO_LOCK_MASKED          ,
+    PROT_OOO_UNMASKED            ,
+    PROT_OOO_MASKED              ,
+    TEST_COUNT                   ,
+};
+enum boot_count_list {
+    BEFORE_FIRST_ICCM_FAILURE  = 1,
+    BEFORE_SECOND_ICCM_FAILURE    ,
+    BEFORE_FIRST_DCCM_FAILURE     ,
+    BEFORE_FIRST_NMI_FAILURE      ,
+    BEFORE_SECOND_NMI_FAILURE     ,
+    AFTER_SECOND_NMI_FAILURE      ,
+    AFTER_FIRST_MBOX_OOO_FAILURE  ,
+    AFTER_SECOND_MBOX_OOO_FAILURE
+};
+//enum boot_count_list {
+//    RUN_MBOX_AND_FIRST_ICCM_SRAM_ECC  = 1,
+//    RUN_AND_CHK_ICCM_SRAM_ECC_MASKED     ,
+//    RUN_DCCM_SRAM_ECC_UNMASKED           ,
+//    RUN_AND_CHK_DCCM_SRAM_ECC_MASKED     ,
+//    RUN_AND_CHK_NMI_MASKED               ,
+//    RUN_AND_CHK_MBOX_PROT_ERROR          ,
+//};
+
+////////////////////////////////////////////////////////////////////
+// Globals
+//
+extern uintptr_t iccm_code0_start, iccm_code0_end;
+volatile char* stdout = (char *)STDOUT;
+#ifdef CPT_VERBOSITY
+    enum printf_verbosity verbosity_g = CPT_VERBOSITY;
+#else
+    enum printf_verbosity verbosity_g = HIGH;
+#endif
+
+volatile uint32_t intr_count;
+volatile caliptra_intr_received_s cptra_intr_rcv = {
+    .doe_error        = 0,
+    .doe_notif        = 0,
+    .ecc_error        = 0,
+    .ecc_notif        = 0,
+    .hmac_error       = 0,
+    .hmac_notif       = 0,
+    .kv_error         = 0,
+    .kv_notif         = 0,
+    .sha512_error     = 0,
+    .sha512_notif     = 0,
+    .sha256_error     = 0,
+    .sha256_notif     = 0,
+    .qspi_error       = 0,
+    .qspi_notif       = 0,
+    .uart_error       = 0,
+    .uart_notif       = 0,
+    .i3c_error        = 0,
+    .i3c_notif        = 0,
+    .soc_ifc_error    = 0,
+    .soc_ifc_notif    = 0,
+    .sha512_acc_error = 0,
+    .sha512_acc_notif = 0,
+};
+volatile rv_exception_struct_s exc_flag __attribute__((section(".dccm.persistent"))); // WARNING: if DCCM ERROR injection is enabled, writes to this may be corrupted
+volatile uint32_t boot_count __attribute__((section(".dccm.persistent"))) = 0;
+volatile uint32_t generic_input_wires_0_before_rst __attribute__((section(".dccm.persistent")));
+// Track test progress across resets by allocating the variable in DCCM, which
+// is initialized only once at time 0
+enum test_progress test_progress_g[TEST_COUNT] __attribute__((section(".dccm.persistent"))) = {
+    NOT_STARTED,
+    NOT_STARTED,
+    NOT_STARTED,
+    NOT_STARTED,
+    NOT_STARTED,
+    NOT_STARTED,
+    NOT_STARTED,
+    NOT_STARTED,
+    NOT_STARTED,
+    NOT_STARTED,
+    NOT_STARTED,
+    NOT_STARTED,
+    NOT_STARTED,
+    NOT_STARTED
+};
+
+
+////////////////////////////////////////////////////////////////////
+// Function Prototypes
+//
+/* MBOX ECC */
+void     run_mbox_sram_ecc  (enum ecc_error_mode_type type, enum mask_config test_mask);
+uint32_t check_mbox_sram_ecc(enum ecc_error_mode_type type, enum mask_config test_mask);
+uint32_t test_mbox_sram_ecc       (enum mask_config test_mask);
+
+/* ICCM ECC */
+uint32_t run_iccm_sram_ecc        (enum mask_config test_mask);
+uint32_t check_iccm_sram_ecc      (enum mask_config test_mask);
+
+/* DCCM ECC */
+uint32_t run_dccm_sram_ecc        (enum mask_config test_mask);
+uint32_t check_dccm_sram_ecc      (enum mask_config test_mask);
+
+/* MBOX PROT */
+void     run_mbox_no_lock_error  (enum mask_config test_mask);
+uint32_t check_mbox_no_lock_error(enum mask_config test_mask);
+void     run_mbox_ooo_error      (enum mask_config test_mask);
+uint32_t check_mbox_ooo_error    (enum mask_config test_mask);
+
+/* NMI */
+void     run_nmi_test             (enum mask_config test_mask);
+uint32_t check_nmi_test           (enum mask_config test_mask);
+
+/* Supporting code */
+void nmi_handler       (void);
+void execute_from_iccm (void) __attribute__ ((aligned(4),section (".data_iccm0")));
+
+
+////////////////////////////////////////////////////////////////////
+// Function Definitions
+//
+void run_mbox_sram_ecc(enum ecc_error_mode_type type, enum mask_config test_mask) {
+    enum test_list cur_test;
+
+    VPRINTF(MEDIUM, "\n*** Run Mbox SRAM ECC Err ***\n  Type: %s\n  Masked: %d\n\n", (type == MBOX_SINGLE) ? "1-bit" : "2-bit", test_mask == WITH_MASK);
+
+    // Grab test enum
+    if      (type == MBOX_SINGLE && test_mask == WITH_MASK) { cur_test = MBOX_SRAM_ECC_SINGLE_MASKED;   }
+    else if (type == MBOX_SINGLE && test_mask == NO_MASK)   { cur_test = MBOX_SRAM_ECC_SINGLE_UNMASKED; }
+    else if (type == MBOX_DOUBLE && test_mask == WITH_MASK) { cur_test = MBOX_SRAM_ECC_DOUBLE_MASKED;   }
+    else if (type == MBOX_DOUBLE && test_mask == NO_MASK)   { cur_test = MBOX_SRAM_ECC_DOUBLE_UNMASKED; }
+    else                                                    { cur_test = TEST_COUNT;                    }
+
+    // Acquire the mailbox lock
+    while((lsu_read_32(CLP_MBOX_CSR_MBOX_LOCK) & MBOX_CSR_MBOX_LOCK_LOCK_MASK) != 0);
+
+    // Set the Error Injection
+    SEND_STDOUT_CTRL((uint32_t) type);
+
+    // Set the MASK mode
+    if (test_mask == WITH_MASK && type == MBOX_DOUBLE) {
+        lsu_write_32(CLP_SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK, SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK_MASK_MBOX_ECC_UNC_MASK);
+    } else if (test_mask == NO_MASK || type == MBOX_SINGLE) {
+        uint32_t mask_val = lsu_read_32(CLP_SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK);
+        mask_val &= ~SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK_MASK_MBOX_ECC_UNC_MASK;
+        lsu_write_32(CLP_SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK, mask_val);
+    }
+
+    // Allocate an array in Mailbox SRAM
+    volatile uint32_t* myarray = (uint32_t*) MBOX_DIR_BASE_ADDR;
+    for (uint32_t ii; ii < 64; ii++) {
+        myarray[ii] = 64-ii;
+    }
+
+    // Read the array from the Mailbox and write to STDOUT
+    for (uint32_t ii; ii < 64; ii++) {
+        printf("[%d]:%x\n", ii, myarray[ii]); // no verbosity control -- dereferencing the array IS the test
+    }
+
+    // Log that the test ran
+    test_progress_g[cur_test] = RUN_NOT_CHECKED;
+}
+
+uint32_t check_mbox_sram_ecc(enum ecc_error_mode_type type, enum mask_config test_mask) {
+    uint32_t sts = 0;
+    uint32_t rsp = 0;
+    enum test_list cur_test;
+
+    VPRINTF(MEDIUM, "\n*** Check Mbox SRAM ECC Err ***\n  Type: %s\n  Masked: %d\n\n", (type == MBOX_SINGLE) ? "1-bit" : "2-bit", test_mask == WITH_MASK);
+
+    // Check that the test ran
+    if      (type == MBOX_SINGLE && test_mask == WITH_MASK) { cur_test = MBOX_SRAM_ECC_SINGLE_MASKED;   }
+    else if (type == MBOX_SINGLE && test_mask == NO_MASK)   { cur_test = MBOX_SRAM_ECC_SINGLE_UNMASKED; }
+    else if (type == MBOX_DOUBLE && test_mask == WITH_MASK) { cur_test = MBOX_SRAM_ECC_DOUBLE_MASKED;   }
+    else if (type == MBOX_DOUBLE && test_mask == NO_MASK)   { cur_test = MBOX_SRAM_ECC_DOUBLE_UNMASKED; }
+    else                                                    { cur_test = TEST_COUNT;
+                                                              sts     |= UNEXP_ARG;                     }
+
+    if (test_progress_g[cur_test] != RUN_NOT_CHECKED) {
+        VPRINTF(ERROR, "Mbox chkr hit unexpected state. Idx: %d Prog: %d", cur_test, test_progress_g[cur_test]);
+        sts |= INV_STATE;
+    }
+
+    // Check Interrupt Counts
+    if (type == MBOX_SINGLE && !(cptra_intr_rcv.soc_ifc_notif & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK)) {
+        VPRINTF(ERROR, "ERROR: No notif intr rcv (cor errors) in ECC sram test\n");
+        sts |= INTR_COUNT_0;
+    } else {
+        cptra_intr_rcv.soc_ifc_notif &= ~SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+    }
+    if (type == MBOX_DOUBLE && !(cptra_intr_rcv.soc_ifc_error & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK)) {
+        VPRINTF(ERROR, "ERROR: No err intr rcv for unc err in ECC sram test\n");
+        sts |= INTR_COUNT_0;
+    } else {
+        cptra_intr_rcv.soc_ifc_error &= ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+    }
+    // Sleep in between checking/clearing intr_count to allow any ISR to execute and show idle time in sims
+    for (uint16_t slp = 0; slp < 100; slp++) {
+        __asm__ volatile ("nop"); // Sleep loop as "nop"
+    }
+    intr_count = 0;
+
+    // Get the interrupt count for the expected type
+    if (type == MBOX_SINGLE) {
+        if (lsu_read_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_R) == 0) {
+            VPRINTF(ERROR, "ERROR: 0 count value for cor ECC errors\n");
+            sts |= INTR_COR_COUNT_0;
+        } else {
+            VPRINTF(LOW, "Cor ECC err no.: %x\n", lsu_read_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_R));
+        }
+    } else if (type == MBOX_DOUBLE) {
+        if (lsu_read_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_MBOX_ECC_UNC_INTR_COUNT_R) == 0) {
+            VPRINTF(ERROR, "ERROR: 0 count value for unc ECC errors\n");
+            sts |= INTR_UNC_COUNT_0;
+        } else {
+            VPRINTF(LOW, "Unc ECC err no.: %x\n", lsu_read_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_MBOX_ECC_UNC_INTR_COUNT_R));
+        }
+    } else {
+        VPRINTF(ERROR, "ERROR: ecc_error_mode: %x\n", type);
+        sts |= UNEXP_ARG;
+    }
+
+    // For Correctable Errors, only expect internal interrupts (no output to SOC)
+    // For Masked Uncorrectable Errors, interrupt should not go to SOC
+    if (type == MBOX_DOUBLE) {
+        uint32_t resp = lsu_read_32(CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0);
+        // Check GENERIC_INPUT_WIRES for detection of cptra_error_non_fatal
+        if (test_mask == NO_MASK && resp != MBOX_NON_FATAL_OBSERVED) {
+            VPRINTF(ERROR, "ERROR: Bad resp from TB. Got: 0x%x Exp 0x%x\n", resp, MBOX_NON_FATAL_OBSERVED);
+            sts |= BAD_CPTRA_SIG;
+        }
+        else if (test_mask == WITH_MASK && resp == ERROR_NONE_SET) {
+            lsu_write_32(CLP_SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL, SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_ECC_UNC_MASK);
+        }
+        else if (test_mask == WITH_MASK) {
+            VPRINTF(ERROR, "ERROR: Bad resp from TB. Got: 0x%x Exp 0x%x\n", resp, ERROR_NONE_SET);
+            sts |= BAD_CPTRA_SIG;
+        }
+    }
+
+    // Unlock Mailbox
+    lsu_write_32(CLP_MBOX_CSR_MBOX_UNLOCK, MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK);
+
+    // Reset the Error Injection Function
+    SEND_STDOUT_CTRL((uint32_t) ERROR_NONE);
+
+    // Increment test progress
+    if (sts) {
+        test_progress_g[cur_test] = RUN_AND_FAILED;
+        VPRINTF(ERROR, "ERROR: Test fail. Sts: 0x%x\n", sts);
+    } else {
+        test_progress_g[cur_test] = RUN_AND_PASSED;
+    }
+
+    return sts;
+}
+
+uint32_t test_mbox_sram_ecc (enum mask_config test_mask) {
+    VPRINTF(MEDIUM, "\nEnter Mbox SRAM ECC Err test\n  Masked: %d\n", test_mask == WITH_MASK);
+
+    // Single-bit Correctable ECC Error injection
+    run_mbox_sram_ecc(MBOX_SINGLE, test_mask);
+    check_mbox_sram_ecc(MBOX_SINGLE, test_mask);
+    // Double-bit Uncorrectable ECC Error injection
+    run_mbox_sram_ecc(MBOX_DOUBLE, test_mask);
+    check_mbox_sram_ecc(MBOX_DOUBLE, test_mask);
+}
+
+uint32_t run_iccm_sram_ecc (enum mask_config test_mask) {
+    enum test_list cur_test;
+
+    uint32_t * ICCM = (uint32_t *) RV_ICCM_SADR;
+    uint32_t * code_word = 0;
+    uint32_t * iccm_dest = ICCM;
+    void (* iccm_fn) (void) = (void*) ICCM;
+
+    uint32_t resp;
+
+    VPRINTF(MEDIUM, "\n*** Run ICCM SRAM ECC Err ***\n  Masked: %d\n\n", test_mask == WITH_MASK);
+
+    // Grab test enum
+    if      (test_mask == WITH_MASK) { cur_test = ICCM_SRAM_ECC_SINGLE_MASKED;   }
+    else if (test_mask == NO_MASK)   { cur_test = ICCM_SRAM_ECC_SINGLE_UNMASKED; }
+    else                             { cur_test = TEST_COUNT;                    }
+
+    // Request that TB inject ICCM SRAM single-bit errors
+    // This should not result in any reset or reporting activity
+    SEND_STDOUT_CTRL(ICCM_SINGLE);
+
+    // Copy routine to ICCM
+    code_word = (uint32_t *) &iccm_code0_start;
+    VPRINTF(LOW, "Copy code from %x [thru %x] to %x\n", (uintptr_t) code_word, &iccm_code0_end, (uintptr_t) iccm_dest);
+    while (code_word < (uint32_t *) &iccm_code0_end) {
+        VPRINTF(ALL, "at %x: %x\n", (uintptr_t) code_word, *code_word);
+        *iccm_dest++ = *code_word++;
+    }
+
+    // Reset the Error Injection Function
+    SEND_STDOUT_CTRL((uint32_t) ERROR_NONE);
+
+    // Flag Single-bit test as having run
+    test_progress_g[cur_test] = RUN_NOT_CHECKED;
+
+    // Run ICCM routine
+    iccm_fn();
+
+    // Confirm TB reports no observed activity
+    resp = lsu_read_32(CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0);
+    if (resp != ERROR_NONE_SET) {
+        VPRINTF(ERROR, "ERROR: Bad resp from TB. Got: 0x%x Exp 0x%x\n", resp, ERROR_NONE_SET);
+        test_progress_g[cur_test] = RUN_AND_FAILED;
+    } else {
+        __asm__ volatile ("csrr    %0, %1"
+                          : "=r" (resp)  /* output : register */
+                          : "i" (VEER_CSR_MICCMECT) /* input : immediate */
+                          : /* clobbers: none */);
+        if (resp == 0) {
+            VPRINTF(ERROR, "ERROR: ICCM Cor error count is 0\n");
+            test_progress_g[cur_test] = RUN_AND_FAILED;
+        } else {
+            test_progress_g[cur_test] = RUN_AND_PASSED;
+        }
+    }
+
+    // Should return here after encountering single-bit (correctable) ECC errors
+    // while running ICCM routine
+    // Set new test enum
+    if      (test_mask == WITH_MASK) { cur_test = ICCM_SRAM_ECC_DOUBLE_MASKED;   }
+    else if (test_mask == NO_MASK)   { cur_test = ICCM_SRAM_ECC_DOUBLE_UNMASKED; }
+    else                             { cur_test = TEST_COUNT;                    }
+
+    // Now, set the MASK (per arg)
+    if (test_mask == WITH_MASK) {
+        lsu_write_32(CLP_SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK, SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_ICCM_ECC_UNC_MASK);
+    } else if (test_mask == NO_MASK) {
+        uint32_t mask_val = lsu_read_32(CLP_SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK);
+        mask_val &= ~SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_ICCM_ECC_UNC_MASK;
+        lsu_write_32(CLP_SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK, mask_val);
+    }
+
+    // Request that TB inject ICCM SRAM double-bit errors
+    // This should result in FATAL error and caliptra reset
+    SEND_STDOUT_CTRL(ICCM_DOUBLE);
+
+    // Copy routine to ICCM
+    code_word = (uint32_t *) &iccm_code0_start;
+    iccm_dest = ICCM;
+    VPRINTF(LOW, "Copy code from %x [thru %x] to %x\n", (uintptr_t) code_word, &iccm_code0_end, (uintptr_t) iccm_dest);
+    while (code_word < (uint32_t *) &iccm_code0_end) {
+        VPRINTF(ALL, "at %x: %x\n", (uintptr_t) code_word, *code_word);
+        *iccm_dest++ = *code_word++;
+    }
+
+    // Reset the Error Injection Function
+    SEND_STDOUT_CTRL((uint32_t) ERROR_NONE);
+
+    // Clear the exception flag so we can properly check that it was set for an unmasked test
+    exc_flag.exception_hit = 0;
+    exc_flag.mcause        = 0;
+    exc_flag.mscause       = 0;
+
+    // Flag Double-bit test as having run
+    test_progress_g[cur_test] = RUN_NOT_CHECKED;
+
+    // Run ICCM routine
+    // If FATAL error unmasked, this will trigger a reset.
+    // Else, we'll observe a precise exception, which should do a firmware reset
+    iccm_fn();
+
+    // Wait for the reset to occur
+    if (test_mask == NO_MASK) { VPRINTF(HIGH, "...\n"); while(1); }
+
+}
+
+uint32_t check_iccm_sram_ecc (enum mask_config test_mask) {
+    enum test_list cur_test;
+    uint32_t resp;
+    uint32_t sts = SUCCESS;
+
+    VPRINTF(MEDIUM, "\n*** Check ICCM SRAM ECC Err ***\n  Masked: %d\n\n", test_mask == WITH_MASK);
+
+    // Get test ID
+    if (test_mask == WITH_MASK) { cur_test = ICCM_SRAM_ECC_DOUBLE_MASKED;   }
+    else                        { cur_test = ICCM_SRAM_ECC_DOUBLE_UNMASKED; }
+
+    // Verify correct response path was taken
+    resp = lsu_read_32(CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0);
+    if (test_mask == WITH_MASK) {
+        // For a MASKED error, we only expect the exception path and no response from TB
+        if (exc_flag.exception_hit == 0) {
+            test_progress_g[cur_test] = RUN_AND_FAILED;
+            sts |= INTR_COUNT_0;
+        } else if (exc_flag.mcause  != RISCV_EXCP_INSTRUCTION_ACCESS_FAULT ||
+                   exc_flag.mscause != RISC_EXCP_MSCAUSE_ICCM_INST_UNC_ECC_ERR) {
+            test_progress_g[cur_test] = RUN_AND_FAILED;
+            sts |= BAD_EXCP_CODE;
+        } else if (resp != ERROR_NONE_SET) {
+            test_progress_g[cur_test] = RUN_AND_FAILED;
+            sts |= BAD_CPTRA_SIG;
+        } else {
+            test_progress_g[cur_test] = RUN_AND_PASSED;
+        }
+        lsu_write_32(CLP_SOC_IFC_REG_CPTRA_HW_ERROR_FATAL, SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_ICCM_ECC_UNC_MASK);
+    } else {
+        // For an UNMASKED error, we expect ICCM ECC FATAL Error to trigger TB reset and input val
+        if (resp == ICCM_FATAL_OBSERVED) {
+            test_progress_g[cur_test] = RUN_AND_PASSED;
+        } else {
+            test_progress_g[cur_test] = RUN_AND_FAILED;
+            sts |= BAD_CPTRA_SIG;
+        }
+    }
+
+    return sts;
+}
+
+// TODO should test both DMA slave and internal DCCM accesses?
+uint32_t run_dccm_sram_ecc (enum mask_config test_mask) {
+    enum test_list cur_test;
+
+    uint32_t array_in_dccm [10]; // stack is in DCCM, so this automatically goes there
+    uint32_t* safe_iter = (uint32_t*) MBOX_DIR_BASE_ADDR; // Pointer to mailbox memory allows us to define an iteration variable that will not be corrupted by DCCM error injection
+
+    uint32_t resp = lsu_read_32(CLP_SOC_IFC_REG_INTERNAL_RV_MTIME_L);
+
+    VPRINTF(MEDIUM, "\n*** Run DCCM SRAM ECC Err ***\n  Masked: %d\n\n", test_mask == WITH_MASK);
+
+    // Grab test enum
+    if      (test_mask == WITH_MASK) { cur_test = DCCM_SRAM_ECC_SINGLE_MASKED;   }
+    else if (test_mask == NO_MASK)   { cur_test = DCCM_SRAM_ECC_SINGLE_UNMASKED; }
+    else                             { cur_test = TEST_COUNT;                    }
+
+    // Acquire the mailbox lock (to allow direct-mode use of safe_iter)
+    while((lsu_read_32(CLP_MBOX_CSR_MBOX_LOCK) & MBOX_CSR_MBOX_LOCK_LOCK_MASK) != 0) {
+        VPRINTF(MEDIUM, "Get mbox lock\n");
+    }
+
+    // Request that TB inject DCCM SRAM single-bit errors
+    // This should not result in any reset or reporting activity
+    SEND_STDOUT_CTRL(DCCM_SINGLE);
+
+    // Populate array in DCCM (should be corrupted)
+    *safe_iter = 0;
+    while(*safe_iter < 10) { 
+        resp = (resp << 1) ^ lsu_read_32(CLP_SOC_IFC_REG_INTERNAL_RV_MTIME_L);
+        array_in_dccm[*safe_iter] = resp;
+        *safe_iter = (*safe_iter) + 1;
+    }
+
+    // Reset the Error Injection Function
+    SEND_STDOUT_CTRL((uint32_t) ERROR_NONE);
+    __asm__ volatile ("fence.i");
+
+    // Flag Single-bit test as having run
+    test_progress_g[cur_test] = RUN_NOT_CHECKED;
+
+    // Read-back the array in DCCM
+    *safe_iter = 0;
+    while(*safe_iter < 10) { 
+        printf("[%d]:%x\n", *safe_iter, array_in_dccm[*safe_iter]); // no verbosity control -- dereferencing the array IS the test
+        *safe_iter = (*safe_iter) + 1;
+    }
+
+    // Unlock Mailbox
+    lsu_write_32(CLP_MBOX_CSR_MBOX_UNLOCK, MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK);
+
+    // Confirm TB reports no observed activity
+    resp = lsu_read_32(CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0);
+    if (resp != ERROR_NONE_SET) {
+        VPRINTF(ERROR, "ERROR: Bad resp from TB. Got: 0x%x Exp 0x%x\n", resp, ERROR_NONE_SET);
+        test_progress_g[cur_test] = RUN_AND_FAILED;
+    } else {
+        __asm__ volatile ("csrr    %0, %1"
+                          : "=r" (resp)  /* output : register */
+                          : "i" (VEER_CSR_MDCCMECT) /* input : immediate */
+                          : /* clobbers: none */);
+        if (resp == 0) {
+            VPRINTF(ERROR, "ERROR: DCCM Cor error count is 0\n");
+            test_progress_g[cur_test] = RUN_AND_FAILED;
+        } else {
+            test_progress_g[cur_test] = RUN_AND_PASSED;
+        }
+    }
+
+    // Should return here after encountering single-bit (correctable) ECC errors
+    // while running DCCM routine
+    // Set new test enum
+    if      (test_mask == WITH_MASK) { cur_test = DCCM_SRAM_ECC_DOUBLE_MASKED;   }
+    else if (test_mask == NO_MASK)   { cur_test = DCCM_SRAM_ECC_DOUBLE_UNMASKED; }
+    else                             { cur_test = TEST_COUNT;                    }
+
+    // Now, set the MASK (per arg)
+    if (test_mask == WITH_MASK) {
+        lsu_write_32(CLP_SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK, SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_DCCM_ECC_UNC_MASK);
+    } else if (test_mask == NO_MASK) {
+        uint32_t mask_val = lsu_read_32(CLP_SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK);
+        mask_val &= ~SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_DCCM_ECC_UNC_MASK;
+        lsu_write_32(CLP_SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK, mask_val);
+    }
+
+    // Acquire the mailbox lock (to allow direct-mode use of safe_iter)
+    while((lsu_read_32(CLP_MBOX_CSR_MBOX_LOCK) & MBOX_CSR_MBOX_LOCK_LOCK_MASK) != 0) {
+        VPRINTF(MEDIUM, "Get mbox lock\n");
+    }
+
+    // Request that TB inject DCCM SRAM double-bit errors
+    // This should result in FATAL error and caliptra reset
+    // when reading back
+    SEND_STDOUT_CTRL(DCCM_DOUBLE);
+
+    // Populate array in DCCM (should be corrupted)
+    *safe_iter = 0;
+    while(*safe_iter < 10) { 
+        resp = (resp << 1) ^ lsu_read_32(CLP_SOC_IFC_REG_INTERNAL_RV_MTIME_L);
+        array_in_dccm[*safe_iter] = resp;
+        *safe_iter = (*safe_iter) + 1;
+    }
+
+    // Reset the Error Injection Function
+    SEND_STDOUT_CTRL((uint32_t) ERROR_NONE);
+    __asm__ volatile ("fence.i");
+
+    // TODO check for AMO/Store exception here?
+
+    // Clear the exception flag so we can properly check that it was set for an unmasked test
+    exc_flag.exception_hit = 0;
+    exc_flag.mcause        = 0;
+    exc_flag.mscause       = 0;
+
+    // Flag Double-bit test as having run
+    test_progress_g[cur_test] = RUN_NOT_CHECKED;
+
+    // Read-back the array in DCCM
+    // If FATAL error unmasked, this will trigger a reset.
+    // Else, we'll observe a precise exception
+    *safe_iter = 0;
+    while(*safe_iter < 10) { 
+        printf("[%d]:%x\n", *safe_iter, array_in_dccm[*safe_iter]); // no verbosity control -- dereferencing the array IS the test
+        *safe_iter = (*safe_iter) + 1;
+    }
+
+    // Unlock Mailbox
+    lsu_write_32(CLP_MBOX_CSR_MBOX_UNLOCK, MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK);
+
+    // Wait for the reset to occur
+    if (test_mask == NO_MASK) { VPRINTF(HIGH, "...\n"); while(1); }
+
+}
+
+uint32_t check_dccm_sram_ecc (enum mask_config test_mask) {
+    enum test_list cur_test;
+    uint32_t resp;
+    uint32_t sts = SUCCESS;
+
+    VPRINTF(MEDIUM, "\n*** Check DCCM SRAM ECC Err ***\n  Masked: %d\n\n", test_mask == WITH_MASK);
+
+    // Get test ID
+    if (test_mask == WITH_MASK) { cur_test = DCCM_SRAM_ECC_DOUBLE_MASKED;   }
+    else                        { cur_test = DCCM_SRAM_ECC_DOUBLE_UNMASKED; }
+
+    // Verify correct response path was taken
+    resp = lsu_read_32(CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0);
+    if (test_mask == WITH_MASK) {
+        // For a MASKED error, we only expect the exception path and no response from TB
+        if (exc_flag.exception_hit == 0) {
+            test_progress_g[cur_test] = RUN_AND_FAILED;
+            sts |= INTR_COUNT_0;
+            VPRINTF(ERROR, "ERROR: No excpn\n");
+        } else if (exc_flag.mcause  != RISCV_EXCP_LOAD_ACCESS_FAULT ||
+                   exc_flag.mscause != RISC_EXCP_MSCAUSE_DCCM_LOAD_UNC_ECC_ERR) {
+            test_progress_g[cur_test] = RUN_AND_FAILED;
+            sts |= BAD_EXCP_CODE;
+            VPRINTF(ERROR, "ERROR: Wrong excpn cause. Got: 0x%x msc 0x%x\n", exc_flag.mcause, exc_flag.mscause);
+        } else if (resp != ERROR_NONE_SET) {
+            test_progress_g[cur_test] = RUN_AND_FAILED;
+            sts |= BAD_CPTRA_SIG;
+            VPRINTF(ERROR, "ERROR: Wrong TB resp\n");
+        } else {
+            test_progress_g[cur_test] = RUN_AND_PASSED;
+        }
+        lsu_write_32(CLP_SOC_IFC_REG_CPTRA_HW_ERROR_FATAL, SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_DCCM_ECC_UNC_MASK);
+    } else {
+        // For an UNMASKED error, we expect DCCM ECC FATAL Error to trigger TB reset and input val
+        if (resp == DCCM_FATAL_OBSERVED) {
+            test_progress_g[cur_test] = RUN_AND_PASSED;
+        } else {
+            test_progress_g[cur_test] = RUN_AND_FAILED;
+            sts |= BAD_CPTRA_SIG;
+            VPRINTF(ERROR, "ERROR: Wrong TB resp. Exp 0x%x Got 0x%x\n", DCCM_FATAL_OBSERVED, resp);
+        }
+    }
+
+    return sts;
+}
+
+void run_nmi_test (enum mask_config test_mask) {
+    enum test_list cur_test;
+    VPRINTF(MEDIUM, "\n*** Run Non-Maskable Intr ***\n  Masked: %d\n\n", test_mask == WITH_MASK);
+    
+    // Get test ID
+    if (test_mask == WITH_MASK) { cur_test = NMI_MASKED;   }
+    else                        { cur_test = NMI_UNMASKED; }
+
+    //Enable WDT so that both timers time out and NMI is issued
+    lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0, 0x00000040);
+    lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1, 0x00000000);
+    lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0, 0x00000040);
+    lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1, 0x00000000);
+    lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_EN, SOC_IFC_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_MASK);
+
+    //Set mask
+    if (test_mask == WITH_MASK) {
+        lsu_write_32(CLP_SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK, SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_NMI_PIN_MASK);
+    }
+    // Wait for interrupt
+    while(1) {
+        __asm__ volatile ("wfi"); // "Wait for interrupt"
+        // Continuously loop to allow the ICCM ECC ERROR to trigger system reset
+        for (uint16_t slp = 0; slp < 1000; slp++) {
+            __asm__ volatile ("nop"); // Sleep loop as "nop"
+        }
+        putchar('.');
+    }
+
+    test_progress_g[cur_test] = RUN_NOT_CHECKED;
+
+    return;
+}
+
+uint32_t check_nmi_test (enum mask_config test_mask) {
+    uint32_t sts = 0;
+    enum test_list cur_test;
+    VPRINTF(MEDIUM, "\n*** Check Non-Maskable Intr ***\n  Masked: %d\n\n", test_mask == WITH_MASK);
+    // Get test ID
+    if (test_mask == WITH_MASK) { cur_test = NMI_MASKED;   }
+    else                        { cur_test = NMI_UNMASKED; }
+    //test_progress_g[cur_test] = RUN_AND_PASSED;
+
+    if (test_mask == WITH_MASK) {
+        // No generic input toggle expected out of reset
+        if ((cptra_intr_rcv.soc_ifc_notif & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_GEN_IN_TOGGLE_EN_MASK) && (lsu_read_32(CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0) != generic_input_wires_0_before_rst)) {
+            VPRINTF(ERROR, "ERROR: Gen-in tgl with bad val\n");
+            sts |= BAD_CPTRA_SIG;
+            test_progress_g[cur_test] = RUN_AND_FAILED;
+        } else {
+            sts |= SUCCESS;
+            test_progress_g[cur_test] = RUN_AND_PASSED;
+        }
+
+        lsu_write_32(CLP_SOC_IFC_REG_CPTRA_HW_ERROR_FATAL, SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_NMI_PIN_MASK);
+    } else {
+        // Check for generic_input_wires activity
+        if (!(cptra_intr_rcv.soc_ifc_notif & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_GEN_IN_TOGGLE_EN_MASK)) {
+            VPRINTF(ERROR, "ERROR: Gen-in did not tgl\n");
+            sts |= BAD_CPTRA_SIG;
+            test_progress_g[cur_test] = RUN_AND_FAILED;
+        } else if (lsu_read_32(CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0) != NMI_FATAL_OBSERVED) {
+            VPRINTF(ERROR, "ERROR: Gen-in bad val\n");
+            sts |= BAD_CPTRA_SIG;
+            test_progress_g[cur_test] = RUN_AND_FAILED;
+        } else {
+            sts |= SUCCESS;
+            test_progress_g[cur_test] = RUN_AND_PASSED;
+        }
+    }
+
+
+    return sts;
+}
+
+void run_mbox_no_lock_error(enum mask_config test_mask) {
+    enum test_list cur_test;
+    VPRINTF(MEDIUM, "\n*** Run Mbox No Lock ***\n  Masked: %d\n\n", test_mask == WITH_MASK);
+
+    // Get test ID
+    if      (test_mask == WITH_MASK) { cur_test = PROT_NO_LOCK_MASKED;   }
+    else if (test_mask == NO_MASK)   { cur_test = PROT_NO_LOCK_UNMASKED; }
+    else                             { cur_test = TEST_COUNT;            }
+
+    // Generic input wires should toggle if unmasked, clear the flag so we can see it update
+    cptra_intr_rcv.soc_ifc_notif = 0;
+    // Also clear the mbox cmd fail flag
+    cptra_intr_rcv.soc_ifc_error = 0;
+
+    //Set the mask
+    if (test_mask == WITH_MASK)
+        lsu_write_32(CLP_SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK, SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK_MASK_MBOX_PROT_NO_LOCK_MASK);
+
+    // run test (try to read dataout without having lock)
+    lsu_write_32(CLP_MBOX_CSR_MBOX_UNLOCK,MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK); // Be sure it's unlocked
+    // Instruct TB to do bad mailbox flow
+    SEND_STDOUT_CTRL(0xe5);
+
+    // Flag test as having run
+    test_progress_g[cur_test] = RUN_NOT_CHECKED;
+
+}
+
+void run_mbox_ooo_error(enum mask_config test_mask) {
+    enum test_list cur_test;
+    VPRINTF(MEDIUM, "\n*** Run Mbox Out-of-order ***\n  Masked: %d\n\n", test_mask == WITH_MASK);
+
+    // Get test ID
+    if      (test_mask == WITH_MASK) { cur_test = PROT_OOO_MASKED;   }
+    else if (test_mask == NO_MASK)   { cur_test = PROT_OOO_UNMASKED; }
+    else                             { cur_test = TEST_COUNT;        }
+
+    // Generic input wires should toggle if unmasked, clear the flag so we can see it update
+    cptra_intr_rcv.soc_ifc_notif = 0;
+    // Also clear the mbox cmd fail flag
+    cptra_intr_rcv.soc_ifc_error = 0;
+
+    //Set the mask
+    if (test_mask == WITH_MASK)
+        lsu_write_32(CLP_SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK, SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK_MASK_MBOX_PROT_OOO_MASK);
+
+    // Flag test as having run
+    test_progress_g[cur_test] = RUN_NOT_CHECKED;
+
+    // run test (try to read dataout without having lock)
+    // Instruct TB to do bad mailbox flow
+    SEND_STDOUT_CTRL(0xe6); //Mailbox unlocked through ISR
+
+    //return;
+
+}
+
+uint32_t check_mbox_no_lock_error(enum mask_config test_mask) {
+    enum test_list cur_test;
+    uint32_t sts = 0;
+    VPRINTF(MEDIUM, "\n*** Check Mbox No Lock ***\n  Masked: %d\n\n", test_mask == WITH_MASK);
+
+    // Get test ID
+    if      (test_mask == WITH_MASK) { cur_test = PROT_NO_LOCK_MASKED;   }
+    else if (test_mask == NO_MASK)   { cur_test = PROT_NO_LOCK_UNMASKED; }
+    else                             { cur_test = TEST_COUNT;            }
+
+    if (!(cptra_intr_rcv.soc_ifc_error & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK)) {
+        VPRINTF(ERROR, "ERROR: No cmd fail intr\n");
+        sts |= INTR_COUNT_0;
+        test_progress_g[cur_test] = RUN_AND_FAILED;
+    } else if (test_mask == WITH_MASK) {
+        // Check for generic_input_wires activity
+        if (cptra_intr_rcv.soc_ifc_notif & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_GEN_IN_TOGGLE_EN_MASK) {
+            VPRINTF(ERROR, "ERROR: Gen-in tgl\n");
+            sts |= BAD_CPTRA_SIG;
+            test_progress_g[cur_test] = RUN_AND_FAILED;
+        } else {
+            sts |= SUCCESS;
+            test_progress_g[cur_test] = RUN_AND_PASSED;
+        }
+        lsu_write_32(CLP_SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL, SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_NO_LOCK_MASK);
+    } else {
+        // Check for generic_input_wires activity
+        if (!(cptra_intr_rcv.soc_ifc_notif & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_GEN_IN_TOGGLE_EN_MASK)) {
+            VPRINTF(ERROR, "ERROR: Gen-in did not tgl\n");
+            sts |= BAD_CPTRA_SIG;
+            test_progress_g[cur_test] = RUN_AND_FAILED;
+        } else if (lsu_read_32(CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0) != PROT_NO_LOCK_NON_FATAL_OBSERVED) {
+            VPRINTF(ERROR, "ERROR: Gen-in bad val\n");
+            sts |= BAD_CPTRA_SIG;
+            test_progress_g[cur_test] = RUN_AND_FAILED;
+        } else {
+            sts |= SUCCESS;
+            test_progress_g[cur_test] = RUN_AND_PASSED;
+        }
+    }
+
+    //Unlock mailbox
+    lsu_write_32(CLP_MBOX_CSR_MBOX_UNLOCK,MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK);
+
+    return sts;
+}
+
+uint32_t check_mbox_ooo_error(enum mask_config test_mask) {
+    enum test_list cur_test;
+    uint32_t sts = 0;
+    VPRINTF(MEDIUM, "\n*** Check Mbox Out-of-order ***\n  Masked: %d\n\n", test_mask == WITH_MASK);
+
+    // Get test ID
+    if      (test_mask == WITH_MASK) { cur_test = PROT_OOO_MASKED;   }
+    else if (test_mask == NO_MASK)   { cur_test = PROT_OOO_UNMASKED; }
+    else                             { cur_test = TEST_COUNT;        }
+
+    if (!(cptra_intr_rcv.soc_ifc_error & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK)) {
+        VPRINTF(ERROR, "ERROR: No cmd fail intr\n");
+        sts |= INTR_COUNT_0;
+        test_progress_g[cur_test] = RUN_AND_FAILED;
+    } else if (test_mask == WITH_MASK) {
+        // Check for generic_input_wires activity
+        if (cptra_intr_rcv.soc_ifc_notif & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_GEN_IN_TOGGLE_EN_MASK) {
+            VPRINTF(ERROR, "ERROR: Gen-in tgl\n");
+            sts |= BAD_CPTRA_SIG;
+            test_progress_g[cur_test] = RUN_AND_FAILED;
+        } else {
+            sts |= SUCCESS;
+            test_progress_g[cur_test] = RUN_AND_PASSED;
+        }
+        lsu_write_32(CLP_SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL, SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_OOO_MASK);
+
+        //Reset out-of-order access flag
+        SEND_STDOUT_CTRL(0xe7);
+    } else {
+        // Check for generic_input_wires activity
+        if (!(cptra_intr_rcv.soc_ifc_notif & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_GEN_IN_TOGGLE_EN_MASK)) {
+            VPRINTF(ERROR, "ERROR: Gen-in did not tgl\n");
+            sts |= BAD_CPTRA_SIG;
+            test_progress_g[cur_test] = RUN_AND_FAILED;
+        } else if (lsu_read_32(CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0) != PROT_OOO_NON_FATAL_OBSERVED) {
+            VPRINTF(ERROR, "ERROR: Gen-in bad val\n");
+            sts |= BAD_CPTRA_SIG;
+            test_progress_g[cur_test] = RUN_AND_FAILED;
+        } else {
+            sts |= SUCCESS;
+            test_progress_g[cur_test] = RUN_AND_PASSED;
+        }
+    }
+
+    return sts;
+}
+
+void execute_from_iccm (void) {
+    // Do a bunch of nonsense tasks just to populate the code space.
+    // When running this routine, we expect to encounter ICCM ECC Errors and
+    // get reset by TB
+    uint32_t tmp_reg, tmp_reg2;
+    VPRINTF(LOW, "Exec from ICCM\n");
+    tmp_reg = lsu_read_32(CLP_SOC_IFC_REG_CPTRA_HW_CONFIG);
+    VPRINTF(LOW, "HW_CFG: 0x%x\n", tmp_reg);
+    tmp_reg  = lsu_read_32(CLP_SOC_IFC_REG_INTERNAL_RV_MTIMECMP_L);
+    tmp_reg2 = lsu_read_32(CLP_SOC_IFC_REG_INTERNAL_RV_MTIMECMP_H);
+    VPRINTF(LOW, "MTIMECMP: 0x%x %x\n", tmp_reg2, tmp_reg);
+    tmp_reg  = lsu_read_32(CLP_SOC_IFC_REG_INTERNAL_RV_MTIME_L);
+    tmp_reg2 = lsu_read_32(CLP_SOC_IFC_REG_INTERNAL_RV_MTIME_H);
+    VPRINTF(LOW, "MTIME: 0x%x %x\n", tmp_reg2, tmp_reg);
+    // This reg isn't even writable, so nothing should happen...
+    if (tmp_reg2) {
+        lsu_write_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R, tmp_reg2 ^ tmp_reg);
+    } else {
+        lsu_write_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R, (tmp_reg2 - 1) ^ tmp_reg);
+    }
+    tmp_reg = csr_read_mepc();
+    tmp_reg2 = csr_read_mtval();
+    tmp_reg ^= csr_read_mtvec();
+    tmp_reg2 ^= csr_read_mie();
+    tmp_reg ^= csr_read_mip();
+    tmp_reg2 ^= csr_read_mvendorid();
+    tmp_reg ^= tmp_reg2;
+    VPRINTF(LOW, "Nonsense result: 0x%x\n", tmp_reg);
+    // ERROR_FATAL interrupt will only go to TB if running the unmasked
+    // double-bit error test, so we expect to get here successfully and return
+    // in other test cases
+    if (test_progress_g[ICCM_SRAM_ECC_DOUBLE_UNMASKED] == RUN_NOT_CHECKED &&
+        test_progress_g[ICCM_SRAM_ECC_SINGLE_MASKED  ] == NOT_STARTED) {
+        while(1) {
+            __asm__ volatile ("wfi"); // "Wait for interrupt"
+            // Continuously loop to allow the ICCM ECC ERROR to trigger system reset
+            for (uint16_t slp = 0; slp < 1000; slp++) {
+                __asm__ volatile ("nop"); // Sleep loop as "nop"
+            }
+            putchar('.');
+        }
+    } else {
+        return;
+    }
+}
+
+// In the ROM .text section
+void nmi_handler (void) {
+    VPRINTF(LOW, "**** NMI ****\n");
+    if (boot_count != BEFORE_FIRST_NMI_FAILURE && boot_count != BEFORE_SECOND_NMI_FAILURE) {
+        VPRINTF(ERROR, "ERROR: NMI unexpected. mcause [0x%x]!\n", csr_read_mcause()); // did not expect NMI
+        VPRINTF(ERROR, "       mepc [0x%x]\n", csr_read_mepc());
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+    // If we got here via internal NMI, it's an error - kill the sim
+    if ((csr_read_mcause() & MCAUSE_NMI_BIT_MASK) == MCAUSE_NMI_BIT_MASK) {
+        VPRINTF(ERROR, "ERROR: NMI w/ mcause [0x%x]!\n", csr_read_mcause());
+        VPRINTF(ERROR, "       mepc [0x%x]\n", csr_read_mepc());
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+    // NMI occurred, but was caused by pin-assertion due to Watchdog Timer
+    else if (lsu_read_32(CLP_SOC_IFC_REG_CPTRA_HW_ERROR_FATAL) & SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_NMI_PIN_MASK) {
+        //Save generic_input_wires value before reset to compare later. This is to avoid flagging the toggle during reset as an error
+        generic_input_wires_0_before_rst = lsu_read_32(CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0);
+        VPRINTF(MEDIUM, "NMI w/ mcause [0x%x] during NMI test\n", csr_read_mcause());
+        VPRINTF(MEDIUM, "mepc [0x%x]\n", csr_read_mepc());
+        // If the FATAL Error bit for NMI is masked, manually trigger firmware reset
+        if (lsu_read_32(CLP_SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK) & SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_NMI_PIN_MASK) {
+            VPRINTF(LOW, "NMI bit masked, no rst exp from TB: rst core manually!\n");
+            //lsu_write_32(CLP_SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET, SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_CORE_RST_MASK);
+            SEND_STDOUT_CTRL(0xf6);
+        // Otherwise, wait for core reset
+        } else {
+            VPRINTF(LOW, "NMI bit unmasked, wait for TB rst!\n");
+            while(1);
+        }
+    }
+}
+
+void main(void) {
+
+        uint32_t sts;
+        uint8_t test_fail = 0;
+
+        VPRINTF(LOW, "\n----------------------------------\nRAS Smoke Test!!\n----------------------------------\n");
+
+        // Setup the interrupt CSR configuration
+        init_interrupts();
+
+        // Initialize the counter
+        intr_count = 0;
+        boot_count++; // After first boot should be 1
+
+        // Setup the NMI Handler
+        lsu_write_32((uintptr_t) (CLP_SOC_IFC_REG_INTERNAL_NMI_VECTOR), (uint32_t) (nmi_handler));
+
+        // Test Mailbox SRAM ECC
+        if (boot_count == BEFORE_FIRST_ICCM_FAILURE) {
+            test_mbox_sram_ecc(NO_MASK);
+            test_mbox_sram_ecc(WITH_MASK);
+        }
+        // No reset expected following MBOX SRAM ECC Error injection
+
+        // Test ICCM SRAM ECC
+        if      (boot_count == BEFORE_FIRST_ICCM_FAILURE)  {   run_iccm_sram_ecc(NO_MASK  ); }
+        else if (boot_count == BEFORE_SECOND_ICCM_FAILURE) { check_iccm_sram_ecc(NO_MASK  );
+                                                               run_iccm_sram_ecc(WITH_MASK); }
+        else if (boot_count == BEFORE_FIRST_DCCM_FAILURE)  { check_iccm_sram_ecc(WITH_MASK); }
+
+        // Test DCCM SRAM ECC
+        if      (boot_count == BEFORE_FIRST_DCCM_FAILURE){   run_dccm_sram_ecc(NO_MASK  ); }
+        else if (boot_count == BEFORE_FIRST_NMI_FAILURE) { check_dccm_sram_ecc(NO_MASK  );
+                                                             run_dccm_sram_ecc(WITH_MASK);
+                                                           check_dccm_sram_ecc(WITH_MASK); }
+
+        // Test WDT Expiration
+        if      (boot_count == BEFORE_FIRST_NMI_FAILURE) {   run_nmi_test(NO_MASK  ); }
+        else if (boot_count == BEFORE_SECOND_NMI_FAILURE){ check_nmi_test(NO_MASK  );
+                                                             run_nmi_test(WITH_MASK); }
+        else if (boot_count == AFTER_SECOND_NMI_FAILURE) { check_nmi_test(WITH_MASK); }
+
+        // Test Mailbox Protocol Violations (no reset expected)
+        if      (boot_count == AFTER_SECOND_NMI_FAILURE) {   run_mbox_no_lock_error  (  NO_MASK);
+                                                           check_mbox_no_lock_error  (  NO_MASK); 
+                                                             run_mbox_ooo_error      (  NO_MASK);
+                                                           check_mbox_ooo_error      (  NO_MASK);
+                                                             run_mbox_no_lock_error  (WITH_MASK);
+                                                           check_mbox_no_lock_error  (WITH_MASK);
+                                                             run_mbox_ooo_error      (WITH_MASK);
+                                                           check_mbox_ooo_error      (WITH_MASK); }
+
+        // Final Report
+        VPRINTF(MEDIUM, "Eval test progress...\n");
+        for (enum test_list tests = 0; tests < TEST_COUNT; tests++) {
+            if (test_progress_g[tests] != RUN_AND_PASSED) {
+                VPRINTF(ERROR, "Test [%d] failed! Progress: %d\n", tests, test_progress_g[tests]);
+                test_fail = 1;
+            }
+        }
+
+        if (test_fail) {
+            VPRINTF(ERROR, "RAS error injection test failed\n");
+            SEND_STDOUT_CTRL(0x1);
+            while(1);
+        } else {
+            VPRINTF(LOW, "RAS test pass\n");
+        }
+
+        return;
+
+}
diff --git a/src/integration/test_suites/smoke_test_ras/smoke_test_ras.ld b/src/integration/test_suites/smoke_test_ras/smoke_test_ras.ld
new file mode 100644
index 000000000..39fa35419
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_ras/smoke_test_ras.ld
@@ -0,0 +1,69 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+OUTPUT_ARCH( "riscv" )
+ENTRY(_start)
+
+SECTIONS {
+  . = 0x0;
+  .text   : { *(.text*) }
+
+  .eh_frame : { *(.eh_frame) }
+  /* DCCM as VMA */
+  /* Data is bundled with ROM image in iMem */
+  /* Align data to 4-bytes to allow LSU access to work
+   * when copying to DCCM */
+  /* Only upper half of DCCM is used for ROM image */
+  _data_lma_start = ALIGN(4);
+  _data_vma_start = 0x50010000;
+  .data _data_vma_start : AT(_data_lma_start) {  *(.srodata*) ; . = ALIGN(4);} =0x0000,
+  _data_lma_end = _data_lma_start + SIZEOF(.data);
+  _data_vma_end = _data_vma_start + SIZEOF(.data);
+
+  _bss_lma_start = _data_lma_end;
+  _bss_vma_start = _data_vma_end;
+  .bss _bss_vma_start : AT(_bss_lma_start) { *(.sbss) *(.bss) ; . = ALIGN(4);} =0x0000,
+  _bss_lma_end = _bss_lma_start + SIZEOF(.bss);
+  _bss_vma_end = _bss_vma_start + SIZEOF(.bss);
+
+  _end = _bss_lma_end;
+  ASSERT( _end < 0x0000C000, "ERROR: ROM size exceeds 48KiB")
+
+  /* DCCM as VMA and LMA */
+  . = _bss_vma_end;
+  _dccm_lma_start = _bss_vma_end; /* ----\___ SAME */
+  _dccm_vma_start = _bss_vma_end; /* ----/         */
+  .dccm _dccm_vma_start : AT(_dccm_lma_start) { *(.*data) *(.rodata*) *(.dccm*) . = ALIGN(4); } =0x0000,
+  iccm_code0_start = .;
+
+  /* ICCM as VMA */
+  /* All of these sections start at the base address of ICCM, and cannot coexist */
+  /* The code in these sections will be loaded to DCCM alongside .data and later
+   * copied into ICCM for execution.
+   * NOTE: none of these sections will be used by the val image/FMC/RT flows */
+  .data_iccm0 0x40000000 : AT(iccm_code0_start) {*(.data_iccm0) ; . = ALIGN(4); } =0x0000, /* iccm_code0_start, after .data, as LMA */
+  iccm_code0_end = iccm_code0_start + SIZEOF(.data_iccm0);
+  iccm_code1_start = ALIGN(iccm_code0_end,4);
+  .data_iccm1 0x40000000 : AT(iccm_code1_start) {*(.data_iccm1) ; . = ALIGN(4); } =0x0000, /* iccm_code1_start, after .data, as LMA */
+  iccm_code1_end = iccm_code1_start + SIZEOF(.data_iccm1);
+  iccm_code2_start = ALIGN(iccm_code1_end,4);
+  .data_iccm2 0x40000000 : AT(iccm_code2_start) {*(.data_iccm2) ; . = ALIGN(4); } =0x0000, /* iccm_code2_start, after .data, as LMA */
+  iccm_code2_end = iccm_code2_start + SIZEOF(.data_iccm2);
+
+  /* Stack is at the end of DCCM after .data_iccm2 */
+  . = ALIGN(iccm_code2_end,16);
+  STACK = ALIGN(16) + 0x4000;
+  ASSERT( (STACK < 0x50020000), "ERROR: Stack overflows the DCCM -- note: lower half of DCCM is allocated in the validation image for remote firmware images")
+}
diff --git a/src/integration/test_suites/smoke_test_ras/smoke_test_ras.yml b/src/integration/test_suites/smoke_test_ras/smoke_test_ras.yml
new file mode 100755
index 000000000..af6e62ff1
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_ras/smoke_test_ras.yml
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+---
+seed: 1
+testname: smoke_test_ras
diff --git a/src/integration/test_suites/smoke_test_sha256/caliptra_isr.h b/src/integration/test_suites/smoke_test_sha256/caliptra_isr.h
index 6ffd71c0a..8f5779e04 100644
--- a/src/integration/test_suites/smoke_test_sha256/caliptra_isr.h
+++ b/src/integration/test_suites/smoke_test_sha256/caliptra_isr.h
@@ -204,6 +204,22 @@ inline void service_soc_ifc_notif_intr () {
         *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
         cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
     }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
     if (sts == 0) {
         VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
         SEND_STDOUT_CTRL(0x1);
diff --git a/src/integration/test_suites/smoke_test_sha256/smoke_test_sha256.c b/src/integration/test_suites/smoke_test_sha256/smoke_test_sha256.c
index 33a5bce9e..8fff012a9 100644
--- a/src/integration/test_suites/smoke_test_sha256/smoke_test_sha256.c
+++ b/src/integration/test_suites/smoke_test_sha256/smoke_test_sha256.c
@@ -88,7 +88,7 @@ void main() {
     VPRINTF(LOW, "----------------------------------\n");
 
     // Call interrupt init
-    //init_interrupts();
+    init_interrupts();
 
     sha256_io sha256_block;
     sha256_io sha256_digest;
diff --git a/src/integration/test_suites/smoke_test_sha512/caliptra_isr.h b/src/integration/test_suites/smoke_test_sha512/caliptra_isr.h
index b9a1b0bd5..8f5779e04 100644
--- a/src/integration/test_suites/smoke_test_sha512/caliptra_isr.h
+++ b/src/integration/test_suites/smoke_test_sha512/caliptra_isr.h
@@ -32,7 +32,32 @@
 #include <stdint.h>
 #include "printf.h"
 
-extern volatile uint32_t sha512_intr_status;
+/* --------------- symbols/typedefs --------------- */
+typedef struct {
+    uint32_t doe_error;
+    uint32_t doe_notif;
+    uint32_t ecc_error;
+    uint32_t ecc_notif;
+    uint32_t hmac_error;
+    uint32_t hmac_notif;
+    uint32_t kv_error;
+    uint32_t kv_notif;
+    uint32_t sha512_error;
+    uint32_t sha512_notif;
+    uint32_t sha256_error;
+    uint32_t sha256_notif;
+    uint32_t qspi_error;
+    uint32_t qspi_notif;
+    uint32_t uart_error;
+    uint32_t uart_notif;
+    uint32_t i3c_error;
+    uint32_t i3c_notif;
+    uint32_t soc_ifc_error;
+    uint32_t soc_ifc_notif;
+    uint32_t sha512_acc_error;
+    uint32_t sha512_acc_notif;
+} caliptra_intr_received_s;
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
 
 //////////////////////////////////////////////////////////////////////////////
 // Function Declarations
@@ -44,41 +69,179 @@ void init_interrupts(void);
 // These inline functions are used to insert event-specific functionality into the
 // otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr"
 inline void service_doe_error_intr() {return;}
-inline void service_doe_notif_intr() {printf("ERROR");}
-inline void service_ecc_error_intr   () {printf("ERROR");}
-inline void service_ecc_notif_intr   () {printf("ERROR");}
-inline void service_hmac_error_intr  () {printf("ERROR");}
-inline void service_hmac_notif_intr  () {printf("ERROR");}
-inline void service_kv_error_intr    () {printf("ERROR");}
-inline void service_kv_notif_intr    () {printf("ERROR");}
-inline void service_sha512_error_intr() {printf("ERROR");}
+inline void service_doe_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.doe_notif |= DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad doe_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_ecc_error_intr() {return;}
+inline void service_ecc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.ecc_notif |= ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad ecc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_hmac_error_intr() {return;}
+inline void service_hmac_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.hmac_notif |= HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad hmac_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_kv_error_intr() {return;}
+inline void service_kv_notif_intr() {return;}
+inline void service_sha512_error_intr() {return;}
 inline void service_sha512_notif_intr() {
     uint32_t * reg = (uint32_t *) (CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
     uint32_t sts = *reg;
     /* Write 1 to Clear the pending interrupt */
     if (sts & SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
         *reg = SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_notif |= SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
     }
     if (sts == 0) {
-        printf("bad sha512_notif_intr sts:%x\n", sts);
-    } else {
-        reg = (uint32_t *) (CLP_SHA512_REG_SHA512_STATUS);
-        sha512_intr_status = *reg;
+        VPRINTF(ERROR,"bad sha512_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
     }
 }
 
-inline void service_sha256_error_intr() {printf("ERROR");}
-inline void service_sha256_notif_intr() {printf("ERROR");}
-inline void service_qspi_error_intr  () {printf("ERROR");}
-inline void service_qspi_notif_intr  () {printf("ERROR");}
-inline void service_uart_error_intr  () {printf("ERROR");}
-inline void service_uart_notif_intr  () {printf("ERROR");}
-inline void service_i3c_error_intr   () {printf("ERROR");}
-inline void service_i3c_notif_intr   () {printf("ERROR");}
-inline void service_soc_ifc_error_intr  () {printf("ERROR");}
-inline void service_soc_ifc_notif_intr  () {printf("ERROR");}
-inline void service_sha512_acc_error_intr   () {printf("ERROR");}
-inline void service_sha512_acc_notif_intr   () {printf("ERROR");}
+inline void service_sha256_error_intr() {return;}
+inline void service_sha256_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha256_notif |= SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha256_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_qspi_error_intr() {return;}
+inline void service_qspi_notif_intr() {return;}
+inline void service_uart_error_intr() {return;}
+inline void service_uart_notif_intr() {return;}
+inline void service_i3c_error_intr() {return;}
+inline void service_i3c_notif_intr() {return;}
+
+inline void service_soc_ifc_error_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_error_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_soc_ifc_notif_intr () {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha512_acc_error_intr() {return;}
+inline void service_sha512_acc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_acc_notif |= SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_acc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
 
 
 #endif //CALIPTRA_ISR_H
diff --git a/src/integration/test_suites/smoke_test_sha512/smoke_test_sha512.c b/src/integration/test_suites/smoke_test_sha512/smoke_test_sha512.c
new file mode 100644
index 000000000..4f31d91fd
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_sha512/smoke_test_sha512.c
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+#include "caliptra_defines.h"
+#include "caliptra_isr.h"
+#include <string.h>
+#include <stdint.h>
+#include "printf.h"
+#include "sha512.h"
+
+#ifdef CPT_VERBOSITY
+    enum printf_verbosity verbosity_g = CPT_VERBOSITY;
+#else
+    enum printf_verbosity verbosity_g = LOW;
+#endif
+volatile char*    stdout           = (char *)STDOUT;
+volatile uint32_t intr_count       = 0;
+
+volatile caliptra_intr_received_s cptra_intr_rcv = {
+    .doe_error        = 0,
+    .doe_notif        = 0,
+    .ecc_error        = 0,
+    .ecc_notif        = 0,
+    .hmac_error       = 0,
+    .hmac_notif       = 0,
+    .kv_error         = 0,
+    .kv_notif         = 0,
+    .sha512_error     = 0,
+    .sha512_notif     = 0,
+    .sha512_error     = 0,
+    .sha512_notif     = 0,
+    .qspi_error       = 0,
+    .qspi_notif       = 0,
+    .uart_error       = 0,
+    .uart_notif       = 0,
+    .i3c_error        = 0,
+    .i3c_notif        = 0,
+    .soc_ifc_error    = 0,
+    .soc_ifc_notif    = 0,
+    .sha512_acc_error = 0,
+    .sha512_acc_notif = 0,
+};
+
+
+void main() {
+
+    uint32_t block_data[] = {0x61626380,
+                             0x00000000,
+                             0x00000000,
+                             0x00000000,
+                             0x00000000,
+                             0x00000000,
+                             0x00000000,
+                             0x00000000,
+                             0x00000000,
+                             0x00000000,
+                             0x00000000,
+                             0x00000000,
+                             0x00000000,
+                             0x00000000,
+                             0x00000000,
+                             0x00000000,
+                             0x00000000,
+                             0x00000000,
+                             0x00000000,
+                             0x00000000,
+                             0x00000000,
+                             0x00000000,
+                             0x00000000,
+                             0x00000000,
+                             0x00000000,
+                             0x00000000,
+                             0x00000000,
+                             0x00000000,
+                             0x00000000,
+                             0x00000000,
+                             0x00000000,
+                             0x00000018};
+
+    uint32_t expected_digest[] =   {0xDDAF35A1,
+                                    0x93617ABA,
+                                    0xCC417349,
+                                    0xAE204131,
+                                    0x12E6FA4E,
+                                    0x89A97EA2,
+                                    0x0A9EEEE6,
+                                    0x4B55D39A,
+                                    0x2192992A,
+                                    0x274FC1A8,
+                                    0x36BA3C23,
+                                    0xA3FEEBBD,
+                                    0x454D4423,
+                                    0x643CE80E,
+                                    0x2A9AC94F,
+                                    0xA54CA49F};
+                                    
+
+
+    // Entry message
+    VPRINTF(LOW, "----------------------------------\n");
+    VPRINTF(LOW, " SHA512 smoke test !!\n"             );
+    VPRINTF(LOW, "----------------------------------\n");
+
+    // Call interrupt init
+    init_interrupts();
+
+    sha512_io sha512_block;
+    sha512_io sha512_digest;
+
+    sha512_block.data_size = 32;
+    for (int i = 0; i < sha512_block.data_size; i++)
+        sha512_block.data[i] = block_data[i];
+
+    sha512_digest.data_size = 16;
+    for (int i = 0; i < sha512_digest.data_size; i++)
+        sha512_digest.data[i] = expected_digest[i];
+
+    sha512_flow(sha512_block, SHA512_512_MODE, sha512_digest);
+    sha512_zeroize();
+
+    // Write 0xff to STDOUT for TB to terminate test.
+    SEND_STDOUT_CTRL( 0xff);
+    while(1);
+
+}
diff --git a/src/integration/test_suites/smoke_test_sha512/smoke_test_sha512.s b/src/integration/test_suites/smoke_test_sha512/smoke_test_sha512.s
deleted file mode 100644
index 3f26cf86d..000000000
--- a/src/integration/test_suites/smoke_test_sha512/smoke_test_sha512.s
+++ /dev/null
@@ -1,175 +0,0 @@
-// SPDX-License-Identifier: Apache-2.0
-// Copyright 2019 Western Digital Corporation or its affiliates.
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-//
-
-// Assembly code for Hello World
-// Not using only ALU ops for creating the string
-
-
-#include "../includes/caliptra_defines.h"
-#include "./smoke_test_sha512_vectors.s"
-
-// Code to execute
-.section .text
-.global _start
-_start:
-
-    // Clear minstret
-    csrw minstret, zero
-    csrw minstreth, zero
-
-    // Enable Caches in MRAC
-    li x1, 0xaaaaaaaa
-    csrw 0x7c0, x1
-
-    // Initialize MTVEC to point to a dummy interrupt handler prior to entering
-    // main and subsequent (more complex) initialization procedure
-    la t0, early_trap_vector
-    csrw mtvec, t0
-
-    // Init. the stack
-    la sp, STACK
-
-    // Entry message
-    call print_startup
-
-    // Call interrupt init
-    call init_interrupts
-
-    li t4, 0
-    li t5, 1
-
-    write_msg_loop:
-        // loop cnt, indicate whether it's the first block
-        addi t4, t4, 1
-
-        // Load block from hw_data and write to SHA512 core
-        li x3, CLP_SHA512_REG_SHA512_BLOCK_0
-        li x1, CLP_SHA512_REG_SHA512_BLOCK_31
-        // set t3 to constantly tracking current ptr
-        la t3, SHA512ShortMsg
-        // set x7 as last word check
-        lw x7, 0(t3)
-        addi t3, t3, 4
-        write_block_loop:
-            lw x5, 0(t3) 
-
-            sw x5, 0(x3)
-            addi t3, t3, 4
-            addi x3, x3, 4
-            ble x3, x1, write_block_loop
-
-        // store the last word for further checking
-        mv x6, x5
-
-        // Enable SHA512 core
-        li x3, CLP_SHA512_REG_SHA512_CTRL
-        li x4, SHA512_NEXT
-        bne t4, t5, indicate_next
-        li x4, SHA512_INIT
-        indicate_next:
-            sw x4, 0(x3)
-
-        // wait for SHA512 process
-        la x3, sha512_intr_status
-        li x1, SHA512_VALID
-        ready_loop:
-            lw x5, 0(x3)
-            bne x5, x1, ready_loop
-        sw x0, 0(x3) // clear status variable
-
-        // check if reaches the last block of message
-        bne x6, x7, write_msg_loop
-
-    // Read the data back from SHA512 register
-    li x3, CLP_SHA512_REG_SHA512_DIGEST_0
-    li x1, CLP_SHA512_REG_SHA512_DIGEST_15
-    la x4, SHA512ShortMsg
-    addi x4, x4, 132
-    read_result_loop:
-        lw x5, 0(x3)
-        lw t2, 0(x4)
-        beq x5, t2, equal
-        li x6, STDOUT
-        li x7, 0x01
-        sb x7, 0(x6)
-        equal:
-            addi x3, x3, 4
-            addi x4, x4, 4
-            ble x3, x1, read_result_loop
-
-
-// Write 0xff to STDOUT for TB to terminate test.
-_finish:
-    li x3, STDOUT
-    addi x5, x0, 0xff
-    sb x5, 0(x3)
-    beq x0, x0, _finish
-.rept 100
-    nop
-.endr
-
-print_startup:
-    li x3, STDOUT
-    la x4, print_data
-    j loop
-
-print_loop:
-    li x3, STDOUT
-    la x4, loop_data
-    j loop
-
-loop:
-   lb x5, 0(x4)
-   sb x5, 0(x3)
-   addi x4, x4, 1
-   bnez x5, loop
-   ret
-
-// .data is in ROM now, can't write to intr_count there...
-.section .dccm
-.global stdout
-stdout: .word STDOUT
-.global intr_count
-intr_count: .word 0
-.global verbosity_g
-verbosity_g: .word 2
-// FW polls this variable instead of the SHA512 reg....
-.global sha512_intr_status
-sha512_intr_status: .word 0
-print_data:
-.ascii "----------------------------------------\n"
-.ascii "Running SHA512 Smoke Test             !!\n"
-.ascii "----------------------------------------\n"
-.byte 0
-loop_data:
-.ascii "End of block loop\n"
-.byte 0
-
-// From SiFive Interrupt Cookbook:
-// https://sifive.cdn.prismic.io/sifive/0d163928-2128-42be-a75a-464df65e04e0_sifive-interrupt-cookbook.pdf
-//
-/* For sanity's sake we set up an early trap vector that just does nothing. If
-* you end up here then there's a bug in the early boot code somewhere. */
-.section .text.metal.init.trapvec
-.align 2 /* Aligns to 4-bytes (log2(4) = 2) */
-.global early_trap_vector
-early_trap_vector:
-.cfi_startproc
-csrr t0, mcause
-csrr t1, mepc
-csrr t2, mtval
-j early_trap_vector
-.cfi_endproc
diff --git a/src/integration/test_suites/smoke_test_sha512/smoke_test_sha512_vectors.s b/src/integration/test_suites/smoke_test_sha512/smoke_test_sha512_vectors.s
deleted file mode 100644
index bc3afe356..000000000
--- a/src/integration/test_suites/smoke_test_sha512/smoke_test_sha512_vectors.s
+++ /dev/null
@@ -1,223401 +0,0 @@
-/*
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-.section .dccm
-hw_data:
-// start of input message
-.word 0x61626380
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000018
-// expected value
-.word 0xDDAF35A1
-.word 0x93617ABA
-.word 0xCC417349
-.word 0xAE204131
-.word 0x12E6FA4E
-.word 0x89A97EA2
-.word 0x0A9EEEE6
-.word 0x4B55D39A
-.word 0x2192992A
-.word 0x274FC1A8
-.word 0x36BA3C23
-.word 0xA3FEEBBD
-.word 0x454D4423
-.word 0x643CE80E
-.word 0x2A9AC94F
-.word 0xA54CA49F
-// .ascii "----------------------------------\n"
-// .ascii "SHA512 test !!\n"
-// .ascii "----------------------------------\n"
-// .byte 0
-SHA512ShortMsg:
-// SHA512ShortMsgvector_2
-// vector length
-.word 0x00000008
-// input message
-.word 0x21800000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000000
-.word 0x00000008
-// expected output
-.word 0x3831a6a6
-.word 0x155e509d
-.word 0xee59a7f4
-.word 0x51eb3532
-.word 0x4d8f8f2d
-.word 0xf6e37088
-.word 0x94740f98
-.word 0xfdee2388
-.word 0x9f4de5ad
-.word 0xb0c5010d
-.word 0xfb555cda
-.word 0x77c8ab5d
-.word 0xc902094c
-.word 0x52de3278
-.word 0xf35a75eb
-.word 0xc25f093a
-//// SHA512ShortMsgvector_3
-//// vector length
-//.word 0x00000010
-//// input message
-//.word 0x90838000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000010
-//// expected output
-//.word 0x55586ebb
-//.word 0xa48768ae
-//.word 0xb323655a
-//.word 0xb6f4298f
-//.word 0xc9f67096
-//.word 0x4fc2e5f2
-//.word 0x731e34df
-//.word 0xa4b0c09e
-//.word 0x6e1e12e3
-//.word 0xd7286b31
-//.word 0x45c61c20
-//.word 0x47fb1a2a
-//.word 0x1297f36d
-//.word 0xa64160b3
-//.word 0x1fa4c8c2
-//.word 0xcddd2fb4
-//// SHA512ShortMsgvector_4
-//// vector length
-//.word 0x00000018
-//// input message
-//.word 0x0a55db80
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000018
-//// expected output
-//.word 0x7952585e
-//.word 0x5330cb24
-//.word 0x7d72bae6
-//.word 0x96fc8a6b
-//.word 0x0f7d0804
-//.word 0x577e347d
-//.word 0x99bc1b11
-//.word 0xe52f3849
-//.word 0x85a42844
-//.word 0x9382306a
-//.word 0x89261ae1
-//.word 0x43c2f3fb
-//.word 0x613804ab
-//.word 0x20b42dc0
-//.word 0x97e5bf4a
-//.word 0x96ef919b
-//// SHA512ShortMsgvector_5
-//// vector length
-//.word 0x00000020
-//// input message
-//.word 0x23be86d5
-//.word 0x80000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000020
-//// expected output
-//.word 0x76d42c8e
-//.word 0xadea35a6
-//.word 0x9990c63a
-//.word 0x762f3306
-//.word 0x14a46999
-//.word 0x77f058ad
-//.word 0xb988f406
-//.word 0xfb0be8f2
-//.word 0xea3dce3a
-//.word 0x2bbd1d82
-//.word 0x7b70b9b2
-//.word 0x99ae6f9e
-//.word 0x5058ee97
-//.word 0xb50bd492
-//.word 0x2d6d37dd
-//.word 0xc761f8eb
-//// SHA512ShortMsgvector_6
-//// vector length
-//.word 0x00000028
-//// input message
-//.word 0xeb0ca946
-//.word 0xc1800000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000028
-//// expected output
-//.word 0xd39ecedf
-//.word 0xe6e705a8
-//.word 0x21aee4f5
-//.word 0x8bfc489c
-//.word 0x3d9433eb
-//.word 0x4ac1b03a
-//.word 0x97e321a2
-//.word 0x586b40dd
-//.word 0x0522f40f
-//.word 0xa5aef36a
-//.word 0xfff591a7
-//.word 0x8c916bfc
-//.word 0x6d1ca515
-//.word 0xc4983dd8
-//.word 0x695b1ec7
-//.word 0x951d723e
-//// SHA512ShortMsgvector_7
-//// vector length
-//.word 0x00000030
-//// input message
-//.word 0x38667f39
-//.word 0x277b8000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000030
-//// expected output
-//.word 0x85708b8f
-//.word 0xf05d974d
-//.word 0x6af0801c
-//.word 0x152b95f5
-//.word 0xfa5c06af
-//.word 0x9a35230c
-//.word 0x5bea2752
-//.word 0xf031f9bd
-//.word 0x84bd8447
-//.word 0x17b3add3
-//.word 0x08a70dc7
-//.word 0x77f90813
-//.word 0xc20b47b1
-//.word 0x6385664e
-//.word 0xefc88449
-//.word 0xf04f2131
-//// SHA512ShortMsgvector_8
-//// vector length
-//.word 0x00000038
-//// input message
-//.word 0xb39f71aa
-//.word 0xa8a10880
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000038
-//// expected output
-//.word 0x258b8efa
-//.word 0x05b4a06b
-//.word 0x1e63c7a3
-//.word 0xf925c5ef
-//.word 0x11fa03e3
-//.word 0xd47d631b
-//.word 0xf4d47498
-//.word 0x3783d8c0
-//.word 0xb0944900
-//.word 0x9e842fc9
-//.word 0xfa15de58
-//.word 0x6c67cf89
-//.word 0x55a17d79
-//.word 0x0b20f41d
-//.word 0xadf67ee8
-//.word 0xcdcdfce6
-//// SHA512ShortMsgvector_9
-//// vector length
-//.word 0x00000040
-//// input message
-//.word 0x6f8d58b7
-//.word 0xcab1888c
-//.word 0x80000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000040
-//// expected output
-//.word 0xa3941def
-//.word 0x2803c8df
-//.word 0xc08f20c0
-//.word 0x6ba7e9a3
-//.word 0x32ae0c67
-//.word 0xe47ae573
-//.word 0x65c243ef
-//.word 0x40059b11
-//.word 0xbe22c91d
-//.word 0xa6a80c2c
-//.word 0xff0742a8
-//.word 0xf4bcd941
-//.word 0xbdee0b86
-//.word 0x1ec872b2
-//.word 0x15433ce8
-//.word 0xdcf3c031
-//// SHA512ShortMsgvector_10
-//// vector length
-//.word 0x00000048
-//// input message
-//.word 0x162b0cf9
-//.word 0xb3750f94
-//.word 0x38800000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000048
-//// expected output
-//.word 0xade21730
-//.word 0x5dc34392
-//.word 0xaa4b8e57
-//.word 0xf64f5a3a
-//.word 0xfdd27f1f
-//.word 0xa969a9a2
-//.word 0x608353f8
-//.word 0x2b95cfb4
-//.word 0xae84598d
-//.word 0x01575a57
-//.word 0x8a1068a5
-//.word 0x9b34b504
-//.word 0x5ff6d529
-//.word 0x9c5cb7ee
-//.word 0x17180701
-//.word 0xb2d1d695
-//// SHA512ShortMsgvector_11
-//// vector length
-//.word 0x00000050
-//// input message
-//.word 0xbad7c618
-//.word 0xf45be207
-//.word 0x975e8000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000050
-//// expected output
-//.word 0x58868289
-//.word 0x59d1f822
-//.word 0x54068be0
-//.word 0xbd14b6a8
-//.word 0x8f59f534
-//.word 0x061fb203
-//.word 0x76a05410
-//.word 0x52dd3635
-//.word 0xedf3c6f0
-//.word 0xca3d0877
-//.word 0x5e13525d
-//.word 0xf9333a21
-//.word 0x13c0b2af
-//.word 0x76515887
-//.word 0x529910b6
-//.word 0xc793c8a5
-//// SHA512ShortMsgvector_12
-//// vector length
-//.word 0x00000058
-//// input message
-//.word 0x6213e10a
-//.word 0x4420e0d9
-//.word 0xb7703780
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000058
-//// expected output
-//.word 0x9982dc2a
-//.word 0x04dff165
-//.word 0x567f276f
-//.word 0xd463efef
-//.word 0x2b369fa2
-//.word 0xfbca8cee
-//.word 0x31ce0de8
-//.word 0xa79a2eb0
-//.word 0xb53e437f
-//.word 0x7d9d1f41
-//.word 0xc71d725c
-//.word 0xabb949b5
-//.word 0x13075bad
-//.word 0x1740c9ee
-//.word 0xfbf6a5c6
-//.word 0x633400c7
-//// SHA512ShortMsgvector_13
-//// vector length
-//.word 0x00000060
-//// input message
-//.word 0x6332c3c2
-//.word 0xa0a625a6
-//.word 0x1df71858
-//.word 0x80000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000060
-//// expected output
-//.word 0x9d60375d
-//.word 0x9858d9f2
-//.word 0x416fb86f
-//.word 0xa0a2189e
-//.word 0xe4213e87
-//.word 0x10314fd1
-//.word 0xebed0fd1
-//.word 0x58b043e6
-//.word 0xe7c9a76d
-//.word 0x62c6ba1e
-//.word 0x1d411a73
-//.word 0x0902309e
-//.word 0xc676dd49
-//.word 0x1433c6ef
-//.word 0x66c8f116
-//.word 0x233d6ce7
-//// SHA512ShortMsgvector_14
-//// vector length
-//.word 0x00000068
-//// input message
-//.word 0xf47be3a2
-//.word 0xb019d1be
-//.word 0xededf5b8
-//.word 0x0c800000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000068
-//// expected output
-//.word 0xb9429262
-//.word 0x5caa28c7
-//.word 0xbe24a099
-//.word 0x7eb73280
-//.word 0x62a76d9b
-//.word 0x529c0f1d
-//.word 0x568f850d
-//.word 0xf6d569b5
-//.word 0xe84df07e
-//.word 0x9e246be2
-//.word 0x32033ffa
-//.word 0xc3adf2d1
-//.word 0x8f92ab9d
-//.word 0xacfc0ecf
-//.word 0x08aff714
-//.word 0x5f0b833b
-//// SHA512ShortMsgvector_15
-//// vector length
-//.word 0x00000070
-//// input message
-//.word 0xb1715f78
-//.word 0x2ff02c6b
-//.word 0x88937f05
-//.word 0x41168000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000070
-//// expected output
-//.word 0xee1a56ee
-//.word 0x78182ec4
-//.word 0x1d2c3ab3
-//.word 0x3d4c4187
-//.word 0x1d437c5c
-//.word 0x1ca060ee
-//.word 0x9e219cb8
-//.word 0x3689b4e5
-//.word 0xa4174dfd
-//.word 0xab5d1d10
-//.word 0x96a31a7c
-//.word 0x8d3abda7
-//.word 0x5c1b5e6d
-//.word 0xa97e1814
-//.word 0x901c505b
-//.word 0x0bc07f25
-//// SHA512ShortMsgvector_16
-//// vector length
-//.word 0x00000078
-//// input message
-//.word 0x9bcd5262
-//.word 0x868cd9c8
-//.word 0xa96c9e82
-//.word 0x987f0380
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000078
-//// expected output
-//.word 0x2e07662a
-//.word 0x001b9755
-//.word 0xae922c8e
-//.word 0x8a95756d
-//.word 0xb5341dc0
-//.word 0xf2e62ae1
-//.word 0xcf827038
-//.word 0xf33ce055
-//.word 0xf63ad5c0
-//.word 0x0b653914
-//.word 0x28434ddc
-//.word 0x01e5535e
-//.word 0x7fecbf53
-//.word 0xdb66d930
-//.word 0x99b8e0b7
-//.word 0xe44e4b25
-//// SHA512ShortMsgvector_17
-//// vector length
-//.word 0x00000080
-//// input message
-//.word 0xcd67bd40
-//.word 0x54aaa3ba
-//.word 0xa0db178c
-//.word 0xe232fd5a
-//.word 0x80000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000080
-//// expected output
-//.word 0x0d8521f8
-//.word 0xf2f39003
-//.word 0x32d1a1a5
-//.word 0x5c60ba81
-//.word 0xd04d28df
-//.word 0xe8c504b6
-//.word 0x328ae787
-//.word 0x925fe018
-//.word 0x8f2ba91c
-//.word 0x3a9f0c16
-//.word 0x53c4bf0a
-//.word 0xda356455
-//.word 0xea36fd31
-//.word 0xf8e73e39
-//.word 0x51cad4eb
-//.word 0xba8c6e04
-//// SHA512ShortMsgvector_18
-//// vector length
-//.word 0x00000088
-//// input message
-//.word 0x6ba004fd
-//.word 0x176791ef
-//.word 0xb381b862
-//.word 0xe298c67b
-//.word 0x08800000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000088
-//// expected output
-//.word 0x112e1914
-//.word 0x4a9c51a2
-//.word 0x23a002b9
-//.word 0x77459920
-//.word 0xe38afd4c
-//.word 0xa610bd1c
-//.word 0x532349e9
-//.word 0xfa7c0d50
-//.word 0x3215c01a
-//.word 0xd70e1b2a
-//.word 0xc5133cf2
-//.word 0xd10c9e8c
-//.word 0x1a4c9405
-//.word 0xf291da2d
-//.word 0xc45f7067
-//.word 0x61c5e8fe
-//// SHA512ShortMsgvector_19
-//// vector length
-//.word 0x00000090
-//// input message
-//.word 0xc6a17093
-//.word 0x65686510
-//.word 0x20edfe15
-//.word 0xdf8012ac
-//.word 0xda8d8000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000090
-//// expected output
-//.word 0xc36c100c
-//.word 0xdb6c8c45
-//.word 0xb072f182
-//.word 0x56d63a66
-//.word 0xc9843acb
-//.word 0x4d07de62
-//.word 0xe0600711
-//.word 0xd4fbe64c
-//.word 0x8cf314ec
-//.word 0x3457c903
-//.word 0x08147cb7
-//.word 0xac7e4d07
-//.word 0x3ba10f0c
-//.word 0xed78ea72
-//.word 0x4a474b32
-//.word 0xdae71231
-//// SHA512ShortMsgvector_20
-//// vector length
-//.word 0x00000098
-//// input message
-//.word 0x61be0c9f
-//.word 0x5cf62745
-//.word 0xc7da47c1
-//.word 0x04597194
-//.word 0xdb245c80
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000098
-//// expected output
-//.word 0xb379249a
-//.word 0x3ca5f14c
-//.word 0x29456710
-//.word 0x114ba6f6
-//.word 0x136b34c3
-//.word 0xfc9f6fb9
-//.word 0x1b59d491
-//.word 0xaf782d6b
-//.word 0x237eb71a
-//.word 0xaffdd380
-//.word 0x79461cf6
-//.word 0x90a46d9a
-//.word 0x4ddd602d
-//.word 0x19808ab6
-//.word 0x235d1d8a
-//.word 0xa01e8200
-//// SHA512ShortMsgvector_21
-//// vector length
-//.word 0x000000A0
-//// input message
-//.word 0xe07056d4
-//.word 0xf7277bc5
-//.word 0x48099577
-//.word 0x720a581e
-//.word 0xec94141d
-//.word 0x80000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000000A0
-//// expected output
-//.word 0x59f18563
-//.word 0x03ff165e
-//.word 0x2ab5683d
-//.word 0xddeb6e8a
-//.word 0xd81f15bb
-//.word 0x578579b9
-//.word 0x99eb5746
-//.word 0x680f22cf
-//.word 0xec6dba74
-//.word 0x1e591ca4
-//.word 0xd9e53904
-//.word 0x837701b3
-//.word 0x74be74bb
-//.word 0xc0847a92
-//.word 0x179ac2b6
-//.word 0x7496d807
-//// SHA512ShortMsgvector_22
-//// vector length
-//.word 0x000000A8
-//// input message
-//.word 0x67ebda0a
-//.word 0x3573a9a5
-//.word 0x8751d416
-//.word 0x9e10c7e8
-//.word 0x663febb3
-//.word 0xa8800000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000000A8
-//// expected output
-//.word 0x13963f81
-//.word 0xcfabfca7
-//.word 0x1de4739f
-//.word 0xd24a10ce
-//.word 0x3897bba1
-//.word 0xd716907f
-//.word 0xc0a28490
-//.word 0xc192a7fc
-//.word 0x3ccb8db1
-//.word 0xf91af7a2
-//.word 0xd250d661
-//.word 0x7f0dfd15
-//.word 0x19d221d6
-//.word 0x18a02e3e
-//.word 0x3fa9041c
-//.word 0xf35ed1ea
-//// SHA512ShortMsgvector_23
-//// vector length
-//.word 0x000000B0
-//// input message
-//.word 0x63e09db9
-//.word 0x9eb4cd62
-//.word 0x38677859
-//.word 0xa567df31
-//.word 0x3c8520d8
-//.word 0x45b48000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000000B0
-//// expected output
-//.word 0x9083e534
-//.word 0x8b08eb98
-//.word 0x10b2d157
-//.word 0x81d82658
-//.word 0x45410de5
-//.word 0x4fe61750
-//.word 0xd4b93853
-//.word 0x690649ad
-//.word 0xc6e72490
-//.word 0xbc2b7c36
-//.word 0x5e239057
-//.word 0x3d9414be
-//.word 0xcc093971
-//.word 0x9e0cb78e
-//.word 0xca6b2c80
-//.word 0xc2fda920
-//// SHA512ShortMsgvector_24
-//// vector length
-//.word 0x000000B8
-//// input message
-//.word 0xf3e06b4b
-//.word 0xd79e380a
-//.word 0x65cb679a
-//.word 0x98ccd732
-//.word 0x563cc5eb
-//.word 0xe892e280
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000000B8
-//// expected output
-//.word 0x6b315f10
-//.word 0x6b07c59e
-//.word 0xedc5ab1d
-//.word 0xf813b3c0
-//.word 0xb903060e
-//.word 0x7217cc01
-//.word 0x0e907027
-//.word 0x8512a885
-//.word 0x008dac8b
-//.word 0x2472a521
-//.word 0xe77835a7
-//.word 0xf4deadc1
-//.word 0xd591aa23
-//.word 0xb624b699
-//.word 0x48a99bb6
-//.word 0x0121c54e
-//// SHA512ShortMsgvector_25
-//// vector length
-//.word 0x000000C0
-//// input message
-//.word 0x16b17074
-//.word 0xd3e3d975
-//.word 0x57f9ed77
-//.word 0xd920b4b1
-//.word 0xbff4e845
-//.word 0xb345a922
-//.word 0x80000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000000C0
-//// expected output
-//.word 0x68841345
-//.word 0x82a76004
-//.word 0x6433abcb
-//.word 0xd53db8ff
-//.word 0x1a899958
-//.word 0x62f305b8
-//.word 0x87020f6d
-//.word 0xa6c7b903
-//.word 0xa314721e
-//.word 0x972bf438
-//.word 0x483f452a
-//.word 0x8b095962
-//.word 0x98a576c9
-//.word 0x03c91df4
-//.word 0xa414c7bd
-//.word 0x20fd1d07
-//// SHA512ShortMsgvector_26
-//// vector length
-//.word 0x000000C8
-//// input message
-//.word 0x3edf9325
-//.word 0x1349d228
-//.word 0x06bed253
-//.word 0x45fd5c19
-//.word 0x0aac96d6
-//.word 0xcdb2d758
-//.word 0xb8800000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000000C8
-//// expected output
-//.word 0x299e0daf
-//.word 0x6605e5b0
-//.word 0xc30e1ec8
-//.word 0xbb98e7a3
-//.word 0xbd7b33b3
-//.word 0x88bdb457
-//.word 0x452dab50
-//.word 0x9594406c
-//.word 0x8e7b841e
-//.word 0x6f4e75c8
-//.word 0xd6fbd614
-//.word 0xd5eb9e56
-//.word 0xc359bfaf
-//.word 0xb4285754
-//.word 0x787ab72b
-//.word 0x46dd33f0
-//// SHA512ShortMsgvector_27
-//// vector length
-//.word 0x000000D0
-//// input message
-//.word 0xb2d5a14f
-//.word 0x01e6b778
-//.word 0x888c562a
-//.word 0x059ec819
-//.word 0xad89992d
-//.word 0x16a09f7a
-//.word 0x54b48000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000000D0
-//// expected output
-//.word 0xab2e7d74
-//.word 0x5d8ad393
-//.word 0x439af2a3
-//.word 0xfbc9cdc2
-//.word 0x5510d4a0
-//.word 0x4e78b526
-//.word 0xe12b1c0b
-//.word 0xe3b22966
-//.word 0x872ebe65
-//.word 0x2e2f46ed
-//.word 0x5c5acecd
-//.word 0x2f233a91
-//.word 0x75dd295e
-//.word 0xbeb3a070
-//.word 0x6fc66fa1
-//.word 0xb137042b
-//// SHA512ShortMsgvector_28
-//// vector length
-//.word 0x000000D8
-//// input message
-//.word 0x844b66f1
-//.word 0x2ba0c5f9
-//.word 0xe92731f5
-//.word 0x71539d1e
-//.word 0xef332e15
-//.word 0x49a49dbf
-//.word 0xa4c6de80
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000000D8
-//// expected output
-//.word 0xc3f9c578
-//.word 0x19257747
-//.word 0x83ae9d83
-//.word 0x9772d751
-//.word 0x3dfcea8c
-//.word 0x5af8da26
-//.word 0x2c196f9f
-//.word 0xe80135b2
-//.word 0xb0c8c6ca
-//.word 0x0a1604e0
-//.word 0xa3460247
-//.word 0x620de20b
-//.word 0x299f2db7
-//.word 0x871982d2
-//.word 0x7c2176ae
-//.word 0x5fa7ad65
-//// SHA512ShortMsgvector_29
-//// vector length
-//.word 0x000000E0
-//// input message
-//.word 0x6b6cc692
-//.word 0xd39860b1
-//.word 0xf3020365
-//.word 0x3e25d09c
-//.word 0x01e6a804
-//.word 0x3c1a9cb8
-//.word 0xb249a41e
-//.word 0x80000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000000E0
-//// expected output
-//.word 0x2e5263d9
-//.word 0xa4f21b21
-//.word 0x0e0e161e
-//.word 0xd39df441
-//.word 0x02864325
-//.word 0x78864726
-//.word 0x1a6e70ea
-//.word 0x4b1ee0ab
-//.word 0xb57b5749
-//.word 0x9bc82158
-//.word 0xd82336dd
-//.word 0x53f1ef44
-//.word 0x64c6a081
-//.word 0x26e138b2
-//.word 0xcc0892f7
-//.word 0x65f6af85
-//// SHA512ShortMsgvector_30
-//// vector length
-//.word 0x000000E8
-//// input message
-//.word 0xab1fc9ee
-//.word 0x845eeb20
-//.word 0x5ec13725
-//.word 0xdaf1fb1f
-//.word 0x5d50629b
-//.word 0x14ea9a22
-//.word 0x35a9350a
-//.word 0x88800000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000000E8
-//// expected output
-//.word 0x72d188a9
-//.word 0xdf5f3b00
-//.word 0x057bca22
-//.word 0xc92c0f82
-//.word 0x28422d97
-//.word 0x4302d22d
-//.word 0x4b322e7a
-//.word 0x6c8fc3b2
-//.word 0xb50ec74c
-//.word 0x6842781f
-//.word 0x29f7075c
-//.word 0x3d4bd065
-//.word 0x87864884
-//.word 0x6c39bb3e
-//.word 0x4e2692c0
-//.word 0xf053f7ed
-//// SHA512ShortMsgvector_31
-//// vector length
-//.word 0x000000F0
-//// input message
-//.word 0x594ed82a
-//.word 0xcfc03c0e
-//.word 0x359cc560
-//.word 0xb8e4b85f
-//.word 0x6ee77ee5
-//.word 0x9a70023c
-//.word 0x2b3d5b32
-//.word 0x85b28000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000000F0
-//// expected output
-//.word 0x5ef322cb
-//.word 0x4014ecbb
-//.word 0x713a1365
-//.word 0x9612a222
-//.word 0x225984d3
-//.word 0x1c187deb
-//.word 0xc4459ba7
-//.word 0x901f03da
-//.word 0xc775400a
-//.word 0xcfe3510b
-//.word 0x306b7989
-//.word 0x4fb0e843
-//.word 0x7b412150
-//.word 0xc9193ee5
-//.word 0xa2164306
-//.word 0xebb78301
-//// SHA512ShortMsgvector_32
-//// vector length
-//.word 0x000000F8
-//// input message
-//.word 0xf2c66efb
-//.word 0xf2a76c5b
-//.word 0x041860ea
-//.word 0x576103cd
-//.word 0x8c6b25e5
-//.word 0x0eca9ff6
-//.word 0xa2fa8808
-//.word 0x3fe9ac80
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000000F8
-//// expected output
-//.word 0x7978f93e
-//.word 0xf7ed02c4
-//.word 0xa24abecb
-//.word 0xa124d14d
-//.word 0xd214e149
-//.word 0x2ff1e168
-//.word 0x304c0eab
-//.word 0x89637da0
-//.word 0xf7a569c4
-//.word 0x3dc4562b
-//.word 0xdb9404a0
-//.word 0x18b6314f
-//.word 0xe0eebacc
-//.word 0xfb25ba76
-//.word 0x506aa7e9
-//.word 0xdcd956a7
-//// SHA512ShortMsgvector_33
-//// vector length
-//.word 0x00000100
-//// input message
-//.word 0x8ccb08d2
-//.word 0xa1a282aa
-//.word 0x8cc99902
-//.word 0xecaf0f67
-//.word 0xa9f21cff
-//.word 0xe28005cb
-//.word 0x27fcf129
-//.word 0xe963f99d
-//.word 0x80000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000100
-//// expected output
-//.word 0x4551def2
-//.word 0xf9127386
-//.word 0xeea8d4da
-//.word 0xe1ea8d8e
-//.word 0x49b2add0
-//.word 0x509f27cc
-//.word 0xbce7d9e9
-//.word 0x50ac7db0
-//.word 0x1d5bca57
-//.word 0x9c271b9f
-//.word 0x2d806730
-//.word 0xd88f5825
-//.word 0x2fd0c258
-//.word 0x7851c3ac
-//.word 0x8a0e72b4
-//.word 0xe1dc0da6
-//// SHA512ShortMsgvector_34
-//// vector length
-//.word 0x00000108
-//// input message
-//.word 0x9f8c4932
-//.word 0x0af9370c
-//.word 0xd3db20e9
-//.word 0xb50d3eaa
-//.word 0x59a6232d
-//.word 0x7a86fb7d
-//.word 0x472f1245
-//.word 0x08d7968b
-//.word 0x05800000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000108
-//// expected output
-//.word 0x81b002f1
-//.word 0x5c4d48be
-//.word 0x8517f7ed
-//.word 0x89df302f
-//.word 0xb1435c94
-//.word 0x35efefed
-//.word 0x58f3eb8e
-//.word 0xa1191062
-//.word 0x3f1eb902
-//.word 0x8a66e021
-//.word 0x21a7f08a
-//.word 0x7c604226
-//.word 0xf2324f48
-//.word 0x3e91548d
-//.word 0xbbd2c441
-//.word 0xab704ce5
-//// SHA512ShortMsgvector_35
-//// vector length
-//.word 0x00000110
-//// input message
-//.word 0x4ab9aa06
-//.word 0x9475e54b
-//.word 0x25e5688a
-//.word 0x52dd4acd
-//.word 0x134169c8
-//.word 0x58105f01
-//.word 0xa0a1b134
-//.word 0xc72d4af5
-//.word 0x1f8e8000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000110
-//// expected output
-//.word 0x48ba5a63
-//.word 0xaba7e7bd
-//.word 0x8e420475
-//.word 0x331125a9
-//.word 0x47928c67
-//.word 0xfdb00f65
-//.word 0xc4080d9a
-//.word 0x0b99c067
-//.word 0x2424e76a
-//.word 0x1ba6bd76
-//.word 0xdfe492c7
-//.word 0x30f6f9ad
-//.word 0xccaee7bb
-//.word 0x11571aad
-//.word 0xb31f6bb6
-//.word 0x28cfa933
-//// SHA512ShortMsgvector_36
-//// vector length
-//.word 0x00000118
-//// input message
-//.word 0xf0c1d340
-//.word 0x7de92ef7
-//.word 0x421e42df
-//.word 0x5c9ab31d
-//.word 0x2ec0a750
-//.word 0xa9522869
-//.word 0xcbe4cabd
-//.word 0x66908d58
-//.word 0x23ec0480
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000118
-//// expected output
-//.word 0x9e75c5bc
-//.word 0xa2c2af1d
-//.word 0x7739787f
-//.word 0x46e1d981
-//.word 0xc4f98e49
-//.word 0x3d0724b5
-//.word 0x252c2fba
-//.word 0xe3c52671
-//.word 0x9f1d27e6
-//.word 0xccd0d705
-//.word 0x240281e8
-//.word 0xfbf3db75
-//.word 0xb9b3205c
-//.word 0x1413436d
-//.word 0x3b5d1400
-//.word 0x04b8cca1
-//// SHA512ShortMsgvector_37
-//// vector length
-//.word 0x00000120
-//// input message
-//.word 0xae8c9f8f
-//.word 0xb41b519b
-//.word 0x6d943833
-//.word 0xfe1c32d1
-//.word 0xc4292fb1
-//.word 0xddf1dbe2
-//.word 0xeb227d9e
-//.word 0x14d31ed7
-//.word 0x4ebaef12
-//.word 0x80000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000120
-//// expected output
-//.word 0x042f9fd0
-//.word 0xa4ed3d9f
-//.word 0xec3655ae
-//.word 0x11011c6f
-//.word 0x2bc7e457
-//.word 0xe8812b6d
-//.word 0x8be2cd45
-//.word 0xfc6c432a
-//.word 0x94558c88
-//.word 0xf22c0143
-//.word 0x9618865e
-//.word 0x8e49e509
-//.word 0xc448b342
-//.word 0xca914b12
-//.word 0x0344aaf7
-//.word 0xbcbdca18
-//// SHA512ShortMsgvector_38
-//// vector length
-//.word 0x00000128
-//// input message
-//.word 0xda39fb86
-//.word 0x237f0030
-//.word 0x3844e61f
-//.word 0xc6cfe779
-//.word 0xe42af533
-//.word 0x49839590
-//.word 0xbcd2f0e4
-//.word 0xcbbc279e
-//.word 0xc0b7e885
-//.word 0xd1800000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000128
-//// expected output
-//.word 0xecb43de8
-//.word 0xc233a731
-//.word 0xb38e30c5
-//.word 0x696f8876
-//.word 0x761b7ea7
-//.word 0x2efe283f
-//.word 0xd07bedf2
-//.word 0x0029f47c
-//.word 0x6d2a4427
-//.word 0x823e100f
-//.word 0xb087abaf
-//.word 0x22d7eff4
-//.word 0x2a951c97
-//.word 0xc3dd05f4
-//.word 0x8a20163f
-//.word 0xa4367cba
-//// SHA512ShortMsgvector_39
-//// vector length
-//.word 0x00000130
-//// input message
-//.word 0x3e7271d2
-//.word 0x070ef095
-//.word 0x394620c4
-//.word 0xb016576c
-//.word 0x150f34be
-//.word 0xa6078461
-//.word 0x3a0f660d
-//.word 0x7fa5ae56
-//.word 0x872b88c5
-//.word 0x83988000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000130
-//// expected output
-//.word 0x8154d0da
-//.word 0x634ab226
-//.word 0x6061acc1
-//.word 0x23acb407
-//.word 0x650ffe91
-//.word 0x64a22de3
-//.word 0xfe29bf05
-//.word 0x393b2aec
-//.word 0xe92cf4db
-//.word 0x00ea5b43
-//.word 0x41c31ddb
-//.word 0x7de15168
-//.word 0x3c8a71b5
-//.word 0xa44d5c31
-//.word 0x75790fea
-//.word 0xc67d18ee
-//// SHA512ShortMsgvector_40
-//// vector length
-//.word 0x00000138
-//// input message
-//.word 0x311fb67f
-//.word 0x6a0784bb
-//.word 0x01a2d5a3
-//.word 0xf3092c40
-//.word 0x7a9d3322
-//.word 0x319dff9a
-//.word 0x79f89429
-//.word 0x1c5fac37
-//.word 0x319fb408
-//.word 0x402e1880
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000138
-//// expected output
-//.word 0x1870fe91
-//.word 0x3abb0a4b
-//.word 0x4f53b658
-//.word 0x1ae18322
-//.word 0xcd053285
-//.word 0x14556607
-//.word 0xf3f4d7b6
-//.word 0xa2ac8e91
-//.word 0x85d94d94
-//.word 0x7d8b9c88
-//.word 0xe0efa66d
-//.word 0x89b59f74
-//.word 0x39c75fda
-//.word 0xdd1816f7
-//.word 0x412306ab
-//.word 0x2b59d664
-//// SHA512ShortMsgvector_41
-//// vector length
-//.word 0x00000140
-//// input message
-//.word 0x7651ab49
-//.word 0x1b8fa86f
-//.word 0x969d4297
-//.word 0x7d09df5f
-//.word 0x8bee3e58
-//.word 0x99180b52
-//.word 0xc968b0db
-//.word 0x057a6f02
-//.word 0xa886ad61
-//.word 0x7a84915a
-//.word 0x80000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000140
-//// expected output
-//.word 0xf35e50e2
-//.word 0xe02b8781
-//.word 0x345f8ceb
-//.word 0x2198f068
-//.word 0xba103476
-//.word 0xf715cfb4
-//.word 0x87a45288
-//.word 0x2c9f0de0
-//.word 0xc720b2a0
-//.word 0x88a39d06
-//.word 0xa8a6b64c
-//.word 0xe4d6470d
-//.word 0xfeadc4f6
-//.word 0x5ae06672
-//.word 0xc057e29f
-//.word 0x14c4daf9
-//// SHA512ShortMsgvector_42
-//// vector length
-//.word 0x00000148
-//// input message
-//.word 0xdbe5db68
-//.word 0x5ed7cb84
-//.word 0x8c094524
-//.word 0xc1723519
-//.word 0xd49dc66e
-//.word 0xf9fe6d57
-//.word 0xe6862a64
-//.word 0x35750bfa
-//.word 0x0a70f104
-//.word 0xf5d396e6
-//.word 0x1a800000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000148
-//// expected output
-//.word 0x2fa6e5b2
-//.word 0xc443a680
-//.word 0x50f093e7
-//.word 0xfb713bd6
-//.word 0xb18f6274
-//.word 0xc061ed61
-//.word 0xd79bf068
-//.word 0x8a61dba1
-//.word 0x940bcc30
-//.word 0x99827686
-//.word 0x0943ab03
-//.word 0x8902896d
-//.word 0x0fbf59b8
-//.word 0x8b07c80d
-//.word 0xe9270370
-//.word 0x97150c40
-//// SHA512ShortMsgvector_43
-//// vector length
-//.word 0x00000150
-//// input message
-//.word 0x9fa83e96
-//.word 0xb2a6df23
-//.word 0xfb372895
-//.word 0x015678e0
-//.word 0xb2c9cd18
-//.word 0xa8542c3e
-//.word 0xaa2c435a
-//.word 0x76ae4dc9
-//.word 0xbd5136d9
-//.word 0x70daff93
-//.word 0x3acf8000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000150
-//// expected output
-//.word 0x3a2c0ec8
-//.word 0x8a3e5347
-//.word 0xcf0ea9c0
-//.word 0x78838300
-//.word 0xef7356f9
-//.word 0xa6c34206
-//.word 0x3277c106
-//.word 0xb880a00e
-//.word 0xd2be205c
-//.word 0x13064097
-//.word 0xbd372fde
-//.word 0x38007bc3
-//.word 0x06561eb4
-//.word 0xe74bba2b
-//.word 0xb20bd354
-//.word 0xaa690ca6
-//// SHA512ShortMsgvector_44
-//// vector length
-//.word 0x00000158
-//// input message
-//.word 0x8a5a45e3
-//.word 0x98bac1d9
-//.word 0xb896b5a2
-//.word 0xb4e3566b
-//.word 0x91d80ad2
-//.word 0x0c977ea7
-//.word 0x450ff2ef
-//.word 0xb521d82f
-//.word 0x65019ee7
-//.word 0x62e0c85c
-//.word 0x6cc84180
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000158
-//// expected output
-//.word 0x3c704620
-//.word 0xf4066d79
-//.word 0xc1ff6775
-//.word 0x2980f39e
-//.word 0xf3d9c102
-//.word 0x3fa5a213
-//.word 0xa5265376
-//.word 0xb14a1516
-//.word 0x6ffe069b
-//.word 0x51df7710
-//.word 0xd8907fef
-//.word 0x9406bf37
-//.word 0x5d502ce0
-//.word 0x86ac82af
-//.word 0xf17229aa
-//.word 0xa7a5a334
-//// SHA512ShortMsgvector_45
-//// vector length
-//.word 0x00000160
-//// input message
-//.word 0x49cfffda
-//.word 0xf4d031e3
-//.word 0x3b1d28a4
-//.word 0x47450545
-//.word 0xf6c4293b
-//.word 0x38d5afbc
-//.word 0xb9883976
-//.word 0xc014f080
-//.word 0x576ec691
-//.word 0xac1bff70
-//.word 0xb742efab
-//.word 0x80000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000160
-//// expected output
-//.word 0x8bcc4f1e
-//.word 0xa2b7862e
-//.word 0xf1591bfa
-//.word 0x73916665
-//.word 0xde8faf65
-//.word 0x439ddf5c
-//.word 0xc1be43ce
-//.word 0xbfd5f60f
-//.word 0x205e835a
-//.word 0x2b186b67
-//.word 0x5b041258
-//.word 0xc5cff426
-//.word 0x69316ce2
-//.word 0x5b46a2f4
-//.word 0xd4218e10
-//.word 0x2f0f5d6f
-//// SHA512ShortMsgvector_46
-//// vector length
-//.word 0x00000168
-//// input message
-//.word 0x2ff845d8
-//.word 0x5efbc4fa
-//.word 0x5637e944
-//.word 0x8d950496
-//.word 0xf19d8d57
-//.word 0xda99b7bd
-//.word 0x3df74748
-//.word 0x22f0a790
-//.word 0x58673641
-//.word 0x6714e364
-//.word 0xc6e1fae0
-//.word 0x4e800000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000168
-//// expected output
-//.word 0x236f6f4e
-//.word 0xd6e858c0
-//.word 0x2d51787e
-//.word 0x60c578f7
-//.word 0x31f694f8
-//.word 0xe52b5df4
-//.word 0xecd5b04d
-//.word 0xff14c78e
-//.word 0x56bad102
-//.word 0x8d6f626c
-//.word 0x29d85aee
-//.word 0xe151a2a2
-//.word 0x846d3eed
-//.word 0x5cfafa98
-//.word 0x54a69fea
-//.word 0x8af6d04a
-//// SHA512ShortMsgvector_47
-//// vector length
-//.word 0x00000170
-//// input message
-//.word 0xcfca05fd
-//.word 0x893c0f00
-//.word 0x5f5ff796
-//.word 0xf4da19ba
-//.word 0x27a1e729
-//.word 0x956b8b71
-//.word 0x5e67ce4b
-//.word 0x2d2a382a
-//.word 0x72ec7814
-//.word 0xf2f507b1
-//.word 0x825209a2
-//.word 0x0fcc8000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000170
-//// expected output
-//.word 0xd8096928
-//.word 0x4a4565ad
-//.word 0xd4dad6ab
-//.word 0x9b3bdf53
-//.word 0x446142f8
-//.word 0x4aaf92d4
-//.word 0xb23dd22e
-//.word 0xe7241e6c
-//.word 0x81489ac8
-//.word 0xb246edcb
-//.word 0x6df9bd7b
-//.word 0x23d91a0c
-//.word 0x517f546f
-//.word 0xeba4ed57
-//.word 0x90a2be6e
-//.word 0x165c1709
-//// SHA512ShortMsgvector_48
-//// vector length
-//.word 0x00000178
-//// input message
-//.word 0xcfc42575
-//.word 0x9a9c36bb
-//.word 0x9f4b32ee
-//.word 0xd7767af6
-//.word 0x566f68de
-//.word 0xd0adeae2
-//.word 0x5c7a70ca
-//.word 0x78ec0977
-//.word 0x4d16c8bc
-//.word 0x357f6d6f
-//.word 0x7bd441bf
-//.word 0x62d94280
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000178
-//// expected output
-//.word 0xb587a785
-//.word 0xcdf455cc
-//.word 0x9c544e75
-//.word 0x6c1e3063
-//.word 0x00aa3c59
-//.word 0xf8725012
-//.word 0xe68ab4d5
-//.word 0x4020b6d2
-//.word 0x27a164d9
-//.word 0xf83c905e
-//.word 0x86f8cebe
-//.word 0xef708a69
-//.word 0xf976d6e7
-//.word 0xb18b9bf7
-//.word 0x8e9b98cc
-//.word 0x4a5cd1b6
-//// SHA512ShortMsgvector_49
-//// vector length
-//.word 0x00000180
-//// input message
-//.word 0x097c9db9
-//.word 0x19515242
-//.word 0xc99d973a
-//.word 0xcb1dc4ed
-//.word 0x482768f9
-//.word 0x74eb83b4
-//.word 0x65f9f6c8
-//.word 0x25033720
-//.word 0x06e44908
-//.word 0x35e2ec8f
-//.word 0x92301130
-//.word 0xbfb790b2
-//.word 0x80000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000180
-//// expected output
-//.word 0xff5a376f
-//.word 0x938e7301
-//.word 0x4caef7fe
-//.word 0x3962944a
-//.word 0x7230d020
-//.word 0xb7087869
-//.word 0xebe7ec70
-//.word 0x302721cd
-//.word 0x06fcdc98
-//.word 0x1c893a42
-//.word 0x5d05e2f9
-//.word 0x9fe198e4
-//.word 0xdb50a088
-//.word 0xaee2bf12
-//.word 0x63212110
-//.word 0xefed422c
-//// SHA512ShortMsgvector_50
-//// vector length
-//.word 0x00000188
-//// input message
-//.word 0x77e73d38
-//.word 0x7e7bc804
-//.word 0x19ebf548
-//.word 0x2b61d525
-//.word 0x5caf819f
-//.word 0xb59251ff
-//.word 0x6a384e75
-//.word 0xf601ea02
-//.word 0x6d83ef95
-//.word 0x0ed0b675
-//.word 0x18fb99de
-//.word 0xe0d8aaef
-//.word 0x1f800000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000188
-//// expected output
-//.word 0xc4c89cd8
-//.word 0x82ec945c
-//.word 0xc888fb9a
-//.word 0x0127d35e
-//.word 0x585ecc14
-//.word 0xa75e4b5b
-//.word 0x3d833053
-//.word 0x8d22da28
-//.word 0xcf6af1eb
-//.word 0xec96dc24
-//.word 0x7f109cd2
-//.word 0xaaab9756
-//.word 0xe6946a3d
-//.word 0x80db8363
-//.word 0xa4da3e6d
-//.word 0xdbb510a1
-//// SHA512ShortMsgvector_51
-//// vector length
-//.word 0x00000190
-//// input message
-//.word 0x317e5d9a
-//.word 0xc73ed063
-//.word 0x3fa18ebe
-//.word 0xbbca7909
-//.word 0xec3a5ef7
-//.word 0x90478f9c
-//.word 0x38cacec4
-//.word 0x4f196d89
-//.word 0x5835b425
-//.word 0x77448304
-//.word 0x3341381e
-//.word 0x7af2d383
-//.word 0xe51a8000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000190
-//// expected output
-//.word 0xb10bb044
-//.word 0x91b9c0c3
-//.word 0x34709b40
-//.word 0x7cda1d50
-//.word 0x3efb6b63
-//.word 0xee944f2d
-//.word 0x366b6855
-//.word 0xe6e63e5b
-//.word 0x80115be4
-//.word 0xbe7ff63e
-//.word 0xdecdfb59
-//.word 0x23792e68
-//.word 0x123976d7
-//.word 0x9212b388
-//.word 0x4dec2179
-//.word 0xd1fcf382
-//// SHA512ShortMsgvector_52
-//// vector length
-//.word 0x00000198
-//// input message
-//.word 0x209461f2
-//.word 0x0666a346
-//.word 0xfedf4a53
-//.word 0x0f41a6fa
-//.word 0x280c4366
-//.word 0x5767be92
-//.word 0x3bc1d80b
-//.word 0xbcb8c9f8
-//.word 0xf93ad757
-//.word 0x82ea2689
-//.word 0xc8c5d211
-//.word 0xd2053b99
-//.word 0x3145a080
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000198
-//// expected output
-//.word 0x67b7a328
-//.word 0xd9444056
-//.word 0xa52ca2f6
-//.word 0x95c5d3f3
-//.word 0xbaafb625
-//.word 0xa14fb32e
-//.word 0xee8ff26a
-//.word 0x40ccb296
-//.word 0xbec1771a
-//.word 0x826b55f7
-//.word 0xddb6170d
-//.word 0x4caf7795
-//.word 0xb612448e
-//.word 0x66a0f193
-//.word 0x56fe5059
-//.word 0x27149b47
-//// SHA512ShortMsgvector_53
-//// vector length
-//.word 0x000001A0
-//// input message
-//.word 0x5d61aa45
-//.word 0xc446f3bf
-//.word 0x93604b05
-//.word 0x11313b4e
-//.word 0x2f306d6b
-//.word 0x046fbd94
-//.word 0x797b9267
-//.word 0x46836f2e
-//.word 0x1dbdc561
-//.word 0x24060c6c
-//.word 0xa9c911b1
-//.word 0x122192d1
-//.word 0x12420827
-//.word 0x80000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000001A0
-//// expected output
-//.word 0xd3931bde
-//.word 0x2bde8271
-//.word 0xed18ca0b
-//.word 0x9148b12f
-//.word 0x6f16161e
-//.word 0x637e376f
-//.word 0xc961f65b
-//.word 0xc33bcacf
-//.word 0x2f6addf2
-//.word 0x6a3eaa81
-//.word 0xb196653c
-//.word 0xc37e8a73
-//.word 0x9ec5b3df
-//.word 0x870d8c38
-//.word 0xc8f28691
-//.word 0xc22a39bb
-//// SHA512ShortMsgvector_54
-//// vector length
-//.word 0x000001A8
-//// input message
-//.word 0x9288c795
-//.word 0xbb0b86c0
-//.word 0x419d9c56
-//.word 0x37dcc37b
-//.word 0x39bfa18d
-//.word 0x441e3fbf
-//.word 0xca75bc03
-//.word 0x06e5432e
-//.word 0x8e7b3a56
-//.word 0x27b5bc7f
-//.word 0xdc424a77
-//.word 0x520abdff
-//.word 0x566e7f2b
-//.word 0xb8800000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000001A8
-//// expected output
-//.word 0xe363d0e9
-//.word 0x5d8cd18c
-//.word 0x384016eb
-//.word 0xeed6d99c
-//.word 0x4fa2768e
-//.word 0x2bd58fca
-//.word 0x019c5108
-//.word 0xb9cde1cb
-//.word 0x46f3f884
-//.word 0x028a55ce
-//.word 0x282ec310
-//.word 0xa10037fa
-//.word 0xa1b16b4a
-//.word 0x6a669957
-//.word 0xf0b00f35
-//.word 0x0bbd63d0
-//// SHA512ShortMsgvector_55
-//// vector length
-//.word 0x000001B0
-//// input message
-//.word 0x780427dc
-//.word 0x164b2f69
-//.word 0xb8c7d569
-//.word 0x266f461e
-//.word 0x2d30c88c
-//.word 0x4cd6057f
-//.word 0xb030a6cf
-//.word 0x636f24e3
-//.word 0xc0d0db74
-//.word 0x2a7b6193
-//.word 0xfdaa15ee
-//.word 0xc50dfb4f
-//.word 0xae6ec765
-//.word 0x3c918000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000001B0
-//// expected output
-//.word 0x2964b009
-//.word 0xfb1bf996
-//.word 0xde12e030
-//.word 0xb9d6e060
-//.word 0x8ae8b9db
-//.word 0xf2acfb9b
-//.word 0xeb76fc53
-//.word 0x61cc104e
-//.word 0xe85c2a46
-//.word 0xfb7b4cee
-//.word 0x90848312
-//.word 0xda302de4
-//.word 0x9afe61c5
-//.word 0x46477e2b
-//.word 0x25d223d5
-//.word 0xe3d33560
-//// SHA512ShortMsgvector_56
-//// vector length
-//.word 0x000001B8
-//// input message
-//.word 0xec2a92e4
-//.word 0x7f692b53
-//.word 0xc1355475
-//.word 0xc71ceff0
-//.word 0xb0952a8b
-//.word 0x3541b293
-//.word 0x8270247d
-//.word 0x44e7c5cc
-//.word 0x04e17236
-//.word 0xb353da02
-//.word 0x8674eab4
-//.word 0x047d89ec
-//.word 0x5dad868c
-//.word 0xfd91ce80
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000001B8
-//// expected output
-//.word 0xc83aca61
-//.word 0x47bfcbbc
-//.word 0x72c377ef
-//.word 0xa8d53654
-//.word 0xba0830c5
-//.word 0xa6a89e1d
-//.word 0x2a19b713
-//.word 0xe68fb534
-//.word 0x640deb83
-//.word 0x3ca51224
-//.word 0x7166dd27
-//.word 0x3b5897e5
-//.word 0x7d526f88
-//.word 0xeef58f6f
-//.word 0xf97baee0
-//.word 0xb4ee5644
-//// SHA512ShortMsgvector_57
-//// vector length
-//.word 0x000001C0
-//// input message
-//.word 0xc99e31ad
-//.word 0x4e23ac68
-//.word 0xe15e605d
-//.word 0x0b02437f
-//.word 0x8147c44f
-//.word 0x5445a55b
-//.word 0x68a10905
-//.word 0x276cce86
-//.word 0x76481c33
-//.word 0xe8cd3efe
-//.word 0x322bb13f
-//.word 0xe0107bb5
-//.word 0x46ccbec7
-//.word 0xb8b38d10
-//.word 0x80000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000001C0
-//// expected output
-//.word 0x52992d45
-//.word 0xa88221d9
-//.word 0x72958e9f
-//.word 0x2854adaa
-//.word 0x9a21d2bf
-//.word 0x7051e1f1
-//.word 0x019ae780
-//.word 0x04da50c5
-//.word 0xb55c144a
-//.word 0x02afffe5
-//.word 0x39d75394
-//.word 0x9a2b0565
-//.word 0x34f5b4c2
-//.word 0x1f248a05
-//.word 0xbaa52a6c
-//.word 0x38c7f5dd
-//// SHA512ShortMsgvector_58
-//// vector length
-//.word 0x000001C8
-//// input message
-//.word 0x9aa3e8ad
-//.word 0x92777dfe
-//.word 0xb121a646
-//.word 0xce2e918d
-//.word 0x1e12b307
-//.word 0x54bc0947
-//.word 0x0d6da4af
-//.word 0x6cc9642b
-//.word 0x012f041f
-//.word 0xf046569d
-//.word 0x4fd8d0dc
-//.word 0xcfe448e5
-//.word 0x9feefc90
-//.word 0x8d9ad5af
-//.word 0x6f800000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000001C8
-//// expected output
-//.word 0x994d1cda
-//.word 0x4de40aff
-//.word 0x4713237c
-//.word 0xf9f78f70
-//.word 0x33af8336
-//.word 0x9ac9c64e
-//.word 0x504091ea
-//.word 0x2f1caff6
-//.word 0xc5152d6a
-//.word 0x0c5608f8
-//.word 0x2886c009
-//.word 0x3b3d7fba
-//.word 0xdd49dfd1
-//.word 0xf9e0f85a
-//.word 0xccf23bc7
-//.word 0xdad48904
-//// SHA512ShortMsgvector_59
-//// vector length
-//.word 0x000001D0
-//// input message
-//.word 0x5842512c
-//.word 0x37312511
-//.word 0xa3d8ae41
-//.word 0xf5801df6
-//.word 0x0cd682d5
-//.word 0x8b4a9973
-//.word 0x42b6e717
-//.word 0xe94006c2
-//.word 0x14813e6c
-//.word 0x63e75591
-//.word 0xf957a7ec
-//.word 0x30177983
-//.word 0x8bec8ae3
-//.word 0xed7febad
-//.word 0x08058000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000001D0
-//// expected output
-//.word 0x9763c433
-//.word 0x31ad0eb2
-//.word 0x79d704c5
-//.word 0xf6e97e02
-//.word 0xda872411
-//.word 0x5026827f
-//.word 0x889e9fcd
-//.word 0xa21f60fd
-//.word 0x230894ab
-//.word 0x35abb719
-//.word 0x890f3afa
-//.word 0x51afd31b
-//.word 0xc6852183
-//.word 0xb9c51059
-//.word 0x910af460
-//.word 0xabd2474d
-//// SHA512ShortMsgvector_60
-//// vector length
-//.word 0x000001D8
-//// input message
-//.word 0xca14e2ea
-//.word 0x2f37c78f
-//.word 0x78ef280f
-//.word 0x58707ec5
-//.word 0x49a31a94
-//.word 0x361073e3
-//.word 0x7701bfe5
-//.word 0x03e4c01e
-//.word 0xe1f2e123
-//.word 0xe00e81a1
-//.word 0x88f08fa0
-//.word 0x50825709
-//.word 0x128a9b66
-//.word 0xbb8ae6ea
-//.word 0x47e41d80
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000001D8
-//// expected output
-//.word 0x4600e022
-//.word 0xa0225873
-//.word 0x9f67fdd3
-//.word 0x67cc1e66
-//.word 0x2631fb08
-//.word 0x79187683
-//.word 0x52062b9b
-//.word 0x3c8de8db
-//.word 0xca0e9ec7
-//.word 0x51b91f28
-//.word 0x4694fbdd
-//.word 0xb8d325c0
-//.word 0x637bccb2
-//.word 0x1dd2efa9
-//.word 0x2e48dbab
-//.word 0x2e5e9c26
-//// SHA512ShortMsgvector_61
-//// vector length
-//.word 0x000001E0
-//// input message
-//.word 0x647629c7
-//.word 0x79b24c1e
-//.word 0x76f41744
-//.word 0xaba17159
-//.word 0x487532a0
-//.word 0x156a7d82
-//.word 0x64db50d6
-//.word 0x45e9595f
-//.word 0xf81e0c96
-//.word 0xa850f2aa
-//.word 0x56c844c6
-//.word 0x13a4b892
-//.word 0x727a9bfc
-//.word 0x3d3e2038
-//.word 0x6766f805
-//.word 0x80000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000001E0
-//// expected output
-//.word 0x5bc842fc
-//.word 0x2d3b7eb3
-//.word 0x1d2d3044
-//.word 0xdf3ec32a
-//.word 0xf114feaa
-//.word 0x7cfc27eb
-//.word 0xc8630f46
-//.word 0xab6f0c54
-//.word 0x3f59b812
-//.word 0xe776e530
-//.word 0x3861d17d
-//.word 0xa3f1f160
-//.word 0x97641f3b
-//.word 0x808d4d5c
-//.word 0xb3e48394
-//.word 0x6409746c
-//// SHA512ShortMsgvector_62
-//// vector length
-//.word 0x000001E8
-//// input message
-//.word 0x1c5dc0d1
-//.word 0xdd2e4c71
-//.word 0x7635ff3e
-//.word 0x9b67caf9
-//.word 0x57aec0f8
-//.word 0xf63c1b1e
-//.word 0x221e800a
-//.word 0x4c14848f
-//.word 0x4ea06e64
-//.word 0x4e5d3e1d
-//.word 0xe592ef5a
-//.word 0x8007fa3f
-//.word 0x07171b24
-//.word 0xbd07578d
-//.word 0x68963e5c
-//.word 0xb1800000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000001E8
-//// expected output
-//.word 0xcbf1ea86
-//.word 0xfa5b3dbf
-//.word 0x67be82fa
-//.word 0xc41e84cc
-//.word 0xcd0d296c
-//.word 0x757169b3
-//.word 0x7837d273
-//.word 0xccc015ee
-//.word 0xcd102b9c
-//.word 0xe1cff68f
-//.word 0xdc7f05d2
-//.word 0x2f2b7747
-//.word 0x34f62ded
-//.word 0x54c8ee0b
-//.word 0xf57a5a82
-//.word 0x010d74f5
-//// SHA512ShortMsgvector_63
-//// vector length
-//.word 0x000001F0
-//// input message
-//.word 0x8a555e75
-//.word 0x477d065b
-//.word 0x3af7e615
-//.word 0x475f37c0
-//.word 0xa667f73a
-//.word 0x4c7af5e4
-//.word 0xa69f28a6
-//.word 0x8d9f4434
-//.word 0x776a8f90
-//.word 0xeab7f1d1
-//.word 0x37eb4b22
-//.word 0x643c0a0d
-//.word 0x6a16fcfa
-//.word 0xa1bd62f2
-//.word 0x783546a9
-//.word 0x695f8000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000001F0
-//// expected output
-//.word 0xc088e4a3
-//.word 0xd7da2f6f
-//.word 0x99a8f3f7
-//.word 0x17361108
-//.word 0x872b8ffe
-//.word 0xf921b383
-//.word 0xc24b8061
-//.word 0xd4e7c27f
-//.word 0xc56f4f20
-//.word 0xdc8f952a
-//.word 0x14043c56
-//.word 0x50b5a9e7
-//.word 0x77c49c41
-//.word 0xcfeb3f2d
-//.word 0xe97ee2e1
-//.word 0x6b2c3924
-//// SHA512ShortMsgvector_64
-//// vector length
-//.word 0x000001F8
-//// input message
-//.word 0xebb3e2ad
-//.word 0x7803508b
-//.word 0xa46e81e2
-//.word 0x20b1cff3
-//.word 0x3ea83815
-//.word 0x04110e9f
-//.word 0x8092ef08
-//.word 0x5afef84d
-//.word 0xb0d43693
-//.word 0x1d085d0e
-//.word 0x1b06bd21
-//.word 0x8cf571c7
-//.word 0x9338da31
-//.word 0xa83b4cb1
-//.word 0xec6c06d6
-//.word 0xb9876880
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000001F8
-//// expected output
-//.word 0xf33428d8
-//.word 0xfc67aa2c
-//.word 0xc1adcb28
-//.word 0x22f37f29
-//.word 0xcbd72abf
-//.word 0xf6819048
-//.word 0x3e415824
-//.word 0xf0bcecd4
-//.word 0x47cb4f05
-//.word 0xa9c47031
-//.word 0xb9c50e04
-//.word 0x11c552f3
-//.word 0x1cd04c30
-//.word 0xcea2bc64
-//.word 0xbcf825a5
-//.word 0xf8a66028
-//// SHA512ShortMsgvector_65
-//// vector length
-//.word 0x00000200
-//// input message
-//.word 0xc1ca70ae
-//.word 0x1279ba0b
-//.word 0x91815755
-//.word 0x8b4920d6
-//.word 0xb7fba8a0
-//.word 0x6be51517
-//.word 0x0f202faf
-//.word 0xd36fb7f7
-//.word 0x9d69fad7
-//.word 0x45dba615
-//.word 0x0568db1e
-//.word 0x2b728504
-//.word 0x113eeac3
-//.word 0x4f527fc8
-//.word 0x2f2200b4
-//.word 0x62ecbf5d
-//.word 0x80000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000200
-//// expected output
-//.word 0x046e4662
-//.word 0x3912b393
-//.word 0x2b8d662a
-//.word 0xb4258342
-//.word 0x38432063
-//.word 0x01b58bf2
-//.word 0x0ab6d76f
-//.word 0xd47f1cbb
-//.word 0xcf421df5
-//.word 0x36ecd7e5
-//.word 0x6db5354e
-//.word 0x7e0f9882
-//.word 0x2d2129c1
-//.word 0x97f6f0f2
-//.word 0x22b8ec52
-//.word 0x31f3967d
-//// SHA512ShortMsgvector_66
-//// vector length
-//.word 0x00000208
-//// input message
-//.word 0xd3ddddf8
-//.word 0x05b1678a
-//.word 0x02e39200
-//.word 0xf6440047
-//.word 0xacbb062e
-//.word 0x4a2f046a
-//.word 0x3ca7f1dd
-//.word 0x6eb03a18
-//.word 0xbe00cd1e
-//.word 0xb158706a
-//.word 0x64af5834
-//.word 0xc68cf7f1
-//.word 0x05b41519
-//.word 0x4605222c
-//.word 0x99a2cbf7
-//.word 0x2c50cb14
-//.word 0xbf800000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000208
-//// expected output
-//.word 0xbae7c5d5
-//.word 0x90bf25a4
-//.word 0x93d8f48b
-//.word 0x8b4638cc
-//.word 0xb10541c6
-//.word 0x7996e472
-//.word 0x87b98432
-//.word 0x2009d27d
-//.word 0x1348f3ef
-//.word 0x2999f5ee
-//.word 0x0d38e112
-//.word 0xcd5a807a
-//.word 0x57830cdc
-//.word 0x318a1181
-//.word 0xe6c4653c
-//.word 0xdb8cf122
-//// SHA512ShortMsgvector_67
-//// vector length
-//.word 0x00000210
-//// input message
-//.word 0x8e8ef8aa
-//.word 0x336b3b98
-//.word 0x894c3126
-//.word 0xc7187891
-//.word 0x0618838c
-//.word 0x00ac8590
-//.word 0x173c9174
-//.word 0x9972ff3d
-//.word 0x42a61137
-//.word 0x029ad745
-//.word 0x01684f75
-//.word 0xe1b8d1d7
-//.word 0x4336aa90
-//.word 0x8c44082a
-//.word 0xe9eb162e
-//.word 0x901867f5
-//.word 0x49058000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000210
-//// expected output
-//.word 0x41672931
-//.word 0x558a9376
-//.word 0x2522b1d5
-//.word 0x5389ecf1
-//.word 0xb8c0feb8
-//.word 0xb88f4587
-//.word 0xfbd417ca
-//.word 0x809055b0
-//.word 0xcb630d8b
-//.word 0xea133ab7
-//.word 0xf6cf1f21
-//.word 0xc6b35e2e
-//.word 0x25c0d195
-//.word 0x83258808
-//.word 0xe6c23e1a
-//.word 0x75336103
-//// SHA512ShortMsgvector_68
-//// vector length
-//.word 0x00000218
-//// input message
-//.word 0x52761e1d
-//.word 0xac0eaea8
-//.word 0x98e0b07c
-//.word 0xd24f4b2e
-//.word 0x6bb7bc20
-//.word 0x0ea4b052
-//.word 0x8842f17b
-//.word 0x87154559
-//.word 0xa2ea9445
-//.word 0x9a0e480a
-//.word 0xe0bdf9f7
-//.word 0x57dd4a33
-//.word 0x5aed0e51
-//.word 0x0138b024
-//.word 0xa04ed1d5
-//.word 0x91b43232
-//.word 0x34dbd580
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000218
-//// expected output
-//.word 0xb826fe80
-//.word 0x494e19c5
-//.word 0x1b42f258
-//.word 0x2b2d080b
-//.word 0xa6b90512
-//.word 0xf35f2db6
-//.word 0x7dd7fd5e
-//.word 0xe532eaa1
-//.word 0x6498afba
-//.word 0x08b4996c
-//.word 0xbcfdf8d1
-//.word 0xa2df6b1d
-//.word 0xa939e826
-//.word 0x5115a48a
-//.word 0xefa42f38
-//.word 0x205db436
-//// SHA512ShortMsgvector_69
-//// vector length
-//.word 0x00000220
-//// input message
-//.word 0x3804ebc4
-//.word 0x3cbea80c
-//.word 0x2bd7e4fd
-//.word 0xa5c55155
-//.word 0x00cd2d2b
-//.word 0x846a1378
-//.word 0xdbf218d5
-//.word 0xc3771386
-//.word 0x06eb3cb8
-//.word 0xac88f907
-//.word 0x6f6ff443
-//.word 0x6f907174
-//.word 0x27c9df1b
-//.word 0xa052acbb
-//.word 0xe4585e98
-//.word 0xb6e8e0bf
-//.word 0x800f1946
-//.word 0x80000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000220
-//// expected output
-//.word 0x17dd6d87
-//.word 0xbc677305
-//.word 0x1e52047f
-//.word 0xd444996a
-//.word 0xfa8124b0
-//.word 0x483fe121
-//.word 0x877f9855
-//.word 0x3448772b
-//.word 0xd0e7751f
-//.word 0xc655e9cc
-//.word 0x2d298302
-//.word 0x11015d31
-//.word 0x0f191474
-//.word 0xca6adc04
-//.word 0x77a187c0
-//.word 0x3b8fe252
-//// SHA512ShortMsgvector_70
-//// vector length
-//.word 0x00000228
-//// input message
-//.word 0x2249d698
-//.word 0xc4d807a8
-//.word 0xe7b4de21
-//.word 0xc4857389
-//.word 0x59a0d67e
-//.word 0x5d2ca6f7
-//.word 0x7983dfcc
-//.word 0xb5dbf479
-//.word 0x31261e1f
-//.word 0x1537f3cb
-//.word 0xca253afb
-//.word 0x6bf4fe5e
-//.word 0x7672e1dc
-//.word 0xc860b3d6
-//.word 0xc8d243af
-//.word 0xe2d9758b
-//.word 0x375e9556
-//.word 0x92800000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000228
-//// expected output
-//.word 0x6af44563
-//.word 0xfc468d51
-//.word 0x182f6c3b
-//.word 0xe58d4593
-//.word 0x2af1d985
-//.word 0xc6f28397
-//.word 0x6c91a9ff
-//.word 0x421f383f
-//.word 0xe21dc732
-//.word 0x2f397cce
-//.word 0xad583e26
-//.word 0xb3e3fda0
-//.word 0x67976a7f
-//.word 0x34665df2
-//.word 0x5a2ced7b
-//.word 0x4b09cdec
-//// SHA512ShortMsgvector_71
-//// vector length
-//.word 0x00000230
-//// input message
-//.word 0x32a9c170
-//.word 0x33658c54
-//.word 0xf22c7135
-//.word 0xddfc879d
-//.word 0xe94d7959
-//.word 0x3ef2dc7d
-//.word 0x3041bfa8
-//.word 0x72738389
-//.word 0x864eeda2
-//.word 0x7801794c
-//.word 0xcc4ff1fc
-//.word 0xb5ef3fc4
-//.word 0x8833801d
-//.word 0x6fe959e3
-//.word 0x627f8ea1
-//.word 0x536ad00f
-//.word 0xa9c7d7d9
-//.word 0xf0438000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000230
-//// expected output
-//.word 0x6a47699d
-//.word 0xd3ada2f1
-//.word 0x1bc4ea42
-//.word 0x072b06cc
-//.word 0x20857bf1
-//.word 0x64497df1
-//.word 0x285400c2
-//.word 0x50f5848b
-//.word 0x6f71957d
-//.word 0xbdc845f5
-//.word 0xdaeab913
-//.word 0x036661f6
-//.word 0x9387893f
-//.word 0xc2d61c25
-//.word 0xfa59b9d8
-//.word 0x5b19f401
-//// SHA512ShortMsgvector_72
-//// vector length
-//.word 0x00000238
-//// input message
-//.word 0x3d65f69a
-//.word 0x590a5baa
-//.word 0xabcd274f
-//.word 0xe3ef9e88
-//.word 0x920ffc7a
-//.word 0xdf05c16d
-//.word 0x7b0f4d18
-//.word 0xd72bac1e
-//.word 0x94c3b3d8
-//.word 0x3b8f4c55
-//.word 0x2eb80e9f
-//.word 0xde391140
-//.word 0x3f8b0005
-//.word 0x79816f02
-//.word 0xe1716fd6
-//.word 0x27946031
-//.word 0xd0af0793
-//.word 0xe7f3e180
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000238
-//// expected output
-//.word 0xffb2d945
-//.word 0x0943c24b
-//.word 0x5933c248
-//.word 0x12459b75
-//.word 0xd3d9f380
-//.word 0x344c9bc0
-//.word 0x6fa3e17e
-//.word 0xe448eca2
-//.word 0xf98ff79f
-//.word 0x7e2235cc
-//.word 0xd9f9a817
-//.word 0x6f68a225
-//.word 0x4bbc9b83
-//.word 0x4d6ac8d2
-//.word 0xbfdbc159
-//.word 0x7c432c9f
-//// SHA512ShortMsgvector_73
-//// vector length
-//.word 0x00000240
-//// input message
-//.word 0x76ff8b20
-//.word 0xa18cf104
-//.word 0xf6cdb65e
-//.word 0x2ba8f66e
-//.word 0xcf844af7
-//.word 0xe85e8ef2
-//.word 0xda19e884
-//.word 0x8a16052e
-//.word 0xc405a644
-//.word 0xdafb5ca0
-//.word 0x8ec48f97
-//.word 0x327ac52c
-//.word 0x0e562184
-//.word 0x02c72a9a
-//.word 0x6dc1cf34
-//.word 0x4d58a716
-//.word 0xa78d7d75
-//.word 0x29680bae
-//.word 0x80000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000240
-//// expected output
-//.word 0xf8858144
-//.word 0xc6d709dd
-//.word 0x0689a526
-//.word 0xa548a43f
-//.word 0x17494950
-//.word 0xba2ac205
-//.word 0x44799e8e
-//.word 0xa27201d7
-//.word 0x8bce5b92
-//.word 0x1e29a7b4
-//.word 0x029278e6
-//.word 0x8341ef2a
-//.word 0x0ca4ba38
-//.word 0x94566b3c
-//.word 0x8f8950e3
-//.word 0xe545a689
-//// SHA512ShortMsgvector_74
-//// vector length
-//.word 0x00000248
-//// input message
-//.word 0xca88dddf
-//.word 0xc876a12f
-//.word 0x45f19562
-//.word 0xbc9ca250
-//.word 0xf43267ab
-//.word 0x251a7f34
-//.word 0x5c3c022e
-//.word 0x20144e13
-//.word 0x56040787
-//.word 0x62ef5c8a
-//.word 0x8f038cf1
-//.word 0xb1d6a917
-//.word 0x09b59dd0
-//.word 0x68396a9e
-//.word 0x971ab628
-//.word 0xf74886e7
-//.word 0x65384a23
-//.word 0x607c1a1e
-//.word 0x6e800000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000248
-//// expected output
-//.word 0x4f3d9eee
-//.word 0xf349ca51
-//.word 0xa7e419af
-//.word 0x1686f427
-//.word 0x95abde58
-//.word 0xa85335ce
-//.word 0x68d496e8
-//.word 0x1e4436a8
-//.word 0x0a61dc14
-//.word 0x3a430000
-//.word 0x8c23a3e7
-//.word 0x1f4ba987
-//.word 0x43195a36
-//.word 0x94a8d02f
-//.word 0xee11bd31
-//.word 0x4569abc0
-//// SHA512ShortMsgvector_75
-//// vector length
-//.word 0x00000250
-//// input message
-//.word 0x0a78b16b
-//.word 0x4026f7ec
-//.word 0x063db4e7
-//.word 0xb77c42a2
-//.word 0x98e524e2
-//.word 0x68093c50
-//.word 0x38853e21
-//.word 0x7dcd65f6
-//.word 0x64286501
-//.word 0x65fca06a
-//.word 0x1b4c9cf1
-//.word 0x537fb5d4
-//.word 0x63630ff3
-//.word 0xbd71cf32
-//.word 0xc3538b1f
-//.word 0xdda3fed5
-//.word 0xc9f60120
-//.word 0x3319b7e1
-//.word 0x869a8000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000250
-//// expected output
-//.word 0x6095c3df
-//.word 0x5b9db7ce
-//.word 0x524d7612
-//.word 0x3f77421c
-//.word 0xe888b86a
-//.word 0x477ae8c6
-//.word 0xdb1d0be8
-//.word 0xd326d22c
-//.word 0x852915ab
-//.word 0x03c0c81a
-//.word 0x5b7ac71e
-//.word 0x2c14e74b
-//.word 0xda17a78d
-//.word 0x2b10585f
-//.word 0xa214f654
-//.word 0x6eb710a0
-//// SHA512ShortMsgvector_76
-//// vector length
-//.word 0x00000258
-//// input message
-//.word 0x20f10ef9
-//.word 0xa0e61286
-//.word 0x75340171
-//.word 0xcd248df3
-//.word 0x0b586557
-//.word 0x620b615c
-//.word 0xa39a00db
-//.word 0x534315a9
-//.word 0x012dbdbf
-//.word 0xd6a99498
-//.word 0x6eb829db
-//.word 0xe6cdaf3a
-//.word 0x37d4f59a
-//.word 0xc2729874
-//.word 0x2c8f777b
-//.word 0x6b12677f
-//.word 0x21eb2891
-//.word 0x29579868
-//.word 0x705f2780
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000258
-//// expected output
-//.word 0xb4ead3f8
-//.word 0x60eabbd3
-//.word 0x6c770d66
-//.word 0xc7356f81
-//.word 0x07acd148
-//.word 0x5c7c9417
-//.word 0x8c2eaabd
-//.word 0x50266d76
-//.word 0x45d00997
-//.word 0x2586ef83
-//.word 0xed43ed92
-//.word 0x882137df
-//.word 0x5117b88f
-//.word 0x35231b89
-//.word 0x4ec1741a
-//.word 0xe7501145
-//// SHA512ShortMsgvector_77
-//// vector length
-//.word 0x00000260
-//// input message
-//.word 0x995c8f74
-//.word 0x7ea418f7
-//.word 0xd63aba22
-//.word 0x60b34ac3
-//.word 0xc7dceebb
-//.word 0x78438ca4
-//.word 0xb1f982b7
-//.word 0xdb9798ec
-//.word 0x1a7f3262
-//.word 0x2264cb02
-//.word 0x4c0d9e60
-//.word 0xe955a6e1
-//.word 0xd677c923
-//.word 0x51885199
-//.word 0x0a459b76
-//.word 0x7d0f13cd
-//.word 0x803460f6
-//.word 0x1870db33
-//.word 0x91b44693
-//.word 0x80000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000260
-//// expected output
-//.word 0xa00a601e
-//.word 0xdeaca830
-//.word 0x41dc452d
-//.word 0x438a8de5
-//.word 0x49594e25
-//.word 0xd843c2cf
-//.word 0x60a0e009
-//.word 0xfb92d87a
-//.word 0xbe28a726
-//.word 0x90ab657c
-//.word 0x8d35b43c
-//.word 0xd02d22ec
-//.word 0x0755de22
-//.word 0x9d1f922f
-//.word 0xa6ca18a6
-//.word 0xd6c2aaae
-//// SHA512ShortMsgvector_78
-//// vector length
-//.word 0x00000268
-//// input message
-//.word 0x0feb23c7
-//.word 0xe4a19bcb
-//.word 0xd70bd300
-//.word 0xd76ec904
-//.word 0x5d696f8c
-//.word 0x9687f49e
-//.word 0xc4154400
-//.word 0xe231d2f0
-//.word 0x86249515
-//.word 0x0cf250b6
-//.word 0xf12f172a
-//.word 0x7d130f8f
-//.word 0xa5d175bf
-//.word 0x2f25e280
-//.word 0x172ccdfb
-//.word 0x32795170
-//.word 0x11653027
-//.word 0x28a619aa
-//.word 0x2f242631
-//.word 0xc9800000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000268
-//// expected output
-//.word 0xeeb6dee3
-//.word 0x0c119fb1
-//.word 0xe1eb5c15
-//.word 0xff2b32d8
-//.word 0xb9c7464a
-//.word 0x4e4cc681
-//.word 0x5cd251a6
-//.word 0xbae29b49
-//.word 0x961dd5c2
-//.word 0xfa9c44a9
-//.word 0xb142ca06
-//.word 0x2c7072cb
-//.word 0xf3db0429
-//.word 0x9b767789
-//.word 0x040196bf
-//.word 0x0c06aa76
-//// SHA512ShortMsgvector_79
-//// vector length
-//.word 0x00000270
-//// input message
-//.word 0xac59a110
-//.word 0x623f1a64
-//.word 0x666f160e
-//.word 0xd3292667
-//.word 0x6cb5be25
-//.word 0xdd9d962f
-//.word 0x441951b0
-//.word 0xefcb5d6a
-//.word 0x67ac1a4e
-//.word 0xae473e49
-//.word 0xc6257860
-//.word 0x728853ff
-//.word 0x415c5e8e
-//.word 0xc76a8a46
-//.word 0x2ecfd343
-//.word 0xeeac22da
-//.word 0xd820722c
-//.word 0x597332fb
-//.word 0xfd94ebbd
-//.word 0x32c68000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000270
-//// expected output
-//.word 0xf65ea942
-//.word 0xae0a47e7
-//.word 0x3b02b144
-//.word 0x2e5b2608
-//.word 0x3db79307
-//.word 0xf64dd34a
-//.word 0x039c476f
-//.word 0xaf18d5c5
-//.word 0x14bb77a2
-//.word 0xc412a607
-//.word 0x4a7afc32
-//.word 0x6ea66c74
-//.word 0xe5705fe2
-//.word 0xabbabf27
-//.word 0x4333325a
-//.word 0x15b61fd9
-//// SHA512ShortMsgvector_80
-//// vector length
-//.word 0x00000278
-//// input message
-//.word 0x9e3e1077
-//.word 0xe1333a1f
-//.word 0xb1aa633c
-//.word 0xcf2f7465
-//.word 0x88ad4264
-//.word 0x89ea08df
-//.word 0xf5511438
-//.word 0xb5f4c0b1
-//.word 0x10d1a4d4
-//.word 0x7b540a12
-//.word 0xb21ea2aa
-//.word 0x070578cc
-//.word 0xfa5c22fe
-//.word 0x0b743ec0
-//.word 0xcc621c6b
-//.word 0x3a03b75f
-//.word 0x4d3eea5d
-//.word 0xce89e032
-//.word 0x69afcd96
-//.word 0x03d0db80
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000278
-//// expected output
-//.word 0x4b5c5df8
-//.word 0x0c344c12
-//.word 0x388c7238
-//.word 0x56cd0696
-//.word 0x5b2190af
-//.word 0x65248047
-//.word 0x6747dc21
-//.word 0x95ea3716
-//.word 0xf87c1762
-//.word 0x359583a5
-//.word 0xf31522f8
-//.word 0x3f7833be
-//.word 0xc30f1f47
-//.word 0xd1454041
-//.word 0x7dd463f5
-//.word 0xd258cd4a
-//// SHA512ShortMsgvector_81
-//// vector length
-//.word 0x00000280
-//// input message
-//.word 0xe881e328
-//.word 0x4c79d8f5
-//.word 0x237e699e
-//.word 0x4fbca840
-//.word 0x90c664bb
-//.word 0x53229f58
-//.word 0xcb0842b0
-//.word 0x436710c9
-//.word 0xb329d981
-//.word 0x91b8f030
-//.word 0xe9c1df89
-//.word 0xb03858c1
-//.word 0x569c6ff4
-//.word 0x9a7c07c4
-//.word 0xa23a8a43
-//.word 0x4b0fde13
-//.word 0xbe4f94cb
-//.word 0x44ee629d
-//.word 0x5b44d336
-//.word 0x090d3de6
-//.word 0x80000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000280
-//// expected output
-//.word 0x147d8071
-//.word 0xc7871ef9
-//.word 0x256cff32
-//.word 0xaa63ea03
-//.word 0x1404fa5e
-//.word 0xe4ec09c5
-//.word 0x6afdd5da
-//.word 0x919b0cc8
-//.word 0x4a9d35d1
-//.word 0x42c41771
-//.word 0x52033160
-//.word 0x11cc620c
-//.word 0xd6855bb1
-//.word 0x17063a5e
-//.word 0x52867fac
-//.word 0xc680d5f4
-//// SHA512ShortMsgvector_82
-//// vector length
-//.word 0x00000288
-//// input message
-//.word 0xe5852109
-//.word 0x8911503d
-//.word 0xe8431138
-//.word 0x7d375c25
-//.word 0x929e6e55
-//.word 0x076eb693
-//.word 0x4fd8f2b1
-//.word 0xbb7b9667
-//.word 0xfbd76d5e
-//.word 0xe2048287
-//.word 0x69a341b1
-//.word 0xf716da5b
-//.word 0xdfece6c6
-//.word 0x2a9f4d4f
-//.word 0x988267fc
-//.word 0xe1f56155
-//.word 0x40dbe375
-//.word 0x324eef60
-//.word 0x7c910d97
-//.word 0x6b45a5ea
-//.word 0x5f800000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000288
-//// expected output
-//.word 0xf97ba056
-//.word 0xfa41f43b
-//.word 0x8e198707
-//.word 0x2a09e828
-//.word 0xc71c5ff6
-//.word 0xad4e37f9
-//.word 0xab6b89e2
-//.word 0xa078933d
-//.word 0xd23052fa
-//.word 0x72c6615b
-//.word 0x61390425
-//.word 0x9e9ff9b5
-//.word 0x5ef7b923
-//.word 0xb89bc875
-//.word 0x2f6babdd
-//.word 0xd256e117
-//// SHA512ShortMsgvector_83
-//// vector length
-//.word 0x00000290
-//// input message
-//.word 0x3796cf51
-//.word 0xb8726652
-//.word 0xa4204733
-//.word 0xb8fbb047
-//.word 0xcf00fb91
-//.word 0xa9837e22
-//.word 0xec22b1a2
-//.word 0x68f88e2c
-//.word 0x9f133e5f
-//.word 0x8527f1b1
-//.word 0x84830e07
-//.word 0xc3458c83
-//.word 0xa8ca9f9d
-//.word 0x9c699876
-//.word 0x0e610668
-//.word 0xba0f22e2
-//.word 0x2b656a73
-//.word 0x7e978b24
-//.word 0x6a17840b
-//.word 0x7dc4091d
-//.word 0xa85f8000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000290
-//// expected output
-//.word 0xc8a46619
-//.word 0x9acbcbc9
-//.word 0x3f2ce042
-//.word 0x968508c0
-//.word 0x46901631
-//.word 0xe3118a2d
-//.word 0x0bf39a9b
-//.word 0x42b4197a
-//.word 0x379b3a86
-//.word 0xcdeca9df
-//.word 0x2de1a3eb
-//.word 0x71b79ae9
-//.word 0xbf2d6575
-//.word 0xeadf1878
-//.word 0x029c4093
-//.word 0x133f54d3
-//// SHA512ShortMsgvector_84
-//// vector length
-//.word 0x00000298
-//// input message
-//.word 0x9af608d0
-//.word 0x31ccf309
-//.word 0xd7273c60
-//.word 0x7a8e5e36
-//.word 0x840d449b
-//.word 0x55db5b13
-//.word 0xf03aeb9a
-//.word 0xf49fa7e7
-//.word 0xcf1383ee
-//.word 0x2ed9c5a8
-//.word 0xb7515f16
-//.word 0xfb1c7c84
-//.word 0xa681590b
-//.word 0xf90f5659
-//.word 0x7b844db5
-//.word 0xebee223d
-//.word 0x78109b72
-//.word 0x350772f7
-//.word 0xc72ea996
-//.word 0x603e1e84
-//.word 0xf2ba5f80
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000298
-//// expected output
-//.word 0xf0ded949
-//.word 0x5b4f64ca
-//.word 0xc585be8a
-//.word 0x737cfa14
-//.word 0x247a4a81
-//.word 0xcdf7f01e
-//.word 0xbcb134ac
-//.word 0xe71f5a83
-//.word 0xdf2cd72e
-//.word 0x7773fea1
-//.word 0xe82beae1
-//.word 0x7e138573
-//.word 0x72792c82
-//.word 0x31e2ab9f
-//.word 0xbeb633e3
-//.word 0x99d5f0ae
-//// SHA512ShortMsgvector_85
-//// vector length
-//.word 0x000002A0
-//// input message
-//.word 0xd0df1bdf
-//.word 0x1df62032
-//.word 0x41722fb9
-//.word 0xc9c1cf74
-//.word 0x05017497
-//.word 0xae154538
-//.word 0xccf9224a
-//.word 0xd752e6ce
-//.word 0x1d4ae948
-//.word 0x639aca70
-//.word 0xcfe86b2b
-//.word 0x06543cb9
-//.word 0x914ebd30
-//.word 0x85aa3e29
-//.word 0x63f6e9b9
-//.word 0x3d0b03a3
-//.word 0x1ae26fcb
-//.word 0x9ca974ee
-//.word 0xe016c091
-//.word 0xa6fcac37
-//.word 0xb21cc1d7
-//.word 0x80000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000002A0
-//// expected output
-//.word 0xc2da3ea3
-//.word 0xc8a3fd88
-//.word 0xa5bc5dea
-//.word 0x2bc076f8
-//.word 0x61abedef
-//.word 0xae5a5fbd
-//.word 0x941ddfd1
-//.word 0xc41cc331
-//.word 0x2eb2dc82
-//.word 0x6c2c0f65
-//.word 0x414fe72e
-//.word 0xbee447d2
-//.word 0xf9b1a6a5
-//.word 0x6302660d
-//.word 0x1f86632e
-//.word 0xe80a175f
-//// SHA512ShortMsgvector_86
-//// vector length
-//.word 0x000002A8
-//// input message
-//.word 0x8cbc9480
-//.word 0x553acef7
-//.word 0xbcdba971
-//.word 0x6ea8d66b
-//.word 0x41317809
-//.word 0x17de2b0b
-//.word 0x048045fc
-//.word 0xb32b5cac
-//.word 0x054808e1
-//.word 0xfce6e94a
-//.word 0xd851ecb4
-//.word 0x7fe6cb80
-//.word 0x2225d355
-//.word 0x1e08ea12
-//.word 0x2093d007
-//.word 0x8dada564
-//.word 0x212eacf1
-//.word 0xd6394e00
-//.word 0x07cc62a1
-//.word 0xd595ab14
-//.word 0xca08a284
-//.word 0xbc800000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000002A8
-//// expected output
-//.word 0x63b39b88
-//.word 0xceb84818
-//.word 0x8b37316e
-//.word 0x04560e75
-//.word 0xa5340ab8
-//.word 0xd417932d
-//.word 0x231c997e
-//.word 0x892b41da
-//.word 0xa69d9fe3
-//.word 0xe9a14dd1
-//.word 0x9ccfbbfa
-//.word 0x01488c20
-//.word 0x8e7b946c
-//.word 0xfaf16ca2
-//.word 0xb1bf7c8d
-//.word 0x8da4e6b2
-//// SHA512ShortMsgvector_87
-//// vector length
-//.word 0x000002B0
-//// input message
-//.word 0x38f18444
-//.word 0x8f3cf82a
-//.word 0x54cafc55
-//.word 0x6aff336f
-//.word 0x23f9149e
-//.word 0x612134b3
-//.word 0xfc00c8a5
-//.word 0x6455653d
-//.word 0x88640b12
-//.word 0xf69062b8
-//.word 0x432c4335
-//.word 0xad8f7ab4
-//.word 0xff66cb7e
-//.word 0xb54f3325
-//.word 0x61a36f02
-//.word 0x4d92c3e2
-//.word 0x6276f4fd
-//.word 0x48619628
-//.word 0xcff88e4b
-//.word 0x8e85cf14
-//.word 0xca4767ed
-//.word 0x990d8000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000002B0
-//// expected output
-//.word 0x9a49265f
-//.word 0xc641c59f
-//.word 0x1a91872c
-//.word 0xdae490d3
-//.word 0xda73c0c6
-//.word 0x0fd59648
-//.word 0xe1d17dba
-//.word 0x1a647a5b
-//.word 0x95629392
-//.word 0xbb4ff516
-//.word 0x3d1a3cb4
-//.word 0x5427c143
-//.word 0x7a3b2e1d
-//.word 0x9f030c0a
-//.word 0x8bcc5ed2
-//.word 0x2da9e2ed
-//// SHA512ShortMsgvector_88
-//// vector length
-//.word 0x000002B8
-//// input message
-//.word 0x70900618
-//.word 0xb1e9e9db
-//.word 0x62296fb6
-//.word 0xc6590c9f
-//.word 0x10b0a632
-//.word 0x765c489c
-//.word 0x887f1ab7
-//.word 0xc0779176
-//.word 0x5a62e384
-//.word 0x65e1be28
-//.word 0x1b1d396c
-//.word 0x6e080b7e
-//.word 0xe3e6fa56
-//.word 0xa30b9799
-//.word 0xd0e629be
-//.word 0x153ee76f
-//.word 0x81bc6a32
-//.word 0x95aa6148
-//.word 0x9bfa87d5
-//.word 0x3a8ad242
-//.word 0x48a6ede0
-//.word 0xdfcfe980
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000002B8
-//// expected output
-//.word 0x1c8c3357
-//.word 0xff1f8d6a
-//.word 0xc4defb3a
-//.word 0xf462a73e
-//.word 0x09159e3a
-//.word 0x20c6506e
-//.word 0xdd8cd305
-//.word 0x2df941c8
-//.word 0x1f68c5fb
-//.word 0xb8939126
-//.word 0x19e28640
-//.word 0x977fe8ea
-//.word 0xae8e9d5d
-//.word 0x4e7d5f13
-//.word 0x2552cefa
-//.word 0xb4540bac
-//// SHA512ShortMsgvector_89
-//// vector length
-//.word 0x000002C0
-//// input message
-//.word 0x4e6ddae0
-//.word 0xd805afcd
-//.word 0x10a055bc
-//.word 0xe584c848
-//.word 0xd050fb29
-//.word 0xfe8f1c64
-//.word 0xb18e1abf
-//.word 0xe46b6578
-//.word 0x2e6ff536
-//.word 0xe89d8d40
-//.word 0x928b41ed
-//.word 0x7371365c
-//.word 0x8080a964
-//.word 0x7f7532ce
-//.word 0x6c6d4ac2
-//.word 0x1cfb0c80
-//.word 0x20783851
-//.word 0xec9a7dbc
-//.word 0x3948f8fc
-//.word 0xa7adf8b2
-//.word 0xa78c04d8
-//.word 0x98d31ff6
-//.word 0x80000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000002C0
-//// expected output
-//.word 0x5c2f996c
-//.word 0x779b91b3
-//.word 0xc4639311
-//.word 0xf54fabbd
-//.word 0xde7e2212
-//.word 0xb53dbae4
-//.word 0x828c8399
-//.word 0x588fc00d
-//.word 0x3b2ae609
-//.word 0x18aaaf6b
-//.word 0xb48bc757
-//.word 0xe52b2bce
-//.word 0xa84f5d15
-//.word 0xbf4ec25d
-//.word 0x5519fb54
-//.word 0xf6f26e1b
-//// SHA512ShortMsgvector_90
-//// vector length
-//.word 0x000002C8
-//// input message
-//.word 0x696825f6
-//.word 0xd6ea8173
-//.word 0xec47d095
-//.word 0x9a401c4d
-//.word 0xdf69f8f0
-//.word 0x8ddd678a
-//.word 0x4d2ff976
-//.word 0xe3a4372b
-//.word 0xb39f4159
-//.word 0x845cb635
-//.word 0x85e1d410
-//.word 0x8d32e12f
-//.word 0xa7c5c9d7
-//.word 0xce3508a7
-//.word 0xf53aca2b
-//.word 0x4bd951ad
-//.word 0xbcd8984e
-//.word 0xbb753656
-//.word 0x3f5884c9
-//.word 0x0bc5023b
-//.word 0x3316f7e4
-//.word 0xdc6958f7
-//.word 0x43800000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000002C8
-//// expected output
-//.word 0x3ce940ca
-//.word 0x96b00011
-//.word 0x375daa95
-//.word 0xc65f6690
-//.word 0x7d69b3eb
-//.word 0x3b8d779e
-//.word 0x6fc971af
-//.word 0xcc05e990
-//.word 0xbc4c541f
-//.word 0x434590f6
-//.word 0xb18b68c0
-//.word 0x80d0f244
-//.word 0x75a3e764
-//.word 0xe9cb8534
-//.word 0x3301314e
-//.word 0xe2fb661e
-//// SHA512ShortMsgvector_91
-//// vector length
-//.word 0x000002D0
-//// input message
-//.word 0x79ecdfd4
-//.word 0x7a29a742
-//.word 0x20a52819
-//.word 0xce458974
-//.word 0x7f2b30b3
-//.word 0x64d0852c
-//.word 0xce52f91e
-//.word 0x4f0f48e6
-//.word 0x1c72fa76
-//.word 0xb60d3002
-//.word 0xcae89dfc
-//.word 0x5519d343
-//.word 0x0b95c098
-//.word 0xfa467851
-//.word 0x6b5e3551
-//.word 0x09ea9b37
-//.word 0x45aa41d6
-//.word 0xf8206ee6
-//.word 0x4ae720f8
-//.word 0xd44653b0
-//.word 0x01057f2e
-//.word 0xba7f63cd
-//.word 0x42f98000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000002D0
-//// expected output
-//.word 0xba3d0fe0
-//.word 0x4470f4cf
-//.word 0x8f08c46d
-//.word 0x82ae3afd
-//.word 0x1caea8c1
-//.word 0x3bebbe02
-//.word 0x6b5c1777
-//.word 0xaa59860a
-//.word 0xf2e3da77
-//.word 0x51844e0b
-//.word 0xe24072af
-//.word 0x48bc8a6f
-//.word 0xd77678aa
-//.word 0xee04e08f
-//.word 0x63395f5c
-//.word 0x8a465763
-//// SHA512ShortMsgvector_92
-//// vector length
-//.word 0x000002D8
-//// input message
-//.word 0x9263fe75
-//.word 0xe8f6c7d5
-//.word 0xd642e2ca
-//.word 0x6a6eea4f
-//.word 0x44e9a0f2
-//.word 0x49513ed7
-//.word 0x9c9409ff
-//.word 0xca5526ca
-//.word 0x4491aebb
-//.word 0x1382057c
-//.word 0xc7c36722
-//.word 0xb0b6c3b1
-//.word 0x5123cde3
-//.word 0x12214f25
-//.word 0x353abfe3
-//.word 0x0bca1705
-//.word 0x68a8e1ba
-//.word 0x54089174
-//.word 0x03a01834
-//.word 0x080ab607
-//.word 0xc56a10d0
-//.word 0x26508249
-//.word 0x8fe0b680
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000002D8
-//// expected output
-//.word 0x7736d7a7
-//.word 0xfc1eb058
-//.word 0x57ce7d88
-//.word 0xabfffa87
-//.word 0xf58c670b
-//.word 0xfdfc0a80
-//.word 0x31f60f37
-//.word 0x9e4b6ad9
-//.word 0x4ac8f13f
-//.word 0xfe28c697
-//.word 0x809b5cfa
-//.word 0xc7f13be0
-//.word 0x1e7496a8
-//.word 0x5237c402
-//.word 0x5539051f
-//.word 0xb2e32fb6
-//// SHA512ShortMsgvector_93
-//// vector length
-//.word 0x000002E0
-//// input message
-//.word 0x78c17bfe
-//.word 0x0e02eb52
-//.word 0x6d1a44a1
-//.word 0xac127be0
-//.word 0x82181452
-//.word 0xb625394b
-//.word 0xd6dc093a
-//.word 0x2cb432e6
-//.word 0xee59c2f8
-//.word 0xb5503aba
-//.word 0x30dae41e
-//.word 0x1a1c6702
-//.word 0x697c99b2
-//.word 0xc94e94af
-//.word 0x48b00caf
-//.word 0x53b2e0e4
-//.word 0xe1bbee81
-//.word 0xee282c7b
-//.word 0x2b35f58c
-//.word 0xf421a07e
-//.word 0x828d57a6
-//.word 0x622626af
-//.word 0x25835399
-//.word 0x80000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000002E0
-//// expected output
-//.word 0xb56b6e34
-//.word 0x31663285
-//.word 0x23e0d169
-//.word 0x3e5174da
-//.word 0x643ae83c
-//.word 0xf69c85a7
-//.word 0xb3c3bee2
-//.word 0x47b77b84
-//.word 0x702069d9
-//.word 0xe6b4cab0
-//.word 0x3bf17fe6
-//.word 0x12009bf4
-//.word 0x239683ca
-//.word 0x78ca7e87
-//.word 0x6aca7d07
-//.word 0x603ba714
-//// SHA512ShortMsgvector_94
-//// vector length
-//.word 0x000002E8
-//// input message
-//.word 0x298bb304
-//.word 0xa920f960
-//.word 0x447d8fd3
-//.word 0x8b061bf8
-//.word 0xfe4ac1f8
-//.word 0x71d8a0fe
-//.word 0xb4549feb
-//.word 0x72ca694a
-//.word 0x5a41b686
-//.word 0x7d94cd5a
-//.word 0xf77d468a
-//.word 0xd2f315d1
-//.word 0x27b6c41a
-//.word 0x862800f3
-//.word 0x985e573e
-//.word 0x03774029
-//.word 0x8e2c5c61
-//.word 0x86a9fb83
-//.word 0x609be2d4
-//.word 0x9f8b4c31
-//.word 0xf96a2e49
-//.word 0xb56dbf09
-//.word 0x571b3858
-//.word 0x7f800000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000002E8
-//// expected output
-//.word 0x34e38786
-//.word 0x27904ffb
-//.word 0xbbd85266
-//.word 0xcc973c34
-//.word 0xf931e3ca
-//.word 0xb5d4c31f
-//.word 0x841c553d
-//.word 0xd69f8483
-//.word 0x8206067d
-//.word 0xf4f9f3b9
-//.word 0x102001be
-//.word 0x19267151
-//.word 0xe673f5c2
-//.word 0xd4c2f843
-//.word 0x8a6999a0
-//.word 0xa325487d
-//// SHA512ShortMsgvector_95
-//// vector length
-//.word 0x000002F0
-//// input message
-//.word 0xa3cf714b
-//.word 0xf112647e
-//.word 0x727e8cfd
-//.word 0x46499acd
-//.word 0x35a640dd
-//.word 0x393ddd26
-//.word 0x3cd85cf6
-//.word 0x225f5989
-//.word 0x0a0686da
-//.word 0xd1c54eb8
-//.word 0xd809b81c
-//.word 0x08a98dba
-//.word 0x131bbdd6
-//.word 0xfce8ff59
-//.word 0xd95db824
-//.word 0xd8831ea4
-//.word 0x80529da7
-//.word 0x39227a6e
-//.word 0x0f62b603
-//.word 0xb38c35cd
-//.word 0xc2581f61
-//.word 0x4a31879b
-//.word 0x8be54aee
-//.word 0xfaa08000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000002F0
-//// expected output
-//.word 0x6f230ae4
-//.word 0x903ddbef
-//.word 0x0ba384c2
-//.word 0xe3506eab
-//.word 0x318bfd1a
-//.word 0x46ea7609
-//.word 0x9f65a3fd
-//.word 0x529c91bc
-//.word 0x2865b9fd
-//.word 0x943e346d
-//.word 0xe64626b8
-//.word 0x529f9db1
-//.word 0x377bf2c5
-//.word 0xe0129c66
-//.word 0xb50c6a5c
-//.word 0xfb364b3a
-//// SHA512ShortMsgvector_96
-//// vector length
-//.word 0x000002F8
-//// input message
-//.word 0x0a427ae5
-//.word 0x5ef3a7e6
-//.word 0x044a08cf
-//.word 0x6128cbaa
-//.word 0xabfd776c
-//.word 0x4e937470
-//.word 0x8f2ece24
-//.word 0x6fd73603
-//.word 0xd2f54ac3
-//.word 0xe01d16cf
-//.word 0xac2bdaf7
-//.word 0x13920d66
-//.word 0xe8f0a3d5
-//.word 0x4ee68cff
-//.word 0x64267d55
-//.word 0x28cdf2f2
-//.word 0x95f474d1
-//.word 0x0f81173e
-//.word 0x0143488a
-//.word 0xc53fc503
-//.word 0xc444ed23
-//.word 0xdec63a08
-//.word 0x0ce90c24
-//.word 0x43dba880
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000002F8
-//// expected output
-//.word 0xf6bbe5d0
-//.word 0xcf13ddf4
-//.word 0x1c143674
-//.word 0x8a5d1cca
-//.word 0xe2948547
-//.word 0xb452c217
-//.word 0x1c7c8e8b
-//.word 0x66c6ae4d
-//.word 0xe3c0e8b2
-//.word 0x962bcb60
-//.word 0xd3de3608
-//.word 0x479f80e4
-//.word 0x55c9024d
-//.word 0x9716c38f
-//.word 0x6f120686
-//.word 0x1ab1eaac
-//// SHA512ShortMsgvector_97
-//// vector length
-//.word 0x00000300
-//// input message
-//.word 0x2cbbb875
-//.word 0x11f4948e
-//.word 0xfec3a61b
-//.word 0x511ededb
-//.word 0x1dda8b6e
-//.word 0xcfc0210c
-//.word 0x11e43a77
-//.word 0xee32dc2e
-//.word 0x374afae4
-//.word 0x268e3d30
-//.word 0x42780486
-//.word 0x8232a966
-//.word 0xb56006d3
-//.word 0x21403707
-//.word 0x6bf6a265
-//.word 0xb72135af
-//.word 0x0fb2ef79
-//.word 0x09fea2de
-//.word 0xa412f771
-//.word 0x7446b276
-//.word 0xff153753
-//.word 0x662b4d41
-//.word 0x48c02347
-//.word 0xe3259169
-//.word 0x80000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000300
-//// expected output
-//.word 0x76897b87
-//.word 0xa8a1cf83
-//.word 0x5c434f6d
-//.word 0x391c9e52
-//.word 0x27351af9
-//.word 0xd3e20a33
-//.word 0x89c796b9
-//.word 0x8b424281
-//.word 0xa59068d9
-//.word 0xc8d567ec
-//.word 0x2bebc435
-//.word 0xb0126b05
-//.word 0x9e2d8639
-//.word 0x4a9854d6
-//.word 0x611e1c92
-//.word 0x2f385496
-//// SHA512ShortMsgvector_98
-//// vector length
-//.word 0x00000308
-//// input message
-//.word 0x2b23324c
-//.word 0x9992f60a
-//.word 0x7fc01015
-//.word 0x9a03cb9a
-//.word 0x2b290df4
-//.word 0xfa6a8235
-//.word 0x9b9af602
-//.word 0xf0a403a5
-//.word 0xef33ed5d
-//.word 0xa5b2caf8
-//.word 0x7b77e6a4
-//.word 0xb93b6503
-//.word 0x48ce2a7d
-//.word 0xbc08f8da
-//.word 0x9203d710
-//.word 0xb587ba59
-//.word 0x47c65e89
-//.word 0x9f4a759f
-//.word 0x8e2b049a
-//.word 0xe7850a8e
-//.word 0x3e2962f6
-//.word 0xef93ea4c
-//.word 0x631de5d7
-//.word 0x8e729ec5
-//.word 0xbc800000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000308
-//// expected output
-//.word 0x3beea0b3
-//.word 0x73ed09cf
-//.word 0x1c919c51
-//.word 0xd86d642c
-//.word 0x9125e0ee
-//.word 0x81698dc4
-//.word 0xcbadf02e
-//.word 0x9e6925ef
-//.word 0xb562fd9b
-//.word 0x87301a63
-//.word 0x77ca192b
-//.word 0xe79c4118
-//.word 0xdeabc450
-//.word 0xb5463900
-//.word 0x0c2e3129
-//.word 0x45451fb5
-//// SHA512ShortMsgvector_99
-//// vector length
-//.word 0x00000310
-//// input message
-//.word 0x4022f930
-//.word 0xc7033b00
-//.word 0xd986c65f
-//.word 0xf6bbbdf9
-//.word 0xebd0e58c
-//.word 0x52844ff6
-//.word 0x58df3893
-//.word 0xc3202dc5
-//.word 0x33f873d4
-//.word 0xa7f5a5f9
-//.word 0x44419fb5
-//.word 0x528c9b67
-//.word 0x88479a1e
-//.word 0x891306ac
-//.word 0xae7995fc
-//.word 0x06db70a5
-//.word 0x9baa95be
-//.word 0xf7da79f5
-//.word 0xe793f2db
-//.word 0x7f2a5582
-//.word 0x5e4fdb4a
-//.word 0x34884af8
-//.word 0x81ded108
-//.word 0x9fd53345
-//.word 0x02a28000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000310
-//// expected output
-//.word 0x0358775b
-//.word 0xbb733ccc
-//.word 0x49e78f54
-//.word 0x4aeee512
-//.word 0x370d480d
-//.word 0x0e13c7e8
-//.word 0xd5c444c4
-//.word 0x23e59214
-//.word 0x6b45fdb9
-//.word 0x1a1b694d
-//.word 0x35e36b60
-//.word 0xe4bc8397
-//.word 0xfca8bb97
-//.word 0x90e61933
-//.word 0x9778b9cd
-//.word 0x1abe3fe9
-//// SHA512ShortMsgvector_100
-//// vector length
-//.word 0x00000318
-//// input message
-//.word 0x1cb77ba4
-//.word 0x3ce77e23
-//.word 0x6b9fc925
-//.word 0xf589b1c0
-//.word 0x70780a84
-//.word 0xf99e8f50
-//.word 0xc1ff846a
-//.word 0xc92599cf
-//.word 0xe91612c8
-//.word 0x178325be
-//.word 0xe642a34f
-//.word 0x4dffdba2
-//.word 0xaa2ebcf7
-//.word 0x06433982
-//.word 0x9b26f279
-//.word 0x93e1106c
-//.word 0x139c70d5
-//.word 0x78cc05f0
-//.word 0xe1a777cc
-//.word 0xeddb10a2
-//.word 0xc67fd967
-//.word 0x5e4a009d
-//.word 0xf8037d6e
-//.word 0xeb38f5fb
-//.word 0xa233df80
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000318
-//// expected output
-//.word 0x6502f465
-//.word 0x51a3fab3
-//.word 0xa96428fb
-//.word 0x97801d7a
-//.word 0x4aa2f17f
-//.word 0xef660323
-//.word 0x8df84e17
-//.word 0xc74309ed
-//.word 0x3d9489c8
-//.word 0xb16a9384
-//.word 0xee634a3f
-//.word 0x86d0b3ba
-//.word 0x9a4dbc9c
-//.word 0x51ec8bd4
-//.word 0xbf8d61de
-//.word 0x6d3d87d7
-//// SHA512ShortMsgvector_101
-//// vector length
-//.word 0x00000320
-//// input message
-//.word 0x52167de2
-//.word 0xd6c502d9
-//.word 0x9fa10c27
-//.word 0xb2ab6203
-//.word 0xbdebc2ca
-//.word 0xfbbfdef1
-//.word 0x5872a43d
-//.word 0xd610c236
-//.word 0x2f796ad9
-//.word 0xbcb5528d
-//.word 0x95870058
-//.word 0xfa454453
-//.word 0xf1e6065b
-//.word 0x315d410a
-//.word 0x3f2650e5
-//.word 0xd71e69d7
-//.word 0x8d9767df
-//.word 0xb4accc05
-//.word 0x7fd20692
-//.word 0x66b0f180
-//.word 0xcb319e30
-//.word 0xded7535b
-//.word 0xbe52d24b
-//.word 0xe151de4b
-//.word 0xb598fc5c
-//.word 0x80000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000320
-//// expected output
-//.word 0x25cb3ed3
-//.word 0x983a91b4
-//.word 0xcf37a651
-//.word 0x93916c5e
-//.word 0x3e211b63
-//.word 0xe943e2f7
-//.word 0xb50a85d3
-//.word 0x49a463b9
-//.word 0x41aad33e
-//.word 0xff16561b
-//.word 0xdfdc92fd
-//.word 0xa06a4e1d
-//.word 0x94b162de
-//.word 0x48f06d3c
-//.word 0x626940b3
-//.word 0x1020925f
-//// SHA512ShortMsgvector_102
-//// vector length
-//.word 0x00000328
-//// input message
-//.word 0xcede6697
-//.word 0xd422ddaa
-//.word 0x78e2d55a
-//.word 0xe080b8b9
-//.word 0xe9356c69
-//.word 0xbc558201
-//.word 0xa2d4b0b3
-//.word 0x190a812c
-//.word 0x27b34bbc
-//.word 0xee3a62b7
-//.word 0x81378b1b
-//.word 0xf636b372
-//.word 0xbcbae1fa
-//.word 0x2f816a04
-//.word 0x6a0a649a
-//.word 0x5c555c64
-//.word 0x1fea4ccd
-//.word 0x841cc761
-//.word 0xf38f7779
-//.word 0x72f8c91b
-//.word 0x0324e71c
-//.word 0x333ce787
-//.word 0xf0474143
-//.word 0x9bf087ef
-//.word 0x5e895011
-//.word 0xc0800000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000328
-//// expected output
-//.word 0x0be42a25
-//.word 0xd77ac6ad
-//.word 0x995c6be4
-//.word 0x8e783380
-//.word 0xbad25a61
-//.word 0x732f87ce
-//.word 0xfb0cce1a
-//.word 0x769cd690
-//.word 0x81f494a1
-//.word 0xa12d6576
-//.word 0x64ef2b4d
-//.word 0x9c41f2ee
-//.word 0x83f6e9a8
-//.word 0x4327d875
-//.word 0x6af9f985
-//.word 0x595e7d3b
-//// SHA512ShortMsgvector_103
-//// vector length
-//.word 0x00000330
-//// input message
-//.word 0x56d18d3e
-//.word 0x2e496440
-//.word 0xd0a5c9e1
-//.word 0xbcb464fa
-//.word 0xf5bc70a8
-//.word 0xb562124f
-//.word 0x5fc9e9de
-//.word 0xb5fee654
-//.word 0x4b945e83
-//.word 0x3b8b5d13
-//.word 0x1b773ecb
-//.word 0x2cdd780c
-//.word 0xd4e1bb9e
-//.word 0x4f1e3cb0
-//.word 0xa1d64d19
-//.word 0xcf4b30e4
-//.word 0x4e6c2d0c
-//.word 0xbcb4e284
-//.word 0xce50db7a
-//.word 0x8a8062dd
-//.word 0xb63f981d
-//.word 0x9026c532
-//.word 0xbf8eeddf
-//.word 0x8af5a438
-//.word 0x48a32262
-//.word 0x178c8000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000330
-//// expected output
-//.word 0x982dc61c
-//.word 0x91a93770
-//.word 0x582eee80
-//.word 0x25aa55da
-//.word 0x8e9edb96
-//.word 0x6bf5cf70
-//.word 0xd4a6534c
-//.word 0x0d53a278
-//.word 0x9a8c4fb6
-//.word 0x5b7fed47
-//.word 0x8cda02ed
-//.word 0x1e0d198d
-//.word 0x85c5c735
-//.word 0xb2417c5f
-//.word 0xab5d34e9
-//.word 0x69fc8e7e
-//// SHA512ShortMsgvector_104
-//// vector length
-//.word 0x00000338
-//// input message
-//.word 0x25a7320d
-//.word 0xfaec5af6
-//.word 0x5da4d0f8
-//.word 0x688e29e8
-//.word 0xe95532ec
-//.word 0xc16679ea
-//.word 0x8aff0f40
-//.word 0x7d898db6
-//.word 0x922855b0
-//.word 0xe8901aa9
-//.word 0x681aa3dc
-//.word 0xa617cb44
-//.word 0x0764cdc7
-//.word 0x293fbeaf
-//.word 0x7f585b59
-//.word 0x3c2b0531
-//.word 0x738e0ade
-//.word 0x7c8626b9
-//.word 0x995f4a84
-//.word 0xd9fc9b59
-//.word 0x3d6bbee0
-//.word 0x1abc53c5
-//.word 0xbe14bf69
-//.word 0x56fd2fd8
-//.word 0x1000dafc
-//.word 0x7c768680
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000338
-//// expected output
-//.word 0x749c928c
-//.word 0x3d551092
-//.word 0x5bfe9865
-//.word 0x9025b0ed
-//.word 0x7c01acd4
-//.word 0xd59a9bf1
-//.word 0xc54863a0
-//.word 0x88091771
-//.word 0xdc9d407b
-//.word 0xdbf83b0f
-//.word 0x44b0902e
-//.word 0x10349ba7
-//.word 0x9c84d098
-//.word 0x1d5e8c4f
-//.word 0x5c733a11
-//.word 0x7fed0790
-//// SHA512ShortMsgvector_105
-//// vector length
-//.word 0x00000340
-//// input message
-//.word 0x3d7177b2
-//.word 0x8ffd916e
-//.word 0x7e063489
-//.word 0x5833ba0b
-//.word 0xd9e0653d
-//.word 0xf2cc4202
-//.word 0xc811536a
-//.word 0x005aec85
-//.word 0x3a505e75
-//.word 0xdb55d3c7
-//.word 0x10757904
-//.word 0x1099e382
-//.word 0xa1feac80
-//.word 0xdde65d72
-//.word 0x368e909a
-//.word 0xb85f56d8
-//.word 0x8e68d7c3
-//.word 0xc80c38f8
-//.word 0x5bf8c2b3
-//.word 0x6959409c
-//.word 0xc34ba8e3
-//.word 0xad94fe8e
-//.word 0xe1927612
-//.word 0xd672d921
-//.word 0x41a329c4
-//.word 0xdd8a88a9
-//.word 0x80000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000340
-//// expected output
-//.word 0x14a33150
-//.word 0x8cd7d94f
-//.word 0xcce56a66
-//.word 0xbf65f208
-//.word 0x70a281c8
-//.word 0x442f8dbd
-//.word 0x4c237145
-//.word 0x4a2b66f8
-//.word 0xd0994a0b
-//.word 0x67692e77
-//.word 0x1efc6a5e
-//.word 0x0b887aca
-//.word 0xe7d6f4ec
-//.word 0x7338e1aa
-//.word 0x89f2abc7
-//.word 0x034c4e4c
-//// SHA512ShortMsgvector_106
-//// vector length
-//.word 0x00000348
-//// input message
-//.word 0xc033e4a5
-//.word 0x12297cae
-//.word 0xcdbead89
-//.word 0x2b11a9f7
-//.word 0x007af9a7
-//.word 0x4bcab89e
-//.word 0x0bd4ffdd
-//.word 0x542ca03e
-//.word 0xa12e17a0
-//.word 0x6c42bd43
-//.word 0xfc5f3f75
-//.word 0x7fce4f6f
-//.word 0x5831997a
-//.word 0xbac3f956
-//.word 0x76e1ebdb
-//.word 0x11ca43e1
-//.word 0x1aa31e5e
-//.word 0xbabe18ce
-//.word 0x8d1bbfd8
-//.word 0xb02f482e
-//.word 0x1ce581b5
-//.word 0x32e307e6
-//.word 0x960eb974
-//.word 0x41506c2e
-//.word 0xd299e128
-//.word 0x2523f415
-//.word 0x27800000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000348
-//// expected output
-//.word 0x95ac9b7d
-//.word 0x22aa4589
-//.word 0x21874c4b
-//.word 0x4331e7d6
-//.word 0x47618532
-//.word 0x17c3f83c
-//.word 0x601abcbc
-//.word 0xcd7e2eaa
-//.word 0x6ca6ce9a
-//.word 0x22ebcfe5
-//.word 0x046d52f8
-//.word 0xa09097f0
-//.word 0x43ab8bc5
-//.word 0x9243fd77
-//.word 0x0090bb43
-//.word 0x2c3155e9
-//// SHA512ShortMsgvector_107
-//// vector length
-//.word 0x00000350
-//// input message
-//.word 0x69fff0f1
-//.word 0xa3dbfb36
-//.word 0xe32f0258
-//.word 0x19fa99ea
-//.word 0x9a0edaef
-//.word 0x73145bf7
-//.word 0xfcd05d8b
-//.word 0xb0a646cb
-//.word 0x3b5d5256
-//.word 0xd524856a
-//.word 0xcfd2e44d
-//.word 0x6b72e4eb
-//.word 0xf1ff23c0
-//.word 0xff6c56f8
-//.word 0x21e782d5
-//.word 0xa15f7052
-//.word 0xa1445b06
-//.word 0x668eeb4a
-//.word 0xf700679e
-//.word 0xe7ae2649
-//.word 0x6fbd4640
-//.word 0xc06aa149
-//.word 0x964dfd60
-//.word 0x11df835a
-//.word 0xc13b73c8
-//.word 0xff21151e
-//.word 0x84408000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000350
-//// expected output
-//.word 0x45d4daa6
-//.word 0x52558d1c
-//.word 0x12beb0f5
-//.word 0x662c712f
-//.word 0x325b4c80
-//.word 0x2fc6eb9e
-//.word 0xe039c949
-//.word 0xd002bb78
-//.word 0x6f1a7327
-//.word 0x12be941f
-//.word 0x9c5c79b3
-//.word 0xe5c43064
-//.word 0xd63a3857
-//.word 0x8e5a54ee
-//.word 0x526acb73
-//.word 0x5b9ad45f
-//// SHA512ShortMsgvector_108
-//// vector length
-//.word 0x00000358
-//// input message
-//.word 0xb2c439c9
-//.word 0x7ab7c637
-//.word 0x36b37963
-//.word 0x24d68eeb
-//.word 0x7a471ed1
-//.word 0x42bd9622
-//.word 0x684167d6
-//.word 0x1234fff8
-//.word 0x2f93f907
-//.word 0x537a909b
-//.word 0xc2e75a4b
-//.word 0xcbc133cf
-//.word 0x57197662
-//.word 0xc1af746a
-//.word 0xe8b81e5b
-//.word 0x83de05d9
-//.word 0xb589851d
-//.word 0xe25d3c99
-//.word 0xc004c1df
-//.word 0xb12d93bf
-//.word 0x50d450af
-//.word 0x49c42871
-//.word 0x6f5b90ef
-//.word 0x088e3b6a
-//.word 0x6b2c46d3
-//.word 0xce67b379
-//.word 0x59901880
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000358
-//// expected output
-//.word 0xc48ec83b
-//.word 0xe5fa669e
-//.word 0x6ec8db90
-//.word 0xaca9676c
-//.word 0xfe2ec0d5
-//.word 0xe8e7a243
-//.word 0x1687bb95
-//.word 0x3c0a300b
-//.word 0xe3db4075
-//.word 0xcca3bac4
-//.word 0xdfa4d971
-//.word 0xbaf0fa1a
-//.word 0xff46639d
-//.word 0xb4b23885
-//.word 0x6ff36d1d
-//.word 0xfcd520f1
-//// SHA512ShortMsgvector_109
-//// vector length
-//.word 0x00000360
-//// input message
-//.word 0xc016f522
-//.word 0xf26b7470
-//.word 0xe922b9a2
-//.word 0x87e6d45f
-//.word 0x6c28813b
-//.word 0x68c1457e
-//.word 0x36d9ba26
-//.word 0x6708272f
-//.word 0x9cbc5411
-//.word 0xf8db9d8b
-//.word 0xd5a9449f
-//.word 0xb6eb0cde
-//.word 0x7d4d03e5
-//.word 0xdf019f28
-//.word 0x14a90cee
-//.word 0xd377c59d
-//.word 0x7d926238
-//.word 0x99bcb026
-//.word 0x80330735
-//.word 0x59d4d8de
-//.word 0x488686cb
-//.word 0xe3d67796
-//.word 0xe6df6ad4
-//.word 0x276d0b52
-//.word 0xcc62c49e
-//.word 0xbb58d7c9
-//.word 0x5287aa6c
-//.word 0x80000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000360
-//// expected output
-//.word 0x7402f1a9
-//.word 0x9b47e102
-//.word 0xb3b73140
-//.word 0xc6771b07
-//.word 0xee6c33b3
-//.word 0x715e9c40
-//.word 0x27c441be
-//.word 0xe40511b7
-//.word 0x35d95e50
-//.word 0x8baea78d
-//.word 0xa26fded9
-//.word 0xb7038e9a
-//.word 0x53defa58
-//.word 0x448aba40
-//.word 0xdc1e62d7
-//.word 0xec592107
-//// SHA512ShortMsgvector_110
-//// vector length
-//.word 0x00000368
-//// input message
-//.word 0xa766b2a7
-//.word 0xef916721
-//.word 0xf4677b67
-//.word 0xdbc65ef9
-//.word 0xb4d1bda1
-//.word 0xad4e53fc
-//.word 0x854b0236
-//.word 0x44082215
-//.word 0x2a111939
-//.word 0xe5ab2ba2
-//.word 0x07719472
-//.word 0xb63fd4f4
-//.word 0xa54f4bde
-//.word 0x44a205d3
-//.word 0x34a2d72c
-//.word 0xfe05abf8
-//.word 0x04f41841
-//.word 0xb86d3692
-//.word 0x0be6b0b5
-//.word 0x29331ac1
-//.word 0x63a98555
-//.word 0x6c84511e
-//.word 0xc986439f
-//.word 0x83e1d731
-//.word 0x1f57d848
-//.word 0xcfa02df9
-//.word 0xea0cf6b9
-//.word 0x9a800000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000368
-//// expected output
-//.word 0xddd60f93
-//.word 0xa3babc78
-//.word 0x299cf763
-//.word 0xe7919d45
-//.word 0xac6f4797
-//.word 0x00e1adb0
-//.word 0x5ab137ac
-//.word 0xdf89c152
-//.word 0x1ecb9dfe
-//.word 0xacd091e5
-//.word 0x8ca57a1d
-//.word 0xb964a9c3
-//.word 0xcd1fa391
-//.word 0x92cc1e9f
-//.word 0x734caa1c
-//.word 0x5fa62975
-//// SHA512ShortMsgvector_111
-//// vector length
-//.word 0x00000370
-//// input message
-//.word 0x10f2be77
-//.word 0xa4055771
-//.word 0xa67007cd
-//.word 0x8630e323
-//.word 0x0e382884
-//.word 0x99cb1603
-//.word 0x80290174
-//.word 0xd66da574
-//.word 0x55b6baaa
-//.word 0x9785c84c
-//.word 0x8a663de4
-//.word 0x1ed3bd54
-//.word 0x4055b917
-//.word 0x0cec43cb
-//.word 0x3eb120ec
-//.word 0xeaba1fe3
-//.word 0x6e3eaa3f
-//.word 0xa4f99b42
-//.word 0x5cd2519f
-//.word 0x09bc0282
-//.word 0xbada52d1
-//.word 0x4ce625b1
-//.word 0xded3b24d
-//.word 0x86b1dad3
-//.word 0x42d2b7be
-//.word 0x322b775b
-//.word 0x04fc6b86
-//.word 0xafb48000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000370
-//// expected output
-//.word 0xa872fa33
-//.word 0xd463b334
-//.word 0x3cec57c2
-//.word 0x0c66979c
-//.word 0x33e1ad06
-//.word 0x7bfc7034
-//.word 0x54696aab
-//.word 0x5dd0003b
-//.word 0xc194318f
-//.word 0x4a8ebbc7
-//.word 0x4503feb7
-//.word 0x211a472d
-//.word 0xadee991e
-//.word 0xfe3e38f2
-//.word 0x1a1310f8
-//.word 0xa76eac80
-//// SHA512ShortMsgvector_112
-//// vector length
-//.word 0x00000378
-//// input message
-//.word 0x324533e6
-//.word 0x85f1852e
-//.word 0x358eea8e
-//.word 0xa8b81c28
-//.word 0x8b3f3beb
-//.word 0x1f2bc2b8
-//.word 0xd3fdbac3
-//.word 0x18382e3d
-//.word 0x7120de30
-//.word 0xc9c237aa
-//.word 0x0a34831d
-//.word 0xeb1e5e06
-//.word 0x0a7969cd
-//.word 0x3a9742ec
-//.word 0x1e64b354
-//.word 0xf7eb290c
-//.word 0xba1c681c
-//.word 0x66cc7ea9
-//.word 0x94fdf561
-//.word 0x4f604d1a
-//.word 0x2718aab5
-//.word 0x81c1c949
-//.word 0x31b1387e
-//.word 0x4b7dc736
-//.word 0x35bf3a73
-//.word 0x01174075
-//.word 0xfa70a922
-//.word 0x7d85d380
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000378
-//// expected output
-//.word 0x3b26c517
-//.word 0x0729d081
-//.word 0x4153becb
-//.word 0x95f1b65c
-//.word 0xd42f9a6d
-//.word 0x0649d914
-//.word 0xe4f69d93
-//.word 0x8b5e9dc0
-//.word 0x41cd0f5c
-//.word 0x8da0b484
-//.word 0xd7c7bc7b
-//.word 0x1bdefb08
-//.word 0xfe8b1bfe
-//.word 0xdc811093
-//.word 0x45bc9e9a
-//.word 0x399feedf
-//// SHA512ShortMsgvector_113
-//// vector length
-//.word 0x00000380
-//// input message
-//.word 0x51898597
-//.word 0x7ee21d2b
-//.word 0xf622a205
-//.word 0x67124fcb
-//.word 0xf11c72df
-//.word 0x80536583
-//.word 0x5ab3c041
-//.word 0xf4a9cd8a
-//.word 0x0ad63c9d
-//.word 0xee1018aa
-//.word 0x21a9fa37
-//.word 0x20f47dc4
-//.word 0x8006f1aa
-//.word 0x3dba5449
-//.word 0x50f87e62
-//.word 0x7f369bc2
-//.word 0x793ede21
-//.word 0x22327449
-//.word 0x2cceb77b
-//.word 0xe7eea50e
-//.word 0x5a509059
-//.word 0x929a16d3
-//.word 0x3a9f5479
-//.word 0x6cde5770
-//.word 0xc74bd3ec
-//.word 0xc2531850
-//.word 0x3f1a4197
-//.word 0x6407aff2
-//.word 0x80000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000380
-//// expected output
-//.word 0xc00926a3
-//.word 0x74cde55b
-//.word 0x8fbd77f5
-//.word 0x0da1363d
-//.word 0xa19744d3
-//.word 0xf464e07c
-//.word 0xe31794c5
-//.word 0xa61b6f9c
-//.word 0x85689fa1
-//.word 0xcfe13655
-//.word 0x3527fd87
-//.word 0x6be91673
-//.word 0xc2cac2dd
-//.word 0x157b2def
-//.word 0xea360851
-//.word 0xb6d92cf4
-//// SHA512ShortMsgvector_114
-//// vector length
-//.word 0x00000388
-//// input message
-//.word 0x91597672
-//.word 0x75ba6f79
-//.word 0xcbb3d58c
-//.word 0x0108339d
-//.word 0x8c6a4113
-//.word 0x8991ab7a
-//.word 0xa58b1479
-//.word 0x3b545b04
-//.word 0xbda61dd2
-//.word 0x55127b12
-//.word 0xcc501d5a
-//.word 0xaad476e0
-//.word 0x9fa14aec
-//.word 0x21626e8d
-//.word 0x57b7d08c
-//.word 0x36cdb79e
-//.word 0xea314bdd
-//.word 0x77e65779
-//.word 0xa0b54eab
-//.word 0x08c48ceb
-//.word 0x976adf63
-//.word 0x1f4246a3
-//.word 0x3f7ef896
-//.word 0x887ea8b5
-//.word 0xdfa2087a
-//.word 0x225c8c18
-//.word 0x0f897069
-//.word 0x6101fc28
-//.word 0x3b800000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000388
-//// expected output
-//.word 0x3cd3380a
-//.word 0x90868de1
-//.word 0x7dee4bd4
-//.word 0xd7f90d75
-//.word 0x12696f0a
-//.word 0x92b2d089
-//.word 0x240d61a9
-//.word 0xd20cd3af
-//.word 0x094c78bf
-//.word 0x466c2d40
-//.word 0x4dd2f662
-//.word 0xec5f4a29
-//.word 0x9be2adea
-//.word 0xdf627b98
-//.word 0xe50e1c07
-//.word 0x2b769d62
-//// SHA512ShortMsgvector_115
-//// vector length
-//.word 0x00000390
-//// input message
-//.word 0xfe2d8ae2
-//.word 0x00e6657f
-//.word 0xdc7494af
-//.word 0x5a12b2ae
-//.word 0x940348f1
-//.word 0xf983f0ba
-//.word 0x98febbe9
-//.word 0x9c80d115
-//.word 0x126d57db
-//.word 0xf3729676
-//.word 0x5ebb5990
-//.word 0x25669658
-//.word 0x8b3851d5
-//.word 0x4c8fbe7a
-//.word 0xde98a6fa
-//.word 0xf7c20b5e
-//.word 0x4f730f54
-//.word 0xa7f912ca
-//.word 0x0ac31bbb
-//.word 0x53d17949
-//.word 0xef69aa0d
-//.word 0xe40c7bab
-//.word 0x12a871a9
-//.word 0xb90f6881
-//.word 0x3ca87af4
-//.word 0x256422a2
-//.word 0x68f4a1d8
-//.word 0xec3aa1a9
-//.word 0x47fd8000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000390
-//// expected output
-//.word 0x8025a860
-//.word 0x8df0f6a0
-//.word 0x1c34cdec
-//.word 0x012d4cb2
-//.word 0x5852e1b1
-//.word 0x00b68172
-//.word 0xfc4e86ac
-//.word 0x8b7126b6
-//.word 0x4859cb9e
-//.word 0x767a7e59
-//.word 0x060989ce
-//.word 0xdbd925af
-//.word 0xc475ca73
-//.word 0x69bd43f8
-//.word 0x5ae590e2
-//.word 0x24e036dd
-//// SHA512ShortMsgvector_116
-//// vector length
-//.word 0x00000398
-//// input message
-//.word 0xdc28484e
-//.word 0xbfd293d6
-//.word 0x2ac759d5
-//.word 0x754bdf50
-//.word 0x2423e4d4
-//.word 0x19fa7902
-//.word 0x0805134b
-//.word 0x2ce3dff7
-//.word 0x38c7556c
-//.word 0x91d810ad
-//.word 0xbad8dd21
-//.word 0x0f041296
-//.word 0xb73c2185
-//.word 0xd4646c97
-//.word 0xfc0a5b69
-//.word 0xed49ac8c
-//.word 0x7ced0bd1
-//.word 0xcfd7e3c3
-//.word 0xcca47374
-//.word 0xd189247d
-//.word 0xa6811a40
-//.word 0xb0ab0970
-//.word 0x67ed4ad4
-//.word 0x0ade2e47
-//.word 0x91e39204
-//.word 0xe398b320
-//.word 0x49714458
-//.word 0x22a1be0d
-//.word 0xd93af880
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000398
-//// expected output
-//.word 0x615115d2
-//.word 0xe8b62e34
-//.word 0x5adaa4bd
-//.word 0xb95395a3
-//.word 0xb4fe27d7
-//.word 0x1c4a111b
-//.word 0x86c18414
-//.word 0x63c5f03d
-//.word 0x6b20d164
-//.word 0xa39948ab
-//.word 0x08ae0607
-//.word 0x20d05c10
-//.word 0xf6022e5c
-//.word 0x8caf2fa3
-//.word 0xbca2e04d
-//.word 0x9c539ded
-//// SHA512ShortMsgvector_117
-//// vector length
-//.word 0x000003A0
-//// input message
-//.word 0x5af8c0f2
-//.word 0x6db4e99b
-//.word 0x47ec2e4a
-//.word 0x01a786e7
-//.word 0x7899e46d
-//.word 0x464ac337
-//.word 0xf175027b
-//.word 0x61aef314
-//.word 0x9848af84
-//.word 0x9d76ac39
-//.word 0xb9b0910f
-//.word 0xe6594817
-//.word 0x859e5597
-//.word 0x4fa16751
-//.word 0x8ed72d08
-//.word 0x8dae6b41
-//.word 0x4d744d47
-//.word 0x7974fb71
-//.word 0x9c626da7
-//.word 0x92f98123
-//.word 0x3de24b75
-//.word 0x79d8acca
-//.word 0x510a266d
-//.word 0x73c0ee8e
-//.word 0xe1424343
-//.word 0xeaf6ffcc
-//.word 0x59c86c1b
-//.word 0xecce5894
-//.word 0x072c6c11
-//.word 0x80000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000003A0
-//// expected output
-//.word 0x09da284d
-//.word 0x5b655650
-//.word 0x8be54c8a
-//.word 0xb6c97bbd
-//.word 0x472995c6
-//.word 0xbbd58591
-//.word 0x7ecdb54e
-//.word 0xa9167208
-//.word 0xdaaa070a
-//.word 0x7b2b7d8e
-//.word 0x93ce1315
-//.word 0xf0d1ef8d
-//.word 0x69667429
-//.word 0xc44dc5ee
-//.word 0x1499de57
-//.word 0xb229a398
-//// SHA512ShortMsgvector_118
-//// vector length
-//.word 0x000003A8
-//// input message
-//.word 0x49cd0ba0
-//.word 0xdf5bb3f4
-//.word 0x3f68464e
-//.word 0x3e83e9cb
-//.word 0xd5d5ee07
-//.word 0x7ffa5591
-//.word 0xe30f939c
-//.word 0xb30c93f7
-//.word 0xd454fb3f
-//.word 0xbf8bb053
-//.word 0x27a89c08
-//.word 0xdc4baf1e
-//.word 0xef502373
-//.word 0x17a40577
-//.word 0x5357f1e0
-//.word 0xd1f31d9f
-//.word 0x0f0d9812
-//.word 0x4019d47b
-//.word 0xf18363b1
-//.word 0xecfbfe15
-//.word 0x5c10cbc8
-//.word 0x3300e01b
-//.word 0xc9ce0347
-//.word 0xc596b35f
-//.word 0x411e6d82
-//.word 0x29ad2855
-//.word 0xe42022b0
-//.word 0x373ade98
-//.word 0x663c6d6e
-//.word 0x9c800000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000003A8
-//// expected output
-//.word 0x30cbf067
-//.word 0x9a97c871
-//.word 0x574d2fc0
-//.word 0x5d7aa760
-//.word 0xc6bc8a86
-//.word 0x4b7d246c
-//.word 0x39b9e812
-//.word 0xf9b7ff7b
-//.word 0x4ef5197d
-//.word 0xd5b69493
-//.word 0x306688b8
-//.word 0x564de1ad
-//.word 0x47d75505
-//.word 0xc913ba6a
-//.word 0x78788f8c
-//.word 0xaf5788bd
-//// SHA512ShortMsgvector_119
-//// vector length
-//.word 0x000003B0
-//// input message
-//.word 0xa8a37dfc
-//.word 0x083ad2f4
-//.word 0x7fff4687
-//.word 0x38bf8b72
-//.word 0x8eb7f190
-//.word 0x7e427fa1
-//.word 0x5cb4424b
-//.word 0xc685e55e
-//.word 0xd7b2825c
-//.word 0x9c60b839
-//.word 0xccc2fe5f
-//.word 0xb33e36f5
-//.word 0x70cb8661
-//.word 0x609e630b
-//.word 0xda05ee64
-//.word 0x1d938428
-//.word 0x867d90e0
-//.word 0x0744a4aa
-//.word 0xd494c93c
-//.word 0x5f6d1327
-//.word 0x87807859
-//.word 0x0cdce1e6
-//.word 0x47c98208
-//.word 0x18f46764
-//.word 0x1fcd508e
-//.word 0x2f2ebfd0
-//.word 0xff3d4f27
-//.word 0x2393478f
-//.word 0x3b9e6f80
-//.word 0x6b438000
-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000003B0
-//// expected output
-//.word 0x8e1c9172
-//.word 0x9be8eb40
-//.word 0x226f6c58
-//.word 0xa029380e
-//.word 0xf7edb9dc
-//.word 0x166a5c3c
-//.word 0xdbcefe90
-//.word 0xbd30d85c
-//.word 0xb7c4b248
-//.word 0xe66abf0a
-//.word 0x3a4c8422
-//.word 0x81299bef
-//.word 0x6db88858
-//.word 0xd9e5ab52
-//.word 0x44f70b79
-//.word 0x69e1c072
-//// SHA512ShortMsgvector_120
-//// vector length
-//.word 0x000003B8
-//// input message
-//.word 0x36af1759
-//.word 0x5494ef79
-//.word 0x3c42f484
-//.word 0x10246df0
-//.word 0x7d05936a
-//.word 0x918afe74
-//.word 0xcd005e53
-//.word 0x7c586b28
-//.word 0x43701f5d
-//.word 0xf8952242
-//.word 0xb74586f8
-//.word 0x3339b48f
-//.word 0x4ba3a66b
-//.word 0xdeb457ec
-//.word 0xdf61784e
-//.word 0xac6765cd
-//.word 0x9b8c570d
-//.word 0xd628dbba
-//.word 0x6ae5836b
-//.word 0x9ac3dbcd
-//.word 0x795f9efd
-//.word 0xb8742a35
-//.word 0xbca232ab
-//.word 0xf36eb3b6
-//.word 0x698b2933
-//.word 0x96580227
-//.word 0x7ba953a6
-//.word 0xedcacaf3
-//.word 0x30c1e4e8
-//.word 0xc7d45f80
-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000003B8
-//// expected output
-//.word 0x158bfc34
-//.word 0x8a30b4fa
-//.word 0xbbe355a7
-//.word 0xd44bdc21
-//.word 0x22a4c850
-//.word 0x444c03f2
-//.word 0x89003ce0
-//.word 0x1bfc1ebf
-//.word 0x3ecc0feb
-//.word 0xb6a8ff52
-//.word 0x3d25db76
-//.word 0x81b05bdc
-//.word 0xe048d119
-//.word 0x43ab476c
-//.word 0x1967cf65
-//.word 0x56c4a120
-//// SHA512ShortMsgvector_121
-//// vector length
-//.word 0x000003C0
-//// input message
-//.word 0x42d66edc
-//.word 0x5f22e0c1
-//.word 0x3c25504c
-//.word 0x5101a5d1
-//.word 0x72d2db72
-//.word 0x09e461ef
-//.word 0xa323c0bf
-//.word 0xaed27e5f
-//.word 0x808042ea
-//.word 0x9c3838ea
-//.word 0x31f9b76d
-//.word 0xe465225c
-//.word 0xcfbd0c09
-//.word 0xca0d9f07
-//.word 0xe9a43e3e
-//.word 0x46c7693e
-//.word 0x00a7e1d4
-//.word 0x83900ddb
-//.word 0x0a629d55
-//.word 0x63456dbb
-//.word 0xf299ac91
-//.word 0xf92c3d3c
-//.word 0x17b05d18
-//.word 0x0e6c87c6
-//.word 0xc93194c3
-//.word 0x9d90273f
-//.word 0xcf4a482c
-//.word 0x56084f95
-//.word 0xe34c0431
-//.word 0x1fa80438
-//.word 0x80000000
-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000003C0
-//// expected output
-//.word 0x061afb11
-//.word 0x9a3c6087
-//.word 0x6e04c10f
-//.word 0x12ad0f4b
-//.word 0x977593dc
-//.word 0x5a2d2109
-//.word 0x6a57e7d3
-//.word 0xf7d4d44f
-//.word 0xdef934b2
-//.word 0xc17d7530
-//.word 0x674e4f4a
-//.word 0x1c176dbd
-//.word 0xcc54811a
-//.word 0x22e1b871
-//.word 0x2e4192fc
-//.word 0x2d4bf8e8
-//// SHA512ShortMsgvector_122
-//// vector length
-//.word 0x000003C8
-//// input message
-//.word 0xf91bb2e1
-//.word 0xa9c4cd96
-//.word 0xbf250426
-//.word 0xb3a6afd9
-//.word 0xb87ac51e
-//.word 0x93254d2d
-//.word 0xae3b16ec
-//.word 0x686ba80f
-//.word 0xb0bd7a84
-//.word 0xd218660e
-//.word 0x90075930
-//.word 0x75bc4f4c
-//.word 0x66567f0c
-//.word 0x7a5fd201
-//.word 0x0c999a8a
-//.word 0x0efa81f8
-//.word 0x9ff5bfef
-//.word 0xe0fb910f
-//.word 0x0442e6d4
-//.word 0xa7c55bbb
-//.word 0x618c69a7
-//.word 0x9a2ddd82
-//.word 0xa0938927
-//.word 0xf6fe3a80
-//.word 0xf04beaeb
-//.word 0x7c7636e3
-//.word 0x435d12dc
-//.word 0xf1c6bb6e
-//.word 0xd0a4edb6
-//.word 0x9c9657fa
-//.word 0x93800000
-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000003C8
-//// expected output
-//.word 0x6e692c8c
-//.word 0x694ee0a3
-//.word 0x565f37a2
-//.word 0x99e0006b
-//.word 0x85ab4a82
-//.word 0x1b20e767
-//.word 0x98220229
-//.word 0xf656efc6
-//.word 0xa20211a4
-//.word 0xe7e4ed77
-//.word 0xfacde0d7
-//.word 0x0e4d5d95
-//.word 0xbc8ed1d7
-//.word 0xa56d8df1
-//.word 0x446d562f
-//.word 0x044b344c
-//// SHA512ShortMsgvector_123
-//// vector length
-//.word 0x000003D0
-//// input message
-//.word 0xd1eb961c
-//.word 0xa6a8f67c
-//.word 0x49b61e4d
-//.word 0x3ceaa2a1
-//.word 0xde6f0ea9
-//.word 0x27b132bf
-//.word 0x987abdaa
-//.word 0x725b0e1e
-//.word 0x274e4683
-//.word 0x0e99a2f7
-//.word 0x5af60896
-//.word 0x4df0dff9
-//.word 0xa99024fc
-//.word 0x6839bac5
-//.word 0xacd10202
-//.word 0xf921ac71
-//.word 0xa27fcda6
-//.word 0x81aa3109
-//.word 0xebf5f21e
-//.word 0xe3a84909
-//.word 0x8ea3a551
-//.word 0xe844fae4
-//.word 0xb48b5c5b
-//.word 0xb97ccc80
-//.word 0x2bc5520d
-//.word 0x68a14cb7
-//.word 0xe5fc056b
-//.word 0x67d889d8
-//.word 0x76efb82d
-//.word 0x0e9a9a24
-//.word 0x99f18000
-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000003D0
-//// expected output
-//.word 0x39b2c76e
-//.word 0xc207120d
-//.word 0xe4b320c7
-//.word 0xfe069e60
-//.word 0x2c9c38f2
-//.word 0x57596da7
-//.word 0x369395e8
-//.word 0x7eb64b3a
-//.word 0xcff988c1
-//.word 0x839ac269
-//.word 0xd5012c09
-//.word 0x3f9edd4b
-//.word 0x7cabf13b
-//.word 0xdea7d42e
-//.word 0x969ab108
-//.word 0x269c6ab0
-//// SHA512ShortMsgvector_124
-//// vector length
-//.word 0x000003D8
-//// input message
-//.word 0xadf22632
-//.word 0x00f37688
-//.word 0x6ba7b6f5
-//.word 0xe4411d5f
-//.word 0x07f7d9d1
-//.word 0x01590c73
-//.word 0xace114ba
-//.word 0xfbcb0fdc
-//.word 0x99269e87
-//.word 0xcd2cead2
-//.word 0xa1cfe574
-//.word 0x4394d333
-//.word 0xaba408a0
-//.word 0x7e21f302
-//.word 0x33b65b90
-//.word 0x7472e9e3
-//.word 0xc7d6e7aa
-//.word 0x6d2c47a0
-//.word 0x8a1be7bb
-//.word 0x877913a6
-//.word 0xb5604c72
-//.word 0x33844789
-//.word 0x11c339e3
-//.word 0xb5fe527c
-//.word 0x7e288705
-//.word 0xa89c95d9
-//.word 0x70b44334
-//.word 0x7897e79f
-//.word 0x6c522baf
-//.word 0xe62b11ef
-//.word 0x8f313580
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000003D8
-//// expected output
-//.word 0x3c23d2d8
-//.word 0xcf4db6ac
-//.word 0x6a42e272
-//.word 0x08180f37
-//.word 0x668bef5e
-//.word 0xe0a3f879
-//.word 0x483c8e60
-//.word 0x4e7f4258
-//.word 0x3f202037
-//.word 0xb8d242c0
-//.word 0x4a87345b
-//.word 0x8be6dc8b
-//.word 0x121d6484
-//.word 0xb9edad0d
-//.word 0x73c894c1
-//.word 0x288f5cae
-//// SHA512ShortMsgvector_125
-//// vector length
-//.word 0x000003E0
-//// input message
-//.word 0x18e75b47
-//.word 0xd898ac62
-//.word 0x9c48e80d
-//.word 0xbfb75dae
-//.word 0x1e1700b7
-//.word 0x71165ecc
-//.word 0xdb18d628
-//.word 0xbfc4063d
-//.word 0xd6c3839a
-//.word 0x7ec4cd12
-//.word 0x55c4821b
-//.word 0x078cd174
-//.word 0x647b320b
-//.word 0xb685541d
-//.word 0x517c579f
-//.word 0x6b8e3cdd
-//.word 0x2e109a61
-//.word 0x0c7a9216
-//.word 0x53b204ad
-//.word 0x018d0340
-//.word 0xd9938735
-//.word 0xb6026266
-//.word 0x2016767e
-//.word 0x1d8824a6
-//.word 0x49540862
-//.word 0x29c0e3b5
-//.word 0xbd9ad88c
-//.word 0x54c1dc5a
-//.word 0xa4e768ff
-//.word 0x1a9470ee
-//.word 0x6f6e998f
-//.word 0x80000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000003E0
-//// expected output
-//.word 0x01c756b7
-//.word 0xc20b5f95
-//.word 0xfd2b079a
-//.word 0xb6a50f28
-//.word 0xb946fb16
-//.word 0x266b07c6
-//.word 0x060945dc
-//.word 0x4fe9e0d2
-//.word 0x79c5b150
-//.word 0x5b9ec7d8
-//.word 0xf8f3c9eb
-//.word 0xf0c5ee93
-//.word 0x65aec08c
-//.word 0xf278d65b
-//.word 0x64daeccc
-//.word 0x19d3cbf4
-//// SHA512ShortMsgvector_126
-//// vector length
-//.word 0x000003E8
-//// input message
-//.word 0xc2963342
-//.word 0xcfaa88cc
-//.word 0xd102a258
-//.word 0xe6d629f6
-//.word 0xb0d367dd
-//.word 0x55116502
-//.word 0xca4451ea
-//.word 0x523623bc
-//.word 0x4175819a
-//.word 0x0648df31
-//.word 0x68e8ea8f
-//.word 0x10ed2735
-//.word 0x4807d76e
-//.word 0x02ee1fdf
-//.word 0x1c9c655e
-//.word 0xe2b9fd08
-//.word 0xd557058d
-//.word 0xabdf8dcf
-//.word 0x964bfcac
-//.word 0xc996ae17
-//.word 0x3971e26e
-//.word 0xa038d407
-//.word 0xc824260d
-//.word 0x06c2848a
-//.word 0x04a488c4
-//.word 0xc456dbcd
-//.word 0xe2939e56
-//.word 0x1ab908c4
-//.word 0x097b5086
-//.word 0x38d6cda5
-//.word 0x56465c9c
-//.word 0xc5800000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000003E8
-//// expected output
-//.word 0xa4d2f593
-//.word 0x93a5fea6
-//.word 0x12c3c745
-//.word 0xf4bb9f41
-//.word 0xaaf3a3ce
-//.word 0x1679aa8a
-//.word 0xfc1a62ba
-//.word 0xa4ed4528
-//.word 0x19418c8a
-//.word 0xe1a1e658
-//.word 0x75797669
-//.word 0x2390fc43
-//.word 0xd4decf7d
-//.word 0x855cd8b4
-//.word 0x98b6dc60
-//.word 0xcae05a90
-//// SHA512ShortMsgvector_127
-//// vector length
-//.word 0x000003F0
-//// input message
-//.word 0x85360c3d
-//.word 0x4257d987
-//.word 0x8e2f5c16
-//.word 0xd3cd7d07
-//.word 0x47df3d23
-//.word 0x1e1a8f63
-//.word 0xfddc69b3
-//.word 0xb1101af7
-//.word 0x2153de4c
-//.word 0x8154b090
-//.word 0xc9815f24
-//.word 0x66e0e4f0
-//.word 0x2f3af3a8
-//.word 0x9a7fd04e
-//.word 0x306664f9
-//.word 0x3e5490d4
-//.word 0xce7fc169
-//.word 0xd553c520
-//.word 0xae15dd02
-//.word 0xc7c613c3
-//.word 0x9b4acd00
-//.word 0xe0c9a3c5
-//.word 0x01566e52
-//.word 0xcecea11f
-//.word 0x7303dd1d
-//.word 0xa61abf3f
-//.word 0x2532fd39
-//.word 0x6047b188
-//.word 0x7255f4b2
-//.word 0x56c0afcf
-//.word 0x58f3ae48
-//.word 0xc9478000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000003F0
-//// expected output
-//.word 0xe8352ddc
-//.word 0xac59e377
-//.word 0xea0f9c32
-//.word 0xbbb43dfd
-//.word 0x1b6c829f
-//.word 0xad195424
-//.word 0x0c41b7c4
-//.word 0x5b0b09db
-//.word 0x11064b64
-//.word 0xe2442a96
-//.word 0xf6530aac
-//.word 0x2c4abf3b
-//.word 0xeb1eae77
-//.word 0xf2bce4ef
-//.word 0xe88fee1a
-//.word 0x70cf5423
-//// SHA512ShortMsgvector_128
-//// vector length
-//.word 0x000003F8
-//// input message
-//.word 0xc13e6ca3
-//.word 0xabb893aa
-//.word 0x5f82c4a8
-//.word 0xef754460
-//.word 0x628af6b7
-//.word 0x5af02168
-//.word 0xf45b72f8
-//.word 0xf09e45ed
-//.word 0x127c203b
-//.word 0xc7bb80ff
-//.word 0x0c7bd96f
-//.word 0x8cc6d811
-//.word 0x0868eb2c
-//.word 0xfc01037d
-//.word 0x8058992a
-//.word 0x6cf2effc
-//.word 0xbfe498c8
-//.word 0x42e53a2e
-//.word 0x68a79386
-//.word 0x7968ba18
-//.word 0xefc4a78b
-//.word 0x21cdf6a1
-//.word 0x1e5de821
-//.word 0xdcabab14
-//.word 0x921ddb33
-//.word 0x625d48a1
-//.word 0x3baffad6
-//.word 0xfe8272db
-//.word 0xdf4433bd
-//.word 0x0f7b813c
-//.word 0x981269c3
-//.word 0x88f00180
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000003F8
-//// expected output
-//.word 0x6e56f77f
-//.word 0x6883d0bd
-//.word 0x4face8b8
-//.word 0xd557f144
-//.word 0x661989f6
-//.word 0x6d51b1fe
-//.word 0x4b8fc712
-//.word 0x4d66d9d2
-//.word 0x0218616f
-//.word 0xea1bcf86
-//.word 0xc08d63bf
-//.word 0x8f2f2184
-//.word 0x5a3e5190
-//.word 0x83b937e7
-//.word 0x0aa7c358
-//.word 0x310b5a7c
-//// SHA512ShortMsgvector_129
-//// vector length
-//.word 0x00000400
-//// input message
-//.word 0xfd2203e4
-//.word 0x67574e83
-//.word 0x4ab07c90
-//.word 0x97ae1645
-//.word 0x32f24be1
-//.word 0xeb5d88f1
-//.word 0xaf7748ce
-//.word 0xff0d2c67
-//.word 0xa21f4e40
-//.word 0x97f9d3bb
-//.word 0x4e9fbf97
-//.word 0x186e0db6
-//.word 0xdb010023
-//.word 0x0a52b453
-//.word 0xd421f8ab
-//.word 0x9c9a6043
-//.word 0xaa3295ea
-//.word 0x20d2f06a
-//.word 0x2f37470d
-//.word 0x8a99075f
-//.word 0x1b8a8336
-//.word 0xf6228cf0
-//.word 0x8b5942fc
-//.word 0x1fb4299c
-//.word 0x7d2480e8
-//.word 0xe82bce17
-//.word 0x5540bdfa
-//.word 0xd7752bc9
-//.word 0x5b577f22
-//.word 0x9515394f
-//.word 0x3ae5cec8
-//.word 0x70a4b2f8
-//.word 0x80000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000400
-//// expected output
-//.word 0xa21b1077
-//.word 0xd52b27ac
-//.word 0x545af63b
-//.word 0x32746c6e
-//.word 0x3c51cb0c
-//.word 0xb9f281eb
-//.word 0x9f3580a6
-//.word 0xd4996d5c
-//.word 0x9917d2a6
-//.word 0xe484627a
-//.word 0x9d5a06fa
-//.word 0x1b25327a
-//.word 0x9d710e02
-//.word 0x7387fc3e
-//.word 0x07d7c4d1
-//.word 0x4c6086cc
-//SHA512LongMsg:
-//// SHA512LongMsgvector_1
-//// vector length
-//.word 0x00000718
-//// input message
-//.word 0x4f056009
-//.word 0x50664d51
-//.word 0x90a2ebc2
-//.word 0x9c9edb89
-//.word 0xc20079a4
-//.word 0xd3e6bc3b
-//.word 0x27d75e34
-//.word 0xe2fa3d02
-//.word 0x768502bd
-//.word 0x69790078
-//.word 0x598d5fcf
-//.word 0x3d6779bf
-//.word 0xed1284bb
-//.word 0xe5ad72fb
-//.word 0x45601518
-//.word 0x1d9587d6
-//.word 0xe864c940
-//.word 0x564eaafb
-//.word 0x4f2fead4
-//.word 0x346ea09b
-//.word 0x6877d934
-//.word 0x0f6b82eb
-//.word 0x15158808
-//.word 0x72213da3
-//.word 0xad88feba
-//.word 0x9f4f1381
-//.word 0x7a71d6f9
-//.word 0x0a1a17c4
-//.word 0x3a15c038
-//.word 0xd988b5b2
-//.word 0x9edffe2d
-//.word 0x6a062813
-//.word 0xcedbe852
-//.word 0xcde302b3
-//.word 0xe33b6968
-//.word 0x46d2a8e3
-//.word 0x6bd680ef
-//.word 0xcc6cd3f9
-//.word 0xe9a4c1ae
-//.word 0x8cac10cc
-//.word 0x5244d131
-//.word 0x67714039
-//.word 0x9176ed46
-//.word 0x700019a0
-//.word 0x04a16380
-//.word 0x6f7fa467
-//.word 0xfc4e17b4
-//.word 0x617bbd76
-//.word 0x41aaff7f
-//.word 0xf56396ba
-//.word 0x8c08a8be
-//.word 0x100b33a2
-//.word 0x0b5daf13
-//.word 0x4a2aefa5
-//.word 0xe1c34967
-//.word 0x70dcf6ba
-//.word 0xa4f7bb80
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000718
-//// expected output
-//.word 0xa9db490c
-//.word 0x708cc725
-//.word 0x48d78635
-//.word 0xaa7da79b
-//.word 0xb253f945
-//.word 0xd710e5cb
-//.word 0x677a474e
-//.word 0xfc7c65a2
-//.word 0xaab45bc7
-//.word 0xca1113c8
-//.word 0xce0f3c32
-//.word 0xe1399de9
-//.word 0xc459535e
-//.word 0x8816521a
-//.word 0xb714b2a6
-//.word 0xcd200525
-//// SHA512LongMsgvector_2
-//// vector length
-//.word 0x00000A30
-//// input message
-//.word 0xd5e378ae
-//.word 0x9fc2648f
-//.word 0x4a13bbec
-//.word 0x4b0935af
-//.word 0xb4f822f5
-//.word 0xfe0d5063
-//.word 0x053d2fbd
-//.word 0x547b33b4
-//.word 0xa32e7a00
-//.word 0x9ee2afaf
-//.word 0xe83d2ebd
-//.word 0x603568e4
-//.word 0xa38189b5
-//.word 0xd24d59e8
-//.word 0x953260f1
-//.word 0x5f654ed4
-//.word 0xf42f9a39
-//.word 0x299d68c3
-//.word 0xeb78b09e
-//.word 0x83779d57
-//.word 0x18b433f1
-//.word 0x765d3535
-//.word 0x0eac4649
-//.word 0x3d194e84
-//.word 0xd1ce1f81
-//.word 0xc95b5972
-//.word 0x5cab8ab7
-//.word 0x3d369ab0
-//.word 0x1e7967cf
-//.word 0x73a3acf1
-//.word 0x789227ee
-//.word 0x75fdfb6e
-//.word 0x40f353ff
-//.word 0x04844865
-//.word 0x42be0531
-//.word 0x15db2896
-//.word 0xbab86c77
-//.word 0x4f8985c4
-//.word 0xdbcc4c07
-//.word 0x8f7b1c3a
-//.word 0x4c867cdc
-//.word 0x6580fe44
-//.word 0xa5986734
-//.word 0x94cc0fb1
-//.word 0xf6598b12
-//.word 0x95768a58
-//.word 0x4041fdbd
-//.word 0x14fa7b90
-//.word 0xfa6fe33f
-//.word 0x71b743b6
-//.word 0x8e23f8e7
-//.word 0x407217aa
-//.word 0xd9440cc8
-//.word 0xcad28152
-//.word 0xaedb8238
-//.word 0x8be2de16
-//.word 0x5496d051
-//.word 0xb292de63
-//.word 0x03460273
-//.word 0xa4350829
-//.word 0x6b6237c0
-//.word 0x7804335d
-//.word 0x2e81229f
-//.word 0x7c9a0e77
-//.word 0x61e38a3a
-//.word 0xaf7799f4
-//.word 0x0fe9cb00
-//.word 0x457ea9d5
-//.word 0xb5995323
-//.word 0x2676681f
-//.word 0xc71b261a
-//.word 0x6f8cd359
-//.word 0x293f5b21
-//.word 0xf0cf3a11
-//.word 0xb7f49cb5
-//.word 0xadb3c357
-//.word 0xbed2aa18
-//.word 0x5d8fe840
-//.word 0x8192d6d3
-//.word 0xed1ff465
-//.word 0xb590892e
-//.word 0xfe038000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000A30
-//// expected output
-//.word 0xa70c75b9
-//.word 0xb1f0ac2e
-//.word 0xd2c27977
-//.word 0x63ac9a66
-//.word 0x01d95f46
-//.word 0x889b00fc
-//.word 0x3ddae4d0
-//.word 0xac692375
-//.word 0x0a108d79
-//.word 0xeb764e77
-//.word 0xac07b7cb
-//.word 0x5c01cb4b
-//.word 0x3747dcf6
-//.word 0x9ba3b35c
-//.word 0x51fb995d
-//.word 0xa2632e70
-//// SHA512LongMsgvector_3
-//// vector length
-//.word 0x00000D48
-//// input message
-//.word 0x4f7a5618
-//.word 0x870945b8
-//.word 0x9f194e31
-//.word 0xb1aa802c
-//.word 0x5350326d
-//.word 0xc691df58
-//.word 0x708e34b4
-//.word 0x8ce666b0
-//.word 0x21d7c923
-//.word 0x30a69f18
-//.word 0x32412d8a
-//.word 0xc224156c
-//.word 0x9679dfed
-//.word 0xb383d9f9
-//.word 0xe13c2103
-//.word 0x5d3d0002
-//.word 0xcfdf79b9
-//.word 0x7ba0223c
-//.word 0xbbc833b0
-//.word 0xad4cdd52
-//.word 0x29f2ddbb
-//.word 0xf6b65062
-//.word 0x3d6cc962
-//.word 0x3da8a17d
-//.word 0x41db8e61
-//.word 0xcfbe772b
-//.word 0x23f4872a
-//.word 0xdceb81e5
-//.word 0xf403535f
-//.word 0xf5f2ed99
-//.word 0x6a675359
-//.word 0x94edf12a
-//.word 0x5f1230a4
-//.word 0x94c946ed
-//.word 0x500e5280
-//.word 0xb5c8a82d
-//.word 0xdff36961
-//.word 0x1afe58a8
-//.word 0x5272e870
-//.word 0xcbd59a10
-//.word 0x12ce8509
-//.word 0x338a368b
-//.word 0x2c5dbb3b
-//.word 0xa2adfb33
-//.word 0xd30c494a
-//.word 0xcca43896
-//.word 0xdbd8b030
-//.word 0x48284137
-//.word 0x4055b818
-//.word 0x12c6f00c
-//.word 0x9e2bebe2
-//.word 0x096021fe
-//.word 0xb69418a2
-//.word 0x72aa356c
-//.word 0xefdfd220
-//.word 0x74ae91a8
-//.word 0xd2f1ef59
-//.word 0x9a481c78
-//.word 0x8dbe0afd
-//.word 0x54aac396
-//.word 0x72d401ef
-//.word 0x76d9f831
-//.word 0x75d177c9
-//.word 0xb72e2f6a
-//.word 0xb1e75255
-//.word 0x33d761d8
-//.word 0xe3603f14
-//.word 0xea538904
-//.word 0xed142abb
-//.word 0x3ff929ed
-//.word 0x55f4c6b1
-//.word 0x7a72c685
-//.word 0xc3820b93
-//.word 0x463a6733
-//.word 0x8756b2b0
-//.word 0x33231a4f
-//.word 0x119cbb8d
-//.word 0x35d270a9
-//.word 0x7791e862
-//.word 0x2340fc02
-//.word 0xf2093f9b
-//.word 0x393ad791
-//.word 0x61eb8c58
-//.word 0x97e21f7f
-//.word 0xc4b3ddee
-//.word 0xc02b736c
-//.word 0xc3ef0464
-//.word 0x1c6179e8
-//.word 0x25c319f6
-//.word 0x769f59fa
-//.word 0x5966f595
-//.word 0x7e573f9d
-//.word 0xf0a2b765
-//.word 0x48cedd3e
-//.word 0x2158433d
-//.word 0xcb9de63f
-//.word 0x44f9be2b
-//.word 0x63319477
-//.word 0x570e14ee
-//.word 0x504b23b0
-//.word 0x7cb2737a
-//.word 0x35815427
-//.word 0x7912cd77
-//.word 0x9abbeb10
-//.word 0x36f459c2
-//.word 0x6ab7310f
-//.word 0x43800000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000D48
-//// expected output
-//.word 0x713d5c26
-//.word 0xde17e144
-//.word 0x0a36aab9
-//.word 0x3f7cd811
-//.word 0x1cd62fd8
-//.word 0xbea5099b
-//.word 0x2b6bf93e
-//.word 0x470e1eae
-//.word 0xab8b925c
-//.word 0x646e9e67
-//.word 0xce01b03b
-//.word 0x33d2b500
-//.word 0xb9400e59
-//.word 0xf0ecdfb0
-//.word 0x0dd7ddcd
-//.word 0x230cc837
-//// SHA512LongMsgvector_4
-//// vector length
-//.word 0x00001060
-//// input message
-//.word 0x5e0e8441
-//.word 0x9c02ddda
-//.word 0x289aa126
-//.word 0xbdb40a06
-//.word 0x0464aa58
-//.word 0xb88bad27
-//.word 0x08ab5f1e
-//.word 0x3df9ee43
-//.word 0x9cb470e2
-//.word 0x8eb627c6
-//.word 0xfe4904af
-//.word 0x033b6b01
-//.word 0xbf3536ba
-//.word 0x8748fca6
-//.word 0x43c993d6
-//.word 0x185fd34e
-//.word 0x455a9dfe
-//.word 0x4b461cf4
-//.word 0x51c04bcf
-//.word 0xc689b877
-//.word 0x48d9870b
-//.word 0xc5f6b91b
-//.word 0xe004af18
-//.word 0x961fe908
-//.word 0x21a7147e
-//.word 0x1cdb44ca
-//.word 0xe9aa7e6d
-//.word 0x50c579d0
-//.word 0x68f9a535
-//.word 0xbbbc6ded
-//.word 0xa506b9cb
-//.word 0xfd62b8da
-//.word 0xf744dc4b
-//.word 0x499d26b1
-//.word 0x8dada371
-//.word 0xe7183773
-//.word 0xe73d991e
-//.word 0xb1c39f84
-//.word 0x5b74bcd9
-//.word 0x964fc72a
-//.word 0x91d8fd4b
-//.word 0x1ab34a12
-//.word 0x0771c4c2
-//.word 0xd4aa78ca
-//.word 0x8d4c6ab0
-//.word 0xee32d748
-//.word 0xcaf9bd29
-//.word 0xa90f9e61
-//.word 0xb50c8068
-//.word 0xd7463853
-//.word 0x1d9fe84a
-//.word 0x5fa2c73c
-//.word 0x22cf20d1
-//.word 0xbc329ea1
-//.word 0xb93bc6a3
-//.word 0x7ec9c5e8
-//.word 0x2c886c89
-//.word 0xc77d79de
-//.word 0x98df18f0
-//.word 0xcf29a931
-//.word 0x6d6dc46b
-//.word 0x61eb7af7
-//.word 0xf1e2de2f
-//.word 0x5ca6c525
-//.word 0xbef3c996
-//.word 0x33819419
-//.word 0x3fd85b9c
-//.word 0x6e66a811
-//.word 0x37cf5d65
-//.word 0x2684f6b2
-//.word 0x3b970eb5
-//.word 0x8dce2482
-//.word 0x32f6a076
-//.word 0x6379116e
-//.word 0xdc33b936
-//.word 0x82824b45
-//.word 0x489cf3a7
-//.word 0x5326973a
-//.word 0x5d025d1d
-//.word 0x57686d66
-//.word 0x5238f813
-//.word 0x9f8e7944
-//.word 0x35973aa7
-//.word 0x54a41a33
-//.word 0x687d8f19
-//.word 0x30f8e7f7
-//.word 0x1fcad34f
-//.word 0x039c2539
-//.word 0xe462d954
-//.word 0x2fe85202
-//.word 0x14ade7d5
-//.word 0x2cf59e44
-//.word 0x5f1a37a3
-//.word 0x05236d52
-//.word 0x4b977834
-//.word 0xd894d662
-//.word 0xb11b4b21
-//.word 0x5aae2712
-//.word 0x3f1dc7a9
-//.word 0x529d5ee0
-//.word 0xf41af62d
-//.word 0x19ceb1b1
-//.word 0xa71355b2
-//.word 0x2075074b
-//.word 0x810c5762
-//.word 0x6a097ddb
-//.word 0x7e8ee20b
-//.word 0x0dc3e370
-//.word 0xf126d19f
-//.word 0xb5223c7d
-//.word 0xfde471b2
-//.word 0x216a415b
-//.word 0x1cdc04ff
-//.word 0xa520dec5
-//.word 0x9ba941e4
-//.word 0xa68fb35a
-//.word 0x1ce5d2e1
-//.word 0x2147951f
-//.word 0x13b2d41d
-//.word 0x25980bfa
-//.word 0x49345be1
-//.word 0x541cd138
-//.word 0x5c15eb1a
-//.word 0x652a5808
-//.word 0x3d0000db
-//.word 0xa56444fd
-//.word 0xb12687d9
-//.word 0x722aed90
-//.word 0xd2bc62ee
-//.word 0xbe24df9c
-//.word 0x8b7ae897
-//.word 0x80000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00001060
-//// expected output
-//.word 0xd4a3b38f
-//.word 0x18b048e6
-//.word 0x1686c215
-//.word 0x9c666469
-//.word 0xce9a9400
-//.word 0x632fd40a
-//.word 0xc1d6ed33
-//.word 0x162b921b
-//.word 0x95ac2623
-//.word 0x8af9fa00
-//.word 0xa4314a60
-//.word 0x46e1733f
-//.word 0xd4fadc60
-//.word 0x33f3ac33
-//.word 0xd2b8c202
-//.word 0xafa5f02f
-//// SHA512LongMsgvector_5
-//// vector length
-//.word 0x00001378
-//// input message
-//.word 0xf516561e
-//.word 0xdc530bf7
-//.word 0xaa1a6330
-//.word 0x7d62812f
-//.word 0xb560dd5d
-//.word 0xa6629729
-//.word 0x8ffb0c4f
-//.word 0xd060a85a
-//.word 0x5712fb67
-//.word 0x5cbd0e2d
-//.word 0x4e60f73a
-//.word 0x0dafab7f
-//.word 0x59b6140f
-//.word 0x8bbe6324
-//.word 0x8274a863
-//.word 0xe1489f61
-//.word 0x7814cd65
-//.word 0xfffecc70
-//.word 0x0a9fe47a
-//.word 0x3965dbff
-//.word 0xaf350dba
-//.word 0xc655bfb1
-//.word 0x018ab071
-//.word 0x437df19b
-//.word 0x3e63f79f
-//.word 0x2dddefc8
-//.word 0xc61d5179
-//.word 0x6a4bb8b6
-//.word 0xa027f1e5
-//.word 0xc1ef51d6
-//.word 0xf5834c02
-//.word 0x5dc74410
-//.word 0x92499f9e
-//.word 0x4f241c3d
-//.word 0x6a2467bd
-//.word 0x092aebac
-//.word 0x12d2e719
-//.word 0xe354c49d
-//.word 0x44a8a69d
-//.word 0x99ee41c9
-//.word 0x5d0ceee8
-//.word 0xcb99fdd8
-//.word 0xdefa4dd0
-//.word 0x7cca1be9
-//.word 0xee8018dd
-//.word 0x944bbe0e
-//.word 0xd741e3ca
-//.word 0x5eb98fcd
-//.word 0x85f50b07
-//.word 0x0b053aa0
-//.word 0x0ae72c3a
-//.word 0x2df3f176
-//.word 0x1d77abb9
-//.word 0x3c9ee730
-//.word 0x96962e11
-//.word 0x15f1d624
-//.word 0xf44c1e83
-//.word 0x752f7b9e
-//.word 0xd7352c81
-//.word 0x826d145a
-//.word 0x86ffc935
-//.word 0x4313e90b
-//.word 0x69eeadfb
-//.word 0x245ec0d7
-//.word 0x905951e2
-//.word 0x73e167d8
-//.word 0x2b2a742f
-//.word 0xe5ff2e9d
-//.word 0x10629ada
-//.word 0x127369a7
-//.word 0x3993880f
-//.word 0xf4c8f3ed
-//.word 0x4363caae
-//.word 0x6ce1a658
-//.word 0xf0102dcb
-//.word 0xbd73e448
-//.word 0xa5e6452f
-//.word 0x0f85120d
-//.word 0xeccbe8d5
-//.word 0xedf7176e
-//.word 0xf3b4b16e
-//.word 0xc8f8e126
-//.word 0x0c2d7ede
-//.word 0x728fe061
-//.word 0x2cd5f3bd
-//.word 0xa3138944
-//.word 0x6cdff5d6
-//.word 0x77b3d563
-//.word 0x8a922fab
-//.word 0xeeeec048
-//.word 0x69ca90ef
-//.word 0x6c1ccaf3
-//.word 0x8c75cb0a
-//.word 0x36e37954
-//.word 0x9f17d699
-//.word 0xfbc3d5d3
-//.word 0xef466cec
-//.word 0x488beac8
-//.word 0xed2e8b86
-//.word 0x12e14903
-//.word 0xaf0ff6a0
-//.word 0x31bf8846
-//.word 0x6fbab4a7
-//.word 0xdff0bec6
-//.word 0x0a188fb9
-//.word 0x3d9708ad
-//.word 0x82a3962c
-//.word 0xcea8069b
-//.word 0x7cea9b07
-//.word 0xfa6d5e21
-//.word 0xc312b686
-//.word 0x8d023844
-//.word 0xc34fc09a
-//.word 0x35d9c100
-//.word 0x0f6fd967
-//.word 0x0737a9c2
-//.word 0xdb50e3c5
-//.word 0xfbb5a4ed
-//.word 0x826505c0
-//.word 0x6bc1ed56
-//.word 0x02352918
-//.word 0x981abec8
-//.word 0x7bdb7dc2
-//.word 0x2657d981
-//.word 0xb487f664
-//.word 0x9b6102b2
-//.word 0x96fcc8dd
-//.word 0xe3f48203
-//.word 0xaf10efba
-//.word 0xcf22a60d
-//.word 0xb02faac2
-//.word 0x91d03edf
-//.word 0xefd8fb6c
-//.word 0x41371f79
-//.word 0xe61f2863
-//.word 0x5c65a254
-//.word 0xb2293d09
-//.word 0x40b922d8
-//.word 0x95b387f1
-//.word 0xb16a81e4
-//.word 0x758b1a63
-//.word 0x5701a449
-//.word 0x5a154ddc
-//.word 0x3edaf34f
-//.word 0xf3c8398c
-//.word 0x54a7da30
-//.word 0x12af3dd6
-//.word 0xeeed4a98
-//.word 0x2ce87dd3
-//.word 0x4485382b
-//.word 0xda285ecf
-//.word 0xf01c1dfe
-//.word 0x5b350bcb
-//.word 0x73b3751d
-//.word 0x0f6af3f9
-//.word 0xb1204080
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00001378
-//// expected output
-//.word 0x1288010a
-//.word 0x5092c66d
-//.word 0xc8777168
-//.word 0x7ca62271
-//.word 0x39ce5dcb
-//.word 0x48a79dbc
-//.word 0xacb22bd3
-//.word 0x65f661fb
-//.word 0x1229493c
-//.word 0x662881b8
-//.word 0x6bf1eca2
-//.word 0x071095bd
-//.word 0xe47c96b9
-//.word 0x92ee16d3
-//.word 0xe3277662
-//.word 0xcdbf960c
-//// SHA512LongMsgvector_6
-//// vector length
-//.word 0x00001690
-//// input message
-//.word 0xbc4b7d3a
-//.word 0x380be067
-//.word 0xed7a2a02
-//.word 0xf6137cf2
-//.word 0xaaa6f533
-//.word 0x2aa0dd34
-//.word 0x368d237e
-//.word 0x45db0a97
-//.word 0xd4e11f26
-//.word 0xfe206e57
-//.word 0x4dc8f581
-//.word 0xd07e5907
-//.word 0x6d5cd87c
-//.word 0x79397f0a
-//.word 0x862b9d14
-//.word 0x7c4b771a
-//.word 0xecb83ddd
-//.word 0xa0df3dc4
-//.word 0x77f9577f
-//.word 0x70d4b1ea
-//.word 0x04d7ac34
-//.word 0xb9411640
-//.word 0xf4b1a14b
-//.word 0x0eeb93d0
-//.word 0xabd9c0a8
-//.word 0x47d0b576
-//.word 0x12153742
-//.word 0xfea0ec64
-//.word 0x161f57a4
-//.word 0x113e0a9f
-//.word 0x2726166d
-//.word 0x2343c780
-//.word 0xba4b8ecf
-//.word 0x1b7c3f34
-//.word 0xc7257c13
-//.word 0xa367713d
-//.word 0x4b3dc314
-//.word 0xaabac2ef
-//.word 0xc892e6c0
-//.word 0xe2dc79f4
-//.word 0xc016919a
-//.word 0x436a41c8
-//.word 0x3e2f103a
-//.word 0x86b3aa3d
-//.word 0x4d38d6cb
-//.word 0xab3ca8f8
-//.word 0x7efef88d
-//.word 0x743d13f2
-//.word 0x6643af51
-//.word 0xe82225f8
-//.word 0x1e3edaff
-//.word 0xd10bfe2b
-//.word 0xc1187a13
-//.word 0x3d4d2381
-//.word 0xf271341b
-//.word 0x01eefb43
-//.word 0x54d9d23b
-//.word 0x312d518d
-//.word 0x0f57c2aa
-//.word 0xa9f8d5d1
-//.word 0x52e69632
-//.word 0x88749b54
-//.word 0xcbf382b4
-//.word 0xb0789baf
-//.word 0x31e0e1a1
-//.word 0x47122f4f
-//.word 0xbb84b082
-//.word 0x380198f5
-//.word 0xa6a91171
-//.word 0xb3397837
-//.word 0xb28cca9e
-//.word 0xa96259fd
-//.word 0xa561c4cb
-//.word 0x51592505
-//.word 0xc7cc8cd0
-//.word 0xa6aead60
-//.word 0x6569d518
-//.word 0xe72423f3
-//.word 0x4f45f422
-//.word 0x15349ff7
-//.word 0x5a626301
-//.word 0x788b9d79
-//.word 0xde383edc
-//.word 0x1b877dda
-//.word 0x382ec96f
-//.word 0x4bbe0250
-//.word 0x4925e888
-//.word 0x1c77d463
-//.word 0xf5eea68b
-//.word 0xe42ffe71
-//.word 0xa6ceafee
-//.word 0xbe15702b
-//.word 0xc701d5be
-//.word 0x088e7e15
-//.word 0x49348f18
-//.word 0xe5b25f0a
-//.word 0x210a75b0
-//.word 0xbccdb0b6
-//.word 0xc798c54e
-//.word 0xb7dfef1a
-//.word 0xb9e9e14c
-//.word 0x451c000c
-//.word 0xf67bcf1a
-//.word 0x996daab4
-//.word 0x84c0b8ba
-//.word 0x29ed1b10
-//.word 0xea9e6944
-//.word 0x2f6d6070
-//.word 0xb6efd562
-//.word 0x2bf1eefb
-//.word 0xf90191d5
-//.word 0x5f311c28
-//.word 0xc61757ef
-//.word 0x5218a746
-//.word 0xb7e78417
-//.word 0x4e482cf5
-//.word 0x681a9948
-//.word 0xe294b1ab
-//.word 0xf9cfbe92
-//.word 0x60841d30
-//.word 0x90183a98
-//.word 0x60d5bc22
-//.word 0xd57bfc10
-//.word 0x3bf7bc71
-//.word 0x74721646
-//.word 0x918db2e4
-//.word 0x9feb3c99
-//.word 0xc3f11592
-//.word 0x8ac949fc
-//.word 0x7aadc26a
-//.word 0xed62bb77
-//.word 0x1f0277ac
-//.word 0x85ff32a4
-//.word 0x6065586d
-//.word 0x935ff532
-//.word 0xb1fd6c17
-//.word 0x5b346d65
-//.word 0xc92721e7
-//.word 0xa6a4a794
-//.word 0x21f2c46d
-//.word 0x41cad6a9
-//.word 0x78a30a10
-//.word 0x7c33cfa5
-//.word 0x52328b87
-//.word 0xab618c19
-//.word 0x74cb4161
-//.word 0xa94aaaae
-//.word 0x6a4e0d7e
-//.word 0x50daeb9e
-//.word 0x01cf3293
-//.word 0x026db439
-//.word 0xcd17d8aa
-//.word 0x24568f61
-//.word 0xa4218aa0
-//.word 0x9d5cab0e
-//.word 0x219eb9a5
-//.word 0x5b3757cb
-//.word 0x227237bf
-//.word 0xce178b37
-//.word 0x4b34bc48
-//.word 0x6c1d5f85
-//.word 0x81b2656b
-//.word 0x2be091fd
-//.word 0x6f6b30ab
-//.word 0x0aea0478
-//.word 0x0413815c
-//.word 0x88383ce7
-//.word 0xf312a028
-//.word 0x2bbee2cd
-//.word 0x3205388b
-//.word 0xfbe046c1
-//.word 0x7c3bd958
-//.word 0x04fad8ed
-//.word 0xcf3a7832
-//.word 0xd8d9ae91
-//.word 0xee38ea13
-//.word 0x0a3f0281
-//.word 0xe0a26cc9
-//.word 0xb463b1a2
-//.word 0x6f991e73
-//.word 0xf26f8000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00001690
-//// expected output
-//.word 0x34b4cf4e
-//.word 0xd7281ecb
-//.word 0x07f381e9
-//.word 0xfc380507
-//.word 0x2238e21e
-//.word 0xa0d1d2c5
-//.word 0xec0ad3b2
-//.word 0x3ea70024
-//.word 0x7b8e9535
-//.word 0xde9fac67
-//.word 0x83f95516
-//.word 0x6c4ca9a9
-//.word 0x0f4caa47
-//.word 0x056fa9f3
-//.word 0x13be75da
-//.word 0xf27ec8d2
-//// SHA512LongMsgvector_7
-//// vector length
-//.word 0x000019A8
-//// input message
-//.word 0xedba7d63
-//.word 0x12144e90
-//.word 0xec9eaace
-//.word 0x7576045a
-//.word 0x46e553dc
-//.word 0xb8ee5a98
-//.word 0x49272de8
-//.word 0x41c8f1ea
-//.word 0x9502e376
-//.word 0x0b929c53
-//.word 0x9f9593aa
-//.word 0x259ee3ba
-//.word 0x31064ece
-//.word 0x3483826c
-//.word 0xe7fc9cd0
-//.word 0xed9ceb99
-//.word 0xb426f6c1
-//.word 0x9c88c0d2
-//.word 0x5bb24a57
-//.word 0xa0a85a91
-//.word 0xf6d67b6c
-//.word 0xeba545b1
-//.word 0x724bde7d
-//.word 0x87e7c1f2
-//.word 0x11cdbe2c
-//.word 0x0c1e4277
-//.word 0xe79dd9bf
-//.word 0x2bbdf148
-//.word 0x5effe19f
-//.word 0x277a2ad0
-//.word 0xb3bbfcd9
-//.word 0x56d0fc5f
-//.word 0x76a044a0
-//.word 0xa57eaba9
-//.word 0x0dfd47c8
-//.word 0x11053145
-//.word 0x3126884d
-//.word 0x2e2db92f
-//.word 0x6ff5fdcb
-//.word 0xa4802346
-//.word 0xa9468f03
-//.word 0xadcd83cf
-//.word 0x937a9d5c
-//.word 0x98a7a1f1
-//.word 0x37f6795f
-//.word 0x4ae47a37
-//.word 0x71a1e93a
-//.word 0xb71fbe11
-//.word 0x7368a73f
-//.word 0x6d365053
-//.word 0x42bde262
-//.word 0x0acccab4
-//.word 0x3714bbbe
-//.word 0xc0c7f650
-//.word 0x8066c910
-//.word 0xd9d45527
-//.word 0x9cae953a
-//.word 0x2ddf9c9c
-//.word 0xe26e1ec2
-//.word 0xad9b32f7
-//.word 0xfb2b5650
-//.word 0xdb00b4e3
-//.word 0x63eca434
-//.word 0x4fc771f0
-//.word 0xecbf60de
-//.word 0x35f0ee12
-//.word 0x3b355a64
-//.word 0xca3d6320
-//.word 0x49e153ff
-//.word 0xe2b43c56
-//.word 0xe3dc828e
-//.word 0x642199d4
-//.word 0x2b441011
-//.word 0xcc92cf1d
-//.word 0x14b89d30
-//.word 0xa8d9e599
-//.word 0xeadeb9b2
-//.word 0x1c0e1713
-//.word 0xc8de6b06
-//.word 0x5f0a563b
-//.word 0x20e4aebd
-//.word 0x3becc625
-//.word 0x37a2ef0e
-//.word 0x91983ec8
-//.word 0xa6cb9051
-//.word 0xd233cc80
-//.word 0xda996884
-//.word 0x87a92f8d
-//.word 0x944841c9
-//.word 0xcb285b92
-//.word 0x6a9958e6
-//.word 0xcba2f817
-//.word 0x4450e1c3
-//.word 0x4d4ee307
-//.word 0xe0b680f0
-//.word 0x2627ac32
-//.word 0x4f18d11d
-//.word 0xc16b16cc
-//.word 0x7645e1a0
-//.word 0x9f1e9aed
-//.word 0x8e14b3f2
-//.word 0xd285e50f
-//.word 0xa4dcbc32
-//.word 0x82ab5593
-//.word 0x19fb67a1
-//.word 0x68e0803b
-//.word 0x23509124
-//.word 0x5534adb1
-//.word 0x4ac00ec5
-//.word 0xac0059ff
-//.word 0xecb42232
-//.word 0xe35eb316
-//.word 0xba99093d
-//.word 0x07ac2048
-//.word 0x385f715a
-//.word 0x350eb8cd
-//.word 0x41fbfa24
-//.word 0x21e8c741
-//.word 0x81e6bdd9
-//.word 0x93684d24
-//.word 0xf99bc2d9
-//.word 0xe5fa7e59
-//.word 0x7f1d872a
-//.word 0x87d143a8
-//.word 0x3b6e80f7
-//.word 0x7b65b73c
-//.word 0x2b19920d
-//.word 0xd9f0ab26
-//.word 0x9fa9975d
-//.word 0x4bf023d8
-//.word 0xbe2fdd7d
-//.word 0x92a8d7aa
-//.word 0x00c1a726
-//.word 0x009eb258
-//.word 0xb1f5abb7
-//.word 0xfc1e5682
-//.word 0x746a92b1
-//.word 0x81b6962b
-//.word 0xbe407b39
-//.word 0x9fb9fb3b
-//.word 0x579b789a
-//.word 0xf9bc3ffd
-//.word 0xdd240fc0
-//.word 0x451bd5a2
-//.word 0x4087babd
-//.word 0xcf755fbc
-//.word 0x47f66748
-//.word 0xf62c37c3
-//.word 0x09a4f939
-//.word 0xade6e793
-//.word 0x754bc60e
-//.word 0xfc0fb0ec
-//.word 0xcba7176a
-//.word 0x7d5507f1
-//.word 0x21f9ab90
-//.word 0xdf2a13aa
-//.word 0xdf8534ec
-//.word 0x66453182
-//.word 0x4215d98b
-//.word 0x692270ca
-//.word 0xdd73b29e
-//.word 0xd27d1534
-//.word 0x13f24ffb
-//.word 0xa2db1858
-//.word 0x9ee6319c
-//.word 0x6a01a533
-//.word 0x0c274f1d
-//.word 0xd37a9ca3
-//.word 0x3d939242
-//.word 0x171611ec
-//.word 0xe6895970
-//.word 0x8666cd36
-//.word 0x116ef72f
-//.word 0x0341cb0c
-//.word 0x9b2c30ae
-//.word 0x8442bcde
-//.word 0xb4aebf3f
-//.word 0x95478480
-//.word 0x6265d3d6
-//.word 0xd4f3baaa
-//.word 0xffc68e8f
-//.word 0x762d2c76
-//.word 0xb6ca8425
-//.word 0xc2a059e5
-//.word 0x0a6c427b
-//.word 0x9139f55a
-//.word 0x4f2fc417
-//.word 0xd5ac681d
-//.word 0x2f96fea2
-//.word 0x0eef4fda
-//.word 0x27a9546a
-//.word 0xd6bcfa1f
-//.word 0x077722e0
-//.word 0x5613ece1
-//.word 0x758e351a
-//.word 0xceb75ef8
-//.word 0x6a854f52
-//.word 0x12acbc9e
-//.word 0xb472a765
-//.word 0x08bf27f4
-//.word 0x72746755
-//.word 0x2bfef17d
-//.word 0x9c2b2dc7
-//.word 0x0a3c24a1
-//.word 0x783b8a85
-//.word 0xc9800000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000019A8
-//// expected output
-//.word 0xffcb3b31
-//.word 0x3e576ea5
-//.word 0xb0a87449
-//.word 0x749b82c1
-//.word 0x523947ad
-//.word 0x019c6334
-//.word 0x01a185fb
-//.word 0xcb4fd475
-//.word 0xdfe42289
-//.word 0xc5413f44
-//.word 0x0d083f73
-//.word 0xb65abcf2
-//.word 0x386e0eff
-//.word 0x39acfafa
-//.word 0x398a3d6b
-//.word 0x778fde23
-//// SHA512LongMsgvector_8
-//// vector length
-//.word 0x00001CC0
-//// input message
-//.word 0x89eb3056
-//.word 0x770a6157
-//.word 0xf06921bc
-//.word 0x15383444
-//.word 0x7c4b6d86
-//.word 0x2d10d185
-//.word 0xf1c3f984
-//.word 0xcde5b81c
-//.word 0xc9eafe8b
-//.word 0xf532fc4f
-//.word 0xae3a89f4
-//.word 0x1e14c52a
-//.word 0x0214fc1a
-//.word 0xb0cdcdfa
-//.word 0x583b8bdf
-//.word 0x8a42e3d3
-//.word 0xf857bf28
-//.word 0x7e7e6b0c
-//.word 0x5f74f65d
-//.word 0xd22ddcbe
-//.word 0xbd81e1ea
-//.word 0xc0224048
-//.word 0x75d105c0
-//.word 0xf6d1b8ce
-//.word 0xa09c3bd4
-//.word 0x17d6f5b5
-//.word 0x8a7f319f
-//.word 0x396cc028
-//.word 0x34f8e69d
-//.word 0x65f77496
-//.word 0xd0eb31ce
-//.word 0x1a7b7e32
-//.word 0x48203a38
-//.word 0xca22e472
-//.word 0xb8c3ff63
-//.word 0x5bb9bb91
-//.word 0xefe2d1db
-//.word 0xa734af0d
-//.word 0xf2f3d5b2
-//.word 0xfd267f2a
-//.word 0x794b84fc
-//.word 0x9e4a7e6d
-//.word 0x70a82b51
-//.word 0x41fd1321
-//.word 0x77a86b4e
-//.word 0x8fc13ad5
-//.word 0x624fba14
-//.word 0xa7bb01db
-//.word 0xba85e0c7
-//.word 0x9c360ccb
-//.word 0x3a967b10
-//.word 0xf21e11ff
-//.word 0x53b07c9c
-//.word 0x24865d15
-//.word 0xa869a89a
-//.word 0x21234d70
-//.word 0x93361841
-//.word 0xcaced5b7
-//.word 0x9ef5b949
-//.word 0x7606fd54
-//.word 0x0b64cc6d
-//.word 0x6f6b5ff6
-//.word 0x4da767ef
-//.word 0x7244ab0f
-//.word 0x8cc6f213
-//.word 0x32fb2357
-//.word 0x252daba3
-//.word 0xd69b1f47
-//.word 0x282b226a
-//.word 0x76598a9f
-//.word 0xd873beb9
-//.word 0xa20862e1
-//.word 0x2e9e37e5
-//.word 0xdca33cd3
-//.word 0x56a61ac7
-//.word 0x19c7be01
-//.word 0x316c483a
-//.word 0x43362438
-//.word 0xd13476a1
-//.word 0xba56bc0d
-//.word 0x0024af5e
-//.word 0xceaf6954
-//.word 0xbac8cd5c
-//.word 0x477124a9
-//.word 0xae910486
-//.word 0xdeec76eb
-//.word 0xc151574e
-//.word 0xc115ffbb
-//.word 0x8bc12127
-//.word 0x1208f202
-//.word 0xd7fc8e0b
-//.word 0x69819768
-//.word 0x27011ff6
-//.word 0x4d61c8de
-//.word 0x2f342969
-//.word 0xbf2f7415
-//.word 0x55dd56e8
-//.word 0xb0941f04
-//.word 0x38a8237c
-//.word 0x85de6066
-//.word 0x25246131
-//.word 0x9a7f6239
-//.word 0xa344b499
-//.word 0xbd8b6340
-//.word 0xe8e11748
-//.word 0xae3d3883
-//.word 0x62365556
-//.word 0xa672c7ca
-//.word 0x2f6291e0
-//.word 0xcd2c8b25
-//.word 0xa5e9c087
-//.word 0xc1111467
-//.word 0xcc332aef
-//.word 0x16ea84a6
-//.word 0xdf0cec41
-//.word 0xd12413bd
-//.word 0xce2379aa
-//.word 0xec528cca
-//.word 0xbe8b14da
-//.word 0xd6a9ceb0
-//.word 0x873d5786
-//.word 0xf0834c96
-//.word 0x3594b0e7
-//.word 0x10dc8e66
-//.word 0x89cfdf38
-//.word 0x01d8ad4f
-//.word 0x7592793b
-//.word 0x013bdb43
-//.word 0xa36668b5
-//.word 0x42efd87a
-//.word 0xef3469ed
-//.word 0x6a827eee
-//.word 0xe8ce8c31
-//.word 0x13a636dc
-//.word 0x5367b752
-//.word 0x4caf8149
-//.word 0xa8152323
-//.word 0x1618707b
-//.word 0x9256defe
-//.word 0xe8ff2c7c
-//.word 0x7388483e
-//.word 0x2ba46f9b
-//.word 0xdf7096c6
-//.word 0xbeed09ea
-//.word 0x1cb45279
-//.word 0x73e55cc1
-//.word 0xa861d8c0
-//.word 0x9039e039
-//.word 0xb366da07
-//.word 0x50baa0b2
-//.word 0xa116de40
-//.word 0x5fdebb4d
-//.word 0x89aabb5e
-//.word 0x623ee373
-//.word 0xb9bd1fdb
-//.word 0x6c19e24c
-//.word 0x2fce0c33
-//.word 0x8ad01049
-//.word 0x21c15667
-//.word 0x3868de9b
-//.word 0x765f277b
-//.word 0xe90b4fb9
-//.word 0x4bd17bf8
-//.word 0x848779de
-//.word 0x6f29a46b
-//.word 0xe1ce0889
-//.word 0xe8dac7e4
-//.word 0x5074bcfb
-//.word 0x6c3b5d78
-//.word 0x1334e6bc
-//.word 0xe807b4bf
-//.word 0xde6cee17
-//.word 0xfce06b56
-//.word 0x5e9cd099
-//.word 0x7dc7f95e
-//.word 0xb0eb9b96
-//.word 0xf2a627fc
-//.word 0xe5a2f1a4
-//.word 0x17c691d7
-//.word 0x84ae891e
-//.word 0x5d59299d
-//.word 0x0822b0a2
-//.word 0x68f2b47e
-//.word 0x5eb3c494
-//.word 0x90084baf
-//.word 0x693bb799
-//.word 0x6177dbe9
-//.word 0x7e37921c
-//.word 0x1afea6e7
-//.word 0xe849f0cc
-//.word 0x32c1c0ec
-//.word 0x64b67f1c
-//.word 0xcec9923a
-//.word 0xa6e882c2
-//.word 0x4c805a9c
-//.word 0xd2ed5138
-//.word 0xbc36a9dd
-//.word 0x04f7d73e
-//.word 0x629ee44f
-//.word 0xcada1356
-//.word 0x3551c445
-//.word 0xa4929847
-//.word 0x624ad699
-//.word 0x8aba0e9b
-//.word 0xca68fc27
-//.word 0x6615ae21
-//.word 0x80f0e94f
-//.word 0x9609ca6b
-//.word 0x4c08a977
-//.word 0x6c1f4251
-//.word 0x2b3d1787
-//.word 0xae85106c
-//.word 0xccfe656c
-//.word 0x168cbd9c
-//.word 0x141f9895
-//.word 0xd22aea83
-//.word 0x9b570879
-//.word 0x0579c808
-//.word 0x2ec1e40f
-//.word 0x4436a0d4
-//.word 0x4b5fad54
-//.word 0x1a424cd8
-//.word 0xa793b7c9
-//.word 0x8525bcc5
-//.word 0xaba4abf2
-//.word 0x77867293
-//.word 0xf33f07d9
-//.word 0x56b406fb
-//.word 0xcef39c89
-//.word 0x7c21a3fd
-//.word 0x80000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00001CC0
-//// expected output
-//.word 0x6b8be942
-//.word 0xecd6e850
-//.word 0x9b88c0eb
-//.word 0xed80e0e2
-//.word 0x193eccf2
-//.word 0x12430429
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-//.word 0xd046cfbf
-//.word 0x37f80f92
-//.word 0x2e36bb1c
-//.word 0x3b9e9d43
-//.word 0xcbbc477d
-//.word 0xc80eefc7
-//.word 0x83adc20b
-//// SHA512LongMsgvector_9
-//// vector length
-//.word 0x00001FD8
-//// input message
-//.word 0xafdccc84
-//.word 0xf257cb76
-//.word 0x8b7ad735
-//.word 0xedbd1990
-//.word 0xb6114bad
-//.word 0x876928ab
-//.word 0x12792085
-//.word 0x74bd513a
-//.word 0xc6beb32b
-//.word 0xee9192c4
-//.word 0xbba0425e
-//.word 0x32ad0e64
-//.word 0x221371b5
-//.word 0xff4f894a
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-//.word 0x1aabed39
-//.word 0x51823246
-//.word 0xcc66c707
-//.word 0x4aea804e
-//.word 0x621acb20
-//.word 0x17bce416
-//.word 0xacd54c03
-//.word 0xba6f77d7
-//.word 0x7f9ac4c4
-//.word 0x79b1b39f
-//.word 0x33de5388
-//.word 0x60e0f9cd
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-//.word 0x3702591e
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-//.word 0x72990317
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-//.word 0x3b5fc900
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-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00001FD8
-//// expected output
-//.word 0x014fd2fa
-//.word 0x6b05c4fc
-//.word 0xa1a5c075
-//.word 0x3f15c940
-//.word 0xb5f976b4
-//.word 0x1a40bf6b
-//.word 0xb14afe83
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-//.word 0x61739407
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-//.word 0x6a2ac77f
-//.word 0x573e6744
-//.word 0xcf0002b7
-//.word 0x8b5b7f66
-//.word 0x4e22434e
-//.word 0x22d0ccd0
-//// SHA512LongMsgvector_10
-//// vector length
-//.word 0x000022F0
-//// input message
-//.word 0x7a26b7f5
-//.word 0x5809d585
-//.word 0x28540601
-//.word 0xc87db4bb
-//.word 0x8e908c3d
-//.word 0x2d82823a
-//.word 0xddc315c4
-//.word 0xb612d4be
-//.word 0x5d952195
-//.word 0xe329352b
-//.word 0xeaf76414
-//.word 0x0a48a205
-//.word 0x739a4789
-//.word 0xd3f20ff6
-//.word 0x7a7565a0
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-//.word 0x96430fe8
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-//.word 0xd175cabd
-//.word 0x0302fecf
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-//.word 0x5ebdf110
-//.word 0x6d570956
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-//.word 0x98ad3bda
-//.word 0x14534223
-//.word 0x632ba862
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-//.word 0x0997ca4d
-//.word 0x617d91c7
-//.word 0xbf3c0988
-//.word 0x4b6d311a
-//.word 0xb21cbbfd
-//.word 0xcad6ca54
-//.word 0x7503fadf
-//.word 0xc777a129
-//.word 0x6b435403
-//.word 0x42d1ad30
-//.word 0x4e304c62
-//.word 0xcfac1c66
-//.word 0xaba2d79b
-//.word 0x1392cda8
-//.word 0x6476e16e
-//.word 0x4b52d43c
-//.word 0x2d0dc642
-//.word 0xc67ff949
-//.word 0x10cbd9a1
-//.word 0x66ef395a
-//.word 0xe999e0b7
-//.word 0x233d44df
-//.word 0xea6495d6
-//.word 0x8747fdac
-//.word 0x189c27f4
-//.word 0x33b0fe78
-//.word 0xccb6b72b
-//.word 0x595e115f
-//.word 0x33aadb38
-//.word 0x40feb761
-//.word 0xcf761ffd
-//.word 0xc37ba5e1
-//.word 0xf4997f00
-//.word 0xd28b4226
-//.word 0x4c98eeea
-//.word 0xf0232bde
-//.word 0x537dd208
-//.word 0xb3fdaf96
-//.word 0xdb5386cd
-//.word 0x47195343
-//.word 0x89abd64e
-//.word 0xeb394fbc
-//.word 0x561a87c4
-//.word 0x72630f3d
-//.word 0x0fb98000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000022F0
-//// expected output
-//.word 0x5f1da3c0
-//.word 0x3d633d35
-//.word 0xd6f28c19
-//.word 0x87ad25ae
-//.word 0x9e26b6af
-//.word 0xdebb2aed
-//.word 0x02f1719b
-//.word 0x706d20e5
-//.word 0x632b2005
-//.word 0x933db621
-//.word 0x29032fa3
-//.word 0xfd230446
-//.word 0x9928f681
-//.word 0x0af1742c
-//.word 0x27731a5b
-//.word 0xeffb15bf
-//// SHA512LongMsgvector_11
-//// vector length
-//.word 0x00002608
-//// input message
-//.word 0x8ceddebd
-//.word 0x38f00406
-//.word 0x743a6756
-//.word 0x565ce762
-//.word 0xd3464435
-//.word 0xd50bd61b
-//.word 0x8de57fbe
-//.word 0x0b79df8f
-//.word 0x0c5cc667
-//.word 0x13d5ef6e
-//.word 0xbbe5eb3d
-//.word 0x4b845b3f
-//.word 0x8b2e625d
-//.word 0xd69e5ada
-//.word 0x71dac67b
-//.word 0x1b6f88ec
-//.word 0xe5fe555f
-//.word 0x44f76576
-//.word 0x65a56f63
-//.word 0xc06bd44e
-//.word 0xf04d1bf6
-//.word 0xc2b19d9c
-//.word 0x8c67811d
-//.word 0xc0e8eb5e
-//.word 0xc0db71ec
-//.word 0xf4decfe4
-//.word 0x1b82db11
-//.word 0xde97bb55
-//.word 0xabab554a
-//.word 0xc0cd0728
-//.word 0x869798ea
-//.word 0x216b6fac
-//.word 0x45fc0358
-//.word 0x4b109381
-//.word 0x8485178f
-//.word 0xcd92761d
-//.word 0x6350f99f
-//.word 0xf9790048
-//.word 0x086ff42b
-//.word 0x67807ca0
-//.word 0x1b68f4e9
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-//.word 0x49b50b25
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-//.word 0xb9af7a00
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-//.word 0x3400c5ec
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-//.word 0x09652e29
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-//.word 0xda5ff4b7
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-//.word 0xb3ed781b
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-//.word 0x6a380bca
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-//.word 0x56384205
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-//.word 0xdb50822b
-//.word 0xa642f823
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-//.word 0xfbef69ec
-//.word 0xbea29cb2
-//.word 0x900338de
-//.word 0x4e4731e2
-//.word 0xb0181762
-//.word 0xd9de4699
-//.word 0x2c3d5df9
-//.word 0x62def111
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-//.word 0x2ff5ad58
-//.word 0x1030a4bc
-//.word 0x4c82dcce
-//.word 0x2de005cb
-//.word 0x07193fa8
-//.word 0x105f8bb1
-//.word 0x72037f70
-//.word 0x9f803fd0
-//.word 0xe5bba882
-//.word 0x4289cea0
-//.word 0x7972a990
-//.word 0x65b50b2c
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-//.word 0xfab06b92
-//.word 0x46206509
-//.word 0xf51e8887
-//.word 0x077bf4f9
-//.word 0xcd159ed1
-//.word 0xfd9e01f2
-//.word 0x029f11cc
-//.word 0x95bc71c8
-//.word 0x9139e5e6
-//.word 0x03bd0aa4
-//.word 0x81564523
-//.word 0xbebef985
-//.word 0x5bddfd99
-//.word 0xff8e4dba
-//.word 0xa9a6fff4
-//.word 0x45337969
-//.word 0x7e01e2f3
-//.word 0xd463d60b
-//.word 0xee2f5eea
-//.word 0x310b1fed
-//.word 0x91e7d13e
-//.word 0xa7cbf3b1
-//.word 0x04d3bdec
-//.word 0xc67857cb
-//.word 0x69104803
-//.word 0xdf983105
-//.word 0xe2b2bb25
-//.word 0x89eacefb
-//.word 0x193d0409
-//.word 0x1edc5d9f
-//.word 0xbb2d34fc
-//.word 0x3f1371b6
-//.word 0xf86f015c
-//.word 0x4ce78359
-//.word 0x05e6441b
-//.word 0xede36e75
-//.word 0x9b800000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00002608
-//// expected output
-//.word 0x1c7665a6
-//.word 0x1930433f
-//.word 0xcc7660b3
-//.word 0x6049c016
-//.word 0xa7c646dd
-//.word 0x1e841272
-//.word 0x1314f969
-//.word 0xd3661554
-//.word 0xb97b18fd
-//.word 0x35945109
-//.word 0xcfbfc783
-//.word 0xbdc424b2
-//.word 0x04ab19af
-//.word 0xaac855c2
-//.word 0x84daf7f2
-//.word 0xcb333a65
-//// SHA512LongMsgvector_12
-//// vector length
-//.word 0x00002920
-//// input message
-//.word 0xeb22f73a
-//.word 0x99b3b00d
-//.word 0x6c9b15c8
-//.word 0xbe5cf11a
-//.word 0x5435d561
-//.word 0xe398bbc1
-//.word 0xd3dee973
-//.word 0x423a1860
-//.word 0x4cebd6ef
-//.word 0x8ab6291b
-//.word 0xd89475c8
-//.word 0x5ca89f57
-//.word 0xc4737378
-//.word 0xce4b433f
-//.word 0x0e09d17b
-//.word 0xec037043
-//.word 0xec3a65d1
-//.word 0x32d49394
-//.word 0x45cc5880
-//.word 0x13e8b2a9
-//.word 0x35eba610
-//.word 0x750ce2bc
-//.word 0x8da8a10d
-//.word 0x3234cf4e
-//.word 0x51756d89
-//.word 0x99f3389f
-//.word 0x39ab8597
-//.word 0xeb047037
-//.word 0x310435d1
-//.word 0xdec4de60
-//.word 0xd9211fd4
-//.word 0x1eb57ea9
-//.word 0x0506b6be
-//.word 0xc7fc5e65
-//.word 0x3e99c6b6
-//.word 0xece4222a
-//.word 0x3f26ea65
-//.word 0x13598052
-//.word 0x79de1475
-//.word 0xb76ec57d
-//.word 0x90530819
-//.word 0xc5d84e0d
-//.word 0xdbfee185
-//.word 0x1f700fa9
-//.word 0xe8b98b71
-//.word 0x1cb510bb
-//.word 0xf545479b
-//.word 0x0547ebf2
-//.word 0x78c62b42
-//.word 0x9a6d50c0
-//.word 0x99429fab
-//.word 0x8b9181dd
-//.word 0xb225e1a0
-//.word 0xffbed6c2
-//.word 0xd6c082ec
-//.word 0x11293a2f
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-//.word 0xfecdc8d1
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-//.word 0xc5a47ebd
-//.word 0x0ab2fc88
-//.word 0x1979124a
-//.word 0x0d335f33
-//.word 0x23be9b29
-//.word 0x794c7e1b
-//.word 0x165bdd93
-//.word 0x2be8178b
-//.word 0x98dfaf82
-//.word 0xb2d73acf
-//.word 0x44fc7c34
-//.word 0xd44cceb6
-//.word 0x2707c2ac
-//.word 0x07600a17
-//.word 0x43799631
-//.word 0xf88efd49
-//.word 0x0f711ecd
-//.word 0x073607a9
-//.word 0xf42f16cf
-//.word 0xc81b5d17
-//.word 0xd29a4b4a
-//.word 0x84e48979
-//.word 0x79bb2394
-//.word 0xb79ee838
-//.word 0x314013c7
-//.word 0x90382bbe
-//.word 0x32fa2743
-//.word 0x7306d6fe
-//.word 0x2c5f7e2a
-//.word 0x7a3fc4ec
-//.word 0xc109cbe3
-//.word 0xf07fa000
-//.word 0x0635d698
-//.word 0xd5456db7
-//.word 0x0545f9b8
-//.word 0x5d76ff12
-//.word 0x3e3ea375
-//.word 0x70d98016
-//.word 0x224bd847
-//.word 0x2b99ed4a
-//.word 0x9638ae67
-//.word 0x5ec6963c
-//.word 0x76f8d255
-//.word 0x0cd4a2fc
-//.word 0x0f200152
-//.word 0xef1a889f
-//.word 0xa46990e7
-//.word 0xf15497be
-//.word 0xea32e55c
-//.word 0xb4216ef4
-//.word 0x8cfbfb42
-//.word 0x0a868564
-//.word 0xa7ebe1ea
-//.word 0x7e6aa330
-//.word 0x4f4b3cec
-//.word 0xc9186503
-//.word 0x0909c1a1
-//.word 0x5ec0bd88
-//.word 0x4f36bca8
-//.word 0xdff671f0
-//.word 0x0f898b65
-//.word 0xa5319871
-//.word 0x2cda237d
-//.word 0x3c4d20c2
-//.word 0xfba78b5b
-//.word 0xe4094b9f
-//.word 0xc7925caf
-//.word 0x118a2d4b
-//.word 0x4ee047ea
-//.word 0xecd73009
-//.word 0x42fc8fc3
-//.word 0xd15b90a2
-//.word 0xc9f28ab5
-//.word 0xcf66e0e2
-//.word 0xfdf5257e
-//.word 0x2aac831b
-//.word 0x6cda5da1
-//.word 0xdcc433a1
-//.word 0x999ac6e5
-//.word 0x10aa7d4c
-//.word 0x7ad408d5
-//.word 0xa53e43f9
-//.word 0xf8495d3e
-//.word 0xb2c33909
-//.word 0x725e14b3
-//.word 0xfc6069e0
-//.word 0x3a9d110c
-//.word 0x81a2af67
-//.word 0x16344be3
-//.word 0xf1f93d8b
-//.word 0xc0744d16
-//.word 0x2f3718bc
-//.word 0x80000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00002920
-//// expected output
-//.word 0x97c433de
-//.word 0x3cd8f18b
-//.word 0x75e494ba
-//.word 0xfc3c813e
-//.word 0x112b2261
-//.word 0xf1261ea6
-//.word 0xfab9dce0
-//.word 0xaaee5e53
-//.word 0x59f0e763
-//.word 0xf02154ca
-//.word 0xc1589bb7
-//.word 0x0c2cbe9c
-//.word 0xd22f9765
-//.word 0x59032923
-//.word 0xc4e2beaf
-//.word 0x3f88f196
-//// SHA512LongMsgvector_13
-//// vector length
-//.word 0x00002C38
-//// input message
-//.word 0xbd361ca6
-//.word 0xc8d3531d
-//.word 0x4dc2415d
-//.word 0xb16ff93d
-//.word 0x3e81d3c2
-//.word 0xb4511138
-//.word 0x00a1c281
-//.word 0x4b8be7ae
-//.word 0x36b7d5cc
-//.word 0x64d1da00
-//.word 0x3a3a23d7
-//.word 0xe2feddd7
-//.word 0x96079b5a
-//.word 0x1b90f89c
-//.word 0x8bdc7d12
-//.word 0x5827c5fd
-//.word 0x8eddde40
-//.word 0x580af36e
-//.word 0xc6112828
-//.word 0xcda2c6a6
-//.word 0x90e69893
-//.word 0xddfc951e
-//.word 0xfba9be4e
-//.word 0xa34b4a95
-//.word 0x4c0f01a9
-//.word 0xac64e68f
-//.word 0x7bb018f8
-//.word 0x7a41fad1
-//.word 0xb4869216
-//.word 0x037f2fe7
-//.word 0xd7724fdd
-//.word 0x33e0bf9e
-//.word 0xf8b704af
-//.word 0x66c9fa8a
-//.word 0xe07dbbf1
-//.word 0xefc4c281
-//.word 0x8a4f518a
-//.word 0x95000f1e
-//.word 0xa79ef668
-//.word 0x10cc6c3f
-//.word 0x1b3cb0fb
-//.word 0x90207888
-//.word 0x7de1d9b9
-//.word 0x361466de
-//.word 0x9baa9c98
-//.word 0x99667eec
-//.word 0xf4957c97
-//.word 0x43f999a1
-//.word 0x3c06cd35
-//.word 0x3151a8b0
-//.word 0xdb4539f8
-//.word 0x57172e0f
-//.word 0x6efd3ce8
-//.word 0x199bc279
-//.word 0x44bea911
-//.word 0xd34d8eec
-//.word 0xe37d2305
-//.word 0x5243d22b
-//.word 0x810fa457
-//.word 0x58b7623d
-//.word 0x8bb1fa21
-//.word 0x1c8623ec
-//.word 0x2283447f
-//.word 0xc8b29247
-//.word 0x98097911
-//.word 0xfae03e20
-//.word 0xf7a9e27d
-//.word 0x43db498f
-//.word 0x7b2f9ceb
-//.word 0xab0feb6d
-//.word 0x134b1788
-//.word 0x2b0fefda
-//.word 0xe4129904
-//.word 0x310f34b8
-//.word 0xc679bb14
-//.word 0x1f6b2c2e
-//.word 0xc5deeaf0
-//.word 0xcd1e6026
-//.word 0xa17fe8d5
-//.word 0x034bebce
-//.word 0x4e004984
-//.word 0xffb8fb1b
-//.word 0x75e9f7c1
-//.word 0xf54e5341
-//.word 0xf125aed5
-//.word 0x8a9bcc3c
-//.word 0x5385800d
-//.word 0x5850cf4b
-//.word 0x5f3b5239
-//.word 0x6dc3dc70
-//.word 0x8c5f5d2e
-//.word 0xcc6e06f1
-//.word 0x886eae45
-//.word 0xea6e75da
-//.word 0xb1c6a7d9
-//.word 0x3205e378
-//.word 0x9d2b7ccd
-//.word 0x82191fdf
-//.word 0x9445b603
-//.word 0xacb28d66
-//.word 0x1120b3e6
-//.word 0xf680a426
-//.word 0x44aa24e1
-//.word 0x9a526e7e
-//.word 0x92388ee5
-//.word 0x47a00c92
-//.word 0x1402cae7
-//.word 0x9e022fc7
-//.word 0x14a28560
-//.word 0xb5b7a048
-//.word 0x939ac1cc
-//.word 0x971fba85
-//.word 0xc6cb522c
-//.word 0xc241eaae
-//.word 0x94fe6183
-//.word 0xa846363c
-//.word 0x195eec5c
-//.word 0x30fcb369
-//.word 0x27fc4443
-//.word 0x32540db4
-//.word 0xc04a8e47
-//.word 0xfde5035e
-//.word 0x9ca1437f
-//.word 0xd566e8ef
-//.word 0xa9bbb082
-//.word 0x6d3823b1
-//.word 0x863976ed
-//.word 0x72dab033
-//.word 0x081f0be1
-//.word 0x00729dc8
-//.word 0xb5533782
-//.word 0x2a4b8e05
-//.word 0x4b219879
-//.word 0x76513947
-//.word 0x3aba1f73
-//.word 0x5f97eb2b
-//.word 0x26b091a0
-//.word 0xd1d20114
-//.word 0x667c0734
-//.word 0xb1db6fa9
-//.word 0x88f86eea
-//.word 0x53313d54
-//.word 0xcbe6077c
-//.word 0x017405c4
-//.word 0xa267e82c
-//.word 0x7aeb776b
-//.word 0x3884793f
-//.word 0x71ffd501
-//.word 0xe7a9f87c
-//.word 0x0abe77ff
-//.word 0xbf24f5b1
-//.word 0x61594825
-//.word 0x05abd72e
-//.word 0x03a746f5
-//.word 0xb2d35648
-//.word 0x72a00635
-//.word 0xf09affd8
-//.word 0xa5e22e71
-//.word 0xa0deb3b9
-//.word 0x862ffa77
-//.word 0xd7e3274e
-//.word 0x72ecb8d9
-//.word 0x5cd165fa
-//.word 0xbda44b6e
-//.word 0x2b344aa5
-//.word 0x2b83acd1
-//.word 0xf57b073e
-//.word 0x78dc64e1
-//.word 0x9e79a033
-//.word 0xd1a41340
-//.word 0xbee770fa
-//.word 0x59f5ecd4
-//.word 0x21dfa38c
-//.word 0xa58b3748
-//.word 0x4763bae5
-//.word 0x404ace8c
-//.word 0xe4d40a86
-//.word 0x27b6a051
-//.word 0x617b3df3
-//.word 0x4e79318e
-//.word 0x5904d035
-//.word 0x1ae118fe
-//.word 0x1dfd9458
-//.word 0xe55f7f9f
-//.word 0x305c2dee
-//.word 0x7d0aa735
-//.word 0xccf7968b
-//.word 0xa51a62c5
-//.word 0x5b099a47
-//.word 0x926d971a
-//.word 0xffb35c3f
-//.word 0x6f05c143
-//.word 0x0b79d114
-//.word 0xda887013
-//.word 0x87c1416a
-//.word 0x65bec6a0
-//.word 0xb058c96b
-//.word 0x1617fbc5
-//.word 0x75ecdc41
-//.word 0xe723daa0
-//.word 0xfc93bd9f
-//.word 0x46184214
-//.word 0x1b430639
-//.word 0x964fa648
-//.word 0xdf572548
-//.word 0xacc78e26
-//.word 0x0811da07
-//.word 0x54a113dd
-//.word 0x8b12ba38
-//.word 0xcaa26760
-//.word 0x0fe3afa0
-//.word 0x40b44ae4
-//.word 0x70707587
-//.word 0x5f659666
-//.word 0x3f881f39
-//.word 0xbe66b423
-//.word 0x405e9087
-//.word 0x6c0e251e
-//.word 0xeb0b0246
-//.word 0x6cd5fa9d
-//.word 0xec0a83cf
-//.word 0x34d95cac
-//.word 0xa3ba737e
-//.word 0x2d5c0599
-//.word 0xa4df0733
-//.word 0x3644c576
-//.word 0x3822c9d4
-//.word 0x229afe9b
-//.word 0xda8c15c9
-//.word 0x350b2821
-//.word 0xbb0f9d7e
-//.word 0xaa6a4e68
-//.word 0x3efee6e5
-//.word 0x302c8e91
-//.word 0x7c90caf1
-//.word 0x68eb9d05
-//.word 0xc260f41c
-//.word 0x69e442ec
-//.word 0x0ff067e2
-//.word 0x3c78d6b7
-//.word 0x9621f744
-//.word 0x61afca97
-//.word 0x42bcce46
-//.word 0x48b02103
-//.word 0x2cede871
-//.word 0xd84af137
-//.word 0x27c39752
-//.word 0xec6fe6af
-//.word 0x35b200f9
-//.word 0xd1b3bfb0
-//.word 0x0f109c7b
-//.word 0xc9d1d0bf
-//.word 0xa19bb970
-//.word 0x8b267e27
-//.word 0x8cf1f675
-//.word 0xc135c678
-//.word 0xa217caab
-//.word 0x8821b702
-//.word 0x6df3fe37
-//.word 0xf336f35e
-//.word 0xa8d22ec0
-//.word 0x896131e6
-//.word 0xc5e34cf4
-//.word 0xc3b3be39
-//.word 0x65ba1d03
-//.word 0x8fe2f8b8
-//.word 0xe3cdba22
-//.word 0xcfc8d10b
-//.word 0xcafa100a
-//.word 0xdae1529c
-//.word 0x5a006176
-//.word 0xfad1161a
-//.word 0x0701c1a9
-//.word 0xeddccaf8
-//.word 0xfa0799e5
-//.word 0x646db4ec
-//.word 0x8e7b27f5
-//.word 0x87902970
-//.word 0xd3affca4
-//.word 0x6f781544
-//.word 0x0f567d44
-//.word 0xaaf977ea
-//.word 0x38076328
-//.word 0xbb0ee229
-//.word 0x7cbe3b2a
-//.word 0x9755fe8b
-//.word 0xb95ae726
-//.word 0x298e04df
-//.word 0x05201a7c
-//.word 0xcf2046b8
-//.word 0x2836e092
-//.word 0xda94a4eb
-//.word 0x1c291450
-//.word 0x12171815
-//.word 0x9468e8a3
-//.word 0x30fc2b12
-//.word 0x72c661fb
-//.word 0x62397e87
-//.word 0x4ffcd7cc
-//.word 0xcbe5425a
-//.word 0xf7257910
-//.word 0x01c0c035
-//.word 0xea41c8c4
-//.word 0x8dabd206
-//.word 0xddb21766
-//.word 0x6e2b6882
-//.word 0x37c2127e
-//.word 0x96eb049d
-//.word 0x941b3412
-//.word 0x6b373e13
-//.word 0x454d4e30
-//.word 0x478241e3
-//.word 0xce4b0768
-//.word 0xf8e04cce
-//.word 0x67ee574f
-//.word 0x418c32dd
-//.word 0x7b710bfd
-//.word 0x5864dad8
-//.word 0x2cf3448f
-//.word 0x6668bfd0
-//.word 0xcdf9f8a7
-//.word 0x0a3f7296
-//.word 0x67ea6fe7
-//.word 0xd6b21341
-//.word 0x3591c77a
-//.word 0xd02fdcac
-//.word 0x289e708b
-//.word 0xf34796f5
-//.word 0x6324b1cb
-//.word 0xab302100
-//.word 0xc01c22ef
-//.word 0x5c44f0f2
-//.word 0x49e13030
-//.word 0xdc808bb6
-//.word 0xc0b39cca
-//.word 0xf4060c7b
-//.word 0x1734fb7d
-//.word 0xe49ba234
-//.word 0xf9ee370f
-//.word 0xdc2a1117
-//.word 0x3fcb0dc8
-//.word 0x833f301f
-//.word 0x7c9b8ef4
-//.word 0x748d6a8a
-//.word 0x72919e65
-//.word 0xbc683e5b
-//.word 0x9ac778ee
-//.word 0x5d4cbed9
-//.word 0xa0b528e9
-//.word 0xce54130e
-//.word 0xe4be0fb2
-//.word 0x78c4f849
-//.word 0xfba4622a
-//.word 0x3b803a80
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00002C38
-//// expected output
-//.word 0x44a012fc
-//.word 0xcd62e69a
-//.word 0xe9a2e9e4
-//.word 0x6427fa49
-//.word 0x1b88f665
-//.word 0x22cdc1f4
-//.word 0xab5c5157
-//.word 0x196b15db
-//.word 0xa3905b99
-//.word 0xc460bf69
-//.word 0x0711797e
-//.word 0xa556fcf4
-//.word 0xb2550539
-//.word 0x151f80ee
-//.word 0xb522fbc0
-//.word 0x0450c723
-//// SHA512LongMsgvector_14
-//// vector length
-//.word 0x00002F50
-//// input message
-//.word 0xcb7e0a28
-//.word 0x78bbccbb
-//.word 0x7dbdd8a2
-//.word 0xe2791ea2
-//.word 0xaeee73c9
-//.word 0x09b5d9a1
-//.word 0x9eda01aa
-//.word 0x43ea0e07
-//.word 0xdc4d9c78
-//.word 0x7cd60188
-//.word 0xce99d208
-//.word 0xb4fdaabb
-//.word 0x2d122653
-//.word 0x7c24349c
-//.word 0x87908ef8
-//.word 0x7dd6810b
-//.word 0xbbf0f3b7
-//.word 0xf1e2a44b
-//.word 0x8093b4f7
-//.word 0x27db6684
-//.word 0xdfdd2341
-//.word 0x0397c241
-//.word 0xb4b706c3
-//.word 0x7cb068f2
-//.word 0x310e17cf
-//.word 0x1d063e6b
-//.word 0x5b528559
-//.word 0x843cda63
-//.word 0x8cf8717c
-//.word 0xe63609f6
-//.word 0xeff872f5
-//.word 0x89a14c24
-//.word 0x064f11a6
-//.word 0x496b5650
-//.word 0x277f4d15
-//.word 0x13478fc1
-//.word 0xfb0a18eb
-//.word 0x6d2a9324
-//.word 0xfefbd975
-//.word 0xecd1b409
-//.word 0x025de826
-//.word 0xbc397462
-//.word 0xacc11513
-//.word 0x1c250c07
-//.word 0xf5bc2175
-//.word 0xe09be834
-//.word 0xaa67432b
-//.word 0xed672809
-//.word 0xeddda436
-//.word 0xc0972009
-//.word 0xb2c1e43b
-//.word 0xe7fdd99b
-//.word 0x42b69304
-//.word 0x86b08e8c
-//.word 0xbbe4b8ff
-//.word 0xd48c308c
-//.word 0x8e7a4ebd
-//.word 0x9bade3ad
-//.word 0x0026c275
-//.word 0xbcf87fe7
-//.word 0xaa9f767f
-//.word 0xa8920f96
-//.word 0xf91c41d9
-//.word 0xe86755fa
-//.word 0xaedaeda5
-//.word 0x96a444b6
-//.word 0x5f99b7a9
-//.word 0xe23e8551
-//.word 0xf51fd3cd
-//.word 0x8e69f3b9
-//.word 0x2cb4e5a1
-//.word 0x72211ebb
-//.word 0x15a589d5
-//.word 0xf9a4cc8c
-//.word 0x97c2ccbf
-//.word 0xa2f67343
-//.word 0xeae0b1d8
-//.word 0x805cc05c
-//.word 0x1b57ad3f
-//.word 0xbae11437
-//.word 0x8b842b35
-//.word 0x0cd40197
-//.word 0x7048089f
-//.word 0x4448d224
-//.word 0x52871887
-//.word 0xc69300e9
-//.word 0x8fab9f9b
-//.word 0x08d0bdd6
-//.word 0xd81ed9ad
-//.word 0x175d6d3f
-//.word 0xb2d47431
-//.word 0x105d285c
-//.word 0xf5bf10c2
-//.word 0xa7373ac7
-//.word 0x5058c69e
-//.word 0xa416a401
-//.word 0xc31d9d25
-//.word 0x616798ed
-//.word 0x240d165e
-//.word 0x4d5d0053
-//.word 0x9b2ea271
-//.word 0x6c70f75e
-//.word 0x2607272e
-//.word 0xd5da4e1e
-//.word 0x16267f85
-//.word 0x33190907
-//.word 0x8f9cf80c
-//.word 0x4570df70
-//.word 0x0c7cd57d
-//.word 0x5e65be16
-//.word 0xd960cc34
-//.word 0xe5444597
-//.word 0x97e486b5
-//.word 0xd59b48f7
-//.word 0xbb282224
-//.word 0x3ebc4f1d
-//.word 0x0f52b2cc
-//.word 0xc23f1757
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
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-//// expected output
-//.word 0xb4641572
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-//// SHA512LongMsgvector_15
-//// vector length
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-//// input message
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-//.word 0x0a83f7b1
-//.word 0x35c23b21
-//.word 0x6eb3d458
-//.word 0x086f445d
-//.word 0x366cf979
-//.word 0x7051cfa6
-//.word 0x1908d745
-//.word 0x5e15570f
-//.word 0x6127114e
-//.word 0x97edc84d
-//.word 0x6e2b010d
-//.word 0x340d0739
-//.word 0x34bb315c
-//.word 0x222d6752
-//.word 0xb941e3fd
-//.word 0xa20b3539
-//.word 0x986c8a11
-//.word 0xcae62d33
-//.word 0x80ae4ea1
-//.word 0x020303aa
-//.word 0xb6bf8c19
-//.word 0x882cdbac
-//.word 0x8e1854c7
-//.word 0xec2cd16a
-//.word 0xf679e961
-//.word 0x955472ba
-//.word 0xec64447c
-//.word 0x3bf94096
-//.word 0x039f9116
-//.word 0x6bf4329b
-//.word 0xe2b6b00d
-//.word 0x0620328b
-//.word 0xc477b6a5
-//.word 0xc1e09dcc
-//.word 0xf9746a06
-//.word 0xa796c7e7
-//.word 0x6484c9bc
-//.word 0x922d7409
-//.word 0xfb438236
-//.word 0xb6906085
-//.word 0x4b8d7a47
-//.word 0x1631b850
-//.word 0xf10748a8
-//.word 0x0d839f83
-//.word 0x21800000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00003268
-//// expected output
-//.word 0xa1a60fb8
-//.word 0x9d420fc8
-//.word 0x4c2caab2
-//.word 0x4079d75d
-//.word 0xdca9a467
-//.word 0x6eb8677b
-//.word 0x3d64038f
-//.word 0xba871120
-//.word 0x3a459bc2
-//.word 0x6259112c
-//.word 0x64138d4c
-//.word 0xd1ebba40
-//.word 0x6720cf29
-//.word 0xcd1e4ac3
-//.word 0x5e35be50
-//.word 0x464ef1df
-//// SHA512LongMsgvector_16
-//// vector length
-//.word 0x00003580
-//// input message
-//.word 0x1cecb230
-//.word 0xf8c80f87
-//.word 0xe65e6a5c
-//.word 0xf1de4301
-//.word 0xb2cf1ac7
-//.word 0xc4ae81c4
-//.word 0x78d875d3
-//.word 0xc9aaeedb
-//.word 0x92e6b555
-//.word 0xfe587608
-//.word 0x40ba1617
-//.word 0x85d6463e
-//.word 0x27ea5959
-//.word 0x24505226
-//.word 0xce5e424b
-//.word 0xc48cd19b
-//.word 0x20d41a95
-//.word 0xf25fbc2d
-//.word 0xee5d2dd0
-//.word 0x613552a2
-//.word 0x6ade4d0a
-//.word 0x668c9770
-//.word 0xac904e45
-//.word 0x7b79d044
-//.word 0x308088f8
-//.word 0xbc23087f
-//.word 0x560f588d
-//.word 0x6d438eb4
-//.word 0xe1739fe2
-//.word 0x72aa752b
-//.word 0x793442c8
-//.word 0xd6bb1360
-//.word 0x29b0a887
-//.word 0x45ed8385
-//.word 0xe1983f58
-//.word 0x914a23fc
-//.word 0xf570f7e9
-//.word 0x30f216de
-//.word 0x9c13c5dd
-//.word 0xbd99c376
-//.word 0x732d2249
-//.word 0x730454c7
-//.word 0xf7bf8938
-//.word 0xb5903902
-//.word 0x0e9ffc28
-//.word 0x89aca211
-//.word 0x7ff5808b
-//.word 0x185a080f
-//.word 0x76bf9d47
-//.word 0x2fb2a5cd
-//.word 0x014ddf36
-//.word 0xc15ef64f
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-//.word 0x631f404c
-//.word 0x89a21ada
-//.word 0xcf4709b2
-//.word 0x992dc187
-//.word 0x623d9b20
-//.word 0x650be858
-//.word 0x9dfc856a
-//.word 0xf0aeb06b
-//.word 0xa8941918
-//.word 0x22e13cd2
-//.word 0xcaa8efe7
-//.word 0x47413713
-//.word 0xf2ee6047
-//.word 0x8dbe4da8
-//.word 0x32b20cdb
-//.word 0x891fad80
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-//.word 0x66c8b42b
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-//.word 0xdc76b82d
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-//.word 0x01cf932d
-//.word 0x58e16003
-//.word 0x64518c44
-//.word 0x942813cb
-//.word 0xe8b41705
-//.word 0xa67331f9
-//.word 0x4f330585
-//.word 0xd17619ea
-//.word 0xfe1be78b
-//.word 0x3d3b30f1
-//.word 0x7f529413
-//.word 0x759f60d4
-//.word 0x01cda7ce
-//.word 0xead2944e
-//.word 0xd318fe9f
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-//.word 0xb911d0b0
-//.word 0x672e481c
-//.word 0xe8a24651
-//.word 0xff73cd12
-//.word 0xf8109af9
-//.word 0x987cb8b8
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-//.word 0xb53abd76
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-//.word 0xdfbdf63e
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-//.word 0x174c1ec2
-//.word 0x3a9957fc
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-//.word 0x81e60d05
-//.word 0x83ccdb5d
-//.word 0x753fdd82
-//.word 0xc8421d25
-//.word 0xf6b801e4
-//.word 0xb5ca21cb
-//.word 0x7088561a
-//.word 0xf7d31348
-//.word 0x767af949
-//.word 0xa4a3a50d
-//.word 0x3c6dcd49
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-//.word 0x1ed4f826
-//.word 0x7bd0fd64
-//.word 0x173666a0
-//.word 0x425c3898
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-//.word 0xba8bedb8
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-//.word 0xc0480155
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-//.word 0x67876e56
-//.word 0x7296f001
-//.word 0x269bbe3c
-//.word 0xbe360a4b
-//.word 0x025b016d
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-//.word 0x693ba057
-//.word 0x3388fabf
-//.word 0xd16a668e
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-//.word 0x0a74e3ff
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-//.word 0x0f445876
-//.word 0xc0e2ac2e
-//.word 0xb003b31a
-//.word 0x2c11408e
-//.word 0xc4b079e4
-//.word 0xfb9e307c
-//.word 0x43dd7000
-//.word 0x281555ed
-//.word 0xcb34214f
-//.word 0x92578dcc
-//.word 0x1eed5de3
-//.word 0x7d193776
-//.word 0xa159b586
-//.word 0x1166b93f
-//.word 0xdf5b0134
-//.word 0xda18fbeb
-//.word 0x04e9da9c
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-//.word 0x638f1fa3
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-//.word 0xc834be22
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-//.word 0xa4aca9e6
-//.word 0x47ce6976
-//.word 0x693122e1
-//.word 0x9e6d1f1b
-//.word 0x9bb1dd7b
-//.word 0xebae62c0
-//.word 0xe4b0d052
-//.word 0xda0e3aca
-//.word 0x92c5b6b3
-//.word 0xf960b492
-//.word 0x161b8e25
-//.word 0x3e4760e9
-//.word 0x87f019de
-//.word 0x7fbed28e
-//.word 0x1d195f4c
-//.word 0xf79024ba
-//.word 0xb67c2a8e
-//.word 0xc7e07395
-//.word 0x54948af8
-//.word 0x73a35dbe
-//.word 0x9df14f92
-//.word 0x61218ac6
-//.word 0x59b59299
-//.word 0x5e7720b5
-//.word 0xf8182dfc
-//.word 0x18184d84
-//.word 0x0ae53ee0
-//.word 0xa547c1a2
-//.word 0xc5fba81d
-//.word 0xfb9f3170
-//.word 0x82ce92c0
-//.word 0x758bd5c4
-//.word 0x40e3e687
-//.word 0x55ceeb69
-//.word 0x2057d367
-//.word 0x3cfc329d
-//.word 0xe7584c09
-//.word 0xb3ff6f92
-//.word 0x7faa8749
-//.word 0xa694ecee
-//.word 0x76237eb6
-//.word 0xe4cbf44b
-//.word 0x7d307115
-//.word 0xa08a58b8
-//.word 0xeb4e62de
-//.word 0xf30bee36
-//.word 0x389198bd
-//.word 0x58590c3c
-//.word 0x82211d11
-//.word 0x2ed71133
-//.word 0x0bb83f71
-//.word 0x39b9ddfa
-//.word 0xb9261322
-//.word 0x22895363
-//.word 0x95cdeda2
-//.word 0xf2a3deb4
-//.word 0x4c25e921
-//.word 0x9bb9ea28
-//.word 0xb1396603
-//.word 0x7051666c
-//.word 0x3928865f
-//.word 0xa7424922
-//.word 0x7ea5af83
-//.word 0xde3a0a61
-//.word 0xbd770d6d
-//.word 0x943b2632
-//.word 0x57f90e53
-//.word 0xab199e14
-//.word 0x549be41c
-//.word 0xecfe767a
-//.word 0xdb6006e5
-//.word 0x83e63748
-//.word 0xbb5eaf7e
-//.word 0x7f236d59
-//.word 0xe5415dea
-//.word 0x53da2afc
-//.word 0xf0c954e2
-//.word 0x58848273
-//.word 0x94471952
-//.word 0x496f0d73
-//.word 0x2f24f8da
-//.word 0xc53a69a6
-//.word 0x44597e4f
-//.word 0xd15cb52c
-//.word 0xf6f8ff38
-//.word 0x539e1615
-//.word 0x91a21151
-//.word 0x989c36e9
-//.word 0x020f0f0b
-//.word 0xcf48c020
-//.word 0x5a89970a
-//.word 0x8b67e5aa
-//.word 0x4f710ca6
-//.word 0x4512da69
-//.word 0xbbb9156b
-//.word 0xd83657b2
-//.word 0x1a681c99
-//.word 0x04151ad0
-//.word 0x1019d1a4
-//.word 0xebc36280
-//.word 0xe17ca4b4
-//.word 0x96a97576
-//.word 0xf8d34e26
-//.word 0x71051bd7
-//.word 0x6176490a
-//.word 0xcb6820bc
-//.word 0x4f5053a4
-//.word 0x5837d5b6
-//.word 0x9660efeb
-//.word 0xaf2b9044
-//.word 0x3139e40d
-//.word 0xccd1275f
-//.word 0xbe83bce8
-//.word 0x8e0b79ee
-//.word 0xfd784692
-//.word 0x3a8de652
-//.word 0x556714d2
-//.word 0xf660d2dc
-//.word 0x4f34fea5
-//.word 0x4f622652
-//.word 0x18d59dba
-//.word 0xb4c4ce6e
-//.word 0x03d7d1f7
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-//.word 0x05d73cf2
-//.word 0xd410e445
-//.word 0x380ac478
-//.word 0x6380beb8
-//.word 0x59b51509
-//.word 0xa55cc742
-//.word 0x4ab51d59
-//.word 0xfcfa80e1
-//.word 0x90f98ed1
-//.word 0xb2026d87
-//.word 0xd6035f0d
-//.word 0x71f2979a
-//.word 0x686b4c5c
-//.word 0xc89b0b74
-//.word 0xb95c5143
-//.word 0xada159e4
-//.word 0xdd1533f9
-//.word 0xf6ff16ab
-//.word 0x0f69f7ec
-//.word 0xdf815aff
-//.word 0x2d3f693b
-//.word 0x8748430c
-//.word 0x3713963a
-//.word 0x734a706e
-//.word 0xd47352f2
-//.word 0x0acf87b8
-//.word 0xcd82b39e
-//.word 0x16f5aff0
-//.word 0x9079942e
-//.word 0x492d1610
-//.word 0xae2114c8
-//.word 0xb6bb6c87
-//.word 0x5d5a1442
-//.word 0x543a67b6
-//.word 0xf798bcaa
-//.word 0x7f163d74
-//.word 0x7960f7be
-//.word 0x77102d8a
-//.word 0x05cff274
-//.word 0xdebdf737
-//.word 0x6014a173
-//.word 0x3e085eae
-//.word 0x75f13a98
-//.word 0x81abad93
-//.word 0xd03db772
-//.word 0x77ba2f81
-//.word 0x246559c6
-//.word 0x5318b687
-//.word 0xc5e7200d
-//.word 0x2e0016a7
-//.word 0x2fd554f1
-//.word 0x837ea655
-//.word 0x7d58ffd3
-//.word 0xb2f3c5fe
-//.word 0xf32b7047
-//.word 0x7e94537e
-//.word 0x741cb996
-//.word 0x8eeb34a9
-//.word 0x0c8e323b
-//.word 0xef55d1c3
-//.word 0x68f9f568
-//.word 0x90829708
-//.word 0x5968607e
-//.word 0xc5f97625
-//.word 0x56fa9698
-//.word 0xc59163bc
-//.word 0xf763fd01
-//.word 0x2cf9d6e4
-//.word 0x7a68c1b9
-//.word 0x7a314ca7
-//.word 0x416650f4
-//.word 0x80000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00003580
-//// expected output
-//.word 0x3ed79e61
-//.word 0xd5843b36
-//.word 0xb6228023
-//.word 0x670b3332
-//.word 0x08cf9bf5
-//.word 0x56b1d6fc
-//.word 0x54e95808
-//.word 0xdfac2402
-//.word 0xae06fb74
-//.word 0x9e45883f
-//.word 0x21211ff4
-//.word 0x1b28cced
-//.word 0x38d70639
-//.word 0x0a398afa
-//.word 0x8f5eee76
-//.word 0x0da041f2
-//// SHA512LongMsgvector_17
-//// vector length
-//.word 0x00003898
-//// input message
-//.word 0x1297bed1
-//.word 0xf0bd4980
-//.word 0x3921a12a
-//.word 0x636f92fe
-//.word 0x2d7a7a74
-//.word 0x84884e3b
-//.word 0xa8f0dd73
-//.word 0x8be8591d
-//.word 0x7a9813d0
-//.word 0xfe7386ad
-//.word 0x05c69795
-//.word 0x3d911b99
-//.word 0xc1979ab1
-//.word 0xf7b152b1
-//.word 0xb8677f7a
-//.word 0xb2c1da6d
-//.word 0x0b5b6026
-//.word 0x47b85466
-//.word 0x6cd88750
-//.word 0x640dd7d9
-//.word 0xa20af67a
-//.word 0x093d6d27
-//.word 0x095fe085
-//.word 0x0b499358
-//.word 0x0f092d3a
-//.word 0x9335bc93
-//.word 0xb77ffac5
-//.word 0xa08acfa7
-//.word 0x1afc1635
-//.word 0x81d5a486
-//.word 0xe1ff86fe
-//.word 0x5c258bc4
-//.word 0xccc90376
-//.word 0xaa91c51c
-//.word 0x2fe2775b
-//.word 0xb8b009ec
-//.word 0x6f95834c
-//.word 0x282001b4
-//.word 0x896ffb4b
-//.word 0x6e00ca9b
-//.word 0x8bc46841
-//.word 0x547578e9
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-//.word 0x76298f8e
-//.word 0xeafcc425
-//.word 0xc6c78b9a
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-//.word 0x9421e703
-//.word 0x5889dbe3
-//.word 0xc07eaf8a
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-//.word 0xd35a612a
-//.word 0x23714a20
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-//// expected output
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-//// SHA512LongMsgvector_18
-//// vector length
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00003BB0
-//// expected output
-//.word 0xa163a713
-//.word 0x6bcc9258
-//.word 0x9303cb15
-//.word 0xe26bc6ba
-//.word 0x7abd91b8
-//.word 0xed194e2a
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-//.word 0x6aa3b964
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-//// SHA512LongMsgvector_19
-//// vector length
-//.word 0x00003EC8
-//// input message
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00003EC8
-//// expected output
-//.word 0x0a6bd4a3
-//.word 0xbe10c690
-//.word 0xba358fd4
-//.word 0xabe6bb3b
-//.word 0x05c6e747
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-//.word 0xe18a9c45
-//// SHA512LongMsgvector_20
-//// vector length
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-//// input message
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-//.word 0x93ae387b
-//.word 0xbebe94fd
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-//.word 0x7142f7cd
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-//.word 0x84bbf321
-//.word 0xc347ad14
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-//.word 0xa0c6f109
-//.word 0xaaf7b01a
-//.word 0xcdd19f14
-//.word 0xc95db5e1
-//.word 0x71796aeb
-//.word 0x177acadf
-//.word 0x4516c8b1
-//.word 0xae82d4e0
-//.word 0x63d7b0fb
-//.word 0x4aba7f64
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-//.word 0xe49b95b9
-//.word 0xc13f3379
-//.word 0xf19c981e
-//.word 0xcafee610
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-//.word 0x7fce6a70
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-//.word 0xad7e6fdc
-//.word 0x85ac08ec
-//.word 0x0367750a
-//.word 0xbd3e1ad8
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-//.word 0x4d4e2973
-//.word 0xba622036
-//.word 0xb9d1d35c
-//.word 0xc37fa590
-//.word 0x670fc024
-//.word 0x3f03a857
-//.word 0x242516d3
-//.word 0x9e26037a
-//.word 0x9e860362
-//.word 0x70b3d41e
-//.word 0xeb753740
-//.word 0xeb89fe1b
-//.word 0x018d67ce
-//.word 0x681ca87e
-//.word 0x3b39cbe2
-//.word 0xe6f1bc05
-//.word 0xdb3ca147
-//.word 0x862569a5
-//.word 0x822aa83b
-//.word 0x0de6a207
-//.word 0x80000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000041E0
-//// expected output
-//.word 0xca2928c7
-//.word 0x468e8e42
-//.word 0x1b00fb12
-//.word 0x8b1c114a
-//.word 0x983745f9
-//.word 0xb20521e8
-//.word 0xc8954a68
-//.word 0x178ccefc
-//.word 0x2e81d0f0
-//.word 0xc4925515
-//.word 0x7e9b86cf
-//.word 0x09e59e18
-//.word 0x7ad938ff
-//.word 0xd35664f9
-//.word 0xa3ddb471
-//.word 0xb85ee250
-//// SHA512LongMsgvector_21
-//// vector length
-//.word 0x000044F8
-//// input message
-//.word 0xedf5557e
-//.word 0x15473b74
-//.word 0x7a819398
-//.word 0xc9ac1459
-//.word 0xffdb4c97
-//.word 0xd0072c12
-//.word 0x4a16c723
-//.word 0xb63d57aa
-//.word 0xbf888147
-//.word 0xd6b7dacd
-//.word 0xd44ca9f3
-//.word 0xe1e2ef4d
-//.word 0x95c0a47b
-//.word 0x5eae44a1
-//.word 0x22088a17
-//.word 0x25107b61
-//.word 0x2c88a761
-//.word 0xe381accb
-//.word 0x7c6efbda
-//.word 0x997cdf41
-//.word 0x6c26bb65
-//.word 0x1c0393c9
-//.word 0x6be3cdc9
-//.word 0x971b398c
-//.word 0x7d1d5034
-//.word 0x044cb957
-//.word 0xb90e12b3
-//.word 0xb722ec1d
-//.word 0xca3417bb
-//.word 0xd4ae2173
-//.word 0x6fd219a3
-//.word 0xd3069813
-//.word 0xfb6e0328
-//.word 0x03c00a5a
-//.word 0xd55474e7
-//.word 0x047b1fc9
-//.word 0xf81242e6
-//.word 0x4c57f688
-//.word 0x74fbf50c
-//.word 0xa378a1de
-//.word 0xeba448a5
-//.word 0xa786a6ba
-//.word 0x1669abdf
-//.word 0x48307f2e
-//.word 0x3ee9c44f
-//.word 0x4da51bee
-//.word 0xc386e96c
-//.word 0xcd195bd5
-//.word 0x98e6a713
-//.word 0xb7469561
-//.word 0xc5753f02
-//.word 0x4be81432
-//.word 0xe3e1235d
-//.word 0x9e40978f
-//.word 0xa49c7d2c
-//.word 0x1a92cee1
-//.word 0x495da9da
-//.word 0xfca7e035
-//.word 0x299fb6b7
-//.word 0xd44ce7be
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-//.word 0x996dba22
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-//.word 0x9fa0cd68
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-//.word 0xb486f2b0
-//.word 0x5fcd89f2
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-//.word 0x8aa625e4
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-//.word 0xa37f74a6
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-//.word 0xd9150ade
-//.word 0x3bce83c7
-//.word 0xc6992135
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-//.word 0xf2444de8
-//.word 0xe8a1b765
-//.word 0x7b0574ae
-//.word 0x5c6b6780
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000044F8
-//// expected output
-//.word 0xba3ad050
-//.word 0xbcbd2feb
-//.word 0xe8989cd0
-//.word 0xade13530
-//.word 0x3de9d9a4
-//.word 0x19daaa64
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-//.word 0xd637a1a8
-//.word 0x03d2de1f
-//.word 0xf35b0d42
-//.word 0x98519cbc
-//// SHA512LongMsgvector_22
-//// vector length
-//.word 0x00004810
-//// input message
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-//.word 0xcd412d3e
-//.word 0x7ca2021b
-//.word 0x177aba71
-//.word 0xd92cfcde
-//.word 0x347171f9
-//.word 0xb7a8c841
-//.word 0x356dfe54
-//.word 0x246cdc62
-//.word 0x4377c1e0
-//.word 0x80d7a181
-//.word 0x18e04e62
-//.word 0x00c9f684
-//.word 0x84baed80
-//.word 0x2e25ad76
-//.word 0xe95a1c47
-//.word 0x66560d04
-//.word 0xbfdc08a6
-//.word 0x5ac84eff
-//.word 0x119f18f0
-//.word 0x8f6a20dd
-//.word 0xfdc5625e
-//.word 0xdf338000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00004810
-//// expected output
-//.word 0xa86c70c2
-//.word 0x063f12bd
-//.word 0xdf997c91
-//.word 0xd1ebb57f
-//.word 0x5c55ca67
-//.word 0x614f397c
-//.word 0x1c52a87b
-//.word 0x0621fc43
-//.word 0x78c2eeb0
-//.word 0x7732e5eb
-//.word 0x0fbb4b3c
-//.word 0x1fdde87e
-//.word 0x9ed71b50
-//.word 0xf83eeb02
-//.word 0xcba03baf
-//.word 0xedc84764
-//// SHA512LongMsgvector_23
-//// vector length
-//.word 0x00004B28
-//// input message
-//.word 0xd99f8229
-//.word 0x6f56251e
-//.word 0x365764e1
-//.word 0xacf4d207
-//.word 0x28f89f54
-//.word 0x6cebc621
-//.word 0x7d918700
-//.word 0xb3b418a3
-//.word 0x0c2398fa
-//.word 0xc5fb449c
-//.word 0x2c25ed68
-//.word 0xb020aa6c
-//.word 0x3a01ca06
-//.word 0xc0b80c48
-//.word 0x179413a1
-//.word 0x080a14ba
-//.word 0xa7b2d29f
-//.word 0xe092cc1f
-//.word 0x539fb475
-//.word 0x62812428
-//.word 0x87978d2f
-//.word 0xeb3b7059
-//.word 0x3547d0ec
-//.word 0xa0d7e78c
-//.word 0x5151185f
-//.word 0xe7a3256f
-//.word 0x53cca250
-//.word 0xea9ea902
-//.word 0xb8c2d018
-//.word 0x18fc581a
-//.word 0x82b0a729
-//.word 0xa3a6f8e1
-//.word 0xb30a5284
-//.word 0x03b7b654
-//.word 0xd5b59d40
-//.word 0x71ffa2c3
-//.word 0x758a7b0a
-//.word 0x6d842d55
-//.word 0xa3d9809f
-//.word 0x39fcb181
-//.word 0x74e46854
-//.word 0x5b55e996
-//.word 0x81608e8e
-//.word 0x1f2d7533
-//.word 0x65f8764b
-//.word 0x125a58d0
-//.word 0x43ca4497
-//.word 0x88637934
-//.word 0x3de84218
-//.word 0x180525fc
-//.word 0xfed75e83
-//.word 0x1baf8c1a
-//.word 0x3113a923
-//.word 0x30063f54
-//.word 0x088ad959
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-//.word 0xb61cc817
-//.word 0x614fd34f
-//.word 0xf522f365
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-//.word 0xebb88476
-//.word 0xd19a5fa5
-//.word 0x44812ee8
-//.word 0xa909b053
-//.word 0xd488738e
-//.word 0xd994447e
-//.word 0x1ec5ea21
-//.word 0xb5bb14ba
-//.word 0xe9638f2f
-//.word 0x1777bcaf
-//.word 0xc0444297
-//.word 0xdbb00097
-//.word 0x707b4611
-//.word 0x62c544c1
-//.word 0x8dd1c2a3
-//.word 0x10081211
-//.word 0xec41432c
-//.word 0xcf3f987e
-//.word 0x2a7b38de
-//.word 0x89242793
-//.word 0x246575bc
-//.word 0xb1e6b6ef
-//.word 0x7d95b220
-//.word 0xbba65dc4
-//.word 0x1c800000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00004B28
-//// expected output
-//.word 0xdb7e2ece
-//.word 0x42b5186f
-//.word 0x84e6c140
-//.word 0x7593a9b9
-//.word 0xe2971aba
-//.word 0x7122b816
-//.word 0x7b21b31e
-//.word 0xa5f0bd21
-//.word 0xff754e4f
-//.word 0xefba71c9
-//.word 0x327eeb19
-//.word 0x625702b6
-//.word 0x4426acce
-//.word 0x7fd88467
-//.word 0xadc3d2b3
-//.word 0x8a861abd
-//// SHA512LongMsgvector_24
-//// vector length
-//.word 0x00004E40
-//// input message
-//.word 0x1dc9e32a
-//.word 0xc4176f64
-//.word 0xbd78a6ed
-//.word 0xd651ebee
-//.word 0xa3ba85df
-//.word 0xcd8298a8
-//.word 0xad725406
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-//.word 0x7e3acbbc
-//.word 0x2f7282bc
-//.word 0xfddd042c
-//.word 0x08ea9690
-//.word 0xd5da00d9
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-//.word 0xf3e72217
-//.word 0x770ce295
-//.word 0x0b6cb290
-//.word 0x13a64a38
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-//.word 0x7cfd0e08
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-//.word 0x21e39d61
-//.word 0x6ac019f3
-//.word 0xe9e6016f
-//.word 0x16bcad1f
-//.word 0x24751472
-//.word 0xd9953d9e
-//.word 0x9cb0f789
-//.word 0xd075caea
-//.word 0x60ec2dab
-//.word 0x9bfcf993
-//.word 0x43301e21
-//.word 0xe0bb95bb
-//.word 0x5ab99608
-//.word 0xc7b70a9a
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-//.word 0x7decebfa
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-//.word 0x2af59f6b
-//.word 0xdc7b78df
-//.word 0xc5372772
-//.word 0x6b6388e1
-//.word 0xad339196
-//.word 0x57168815
-//.word 0xf4397396
-//.word 0xe34cd1f3
-//.word 0xad8a87c5
-//.word 0x96f31dca
-//.word 0x72dc2a8b
-//.word 0xbaaa0d3b
-//.word 0xdfdbdee1
-//.word 0xde46a5ba
-//.word 0x15a3c9d8
-//.word 0x554dcb10
-//.word 0x38473313
-//.word 0xb57dcbdb
-//.word 0xf14d0c49
-//.word 0x5846d60c
-//.word 0xed3064c4
-//.word 0xde4c7e67
-//.word 0x5cddf0e4
-//.word 0xa9e63c07
-//.word 0x73368c9d
-//.word 0x60a2ead8
-//.word 0xea92b3f5
-//.word 0x6dbf491b
-//.word 0x7e3a0987
-//.word 0x7fb17de6
-//.word 0x70eed202
-//.word 0x08a08ca1
-//.word 0x055e78aa
-//.word 0x80000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00004E40
-//// expected output
-//.word 0x99820341
-//.word 0x517e3140
-//.word 0x475fc1a9
-//.word 0xe57a7f8b
-//.word 0x8bb85293
-//.word 0xff7ccee2
-//.word 0x37542e72
-//.word 0x9531fe9d
-//.word 0xaeeed96c
-//.word 0x3f41d87f
-//.word 0xaaae3a7c
-//.word 0x6ecf3088
-//.word 0x42b2e08a
-//.word 0xeb17e77a
-//.word 0x64484f41
-//.word 0xc60cd93d
-//// SHA512LongMsgvector_25
-//// vector length
-//.word 0x00005158
-//// input message
-//.word 0xf72b6620
-//.word 0xe71f7b50
-//.word 0x486d868e
-//.word 0xaa2cd34b
-//.word 0xcfef394b
-//.word 0x7447944f
-//.word 0x6f8a75f1
-//.word 0xfad317cf
-//.word 0x4f4a95eb
-//.word 0x75a65b52
-//.word 0x59f0dafc
-//.word 0x208981f4
-//.word 0xbc6ee8b8
-//.word 0xbdbb4ee3
-//.word 0x6a6e4509
-//.word 0x116eace3
-//.word 0x9bccdeac
-//.word 0x634829ca
-//.word 0x491782b1
-//.word 0x02e37605
-//.word 0xb21464fe
-//.word 0xbc4eea11
-//.word 0xd83a9dcd
-//.word 0x678afd03
-//.word 0x0437a829
-//.word 0x5c0dcd00
-//.word 0x3f6ae475
-//.word 0xf7439cc5
-//.word 0xd86715e5
-//.word 0x18085021
-//.word 0xe177e403
-//.word 0xa52ff276
-//.word 0xb2155a2b
-//.word 0x06fe2f3c
-//.word 0x64726910
-//.word 0xa7b0da7e
-//.word 0x57f16435
-//.word 0x7af1685b
-//.word 0xacac8174
-//.word 0x72657386
-//.word 0xcced5e7a
-//.word 0x092238c6
-//.word 0xdfb67949
-//.word 0xbb321876
-//.word 0x563ab7b5
-//.word 0x89121b06
-//.word 0x6261dee8
-//.word 0x77356879
-//.word 0x7a481bde
-//.word 0x0e82cee5
-//.word 0xd9be7de9
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-//.word 0xfec8772e
-//.word 0xee724f6c
-//.word 0x2a1f6227
-//.word 0x5ca6b998
-//.word 0xe6adf91f
-//.word 0xbd24dae3
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-//.word 0x9db49764
-//.word 0xcaa4a580
-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00005158
-//// expected output
-//.word 0xc1d54f9d
-//.word 0x273a339c
-//.word 0xd1750ffe
-//.word 0x36b10b1b
-//.word 0x9a60c9be
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-//.word 0x84efc1ee
-//.word 0x24325539
-//// SHA512LongMsgvector_26
-//// vector length
-//.word 0x00005470
-//// input message
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-//.word 0xb79ae695
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-//.word 0x04643c3d
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-//.word 0xd6da1213
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-//.word 0x83dde8f0
-//.word 0x12f08000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00005470
-//// expected output
-//.word 0xbc393bc5
-//.word 0x50a3705f
-//.word 0xcd5828ea
-//.word 0x43b536f6
-//.word 0xb2de8426
-//.word 0xbb7d0857
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-//.word 0x8a3c27a9
-//.word 0x3096b4eb
-//.word 0xf7861843
-//.word 0xda5e4c31
-//.word 0xa43fd715
-//.word 0x5ce8c986
-//.word 0xecbb0397
-//.word 0x39ceeb04
-//// SHA512LongMsgvector_27
-//// vector length
-//.word 0x00005788
-//// input message
-//.word 0x02b74a2c
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-//.word 0x86887f52
-//.word 0xa287c7eb
-//.word 0xc788b39c
-//.word 0x95be7a50
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-//.word 0xb8cce647
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-//.word 0xb5214844
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-//.word 0x32c0eaa1
-//.word 0xcc8611f4
-//.word 0xb17d82e3
-//.word 0x64238f01
-//.word 0x7acf037e
-//.word 0xb7436655
-//.word 0x74847cc6
-//.word 0x43ea0f07
-//.word 0xd673ee37
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-//.word 0xaff3d0ec
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-//.word 0x5f618c29
-//.word 0xe917b31b
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-//// expected output
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-//.word 0x8c2f76d2
-//.word 0x55fc3243
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-//// SHA512LongMsgvector_28
-//// vector length
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-//// input message
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-//// expected output
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-//// SHA512LongMsgvector_31
-//// vector length
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-//// input message
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-//.word 0x00000000
-//.word 0x00000000
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-//// expected output
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-//.word 0xaba950b9
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-//// SHA512LongMsgvector_32
-//// vector length
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-//// input message
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-//// vector length
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00006A18
-//// expected output
-//.word 0x40180974
-//.word 0x93d3386e
-//.word 0x4adafea2
-//.word 0x0ca962c9
-//.word 0x925bd5dd
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-//.word 0x5ca8f1c9
-//.word 0xf802d965
-//// SHA512LongMsgvector_34
-//// vector length
-//.word 0x00006D30
-//// input message
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-//.word 0xb511e659
-//.word 0x1bb4c1c1
-//.word 0x389e7d5c
-//.word 0x3d4d74a8
-//.word 0x014dd3b4
-//.word 0xa34e56d8
-//.word 0x727953a3
-//.word 0x0904fa15
-//.word 0xbe04db0e
-//.word 0x3e83a907
-//.word 0x71d33d00
-//.word 0xa421ddb9
-//.word 0xe64dbf25
-//.word 0xb2fac91c
-//.word 0xcfe19b50
-//.word 0x756acf82
-//.word 0xb17d7ff6
-//.word 0x0a950824
-//.word 0x65170eb0
-//.word 0x26e3c19c
-//.word 0x98285ebd
-//.word 0x8f7cf86b
-//.word 0x4c2c787d
-//.word 0xa0d0e375
-//.word 0x5523dbf7
-//.word 0xc9126980
-//.word 0xdc13f954
-//.word 0x0cb8a6b8
-//.word 0xdf84b862
-//.word 0x82fd6b2e
-//.word 0xaf02f312
-//.word 0xd35fbc54
-//.word 0x719ff6fa
-//.word 0xc1225183
-//.word 0x9e6f05d4
-//.word 0x9fca1675
-//.word 0x830ad6fd
-//.word 0xd2a5abcb
-//.word 0xc10d12f7
-//.word 0x563fe488
-//.word 0xce98d9e8
-//.word 0x3ceb4a95
-//.word 0x72d23b18
-//.word 0x2441983b
-//.word 0x4b61bf77
-//.word 0xc89b3fac
-//.word 0x4af2df15
-//.word 0x7197e37a
-//.word 0x34b78aa7
-//.word 0x8098db1e
-//.word 0x21e4a109
-//.word 0xe645b572
-//.word 0x00317bb6
-//.word 0xac08af37
-//.word 0x125c6252
-//.word 0x6c8f3f91
-//.word 0x6aa41321
-//.word 0xd54f8d86
-//.word 0x744e428d
-//.word 0x2cfcf382
-//.word 0x6a2413a4
-//.word 0xc61384d6
-//.word 0xe0800000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00007048
-//// expected output
-//.word 0x858deb41
-//.word 0xf50d96ce
-//.word 0xc9a0850e
-//.word 0xd70b0d96
-//.word 0x207e6d5d
-//.word 0x8b3641fd
-//.word 0x09af5084
-//.word 0xd65a7c7b
-//.word 0x71fbb6fe
-//.word 0x04876ac7
-//.word 0x28750a54
-//.word 0x3ee31e94
-//.word 0xe388d42c
-//.word 0xa5aa2197
-//.word 0xfb006379
-//.word 0xdc67b423
-//// SHA512LongMsgvector_36
-//// vector length
-//.word 0x00007360
-//// input message
-//.word 0x2522cf92
-//.word 0xda7d8f15
-//.word 0x3dca86dd
-//.word 0x249aca30
-//.word 0x0b85697a
-//.word 0xfe796441
-//.word 0xba51fb5b
-//.word 0x0fa92b5f
-//.word 0x88f17659
-//.word 0x4ec1e2c2
-//.word 0x4a6c44af
-//.word 0x8ad8be48
-//.word 0xe68d877c
-//.word 0xe30beaf3
-//.word 0xd7619244
-//.word 0x4efb0469
-//.word 0xadbc6d70
-//.word 0x154d9e72
-//.word 0x8ab455c9
-//.word 0x5528be7e
-//.word 0xa6233901
-//.word 0x7eba5e1d
-//.word 0xcc2a3e2a
-//.word 0xd7b3ec85
-//.word 0xdba93d3d
-//.word 0xf7c8cb0f
-//.word 0x46c84095
-//.word 0x4d31d1ba
-//.word 0x95710871
-//.word 0x982bc7a7
-//.word 0xe2d38a75
-//.word 0x7078ec9b
-//.word 0x5ce06d2a
-//.word 0xbcda7280
-//.word 0xc7d08d79
-//.word 0x399cffe4
-//.word 0xf99c7b34
-//.word 0xf9092d78
-//.word 0x5e84fb8e
-//.word 0xe2f20b93
-//.word 0x768a859d
-//.word 0x2b2c9aad
-//.word 0x52f5c5df
-//.word 0xe21050e4
-//.word 0x1bcf1bb2
-//.word 0x69fa997a
-//.word 0x8b671bdb
-//.word 0xf4ca5155
-//.word 0x72cf0d00
-//.word 0x0d664b7e
-//.word 0x325e6f2e
-//.word 0x1136cda2
-//.word 0x43306e54
-//.word 0xb0a61194
-//.word 0xb0a171c5
-//.word 0x70a8c6c9
-//.word 0x98d68eba
-//.word 0x2a308ddb
-//.word 0xad3513ce
-//.word 0x8cb67d07
-//.word 0xb9e7fe80
-//.word 0x95b7a0ae
-//.word 0x145d85b5
-//.word 0x1c3373d8
-//.word 0x2fc89033
-//.word 0x4a3069ac
-//.word 0x0d9f3927
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-//.word 0xc41d539f
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-//.word 0x88619761
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-//.word 0xbda56857
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-//.word 0xfffb4d37
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-//.word 0xd35dcff4
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-//.word 0x6df5b49f
-//.word 0xd9e58782
-//.word 0x5831822c
-//.word 0xccc53aeb
-//.word 0x168b3e25
-//.word 0xdc23f9a4
-//.word 0x89dada32
-//.word 0x95dab266
-//.word 0x069e5dbd
-//.word 0x37a9a4ec
-//.word 0xd8786275
-//.word 0x36b5e679
-//.word 0xbcad99cd
-//.word 0xba04e050
-//.word 0x66a7447b
-//.word 0x2103d139
-//.word 0xfb75bbf9
-//.word 0x78014802
-//.word 0x9546e907
-//.word 0x06b1aafc
-//.word 0xc2f2cd28
-//.word 0xc1acb27a
-//.word 0x0471fb20
-//.word 0xd7eded56
-//.word 0x5361187c
-//.word 0x26543a6c
-//.word 0x9785610a
-//.word 0xc423501d
-//.word 0x2e40245d
-//.word 0x788437cc
-//.word 0x6c1e454a
-//.word 0x3f00cd64
-//.word 0x164cba6e
-//.word 0xc80943d1
-//.word 0xe61b10a5
-//.word 0xf9729e83
-//.word 0x0a81e494
-//.word 0x68f237ee
-//.word 0xa5986b21
-//.word 0xe2a53b0c
-//.word 0x4c1deaf6
-//.word 0xe78a2bda
-//.word 0x8bf23f01
-//.word 0x2c065dd6
-//.word 0x5e9c56f7
-//.word 0x175f7988
-//.word 0xb7c5b4cc
-//.word 0x4742fdf6
-//.word 0xfebcf03c
-//.word 0x0a3eba2e
-//.word 0x8df03546
-//.word 0xe54754c0
-//.word 0x3079c2ab
-//.word 0x0f34c641
-//.word 0xab8f6a74
-//.word 0xf641dcc9
-//.word 0x34101469
-//.word 0xb98db776
-//.word 0xf4ff3c9b
-//.word 0xac9d4de7
-//.word 0x8a0070db
-//.word 0xd8d7e6c1
-//.word 0x88ddd340
-//.word 0x7808a02e
-//.word 0xf4039ea5
-//.word 0x7ddfec59
-//.word 0xc8069a28
-//.word 0x0a700ef3
-//.word 0x7319a7ad
-//.word 0xf8b2a1b1
-//.word 0x56963959
-//.word 0x540111cc
-//.word 0x487cd517
-//.word 0xdc9c1f80
-//.word 0x12ec9816
-//.word 0x8628618d
-//.word 0xf4acb149
-//.word 0xf92bbfb9
-//.word 0x1ea4e280
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00007678
-//// expected output
-//.word 0xbd8fbb9b
-//.word 0xc746521c
-//.word 0xba862867
-//.word 0x0493cd85
-//.word 0x1f43b6f0
-//.word 0x263f49d3
-//.word 0xb6259519
-//.word 0xfbbcd93c
-//.word 0xac1c7d21
-//.word 0x5425a26a
-//.word 0x73a3c0f2
-//.word 0x8aa18833
-//.word 0xa4811e3e
-//.word 0xcabeeac0
-//.word 0x917f2e18
-//.word 0xf7718c8a
-//// SHA512LongMsgvector_38
-//// vector length
-//.word 0x00007990
-//// input message
-//.word 0x73dfee3b
-//.word 0x9a968877
-//.word 0x082b72fd
-//.word 0xec5a8902
-//.word 0x39a55eab
-//.word 0x0ef441cf
-//.word 0x757f9eff
-//.word 0x51ed8dc3
-//.word 0x92bda427
-//.word 0xabe60f76
-//.word 0x46bae346
-//.word 0x3610b0b4
-//.word 0xada256f1
-//.word 0xafb419fe
-//.word 0xc6f7f7b3
-//.word 0xf8ac3806
-//.word 0xf60c488a
-//.word 0x96e8c236
-//.word 0x838dcd68
-//.word 0x33eaab29
-//.word 0x1af58fb3
-//.word 0x1e4aaf31
-//.word 0x4a159bc5
-//.word 0xc633cdcf
-//.word 0x0794816d
-//.word 0x43e4c73e
-//.word 0x286ad66c
-//.word 0xcd30a3e9
-//.word 0xe964b2f8
-//.word 0x43fe2cf0
-//.word 0x69a3333c
-//.word 0xa5c972a7
-//.word 0x2d1df8d7
-//.word 0x9a214616
-//.word 0x9b1aa659
-//.word 0xeb29bf7a
-//.word 0x80b867c9
-//.word 0x0617b8c3
-//.word 0x8b676621
-//.word 0x7cb84f15
-//.word 0xd06e54d0
-//.word 0x83e96847
-//.word 0x4665e637
-//.word 0x751e2866
-//.word 0x49b8552d
-//.word 0x4fdf7a33
-//.word 0x182bdd7b
-//.word 0x32468ea1
-//.word 0x58503e60
-//.word 0xe6825458
-//.word 0x90123e0e
-//.word 0x52570535
-//.word 0xaa2e252c
-//.word 0x069c9bc7
-//.word 0x78b53f52
-//.word 0xb1bc54d3
-//.word 0x2d8b5e90
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-//.word 0xe0eb55e7
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-//// SHA512LongMsgvector_39
-//// vector length
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
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-//// expected output
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-//// SHA512LongMsgvector_40
-//// vector length
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-//// input message
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00007FC0
-//// expected output
-//.word 0xe8e09fc5
-//.word 0x7bd3b8e1
-//.word 0x8b272641
-//.word 0x8836852c
-//.word 0xf1544eb2
-//.word 0xcf28c18f
-//.word 0x5b984363
-//.word 0x82d0b621
-//.word 0x953d2faa
-//.word 0x60d155dd
-//.word 0x28c2cb76
-//.word 0xc00ee93d
-//.word 0x3de56289
-//.word 0xb399c22a
-//.word 0x4fd82f00
-//.word 0xdd35ef27
-//// SHA512LongMsgvector_41
-//// vector length
-//.word 0x000082D8
-//// input message
-//.word 0x9c06316a
-//.word 0xc709e944
-//.word 0x70a68650
-//.word 0xe1d6aeee
-//.word 0x089aefbf
-//.word 0x133df90a
-//.word 0x3eda0a5e
-//.word 0xe91fa979
-//.word 0xee509769
-//.word 0x318f03f1
-//.word 0x795afd2e
-//.word 0x7e552d7a
-//.word 0x434ac591
-//.word 0xa56eb4f3
-//.word 0x34e61d89
-//.word 0x4389078a
-//.word 0x3be856a0
-//.word 0x358bfa47
-//.word 0xc77e6676
-//.word 0x1d0d4382
-//.word 0x4ccb663f
-//.word 0xe4d90068
-//.word 0xc4641541
-//.word 0x3370307a
-//.word 0x2cd45457
-//.word 0xf886350e
-//.word 0x0319a871
-//.word 0xe88459cc
-//.word 0xce25bc11
-//.word 0xf7064632
-//.word 0x965edccf
-//.word 0xe15b8c11
-//.word 0x681e7bd6
-//.word 0xa5081e0e
-//.word 0xd434ad64
-//.word 0x0544d522
-//.word 0x6f61ae4e
-//.word 0x077dec19
-//.word 0x51db597b
-//.word 0x76d28317
-//.word 0x98ceb164
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-//.word 0xd7862340
-//.word 0x3bc75ce5
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-//.word 0x63eae04a
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-//.word 0x2480154c
-//.word 0xf485e28e
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-//.word 0xae01f732
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-//.word 0xbdbcf6d7
-//.word 0xf9f6c438
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-//.word 0x9d0a8018
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-//.word 0x20e358e9
-//.word 0xd6de49ae
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-//.word 0x8a9f371a
-//.word 0xdff18796
-//.word 0x6a99f84b
-//.word 0x70548000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000085F0
-//// expected output
-//.word 0x2711cb98
-//.word 0x0cb4fd62
-//.word 0xdf854469
-//.word 0x40d9c5d0
-//.word 0xe382912c
-//.word 0x96e80ecf
-//.word 0xdcdaf719
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-//.word 0x8c371e7a
-//.word 0x91e3a738
-//.word 0x814ca8c7
-//.word 0xb1139d98
-//.word 0x47756f24
-//.word 0xe9d247fe
-//// SHA512LongMsgvector_43
-//// vector length
-//.word 0x00008908
-//// input message
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-//.word 0x398fece8
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-//.word 0x60fc009f
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-//.word 0x54d45ae8
-//.word 0x47c088cf
-//.word 0x8c4c15d0
-//.word 0xc9147d8f
-//.word 0xe3f97205
-//.word 0xc4d0c4d1
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-//.word 0xe56d69ec
-//.word 0x6c827239
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-//.word 0x84deed9d
-//.word 0x6248e552
-//.word 0xaf5b052b
-//.word 0xbcb0cfb3
-//.word 0xb35c55c4
-//.word 0xd9219e57
-//.word 0x11e64c9a
-//.word 0xa2657c43
-//.word 0x3924ee24
-//.word 0x32a66600
-//.word 0x13e2519e
-//.word 0x59f4ac1b
-//.word 0x78132284
-//.word 0x1dc374a5
-//.word 0xb64b1e1b
-//.word 0x346a38b1
-//.word 0x0f469ae9
-//.word 0x8ba543d8
-//.word 0x3b5ffc37
-//.word 0xc31438b8
-//.word 0xe11a3f96
-//.word 0xafb98b70
-//.word 0x229b7257
-//.word 0xd77e0626
-//.word 0x0f2c3a11
-//.word 0xf8ad4681
-//.word 0x2ebb4c20
-//.word 0x81763b2f
-//.word 0xf959f420
-//.word 0x176dab61
-//.word 0x5ebc9076
-//.word 0x1209af4a
-//.word 0x40be15c7
-//.word 0xfe2635a4
-//.word 0xf4dc8a7e
-//.word 0x1b847d2b
-//.word 0xc5b8884b
-//.word 0xde459c1f
-//.word 0x7198c09f
-//.word 0x6d73fcc6
-//.word 0xaae57531
-//.word 0x2778d9e8
-//.word 0x96acfd7c
-//.word 0x1aa4c552
-//.word 0x4f20453e
-//.word 0x8bab2553
-//.word 0x63164afa
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-//.word 0xff486075
-//.word 0x8bf5a6f2
-//.word 0x64bf8bc2
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-//.word 0xb7be23bc
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-//.word 0xc089985c
-//.word 0xac96395b
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-//.word 0xc66bd2cc
-//.word 0xbef22843
-//.word 0x2f66b906
-//.word 0xc15b1969
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-//.word 0x85819382
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-//.word 0x8d03fd2d
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-//.word 0xf9fcdf9e
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-//.word 0xa595bc92
-//.word 0x9e83aae0
-//.word 0xa9bf2046
-//.word 0x67f566f4
-//.word 0x16013ebc
-//.word 0x105f8023
-//.word 0x94e202b8
-//.word 0xc9a9baa4
-//.word 0x00502783
-//.word 0x3a63ec72
-//.word 0xea18bf69
-//.word 0xfc3d81cc
-//.word 0x156fae3c
-//.word 0x1d8df8b3
-//.word 0xfb6c2fd0
-//.word 0x9fcc646f
-//.word 0x468b4e7d
-//.word 0xf919ed0b
-//.word 0x572c6ca0
-//.word 0x95b54cd4
-//.word 0xc312bf1a
-//.word 0x518552de
-//.word 0xd1e5cfd0
-//.word 0xfe93627f
-//.word 0xfeb0fa29
-//.word 0xe48df2d1
-//.word 0x7963f193
-//.word 0x3c450f35
-//.word 0xa75239fe
-//.word 0xb42fd6cb
-//.word 0xa0b5aa5f
-//.word 0xefe6fbfb
-//.word 0xb026f32e
-//.word 0x02a846ef
-//.word 0xd72615e9
-//.word 0xf8d51116
-//.word 0x4a98e38f
-//.word 0x4f73cca3
-//.word 0xef438826
-//.word 0x79ad790b
-//.word 0xe5550136
-//.word 0x5c50308b
-//.word 0xfadb9f4b
-//.word 0xd24d9ba0
-//.word 0x324a8676
-//.word 0x293a7b8d
-//.word 0x47f931cc
-//.word 0xa4d022d9
-//.word 0x23a5ece6
-//.word 0xf86ef7ce
-//.word 0x68ec5860
-//.word 0xd095f5fa
-//.word 0xe9d2ea5b
-//.word 0x4a6a2cb2
-//.word 0x2f3e6cfa
-//.word 0x78383f8a
-//.word 0xf57e7be8
-//.word 0xe0ebe4df
-//.word 0xab800000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00008908
-//// expected output
-//.word 0x73e3a0b5
-//.word 0x52605e08
-//.word 0xc1ca390e
-//.word 0x9b8d498f
-//.word 0xa2679a4f
-//.word 0x2f29bd80
-//.word 0xca7e40a8
-//.word 0x6e20a5ed
-//.word 0x4a9b8707
-//.word 0xdb0aeb79
-//.word 0xe251c8c0
-//.word 0xf4259ecd
-//.word 0x25dbb9c8
-//.word 0x2de838ae
-//.word 0x953e712d
-//.word 0x36991546
-//// SHA512LongMsgvector_44
-//// vector length
-//.word 0x00008C20
-//// input message
-//.word 0xd5233637
-//.word 0xf4320cf1
-//.word 0x57967343
-//.word 0x0ac26259
-//.word 0x595f2e48
-//.word 0xd742aba0
-//.word 0xa59c9440
-//.word 0xf0712d6f
-//.word 0xbc4c2628
-//.word 0xe030c3b4
-//.word 0x52d13a7f
-//.word 0xa5045d24
-//.word 0xd07578ca
-//.word 0x31987db3
-//.word 0xd2e25e12
-//.word 0xea38bb1d
-//.word 0xa7a8bd64
-//.word 0x2a574261
-//.word 0xd4ba3a50
-//.word 0xc0095041
-//.word 0x90f1ce6b
-//.word 0x6d8abac3
-//.word 0x498845cd
-//.word 0x67b567b2
-//.word 0x1e9fc394
-//.word 0xda8dd01e
-//.word 0x63b83a5f
-//.word 0x62b886d8
-//.word 0x213df6d3
-//.word 0x92ffacf7
-//.word 0x93f8111a
-//.word 0x70d07856
-//.word 0xa999ff5f
-//.word 0xf6bcb613
-//.word 0x89330453
-//.word 0x93f94612
-//.word 0x09bfb8ab
-//.word 0xa8e19978
-//.word 0x37988aa0
-//.word 0x0c713830
-//.word 0xd1fe3a6e
-//.word 0x88cb3d6a
-//.word 0xcd935ed5
-//.word 0x5bb4d716
-//.word 0xd2e1de9b
-//.word 0xb817ca6d
-//.word 0xbdd27808
-//.word 0x4380ed69
-//.word 0x1d363c68
-//.word 0x97a2aa48
-//.word 0xb741118d
-//.word 0xc3d1820d
-//.word 0x030a2e4a
-//.word 0xc88987ff
-//.word 0xae0da2f9
-//.word 0x1de5e028
-//.word 0x16a9cdf6
-//.word 0x2c2948d7
-//.word 0xd0a3e522
-//.word 0xd2398f1f
-//.word 0x25a17261
-//.word 0xe31f1856
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-//.word 0x4e485e3f
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-//.word 0x0770671b
-//.word 0xa7bd39bb
-//.word 0xc7a00b18
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-//.word 0x2684d5d6
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-//.word 0x5944ce7d
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-//.word 0x1a7e6993
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-//.word 0xa79dfd48
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-//.word 0x0082facc
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-//.word 0x969f0774
-//.word 0xaf292ef5
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-//.word 0x4d541875
-//.word 0xcf22f44c
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-//.word 0x42c0f47f
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-//.word 0x063801bd
-//.word 0xb20b45f7
-//.word 0x304b941e
-//.word 0xbed2afff
-//.word 0xcbe024fb
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-//.word 0x99a67f27
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-//.word 0x410bbe9d
-//.word 0x88e1750f
-//.word 0xb2279de8
-//.word 0x6d5b0bbf
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-//.word 0xb3daa5b2
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-//.word 0x86fd610c
-//.word 0xf33b5b43
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-//.word 0xb2dd176a
-//.word 0xdfe97cdd
-//.word 0xde236986
-//.word 0xd3b0bed3
-//.word 0x458bd9bb
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-//.word 0xb2158888
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-//.word 0xd88979d5
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-//.word 0x59a83b30
-//.word 0xb5a83c6b
-//.word 0x8dc91a4b
-//.word 0xbc0c22f9
-//.word 0x9af51c31
-//.word 0xc53d2b96
-//.word 0x22c6f449
-//.word 0x1ed402b9
-//.word 0x3a7969bd
-//.word 0xc651aae0
-//.word 0xec70d7fb
-//.word 0xf199f80a
-//.word 0xb8b0ac38
-//.word 0x8872143c
-//.word 0x0e64ece8
-//.word 0xa609fbff
-//.word 0xd658ae48
-//.word 0x1b6d00e0
-//.word 0xe97f9cd4
-//.word 0xed1246ef
-//.word 0x956e77d1
-//.word 0xd24f4741
-//.word 0x1dde90c5
-//.word 0xb8e0516f
-//.word 0x362e50f9
-//.word 0x3d650415
-//.word 0x8bdeb1fe
-//.word 0x37e1d553
-//.word 0x3915c325
-//.word 0x2d3b8e4f
-//.word 0x541c2805
-//.word 0xdcc0cbb0
-//.word 0x61e198f9
-//.word 0xb39f7f24
-//.word 0x80000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00008C20
-//// expected output
-//.word 0xf0549331
-//.word 0x42774856
-//.word 0xdac63b63
-//.word 0xf1755442
-//.word 0x98a3d368
-//.word 0x74bc3765
-//.word 0x0a268220
-//.word 0x1f8336b6
-//.word 0x21cbf9d9
-//.word 0x5c87a983
-//.word 0x8181c1b5
-//.word 0xc015dd0c
-//.word 0x08723beb
-//.word 0x82830326
-//.word 0x382b5db5
-//.word 0x1ea9283c
-//// SHA512LongMsgvector_45
-//// vector length
-//.word 0x00008F38
-//// input message
-//.word 0xa2871817
-//.word 0xb7ec41d5
-//.word 0x116195f9
-//.word 0x7ecf6e4c
-//.word 0x35dfde5f
-//.word 0x0d5e8a17
-//.word 0xede6bc69
-//.word 0x84bbb363
-//.word 0x3af33e6c
-//.word 0x66da89cc
-//.word 0xc194366f
-//.word 0x1b04afe5
-//.word 0x4cedbbae
-//.word 0x6e5750b5
-//.word 0x4935a91a
-//.word 0x0f449734
-//.word 0x4a361cd7
-//.word 0x121036d2
-//.word 0x83d1f9bc
-//.word 0x6e54e0f1
-//.word 0x4f7765d7
-//.word 0x7f7dcf66
-//.word 0xabb14ce7
-//.word 0x854c3ffb
-//.word 0xb999dbe0
-//.word 0x2357f1f0
-//.word 0x3f5f066a
-//.word 0xe187a975
-//.word 0x26c50462
-//.word 0xaa98b032
-//.word 0xfba3ce58
-//.word 0x4e9b53c0
-//.word 0x7164a30f
-//.word 0x0177622d
-//.word 0xdd878601
-//.word 0xda64b17b
-//.word 0xb91fbfd8
-//.word 0x566f9a21
-//.word 0x215356f5
-//.word 0xd2f97a89
-//.word 0x59df9bed
-//.word 0x14383091
-//.word 0x4591a107
-//.word 0xc3b4a10a
-//.word 0xf0cdbec0
-//.word 0xeacb363c
-//.word 0x06090d47
-//.word 0x7a2e5c60
-//.word 0x5952ec01
-//.word 0xc5620324
-//.word 0x60c57e06
-//.word 0x033f202b
-//.word 0xb3162aa2
-//.word 0xd0742c8a
-//.word 0x900d1ad5
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-//// vector length
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-//// SHA512LongMsgvector_49
-//// vector length
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-//// SHA512LongMsgvector_50
-//// vector length
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-//// vector length
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-//.word 0x7df5f4b4
-//.word 0x6adc77c5
-//.word 0xaee518e9
-//.word 0x6789fe02
-//.word 0xfe5dfae8
-//.word 0xfd93020b
-//.word 0x20c4e25a
-//.word 0xaeed2e63
-//.word 0x09b77bbb
-//.word 0x80000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x0000A4E0
-//// expected output
-//.word 0x8ecdb553
-//.word 0xcfbe2451
-//.word 0xfeb4b644
-//.word 0x0056099d
-//.word 0xd6511fae
-//.word 0xf2ac7ba9
-//.word 0x2b646c06
-//.word 0x1be2857c
-//.word 0x5bd09710
-//.word 0xaa56658d
-//.word 0x4e3f5668
-//.word 0x50b680b2
-//.word 0x3f2e0134
-//.word 0x4902fe0c
-//.word 0x83e8d3c8
-//.word 0x714c8fac
-//// SHA512LongMsgvector_53
-//// vector length
-//.word 0x0000A7F8
-//// input message
-//.word 0x5e7d99ce
-//.word 0xbeb23c5c
-//.word 0xf1c7340b
-//.word 0x5b5e2c2d
-//.word 0x1af148a5
-//.word 0x97125a48
-//.word 0x5bf7588a
-//.word 0x25350e56
-//.word 0x39cc103d
-//.word 0xfa64f3d3
-//.word 0xbbd6bc56
-//.word 0xd3ee9991
-//.word 0xef70cf00
-//.word 0xad58f435
-//.word 0x66665e7a
-//.word 0x4adadbb8
-//.word 0xb37da298
-//.word 0xb3e08ae7
-//.word 0xefe87a3f
-//.word 0xb18a21e4
-//.word 0x38d4e7ec
-//.word 0x532d23a3
-//.word 0x2edd8e2d
-//.word 0x6bd0f86d
-//.word 0x74963926
-//.word 0x10af6b60
-//.word 0x3506560e
-//.word 0x1ebb2ced
-//.word 0x9c2577af
-//.word 0xb1184f59
-//.word 0x5b63d0ea
-//.word 0xae9dcb3d
-//.word 0x2522bc30
-//.word 0x3a58fc06
-//.word 0x3437380a
-//.word 0x41082275
-//.word 0xc46c6692
-//.word 0xf0a1e020
-//.word 0x96010cf8
-//.word 0x3bcbbef0
-//.word 0x6e2613fe
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-//.word 0x9583087c
-//.word 0x43f96b44
-//.word 0x58b19edd
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-//.word 0x87be2aa0
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-//.word 0xfff2aeac
-//.word 0x4b166f22
-//.word 0xfffa06d8
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-//.word 0xd5a2122a
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-//.word 0x00000000
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-//// SHA512LongMsgvector_55
-//// vector length
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-//// expected output
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-//// SHA512LongMsgvector_58
-//// vector length
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-//// input message
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-//.word 0x0cf03aad
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-//.word 0x5d354775
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-//.word 0x765a47e7
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-//.word 0x011500fb
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-//.word 0x70ac4ba9
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-//.word 0x29c63739
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-//.word 0xb4a3a26f
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-//.word 0x76717f87
-//.word 0x4b1b4429
-//.word 0xd08a3fa6
-//.word 0x4d7593a6
-//.word 0x98eb6bb7
-//.word 0xdcfce09d
-//.word 0x9ab61de9
-//.word 0xed53c0ce
-//.word 0x12b0842f
-//.word 0x27011dfc
-//.word 0x33c464bf
-//.word 0x67f3b472
-//.word 0xa47e9494
-//.word 0x3df8967c
-//.word 0xfd907fec
-//.word 0x80000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x0000BDA0
-//// expected output
-//.word 0xf52e1999
-//.word 0x9a5773b2
-//.word 0x70b3ac58
-//.word 0xb152965e
-//.word 0x6c5b37eb
-//.word 0xb082d1f7
-//.word 0xa6d723ca
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-//.word 0x6d350592
-//.word 0xca7c3210
-//.word 0x675ed12a
-//.word 0x03b559ba
-//.word 0x66f9e681
-//.word 0xdff9ae71
-//// SHA512LongMsgvector_61
-//// vector length
-//.word 0x0000C0B8
-//// input message
-//.word 0xfe3ef26e
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-//.word 0xa8176696
-//.word 0xe1dc0725
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-//.word 0x7e0124a5
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-//.word 0xdebfcb8f
-//.word 0xbe2d991d
-//.word 0x6d57ba23
-//.word 0x60ac6a3b
-//.word 0xd93b1576
-//.word 0xb82fc7fc
-//.word 0x9495e4f2
-//.word 0x0a6619a1
-//.word 0x55c192d4
-//.word 0x1f786d81
-//.word 0x97ce6fac
-//.word 0xc47ff689
-//.word 0x19012fe1
-//.word 0x490a89b6
-//.word 0x5d526a2a
-//.word 0x039a209d
-//.word 0x29ed1a16
-//.word 0xca2658e4
-//.word 0x08b22085
-//.word 0x7c97f3c6
-//.word 0xcab5bf2c
-//.word 0x784c5693
-//.word 0x00bf1f15
-//.word 0x23980b2d
-//.word 0x81cbcb1c
-//.word 0x673f418c
-//.word 0xe88a3474
-//.word 0x2ffd473b
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-//// SHA512LongMsgvector_63
-//// vector length
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-//.word 0xb9e8e34b
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-//.word 0x5a21a67d
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-//.word 0x80000000
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-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x0000CA00
-//// expected output
-//.word 0x1333d76d
-//.word 0x9642fff2
-//.word 0x5a78e1df
-//.word 0x287d433b
-//.word 0xf30c61c2
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-//.word 0x7662d3c4
-//.word 0x409e5701
-//// SHA512LongMsgvector_65
-//// vector length
-//.word 0x0000CD18
-//// input message
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-//.word 0x32373d80
-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x0000CD18
-//// expected output
-//.word 0x4bccd0e1
-//.word 0x58f345b3
-//.word 0x4d583f92
-//.word 0x9c0a74d2
-//.word 0xb502d3a8
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-//.word 0xc9a5dead
-//.word 0x09fc2266
-//.word 0x319733ca
-//.word 0x2371051a
-//.word 0x4e358e0e
-//// SHA512LongMsgvector_66
-//// vector length
-//.word 0x0000D030
-//// input message
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-//.word 0x00000000
-//.word 0x00000000
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-//// expected output
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-//// SHA512LongMsgvector_68
-//// vector length
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-//// input message
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-//// expected output
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-//// SHA512LongMsgvector_69
-//// vector length
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x0000D978
-//// expected output
-//.word 0xafbe6328
-//.word 0x20e278b6
-//.word 0x33260ee8
-//.word 0x6ea0c2a8
-//.word 0x8735afec
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-//.word 0xeba7fea0
-//.word 0xba783398
-//.word 0x109b10bf
-//.word 0x1373a331
-//.word 0x6e72ad68
-//// SHA512LongMsgvector_70
-//// vector length
-//.word 0x0000DC90
-//// input message
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-//// SHA512LongMsgvector_71
-//// vector length
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-//// SHA512LongMsgvector_72
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-//// vector length
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-//// SHA512LongMsgvector_75
-//// vector length
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-//// expected output
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-//// SHA512LongMsgvector_76
-//// vector length
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-//.word 0x00000000
-//.word 0x00000000
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-//// expected output
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-//// SHA512LongMsgvector_78
-//// vector length
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-//// input message
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-//// SHA512LongMsgvector_79
-//// vector length
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x0000F868
-//// expected output
-//.word 0x06b3fe00
-//.word 0xa2c681db
-//.word 0xc14f6e81
-//.word 0xae1e7add
-//.word 0xedeeaaf4
-//.word 0xc7485d28
-//.word 0xbeed0b52
-//.word 0xd128cb9e
-//.word 0x7b295838
-//.word 0xdad38405
-//.word 0x4a826cd3
-//.word 0x16fe20b8
-//.word 0xea1aa35d
-//.word 0xe2b39ae6
-//.word 0x12342dd1
-//.word 0x911212d9
-//// SHA512LongMsgvector_80
-//// vector length
-//.word 0x0000FB80
-//// input message
-//.word 0x20e0a773
-//.word 0x19b72144
-//.word 0x235b24a9
-//.word 0xec5c53c5
-//.word 0xd816e9fc
-//.word 0x8e285804
-//.word 0xb727303f
-//.word 0x02934148
-//.word 0x6c0904cc
-//.word 0xbebb379b
-//.word 0x571ec8fe
-//.word 0x2be2f44c
-//.word 0x0c27b0b8
-//.word 0x29ee486d
-//.word 0xd4cd46dd
-//.word 0x88e89555
-//.word 0x2a1ce6d5
-//.word 0x8f7d5320
-//.word 0x3f03420f
-//.word 0x78808d2a
-//.word 0x76d5e079
-//.word 0xf2666298
-//.word 0xe9cb970a
-//.word 0x9ec985cf
-//.word 0xe2801539
-//.word 0x93e5bdfb
-//.word 0x63735c83
-//.word 0xda1e658a
-//.word 0x9f8940e9
-//.word 0xf378edae
-//.word 0x7e88eb6f
-//.word 0x4e1e58de
-//.word 0x1d9d599e
-//.word 0xd2dcbc55
-//.word 0x4bd7dc03
-//.word 0x5aa4c592
-//.word 0x0da999ae
-//.word 0x330d33d6
-//.word 0x1b6c09b3
-//.word 0x9fcf57a9
-//.word 0x61db7aad
-//.word 0x55489956
-//.word 0x80958b36
-//.word 0xfffaf56a
-//.word 0x4a9fb370
-//.word 0xba0b7a39
-//.word 0x49dfbb7f
-//.word 0x9ac4ca59
-//.word 0x39a23f0d
-//.word 0x23139d25
-//.word 0x891731c5
-//.word 0xd1093d3b
-//.word 0xded156d8
-//.word 0x915c0bfe
-//.word 0x8f49c77b
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-//.word 0x2a5a7166
-//.word 0x44230deb
-//.word 0xeec39657
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-//.word 0xbe6bd862
-//.word 0xc16234cf
-//.word 0x38038195
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x0000FB80
-//// expected output
-//.word 0x8bcf4c7d
-//.word 0xf9b79044
-//.word 0xab522ecb
-//.word 0x2d9bb9dc
-//.word 0xf54b6e13
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-//.word 0x67e3f95b
-//.word 0x249d160a
-//.word 0xe5e0c4d3
-//.word 0x48807926
-//.word 0x3e5ed128
-//// SHA512LongMsgvector_81
-//// vector length
-//.word 0x0000FE98
-//// input message
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
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-//// expected output
-//.word 0xc9c7d9b0
-//.word 0x413dd754
-//.word 0x96646779
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-//// SHA512LongMsgvector_82
-//// vector length
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-//// input message
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-//// SHA512LongMsgvector_84
-//// vector length
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-//// input message
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000107E0
-//// expected output
-//.word 0x9dce12e4
-//.word 0x9fae09e0
-//.word 0xb1a60f44
-//.word 0x199449fa
-//.word 0x31b9bb27
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-//.word 0x6202535e
-//.word 0x7abacd53
-//.word 0xe25ab84f
-//// SHA512LongMsgvector_85
-//// vector length
-//.word 0x00010AF8
-//// input message
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-//// vector length
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-//.word 0x80000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
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-//// expected output
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-//// SHA512LongMsgvector_89
-//// vector length
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-//// input message
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00011A70
-//// expected output
-//.word 0xaa13b83b
-//.word 0x4db9a58a
-//.word 0x7684bad6
-//.word 0xb864abda
-//.word 0xd23bdd71
-//.word 0xb4e5bcab
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-//.word 0x573c8fb6
-//.word 0xecf3962a
-//.word 0x30e0af0b
-//// SHA512LongMsgvector_91
-//// vector length
-//.word 0x00011D88
-//// input message
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-//.word 0x6f5b2f5b
-//.word 0x8dc8d0ff
-//.word 0x4fbd8758
-//.word 0x04974a58
-//.word 0x6b6bee4e
-//.word 0x27a53dac
-//.word 0x6def480d
-//.word 0x0055ff76
-//.word 0x5fa6fedc
-//.word 0x3c1daae7
-//.word 0x31407df6
-//.word 0xaf099e63
-//.word 0x3744b508
-//.word 0xcc38fd02
-//.word 0xa8899bb4
-//.word 0x2e5d2e0f
-//.word 0x20bea711
-//.word 0x12405b8c
-//.word 0x1ee35629
-//.word 0xda3af2ac
-//.word 0x87cda97a
-//.word 0x8bbd2858
-//.word 0x22a6a475
-//.word 0x50c971ab
-//.word 0x1a6bd102
-//.word 0xf5780a76
-//.word 0x7f6cbbfa
-//.word 0x6d736fbc
-//.word 0xc4cf73ab
-//.word 0x4d7be537
-//.word 0x420e0e57
-//.word 0x4ee1f2d1
-//.word 0xb5800000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00011D88
-//// expected output
-//.word 0x6730a70e
-//.word 0xd95c48d1
-//.word 0xfa1c04dd
-//.word 0x32c19233
-//.word 0x7ab47f4d
-//.word 0xf3c6a1e9
-//.word 0xd101c098
-//.word 0x3cceded1
-//.word 0xa10ab25f
-//.word 0xe0437de2
-//.word 0x4a6f9e38
-//.word 0x48f892c2
-//.word 0x327fc7fa
-//.word 0x6a0fb185
-//.word 0x4d81bf05
-//.word 0xd9733573
-//// SHA512LongMsgvector_92
-//// vector length
-//.word 0x000120A0
-//// input message
-//.word 0x645d2797
-//.word 0x0ccce096
-//.word 0xd082fccf
-//.word 0xc1183955
-//.word 0xbad2611a
-//.word 0xf0dd7c58
-//.word 0xc9d54430
-//.word 0xf28bd992
-//.word 0xac04b65c
-//.word 0x66c5e4c6
-//.word 0x914d6dfd
-//.word 0xb0e4140e
-//.word 0xae934306
-//.word 0x75744557
-//.word 0xbc2cb57e
-//.word 0x20b537e3
-//.word 0x77616601
-//.word 0x611b0dc6
-//.word 0x1ff0993d
-//.word 0xa9cfce6a
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-//.word 0xaf2ce70c
-//.word 0xd05dd502
-//.word 0xee43a73c
-//.word 0x6e7a1dcd
-//.word 0x2458c260
-//.word 0x247367d7
-//.word 0xd463cf31
-//.word 0x46c9acb1
-//.word 0xc590ca3c
-//.word 0xae728b04
-//.word 0x82be9363
-//.word 0x3859c409
-//.word 0xd8036d5a
-//.word 0x45dcbe12
-//.word 0x5a27802b
-//.word 0x394d0300
-//.word 0xe02557b2
-//.word 0xfe72becb
-//.word 0x04ae6221
-//.word 0x7e0644fe
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-//.word 0xc4070a8c
-//.word 0x915540cb
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-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
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-//// expected output
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-//.word 0x0077f460
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-//// SHA512LongMsgvector_93
-//// vector length
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-//// input message
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-//// SHA512LongMsgvector_94
-//// vector length
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000126D0
-//// expected output
-//.word 0x956d5ca8
-//.word 0xfb9c84cd
-//.word 0xc882eb0b
-//.word 0xf3f5ff0a
-//.word 0x61238f98
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-//.word 0xff0c6d63
-//// SHA512LongMsgvector_95
-//// vector length
-//.word 0x000129E8
-//// input message
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-//.word 0x18351198
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-//.word 0x9f30b047
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000129E8
-//// expected output
-//.word 0x46cf6321
-//.word 0x94dc6c65
-//.word 0xbea19ef7
-//.word 0x91b91ebd
-//.word 0x5a6d21f5
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-//.word 0x73cd86cc
-//.word 0xc936b735
-//.word 0xeffa0ed0
-//.word 0x1ef8c4d9
-//// SHA512LongMsgvector_96
-//// vector length
-//.word 0x00012D00
-//// input message
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-//// vector length
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-//// expected output
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-//// SHA512LongMsgvector_98
-//// vector length
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-//// SHA512LongMsgvector_99
-//// vector length
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-//.word 0x00000000
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-//// expected output
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-//// SHA512LongMsgvector_100
-//// vector length
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-//// input message
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
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-//// expected output
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-//.word 0x1cb3e4b7
-//.word 0x54b24e6c
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-//// SHA512LongMsgvector_101
-//// vector length
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-//// input message
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-//// expected output
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-//// SHA512LongMsgvector_102
-//// vector length
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-//// input message
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-//// SHA512LongMsgvector_103
-//// vector length
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-//// SHA512LongMsgvector_104
-//// vector length
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-//.word 0x6ff2a480
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000148D8
-//// expected output
-//.word 0x9e99388d
-//.word 0x377aac36
-//.word 0xafac4a85
-//.word 0x66b9d168
-//.word 0xc6f0faad
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-//.word 0xc9dfffe9
-//.word 0x1ad04bc3
-//.word 0x940faceb
-//.word 0x2eec299a
-//.word 0xc386c4d7
-//// SHA512LongMsgvector_106
-//// vector length
-//.word 0x00014BF0
-//// input message
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-//.word 0x252e620b
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00014BF0
-//// expected output
-//.word 0x0d61f8f4
-//.word 0x238bb647
-//.word 0xfd02199f
-//.word 0x8555a38d
-//.word 0x2eb4ac07
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-//.word 0x57d6f103
-//.word 0xde1b3229
-//.word 0x1705486b
-//.word 0x29f93975
-//// SHA512LongMsgvector_107
-//// vector length
-//.word 0x00014F08
-//// input message
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-//// vector length
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-//// SHA512LongMsgvector_109
-//// vector length
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-//.word 0x440e5d5d
-//.word 0xc6beec0f
-//.word 0xd07e5033
-//.word 0xb1327080
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00015538
-//// expected output
-//.word 0x9354325b
-//.word 0xe0d81277
-//.word 0x22ab167c
-//.word 0x4ba9b8c0
-//.word 0x4d6fb4b7
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-//.word 0x28152824
-//.word 0x56cb9042
-//.word 0xca8a6a6b
-//.word 0x9cf57e97
-//.word 0x37ec2592
-//// SHA512LongMsgvector_110
-//// vector length
-//.word 0x00015850
-//// input message
-//.word 0xf1ec3715
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-//.word 0x58fd754a
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-//.word 0x6af1d919
-//.word 0x1bc1fc35
-//.word 0x82a0613f
-//.word 0xf0eef645
-//.word 0xd1b2b721
-//.word 0x263bc341
-//.word 0x3507b6a9
-//.word 0x7ee3333a
-//.word 0xf254c034
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-//.word 0x30a33915
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-//.word 0x903bc305
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-//.word 0xb4d6e3d4
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-//.word 0x79edaf7d
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-//.word 0x0c81c391
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-//.word 0x89215e08
-//.word 0x96389c06
-//.word 0xbea1032d
-//.word 0x6d658481
-//.word 0x2941fa41
-//.word 0xc807ff6b
-//.word 0xe142047e
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-//.word 0x1e76294e
-//.word 0xd0678202
-//.word 0xbec433d3
-//.word 0xd712bf10
-//.word 0xc3a73260
-//.word 0x190ff94c
-//.word 0xd3aff6fd
-//.word 0xffa88000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00015850
-//// expected output
-//.word 0xfc85c2a2
-//.word 0x7bac2627
-//.word 0x72a53f8e
-//.word 0xaa19b3df
-//.word 0x653c1047
-//.word 0x4adc1049
-//.word 0x7637f246
-//.word 0xb32909b8
-//.word 0xb4c97bb1
-//.word 0x9fb209bb
-//.word 0xbd217ec4
-//.word 0x40e2953d
-//.word 0xdece86dd
-//.word 0x54f3000b
-//.word 0x00b37ff3
-//.word 0x4a61d2e5
-//// SHA512LongMsgvector_111
-//// vector length
-//.word 0x00015B68
-//// input message
-//.word 0x8595ad7e
-//.word 0xf34cc6b6
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-//.word 0x9a72827a
-//.word 0x4b199a47
-//.word 0xe29a8c58
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-//.word 0x55a4c332
-//.word 0xab609006
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-//.word 0xff0e0991
-//.word 0xbc62ae00
-//.word 0x9b8a2ce3
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-//.word 0x74bf0e7c
-//.word 0x4df84c46
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-//.word 0xc2d38f83
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-//.word 0x7cd7ad69
-//.word 0xabfa7d92
-//.word 0xa9d6a425
-//.word 0x1366c786
-//.word 0xd4bd390b
-//.word 0xf38f6fa6
-//.word 0xb0f3b4c4
-//.word 0xd0671d74
-//.word 0x3515c0cc
-//.word 0xb1552188
-//.word 0x1c72edf5
-//.word 0xa4b1eb0e
-//.word 0x658f2fe4
-//.word 0x3a4b9143
-//.word 0xd2a45d92
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-//.word 0xa31cf398
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-//.word 0x74e27514
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-//// SHA512LongMsgvector_112
-//// vector length
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-//.word 0xc6b217d8
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-//.word 0x21066b73
-//.word 0x655c4498
-//.word 0x80000000
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-//.word 0x00000000
-//.word 0x00000000
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00015E80
-//// expected output
-//.word 0x9f0c0f9c
-//.word 0xc172a278
-//.word 0x0b8f378a
-//.word 0x51155eb7
-//.word 0xecebd238
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-//.word 0x11f9277b
-//.word 0xade2d389
-//.word 0xc9577d54
-//.word 0x95930f24
-//// SHA512LongMsgvector_113
-//// vector length
-//.word 0x00016198
-//// input message
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-//// SHA512LongMsgvector_114
-//// vector length
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-//// expected output
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-//// SHA512LongMsgvector_115
-//// vector length
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x000167C8
-//// expected output
-//.word 0x661b576d
-//.word 0x9751845a
-//.word 0x0dbcb2bf
-//.word 0xca1d1cc2
-//.word 0xb556e22a
-//.word 0x0d671e35
-//.word 0xdbc349eb
-//.word 0x51baee0d
-//.word 0xed828f52
-//.word 0x88a01d70
-//.word 0x0509fca2
-//.word 0x06e4a398
-//.word 0x15dd85af
-//.word 0x1b7d706d
-//.word 0xa78abb8e
-//.word 0x99701129
-//// SHA512LongMsgvector_116
-//// vector length
-//.word 0x00016AE0
-//// input message
-//.word 0xcc5a4209
-//.word 0xa6a60dcf
-//.word 0x12621e17
-//.word 0x150b4576
-//.word 0xb918732e
-//.word 0x0ee8d9ba
-//.word 0x6ff94ea6
-//.word 0x065af1a4
-//.word 0x936310dd
-//.word 0x68a34985
-//.word 0xb81aefb2
-//.word 0x12a8b06e
-//.word 0x29c6740a
-//.word 0xd67487b6
-//.word 0x6072fb4f
-//.word 0xfab34878
-//.word 0x8d0f36ec
-//.word 0xb838fd13
-//.word 0x16efaad3
-//.word 0xbf78c4a8
-//.word 0x114b30f7
-//.word 0xb00c529f
-//.word 0xcbbd75d2
-//.word 0xa1336d23
-//.word 0x44c67adf
-//.word 0x9d4d70a1
-//.word 0xb14a1521
-//.word 0x2261cb4d
-//.word 0xf90f6f9b
-//.word 0xa298809d
-//.word 0x384184d6
-//.word 0x04c0a7cc
-//.word 0x40f1a65e
-//.word 0x20caeb58
-//.word 0x1391fa45
-//.word 0x464c0b84
-//.word 0x697af89e
-//.word 0xb7005ad7
-//.word 0x3066ef03
-//.word 0x2943409b
-//.word 0x07f68010
-//.word 0x4897b65f
-//.word 0xc32e1fe6
-//.word 0x3022cd76
-//.word 0xeaf495a9
-//.word 0xf42c2876
-//.word 0x3a948002
-//.word 0x1aa57eb9
-//.word 0x233fd19e
-//.word 0x1d9d19df
-//.word 0x49874cad
-//.word 0xeac9594a
-//.word 0x03e50c64
-//.word 0x630532a1
-//.word 0xdf33fd7b
-//.word 0xdfccaa4e
-//.word 0x1c3260af
-//.word 0xa7c25c00
-//.word 0x2e064b41
-//.word 0x7b2bf729
-//.word 0x3db52676
-//.word 0x0b71bf81
-//.word 0xa6ab2f15
-//.word 0x7ea20b81
-//.word 0x7839f7ec
-//.word 0xefefc6e9
-//.word 0xf911e34c
-//.word 0xeb2fef3b
-//.word 0x1fccab88
-//.word 0xf459193e
-//.word 0x1765de79
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-//.word 0xc1bb5cfd
-//.word 0xfc0da0c3
-//.word 0x3212db73
-//.word 0x42bc88a7
-//.word 0x31926341
-//.word 0x27a686ff
-//.word 0xbac7d24f
-//.word 0x6ff79064
-//.word 0x7e205889
-//.word 0xd60232b5
-//.word 0x6170fc60
-//.word 0x89bc0c96
-//.word 0xfb70164a
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-//.word 0x183ad23e
-//.word 0xd1474363
-//.word 0x38cfb338
-//.word 0x86b8c4e8
-//.word 0x0f930ebb
-//.word 0xc816c12f
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-//.word 0x880bbc2e
-//.word 0xb827a8ee
-//.word 0x2ee54ca0
-//.word 0x763235b4
-//.word 0x13159e84
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-//// SHA512LongMsgvector_117
-//// vector length
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-//// vector length
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-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
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-//// expected output
-//.word 0x61dce069
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-//.word 0x7f4ae87e
-//.word 0x5e9e814c
-//.word 0x1521d655
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-//.word 0x1a2ff6ec
-//// SHA512LongMsgvector_120
-//// vector length
-//.word 0x00017740
-//// input message
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-//// expected output
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-//// SHA512LongMsgvector_121
-//// vector length
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-//.word 0x81774e52
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-//.word 0x5a5309b7
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-//.word 0x52c6219c
-//.word 0x7a1fe427
-//.word 0x99be4e53
-//.word 0x197baacf
-//.word 0x36acc0d0
-//.word 0xa73d9ebf
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-//.word 0x7055f8c6
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-//.word 0xce449241
-//.word 0x5acda929
-//.word 0x5fcdc4ca
-//.word 0xe82a015a
-//.word 0xa6e6290d
-//.word 0x4ef43588
-//.word 0x3c4a1198
-//.word 0x5c37a124
-//.word 0x4af70260
-//.word 0xb8851244
-//.word 0x11b0323d
-//.word 0x5b714a22
-//.word 0x627c0e69
-//.word 0x1315809b
-//.word 0x2625b605
-//.word 0x008ddeb1
-//.word 0xd7ba7f94
-//.word 0x17790209
-//.word 0x040d707e
-//.word 0xa1807d6d
-//.word 0xd136c68f
-//.word 0xbdc8574c
-//.word 0x750f7075
-//.word 0xda7e8935
-//.word 0xbbb59345
-//.word 0x3e548160
-//.word 0x820d07f7
-//.word 0x82fea180
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00017A58
-//// expected output
-//.word 0x64fd89d0
-//.word 0xb0992719
-//.word 0x4001a751
-//.word 0xb7424279
-//.word 0x40c96104
-//.word 0xd7bc3748
-//.word 0x9852000b
-//.word 0xebfed610
-//.word 0x55d2ac26
-//.word 0x076d5abb
-//.word 0x8c34fcee
-//.word 0x0d0fb3e0
-//.word 0xcb99ee1c
-//.word 0x7dc35d3b
-//.word 0xd35350c9
-//.word 0xfd1b5b52
-//// SHA512LongMsgvector_122
-//// vector length
-//.word 0x00017D70
-//// input message
-//.word 0x00c317f6
-//.word 0xb591269b
-//.word 0x94cc28ba
-//.word 0x064e5f1e
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-//.word 0x7bd3a359
-//.word 0xb74dee92
-//.word 0xffe034fe
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-//.word 0xc3de544c
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-//.word 0x3d8ef173
-//.word 0xd81c67f0
-//.word 0x0eb72160
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-//.word 0x94737c22
-//.word 0xe1c23645
-//.word 0xc85db128
-//.word 0x60115d0d
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-//.word 0x9d1e71a3
-//.word 0x75faf032
-//.word 0xef5c9423
-//.word 0xc1355e09
-//.word 0x85c55b49
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-//.word 0xdf5551f6
-//.word 0x295bd7dc
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-//// SHA512LongMsgvector_125
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-//// vector length
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-//.word 0x8b31cd40
-//.word 0x3db8a2c1
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-//.word 0x1d443ef1
-//.word 0x2608905d
-//.word 0xfa856f04
-//.word 0x79ead73f
-//.word 0xabf13226
-//.word 0x531c83f9
-//.word 0xc73ee4bf
-//.word 0xfe3e322c
-//.word 0xeb1807c8
-//.word 0x0924e84e
-//.word 0x389bc052
-//.word 0xc7578d27
-//.word 0xd2da5a00
-//.word 0xce926d55
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-//.word 0x774c6541
-//.word 0x692ae6a5
-//.word 0xc2cf2986
-//.word 0x62673913
-//.word 0xcb3ec194
-//.word 0x3382c751
-//.word 0xd74996af
-//.word 0x91d5fc9d
-//.word 0xad17b62e
-//.word 0xf9732987
-//.word 0x1bc353fc
-//.word 0x279e0076
-//.word 0x71da4118
-//.word 0xa04f1a22
-//.word 0x04de7b15
-//.word 0x2ab37118
-//.word 0xadc69e9a
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-//.word 0x477c6ce2
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-//.word 0x355e4b3d
-//.word 0x684d1c25
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-//.word 0xc7c290d7
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-//.word 0xabdfd727
-//.word 0xbed1c64d
-//.word 0xb3043524
-//.word 0xfeed5863
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-//.word 0xbb5e0f1e
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-//.word 0xb53b9c8e
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-//.word 0xf677e99f
-//.word 0x872112f6
-//.word 0x52976904
-//.word 0x3219c29c
-//.word 0xc1a4b449
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-//.word 0xd7610540
-//.word 0x496ef183
-//.word 0xac0339d2
-//.word 0x8757ccb2
-//.word 0x5db5527a
-//.word 0x3ac863b4
-//.word 0x8b15f6c5
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-//.word 0x8897c326
-//.word 0x739ba7eb
-//.word 0x16210926
-//.word 0x83c1b4c7
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-//.word 0xba954a4c
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-//.word 0xcd7ac2ed
-//.word 0x949a47f6
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-//.word 0x5b083118
-//.word 0x6dc27634
-//.word 0x9bf00485
-//.word 0xf72d9824
-//.word 0x47f94627
-//.word 0x58b96bc5
-//.word 0x95ffe4bb
-//.word 0xd70c7ded
-//.word 0x7f93ac51
-//.word 0xc3c08009
-//.word 0x4579d4cf
-//.word 0xeae4c896
-//.word 0xe929726e
-//.word 0x2279d0a9
-//.word 0xb24f013c
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-//.word 0xa94be399
-//.word 0x2cc4ba8e
-//.word 0x1fb1d9ba
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-//.word 0x13110842
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-//.word 0x521f7b0e
-//.word 0x90cf6e68
-//.word 0x2562fe1e
-//.word 0x159c6eb4
-//.word 0xe1cd6095
-//.word 0x595248b5
-//.word 0xb25e2075
-//.word 0xd8fb5ec7
-//.word 0x054b2392
-//.word 0x9314b558
-//.word 0x0f7b2f16
-//.word 0x8e10776b
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-//.word 0x52d57219
-//.word 0xe0cbf899
-//.word 0x6c3e980b
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-//.word 0xe725dc4e
-//.word 0x6354a342
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-//.word 0xb5832aec
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-//.word 0x424f6e2e
-//.word 0xc7e485a5
-//.word 0x672f5e2b
-//.word 0xe9ae11c1
-//.word 0x58102036
-//.word 0x563d644b
-//.word 0xb3964714
-//.word 0x3e7e34a1
-//.word 0xdb194cde
-//.word 0xd6535bb8
-//.word 0x77250a81
-//.word 0xd7145696
-//.word 0xf1fa403f
-//.word 0xfc08c6d6
-//.word 0xf90c132c
-//.word 0x88f0f328
-//.word 0xff8389b1
-//.word 0xbd7d44ce
-//.word 0xbcbd0f0c
-//.word 0x66d4c821
-//.word 0xaac7f4ce
-//.word 0x4e11b10a
-//.word 0x87e8eb5c
-//.word 0xc7c1d389
-//.word 0xd6168d6f
-//.word 0x24672931
-//.word 0x5e7fd594
-//.word 0x3ff851a9
-//.word 0xa901a3ad
-//.word 0xf45f0b2d
-//.word 0x86b2396d
-//.word 0xa3fabe0b
-//.word 0x8759c1e0
-//.word 0xb21bf327
-//.word 0x84f3c5e1
-//.word 0x0987d878
-//.word 0x162fb4a2
-//.word 0x95fabe88
-//.word 0x1df36428
-//.word 0xc6a29bf7
-//.word 0x3bd58bcb
-//.word 0x10a088f9
-//.word 0x56a245ba
-//.word 0x6d8a44d4
-//.word 0x1ada9176
-//.word 0xd9ebb063
-//.word 0x7531d452
-//.word 0xd5c15295
-//.word 0x191054fa
-//.word 0xe6fed2ef
-//.word 0xfd13bee9
-//.word 0x13087f06
-//.word 0xdd89a1f1
-//.word 0x6a39cb06
-//.word 0xb5f7f1b6
-//.word 0x7b60ca2d
-//.word 0x4a948533
-//.word 0xdb3db850
-//.word 0xa1ce9934
-//.word 0xa2097055
-//.word 0x86c44cda
-//.word 0xedecf5b8
-//.word 0x06ca231b
-//.word 0x5e85ed07
-//.word 0xf5e9843f
-//.word 0x97662166
-//.word 0x695c3c64
-//.word 0xc396ff0b
-//.word 0x3d14fafb
-//.word 0x0d0d18c2
-//.word 0x9034d248
-//.word 0x263ba26b
-//.word 0x4395bbe6
-//.word 0xc381f777
-//.word 0x7e441141
-//.word 0x1db5146f
-//.word 0x2cff131a
-//.word 0x70a31b6c
-//.word 0x7abc6606
-//.word 0x7c87d1a0
-//.word 0x5c2290ef
-//.word 0x079421cc
-//.word 0x080e7e92
-//.word 0x597197c8
-//.word 0x780fff00
-//.word 0xbeb6e6fe
-//.word 0xedeb471d
-//.word 0x087362ef
-//.word 0x67186d24
-//.word 0x0aa987ad
-//.word 0x2e43ed21
-//.word 0x1ecf705f
-//.word 0x4ccc2775
-//.word 0xa04f61c0
-//.word 0x1047dd55
-//.word 0x71063ea0
-//.word 0x8cfdb94b
-//.word 0x75c71161
-//.word 0x186ac5b4
-//.word 0x15d9887c
-//.word 0xcebdf140
-//.word 0xbd7474fa
-//.word 0x0c5a9176
-//.word 0x5f484bfb
-//.word 0xf55bdc2d
-//.word 0xeff7a732
-//.word 0xef0b6e14
-//.word 0xe596c566
-//.word 0x266ac62b
-//.word 0xbf3007f3
-//.word 0x08acc947
-//.word 0x7c427247
-//.word 0xc7b93e92
-//.word 0x21403166
-//.word 0xdbae5009
-//.word 0x370e1067
-//.word 0x7d5b0ffc
-//.word 0x4b8802f4
-//.word 0x2dc3ee91
-//.word 0x6dfb9cce
-//.word 0x2da04742
-//.word 0xb2aa9746
-//.word 0x03dcd35a
-//.word 0xb34a52c5
-//.word 0xfb19327c
-//.word 0x0c864d45
-//.word 0xa229691c
-//.word 0xdd7bafd6
-//.word 0x4d975f04
-//.word 0x4b3dc11a
-//.word 0x901c5fd1
-//.word 0x005171c9
-//.word 0xc72b9973
-//.word 0xa731d02e
-//.word 0x9066a0b0
-//.word 0x72cb95a8
-//.word 0x4f26eea1
-//.word 0x9402972a
-//.word 0xa9f75c34
-//.word 0xc72b57bb
-//.word 0x0a19aaa9
-//.word 0xc79174f7
-//.word 0x1f00fd15
-//.word 0xd4f2348c
-//.word 0x5cd55ce2
-//.word 0x340002bd
-//.word 0x77f4324c
-//.word 0xafe1eae3
-//.word 0xeb6ccfe5
-//.word 0x12af1fe7
-//.word 0x7681e712
-//.word 0xacf876c9
-//.word 0x9c2d118c
-//.word 0xd43fe81d
-//.word 0x229b49e1
-//.word 0x617a1488
-//.word 0x93ab6ff1
-//.word 0x3092ba47
-//.word 0xbe71c671
-//.word 0xa2e641a9
-//.word 0x36b5756a
-//.word 0x1bc83390
-//.word 0xd17409bb
-//.word 0x84febbf4
-//.word 0x295ef193
-//.word 0xca422e5f
-//.word 0x1e5601f8
-//.word 0x5dc37f72
-//.word 0x52f5f043
-//.word 0xb2a2c95f
-//.word 0xac08dba1
-//.word 0xc176c96d
-//.word 0xd60dbf94
-//.word 0x88c86177
-//.word 0xbfba0270
-//.word 0x8697176d
-//.word 0x1a76ebde
-//.word 0x40d594d2
-//.word 0xdcde255c
-//.word 0xc0e9253c
-//.word 0xc24140bb
-//.word 0x112b3dd7
-//.word 0xc92430a0
-//.word 0xc46bf1e2
-//.word 0xb4bfcc04
-//.word 0x6e6a7a30
-//.word 0x897e50b5
-//.word 0x285fb7a9
-//.word 0x1481dcd2
-//.word 0x0e73a9c7
-//.word 0x631df352
-//.word 0xc046f519
-//.word 0x4859fd7d
-//.word 0xe46865c3
-//.word 0xda71c571
-//.word 0xa2e067fb
-//.word 0xf556fb9f
-//.word 0x26a98c8e
-//.word 0xb52cb34c
-//.word 0x22300b59
-//.word 0xffcae411
-//.word 0x49d73cd1
-//.word 0xf83eeb5b
-//.word 0xd5751d7c
-//.word 0x8c4705ec
-//.word 0x02d4d075
-//.word 0xe8d9d857
-//.word 0x91311bec
-//.word 0x009ceb88
-//.word 0x46c0e7a3
-//.word 0x0b6d293a
-//.word 0x6a25c172
-//.word 0x02dc627f
-//.word 0x49fc5cc4
-//.word 0x24acca3b
-//.word 0xb5520d18
-//.word 0x745679a9
-//.word 0x822a4d81
-//.word 0x3a87e9d5
-//.word 0x08f93b26
-//.word 0x7e9d7b20
-//.word 0xa42918c3
-//.word 0x902ef2c0
-//.word 0x379ac926
-//.word 0x8381f53d
-//.word 0xa61d58b2
-//.word 0xad1392f5
-//.word 0x58f773e0
-//.word 0x2913b699
-//.word 0xbb64ecb9
-//.word 0x55e6b6ae
-//.word 0xbf12375e
-//.word 0x54a4c90c
-//.word 0x59a1ef80
-//.word 0x8d998c62
-//.word 0x012952e8
-//.word 0x2ac57cb1
-//.word 0x35b4c0f0
-//.word 0x9a5c7fcc
-//.word 0xf4c04007
-//.word 0x10475cde
-//.word 0x44bffa31
-//.word 0x02a13ee4
-//.word 0xac97be85
-//.word 0xaa3b362f
-//.word 0xbb227cae
-//.word 0x8819b6e3
-//.word 0x7faeca6a
-//.word 0xdef3167b
-//.word 0x0e7e620e
-//.word 0x33b41243
-//.word 0x0148a000
-//.word 0xd1fe4adc
-//.word 0xf4b5083c
-//.word 0x47a4c1bb
-//.word 0x07e4bed0
-//.word 0xe72e5fab
-//.word 0x60e70d5f
-//.word 0x49596f46
-//.word 0xa744e1a1
-//.word 0xc6952280
-//.word 0x89754ce2
-//.word 0xfe850a1c
-//.word 0x3568057f
-//.word 0x53839f35
-//.word 0xe200e46c
-//.word 0x6b19bdb7
-//.word 0x479367b0
-//.word 0xb28824e3
-//.word 0x216a31e7
-//.word 0xd645f7ce
-//.word 0xb14485c0
-//.word 0x49773ee2
-//.word 0x3bd3cf7c
-//.word 0xc27b655c
-//.word 0x883e1c75
-//.word 0xbc60bacc
-//.word 0x659d9d95
-//.word 0xf66bf298
-//.word 0x228028da
-//.word 0xf194a47a
-//.word 0x1468b7d9
-//.word 0x7607cdfd
-//.word 0x134be738
-//.word 0x0da44b04
-//.word 0xfc157932
-//.word 0x867f6244
-//.word 0x3122d517
-//.word 0x74613ac5
-//.word 0x14c582c9
-//.word 0xae455e64
-//.word 0x8fc5af40
-//.word 0xccdc3e54
-//.word 0x90daae07
-//.word 0xb00aaf98
-//.word 0x853474bd
-//.word 0xfa66668a
-//.word 0xe4f41a95
-//.word 0x92be8058
-//.word 0xa5b15ed6
-//.word 0x2291fd82
-//.word 0xc6f5235c
-//.word 0x9a93405d
-//.word 0xc7bdec15
-//.word 0xaa2c9193
-//.word 0x2bfd6585
-//.word 0x4bf99ca0
-//.word 0xfd19db42
-//.word 0x3749ef56
-//.word 0x486dbf79
-//.word 0x6ca27f5a
-//.word 0x9ec62767
-//.word 0xad3a24a6
-//.word 0x92e64de0
-//.word 0x017e1805
-//.word 0x3e040ecc
-//.word 0x328f7c9a
-//.word 0xbe4a6ca5
-//.word 0x4fbfd359
-//.word 0xb3560cfb
-//.word 0x2b18858c
-//.word 0xc1b9b9f0
-//.word 0xdbd65e4f
-//.word 0x117bdfbc
-//.word 0x3ce80c14
-//.word 0xcf951129
-//.word 0x6b73a420
-//.word 0xad758318
-//.word 0x4b4f1e0d
-//.word 0x5f7e90fb
-//.word 0x0288d446
-//.word 0x1d853659
-//.word 0x7cde078d
-//.word 0x2455954d
-//.word 0xe7455b79
-//.word 0x352b7407
-//.word 0x356656f0
-//.word 0x80000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00000000
-//.word 0x00019000
-//// expected output
-//.word 0x26263445
-//.word 0x024bbdbd
-//.word 0x0518b331
-//.word 0xa7ab88e7
-//.word 0xbdc8d834
-//.word 0x4a3480d1
-//.word 0xc19ad0e7
-//.word 0xc7cb2244
-//.word 0x7cf88e53
-//.word 0xd2536fd2
-//.word 0x15e25c51
-//.word 0x58dbc52e
-//.word 0xf56585f7
-//.word 0xab5b7713
-//.word 0x87811a9f
-//.word 0x9afbdb7f
diff --git a/src/integration/test_suites/smoke_test_sha_accel/caliptra_isr.h b/src/integration/test_suites/smoke_test_sha_accel/caliptra_isr.h
index 0193842cc..841da2048 100644
--- a/src/integration/test_suites/smoke_test_sha_accel/caliptra_isr.h
+++ b/src/integration/test_suites/smoke_test_sha_accel/caliptra_isr.h
@@ -32,6 +32,34 @@
 #include <stdint.h>
 #include "printf.h"
 
+/* --------------- symbols/typedefs --------------- */
+//TODO: Fix this since ISR is not currently populating these variables.
+typedef struct {
+    uint32_t doe_error;
+    uint32_t doe_notif;
+    uint32_t ecc_error;
+    uint32_t ecc_notif;
+    uint32_t hmac_error;
+    uint32_t hmac_notif;
+    uint32_t kv_error;
+    uint32_t kv_notif;
+    uint32_t sha512_error;
+    uint32_t sha512_notif;
+    uint32_t sha256_error;
+    uint32_t sha256_notif;
+    uint32_t qspi_error;
+    uint32_t qspi_notif;
+    uint32_t uart_error;
+    uint32_t uart_notif;
+    uint32_t i3c_error;
+    uint32_t i3c_notif;
+    uint32_t soc_ifc_error;
+    uint32_t soc_ifc_notif;
+    uint32_t sha512_acc_error;
+    uint32_t sha512_acc_notif;
+} caliptra_intr_received_s;
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
+
 extern volatile uint32_t sha_intr_status;
 
 //////////////////////////////////////////////////////////////////////////////
diff --git a/src/integration/test_suites/smoke_test_sha_accel/smoke_test_sha_accel.s b/src/integration/test_suites/smoke_test_sha_accel/smoke_test_sha_accel.s
index c79d4f721..fffd13cd1 100644
--- a/src/integration/test_suites/smoke_test_sha_accel/smoke_test_sha_accel.s
+++ b/src/integration/test_suites/smoke_test_sha_accel/smoke_test_sha_accel.s
@@ -48,12 +48,20 @@ _start:
     // Call interrupt init
     call init_interrupts
 
-    //Acquire SHA lock
-    li x3, CLP_SHA512_ACC_CSR_LOCK
-    lock_poll_loop0:
-        lw x5, 0(x3)
-        andi x5, x5, SHA512_ACC_CSR_LOCK_LOCK_MASK
-        bne x5, x0, lock_poll_loop0
+    
+   //For FIPS, SHA starts of in a locked mode for uController
+   //Release SHA lock - although this step is NOT explicitly required if uC wants to just go ahead and use it directly
+   // Note that this case was also tested by commenting out the unlocking & relocking code below as a directed test case during the design
+   li x3, CLP_SHA512_ACC_CSR_LOCK
+   li x1, SHA512_ACC_CSR_LOCK_LOCK_MASK
+   sw x1, 0(x3)
+
+   //Acquire SHA lock
+   li x3, CLP_SHA512_ACC_CSR_LOCK
+   lock_poll_loop0:
+       lw x5, 0(x3)
+       andi x5, x5, SHA512_ACC_CSR_LOCK_LOCK_MASK
+       bne x5, x0, lock_poll_loop0
 
     //Set to Streaming SHA512 Mode
     li x3, CLP_SHA512_ACC_CSR_MODE
@@ -402,6 +410,8 @@ verbosity_g: .word 2
 // FW polls this variable instead of the SHA reg....
 .global sha_intr_status
 sha_intr_status: .word 0
+.global cptra_intr_rcv
+cptra_intr_rcv: .word 0
 print_data:
 .ascii "----------------------------------------\n"
 .ascii "Running SHA Accelerator Smoke Test    !!\n"
diff --git a/src/integration/test_suites/smoke_test_sram_ecc/caliptra_isr.h b/src/integration/test_suites/smoke_test_sram_ecc/caliptra_isr.h
index 1e2d2ac27..8f5779e04 100644
--- a/src/integration/test_suites/smoke_test_sram_ecc/caliptra_isr.h
+++ b/src/integration/test_suites/smoke_test_sram_ecc/caliptra_isr.h
@@ -26,12 +26,39 @@
 #ifndef CALIPTRA_ISR_H
     #define CALIPTRA_ISR_H
 
-#define EN_ISR_PRINTS 0
+#define EN_ISR_PRINTS 1
 
-#include "caliptra_reg.h"
+#include "caliptra_defines.h"
 #include <stdint.h>
 #include "printf.h"
 
+/* --------------- symbols/typedefs --------------- */
+typedef struct {
+    uint32_t doe_error;
+    uint32_t doe_notif;
+    uint32_t ecc_error;
+    uint32_t ecc_notif;
+    uint32_t hmac_error;
+    uint32_t hmac_notif;
+    uint32_t kv_error;
+    uint32_t kv_notif;
+    uint32_t sha512_error;
+    uint32_t sha512_notif;
+    uint32_t sha256_error;
+    uint32_t sha256_notif;
+    uint32_t qspi_error;
+    uint32_t qspi_notif;
+    uint32_t uart_error;
+    uint32_t uart_notif;
+    uint32_t i3c_error;
+    uint32_t i3c_notif;
+    uint32_t soc_ifc_error;
+    uint32_t soc_ifc_notif;
+    uint32_t sha512_acc_error;
+    uint32_t sha512_acc_notif;
+} caliptra_intr_received_s;
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
+
 //////////////////////////////////////////////////////////////////////////////
 // Function Declarations
 //
@@ -42,21 +69,86 @@ void init_interrupts(void);
 // These inline functions are used to insert event-specific functionality into the
 // otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr"
 inline void service_doe_error_intr() {return;}
-inline void service_doe_notif_intr() {return;}
+inline void service_doe_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.doe_notif |= DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad doe_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
 
 inline void service_ecc_error_intr() {return;}
-inline void service_ecc_notif_intr() {return;}
+inline void service_ecc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.ecc_notif |= ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad ecc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
 
 inline void service_hmac_error_intr() {return;}
-inline void service_hmac_notif_intr() {return;}
+inline void service_hmac_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.hmac_notif |= HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad hmac_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
 
 inline void service_kv_error_intr() {return;}
 inline void service_kv_notif_intr() {return;}
 inline void service_sha512_error_intr() {return;}
-inline void service_sha512_notif_intr() {return;}
+inline void service_sha512_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_notif |= SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
 
 inline void service_sha256_error_intr() {return;}
-inline void service_sha256_notif_intr() {return;}
+inline void service_sha256_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha256_notif |= SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha256_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
 
 inline void service_qspi_error_intr() {return;}
 inline void service_qspi_notif_intr() {return;}
@@ -71,25 +163,32 @@ inline void service_soc_ifc_error_intr() {
     /* Write 1 to Clear the pending interrupt */
     if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
         *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
     }
     if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) {
         *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
     }
     if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
         *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
     }
     if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK) {
         *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
     }
     if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK) {
         *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
     }
     if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) {
         *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
     }
     if (sts == 0) {
-        printf("bad soc_ifc_error_intr sts:%x\n", sts);
-        printf("%c", 0x1);
+        VPRINTF(ERROR,"bad soc_ifc_error_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
     }
 }
 
@@ -99,16 +198,32 @@ inline void service_soc_ifc_notif_intr () {
     /* Write 1 to Clear the pending interrupt */
     if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
         *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
     }
     if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK) {
         *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
     }
     if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
         *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
     }
     if (sts == 0) {
-        printf("bad soc_ifc_notif_intr sts:%x\n", sts);
-        printf("%c", 0x1);
+        VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
     }
 }
 
@@ -119,10 +234,12 @@ inline void service_sha512_acc_notif_intr() {
     /* Write 1 to Clear the pending interrupt */
     if (sts & SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
         *reg = SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_acc_notif |= SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
     }
     if (sts == 0) {
-        printf("bad sha512_acc_notif_intr sts:%x\n", sts);
-        printf("%c", 0x1);
+        VPRINTF(ERROR,"bad sha512_acc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
     }
 }
 
diff --git a/src/integration/test_suites/smoke_test_sram_ecc/smoke_test_sram_ecc.c b/src/integration/test_suites/smoke_test_sram_ecc/smoke_test_sram_ecc.c
index 9702e2464..f9c3ceb44 100644
--- a/src/integration/test_suites/smoke_test_sram_ecc/smoke_test_sram_ecc.c
+++ b/src/integration/test_suites/smoke_test_sram_ecc/smoke_test_sram_ecc.c
@@ -30,6 +30,31 @@ volatile uint32_t intr_count;
     enum printf_verbosity verbosity_g = LOW;
 #endif
 
+volatile caliptra_intr_received_s cptra_intr_rcv = {
+    .doe_error        = 0,
+    .doe_notif        = 0,
+    .ecc_error        = 0,
+    .ecc_notif        = 0,
+    .hmac_error       = 0,
+    .hmac_notif       = 0,
+    .kv_error         = 0,
+    .kv_notif         = 0,
+    .sha512_error     = 0,
+    .sha512_notif     = 0,
+    .sha256_error     = 0,
+    .sha256_notif     = 0,
+    .qspi_error       = 0,
+    .qspi_notif       = 0,
+    .uart_error       = 0,
+    .uart_notif       = 0,
+    .i3c_error        = 0,
+    .i3c_notif        = 0,
+    .soc_ifc_error    = 0,
+    .soc_ifc_notif    = 0,
+    .sha512_acc_error = 0,
+    .sha512_acc_notif = 0,
+};
+
 enum ecc_error_mode_type {
     NONE,
     SINGLE,
@@ -131,7 +156,6 @@ void main(void) {
         sts = test_mbox_sram_ecc();
 
         // Enable Random ECC double-bit error injection
-        SEND_STDOUT_CTRL( 0xfd);
         SEND_STDOUT_CTRL( 0xfe);
         ecc_error_mode = DOUBLE;
 
@@ -142,7 +166,7 @@ void main(void) {
         // TODO Test SRAM single-bit errors corrected during a mailbox protocol operation
 
         // Disable Random ECC double-bit error injection
-        SEND_STDOUT_CTRL( 0xfe);
+        SEND_STDOUT_CTRL( 0x0);
         ecc_error_mode = NONE;
 
         // Disable interrutps
diff --git a/src/integration/test_suites/smoke_test_trng/caliptra_isr.h b/src/integration/test_suites/smoke_test_trng/caliptra_isr.h
index 48879dc68..8f5779e04 100644
--- a/src/integration/test_suites/smoke_test_trng/caliptra_isr.h
+++ b/src/integration/test_suites/smoke_test_trng/caliptra_isr.h
@@ -32,39 +32,216 @@
 #include <stdint.h>
 #include "printf.h"
 
-//extern volatile uint32_t hmac_intr_status;
+/* --------------- symbols/typedefs --------------- */
+typedef struct {
+    uint32_t doe_error;
+    uint32_t doe_notif;
+    uint32_t ecc_error;
+    uint32_t ecc_notif;
+    uint32_t hmac_error;
+    uint32_t hmac_notif;
+    uint32_t kv_error;
+    uint32_t kv_notif;
+    uint32_t sha512_error;
+    uint32_t sha512_notif;
+    uint32_t sha256_error;
+    uint32_t sha256_notif;
+    uint32_t qspi_error;
+    uint32_t qspi_notif;
+    uint32_t uart_error;
+    uint32_t uart_notif;
+    uint32_t i3c_error;
+    uint32_t i3c_notif;
+    uint32_t soc_ifc_error;
+    uint32_t soc_ifc_notif;
+    uint32_t sha512_acc_error;
+    uint32_t sha512_acc_notif;
+} caliptra_intr_received_s;
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
 
 //////////////////////////////////////////////////////////////////////////////
 // Function Declarations
 //
+
 // Performs all the CSR setup to configure and enable vectored external interrupts
 void init_interrupts(void);
 
 // These inline functions are used to insert event-specific functionality into the
 // otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr"
-inline void service_doe_error_intr() {printf("ERROR");}
-inline void service_doe_notif_intr() {printf("ERROR");}
-inline void service_ecc_error_intr   () {printf("ERROR");}
-inline void service_ecc_notif_intr   () {printf("ERROR");}
-inline void service_hmac_error_intr  () {printf("ERROR");}
-inline void service_hmac_notif_intr  () {printf("ERROR");}
-
-inline void service_kv_error_intr    () {printf("ERROR");}
-inline void service_kv_notif_intr    () {printf("ERROR");}
-inline void service_sha512_error_intr() {printf("ERROR");}
-inline void service_sha512_notif_intr() {printf("ERROR");}
-inline void service_sha256_error_intr() {printf("ERROR");}
-inline void service_sha256_notif_intr() {printf("ERROR");}
-inline void service_qspi_error_intr  () {printf("ERROR");}
-inline void service_qspi_notif_intr  () {printf("ERROR");}
-inline void service_uart_error_intr  () {printf("ERROR");}
-inline void service_uart_notif_intr  () {printf("ERROR");}
-inline void service_i3c_error_intr   () {printf("ERROR");}
-inline void service_i3c_notif_intr   () {printf("ERROR");}
-inline void service_soc_ifc_error_intr  () {printf("ERROR");}
-inline void service_soc_ifc_notif_intr  () {printf("ERROR");}
-inline void service_sha512_acc_error_intr() {printf("ERROR");}
-inline void service_sha512_acc_notif_intr() {printf("ERROR");}
+inline void service_doe_error_intr() {return;}
+inline void service_doe_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.doe_notif |= DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad doe_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_ecc_error_intr() {return;}
+inline void service_ecc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.ecc_notif |= ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad ecc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_hmac_error_intr() {return;}
+inline void service_hmac_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.hmac_notif |= HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad hmac_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_kv_error_intr() {return;}
+inline void service_kv_notif_intr() {return;}
+inline void service_sha512_error_intr() {return;}
+inline void service_sha512_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_notif |= SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha256_error_intr() {return;}
+inline void service_sha256_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha256_notif |= SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha256_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_qspi_error_intr() {return;}
+inline void service_qspi_notif_intr() {return;}
+inline void service_uart_error_intr() {return;}
+inline void service_uart_notif_intr() {return;}
+inline void service_i3c_error_intr() {return;}
+inline void service_i3c_notif_intr() {return;}
+
+inline void service_soc_ifc_error_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_error_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_soc_ifc_notif_intr () {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha512_acc_error_intr() {return;}
+inline void service_sha512_acc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_acc_notif |= SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_acc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
 
 
 #endif //CALIPTRA_ISR_H
diff --git a/src/integration/test_suites/smoke_test_trng/smoke_test_trng.c b/src/integration/test_suites/smoke_test_trng/smoke_test_trng.c
index 97c43b9a2..e0e34369f 100644
--- a/src/integration/test_suites/smoke_test_trng/smoke_test_trng.c
+++ b/src/integration/test_suites/smoke_test_trng/smoke_test_trng.c
@@ -31,6 +31,31 @@ enum printf_verbosity verbosity_g = CPT_VERBOSITY;
 enum printf_verbosity verbosity_g = LOW;
 #endif
 
+volatile caliptra_intr_received_s cptra_intr_rcv = {
+    .doe_error        = 0,
+    .doe_notif        = 0,
+    .ecc_error        = 0,
+    .ecc_notif        = 0,
+    .hmac_error       = 0,
+    .hmac_notif       = 0,
+    .kv_error         = 0,
+    .kv_notif         = 0,
+    .sha512_error     = 0,
+    .sha512_notif     = 0,
+    .sha256_error     = 0,
+    .sha256_notif     = 0,
+    .qspi_error       = 0,
+    .qspi_notif       = 0,
+    .uart_error       = 0,
+    .uart_notif       = 0,
+    .i3c_error        = 0,
+    .i3c_notif        = 0,
+    .soc_ifc_error    = 0,
+    .soc_ifc_notif    = 0,
+    .sha512_acc_error = 0,
+    .sha512_acc_notif = 0,
+};
+
 // read data and compare against expected value. If there is no error, return 0
 int read_and_compare(uint32_t addr, uint32_t exp_data) {
   uint32_t act_data;
diff --git a/src/integration/test_suites/smoke_test_uart/caliptra_isr.h b/src/integration/test_suites/smoke_test_uart/caliptra_isr.h
index 23b511c4b..fca82fef0 100644
--- a/src/integration/test_suites/smoke_test_uart/caliptra_isr.h
+++ b/src/integration/test_suites/smoke_test_uart/caliptra_isr.h
@@ -32,39 +32,212 @@
 #include <stdint.h>
 #include "printf.h"
 
-//extern volatile uint32_t hmac_intr_status;
+/* --------------- symbols/typedefs --------------- */
+typedef struct {
+    uint32_t doe_error;
+    uint32_t doe_notif;
+    uint32_t ecc_error;
+    uint32_t ecc_notif;
+    uint32_t hmac_error;
+    uint32_t hmac_notif;
+    uint32_t kv_error;
+    uint32_t kv_notif;
+    uint32_t sha512_error;
+    uint32_t sha512_notif;
+    uint32_t sha256_error;
+    uint32_t sha256_notif;
+    uint32_t qspi_error;
+    uint32_t qspi_notif;
+    uint32_t uart_error;
+    uint32_t uart_notif;
+    uint32_t i3c_error;
+    uint32_t i3c_notif;
+    uint32_t soc_ifc_error;
+    uint32_t soc_ifc_notif;
+    uint32_t sha512_acc_error;
+    uint32_t sha512_acc_notif;
+} caliptra_intr_received_s;
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
 
 //////////////////////////////////////////////////////////////////////////////
 // Function Declarations
 //
+
 // Performs all the CSR setup to configure and enable vectored external interrupts
 void init_interrupts(void);
 
 // These inline functions are used to insert event-specific functionality into the
-// otherwise generic ISR that gets laid down by the parameterized macro "nonstd_swerv_isr"
-inline void service_doe_error_intr() {printf("ERROR");}
-inline void service_doe_notif_intr() {printf("ERROR");}
-inline void service_ecc_error_intr   () {printf("ERROR");}
-inline void service_ecc_notif_intr   () {printf("ERROR");}
-inline void service_hmac_error_intr  () {printf("ERROR");}
-inline void service_hmac_notif_intr  () {printf("ERROR");}
-
-inline void service_kv_error_intr    () {printf("ERROR");}
-inline void service_kv_notif_intr    () {printf("ERROR");}
-inline void service_sha512_error_intr() {printf("ERROR");}
-inline void service_sha512_notif_intr() {printf("ERROR");}
-inline void service_sha256_error_intr() {printf("ERROR");}
-inline void service_sha256_notif_intr() {printf("ERROR");}
-inline void service_qspi_error_intr  () {printf("ERROR");}
-inline void service_qspi_notif_intr  () {printf("ERROR");}
-inline void service_uart_error_intr  () {printf("ERROR");}
-inline void service_uart_notif_intr  () {printf("ERROR");}
-inline void service_i3c_error_intr   () {printf("ERROR");}
-inline void service_i3c_notif_intr   () {printf("ERROR");}
-inline void service_soc_ifc_error_intr  () {printf("ERROR");}
-inline void service_soc_ifc_notif_intr  () {printf("ERROR");}
-inline void service_sha512_acc_error_intr() {printf("ERROR");}
-inline void service_sha512_acc_notif_intr() {printf("ERROR");}
+// otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr"
+inline void service_doe_error_intr() {return;}
+inline void service_doe_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.doe_notif |= DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad doe_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_ecc_error_intr() {return;}
+inline void service_ecc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.ecc_notif |= ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad ecc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_hmac_error_intr() {return;}
+inline void service_hmac_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.hmac_notif |= HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad hmac_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_kv_error_intr() {return;}
+inline void service_kv_notif_intr() {return;}
+inline void service_sha512_error_intr() {return;}
+inline void service_sha512_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_notif |= SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha256_error_intr() {return;}
+inline void service_sha256_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha256_notif |= SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha256_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_qspi_error_intr() {return;}
+inline void service_qspi_notif_intr() {return;}
+inline void service_uart_error_intr() {return;}
+inline void service_uart_notif_intr() {return;}
+inline void service_i3c_error_intr() {return;}
+inline void service_i3c_notif_intr() {return;}
+
+inline void service_soc_ifc_error_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_error_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_soc_ifc_notif_intr () {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha512_acc_error_intr() {return;}
+inline void service_sha512_acc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_acc_notif |= SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_acc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
 
 
 #endif //CALIPTRA_ISR_H
diff --git a/src/integration/test_suites/smoke_test_uart/smoke_test_uart.c b/src/integration/test_suites/smoke_test_uart/smoke_test_uart.c
index b5c97eb38..c0918a194 100644
--- a/src/integration/test_suites/smoke_test_uart/smoke_test_uart.c
+++ b/src/integration/test_suites/smoke_test_uart/smoke_test_uart.c
@@ -31,6 +31,31 @@ enum printf_verbosity verbosity_g = CPT_VERBOSITY;
 enum printf_verbosity verbosity_g = LOW;
 #endif
 
+volatile caliptra_intr_received_s cptra_intr_rcv = {
+    .doe_error        = 0,
+    .doe_notif        = 0,
+    .ecc_error        = 0,
+    .ecc_notif        = 0,
+    .hmac_error       = 0,
+    .hmac_notif       = 0,
+    .kv_error         = 0,
+    .kv_notif         = 0,
+    .sha512_error     = 0,
+    .sha512_notif     = 0,
+    .sha256_error     = 0,
+    .sha256_notif     = 0,
+    .qspi_error       = 0,
+    .qspi_notif       = 0,
+    .uart_error       = 0,
+    .uart_notif       = 0,
+    .i3c_error        = 0,
+    .i3c_notif        = 0,
+    .soc_ifc_error    = 0,
+    .soc_ifc_notif    = 0,
+    .sha512_acc_error = 0,
+    .sha512_acc_notif = 0,
+};
+
 void end_sim_if_uart_disabled() {
   uint32_t hw_cfg;
   hw_cfg = lsu_read_32(CLP_SOC_IFC_REG_CPTRA_HW_CONFIG);
diff --git a/src/integration/test_suites/smoke_test_veer/caliptra_isr.h b/src/integration/test_suites/smoke_test_veer/caliptra_isr.h
new file mode 100644
index 000000000..8f5779e04
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_veer/caliptra_isr.h
@@ -0,0 +1,247 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// ---------------------------------------------------------------------
+// File: caliptra_isr.h
+// Description:
+//     Provides function declarations for use by external test files, so
+//     that the ISR functionality may behave like a library.
+//     TODO:
+//     This header file includes inline function definitions for event and
+//     test specific interrupt service behavior, so it should be copied and
+//     modified for each test.
+// ---------------------------------------------------------------------
+
+#ifndef CALIPTRA_ISR_H
+    #define CALIPTRA_ISR_H
+
+#define EN_ISR_PRINTS 1
+
+#include "caliptra_defines.h"
+#include <stdint.h>
+#include "printf.h"
+
+/* --------------- symbols/typedefs --------------- */
+typedef struct {
+    uint32_t doe_error;
+    uint32_t doe_notif;
+    uint32_t ecc_error;
+    uint32_t ecc_notif;
+    uint32_t hmac_error;
+    uint32_t hmac_notif;
+    uint32_t kv_error;
+    uint32_t kv_notif;
+    uint32_t sha512_error;
+    uint32_t sha512_notif;
+    uint32_t sha256_error;
+    uint32_t sha256_notif;
+    uint32_t qspi_error;
+    uint32_t qspi_notif;
+    uint32_t uart_error;
+    uint32_t uart_notif;
+    uint32_t i3c_error;
+    uint32_t i3c_notif;
+    uint32_t soc_ifc_error;
+    uint32_t soc_ifc_notif;
+    uint32_t sha512_acc_error;
+    uint32_t sha512_acc_notif;
+} caliptra_intr_received_s;
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
+
+//////////////////////////////////////////////////////////////////////////////
+// Function Declarations
+//
+
+// Performs all the CSR setup to configure and enable vectored external interrupts
+void init_interrupts(void);
+
+// These inline functions are used to insert event-specific functionality into the
+// otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr"
+inline void service_doe_error_intr() {return;}
+inline void service_doe_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.doe_notif |= DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad doe_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_ecc_error_intr() {return;}
+inline void service_ecc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.ecc_notif |= ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad ecc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_hmac_error_intr() {return;}
+inline void service_hmac_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.hmac_notif |= HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad hmac_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_kv_error_intr() {return;}
+inline void service_kv_notif_intr() {return;}
+inline void service_sha512_error_intr() {return;}
+inline void service_sha512_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_notif |= SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha256_error_intr() {return;}
+inline void service_sha256_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha256_notif |= SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha256_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_qspi_error_intr() {return;}
+inline void service_qspi_notif_intr() {return;}
+inline void service_uart_error_intr() {return;}
+inline void service_uart_notif_intr() {return;}
+inline void service_i3c_error_intr() {return;}
+inline void service_i3c_notif_intr() {return;}
+
+inline void service_soc_ifc_error_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_error_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_soc_ifc_notif_intr () {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha512_acc_error_intr() {return;}
+inline void service_sha512_acc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_acc_notif |= SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_acc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+
+#endif //CALIPTRA_ISR_H
diff --git a/src/integration/test_suites/smoke_test_veer/smoke_test_veer.s b/src/integration/test_suites/smoke_test_veer/smoke_test_veer.s
index cfa976142..13b673627 100644
--- a/src/integration/test_suites/smoke_test_veer/smoke_test_veer.s
+++ b/src/integration/test_suites/smoke_test_veer/smoke_test_veer.s
@@ -39,6 +39,9 @@ _start:
     li x1, 0xaaaaaaaa
     csrw 0x7c0, x1
 
+    // Call interrupt init
+    call init_interrupts
+
     // Load string from hw_data
     // and write to stdout address
 
@@ -66,6 +69,11 @@ _finish:
 stdout: .word STDOUT
 .global verbosity_g
 verbosity_g: .word 2
+// FW polls this variable for intr
+.global intr_count
+intr_count: .word 0
+.global cptra_intr_rcv
+cptra_intr_rcv: .word 0
 hw_data:
 .ascii "----------------------------------\n"
 .ascii "Hello World from VeeR EL2  !!\n"
diff --git a/src/integration/test_suites/smoke_test_wdt/caliptra_isr.h b/src/integration/test_suites/smoke_test_wdt/caliptra_isr.h
index c53e94942..bb60f9fb2 100644
--- a/src/integration/test_suites/smoke_test_wdt/caliptra_isr.h
+++ b/src/integration/test_suites/smoke_test_wdt/caliptra_isr.h
@@ -34,6 +34,33 @@
 
 //extern volatile uint32_t hmac_intr_status;
 
+/* --------------- symbols/typedefs --------------- */
+typedef struct {
+    uint32_t doe_error;
+    uint32_t doe_notif;
+    uint32_t ecc_error;
+    uint32_t ecc_notif;
+    uint32_t hmac_error;
+    uint32_t hmac_notif;
+    uint32_t kv_error;
+    uint32_t kv_notif;
+    uint32_t sha512_error;
+    uint32_t sha512_notif;
+    uint32_t sha256_error;
+    uint32_t sha256_notif;
+    uint32_t qspi_error;
+    uint32_t qspi_notif;
+    uint32_t uart_error;
+    uint32_t uart_notif;
+    uint32_t i3c_error;
+    uint32_t i3c_notif;
+    uint32_t soc_ifc_error;
+    uint32_t soc_ifc_notif;
+    uint32_t sha512_acc_error;
+    uint32_t sha512_acc_notif;
+} caliptra_intr_received_s;
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
+
 //////////////////////////////////////////////////////////////////////////////
 // Function Declarations
 //
diff --git a/src/integration/test_suites/smoke_test_wdt/smoke_test_wdt.c b/src/integration/test_suites/smoke_test_wdt/smoke_test_wdt.c
index 9e2fe497d..2dae66c8d 100644
--- a/src/integration/test_suites/smoke_test_wdt/smoke_test_wdt.c
+++ b/src/integration/test_suites/smoke_test_wdt/smoke_test_wdt.c
@@ -43,6 +43,31 @@ volatile uint32_t * wdt_timer2_period_1 = (uint32_t *) CLP_SOC_IFC_REG_CPTRA_WDT
 
 volatile uint32_t * hw_error_fatal      = (uint32_t *) CLP_SOC_IFC_REG_CPTRA_HW_ERROR_FATAL;
 
+volatile caliptra_intr_received_s cptra_intr_rcv = {
+    .doe_error        = 0,
+    .doe_notif        = 0,
+    .ecc_error        = 0,
+    .ecc_notif        = 0,
+    .hmac_error       = 0,
+    .hmac_notif       = 0,
+    .kv_error         = 0,
+    .kv_notif         = 0,
+    .sha512_error     = 0,
+    .sha512_notif     = 0,
+    .sha256_error     = 0,
+    .sha256_notif     = 0,
+    .qspi_error       = 0,
+    .qspi_notif       = 0,
+    .uart_error       = 0,
+    .uart_notif       = 0,
+    .i3c_error        = 0,
+    .i3c_notif        = 0,
+    .soc_ifc_error    = 0,
+    .soc_ifc_notif    = 0,
+    .sha512_acc_error = 0,
+    .sha512_acc_notif = 0,
+};
+
 void main() {
     VPRINTF(LOW, "---------------------------\n");
     VPRINTF(LOW, " WDT Smoke Test !!\n");
@@ -99,6 +124,11 @@ void main() {
     }
     else {
         //Write 1 to clear HW fatal error register
-        *hw_error_fatal = 0x00000001;
+        if ((*hw_error_fatal && SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_NMI_PIN_MASK) == 1) {
+            *hw_error_fatal = SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_NMI_PIN_MASK;
+        }
+        else {
+            VPRINTF(ERROR, "Did not see expected hw fatal error!");
+        }
     }
 }
diff --git a/src/integration/test_suites/smoke_test_zeroize_crypto/caliptra_isr.h b/src/integration/test_suites/smoke_test_zeroize_crypto/caliptra_isr.h
new file mode 100644
index 000000000..8f5779e04
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_zeroize_crypto/caliptra_isr.h
@@ -0,0 +1,247 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// ---------------------------------------------------------------------
+// File: caliptra_isr.h
+// Description:
+//     Provides function declarations for use by external test files, so
+//     that the ISR functionality may behave like a library.
+//     TODO:
+//     This header file includes inline function definitions for event and
+//     test specific interrupt service behavior, so it should be copied and
+//     modified for each test.
+// ---------------------------------------------------------------------
+
+#ifndef CALIPTRA_ISR_H
+    #define CALIPTRA_ISR_H
+
+#define EN_ISR_PRINTS 1
+
+#include "caliptra_defines.h"
+#include <stdint.h>
+#include "printf.h"
+
+/* --------------- symbols/typedefs --------------- */
+typedef struct {
+    uint32_t doe_error;
+    uint32_t doe_notif;
+    uint32_t ecc_error;
+    uint32_t ecc_notif;
+    uint32_t hmac_error;
+    uint32_t hmac_notif;
+    uint32_t kv_error;
+    uint32_t kv_notif;
+    uint32_t sha512_error;
+    uint32_t sha512_notif;
+    uint32_t sha256_error;
+    uint32_t sha256_notif;
+    uint32_t qspi_error;
+    uint32_t qspi_notif;
+    uint32_t uart_error;
+    uint32_t uart_notif;
+    uint32_t i3c_error;
+    uint32_t i3c_notif;
+    uint32_t soc_ifc_error;
+    uint32_t soc_ifc_notif;
+    uint32_t sha512_acc_error;
+    uint32_t sha512_acc_notif;
+} caliptra_intr_received_s;
+extern volatile caliptra_intr_received_s cptra_intr_rcv;
+
+//////////////////////////////////////////////////////////////////////////////
+// Function Declarations
+//
+
+// Performs all the CSR setup to configure and enable vectored external interrupts
+void init_interrupts(void);
+
+// These inline functions are used to insert event-specific functionality into the
+// otherwise generic ISR that gets laid down by the parameterized macro "nonstd_veer_isr"
+inline void service_doe_error_intr() {return;}
+inline void service_doe_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.doe_notif |= DOE_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad doe_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_ecc_error_intr() {return;}
+inline void service_ecc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.ecc_notif |= ECC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad ecc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_hmac_error_intr() {return;}
+inline void service_hmac_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.hmac_notif |= HMAC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad hmac_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_kv_error_intr() {return;}
+inline void service_kv_notif_intr() {return;}
+inline void service_sha512_error_intr() {return;}
+inline void service_sha512_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_notif |= SHA512_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha256_error_intr() {return;}
+inline void service_sha256_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha256_notif |= SHA256_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha256_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_qspi_error_intr() {return;}
+inline void service_qspi_notif_intr() {return;}
+inline void service_uart_error_intr() {return;}
+inline void service_uart_notif_intr() {return;}
+inline void service_i3c_error_intr() {return;}
+inline void service_i3c_notif_intr() {return;}
+
+inline void service_soc_ifc_error_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+        cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_error_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_soc_ifc_notif_intr () {
+    uint32_t * reg = (uint32_t *) (CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK;
+    }
+    if (sts & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK) {
+        *reg = SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+        cptra_intr_rcv.soc_ifc_notif |= SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad soc_ifc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+inline void service_sha512_acc_error_intr() {return;}
+inline void service_sha512_acc_notif_intr() {
+    uint32_t * reg = (uint32_t *) (CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R);
+    uint32_t sts = *reg;
+    /* Write 1 to Clear the pending interrupt */
+    if (sts & SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK) {
+        *reg = SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+        cptra_intr_rcv.sha512_acc_notif |= SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK;
+    }
+    if (sts == 0) {
+        VPRINTF(ERROR,"bad sha512_acc_notif_intr sts:%x\n", sts);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    }
+}
+
+
+#endif //CALIPTRA_ISR_H
diff --git a/src/integration/test_suites/smoke_test_zeroize_crypto/smoke_test_zeroize_crypto.c b/src/integration/test_suites/smoke_test_zeroize_crypto/smoke_test_zeroize_crypto.c
new file mode 100644
index 000000000..5d2305faf
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_zeroize_crypto/smoke_test_zeroize_crypto.c
@@ -0,0 +1,203 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+
+#include "caliptra_defines.h"
+#include "caliptra_isr.h"
+#include "riscv_hw_if.h"
+#include "riscv-csr.h"
+#include <string.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include "printf.h"
+#include "hmac.h"
+
+volatile char*    stdout           = (char *)STDOUT;
+volatile uint32_t intr_count = 0;
+
+#ifdef CPT_VERBOSITY
+    enum printf_verbosity verbosity_g = CPT_VERBOSITY;
+#else
+    enum printf_verbosity verbosity_g = LOW;
+#endif
+
+volatile caliptra_intr_received_s cptra_intr_rcv = {
+    .doe_error        = 0,
+    .doe_notif        = 0,
+    .ecc_error        = 0,
+    .ecc_notif        = 0,
+    .hmac_error       = 0,
+    .hmac_notif       = 0,
+    .kv_error         = 0,
+    .kv_notif         = 0,
+    .sha512_error     = 0,
+    .sha512_notif     = 0,
+    .sha256_error     = 0,
+    .sha256_notif     = 0,
+    .qspi_error       = 0,
+    .qspi_notif       = 0,
+    .uart_error       = 0,
+    .uart_notif       = 0,
+    .i3c_error        = 0,
+    .i3c_notif        = 0,
+    .soc_ifc_error    = 0,
+    .soc_ifc_notif    = 0,
+    .sha512_acc_error = 0,
+    .sha512_acc_notif = 0,
+};
+
+
+/* HMAC384 test vector
+    KEY = 0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b
+    BLOCK = 4869205468657265800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000440
+    LFSR_SEED = C8F518D4F3AA1BD46ED56C1C3C9E16FB800AF504
+    TAG = b6a8d5636f5c6a7224f9977dcf7ee6c7fb6d0c48cbdee9737a959796489bddbc4c5df61d5b3297b4fb68dab9f1b582c2
+*/
+
+
+
+
+void main() {
+    printf("----------------------------------\n");
+    printf(" Smoke Test With Crypto Zeroize !!\n");
+    printf("----------------------------------\n");
+
+    //Call interrupt init
+    init_interrupts();
+
+    uint32_t block[32] =   {0x48692054,
+                            0x68657265,
+                            0x80000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000000,
+                            0x00000440};
+
+    //this is a random lfsr_seed 160-bit
+    uint32_t lfsr_seed_data[5] = {0xC8F518D4,
+                                 0xF3AA1BD4,
+                                 0x6ED56C1C,
+                                 0x3C9E16FB,
+                                 0x800AF504}; 
+
+    uint32_t expected_tag[12] =   {0xb6a8d563,
+                                    0x6f5c6a72,
+                                    0x24f9977d,
+                                    0xcf7ee6c7,
+                                    0xfb6d0c48,
+                                    0xcbdee973,
+                                    0x7a959796,
+                                    0x489bddbc,
+                                    0x4c5df61d,
+                                    0x5b3297b4,
+                                    0xfb68dab9,
+                                    0xf1b582c2}; 
+
+
+    uint8_t hmackey_kv_id       = 0x2;
+    uint8_t tag_kv_id           = 0x0;
+    uint8_t offset;
+    volatile uint32_t * reg_ptr;
+    uint8_t fail_cmd = 0x1;
+    uint32_t check_data;
+
+    //inject hmac_key to kv key reg (in RTL)
+    uint8_t key_inject_cmd = 0xa0 + (hmackey_kv_id & 0x7);
+    printf("%c", key_inject_cmd);
+
+    // wait for HMAC to be ready
+    while((lsu_read_32(CLP_HMAC_REG_HMAC384_STATUS) & HMAC_REG_HMAC384_STATUS_READY_MASK) == 0);
+
+
+    // Program KEY Read with 12 dwords from key_kv_id
+    lsu_write_32(CLP_HMAC_REG_HMAC384_KV_RD_KEY_CTRL, HMAC_REG_HMAC384_KV_RD_KEY_CTRL_READ_EN_MASK |
+                                                    ((hmackey_kv_id << HMAC_REG_HMAC384_KV_RD_KEY_CTRL_READ_ENTRY_LOW) & HMAC_REG_HMAC384_KV_RD_KEY_CTRL_READ_ENTRY_MASK));
+
+    // Check that HMAC KEY is loaded
+    while((lsu_read_32(CLP_HMAC_REG_HMAC384_KV_RD_KEY_STATUS) & HMAC_REG_HMAC384_KV_RD_KEY_STATUS_VALID_MASK) == 0);
+
+
+
+    reg_ptr = (uint32_t*) CLP_HMAC_REG_HMAC384_BLOCK_0;
+    offset = 0;
+    while (reg_ptr <= (uint32_t*) CLP_HMAC_REG_HMAC384_BLOCK_31) {
+        *reg_ptr++ = block[offset++];
+    }
+
+
+    // Program LFSR_SEED
+    reg_ptr = (uint32_t*) CLP_HMAC_REG_HMAC384_LFSR_SEED_0;
+    offset = 0;
+    while (reg_ptr <= (uint32_t*) CLP_HMAC_REG_HMAC384_LFSR_SEED_4) {
+        *reg_ptr++ = lfsr_seed_data[offset++];
+    }
+
+    // if we want to store the results into kv
+    // set tag DEST to write
+
+    lsu_write_32(CLP_HMAC_REG_HMAC384_KV_WR_CTRL, HMAC_REG_HMAC384_KV_WR_CTRL_WRITE_EN_MASK |
+                                                HMAC_REG_HMAC384_KV_WR_CTRL_HMAC_KEY_DEST_VALID_MASK  |
+                                                HMAC_REG_HMAC384_KV_WR_CTRL_HMAC_BLOCK_DEST_VALID_MASK|
+                                                HMAC_REG_HMAC384_KV_WR_CTRL_SHA_BLOCK_DEST_VALID_MASK |
+                                                HMAC_REG_HMAC384_KV_WR_CTRL_ECC_PKEY_DEST_VALID_MASK  |
+                                                HMAC_REG_HMAC384_KV_WR_CTRL_ECC_SEED_DEST_VALID_MASK  |
+                                                ((tag_kv_id << HMAC_REG_HMAC384_KV_WR_CTRL_WRITE_ENTRY_LOW) & HMAC_REG_HMAC384_KV_WR_CTRL_WRITE_ENTRY_MASK));
+
+
+    //inject zeroize command (in RTL)
+    SEND_STDOUT_CTRL(0x99);
+
+    // Enable HMAC core
+    lsu_write_32(CLP_HMAC_REG_HMAC384_CTRL, HMAC_REG_HMAC384_CTRL_INIT_MASK);
+
+    // wait for HMAC to be ready
+    while((lsu_read_32(CLP_HMAC_REG_HMAC384_STATUS) & HMAC_REG_HMAC384_STATUS_READY_MASK) == 0);
+
+    // check that dest valid bits are 0 since the key generation was interrupted
+    check_data = lsu_read_32(CLP_KV_REG_KEY_CTRL_0);
+    if ((check_data & (KV_REG_KEY_CTRL_0_DEST_VALID_MASK)) != 0) {
+        VPRINTF(ERROR, "ERROR: Dest valid mismatch actual (0x%x) expected (0x00000000)\n", check_data);
+        SEND_STDOUT_CTRL(0x1);
+        while(1);
+    } else {
+        SEND_STDOUT_CTRL(0xff); //End the test
+    }
+
+    
+}
diff --git a/src/integration/test_suites/smoke_test_zeroize_crypto/smoke_test_zeroize_crypto.yml b/src/integration/test_suites/smoke_test_zeroize_crypto/smoke_test_zeroize_crypto.yml
new file mode 100644
index 000000000..fe168f04a
--- /dev/null
+++ b/src/integration/test_suites/smoke_test_zeroize_crypto/smoke_test_zeroize_crypto.yml
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+---
+seed: 1
+testname: smoke_test_zeroize_crypto
\ No newline at end of file
diff --git a/src/integration/testplan/caliptra_top.hvp b/src/integration/testplan/caliptra_top.hvp
new file mode 100644
index 000000000..fb0e9f90c
--- /dev/null
+++ b/src/integration/testplan/caliptra_top.hvp
@@ -0,0 +1,16 @@
+
+plan "CAPI Coverage";
+
+
+    feature "Design coverage";
+        measure Line, Cond, FSM, Toggle, Branch, Assert CodeCov;
+            source = "tree: *";
+        endmeasure
+    endfeature
+    feature "Functional Coverage";
+        measure Group, Group.count, Group.covered_count, Group.uncovered_count FuncCov;
+            source = "group: *", "group instance: *";
+        endmeasure
+    endfeature
+endplan
+
diff --git a/src/integration/uvmf_caliptra_top/config/compile.yml b/src/integration/uvmf_caliptra_top/config/compile.yml
index 40f56d2ac..a6eaa74e2 100644
--- a/src/integration/uvmf_caliptra_top/config/compile.yml
+++ b/src/integration/uvmf_caliptra_top/config/compile.yml
@@ -16,6 +16,11 @@ schema_version: 2.4.0
 requires:
   - uvmf_caliptra_top_vip
   - caliptra_top
+  - sha512_coverage
+  - sha256_coverage
+  - hmac_coverage
+  - ecc_coverage
+  - soc_ifc_coverage
 targets:
   tb:
     directories:
@@ -28,24 +33,21 @@ targets:
       - ${COMPILE_ROOT}/uvmf_template_output/project_benches/caliptra_top/tb/parameters/caliptra_top_parameters_pkg.sv
       - ${COMPILE_ROOT}/uvmf_template_output/project_benches/caliptra_top/tb/sequences/caliptra_top_sequences_pkg.sv
       - ${COMPILE_ROOT}/uvmf_template_output/project_benches/caliptra_top/tb/tests/caliptra_top_tests_pkg.sv
-      - ${COMPILE_ROOT}/../tb/caliptra_veer_sram_export.sv
       - ${COMPILE_ROOT}/../tb/caliptra_top_tb_pkg.sv
+      - ${COMPILE_ROOT}/../tb/caliptra_veer_sram_export.sv
       - ${COMPILE_ROOT}/../tb/caliptra_top_tb_services.sv
+      - ${COMPILE_ROOT}/../coverage/caliptra_top_cov_if.sv
+      - ${COMPILE_ROOT}/../coverage/caliptra_top_cov_bind.sv
       - ${COMPILE_ROOT}/uvmf_template_output/project_benches/caliptra_top/tb/testbench/hdl_top.sv
       - ${COMPILE_ROOT}/uvmf_template_output/project_benches/caliptra_top/tb/testbench/hvl_top.sv
     tops:
       - hdl_top
       - hvl_top
   sim:
-    # TODO: Eventually we will load caliptra_fmc/rt hexfiles to mailbox in the TB logic instead
-    #       of preloading here with this rename approach
     pre_exec: |
         echo "[PRE-EXEC] Copying SHA512 Vectors to $(pwd)"
         cp ${COMPILE_ROOT}/../tb/vectors/SHA*.rsp .
-        make -f ${CALIPTRA_ROOT}/tools/scripts/Makefile TESTNAME=caliptra_top program.hex
-        make -f ${CALIPTRA_ROOT}/tools/scripts/Makefile TESTNAME=caliptra_fmc caliptra_fmc.hex
-        make -f ${CALIPTRA_ROOT}/tools/scripts/Makefile TESTNAME=caliptra_rt  caliptra_rt.hex
-        cp caliptra_fmc.hex mailbox.hex
+        $TOOLS/scripts/run_test_makefile
 global:
   tool:
     vcs:
@@ -76,3 +78,44 @@ global:
         - '-sv_lib libapb3_IN_SystemVerilog_VCS_full'
         # Report "MVC_ERROR" as "UVM_ERROR"
         - '+QVIP_UVM_REPORTING'
+---
+provides: [uvmf_caliptra_top_itrng]
+schema_version: 2.4.0
+requires:
+  - uvmf_caliptra_top
+targets:
+  tb:
+    tops:
+      - hdl_top
+      - hvl_top
+  sim:
+    pre_exec: |
+        echo "[PRE-EXEC] Copying SHA512 Vectors to $(pwd)"
+        cp ${COMPILE_ROOT}/../tb/vectors/SHA*.rsp .
+        $TOOLS/scripts/run_test_makefile
+global:
+  tool:
+    vcs:
+      default:
+        - '-assert svaext'
+        - +define+CLP_ASSERT_ON
+        - '-noinherit_timescale=1ns/1ps'
+        - '+define+CALIPTRA_INTERNAL_TRNG'
+        # Suppress a warning due to calling $fgets as task instead of function
+        # i.e. discarding the return value. This is in auto-generated code.
+        - '+warn=noRVOSFD'
+        # Suppress NOTE about repeated package imports within the same
+        # package (each .svh file included in the auto-generated UVM _pkg.sv
+        # files imports the same dependencies)
+        - '-suppress=SV-LCM-PPWI'
+      elab:
+        # Suppress warnings about too few port connections - auto-generated interfaces
+        # declare all signals as inout, but are driven at a lower layer than the
+        # instantiation, so they will always flag this
+        - '-suppress=TFIPC'
+      sim:
+        - '-sv_root $QUESTA_MVC_HOME/questa_mvc_core/linux_x86_64_gcc-6.2.0_vcs'
+        - '-sv_lib libahb_IN_SystemVerilog_VCS_full'
+        - '-sv_lib libapb3_IN_SystemVerilog_VCS_full'
+        # Report "MVC_ERROR" as "UVM_ERROR"
+        - '+QVIP_UVM_REPORTING'
diff --git a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/parameters/caliptra_top_parameters_pkg.sv b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/parameters/caliptra_top_parameters_pkg.sv
index 5652f4e6b..514477d8f 100644
--- a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/parameters/caliptra_top_parameters_pkg.sv
+++ b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/parameters/caliptra_top_parameters_pkg.sv
@@ -45,6 +45,7 @@ package caliptra_top_parameters_pkg;
   parameter string soc_ifc_subenv_cptra_ctrl_agent_BFM  = "soc_ifc_subenv_cptra_ctrl_agent_BFM"; /* [3] */
   parameter string soc_ifc_subenv_soc_ifc_status_agent_BFM  = "soc_ifc_subenv_soc_ifc_status_agent_BFM"; /* [4] */
   parameter string soc_ifc_subenv_cptra_status_agent_BFM  = "soc_ifc_subenv_cptra_status_agent_BFM"; /* [5] */
+  parameter string soc_ifc_subenv_mbox_sram_agent_BFM  = "soc_ifc_subenv_mbox_sram_agent_BFM"; /* [6] */
 
   // pragma uvmf custom package_item_additional begin
   // pragma uvmf custom package_item_additional end
diff --git a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/caliptra_top_sequences_pkg.sv b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/caliptra_top_sequences_pkg.sv
index 9f12b1fc2..e890eda40 100644
--- a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/caliptra_top_sequences_pkg.sv
+++ b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/caliptra_top_sequences_pkg.sv
@@ -47,6 +47,8 @@ package caliptra_top_sequences_pkg;
   import soc_ifc_status_pkg_hdl::*;
   import cptra_status_pkg::*;
   import cptra_status_pkg_hdl::*;
+  import mbox_sram_pkg::*;
+  import mbox_sram_pkg_hdl::*;
   import caliptra_top_parameters_pkg::*;
   import caliptra_top_env_pkg::*;
   import qvip_ahb_lite_slave_params_pkg::*;
@@ -68,9 +70,10 @@ package caliptra_top_sequences_pkg;
   //    compiled as part of the sequence package.  Be sure to place
   //    the new sequence after any base sequences of the new sequence.
   `include "src/caliptra_top_rand_sequence.svh"
-  `include "src/caliptra_top_fw_update_sequence.svh"
-  `include "src/caliptra_top_reg_access_sequence.svh"
   `include "src/caliptra_top_cmdline_sequence.svh"
+  `include "src/caliptra_top_rom_sequence.svh"
+  `include "src/caliptra_top_wdt_sequence.svh"
+  `include "src/caliptra_top_wdt_independent_sequence.svh"
   // pragma uvmf custom package_item_additional end
 
 endpackage
diff --git a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_bench_sequence_base.svh b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_bench_sequence_base.svh
index d0303bd74..cf13af914 100644
--- a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_bench_sequence_base.svh
+++ b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_bench_sequence_base.svh
@@ -57,6 +57,8 @@ rand soc_ifc_env_sequence_base_t soc_ifc_env_seq;
   soc_ifc_subenv_soc_ifc_ctrl_agent_random_seq_t soc_ifc_subenv_soc_ifc_ctrl_agent_random_seq;
   typedef soc_ifc_status_responder_sequence  soc_ifc_subenv_soc_ifc_status_agent_responder_seq_t;
   soc_ifc_subenv_soc_ifc_status_agent_responder_seq_t soc_ifc_subenv_soc_ifc_status_agent_responder_seq;
+  typedef mbox_sram_responder_sequence  soc_ifc_subenv_mbox_sram_agent_responder_seq_t;
+  soc_ifc_subenv_mbox_sram_agent_responder_seq_t soc_ifc_subenv_mbox_sram_agent_responder_seq;
   // pragma uvmf custom sequences end
 
   // Sequencer handles for each active interface in the environment
@@ -64,6 +66,8 @@ rand soc_ifc_env_sequence_base_t soc_ifc_env_seq;
   uvm_sequencer #(soc_ifc_subenv_soc_ifc_ctrl_agent_transaction_t)  soc_ifc_subenv_soc_ifc_ctrl_agent_sequencer; 
   typedef soc_ifc_status_transaction  soc_ifc_subenv_soc_ifc_status_agent_transaction_t;
   uvm_sequencer #(soc_ifc_subenv_soc_ifc_status_agent_transaction_t)  soc_ifc_subenv_soc_ifc_status_agent_sequencer; 
+  typedef mbox_sram_transaction  soc_ifc_subenv_mbox_sram_agent_transaction_t;
+  uvm_sequencer #(soc_ifc_subenv_mbox_sram_agent_transaction_t)  soc_ifc_subenv_mbox_sram_agent_sequencer; 
 
   // Sequencer handles for each QVIP interface
   mvc_sequencer uvm_test_top_environment_soc_ifc_subenv_qvip_ahb_lite_slave_subenv_ahb_lite_slave_0_sqr;
@@ -77,6 +81,7 @@ rand soc_ifc_env_sequence_base_t soc_ifc_env_seq;
   cptra_ctrl_configuration  soc_ifc_subenv_cptra_ctrl_agent_config;
   soc_ifc_status_configuration  soc_ifc_subenv_soc_ifc_status_agent_config;
   cptra_status_configuration  soc_ifc_subenv_cptra_status_agent_config;
+  mbox_sram_configuration  soc_ifc_subenv_mbox_sram_agent_config;
 
   // pragma uvmf custom class_item_additional begin
   // pragma uvmf custom class_item_additional end
@@ -101,10 +106,13 @@ rand soc_ifc_env_sequence_base_t soc_ifc_env_seq;
       `uvm_fatal("CFG" , "uvm_config_db #( soc_ifc_status_configuration )::get cannot find resource soc_ifc_subenv_soc_ifc_status_agent_BFM" )
     if( !uvm_config_db #( cptra_status_configuration )::get( null , UVMF_CONFIGURATIONS , soc_ifc_subenv_cptra_status_agent_BFM , soc_ifc_subenv_cptra_status_agent_config ) ) 
       `uvm_fatal("CFG" , "uvm_config_db #( cptra_status_configuration )::get cannot find resource soc_ifc_subenv_cptra_status_agent_BFM" )
+    if( !uvm_config_db #( mbox_sram_configuration )::get( null , UVMF_CONFIGURATIONS , soc_ifc_subenv_mbox_sram_agent_BFM , soc_ifc_subenv_mbox_sram_agent_config ) ) 
+      `uvm_fatal("CFG" , "uvm_config_db #( mbox_sram_configuration )::get cannot find resource soc_ifc_subenv_mbox_sram_agent_BFM" )
 
     // Assign the sequencer handles from the handles within agent configurations
     soc_ifc_subenv_soc_ifc_ctrl_agent_sequencer = soc_ifc_subenv_soc_ifc_ctrl_agent_config.get_sequencer();
     soc_ifc_subenv_soc_ifc_status_agent_sequencer = soc_ifc_subenv_soc_ifc_status_agent_config.get_sequencer();
+    soc_ifc_subenv_mbox_sram_agent_sequencer = soc_ifc_subenv_mbox_sram_agent_config.get_sequencer();
 
     // Retrieve QVIP sequencer handles from the uvm_config_db
     if( !uvm_config_db #(mvc_sequencer)::get( null,UVMF_SEQUENCERS,"uvm_test_top.environment.soc_ifc_subenv.qvip_apb5_slave_subenv.apb5_master_0", uvm_test_top_environment_soc_ifc_subenv_qvip_apb5_slave_subenv_apb5_master_0_sqr) ) 
@@ -124,17 +132,20 @@ rand soc_ifc_env_sequence_base_t soc_ifc_env_seq;
 
     caliptra_top_env_seq = caliptra_top_env_sequence_base_t::type_id::create("caliptra_top_env_seq");
 
-    soc_ifc_subenv_soc_ifc_ctrl_agent_random_seq     = soc_ifc_subenv_soc_ifc_ctrl_agent_random_seq_t::type_id::create("soc_ifc_subenv_soc_ifc_ctrl_agent_random_seq");
-    soc_ifc_subenv_soc_ifc_status_agent_responder_seq  = soc_ifc_subenv_soc_ifc_status_agent_responder_seq_t::type_id::create("soc_ifc_subenv_soc_ifc_status_agent_responder_seq");
+    soc_ifc_subenv_soc_ifc_ctrl_agent_random_seq      = soc_ifc_subenv_soc_ifc_ctrl_agent_random_seq_t::type_id::create("soc_ifc_subenv_soc_ifc_ctrl_agent_random_seq");
+    soc_ifc_subenv_soc_ifc_status_agent_responder_seq = soc_ifc_subenv_soc_ifc_status_agent_responder_seq_t::type_id::create("soc_ifc_subenv_soc_ifc_status_agent_responder_seq");
+    soc_ifc_subenv_mbox_sram_agent_responder_seq      = soc_ifc_subenv_mbox_sram_agent_responder_seq_t::type_id::create("soc_ifc_subenv_mbox_sram_agent_responder_seq");
     fork
       soc_ifc_subenv_soc_ifc_ctrl_agent_config.wait_for_reset();
       soc_ifc_subenv_cptra_ctrl_agent_config.wait_for_reset();
       soc_ifc_subenv_soc_ifc_status_agent_config.wait_for_reset();
       soc_ifc_subenv_cptra_status_agent_config.wait_for_reset();
+      soc_ifc_subenv_mbox_sram_agent_config.wait_for_reset();
     join
     // Start RESPONDER sequences here
     fork
       soc_ifc_subenv_soc_ifc_status_agent_responder_seq.start(soc_ifc_subenv_soc_ifc_status_agent_sequencer);
+      soc_ifc_subenv_mbox_sram_agent_responder_seq.start(soc_ifc_subenv_mbox_sram_agent_sequencer);
     join_none
     // Start INITIATOR sequences here
     fork
@@ -151,6 +162,7 @@ caliptra_top_env_seq.start(top_configuration.vsqr);
       soc_ifc_subenv_cptra_ctrl_agent_config.wait_for_num_clocks(400);
       soc_ifc_subenv_soc_ifc_status_agent_config.wait_for_num_clocks(400);
       soc_ifc_subenv_cptra_status_agent_config.wait_for_num_clocks(400);
+      soc_ifc_subenv_mbox_sram_agent_config.wait_for_num_clocks(400);
     join
 
     // pragma uvmf custom body end
diff --git a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_cmdline_sequence.svh b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_cmdline_sequence.svh
index 2a2d567ca..7b45d983f 100644
--- a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_cmdline_sequence.svh
+++ b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_cmdline_sequence.svh
@@ -49,21 +49,21 @@ class caliptra_top_cmdline_sequence extends caliptra_top_bench_sequence_base;
     bit ready_for_rt = 0;
     while (!ready_for_fw) begin
         while(!sts_rsp_count)soc_ifc_subenv_soc_ifc_ctrl_agent_config.wait_for_num_clocks(1); // Wait for new status updates
-        `uvm_info("CALIPTRA_TOP_RAND_TEST", "Observed status response, checking contents", UVM_DEBUG)
+        `uvm_info("CALIPTRA_TOP_CMDLINE_TEST", "Observed status response, checking contents", UVM_DEBUG)
         sts_rsp_count = 0; // We only care about the latest rsp, so even if count > 1, reset back to 0
         ready_for_fw = soc_ifc_subenv_soc_ifc_status_agent_responder_seq.rsp.ready_for_fw_push;
     end
     if (!fmc_seq.randomize() with { fmc_seq.mbox_op_rand.cmd == mbox_cmd_e'(MBOX_CMD_FMC_UPDATE); })
-        `uvm_fatal("CALIPTRA_TOP_RAND_TEST", "caliptra_top_rand_sequence::body() - fmc_seq randomization failed")
+        `uvm_fatal("CALIPTRA_TOP_CMDLINE_TEST", "caliptra_top_rand_sequence::body() - fmc_seq randomization failed")
     fmc_seq.start(top_configuration.soc_ifc_subenv_config.vsqr);
     if (!rt_seq.randomize() with { rt_seq.mbox_op_rand.cmd == mbox_cmd_e'(MBOX_CMD_RT_UPDATE); })
-        `uvm_fatal("CALIPTRA_TOP_RAND_TEST", "caliptra_top_rand_sequence::body() - rt_seq randomization failed")
+        `uvm_fatal("CALIPTRA_TOP_CMDLINE_TEST", "caliptra_top_rand_sequence::body() - rt_seq randomization failed")
     rt_seq.start(top_configuration.soc_ifc_subenv_config.vsqr);
 
     // Wait for RT image to set the ready_for_rt bit
     while (!ready_for_rt) begin
         while(!sts_rsp_count)soc_ifc_subenv_soc_ifc_ctrl_agent_config.wait_for_num_clocks(1); // Wait for new status updates
-        `uvm_info("CALIPTRA_TOP_RAND_TEST", "Observed status response, checking contents", UVM_DEBUG)
+        `uvm_info("CALIPTRA_TOP_CMDLINE_TEST", "Observed status response, checking contents", UVM_DEBUG)
         sts_rsp_count = 0; // We only care about the latest rsp, so even if count > 1, reset back to 0
         ready_for_rt = soc_ifc_subenv_soc_ifc_status_agent_responder_seq.rsp.ready_for_runtime;
     end
@@ -85,6 +85,7 @@ class caliptra_top_cmdline_sequence extends caliptra_top_bench_sequence_base;
 
     soc_ifc_subenv_soc_ifc_ctrl_agent_random_seq     = soc_ifc_subenv_soc_ifc_ctrl_agent_random_seq_t::type_id::create("soc_ifc_subenv_soc_ifc_ctrl_agent_random_seq");
     soc_ifc_subenv_soc_ifc_status_agent_responder_seq  = soc_ifc_subenv_soc_ifc_status_agent_responder_seq_t::type_id::create("soc_ifc_subenv_soc_ifc_status_agent_responder_seq");
+    soc_ifc_subenv_mbox_sram_agent_responder_seq      = soc_ifc_subenv_mbox_sram_agent_responder_seq_t::type_id::create("soc_ifc_subenv_mbox_sram_agent_responder_seq");
 
     // Handle to the responder sequence for getting response transactions
     soc_ifc_env_bringup_seq.soc_ifc_status_agent_rsp_seq = soc_ifc_subenv_soc_ifc_status_agent_responder_seq;
@@ -95,6 +96,7 @@ class caliptra_top_cmdline_sequence extends caliptra_top_bench_sequence_base;
     // Start RESPONDER sequences here
     fork
         soc_ifc_subenv_soc_ifc_status_agent_responder_seq.start(soc_ifc_subenv_soc_ifc_status_agent_sequencer);
+        soc_ifc_subenv_mbox_sram_agent_responder_seq.start(soc_ifc_subenv_mbox_sram_agent_sequencer);
     join_none
 
     fork
@@ -103,7 +105,7 @@ class caliptra_top_cmdline_sequence extends caliptra_top_bench_sequence_base;
 
     // Start INITIATOR sequences here
     if(!soc_ifc_env_bringup_seq.randomize())
-        `uvm_fatal("CALIPTRA_TOP_RAND_TEST", "caliptra_top_rand_sequence::body() - soc_ifc_env_bringup_seq randomization failed")
+        `uvm_fatal("CALIPTRA_TOP_CMDLINE_TEST", "caliptra_top_rand_sequence::body() - soc_ifc_env_bringup_seq randomization failed")
     soc_ifc_env_bringup_seq.start(top_configuration.soc_ifc_subenv_config.vsqr);
 
     `uvm_info("CALIPTRA_TOP_BRINGUP", "SoC completed poweron and observed reset deassertion to system", UVM_LOW)
@@ -113,7 +115,7 @@ class caliptra_top_cmdline_sequence extends caliptra_top_bench_sequence_base;
     // Run cmdline provided env sequences
     clp = uvm_cmdline_processor::get_inst();
     if (!clp.get_arg_values("+CLP_SEQ=", seq_names))
-        `uvm_fatal("SOC_IFC_CMDLINE_TEST", "No cmdline sequence name arguments provided to cmdline test!")
+        `uvm_fatal("CALIPTRA_TOP_CMDLINE_TEST", "No cmdline sequence name arguments provided to cmdline test!")
     else
         soc_ifc_env_seq_ii = new[seq_names.size()];
 
@@ -151,6 +153,7 @@ class caliptra_top_cmdline_sequence extends caliptra_top_bench_sequence_base;
       soc_ifc_subenv_cptra_ctrl_agent_config.wait_for_num_clocks(400);
       soc_ifc_subenv_soc_ifc_status_agent_config.wait_for_num_clocks(400);
       soc_ifc_subenv_cptra_status_agent_config.wait_for_num_clocks(400);
+      soc_ifc_subenv_mbox_sram_agent_config.wait_for_num_clocks(400);
     join
 
     // pragma uvmf custom body end
diff --git a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_fw_update_sequence.svh b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_fw_update_sequence.svh
deleted file mode 100644
index 50a0dbb23..000000000
--- a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_fw_update_sequence.svh
+++ /dev/null
@@ -1,203 +0,0 @@
-//----------------------------------------------------------------------
-// Created with uvmf_gen version 2022.3
-//----------------------------------------------------------------------
-// SPDX-License-Identifier: Apache-2.0
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-// pragma uvmf custom header begin
-// pragma uvmf custom header end
-//----------------------------------------------------------------------
-//
-//----------------------------------------------------------------------
-//                                          
-// DESCRIPTION: This file contains the top level sequence used in caliptra_top_rand_test.
-//
-//----------------------------------------------------------------------
-//----------------------------------------------------------------------
-//
-
-class caliptra_top_fw_update_sequence extends caliptra_top_bench_sequence_base;
-
-  `uvm_object_utils( caliptra_top_fw_update_sequence );
-
-  typedef soc_ifc_env_bringup_sequence soc_ifc_env_bringup_sequence_t;
-  rand soc_ifc_env_bringup_sequence_t soc_ifc_env_bringup_seq;
-  // Local handle to register model for convenience
-  soc_ifc_reg_model_top reg_model;
-
-  function new(string name = "" );
-    super.new(name);
-    reg_model = top_configuration.soc_ifc_subenv_config.soc_ifc_rm;
-  endfunction
-
-  // ****************************************************************************
-  virtual task body();
-    // pragma uvmf custom body begin
-    int sts_rsp_count = 0;
-    bit mailbox_locked = 1'b1;
-    bit ready_for_fw = 1'b0;
-    bit ready_for_rt = 1'b0;
-    bit [7:0] rt_fw [32768][3:0];
-    int firmware_iccm_length;
-    int firmware_dccm_length;
-    int firmware_iccm_end;
-    int firmware_end;
-    int fw_rd_ptr;
-    uvm_status_e sts;
-    uvm_reg_data_t rdata;
-    uvm_reg_data_t wdata;
-    // Construct sequences here
-
-    caliptra_top_env_seq = caliptra_top_env_sequence_base_t::type_id::create("caliptra_top_env_seq");
-    soc_ifc_env_bringup_seq = soc_ifc_env_bringup_sequence_t::type_id::create("soc_ifc_env_bringup_seq");
-
-    soc_ifc_subenv_soc_ifc_ctrl_agent_random_seq     = soc_ifc_subenv_soc_ifc_ctrl_agent_random_seq_t::type_id::create("soc_ifc_subenv_soc_ifc_ctrl_agent_random_seq");
-    soc_ifc_subenv_soc_ifc_status_agent_responder_seq  = soc_ifc_subenv_soc_ifc_status_agent_responder_seq_t::type_id::create("soc_ifc_subenv_soc_ifc_status_agent_responder_seq");
-
-    // Handle to the responder sequence for getting response transactions
-    soc_ifc_env_bringup_seq.soc_ifc_status_agent_rsp_seq = soc_ifc_subenv_soc_ifc_status_agent_responder_seq;
-
-//    fork
-//      soc_ifc_subenv_soc_ifc_ctrl_agent_config.wait_for_reset();
-//      soc_ifc_subenv_cptra_ctrl_agent_config.wait_for_reset();
-//      soc_ifc_subenv_soc_ifc_status_agent_config.wait_for_reset();
-//      soc_ifc_subenv_cptra_status_agent_config.wait_for_reset();
-//    join
-    reg_model.reset();
-    // Start RESPONDER sequences here
-    fork
-        soc_ifc_subenv_soc_ifc_status_agent_responder_seq.start(soc_ifc_subenv_soc_ifc_status_agent_sequencer);
-    join_none
-
-    if (soc_ifc_subenv_soc_ifc_status_agent_responder_seq == null)
-    `uvm_error("FW_UPD_SEQ", "SOC_IFC ENV bringup sequence expected a handle to the soc_ifc status agent responder sequence (from bench-level sequence) but got null!")
-    fork
-      forever begin
-          @(soc_ifc_subenv_soc_ifc_status_agent_responder_seq.new_rsp) sts_rsp_count++;
-      end
-    join_none
-
-    `uvm_info("FW_UPD_SEQ", "Starting soc_ifc_env_bringup_seq", UVM_LOW)
-
-    soc_ifc_env_bringup_seq.start(top_configuration.soc_ifc_subenv_config.vsqr);
-//    caliptra_top_env_seq.start(top_configuration.vsqr);
-
-    `uvm_info("FW_UPD_SEQ", "SoC completed poweron and observed reset deassertion to system", UVM_LOW)
-
-    `uvm_info("FW_UPD_SEQ", "Waiting for ready for fw to assert", UVM_MEDIUM)
-
-    //Wait for ready for fw to be asserted
-    while(!ready_for_fw) begin
-        wait (sts_rsp_count > 0);
-        `uvm_info("FW_UPD_SEQ", "Received response from status agent", UVM_MEDIUM)
-        ready_for_fw = soc_ifc_subenv_soc_ifc_status_agent_responder_seq.rsp.ready_for_fw_push;
-        `uvm_info("FW_UPD_SEQ", $sformatf("Ready for FW bit set to: %h", ready_for_fw), UVM_MEDIUM)
-        sts_rsp_count--;
-    end
-    `uvm_info("FW_UPD_SEQ", "Ready for FW asserted, begin FW push", UVM_LOW)
-
-    //Step through the mailbox state machine to trigger interrupt
-    //Acquire the mailbox lock
-    while(mailbox_locked) begin
-      soc_ifc_subenv_soc_ifc_ctrl_agent_config.wait_for_num_clocks(50);
-      reg_model.mbox_csr_rm.mbox_lock.read(sts, rdata, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this);
-      mailbox_locked = rdata[0];
-    end
-    //Mark the mailbox locked now that we acquired it
-    mailbox_locked = 1'b1;
-    reg_model.mbox_csr_rm.mbox_cmd.write(sts, `UVM_REG_DATA_WIDTH'(32'hba5eba11), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this);
-    reg_model.mbox_csr_rm.mbox_dlen.write(sts, `UVM_REG_DATA_WIDTH'(32'hFFFF), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this);
-    reg_model.mbox_csr_rm.mbox_execute.write(sts, `UVM_REG_DATA_WIDTH'(1), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this);
-    //This only works because FW is pre-loaded. Otherwise we need to actually read the .hex and write it to mailbox
-
-    //read FW from file and write to mailbox
-    $readmemh("caliptra_rt.hex", rt_fw);
-    //Read the first dword, that's the length of ICCM location
-    firmware_iccm_length = int'(rt_fw[0][3:0]);
-    firmware_iccm_end = firmware_iccm_length + 32'd16;
-    //DCCM length is printed at end of ICCM
-    firmware_dccm_length = int'(rt_fw[firmware_iccm_end>>2][3:0]);
-    //firmware end is after ICCM, DCCM and the two lines (16 bytes) of length encodings
-    firmware_end = firmware_iccm_end + firmware_dccm_length + 32'd16;
-
-    `uvm_info("FW_UPD_SEQ", $sformatf("Firmware ICCM length: %h", int'(firmware_iccm_length)), UVM_MEDIUM);
-    `uvm_info("FW_UPD_SEQ", $sformatf("Firmware ICCM end: %h", firmware_iccm_end), UVM_MEDIUM);
-    `uvm_info("FW_UPD_SEQ", $sformatf("Firmware DCCM length: %h", int'(firmware_dccm_length)), UVM_MEDIUM);
-    `uvm_info("FW_UPD_SEQ", $sformatf("Firmware end: %h", firmware_end), UVM_MEDIUM);
-
-    //Mailbox API to send RT FW
-    //Acquire the mailbox lock
-    while(mailbox_locked) begin
-      soc_ifc_subenv_soc_ifc_ctrl_agent_config.wait_for_num_clocks(50);
-      reg_model.mbox_csr_rm.mbox_lock.read(sts, rdata, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this);
-      mailbox_locked = rdata[0];
-    end
-    //Mark the mailbox locked now that we acquired it
-    mailbox_locked = 1'b1;
-    reg_model.mbox_csr_rm.mbox_cmd.write(sts, `UVM_REG_DATA_WIDTH'(32'hbabecafe), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this);
-    reg_model.mbox_csr_rm.mbox_dlen.write(sts, `UVM_REG_DATA_WIDTH'(firmware_end), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this);
-    
-    for (fw_rd_ptr = 0; fw_rd_ptr < firmware_end; fw_rd_ptr++) begin
-      wdata = uvm_reg_data_t'({rt_fw[fw_rd_ptr][3],rt_fw[fw_rd_ptr][2],rt_fw[fw_rd_ptr][1],rt_fw[fw_rd_ptr][0]});
-      reg_model.mbox_csr_rm.mbox_datain.write(sts, wdata, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this);
-    end
-    reg_model.mbox_csr_rm.mbox_execute.write(sts, `UVM_REG_DATA_WIDTH'(1), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this);
-
-    //Wait for ready for rt to be asserted
-    while(!ready_for_rt) begin
-      wait (sts_rsp_count > 0);
-      `uvm_info("FW_UPD_SEQ", "Received response from status agent", UVM_MEDIUM)
-      ready_for_rt = soc_ifc_subenv_soc_ifc_status_agent_responder_seq.rsp.ready_for_runtime;
-      `uvm_info("FW_UPD_SEQ", $sformatf("Ready for RT bit set to: %h", ready_for_rt), UVM_MEDIUM)
-      sts_rsp_count--;
-    end   
-
-    //Sending RT firmware again to trigger the firmware update reset
-
-    //Mailbox API to send RT FW
-    //Acquire the mailbox lock
-    while(mailbox_locked) begin
-      soc_ifc_subenv_soc_ifc_ctrl_agent_config.wait_for_num_clocks(50);
-      reg_model.mbox_csr_rm.mbox_lock.read(sts, rdata, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this);
-      mailbox_locked = rdata[0];
-    end
-    //Mark the mailbox locked now that we acquired it
-    mailbox_locked = 1'b1;
-    reg_model.mbox_csr_rm.mbox_cmd.write(sts, `UVM_REG_DATA_WIDTH'(32'hbabecafe), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this);
-    reg_model.mbox_csr_rm.mbox_dlen.write(sts, `UVM_REG_DATA_WIDTH'(firmware_end), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this);
-    
-    for (fw_rd_ptr = 0; fw_rd_ptr < firmware_end; fw_rd_ptr++) begin
-      wdata = uvm_reg_data_t'({rt_fw[fw_rd_ptr][3],rt_fw[fw_rd_ptr][2],rt_fw[fw_rd_ptr][1],rt_fw[fw_rd_ptr][0]});
-      reg_model.mbox_csr_rm.mbox_datain.write(sts, wdata, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this);
-    end
-    reg_model.mbox_csr_rm.mbox_execute.write(sts, `UVM_REG_DATA_WIDTH'(1), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this);
-
-    // UVMF_CHANGE_ME : Extend the simulation XXX number of clocks after 
-    // the last sequence to allow for the last sequence item to flow 
-    // through the design.
-    fork
-      soc_ifc_subenv_soc_ifc_ctrl_agent_config.wait_for_num_clocks(80000);
-      soc_ifc_subenv_cptra_ctrl_agent_config.wait_for_num_clocks(80000);
-      soc_ifc_subenv_soc_ifc_status_agent_config.wait_for_num_clocks(80000);
-      soc_ifc_subenv_cptra_status_agent_config.wait_for_num_clocks(80000);
-    join
-
-    // pragma uvmf custom body end
-  endtask
-
-endclass
-
-// pragma uvmf custom external begin
-// pragma uvmf custom external end
-
diff --git a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_rand_sequence.svh b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_rand_sequence.svh
index 168d6393a..b09954f4e 100644
--- a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_rand_sequence.svh
+++ b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_rand_sequence.svh
@@ -49,15 +49,38 @@ class caliptra_top_rand_sequence extends caliptra_top_bench_sequence_base;
       IDX_SOC_IFC_ENV_MBOX_RAND_SMALL,
       IDX_SOC_IFC_ENV_MBOX_RAND_MEDIUM,
       IDX_SOC_IFC_ENV_MBOX_RAND_LARGE,
+      IDX_SOC_IFC_ENV_MBOX_MIN,
+      IDX_SOC_IFC_ENV_MBOX_MAX,
       IDX_SOC_IFC_ENV_MBOX_RAND_PAUSER_SMALL,
       IDX_SOC_IFC_ENV_MBOX_RAND_PAUSER_MEDIUM,
+      IDX_SOC_IFC_ENV_MBOX_RAND_PAUSER_LARGE,
+      IDX_SOC_IFC_ENV_MBOX_RAND_DELAY_SMALL,
+      IDX_SOC_IFC_ENV_MBOX_RAND_DELAY_MEDIUM,
+      IDX_SOC_IFC_ENV_MBOX_RAND_DELAY_LARGE,
+      IDX_SOC_IFC_ENV_MBOX_RAND_MEDIUM_INTERFERENCE,
+      IDX_SOC_IFC_ENV_MBOX_DLEN_INVALID,
+      IDX_SOC_IFC_ENV_MBOX_DLEN_OVERFLOW_SMALL,
+      IDX_SOC_IFC_ENV_MBOX_DLEN_OVERFLOW_MEDIUM,
+      IDX_SOC_IFC_ENV_MBOX_DLEN_OVERFLOW_LARGE,
+      IDX_SOC_IFC_ENV_MBOX_DLEN_UNDERFLOW_SMALL,
+      IDX_SOC_IFC_ENV_MBOX_DLEN_UNDERFLOW_MEDIUM,
+      IDX_SOC_IFC_ENV_MBOX_DLEN_UNDERFLOW_LARGE,
+      IDX_SOC_IFC_ENV_MBOX_REG_AXS_INV_SMALL,
+      IDX_SOC_IFC_ENV_MBOX_REG_AXS_INV_MEDIUM,
+      IDX_SOC_IFC_ENV_MBOX_REG_AXS_INV_LARGE,
+      IDX_SOC_IFC_ENV_MBOX_2BIT_FLIP_SMALL,
+      IDX_SOC_IFC_ENV_MBOX_2BIT_FLIP_MEDIUM,
+      IDX_SOC_IFC_ENV_MBOX_2BIT_FLIP_LARGE,
       IDX_SOC_IFC_ENV_MBOX_MULTI_AGENT,
       IDX_SOC_IFC_ENV_RST_WARM,
       IDX_SOC_IFC_ENV_RST_COLD,
       IDX_SOC_IFC_ENV_MBOX_RST_WARM_RAND_MEDIUM,
       IDX_SOC_IFC_ENV_MBOX_RST_COLD_RAND_MEDIUM,
       IDX_SOC_IFC_ENV_MBOX_SHA_ACCEL,
-      IDX_SOC_IFC_ENV_SHA_ACCEL
+      IDX_SOC_IFC_ENV_SHA_ACCEL,
+      IDX_SOC_IFC_ENV_FW_UPD,
+      IDX_SOC_IFC_ENV_MBOX_UC_REG_ACCESS,
+      IDX_SOC_IFC_ENV_MBOX_DIR_READ
   } rand_seq_idx;
 
   rand int iteration_count;
@@ -66,32 +89,82 @@ class caliptra_top_rand_sequence extends caliptra_top_bench_sequence_base;
   // Choose rand weights for each sequence to determine run frequency
   constraint avail_env_seqs_c {
       rand_seq_idx dist {
-          //IDX_SOC_IFC_ENV_MBOX_RAND_FW            := 0,
-          IDX_SOC_IFC_ENV_MBOX_RAND_SMALL           := 125,
-          IDX_SOC_IFC_ENV_MBOX_RAND_MEDIUM          := 100,
-          IDX_SOC_IFC_ENV_MBOX_RAND_LARGE           := 1,
-          IDX_SOC_IFC_ENV_MBOX_RAND_PAUSER_SMALL    := 125,
-          IDX_SOC_IFC_ENV_MBOX_RAND_PAUSER_MEDIUM   := 100,
-          IDX_SOC_IFC_ENV_MBOX_MULTI_AGENT          := 100,
-          IDX_SOC_IFC_ENV_RST_WARM                  := 100,
-          IDX_SOC_IFC_ENV_RST_COLD                  := 100,
-          IDX_SOC_IFC_ENV_MBOX_RST_WARM_RAND_MEDIUM := 100,
-          IDX_SOC_IFC_ENV_MBOX_RST_COLD_RAND_MEDIUM := 100,
-          IDX_SOC_IFC_ENV_MBOX_SHA_ACCEL            := 100,
-          IDX_SOC_IFC_ENV_SHA_ACCEL                 := 100
+          //IDX_SOC_IFC_ENV_MBOX_RAND_FW                := 0,
+          IDX_SOC_IFC_ENV_MBOX_RAND_SMALL               := 20,
+          IDX_SOC_IFC_ENV_MBOX_RAND_MEDIUM              := 20,
+          IDX_SOC_IFC_ENV_MBOX_RAND_LARGE               := 2,
+          IDX_SOC_IFC_ENV_MBOX_MIN                      := 100,
+          IDX_SOC_IFC_ENV_MBOX_MAX                      := 10,
+          IDX_SOC_IFC_ENV_MBOX_RAND_PAUSER_SMALL        := 100,
+          IDX_SOC_IFC_ENV_MBOX_RAND_PAUSER_MEDIUM       := 100,
+          IDX_SOC_IFC_ENV_MBOX_RAND_PAUSER_LARGE        := 10,
+          IDX_SOC_IFC_ENV_MBOX_RAND_DELAY_SMALL         := 100,
+          IDX_SOC_IFC_ENV_MBOX_RAND_DELAY_MEDIUM        := 100,
+          IDX_SOC_IFC_ENV_MBOX_RAND_DELAY_LARGE         := 5,
+          IDX_SOC_IFC_ENV_MBOX_RAND_MEDIUM_INTERFERENCE := 100,
+          IDX_SOC_IFC_ENV_MBOX_DLEN_INVALID             := 10,
+          IDX_SOC_IFC_ENV_MBOX_DLEN_OVERFLOW_SMALL      := 100,
+          IDX_SOC_IFC_ENV_MBOX_DLEN_OVERFLOW_MEDIUM     := 100,
+          IDX_SOC_IFC_ENV_MBOX_DLEN_OVERFLOW_LARGE      := 10,
+          IDX_SOC_IFC_ENV_MBOX_DLEN_UNDERFLOW_SMALL     := 100,
+          IDX_SOC_IFC_ENV_MBOX_DLEN_UNDERFLOW_MEDIUM    := 100,
+          IDX_SOC_IFC_ENV_MBOX_DLEN_UNDERFLOW_LARGE     := 10,
+          IDX_SOC_IFC_ENV_MBOX_REG_AXS_INV_SMALL        := 200,
+          IDX_SOC_IFC_ENV_MBOX_REG_AXS_INV_MEDIUM       := 200,
+          IDX_SOC_IFC_ENV_MBOX_REG_AXS_INV_LARGE        := 20,
+          IDX_SOC_IFC_ENV_MBOX_2BIT_FLIP_SMALL          := 200,
+          IDX_SOC_IFC_ENV_MBOX_2BIT_FLIP_MEDIUM         := 200,
+          IDX_SOC_IFC_ENV_MBOX_2BIT_FLIP_LARGE          := 10,
+          IDX_SOC_IFC_ENV_MBOX_MULTI_AGENT              := 200,
+          IDX_SOC_IFC_ENV_RST_WARM                      := 100,
+          IDX_SOC_IFC_ENV_RST_COLD                      := 100,
+          IDX_SOC_IFC_ENV_MBOX_RST_WARM_RAND_MEDIUM     := 100,
+          IDX_SOC_IFC_ENV_MBOX_RST_COLD_RAND_MEDIUM     := 100,
+          IDX_SOC_IFC_ENV_MBOX_SHA_ACCEL                := 100,
+          IDX_SOC_IFC_ENV_SHA_ACCEL                     := 100,
+          IDX_SOC_IFC_ENV_FW_UPD                        := 10,
+          IDX_SOC_IFC_ENV_MBOX_UC_REG_ACCESS            := 100,
+          IDX_SOC_IFC_ENV_MBOX_DIR_READ                 := 100
       };
   }
+  constraint disable_long_env_seqs_c {
+      !(rand_seq_idx inside {IDX_SOC_IFC_ENV_MBOX_RAND_LARGE,
+                             IDX_SOC_IFC_ENV_MBOX_MAX,
+                             IDX_SOC_IFC_ENV_MBOX_RAND_PAUSER_LARGE,
+                             IDX_SOC_IFC_ENV_MBOX_RAND_DELAY_MEDIUM,
+                             IDX_SOC_IFC_ENV_MBOX_RAND_DELAY_LARGE,
+                             IDX_SOC_IFC_ENV_MBOX_DLEN_INVALID,
+                             IDX_SOC_IFC_ENV_MBOX_DLEN_OVERFLOW_LARGE,
+                             IDX_SOC_IFC_ENV_MBOX_DLEN_UNDERFLOW_LARGE,
+                             IDX_SOC_IFC_ENV_MBOX_REG_AXS_INV_LARGE,
+                             IDX_SOC_IFC_ENV_MBOX_2BIT_FLIP_LARGE,
+                             IDX_SOC_IFC_ENV_MBOX_MULTI_AGENT});
+  }
   constraint iter_count_c {
       iteration_count inside {[1:10]};
   }
+  constraint iter_count_short_c {
+      iteration_count < 5;
+  }
 
   function new(string name = "" );
     super.new(name);
     reg_model = top_configuration.soc_ifc_subenv_config.soc_ifc_rm;
+    // The short test suite is used in promote pipeline to quickly check for UVM issues
+    if ($test$plusargs("CLP_SHORT_SUITE")) begin
+        this.disable_long_env_seqs_c.constraint_mode(1);
+        this.iter_count_short_c.constraint_mode(1);
+    end
+    else begin
+        this.disable_long_env_seqs_c.constraint_mode(0);
+        this.iter_count_short_c.constraint_mode(0);
+    end
+    // Users can manually override the number of random iterations to any desired value
     if ($value$plusargs("CALIPTRA_TOP_RAND_ITER=%0d", iteration_count)) begin
         `uvm_info("CALIPTRA_TOP_RAND_TEST", $sformatf("Received Command Line Iteration Count Argument of %0d", iteration_count), UVM_LOW);
         iteration_count.rand_mode(0);
         this.iter_count_c.constraint_mode(0);
+        this.iter_count_short_c.constraint_mode(0);
     end
     else begin
         if (!this.randomize(iteration_count))
@@ -135,6 +208,8 @@ class caliptra_top_rand_sequence extends caliptra_top_bench_sequence_base;
     bit pauser_valid_initialized = 1'b0;
     uvm_object obj;
     int ii;
+    int unsigned mbox_ecc_single_error_burst;
+    int unsigned mbox_ecc_single_error_delay_clocks;
 
     caliptra_top_env_seq = caliptra_top_env_sequence_base_t::type_id::create("caliptra_top_env_seq");
     soc_ifc_env_bringup_seq = soc_ifc_env_bringup_sequence_t::type_id::create("soc_ifc_env_bringup_seq");
@@ -144,6 +219,7 @@ class caliptra_top_rand_sequence extends caliptra_top_bench_sequence_base;
 
     soc_ifc_subenv_soc_ifc_ctrl_agent_random_seq     = soc_ifc_subenv_soc_ifc_ctrl_agent_random_seq_t::type_id::create("soc_ifc_subenv_soc_ifc_ctrl_agent_random_seq");
     soc_ifc_subenv_soc_ifc_status_agent_responder_seq  = soc_ifc_subenv_soc_ifc_status_agent_responder_seq_t::type_id::create("soc_ifc_subenv_soc_ifc_status_agent_responder_seq");
+    soc_ifc_subenv_mbox_sram_agent_responder_seq      = soc_ifc_subenv_mbox_sram_agent_responder_seq_t::type_id::create("soc_ifc_subenv_mbox_sram_agent_responder_seq");
 
     // Handle to the responder sequence for getting response transactions
     soc_ifc_env_bringup_seq.soc_ifc_status_agent_rsp_seq = soc_ifc_subenv_soc_ifc_status_agent_responder_seq;
@@ -161,11 +237,27 @@ class caliptra_top_rand_sequence extends caliptra_top_bench_sequence_base;
     // Start RESPONDER sequences here
     fork
         soc_ifc_subenv_soc_ifc_status_agent_responder_seq.start(soc_ifc_subenv_soc_ifc_status_agent_sequencer);
+        soc_ifc_subenv_mbox_sram_agent_responder_seq.start(soc_ifc_subenv_mbox_sram_agent_sequencer);
     join_none
 //    // Start INITIATOR sequences here
 //    fork
 //      repeat (25) soc_ifc_subenv_soc_ifc_ctrl_agent_random_seq.start(soc_ifc_subenv_soc_ifc_ctrl_agent_sequencer);
 //    join
+    fork
+        forever begin
+            if (!std::randomize(mbox_ecc_single_error_burst,mbox_ecc_single_error_delay_clocks) with {mbox_ecc_single_error_burst        dist {1 :/ 10000, [2:5] :/ 2000, [6:31] :/ 200, [32:1023] :/ 10, [1024:131071] :/ 2, [131072:524288] :/ 1};
+                                                                                                      mbox_ecc_single_error_delay_clocks dist {1 :/ 1, [2:31] :/ 3, [32:127] :/ 5, [128:1023] :/ 3, [1024:131072] :/ 1};    })
+                `uvm_fatal("CALIPTRA_TOP_RAND_TEST", "Failed to randomize mbox ecc bit flip injection parameters")
+            else
+                `uvm_info("CALIPTRA_TOP_RAND_TEST", $sformatf("Randomized mbox ecc bit flip injection parameters: burst [%0d] delay [%0d clocks]", mbox_ecc_single_error_burst, mbox_ecc_single_error_delay_clocks), UVM_FULL)
+            soc_ifc_subenv_soc_ifc_ctrl_agent_config.wait_for_num_clocks(mbox_ecc_single_error_delay_clocks);
+            `uvm_info("CALIPTRA_TOP_RAND_TEST", $sformatf("Injecting mbox ecc error with burst [%0d]", mbox_ecc_single_error_burst), UVM_DEBUG)
+            repeat(mbox_ecc_single_error_burst) begin
+                soc_ifc_subenv_mbox_sram_agent_config.inject_ecc_error |= 2'b01;
+                @soc_ifc_subenv_mbox_sram_agent_responder_seq.new_rsp;
+            end
+        end
+    join_none
     fork
         forever @(soc_ifc_subenv_soc_ifc_status_agent_responder_seq.new_rsp) sts_rsp_count++;
     join_none
@@ -193,6 +285,10 @@ class caliptra_top_rand_sequence extends caliptra_top_bench_sequence_base;
                 obj = soc_ifc_env_mbox_rand_medium_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
             IDX_SOC_IFC_ENV_MBOX_RAND_LARGE:
                 obj = soc_ifc_env_mbox_rand_large_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
+            IDX_SOC_IFC_ENV_MBOX_MIN:
+                obj = soc_ifc_env_mbox_min_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
+            IDX_SOC_IFC_ENV_MBOX_MAX:
+                obj = soc_ifc_env_mbox_max_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
             IDX_SOC_IFC_ENV_MBOX_RAND_PAUSER_SMALL: begin
                 if (!pauser_valid_initialized) begin
                     if(!soc_ifc_env_pauser_init_seq.randomize())
@@ -215,6 +311,54 @@ class caliptra_top_rand_sequence extends caliptra_top_bench_sequence_base;
                 end
                 obj = soc_ifc_env_mbox_rand_pauser_medium_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
             end
+            IDX_SOC_IFC_ENV_MBOX_RAND_PAUSER_LARGE: begin
+                if (!pauser_valid_initialized) begin
+                    if(!soc_ifc_env_pauser_init_seq.randomize())
+                        `uvm_fatal("CALIPTRA_TOP_RAND_TEST", "caliptra_top_rand_sequence::body() - soc_ifc_env_pauser_init_seq randomization failed")
+                    soc_ifc_env_pauser_init_seq.start(top_configuration.soc_ifc_subenv_config.vsqr);
+
+                    `uvm_info("CALIPTRA_TOP_RAND_TEST", "SoC completed PAUSER VALID initialization", UVM_LOW)
+                    pauser_valid_initialized = 1'b1;
+                end
+                obj = soc_ifc_env_mbox_rand_pauser_large_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
+            end
+            IDX_SOC_IFC_ENV_MBOX_RAND_DELAY_SMALL: begin
+                obj = soc_ifc_env_mbox_rand_delay_small_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
+            end
+            IDX_SOC_IFC_ENV_MBOX_RAND_DELAY_MEDIUM: begin
+                obj = soc_ifc_env_mbox_rand_delay_medium_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
+            end
+            IDX_SOC_IFC_ENV_MBOX_RAND_DELAY_LARGE: begin
+                obj = soc_ifc_env_mbox_rand_delay_large_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
+            end
+            IDX_SOC_IFC_ENV_MBOX_RAND_MEDIUM_INTERFERENCE:
+                obj = soc_ifc_env_mbox_rand_medium_interference_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
+            IDX_SOC_IFC_ENV_MBOX_DLEN_INVALID:
+                obj = soc_ifc_env_mbox_dlen_invalid_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
+            IDX_SOC_IFC_ENV_MBOX_DLEN_OVERFLOW_SMALL:
+                obj = soc_ifc_env_mbox_dlen_overflow_small_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
+            IDX_SOC_IFC_ENV_MBOX_DLEN_OVERFLOW_MEDIUM:
+                obj = soc_ifc_env_mbox_dlen_overflow_medium_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
+            IDX_SOC_IFC_ENV_MBOX_DLEN_OVERFLOW_LARGE:
+                obj = soc_ifc_env_mbox_dlen_overflow_large_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
+            IDX_SOC_IFC_ENV_MBOX_DLEN_UNDERFLOW_SMALL:
+                obj = soc_ifc_env_mbox_dlen_underflow_small_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
+            IDX_SOC_IFC_ENV_MBOX_DLEN_UNDERFLOW_MEDIUM:
+                obj = soc_ifc_env_mbox_dlen_underflow_medium_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
+            IDX_SOC_IFC_ENV_MBOX_DLEN_UNDERFLOW_LARGE:
+                obj = soc_ifc_env_mbox_dlen_underflow_large_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
+            IDX_SOC_IFC_ENV_MBOX_REG_AXS_INV_SMALL:
+                obj = soc_ifc_env_mbox_reg_axs_invalid_small_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
+            IDX_SOC_IFC_ENV_MBOX_REG_AXS_INV_MEDIUM:
+                obj = soc_ifc_env_mbox_reg_axs_invalid_medium_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
+            IDX_SOC_IFC_ENV_MBOX_REG_AXS_INV_LARGE:
+                obj = soc_ifc_env_mbox_reg_axs_invalid_large_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
+            IDX_SOC_IFC_ENV_MBOX_2BIT_FLIP_SMALL:
+                obj = soc_ifc_env_mbox_sram_double_bit_flip_small_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
+            IDX_SOC_IFC_ENV_MBOX_2BIT_FLIP_MEDIUM:
+                obj = soc_ifc_env_mbox_sram_double_bit_flip_medium_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
+            IDX_SOC_IFC_ENV_MBOX_2BIT_FLIP_LARGE:
+                obj = soc_ifc_env_mbox_sram_double_bit_flip_large_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
             IDX_SOC_IFC_ENV_MBOX_MULTI_AGENT:
                 // TODO PAUSER init first?
                 obj = soc_ifc_env_mbox_rand_multi_agent_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
@@ -230,6 +374,12 @@ class caliptra_top_rand_sequence extends caliptra_top_bench_sequence_base;
                 obj = soc_ifc_env_mbox_sha_accel_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
             IDX_SOC_IFC_ENV_SHA_ACCEL:
                 obj = soc_ifc_env_sha_accel_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
+            IDX_SOC_IFC_ENV_FW_UPD:
+                obj = soc_ifc_env_mbox_fw_upd_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
+            IDX_SOC_IFC_ENV_MBOX_UC_REG_ACCESS:
+                obj = soc_ifc_env_mbox_uc_reg_access_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
+            IDX_SOC_IFC_ENV_MBOX_DIR_READ:
+                obj = soc_ifc_env_mbox_dir_read_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
             default:
                 `uvm_error("CALIPTRA_TOP_RAND_TEST", $sformatf("rand_seq_idx randomized to illegal value: %p", rand_seq_idx))
         endcase
@@ -267,10 +417,11 @@ class caliptra_top_rand_sequence extends caliptra_top_bench_sequence_base;
     // the last sequence to allow for the last sequence item to flow 
     // through the design.
     fork
-      soc_ifc_subenv_soc_ifc_ctrl_agent_config.wait_for_num_clocks(400);
-      soc_ifc_subenv_cptra_ctrl_agent_config.wait_for_num_clocks(400);
-      soc_ifc_subenv_soc_ifc_status_agent_config.wait_for_num_clocks(400);
-      soc_ifc_subenv_cptra_status_agent_config.wait_for_num_clocks(400);
+      soc_ifc_subenv_soc_ifc_ctrl_agent_config.wait_for_num_clocks(4000);
+      soc_ifc_subenv_cptra_ctrl_agent_config.wait_for_num_clocks(4000);
+      soc_ifc_subenv_soc_ifc_status_agent_config.wait_for_num_clocks(4000);
+      soc_ifc_subenv_cptra_status_agent_config.wait_for_num_clocks(4000);
+      soc_ifc_subenv_mbox_sram_agent_config.wait_for_num_clocks(4000);
     join
 
     // pragma uvmf custom body end
diff --git a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_rom_sequence.svh b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_rom_sequence.svh
new file mode 100644
index 000000000..9182b23a6
--- /dev/null
+++ b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_rom_sequence.svh
@@ -0,0 +1,135 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//----------------------------------------------------------------------
+//
+//----------------------------------------------------------------------
+//                                          
+// DESCRIPTION: This file contains the top level sequence used in caliptra_top_rom_test.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+class caliptra_top_rom_sequence extends caliptra_top_bench_sequence_base;
+
+  `uvm_object_utils( caliptra_top_rom_sequence );
+
+  rand soc_ifc_env_rom_bringup_sequence_t soc_ifc_env_bringup_seq;
+  rand soc_ifc_env_trng_write_data_sequence_t soc_ifc_env_trng_write_data_seq;
+  rand soc_ifc_env_mbox_rom_fw_sequence_t soc_ifc_env_mbox_rom_seq;
+  rand soc_ifc_env_sequence_base_t soc_ifc_env_seq_ii[];
+  // Local handle to register model for convenience
+  soc_ifc_reg_model_top reg_model;
+
+  int sts_rsp_count = 0;
+
+  function new(string name = "" );
+    super.new(name);
+    reg_model = top_configuration.soc_ifc_subenv_config.soc_ifc_rm;
+  endfunction
+
+  // ****************************************************************************
+  virtual task run_firmware_init(soc_ifc_env_mbox_rom_fw_sequence_t rom_seq);
+    bit ready_for_fw = 0;
+    bit ready_for_rt = 0;
+    while (!ready_for_fw) begin
+        while(!sts_rsp_count)soc_ifc_subenv_soc_ifc_ctrl_agent_config.wait_for_num_clocks(1); // Wait for new status updates
+        `uvm_info("CALIPTRA_TOP_ROM_TEST", "Observed status response, checking contents", UVM_DEBUG)
+        sts_rsp_count = 0; // We only care about the latest rsp, so even if count > 1, reset back to 0
+        ready_for_fw = soc_ifc_subenv_soc_ifc_status_agent_responder_seq.rsp.ready_for_fw_push;
+    end
+    if (!rom_seq.randomize())
+        `uvm_fatal("CALIPTRA_TOP_ROM_TEST", "caliptra_top_rom_sequence::body() - rom_seq randomization failed")
+    rom_seq.start(top_configuration.soc_ifc_subenv_config.vsqr);
+
+  endtask
+
+  // ****************************************************************************
+  virtual task body();
+    // pragma uvmf custom body begin
+    // Construct sequences here
+    uvm_object obj;
+
+    caliptra_top_env_seq = caliptra_top_env_sequence_base_t::type_id::create("caliptra_top_env_seq");
+    soc_ifc_env_bringup_seq = soc_ifc_env_rom_bringup_sequence_t::type_id::create("soc_ifc_env_bringup_seq");
+    soc_ifc_env_mbox_rom_seq = soc_ifc_env_mbox_rom_fw_sequence_t::type_id::create("soc_ifc_env_mbox_rom_seq");
+
+    soc_ifc_subenv_soc_ifc_ctrl_agent_random_seq     = soc_ifc_subenv_soc_ifc_ctrl_agent_random_seq_t::type_id::create("soc_ifc_subenv_soc_ifc_ctrl_agent_random_seq");
+    soc_ifc_subenv_soc_ifc_status_agent_responder_seq  = soc_ifc_subenv_soc_ifc_status_agent_responder_seq_t::type_id::create("soc_ifc_subenv_soc_ifc_status_agent_responder_seq");
+    soc_ifc_subenv_mbox_sram_agent_responder_seq      = soc_ifc_subenv_mbox_sram_agent_responder_seq_t::type_id::create("soc_ifc_subenv_mbox_sram_agent_responder_seq");
+
+    // Handle to the responder sequence for getting response transactions
+    soc_ifc_env_bringup_seq.soc_ifc_status_agent_rsp_seq = soc_ifc_subenv_soc_ifc_status_agent_responder_seq;
+    soc_ifc_env_mbox_rom_seq.soc_ifc_status_agent_rsp_seq = soc_ifc_subenv_soc_ifc_status_agent_responder_seq;
+
+    reg_model.reset();
+    // Start RESPONDER sequences here
+    fork
+        soc_ifc_subenv_soc_ifc_status_agent_responder_seq.start(soc_ifc_subenv_soc_ifc_status_agent_sequencer);
+        soc_ifc_subenv_mbox_sram_agent_responder_seq.start(soc_ifc_subenv_mbox_sram_agent_sequencer);
+    join_none
+
+    fork
+        forever @(soc_ifc_subenv_soc_ifc_status_agent_responder_seq.new_rsp) sts_rsp_count++;
+    join_none
+
+    // Start INITIATOR sequences here
+    if(!soc_ifc_env_bringup_seq.randomize())
+        `uvm_fatal("CALIPTRA_TOP_ROM_TEST", "caliptra_top_rom_sequence::body() - soc_ifc_env_bringup_seq randomization failed")
+    soc_ifc_env_bringup_seq.start(top_configuration.soc_ifc_subenv_config.vsqr);
+
+    `uvm_info("CALIPTRA_TOP_BRINGUP", "SoC completed poweron and observed reset deassertion to system", UVM_LOW)
+
+`ifndef CALIPTRA_INTERNAL_TRNG
+    `uvm_info("CALIPTRA_TOP_ROM_TEST", "Initiating TRNG responder sequence in an infinite loop to handle ROM TRNG requests", UVM_LOW)
+    fork
+        forever begin
+            soc_ifc_env_trng_write_data_seq = soc_ifc_env_trng_write_data_sequence_t::type_id::create("soc_ifc_env_trng_write_data_seq");
+            soc_ifc_env_trng_write_data_seq.soc_ifc_status_agent_rsp_seq = soc_ifc_subenv_soc_ifc_status_agent_responder_seq;
+            if (!soc_ifc_env_trng_write_data_seq.randomize())
+              `uvm_fatal("CALIPTRA_TOP_ROM_TEST", $sformatf("caliptra_top_rom_sequence::body() - %s randomization failed", soc_ifc_env_trng_write_data_seq.get_type_name()));
+            soc_ifc_env_trng_write_data_seq.start(top_configuration.soc_ifc_subenv_config.vsqr);
+        end
+    join_none
+`else
+    `uvm_info("CALIPTRA_TOP_ROM_TEST", "Not initiating TRNG responder sequence to handle ROM TRNG requests because INTERNAL TRNG is enabled", UVM_LOW)
+`endif
+
+    run_firmware_init(soc_ifc_env_mbox_rom_seq);
+
+    // After firmware init, wait for generic_output_wires write to 0xFF
+    while(soc_ifc_subenv_soc_ifc_status_agent_responder_seq.rsp.generic_output_val[31:0] != 32'hff) begin
+        sts_rsp_count = 0;
+        while(!sts_rsp_count) soc_ifc_subenv_soc_ifc_ctrl_agent_config.wait_for_num_clocks(1); // Wait for new status updates
+    end
+
+    // UVMF_CHANGE_ME : Extend the simulation XXX number of clocks after 
+    // the last sequence to allow for the last sequence item to flow 
+    // through the design.
+    fork
+      soc_ifc_subenv_soc_ifc_ctrl_agent_config.wait_for_num_clocks(400);
+      soc_ifc_subenv_cptra_ctrl_agent_config.wait_for_num_clocks(400);
+      soc_ifc_subenv_soc_ifc_status_agent_config.wait_for_num_clocks(400);
+      soc_ifc_subenv_cptra_status_agent_config.wait_for_num_clocks(400);
+      soc_ifc_subenv_mbox_sram_agent_config.wait_for_num_clocks(400);
+    join
+
+    // pragma uvmf custom body end
+  endtask
+
+endclass
diff --git a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_reg_access_sequence.svh b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_wdt_independent_sequence.svh
similarity index 58%
rename from src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_reg_access_sequence.svh
rename to src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_wdt_independent_sequence.svh
index 44cfc04e9..426616a3a 100644
--- a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_reg_access_sequence.svh
+++ b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_wdt_independent_sequence.svh
@@ -21,137 +21,133 @@
 //
 //----------------------------------------------------------------------
 //                                          
-// DESCRIPTION: This file contains the top level sequence used in CALIPTRA_TOP_REG_ACCESS_TEST.
+// DESCRIPTION: This file contains the top level sequence used in caliptra_top_wdt_test.
 //
 //----------------------------------------------------------------------
 //----------------------------------------------------------------------
 //
 
-class caliptra_top_reg_access_sequence extends caliptra_top_bench_sequence_base;
+class caliptra_top_wdt_independent_sequence extends caliptra_top_bench_sequence_base;
 
-  `uvm_object_utils( caliptra_top_reg_access_sequence );
+  `uvm_object_utils( caliptra_top_wdt_independent_sequence );
 
   rand soc_ifc_env_bringup_sequence_t soc_ifc_env_bringup_seq;
   rand soc_ifc_env_pauser_init_sequence_t soc_ifc_env_pauser_init_seq;
   rand soc_ifc_env_mbox_real_fw_sequence_t soc_ifc_env_mbox_fmc_seq;
   rand soc_ifc_env_mbox_real_fw_sequence_t soc_ifc_env_mbox_rt_seq;
-  rand soc_ifc_env_sequence_base_t soc_ifc_env_seq_ii[];
+  rand soc_ifc_env_reset_warm_sequence_t soc_ifc_env_reset_warm_seq;
+  rand soc_ifc_env_reset_cold_sequence_t soc_ifc_env_reset_cold_seq;
+  rand soc_ifc_env_cptra_wdt_independent_sequence_t soc_ifc_env_wdt_indep_seq;
+  rand soc_ifc_env_cptra_wdt_cascade_sequence_t soc_ifc_env_wdt_cascade_seq;
   // Local handle to register model for convenience
   soc_ifc_reg_model_top reg_model;
 
-  // TODO: To add new sequences to the randomized portion of this test:
-  //        - Update rand_seq_idx enum definition
-  //        - Update avail_env_seqs_c definition
-  //        - Add instantiation logic in the RAND_LOOP below
 
   rand int iteration_count;
+  int sts_rsp_count = 0;
+  int rsp_count = 0;
 
-  constraint iter_count_c {
-      iteration_count inside {[1:10]};
-  }
 
   function new(string name = "" );
     super.new(name);
     reg_model = top_configuration.soc_ifc_subenv_config.soc_ifc_rm;
-    if ($value$plusargs("CALIPTRA_TOP_RAND_ITER=%d", iteration_count)) begin
-        `uvm_info("CALIPTRA_TOP_REG_ACCESS_TEST", $sformatf("Received Command Line Iteration Count Argument of %d", iteration_count), UVM_LOW);
-        iteration_count.rand_mode(0);
-        this.iter_count_c.constraint_mode(0);
+  endfunction
+
+  // ****************************************************************************
+  virtual task run_firmware_init(soc_ifc_env_mbox_real_fw_sequence_t fmc_seq, soc_ifc_env_mbox_real_fw_sequence_t rt_seq);
+    bit ready_for_fw = 0;
+    bit ready_for_rt = 0;
+    while (!ready_for_fw) begin
+        while(!sts_rsp_count)soc_ifc_subenv_soc_ifc_ctrl_agent_config.wait_for_num_clocks(1); // Wait for new status updates
+        `uvm_info("CALIPTRA_TOP_WDT_INDEP_TEST", "Observed status response, checking contents", UVM_DEBUG)
+        sts_rsp_count = 0; // We only care about the latest rsp, so even if count > 1, reset back to 0
+        ready_for_fw = soc_ifc_subenv_soc_ifc_status_agent_responder_seq.rsp.ready_for_fw_push;
     end
-    else begin
-        if (!this.randomize(iteration_count))
-            `uvm_fatal("CALIPTRA_TOP_REG_ACCESS_TEST", "Failed to randomize iteration_count after receiving no command line override")
-        else
-            `uvm_info("CALIPTRA_TOP_REG_ACCESS_TEST", $sformatf("Did not receive Command Line Iteration Count Argument with +CALIPTRA_TOP_RAND_ITER, defaulting to %d", iteration_count), UVM_LOW);
+    if (!fmc_seq.randomize() with { fmc_seq.mbox_op_rand.cmd == mbox_cmd_e'(MBOX_CMD_FMC_UPDATE); })
+        `uvm_fatal("CALIPTRA_TOP_WDT_INDEP_TEST", "caliptra_top_wdt_independent_sequence::body() - fmc_seq randomization failed")
+    fmc_seq.start(top_configuration.soc_ifc_subenv_config.vsqr);
+    if (!rt_seq.randomize() with { rt_seq.mbox_op_rand.cmd == mbox_cmd_e'(MBOX_CMD_RT_UPDATE); })
+        `uvm_fatal("CALIPTRA_TOP_WDT_INDEP_TEST", "caliptra_top_wdt_independent_sequence::body() - rt_seq randomization failed")
+    rt_seq.start(top_configuration.soc_ifc_subenv_config.vsqr);
+
+    // Wait for RT image to set the ready_for_rt bit
+    while (!ready_for_rt) begin
+        while(!sts_rsp_count)soc_ifc_subenv_soc_ifc_ctrl_agent_config.wait_for_num_clocks(1); // Wait for new status updates
+        `uvm_info("CALIPTRA_TOP_WDT_INDEP_TEST", "Observed status response, checking contents", UVM_DEBUG)
+        sts_rsp_count = 0; // We only care about the latest rsp, so even if count > 1, reset back to 0
+        ready_for_rt = soc_ifc_subenv_soc_ifc_status_agent_responder_seq.rsp.ready_for_runtime;
     end
-    soc_ifc_env_seq_ii = new[iteration_count];
-  endfunction
+  endtask
 
   // ****************************************************************************
   virtual task body();
     // pragma uvmf custom body begin
     // Construct sequences here
-    int sts_rsp_count = 0;
-    bit ready_for_fw = 0;
-    bit ready_for_rt = 0;
     bit pauser_valid_initialized = 1'b0;
     uvm_object obj;
     int ii;
+    bit nmi_intr;
+    bit hw_error_fatal;
+    uvm_status_e reg_sts;
+    uvm_reg_data_t wdt_status_data;
 
     caliptra_top_env_seq = caliptra_top_env_sequence_base_t::type_id::create("caliptra_top_env_seq");
     soc_ifc_env_bringup_seq = soc_ifc_env_bringup_sequence_t::type_id::create("soc_ifc_env_bringup_seq");
     soc_ifc_env_pauser_init_seq = soc_ifc_env_pauser_init_sequence_t::type_id::create("soc_ifc_env_pauser_init_seq");
     soc_ifc_env_mbox_fmc_seq = soc_ifc_env_mbox_real_fw_sequence_t::type_id::create("soc_ifc_env_mbox_fmc_seq");
     soc_ifc_env_mbox_rt_seq = soc_ifc_env_mbox_real_fw_sequence_t::type_id::create("soc_ifc_env_mbox_rt_seq");
-
+    soc_ifc_env_reset_warm_seq = soc_ifc_env_reset_warm_sequence_t::type_id::create("soc_ifc_env_reset_warm_seq");
+    soc_ifc_env_reset_cold_seq = soc_ifc_env_reset_cold_sequence_t::type_id::create("soc_ifc_env_reset_cold_seq");
+    soc_ifc_env_wdt_indep_seq = soc_ifc_env_cptra_wdt_independent_sequence_t::type_id::create("soc_ifc_env_wdt_indep_seq");
+    soc_ifc_env_wdt_cascade_seq = soc_ifc_env_cptra_wdt_cascade_sequence_t::type_id::create("soc_ifc_env_wdt_cascade_seq");
+    
     soc_ifc_subenv_soc_ifc_ctrl_agent_random_seq     = soc_ifc_subenv_soc_ifc_ctrl_agent_random_seq_t::type_id::create("soc_ifc_subenv_soc_ifc_ctrl_agent_random_seq");
     soc_ifc_subenv_soc_ifc_status_agent_responder_seq  = soc_ifc_subenv_soc_ifc_status_agent_responder_seq_t::type_id::create("soc_ifc_subenv_soc_ifc_status_agent_responder_seq");
+    soc_ifc_subenv_mbox_sram_agent_responder_seq      = soc_ifc_subenv_mbox_sram_agent_responder_seq_t::type_id::create("soc_ifc_subenv_mbox_sram_agent_responder_seq");
 
     // Handle to the responder sequence for getting response transactions
     soc_ifc_env_bringup_seq.soc_ifc_status_agent_rsp_seq = soc_ifc_subenv_soc_ifc_status_agent_responder_seq;
     soc_ifc_env_pauser_init_seq.soc_ifc_status_agent_rsp_seq = soc_ifc_subenv_soc_ifc_status_agent_responder_seq;
     soc_ifc_env_mbox_fmc_seq.soc_ifc_status_agent_rsp_seq = soc_ifc_subenv_soc_ifc_status_agent_responder_seq;
     soc_ifc_env_mbox_rt_seq.soc_ifc_status_agent_rsp_seq = soc_ifc_subenv_soc_ifc_status_agent_responder_seq;
+    soc_ifc_env_reset_warm_seq.soc_ifc_status_agent_rsp_seq = soc_ifc_subenv_soc_ifc_status_agent_responder_seq;
+    soc_ifc_env_reset_cold_seq.soc_ifc_status_agent_rsp_seq = soc_ifc_subenv_soc_ifc_status_agent_responder_seq;
+    soc_ifc_env_wdt_indep_seq.soc_ifc_status_agent_rsp_seq = soc_ifc_subenv_soc_ifc_status_agent_responder_seq;
+    soc_ifc_env_wdt_cascade_seq.soc_ifc_status_agent_rsp_seq = soc_ifc_subenv_soc_ifc_status_agent_responder_seq;
 
     reg_model.reset();
     // Start RESPONDER sequences here
     fork
         soc_ifc_subenv_soc_ifc_status_agent_responder_seq.start(soc_ifc_subenv_soc_ifc_status_agent_sequencer);
+        soc_ifc_subenv_mbox_sram_agent_responder_seq.start(soc_ifc_subenv_mbox_sram_agent_sequencer);
     join_none
-//    // Start INITIATOR sequences here
-//    fork
-//      repeat (25) soc_ifc_subenv_soc_ifc_ctrl_agent_random_seq.start(soc_ifc_subenv_soc_ifc_ctrl_agent_sequencer);
-//    join
+
     fork
-        forever @(soc_ifc_subenv_soc_ifc_status_agent_responder_seq.new_rsp) sts_rsp_count++;
+        forever @(soc_ifc_subenv_soc_ifc_status_agent_responder_seq.new_rsp) begin 
+          sts_rsp_count++;
+          rsp_count++;
+        end
     join_none
 
     if(!soc_ifc_env_bringup_seq.randomize())
-        `uvm_fatal("CALIPTRA_TOP_REG_ACCESS_TEST", "caliptra_top_reg_access_sequence::body() - soc_ifc_env_bringup_seq randomization failed")
+        `uvm_fatal("CALIPTRA_TOP_WDT_INDEP_TEST", "caliptra_top_wdt_independent_sequence::body() - soc_ifc_env_bringup_seq randomization failed")
     soc_ifc_env_bringup_seq.start(top_configuration.soc_ifc_subenv_config.vsqr);
 
     `uvm_info("CALIPTRA_TOP_BRINGUP", "SoC completed poweron and observed reset deassertion to system", UVM_LOW)
-    
-    while (!ready_for_fw) begin
-        while(!sts_rsp_count)soc_ifc_subenv_soc_ifc_ctrl_agent_config.wait_for_num_clocks(1); // Wait for new status updates
-        `uvm_info("CALIPTRA_TOP_REG_ACCESS_TEST", "Observed status response, checking contents", UVM_DEBUG)
-        sts_rsp_count = 0; // We only care about the latest rsp, so even if count > 1, reset back to 0
-        ready_for_fw = soc_ifc_subenv_soc_ifc_status_agent_responder_seq.rsp.ready_for_fw_push;
-    end
-    if (!soc_ifc_env_mbox_fmc_seq.randomize() with { soc_ifc_env_mbox_fmc_seq.mbox_op_rand.cmd == 32'hba5eba11; })
-        `uvm_fatal("CALIPTRA_TOP_REG_ACCESS_TEST", "caliptra_top_reg_access_sequence::body() - soc_ifc_env_mbox_fmc_seq randomization failed")
-    soc_ifc_env_mbox_fmc_seq.start(top_configuration.soc_ifc_subenv_config.vsqr);
-    if (!soc_ifc_env_mbox_rt_seq.randomize() with { soc_ifc_env_mbox_rt_seq.mbox_op_rand.cmd == 32'hbabecafe; })
-        `uvm_fatal("CALIPTRA_TOP_REG_ACCESS_TEST", "caliptra_top_reg_access_sequence::body() - soc_ifc_env_mbox_rt_seq randomization failed")
-    soc_ifc_env_mbox_rt_seq.start(top_configuration.soc_ifc_subenv_config.vsqr);
 
-    // Wait for RT image to set the ready_for_rt bit
-    while (!ready_for_rt) begin
-        while(!sts_rsp_count)soc_ifc_subenv_soc_ifc_ctrl_agent_config.wait_for_num_clocks(1); // Wait for new status updates
-        `uvm_info("CALIPTRA_TOP_REG_ACCESS_TEST", "Observed status response, checking contents", UVM_DEBUG)
-        sts_rsp_count = 0; // We only care about the latest rsp, so even if count > 1, reset back to 0
-        ready_for_rt = soc_ifc_subenv_soc_ifc_status_agent_responder_seq.rsp.ready_for_runtime;
-    end
-
-    // In this loop, randomly select a sequence to run (from the list of available
-    // ENV level sequences), randomize the sequence object, and kick it off
-    for (ii = 0; ii < iteration_count; ii++) begin: RAND_LOOP
-        obj = soc_ifc_env_mbox_uc_reg_access_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%d]",ii));
-
-        // Randomize and run the sequence
-        if(!$cast(soc_ifc_env_seq_ii[ii],obj)) `uvm_fatal("CALIPTRA_TOP_REG_ACCESS_TEST", "caliptra_top_reg_access_sequence::body() - <seq_type>.create_object() failed")
-        `uvm_info("CALIPTRA_TOP_REG_ACCESS_TEST", $sformatf("rand_seq randomized to: %s", soc_ifc_env_seq_ii[ii].get_type_name()), UVM_LOW)
-        if(!soc_ifc_env_seq_ii[ii].randomize())
-            `uvm_fatal("CALIPTRA_TOP_REG_ACCESS_TEST", $sformatf("caliptra_top_reg_access_sequence::body() - %s randomization failed", soc_ifc_env_seq_ii[ii].get_type_name()));
-        soc_ifc_env_seq_ii[ii].soc_ifc_status_agent_rsp_seq = soc_ifc_subenv_soc_ifc_status_agent_responder_seq;
-        soc_ifc_env_seq_ii[ii].start(top_configuration.soc_ifc_subenv_config.vsqr);
-    end
+    run_firmware_init(soc_ifc_env_mbox_fmc_seq,soc_ifc_env_mbox_rt_seq);
 
+    soc_ifc_env_wdt_indep_seq.start(top_configuration.soc_ifc_subenv_config.vsqr);
+    
+    // UVMF_CHANGE_ME : Extend the simulation XXX number of clocks after 
+    // the last sequence to allow for the last sequence item to flow 
+    // through the design.
     fork
-      soc_ifc_subenv_soc_ifc_ctrl_agent_config.wait_for_num_clocks(400);
-      soc_ifc_subenv_cptra_ctrl_agent_config.wait_for_num_clocks(400);
-      soc_ifc_subenv_soc_ifc_status_agent_config.wait_for_num_clocks(400);
-      soc_ifc_subenv_cptra_status_agent_config.wait_for_num_clocks(400);
+      soc_ifc_subenv_soc_ifc_ctrl_agent_config.wait_for_num_clocks(10000);
+      soc_ifc_subenv_cptra_ctrl_agent_config.wait_for_num_clocks(10000);
+      soc_ifc_subenv_soc_ifc_status_agent_config.wait_for_num_clocks(10000);
+      soc_ifc_subenv_cptra_status_agent_config.wait_for_num_clocks(10000);
+      soc_ifc_subenv_mbox_sram_agent_config.wait_for_num_clocks(10000);
     join
 
     // pragma uvmf custom body end
diff --git a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_wdt_sequence.svh b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_wdt_sequence.svh
new file mode 100644
index 000000000..a06e803c8
--- /dev/null
+++ b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_wdt_sequence.svh
@@ -0,0 +1,184 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//
+//----------------------------------------------------------------------
+//                                          
+// DESCRIPTION: This file contains the top level sequence used in caliptra_top_wdt_test.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+class caliptra_top_wdt_sequence extends caliptra_top_bench_sequence_base;
+
+  `uvm_object_utils( caliptra_top_wdt_sequence );
+
+  rand soc_ifc_env_bringup_sequence_t soc_ifc_env_bringup_seq;
+  rand soc_ifc_env_pauser_init_sequence_t soc_ifc_env_pauser_init_seq;
+  rand soc_ifc_env_mbox_real_fw_sequence_t soc_ifc_env_mbox_fmc_seq;
+  rand soc_ifc_env_mbox_real_fw_sequence_t soc_ifc_env_mbox_rt_seq;
+  rand soc_ifc_env_reset_warm_sequence_t soc_ifc_env_reset_warm_seq;
+  rand soc_ifc_env_reset_cold_sequence_t soc_ifc_env_reset_cold_seq;
+  rand soc_ifc_env_cptra_wdt_independent_sequence_t soc_ifc_env_wdt_indep_seq;
+  rand soc_ifc_env_cptra_wdt_cascade_sequence_t soc_ifc_env_wdt_cascade_seq;
+  // Local handle to register model for convenience
+  soc_ifc_reg_model_top reg_model;
+
+
+  rand int iteration_count;
+  int sts_rsp_count = 0;
+  int rsp_count = 0;
+
+
+  function new(string name = "" );
+    super.new(name);
+    reg_model = top_configuration.soc_ifc_subenv_config.soc_ifc_rm;
+  endfunction
+
+  // ****************************************************************************
+  virtual task run_firmware_init(soc_ifc_env_mbox_real_fw_sequence_t fmc_seq, soc_ifc_env_mbox_real_fw_sequence_t rt_seq);
+    bit ready_for_fw = 0;
+    bit ready_for_rt = 0;
+    while (!ready_for_fw) begin
+        while(!sts_rsp_count)soc_ifc_subenv_soc_ifc_ctrl_agent_config.wait_for_num_clocks(1); // Wait for new status updates
+        `uvm_info("CALIPTRA_TOP_WDT_TEST", "Observed status response, checking contents", UVM_DEBUG)
+        sts_rsp_count = 0; // We only care about the latest rsp, so even if count > 1, reset back to 0
+        ready_for_fw = soc_ifc_subenv_soc_ifc_status_agent_responder_seq.rsp.ready_for_fw_push;
+    end
+    if (!fmc_seq.randomize() with { fmc_seq.mbox_op_rand.cmd == mbox_cmd_e'(MBOX_CMD_FMC_UPDATE); })
+        `uvm_fatal("CALIPTRA_TOP_WDT_TEST", "caliptra_top_wdt_sequence::body() - fmc_seq randomization failed")
+    fmc_seq.start(top_configuration.soc_ifc_subenv_config.vsqr);
+    if (!rt_seq.randomize() with { rt_seq.mbox_op_rand.cmd == mbox_cmd_e'(MBOX_CMD_RT_UPDATE); })
+        `uvm_fatal("CALIPTRA_TOP_WDT_TEST", "caliptra_top_wdt_sequence::body() - rt_seq randomization failed")
+    rt_seq.start(top_configuration.soc_ifc_subenv_config.vsqr);
+
+    // Wait for RT image to set the ready_for_rt bit
+    while (!ready_for_rt) begin
+        while(!sts_rsp_count)soc_ifc_subenv_soc_ifc_ctrl_agent_config.wait_for_num_clocks(1); // Wait for new status updates
+        `uvm_info("CALIPTRA_TOP_WDT_TEST", "Observed status response, checking contents", UVM_DEBUG)
+        sts_rsp_count = 0; // We only care about the latest rsp, so even if count > 1, reset back to 0
+        ready_for_rt = soc_ifc_subenv_soc_ifc_status_agent_responder_seq.rsp.ready_for_runtime;
+    end
+  endtask
+
+  // ****************************************************************************
+  virtual task body();
+    // pragma uvmf custom body begin
+    // Construct sequences here
+    bit pauser_valid_initialized = 1'b0;
+    uvm_object obj;
+    int ii;
+    bit nmi_intr;
+    bit hw_error_fatal;
+    uvm_status_e reg_sts;
+    uvm_reg_data_t wdt_status_data;
+
+    caliptra_top_env_seq = caliptra_top_env_sequence_base_t::type_id::create("caliptra_top_env_seq");
+    soc_ifc_env_bringup_seq = soc_ifc_env_bringup_sequence_t::type_id::create("soc_ifc_env_bringup_seq");
+    soc_ifc_env_pauser_init_seq = soc_ifc_env_pauser_init_sequence_t::type_id::create("soc_ifc_env_pauser_init_seq");
+    soc_ifc_env_mbox_fmc_seq = soc_ifc_env_mbox_real_fw_sequence_t::type_id::create("soc_ifc_env_mbox_fmc_seq");
+    soc_ifc_env_mbox_rt_seq = soc_ifc_env_mbox_real_fw_sequence_t::type_id::create("soc_ifc_env_mbox_rt_seq");
+    soc_ifc_env_reset_warm_seq = soc_ifc_env_reset_warm_sequence_t::type_id::create("soc_ifc_env_reset_warm_seq");
+    soc_ifc_env_reset_cold_seq = soc_ifc_env_reset_cold_sequence_t::type_id::create("soc_ifc_env_reset_cold_seq");
+    soc_ifc_env_wdt_indep_seq = soc_ifc_env_cptra_wdt_independent_sequence_t::type_id::create("soc_ifc_env_wdt_indep_seq");
+    soc_ifc_env_wdt_cascade_seq = soc_ifc_env_cptra_wdt_cascade_sequence_t::type_id::create("soc_ifc_env_wdt_cascade_seq");
+
+    soc_ifc_subenv_soc_ifc_ctrl_agent_random_seq     = soc_ifc_subenv_soc_ifc_ctrl_agent_random_seq_t::type_id::create("soc_ifc_subenv_soc_ifc_ctrl_agent_random_seq");
+    soc_ifc_subenv_soc_ifc_status_agent_responder_seq  = soc_ifc_subenv_soc_ifc_status_agent_responder_seq_t::type_id::create("soc_ifc_subenv_soc_ifc_status_agent_responder_seq");
+    soc_ifc_subenv_mbox_sram_agent_responder_seq      = soc_ifc_subenv_mbox_sram_agent_responder_seq_t::type_id::create("soc_ifc_subenv_mbox_sram_agent_responder_seq");
+
+    // Handle to the responder sequence for getting response transactions
+    soc_ifc_env_bringup_seq.soc_ifc_status_agent_rsp_seq = soc_ifc_subenv_soc_ifc_status_agent_responder_seq;
+    soc_ifc_env_pauser_init_seq.soc_ifc_status_agent_rsp_seq = soc_ifc_subenv_soc_ifc_status_agent_responder_seq;
+    soc_ifc_env_mbox_fmc_seq.soc_ifc_status_agent_rsp_seq = soc_ifc_subenv_soc_ifc_status_agent_responder_seq;
+    soc_ifc_env_mbox_rt_seq.soc_ifc_status_agent_rsp_seq = soc_ifc_subenv_soc_ifc_status_agent_responder_seq;
+    soc_ifc_env_reset_warm_seq.soc_ifc_status_agent_rsp_seq = soc_ifc_subenv_soc_ifc_status_agent_responder_seq;
+    soc_ifc_env_reset_cold_seq.soc_ifc_status_agent_rsp_seq = soc_ifc_subenv_soc_ifc_status_agent_responder_seq;
+    soc_ifc_env_wdt_indep_seq.soc_ifc_status_agent_rsp_seq = soc_ifc_subenv_soc_ifc_status_agent_responder_seq;
+    soc_ifc_env_wdt_cascade_seq.soc_ifc_status_agent_rsp_seq = soc_ifc_subenv_soc_ifc_status_agent_responder_seq;
+
+    reg_model.reset();
+    // Start RESPONDER sequences here
+    fork
+        soc_ifc_subenv_soc_ifc_status_agent_responder_seq.start(soc_ifc_subenv_soc_ifc_status_agent_sequencer);
+        soc_ifc_subenv_mbox_sram_agent_responder_seq.start(soc_ifc_subenv_mbox_sram_agent_sequencer);
+    join_none
+
+    fork
+        forever @(soc_ifc_subenv_soc_ifc_status_agent_responder_seq.new_rsp) begin 
+          sts_rsp_count++;
+          rsp_count++;
+        end
+    join_none
+
+    if(!soc_ifc_env_bringup_seq.randomize())
+        `uvm_fatal("CALIPTRA_TOP_WDT_TEST", "caliptra_top_wdt_sequence::body() - soc_ifc_env_bringup_seq randomization failed")
+    soc_ifc_env_bringup_seq.start(top_configuration.soc_ifc_subenv_config.vsqr);
+
+    `uvm_info("CALIPTRA_TOP_BRINGUP", "SoC completed poweron and observed reset deassertion to system", UVM_LOW)
+
+    run_firmware_init(soc_ifc_env_mbox_fmc_seq,soc_ifc_env_mbox_rt_seq);
+
+    soc_ifc_env_wdt_cascade_seq.start(top_configuration.soc_ifc_subenv_config.vsqr);
+
+    //--------------------------------
+    //Wait for NMI to occur
+    while (!hw_error_fatal) begin
+      while(!rsp_count)soc_ifc_subenv_soc_ifc_ctrl_agent_config.wait_for_num_clocks(1); // Wait for new status updates
+      `uvm_info("CALIPTRA_TOP_WDT_TEST", "Observed status response, checking contents", UVM_MEDIUM)
+      `uvm_info("CALIPTRA_TOP_WDT_TEST", soc_ifc_subenv_soc_ifc_status_agent_responder_seq.rsp.convert2string(), UVM_MEDIUM)
+      rsp_count = 0; // We only care about the latest rsp, so even if count > 1, reset back to 0
+      hw_error_fatal = soc_ifc_subenv_soc_ifc_status_agent_responder_seq.rsp.cptra_error_fatal_intr_pending;
+    end
+      
+    //Check that NMI bit was set in the fatal error reg
+    if (reg_model.soc_ifc_reg_rm.CPTRA_HW_ERROR_FATAL.nmi_pin.get_mirrored_value()) begin
+      `uvm_info("CALIPTRA_TOP_WDT_TEST", "Encountered NMI, issuing reset", UVM_MEDIUM);
+      
+      //Issue warm reset
+      if(!soc_ifc_env_reset_warm_seq.randomize())
+          `uvm_fatal("CALIPTRA_TOP_WDT_TEST", "caliptra_top_wdt_sequence::body() - soc_ifc_env_reset_warm_seq randomization failed")
+      soc_ifc_env_reset_warm_seq.start(top_configuration.soc_ifc_subenv_config.vsqr);
+      // //--------------------------------
+    end
+    else begin
+      `uvm_error("CALIPTRA_TOP_WDT_TEST", "Did not see expected NMI interrupt")
+    end
+
+    // UVMF_CHANGE_ME : Extend the simulation XXX number of clocks after 
+    // the last sequence to allow for the last sequence item to flow 
+    // through the design.
+    fork
+      soc_ifc_subenv_soc_ifc_ctrl_agent_config.wait_for_num_clocks(10000);
+      soc_ifc_subenv_cptra_ctrl_agent_config.wait_for_num_clocks(10000);
+      soc_ifc_subenv_soc_ifc_status_agent_config.wait_for_num_clocks(10000);
+      soc_ifc_subenv_cptra_status_agent_config.wait_for_num_clocks(10000);
+      soc_ifc_subenv_mbox_sram_agent_config.wait_for_num_clocks(10000);
+    join
+
+    // pragma uvmf custom body end
+  endtask
+
+endclass
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/testbench/hdl_top.sv b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/testbench/hdl_top.sv
index 302144da3..3084672f4 100644
--- a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/testbench/hdl_top.sv
+++ b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/testbench/hdl_top.sv
@@ -86,6 +86,7 @@ import uvmf_base_pkg_hdl::*;
    // Custom Signal Declarations
    //=========================================================================-
     import soc_ifc_pkg::*;
+    import caliptra_top_tb_pkg::*;
 
     `include "config_defines.svh"
 
@@ -99,6 +100,7 @@ import uvmf_base_pkg_hdl::*;
     int                         cycleCnt;
     bit                         int_flag;
     bit                         cycleCnt_smpl_en;
+    ras_test_ctrl_t             ras_test_ctrl;
 
     //jtag interface
     logic                       jtag_tck    = '0; // JTAG clk
@@ -107,16 +109,22 @@ import uvmf_base_pkg_hdl::*;
     logic                       jtag_trst_n = '0; // JTAG Reset
     logic                       jtag_tdo;    // JTAG TDO
 
-    logic mbox_sram_cs;
-    logic mbox_sram_we;
-    logic [14:0] mbox_sram_addr;
-    logic [MBOX_DATA_AND_ECC_W-1:0] mbox_sram_wdata;
-    logic [MBOX_DATA_AND_ECC_W-1:0] mbox_sram_rdata;
+    mbox_sram_req_t mbox_sram_req;
+    mbox_sram_resp_t mbox_sram_resp;
+    logic mbox_sram_cs_stub_inactive;
+    logic mbox_sram_we_stub_inactive;
+    logic [14:0] mbox_sram_addr_stub_inactive;
+    logic [MBOX_DATA_AND_ECC_W-1:0] mbox_sram_wdata_stub_inactive;
+    logic [MBOX_DATA_AND_ECC_W-1:0] mbox_sram_rdata_stub_inactive;
 
     logic imem_cs;
     logic [`CALIPTRA_IMEM_ADDR_WIDTH-1:0] imem_addr;
     logic [`CALIPTRA_IMEM_DATA_WIDTH-1:0] imem_rdata;
 
+    logic        etrng_req;
+    logic  [3:0] itrng_data;
+    logic        itrng_valid;
+
     //device lifecycle
     security_state_t security_state_stub_inactive;
 
@@ -151,19 +159,26 @@ import uvmf_base_pkg_hdl::*;
      .clk(clk), .dummy(1'b1)
      // pragma uvmf custom soc_ifc_subenv_cptra_status_agent_bus_connections end
      );
+  mbox_sram_if  soc_ifc_subenv_mbox_sram_agent_bus(
+     // pragma uvmf custom soc_ifc_subenv_mbox_sram_agent_bus_connections begin
+     .clk(clk), .dummy(1'b1)
+     // pragma uvmf custom soc_ifc_subenv_mbox_sram_agent_bus_connections end
+     );
   soc_ifc_ctrl_monitor_bfm  soc_ifc_subenv_soc_ifc_ctrl_agent_mon_bfm(soc_ifc_subenv_soc_ifc_ctrl_agent_bus.monitor_port);
   cptra_ctrl_monitor_bfm  soc_ifc_subenv_cptra_ctrl_agent_mon_bfm(soc_ifc_subenv_cptra_ctrl_agent_bus.monitor_port);
   soc_ifc_status_monitor_bfm  soc_ifc_subenv_soc_ifc_status_agent_mon_bfm(soc_ifc_subenv_soc_ifc_status_agent_bus.monitor_port);
   cptra_status_monitor_bfm  soc_ifc_subenv_cptra_status_agent_mon_bfm(soc_ifc_subenv_cptra_status_agent_bus.monitor_port);
+  mbox_sram_monitor_bfm  soc_ifc_subenv_mbox_sram_agent_mon_bfm(soc_ifc_subenv_mbox_sram_agent_bus.monitor_port);
   soc_ifc_ctrl_driver_bfm  soc_ifc_subenv_soc_ifc_ctrl_agent_drv_bfm(soc_ifc_subenv_soc_ifc_ctrl_agent_bus.initiator_port);
   soc_ifc_status_driver_bfm  soc_ifc_subenv_soc_ifc_status_agent_drv_bfm(soc_ifc_subenv_soc_ifc_status_agent_bus.responder_port);
+  mbox_sram_driver_bfm  soc_ifc_subenv_mbox_sram_agent_drv_bfm(soc_ifc_subenv_mbox_sram_agent_bus.responder_port);
 
   // pragma uvmf custom dut_instantiation begin
   // AHB Clock/reset
   assign uvm_test_top_environment_soc_ifc_subenv_qvip_ahb_lite_slave_subenv_qvip_hdl.default_clk_gen_CLK     = clk;
   assign uvm_test_top_environment_soc_ifc_subenv_qvip_ahb_lite_slave_subenv_qvip_hdl.default_reset_gen_RESET = caliptra_top_dut.cptra_noncore_rst_b;
   assign uvm_test_top_environment_soc_ifc_subenv_qvip_apb5_slave_subenv_qvip_hdl.default_clk_gen_CLK         = clk;
-  assign uvm_test_top_environment_soc_ifc_subenv_qvip_apb5_slave_subenv_qvip_hdl.default_reset_gen_RESET     = soc_ifc_subenv_soc_ifc_ctrl_agent_bus.cptra_rst_b;
+  assign uvm_test_top_environment_soc_ifc_subenv_qvip_apb5_slave_subenv_qvip_hdl.default_reset_gen_RESET     = caliptra_top_dut.cptra_noncore_rst_b;
 
 
     //=========================================================================-
@@ -193,21 +208,23 @@ import uvmf_base_pkg_hdl::*;
         .PWDATA (uvm_test_top_environment_soc_ifc_subenv_qvip_apb5_slave_subenv_qvip_hdl.apb5_master_0_PWDATA     ),
         .PWRITE (uvm_test_top_environment_soc_ifc_subenv_qvip_apb5_slave_subenv_qvip_hdl.apb5_master_0_PWRITE     ),
 
-        .qspi_clk_o(/*TODO*/),
-        .qspi_cs_no(/*TODO*/),
-        .qspi_d_io (/*TODO*/),
+        .qspi_clk_o  (/*TODO*/),
+        .qspi_cs_no  (/*TODO*/),
+        .qspi_d_i    (/*TODO*/),
+        .qspi_d_o    (/*TODO*/),
+        .qspi_d_en_o (/*TODO*/),
 
-        .el2_mem_export(el2_mem_export),
+        .el2_mem_export(el2_mem_export.veer_sram_src),
 
         .ready_for_fuses  (soc_ifc_subenv_soc_ifc_status_agent_bus.ready_for_fuses   ),
         .ready_for_fw_push(soc_ifc_subenv_soc_ifc_status_agent_bus.ready_for_fw_push ),
         .ready_for_runtime(soc_ifc_subenv_soc_ifc_status_agent_bus.ready_for_runtime ),
 
-        .mbox_sram_cs   (mbox_sram_cs   ),
-        .mbox_sram_we   (mbox_sram_we   ),
-        .mbox_sram_addr (mbox_sram_addr ),
-        .mbox_sram_wdata(mbox_sram_wdata),
-        .mbox_sram_rdata(mbox_sram_rdata),
+        .mbox_sram_cs   (mbox_sram_req.cs   ),
+        .mbox_sram_we   (mbox_sram_req.we   ),
+        .mbox_sram_addr (mbox_sram_req.addr ),
+        .mbox_sram_wdata(mbox_sram_req.wdata),
+        .mbox_sram_rdata(mbox_sram_resp.rdata),
 
         .imem_cs        (imem_cs        ),
         .imem_addr      (imem_addr      ),
@@ -221,16 +238,23 @@ import uvmf_base_pkg_hdl::*;
         .cptra_error_fatal    (soc_ifc_subenv_soc_ifc_status_agent_bus.cptra_error_fatal),
         .cptra_error_non_fatal(soc_ifc_subenv_soc_ifc_status_agent_bus.cptra_error_non_fatal),
         // External TRNG
+`ifdef CALIPTRA_INTERNAL_TRNG
+        .etrng_req             (etrng_req),
+        // Internal TRNG
+        .itrng_data            (itrng_data ),
+        .itrng_valid           (itrng_valid),
+`else
         .etrng_req             (soc_ifc_subenv_soc_ifc_status_agent_bus.trng_req),
         // Internal TRNG
-        .itrng_data            (4'h0),  // TODO
-        .itrng_valid           (1'b0),  // TODO
+        .itrng_data            (4'h0),
+        .itrng_valid           (1'b0),
+`endif
 
         .generic_input_wires (soc_ifc_subenv_soc_ifc_ctrl_agent_bus.generic_input_wires),
         .generic_output_wires(soc_ifc_subenv_soc_ifc_status_agent_bus.generic_output_wires),
 
         .security_state(soc_ifc_subenv_soc_ifc_ctrl_agent_bus.security_state),
-        .scan_mode     (1'b0)
+        .scan_mode     (1'b0) // TODO
     );
     assign uvm_test_top_environment_soc_ifc_subenv_qvip_apb5_slave_subenv_qvip_hdl.apb5_master_0_PWUSER           = 0;
     assign uvm_test_top_environment_soc_ifc_subenv_qvip_apb5_slave_subenv_qvip_hdl.apb5_master_0_PRUSER           = 0;
@@ -278,17 +302,38 @@ import uvmf_base_pkg_hdl::*;
     assign soc_ifc_subenv_cptra_status_agent_bus.cptra_noncore_rst_b = caliptra_top_dut.cptra_noncore_rst_b;
     assign soc_ifc_subenv_cptra_status_agent_bus.cptra_obf_key_reg = caliptra_top_dut.cptra_obf_key_reg;
     assign soc_ifc_subenv_cptra_status_agent_bus.cptra_uc_rst_b = caliptra_top_dut.cptra_uc_rst_b;
+    assign soc_ifc_subenv_cptra_status_agent_bus.fw_update_rst_window = caliptra_top_dut.fw_update_rst_window;
     assign soc_ifc_subenv_cptra_status_agent_bus.iccm_lock = caliptra_top_dut.iccm_lock;
     assign soc_ifc_subenv_cptra_status_agent_bus.nmi_vector = caliptra_top_dut.nmi_vector;
+    assign soc_ifc_subenv_cptra_status_agent_bus.nmi_intr = caliptra_top_dut.nmi_int;
     assign soc_ifc_subenv_cptra_status_agent_bus.obf_field_entropy = caliptra_top_dut.obf_field_entropy;
     assign soc_ifc_subenv_cptra_status_agent_bus.obf_uds_seed = caliptra_top_dut.obf_uds_seed;
     assign soc_ifc_subenv_cptra_status_agent_bus.sha_error_intr = caliptra_top_dut.sha_error_intr;
     assign soc_ifc_subenv_cptra_status_agent_bus.sha_notif_intr = caliptra_top_dut.sha_notif_intr;
     assign soc_ifc_subenv_cptra_status_agent_bus.soc_ifc_error_intr = caliptra_top_dut.soc_ifc_error_intr;
     assign soc_ifc_subenv_cptra_status_agent_bus.soc_ifc_notif_intr = caliptra_top_dut.soc_ifc_notif_intr;
+    assign soc_ifc_subenv_cptra_status_agent_bus.timer_intr = caliptra_top_dut.timer_int;
 
     assign soc_ifc_subenv_cptra_ctrl_agent_bus.clear_obf_secrets = caliptra_top_dut.clear_obf_secrets_debugScanQ;
     assign soc_ifc_subenv_cptra_ctrl_agent_bus.iccm_axs_blocked = caliptra_top_dut.ahb_lite_resp_access_blocked[`CALIPTRA_SLAVE_SEL_IDMA];
+    assign soc_ifc_subenv_cptra_ctrl_agent_bus.rv_ecc_sts = caliptra_top_dut.rv_ecc_sts;
+
+    assign soc_ifc_subenv_mbox_sram_agent_bus.mbox_sram_req = mbox_sram_req;
+    assign mbox_sram_resp = soc_ifc_subenv_mbox_sram_agent_bus.mbox_sram_resp;
+
+`ifdef CALIPTRA_INTERNAL_TRNG
+    //=========================================================================-
+    // Physical RNG used for Internal TRNG
+    //=========================================================================-
+    physical_rng physical_rng_i (
+        .clk    (clk),
+        .enable (etrng_req),
+        .data   (itrng_data),
+        .valid  (itrng_valid)
+    );
+
+    assign soc_ifc_subenv_soc_ifc_status_agent_bus.trng_req = 1'b0;
+`endif
 
     //=========================================================================-
     // Services for SRAM exports, STDOUT, etc
@@ -301,14 +346,14 @@ import uvmf_base_pkg_hdl::*;
         .cptra_rst_b(soc_ifc_subenv_soc_ifc_ctrl_agent_bus.cptra_rst_b  ),
 
         // Caliptra Memory Export Interface
-        .el2_mem_export (el2_mem_export),
+        .el2_mem_export (el2_mem_export.veer_sram_sink),
 
         //SRAM interface for mbox
-        .mbox_sram_cs   (mbox_sram_cs   ),
-        .mbox_sram_we   (mbox_sram_we   ),
-        .mbox_sram_addr (mbox_sram_addr ),
-        .mbox_sram_wdata(mbox_sram_wdata),
-        .mbox_sram_rdata(mbox_sram_rdata),
+        .mbox_sram_cs   (mbox_sram_cs_stub_inactive   ),
+        .mbox_sram_we   (mbox_sram_we_stub_inactive   ),
+        .mbox_sram_addr (mbox_sram_addr_stub_inactive ),
+        .mbox_sram_wdata(mbox_sram_wdata_stub_inactive),
+        .mbox_sram_rdata(mbox_sram_rdata_stub_inactive),
 
         //SRAM interface for imem
         .imem_cs   (imem_cs   ),
@@ -319,6 +364,7 @@ import uvmf_base_pkg_hdl::*;
         .security_state(security_state_stub_inactive),
 
         // TB Controls
+        .ras_test_ctrl(ras_test_ctrl),
         .cycleCnt(cycleCnt),
         .cycleCnt_smpl_en(cycleCnt_smpl_en),
 
@@ -338,8 +384,10 @@ import uvmf_base_pkg_hdl::*;
     uvm_config_db #( virtual cptra_ctrl_monitor_bfm  )::set( null , UVMF_VIRTUAL_INTERFACES , soc_ifc_subenv_cptra_ctrl_agent_BFM , soc_ifc_subenv_cptra_ctrl_agent_mon_bfm ); 
     uvm_config_db #( virtual soc_ifc_status_monitor_bfm  )::set( null , UVMF_VIRTUAL_INTERFACES , soc_ifc_subenv_soc_ifc_status_agent_BFM , soc_ifc_subenv_soc_ifc_status_agent_mon_bfm ); 
     uvm_config_db #( virtual cptra_status_monitor_bfm  )::set( null , UVMF_VIRTUAL_INTERFACES , soc_ifc_subenv_cptra_status_agent_BFM , soc_ifc_subenv_cptra_status_agent_mon_bfm ); 
+    uvm_config_db #( virtual mbox_sram_monitor_bfm  )::set( null , UVMF_VIRTUAL_INTERFACES , soc_ifc_subenv_mbox_sram_agent_BFM , soc_ifc_subenv_mbox_sram_agent_mon_bfm ); 
     uvm_config_db #( virtual soc_ifc_ctrl_driver_bfm  )::set( null , UVMF_VIRTUAL_INTERFACES , soc_ifc_subenv_soc_ifc_ctrl_agent_BFM , soc_ifc_subenv_soc_ifc_ctrl_agent_drv_bfm  );
     uvm_config_db #( virtual soc_ifc_status_driver_bfm  )::set( null , UVMF_VIRTUAL_INTERFACES , soc_ifc_subenv_soc_ifc_status_agent_BFM , soc_ifc_subenv_soc_ifc_status_agent_drv_bfm  );
+    uvm_config_db #( virtual mbox_sram_driver_bfm  )::set( null , UVMF_VIRTUAL_INTERFACES , soc_ifc_subenv_mbox_sram_agent_BFM , soc_ifc_subenv_mbox_sram_agent_drv_bfm ); 
   end
 
 endmodule
diff --git a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/caliptra_top_tests_pkg.sv b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/caliptra_top_tests_pkg.sv
index f01a3b95a..751ca96c5 100644
--- a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/caliptra_top_tests_pkg.sv
+++ b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/caliptra_top_tests_pkg.sv
@@ -65,9 +65,10 @@ package caliptra_top_tests_pkg;
    `include "src/register_test.svh"
    `include "src/example_derived_test.svh"
    `include "src/caliptra_top_rand_test.svh"
-   `include "src/caliptra_top_fw_update_test.svh"
-   `include "src/caliptra_top_reg_access_test.svh"
+   `include "src/caliptra_top_wdt_test.svh"
+   `include "src/caliptra_top_wdt_independent_test.svh"
    `include "src/caliptra_top_cmdline_test.svh"
+   `include "src/caliptra_top_rom_test.svh"
 
   // pragma uvmf custom package_item_additional begin
   // UVMF_CHANGE_ME : When adding new tests to the src directory
diff --git a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_fw_update_test.yml b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_fw_update_test.yml
deleted file mode 100644
index c630b96ee..000000000
--- a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_fw_update_test.yml
+++ /dev/null
@@ -1,6 +0,0 @@
----
-# Random seed desired...
-seed: ${PLAYBOOK_RANDOM_SEED}
-plusargs:
-- '+UVM_TESTNAME=caliptra_top_fw_update_test'
-testname: caliptra_top_fw_update_test
diff --git a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_reg_access_test.yml b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_reg_access_test.yml
deleted file mode 100644
index fda0cf23f..000000000
--- a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_reg_access_test.yml
+++ /dev/null
@@ -1,6 +0,0 @@
----
-# Random seed desired...
-seed: ${PLAYBOOK_RANDOM_SEED}
-plusargs:
-- '+UVM_TESTNAME=caliptra_top_reg_access_test'
-testname: caliptra_top_reg_access_test
diff --git a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_rom_test.svh b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_rom_test.svh
new file mode 100644
index 000000000..30926d48e
--- /dev/null
+++ b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_rom_test.svh
@@ -0,0 +1,82 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: This test extends test_top and makes
+//    changes to test_top using the UVM factory type_override:
+//
+//    Test scenario:
+//      Load the FW-team ROM image and use it to boot a subsequent FW image.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+class caliptra_top_rom_test extends test_top;
+
+  `uvm_component_utils( caliptra_top_rom_test );
+
+  function new( string name = "", uvm_component parent = null );
+    super.new( name, parent );
+  endfunction
+
+  virtual function void build_phase(uvm_phase phase);
+    // The factory override below is an example of how to replace the caliptra_top_bench_sequence_base
+    // sequence with the example_derived_test_sequence.
+    caliptra_top_bench_sequence_base::type_id::set_type_override(caliptra_top_rom_sequence::get_type());
+    // Execute the build_phase of test_top AFTER all factory overrides have been created.
+    super.build_phase(phase);
+    // pragma uvmf custom configuration_settings_post_randomize begin
+    // UVMF_CHANGE_ME Test specific configuration values can be set here.
+    // The configuration structure has already been randomized.
+    // pragma uvmf custom configuration_settings_post_randomize end
+  endfunction
+
+  virtual function void start_of_simulation_phase(uvm_phase phase);
+      super.start_of_simulation_phase(phase);
+      if ($test$plusargs("CLP_REGRESSION")) begin
+          uvm_top.set_report_verbosity_level_hier(UVM_LOW);
+//          this.environment.soc_ifc_subenv.soc_ifc_pred.set_report_severity_action(UVM_WARNING,UVM_NO_ACTION);
+//          this.environment.soc_ifc_subenv.soc_ifc_sb.set_report_severity_action(UVM_WARNING,UVM_NO_ACTION);
+          // Since en_sb is recently set to 0, this is unavailable and gives null-object
+          //this.environment.soc_ifc_subenv.qvip_apb5_slave_subenv.apb5_master_0.get_analysis_component("checker").set_report_severity_id_action(UVM_WARNING,"scoreboard_debug",UVM_NO_ACTION);
+      end
+  endfunction
+
+// FUNCTION: run_phase
+// This task manages the test objection and starts the top level sequence.
+  virtual task run_phase( uvm_phase phase );
+    int fd;
+    string system_time;
+    fork
+        forever begin
+            configuration.soc_ifc_subenv_config.soc_ifc_ctrl_agent_config.wait_for_num_clocks(10000); // Report time every 100us
+            $system("date | tr -d '\\n' > curdate");
+            fd = $fopen("curdate", "r");
+            assert($fgets(system_time, fd) != 0);
+            $fclose(fd);
+            `uvm_info("ROM_TEST_HEARTBEAT",$sformatf("system time is [%s]", system_time),UVM_LOW);
+        end
+    join_none
+    super.run_phase(phase);
+  endtask
+
+endclass
diff --git a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_rom_test.yml b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_rom_test.yml
new file mode 100644
index 000000000..bf1f60e7c
--- /dev/null
+++ b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_rom_test.yml
@@ -0,0 +1,6 @@
+---
+# Random seed desired...
+seed: ${PLAYBOOK_RANDOM_SEED}
+plusargs:
+- '+UVM_TESTNAME=caliptra_top_rom_test'
+testname: caliptra_top_rom_test
diff --git a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_reg_access_test.svh b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_wdt_independent_test.svh
similarity index 64%
rename from src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_reg_access_test.svh
rename to src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_wdt_independent_test.svh
index 3d8d93533..b1138994a 100644
--- a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_reg_access_test.svh
+++ b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_wdt_independent_test.svh
@@ -24,15 +24,15 @@
 //    changes to test_top using the UVM factory type_override:
 //
 //    Test scenario:
-//      Randomized activity to mailbox
+//      Randomized activity to Caliptra
 //
 //----------------------------------------------------------------------
 //----------------------------------------------------------------------
 //
 
-class caliptra_top_reg_access_test extends test_top;
+class caliptra_top_wdt_independent_test extends test_top;
 
-  `uvm_component_utils( caliptra_top_reg_access_test );
+  `uvm_component_utils( caliptra_top_wdt_independent_test );
 
   function new( string name = "", uvm_component parent = null );
     super.new( name, parent );
@@ -41,7 +41,7 @@ class caliptra_top_reg_access_test extends test_top;
   virtual function void build_phase(uvm_phase phase);
     // The factory override below is an example of how to replace the caliptra_top_bench_sequence_base
     // sequence with the example_derived_test_sequence.
-    caliptra_top_bench_sequence_base::type_id::set_type_override(caliptra_top_reg_access_sequence::get_type());
+    caliptra_top_bench_sequence_base::type_id::set_type_override(caliptra_top_wdt_independent_sequence::get_type());
     // Execute the build_phase of test_top AFTER all factory overrides have been created.
     super.build_phase(phase);
     // pragma uvmf custom configuration_settings_post_randomize begin
@@ -50,6 +50,20 @@ class caliptra_top_reg_access_test extends test_top;
     // pragma uvmf custom configuration_settings_post_randomize end
   endfunction
 
+  // FIXME this disables uvm_warning messages! We should fix the warnings, but for
+  //       now this reduces sim.log (for regressions) to a manageable level
+  // NOTE: UVM_WARNING now re-enabled, need to clean this up after some regression cycles
+  virtual function void start_of_simulation_phase(uvm_phase phase);
+      super.start_of_simulation_phase(phase);
+      if ($test$plusargs("CLP_REGRESSION")) begin
+          uvm_top.set_report_verbosity_level_hier(UVM_NONE);
+//          this.environment.soc_ifc_subenv.soc_ifc_pred.set_report_severity_action(UVM_WARNING,UVM_NO_ACTION);
+//          this.environment.soc_ifc_subenv.soc_ifc_sb.set_report_severity_action(UVM_WARNING,UVM_NO_ACTION);
+          // Since en_sb is recently set to 0, this is unavailable and gives null-object
+          //this.environment.soc_ifc_subenv.qvip_apb5_slave_subenv.apb5_master_0.get_analysis_component("checker").set_report_severity_id_action(UVM_WARNING,"scoreboard_debug",UVM_NO_ACTION);
+      end
+  endfunction
+
 endclass
 
 // pragma uvmf custom external begin
diff --git a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_wdt_independent_test.yml b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_wdt_independent_test.yml
new file mode 100644
index 000000000..1be3f550b
--- /dev/null
+++ b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_wdt_independent_test.yml
@@ -0,0 +1,6 @@
+---
+# Random seed desired...
+seed: ${PLAYBOOK_RANDOM_SEED}
+plusargs:
+- '+UVM_TESTNAME=caliptra_top_wdt_independent_test'
+testname: caliptra_top_wdt_independent_test
diff --git a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_fw_update_test.svh b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_wdt_test.svh
similarity index 64%
rename from src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_fw_update_test.svh
rename to src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_wdt_test.svh
index 465e52581..504820b6c 100644
--- a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_fw_update_test.svh
+++ b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_wdt_test.svh
@@ -24,15 +24,15 @@
 //    changes to test_top using the UVM factory type_override:
 //
 //    Test scenario:
-//      Randomized activity to mailbox
+//      Randomized activity to Caliptra
 //
 //----------------------------------------------------------------------
 //----------------------------------------------------------------------
 //
 
-class caliptra_top_fw_update_test extends test_top;
+class caliptra_top_wdt_test extends test_top;
 
-  `uvm_component_utils( caliptra_top_fw_update_test );
+  `uvm_component_utils( caliptra_top_wdt_test );
 
   function new( string name = "", uvm_component parent = null );
     super.new( name, parent );
@@ -41,7 +41,7 @@ class caliptra_top_fw_update_test extends test_top;
   virtual function void build_phase(uvm_phase phase);
     // The factory override below is an example of how to replace the caliptra_top_bench_sequence_base
     // sequence with the example_derived_test_sequence.
-    caliptra_top_bench_sequence_base::type_id::set_type_override(caliptra_top_fw_update_sequence::get_type());
+    caliptra_top_bench_sequence_base::type_id::set_type_override(caliptra_top_wdt_sequence::get_type());
     // Execute the build_phase of test_top AFTER all factory overrides have been created.
     super.build_phase(phase);
     // pragma uvmf custom configuration_settings_post_randomize begin
@@ -50,6 +50,20 @@ class caliptra_top_fw_update_test extends test_top;
     // pragma uvmf custom configuration_settings_post_randomize end
   endfunction
 
+  // FIXME this disables uvm_warning messages! We should fix the warnings, but for
+  //       now this reduces sim.log (for regressions) to a manageable level
+  // NOTE: UVM_WARNING now re-enabled, need to clean this up after some regression cycles
+  virtual function void start_of_simulation_phase(uvm_phase phase);
+      super.start_of_simulation_phase(phase);
+      if ($test$plusargs("CLP_REGRESSION")) begin
+          uvm_top.set_report_verbosity_level_hier(UVM_NONE);
+//          this.environment.soc_ifc_subenv.soc_ifc_pred.set_report_severity_action(UVM_WARNING,UVM_NO_ACTION);
+//          this.environment.soc_ifc_subenv.soc_ifc_sb.set_report_severity_action(UVM_WARNING,UVM_NO_ACTION);
+          // Since en_sb is recently set to 0, this is unavailable and gives null-object
+          //this.environment.soc_ifc_subenv.qvip_apb5_slave_subenv.apb5_master_0.get_analysis_component("checker").set_report_severity_id_action(UVM_WARNING,"scoreboard_debug",UVM_NO_ACTION);
+      end
+  endfunction
+
 endclass
 
 // pragma uvmf custom external begin
diff --git a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_wdt_test.yml b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_wdt_test.yml
new file mode 100644
index 000000000..1f1af25ad
--- /dev/null
+++ b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_wdt_test.yml
@@ -0,0 +1,6 @@
+---
+# Random seed desired...
+seed: ${PLAYBOOK_RANDOM_SEED}
+plusargs:
+- '+UVM_TESTNAME=caliptra_top_wdt_test'
+testname: caliptra_top_wdt_test
diff --git a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/test_top.svh b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/test_top.svh
index d7b840b4a..1d0b78285 100644
--- a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/test_top.svh
+++ b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/test_top.svh
@@ -52,7 +52,8 @@ qvip_memory_message_handler message_handler;
     soc_ifc_subenv_soc_ifc_ctrl_agent_BFM /* soc_ifc_subenv_soc_ifc_ctrl_agent     [2] */ , 
     soc_ifc_subenv_cptra_ctrl_agent_BFM /* soc_ifc_subenv_cptra_ctrl_agent     [3] */ , 
     soc_ifc_subenv_soc_ifc_status_agent_BFM /* soc_ifc_subenv_soc_ifc_status_agent     [4] */ , 
-    soc_ifc_subenv_cptra_status_agent_BFM /* soc_ifc_subenv_cptra_status_agent     [5] */ 
+    soc_ifc_subenv_cptra_status_agent_BFM /* soc_ifc_subenv_cptra_status_agent     [5] */ , 
+    soc_ifc_subenv_mbox_sram_agent_BFM /* soc_ifc_subenv_mbox_sram_agent     [6] */ 
 };
 
 uvmf_active_passive_t interface_activities[] = { 
@@ -61,7 +62,8 @@ uvmf_active_passive_t interface_activities[] = {
     ACTIVE /* soc_ifc_subenv_soc_ifc_ctrl_agent     [2] */ , 
     PASSIVE /* soc_ifc_subenv_cptra_ctrl_agent     [3] */ , 
     ACTIVE /* soc_ifc_subenv_soc_ifc_status_agent     [4] */ , 
-    PASSIVE /* soc_ifc_subenv_cptra_status_agent     [5] */   };
+    PASSIVE /* soc_ifc_subenv_cptra_status_agent     [5] */ ,
+    ACTIVE /* soc_ifc_subenv_mbox_sram_agent     [6] */   };
 
   // pragma uvmf custom class_item_additional begin
   // pragma uvmf custom class_item_additional end
diff --git a/src/integration/uvmf_caliptra_top/uvmf_template_output/verification_ip/environment_packages/caliptra_top_env_pkg/src/caliptra_top_env_configuration.svh b/src/integration/uvmf_caliptra_top/uvmf_template_output/verification_ip/environment_packages/caliptra_top_env_pkg/src/caliptra_top_env_configuration.svh
index 8c57ff4c2..52763e73d 100644
--- a/src/integration/uvmf_caliptra_top/uvmf_template_output/verification_ip/environment_packages/caliptra_top_env_pkg/src/caliptra_top_env_configuration.svh
+++ b/src/integration/uvmf_caliptra_top/uvmf_template_output/verification_ip/environment_packages/caliptra_top_env_pkg/src/caliptra_top_env_configuration.svh
@@ -130,11 +130,11 @@ rand soc_ifc_subenv_config_t soc_ifc_subenv_config;
     super.initialize(sim_level, environment_path, interface_names, register_model, interface_activity);
 
   // Interface initialization for sub-environments
-    soc_ifc_subenv_interface_names    = new[6];
-    soc_ifc_subenv_interface_activity = new[6];
+    soc_ifc_subenv_interface_names    = new[7];
+    soc_ifc_subenv_interface_activity = new[7];
 
-    soc_ifc_subenv_interface_names     = interface_names[0:5];
-    soc_ifc_subenv_interface_activity  = interface_activity[0:5];
+    soc_ifc_subenv_interface_names     = interface_names[0:6];
+    soc_ifc_subenv_interface_activity  = interface_activity[0:6];
 
 
 
diff --git a/src/keyvault/config/compile.yml b/src/keyvault/config/compile.yml
index 68cb53727..e0d516e0e 100644
--- a/src/keyvault/config/compile.yml
+++ b/src/keyvault/config/compile.yml
@@ -21,6 +21,17 @@ targets:
     files:
       - $COMPILE_ROOT/rtl/kv_reg_uvm.sv
 ---
+provides: [keyvault_cov]
+schema_version: 2.4.0
+targets:
+  tb:
+    directories:
+      - $COMPILE_ROOT/coverage
+    files:
+      - $COMPILE_ROOT/coverage/keyvault_cov_if.sv
+      - $COMPILE_ROOT/coverage/keyvault_cov_props.sv
+      - $COMPILE_ROOT/coverage/keyvault_cov_bind.sv
+---
 provides: [keyvault]
 schema_version: 2.4.0
 requires: 
diff --git a/src/keyvault/config/keyvault.vf b/src/keyvault/config/keyvault.vf
index 825fd9d1c..40ef426e3 100644
--- a/src/keyvault/config/keyvault.vf
+++ b/src/keyvault/config/keyvault.vf
@@ -12,6 +12,7 @@ ${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
 ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_defines_pkg.sv
 ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_macros.svh
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
diff --git a/src/keyvault/config/keyvault_cov.vf b/src/keyvault/config/keyvault_cov.vf
new file mode 100644
index 000000000..b5d6ed794
--- /dev/null
+++ b/src/keyvault/config/keyvault_cov.vf
@@ -0,0 +1,4 @@
++incdir+${CALIPTRA_ROOT}/src/keyvault/coverage
+${CALIPTRA_ROOT}/src/keyvault/coverage/keyvault_cov_if.sv
+${CALIPTRA_ROOT}/src/keyvault/coverage/keyvault_cov_props.sv
+${CALIPTRA_ROOT}/src/keyvault/coverage/keyvault_cov_bind.sv
\ No newline at end of file
diff --git a/src/keyvault/coverage/keyvault_cov_bind.sv b/src/keyvault/coverage/keyvault_cov_bind.sv
new file mode 100644
index 000000000..7e2311508
--- /dev/null
+++ b/src/keyvault/coverage/keyvault_cov_bind.sv
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+module keyvault_cov_bind;
+    //`ifdef FCOV
+    bind dut keyvault_cov_if i_keyvault_cov_if(.*);
+    bind dut keyvault_cov_props i_keyvault_cov_props(.*);
+    //`endif
+endmodule
diff --git a/src/keyvault/coverage/keyvault_cov_if.sv b/src/keyvault/coverage/keyvault_cov_if.sv
new file mode 100644
index 000000000..f896c3d02
--- /dev/null
+++ b/src/keyvault/coverage/keyvault_cov_if.sv
@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// This file contains cross coverage for keyvault at the dut level
+// This interface is instantiated in uvmf_kv for coverage during randomized UVM tests
+
+`ifndef VERILATOR
+
+interface keyvault_cov_if     
+    import kv_defines_pkg::*;
+    (
+    //Keyvault IO
+    input logic clk,
+    input logic rst_b,
+    input logic core_only_rst_b,
+    input logic cptra_pwrgood,
+    input logic debugUnlock_or_scan_mode_switch
+);
+
+    //Intermediate wires
+    logic [KV_NUM_KEYS-1:0] key_ctrl_lock_wr;
+    logic [KV_NUM_KEYS-1:0] key_ctrl_lock_use;
+    logic [KV_NUM_KEYS-1:0] key_ctrl_clear;
+
+    logic clear_secrets_wr;
+    logic clear_secrets_sel;
+    logic [KV_NUM_WRITE-1:0] kv_write_en;
+    logic ahb_write, ahb_read;
+    
+    //Assign clear and locks of each KEY_CTRL reg to corresponding bit in the intermediate bus
+    generate
+        for(genvar i = 0; i < KV_NUM_KEYS; i++) begin
+            assign key_ctrl_lock_wr[i] = dut.kv_reg_hwif_out.KEY_CTRL[i].lock_wr;
+            assign key_ctrl_lock_use[i] = dut.kv_reg_hwif_out.KEY_CTRL[i].lock_use;
+            assign key_ctrl_clear[i] = dut.kv_reg_hwif_out.KEY_CTRL[i].clear;
+        end
+    endgenerate
+
+    //CLEAR_SECRETS
+    assign clear_secrets_wr = dut.kv_reg_hwif_out.CLEAR_SECRETS.wr_debug_values;
+    assign clear_secrets_sel = dut.kv_reg_hwif_out.CLEAR_SECRETS.sel_debug_value;
+
+    //Crypto interface write_en
+    generate
+        for(genvar client = 0; client < KV_NUM_WRITE; client++) begin
+            assign kv_write_en[client] = dut.kv_write[client].write_en;
+        end
+    endgenerate
+
+    //AHB signals
+    assign ahb_write = dut.kv_ahb_slv1.dv & dut.kv_ahb_slv1.write;
+    assign ahb_read  = dut.kv_ahb_slv1.dv & ~dut.kv_ahb_slv1.write;
+
+    covergroup keyvault_top_cov_grp @(posedge clk);
+        option.per_instance = 1;
+        debug: coverpoint debugUnlock_or_scan_mode_switch;
+
+        //Note: Bit transitions and values for lock_wr, lock_use and clear are covered
+        //in UVM reg coverage. This coverpoint bins the 32-bit lock/clear bus so that
+        //they can be used to cross with other signals
+        lock_wr: coverpoint key_ctrl_lock_wr {
+            bins bin0 = {[0:'hFFFF]};
+            bins bin1 = {['h1_0000:'hF_FFFF]};
+            bins bin2 = {['h10_0000:'hFF_FFFF]};
+            bins bin3 = {['h100_0000:'hFFF_FFFF]};
+            bins bin4 = {['h1000_0000: 'hFFFF_FFFF]};
+        }
+        lock_use: coverpoint key_ctrl_lock_use {
+            bins bin0 = {[0:'hFFFF]};
+            bins bin1 = {['h1_0000:'hF_FFFF]};
+            bins bin2 = {['h10_0000:'hFF_FFFF]};
+            bins bin3 = {['h100_0000:'hFFF_FFFF]};
+            bins bin4 = {['h1000_0000: 'hFFFF_FFFF]};
+        }
+        clear: coverpoint key_ctrl_clear {
+            bins bin0 = {[0:'hFFFF]};
+            bins bin1 = {['h1_0000:'hF_FFFF]};
+            bins bin2 = {['h10_0000:'hFF_FFFF]};
+            bins bin3 = {['h100_0000:'hFFF_FFFF]};
+            bins bin4 = {['h1000_0000: 'hFFFF_FFFF]};
+        }
+        cp_clear_secrets_sel: coverpoint clear_secrets_sel;
+        cp_clear_secrets_wr : coverpoint clear_secrets_wr;
+        cp_ahb_write        : coverpoint ahb_write;
+        cp_ahb_read         : coverpoint ahb_read;
+
+        //Cover debug mode unlocked while regs are locked/cleared
+        debugXlock_wr:                  cross debug, lock_wr;
+        debugXlock_use:                 cross debug, lock_use;
+        debugXclear:                    cross debug, clear;
+        debugXlock_wrXlock_useXclear:   cross debug, lock_wr, lock_use, clear;
+        debugXclear_secrets:            cross debug, cp_clear_secrets_wr, cp_clear_secrets_sel;
+
+        //Cover warm reset assertion while regs are locked/cleared
+        lock_wrXwarm_rst:   cross lock_wr, rst_b;
+        lock_useXwarm_rst:  cross lock_use, rst_b;
+        clearXwarm_rst:     cross clear, rst_b;
+
+        //Cover cold reset while regs are locked/cleared
+        lock_wrXcold_rst:   cross lock_wr, cptra_pwrgood;
+        lock_useXcold_rst:  cross lock_use, cptra_pwrgood;
+        clearXcold_rst:     cross clear, cptra_pwrgood;
+
+        //Cover core reset while regs are locked/cleared
+        lock_wrXcore_rst:   cross lock_wr, core_only_rst_b;
+        lock_useXcore_rst:  cross lock_use, core_only_rst_b;
+        clearXcore_rst:     cross clear, core_only_rst_b;
+
+        //Cover simultaneous locks/clear settings
+        lock_wrXlock_useXclearXclear_secrets: cross lock_wr, lock_use, clear, cp_clear_secrets_wr, cp_clear_secrets_sel;
+        
+        //Cross with crypto write. There's no cross with read since reads are async
+        //Due to this, at any given time, all signals are by default crossed with read IF
+        lock_wrXkv_write:   cross lock_wr, kv_write_en;
+        lock_useXkv_write:  cross lock_use, kv_write_en;
+        clearXkv_write:     cross clear, kv_write_en;
+
+        clear_secretsXkv_write: cross kv_write_en, cp_clear_secrets_wr, cp_clear_secrets_sel;
+
+        //Cover ahb write/read during crypto write and debug mode unlocked
+        ahbXkv_write:       cross cp_ahb_write, cp_ahb_read, kv_write_en;
+        ahbXdebug:          cross cp_ahb_write, cp_ahb_read, debug; //TODO: maybe not a real use case - revisit
+        
+
+    endgroup
+
+
+    keyvault_top_cov_grp keyvault_top_cov_grp1 = new();
+    
+endinterface
+
+`endif
\ No newline at end of file
diff --git a/src/keyvault/coverage/keyvault_cov_props.sv b/src/keyvault/coverage/keyvault_cov_props.sv
new file mode 100644
index 000000000..f1ea9b9b7
--- /dev/null
+++ b/src/keyvault/coverage/keyvault_cov_props.sv
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: Apache-2.0
+// Copyright 2019 Western Digital Corporation or its affiliates.
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+
+// This file contains properties that define various sequences of events in KV
+
+module keyvault_cov_props
+    import kv_defines_pkg::*;
+    ();
+
+    `ifndef VERILATOR
+    
+    //clear_secrets followed by warm reset in the next clk
+    //Expectation: Keys cleared before warm reset
+    property cover_prop_clear_secr_warm_rst;
+        @(posedge dut.clk)
+        (dut.kv_reg_hwif_out.CLEAR_SECRETS.wr_debug_values |-> ##[1:$] !dut.rst_b);
+    endproperty
+    covprop_clear_secr_warmrst: cover property(cover_prop_clear_secr_warm_rst);
+
+    generate
+        for(genvar i = 0; i < KV_NUM_KEYS; i++) begin
+
+            //lock write => clear secrets => warm reset in next clk
+            //Expectation: Keys will be flushed since reset is not seen until next clk, locks are reset    
+            property cover_prop_locks_clear_secr_warm_rst;
+                @(posedge dut.clk)
+                (dut.kv_reg_hwif_out.KEY_CTRL[i].lock_wr && dut.kv_reg_hwif_out.CLEAR_SECRETS.wr_debug_values |-> ##[1:$] !dut.rst_b);
+            endproperty
+            covprop_lock_clear_secr_warmrst: cover property(cover_prop_locks_clear_secr_warm_rst);
+
+            //lock write => clear secrets => cold reset in next clk
+            //Expectation: Keys will be flushed since reset is not seen until next clk, locks and keys are reset once cold reset happens
+            property cover_prop_locks_clear_secr_cold_rst;
+                @(posedge dut.clk)
+                (dut.kv_reg_hwif_out.KEY_CTRL[i].lock_wr && dut.kv_reg_hwif_out.CLEAR_SECRETS.wr_debug_values |-> ##[1:$] !dut.cptra_pwrgood);
+            endproperty
+            covprop_lock_clear_secr_coldrst: cover property(cover_prop_locks_clear_secr_cold_rst);
+        end
+    endgenerate
+
+    `endif
+
+endmodule
\ No newline at end of file
diff --git a/src/keyvault/rtl/kv.sv b/src/keyvault/rtl/kv.sv
index 541d8f7de..4188fde2f 100644
--- a/src/keyvault/rtl/kv.sv
+++ b/src/keyvault/rtl/kv.sv
@@ -29,7 +29,8 @@ module kv
     input logic rst_b,
     input logic core_only_rst_b,
     input logic cptra_pwrgood,
-
+    input logic fw_update_rst_window,
+    input logic cptra_in_debug_scan_mode,
     input logic debugUnlock_or_scan_mode_switch,
     
     //uC AHB Lite Interface
@@ -61,8 +62,6 @@ logic kv_reg_read_error, kv_reg_write_error;
 logic [AHB_ADDR_WIDTH-1:0] uc_req_addr;
 kv_uc_req_t uc_req;
 
-logic debug_locked_f;
-logic debug_unlocked;
 logic flush_keyvault;
 logic [31:0] debug_value;
 
@@ -72,10 +71,13 @@ logic [KV_NUM_KEYS-1:0] key_entry_ctrl_we;
 logic [KV_NUM_KEYS-1:0][KV_NUM_DWORDS-1:0][31:0] key_entry_next;
 logic [KV_NUM_KEYS-1:0][KV_NUM_READ-1:0] key_entry_dest_valid_next;
 logic [KV_NUM_KEYS-1:0][KV_ENTRY_SIZE_W-1:0] key_entry_last_dword_next;
-
+logic [KV_NUM_KEYS-1:0] lock_wr_q;
+logic [KV_NUM_KEYS-1:0] lock_use_q;
 kv_reg__in_t kv_reg_hwif_in;
 kv_reg__out_t kv_reg_hwif_out;
 
+logic [KV_NUM_KEYS-1:0] key_entry_clear;
+
 ahb_slv_sif #(
     .AHB_ADDR_WIDTH(AHB_ADDR_WIDTH),
     .AHB_DATA_WIDTH(AHB_DATA_WIDTH),
@@ -114,7 +116,8 @@ always_comb uc_req_error = kv_reg_read_error | kv_reg_write_error;
 always_comb uc_req_hold = '0;
 
 //Flush the keyvault with the debug value when FW pokes the register or we detect debug mode unlocking
-always_comb flush_keyvault = debugUnlock_or_scan_mode_switch | kv_reg_hwif_out.CLEAR_SECRETS.wr_debug_values.value;
+always_comb flush_keyvault = debugUnlock_or_scan_mode_switch | 
+                             (cptra_in_debug_scan_mode & kv_reg_hwif_out.CLEAR_SECRETS.wr_debug_values.value);
 //Pick between keyvault debug mode 0 or 1
 always_comb debug_value = kv_reg_hwif_out.CLEAR_SECRETS.sel_debug_value.value ? CLP_DEBUG_MODE_KV_1 : CLP_DEBUG_MODE_KV_0;
 
@@ -124,28 +127,52 @@ always_comb begin : keyvault_pcr_signing
     end 
 end
 
+//Generate clear signal for each key entry 
+//don't clear when writes are locked
+//hold the clear when writes are in progress
+generate
+    for (genvar g_entry = 0; g_entry < KV_NUM_KEYS; g_entry++) begin
+        always_ff@(posedge clk or negedge rst_b) begin
+            if(~rst_b) begin
+                key_entry_clear[g_entry] <= '0;
+            end
+            else begin
+                key_entry_clear[g_entry] <= (kv_reg_hwif_out.KEY_CTRL[g_entry].clear.value & ~lock_wr_q[g_entry] & ~lock_use_q[g_entry]) |
+                                            (key_entry_clear[g_entry] & key_entry_ctrl_we[g_entry]);
+            end
+        end
+    end
+endgenerate
+
 always_comb begin : keyvault_ctrl
     //keyvault control registers
     for (int entry = 0; entry < KV_NUM_KEYS; entry++) begin
-        //once lock is set, only reset can unset it
-        kv_reg_hwif_in.KEY_CTRL[entry].lock_wr.swwel = kv_reg_hwif_out.KEY_CTRL[entry].lock_wr.value;
-        kv_reg_hwif_in.KEY_CTRL[entry].lock_use.swwel = kv_reg_hwif_out.KEY_CTRL[entry].lock_use.value;
-        //clear dest valid and last dword
-        kv_reg_hwif_in.KEY_CTRL[entry].dest_valid.hwclr = kv_reg_hwif_out.KEY_CTRL[entry].clear.value & ~kv_reg_hwif_out.KEY_CTRL[entry].lock_wr.value & ~kv_reg_hwif_out.KEY_CTRL[entry].lock_use.value;
-        kv_reg_hwif_in.KEY_CTRL[entry].last_dword.hwclr = kv_reg_hwif_out.KEY_CTRL[entry].clear.value & ~kv_reg_hwif_out.KEY_CTRL[entry].lock_wr.value & ~kv_reg_hwif_out.KEY_CTRL[entry].lock_use.value;
         //init for AND-OR
         key_entry_ctrl_we[entry] = '0;
         key_entry_dest_valid_next[entry] = '0; 
         key_entry_last_dword_next[entry] = '0;
+
+        //Qualify lock signals as they are on fw upd reset and create RDC violations if allowed to reset asynchronously
+        lock_wr_q[entry] = kv_reg_hwif_out.KEY_CTRL[entry].lock_wr.value & ~fw_update_rst_window;
+        lock_use_q[entry] = kv_reg_hwif_out.KEY_CTRL[entry].lock_use.value & ~fw_update_rst_window;
+        
         for (int client = 0; client < KV_NUM_WRITE; client++) begin
-            key_entry_ctrl_we[entry] |= (kv_write[client].write_entry == entry) & kv_write[client].write_en; 
-            key_entry_dest_valid_next[entry] |= kv_write[client].write_en & (kv_write[client].write_entry == entry) ? kv_write[client].write_dest_valid : '0;
+            key_entry_ctrl_we[entry] |= (kv_write[client].write_entry == entry) & kv_write[client].write_en & 
+                                        ~lock_wr_q[entry] & ~lock_use_q[entry]; 
+            key_entry_dest_valid_next[entry] |= (kv_write[client].write_entry == entry) & kv_write[client].write_en ? kv_write[client].write_dest_valid : '0;
             //store the final offset on the last write cycle, we'll use that to signal last dword on reads
-            key_entry_last_dword_next[entry] |= kv_write[client].write_en & (kv_write[client].write_entry == entry) ? kv_write[client].write_offset : '0;
+            key_entry_last_dword_next[entry] |= (kv_write[client].write_entry == entry) & kv_write[client].write_en ? kv_write[client].write_offset : '0;
         end 
-        kv_reg_hwif_in.KEY_CTRL[entry].dest_valid.we = key_entry_ctrl_we[entry];
+        //once lock is set, only reset can unset it
+        kv_reg_hwif_in.KEY_CTRL[entry].lock_wr.swwel = lock_wr_q[entry];
+        kv_reg_hwif_in.KEY_CTRL[entry].lock_use.swwel = lock_use_q[entry];
+        //clear dest valid and last dword
+        kv_reg_hwif_in.KEY_CTRL[entry].dest_valid.hwclr = key_entry_clear[entry];
+        kv_reg_hwif_in.KEY_CTRL[entry].last_dword.hwclr = key_entry_clear[entry];
+
+        kv_reg_hwif_in.KEY_CTRL[entry].dest_valid.we = key_entry_ctrl_we[entry] & ~key_entry_clear[entry];
         kv_reg_hwif_in.KEY_CTRL[entry].dest_valid.next = key_entry_dest_valid_next[entry];
-        kv_reg_hwif_in.KEY_CTRL[entry].last_dword.we = key_entry_ctrl_we[entry];
+        kv_reg_hwif_in.KEY_CTRL[entry].last_dword.we = key_entry_ctrl_we[entry] & ~key_entry_clear[entry];
         kv_reg_hwif_in.KEY_CTRL[entry].last_dword.next = key_entry_last_dword_next[entry];
     end
 
@@ -161,15 +188,13 @@ always_comb begin : keyvault_ctrl
             for (int client = 0; client < KV_NUM_WRITE; client++) begin
                 key_entry_we[entry][dword] |= ((((kv_write[client].write_entry == entry) & (kv_write[client].write_offset == dword) & 
                                                 kv_write[client].write_en) | flush_keyvault) & 
-                                               ~kv_reg_hwif_out.KEY_CTRL[entry].lock_wr.value &
-                                               ~kv_reg_hwif_out.KEY_CTRL[entry].lock_use.value | debugUnlock_or_scan_mode_switch);
+                                              ((~lock_wr_q[entry] & ~lock_use_q[entry]) | debugUnlock_or_scan_mode_switch));
                 key_entry_next[entry][dword] |= flush_keyvault ? debug_value :
                                                 kv_write[client].write_en & (kv_write[client].write_entry == entry) ? kv_write[client].write_data : '0;
             end
-            kv_reg_hwif_in.KEY_ENTRY[entry][dword].data.we = key_entry_we[entry][dword];
+            kv_reg_hwif_in.KEY_ENTRY[entry][dword].data.we = key_entry_we[entry][dword] & ~key_entry_clear[entry];
             kv_reg_hwif_in.KEY_ENTRY[entry][dword].data.next = key_entry_next[entry][dword];
-            //don't clear when writes are locked
-            kv_reg_hwif_in.KEY_ENTRY[entry][dword].data.hwclr = kv_reg_hwif_out.KEY_CTRL[entry].clear.value & ~kv_reg_hwif_out.KEY_CTRL[entry].lock_wr.value & ~kv_reg_hwif_out.KEY_CTRL[entry].lock_use.value;
+            kv_reg_hwif_in.KEY_ENTRY[entry][dword].data.hwclr = key_entry_clear[entry];
         end
     end
 end
@@ -186,25 +211,24 @@ always_comb begin : keyvault_readmux
         for (int entry = 0; entry < KV_NUM_KEYS; entry++) begin
             for (int dword = 0; dword < KV_NUM_DWORDS; dword++) begin
                 kv_rd_resp[client].read_data |= (kv_read[client].read_entry == entry) & (kv_read[client].read_offset == dword) &
-                                                ~kv_reg_hwif_out.KEY_CTRL[entry].lock_use.value & kv_reg_hwif_out.KEY_CTRL[entry].dest_valid.value[client] ? 
+                                                ~lock_use_q[entry] & kv_reg_hwif_out.KEY_CTRL[entry].dest_valid.value[client] ? 
                                                  kv_reg_hwif_out.KEY_ENTRY[entry][dword].data.value : '0;
             end
         //signal last when reading the last dword
         kv_rd_resp[client].last |= (kv_read[client].read_entry == entry) & (kv_read[client].read_offset == kv_reg_hwif_out.KEY_CTRL[entry].last_dword);
         kv_rd_resp[client].error |= (kv_read[client].read_entry == entry) & 
-                                    (kv_reg_hwif_out.KEY_CTRL[entry].lock_use.value | ~kv_reg_hwif_out.KEY_CTRL[entry].dest_valid.value[client]);
+                                    (lock_use_q[entry] | ~kv_reg_hwif_out.KEY_CTRL[entry].dest_valid.value[client]);
         end
     end
 end
 
-//Write error when attempting to write to entry that is locked for writes
+//Write error when attempting to write to entry that is locked for writes, use, or is being cleared
 always_comb begin : keyvault_write_resp
     for (int client = 0 ; client < KV_NUM_WRITE; client++) begin
         kv_wr_resp[client].error = '0;
         for (int entry = 0; entry < KV_NUM_KEYS; entry++) begin
             kv_wr_resp[client].error |= (kv_write[client].write_entry == entry) & kv_write[client].write_en &
-                                        kv_reg_hwif_out.KEY_CTRL[entry].lock_wr.value &
-                                        kv_reg_hwif_out.KEY_CTRL[entry].lock_use.value;
+                                        (key_entry_clear[entry] | lock_wr_q[entry] | lock_use_q[entry]);
         end
     end
 end
diff --git a/src/keyvault/rtl/kv_fsm.sv b/src/keyvault/rtl/kv_fsm.sv
index 4cffedd11..d0c770834 100644
--- a/src/keyvault/rtl/kv_fsm.sv
+++ b/src/keyvault/rtl/kv_fsm.sv
@@ -25,6 +25,7 @@ module kv_fsm
 (
     input logic clk,
     input logic rst_b,
+    input logic zeroize,
 
     input logic start,
     input logic last,
@@ -37,6 +38,7 @@ module kv_fsm
     output logic [OFFSET_W-1:0] write_offset,
     output logic write_pad,
     output logic [31:0] pad_data,
+    output logic write_last,
 
     output logic ready,
 
@@ -95,6 +97,7 @@ always_comb arc_KV_LENGTH_KV_DONE = kv_fsm_ps == KV_LENGTH;
 always_comb arc_KV_DONE_KV_IDLE = '1;
 
 always_comb offset_rst = arc_KV_RW_KV_DONE | arc_KV_LENGTH_KV_DONE;
+always_comb write_last = arc_KV_RW_KV_DONE | arc_KV_LENGTH_KV_DONE;
 
 always_comb begin : kv_fsm_comb
     kv_fsm_ns = kv_fsm_ps;
@@ -154,6 +157,11 @@ always_ff @(posedge clk or negedge rst_b) begin
         offset <= '0;
         num_dwords_data <= '0;
     end
+    else if (zeroize) begin
+        kv_fsm_ps <= KV_IDLE;
+        offset <= '0;
+        num_dwords_data <= '0;
+    end
     else begin
         kv_fsm_ps <= kv_fsm_ns;
         offset <= offset_rst ? '0 :
diff --git a/src/keyvault/rtl/kv_read_client.sv b/src/keyvault/rtl/kv_read_client.sv
index 810d394a0..a556604b1 100644
--- a/src/keyvault/rtl/kv_read_client.sv
+++ b/src/keyvault/rtl/kv_read_client.sv
@@ -26,6 +26,7 @@ module kv_read_client
 (
     input logic clk,
     input logic rst_b,
+    input logic zeroize,
 
     //client control register
     input kv_read_ctrl_reg_t read_ctrl_reg,
@@ -58,6 +59,7 @@ kv_read_fsm
 (
     .clk(clk),
     .rst_b(rst_b),
+    .zeroize(zeroize),
     .start(read_ctrl_reg.read_en),
     .last (kv_resp.last),
     .pcr_hash_extend(read_ctrl_reg.pcr_hash_extend),
@@ -65,6 +67,7 @@ kv_read_fsm
     .write_en(write_en),
     .write_offset(write_offset),
     .write_pad(write_pad),
+    .write_last(),
     .pad_data(pad_data),
     .ready(kv_ready),
     .done(read_done)
@@ -79,6 +82,9 @@ always_ff @(posedge clk or negedge rst_b) begin
     if (!rst_b) begin
         error_code <= KV_SUCCESS;
     end
+    else if (zeroize) begin
+        error_code <= KV_SUCCESS;
+    end
     else begin
         error_code <= read_ctrl_reg.read_en & kv_resp.error ? KV_READ_FAIL : 
                       read_ctrl_reg.read_en & ~kv_resp.error ? KV_SUCCESS : error_code;
diff --git a/src/keyvault/rtl/kv_reg.rdl b/src/keyvault/rtl/kv_reg.rdl
index 330d9a20b..ee721eb61 100644
--- a/src/keyvault/rtl/kv_reg.rdl
+++ b/src/keyvault/rtl/kv_reg.rdl
@@ -26,9 +26,9 @@ addrmap kv_reg {
     reg kvCtrl {
        desc="Controls for each keyvault and pcr entry";
        field {desc="Lock writes to this entry. Writes will be suppressed and an error will be recorded.";
-              sw=rw; swwel=true; hw=r; resetsignal=core_only_rst_b;} lock_wr=0; //warm reset
+              sw=rw; swwel=true; hw=r; resetsignal=core_only_rst_b;} lock_wr=0; //fw upd reset
        field {desc="Lock use of this entry. Reads will be suppressed and an error will be recorded.";
-              sw=rw; swwel=true; hw=r; resetsignal=core_only_rst_b;} lock_use=0; //warm reset
+              sw=rw; swwel=true; hw=r; resetsignal=core_only_rst_b;} lock_use=0; //fw upd reset
        field {desc="Clear the data stored in this entry. Lock write will prevent this clear.";
               sw=rw; hw=r; singlepulse;} clear=0;
        field {desc="Reserved";
diff --git a/src/keyvault/rtl/kv_reg_covergroups.svh b/src/keyvault/rtl/kv_reg_covergroups.svh
new file mode 100644
index 000000000..a05ec2fe6
--- /dev/null
+++ b/src/keyvault/rtl/kv_reg_covergroups.svh
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+`ifndef KV_REG_COVERGROUPS
+    `define KV_REG_COVERGROUPS
+    
+    /*----------------------- KV_REG__KVCTRL COVERGROUPS -----------------------*/
+    covergroup kv_reg__kvCtrl_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup kv_reg__kvCtrl_fld_cg with function sample(
+    input bit [1-1:0] lock_wr,
+    input bit [1-1:0] lock_use,
+    input bit [1-1:0] clear,
+    input bit [1-1:0] rsvd0,
+    input bit [5-1:0] rsvd1,
+    input bit [8-1:0] dest_valid,
+    input bit [4-1:0] last_dword
+    );
+        option.per_instance = 1;
+        lock_wr_cp : coverpoint lock_wr;
+        lock_use_cp : coverpoint lock_use;
+        clear_cp : coverpoint clear;
+        // rsvd0_cp : coverpoint rsvd0;
+        // rsvd1_cp : coverpoint rsvd1;
+        dest_valid_cp : coverpoint dest_valid {
+            illegal_bins dest_valid_bit5to7 = {['d32:'d255]};
+        }
+        last_dword_cp : coverpoint last_dword {
+            illegal_bins last_dword_12to15 = {['d12:'d15]};
+        }
+        wrXuseXclear: cross lock_wr_cp, lock_use_cp, clear_cp;
+
+    endgroup
+
+    /*----------------------- KV_REG__KEYREG COVERGROUPS -----------------------*/
+    covergroup kv_reg__keyReg_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup kv_reg__keyReg_fld_cg with function sample(
+    input bit [32-1:0] data
+    );
+        option.per_instance = 1;
+        data_cp : coverpoint data;
+
+    endgroup
+
+    /*----------------------- KV_REG__CLEAR_SECRETS COVERGROUPS -----------------------*/
+    covergroup kv_reg__CLEAR_SECRETS_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup kv_reg__CLEAR_SECRETS_fld_cg with function sample(
+    input bit [1-1:0] wr_debug_values,
+    input bit [1-1:0] sel_debug_value
+    );
+        option.per_instance = 1;
+        wr_debug_values_cp : coverpoint wr_debug_values;
+        sel_debug_value_cp : coverpoint sel_debug_value;
+
+    endgroup
+
+`endif
\ No newline at end of file
diff --git a/src/keyvault/rtl/kv_reg_sample.svh b/src/keyvault/rtl/kv_reg_sample.svh
new file mode 100644
index 000000000..1ab285ca2
--- /dev/null
+++ b/src/keyvault/rtl/kv_reg_sample.svh
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+`ifndef KV_REG_SAMPLE
+    `define KV_REG_SAMPLE
+    
+    /*----------------------- KV_REG__KVCTRL SAMPLE FUNCTIONS -----------------------*/
+    function void kv_reg__kvCtrl::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(lock_wr_bit_cg[bt]) this.lock_wr_bit_cg[bt].sample(data[0 + bt]);
+            foreach(lock_use_bit_cg[bt]) this.lock_use_bit_cg[bt].sample(data[1 + bt]);
+            foreach(clear_bit_cg[bt]) this.clear_bit_cg[bt].sample(data[2 + bt]);
+            foreach(rsvd0_bit_cg[bt]) this.rsvd0_bit_cg[bt].sample(data[3 + bt]);
+            foreach(rsvd1_bit_cg[bt]) this.rsvd1_bit_cg[bt].sample(data[4 + bt]);
+            foreach(dest_valid_bit_cg[bt]) this.dest_valid_bit_cg[bt].sample(data[9 + bt]);
+            foreach(last_dword_bit_cg[bt]) this.last_dword_bit_cg[bt].sample(data[17 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*lock_wr*/  ,  data[1:1]/*lock_use*/  ,  data[2:2]/*clear*/  ,  data[3:3]/*rsvd0*/  ,  data[8:4]/*rsvd1*/  ,  data[16:9]/*dest_valid*/  ,  data[20:17]/*last_dword*/   );
+        end
+    endfunction
+
+    function void kv_reg__kvCtrl::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(lock_wr_bit_cg[bt]) this.lock_wr_bit_cg[bt].sample(lock_wr.get_mirrored_value() >> bt);
+            foreach(lock_use_bit_cg[bt]) this.lock_use_bit_cg[bt].sample(lock_use.get_mirrored_value() >> bt);
+            foreach(clear_bit_cg[bt]) this.clear_bit_cg[bt].sample(clear.get_mirrored_value() >> bt);
+            foreach(rsvd0_bit_cg[bt]) this.rsvd0_bit_cg[bt].sample(rsvd0.get_mirrored_value() >> bt);
+            foreach(rsvd1_bit_cg[bt]) this.rsvd1_bit_cg[bt].sample(rsvd1.get_mirrored_value() >> bt);
+            foreach(dest_valid_bit_cg[bt]) this.dest_valid_bit_cg[bt].sample(dest_valid.get_mirrored_value() >> bt);
+            foreach(last_dword_bit_cg[bt]) this.last_dword_bit_cg[bt].sample(last_dword.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( lock_wr.get_mirrored_value()  ,  lock_use.get_mirrored_value()  ,  clear.get_mirrored_value()  ,  rsvd0.get_mirrored_value()  ,  rsvd1.get_mirrored_value()  ,  dest_valid.get_mirrored_value()  ,  last_dword.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- KV_REG__KEYREG SAMPLE FUNCTIONS -----------------------*/
+    function void kv_reg__keyReg::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(data_bit_cg[bt]) this.data_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*data*/   );
+        end
+    endfunction
+
+    function void kv_reg__keyReg::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(data_bit_cg[bt]) this.data_bit_cg[bt].sample(data.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- KV_REG__CLEAR_SECRETS SAMPLE FUNCTIONS -----------------------*/
+    function void kv_reg__CLEAR_SECRETS::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(wr_debug_values_bit_cg[bt]) this.wr_debug_values_bit_cg[bt].sample(data[0 + bt]);
+            foreach(sel_debug_value_bit_cg[bt]) this.sel_debug_value_bit_cg[bt].sample(data[1 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*wr_debug_values*/  ,  data[1:1]/*sel_debug_value*/   );
+        end
+    endfunction
+
+    function void kv_reg__CLEAR_SECRETS::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(wr_debug_values_bit_cg[bt]) this.wr_debug_values_bit_cg[bt].sample(wr_debug_values.get_mirrored_value() >> bt);
+            foreach(sel_debug_value_bit_cg[bt]) this.sel_debug_value_bit_cg[bt].sample(sel_debug_value.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( wr_debug_values.get_mirrored_value()  ,  sel_debug_value.get_mirrored_value()   );
+        end
+    endfunction
+
+`endif
\ No newline at end of file
diff --git a/src/keyvault/rtl/kv_reg_uvm.sv b/src/keyvault/rtl/kv_reg_uvm.sv
index 2d4b86f00..39166e179 100644
--- a/src/keyvault/rtl/kv_reg_uvm.sv
+++ b/src/keyvault/rtl/kv_reg_uvm.sv
@@ -3,9 +3,21 @@
 package kv_reg_uvm;
     `include "uvm_macros.svh"
     import uvm_pkg::*;
-    
+    `include "kv_reg_covergroups.svh"
     // Reg - kv_reg::kvCtrl
     class kv_reg__kvCtrl extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        kv_reg__kvCtrl_bit_cg lock_wr_bit_cg[1];
+        kv_reg__kvCtrl_bit_cg lock_use_bit_cg[1];
+        kv_reg__kvCtrl_bit_cg clear_bit_cg[1];
+        kv_reg__kvCtrl_bit_cg rsvd0_bit_cg[1];
+        kv_reg__kvCtrl_bit_cg rsvd1_bit_cg[5];
+        kv_reg__kvCtrl_bit_cg dest_valid_bit_cg[8];
+        kv_reg__kvCtrl_bit_cg last_dword_bit_cg[4];
+        kv_reg__kvCtrl_fld_cg fld_cg;
         rand uvm_reg_field lock_wr;
         rand uvm_reg_field lock_use;
         rand uvm_reg_field clear;
@@ -15,8 +27,13 @@ package kv_reg_uvm;
         rand uvm_reg_field last_dword;
 
         function new(string name = "kv_reg__kvCtrl");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.lock_wr = new("lock_wr");
@@ -33,37 +50,82 @@ package kv_reg_uvm;
             this.dest_valid.configure(this, 8, 9, "RO", 1, 'h0, 1, 1, 0);
             this.last_dword = new("last_dword");
             this.last_dword.configure(this, 4, 17, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(lock_wr_bit_cg[bt]) lock_wr_bit_cg[bt] = new();
+                foreach(lock_use_bit_cg[bt]) lock_use_bit_cg[bt] = new();
+                foreach(clear_bit_cg[bt]) clear_bit_cg[bt] = new();
+                foreach(rsvd0_bit_cg[bt]) rsvd0_bit_cg[bt] = new();
+                foreach(rsvd1_bit_cg[bt]) rsvd1_bit_cg[bt] = new();
+                foreach(dest_valid_bit_cg[bt]) dest_valid_bit_cg[bt] = new();
+                foreach(last_dword_bit_cg[bt]) last_dword_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : kv_reg__kvCtrl
 
     // Reg - kv_reg::keyReg
     class kv_reg__keyReg extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        kv_reg__keyReg_bit_cg data_bit_cg[32];
+        kv_reg__keyReg_fld_cg fld_cg;
         rand uvm_reg_field data;
 
         function new(string name = "kv_reg__keyReg");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.data = new("data");
             this.data.configure(this, 32, 0, "WO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(data_bit_cg[bt]) data_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : kv_reg__keyReg
 
     // Reg - kv_reg::CLEAR_SECRETS
     class kv_reg__CLEAR_SECRETS extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        kv_reg__CLEAR_SECRETS_bit_cg wr_debug_values_bit_cg[1];
+        kv_reg__CLEAR_SECRETS_bit_cg sel_debug_value_bit_cg[1];
+        kv_reg__CLEAR_SECRETS_fld_cg fld_cg;
         rand uvm_reg_field wr_debug_values;
         rand uvm_reg_field sel_debug_value;
 
         function new(string name = "kv_reg__CLEAR_SECRETS");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.wr_debug_values = new("wr_debug_values");
             this.wr_debug_values.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
             this.sel_debug_value = new("sel_debug_value");
             this.sel_debug_value.configure(this, 1, 1, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(wr_debug_values_bit_cg[bt]) wr_debug_values_bit_cg[bt] = new();
+                foreach(sel_debug_value_bit_cg[bt]) sel_debug_value_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : kv_reg__CLEAR_SECRETS
 
@@ -101,4 +163,5 @@ package kv_reg_uvm;
         endfunction : build
     endclass : kv_reg
 
+    `include "kv_reg_sample.svh"
 endpackage: kv_reg_uvm
diff --git a/src/keyvault/rtl/kv_write_client.sv b/src/keyvault/rtl/kv_write_client.sv
index 2211cd1a7..f8a2ca670 100644
--- a/src/keyvault/rtl/kv_write_client.sv
+++ b/src/keyvault/rtl/kv_write_client.sv
@@ -26,6 +26,7 @@ module kv_write_client
 (
     input logic clk,
     input logic rst_b,
+    input logic zeroize,
 
     //client control register
     input kv_write_ctrl_reg_t write_ctrl_reg,
@@ -49,6 +50,7 @@ logic [DATA_OFFSET_W-1:0] dest_write_offset;
 logic dest_write_en;
 logic [31:0] pad_data;
 logic write_pad;
+logic write_last;
 
 //dest write block
 kv_fsm #(
@@ -59,6 +61,7 @@ kv_dest_write_fsm
 (
     .clk(clk),
     .rst_b(rst_b),
+    .zeroize(zeroize),
     .start(dest_data_avail & write_ctrl_reg.write_en),
     .last('0),
     .pcr_hash_extend(1'b0),
@@ -66,6 +69,7 @@ kv_dest_write_fsm
     .write_en(dest_write_en),
     .write_offset(dest_write_offset),
     .write_pad(write_pad),
+    .write_last(write_last),
     .pad_data(pad_data),
     .ready(kv_ready),
     .done(dest_done)
@@ -77,13 +81,16 @@ always_comb kv_write.write_entry = write_ctrl_reg.write_entry;
 always_comb kv_write.write_offset = dest_write_offset;
 always_comb kv_write.write_en = dest_write_en;
 always_comb kv_write.write_data = dest_data[(DATA_NUM_DWORDS-1) - dest_read_offset];
-
-always_comb kv_write.write_dest_valid = write_ctrl_reg.write_dest_vld;
+//write zeroes here until last cycle
+always_comb kv_write.write_dest_valid = write_last ? write_ctrl_reg.write_dest_vld : '0;
 
 always_ff @(posedge clk or negedge rst_b) begin
     if (!rst_b) begin
         error_code <= KV_SUCCESS;
     end
+    else if (zeroize) begin
+        error_code <= KV_SUCCESS;
+    end
     else begin
         error_code <= dest_write_en & kv_resp.error ? KV_WRITE_FAIL : 
                       dest_write_en & ~kv_resp.error ? KV_SUCCESS : error_code;
diff --git a/src/keyvault/uvmf_kv/config/compile.yml b/src/keyvault/uvmf_kv/config/compile.yml
index 820820338..56dca109a 100644
--- a/src/keyvault/uvmf_kv/config/compile.yml
+++ b/src/keyvault/uvmf_kv/config/compile.yml
@@ -6,6 +6,7 @@ requires:
   - kv_uvm_pkg
   - keyvault
   - caliptra_top_defines
+  - keyvault_cov
 targets:
   tb:
     directories:
diff --git a/src/keyvault/uvmf_kv/coverage/uvmf_kv_cm_hier.cfg b/src/keyvault/uvmf_kv/coverage/uvmf_kv_cm_hier.cfg
new file mode 100644
index 000000000..f8b1e528f
--- /dev/null
+++ b/src/keyvault/uvmf_kv/coverage/uvmf_kv_cm_hier.cfg
@@ -0,0 +1,4 @@
+begin line+tgl+fsm+cond+branch
+    +tree hdl_top.dut 0
+end
+
diff --git a/src/keyvault/uvmf_kv/kv_interfaces.yaml b/src/keyvault/uvmf_kv/kv_interfaces.yaml
index e86ace813..49130c75c 100644
--- a/src/keyvault/uvmf_kv/kv_interfaces.yaml
+++ b/src/keyvault/uvmf_kv/kv_interfaces.yaml
@@ -28,6 +28,9 @@ uvmf:
       - name: debug_locked
         dir: output
         width: '1'
+      - name: cptra_in_debug_scan_mode
+        dir: output
+        width: '1'
 
       transaction_constraints:
       - name: wait_cycles_c
@@ -54,6 +57,10 @@ uvmf:
         type: bit
         iscompare: 'False'
         isrand: 'False'
+      - name: scan_mode
+        type: bit
+        iscompare: 'False'
+        isrand: 'False'
 
     #################### WRITE ####################
     kv_write:
diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/sequences/src/kv_rand_debug_test_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/sequences/src/kv_rand_debug_test_sequence.svh
index 9f09815a9..15d6b3fbf 100644
--- a/src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/sequences/src/kv_rand_debug_test_sequence.svh
+++ b/src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/sequences/src/kv_rand_debug_test_sequence.svh
@@ -68,6 +68,9 @@ class kv_rand_debug_test_sequence extends kv_bench_sequence_base;
     typedef kv_wr_rd_debug_lock_sequence #(.CONFIG_T(kv_env_configuration_t)) kv_wr_rd_debug_lock_sequence_t;
     rand kv_wr_rd_debug_lock_sequence_t kv_wr_rd_debug_lock_seq;
 
+    typedef kv_wr_rd_debug_lock_clear_rst_sequence #(.CONFIG_T(kv_env_configuration_t)) kv_wr_rd_debug_lock_clear_rst_sequence_t;
+    rand kv_wr_rd_debug_lock_clear_rst_sequence_t kv_wr_rd_debug_lock_clear_rst_seq;
+
     typedef kv_wr_rd_debug_warm_rst_sequence #(.CONFIG_T(kv_env_configuration_t)) kv_wr_rd_debug_warm_rst_sequence_t;
     rand kv_wr_rd_debug_warm_rst_sequence_t kv_wr_rd_debug_warm_rst_seq;
 
@@ -97,6 +100,7 @@ class kv_rand_debug_test_sequence extends kv_bench_sequence_base;
         kv_wr_rd_lock_core_rst_seq = kv_wr_rd_lock_core_rst_sequence_t::type_id::create("kv_wr_rd_lock_core_rst_seq");
         kv_wr_rd_debug_seq = kv_wr_rd_debug_sequence_t::type_id::create("kv_wr_rd_debug_seq");
         kv_wr_rd_debug_lock_seq = kv_wr_rd_debug_lock_sequence_t::type_id::create("kv_wr_rd_debug_lock_seq");
+        kv_wr_rd_debug_lock_clear_rst_seq = kv_wr_rd_debug_lock_clear_rst_sequence_t::type_id::create("kv_wr_rd_debug_lock_clear_rst_seq");
         kv_wr_rd_debug_warm_rst_seq = kv_wr_rd_debug_warm_rst_sequence_t::type_id::create("kv_wr_rd_debug_warm_rst_seq");
         kv_wr_rd_debug_cold_rst_seq = kv_wr_rd_debug_cold_rst_sequence_t::type_id::create("kv_wr_rd_debug_cold_rst_seq");
         kv_wr_rd_debug_core_rst_seq = kv_wr_rd_debug_core_rst_sequence_t::type_id::create("kv_wr_rd_debug_core_rst_seq");
@@ -124,6 +128,9 @@ class kv_rand_debug_test_sequence extends kv_bench_sequence_base;
         kv_wr_rd_debug_cold_rst_seq.start(top_configuration.vsqr);
         `uvm_info("TOP", "DEBUG core rst sequence",UVM_MEDIUM);
         kv_wr_rd_debug_core_rst_seq.start(top_configuration.vsqr);
+
+        `uvm_info("TOP", "DEBUG lock clear rst sequence",UVM_MEDIUM);
+        kv_wr_rd_debug_lock_clear_rst_seq.start(top_configuration.vsqr);
         
 
         if(1) $display("** TESTCASE PASSED");
diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/sequences/src/kv_rand_wr_rd_test_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/sequences/src/kv_rand_wr_rd_test_sequence.svh
index c7c7f5636..897bce4e1 100644
--- a/src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/sequences/src/kv_rand_wr_rd_test_sequence.svh
+++ b/src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/sequences/src/kv_rand_wr_rd_test_sequence.svh
@@ -77,6 +77,9 @@ class kv_rand_wr_rd_test_sequence extends kv_bench_sequence_base;
     typedef kv_wr_rd_debug_core_rst_sequence #(.CONFIG_T(kv_env_configuration_t)) kv_wr_rd_debug_core_rst_sequence_t;
     rand kv_wr_rd_debug_core_rst_sequence_t kv_wr_rd_debug_core_rst_seq;
 
+    typedef kv_ahb_sequence #(.CONFIG_T(kv_env_configuration_t)) kv_ahb_sequence_t;
+    rand kv_ahb_sequence_t kv_ahb_seq;
+
     //Responder sequences:
     typedef kv_read_responder_sequence kv_hmac_key_read_agent_responder_seq_t;
     kv_hmac_key_read_agent_responder_seq_t kv_hmac_key_read_agent_responder_seq;
@@ -100,6 +103,7 @@ class kv_rand_wr_rd_test_sequence extends kv_bench_sequence_base;
         kv_wr_rd_debug_warm_rst_seq = kv_wr_rd_debug_warm_rst_sequence_t::type_id::create("kv_wr_rd_debug_warm_rst_seq");
         kv_wr_rd_debug_cold_rst_seq = kv_wr_rd_debug_cold_rst_sequence_t::type_id::create("kv_wr_rd_debug_cold_rst_seq");
         kv_wr_rd_debug_core_rst_seq = kv_wr_rd_debug_core_rst_sequence_t::type_id::create("kv_wr_rd_debug_core_rst_seq");
+        kv_ahb_seq = kv_ahb_sequence_t::type_id::create("kv_ahb_seq");
 
         if(!kv_wr_rd_seq.randomize())
             `uvm_fatal("KV WR RD SEQ", "kv_rand_wr_rd_test_sequence::body() - kv_wr_rd_seq randomization failed");
@@ -111,6 +115,8 @@ class kv_rand_wr_rd_test_sequence extends kv_bench_sequence_base;
             `uvm_fatal("KV WR RD COLD RST SEQ", "kv_rand_wr_rd_test_sequence::body() - kv_wr_rd_cold_rst_seq randomization failed");
         if(!kv_wr_rd_lock_seq.randomize())
             `uvm_fatal("KV_WR_RD_LOCK_SEQ", "kv_rand_wr_rd_test_sequence::body() - kv_wr_rd_lock_seq randomization failed");
+        if(!kv_ahb_seq.randomize())
+            `uvm_fatal("KV_AHB_SEQ", "kv_ahb_sequence::body() - kv_ahb_seq randomization failed");
 
         reg_model.reset();
         
@@ -123,6 +129,8 @@ class kv_rand_wr_rd_test_sequence extends kv_bench_sequence_base;
         kv_wr_rd_rst_seq.start(top_configuration.vsqr);
         `uvm_info("TOP", "wr rd cold rst sequence",UVM_MEDIUM);
         kv_wr_rd_cold_rst_seq.start(top_configuration.vsqr);
+        `uvm_info("TOP", "AHB sequence", UVM_MEDIUM);
+        kv_ahb_seq.start(top_configuration.vsqr);
         
 
         if(1) $display("** TESTCASE PASSED");
diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/testbench/hdl_top.sv b/src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/testbench/hdl_top.sv
index aa8a24f97..7fdc017ce 100644
--- a/src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/testbench/hdl_top.sv
+++ b/src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/testbench/hdl_top.sv
@@ -203,7 +203,7 @@ import uvmf_base_pkg_hdl::*;
       .rst_b            (kv_rst_agent_bus.rst_b        ),
       .core_only_rst_b  (kv_rst_agent_bus.core_only_rst_b),
       .cptra_pwrgood    (kv_rst_agent_bus.cptra_pwrgood),
-
+      .cptra_in_debug_scan_mode        (kv_rst_agent_bus.cptra_in_debug_scan_mode),
       .debugUnlock_or_scan_mode_switch (kv_rst_agent_bus.debug_locked),
 
       //uC AHB Lite Interface
@@ -219,13 +219,16 @@ import uvmf_base_pkg_hdl::*;
       .hresp_o    (uvm_test_top_environment_qvip_ahb_lite_slave_subenv_qvip_hdl.ahb_lite_slave_0_HRESP      ),
       .hreadyout_o(uvm_test_top_environment_qvip_ahb_lite_slave_subenv_qvip_hdl.ahb_lite_slave_0_HREADY     ),
       .hrdata_o   (uvm_test_top_environment_qvip_ahb_lite_slave_subenv_qvip_hdl.ahb_lite_slave_0_HRDATA     ),
-
+      .fw_update_rst_window(kv_rst_agent_bus.fw_update_rst_window),
       .kv_read (kv_read ),
       .kv_write(kv_write),
       .kv_rd_resp(kv_rd_resp),
       .kv_wr_resp(kv_wr_resp),
       .pcr_signing_key() //TODO
   );
+
+  keyvault_cov_bind i_keyvault_cov_bind();
+
     assign uvm_test_top_environment_qvip_ahb_lite_slave_subenv_qvip_hdl.ahb_lite_slave_0_HBURST    = 3'b0;
     assign uvm_test_top_environment_qvip_ahb_lite_slave_subenv_qvip_hdl.ahb_lite_slave_0_HPROT     = 7'b0;
     assign uvm_test_top_environment_qvip_ahb_lite_slave_subenv_qvip_hdl.ahb_lite_slave_0_HMASTLOCK = 1'b0;
@@ -268,6 +271,8 @@ import uvmf_base_pkg_hdl::*;
     uvm_config_db #( virtual kv_read_driver_bfm  )::set( null , UVMF_VIRTUAL_INTERFACES , kv_ecc_seed_read_agent_BFM , kv_ecc_seed_read_agent_drv_bfm  );
   end
 
+  
+
 endmodule
 
 // pragma uvmf custom external begin
diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/kv_env_pkg.sv b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/kv_env_pkg.sv
index 4fb6c72f0..afa6d0c14 100644
--- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/kv_env_pkg.sv
+++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/kv_env_pkg.sv
@@ -117,9 +117,11 @@ package kv_env_pkg;
   `include "src/kv_wr_rd_lock_core_rst_sequence.svh"
   `include "src/kv_wr_rd_debug_sequence.svh"
   `include "src/kv_wr_rd_debug_lock_sequence.svh"
+  `include "src/kv_wr_rd_debug_lock_clear_rst_sequence.svh"
   `include "src/kv_wr_rd_debug_warm_rst_sequence.svh"
   `include "src/kv_wr_rd_debug_cold_rst_sequence.svh"
   `include "src/kv_wr_rd_debug_core_rst_sequence.svh"
+  `include "src/kv_ahb_sequence.svh"
 
   // pragma uvmf custom package_item_additional begin
   // UVMF_CHANGE_ME : When adding new environment level sequences to the src directory
diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/registers/kv_reg_model_top_pkg.sv b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/registers/kv_reg_model_top_pkg.sv
index 7fb4613b5..0132574a6 100644
--- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/registers/kv_reg_model_top_pkg.sv
+++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/registers/kv_reg_model_top_pkg.sv
@@ -169,11 +169,12 @@ package kv_reg_model_top_pkg;
 
       rand uvm_reg_field debug_mode_unlocked;
       rand uvm_reg_field clear_secrets_bit;
+      rand uvm_reg_field cptra_in_debug_scan_mode;
 
       // Function: new
       // 
       function new(string name = "kv_val_reg");
-         super.new(name, 2, UVM_NO_COVERAGE);
+         super.new(name, 3, UVM_NO_COVERAGE);
       endfunction
 
 
@@ -185,6 +186,10 @@ package kv_reg_model_top_pkg;
 
          clear_secrets_bit = uvm_reg_field::type_id::create("clear_secrets_bit");
          clear_secrets_bit.configure(this, 1, 1, "RW", 0, 1'b0, 1, 1, 1);
+
+         cptra_in_debug_scan_mode = uvm_reg_field::type_id::create("cptra_in_debug_scan_mode");
+         cptra_in_debug_scan_mode.configure(this, 1, 2, "RW", 0, 1'b0, 1, 1, 1);
+
       endfunction
    endclass
 
@@ -213,6 +218,26 @@ package kv_reg_model_top_pkg;
          clear.configure(this, 32, 0, "RW", 0, 32'b0, 1, 1, 1);
       endfunction
    endclass
+
+   class kv_val_ctrl_derived extends uvm_reg;
+      `uvm_object_utils(kv_val_ctrl_derived)
+
+      rand uvm_reg_field clear_derived; //32 bits, one for each KEY_CTRL
+
+      // Function: new
+      // 
+      function new(string name = "kv_val_ctrl_derived");
+         super.new(name, 32, UVM_NO_COVERAGE);
+      endfunction
+
+
+      // Function: build
+      // 
+      virtual function void build();
+         clear_derived = uvm_reg_field::type_id::create("clear_derived");
+         clear_derived.configure(this, 32, 0, "RW", 0, 32'b0, 1, 1, 1);
+      endfunction
+   endclass
 // pragma uvmf custom define_register_classes end
 
 // pragma uvmf custom define_block_map_coverage_class begin
@@ -221,37 +246,37 @@ package kv_reg_model_top_pkg;
    // 
    // Coverage for the 'ahb_map' in 'kv_reg_model'
    //--------------------------------------------------------------------
-   class kv_ahb_map_coverage extends uvm_object;
-      `uvm_object_utils(kv_ahb_map_coverage)
+   // class kv_ahb_map_coverage extends uvm_object;
+   //    `uvm_object_utils(kv_ahb_map_coverage)
 
-      covergroup ra_cov(string name) with function sample(uvm_reg_addr_t addr, bit is_read);
+   //    covergroup ra_cov(string name) with function sample(uvm_reg_addr_t addr, bit is_read);
 
-         option.per_instance = 1;
-         option.name = name; 
+   //       option.per_instance = 1;
+   //       option.name = name; 
 
-         ADDR: coverpoint addr {
-            bins example_reg0 = {'h0};
-            bins example_reg1 = {'h1};
-         }
+   //       ADDR: coverpoint addr {
+   //          bins example_reg0 = {'h0};
+   //          bins example_reg1 = {'h1};
+   //       }
 
-         RW: coverpoint is_read {
-            bins RD = {1};
-            bins WR = {0};
-         }
+   //       RW: coverpoint is_read {
+   //          bins RD = {1};
+   //          bins WR = {0};
+   //       }
 
-         ACCESS: cross ADDR, RW;
+   //       ACCESS: cross ADDR, RW;
 
-      endgroup: ra_cov
+   //    endgroup: ra_cov
 
-      function new(string name = "kv_ahb_map_coverage");
-         ra_cov = new(name);
-      endfunction: new
+   //    function new(string name = "kv_ahb_map_coverage");
+   //       ra_cov = new(name);
+   //    endfunction: new
 
-      function void sample(uvm_reg_addr_t offset, bit is_read);
-         ra_cov.sample(offset, is_read);
-      endfunction: sample
+   //    function void sample(uvm_reg_addr_t offset, bit is_read);
+   //       ra_cov.sample(offset, is_read);
+   //    endfunction: sample
 
-   endclass: kv_ahb_map_coverage
+   // endclass: kv_ahb_map_coverage
 // pragma uvmf custom define_block_map_coverage_class end
 
    //TODO: Add coverage classes for each of the maps
@@ -270,6 +295,7 @@ package kv_reg_model_top_pkg;
 
       rand kv_val_reg val_reg;
       rand kv_val_ctrl val_ctrl;
+      rand kv_val_ctrl_derived val_ctrl_derived;
 // pragma uvmf custom instantiate_registers_within_block end
       uvm_reg_map default_map;
 
@@ -291,7 +317,7 @@ package kv_reg_model_top_pkg;
       uvm_reg_map kv_ecc_seed_read_map;
 
       //TODO add coverage for the other maps
-      kv_ahb_map_coverage ahb_map_cg;
+      // kv_ahb_map_coverage ahb_map_cg;
 
       // Function: new
       // 
@@ -303,20 +329,20 @@ package kv_reg_model_top_pkg;
       // 
       virtual function void build();
       ahb_map = create_map("ahb_map", 0, 4, UVM_LITTLE_ENDIAN);
-      if(has_coverage(UVM_CVR_ADDR_MAP)) begin
-         ahb_map_cg = kv_ahb_map_coverage::type_id::create("ahb_map_cg");
-         ahb_map_cg.ra_cov.set_inst_name(this.get_full_name());
-         void'(set_coverage(UVM_CVR_ADDR_MAP));
-      end
+      // if(has_coverage(UVM_CVR_ADDR_MAP)) begin
+      //    ahb_map_cg = kv_ahb_map_coverage::type_id::create("ahb_map_cg");
+      //    ahb_map_cg.ra_cov.set_inst_name(this.get_full_name());
+      //    void'(set_coverage(UVM_CVR_ADDR_MAP));
+      // end
 
 
 // pragma uvmf custom construct_configure_build_registers_within_block begin
-      example_reg0 = kv_example_reg0::type_id::create("example_reg0");
-      example_reg0.configure(this, null, "example_reg0");
-      example_reg0.build();
-      example_reg1 = kv_example_reg1::type_id::create("example_reg1");
-      example_reg1.configure(this, null, "example_reg1");
-      example_reg1.build();
+      // example_reg0 = kv_example_reg0::type_id::create("example_reg0");
+      // example_reg0.configure(this, null, "example_reg0");
+      // example_reg0.build();
+      // example_reg1 = kv_example_reg1::type_id::create("example_reg1");
+      // example_reg1.configure(this, null, "example_reg1");
+      // example_reg1.build();
 
       val_reg = kv_val_reg::type_id::create("val_reg");
       val_reg.configure(this,null,"val_reg");
@@ -325,6 +351,10 @@ package kv_reg_model_top_pkg;
       val_ctrl = kv_val_ctrl::type_id::create("val_ctrl");
       val_ctrl.configure(this,null,"val_ctrl");
       val_ctrl.build();
+
+      val_ctrl_derived = kv_val_ctrl_derived::type_id::create("val_ctrl_derived");
+      val_ctrl_derived.configure(this,null,"val_ctrl_derived");
+      val_ctrl_derived.build();
 // pragma uvmf custom construct_configure_build_registers_within_block end
 // pragma uvmf custom add_registers_to_block_map begin
       //ahb_map.add_reg(example_reg0, 'h0, "RW");
@@ -358,6 +388,7 @@ package kv_reg_model_top_pkg;
       //Add debug_mode reg to all maps (only for TB purposes)
       default_map.add_reg(val_reg, 'h1_0000, "RW");
       default_map.add_reg(val_ctrl, 'h1_0004, "RW");
+      default_map.add_reg(val_ctrl_derived, 'h1_0008, "RW");
 
       kv_hmac_write_map.add_reg(val_reg, 'h1_0000, "RW");
       kv_sha512_write_map.add_reg(val_reg, 'h1_0000, "RW");
@@ -369,8 +400,14 @@ package kv_reg_model_top_pkg;
       kv_ecc_write_map.add_reg   (val_ctrl, 'h1_0004, "RW");
       kv_doe_write_map.add_reg   (val_ctrl, 'h1_0004, "RW");
 
+      kv_hmac_write_map.add_reg  (val_ctrl_derived, 'h1_0008, "RW");
+      kv_sha512_write_map.add_reg(val_ctrl_derived, 'h1_0008, "RW");
+      kv_ecc_write_map.add_reg   (val_ctrl_derived, 'h1_0008, "RW");
+      kv_doe_write_map.add_reg   (val_ctrl_derived, 'h1_0008, "RW");
+
       kv_AHB_map.add_reg(val_reg, 'h1_0000, "RW");
       kv_AHB_map.add_reg(val_ctrl, 'h1_0004, "RW");
+      kv_AHB_map.add_reg(val_ctrl_derived, 'h1_0008, "RW");
       
       kv_hmac_key_read_map.add_reg(val_reg, 'h1_0000, "RW");
       kv_hmac_block_read_map.add_reg(val_reg, 'h1_0000, "RW");
@@ -383,6 +420,12 @@ package kv_reg_model_top_pkg;
       kv_sha512_block_read_map.add_reg(val_ctrl, 'h1_0004, "RW");
       kv_ecc_privkey_read_map.add_reg (val_ctrl, 'h1_0004, "RW");
       kv_ecc_seed_read_map.add_reg    (val_ctrl, 'h1_0004, "RW");
+
+      kv_hmac_key_read_map.add_reg    (val_ctrl_derived, 'h1_0008, "RW");
+      kv_hmac_block_read_map.add_reg  (val_ctrl_derived, 'h1_0008, "RW");
+      kv_sha512_block_read_map.add_reg(val_ctrl_derived, 'h1_0008, "RW");
+      kv_ecc_privkey_read_map.add_reg (val_ctrl_derived, 'h1_0008, "RW");
+      kv_ecc_seed_read_map.add_reg    (val_ctrl_derived, 'h1_0008, "RW");
  
       endfunction
 
@@ -407,17 +450,19 @@ package kv_reg_model_top_pkg;
          this.kv_ecc_privkey_read_map.add_submap   (this.kv_reg_rm.kv_reg_ecc_privkey_read_map, 'h0);
          this.kv_ecc_seed_read_map.add_submap      (this.kv_reg_rm.kv_reg_ecc_seed_read_map, 'h0);
 
+         void'(set_coverage(get_coverage() | UVM_CVR_REG_BITS | UVM_CVR_FIELD_VALS));
+
       endfunction
 
       // Function: sample
       // 
-      function void sample(uvm_reg_addr_t offset, bit is_read, uvm_reg_map  map);
-         if(get_coverage(UVM_CVR_ADDR_MAP)) begin
-            if(map.get_name() == "ahb_map_cg") begin
-               ahb_map_cg.sample(offset, is_read);
-            end
-         end
-      endfunction: sample
+      // function void sample(uvm_reg_addr_t offset, bit is_read, uvm_reg_map  map);
+      //    if(get_coverage(UVM_CVR_ADDR_MAP)) begin
+      //       if(map.get_name() == "ahb_map_cg") begin
+      //          ahb_map_cg.sample(offset, is_read);
+      //       end
+      //    end
+      // endfunction: sample
 
    endclass
 
diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_ahb_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_ahb_sequence.svh
new file mode 100644
index 000000000..3867b3b62
--- /dev/null
+++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_ahb_sequence.svh
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Simple KV write/read sequence that writes random data
+// to all entries and all dwords in order and then reads from them in order
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+class kv_ahb_sequence #(
+    type CONFIG_T
+) extends kv_env_sequence_base #(.CONFIG_T(CONFIG_T));
+
+    `uvm_object_param_utils(kv_ahb_sequence #(CONFIG_T));
+
+    typedef kv_rst_poweron_sequence kv_rst_agent_poweron_sequence_t;
+    kv_rst_agent_poweron_sequence_t kv_rst_agent_poweron_seq;
+
+    rand int unsigned iter;
+
+    function new(string name = "");
+        super.new(name);
+        kv_rst_agent_poweron_seq = kv_rst_agent_poweron_sequence_t::type_id::create("kv_rst_agent_poweron_seq");
+        if(!this.randomize()) `uvm_error("KV AHB", "Failed to randomize KV RST poweron seq");
+    endfunction
+
+    virtual task body();
+        uvm_status_e sts;
+        int offset;
+        int entry;
+        int i;
+        reg [KV_DATA_W-1:0] wr_data, rd_data;
+        
+        reg_model = configuration.kv_rm;
+        // std::randomize(iter) with {
+        //    1 <= iter <= 5; 
+        // };
+        iter = 1;
+        //Issue reset
+        if(configuration.kv_rst_agent_config.sequencer != null)
+            kv_rst_agent_poweron_seq.start(configuration.kv_rst_agent_config.sequencer);
+        else
+            `uvm_error("KV AHB", "kv_rst_agent_config.sequencer is null!")
+        
+        //KEY ENTRY reg writes
+        for (i = 0; i < iter; i++) begin
+            for(entry = 0; entry < KV_NUM_KEYS; entry++) begin
+                for (offset = 0; offset < KV_NUM_DWORDS; offset++) begin
+                    std::randomize(wr_data);
+                    reg_model.kv_reg_rm.KEY_ENTRY[entry][offset].write(sts, wr_data, UVM_FRONTDOOR, reg_model.kv_AHB_map, this);
+                    assert(sts == UVM_IS_OK) else `uvm_error("KV AHB", $sformatf("Failed when writing to KEY[%d][%d] entry",entry, offset))
+                end
+            end
+        end
+        
+        //KEY ENTRY reg reads
+        for(entry = 0; entry < KV_NUM_KEYS; entry++) begin
+            for (offset = 0; offset < KV_NUM_DWORDS; offset++) begin
+                reg_model.kv_reg_rm.KEY_ENTRY[entry][offset].read(sts, rd_data, UVM_FRONTDOOR, reg_model.kv_AHB_map, this);
+                assert(sts == UVM_IS_OK) else `uvm_error("KV AHB", $sformatf("Failed when reading from KEY[%d][%d] entry",entry, offset))
+            end
+        end
+    endtask
+
+
+endclass
\ No newline at end of file
diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_env_configuration.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_env_configuration.svh
index c9c0f8a8f..5c69a35cf 100644
--- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_env_configuration.svh
+++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_env_configuration.svh
@@ -110,7 +110,7 @@ extends uvmf_environment_configuration_base;
     qvip_ahb_lite_slave_subenv_config = qvip_ahb_lite_slave_env_configuration::type_id::create("qvip_ahb_lite_slave_subenv_config");
 
     kv_configuration_cg=new;
-    `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging.  Please note that configuration variables added as a result of re-generation and merging are not automatically added to the covergroup.  Remove this warning after the covergroup has been reviewed.")
+    `uvm_info("COVERAGE_MODEL_REVIEW", "TODO: A covergroup has been constructed which may need review because of either generation or re-generation with merging.  Please note that configuration variables added as a result of re-generation and merging are not automatically added to the covergroup.  Remove this warning after the covergroup has been reviewed.", UVM_MEDIUM)
 
   // pragma uvmf custom new begin
   // pragma uvmf custom new end
@@ -222,8 +222,13 @@ extends uvmf_environment_configuration_base;
     // pragma uvmf custom reg_model_config_initialize begin
     // Register model creation and configuation
     if (register_model == null) begin
+      uvm_reg::include_coverage("*", UVM_CVR_ALL); // Register coverage config with resource DB, used later by build_coverage()
       kv_rm = kv_reg_model_top::type_id::create("kv_rm");
+      //Turn on addr_map_coverage for kv_reg_model
+      kv_rm.set_coverage(UVM_CVR_ADDR_MAP);
+      uvm_reg::include_coverage("*", UVM_CVR_ALL);
       kv_rm.build();
+      kv_rm.set_coverage(UVM_CVR_ALL);
       kv_rm.lock_model();
       kv_rm.build_ext_maps();
       enable_reg_adaptation = 1;
diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_predictor.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_predictor.svh
index eccc290f4..7b9db72bf 100644
--- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_predictor.svh
+++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_predictor.svh
@@ -301,11 +301,12 @@ class kv_predictor #(
         last_dword_written[entry] = 'h0; //Clear last dword on hard rst
       end
     end
-    else if (t.debug_mode) begin
+    else if (t.debug_mode | t.scan_mode) begin
       //Set val_reg to 1 for use in reg predictor
       p_kv_rm.val_reg.debug_mode_unlocked.set(1'b1);
+      p_kv_rm.val_reg.cptra_in_debug_scan_mode.set(1'b1);
       
-      if (clear_secrets_data[1] == 'h1) begin
+      if (clear_secrets_data[p_kv_rm.kv_reg_rm.CLEAR_SECRETS.sel_debug_value.get_lsb_pos()] == 'h1) begin
         for(entry = 0; entry < KV_NUM_KEYS; entry++) begin
           //Debug mode should flush all regs inspite of locks
           for(offset = 0; offset < KV_NUM_DWORDS; offset++) begin
@@ -351,8 +352,13 @@ class kv_predictor #(
     end
 
     //If debug mode was unlocked, set a val register to let reg predictor know
-    if (!t.debug_mode)
+    if (!t.debug_mode) begin
       p_kv_rm.val_reg.debug_mode_unlocked.set(1'b0);
+      //TODO: resetting debug_scan_mode needed?
+      if (!t.scan_mode) begin
+        p_kv_rm.val_reg.cptra_in_debug_scan_mode.set(1'b0);
+      end
+    end
  
     // Code for sending output transaction out through kv_sb_ap
     // Please note that each broadcasted transaction should be a different object than previously 
@@ -586,8 +592,8 @@ class kv_predictor #(
     string reg_name;
     reg [KV_DATA_W-1:0] data_active;
     reg [ahb_lite_slave_0_params::AHB_WDATA_WIDTH-1:0] address_aligned;
-    uvm_reg val_ctrl;
-    uvm_reg_data_t val_ctrl_data;
+    uvm_reg val_ctrl, val_reg, val_ctrl_derived;
+    uvm_reg_data_t val_ctrl_data, val_reg_data, val_ctrl_derived_data;
 
     ahb_slave_0_ae_debug = t;
     `uvm_info("PRED", "Transaction Received through ahb_slave_0_ae", UVM_MEDIUM)
@@ -604,30 +610,40 @@ class kv_predictor #(
       //Copy txn and modify required fields later
       kv_sb_ahb_ap_output_transaction.copy(ahb_txn);
 
-      if (ahb_txn.address == `KV_REG_CLEAR_SECRETS) begin
-        p_kv_rm.val_reg.clear_secrets_bit.set(1'b1);
-        if (data_active[1:0] == 'h1) begin
-          for(entry = 0; entry < KV_NUM_KEYS; entry++) begin
-            //Read locks before clearing - do not clear if locked
-            kv_reg = p_kv_rm.get_reg_by_name($sformatf("KEY_CTRL[%0d]",entry));
-            kv_reg_data = kv_reg.get_mirrored_value();
-            if(kv_reg_data[1:0] == 2'b00) begin
-              for(offset = 0; offset < KV_NUM_DWORDS; offset++) begin              
-                p_kv_rm.kv_reg_rm.KEY_ENTRY[entry][offset].predict(CLP_DEBUG_MODE_KV_0);
-                p_kv_rm.kv_reg_rm.KEY_ENTRY[entry][offset].set(CLP_DEBUG_MODE_KV_0);
+      //Read val reg to determine if we're in debug mode
+      val_reg = p_kv_rm.get_reg_by_name("val_reg");
+      val_reg_data = val_reg.get();
+
+      //Only allow clear_secrets during debug mode
+      if ((ahb_txn.address == `KV_REG_CLEAR_SECRETS) ) begin
+        //Update val register with CLEAR_SECRETS wr_debug_values field
+        p_kv_rm.val_reg.clear_secrets_bit.set(data_active[p_kv_rm.kv_reg_rm.CLEAR_SECRETS.wr_debug_values.get_lsb_pos()]);
+
+        if (val_reg_data[p_kv_rm.val_reg.cptra_in_debug_scan_mode.get_lsb_pos()]) begin //[2]) begin
+          //Only allow clear operation if in debug mode
+          if (data_active[1:0] == 'h1) begin
+            for(entry = 0; entry < KV_NUM_KEYS; entry++) begin
+              //Read locks before clearing - do not clear if locked
+              kv_reg = p_kv_rm.get_reg_by_name($sformatf("KEY_CTRL[%0d]",entry));
+              kv_reg_data = kv_reg.get_mirrored_value();
+              if(kv_reg_data[1:0] == 2'b00) begin
+                for(offset = 0; offset < KV_NUM_DWORDS; offset++) begin              
+                  p_kv_rm.kv_reg_rm.KEY_ENTRY[entry][offset].predict(CLP_DEBUG_MODE_KV_0);
+                  p_kv_rm.kv_reg_rm.KEY_ENTRY[entry][offset].set(CLP_DEBUG_MODE_KV_0);
+                end
               end
             end
           end
-        end
-        else if(data_active[1:0] == 'h3) begin
-          for(entry = 0; entry < KV_NUM_KEYS; entry++) begin
-            //Read locks before clearing
-            kv_reg = p_kv_rm.get_reg_by_name($sformatf("KEY_CTRL[%0d]",entry));
-            kv_reg_data = kv_reg.get_mirrored_value();
-            if(kv_reg_data[1:0] == 2'b00) begin
-              for(offset = 0; offset < KV_NUM_DWORDS; offset++) begin
-                p_kv_rm.kv_reg_rm.KEY_ENTRY[entry][offset].predict(CLP_DEBUG_MODE_KV_1);
-                p_kv_rm.kv_reg_rm.KEY_ENTRY[entry][offset].set(CLP_DEBUG_MODE_KV_1);
+          else if(data_active[1:0] == 'h3) begin
+            for(entry = 0; entry < KV_NUM_KEYS; entry++) begin
+              //Read locks before clearing
+              kv_reg = p_kv_rm.get_reg_by_name($sformatf("KEY_CTRL[%0d]",entry));
+              kv_reg_data = kv_reg.get_mirrored_value();
+              if(kv_reg_data[1:0] == 2'b00) begin
+                for(offset = 0; offset < KV_NUM_DWORDS; offset++) begin
+                  p_kv_rm.kv_reg_rm.KEY_ENTRY[entry][offset].predict(CLP_DEBUG_MODE_KV_1);
+                  p_kv_rm.kv_reg_rm.KEY_ENTRY[entry][offset].set(CLP_DEBUG_MODE_KV_1);
+                end
               end
             end
           end
@@ -646,8 +662,13 @@ class kv_predictor #(
 
         if(data_active[2] && !kv_reg_data[0] && !kv_reg_data[1]) begin
           val_ctrl_data[entry] = 'b1; //In design, clear is a single pulse reg. This val_ctrl[*] will be reset in kv_reg_predictor
+          val_ctrl_derived_data[entry] = 'b1;
           //p_kv_rm.kv_reg_rm.kv_val_ctrl.predict(val_ctrl_data);
+          `uvm_info("PRED", "Setting clear field of val_ctrl register", UVM_MEDIUM)
           p_kv_rm.val_ctrl.set(val_ctrl_data);
+
+          `uvm_info("PRED", "Setting clear field of val_ctrl_derived register", UVM_MEDIUM)
+          p_kv_rm.val_ctrl_derived.set(val_ctrl_derived_data);
           //Clear the entry that is being accessed
           for(offset = 0; offset < KV_NUM_DWORDS; offset++) begin
             p_kv_rm.kv_reg_rm.KEY_ENTRY[entry][offset].predict('h0);
@@ -733,8 +754,9 @@ endclass
       t_expected.error = 'b0;
     end
 
-    if (val_ctrl_data[t_received.read_entry])
+    if (val_ctrl_data[t_received.read_entry]) begin
       last_dword_written[t_received.read_entry] = 'h0;
+    end
 
     t_expected.last = (last_dword_written[t_received.read_entry] == t_received.read_offset); 
     t_expected.read_entry = t_received.read_entry;
@@ -742,10 +764,11 @@ endclass
   endfunction
 
   function void kv_predictor::populate_expected_kv_write_txn (ref kv_sb_ap_output_transaction_write_t t_expected, kv_write_transaction t_received);
-    uvm_reg kv_reg;
-    uvm_reg_data_t kv_reg_data;
+    uvm_reg kv_reg, val_ctrl_derived;
+    uvm_reg_data_t kv_reg_data, val_ctrl_derived_data;
     logic lock_use;
     logic lock_wr;
+    logic clear;
 
     //TODO: This logic takes advantage of the fact that reg model writes happen without a 1 clk delay.
     //So when predictor reads the CTRL reg, the lock info is already up to date
@@ -756,16 +779,38 @@ endclass
     lock_wr = kv_reg_data[0];
     lock_use = kv_reg_data[1];
 
-    //Copy received txn
-    t_expected = t_received;
+    val_ctrl_derived = p_kv_rm.get_reg_by_name("val_ctrl_derived");
+    val_ctrl_derived_data = val_ctrl_derived.get();
 
-    //Error should be set when writing to locked regs
-    if(lock_wr || lock_use)
-      t_expected.error = 'b1;
+    //Copy received txn
+    // t_expected = t_received;
+    t_expected.write_en         = t_received.write_en;
+    t_expected.write_entry      = t_received.write_entry;
+    t_expected.write_offset     = t_received.write_offset;
+    t_expected.write_data       = t_received.write_data;
+    t_expected.write_dest_valid = t_received.write_dest_valid;
+
+    //Error should be set when writing to locked regs //TODO: error when entry is being cleared during write
+    if (t_received.write_en) begin
+      if(lock_wr || lock_use) begin
+        t_expected.error = 1'b1;
+        `uvm_info("PRED", "Trying to write to a locked reg", UVM_MEDIUM)
+      end
+      else if (/*this.write_in_progress[t_received.write_entry] &&*/ val_ctrl_derived_data[t_received.write_entry]) begin
+        t_expected.error = 1'b1;
+        `uvm_info("PRED","Attempts to clear a reg while write is in progress results in an error", UVM_MEDIUM)
+        `uvm_info("PRED", $sformatf("Write entry = %0d, val_ctrl_derived_data = %b", t_received.write_entry, val_ctrl_derived_data), UVM_MEDIUM)
+      end
+      else begin
+        t_expected.error = 1'b0;
+        //Keep track of last dword written
+        last_dword_written[t_received.write_entry] = t_received.write_offset;
+      end
+    end
+    else begin
+      t_expected.error = 1'b0;
+    end
 
-    //Keep track of last dword written
-    last_dword_written[t_received.write_entry] = t_received.write_offset;
-    
       
   endfunction
 // pragma uvmf custom external end
diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_reg_predictor.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_reg_predictor.svh
index 1ad9f9d8e..de58e86f4 100644
--- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_reg_predictor.svh
+++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_reg_predictor.svh
@@ -33,6 +33,8 @@ class kv_reg_predictor#(type BUSTYPE=int) extends uvm_reg_predictor #(.BUSTYPE(B
 
     uvm_reg_adapter adapter;
 
+    extern function logic [(KV_NUM_READ + $clog2(KV_NUM_DWORDS))-1 :0] parse_wr_transaction(uvm_sequence_item bus_item);
+
     //Create new instance of this type
     function new (string name, uvm_component parent);
         super.new(name, parent);
@@ -63,14 +65,19 @@ class kv_reg_predictor#(type BUSTYPE=int) extends uvm_reg_predictor #(.BUSTYPE(B
         uvm_reg_data_t val_reg_data;
         uvm_reg_item val_reg_item;
 
-        uvm_reg val_ctrl;
-        uvm_reg_data_t val_ctrl_data;
+        uvm_reg val_ctrl, val_ctrl_derived;
+        uvm_reg_data_t val_ctrl_data, val_ctrl_derived_data;
         uvm_reg_item val_ctrl_item;
 
         logic lock_wr;
         logic lock_use;
         logic clear;
 
+        logic [KV_NUM_READ-1:0] write_dest_valid;
+        logic [$clog2(KV_NUM_DWORDS)-1:0] last_dword;
+
+        uvm_reg rg;
+
         //Pass variables to parent
         super.reg_ap = reg_ap_local;
         super.map = map;
@@ -78,56 +85,51 @@ class kv_reg_predictor#(type BUSTYPE=int) extends uvm_reg_predictor #(.BUSTYPE(B
         
         //Convert bus txn to reg model txn
         adapter.bus2reg(tr,rw);
-        
+
         //-----------------------------------------------
         //rw contains KEY entry info. Below steps are to
         //derive corresponding CTRL reg info
         //-----------------------------------------------
         if (rw.kind == UVM_WRITE) begin
+            //Get write_dest_valid and last_dword data from tx
+            {write_dest_valid, last_dword} = parse_wr_transaction(tr);
+
             //Convert reg addr to entry/offset
             entry_offset = convert_addr_to_kv(rw.addr);
 
             //Calculate CTRL addr based on entry info
             addr = convert_kv_to_ctrl_addr(entry_offset);
 
-            //Build rw_ctrl (reg model txn for CTRL reg)
-            rw_ctrl = rw;
-            rw_ctrl.addr = uvm_reg_addr_t'(addr); 
-
-            //-----------------------------------------------
-            //Read val reg first
-            //-----------------------------------------------
-            val_reg = map.get_reg_by_offset('h1_0000);
-            val_reg_data = val_reg.get();
-            
-            val_ctrl = map.get_reg_by_offset('h1_0004);
-            val_ctrl_data = val_ctrl.get();
             //-----------------------------------------------
             //Below steps are to read CTRL reg data from reg model
             //and append dest valid to it (we want to keep lock bits same)
             //-----------------------------------------------
+            //Build rw_ctrl (reg model txn for CTRL reg)
+            rw_ctrl = rw;
+            rw_ctrl.addr = uvm_reg_addr_t'(addr); 
+            
             kv_reg = map.get_reg_by_offset(rw.addr, (rw.kind == UVM_READ));
             kv_reg_ctrl = map.get_reg_by_offset(rw_ctrl.addr, (rw_ctrl.kind == UVM_READ));
-
+            
             //TODO: reg null check?
             //Read CTRL reg data
             kv_reg_ctrl_data = kv_reg_ctrl.get_mirrored_value();
             //Append dest valid to it
-            kv_reg_ctrl_data = {kv_reg_ctrl_data[31:14], 5'h1F, kv_reg_ctrl_data[8:0]};
+            kv_reg_ctrl_data = {kv_reg_ctrl_data[31:21], last_dword, kv_reg_ctrl_data[16:14], /*5'h1F*/write_dest_valid, kv_reg_ctrl_data[8:0]};
             rw_ctrl.data = kv_reg_ctrl_data;
+
             //-----------------------------------------------
-            //Predict ctrl reg data so it gets updated in reg model
+            //Read val reg first
             //-----------------------------------------------
-            kv_reg_ctrl_item = new;
-            kv_reg_ctrl_item.element_kind = UVM_REG;
-            kv_reg_ctrl_item.element = kv_reg_ctrl;
-            kv_reg_ctrl_item.path = UVM_PREDICT;
-            kv_reg_ctrl_item.map = map;
-            kv_reg_ctrl_item.kind = UVM_WRITE;
-            kv_reg_ctrl_item.value[0] |= kv_reg_ctrl_data;
+            val_reg = map.get_reg_by_offset('h1_0000);
+            val_reg_data = val_reg.get();
+            
+            val_ctrl = map.get_reg_by_offset('h1_0004);
+            val_ctrl_data = val_ctrl.get();
+
+            val_ctrl_derived = map.get_reg_by_offset('h1_0008);
+            val_ctrl_derived_data = val_ctrl_derived.get();
 
-            //Update CTRL reg 
-            kv_reg_ctrl.do_predict(kv_reg_ctrl_item, UVM_PREDICT_DIRECT);
             
             //-----------------------------------------------
             //Update val_ctrl reg to reset clear bit for the entry that is being written
@@ -145,6 +147,25 @@ class kv_reg_predictor#(type BUSTYPE=int) extends uvm_reg_predictor #(.BUSTYPE(B
             //Update CTRL reg 
             val_ctrl.do_predict(val_ctrl_item, UVM_PREDICT_DIRECT);
 
+            //-----------------------------------------------
+            //Update val_ctrl_derived reg to reset clear bits for all other entries except current one
+            //This will be used to hold the clear until writes are finished to current entry
+            //-----------------------------------------------
+            for (int i = 0; i < KV_NUM_KEYS; i++) begin
+                val_ctrl_derived_data[i] /*[entry_offset[4:0]]*/ = (val_ctrl_derived_data[i] & (i == entry_offset[4:0])); //'b0; //Reset clear bit of current entry
+            end
+
+            val_ctrl_item = new;
+            val_ctrl_item.element_kind = UVM_REG;
+            val_ctrl_item.element = val_ctrl_derived;
+            val_ctrl_item.path = UVM_PREDICT;
+            val_ctrl_item.map = map;
+            val_ctrl_item.kind = UVM_WRITE;
+            val_ctrl_item.value[0] |= val_ctrl_derived_data;
+
+            //Update CTRL reg 
+            val_ctrl_derived.do_predict(val_ctrl_item, UVM_PREDICT_DIRECT);
+
             //-----------------------------------------------
             //Check clear secrets and lock_wr/use before writing
             //-----------------------------------------------
@@ -159,14 +180,38 @@ class kv_reg_predictor#(type BUSTYPE=int) extends uvm_reg_predictor #(.BUSTYPE(B
             //If lock_wr, lock_use, debug mode or clear secrets is enabled, do not write to reg model
 
             //TODO: Revisit lock and clear condition
-            if (!lock_wr && !lock_use && !clear_secrets_data[0] && !val_reg_data[0])begin // && !val_reg_data[1]) begin
+            //TODO: Can write to regs during debug mode. Remove check after updating sequences
+            `uvm_info("KV_REG_PRED", $sformatf("OUTSIDE, lock_wr = %0d, lock_use = %0d, clear_secrets_wren = %0d, val_reg_data = %b", lock_wr, lock_use, clear_secrets_data[0], val_reg_data), UVM_FULL)
+            if (!lock_wr && !lock_use && !(clear_secrets_data[0] && val_reg_data[2]) && !val_reg_data[0]) begin
+                `uvm_info("KV_REG_PRED", "Writing to KEY_ENTRY", UVM_FULL)
                 super.write(tr);
+
+                `uvm_info("KV_REG_PRED", "Updating KEY_CTRL", UVM_FULL)
+                
+                //-----------------------------------------------
+                //Predict ctrl reg data so it gets updated in reg model
+                //-----------------------------------------------
+                kv_reg_ctrl_item = new;
+                kv_reg_ctrl_item.element_kind = UVM_REG;
+                kv_reg_ctrl_item.element = kv_reg_ctrl;
+                kv_reg_ctrl_item.path = UVM_PREDICT;
+                kv_reg_ctrl_item.map = map;
+                kv_reg_ctrl_item.kind = UVM_WRITE;
+                kv_reg_ctrl_item.value[0] |= kv_reg_ctrl_data;
+
+                //Update CTRL reg 
+                kv_reg_ctrl.do_predict(kv_reg_ctrl_item, UVM_PREDICT_DIRECT);
+            end
+            else begin
+                `uvm_info("KV_REG_PRED", "Skipping write to KEY_ENTRY", UVM_FULL)
+                `uvm_info("KV_REG_PRED", $sformatf("lock_wr = %0d, lock_use = %0d, clear_secrets_data = %0d, val_reg_data = %b", lock_wr, lock_use, clear_secrets_data[0], val_reg_data), UVM_FULL)
             end
             
             //-----------------------------------------------
             //Clear secrets wren bit back to 0 (single pulse behv) - do this if clear_secrets reg is not being written to in the same cycle
             //-----------------------------------------------
             if(val_reg_data[1]) begin
+                `uvm_info("KV_REG_PRED", "Clear_secrets bit is reset after a single pulse", UVM_FULL)
                 clear_secrets_item = new;
                 clear_secrets_item.element_kind = UVM_REG;
                 clear_secrets_item.element = clear_secrets_reg;
@@ -186,7 +231,7 @@ class kv_reg_predictor#(type BUSTYPE=int) extends uvm_reg_predictor #(.BUSTYPE(B
             val_reg_item.path = UVM_PREDICT;
             val_reg_item.map = map;
             val_reg_item.kind = UVM_WRITE;
-            val_reg_item.value[0] |= {1'b0,val_reg_data[0]}; //Clear and clear_secrets_bit are single pulse, so make them 0. Keep debug_mode as is
+            val_reg_item.value[0] |= {val_reg_data[2],1'b0,val_reg_data[0]}; //Clear and clear_secrets_bit are single pulse, so make them 0. Keep debug_mode as is
 
             val_reg.do_predict(val_reg_item, UVM_PREDICT_DIRECT);
             
@@ -195,7 +240,28 @@ class kv_reg_predictor#(type BUSTYPE=int) extends uvm_reg_predictor #(.BUSTYPE(B
             super.write(tr);
         end
 
+        rg = map.get_reg_by_offset(rw.addr, (rw.kind == UVM_READ));
+        rg.sample_values();
+        rg = map.get_reg_by_offset(rw_ctrl.addr, (rw_ctrl.kind == UVM_READ));
+        rg.sample_values();
+
     endfunction
 
     
-endclass
\ No newline at end of file
+endclass
+
+function logic [(KV_NUM_READ + $clog2(KV_NUM_DWORDS))-1 :0] kv_reg_predictor::parse_wr_transaction(uvm_sequence_item bus_item);
+    kv_write_transaction #(
+      .KV_WRITE_REQUESTOR("HMAC")
+    )
+    trans_h;
+
+    if (!$cast(trans_h, bus_item)) begin
+      `uvm_fatal("ADAPT","Provided bus_item is not of the correct type")
+    //   return;
+    end
+    // pragma uvmf custom bus2reg begin
+    parse_wr_transaction = {trans_h.write_dest_valid, trans_h.write_offset};
+    // pragma uvmf custom bus2reg end
+
+endfunction: parse_wr_transaction
\ No newline at end of file
diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_cold_rst_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_cold_rst_sequence.svh
index 34c908a9e..22b62fac4 100644
--- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_cold_rst_sequence.svh
+++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_cold_rst_sequence.svh
@@ -153,6 +153,8 @@ class kv_wr_rd_debug_cold_rst_sequence #(
             
             //Issue cold reset before reading
             kv_rst_agent_cold_rst_seq.start(configuration.kv_rst_agent_config.sequencer);
+            //Wait for cold reset to finish
+            configuration.kv_rst_agent_config.wait_for_num_clocks(10);
 
             //Read all entries
             for (read_entry = 0; read_entry < KV_NUM_KEYS; read_entry++) begin
diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_lock_clear_rst_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_lock_clear_rst_sequence.svh
new file mode 100644
index 000000000..48cfbaf03
--- /dev/null
+++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_lock_clear_rst_sequence.svh
@@ -0,0 +1,230 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Sets all KEY_CTRL lock_wr/use/clear bits randomly. Then
+// executes writes and reads in parallel while randomly unlocking debug
+// mode via input pin or CLEAR_SECRETS reg
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+class kv_wr_rd_debug_lock_clear_rst_sequence #(
+    type CONFIG_T
+) extends kv_env_sequence_base #(.CONFIG_T(CONFIG_T));
+
+    `uvm_object_param_utils(kv_wr_rd_debug_lock_clear_rst_sequence #(CONFIG_T));
+
+    typedef kv_rst_poweron_sequence kv_rst_agent_poweron_sequence_t;
+    kv_rst_agent_poweron_sequence_t kv_rst_agent_poweron_seq;
+    kv_rst_agent_poweron_sequence_t kv_rst_agent_poweron_seq_2;
+
+    typedef kv_rst_warm_rst_sequence kv_rst_agent_warm_rst_sequence_t;
+    kv_rst_agent_warm_rst_sequence_t kv_warm_rst_seq;
+
+    typedef kv_rst_cold_rst_sequence kv_rst_agent_cold_rst_sequence_t;
+    kv_rst_agent_cold_rst_sequence_t kv_cold_rst_seq;
+
+    typedef kv_rst_debug_sequence kv_rst_agent_debug_sequence_t;
+    kv_rst_agent_debug_sequence_t kv_rst_agent_debug_seq;
+
+    typedef kv_write_key_entry_sequence kv_write_agent_key_entry_sequence_t;
+    kv_write_agent_key_entry_sequence_t hmac_write_seq;
+    kv_write_agent_key_entry_sequence_t sha512_write_seq;
+    kv_write_agent_key_entry_sequence_t ecc_write_seq;
+    kv_write_agent_key_entry_sequence_t doe_write_seq;
+
+    typedef kv_read_key_entry_sequence kv_read_agent_key_entry_sequence_t;
+    kv_read_agent_key_entry_sequence_t hmac_key_read_seq;
+    kv_read_agent_key_entry_sequence_t hmac_block_read_seq;
+    kv_read_agent_key_entry_sequence_t sha512_block_read_seq;
+    kv_read_agent_key_entry_sequence_t ecc_privkey_read_seq;
+    kv_read_agent_key_entry_sequence_t ecc_seed_read_seq;
+
+    rand reg [KV_ENTRY_ADDR_W-1:0] hmac_write_entry, sha512_write_entry, ecc_write_entry, doe_write_entry;    
+    rand int unsigned wait_cycles_from_seq;
+    rand bit debug_type;
+    rand bit reset_type;
+    rand reg [1:0] clear_secrets_data;
+    rand reg [2:0] lock_data;
+
+    typedef enum {SECURITY_STATE, CLEAR_SECRETS} debug_inputs;
+    typedef enum {WARM_RESET, COLD_RESET} reset_inputs;
+
+    function new(string name = "");
+        super.new(name);
+        kv_rst_agent_poweron_seq = kv_rst_agent_poweron_sequence_t::type_id::create("kv_rst_agent_poweron_seq");
+        if(!this.randomize()) `uvm_error("KV WR RD", "Failed to randomize KV RST poweron seq");
+        kv_rst_agent_poweron_seq_2 = kv_rst_agent_poweron_sequence_t::type_id::create("kv_rst_agent_poweron_seq_2");
+        if(!this.randomize()) `uvm_error("KV WR RD", "Failed to randomize KV RST poweron seq");
+        kv_warm_rst_seq = kv_rst_agent_warm_rst_sequence_t::type_id::create("kv_warm_rst_seq");
+        if(!this.randomize()) `uvm_error("KV WR RD", "Failed to randomize KV_RST warm rst seq");
+        kv_cold_rst_seq = kv_rst_agent_cold_rst_sequence_t::type_id::create("kv_cold_rst_seq");
+        if(!this.randomize()) `uvm_error("KV WR RD", "Failed to randomize KV_RST cold rst seq");
+
+        kv_rst_agent_debug_seq = kv_rst_agent_debug_sequence_t::type_id::create("kv_rst_agent_debug_seq");
+        if(!this.randomize()) `uvm_error("KV WR RD", "Failed to randomize KV RST debug seq");
+        
+        hmac_write_seq = kv_write_agent_key_entry_sequence_t::type_id::create("hmac_write_seq");
+        if(!this.randomize()) `uvm_error("KV WR RD", "Failed to randomize KV WRITE seq");
+        sha512_write_seq = kv_write_agent_key_entry_sequence_t::type_id::create("sha512_write_seq");
+        if(!this.randomize()) `uvm_error("KV WR RD", "Failed to randomize KV WRITE seq");
+        ecc_write_seq = kv_write_agent_key_entry_sequence_t::type_id::create("ecc_write_seq");
+        if(!this.randomize()) `uvm_error("KV WR RD", "Failed to randomize KV WRITE seq");
+        doe_write_seq = kv_write_agent_key_entry_sequence_t::type_id::create("doe_write_seq");
+        if(!this.randomize()) `uvm_error("KV WR RD", "Failed to randomize KV WRITE seq");
+        
+        hmac_key_read_seq = kv_read_agent_key_entry_sequence_t::type_id::create("hmac_key_read_seq");
+        if(!this.randomize()) `uvm_error("KV WR RD", "Failed to randomize KV READ seq");
+        hmac_block_read_seq = kv_read_agent_key_entry_sequence_t::type_id::create("hmac_block_read_seq");
+        if(!this.randomize()) `uvm_error("KV WR RD", "Failed to randomize KV READ seq");
+        sha512_block_read_seq = kv_read_agent_key_entry_sequence_t::type_id::create("sha512_block_read_seq");
+        if(!this.randomize()) `uvm_error("KV WR RD", "Failed to randomize KV READ seq");
+        ecc_privkey_read_seq = kv_read_agent_key_entry_sequence_t::type_id::create("ecc_privkey_read_seq");
+        if(!this.randomize()) `uvm_error("KV WR RD", "Failed to randomize KV READ seq");
+        ecc_seed_read_seq = kv_read_agent_key_entry_sequence_t::type_id::create("ecc_seed_read_seq");
+        if(!this.randomize()) `uvm_error("KV WR RD", "Failed to randomize KV READ seq");
+        //kv_rst_agent_poweron_seq_2 = kv_rst_agent_poweron_sequence_t::type_id::create("kv_rst_agent_poweron_seq_2");
+        
+    endfunction
+
+    virtual task body();
+        uvm_status_e sts;
+        //uvm_reg_data_t rd_data;
+        int write_entry = 0; 
+        int write_offset = 0;
+        int read_entry = 0; 
+        int read_offset = 0;
+        reg [31:0] wr_data, rd_data;
+        reg_model = configuration.kv_rm;
+
+
+        //Issue and wait for reset
+        if(configuration.kv_rst_agent_config.sequencer != null)
+            kv_rst_agent_poweron_seq.start(configuration.kv_rst_agent_config.sequencer);
+        else
+            `uvm_error("KV WR RD", "kv_rst_agent_config.sequencer is null!")
+
+        //Write to all entries
+                for (write_entry = 0; write_entry < KV_NUM_KEYS; write_entry++) begin
+                    for(write_offset = 0; write_offset < KV_NUM_DWORDS; write_offset++) begin
+                        uvm_config_db#(reg [KV_ENTRY_ADDR_W-1:0])::set(null, "uvm_test_top.environment.kv_sha512_write_agent.sequencer.sha512_write_seq", "local_write_entry",write_entry);
+                        uvm_config_db#(reg [KV_ENTRY_SIZE_W-1:0])::set(null, "uvm_test_top.environment.kv_sha512_write_agent.sequencer.sha512_write_seq", "local_write_offset",write_offset);
+                        sha512_write_seq.start(configuration.kv_sha512_write_agent_config.sequencer);
+                    end
+                end
+
+        //Set each CTRL reg with random lock data
+        for(write_entry = 0; write_entry < KV_NUM_KEYS; write_entry++) begin
+            // Construct the transaction
+            lock_data = 'h3; //$urandom_range(1,7); //Can set one of lock_wr, lock_use, clear or all together
+            reg_model.kv_reg_rm.KEY_CTRL[write_entry].write(sts, lock_data, UVM_FRONTDOOR, reg_model.kv_AHB_map, this);
+            assert(sts == UVM_IS_OK) else `uvm_error("AHB_LOCK_SET", $sformatf("Failed when writing to KEY_CTRL[%d]",write_entry))
+        end
+        
+        
+                //Unlock debug mode or clear secrets randomly
+                
+                    std::randomize(debug_type); //0 - security state, 1 - clear secrets
+                    
+                    std::randomize(wait_cycles_from_seq) with {
+                        wait_cycles_from_seq >= 5;
+                        wait_cycles_from_seq <= 100;
+                    };
+
+                    std::randomize(clear_secrets_data); //wren, debug_value0/1
+
+                    //Wait for random delay before starting debug txn
+                    configuration.kv_rst_agent_config.wait_for_num_clocks(wait_cycles_from_seq);
+
+                    case(debug_type)
+                        SECURITY_STATE: begin
+                            //start debug seq on rst agent
+                            kv_rst_agent_debug_seq.start(configuration.kv_rst_agent_config.sequencer);
+                        end
+                        CLEAR_SECRETS: begin
+                            reg_model.kv_reg_rm.CLEAR_SECRETS.write(sts, clear_secrets_data, UVM_FRONTDOOR, reg_model.kv_AHB_map, this);
+                            assert(sts == UVM_IS_OK) else `uvm_error("AHB_CLEAR_SECRETS_SET", "Failed when writing to CLEAR_SECRETS reg!")
+                        end
+                    endcase
+
+                    std::randomize(reset_type);
+
+                    case(reset_type)
+                        WARM_RESET: begin
+                            kv_warm_rst_seq.start(configuration.kv_rst_agent_config.sequencer); //locks cleared
+                        end
+                        COLD_RESET: begin
+                            kv_cold_rst_seq.start(configuration.kv_rst_agent_config.sequencer);
+                        end
+                    endcase
+
+                //Clear secrets again + warm rst, no locks this time
+                std::randomize(debug_type);
+                //debug_type = 1;
+                    
+                    std::randomize(wait_cycles_from_seq) with {
+                        wait_cycles_from_seq >= 5;
+                        wait_cycles_from_seq <= 100;
+                    };
+
+                    std::randomize(clear_secrets_data); //wren, debug_value0/1
+                    // clear_secrets_data = 'h3;
+
+                    //Wait for random delay before starting debug txn
+                    configuration.kv_rst_agent_config.wait_for_num_clocks(wait_cycles_from_seq);
+
+                    case(debug_type)
+                        SECURITY_STATE: begin
+                            //start debug seq on rst agent
+                            kv_rst_agent_debug_seq.start(configuration.kv_rst_agent_config.sequencer);
+                        end
+                        CLEAR_SECRETS: begin
+                            reg_model.kv_reg_rm.CLEAR_SECRETS.write(sts, clear_secrets_data, UVM_FRONTDOOR, reg_model.kv_AHB_map, this);
+                            assert(sts == UVM_IS_OK) else `uvm_error("AHB_CLEAR_SECRETS_SET", "Failed when writing to CLEAR_SECRETS reg!")
+                        end
+                    endcase
+                kv_warm_rst_seq.start(configuration.kv_rst_agent_config.sequencer);
+            
+            fork
+            // begin
+                // //Write to all entries
+                // for (write_entry = 0; write_entry < KV_NUM_KEYS; write_entry++) begin
+                //     for(write_offset = 0; write_offset < KV_NUM_DWORDS; write_offset++) begin
+                //         uvm_config_db#(reg [KV_ENTRY_ADDR_W-1:0])::set(null, "uvm_test_top.environment.kv_sha512_write_agent.sequencer.sha512_write_seq", "local_write_entry",write_entry);
+                //         uvm_config_db#(reg [KV_ENTRY_SIZE_W-1:0])::set(null, "uvm_test_top.environment.kv_sha512_write_agent.sequencer.sha512_write_seq", "local_write_offset",write_offset);
+                //         sha512_write_seq.start(configuration.kv_sha512_write_agent_config.sequencer);
+                //     end
+                // end
+            // end             
+            begin
+                //Read all entries
+                for (read_entry = 0; read_entry < KV_NUM_KEYS; read_entry++) begin
+                    for (read_offset = 0; read_offset < KV_NUM_DWORDS; read_offset++) begin
+                        uvm_config_db#(reg [KV_ENTRY_ADDR_W-1:0])::set(null, "uvm_test_top.environment.kv_sha512_block_read_agent.sequencer.sha512_block_read_seq", "local_read_entry",read_entry);
+                        uvm_config_db#(reg [KV_ENTRY_SIZE_W-1:0])::set(null, "uvm_test_top.environment.kv_sha512_block_read_agent.sequencer.sha512_block_read_seq", "local_read_offset",read_offset);
+                        sha512_block_read_seq.start(configuration.kv_sha512_block_read_agent_config.sequencer);
+                    end
+                end
+            end
+        join
+    endtask
+endclass
\ No newline at end of file
diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_warm_rst_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_warm_rst_sequence.svh
index 90eff5461..0f85dabf9 100644
--- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_warm_rst_sequence.svh
+++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_warm_rst_sequence.svh
@@ -157,6 +157,8 @@ class kv_wr_rd_debug_warm_rst_sequence #(
             
             //Issue warm reset before reading
             kv_rst_agent_warm_rst_seq.start(configuration.kv_rst_agent_config.sequencer);
+            //Wait for warm reset to finish
+            configuration.kv_rst_agent_config.wait_for_num_clocks(10);
 
             //Read all entries
             for (read_entry = 0; read_entry < KV_NUM_KEYS; read_entry++) begin
diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_lock_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_lock_sequence.svh
index 76791e6c6..37b51bb32 100644
--- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_lock_sequence.svh
+++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_lock_sequence.svh
@@ -198,6 +198,47 @@ class kv_wr_rd_lock_sequence #(
             end
         end
 
+        //TODO: this needs env clean up! (Emulate 1 clk delay between key_entry_clear and wr_resp_error)
+        // //clear x write
+        // // fork
+
+        // //Issue and wait for reset
+        // if(configuration.kv_rst_agent_config.sequencer != null)
+        //     kv_rst_agent_poweron_seq.start(configuration.kv_rst_agent_config.sequencer);
+        // else
+        //     `uvm_error("KV_WR_RD_LOCK", "kv_rst_agent_config.sequencer is null!")
+            
+        // // begin
+        //     //Set each CTRL reg with random lock data
+        //     for(int write_entry_temp = 0; write_entry_temp < KV_NUM_KEYS; write_entry_temp++) begin
+        //         // if (write_entry_temp < KV_NUM_KEYS-1) begin
+        //             // lock_data = $urandom_range(1,7); //Can set one of lock_wr, lock_use, clear or all together
+        //             reg_model.kv_reg_rm.KEY_CTRL[write_entry_temp].write(sts, 'h4, UVM_FRONTDOOR, reg_model.kv_AHB_map, this);
+        //             `uvm_info("KNU_LOCK", $sformatf("Setting KEY CTRL: %d", write_entry_temp), UVM_MEDIUM)
+        //             assert(sts == UVM_IS_OK) else `uvm_error("AHB_LOCK_SET", $sformatf("Failed when writing to KEY_CTRL[%d]",write_entry_temp))
+        //         // end
+
+        //         for (int write_offset_temp = 0; write_offset_temp < KV_NUM_DWORDS; write_offset_temp++) begin
+        //             // Construct the transaction
+        //             uvm_config_db#(reg [KV_ENTRY_ADDR_W-1:0])::set(null, "uvm_test_top.environment.kv_hmac_write_agent.sequencer.hmac_write_seq", "local_write_entry",write_entry_temp);
+        //             uvm_config_db#(reg [KV_ENTRY_SIZE_W-1:0])::set(null, "uvm_test_top.environment.kv_hmac_write_agent.sequencer.hmac_write_seq", "local_write_offset",write_offset_temp);
+        //             `uvm_info("KNU_WRITE", $sformatf("Writing to entry: %0d, offset: %0d", write_entry_temp, write_offset_temp), UVM_MEDIUM)
+        //             hmac_write_seq.start(configuration.kv_hmac_write_agent_config.sequencer);
+        //         end
+
+                
+        //     end
+        // // end
+
+        // // begin
+        //     //Write to all entries, random offsets
+        //     // for (int write_entry_temp = 0; write_entry_temp < KV_NUM_KEYS; write_entry_temp++) begin
+                
+        //     // end
+
+        // // end
+        // // join
+
     endtask
 
 endclass
\ No newline at end of file
diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_read_pkg/src/kv_read_monitor_bfm.sv b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_read_pkg/src/kv_read_monitor_bfm.sv
index 8f13af637..ff0275138 100644
--- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_read_pkg/src/kv_read_monitor_bfm.sv
+++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_read_pkg/src/kv_read_monitor_bfm.sv
@@ -221,6 +221,7 @@ end
     kv_read_monitor_struct.error        = kv_rd_resp_i[33];
     kv_read_monitor_struct.last        = kv_rd_resp_i[32];
     kv_read_monitor_struct.read_data    = kv_rd_resp_i[31:0];
+
     // pragma uvmf custom do_monitor end
   endtask         
   
diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_read_pkg/src/kv_read_transaction.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_read_pkg/src/kv_read_transaction.svh
index e53230806..1642ac4e6 100644
--- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_read_pkg/src/kv_read_transaction.svh
+++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_read_pkg/src/kv_read_transaction.svh
@@ -124,7 +124,7 @@ class kv_read_transaction #(
   virtual function string convert2string();
     // pragma uvmf custom convert2string begin
     // UVMF_CHANGE_ME : Customize format if desired.
-    return $sformatf("read_entry:0x%x read_offset:0x%x error: 0x%x last_dword: 0x%x read_data:0x%x ",read_entry,read_offset,error,last,read_data);
+    return $sformatf("read_entry:0x%x read_offset:0x%x read_resp_err: 0x%x last_dword: 0x%x read_data:0x%x ",read_entry,read_offset,error,last,read_data);
     // pragma uvmf custom convert2string end
   endfunction
 
diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_read_pkg/src/kv_read_transaction_coverage.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_read_pkg/src/kv_read_transaction_coverage.svh
index e7e5e9255..83a9258f0 100644
--- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_read_pkg/src/kv_read_transaction_coverage.svh
+++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_read_pkg/src/kv_read_transaction_coverage.svh
@@ -28,6 +28,17 @@
 //----------------------------------------------------------------------
 //----------------------------------------------------------------------
 //
+//
+
+covergroup rd_data(input logic rd_data_bit);
+  option.per_instance = 1;
+  value: coverpoint rd_data_bit;
+  transition:  coverpoint rd_data_bit {
+    bins bin01 = (0 => 1); 
+    bins bin10 = (1 => 0);
+  }
+endgroup
+
 class kv_read_transaction_coverage #(
       string KV_READ_REQUESTOR = "HMAC_KEY"
       )
@@ -44,6 +55,7 @@ class kv_read_transaction_coverage #(
   T coverage_trans;
 
   // pragma uvmf custom class_item_additional begin
+  rd_data rd_data_bus[KV_DATA_W];
   // pragma uvmf custom class_item_additional end
   
   // ****************************************************************************
@@ -58,7 +70,9 @@ class kv_read_transaction_coverage #(
     }
     error: coverpoint coverage_trans.error;
     last: coverpoint coverage_trans.last;
-    //read_data: coverpoint coverage_trans.read_data;
+    //read_data: coverpoint coverage_trans.read_data; --> tgl coverage here
+    //cross last with diff offsets
+    lastXoffset: cross last, read_offset;
     // pragma uvmf custom covergroup end
   endgroup
 
@@ -89,7 +103,12 @@ class kv_read_transaction_coverage #(
   virtual function void write (T t);
     `uvm_info("COV","Received transaction",UVM_HIGH);
     coverage_trans = t;
+
+    foreach(rd_data_bus[i]) rd_data_bus[i] = new(coverage_trans.read_data[i]);
+    foreach(rd_data_bus[i]) rd_data_bus[i].set_inst_name($sformatf("rd_data_bus[%0d]_%s",i,get_full_name()));
+
     kv_read_transaction_cg.sample();
+    foreach(rd_data_bus[i]) rd_data_bus[i].sample();
   endfunction
 
 endclass
diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_cold_rst_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_cold_rst_sequence.svh
index 99bfe2ea9..80d5f746a 100644
--- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_cold_rst_sequence.svh
+++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_cold_rst_sequence.svh
@@ -57,6 +57,7 @@ class kv_rst_cold_rst_sequence extends kv_rst_sequence_base;
     req.assert_rst = 1'b1;
     req.assert_core_rst = 1'b1;
     req.debug_mode = 1'b0;
+    req.scan_mode = 1'b0;
 
     finish_item(req);
     `uvm_info("KV_RST_COLD_RST", {"Response:",req.convert2string()},UVM_MEDIUM)
@@ -71,6 +72,7 @@ class kv_rst_cold_rst_sequence extends kv_rst_sequence_base;
     req.assert_rst = 1'b1;
     req.assert_core_rst = 1'b1;
     req.debug_mode = 1'b0;
+    req.scan_mode = 1'b0;
 
     finish_item(req);
     `uvm_info("KV_RST_COLD_RST", {"Response:",req.convert2string()},UVM_MEDIUM)
@@ -85,6 +87,7 @@ class kv_rst_cold_rst_sequence extends kv_rst_sequence_base;
     req.assert_rst = 1'b0;
     req.assert_core_rst = 1'b0;
     req.debug_mode = 1'b0;
+    req.scan_mode = 1'b0;
 
     finish_item(req);
     `uvm_info("KV_RST_COLD_RST", {"Response:",req.convert2string()},UVM_MEDIUM)
diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_core_rst_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_core_rst_sequence.svh
index 1b3aa73d2..770007363 100644
--- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_core_rst_sequence.svh
+++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_core_rst_sequence.svh
@@ -56,6 +56,7 @@ class kv_rst_core_rst_sequence extends kv_rst_sequence_base;
     req.assert_rst = 1'b0;
     req.assert_core_rst = 1'b1;
     req.debug_mode = 1'b0;
+    req.scan_mode = 1'b0;
 
     finish_item(req);
     `uvm_info("KV_RST_CORE_RST", {"Response:",req.convert2string()},UVM_MEDIUM)
@@ -70,6 +71,7 @@ class kv_rst_core_rst_sequence extends kv_rst_sequence_base;
     req.assert_rst = 1'b0;
     req.assert_core_rst = 1'b0;
     req.debug_mode = 1'b0;
+    req.scan_mode = 1'b0;
 
     finish_item(req);
     `uvm_info("KV_RST_CORE_RST", {"Response:",req.convert2string()},UVM_MEDIUM)
diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_debug_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_debug_sequence.svh
index 09869a7b7..129d9fc8b 100644
--- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_debug_sequence.svh
+++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_debug_sequence.svh
@@ -56,6 +56,7 @@ class kv_rst_debug_sequence extends kv_rst_sequence_base;
     req.assert_rst = 1'b0;
     req.assert_core_rst = 1'b0;
     req.debug_mode = 1'b1;
+    req.scan_mode = 1'b0;
     
     finish_item(req);
     `uvm_info("KV_RST_DEBUG", {"Response:",req.convert2string()},UVM_MEDIUM)
@@ -70,6 +71,7 @@ class kv_rst_debug_sequence extends kv_rst_sequence_base;
     req.assert_rst = 1'b0;
     req.assert_core_rst = 1'b0;
     req.debug_mode = 1'b0;
+    req.scan_mode = 1'b0;
     
     finish_item(req);
     `uvm_info("KV_RST_DEBUG", {"Response:",req.convert2string()},UVM_MEDIUM)
diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_driver_bfm.sv b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_driver_bfm.sv
index 961f86bfd..8e81c2500 100644
--- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_driver_bfm.sv
+++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_driver_bfm.sv
@@ -112,8 +112,12 @@ end
   reg  rst_b_o = 'bz;
   tri  core_only_rst_b_i;
   reg  core_only_rst_b_o = 'bz;
+  tri  fw_update_rst_window_i;
+  reg  fw_update_rst_window_o = 'bz;
   tri  debug_locked_i;
   reg  debug_locked_o = 'bz;
+  tri  cptra_in_debug_scan_mode_i;
+  reg  cptra_in_debug_scan_mode_o = 'bz;
 
   // Bi-directional signals
   
@@ -133,8 +137,12 @@ end
   assign rst_b_i = bus.rst_b;
   assign bus.core_only_rst_b = (initiator_responder == INITIATOR) ? core_only_rst_b_o : 'bz;
   assign core_only_rst_b_i = bus.core_only_rst_b;
+  assign bus.fw_update_rst_window = (initiator_responder == INITIATOR) ? fw_update_rst_window_o : 'bz;
+  assign fw_update_rst_window_i = bus.fw_update_rst_window;
   assign bus.debug_locked = (initiator_responder == INITIATOR) ? debug_locked_o : 'bz;
   assign debug_locked_i = bus.debug_locked;
+  assign bus.cptra_in_debug_scan_mode = (initiator_responder == INITIATOR) ? cptra_in_debug_scan_mode_o : 'bz;
+  assign cptra_in_debug_scan_mode_i = bus.cptra_in_debug_scan_mode;
 
   // Proxy handle to UVM driver
   kv_rst_pkg::kv_rst_driver   proxy;
@@ -169,7 +177,9 @@ end
        cptra_pwrgood_o <= 'bz;
        rst_b_o <= 'bz;
        core_only_rst_b_o <= 'bz;
+       fw_update_rst_window_o <= 'bz;
        debug_locked_o <= 'b1;
+       cptra_in_debug_scan_mode_o <= 'b0;
        // Bi-directional signals
  
      end    
@@ -244,12 +254,19 @@ end
     
     if (initiator_struct.assert_rst)
       rst_b_o <= 1'b0;
+    if (initiator_struct.assert_core_rst)
+      fw_update_rst_window_o <= 1'b1;
     if (initiator_struct.assert_core_rst)
       core_only_rst_b_o <= 1'b0;
     if (!initiator_struct.set_pwrgood)
       cptra_pwrgood_o <= 1'b0;
     if (initiator_struct.debug_mode)
       debug_locked_o <= 1'b1;
+    if (initiator_struct.debug_mode | initiator_struct.scan_mode)
+      cptra_in_debug_scan_mode_o <= 1'b1;
+    else
+      cptra_in_debug_scan_mode_o <= 1'b0;
+    
     
     // Wait for the responder to complete the transfer then place the responder data into 
     // kv_rst_responder_struct.
@@ -257,6 +274,8 @@ end
     @(posedge clk_i);
     if (!initiator_struct.assert_rst)
       rst_b_o <= 1'b1;
+    if (!initiator_struct.assert_core_rst)
+      fw_update_rst_window_o <= 1'b0;
     if (!initiator_struct.assert_core_rst)
       core_only_rst_b_o <= 1'b1;
     if (initiator_struct.set_pwrgood)
@@ -270,6 +289,7 @@ end
     kv_rst_responder_struct.assert_rst = !rst_b_i;
     kv_rst_responder_struct.assert_core_rst = !core_only_rst_b_i;
     kv_rst_responder_struct.debug_mode = debug_locked_i;
+    kv_rst_responder_struct.scan_mode = cptra_in_debug_scan_mode_i & !debug_locked_i;
     responder_struct = kv_rst_responder_struct;
   endtask        
 // pragma uvmf custom initiate_and_get_response end
diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_if.sv b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_if.sv
index 3073307be..e9fc3aafd 100644
--- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_if.sv
+++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_if.sv
@@ -37,6 +37,7 @@
 // .dut_signal_port(kv_rst_bus.rst_b), // Agent output 
 // .dut_signal_port(kv_rst_bus.core_only_rst_b), // Agent output 
 // .dut_signal_port(kv_rst_bus.debug_locked), // Agent output 
+// .dut_signal_port(kv_rst_bus.cptra_in_debug_scan_mode), // Agent output 
 
 import uvmf_base_pkg_hdl::*;
 import kv_rst_pkg_hdl::*;
@@ -49,7 +50,9 @@ interface  kv_rst_if
   inout tri  cptra_pwrgood,
   inout tri  rst_b,
   inout tri  core_only_rst_b,
-  inout tri  debug_locked
+  inout tri  fw_update_rst_window,
+  inout tri  debug_locked,
+  inout tri  cptra_in_debug_scan_mode
   );
 
 modport monitor_port 
@@ -59,7 +62,9 @@ modport monitor_port
   input cptra_pwrgood,
   input rst_b,
   input core_only_rst_b,
-  input debug_locked
+  input fw_update_rst_window,
+  input debug_locked,
+  input cptra_in_debug_scan_mode
   );
 
 modport initiator_port 
@@ -69,7 +74,9 @@ modport initiator_port
   output cptra_pwrgood,
   output rst_b,
   output core_only_rst_b,
-  output debug_locked
+  output fw_update_rst_window,
+  output debug_locked,
+  output cptra_in_debug_scan_mode
   );
 
 modport responder_port 
@@ -79,7 +86,9 @@ modport responder_port
   input cptra_pwrgood,
   input rst_b,
   input core_only_rst_b,
-  input debug_locked
+  input fw_update_rst_window,
+  input debug_locked, 
+  input cptra_in_debug_scan_mode
   );
   
 
diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_macros.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_macros.svh
index 51aa84b58..2cdcba5c9 100644
--- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_macros.svh
+++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_macros.svh
@@ -68,6 +68,7 @@ typedef struct packed  { \
   bit assert_core_rst ; \
   int unsigned wait_cycles ; \
   bit debug_mode ; \
+  bit scan_mode ; \
      } kv_rst_monitor_s;
 
   `define kv_rst_TO_MONITOR_STRUCT_FUNCTION \
@@ -78,7 +79,8 @@ typedef struct packed  { \
             this.assert_rst , \
             this.assert_core_rst , \
             this.wait_cycles , \
-            this.debug_mode  \
+            this.debug_mode , \
+            this.scan_mode  \
             };\
     return ( kv_rst_monitor_struct);\
   endfunction\
@@ -90,7 +92,8 @@ typedef struct packed  { \
             this.assert_rst , \
             this.assert_core_rst , \
             this.wait_cycles , \
-            this.debug_mode  \
+            this.debug_mode , \
+            this.scan_mode  \
             } = kv_rst_monitor_struct;\
   endfunction
 
@@ -105,6 +108,7 @@ typedef struct packed  { \
   bit assert_core_rst ; \
   int unsigned wait_cycles ; \
   bit debug_mode ; \
+  bit scan_mode ; \
      } kv_rst_initiator_s;
 
   `define kv_rst_TO_INITIATOR_STRUCT_FUNCTION \
@@ -115,7 +119,8 @@ typedef struct packed  { \
            this.assert_rst , \
            this.assert_core_rst , \
            this.wait_cycles , \
-           this.debug_mode  \
+           this.debug_mode , \
+           this.scan_mode  \
            };\
     return ( kv_rst_initiator_struct);\
   endfunction
@@ -127,7 +132,8 @@ typedef struct packed  { \
            this.assert_rst , \
            this.assert_core_rst , \
            this.wait_cycles , \
-           this.debug_mode  \
+           this.debug_mode , \
+           this.scan_mode  \
            } = kv_rst_initiator_struct;\
   endfunction
 
@@ -142,6 +148,7 @@ typedef struct packed  { \
   bit assert_core_rst ; \
   int unsigned wait_cycles ; \
   bit debug_mode ; \
+  bit scan_mode ; \
      } kv_rst_responder_s;
 
   `define kv_rst_TO_RESPONDER_STRUCT_FUNCTION \
@@ -152,7 +159,8 @@ typedef struct packed  { \
            this.assert_rst , \
            this.assert_core_rst , \
            this.wait_cycles , \
-           this.debug_mode  \
+           this.debug_mode , \
+           this.scan_mode  \
            };\
     return ( kv_rst_responder_struct);\
   endfunction
@@ -164,7 +172,8 @@ typedef struct packed  { \
            this.assert_rst , \
            this.assert_core_rst , \
            this.wait_cycles , \
-           this.debug_mode  \
+           this.debug_mode , \
+           this.scan_mode  \
            } = kv_rst_responder_struct;\
   endfunction
 // pragma uvmf custom additional begin
diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_monitor_bfm.sv b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_monitor_bfm.sv
index 5d17716e2..2d27cd624 100644
--- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_monitor_bfm.sv
+++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_monitor_bfm.sv
@@ -86,13 +86,17 @@ end
   tri  cptra_pwrgood_i;
   tri  rst_b_i;
   tri  core_only_rst_b_i;
+  tri  fw_update_rst_window_i;
   tri  debug_locked_i;
+  tri  cptra_in_debug_scan_mode_i;
   assign clk_i = bus.clk;
   assign dummy_i = bus.dummy;
   assign cptra_pwrgood_i = bus.cptra_pwrgood;
   assign rst_b_i = bus.rst_b;
   assign core_only_rst_b_i = bus.core_only_rst_b;
+  assign fw_update_rst_window_i = bus.fw_update_rst_window;
   assign debug_locked_i = bus.debug_locked;
+  assign cptra_in_debug_scan_mode_i = bus.cptra_in_debug_scan_mode;
 
   // Proxy handle to UVM monitor
   kv_rst_pkg::kv_rst_monitor  proxy;
@@ -102,14 +106,18 @@ end
     reg cptra_pwrgood_o = 'b0;
     reg rst_b_o = 'b0;
     reg core_only_rst_b_o = 'b0;
+    reg fw_update_rst_window_o = 'b0;
     reg debug_locked_o = 'b0;
+    reg cptra_in_debug_scan_mode_o = 'b0;
 
     function bit any_signal_changed();
 
       return  |(cptra_pwrgood_i ^ cptra_pwrgood_o) ||
               |(rst_b_i ^ rst_b_o) ||
               |(core_only_rst_b_i ^ core_only_rst_b_o) ||
-              |(debug_locked_i ^ debug_locked_o);
+              |(fw_update_rst_window_i ^ fw_update_rst_window_o) ||
+              |(debug_locked_i ^ debug_locked_o) ||
+              |(cptra_in_debug_scan_mode_i ^ cptra_in_debug_scan_mode_o);
   
     endfunction
 
@@ -191,7 +199,8 @@ end
     //      kv_rst_monitor_struct.xyz = cptra_pwrgood_i;  //     
     //      kv_rst_monitor_struct.xyz = rst_b_i;  //     
     //      kv_rst_monitor_struct.xyz = core_only_rst_b_i;  //     
-    //      kv_rst_monitor_struct.xyz = debug_locked_i;  //     
+    //      kv_rst_monitor_struct.xyz = debug_locked_i;  // 
+    //      kv_rst_monitor_struct.xyz = cptra_in_debug_scan_mode_i;  // 
     // pragma uvmf custom do_monitor begin
     // UVMF_CHANGE_ME : Implement protocol monitoring.  The commented reference code 
     // below are examples of how to capture signal values and assign them to 
@@ -202,16 +211,19 @@ end
     // the next transfer. One clock cycle is consumed between calls to do_monitor.
     while (!any_signal_changed()) @(posedge clk_i);
 
-    cptra_pwrgood_o <= cptra_pwrgood_i;
-    rst_b_o         <= rst_b_i;
-    core_only_rst_b_o         <= core_only_rst_b_i;
-    debug_locked_o  <= debug_locked_i;
+    cptra_pwrgood_o        <= cptra_pwrgood_i;
+    rst_b_o                <= rst_b_i;
+    core_only_rst_b_o      <= core_only_rst_b_i;
+    fw_update_rst_window_o <= fw_update_rst_window_i;
+    debug_locked_o         <= debug_locked_i;
+    cptra_in_debug_scan_mode_o <= cptra_in_debug_scan_mode_i;
 
     kv_rst_monitor_struct.set_pwrgood = cptra_pwrgood_i;
     kv_rst_monitor_struct.assert_rst = !rst_b_i;
     kv_rst_monitor_struct.assert_core_rst = !core_only_rst_b_i;
     kv_rst_monitor_struct.wait_cycles = 0;
     kv_rst_monitor_struct.debug_mode = debug_locked_i;
+    kv_rst_monitor_struct.scan_mode = cptra_in_debug_scan_mode_i & !debug_locked_i;
     // pragma uvmf custom do_monitor end
   endtask         
   
diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_poweron_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_poweron_sequence.svh
index 66f53ec66..8d0fa8c15 100644
--- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_poweron_sequence.svh
+++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_poweron_sequence.svh
@@ -56,6 +56,7 @@ class kv_rst_poweron_sequence extends kv_rst_sequence_base;
     req.assert_rst = 1'b1;
     req.assert_core_rst = 1'b1;
     req.debug_mode = 1'b0;
+    req.scan_mode = 1'b0;
     finish_item(req);
     `uvm_info("KV_RST_POWERON", {"Response:",req.convert2string()},UVM_MEDIUM)
     
@@ -69,6 +70,7 @@ class kv_rst_poweron_sequence extends kv_rst_sequence_base;
     req.assert_rst = 1'b1;
     req.assert_core_rst = 1'b1;
     req.debug_mode = 1'b0;
+    req.scan_mode = 1'b0;
     finish_item(req);
     `uvm_info("KV_RST_POWERON", {"Response:",req.convert2string()},UVM_MEDIUM)
 
@@ -82,6 +84,7 @@ class kv_rst_poweron_sequence extends kv_rst_sequence_base;
     req.assert_rst = 1'b0;
     req.assert_core_rst = 1'b0;
     req.debug_mode = 1'b0;
+    req.scan_mode = 1'b0;
     finish_item(req);
     `uvm_info("KV_RST_POWERON", {"Response:",req.convert2string()},UVM_MEDIUM)
 
diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_transaction.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_transaction.svh
index 0ed69e68e..fdbcca661 100644
--- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_transaction.svh
+++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_transaction.svh
@@ -37,6 +37,7 @@ class kv_rst_transaction  extends uvmf_transaction_base;
   bit assert_core_rst ;
   rand int unsigned wait_cycles ;
   rand bit debug_mode ;
+  rand bit scan_mode ;
 
   //Constraints for the transaction variables:
   constraint wait_cycles_c { wait_cycles dist {[1:25] := 80, [25:100] := 15, [100:500] := 5}; }
@@ -120,7 +121,7 @@ class kv_rst_transaction  extends uvmf_transaction_base;
   virtual function string convert2string();
     // pragma uvmf custom convert2string begin
     // UVMF_CHANGE_ME : Customize format if desired.
-    return $sformatf("set_pwrgood:0x%x assert_rst:0x%x assert_core_rst:0x%x wait_cycles:0x%x debug_mode:0x%x",set_pwrgood,assert_rst,assert_core_rst,wait_cycles,debug_mode);
+    return $sformatf("set_pwrgood:0x%x assert_rst:0x%x assert_core_rst:0x%x wait_cycles:0x%x debug_mode:0x%x scan_mode: 0x%x",set_pwrgood,assert_rst,assert_core_rst,wait_cycles,debug_mode,scan_mode);
     // pragma uvmf custom convert2string end
   endfunction
 
@@ -167,6 +168,7 @@ class kv_rst_transaction  extends uvmf_transaction_base;
     this.assert_core_rst = RHS.assert_core_rst;
     this.wait_cycles = RHS.wait_cycles;
     this.debug_mode = RHS.debug_mode;
+    this.scan_mode = RHS.scan_mode;
     // pragma uvmf custom do_copy end
   endfunction
 
diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_transaction_coverage.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_transaction_coverage.svh
index 48c717306..025bfaad1 100644
--- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_transaction_coverage.svh
+++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_transaction_coverage.svh
@@ -48,10 +48,15 @@ class kv_rst_transaction_coverage  extends uvm_subscriber #(.T(kv_rst_transactio
     assert_core_rst: coverpoint coverage_trans.assert_core_rst;
     //wait_cycles: coverpoint coverage_trans.wait_cycles;
     debug_mode: coverpoint coverage_trans.debug_mode;
+    // scan_mode: coverpoint coverage_trans.scan_mode;
 
     warm_rstXdbg: cross assert_rst, debug_mode;
     cold_rstXdbg: cross set_pwrgood, debug_mode;
     core_rstXdbg: cross assert_core_rst, debug_mode;
+
+    // warm_rstXscan: cross assert_rst, scan_mode;
+    // cold_rstXscan: cross set_pwrgood, scan_mode;
+    // core_rstXscan: cross assert_core_rst, scan_mode;
     // pragma uvmf custom covergroup end
   endgroup
 
diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_warm_rst_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_warm_rst_sequence.svh
index 4dc4e3f7b..8bc89e23d 100644
--- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_warm_rst_sequence.svh
+++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_warm_rst_sequence.svh
@@ -56,6 +56,7 @@ class kv_rst_warm_rst_sequence extends kv_rst_sequence_base;
     req.assert_rst = 1'b1;
     req.assert_core_rst = 1'b1;
     req.debug_mode = 1'b0;
+    req.scan_mode = 1'b0;
 
     finish_item(req);
     `uvm_info("KV_RST_WARM_RST", {"Response:",req.convert2string()},UVM_MEDIUM)
@@ -70,6 +71,7 @@ class kv_rst_warm_rst_sequence extends kv_rst_sequence_base;
     req.assert_rst = 1'b0;
     req.assert_core_rst = 1'b0;
     req.debug_mode = 1'b0;
+    req.scan_mode = 1'b0;
 
     finish_item(req);
     `uvm_info("KV_RST_WARM_RST", {"Response:",req.convert2string()},UVM_MEDIUM)
diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/yaml/kv_rst_interface.yaml b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/yaml/kv_rst_interface.yaml
index 0fcb48a9d..977f71987 100644
--- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/yaml/kv_rst_interface.yaml
+++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/yaml/kv_rst_interface.yaml
@@ -28,6 +28,10 @@ uvmf:
         name: debug_locked
         reset_value: '''bz'
         width: '1'
+      - dir: output
+        name: cptra_in_debug_scan_mode
+        reset_value: '''bz'
+        width: '1'
       reset: dummy
       reset_assertion_level: 'False'
       transaction_constraints:
@@ -65,4 +69,10 @@ uvmf:
         name: debug_mode
         type: bit
         unpacked_dimension: ''
+      - comment: ''
+        iscompare: 'False'
+        isrand: 'False'
+        name: scan_mode
+        type: bit
+        unpacked_dimension: ''
       use_dpi_link: 'False'
diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_write_pkg/src/kv_write_monitor_bfm.sv b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_write_pkg/src/kv_write_monitor_bfm.sv
index 72e944f66..8fd65c003 100644
--- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_write_pkg/src/kv_write_monitor_bfm.sv
+++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_write_pkg/src/kv_write_monitor_bfm.sv
@@ -234,7 +234,6 @@ end
     kv_write_monitor_struct.write_dest_valid  = write_dest_valid_o; //kv_write_i[46:41];
     kv_write_monitor_struct.error             = error_o;
 
-
     // pragma uvmf custom do_monitor end
   endtask         
   
diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_write_pkg/src/kv_write_transaction.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_write_pkg/src/kv_write_transaction.svh
index 3a79a1432..3744645df 100644
--- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_write_pkg/src/kv_write_transaction.svh
+++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_write_pkg/src/kv_write_transaction.svh
@@ -44,7 +44,7 @@ class kv_write_transaction #(
   logic error;
 
   //Constraints for the transaction variables:
-  constraint dest_valid_c { if (KV_WRITE_REQUESTOR inside {"ECC", "HMAC", "DOE", "SHA512"}) write_dest_valid == 31; }
+  constraint dest_valid_c {0 <= write_dest_valid <= 31;} //{ if (KV_WRITE_REQUESTOR inside {"ECC", "HMAC", "DOE", "SHA512"}) write_dest_valid == 31; }
   constraint write_en_c {write_en == 1'b1;}
   constraint write_offset_c {write_offset >= 0; write_offset < 12;}
   // pragma uvmf custom class_item_additional begin
@@ -126,7 +126,7 @@ class kv_write_transaction #(
   virtual function string convert2string();
     // pragma uvmf custom convert2string begin
     // UVMF_CHANGE_ME : Customize format if desired.
-    return $sformatf("write_en:0x%x write_entry:0x%x write_offset: 0x%x write_data:0x%x write_dest_valid:0x%x error:0x%x",write_en,write_entry,write_offset,write_data,write_dest_valid,error);
+    return $sformatf("write_en:0x%x write_entry:0x%x write_offset: 0x%x write_data:0x%x write_dest_valid:0x%x write_resp_err:0x%x",write_en,write_entry,write_offset,write_data,write_dest_valid,error);
     // pragma uvmf custom convert2string end
   endfunction
 
diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_write_pkg/src/kv_write_transaction_coverage.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_write_pkg/src/kv_write_transaction_coverage.svh
index 25bf94115..4ab8d7496 100644
--- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_write_pkg/src/kv_write_transaction_coverage.svh
+++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_write_pkg/src/kv_write_transaction_coverage.svh
@@ -28,6 +28,16 @@
 //----------------------------------------------------------------------
 //----------------------------------------------------------------------
 //
+
+// covergroup data_bit_cg(input logic data_bit);
+//   option.per_instance = 1;
+//   value: coverpoint data_bit;
+//   transition:  coverpoint data_bit {
+//     bins bin01 = (0 => 1); 
+//     bins bin10 = (1 => 0);
+//   }
+// endgroup
+
 class kv_write_transaction_coverage #(
       string KV_WRITE_REQUESTOR = "HMAC"
       )
@@ -42,8 +52,12 @@ class kv_write_transaction_coverage #(
 )
 
   T coverage_trans;
+  
 
   // pragma uvmf custom class_item_additional begin
+  // data_bit_cg wr_data_bus[KV_DATA_W];
+  // data_bit_cg dest_valid_bus[KV_NUM_READ];
+    
   // pragma uvmf custom class_item_additional end
   
   // ****************************************************************************
@@ -54,11 +68,9 @@ class kv_write_transaction_coverage #(
     option.per_instance=1;
     write_en: coverpoint coverage_trans.write_en;
     write_entry: coverpoint coverage_trans.write_entry;
-    //write_data: coverpoint coverage_trans.write_data;
     write_offset: coverpoint coverage_trans.write_offset {
       illegal_bins wr_offset_12_15 = {['d12:'d15]};
     }
-    //write_dest_valid: coverpoint coverage_trans.write_dest_valid; //TODO
     error: coverpoint coverage_trans.error;
     // pragma uvmf custom covergroup end
   endgroup
@@ -70,16 +82,11 @@ class kv_write_transaction_coverage #(
   function new(string name="", uvm_component parent=null);
     super.new(name,parent);
     kv_write_transaction_cg=new;
+    // key_ctrl_cg = new;
     //`uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging.  Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup.  Remove this warning after the covergroup has been reviewed.")
   endfunction
 
-  // ****************************************************************************
-  // FUNCTION : build_phase()
-  // This function is the standard UVM build_phase.
-  //
-  function void build_phase(uvm_phase phase);
-    kv_write_transaction_cg.set_inst_name($sformatf("kv_write_transaction_cg_%s",get_full_name()));
-  endfunction
+  
 
   // ****************************************************************************
   // FUNCTION: write (T t)
@@ -90,7 +97,25 @@ class kv_write_transaction_coverage #(
   virtual function void write (T t);
     `uvm_info("COV","Received transaction",UVM_HIGH);
     coverage_trans = t;
+
+    // foreach(wr_data_bus[i]) wr_data_bus[i] = new(coverage_trans.write_data[i]);
+    // foreach(wr_data_bus[i]) wr_data_bus[i].set_inst_name($sformatf("wr_data_bus[%0d]_%s",i,get_full_name()));
+
+    // foreach(dest_valid_bus[i]) dest_valid_bus[i] = new(coverage_trans.write_dest_valid[i]);
+    // foreach(dest_valid_bus[i]) dest_valid_bus[i].set_inst_name($sformatf("dest_valid_bus[%0d]_%s",i,get_full_name()));
+
     kv_write_transaction_cg.sample();
+    // foreach(wr_data_bus[i]) wr_data_bus[i].sample();
+    // foreach(dest_valid_bus[i]) dest_valid_bus[i].sample();
+
+  endfunction
+
+  // ****************************************************************************
+  // FUNCTION : build_phase()
+  // This function is the standard UVM build_phase.
+  //
+  function void build_phase(uvm_phase phase);
+    kv_write_transaction_cg.set_inst_name($sformatf("kv_write_transaction_cg_%s",get_full_name()));
   endfunction
 
 endclass
diff --git a/src/kmac/config/compile.yml b/src/kmac/config/compile.yml
index c6205ec1d..7280c6a78 100644
--- a/src/kmac/config/compile.yml
+++ b/src/kmac/config/compile.yml
@@ -11,7 +11,7 @@ provides: [kmac]
 schema_version: 2.4.0
 requires:
   - kmac_pkg
-  - prim_pkg
+  - caliptra_prim_pkg
   - lc_ctrl_pkg
 targets:
   rtl:
diff --git a/src/kmac/config/kmac.vf b/src/kmac/config/kmac.vf
index 03fb36cc7..21bfb92e0 100644
--- a/src/kmac/config/kmac.vf
+++ b/src/kmac/config/kmac.vf
@@ -1,12 +1,13 @@
-+incdir+${CALIPTRA_ROOT}/src/prim/rtl
++incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl
 +incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl
 +incdir+${CALIPTRA_ROOT}/src/kmac/rtl
-${CALIPTRA_ROOT}/src/prim/rtl/prim_util_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_alert_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_mubi_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_cipher_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv
 ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv
 ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv
diff --git a/src/kmac/rtl/keccak_2share.sv b/src/kmac/rtl/keccak_2share.sv
index e71d6193c..e93d83f08 100644
--- a/src/kmac/rtl/keccak_2share.sv
+++ b/src/kmac/rtl/keccak_2share.sv
@@ -5,10 +5,10 @@
 // This module is the single round keccak permutation module
 // It supports Keccak with up to 1600b of state
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
 module keccak_2share
-  import prim_mubi_pkg::*;
+  import caliptra_prim_mubi_pkg::*;
 #(
   parameter int Width = 1600, // b= {25, 50, 100, 200, 400, 800, 1600}
 
@@ -315,7 +315,7 @@ module keccak_2share
       assign in_prd[x] = in_rand_ext ? rand_i[x * WSheetHalf +: WSheetHalf] :
                                        out_prd[rot_int(x, 5)];
 
-      prim_dom_and_2share #(
+      caliptra_prim_dom_and_2share #(
         .DW (WSheetHalf), // a half sheet
         .Pipeline(1) // Process the full sheet in 3 clock cycles. This reduces
                      // SCA leakage.
diff --git a/src/kmac/rtl/keccak_round.sv b/src/kmac/rtl/keccak_round.sv
index 0e91f2f2e..3fd223d9a 100644
--- a/src/kmac/rtl/keccak_round.sv
+++ b/src/kmac/rtl/keccak_round.sv
@@ -5,10 +5,10 @@
 // Keccak full round logic based on given input `Width`
 // e.g. Width 800 requires 22 rounds
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
 module keccak_round
-  import prim_mubi_pkg::*;
+  import caliptra_prim_mubi_pkg::*;
 #(
   parameter int Width = 1600, // b= {25, 50, 100, 200, 400, 800, 1600}
 
@@ -55,13 +55,13 @@ module keccak_round
   // Errors:
   //  sparse_fsm_error: Checking if FSM state falls into unknown value
   output logic             sparse_fsm_error_o,
-  //  round_count_error: prim_count checks round value consistency
+  //  round_count_error: caliptra_prim_count checks round value consistency
   output logic             round_count_error_o,
   //  rst_storage_error: check if reset signal asserted out of the
   //                     permitted window
   output logic             rst_storage_error_o,
 
-  input  prim_mubi_pkg::mubi4_t clear_i     // Clear internal state to '0
+  input  caliptra_prim_mubi_pkg::mubi4_t clear_i     // Clear internal state to '0
 );
 
   /////////////////////
@@ -188,7 +188,7 @@ module keccak_round
       StTerminalError = 6'b110110
   } keccak_st_e;
   keccak_st_e keccak_st, keccak_st_d;
-  `PRIM_FLOP_SPARSE_FSM(u_state_regs, keccak_st_d, keccak_st, keccak_st_e, StIdle)
+  `CALIPTRA_PRIM_FLOP_SPARSE_FSM(u_state_regs, keccak_st_d, keccak_st, keccak_st_e, StIdle)
 
   // Next state logic and output logic
   // SEC_CM: FSM.SPARSE
@@ -220,7 +220,7 @@ module keccak_round
 
           xor_message    = 1'b 1;
           update_storage = 1'b 1;
-        end else if (prim_mubi_pkg::mubi4_test_true_strict(clear_i)) begin
+        end else if (caliptra_prim_mubi_pkg::mubi4_test_true_strict(clear_i)) begin
           // Opt1. State machine allows resetting the storage only in Idle
           // Opt2. storage resets regardless of states but clear_i
           // Both are added in the design at this time. Will choose the
@@ -368,9 +368,9 @@ module keccak_round
 
   // SEC_CM: LOGIC.INTEGRITY
   logic rst_n;
-  prim_sec_anchor_buf #(
+  caliptra_prim_sec_anchor_buf #(
    .Width(1)
-  ) u_prim_sec_anchor_buf (
+  ) u_caliptra_prim_sec_anchor_buf (
     .in_i(rst_ni),
     .out_o(rst_n)
   );
@@ -422,7 +422,7 @@ module keccak_round
     if (rst_storage) begin
       // FSM should be in StIdle and clear_i should be high
       if ((keccak_st != StIdle) ||
-        prim_mubi_pkg::mubi4_test_false_loose(clear_i)) begin
+        caliptra_prim_mubi_pkg::mubi4_test_false_loose(clear_i)) begin
         rst_storage_error = 1'b 1;
       end
     end
@@ -460,7 +460,7 @@ module keccak_round
   // Round number
   // This primitive is used to place a hardened counter
   // SEC_CM: CTR.REDUN
-  prim_count #(
+  caliptra_prim_count #(
     .Width(RndW)
   ) u_round_count (
     .clk_i,
@@ -503,7 +503,7 @@ module keccak_round
 
   // clear_i is assumed to be asserted in Idle state
   `CALIPTRA_ASSUME(ClearAssertStIdle_A,
-    prim_mubi_pkg::mubi4_test_true_strict(clear_i)
+    caliptra_prim_mubi_pkg::mubi4_test_true_strict(clear_i)
      |-> keccak_st == StIdle, clk_i, !rst_ni)
 
   // EnMasking controls the valid states
diff --git a/src/kmac/rtl/sha3.sv b/src/kmac/rtl/sha3.sv
index 82f6afdd1..3abc5e824 100644
--- a/src/kmac/rtl/sha3.sv
+++ b/src/kmac/rtl/sha3.sv
@@ -6,7 +6,7 @@
 //
 // It instantiates a keccak_round with 1600 bits of the state.
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
 module sha3
   import sha3_pkg::*;
@@ -47,9 +47,9 @@ module sha3
   // It is used to run additional keccak_f after sponge absorbing is completed.
   // See `keccak_run` signal
   input                        run_i,
-  input prim_mubi_pkg::mubi4_t done_i,    // see sha3pad for details
+  input caliptra_prim_mubi_pkg::mubi4_t done_i,    // see sha3pad for details
 
-  output prim_mubi_pkg::mubi4_t absorbed_o,
+  output caliptra_prim_mubi_pkg::mubi4_t absorbed_o,
   output logic                  squeezing_o,
 
   // Indicate of one block processed. KMAC main state tracks the progression
@@ -106,7 +106,7 @@ module sha3
   // absorbed is a pulse signal that indicates sponge absorbing is done.
   // After this, sha3 core allows software to manually run until squeezing
   // is completed, which is the `done_i` pulse signal.
-  prim_mubi_pkg::mubi4_t absorbed;
+  caliptra_prim_mubi_pkg::mubi4_t absorbed;
 
   // `squeezing` is a status indicator that SHA3 core is in sponge squeezing
   // stage. In this stage, the state output is valid, and software can manually
@@ -124,7 +124,7 @@ module sha3
 
   // Keccak control signal (filtered by State Machine)
   logic keccak_start, keccak_process;
-  prim_mubi_pkg::mubi4_t keccak_done;
+  caliptra_prim_mubi_pkg::mubi4_t keccak_done;
 
   // alert signals
   logic round_count_error, msg_count_error;
@@ -163,7 +163,7 @@ module sha3
   // `absorbed` signal. When this signal goes out, the state is still in
   // `StAbsorb`. Next state is `StSqueeze`.
   always_ff @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) absorbed_o <= prim_mubi_pkg::MuBi4False;
+    if (!rst_ni) absorbed_o <= caliptra_prim_mubi_pkg::MuBi4False;
     else         absorbed_o <= absorbed;
   end
 
@@ -174,7 +174,7 @@ module sha3
   always_ff @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni)        processing <= 1'b 0;
     else if (process_i) processing <= 1'b 1;
-    else if (prim_mubi_pkg::mubi4_test_true_strict(absorbed)) begin
+    else if (caliptra_prim_mubi_pkg::mubi4_test_true_strict(absorbed)) begin
       processing <= 1'b 0;
     end
   end
@@ -192,7 +192,7 @@ module sha3
   ///////////////////
 
   // State Register
-  `PRIM_FLOP_SPARSE_FSM(u_state_regs, st_d, st, sha3_st_sparse_e, StIdle_sparse)
+  `CALIPTRA_PRIM_FLOP_SPARSE_FSM(u_state_regs, st_d, st, sha3_st_sparse_e, StIdle_sparse)
 
 
   // Next State and Output Logic
@@ -208,7 +208,7 @@ module sha3
     keccak_start = 1'b 0;
     keccak_process = 1'b 0;
     sw_keccak_run = 1'b 0;
-    keccak_done = prim_mubi_pkg::MuBi4False;
+    keccak_done = caliptra_prim_mubi_pkg::MuBi4False;
 
     squeezing = 1'b 0;
 
@@ -233,7 +233,7 @@ module sha3
           st_d = StAbsorb_sparse;
 
           keccak_process = 1'b 1;
-        end else if (prim_mubi_pkg::mubi4_test_true_strict(absorbed)) begin
+        end else if (caliptra_prim_mubi_pkg::mubi4_test_true_strict(absorbed)) begin
           st_d = StSqueeze_sparse;
         end else begin
           st_d = StAbsorb_sparse;
@@ -250,7 +250,7 @@ module sha3
           st_d = StManualRun_sparse;
 
           sw_keccak_run = 1'b 1;
-        end else if (prim_mubi_pkg::mubi4_test_true_strict(done_i)) begin
+        end else if (caliptra_prim_mubi_pkg::mubi4_test_true_strict(done_i)) begin
           st_d = StFlush_sparse;
 
           keccak_done = done_i;
@@ -319,7 +319,7 @@ module sha3
     unique case (st)
       StIdle_sparse: begin
         if (process_i || run_i ||
-          prim_mubi_pkg::mubi4_test_true_loose(done_i)) begin
+          caliptra_prim_mubi_pkg::mubi4_test_true_loose(done_i)) begin
           error_o = '{
             valid: 1'b 1,
             code: ErrSha3SwControl,
@@ -329,7 +329,7 @@ module sha3
       end
 
       StAbsorb_sparse: begin
-        if (start_i || run_i || prim_mubi_pkg::mubi4_test_true_loose(done_i)
+        if (start_i || run_i || caliptra_prim_mubi_pkg::mubi4_test_true_loose(done_i)
           || (process_i && processing)) begin
           error_o = '{
             valid: 1'b 1,
@@ -351,7 +351,7 @@ module sha3
 
       StManualRun_sparse: begin
         if (start_i || process_i || run_i ||
-          prim_mubi_pkg::mubi4_test_true_loose(done_i)) begin
+          caliptra_prim_mubi_pkg::mubi4_test_true_loose(done_i)) begin
           error_o = '{
             valid: 1'b 1,
             code: ErrSha3SwControl,
@@ -362,7 +362,7 @@ module sha3
 
       StFlush_sparse: begin
         if (start_i || process_i || run_i ||
-          prim_mubi_pkg::mubi4_test_true_loose(done_i)) begin
+          caliptra_prim_mubi_pkg::mubi4_test_true_loose(done_i)) begin
           error_o = '{
             valid: 1'b 1,
             code: ErrSha3SwControl,
diff --git a/src/kmac/rtl/sha3pad.sv b/src/kmac/rtl/sha3pad.sv
index 9eb0e69f4..a8c488858 100644
--- a/src/kmac/rtl/sha3pad.sv
+++ b/src/kmac/rtl/sha3pad.sv
@@ -4,7 +4,7 @@
 //
 // SHA3 padding logic
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
 module sha3pad
   import sha3_pkg::*;
@@ -55,12 +55,12 @@ module sha3pad
   // done_i is a pulse signal to make the pad logic to clear internal variables
   // and to move back to the Idle state for next hashing process.
   // done_i may not needed if sw controls the keccak_round directly.
-  input prim_mubi_pkg::mubi4_t done_i,
+  input caliptra_prim_mubi_pkg::mubi4_t done_i,
 
   // Indication of the Keccak Sponge Absorbing is complete, it is time for SW to
   // control the Keccak-round if it needs more digest, or complete by asserting
   // `done_i`
-  output prim_mubi_pkg::mubi4_t absorbed_o,
+  output caliptra_prim_mubi_pkg::mubi4_t absorbed_o,
 
   // Life cycle
   input  lc_ctrl_pkg::lc_tx_t lc_escalate_en_i,
@@ -105,7 +105,7 @@ module sha3pad
     // (SHA3, SHAKE), sending prefix is not needed. FSM moves from Idle to
     // Message directly in that case.
     //
-    // As prim_slicer is instantiated, zerofill after the actual prefix is done
+    // As caliptra_prim_slicer is instantiated, zerofill after the actual prefix is done
     // by the module.
     StPrefix = 7'b0111100,
     StPrefixWait =7'b1001100,
@@ -188,7 +188,7 @@ module sha3pad
 
   // This primitive is used to place a hardened counter
   // SEC_CM: CTR.REDUN
-  prim_count #(
+  caliptra_prim_count #(
     .Width(KeccakCountW)
   ) u_sentmsg_count (
     .clk_i,
@@ -267,7 +267,7 @@ module sha3pad
       process_latched <= 1'b 0;
     end else if (process_i) begin
       process_latched <= 1'b 1;
-    end else if (prim_mubi_pkg::mubi4_test_true_strict(done_i)) begin
+    end else if (caliptra_prim_mubi_pkg::mubi4_test_true_strict(done_i)) begin
       process_latched <= 1'b0;
     end
   end
@@ -275,7 +275,7 @@ module sha3pad
   // State Register ===========================================================
   pad_st_e st, st_d;
 
-  `PRIM_FLOP_SPARSE_FSM(u_state_regs, st_d, st, pad_st_e, StPadIdle)
+  `CALIPTRA_PRIM_FLOP_SPARSE_FSM(u_state_regs, st_d, st, pad_st_e, StPadIdle)
 
   // `end_of_block` indicates current beat is end of the block
   // It shall set when the address reaches to the end of the block. End address
@@ -287,9 +287,9 @@ module sha3pad
 
   // Next logic and output logic ==============================================
   // SEC_CM: ABSORBED.CTRL.MUBI
-  prim_mubi_pkg::mubi4_t absorbed_d;
+  caliptra_prim_mubi_pkg::mubi4_t absorbed_d;
   always_ff @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) absorbed_o <= prim_mubi_pkg::MuBi4False;
+    if (!rst_ni) absorbed_o <= caliptra_prim_mubi_pkg::MuBi4False;
     else         absorbed_o <= absorbed_d;
   end
 
@@ -308,7 +308,7 @@ module sha3pad
     en_msgbuf = 1'b 0;
     clr_msgbuf = 1'b 0;
 
-    absorbed_d = prim_mubi_pkg::MuBi4False;
+    absorbed_d = caliptra_prim_mubi_pkg::MuBi4False;
 
     sparse_fsm_error_o = 1'b 0;
 
@@ -468,7 +468,7 @@ module sha3pad
         if (keccak_complete_i) begin
           st_d = StPadIdle;
 
-          absorbed_d = prim_mubi_pkg::MuBi4True;
+          absorbed_d = caliptra_prim_mubi_pkg::MuBi4True;
         end else begin
           st_d = StPadFlush;
         end
@@ -521,7 +521,7 @@ module sha3pad
   logic [MsgWidth-1:0] prefix_sliced;
   logic [MsgWidth-1:0] prefix_data [Share];
 
-  prim_slicer #(
+  caliptra_prim_slicer #(
     .InW (PrefixSize*8),
     .IndexW(KeccakMsgAddrW),
     .OutW(MsgWidth)
@@ -622,19 +622,19 @@ module sha3pad
     endcase
   end
 
-  // prim_packer : packing to 64bit to update keccak storage
-  // two prim_packer in this module are used to pack the data received from
+  // caliptra_prim_packer : packing to 64bit to update keccak storage
+  // two caliptra_prim_packer in this module are used to pack the data received from
   // upper layer (KMAC core) and also the 5bit padding bits.
   // It is assumed that the message from upper layer could be partial at the
   // end of the message. Then the 2 or 4bit padding is required. It can be
-  // handled by some custom logic or could be done by prim_packer.
-  // If packer is used, the MSG_FIFO doesn't have to have another prim_packer
+  // handled by some custom logic or could be done by caliptra_prim_packer.
+  // If packer is used, the MSG_FIFO doesn't have to have another caliptra_prim_packer
   // in front of the FIFO. This logic can handle the partial writes from the
   // software.
   //
-  // If a custom logic is implemented here, prim_packer is necessary in front
+  // If a custom logic is implemented here, caliptra_prim_packer is necessary in front
   // of the FIFO, as this logic only appends at the end of the message when
-  // `process_i` is asserted. Also, in this case, even prim_packer is not
+  // `process_i` is asserted. Also, in this case, even caliptra_prim_packer is not
   // needed, still 64bit registers to latch the partial write is required.
   // If not, the logic has to delay the acceptance of the incoming write
   // accesses. It may trigger the back-pressuring in some case which may result
@@ -747,13 +747,13 @@ module sha3pad
   `CALIPTRA_ASSUME(StartPulse_A, start_i |=> !start_i)
   `CALIPTRA_ASSUME(ProcessPulse_A, process_i |=> !process_i)
   `CALIPTRA_ASSUME(DonePulse_A,
-    prim_mubi_pkg::mubi4_test_true_strict(done_i) |=>
-      prim_mubi_pkg::mubi4_test_false_strict(done_i))
+    caliptra_prim_mubi_pkg::mubi4_test_true_strict(done_i) |=>
+      caliptra_prim_mubi_pkg::mubi4_test_false_strict(done_i))
 
   // CALIPTRA_ASSERT output pulse signals: absorbed_o, keccak_run_o
   `CALIPTRA_ASSERT(AbsorbedPulse_A,
-    prim_mubi_pkg::mubi4_test_true_strict(absorbed_o) |=>
-      prim_mubi_pkg::mubi4_test_false_strict(absorbed_o))
+    caliptra_prim_mubi_pkg::mubi4_test_true_strict(absorbed_o) |=>
+      caliptra_prim_mubi_pkg::mubi4_test_false_strict(absorbed_o))
   `CALIPTRA_ASSERT(KeccakRunPulse_A, keccak_run_o |=> !keccak_run_o)
 
   // start_i, done_i, process_i cannot set high at the same time
@@ -761,7 +761,7 @@ module sha3pad
     $onehot0({
       start_i,
       process_i,
-      prim_mubi_pkg::mubi4_test_true_loose(done_i)
+      caliptra_prim_mubi_pkg::mubi4_test_true_loose(done_i)
     }))
 
   // Sequence, start_i --> process_i --> absorbed_o --> done_i
@@ -779,7 +779,7 @@ module sha3pad
       start_valid <= 1'b 1;
     end else if (start_i) begin
       start_valid <= 1'b 0;
-    end else if (prim_mubi_pkg::mubi4_test_true_strict(done_i)) begin
+    end else if (caliptra_prim_mubi_pkg::mubi4_test_true_strict(done_i)) begin
       start_valid <= 1'b 1;
     end
   end
@@ -796,9 +796,9 @@ module sha3pad
   always_ff @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       done_valid <= 1'b 0;
-    end else if (prim_mubi_pkg::mubi4_test_true_strict(absorbed_o)) begin
+    end else if (caliptra_prim_mubi_pkg::mubi4_test_true_strict(absorbed_o)) begin
       done_valid <= 1'b 1;
-    end else if (prim_mubi_pkg::mubi4_test_true_strict(done_i)) begin
+    end else if (caliptra_prim_mubi_pkg::mubi4_test_true_strict(done_i)) begin
       done_valid <= 1'b 0;
     end
   end
@@ -812,7 +812,7 @@ module sha3pad
   `CALIPTRA_ASSUME(ProcessCondition_M, process_i |-> process_valid)
   `CALIPTRA_ASSUME(StartCondition_M, start_i |-> start_valid)
   `CALIPTRA_ASSUME(DoneCondition_M,
-    prim_mubi_pkg::mubi4_test_true_strict(done_i) |-> done_valid)
+    caliptra_prim_mubi_pkg::mubi4_test_true_strict(done_i) |-> done_valid)
 
   // Assume mode_i and strength_i are stable during the operation
   // This will be guarded at the kmac top level
diff --git a/src/lc_ctrl/config/compile.yml b/src/lc_ctrl/config/compile.yml
index 2be1b0d93..eff0a412e 100644
--- a/src/lc_ctrl/config/compile.yml
+++ b/src/lc_ctrl/config/compile.yml
@@ -2,7 +2,7 @@
 provides: [lc_ctrl_pkg]
 schema_version: 2.4.0
 requires:
-  - prim_pkg
+  - caliptra_prim_pkg
 targets:
   rtl:
     directories: [$COMPILE_ROOT/rtl]
diff --git a/src/lc_ctrl/config/lc_ctrl_pkg.vf b/src/lc_ctrl/config/lc_ctrl_pkg.vf
index b314749ea..e41a7f442 100644
--- a/src/lc_ctrl/config/lc_ctrl_pkg.vf
+++ b/src/lc_ctrl/config/lc_ctrl_pkg.vf
@@ -1,11 +1,12 @@
-+incdir+${CALIPTRA_ROOT}/src/prim/rtl
++incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl
 +incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl
-${CALIPTRA_ROOT}/src/prim/rtl/prim_util_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_alert_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_mubi_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_cipher_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv
 ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv
 ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv
diff --git a/src/lc_ctrl/rtl/lc_ctrl_pkg.sv b/src/lc_ctrl/rtl/lc_ctrl_pkg.sv
index e67e1bf43..8793c5dbe 100644
--- a/src/lc_ctrl/rtl/lc_ctrl_pkg.sv
+++ b/src/lc_ctrl/rtl/lc_ctrl_pkg.sv
@@ -3,11 +3,11 @@
 // SPDX-License-Identifier: Apache-2.0
 //
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
 package lc_ctrl_pkg;
 
-  import prim_util_pkg::vbits;
+  import caliptra_prim_util_pkg::vbits;
   import lc_ctrl_state_pkg::*;
 
   ///////////////////////////////////////
@@ -65,31 +65,31 @@ package lc_ctrl_pkg;
   // This is a prerequisite for the multibit functions below to work.
   `CALIPTRA_ASSERT_STATIC_IN_PACKAGE(CheckLcTxValsComplementary_A, On == ~Off)
   // Check for bit-width matching between lc_tx_t and mubi4_t
-  `CALIPTRA_ASSERT_STATIC_IN_PACKAGE(LcMuBiWidthCheck_A, $bits(TxWidth) == $bits(prim_mubi_pkg::MuBi4Width))
+  `CALIPTRA_ASSERT_STATIC_IN_PACKAGE(LcMuBiWidthCheck_A, $bits(TxWidth) == $bits(caliptra_prim_mubi_pkg::MuBi4Width))
 
   // Convert a life cycle signal to mubi4
   // If in the future other versions are desired, this should really be
-  // moved to prim_mubi_pkg
+  // moved to caliptra_prim_mubi_pkg
   //
   // The On ^ MuBi4True determines the bit differences between
-  // an lc_ctrl_pkg::On and prim_mubi_pkg::MuBi4True.
+  // an lc_ctrl_pkg::On and caliptra_prim_mubi_pkg::MuBi4True.
   // Once the required inversions are determined, it is then applied
   // to the incoming value.  If the incoming value is true, it will
   // appropriately flip to the correct MuBiValue.
   // Since the false value is always complement of the true value,
   // this mechanism will also work for the other polarity.
-  function automatic prim_mubi_pkg::mubi4_t lc_to_mubi4(lc_tx_t val);
-    return prim_mubi_pkg::mubi4_t'(val ^ (On ^ prim_mubi_pkg::MuBi4True));
+  function automatic caliptra_prim_mubi_pkg::mubi4_t lc_to_mubi4(lc_tx_t val);
+    return caliptra_prim_mubi_pkg::mubi4_t'(val ^ (On ^ caliptra_prim_mubi_pkg::MuBi4True));
   endfunction : lc_to_mubi4
 
-  function automatic lc_tx_t mubi4_to_lc(prim_mubi_pkg::mubi4_t val);
-    return lc_tx_t'(val ^ (prim_mubi_pkg::MuBi4True ^ On));
+  function automatic lc_tx_t mubi4_to_lc(caliptra_prim_mubi_pkg::mubi4_t val);
+    return lc_tx_t'(val ^ (caliptra_prim_mubi_pkg::MuBi4True ^ On));
   endfunction : mubi4_to_lc
 
   // same function as above, but for an input that is MuBi4True, return Off
   // for an input that is MuBi4False, return On
-  function automatic lc_tx_t mubi4_to_lc_inv(prim_mubi_pkg::mubi4_t val);
-    return lc_tx_t'(val ^ (prim_mubi_pkg::MuBi4True ^ Off));
+  function automatic lc_tx_t mubi4_to_lc_inv(caliptra_prim_mubi_pkg::mubi4_t val);
+    return lc_tx_t'(val ^ (caliptra_prim_mubi_pkg::MuBi4True ^ Off));
   endfunction : mubi4_to_lc_inv
 
   // Test whether the value is supplied is one of the valid enumerations
@@ -145,7 +145,7 @@ package lc_ctrl_pkg;
   // Note: due to the nature of the lc_tx_or() function, it is possible that two
   // non-strictly "act" values may produce a strictly "act" value. If this is
   // of concern, e.g. if the output is consumed with a strict check on "act",
-  // consider using the prim_lc_or_hardened primitive instead.
+  // consider using the caliptra_prim_lc_or_hardened primitive instead.
   function automatic lc_tx_t lc_tx_or(lc_tx_t a, lc_tx_t b, lc_tx_t act);
     logic [TxWidth-1:0] a_in, b_in, act_in, out;
     a_in = a;
@@ -176,7 +176,7 @@ package lc_ctrl_pkg;
   // that the lc_tx_or function above does, since only one output value in the
   // truth table is strictly "act". It can hence be used in most scenarios without issues.
   // If however the lc_tx_and() function should be strictly rectifying (i.e., only
-  // output "act" or ~"act"), the prim_lc_and_hardened can be used.
+  // output "act" or ~"act"), the caliptra_prim_lc_and_hardened can be used.
   function automatic lc_tx_t lc_tx_and(lc_tx_t a, lc_tx_t b, lc_tx_t act);
     logic [TxWidth-1:0] a_in, b_in, act_in, out;
     a_in = a;
diff --git a/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv b/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv
index 16897b61f..100e62077 100644
--- a/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv
+++ b/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv
@@ -10,7 +10,7 @@
 //
 package lc_ctrl_state_pkg;
 
-  import prim_util_pkg::vbits;
+  import caliptra_prim_util_pkg::vbits;
 
   ///////////////////////////////
   // General size declarations //
diff --git a/src/libs/config/compile.yml b/src/libs/config/compile.yml
index 3569036ed..c15f5de4b 100644
--- a/src/libs/config/compile.yml
+++ b/src/libs/config/compile.yml
@@ -16,6 +16,7 @@ targets:
       - $COMPILE_ROOT/rtl/ahb_slv_sif.sv
       - $COMPILE_ROOT/rtl/caliptra_icg.sv
       - $COMPILE_ROOT/rtl/clk_gate.sv
+      - $COMPILE_ROOT/rtl/caliptra_2ff_sync.sv
   rtl:
     directories: [$COMPILE_ROOT/rtl]
     files:
@@ -28,6 +29,7 @@ targets:
       - $COMPILE_ROOT/rtl/ahb_slv_sif.sv
       - $COMPILE_ROOT/rtl/caliptra_icg.sv
       - $COMPILE_ROOT/rtl/clk_gate.sv
+      - $COMPILE_ROOT/rtl/caliptra_2ff_sync.sv
       - $COMPILE_ROOT/rtl/ahb_to_reg_adapter.sv
 ---
 provides: [uvm_lib]
diff --git a/src/libs/config/libs.vf b/src/libs/config/libs.vf
index 89d3b44e4..7c0d4c77b 100644
--- a/src/libs/config/libs.vf
+++ b/src/libs/config/libs.vf
@@ -11,4 +11,5 @@ ${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
\ No newline at end of file
diff --git a/src/libs/rtl/ahb_slv_sif.sv b/src/libs/rtl/ahb_slv_sif.sv
index 12fbfceb1..972b58381 100644
--- a/src/libs/rtl/ahb_slv_sif.sv
+++ b/src/libs/rtl/ahb_slv_sif.sv
@@ -147,6 +147,20 @@ always_comb begin : response_block
     end
 end
 
-//bypass lint err //FIXME when lint rule is removed
+//Coverage
+`ifndef VERILATOR
+`ifdef FCOV
+
+covergroup ahb_slv_sif_cov_grp @(posedge hclk);
+    option.per_instance = 1;
+
+    ahb_read_cp: coverpoint (dv & ~write) {option.comment = "AHB read transaction";}
+    ahb_write_cp: coverpoint (dv & write) {option.comment = "AHB write transaction";}
+endgroup
+
+ahb_slv_sif_cov_grp ahb_slv_sif_cov_grp1 = new();
+
+`endif
+`endif
 
 endmodule
diff --git a/src/libs/rtl/apb_slv_sif.sv b/src/libs/rtl/apb_slv_sif.sv
index e0c0d3f4f..eb791e381 100644
--- a/src/libs/rtl/apb_slv_sif.sv
+++ b/src/libs/rtl/apb_slv_sif.sv
@@ -77,12 +77,11 @@ end
 always_comb access_phase = PSEL & PENABLE;
 
 //drive ready if no hold from component
-always_comb PREADY = (dv & access_phase) ? ~req_hold : '1;
+always_comb PREADY = dv ? ~req_hold : '1;
 //drive read data from component
-always_comb PRDATA = (dv & access_phase) ? rdata : '0;
+always_comb PRDATA = rdata;
 //drive error from component for valid access, drive error for invalid access phase
-always_comb PSLVERR = (dv & access_phase) ? slverr : 
-                             access_phase ? '1 : '0;
+always_comb PSLVERR = slverr;
 
 
 
diff --git a/src/libs/rtl/caliptra_2ff_sync.sv b/src/libs/rtl/caliptra_2ff_sync.sv
new file mode 100644
index 000000000..9124daa92
--- /dev/null
+++ b/src/libs/rtl/caliptra_2ff_sync.sv
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+module caliptra_2ff_sync  #( parameter WIDTH=1,
+                             parameter RST_VAL=0)
+    (
+    input logic clk,
+    input logic rst_b,
+    input logic [WIDTH-1:0] din,
+    output logic [WIDTH-1:0] dout
+
+);
+
+logic din_ff;
+
+always_ff@(posedge clk or negedge rst_b) begin
+    if(!rst_b) begin
+        dout <= RST_VAL;
+        din_ff <= RST_VAL;
+    end
+    else begin 
+        din_ff <= din;
+        dout <= din_ff;
+    end
+end
+
+
+endmodule
\ No newline at end of file
diff --git a/src/libs/rtl/clk_gate.sv b/src/libs/rtl/clk_gate.sv
index 483b8ee3c..73e9ba1bd 100644
--- a/src/libs/rtl/clk_gate.sv
+++ b/src/libs/rtl/clk_gate.sv
@@ -17,18 +17,25 @@ module clk_gate (
     input logic cptra_rst_b,
     input logic psel,
     input logic clk_gate_en,
+    input logic rdc_clk_dis,
+    input logic rdc_clk_dis_uc,
     input logic cpu_halt_status,
     input logic [63:0] generic_input_wires,
+    input logic cptra_error_fatal,
+    input logic cptra_in_debug_scan_mode,
     output logic clk_cg,
-    output logic soc_ifc_clk_cg
+    output logic soc_ifc_clk_cg,
+    output logic rdc_clk_cg,
+    output logic uc_clk_cg,
+    input  logic cptra_dmi_reg_en_preQ //JTAG access
 );
 
 logic disable_clk;
 logic disable_soc_ifc_clk;
-logic disable_clk_lat;
-logic disable_soc_ifc_clk_lat;
+logic disable_uc_clk;
 logic [63:0] generic_input_wires_f;
 logic change_in_generic_wires;
+logic sleep_condition;
 
 
 /**********************************************************************
@@ -64,17 +71,23 @@ end
 //Generate clk disable signal
 always_comb begin
     change_in_generic_wires = ((generic_input_wires ^ generic_input_wires_f) != 'h0);
-    disable_clk             = clk_gate_en && (cpu_halt_status && !change_in_generic_wires);
-    disable_soc_ifc_clk     = clk_gate_en && (cpu_halt_status && !psel && !change_in_generic_wires);
+    sleep_condition         = (cpu_halt_status && !change_in_generic_wires && !cptra_error_fatal && !cptra_in_debug_scan_mode && !cptra_dmi_reg_en_preQ);
+    disable_clk             = (clk_gate_en && sleep_condition) | rdc_clk_dis;
+    disable_soc_ifc_clk     = (clk_gate_en && (sleep_condition && !psel)) | rdc_clk_dis;
+    disable_uc_clk          = (rdc_clk_dis | rdc_clk_dis_uc);
 end
 
 
 `ifdef TECH_SPECIFIC_ICG
     `USER_ICG user_icg (.clk(clk), .en(!disable_clk), .clk_cg(clk_cg));
     `USER_ICG user_soc_ifc_icg (.clk(clk), .en(!disable_soc_ifc_clk), .clk_cg(soc_ifc_clk_cg));
+    `USER_ICG user_rdc_icg (.clk(clk), .en(!rdc_clk_dis), .clk_cg(rdc_clk_cg));
+    `USER_ICG user_rdc_uc_icg (.clk(clk), .en(!disable_uc_clk), .clk_cg(uc_clk_cg));
 `else
     `CALIPTRA_ICG caliptra_icg (.clk(clk), .en(!disable_clk), .clk_cg(clk_cg));
     `CALIPTRA_ICG caliptra_soc_ifc_icg (.clk(clk), .en(!disable_soc_ifc_clk), .clk_cg(soc_ifc_clk_cg));
+    `CALIPTRA_ICG caliptra_rdc_icg (.clk(clk), .en(!rdc_clk_dis), .clk_cg(rdc_clk_cg));
+    `CALIPTRA_ICG caliptra_rdc_uc_icg (.clk(clk), .en(!disable_uc_clk), .clk_cg(uc_clk_cg));
 `endif
 
 endmodule
diff --git a/src/libs/uvmf/qvip_ahb_lite_slave_dir/config_policies/ahb_lite_slave_0_config_policy.svh b/src/libs/uvmf/qvip_ahb_lite_slave_dir/config_policies/ahb_lite_slave_0_config_policy.svh
index fb370d55f..1e4a139eb 100644
--- a/src/libs/uvmf/qvip_ahb_lite_slave_dir/config_policies/ahb_lite_slave_0_config_policy.svh
+++ b/src/libs/uvmf/qvip_ahb_lite_slave_dir/config_policies/ahb_lite_slave_0_config_policy.svh
@@ -121,7 +121,7 @@ class ahb_lite_slave_0_config_policy;
         //    // If true, drives previous address when bus is IDLE
         //    cfg.m_bfm.config_address_on_idle = 1'b0;
         //    // Maximum number of successive wait states
-        //    cfg.m_bfm.config_max_wait_states_count = 16;
+              cfg.m_bfm.config_max_wait_states_count = 20;
         //    // Data endianness
         //    cfg.m_bfm.config_endianness = AHB_LITTLE_ENDIAN;
         //    // Sets the domain
diff --git a/src/pcrvault/config/compile.yml b/src/pcrvault/config/compile.yml
index 352818c78..8e17ba963 100644
--- a/src/pcrvault/config/compile.yml
+++ b/src/pcrvault/config/compile.yml
@@ -1,6 +1,7 @@
 provides: [pv_defines_pkg]
 schema_version: 2.4.0
-requires: []
+requires: 
+  - libs
 targets:
   rtl:
     directories: [$COMPILE_ROOT/rtl]
@@ -23,6 +24,17 @@ targets:
     files:
       - $COMPILE_ROOT/rtl/pv_reg_uvm.sv
 ---
+provides: [pcrvault_cov]
+schema_version: 2.4.0
+targets:
+  tb:
+    directories:
+      - $COMPILE_ROOT/coverage
+    files:
+      - $COMPILE_ROOT/coverage/pcrvault_cov_if.sv
+      - $COMPILE_ROOT/coverage/pcrvault_cov_props.sv
+      - $COMPILE_ROOT/coverage/pcrvault_cov_bind.sv
+---
 provides: [pcrvault]
 schema_version: 2.4.0
 requires: 
diff --git a/src/pcrvault/config/pcrvault.vf b/src/pcrvault/config/pcrvault.vf
index a7a532662..5e59b1772 100644
--- a/src/pcrvault/config/pcrvault.vf
+++ b/src/pcrvault/config/pcrvault.vf
@@ -12,6 +12,7 @@ ${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_defines_pkg.sv
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_macros.svh
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_gen_hash.sv
diff --git a/src/pcrvault/config/pcrvault_cov.vf b/src/pcrvault/config/pcrvault_cov.vf
new file mode 100644
index 000000000..e8172adeb
--- /dev/null
+++ b/src/pcrvault/config/pcrvault_cov.vf
@@ -0,0 +1,4 @@
++incdir+${CALIPTRA_ROOT}/src/pcrvault/coverage
+${CALIPTRA_ROOT}/src/pcrvault/coverage/pcrvault_cov_if.sv
+${CALIPTRA_ROOT}/src/pcrvault/coverage/pcrvault_cov_props.sv
+${CALIPTRA_ROOT}/src/pcrvault/coverage/pcrvault_cov_bind.sv
\ No newline at end of file
diff --git a/src/pcrvault/config/pv_defines_pkg.vf b/src/pcrvault/config/pv_defines_pkg.vf
index dd59d584e..ab7aa0fd0 100644
--- a/src/pcrvault/config/pv_defines_pkg.vf
+++ b/src/pcrvault/config/pv_defines_pkg.vf
@@ -1,5 +1,20 @@
++incdir+${CALIPTRA_ROOT}/src/integration/rtl
++incdir+${CALIPTRA_ROOT}/src/libs/rtl
 +incdir+${CALIPTRA_ROOT}/src/pcrvault/rtl
+${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh
+${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sva.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_macros.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sram.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_defines_pkg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_ahb_srom.sv
+${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_defines_pkg.sv
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_macros.svh
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_gen_hash.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_gen_hash.sv
\ No newline at end of file
diff --git a/src/pcrvault/coverage/pcrvault_cov_bind.sv b/src/pcrvault/coverage/pcrvault_cov_bind.sv
new file mode 100644
index 000000000..09251cf44
--- /dev/null
+++ b/src/pcrvault/coverage/pcrvault_cov_bind.sv
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+module pcrvault_cov_bind;
+    //`ifdef FCOV
+    bind dut pcrvault_cov_if i_pcrvault_cov_if(.*);
+    bind dut pcrvault_cov_props i_pcrvault_cov_props(.*);
+    //`endif
+endmodule
diff --git a/src/pcrvault/coverage/pcrvault_cov_if.sv b/src/pcrvault/coverage/pcrvault_cov_if.sv
new file mode 100644
index 000000000..c14ec311a
--- /dev/null
+++ b/src/pcrvault/coverage/pcrvault_cov_if.sv
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+`ifndef VERILATOR
+
+interface pcrvault_cov_if     
+    import pv_defines_pkg::*;
+    (
+    input logic clk,
+    input logic rst_b,
+    input logic cptra_pwrgood
+);
+
+    logic [PV_NUM_PCR-1:0] pcr_ctrl_lock;
+    logic [PV_NUM_PCR-1:0] pcr_ctrl_clear;
+
+    logic [PV_NUM_WRITE-1:0] pv_write_en;
+    logic ahb_write, ahb_read;
+    
+    //Assign clear and locks of each PCR_CTRL reg to corresponding bit in the intermediate bus
+    generate
+        for(genvar i = 0; i < PV_NUM_PCR; i++) begin
+            assign pcr_ctrl_lock[i] = dut.pv_reg_hwif_out.PCR_CTRL[i].lock;
+        end
+    endgenerate
+
+    generate
+        for(genvar client = 0; client < PV_NUM_WRITE; client++) begin
+            assign pv_write_en[client] = dut.pv_write[client].write_en;
+        end
+    endgenerate
+
+    //AHB signals
+    assign ahb_write = dut.pv_ahb_slv1.dv & dut.pv_ahb_slv1.write;
+    assign ahb_read  = dut.pv_ahb_slv1.dv & ~dut.pv_ahb_slv1.write;
+
+    covergroup pcrvault_top_cov_grp @(posedge clk);
+        option.per_instance = 1;
+
+        //Note: Bit transitions and values for lock and clear are covered
+        //in UVM reg coverage. This coverpoint bins the 32-bit lock/clear bus so that
+        //they can be used to cross with other signals
+        lock: coverpoint pcr_ctrl_lock {
+            bins bin0 = {[0:'hFFFF]};
+            bins bin1 = {['h1_0000:'hF_FFFF]};
+            bins bin2 = {['h10_0000:'hFF_FFFF]};
+            bins bin3 = {['h100_0000:'hFFF_FFFF]};
+            bins bin4 = {['h1000_0000: 'hFFFF_FFFF]};
+        }
+        clear: coverpoint pcr_ctrl_clear {
+            bins bin0 = {[0:'hFFFF]};
+            bins bin1 = {['h1_0000:'hF_FFFF]};
+            bins bin2 = {['h10_0000:'hFF_FFFF]};
+            bins bin3 = {['h100_0000:'hFFF_FFFF]};
+            bins bin4 = {['h1000_0000: 'hFFFF_FFFF]};
+        }
+
+        //Cover warm reset assertion while regs are locked/cleared
+        lockXwarm_rst:      cross lock, rst_b;
+        clearXwarm_rst:     cross clear, rst_b;
+
+        //Cover cold reset assertion while regs are locked/cleared
+        lockXcold_rst:      cross lock, cptra_pwrgood;
+        clearXcold_rst:     cross clear, cptra_pwrgood;
+
+        // lockXcore_rst:      cross lock, core_only_rst_b;
+        // clearXcore_rst:     cross clear, core_only_rst_b;
+
+        //Cover crypto writes to locked/cleared regs
+        lockXpv_write:      cross lock, pv_write_en;
+        clearXpv_write:     cross clear, pv_write_en;
+
+        //Cover ahb write and read when crypto writes are happening
+        ahbXpv_write:       cross ahb_write, ahb_read, pv_write_en;
+        
+
+    endgroup
+
+
+    pcrvault_top_cov_grp pcrvault_top_cov_grp1 = new();
+    
+endinterface
+
+`endif
\ No newline at end of file
diff --git a/src/pcrvault/coverage/pcrvault_cov_props.sv b/src/pcrvault/coverage/pcrvault_cov_props.sv
new file mode 100644
index 000000000..ba63232e7
--- /dev/null
+++ b/src/pcrvault/coverage/pcrvault_cov_props.sv
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: Apache-2.0
+// Copyright 2019 Western Digital Corporation or its affiliates.
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+
+module pcrvault_cov_props
+    import pv_defines_pkg::*;
+    ();
+
+    `ifndef VERILATOR
+    
+    generate
+        for(genvar i = 0; i < PV_NUM_PCR; i++) begin
+
+            //clear followed by warm reset in the next clk
+            //Expectation: PCRs cleared before warm reset
+            property cover_prop_clear_warm_rst;
+                @(posedge dut.clk)
+                (dut.pv_reg_hwif_out.PCR_CTRL[i].clear |-> ##[1:$] !dut.rst_b);
+            endproperty
+            covprop_clear_warmrst: cover property(cover_prop_clear_warm_rst);
+        
+            //locks, followed by clear, followed by warm reset in the next clk
+            //Expectation: Unlocked PCRs cleared before warm reset, locks cleared on warm reset
+            property cover_prop_lock_clear_warm_rst;
+                @(posedge dut.clk)
+                (dut.pv_reg_hwif_out.PCR_CTRL[i].lock |-> ##[0:$] dut.pv_reg_hwif_out.PCR_CTRL[i].clear |-> ##[1:$] !dut.rst_b);
+            endproperty
+            covprop_lock_clear_warmrst: cover property(cover_prop_lock_clear_warm_rst);
+        
+            //locks, followed by clear, followed by cold reset in the next clk
+            //Expectation: Unlocked PCRs cleared before cold reset, everything cleared on cold reset
+            property cover_prop_lock_clear_cold_rst;
+                @(posedge dut.clk)
+                (dut.pv_reg_hwif_out.PCR_CTRL[i].lock |-> ##[0:$] dut.pv_reg_hwif_out.PCR_CTRL[i].clear |-> ##[1:$] !dut.cptra_pwrgood);
+            endproperty
+            covprop_lock_clear_coldrst: cover property(cover_prop_lock_clear_cold_rst);
+        end
+    endgenerate
+
+  `endif
+
+endmodule
\ No newline at end of file
diff --git a/src/pcrvault/rtl/pv.sv b/src/pcrvault/rtl/pv.sv
index 264320535..1a0a1fff8 100644
--- a/src/pcrvault/rtl/pv.sv
+++ b/src/pcrvault/rtl/pv.sv
@@ -27,7 +27,9 @@ module pv
     (
     input logic clk,
     input logic rst_b,
+    input logic core_only_rst_b,
     input logic cptra_pwrgood,
+    input logic fw_update_rst_window, 
     
     //uC AHB Lite Interface
     //from SLAVES PORT
@@ -103,9 +105,10 @@ always_comb uc_req_hold = '0;
 
 always_comb begin : keyvault_ctrl
     for (int entry = 0; entry < PV_NUM_PCR; entry++) begin
-        //once lock is set, only hard reset can unset it
-        pv_reg_hwif_in.PCR_CTRL[entry].lock.swwel = pv_reg_hwif_out.PCR_CTRL[entry].lock.value;
-        pv_reg_hwif_in.PCR_CTRL[entry].clear.swwel = pv_reg_hwif_out.PCR_CTRL[entry].lock.value;
+        //once lock is set, any reset can unset it
+        //During a fw update reset we'll be de-asserting locks - avoid RDC violation by synchronously de-asserting
+        pv_reg_hwif_in.PCR_CTRL[entry].lock.swwel = pv_reg_hwif_out.PCR_CTRL[entry].lock.value & ~fw_update_rst_window;
+        pv_reg_hwif_in.PCR_CTRL[entry].clear.swwel = pv_reg_hwif_out.PCR_CTRL[entry].lock.value & ~fw_update_rst_window;
     end
 
     //pcrvault storage
@@ -167,6 +170,7 @@ end
 
 always_comb pv_reg_hwif_in.hard_reset_b = cptra_pwrgood;
 always_comb pv_reg_hwif_in.reset_b = rst_b;
+always_comb pv_reg_hwif_in.core_only_rst_b = core_only_rst_b; //Note that this signal will also reset when rst_b is asserted
 
 pv_reg pv_reg1 (
     .clk(clk),
diff --git a/src/pcrvault/rtl/pv_defines_pkg.sv b/src/pcrvault/rtl/pv_defines_pkg.sv
index 93c9f23a5..b69c43b18 100644
--- a/src/pcrvault/rtl/pv_defines_pkg.sv
+++ b/src/pcrvault/rtl/pv_defines_pkg.sv
@@ -25,7 +25,7 @@ parameter PV_ENTRY_ADDR_W = $clog2(PV_NUM_PCR);
 parameter PV_ENTRY_SIZE_WIDTH = $clog2(PV_NUM_DWORDS);
 parameter PV_NUM_READ = 1;
 parameter PV_NUM_WRITE = 1;
-parameter PV_SIZE_OF_NONCE = 32;
+parameter PV_SIZE_OF_NONCE = 256;
 
 
 typedef struct packed {
diff --git a/src/pcrvault/rtl/pv_gen_hash.sv b/src/pcrvault/rtl/pv_gen_hash.sv
index e007f3824..5ce7fb8b2 100644
--- a/src/pcrvault/rtl/pv_gen_hash.sv
+++ b/src/pcrvault/rtl/pv_gen_hash.sv
@@ -23,6 +23,8 @@ module pv_gen_hash
     ,parameter DATA_W = 32
     ,localparam BLOCK_NO = BLOCK_W/DATA_W
     ,localparam BLOCK_OFFSET_W = $clog2(BLOCK_NO)
+    ,localparam NONCE_LEN_DWORD = PV_SIZE_OF_NONCE/DATA_W
+    ,localparam NONCE_OFFSET_W = $clog2(NONCE_LEN_DWORD)
     )
     (
     input logic clk,
@@ -31,7 +33,7 @@ module pv_gen_hash
     input logic start,
     input logic core_ready,
     input logic core_digest_valid,
-    input [PV_SIZE_OF_NONCE-1:0] nonce,
+    input [NONCE_LEN_DWORD-1:0][DATA_W-1:0] nonce,
 
     output logic gen_hash_ip,
     output logic gen_hash_init_reg,
@@ -88,6 +90,8 @@ logic [PV_ENTRY_SIZE_WIDTH-1:0] read_offset, read_offset_nxt;
 logic inc_rd_ptr;
 logic rst_rd_ptr;
 
+logic [NONCE_OFFSET_W-1:0] nonce_offset_i, nonce_offset_nxt;
+
 
 assign gen_hash_ip = (gen_hash_fsm_ps != GEN_HASH_IDLE);
 assign gen_hash_init_reg = arc_GEN_HASH_BLOCK_0_GEN_HASH_BLOCK_N;
@@ -116,6 +120,10 @@ assign block_offset = block_offset_i[BLOCK_OFFSET_W-1:0];
   always_comb inc_rd_ptr = gen_hash_fsm_ps inside {GEN_HASH_BLOCK_0, GEN_HASH_BLOCK_N} & ~block_full;
   always_comb rst_rd_ptr = arc_GEN_HASH_BLOCK_0_GEN_HASH_NONCE | arc_GEN_HASH_BLOCK_N_GEN_HASH_NONCE;
 
+
+  always_comb nonce_offset_nxt = (gen_hash_fsm_ps != GEN_HASH_NONCE) ? '0 :
+                                 (block_we ? nonce_offset_i + 'd1 : nonce_offset_i);
+
   //State Machine
   //Start processing
   always_comb arc_GEN_HASH_IDLE_GEN_HASH_BLOCK_0 = (gen_hash_fsm_ps == GEN_HASH_IDLE) & start;
@@ -126,7 +134,7 @@ assign block_offset = block_offset_i[BLOCK_OFFSET_W-1:0];
   //Finished reading, start padding - wait for block to process if we need to start a new block
   always_comb arc_GEN_HASH_BLOCK_0_GEN_HASH_NONCE = (gen_hash_fsm_ps == GEN_HASH_BLOCK_0) & ~block_full & last_dword_wr;
   always_comb arc_GEN_HASH_BLOCK_N_GEN_HASH_NONCE = (gen_hash_fsm_ps == GEN_HASH_BLOCK_N) & ~block_full & last_dword_wr;
-  always_comb arc_GEN_HASH_NONCE_GEN_HASH_PAD_LD1 = (gen_hash_fsm_ps == GEN_HASH_NONCE) & ~block_full;
+  always_comb arc_GEN_HASH_NONCE_GEN_HASH_PAD_LD1 = (gen_hash_fsm_ps == GEN_HASH_NONCE) & ~block_full & (nonce_offset_i == NONCE_LEN_DWORD-1);
   always_comb arc_GEN_HASH_PAD_LD1_GEN_HASH_PAD_0S = (gen_hash_fsm_ps == GEN_HASH_PAD_LD1) & ~block_full; 
   //Switch from padding zeros to padding the length                           
   always_comb arc_GEN_HASH_PAD_0S_GEN_HASH_PAD_LEN = (gen_hash_fsm_ps == GEN_HASH_PAD_0S) & ~block_full & (block_offset_i == PAD_LEN_DWORD-1);
@@ -157,7 +165,7 @@ assign block_offset = block_offset_i[BLOCK_OFFSET_W-1:0];
       end
       GEN_HASH_NONCE: begin
         if (arc_GEN_HASH_NONCE_GEN_HASH_PAD_LD1) gen_hash_fsm_ns = GEN_HASH_PAD_LD1;
-        block_wr_data = nonce;
+        block_wr_data = nonce[NONCE_LEN_DWORD-1-nonce_offset_i];
       end
       GEN_HASH_PAD_LD1: begin
         if (arc_GEN_HASH_PAD_LD1_GEN_HASH_PAD_0S) gen_hash_fsm_ns = GEN_HASH_PAD_0S;
@@ -197,6 +205,7 @@ assign block_offset = block_offset_i[BLOCK_OFFSET_W-1:0];
     else begin
       gen_hash_fsm_ps <= gen_hash_fsm_ns;
       block_offset_i <= block_offset_nxt;
+      nonce_offset_i <= nonce_offset_nxt;
       read_entry <= read_entry_nxt;
       read_offset <= read_offset_nxt;
     end
diff --git a/src/pcrvault/rtl/pv_reg.rdl b/src/pcrvault/rtl/pv_reg.rdl
index 9dbdcec4a..7a9a05e37 100644
--- a/src/pcrvault/rtl/pv_reg.rdl
+++ b/src/pcrvault/rtl/pv_reg.rdl
@@ -15,6 +15,7 @@
 addrmap pv_reg {
     desc="address map for pcrvault";
     signal {activelow; async; cpuif_reset; field_reset;} reset_b;
+    signal {activelow; async;} core_only_rst_b;
     signal {activelow; async;} hard_reset_b;
 
     //PCR are sw read only
@@ -26,7 +27,7 @@ addrmap pv_reg {
     reg pvCtrl {
         desc="Controls for each pcr entry";
         field {desc="Lock the PCR from being cleared";
-               sw=rw; swwel=true; hw=r; resetsignal = hard_reset_b;} lock=0; 
+               sw=rw; swwel=true; hw=r; resetsignal = core_only_rst_b;} lock=0; 
         field {desc="Clear the data stored in this entry. Lock will prevent this clear.";
                sw=rw; swwel=true; hw=r; singlepulse;} clear=0;
         field {desc="Reserved";
diff --git a/src/pcrvault/rtl/pv_reg.sv b/src/pcrvault/rtl/pv_reg.sv
index 74e1dd8c0..d8483f2b2 100644
--- a/src/pcrvault/rtl/pv_reg.sv
+++ b/src/pcrvault/rtl/pv_reg.sv
@@ -160,8 +160,8 @@ module pv_reg (
             field_combo.PCR_CTRL[i0].lock.next = next_c;
             field_combo.PCR_CTRL[i0].lock.load_next = load_next_c;
         end
-        always_ff @(posedge clk or negedge hwif_in.hard_reset_b) begin
-            if(~hwif_in.hard_reset_b) begin
+        always_ff @(posedge clk or negedge hwif_in.core_only_rst_b) begin
+            if(~hwif_in.core_only_rst_b) begin
                 field_storage.PCR_CTRL[i0].lock.value <= 'h0;
             end else if(field_combo.PCR_CTRL[i0].lock.load_next) begin
                 field_storage.PCR_CTRL[i0].lock.value <= field_combo.PCR_CTRL[i0].lock.next;
diff --git a/src/pcrvault/rtl/pv_reg_covergroups.svh b/src/pcrvault/rtl/pv_reg_covergroups.svh
new file mode 100644
index 000000000..63f50e1c5
--- /dev/null
+++ b/src/pcrvault/rtl/pv_reg_covergroups.svh
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+`ifndef PV_REG_COVERGROUPS
+    `define PV_REG_COVERGROUPS
+    
+    /*----------------------- PV_REG__PVCTRL COVERGROUPS -----------------------*/
+    covergroup pv_reg__pvCtrl_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup pv_reg__pvCtrl_fld_cg with function sample(
+    input bit [1-1:0] lock,
+    input bit [1-1:0] clear,
+    input bit [1-1:0] rsvd0,
+    input bit [5-1:0] rsvd1
+    );
+        option.per_instance = 1;
+        lock_cp : coverpoint lock;
+        clear_cp : coverpoint clear;
+        rsvd0_cp : coverpoint rsvd0;
+        rsvd1_cp : coverpoint rsvd1;
+        lockXclear: cross lock_cp, clear_cp;
+
+    endgroup
+
+    /*----------------------- PV_REG__PCRREG COVERGROUPS -----------------------*/
+    covergroup pv_reg__pcrReg_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup pv_reg__pcrReg_fld_cg with function sample(
+    input bit [32-1:0] data
+    );
+        option.per_instance = 1;
+        data_cp : coverpoint data;
+
+    endgroup
+
+`endif
\ No newline at end of file
diff --git a/src/pcrvault/rtl/pv_reg_pkg.sv b/src/pcrvault/rtl/pv_reg_pkg.sv
index f61581c70..e0201b175 100644
--- a/src/pcrvault/rtl/pv_reg_pkg.sv
+++ b/src/pcrvault/rtl/pv_reg_pkg.sv
@@ -32,6 +32,7 @@ package pv_reg_pkg;
 
     typedef struct packed{
         logic reset_b;
+        logic core_only_rst_b;
         logic hard_reset_b;
         pv_reg__pvCtrl__in_t [32-1:0]PCR_CTRL;
         pv_reg__pcrReg__in_t [32-1:0][12-1:0]PCR_ENTRY;
diff --git a/src/pcrvault/rtl/pv_reg_sample.svh b/src/pcrvault/rtl/pv_reg_sample.svh
new file mode 100644
index 000000000..8f7d16443
--- /dev/null
+++ b/src/pcrvault/rtl/pv_reg_sample.svh
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+`ifndef PV_REG_SAMPLE
+    `define PV_REG_SAMPLE
+    
+    /*----------------------- PV_REG__PVCTRL SAMPLE FUNCTIONS -----------------------*/
+    function void pv_reg__pvCtrl::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(lock_bit_cg[bt]) this.lock_bit_cg[bt].sample(data[0 + bt]);
+            foreach(clear_bit_cg[bt]) this.clear_bit_cg[bt].sample(data[1 + bt]);
+            foreach(rsvd0_bit_cg[bt]) this.rsvd0_bit_cg[bt].sample(data[2 + bt]);
+            foreach(rsvd1_bit_cg[bt]) this.rsvd1_bit_cg[bt].sample(data[3 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*lock*/  ,  data[1:1]/*clear*/  ,  data[2:2]/*rsvd0*/  ,  data[7:3]/*rsvd1*/   );
+        end
+    endfunction
+
+    function void pv_reg__pvCtrl::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(lock_bit_cg[bt]) this.lock_bit_cg[bt].sample(lock.get_mirrored_value() >> bt);
+            foreach(clear_bit_cg[bt]) this.clear_bit_cg[bt].sample(clear.get_mirrored_value() >> bt);
+            foreach(rsvd0_bit_cg[bt]) this.rsvd0_bit_cg[bt].sample(rsvd0.get_mirrored_value() >> bt);
+            foreach(rsvd1_bit_cg[bt]) this.rsvd1_bit_cg[bt].sample(rsvd1.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( lock.get_mirrored_value()  ,  clear.get_mirrored_value()  ,  rsvd0.get_mirrored_value()  ,  rsvd1.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- PV_REG__PCRREG SAMPLE FUNCTIONS -----------------------*/
+    function void pv_reg__pcrReg::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(data_bit_cg[bt]) this.data_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*data*/   );
+        end
+    endfunction
+
+    function void pv_reg__pcrReg::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(data_bit_cg[bt]) this.data_bit_cg[bt].sample(data.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data.get_mirrored_value()   );
+        end
+    endfunction
+
+`endif
\ No newline at end of file
diff --git a/src/pcrvault/rtl/pv_reg_uvm.sv b/src/pcrvault/rtl/pv_reg_uvm.sv
index ccc1af0d6..dc21effeb 100644
--- a/src/pcrvault/rtl/pv_reg_uvm.sv
+++ b/src/pcrvault/rtl/pv_reg_uvm.sv
@@ -3,17 +3,31 @@
 package pv_reg_uvm;
     `include "uvm_macros.svh"
     import uvm_pkg::*;
-    
+    `include "pv_reg_covergroups.svh"
     // Reg - pv_reg::pvCtrl
     class pv_reg__pvCtrl extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        pv_reg__pvCtrl_bit_cg lock_bit_cg[1];
+        pv_reg__pvCtrl_bit_cg clear_bit_cg[1];
+        pv_reg__pvCtrl_bit_cg rsvd0_bit_cg[1];
+        pv_reg__pvCtrl_bit_cg rsvd1_bit_cg[5];
+        pv_reg__pvCtrl_fld_cg fld_cg;
         rand uvm_reg_field lock;
         rand uvm_reg_field clear;
         rand uvm_reg_field rsvd0;
         rand uvm_reg_field rsvd1;
 
         function new(string name = "pv_reg__pvCtrl");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.lock = new("lock");
@@ -24,20 +38,44 @@ package pv_reg_uvm;
             this.rsvd0.configure(this, 1, 2, "RW", 1, 'h0, 1, 1, 0);
             this.rsvd1 = new("rsvd1");
             this.rsvd1.configure(this, 5, 3, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(lock_bit_cg[bt]) lock_bit_cg[bt] = new();
+                foreach(clear_bit_cg[bt]) clear_bit_cg[bt] = new();
+                foreach(rsvd0_bit_cg[bt]) rsvd0_bit_cg[bt] = new();
+                foreach(rsvd1_bit_cg[bt]) rsvd1_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : pv_reg__pvCtrl
 
     // Reg - pv_reg::pcrReg
     class pv_reg__pcrReg extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        pv_reg__pcrReg_bit_cg data_bit_cg[32];
+        pv_reg__pcrReg_fld_cg fld_cg;
         rand uvm_reg_field data;
 
         function new(string name = "pv_reg__pcrReg");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.data = new("data");
             this.data.configure(this, 32, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(data_bit_cg[bt]) data_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : pv_reg__pcrReg
 
@@ -69,4 +107,5 @@ package pv_reg_uvm;
         endfunction : build
     endclass : pv_reg
 
+    `include "pv_reg_sample.svh"
 endpackage: pv_reg_uvm
diff --git a/src/pcrvault/uvmf_pv/config/compile.yml b/src/pcrvault/uvmf_pv/config/compile.yml
index 82026006e..e8c5fc186 100644
--- a/src/pcrvault/uvmf_pv/config/compile.yml
+++ b/src/pcrvault/uvmf_pv/config/compile.yml
@@ -6,6 +6,7 @@ requires:
   - pv_uvm_pkg
   - pcrvault
   - caliptra_top_defines
+  - pcrvault_cov
 targets:
   tb:
     directories:
diff --git a/src/pcrvault/uvmf_pv/uvmf_template_output/project_benches/pv/tb/testbench/hdl_top.sv b/src/pcrvault/uvmf_pv/uvmf_template_output/project_benches/pv/tb/testbench/hdl_top.sv
index a1c2d9779..ccb7091e0 100644
--- a/src/pcrvault/uvmf_pv/uvmf_template_output/project_benches/pv/tb/testbench/hdl_top.sv
+++ b/src/pcrvault/uvmf_pv/uvmf_template_output/project_benches/pv/tb/testbench/hdl_top.sv
@@ -133,6 +133,8 @@ import uvmf_base_pkg_hdl::*;
       .clk           (clk),
       .rst_b         (pv_rst_agent_bus.rst_b),
       .cptra_pwrgood (pv_rst_agent_bus.cptra_pwrgood),
+      .core_only_rst_b(pv_rst_agent_bus.core_only_rst_b),
+      .fw_update_rst_window(pv_rst_agent_bus.fw_update_rst_window),
       .haddr_i       (uvm_test_top_environment_qvip_ahb_lite_slave_subenv_qvip_hdl.ahb_lite_slave_0_HADDR[14:0]),
       .hwdata_i      (uvm_test_top_environment_qvip_ahb_lite_slave_subenv_qvip_hdl.ahb_lite_slave_0_HWDATA     ),
       .hsel_i        (1'b1),
@@ -149,6 +151,9 @@ import uvmf_base_pkg_hdl::*;
       .pv_rd_resp    (pv_rd_resp),
       .pv_wr_resp    (pv_wr_resp)
   );
+
+  pcrvault_cov_bind i_pcrvault_cov_bind();
+
     assign uvm_test_top_environment_qvip_ahb_lite_slave_subenv_qvip_hdl.ahb_lite_slave_0_HBURST    = 3'b0;
     assign uvm_test_top_environment_qvip_ahb_lite_slave_subenv_qvip_hdl.ahb_lite_slave_0_HPROT     = 7'b0;
     assign uvm_test_top_environment_qvip_ahb_lite_slave_subenv_qvip_hdl.ahb_lite_slave_0_HMASTLOCK = 1'b0;
diff --git a/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_read_pkg/src/pv_read_transaction_coverage.svh b/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_read_pkg/src/pv_read_transaction_coverage.svh
index 2cfac498b..382f34f70 100644
--- a/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_read_pkg/src/pv_read_transaction_coverage.svh
+++ b/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_read_pkg/src/pv_read_transaction_coverage.svh
@@ -28,6 +28,15 @@
 //----------------------------------------------------------------------
 //----------------------------------------------------------------------
 //
+covergroup rd_data(input logic rd_data_bit);
+  //option.per_instance = 1;
+  value: coverpoint rd_data_bit;
+  transition:  coverpoint rd_data_bit {
+    bins bin01 = (0 => 1); 
+    bins bin10 = (1 => 0);
+  }
+endgroup
+
 class pv_read_transaction_coverage #(
       string PV_READ_REQUESTOR = "SHA512_BLOCK"
       )
@@ -44,6 +53,7 @@ class pv_read_transaction_coverage #(
   T coverage_trans;
 
   // pragma uvmf custom class_item_additional begin
+  rd_data rd_data_bus[PV_DATA_W];
   // pragma uvmf custom class_item_additional end
   
   // ****************************************************************************
@@ -60,7 +70,7 @@ class pv_read_transaction_coverage #(
       ignore_bins error1 = {'d1};
     }
     last: coverpoint coverage_trans.last;
-    //read_data: coverpoint coverage_trans.read_data;
+    lastXoffset: cross last, read_offset;
     // pragma uvmf custom covergroup end
   endgroup
 
@@ -90,7 +100,12 @@ class pv_read_transaction_coverage #(
   virtual function void write (T t);
     `uvm_info("COV","Received transaction",UVM_HIGH);
     coverage_trans = t;
+
+    foreach(rd_data_bus[i]) rd_data_bus[i] = new(coverage_trans.read_data[i]);
+    foreach(rd_data_bus[i]) rd_data_bus[i].set_inst_name($sformatf("rd_data_bus[%0d]_%s",i,get_full_name()));
+
     pv_read_transaction_cg.sample();
+    foreach(rd_data_bus[i]) rd_data_bus[i].sample();
   endfunction
 
 endclass
diff --git a/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/pv_rst_pkg.sv b/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/pv_rst_pkg.sv
index 1a30f2ecd..163f5dfa8 100644
--- a/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/pv_rst_pkg.sv
+++ b/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/pv_rst_pkg.sv
@@ -73,6 +73,7 @@ package pv_rst_pkg;
    `include "src/pv_rst_random_sequence.svh"
    `include "src/pv_rst_cold_rst_sequence.svh"
    `include "src/pv_rst_warm_rst_sequence.svh"
+   `include "src/pv_rst_core_rst_sequence.svh"
    `include "src/pv_rst_poweron_sequence.svh"
 
    `include "src/pv_rst_responder_sequence.svh"
diff --git a/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/src/pv_rst_cold_rst_sequence.svh b/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/src/pv_rst_cold_rst_sequence.svh
index a9cb3b752..f7b5ec767 100644
--- a/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/src/pv_rst_cold_rst_sequence.svh
+++ b/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/src/pv_rst_cold_rst_sequence.svh
@@ -55,6 +55,7 @@ class pv_rst_cold_rst_sequence extends pv_rst_sequence_base;
     `uvm_info("PV_RST_COLD_RST", "Asserting reset, pwrgood low", UVM_MEDIUM)
     req.set_pwrgood = 1'b0;
     req.assert_rst = 1'b1;
+    req.assert_core_rst = 1'b1;
 
     finish_item(req);
     `uvm_info("PV_RST_COLD_RST", {"Response:",req.convert2string()},UVM_MEDIUM)
@@ -67,6 +68,7 @@ class pv_rst_cold_rst_sequence extends pv_rst_sequence_base;
     `uvm_info("PV_RST_COLD_RST", "Asserting reset, pwrgood high", UVM_MEDIUM)
     req.set_pwrgood = 1'b1;
     req.assert_rst = 1'b1;
+    req.assert_core_rst = 1'b1;
 
     finish_item(req);
     `uvm_info("PV_RST_COLD_RST", {"Response:",req.convert2string()},UVM_MEDIUM)
@@ -79,6 +81,7 @@ class pv_rst_cold_rst_sequence extends pv_rst_sequence_base;
     `uvm_info("PV_RST_COLD_RST", "Asserting reset, pwrgood high", UVM_MEDIUM)
     req.set_pwrgood = 1'b1;
     req.assert_rst = 1'b0;
+    req.assert_core_rst = 1'b0;
 
     finish_item(req);
     `uvm_info("PV_RST_COLD_RST", {"Response:",req.convert2string()},UVM_MEDIUM)
@@ -87,4 +90,4 @@ class pv_rst_cold_rst_sequence extends pv_rst_sequence_base;
 
 endtask
 
-endclass
\ No newline at end of file
+endclass
diff --git a/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/src/pv_rst_core_rst_sequence.svh b/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/src/pv_rst_core_rst_sequence.svh
new file mode 100644
index 000000000..52514ba80
--- /dev/null
+++ b/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/src/pv_rst_core_rst_sequence.svh
@@ -0,0 +1,79 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION:
+// This sequences randomizes the soc_ifc_ctrl transaction and sends it
+// to the UVM driver.
+//
+// This sequence constructs and randomizes a soc_ifc_ctrl_transaction.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class pv_rst_core_rst_sequence extends pv_rst_sequence_base;
+
+    `uvm_object_utils( pv_rst_core_rst_sequence )
+
+    //*****************************************************************
+  function new(string name = "");
+    super.new(name);
+  endfunction: new
+
+  // ****************************************************************************
+  // TASK : body()
+  // This task is automatically executed when this sequence is started using the
+  // start(sequencerHandle) task.
+  //
+
+  task body();
+
+    // Assert core reset
+    req=pv_rst_transaction::type_id::create("pwr_req");
+    start_item(req);
+    // Randomize the transaction
+    if(!req.randomize()) `uvm_fatal("PV_RST_CORE_RST", "pv_rst_core_rst_sequence::body()-pv_rst_transaction randomization failed")
+    `uvm_info("PV_RST_CORE_RST", "Asserting core reset", UVM_MEDIUM)
+    req.set_pwrgood = 1'b1;
+    req.assert_rst = 1'b0;
+    req.assert_core_rst = 1'b1;
+
+    finish_item(req);
+    `uvm_info("PV_RST_CORE_RST", {"Response:",req.convert2string()},UVM_MEDIUM)
+    
+    // Deassert core reset
+    req=pv_rst_transaction::type_id::create("rst_req");
+    start_item(req);
+    // Randomize the transaction
+    if(!req.randomize()) `uvm_fatal("PV_RST_CORE_RST", "pv_rst_core_rst_sequence::body()-pv_rst_transaction randomization failed")
+    `uvm_info("PV_RST_CORE_RST", "Deasserting core reset", UVM_MEDIUM)
+    req.set_pwrgood = 1'b1;
+    req.assert_rst = 1'b0;
+    req.assert_core_rst = 1'b0;
+
+    finish_item(req);
+    `uvm_info("PV_RST_CORE_RST", {"Response:",req.convert2string()},UVM_MEDIUM)
+
+    
+
+endtask
+
+endclass
diff --git a/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/src/pv_rst_driver_bfm.sv b/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/src/pv_rst_driver_bfm.sv
index 2a16dc139..ddc3fad6e 100644
--- a/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/src/pv_rst_driver_bfm.sv
+++ b/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/src/pv_rst_driver_bfm.sv
@@ -110,6 +110,10 @@ end
   reg  cptra_pwrgood_o = 'bz;
   tri  rst_b_i;
   reg  rst_b_o = 'bz;
+  tri  core_only_rst_b_i;
+  reg  core_only_rst_b_o = 'bz;
+  tri  fw_update_rst_window_i;
+  reg  fw_update_rst_window_o = 'bz;
 
   // Bi-directional signals
   
@@ -127,6 +131,10 @@ end
   assign cptra_pwrgood_i = bus.cptra_pwrgood;
   assign bus.rst_b = (initiator_responder == INITIATOR) ? rst_b_o : 'bz;
   assign rst_b_i = bus.rst_b;
+  assign bus.core_only_rst_b = (initiator_responder == INITIATOR) ? core_only_rst_b_o : 'bz;
+  assign core_only_rst_b_i = bus.core_only_rst_b;
+  assign bus.fw_update_rst_window = (initiator_responder == INITIATOR) ? fw_update_rst_window_o : 'bz;
+  assign fw_update_rst_window_i = bus.fw_update_rst_window;
 
   // Proxy handle to UVM driver
   pv_rst_pkg::pv_rst_driver   proxy;
@@ -160,6 +168,8 @@ end
        // INITIATOR mode output signals
        cptra_pwrgood_o <= 'bz;
        rst_b_o <= 'bz;
+       core_only_rst_b_o <= 'bz;
+       fw_update_rst_window_o <= 'bz;
        // Bi-directional signals
  
      end    
@@ -201,10 +211,12 @@ end
        // Members within the pv_rst_initiator_struct:
        //   bit set_pwrgood ;
        //   bit assert_rst ;
+       //   bit assert_core_rst ;
        //   int unsigned wait_cycles ;
        // Members within the pv_rst_responder_struct:
        //   bit set_pwrgood ;
        //   bit assert_rst ;
+       //   bit assert_core_rst ;
        //   int unsigned wait_cycles ;
        initiator_struct = pv_rst_initiator_struct;
        //
@@ -222,6 +234,7 @@ end
        //    Initiator output signals
        //      cptra_pwrgood_o <= pv_rst_initiator_struct.xyz;  //     
        //      rst_b_o <= pv_rst_initiator_struct.xyz;  //     
+       //      core_rst_b_o <= pv_rst_initiator_struct.xyz;  //     
        //    Initiator inout signals
     // Initiate a transfer using the data received.
     @(posedge clk_i);
@@ -229,8 +242,13 @@ end
 
     if (initiator_struct.assert_rst)
       rst_b_o <= 1'b0;
+    if (initiator_struct.assert_core_rst)
+      fw_update_rst_window_o <= 1'b1;
+    if (initiator_struct.assert_core_rst)
+      core_only_rst_b_o <= 1'b0;
     if (!initiator_struct.set_pwrgood)
       cptra_pwrgood_o <= 1'b0;
+    
     // Wait for the responder to complete the transfer then place the responder data into 
     // pv_rst_responder_struct.
     @(posedge clk_i);
@@ -238,14 +256,18 @@ end
 
     if (!initiator_struct.assert_rst)
       rst_b_o <= 1'b1;
+    if (!initiator_struct.assert_core_rst)
+      fw_update_rst_window_o <= 1'b0;
+    if (!initiator_struct.assert_core_rst)
+      core_only_rst_b_o <= 1'b1;
     if (initiator_struct.set_pwrgood)
       cptra_pwrgood_o <= 1'b1;
 
     repeat(initiator_struct.wait_cycles)
       @(posedge clk_i);
-      
     pv_rst_responder_struct.set_pwrgood = cptra_pwrgood_i;
     pv_rst_responder_struct.assert_rst = !rst_b_i;
+    pv_rst_responder_struct.assert_core_rst = !core_only_rst_b_i;
     responder_struct = pv_rst_responder_struct;
   endtask        
 // pragma uvmf custom initiate_and_get_response end
@@ -285,6 +307,7 @@ bit first_transfer=1;
        //    Responder input signals
        //      pv_rst_responder_struct.xyz = cptra_pwrgood_i;  //     
        //      pv_rst_responder_struct.xyz = rst_b_i;  //     
+       //      pv_rst_responder_struct.xyz = core_rst_b_i;  //     
        //    Responder inout signals
        //    How to assign a signal, named xyz, from an initiator struct member.   
        //    All available responder output and inout signals listed.
diff --git a/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/src/pv_rst_if.sv b/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/src/pv_rst_if.sv
index 5f2c7212b..cace82312 100644
--- a/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/src/pv_rst_if.sv
+++ b/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/src/pv_rst_if.sv
@@ -35,6 +35,8 @@
 //
 // .dut_signal_port(pv_rst_bus.cptra_pwrgood), // Agent output 
 // .dut_signal_port(pv_rst_bus.rst_b), // Agent output 
+// .dut_signal_port(pv_rst_bus.core_only_rst_b), // Agent output 
+// .dut_signal_port(pv_rst_bus.debug_locked), // Agent output 
 
 import uvmf_base_pkg_hdl::*;
 import pv_rst_pkg_hdl::*;
@@ -45,7 +47,9 @@ interface  pv_rst_if
   input tri clk, 
   input tri dummy,
   inout tri  cptra_pwrgood,
-  inout tri  rst_b
+  inout tri  rst_b,
+  inout tri  core_only_rst_b,
+  inout tri  fw_update_rst_window
   );
 
 modport monitor_port 
@@ -53,7 +57,9 @@ modport monitor_port
   input clk,
   input dummy,
   input cptra_pwrgood,
-  input rst_b
+  input rst_b,
+  input core_only_rst_b,
+  input fw_update_rst_window
   );
 
 modport initiator_port 
@@ -61,7 +67,9 @@ modport initiator_port
   input clk,
   input dummy,
   output cptra_pwrgood,
-  output rst_b
+  output rst_b,
+  output core_only_rst_b,
+  output fw_update_rst_window
   );
 
 modport responder_port 
@@ -69,7 +77,9 @@ modport responder_port
   input clk,
   input dummy,  
   input cptra_pwrgood,
-  input rst_b
+  input rst_b,
+  input core_only_rst_b,
+  input fw_update_rst_window
   );
   
 
diff --git a/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/src/pv_rst_macros.svh b/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/src/pv_rst_macros.svh
index 59f50d1e4..b55b0f361 100644
--- a/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/src/pv_rst_macros.svh
+++ b/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/src/pv_rst_macros.svh
@@ -65,6 +65,7 @@ typedef struct packed  { \
   `define pv_rst_MONITOR_STRUCT typedef struct packed  { \
   bit set_pwrgood ; \
   bit assert_rst ; \
+  bit assert_core_rst ; \
   int unsigned wait_cycles ; \
      } pv_rst_monitor_s;
 
@@ -74,6 +75,7 @@ typedef struct packed  { \
             { \
             this.set_pwrgood , \
             this.assert_rst , \
+            this.assert_core_rst , \
             this.wait_cycles  \
             };\
     return ( pv_rst_monitor_struct);\
@@ -84,6 +86,7 @@ typedef struct packed  { \
             {\
             this.set_pwrgood , \
             this.assert_rst , \
+            this.assert_core_rst , \
             this.wait_cycles  \
             } = pv_rst_monitor_struct;\
   endfunction
@@ -96,6 +99,7 @@ typedef struct packed  { \
   `define pv_rst_INITIATOR_STRUCT typedef struct packed  { \
   bit set_pwrgood ; \
   bit assert_rst ; \
+  bit assert_core_rst ; \
   int unsigned wait_cycles ; \
      } pv_rst_initiator_s;
 
@@ -105,6 +109,7 @@ typedef struct packed  { \
            {\
            this.set_pwrgood , \
            this.assert_rst , \
+           this.assert_core_rst , \
            this.wait_cycles  \
            };\
     return ( pv_rst_initiator_struct);\
@@ -115,6 +120,7 @@ typedef struct packed  { \
            {\
            this.set_pwrgood , \
            this.assert_rst , \
+           this.assert_core_rst , \
            this.wait_cycles  \
            } = pv_rst_initiator_struct;\
   endfunction
@@ -127,6 +133,7 @@ typedef struct packed  { \
   `define pv_rst_RESPONDER_STRUCT typedef struct packed  { \
   bit set_pwrgood ; \
   bit assert_rst ; \
+  bit assert_core_rst ; \
   int unsigned wait_cycles ; \
      } pv_rst_responder_s;
 
@@ -136,6 +143,7 @@ typedef struct packed  { \
            {\
            this.set_pwrgood , \
            this.assert_rst , \
+           this.assert_core_rst , \
            this.wait_cycles  \
            };\
     return ( pv_rst_responder_struct);\
@@ -146,6 +154,7 @@ typedef struct packed  { \
            {\
            this.set_pwrgood , \
            this.assert_rst , \
+           this.assert_core_rst , \
            this.wait_cycles  \
            } = pv_rst_responder_struct;\
   endfunction
diff --git a/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/src/pv_rst_monitor_bfm.sv b/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/src/pv_rst_monitor_bfm.sv
index 5bba0d474..b3dc8321e 100644
--- a/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/src/pv_rst_monitor_bfm.sv
+++ b/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/src/pv_rst_monitor_bfm.sv
@@ -85,23 +85,31 @@ end
   tri dummy_i;
   tri  cptra_pwrgood_i;
   tri  rst_b_i;
+  tri  core_only_rst_b_i;
+  tri  fw_update_rst_window_i;
   assign clk_i = bus.clk;
   assign dummy_i = bus.dummy;
   assign cptra_pwrgood_i = bus.cptra_pwrgood;
   assign rst_b_i = bus.rst_b;
+  assign core_only_rst_b_i = bus.core_only_rst_b;
+  assign fw_update_rst_window_i = bus.fw_update_rst_window;
 
   // Proxy handle to UVM monitor
   pv_rst_pkg::pv_rst_monitor  proxy;
   // pragma tbx oneway proxy.notify_transaction                 
 
   // pragma uvmf custom interface_item_additional begin
-  reg cptra_pwrgood_o = 'b0;
-  reg rst_b_o = 'b0;
+    reg cptra_pwrgood_o = 'b0;
+    reg rst_b_o = 'b0;
+    reg core_only_rst_b_o = 'b0;
+    reg fw_update_rst_window_o = 'b0;
 
   function bit any_signal_changed();
 
-    return  |(cptra_pwrgood_i ^ cptra_pwrgood_o) ||
-            |(rst_b_i ^ rst_b_o);
+      return  |(cptra_pwrgood_i ^ cptra_pwrgood_o) ||
+              |(rst_b_i ^ rst_b_o) ||
+              |(core_only_rst_b_i ^ core_only_rst_b_o) ||
+              |(fw_update_rst_window_i ^ fw_update_rst_window_o);
   
   endfunction
   // pragma uvmf custom interface_item_additional end
diff --git a/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/src/pv_rst_poweron_sequence.svh b/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/src/pv_rst_poweron_sequence.svh
index c29898b8b..2ecb8e93a 100644
--- a/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/src/pv_rst_poweron_sequence.svh
+++ b/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/src/pv_rst_poweron_sequence.svh
@@ -54,6 +54,7 @@ class pv_rst_poweron_sequence extends pv_rst_sequence_base;
     `uvm_info("PV_RST_POWERON", "Asserting reset, pwrgood low", UVM_MEDIUM)
     req.set_pwrgood = 1'b0;
     req.assert_rst = 1'b1;
+    req.assert_core_rst = 1'b1;
     finish_item(req);
     `uvm_info("PV_RST_POWERON", {"Response:",req.convert2string()},UVM_MEDIUM)
     
@@ -65,6 +66,7 @@ class pv_rst_poweron_sequence extends pv_rst_sequence_base;
     `uvm_info("PV_RST_POWERON", "Asserting reset, pwrgood high", UVM_MEDIUM)
     req.set_pwrgood = 1'b1;
     req.assert_rst = 1'b1;
+    req.assert_core_rst = 1'b1;
     finish_item(req);
     `uvm_info("PV_RST_POWERON", {"Response:",req.convert2string()},UVM_MEDIUM)
 
@@ -76,9 +78,10 @@ class pv_rst_poweron_sequence extends pv_rst_sequence_base;
     `uvm_info("PV_RST_POWERON", "Deasserting reset, reset phase done", UVM_MEDIUM)
     req.set_pwrgood = 1'b1;
     req.assert_rst = 1'b0;
+    req.assert_core_rst = 1'b0;
     finish_item(req);
     `uvm_info("PV_RST_POWERON", {"Response:",req.convert2string()},UVM_MEDIUM)
 
 endtask
 
-endclass
\ No newline at end of file
+endclass
diff --git a/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/src/pv_rst_transaction.svh b/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/src/pv_rst_transaction.svh
index 952e04a3f..63d478dd3 100644
--- a/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/src/pv_rst_transaction.svh
+++ b/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/src/pv_rst_transaction.svh
@@ -34,6 +34,7 @@ class pv_rst_transaction  extends uvmf_transaction_base;
 
   bit set_pwrgood ;
   bit assert_rst ;
+  bit assert_core_rst ;
   rand int unsigned wait_cycles ;
 
   //Constraints for the transaction variables:
@@ -118,7 +119,7 @@ class pv_rst_transaction  extends uvmf_transaction_base;
   virtual function string convert2string();
     // pragma uvmf custom convert2string begin
     // UVMF_CHANGE_ME : Customize format if desired.
-    return $sformatf("set_pwrgood:0x%x assert_rst:0x%x wait_cycles:0x%x ",set_pwrgood,assert_rst,wait_cycles);
+    return $sformatf("set_pwrgood:0x%x assert_rst:0x%x assert_core_rst:0x%x wait_cycles:0x%x",set_pwrgood,assert_rst,assert_core_rst,wait_cycles);
     // pragma uvmf custom convert2string end
   endfunction
 
@@ -162,6 +163,7 @@ class pv_rst_transaction  extends uvmf_transaction_base;
     super.do_copy(rhs);
     this.set_pwrgood = RHS.set_pwrgood;
     this.assert_rst = RHS.assert_rst;
+    this.assert_core_rst = RHS.assert_core_rst;
     this.wait_cycles = RHS.wait_cycles;
     // pragma uvmf custom do_copy end
   endfunction
@@ -188,6 +190,7 @@ class pv_rst_transaction  extends uvmf_transaction_base;
     // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer
     $add_attribute(transaction_view_h,set_pwrgood,"set_pwrgood");
     $add_attribute(transaction_view_h,assert_rst,"assert_rst");
+    $add_attribute(transaction_view_h,assert_core_rst,"assert_core_rst");
     $add_attribute(transaction_view_h,wait_cycles,"wait_cycles");
     // pragma uvmf custom add_to_wave end
     $end_transaction(transaction_view_h,end_time);
diff --git a/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/src/pv_rst_warm_rst_sequence.svh b/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/src/pv_rst_warm_rst_sequence.svh
index 1b2bc9229..fe69382bd 100644
--- a/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/src/pv_rst_warm_rst_sequence.svh
+++ b/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_rst_pkg/src/pv_rst_warm_rst_sequence.svh
@@ -54,6 +54,7 @@ class pv_rst_warm_rst_sequence extends pv_rst_sequence_base;
     `uvm_info("PV_RST_WARM_RST", "Asserting reset, pwrgood low", UVM_MEDIUM)
     req.set_pwrgood = 1'b1;
     req.assert_rst = 1'b1;
+    req.assert_core_rst = 1'b1;
 
     finish_item(req);
     `uvm_info("PV_RST_WARM_RST", {"Response:",req.convert2string()},UVM_MEDIUM)
@@ -66,6 +67,7 @@ class pv_rst_warm_rst_sequence extends pv_rst_sequence_base;
     `uvm_info("PV_RST_WARM_RST", "Asserting reset, pwrgood high", UVM_MEDIUM)
     req.set_pwrgood = 1'b1;
     req.assert_rst = 1'b0;
+    req.assert_core_rst = 1'b0;
 
     finish_item(req);
     `uvm_info("PV_RST_WARM_RST", {"Response:",req.convert2string()},UVM_MEDIUM)
@@ -74,4 +76,4 @@ class pv_rst_warm_rst_sequence extends pv_rst_sequence_base;
 
 endtask
 
-endclass
\ No newline at end of file
+endclass
diff --git a/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_write_pkg/src/pv_write_transaction_coverage.svh b/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_write_pkg/src/pv_write_transaction_coverage.svh
index ced39224e..56d90ec39 100644
--- a/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_write_pkg/src/pv_write_transaction_coverage.svh
+++ b/src/pcrvault/uvmf_pv/uvmf_template_output/verification_ip/interface_packages/pv_write_pkg/src/pv_write_transaction_coverage.svh
@@ -28,6 +28,15 @@
 //----------------------------------------------------------------------
 //----------------------------------------------------------------------
 //
+covergroup wr_data(input logic wr_data_bit);
+  //option.per_instance = 1;
+  value: coverpoint wr_data_bit;
+  transition:  coverpoint wr_data_bit {
+    bins bin01 = (0 => 1); 
+    bins bin10 = (1 => 0);
+  }
+endgroup
+
 class pv_write_transaction_coverage #(
       string PV_WRITE_REQUESTOR = "SHA512"
       )
@@ -44,6 +53,7 @@ class pv_write_transaction_coverage #(
   T coverage_trans;
 
   // pragma uvmf custom class_item_additional begin
+    wr_data wr_data_bus[PV_DATA_W];
   // pragma uvmf custom class_item_additional end
   
   // ****************************************************************************
@@ -57,7 +67,6 @@ class pv_write_transaction_coverage #(
     write_offset: coverpoint coverage_trans.write_offset {
       illegal_bins wr_offset_12_15 = {['d12:'d15]};
     }
-    //write_data: coverpoint coverage_trans.write_data;
     error: coverpoint coverage_trans.error {
       ignore_bins error1 = {'d1};
     }
@@ -90,7 +99,13 @@ class pv_write_transaction_coverage #(
   virtual function void write (T t);
     `uvm_info("COV","Received transaction",UVM_HIGH);
     coverage_trans = t;
+
+    foreach(wr_data_bus[i]) wr_data_bus[i] = new(coverage_trans.write_data[i]);
+    foreach(wr_data_bus[i]) wr_data_bus[i].set_inst_name($sformatf("wr_data_bus[%0d]_%s",i,get_full_name()));
+
     pv_write_transaction_cg.sample();
+    foreach(wr_data_bus[i]) wr_data_bus[i].sample();
+    
   endfunction
 
 endclass
diff --git a/src/prim/config/compile.yml b/src/prim/config/compile.yml
deleted file mode 100644
index ae69e7735..000000000
--- a/src/prim/config/compile.yml
+++ /dev/null
@@ -1,71 +0,0 @@
----
-provides: [prim_pkg]
-schema_version: 2.4.0
-targets:
-  rtl:
-    directories: [$COMPILE_ROOT/rtl]
-    files:
-      - $COMPILE_ROOT/rtl/prim_util_pkg.sv
-      - $COMPILE_ROOT/rtl/prim_alert_pkg.sv
-      - $COMPILE_ROOT/rtl/prim_subreg_pkg.sv
-      - $COMPILE_ROOT/rtl/prim_mubi_pkg.sv
-      - $COMPILE_ROOT/rtl/prim_cipher_pkg.sv
-      - $COMPILE_ROOT/rtl/prim_pkg.sv
-  tb:
-    directories: [$COMPILE_ROOT/rtl]
-    files:
-      - $COMPILE_ROOT/rtl/prim_util_pkg.sv
-      - $COMPILE_ROOT/rtl/prim_alert_pkg.sv
-      - $COMPILE_ROOT/rtl/prim_subreg_pkg.sv
-      - $COMPILE_ROOT/rtl/prim_mubi_pkg.sv
-      - $COMPILE_ROOT/rtl/prim_cipher_pkg.sv
-      - $COMPILE_ROOT/rtl/prim_pkg.sv
----
-provides: [prim]
-schema_version: 2.4.0
-requires:
-  - libs
-  - lc_ctrl_pkg
-  - prim_pkg
-  - prim_generic
-targets:
-  rtl:
-    directories: [$COMPILE_ROOT/rtl]
-    files:
-#      - $COMPILE_ROOT/rtl/prim_flop_macros.sv
-      - $COMPILE_ROOT/rtl/prim_flop_en.sv
-      - $COMPILE_ROOT/rtl/prim_flop_2sync.sv
-      - $COMPILE_ROOT/rtl/prim_lfsr.sv
-      - $COMPILE_ROOT/rtl/prim_mubi4_sync.sv
-      - $COMPILE_ROOT/rtl/prim_diff_decode.sv
-      - $COMPILE_ROOT/rtl/prim_sec_anchor_buf.sv
-      - $COMPILE_ROOT/rtl/prim_slicer.sv
-#      - $COMPILE_ROOT/rtl/prim_assert_dummy_macros.svh
-      - $COMPILE_ROOT/rtl/prim_count.sv
-#      - $COMPILE_ROOT/rtl/prim_assert_yosys_macros.svh
-      - $COMPILE_ROOT/rtl/prim_sparse_fsm_flop.sv
-      - $COMPILE_ROOT/rtl/prim_dom_and_2share.sv
-      - $COMPILE_ROOT/rtl/prim_sec_anchor_flop.sv
-      - $COMPILE_ROOT/rtl/prim_reg_we_check.sv
-      - $COMPILE_ROOT/rtl/prim_packer_fifo.sv
-      - $COMPILE_ROOT/rtl/prim_max_tree.sv
-      - $COMPILE_ROOT/rtl/prim_subreg_arb.sv
-      - $COMPILE_ROOT/rtl/prim_subreg.sv
-      - $COMPILE_ROOT/rtl/prim_intr_hw.sv
-      - $COMPILE_ROOT/rtl/prim_onehot_check.sv
-      - $COMPILE_ROOT/rtl/prim_mubi8_sync.sv
-      - $COMPILE_ROOT/rtl/prim_fifo_sync_cnt.sv
-      - $COMPILE_ROOT/rtl/prim_buf.sv
-      - $COMPILE_ROOT/rtl/prim_lc_sync.sv
-      - $COMPILE_ROOT/rtl/prim_alert_receiver.sv
-#      - $COMPILE_ROOT/rtl/prim_assert_standard_macros.svh
-      - $COMPILE_ROOT/rtl/prim_flop.sv
-      - $COMPILE_ROOT/rtl/prim_alert_sender.sv
-      - $COMPILE_ROOT/rtl/prim_fifo_sync.sv
-      - $COMPILE_ROOT/rtl/prim_arbiter_ppc.sv
-#      - $COMPILE_ROOT/rtl/prim_assert.sv
-#      - $COMPILE_ROOT/rtl/prim_assert_sec_cm.svh
-      - $COMPILE_ROOT/rtl/prim_sum_tree.sv
-      - $COMPILE_ROOT/rtl/prim_subreg_ext.sv
-      - $COMPILE_ROOT/rtl/prim_edge_detector.sv
-    tops: [prim]
diff --git a/src/prim/config/prim.vf b/src/prim/config/prim.vf
deleted file mode 100644
index e87eac6c4..000000000
--- a/src/prim/config/prim.vf
+++ /dev/null
@@ -1,58 +0,0 @@
-+incdir+${CALIPTRA_ROOT}/src/integration/rtl
-+incdir+${CALIPTRA_ROOT}/src/libs/rtl
-+incdir+${CALIPTRA_ROOT}/src/prim/rtl
-+incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl
-+incdir+${CALIPTRA_ROOT}/src/prim_generic/rtl
-${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh
-${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh
-${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sva.svh
-${CALIPTRA_ROOT}/src/libs/rtl/caliptra_macros.svh
-${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sram.sv
-${CALIPTRA_ROOT}/src/libs/rtl/ahb_defines_pkg.sv
-${CALIPTRA_ROOT}/src/libs/rtl/caliptra_ahb_srom.sv
-${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
-${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
-${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
-${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_util_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_alert_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_mubi_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_cipher_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_pkg.sv
-${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv
-${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv
-${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv
-${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
-${CALIPTRA_ROOT}/src/prim_generic/rtl/prim_generic_flop.sv
-${CALIPTRA_ROOT}/src/prim_generic/rtl/prim_generic_buf.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_flop_en.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_flop_2sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_lfsr.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_mubi4_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_diff_decode.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sec_anchor_buf.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_slicer.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_count.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sparse_fsm_flop.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_dom_and_2share.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sec_anchor_flop.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_reg_we_check.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_packer_fifo.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_max_tree.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg_arb.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_intr_hw.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_onehot_check.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_mubi8_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_fifo_sync_cnt.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_buf.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_lc_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_alert_receiver.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_flop.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_alert_sender.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_fifo_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_arbiter_ppc.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sum_tree.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg_ext.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_edge_detector.sv
diff --git a/src/prim/config/prim_pkg.vf b/src/prim/config/prim_pkg.vf
deleted file mode 100644
index 9cf040afb..000000000
--- a/src/prim/config/prim_pkg.vf
+++ /dev/null
@@ -1,8 +0,0 @@
-+incdir+${CALIPTRA_ROOT}/src/prim/rtl
-${CALIPTRA_ROOT}/src/prim/rtl/prim_util_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_alert_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_mubi_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_cipher_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_pkg.sv
\ No newline at end of file
diff --git a/src/prim/lint/prim_arbiter.vlt b/src/prim/lint/prim_arbiter.vlt
deleted file mode 100644
index 42e44b2ba..000000000
--- a/src/prim/lint/prim_arbiter.vlt
+++ /dev/null
@@ -1,45 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-`verilator_config
-
-// Tell the Verilator scheduler to split up these variables into
-// separate pieces when it's figuring out process scheduling. This
-// avoids spurious UNOPTFLAT warnings caused by the fact that the
-// arrays feed into themselves (with different bits for different
-// positions in the tree).
-split_var -module "prim_arbiter_fixed" -var "data_tree"
-split_var -module "prim_arbiter_fixed" -var "gnt_tree"
-split_var -module "prim_arbiter_fixed" -var "idx_tree"
-split_var -module "prim_arbiter_fixed" -var "req_tree"
-
-split_var -module "prim_arbiter_tree" -var "req_tree"
-split_var -module "prim_arbiter_tree" -var "prio_tree"
-split_var -module "prim_arbiter_tree" -var "sel_tree"
-split_var -module "prim_arbiter_tree" -var "mask_tree"
-split_var -module "prim_arbiter_tree" -var "idx_tree"
-split_var -module "prim_arbiter_tree" -var "data_tree"
-
-// Waive ALWCOMBORDER warnings about the tree variables. We've got
-// lines like "req_tree[Pa] = req_tree[C0] | req_tree[C1];" and it
-// seems that the ALWCOMBORDER warning isn't affected by the split_var
-// rules above.
-lint_off -rule ALWCOMBORDER -file "*/rtl/prim_arbiter_fixed.sv" -match "*data_tree*"
-lint_off -rule ALWCOMBORDER -file "*/rtl/prim_arbiter_fixed.sv" -match "*gnt_tree*"
-lint_off -rule ALWCOMBORDER -file "*/rtl/prim_arbiter_fixed.sv" -match "*idx_tree*"
-lint_off -rule ALWCOMBORDER -file "*/rtl/prim_arbiter_fixed.sv" -match "*req_tree*"
-
-lint_off -rule ALWCOMBORDER -file "*/rtl/prim_arbiter_tree.sv" -match "*req_tree*"
-lint_off -rule ALWCOMBORDER -file "*/rtl/prim_arbiter_tree.sv" -match "*prio_tree*"
-lint_off -rule ALWCOMBORDER -file "*/rtl/prim_arbiter_tree.sv" -match "*sel_tree*"
-lint_off -rule ALWCOMBORDER -file "*/rtl/prim_arbiter_tree.sv" -match "*mask_tree*"
-lint_off -rule ALWCOMBORDER -file "*/rtl/prim_arbiter_tree.sv" -match "*idx_tree*"
-lint_off -rule ALWCOMBORDER -file "*/rtl/prim_arbiter_tree.sv" -match "*data_tree*"
-
-lint_off -rule ALWCOMBORDER -file "*/rtl/prim_arbiter_ppc.sv" -match "*ppc_out*"
-
-// Waive unused clk and reset signals: they're just used for
-// assertions (which Verilator doesn't see)
-lint_off -rule UNUSED -file "*/rtl/prim_arbiter_fixed.sv" -match "*clk_i*"
-lint_off -rule UNUSED -file "*/rtl/prim_arbiter_fixed.sv" -match "*rst_ni*"
diff --git a/src/prim/lint/prim_arbiter.waiver b/src/prim/lint/prim_arbiter.waiver
deleted file mode 100644
index 278740cad..000000000
--- a/src/prim/lint/prim_arbiter.waiver
+++ /dev/null
@@ -1,13 +0,0 @@
-# Copyright lowRISC contributors.
-# Licensed under the Apache License, Version 2.0, see LICENSE for details.
-# SPDX-License-Identifier: Apache-2.0
-#
-# waiver file for prim_arbiter
-
-waive -rules PARTIAL_CONST_ASSIGN -location {prim_arbiter_*.sv} -regexp {'mask.0.' is conditionally assigned a constant} \
-      -comment "makes the code more readable"
-waive -rules CONST_FF -location {prim_arbiter_*.sv} -regexp {Flip-flop 'mask.0.' is driven by constant} \
-      -comment "makes the code more readable"
-
-waive -rules {HIER_BRANCH_NOT_READ INPUT_NOT_READ} -location {prim_arbiter_fixed.sv} -regexp {.*'(clk_i|rst_ni)' is not read from in module 'prim_arbiter_fixed'.*} \
-      -comment "clk_ and rst_ni are only used for assertions in this module."
diff --git a/src/prim/lint/prim_onehot_check.waiver b/src/prim/lint/prim_onehot_check.waiver
deleted file mode 100644
index 65d5b0b33..000000000
--- a/src/prim/lint/prim_onehot_check.waiver
+++ /dev/null
@@ -1,11 +0,0 @@
-# Copyright lowRISC contributors.
-# Licensed under the Apache License, Version 2.0, see LICENSE for details.
-# SPDX-License-Identifier: Apache-2.0
-#
-# waiver file for prim_onehot_check
-
-waive -rules {HIER_BRANCH_NOT_READ INPUT_NOT_READ} -location {prim_onehot_check.sv} -regexp {.*'(clk_i|rst_ni)' is not read from in module 'prim_onehot_check'.*} \
-      -comment "clk_ and rst_ni are only used for assertions in this module."
-
-waive -rules {PARAM_NOT_USED} -location {prim_onehot_check.sv} -regexp {.*EnableAlertTriggerSVA.*} \
-      -comment "The disable parameter is used only during DV / FPV."
diff --git a/src/prim/rtl/prim_assert_sec_cm.svh b/src/prim/rtl/prim_assert_sec_cm.svh
deleted file mode 100644
index b4d132bac..000000000
--- a/src/prim/rtl/prim_assert_sec_cm.svh
+++ /dev/null
@@ -1,65 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-// // Macros and helper code for security countermeasures.
-
-`ifndef PRIM_ASSERT_SEC_CM_SVH
-`define PRIM_ASSERT_SEC_CM_SVH
-
-`define _SEC_CM_ALERT_MAX_CYC 30
-
-// Helper macros
-`define CALIPTRA_ASSERT_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, GATE_, MAX_CYCLES_, ERR_NAME_) \
-  `CALIPTRA_ASSERT(FpvSecCm``NAME_``, \
-          $rose(PRIM_HIER_.ERR_NAME_) && !(GATE_) \
-          |-> ##[0:MAX_CYCLES_] (ALERT_.alert_p)) \
-  `ifdef INC_ASSERT \
-  assign PRIM_HIER_.unused_assert_connected = 1'b1; \
-  `endif \
-  `CALIPTRA_ASSUME_FPV(``NAME_``TriggerAfterAlertInit_S, $stable(rst_ni) == 0 |-> \
-                       PRIM_HIER_.ERR_NAME_ == 0 [*10])
-
-`define CALIPTRA_ASSERT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_, MAX_CYCLES_, ERR_NAME_, CLK_, RST_) \
-  `CALIPTRA_ASSERT(FpvSecCm``NAME_``, \
-          $rose(PRIM_HIER_.ERR_NAME_) && !(GATE_) \
-          |-> ##[0:MAX_CYCLES_] (ERR_), CLK_, RST_) \
-  `ifdef INC_ASSERT \
-  assign PRIM_HIER_.unused_assert_connected = 1'b1; \
-  `endif
-
-// macros for security countermeasures that will trigger alert
-`define CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, GATE_ = 0, MAX_CYCLES_ = `_SEC_CM_ALERT_MAX_CYC) \
-  `CALIPTRA_ASSERT_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, GATE_, MAX_CYCLES_, err_o)
-
-`define CALIPTRA_ASSERT_PRIM_DOUBLE_LFSR_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, GATE_ = 0, MAX_CYCLES_ = `_SEC_CM_ALERT_MAX_CYC) \
-  `CALIPTRA_ASSERT_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, GATE_, MAX_CYCLES_, err_o)
-
-`define CALIPTRA_ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, GATE_ = 0, MAX_CYCLES_ = `_SEC_CM_ALERT_MAX_CYC) \
-  `CALIPTRA_ASSERT_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, GATE_, MAX_CYCLES_, unused_err_o)
-
-`define CALIPTRA_ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, GATE_ = 0, MAX_CYCLES_ = `_SEC_CM_ALERT_MAX_CYC) \
-  `CALIPTRA_ASSERT_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, GATE_, MAX_CYCLES_, err_o)
-
-`define CALIPTRA_ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(NAME_, REG_TOP_HIER_, ALERT_, GATE_ = 0, MAX_CYCLES_ = `_SEC_CM_ALERT_MAX_CYC) \
-  `CALIPTRA_ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ALERT(NAME_, \
-    REG_TOP_HIER_.u_prim_reg_we_check.u_prim_onehot_check, ALERT_, GATE_, MAX_CYCLES_)
-
-// macros for security countermeasures that will trigger other errors
-`define CALIPTRA_ASSERT_PRIM_FSM_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_ = 0, MAX_CYCLES_ = 2, CLK_ = clk_i, RST_ = !rst_ni) \
-  `CALIPTRA_ASSERT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_, MAX_CYCLES_, unused_err_o, CLK_, RST_)
-
-`define CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_ = 0, MAX_CYCLES_ = 2, CLK_ = clk_i, RST_ = !rst_ni) \
-  `CALIPTRA_ASSERT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_, MAX_CYCLES_, err_o, CLK_, RST_)
-
-`define CALIPTRA_ASSERT_PRIM_DOUBLE_LFSR_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_ = 0, MAX_CYCLES_ = 2, CLK_ = clk_i, RST_ = !rst_ni) \
-  `CALIPTRA_ASSERT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_, MAX_CYCLES_, err_o, CLK_, RST_)
-
-`define CALIPTRA_ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_ = 0, MAX_CYCLES_ = `_SEC_CM_ALERT_MAX_CYC, CLK_ = clk_i, RST_ = !rst_ni) \
-  `CALIPTRA_ASSERT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_, MAX_CYCLES_, err_o, CLK_, RST_)
-
-`define CALIPTRA_ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ERR(NAME_, REG_TOP_HIER_, ERR_, GATE_ = 0, MAX_CYCLES_ = `_SEC_CM_ALERT_MAX_CYC, CLK_ = clk_i, RST_ = !rst_ni) \
-  `CALIPTRA_ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ERR(NAME_, \
-    REG_TOP_HIER_.u_prim_reg_we_check.u_prim_onehot_check, ERR_, GATE_, MAX_CYCLES_, CLK_, RST_)
-
-`endif // PRIM_ASSERT_SEC_CM_SVH
diff --git a/src/prim_generic/config/compile.yml b/src/prim_generic/config/compile.yml
deleted file mode 100644
index 16a806228..000000000
--- a/src/prim_generic/config/compile.yml
+++ /dev/null
@@ -1,10 +0,0 @@
----
-provides: [prim_generic]
-schema_version: 2.4.0
-targets:
-  rtl:
-    directories: [$COMPILE_ROOT/rtl]
-    files:
-      - $COMPILE_ROOT/rtl/prim_generic_flop_en.sv
-      - $COMPILE_ROOT/rtl/prim_generic_flop.sv
-      - $COMPILE_ROOT/rtl/prim_generic_buf.sv
diff --git a/src/prim_generic/config/prim_generic.vf b/src/prim_generic/config/prim_generic.vf
deleted file mode 100644
index 844abb8b8..000000000
--- a/src/prim_generic/config/prim_generic.vf
+++ /dev/null
@@ -1,4 +0,0 @@
-+incdir+${CALIPTRA_ROOT}/src/prim_generic/rtl
-${CALIPTRA_ROOT}/src/prim_generic/rtl/prim_generic_flop_en.sv
-${CALIPTRA_ROOT}/src/prim_generic/rtl/prim_generic_flop.sv
-${CALIPTRA_ROOT}/src/prim_generic/rtl/prim_generic_buf.sv
diff --git a/src/riscv_core/veer_el2/config/compile.yml b/src/riscv_core/veer_el2/config/compile.yml
index dc78b734e..ee025269a 100755
--- a/src/riscv_core/veer_el2/config/compile.yml
+++ b/src/riscv_core/veer_el2/config/compile.yml
@@ -24,6 +24,8 @@ targets:
   rtl:
     directories: [$COMPILE_ROOT/rtl]
     files:
+      - $COMPILE_ROOT/rtl/pic_map_auto.h
+      - $COMPILE_ROOT/rtl/el2_param.vh
       - $COMPILE_ROOT/rtl/el2_mem.sv
       - $COMPILE_ROOT/rtl/el2_dma_ctrl.sv
       - $COMPILE_ROOT/rtl/el2_pic_ctrl.sv
@@ -82,6 +84,7 @@ global:
 provides: [el2_veer_wrapper_tb]  
 schema_version: 2.4.0
 requires: 
+  - caliptra_top_defines
   - el2_veer_pkg
   - el2_veer_wrapper
 targets:
diff --git a/src/riscv_core/veer_el2/config/el2_veer_pkg.vf b/src/riscv_core/veer_el2/config/el2_veer_pkg.vf
index db6fc435e..3e3824be2 100644
--- a/src/riscv_core/veer_el2/config/el2_veer_pkg.vf
+++ b/src/riscv_core/veer_el2/config/el2_veer_pkg.vf
@@ -1,10 +1,7 @@
 +incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl
-+incdir+${CALIPTRA_ROOT}/src/soc_ifc/coverage
 +incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl
 ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv
 ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv
-${CALIPTRA_ROOT}/src/soc_ifc/coverage/soc_ifc_cov_if.sv
-${CALIPTRA_ROOT}/src/soc_ifc/coverage/soc_ifc_cov_bind.sv
 ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pdef.vh
 ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/include/el2_def.sv
 ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/common_defines.sv
diff --git a/src/riscv_core/veer_el2/config/el2_veer_wrapper.vf b/src/riscv_core/veer_el2/config/el2_veer_wrapper.vf
index 23603bcfb..da326a7e7 100644
--- a/src/riscv_core/veer_el2/config/el2_veer_wrapper.vf
+++ b/src/riscv_core/veer_el2/config/el2_veer_wrapper.vf
@@ -1,10 +1,7 @@
 +incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl
-+incdir+${CALIPTRA_ROOT}/src/soc_ifc/coverage
 +incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl
 ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv
 ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv
-${CALIPTRA_ROOT}/src/soc_ifc/coverage/soc_ifc_cov_if.sv
-${CALIPTRA_ROOT}/src/soc_ifc/coverage/soc_ifc_cov_bind.sv
 ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pdef.vh
 ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/include/el2_def.sv
 ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/common_defines.sv
diff --git a/src/riscv_core/veer_el2/config/el2_veer_wrapper_tb.vf b/src/riscv_core/veer_el2/config/el2_veer_wrapper_tb.vf
index ab92b3fa9..146b42520 100644
--- a/src/riscv_core/veer_el2/config/el2_veer_wrapper_tb.vf
+++ b/src/riscv_core/veer_el2/config/el2_veer_wrapper_tb.vf
@@ -1,11 +1,11 @@
++incdir+${CALIPTRA_ROOT}/src/integration/rtl
 +incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl
-+incdir+${CALIPTRA_ROOT}/src/soc_ifc/coverage
 +incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl
 +incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/tb
+${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh
+${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh
 ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv
 ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv
-${CALIPTRA_ROOT}/src/soc_ifc/coverage/soc_ifc_cov_if.sv
-${CALIPTRA_ROOT}/src/soc_ifc/coverage/soc_ifc_cov_bind.sv
 ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pdef.vh
 ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/include/el2_def.sv
 ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/common_defines.sv
diff --git a/src/riscv_core/veer_el2/rtl/common_defines.sv b/src/riscv_core/veer_el2/rtl/common_defines.sv
index 702abf75b..afcbaa9a1 100644
--- a/src/riscv_core/veer_el2/rtl/common_defines.sv
+++ b/src/riscv_core/veer_el2/rtl/common_defines.sv
@@ -157,9 +157,11 @@
 `define RV_LDERR_ROLLBACK 1
 `define CPU_TOP `RV_TOP.veer
 `define RV_EXT_DATAWIDTH 64
+`ifndef SYNTHESIS
 `ifndef VERILATOR
     `define RV_ASSERT_ON 
 `endif
+`endif
 `define RV_EXT_ADDRWIDTH 32
 `define RV_BTB_ENABLE 1
 `define RV_BTB_BTAG_FOLD 0
diff --git a/src/riscv_core/veer_el2/rtl/el2_mem.sv b/src/riscv_core/veer_el2/rtl/el2_mem.sv
index 80e770c5c..605b3120f 100644
--- a/src/riscv_core/veer_el2/rtl/el2_mem.sv
+++ b/src/riscv_core/veer_el2/rtl/el2_mem.sv
@@ -79,7 +79,7 @@ import el2_pkg::*;
    output logic [pt.ICACHE_NUM_WAYS-1:0]   ic_rd_hit,
    output logic         ic_tag_perr,        // Icache Tag parity error
 
-   el2_mem_if           mem_export,
+   el2_mem_if.veer_sram_src mem_export,
 
 
    input  logic         scan_mode
@@ -87,13 +87,29 @@ import el2_pkg::*;
 );
 
    logic active_clk;
+   el2_mem_if mem_export_local ();
    rvoclkhdr active_cg   ( .en(1'b1),         .l1clk(active_clk), .* );
 
+   assign mem_export      .clk = clk;
+   assign mem_export_local.clk = clk;
+
+   assign mem_export      .iccm_clken         = mem_export_local.iccm_clken;
+   assign mem_export      .iccm_wren_bank     = mem_export_local.iccm_wren_bank;
+   assign mem_export      .iccm_addr_bank     = mem_export_local.iccm_addr_bank;
+   assign mem_export      .iccm_bank_wr_data  = mem_export_local.iccm_bank_wr_data;
+   assign mem_export_local.iccm_bank_dout     = mem_export.      iccm_bank_dout;
+
+   assign mem_export      .dccm_clken         = mem_export_local.dccm_clken;
+   assign mem_export      .dccm_wren_bank     = mem_export_local.dccm_wren_bank;
+   assign mem_export      .dccm_addr_bank     = mem_export_local.dccm_addr_bank;
+   assign mem_export      .dccm_wr_data_bank  = mem_export_local.dccm_wr_data_bank;
+   assign mem_export_local.dccm_bank_dout     = mem_export      .dccm_bank_dout;
+
    // DCCM Instantiation
    if (pt.DCCM_ENABLE == 1) begin: Gen_dccm_enable
       el2_lsu_dccm_mem #(.pt(pt)) dccm (
          .clk_override(dccm_clk_override),
-         .dccm_mem_export(mem_export.veer_dccm),
+         .dccm_mem_export(mem_export_local.veer_dccm),
          .*
       );
    end else begin: Gen_dccm_disable
@@ -121,7 +137,7 @@ if (pt.ICCM_ENABLE) begin : iccm
                   .clk_override(icm_clk_override),
                   .iccm_rw_addr(iccm_rw_addr[pt.ICCM_BITS-1:1]),
                   .iccm_rd_data(iccm_rd_data[63:0]),
-                  .iccm_mem_export(mem_export.veer_iccm)
+                  .iccm_mem_export(mem_export_local.veer_iccm)
                    );
 end
 else  begin
diff --git a/src/riscv_core/veer_el2/rtl/el2_veer.sv b/src/riscv_core/veer_el2/rtl/el2_veer.sv
index 56dc893c7..1ade17502 100644
--- a/src/riscv_core/veer_el2/rtl/el2_veer.sv
+++ b/src/riscv_core/veer_el2/rtl/el2_veer.sv
@@ -377,6 +377,12 @@ import el2_pkg::*;
    input logic [31:0]           dmi_reg_wdata,             // write data
    output logic [31:0]          dmi_reg_rdata,
 
+   // Caliptra ECC status signals
+   output logic                            cptra_iccm_ecc_single_error,
+   output logic                            cptra_iccm_ecc_double_error,
+   output logic                            cptra_dccm_ecc_single_error,
+   output logic                            cptra_dccm_ecc_double_error,
+
    input logic [pt.PIC_TOTAL_INT:1]           extintsrc_req,
    input logic                   timer_int,
    input logic                   soft_int,
@@ -394,6 +400,7 @@ import el2_pkg::*;
    logic                         ifu_pmu_instr_aligned;
    logic                         ifu_ic_error_start;
    logic                         ifu_iccm_rd_ecc_single_err;
+   logic                         cptra_iccm_rd_ecc_double_err;
 
    logic                         lsu_axi_awready_ahb;
    logic                         lsu_axi_wready_ahb;
@@ -857,6 +864,7 @@ import el2_pkg::*;
    // -----------------   DEBUG END -----------------------------
 
    assign core_rst_l = rst_l & (dbg_core_rst_l | scan_mode);
+
    // fetch
    el2_ifu #(.pt(pt)) ifu (
                             .clk(active_l2clk),
@@ -876,6 +884,8 @@ import el2_pkg::*;
 
                             .*
                             );
+   assign cptra_iccm_ecc_single_error = ifu_iccm_rd_ecc_single_err;
+   assign cptra_iccm_ecc_double_error = cptra_iccm_rd_ecc_double_err;
 
 
    el2_dec #(.pt(pt)) dec (
diff --git a/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv b/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv
index a97e7de9d..cec4d24cf 100755
--- a/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv
+++ b/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv
@@ -314,11 +314,18 @@ import soc_ifc_pkg::*;
    output logic [6:0]                      cptra_uncore_dmi_reg_addr,
    output logic [31:0]                     cptra_uncore_dmi_reg_wdata,
    input  security_state_t                 cptra_security_state_Latched,
+   output logic                            cptra_dmi_reg_en_preQ,
 
    input logic [31:4] core_id,
 
    // Caliptra Memory Export Interface
-   el2_mem_if                              el2_mem_export,
+   el2_mem_if.veer_sram_src                el2_mem_export,
+
+   // Caliptra ECC status signals
+   output logic                            cptra_iccm_ecc_single_error,
+   output logic                            cptra_iccm_ecc_double_error,
+   output logic                            cptra_dccm_ecc_single_error,
+   output logic                            cptra_dccm_ecc_double_error,
 
    // external MPC halt/run interface
    input logic                             mpc_debug_halt_req, // Async halt request
@@ -703,7 +710,6 @@ import soc_ifc_pkg::*;
                              .mem_export(el2_mem_export),
                              .*
                              );
-   assign el2_mem_export.clk = active_l2clk;
 
 
    //  JTAG/DMI instance
@@ -741,6 +747,7 @@ import soc_ifc_pkg::*;
 
    assign cptra_dmi_reg_en_jtag_acccess_allowed    = dmi_reg_en_preQ & cptra_jtag_access_allowed;
    assign cptra_dmi_reg_wr_en_jtag_acccess_allowed = dmi_reg_wr_en_preQ & cptra_jtag_access_allowed;
+   assign cptra_dmi_reg_en_preQ                    = dmi_reg_en_preQ;
 
    // Driving core vs uncore enables based on the right aperture
    assign dmi_reg_en                 = cptra_uncore_tap_aperture ? '0                                       : cptra_dmi_reg_en_jtag_acccess_allowed;
diff --git a/src/riscv_core/veer_el2/rtl/ifu/el2_ifu.sv b/src/riscv_core/veer_el2/rtl/ifu/el2_ifu.sv
index d36cd68bd..ddd429b1d 100644
--- a/src/riscv_core/veer_el2/rtl/ifu/el2_ifu.sv
+++ b/src/riscv_core/veer_el2/rtl/ifu/el2_ifu.sv
@@ -150,6 +150,7 @@ import el2_pkg::*;
    input  logic [77:0]               iccm_rd_data_ecc,   // Data + ECC read from ICCM.
 
    output logic                      ifu_iccm_rd_ecc_single_err, // This fetch has a single ICCM ecc  error.
+   output logic                      cptra_iccm_rd_ecc_double_err, // Output added for Caliptra reporting
 
 // Perf counter sigs
    output logic       ifu_pmu_ic_miss, // ic miss
@@ -281,7 +282,7 @@ import el2_pkg::*;
       assign ifu_bp_inst_mask_f = 1'b1;
    end
 
-
+   assign cptra_iccm_rd_ecc_double_err = |iccm_rd_ecc_double_err;
 
    // aligner
 
diff --git a/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv b/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv
index a36e86fff..a1d1c9793 100644
--- a/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv
+++ b/src/riscv_core/veer_el2/rtl/lib/beh_lib.sv
@@ -291,7 +291,7 @@ endmodule
 // special power flop for predict packet
 // format: { LEFT, RIGHT==31 }
 // LEFT # of bits will be done with rvdffe; RIGHT is enabled by LEFT[LSB] & en
-module rvdffppe #( parameter WIDTH=32 )
+module rvdffppe #( parameter integer WIDTH = 39 )
    (
      input  logic [WIDTH-1:0] din,
      input  logic             clk,
@@ -301,13 +301,13 @@ module rvdffppe #( parameter WIDTH=32 )
      output logic [WIDTH-1:0] dout
      );
 
-   localparam RIGHT = 31;
-   localparam LEFT = WIDTH - RIGHT;
+   localparam integer RIGHT = 31;
+   localparam integer LEFT  = WIDTH - RIGHT;
 
-   localparam LMSB = WIDTH-1;
-   localparam LLSB = LMSB-LEFT+1;
-   localparam RMSB = LLSB-1;
-   localparam RLSB = LLSB-RIGHT;
+   localparam integer LMSB  = WIDTH-1;
+   localparam integer LLSB  = LMSB-LEFT+1;
+   localparam integer RMSB  = LLSB-1;
+   localparam integer RLSB  = LLSB-RIGHT;
 
 
 `ifndef RV_PHYSICAL
@@ -748,7 +748,7 @@ module rvecc_decode_64  (
 
  endmodule // rvecc_decode_64
 
-
+`ifndef TECH_SPECIFIC_EC_RV_ICG
 module `TEC_RV_ICG
   (
    input logic SE, EN, CK,
@@ -773,6 +773,7 @@ module `TEC_RV_ICG
    assign Q = CK & en_ff;
 
 endmodule
+`endif
 
 `ifndef RV_FPGA_OPTIMIZE
 module rvclkhdr
@@ -786,7 +787,11 @@ module rvclkhdr
    logic   SE;
    assign       SE = 0;
 
+`ifdef TECH_SPECIFIC_EC_RV_ICG
+   `USER_EC_RV_ICG clkhdr ( .*, .EN(en), .CK(clk), .Q(l1clk));
+`else
    `TEC_RV_ICG clkhdr ( .*, .EN(en), .CK(clk), .Q(l1clk));
+`endif
 
 endmodule // rvclkhdr
 `endif
@@ -805,7 +810,11 @@ module rvoclkhdr
 `ifdef RV_FPGA_OPTIMIZE
    assign l1clk = clk;
 `else
-   `TEC_RV_ICG clkhdr ( .*, .EN(en), .CK(clk), .Q(l1clk));
+   `ifdef TECH_SPECIFIC_EC_RV_ICG
+      `USER_EC_RV_ICG clkhdr ( .*, .EN(en), .CK(clk), .Q(l1clk));
+   `else
+      `TEC_RV_ICG clkhdr ( .*, .EN(en), .CK(clk), .Q(l1clk));
+    `endif
 `endif
 
 endmodule
diff --git a/src/riscv_core/veer_el2/rtl/lib/el2_mem_if.sv b/src/riscv_core/veer_el2/rtl/lib/el2_mem_if.sv
index 2f6b22a75..1d0a83723 100644
--- a/src/riscv_core/veer_el2/rtl/lib/el2_mem_if.sv
+++ b/src/riscv_core/veer_el2/rtl/lib/el2_mem_if.sv
@@ -85,7 +85,17 @@ modport veer_dccm (
     input  dccm_bank_dout
 );
 
-modport top (
+modport veer_sram_src (
+    output clk,
+    // ICCM
+    output iccm_clken, iccm_wren_bank, iccm_addr_bank, iccm_bank_wr_data,
+    input  iccm_bank_dout,
+    // DCCM
+    output dccm_clken, dccm_wren_bank, dccm_addr_bank, dccm_wr_data_bank,
+    input  dccm_bank_dout
+);
+
+modport veer_sram_sink (
     input clk,
     // ICCM
     input  iccm_clken, iccm_wren_bank, iccm_addr_bank, iccm_bank_wr_data,
diff --git a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu.sv b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu.sv
index 06bd86907..40410c100 100644
--- a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu.sv
+++ b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu.sv
@@ -174,6 +174,10 @@ import el2_pkg::*;
    output logic [63:0]                     dccm_dma_rdata,      // lsu data for DMA dccm read
    output logic                            dccm_ready,          // lsu ready for DMA access
 
+   // Caliptra ECC status signals
+   output logic                            cptra_dccm_ecc_single_error,
+   output logic                            cptra_dccm_ecc_double_error,
+
    input logic                             scan_mode,           // scan mode
    input logic                             clk,                 // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
    input logic                             active_clk,          // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
@@ -357,6 +361,9 @@ import el2_pkg::*;
       .*
    );
 
+   assign cptra_dccm_ecc_single_error = lsu_single_ecc_error_r;
+   assign cptra_dccm_ecc_double_error = lsu_double_ecc_error_r;
+
    el2_lsu_trigger #(.pt(pt)) trigger (
       .store_data_m(store_data_m[31:0]),
       .*
diff --git a/src/riscv_core/veer_el2/tb/dasm.svi b/src/riscv_core/veer_el2/tb/dasm.svi
index ef7017d10..bdca6797a 100755
--- a/src/riscv_core/veer_el2/tb/dasm.svi
+++ b/src/riscv_core/veer_el2/tb/dasm.svi
@@ -23,7 +23,7 @@
 bit[31:0] [31:0] gpr[`RV_NUM_THREADS];
 
 // main DASM function
-function string dasm(input[31:0] opcode, input[31:0] pc, input[4:0] regn, input[31:0] regv, input tid=0);
+function static string dasm(input[31:0] opcode, input[31:0] pc, input[4:0] regn, input[31:0] regv, input tid=0);
     dasm = (opcode[1:0] == 2'b11) ? dasm32(opcode, pc, tid) : dasm16(opcode, pc, tid);
     if(regn) gpr[tid][regn] = regv;
 endfunction
@@ -31,7 +31,7 @@ endfunction
 
 ///////////////// 16 bits instructions ///////////////////////
 
-function string dasm16( input[31:0] opcode, input[31:0] pc, input tid=0);
+function static string dasm16( input[31:0] opcode, input[31:0] pc, input tid=0);
     case(opcode[1:0])
     0: return dasm16_0(opcode, tid);
     1: return dasm16_1(opcode, pc);
@@ -40,7 +40,7 @@ function string dasm16( input[31:0] opcode, input[31:0] pc, input tid=0);
     return $sformatf(".short 0x%h", opcode[15:0]);
 endfunction
 
-function string dasm16_0( input[31:0] opcode, tid);
+function static string dasm16_0( input[31:0] opcode, tid);
     case(opcode[15:13])
     3'b000: return dasm16_ciw(opcode);
     3'b001: return {"c.fld  ", dasm16_cl(opcode, tid)};
@@ -53,7 +53,7 @@ function string dasm16_0( input[31:0] opcode, tid);
     return $sformatf(".short  0x%h", opcode[15:0]);
 endfunction
 
-function string dasm16_ciw( input[31:0] opcode);
+function static string dasm16_ciw( input[31:0] opcode);
 int imm;
     imm=0;
     if(opcode[15:0] == 0) return ".short  0";
@@ -61,7 +61,7 @@ int imm;
     return $sformatf("c.addi4spn %s,0x%0h", abi_reg[opcode[4:2]+8], imm);
 endfunction
 
-function string dasm16_cl( input[31:0] opcode, input tid=0);
+function static string dasm16_cl( input[31:0] opcode, input tid=0);
 int imm;
     imm=0;
     imm[5:3] = opcode[12:10];
@@ -70,7 +70,7 @@ int imm;
     return $sformatf(" %s,%0d(%s) [%h]", abi_reg[opcode[4:2]+8], imm, abi_reg[opcode[9:7]+8], gpr[tid][opcode[9:7]+8]+imm);
 endfunction
 
-function string dasm16_1( input[31:0] opcode, input[31:0] pc);
+function static string dasm16_1( input[31:0] opcode, input[31:0] pc);
     case(opcode[15:13])
     3'b000: return opcode[11:7]==0 ? "c.nop" : {"c.addi  ",dasm16_ci(opcode)};
     3'b001: return {"c.jal   ", dasm16_cj(opcode, pc)};
@@ -83,7 +83,7 @@ function string dasm16_1( input[31:0] opcode, input[31:0] pc);
     endcase
 endfunction
 
-function string dasm16_ci( input[31:0] opcode);
+function static string dasm16_ci( input[31:0] opcode);
 int imm;
     imm=0;
     imm[4:0] = opcode[6:2];
@@ -91,7 +91,7 @@ int imm;
     return $sformatf("%s,%0d", abi_reg[opcode[11:7]], imm);
 endfunction
 
-function string dasm16_cj( input[31:0] opcode, input[31:0] pc);
+function static string dasm16_cj( input[31:0] opcode, input[31:0] pc);
 bit[31:0] imm;
     imm=0;
     {imm[11],imm[4],imm[9:8],imm[10],imm[6], imm[7],imm[3:1], imm[5]} = opcode[12:2];
@@ -99,7 +99,7 @@ bit[31:0] imm;
     return $sformatf("0x%0h", imm+pc);
 endfunction
 
-function string dasm16_cb( input[31:0] opcode, input[31:0] pc);
+function static string dasm16_cb( input[31:0] opcode, input[31:0] pc);
 bit[31:0] imm;
     imm=0;
     {imm[8],imm[4:3]} = opcode[12:10];
@@ -108,7 +108,7 @@ bit[31:0] imm;
     return $sformatf("%s,0x%0h",abi_reg[opcode[9:7]+8], imm+pc);
 endfunction
 
-function string dasm16_cr( input[31:0] opcode);
+function static string dasm16_cr( input[31:0] opcode);
 bit[31:0] imm;
 
     imm = 0;
@@ -128,7 +128,7 @@ bit[31:0] imm;
     endcase
 endfunction
 
-function string dasm16_1_3( input[31:0] opcode);
+function static string dasm16_1_3( input[31:0] opcode);
 int imm;
 
     imm=0;
@@ -145,7 +145,7 @@ int imm;
     end
 endfunction
 
-function string dasm16_2( input[31:0] opcode, input tid=0);
+function static string dasm16_2( input[31:0] opcode, input tid=0);
     case(opcode[15:13])
     3'b000: return {"c.slli  ", dasm16_ci(opcode)};
     3'b001: return {"c.fldsp ", dasm16_cls(opcode,1,tid)};
@@ -167,7 +167,7 @@ function string dasm16_2( input[31:0] opcode, input tid=0);
 endfunction
 
 
-function string dasm16_cls( input[31:0] opcode, input sh1=0, tid=0);
+function static string dasm16_cls( input[31:0] opcode, input sh1=0, tid=0);
 bit[31:0] imm;
     imm=0;
     if(sh1) {imm[4:3],imm[8:6]} = opcode[6:2];
@@ -176,7 +176,7 @@ bit[31:0] imm;
     return $sformatf("%s,0x%0h [%h]", abi_reg[opcode[11:7]], imm, gpr[tid][2]+imm);
 endfunction
 
-function string dasm16_css( input[31:0] opcode, input sh1=0, tid=0);
+function static string dasm16_css( input[31:0] opcode, input sh1=0, tid=0);
 bit[31:0] imm;
     imm=0;
     if(sh1) {imm[5:3],imm[8:6]} = opcode[12:7];
@@ -186,7 +186,7 @@ endfunction
 
 ///////////////// 32 bit instructions ///////////////////////
 
-function string dasm32( input[31:0] opcode, input[31:0] pc, input tid=0);
+function static string dasm32( input[31:0] opcode, input[31:0] pc, input tid=0);
     case(opcode[6:0])
     7'b0110111: return {"lui     ", dasm32_u(opcode)};
     7'b0010111: return {"auipc   ", dasm32_u(opcode)};
@@ -205,14 +205,14 @@ function string dasm32( input[31:0] opcode, input[31:0] pc, input tid=0);
     return $sformatf(".long   0x%h", opcode);
 endfunction
 
-function string dasm32_u( input[31:0] opcode);
+function static string dasm32_u( input[31:0] opcode);
 bit[31:0] imm;
     imm=0;
     imm[31:12] = opcode[31:12];
     return $sformatf("%s,0x%0h", abi_reg[opcode[11:7]], imm);
 endfunction
 
-function string dasm32_j( input[31:0] opcode, input[31:0] pc);
+function static string dasm32_j( input[31:0] opcode, input[31:0] pc);
 int imm;
     imm=0;
     {imm[20], imm[10:1], imm[11], imm[19:12]} = opcode[31:12];
@@ -220,7 +220,7 @@ int imm;
     return $sformatf("%s,0x%0h",abi_reg[opcode[11:7]], imm+pc);
 endfunction
 
-function string dasm32_jr( input[31:0] opcode, input[31:0] pc);
+function static string dasm32_jr( input[31:0] opcode, input[31:0] pc);
 int imm;
     imm=0;
     imm[11:1] = opcode[31:19];
@@ -228,7 +228,7 @@ int imm;
     return $sformatf("%s,%s,0x%0h",abi_reg[opcode[11:7]], abi_reg[opcode[19:15]], imm+pc);
 endfunction
 
-function string dasm32_b( input[31:0] opcode, input[31:0] pc);
+function static string dasm32_b( input[31:0] opcode, input[31:0] pc);
 int imm;
 string mn;
     imm=0;
@@ -247,7 +247,7 @@ string mn;
     return $sformatf("%s%s,%s,0x%0h", mn, abi_reg[opcode[19:15]], abi_reg[opcode[24:20]], imm+pc);
 endfunction
 
-function string dasm32_l( input[31:0] opcode, input tid=0);
+function static string dasm32_l( input[31:0] opcode, input tid=0);
 int imm;
 string mn;
     imm=0;
@@ -264,7 +264,7 @@ string mn;
     return $sformatf("%s%s,%0d(%s) [%h]", mn, abi_reg[opcode[11:7]], imm, abi_reg[opcode[19:15]], imm+gpr[tid][opcode[19:15]]);
 endfunction
 
-function string dasm32_s( input[31:0] opcode, input tid=0);
+function static string dasm32_s( input[31:0] opcode, input tid=0);
 int imm;
 string mn;
     imm=0;
@@ -280,7 +280,7 @@ string mn;
     return $sformatf("%s%s,%0d(%s) [%h]", mn, abi_reg[opcode[24:20]], imm, abi_reg[opcode[19:15]], imm+gpr[tid][opcode[19:15]]);
 endfunction
 
-function string dasm32_ai( input[31:0] opcode);
+function static string dasm32_ai( input[31:0] opcode);
 int imm;
 string mn;
     imm=0;
@@ -299,13 +299,13 @@ endcase
 return $sformatf("%s%s,%s,%0d", mn, abi_reg[opcode[11:7]], abi_reg[opcode[19:15]], imm);
 endfunction
 
-function string dasm32_si( input[31:0] opcode);
+function static string dasm32_si( input[31:0] opcode);
 int imm;
 string mn;
     imm = opcode[24:20];
     case(opcode[14:12])
     1: mn = "slli";
-    5: mn = opcode[30] ? "srli": "srai";
+    5: mn = opcode[30] ? "srai": "srli";
     endcase
 
     return $sformatf("%s    %s,%s,%0d", mn, abi_reg[opcode[11:7]], abi_reg[opcode[19:15]], imm);
@@ -313,7 +313,7 @@ endfunction
 
 
 
-function string dasm32_ar( input[31:0] opcode);
+function static string dasm32_ar( input[31:0] opcode);
 string mn;
     if(opcode[25])
         case(opcode[14:12])
@@ -340,11 +340,11 @@ string mn;
     return $sformatf("%s%s,%s,%s", mn, abi_reg[opcode[11:7]], abi_reg[opcode[19:15]], abi_reg[opcode[24:20]]);
 endfunction
 
-function string dasm32_fence( input[31:0] opcode);
+function static string dasm32_fence( input[31:0] opcode);
     return  opcode[12] ? ".i" : "";
 endfunction
 
-function string dasm32_e(input[31:0] opcode);
+function static string dasm32_e(input[31:0] opcode);
     if(opcode[31:7] == 0) return "ecall";
     else if({opcode[31:21],opcode [19:7]} == 0) return "ebreak";
     else
@@ -360,7 +360,7 @@ function string dasm32_e(input[31:0] opcode);
 endfunction
 
 
-function string dasm32_csr(input[31:0] opcode, input im=0);
+function static string dasm32_csr(input[31:0] opcode, input im=0);
 bit[11:0] csr;
     csr = opcode[31:20];
     if(im) begin
@@ -373,7 +373,7 @@ bit[11:0] csr;
 endfunction
 
 //atomics
-function string dasm32_a(input[31:0] opcode, input tid=0);
+function static string dasm32_a(input[31:0] opcode, input tid=0);
     case(opcode[31:27])
     'b00010: return $sformatf("lr.w    %s,(%s) [%h]",    abi_reg[opcode[11:7]],                         abi_reg[opcode[19:15]], gpr[tid][opcode[19:15]]);
     'b00011: return $sformatf("sc.w    %s,%s,(%s) [%h]", abi_reg[opcode[11:7]], abi_reg[opcode[24:20]], abi_reg[opcode[19:15]], gpr[tid][opcode[19:15]]);
@@ -390,6 +390,6 @@ function string dasm32_a(input[31:0] opcode, input tid=0);
     return $sformatf(".long 0x%h", opcode);
 endfunction
 
-function string dasm32_amo( input[31:0] opcode, input tid=0);
+function static string dasm32_amo( input[31:0] opcode, input tid=0);
     return $sformatf(" %s,%s,(%s) [%h]", abi_reg[opcode[11:7]], abi_reg[opcode[24:20]], abi_reg[opcode[19:15]], gpr[tid][opcode[19:15]]);
 endfunction
diff --git a/src/sha256/config/compile.yml b/src/sha256/config/compile.yml
index a753b68fc..03ecae0e0 100755
--- a/src/sha256/config/compile.yml
+++ b/src/sha256/config/compile.yml
@@ -8,9 +8,9 @@ targets:
     directories: [$COMPILE_ROOT/rtl]
     files:
       - $COMPILE_ROOT/rtl/sha256_reg_pkg.sv
+      - $COMPILE_ROOT/rtl/sha256_params_pkg.sv
       - $COMPILE_ROOT/rtl/sha256_ctrl.sv
       - $COMPILE_ROOT/rtl/sha256.sv
-      - $COMPILE_ROOT/rtl/sha256_param.sv
       - $COMPILE_ROOT/rtl/sha256_core.v
       - $COMPILE_ROOT/rtl/sha256_k_constants.v
       - $COMPILE_ROOT/rtl/sha256_w_mem.v
@@ -28,6 +28,7 @@ provides: [sha256_ctrl_tb]
 schema_version: 2.4.0
 requires: 
   - sha256_ctrl
+  - sha256_coverage
 targets:
   tb:
     directories: 
@@ -36,11 +37,24 @@ targets:
       - $COMPILE_ROOT/tb/sha256_ctrl_tb.sv
     tops: [sha256_ctrl_tb]
 ---
+provides: [sha256_coverage]  
+schema_version: 2.4.0
+requires: 
+  - sha256_ctrl
+targets:
+  tb:
+    directories: 
+      - $COMPILE_ROOT/coverage
+    files:
+      - $COMPILE_ROOT/coverage/sha256_ctrl_cov_if.sv
+      - $COMPILE_ROOT/coverage/sha256_ctrl_cov_bind.sv
+---
 provides: [sha256_random_test]  
 schema_version: 2.4.0
 requires: 
   - sha256_ctrl
   - caliptra_top_defines
+  - sha256_coverage
 targets:
   tb:
     directories: 
diff --git a/src/sha256/config/sha256_coverage.vf b/src/sha256/config/sha256_coverage.vf
new file mode 100644
index 000000000..d85e65af0
--- /dev/null
+++ b/src/sha256/config/sha256_coverage.vf
@@ -0,0 +1,26 @@
++incdir+${CALIPTRA_ROOT}/src/integration/rtl
++incdir+${CALIPTRA_ROOT}/src/libs/rtl
++incdir+${CALIPTRA_ROOT}/src/sha256/coverage
++incdir+${CALIPTRA_ROOT}/src/sha256/rtl
+${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh
+${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sva.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_macros.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sram.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_defines_pkg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_ahb_srom.sv
+${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
+${CALIPTRA_ROOT}/src/sha256/coverage/sha256_ctrl_cov_if.sv
+${CALIPTRA_ROOT}/src/sha256/coverage/sha256_ctrl_cov_bind.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
+${CALIPTRA_ROOT}/src/sha256/rtl/sha256_reg_pkg.sv
+${CALIPTRA_ROOT}/src/sha256/rtl/sha256_params_pkg.sv
+${CALIPTRA_ROOT}/src/sha256/rtl/sha256_ctrl.sv
+${CALIPTRA_ROOT}/src/sha256/rtl/sha256.sv
+${CALIPTRA_ROOT}/src/sha256/rtl/sha256_core.v
+${CALIPTRA_ROOT}/src/sha256/rtl/sha256_k_constants.v
+${CALIPTRA_ROOT}/src/sha256/rtl/sha256_w_mem.v
+${CALIPTRA_ROOT}/src/sha256/rtl/sha256_reg.sv
\ No newline at end of file
diff --git a/src/sha256/config/sha256_ctrl.vf b/src/sha256/config/sha256_ctrl.vf
index e64586dd5..1a53cf1eb 100644
--- a/src/sha256/config/sha256_ctrl.vf
+++ b/src/sha256/config/sha256_ctrl.vf
@@ -12,11 +12,12 @@ ${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
 ${CALIPTRA_ROOT}/src/sha256/rtl/sha256_reg_pkg.sv
+${CALIPTRA_ROOT}/src/sha256/rtl/sha256_params_pkg.sv
 ${CALIPTRA_ROOT}/src/sha256/rtl/sha256_ctrl.sv
 ${CALIPTRA_ROOT}/src/sha256/rtl/sha256.sv
-${CALIPTRA_ROOT}/src/sha256/rtl/sha256_param.sv
 ${CALIPTRA_ROOT}/src/sha256/rtl/sha256_core.v
 ${CALIPTRA_ROOT}/src/sha256/rtl/sha256_k_constants.v
 ${CALIPTRA_ROOT}/src/sha256/rtl/sha256_w_mem.v
diff --git a/src/sha256/config/sha256_ctrl_tb.vf b/src/sha256/config/sha256_ctrl_tb.vf
index af937e6f6..7889eaad5 100644
--- a/src/sha256/config/sha256_ctrl_tb.vf
+++ b/src/sha256/config/sha256_ctrl_tb.vf
@@ -1,5 +1,6 @@
 +incdir+${CALIPTRA_ROOT}/src/integration/rtl
 +incdir+${CALIPTRA_ROOT}/src/libs/rtl
++incdir+${CALIPTRA_ROOT}/src/sha256/coverage
 +incdir+${CALIPTRA_ROOT}/src/sha256/tb
 +incdir+${CALIPTRA_ROOT}/src/sha256/rtl
 ${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh
@@ -13,12 +14,15 @@ ${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
+${CALIPTRA_ROOT}/src/sha256/coverage/sha256_ctrl_cov_if.sv
+${CALIPTRA_ROOT}/src/sha256/coverage/sha256_ctrl_cov_bind.sv
 ${CALIPTRA_ROOT}/src/sha256/tb/sha256_ctrl_tb.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
 ${CALIPTRA_ROOT}/src/sha256/rtl/sha256_reg_pkg.sv
+${CALIPTRA_ROOT}/src/sha256/rtl/sha256_params_pkg.sv
 ${CALIPTRA_ROOT}/src/sha256/rtl/sha256_ctrl.sv
 ${CALIPTRA_ROOT}/src/sha256/rtl/sha256.sv
-${CALIPTRA_ROOT}/src/sha256/rtl/sha256_param.sv
 ${CALIPTRA_ROOT}/src/sha256/rtl/sha256_core.v
 ${CALIPTRA_ROOT}/src/sha256/rtl/sha256_k_constants.v
 ${CALIPTRA_ROOT}/src/sha256/rtl/sha256_w_mem.v
diff --git a/src/sha256/config/sha256_random_test.vf b/src/sha256/config/sha256_random_test.vf
index b8665fcb4..1d5ed66c8 100644
--- a/src/sha256/config/sha256_random_test.vf
+++ b/src/sha256/config/sha256_random_test.vf
@@ -1,5 +1,6 @@
 +incdir+${CALIPTRA_ROOT}/src/integration/rtl
 +incdir+${CALIPTRA_ROOT}/src/libs/rtl
++incdir+${CALIPTRA_ROOT}/src/sha256/coverage
 +incdir+${CALIPTRA_ROOT}/src/sha256/tb
 +incdir+${CALIPTRA_ROOT}/src/sha256/rtl
 ${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh
@@ -13,12 +14,15 @@ ${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
+${CALIPTRA_ROOT}/src/sha256/coverage/sha256_ctrl_cov_if.sv
+${CALIPTRA_ROOT}/src/sha256/coverage/sha256_ctrl_cov_bind.sv
 ${CALIPTRA_ROOT}/src/sha256/tb/sha256_random_test.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
 ${CALIPTRA_ROOT}/src/sha256/rtl/sha256_reg_pkg.sv
+${CALIPTRA_ROOT}/src/sha256/rtl/sha256_params_pkg.sv
 ${CALIPTRA_ROOT}/src/sha256/rtl/sha256_ctrl.sv
 ${CALIPTRA_ROOT}/src/sha256/rtl/sha256.sv
-${CALIPTRA_ROOT}/src/sha256/rtl/sha256_param.sv
 ${CALIPTRA_ROOT}/src/sha256/rtl/sha256_core.v
 ${CALIPTRA_ROOT}/src/sha256/rtl/sha256_k_constants.v
 ${CALIPTRA_ROOT}/src/sha256/rtl/sha256_w_mem.v
diff --git a/src/sha256/coverage/sha256_ctrl_cov_bind.sv b/src/sha256/coverage/sha256_ctrl_cov_bind.sv
new file mode 100644
index 000000000..77ffe590d
--- /dev/null
+++ b/src/sha256/coverage/sha256_ctrl_cov_bind.sv
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+module sha256_ctrl_cov_bind;
+    `ifdef FCOV
+    bind sha256_ctrl sha256_ctrl_cov_if i_sha256_ctrl_cov_if(.*);
+    `endif
+endmodule
diff --git a/src/sha256/coverage/sha256_ctrl_cov_if.sv b/src/sha256/coverage/sha256_ctrl_cov_if.sv
new file mode 100644
index 000000000..5528ca767
--- /dev/null
+++ b/src/sha256/coverage/sha256_ctrl_cov_if.sv
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+`ifndef VERILATOR
+
+interface sha256_ctrl_cov_if     
+    (
+    input logic           clk,
+    input logic           reset_n,
+    input logic           cptra_pwrgood
+
+);
+
+    logic init;
+    logic next;
+    logic mode;
+    logic zeroize;
+    logic ready;
+    logic valid;
+
+
+    logic [1 : 0] hash_cmd;
+    
+    assign init = sha256_ctrl.sha256_inst.init_reg;
+    assign next = sha256_ctrl.sha256_inst.next_reg;
+    assign mode = sha256_ctrl.sha256_inst.mode_reg;
+    assign zeroize = sha256_ctrl.sha256_inst.zeroize_reg;
+    assign ready = sha256_ctrl.sha256_inst.ready_reg;
+    assign valid = sha256_ctrl.sha256_inst.digest_valid_reg;
+
+    assign hash_cmd = {next, init};
+
+    covergroup sha256_ctrl_cov_grp @(posedge clk);
+        reset_cp: coverpoint reset_n;
+        cptra_pwrgood_cp: coverpoint cptra_pwrgood;
+
+        init_cp: coverpoint init;
+        next_cp: coverpoint next;
+        mode_cp: coverpoint mode;
+        zeroize_cp: coverpoint zeroize;
+        ready_cp: coverpoint ready;
+        valid_cp: coverpoint valid;
+
+        hash_cmd_cp: coverpoint hash_cmd  {bins cmd[]   = (0, 0 => 1, 2 => 0, 0);}
+
+        init_ready_cp: cross ready, init;
+        next_ready_cp: cross ready, next;
+        zeroize_ready_cp: cross ready, zeroize;
+        mode_ready_cp: cross ready, mode;
+        zeroize_init_cp: cross zeroize, init;
+        zeroize_next_cp: cross zeroize, next;
+
+    endgroup
+
+    sha256_ctrl_cov_grp sha256_ctrl_cov_grp1 = new();
+
+endinterface
+
+`endif
\ No newline at end of file
diff --git a/src/sha256/rtl/sha256.sv b/src/sha256/rtl/sha256.sv
index 0baca4150..991a6d089 100644
--- a/src/sha256/rtl/sha256.sv
+++ b/src/sha256/rtl/sha256.sv
@@ -2,7 +2,7 @@
 //
 // Updated by Caliptra team to modify data access width
 //
-// sha256.v
+// sha256.sv
 // --------
 // Top level wrapper for the SHA-256 hash function providing
 // a simple memory like interface with 32 bit data access.
@@ -41,6 +41,7 @@
 
 module sha256 
             import sha256_reg_pkg::*;
+            import sha256_params_pkg::*;
             #(
               parameter ADDR_WIDTH = 32,
               parameter DATA_WIDTH = 32
@@ -63,14 +64,10 @@ module sha256
 
               // Interrupts
               output wire error_intr,
-              output wire notif_intr
+              output wire notif_intr,
+              input  logic debugUnlock_or_scan_mode_switch
              );
 
-  //----------------------------------------------------------------
-  // Internal constant and parameter definitions.
-  //----------------------------------------------------------------
-  `include "sha256_param.sv"
-
   //----------------------------------------------------------------
   // Registers including update variables and write enable.
   //----------------------------------------------------------------
@@ -171,7 +168,7 @@ module sha256
     init_reg = hwif_out.SHA256_CTRL.INIT.value;
     next_reg = hwif_out.SHA256_CTRL.NEXT.value;
     mode_reg = hwif_out.SHA256_CTRL.MODE.value;
-    zeroize_reg = hwif_out.SHA256_CTRL.ZEROIZE.value;
+    zeroize_reg = hwif_out.SHA256_CTRL.ZEROIZE.value || debugUnlock_or_scan_mode_switch;
 
     hwif_in.SHA256_STATUS.READY.next = ready_reg;
     hwif_in.SHA256_STATUS.VALID.next = digest_valid_reg;
diff --git a/src/sha256/rtl/sha256_ctrl.sv b/src/sha256/rtl/sha256_ctrl.sv
index 57a09de6b..1932b70d2 100644
--- a/src/sha256/rtl/sha256_ctrl.sv
+++ b/src/sha256/rtl/sha256_ctrl.sv
@@ -46,7 +46,8 @@ module sha256_ctrl #(
 
     // Interrupt
     output logic error_intr,
-    output logic notif_intr
+    output logic notif_intr,
+    input  logic debugUnlock_or_scan_mode_switch
 );
 
     //----------------------------------------------------------------
@@ -73,7 +74,8 @@ module sha256_ctrl #(
         .read_data(sha256_read_data),
         .err(sha256_err),
         .error_intr(error_intr),
-        .notif_intr(notif_intr)
+        .notif_intr(notif_intr),
+        .debugUnlock_or_scan_mode_switch(debugUnlock_or_scan_mode_switch)
     );
 
 
diff --git a/src/sha256/rtl/sha256_param.sv b/src/sha256/rtl/sha256_params_pkg.sv
similarity index 50%
rename from src/sha256/rtl/sha256_param.sv
rename to src/sha256/rtl/sha256_params_pkg.sv
index 8c567d4db..00c36b596 100644
--- a/src/sha256/rtl/sha256_param.sv
+++ b/src/sha256/rtl/sha256_params_pkg.sv
@@ -12,31 +12,9 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 //
-  //----------------------------------------------------------------
-  // Internal constant and parameter definitions.
-  //----------------------------------------------------------------
-  localparam SHA256_ADDR_NAME0       = 32'h00000000;
-  localparam SHA256_ADDR_NAME1       = 32'h00000004;
-  localparam SHA256_ADDR_VERSION0    = 32'h00000008;
-  localparam SHA256_ADDR_VERSION1    = 32'h0000000c;
-
-  localparam SHA256_ADDR_CTRL        = 32'h00000010;
-  localparam SHA256_CTRL_INIT_BIT    = 0;
-  localparam SHA256_CTRL_NEXT_BIT    = 1;
-  localparam SHA256_CTRL_MODE_BIT    = 2;
-
-  localparam SHA256_ADDR_STATUS      = 32'h00000018;
-  //localparam STATUS_READY_BIT = 0;
-  //localparam STATUS_VALID_BIT = 1;
-
-  localparam SHA256_ADDR_BLOCK_START     = 32'h00000080;
-  localparam SHA256_ADDR_BLOCK_END       = 32'h000000bf;
-
-  localparam SHA256_ADDR_DIGEST_START    = 32'h00000100;
-  localparam SHA256_ADDR_DIGEST_END      = 32'h0000011f;
+//
 
-  localparam SHA256_ADDR_INTR_START    = 32'h00000800;
-  localparam SHA256_ADDR_INTR_END      = 32'h00000BFC;
+package sha256_params_pkg;
 
   localparam SHA256_CORE_NAME0        = 32'h61327368; // "sha2"
   localparam SHA256_CORE_NAME1        = 32'h35362d32; // "-256"
@@ -46,6 +24,7 @@
   localparam SHA256_MODE_SHA_224     = 1'h0;
   localparam SHA256_MODE_SHA_256     = 1'h1;
 
+endpackage
 //======================================================================
-// EOF sha256_param.sv
+// EOF sha256_params_pkg.sv
 //======================================================================
diff --git a/src/sha256/rtl/sha256_reg_uvm.sv b/src/sha256/rtl/sha256_reg_uvm.sv
index 350815f38..c9063ea10 100644
--- a/src/sha256/rtl/sha256_reg_uvm.sv
+++ b/src/sha256/rtl/sha256_reg_uvm.sv
@@ -3,45 +3,91 @@
 package sha256_reg_uvm;
     `include "uvm_macros.svh"
     import uvm_pkg::*;
-    
+    `include "sha256_reg_covergroups.svh"
     // Reg - sha256_reg::SHA256_NAME
     class sha256_reg__SHA256_NAME extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha256_reg__SHA256_NAME_bit_cg NAME_bit_cg[32];
+        sha256_reg__SHA256_NAME_fld_cg fld_cg;
         rand uvm_reg_field NAME;
 
         function new(string name = "sha256_reg__SHA256_NAME");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.NAME = new("NAME");
             this.NAME.configure(this, 32, 0, "RO", 1, 'h0, 0, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(NAME_bit_cg[bt]) NAME_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha256_reg__SHA256_NAME
 
     // Reg - sha256_reg::SHA256_VERSION
     class sha256_reg__SHA256_VERSION extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha256_reg__SHA256_VERSION_bit_cg VERSION_bit_cg[32];
+        sha256_reg__SHA256_VERSION_fld_cg fld_cg;
         rand uvm_reg_field VERSION;
 
         function new(string name = "sha256_reg__SHA256_VERSION");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.VERSION = new("VERSION");
             this.VERSION.configure(this, 32, 0, "RO", 1, 'h0, 0, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(VERSION_bit_cg[bt]) VERSION_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha256_reg__SHA256_VERSION
 
     // Reg - sha256_reg::SHA256_CTRL
     class sha256_reg__SHA256_CTRL extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha256_reg__SHA256_CTRL_bit_cg INIT_bit_cg[1];
+        sha256_reg__SHA256_CTRL_bit_cg NEXT_bit_cg[1];
+        sha256_reg__SHA256_CTRL_bit_cg MODE_bit_cg[1];
+        sha256_reg__SHA256_CTRL_bit_cg ZEROIZE_bit_cg[1];
+        sha256_reg__SHA256_CTRL_fld_cg fld_cg;
         rand uvm_reg_field INIT;
         rand uvm_reg_field NEXT;
         rand uvm_reg_field MODE;
         rand uvm_reg_field ZEROIZE;
 
         function new(string name = "sha256_reg__SHA256_CTRL");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.INIT = new("INIT");
@@ -52,81 +98,171 @@ package sha256_reg_uvm;
             this.MODE.configure(this, 1, 2, "WO", 0, 'h1, 1, 1, 0);
             this.ZEROIZE = new("ZEROIZE");
             this.ZEROIZE.configure(this, 1, 3, "WO", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(INIT_bit_cg[bt]) INIT_bit_cg[bt] = new();
+                foreach(NEXT_bit_cg[bt]) NEXT_bit_cg[bt] = new();
+                foreach(MODE_bit_cg[bt]) MODE_bit_cg[bt] = new();
+                foreach(ZEROIZE_bit_cg[bt]) ZEROIZE_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha256_reg__SHA256_CTRL
 
     // Reg - sha256_reg::SHA256_STATUS
     class sha256_reg__SHA256_STATUS extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha256_reg__SHA256_STATUS_bit_cg READY_bit_cg[1];
+        sha256_reg__SHA256_STATUS_bit_cg VALID_bit_cg[1];
+        sha256_reg__SHA256_STATUS_fld_cg fld_cg;
         rand uvm_reg_field READY;
         rand uvm_reg_field VALID;
 
         function new(string name = "sha256_reg__SHA256_STATUS");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.READY = new("READY");
             this.READY.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
             this.VALID = new("VALID");
             this.VALID.configure(this, 1, 1, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(READY_bit_cg[bt]) READY_bit_cg[bt] = new();
+                foreach(VALID_bit_cg[bt]) VALID_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha256_reg__SHA256_STATUS
 
     // Reg - sha256_reg::SHA256_BLOCK
     class sha256_reg__SHA256_BLOCK extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha256_reg__SHA256_BLOCK_bit_cg BLOCK_bit_cg[32];
+        sha256_reg__SHA256_BLOCK_fld_cg fld_cg;
         rand uvm_reg_field BLOCK;
 
         function new(string name = "sha256_reg__SHA256_BLOCK");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.BLOCK = new("BLOCK");
             this.BLOCK.configure(this, 32, 0, "WO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(BLOCK_bit_cg[bt]) BLOCK_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha256_reg__SHA256_BLOCK
 
     // Reg - sha256_reg::SHA256_DIGEST
     class sha256_reg__SHA256_DIGEST extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha256_reg__SHA256_DIGEST_bit_cg DIGEST_bit_cg[32];
+        sha256_reg__SHA256_DIGEST_fld_cg fld_cg;
         rand uvm_reg_field DIGEST;
 
         function new(string name = "sha256_reg__SHA256_DIGEST");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.DIGEST = new("DIGEST");
             this.DIGEST.configure(this, 32, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(DIGEST_bit_cg[bt]) DIGEST_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha256_reg__SHA256_DIGEST
 
     // Reg - sha256_reg::global_intr_en_t
     class sha256_reg__global_intr_en_t extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha256_reg__global_intr_en_t_bit_cg error_en_bit_cg[1];
+        sha256_reg__global_intr_en_t_bit_cg notif_en_bit_cg[1];
+        sha256_reg__global_intr_en_t_fld_cg fld_cg;
         rand uvm_reg_field error_en;
         rand uvm_reg_field notif_en;
 
         function new(string name = "sha256_reg__global_intr_en_t");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.error_en = new("error_en");
             this.error_en.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
             this.notif_en = new("notif_en");
             this.notif_en.configure(this, 1, 1, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(error_en_bit_cg[bt]) error_en_bit_cg[bt] = new();
+                foreach(notif_en_bit_cg[bt]) notif_en_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha256_reg__global_intr_en_t
 
     // Reg - sha256_reg::error_intr_en_t
     class sha256_reg__error_intr_en_t extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha256_reg__error_intr_en_t_bit_cg error0_en_bit_cg[1];
+        sha256_reg__error_intr_en_t_bit_cg error1_en_bit_cg[1];
+        sha256_reg__error_intr_en_t_bit_cg error2_en_bit_cg[1];
+        sha256_reg__error_intr_en_t_bit_cg error3_en_bit_cg[1];
+        sha256_reg__error_intr_en_t_fld_cg fld_cg;
         rand uvm_reg_field error0_en;
         rand uvm_reg_field error1_en;
         rand uvm_reg_field error2_en;
         rand uvm_reg_field error3_en;
 
         function new(string name = "sha256_reg__error_intr_en_t");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.error0_en = new("error0_en");
@@ -137,61 +273,131 @@ package sha256_reg_uvm;
             this.error2_en.configure(this, 1, 2, "RW", 0, 'h0, 1, 1, 0);
             this.error3_en = new("error3_en");
             this.error3_en.configure(this, 1, 3, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(error0_en_bit_cg[bt]) error0_en_bit_cg[bt] = new();
+                foreach(error1_en_bit_cg[bt]) error1_en_bit_cg[bt] = new();
+                foreach(error2_en_bit_cg[bt]) error2_en_bit_cg[bt] = new();
+                foreach(error3_en_bit_cg[bt]) error3_en_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha256_reg__error_intr_en_t
 
     // Reg - sha256_reg::notif_intr_en_t
     class sha256_reg__notif_intr_en_t extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha256_reg__notif_intr_en_t_bit_cg notif_cmd_done_en_bit_cg[1];
+        sha256_reg__notif_intr_en_t_fld_cg fld_cg;
         rand uvm_reg_field notif_cmd_done_en;
 
         function new(string name = "sha256_reg__notif_intr_en_t");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.notif_cmd_done_en = new("notif_cmd_done_en");
             this.notif_cmd_done_en.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(notif_cmd_done_en_bit_cg[bt]) notif_cmd_done_en_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha256_reg__notif_intr_en_t
 
     // Reg - sha256_reg::global_intr_t_agg_sts_dd3dcf0a
     class sha256_reg__global_intr_t_agg_sts_dd3dcf0a extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha256_reg__global_intr_t_agg_sts_dd3dcf0a_bit_cg agg_sts_bit_cg[1];
+        sha256_reg__global_intr_t_agg_sts_dd3dcf0a_fld_cg fld_cg;
         rand uvm_reg_field agg_sts;
 
         function new(string name = "sha256_reg__global_intr_t_agg_sts_dd3dcf0a");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.agg_sts = new("agg_sts");
             this.agg_sts.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(agg_sts_bit_cg[bt]) agg_sts_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha256_reg__global_intr_t_agg_sts_dd3dcf0a
 
     // Reg - sha256_reg::global_intr_t_agg_sts_e6399b4a
     class sha256_reg__global_intr_t_agg_sts_e6399b4a extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha256_reg__global_intr_t_agg_sts_e6399b4a_bit_cg agg_sts_bit_cg[1];
+        sha256_reg__global_intr_t_agg_sts_e6399b4a_fld_cg fld_cg;
         rand uvm_reg_field agg_sts;
 
         function new(string name = "sha256_reg__global_intr_t_agg_sts_e6399b4a");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.agg_sts = new("agg_sts");
             this.agg_sts.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(agg_sts_bit_cg[bt]) agg_sts_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha256_reg__global_intr_t_agg_sts_e6399b4a
 
     // Reg - sha256_reg::error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378
     class sha256_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha256_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378_bit_cg error0_sts_bit_cg[1];
+        sha256_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378_bit_cg error1_sts_bit_cg[1];
+        sha256_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378_bit_cg error2_sts_bit_cg[1];
+        sha256_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378_bit_cg error3_sts_bit_cg[1];
+        sha256_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378_fld_cg fld_cg;
         rand uvm_reg_field error0_sts;
         rand uvm_reg_field error1_sts;
         rand uvm_reg_field error2_sts;
         rand uvm_reg_field error3_sts;
 
         function new(string name = "sha256_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.error0_sts = new("error0_sts");
@@ -202,33 +408,71 @@ package sha256_reg_uvm;
             this.error2_sts.configure(this, 1, 2, "W1C", 1, 'h0, 1, 1, 0);
             this.error3_sts = new("error3_sts");
             this.error3_sts.configure(this, 1, 3, "W1C", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(error0_sts_bit_cg[bt]) error0_sts_bit_cg[bt] = new();
+                foreach(error1_sts_bit_cg[bt]) error1_sts_bit_cg[bt] = new();
+                foreach(error2_sts_bit_cg[bt]) error2_sts_bit_cg[bt] = new();
+                foreach(error3_sts_bit_cg[bt]) error3_sts_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha256_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378
 
     // Reg - sha256_reg::notif_intr_t_notif_cmd_done_sts_1c68637e
     class sha256_reg__notif_intr_t_notif_cmd_done_sts_1c68637e extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha256_reg__notif_intr_t_notif_cmd_done_sts_1c68637e_bit_cg notif_cmd_done_sts_bit_cg[1];
+        sha256_reg__notif_intr_t_notif_cmd_done_sts_1c68637e_fld_cg fld_cg;
         rand uvm_reg_field notif_cmd_done_sts;
 
         function new(string name = "sha256_reg__notif_intr_t_notif_cmd_done_sts_1c68637e");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.notif_cmd_done_sts = new("notif_cmd_done_sts");
             this.notif_cmd_done_sts.configure(this, 1, 0, "W1C", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(notif_cmd_done_sts_bit_cg[bt]) notif_cmd_done_sts_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha256_reg__notif_intr_t_notif_cmd_done_sts_1c68637e
 
     // Reg - sha256_reg::error_intr_trig_t
     class sha256_reg__error_intr_trig_t extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha256_reg__error_intr_trig_t_bit_cg error0_trig_bit_cg[1];
+        sha256_reg__error_intr_trig_t_bit_cg error1_trig_bit_cg[1];
+        sha256_reg__error_intr_trig_t_bit_cg error2_trig_bit_cg[1];
+        sha256_reg__error_intr_trig_t_bit_cg error3_trig_bit_cg[1];
+        sha256_reg__error_intr_trig_t_fld_cg fld_cg;
         rand uvm_reg_field error0_trig;
         rand uvm_reg_field error1_trig;
         rand uvm_reg_field error2_trig;
         rand uvm_reg_field error3_trig;
 
         function new(string name = "sha256_reg__error_intr_trig_t");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.error0_trig = new("error0_trig");
@@ -239,160 +483,344 @@ package sha256_reg_uvm;
             this.error2_trig.configure(this, 1, 2, "W1S", 0, 'h0, 1, 1, 0);
             this.error3_trig = new("error3_trig");
             this.error3_trig.configure(this, 1, 3, "W1S", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(error0_trig_bit_cg[bt]) error0_trig_bit_cg[bt] = new();
+                foreach(error1_trig_bit_cg[bt]) error1_trig_bit_cg[bt] = new();
+                foreach(error2_trig_bit_cg[bt]) error2_trig_bit_cg[bt] = new();
+                foreach(error3_trig_bit_cg[bt]) error3_trig_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha256_reg__error_intr_trig_t
 
     // Reg - sha256_reg::notif_intr_trig_t
     class sha256_reg__notif_intr_trig_t extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha256_reg__notif_intr_trig_t_bit_cg notif_cmd_done_trig_bit_cg[1];
+        sha256_reg__notif_intr_trig_t_fld_cg fld_cg;
         rand uvm_reg_field notif_cmd_done_trig;
 
         function new(string name = "sha256_reg__notif_intr_trig_t");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.notif_cmd_done_trig = new("notif_cmd_done_trig");
             this.notif_cmd_done_trig.configure(this, 1, 0, "W1S", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(notif_cmd_done_trig_bit_cg[bt]) notif_cmd_done_trig_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha256_reg__notif_intr_trig_t
 
     // Reg - sha256_reg::intr_count_t_cnt_35ace267
     class sha256_reg__intr_count_t_cnt_35ace267 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha256_reg__intr_count_t_cnt_35ace267_bit_cg cnt_bit_cg[32];
+        sha256_reg__intr_count_t_cnt_35ace267_fld_cg fld_cg;
         rand uvm_reg_field cnt;
 
         function new(string name = "sha256_reg__intr_count_t_cnt_35ace267");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.cnt = new("cnt");
             this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha256_reg__intr_count_t_cnt_35ace267
 
     // Reg - sha256_reg::intr_count_t_cnt_73c42c28
     class sha256_reg__intr_count_t_cnt_73c42c28 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha256_reg__intr_count_t_cnt_73c42c28_bit_cg cnt_bit_cg[32];
+        sha256_reg__intr_count_t_cnt_73c42c28_fld_cg fld_cg;
         rand uvm_reg_field cnt;
 
         function new(string name = "sha256_reg__intr_count_t_cnt_73c42c28");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.cnt = new("cnt");
             this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha256_reg__intr_count_t_cnt_73c42c28
 
     // Reg - sha256_reg::intr_count_t_cnt_d8af96ff
     class sha256_reg__intr_count_t_cnt_d8af96ff extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha256_reg__intr_count_t_cnt_d8af96ff_bit_cg cnt_bit_cg[32];
+        sha256_reg__intr_count_t_cnt_d8af96ff_fld_cg fld_cg;
         rand uvm_reg_field cnt;
 
         function new(string name = "sha256_reg__intr_count_t_cnt_d8af96ff");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.cnt = new("cnt");
             this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha256_reg__intr_count_t_cnt_d8af96ff
 
     // Reg - sha256_reg::intr_count_t_cnt_9bd7f809
     class sha256_reg__intr_count_t_cnt_9bd7f809 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha256_reg__intr_count_t_cnt_9bd7f809_bit_cg cnt_bit_cg[32];
+        sha256_reg__intr_count_t_cnt_9bd7f809_fld_cg fld_cg;
         rand uvm_reg_field cnt;
 
         function new(string name = "sha256_reg__intr_count_t_cnt_9bd7f809");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.cnt = new("cnt");
             this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha256_reg__intr_count_t_cnt_9bd7f809
 
     // Reg - sha256_reg::intr_count_t_cnt_be67d6d5
     class sha256_reg__intr_count_t_cnt_be67d6d5 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha256_reg__intr_count_t_cnt_be67d6d5_bit_cg cnt_bit_cg[32];
+        sha256_reg__intr_count_t_cnt_be67d6d5_fld_cg fld_cg;
         rand uvm_reg_field cnt;
 
         function new(string name = "sha256_reg__intr_count_t_cnt_be67d6d5");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.cnt = new("cnt");
             this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha256_reg__intr_count_t_cnt_be67d6d5
 
     // Reg - sha256_reg::intr_count_incr_t_pulse_37026c97
     class sha256_reg__intr_count_incr_t_pulse_37026c97 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha256_reg__intr_count_incr_t_pulse_37026c97_bit_cg pulse_bit_cg[1];
+        sha256_reg__intr_count_incr_t_pulse_37026c97_fld_cg fld_cg;
         rand uvm_reg_field pulse;
 
         function new(string name = "sha256_reg__intr_count_incr_t_pulse_37026c97");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.pulse = new("pulse");
             this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha256_reg__intr_count_incr_t_pulse_37026c97
 
     // Reg - sha256_reg::intr_count_incr_t_pulse_d860d977
     class sha256_reg__intr_count_incr_t_pulse_d860d977 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha256_reg__intr_count_incr_t_pulse_d860d977_bit_cg pulse_bit_cg[1];
+        sha256_reg__intr_count_incr_t_pulse_d860d977_fld_cg fld_cg;
         rand uvm_reg_field pulse;
 
         function new(string name = "sha256_reg__intr_count_incr_t_pulse_d860d977");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.pulse = new("pulse");
             this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha256_reg__intr_count_incr_t_pulse_d860d977
 
     // Reg - sha256_reg::intr_count_incr_t_pulse_87b45fe7
     class sha256_reg__intr_count_incr_t_pulse_87b45fe7 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha256_reg__intr_count_incr_t_pulse_87b45fe7_bit_cg pulse_bit_cg[1];
+        sha256_reg__intr_count_incr_t_pulse_87b45fe7_fld_cg fld_cg;
         rand uvm_reg_field pulse;
 
         function new(string name = "sha256_reg__intr_count_incr_t_pulse_87b45fe7");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.pulse = new("pulse");
             this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha256_reg__intr_count_incr_t_pulse_87b45fe7
 
     // Reg - sha256_reg::intr_count_incr_t_pulse_c1689ee6
     class sha256_reg__intr_count_incr_t_pulse_c1689ee6 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha256_reg__intr_count_incr_t_pulse_c1689ee6_bit_cg pulse_bit_cg[1];
+        sha256_reg__intr_count_incr_t_pulse_c1689ee6_fld_cg fld_cg;
         rand uvm_reg_field pulse;
 
         function new(string name = "sha256_reg__intr_count_incr_t_pulse_c1689ee6");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.pulse = new("pulse");
             this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha256_reg__intr_count_incr_t_pulse_c1689ee6
 
     // Reg - sha256_reg::intr_count_incr_t_pulse_6173128e
     class sha256_reg__intr_count_incr_t_pulse_6173128e extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha256_reg__intr_count_incr_t_pulse_6173128e_bit_cg pulse_bit_cg[1];
+        sha256_reg__intr_count_incr_t_pulse_6173128e_fld_cg fld_cg;
         rand uvm_reg_field pulse;
 
         function new(string name = "sha256_reg__intr_count_incr_t_pulse_6173128e");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.pulse = new("pulse");
             this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha256_reg__intr_count_incr_t_pulse_6173128e
 
@@ -583,4 +1011,5 @@ package sha256_reg_uvm;
         endfunction : build
     endclass : sha256_reg
 
+    `include "sha256_reg_sample.svh"
 endpackage: sha256_reg_uvm
diff --git a/src/sha256/tb/sha256_ctrl_tb.sv b/src/sha256/tb/sha256_ctrl_tb.sv
index 77ce87be5..fe99b8290 100644
--- a/src/sha256/tb/sha256_ctrl_tb.sv
+++ b/src/sha256/tb/sha256_ctrl_tb.sv
@@ -39,9 +39,8 @@ module sha256_ctrl_tb();
   parameter ADDR_VERSION1    = 32'h0000000c;
 
   parameter ADDR_CTRL        = 32'h00000010;
-  parameter CTRL_INIT_VALUE  = 8'h01;
-  parameter CTRL_NEXT_VALUE  = 8'h02;
-  parameter CTRL_MODE_VALUE  = 8'h04;
+  parameter CTRL_INIT_VALUE  = 2'h1;
+  parameter CTRL_NEXT_VALUE  = 2'h2;
 
   parameter ADDR_STATUS      = 32'h00000018;
   parameter STATUS_READY_BIT = 0;
@@ -93,6 +92,7 @@ module sha256_ctrl_tb();
 
   reg           clk_tb;
   reg           reset_n_tb;
+  reg           cptra_pwrgood_tb;
 
   reg [AHB_ADDR_WIDTH-1:0]  haddr_i_tb;
   reg [AHB_DATA_WIDTH-1:0]  hwdata_i_tb;
@@ -109,6 +109,9 @@ module sha256_ctrl_tb();
   reg [31 : 0]  read_data;
   reg [255 : 0] digest_data;
 
+  //bind coverage file
+  sha256_ctrl_cov_bind i_sha256_ctrl_cov_bind();
+
   //----------------------------------------------------------------
   // Device Under Test.
   //----------------------------------------------------------------
@@ -119,7 +122,7 @@ module sha256_ctrl_tb();
             dut (
              .clk(clk_tb),
              .reset_n(reset_n_tb),
-             .cptra_pwrgood(reset_n_tb),
+             .cptra_pwrgood(cptra_pwrgood_tb),
 
              .haddr_i(haddr_i_tb),
              .hwdata_i(hwdata_i_tb),
@@ -134,7 +137,8 @@ module sha256_ctrl_tb();
              .hrdata_o(hrdata_o_tb),
 
              .error_intr(),
-             .notif_intr()
+             .notif_intr(),
+             .debugUnlock_or_scan_mode_switch('0)
             );
 
 
@@ -171,17 +175,14 @@ module sha256_ctrl_tb();
     task reset_dut;
     begin
       $display("*** Toggle reset.");
+      cptra_pwrgood_tb = '0;
       reset_n_tb = 0;
 
       #(2 * CLK_PERIOD);
-
-      @(posedge clk_tb);
-      reset_n_tb = 1;
+      cptra_pwrgood_tb = 1;
 
       #(2 * CLK_PERIOD);
-
-      @(posedge clk_tb);
-      $display("");
+      reset_n_tb = 1;
     end
   endtask // reset_dut
 
@@ -200,6 +201,7 @@ module sha256_ctrl_tb();
 
       clk_tb        = 0;
       reset_n_tb    = 0;
+      cptra_pwrgood_tb = 0;
 
       haddr_i_tb      = 0;
       hwdata_i_tb     = 0;
@@ -246,8 +248,10 @@ module sha256_ctrl_tb();
   //----------------------------------------------------------------
   task wait_ready;
     begin
-      read_single_word(ADDR_STATUS);
-      while (hrdata_o_tb == 0)
+      read_data = 0;
+      #(CLK_PERIOD);
+
+      while (read_data == 0)
         begin
           read_single_word(ADDR_STATUS);
         end
@@ -264,22 +268,18 @@ module sha256_ctrl_tb();
   task write_single_word(input [31 : 0]  address,
                   input [31 : 0] word);
     begin
-      hsel_i_tb       <= 1;
-      haddr_i_tb      <= address;
-      hwrite_i_tb     <= 1;
-      hready_i_tb     <= 1;
-      htrans_i_tb     <= AHB_HTRANS_NONSEQ;
-      hsize_i_tb      <= 3'b010;
-      
-      @(posedge clk_tb);
-      haddr_i_tb      <= 'Z;
-      hwdata_i_tb     <= word;
-      hwrite_i_tb     <= 0;
-      htrans_i_tb     <= AHB_HTRANS_IDLE;
-      wait(hreadyout_o_tb == 1'b1);
-
-      @(posedge clk_tb);
-      hsel_i_tb       <= 0;
+      hsel_i_tb       = 1;
+      haddr_i_tb      = address;
+      hwrite_i_tb     = 1;
+      hready_i_tb     = 1;
+      htrans_i_tb     = AHB_HTRANS_NONSEQ;
+      hsize_i_tb      = 3'b010;
+      #(CLK_PERIOD);
+
+      haddr_i_tb      = 'Z;
+      hwdata_i_tb     = word;
+      hwrite_i_tb     = 0;
+      htrans_i_tb     = AHB_HTRANS_IDLE;
     end
   endtask // write_single_word
 
@@ -321,21 +321,18 @@ module sha256_ctrl_tb();
   //----------------------------------------------------------------
   task read_single_word(input [31 : 0]  address);
     begin
-      hsel_i_tb       <= 1;
-      haddr_i_tb      <= address;
-      hwrite_i_tb     <= 0;
-      hready_i_tb     <= 1;
-      htrans_i_tb     <= AHB_HTRANS_NONSEQ;
-      hsize_i_tb      <= 3'b010;
+      hsel_i_tb       = 1;
+      haddr_i_tb      = address;
+      hwrite_i_tb     = 0;
+      hready_i_tb     = 1;
+      htrans_i_tb     = AHB_HTRANS_NONSEQ;
+      hsize_i_tb      = 3'b010;
+      #(CLK_PERIOD);
       
-      @(posedge clk_tb);
-      hwdata_i_tb     <= 0;
-      haddr_i_tb      <= 'Z;
-      htrans_i_tb     <= AHB_HTRANS_IDLE;
-      wait(hreadyout_o_tb == 1'b1);
-
-      @(posedge clk_tb);
-      hsel_i_tb       <= 0;      
+      hwdata_i_tb     = 0;
+      haddr_i_tb     = 'Z;
+      htrans_i_tb     = AHB_HTRANS_IDLE;
+      read_data = hrdata_o_tb;    
     end
   endtask // read_word
 
@@ -421,22 +418,21 @@ module sha256_ctrl_tb();
 
       write_block(block);
 
-      if (mode)
-        write_single_word(ADDR_CTRL, (CTRL_MODE_VALUE + CTRL_INIT_VALUE));
-      else
-        write_single_word(ADDR_CTRL, CTRL_INIT_VALUE);
-
-      start_time = cycle_ctr;
-      
+      write_single_word(ADDR_CTRL, {mode, CTRL_INIT_VALUE});
       #CLK_PERIOD;
       hsel_i_tb       = 0;
 
       #(CLK_PERIOD);
+
+      start_time = cycle_ctr;
+
       wait_ready();
       end_time = cycle_ctr - start_time;
       $display("*** Single block test processing time = %01d cycles", end_time);
       read_digest();
 
+      write_single_word(ADDR_CTRL, {28'h0, 1'b1, 3'b0}); //zeroize
+
       // We need to ignore the LSW in SHA224 mode.
       if (mode == SHA224_MODE)
         digest_data[31 : 0] = 32'h0;
@@ -477,10 +473,8 @@ module sha256_ctrl_tb();
       // First block
       write_block(block0);
 
-      if (mode)
-        write_single_word(ADDR_CTRL, (CTRL_MODE_VALUE + CTRL_INIT_VALUE));
-      else
-        write_single_word(ADDR_CTRL, CTRL_INIT_VALUE);
+      write_single_word(ADDR_CTRL, {mode, CTRL_INIT_VALUE});
+      
       #CLK_PERIOD;
       hsel_i_tb       = 0;
 
@@ -507,10 +501,7 @@ module sha256_ctrl_tb();
       // Final block
       write_block(block1);
 
-      if (mode)
-        write_single_word(ADDR_CTRL, (CTRL_MODE_VALUE + CTRL_NEXT_VALUE));
-      else
-        write_single_word(ADDR_CTRL, CTRL_NEXT_VALUE);
+      write_single_word(ADDR_CTRL, {mode, CTRL_NEXT_VALUE});
       #CLK_PERIOD;
       hsel_i_tb       = 0;
 
@@ -518,6 +509,8 @@ module sha256_ctrl_tb();
       wait_ready();
       read_digest();
 
+      write_single_word(ADDR_CTRL, {28'h0, 1'b1, 3'b0}); //zeroize
+
       // We need to ignore the LSW in SHA224 mode.
       if (mode == SHA224_MODE)
         digest_data[31 : 0] = 32'h0;
@@ -540,6 +533,200 @@ module sha256_ctrl_tb();
   endtask // double_block_test
 
 
+  //----------------------------------------------------------------
+  // continuous_cmd_test()
+  //
+  //
+  // Perform test of a double block digest.
+  //----------------------------------------------------------------
+  task continuous_cmd_test(input         mode,
+                         input [511 : 0] block0,
+                         input [255 : 0] expected0,
+                         input [511 : 0] block1,
+                         input [255 : 0] expected1
+                        );
+    reg [31 : 0] start_time;
+    reg [31 : 0] end_time;
+
+    begin
+      $display("*** TC%01d - continuous command test started.", tc_ctr);
+
+      start_time = cycle_ctr;
+
+      // First block
+      write_block(block0);
+
+      write_single_word(ADDR_CTRL, {mode, CTRL_INIT_VALUE});
+      #CLK_PERIOD;
+      hsel_i_tb       = 0;
+
+      #(CLK_PERIOD);
+
+      for (int i=0; i<10; i++)
+        begin
+          write_single_word(ADDR_CTRL, {29'h0, mode, CTRL_INIT_VALUE});
+          #CLK_PERIOD;
+          write_single_word(ADDR_CTRL, {29'h0, mode, CTRL_NEXT_VALUE});
+          #CLK_PERIOD;
+        end
+
+      wait_ready();
+      
+      // Final block
+      write_block(block1);
+
+      write_single_word(ADDR_CTRL, {mode, CTRL_NEXT_VALUE});
+      #CLK_PERIOD;
+      hsel_i_tb       = 0;
+
+      #(CLK_PERIOD);
+
+      for (int i=0; i<10; i++)
+        begin
+          write_single_word(ADDR_CTRL, {29'h0, mode, CTRL_INIT_VALUE});
+          #CLK_PERIOD;
+          write_single_word(ADDR_CTRL, {29'h0, mode, CTRL_NEXT_VALUE});
+          #CLK_PERIOD;
+        end
+
+      wait_ready();
+
+      read_digest();
+
+      end_time = cycle_ctr - start_time;
+      $display("*** processing time = %01d cycles", end_time);
+      if (digest_data == expected1)
+        begin
+          $display("TC%01d final block: OK.", tc_ctr);
+        end
+      else
+        begin
+          $display("TC%01d: ERROR in final digest", tc_ctr);
+          $display("TC%01d: Expected: 0x%064x", tc_ctr, expected1);
+          $display("TC%01d: Got:      0x%064x", tc_ctr, digest_data);
+          error_ctr = error_ctr + 1;
+        end
+
+      $display("*** TC%01d - Continuous command test done.", tc_ctr);
+      tc_ctr = tc_ctr + 1;
+    end
+  endtask // continuous_cmd_test
+
+
+  //----------------------------------------------------------------
+  // zeroize_test()
+  //
+  //----------------------------------------------------------------
+  task zeroize_test(input           mode,
+                    input [511 : 0] block0,
+                    input [255 : 0] expected0,
+                    input [511 : 0] block1,
+                    input [255 : 0] expected1
+                  );
+    begin
+
+      $display("*** TC%01d - zeroize test started.", tc_ctr);
+
+      // First test: assert zeroize when engine is working 
+      write_block(block0);
+
+      write_single_word(ADDR_CTRL, {28'h0, 1'b0, mode, CTRL_INIT_VALUE});
+      #(10 * CLK_PERIOD);
+
+      write_single_word(ADDR_CTRL, {28'h0, 1'b1, 3'b0}); //zeroize
+      #CLK_PERIOD;
+      hsel_i_tb       = 0;
+
+      wait_ready();
+      read_digest();
+      if (digest_data == 0)
+        begin
+          $display("TC%01d final block: OK.", tc_ctr);
+        end
+      else
+        begin
+          $display("TC%01d: ERROR in final digest", tc_ctr);
+          $display("TC%01d: Expected: 0x%064x", tc_ctr, 0);
+          $display("TC%01d: Got:      0x%064x", tc_ctr, digest_data);
+          error_ctr = error_ctr + 1;
+        end
+      tc_ctr = tc_ctr + 1;
+
+      // Second test: assert zeroize with INIT
+      write_block(block0);
+
+      write_single_word(ADDR_CTRL, {28'h0, 1'b1, mode, CTRL_INIT_VALUE}); //zeroize
+      #CLK_PERIOD;
+      hsel_i_tb       = 0;
+      #(CLK_PERIOD);
+
+      wait_ready();
+      read_digest();
+      if (digest_data == 0)
+        begin
+          $display("TC%01d final block: OK.", tc_ctr);
+        end
+      else
+        begin
+          $display("TC%01d: ERROR in final digest", tc_ctr);
+          $display("TC%01d: Expected: 0x%064x", tc_ctr, 0);
+          $display("TC%01d: Got:      0x%064x", tc_ctr, digest_data);
+          error_ctr = error_ctr + 1;
+        end
+      tc_ctr = tc_ctr + 1;
+
+      // Third test: assert zeroize with NEXT      
+      write_block(block0);
+
+      write_single_word(ADDR_CTRL, {28'h0, 1'b1, mode, CTRL_NEXT_VALUE}); //zeroize
+      #CLK_PERIOD;
+      hsel_i_tb       = 0;
+      #(CLK_PERIOD);
+
+      wait_ready();
+      read_digest();
+      if (digest_data == 0)
+        begin
+          $display("TC%01d final block: OK.", tc_ctr);
+        end
+      else
+        begin
+          $display("TC%01d: ERROR in final digest", tc_ctr);
+          $display("TC%01d: Expected: 0x%064x", tc_ctr, 0);
+          $display("TC%01d: Got:      0x%064x", tc_ctr, digest_data);
+          error_ctr = error_ctr + 1;
+        end
+      tc_ctr = tc_ctr + 1;
+
+      // Forth test: assert zeroize after NEXT      
+      write_block(block0);
+
+      write_single_word(ADDR_CTRL, {mode, CTRL_NEXT_VALUE});
+      #(10 * CLK_PERIOD);
+
+      write_single_word(ADDR_CTRL, {28'h0, 1'b1, 3'b0}); //zeroize
+      #CLK_PERIOD;
+      hsel_i_tb       = 0;
+
+      wait_ready();
+      read_digest();
+      if (digest_data == 0)
+        begin
+          $display("TC%01d final block: OK.", tc_ctr);
+        end
+      else
+        begin
+          $display("TC%01d: ERROR in final digest", tc_ctr);
+          $display("TC%01d: Expected: 0x%064x", tc_ctr, 0);
+          $display("TC%01d: Got:      0x%064x", tc_ctr, digest_data);
+          error_ctr = error_ctr + 1;
+        end
+
+      $display("*** TC%01d - zeroize test done.", tc_ctr);
+      tc_ctr = tc_ctr + 1;
+    end
+  endtask // zeroize_test
+
   //----------------------------------------------------------------
   // sha224_tests()
   //
@@ -604,6 +791,10 @@ module sha256_ctrl_tb();
       res1_1 = 256'h248D6A61D20638B8E5C026930C3E6039A33CE45964FF2167F6ECEDD419DB06C1;
       double_block_test(SHA256_MODE, tc1_0, res1_0, tc1_1, res1_1);
 
+      continuous_cmd_test(SHA256_MODE, tc1_0, res1_0, tc1_1, res1_1);
+
+      zeroize_test(SHA256_MODE, tc1_0, res1_0, tc1_1, res1_1);
+
       $display("*** Testcases for sha256 functionality completed.");
     end
   endtask // sha256_tests
@@ -614,6 +805,7 @@ module sha256_ctrl_tb();
   // issue_test()
   //----------------------------------------------------------------
   task issue_test;
+    reg           mode;
     reg [511 : 0] block0;
     reg [511 : 0] block1;
     reg [511 : 0] block2;
@@ -625,6 +817,8 @@ module sha256_ctrl_tb();
     reg [511 : 0] block8;
     reg [255 : 0] expected;
     begin : issue_test;
+      mode = SHA256_MODE;
+
       block0 = 512'h6b900001_496e2074_68652061_72656120_6f662049_6f542028_496e7465_726e6574_206f6620_5468696e_6773292c_206d6f72_6520616e_64206d6f_7265626f_6f6d2c20;
       block1 = 512'h69742068_61732062_65656e20_6120756e_69766572_73616c20_636f6e73_656e7375_73207468_61742064_61746120_69732074_69732061_206e6577_20746563_686e6f6c;
       block2 = 512'h6f677920_74686174_20696e74_65677261_74657320_64656365_6e747261_6c697a61_74696f6e_2c496e20_74686520_61726561_206f6620_496f5420_28496e74_65726e65;
@@ -640,7 +834,7 @@ module sha256_ctrl_tb();
       $display("Running test for 9 block issue.");
       tc_ctr = tc_ctr + 1;
       write_block(block0);
-      write_single_word(ADDR_CTRL, (CTRL_MODE_VALUE + CTRL_INIT_VALUE));
+      write_single_word(ADDR_CTRL, {mode, CTRL_INIT_VALUE});
       #CLK_PERIOD;
       hsel_i_tb       = 0;
 
@@ -648,56 +842,56 @@ module sha256_ctrl_tb();
       wait_ready();
 
       write_block(block1);
-      write_single_word(ADDR_CTRL, (CTRL_MODE_VALUE + CTRL_NEXT_VALUE));
+      write_single_word(ADDR_CTRL, {mode, CTRL_NEXT_VALUE});
       #CLK_PERIOD;
       hsel_i_tb       = 0;      
       #(CLK_PERIOD);
       wait_ready();
 
       write_block(block2);
-      write_single_word(ADDR_CTRL, (CTRL_MODE_VALUE + CTRL_NEXT_VALUE));
+      write_single_word(ADDR_CTRL, {mode, CTRL_NEXT_VALUE});
       #CLK_PERIOD;
       hsel_i_tb       = 0;      
       #(CLK_PERIOD);
       wait_ready();
 
       write_block(block3);
-      write_single_word(ADDR_CTRL, (CTRL_MODE_VALUE + CTRL_NEXT_VALUE));
+      write_single_word(ADDR_CTRL, {mode, CTRL_NEXT_VALUE});
       #CLK_PERIOD;
       hsel_i_tb       = 0;      
       #(CLK_PERIOD);
       wait_ready();
 
       write_block(block4);
-      write_single_word(ADDR_CTRL, (CTRL_MODE_VALUE + CTRL_NEXT_VALUE));
+      write_single_word(ADDR_CTRL, {mode, CTRL_NEXT_VALUE});
       #CLK_PERIOD;
       hsel_i_tb       = 0;      
       #(CLK_PERIOD);
       wait_ready();
 
       write_block(block5);
-      write_single_word(ADDR_CTRL, (CTRL_MODE_VALUE + CTRL_NEXT_VALUE));
+      write_single_word(ADDR_CTRL, {mode, CTRL_NEXT_VALUE});
       #CLK_PERIOD;
       hsel_i_tb       = 0;      
       #(CLK_PERIOD);
       wait_ready();
 
       write_block(block6);
-      write_single_word(ADDR_CTRL, (CTRL_MODE_VALUE + CTRL_NEXT_VALUE));
+      write_single_word(ADDR_CTRL, {mode, CTRL_NEXT_VALUE});
       #CLK_PERIOD;
       hsel_i_tb       = 0;      
       #(CLK_PERIOD);
       wait_ready();
 
       write_block(block7);
-      write_single_word(ADDR_CTRL, (CTRL_MODE_VALUE + CTRL_NEXT_VALUE));
+      write_single_word(ADDR_CTRL, {mode, CTRL_NEXT_VALUE});
       #CLK_PERIOD;
       hsel_i_tb       = 0;      
       #(CLK_PERIOD);
       wait_ready();
 
       write_block(block8);
-      write_single_word(ADDR_CTRL, (CTRL_MODE_VALUE + CTRL_NEXT_VALUE));
+      write_single_word(ADDR_CTRL, {mode, CTRL_NEXT_VALUE});
       #CLK_PERIOD;
       hsel_i_tb       = 0;      
       #(CLK_PERIOD);
diff --git a/src/sha256/tb/sha256_random_test.sv b/src/sha256/tb/sha256_random_test.sv
index 677a2d73a..b391bfe9f 100644
--- a/src/sha256/tb/sha256_random_test.sv
+++ b/src/sha256/tb/sha256_random_test.sv
@@ -71,6 +71,9 @@ module sha256_random_test();
   reg [255 : 0] digest_data;
   reg [255 : 0] expected;
 
+  //bind coverage file
+  sha256_ctrl_cov_bind i_sha256_ctrl_cov_bind();
+  
   //----------------------------------------------------------------
   // Device Under Test.
   //----------------------------------------------------------------
@@ -96,7 +99,8 @@ module sha256_random_test();
              .hrdata_o(hrdata_o_tb),
 
              .error_intr(),
-             .notif_intr()
+             .notif_intr(),
+             .debugUnlock_or_scan_mode_switch('0)
             );
 
 
diff --git a/src/sha256/tb/sha256_tb.v b/src/sha256/tb/sha256_tb.v
index 43a72a504..7df65ef13 100644
--- a/src/sha256/tb/sha256_tb.v
+++ b/src/sha256/tb/sha256_tb.v
@@ -105,6 +105,7 @@ module sha256_tb();
   sha256 dut(
              .clk(tb_clk),
              .reset_n(tb_reset_n),
+             .cptra_pwrgood(),
 
              .cs(tb_cs),
              .we(tb_we),
@@ -113,7 +114,11 @@ module sha256_tb();
              .address(tb_address),
              .write_data(tb_write_data),
              .read_data(tb_read_data),
-             .error(tb_error)
+             .err(tb_error)
+
+             .error_intr(),
+             .notif_intr(),
+             .debugUnlock_or_scan_mode_switch('0)
             );
 
 
diff --git a/src/sha512/config/compile.yml b/src/sha512/config/compile.yml
index 86435f294..690ae1c4a 100755
--- a/src/sha512/config/compile.yml
+++ b/src/sha512/config/compile.yml
@@ -10,9 +10,9 @@ targets:
     directories: [$COMPILE_ROOT/rtl]
     files:
       - $COMPILE_ROOT/rtl/sha512_reg_pkg.sv
+      - $COMPILE_ROOT/rtl/sha512_params_pkg.sv
       - $COMPILE_ROOT/rtl/sha512_ctrl.sv
       - $COMPILE_ROOT/rtl/sha512.sv
-      - $COMPILE_ROOT/rtl/sha512_param.sv
       - $COMPILE_ROOT/rtl/sha512_core.v
       - $COMPILE_ROOT/rtl/sha512_h_constants.v
       - $COMPILE_ROOT/rtl/sha512_k_constants.v
@@ -31,6 +31,7 @@ provides: [sha512_ctrl_32bit_tb]
 schema_version: 2.4.0
 requires: 
   - sha512_ctrl
+  - sha512_coverage
 targets:
   tb:
     directories: 
@@ -38,6 +39,18 @@ targets:
     files:
       - $COMPILE_ROOT/tb/sha512_ctrl_32bit_tb.sv
     tops: [sha512_ctrl_32bit_tb]
+---
+provides: [sha512_coverage]  
+schema_version: 2.4.0
+requires: 
+  - sha512_ctrl
+targets:
+  tb:
+    directories: 
+      - $COMPILE_ROOT/coverage
+    files:
+      - $COMPILE_ROOT/coverage/sha512_ctrl_cov_if.sv
+      - $COMPILE_ROOT/coverage/sha512_ctrl_cov_bind.sv
 global:
   tool:
     vcs:
diff --git a/src/sha512/config/sha512_coverage.vf b/src/sha512/config/sha512_coverage.vf
new file mode 100644
index 000000000..4e7b74be1
--- /dev/null
+++ b/src/sha512/config/sha512_coverage.vf
@@ -0,0 +1,43 @@
++incdir+${CALIPTRA_ROOT}/src/integration/rtl
++incdir+${CALIPTRA_ROOT}/src/libs/rtl
++incdir+${CALIPTRA_ROOT}/src/keyvault/rtl
++incdir+${CALIPTRA_ROOT}/src/pcrvault/rtl
++incdir+${CALIPTRA_ROOT}/src/sha512/coverage
++incdir+${CALIPTRA_ROOT}/src/sha512/rtl
+${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh
+${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sva.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_macros.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sram.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_defines_pkg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_ahb_srom.sv
+${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
+${CALIPTRA_ROOT}/src/keyvault/rtl/kv_defines_pkg.sv
+${CALIPTRA_ROOT}/src/keyvault/rtl/kv_macros.svh
+${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_defines_pkg.sv
+${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_macros.svh
+${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_gen_hash.sv
+${CALIPTRA_ROOT}/src/sha512/coverage/sha512_ctrl_cov_if.sv
+${CALIPTRA_ROOT}/src/sha512/coverage/sha512_ctrl_cov_bind.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
+${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg_pkg.sv
+${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg.sv
+${CALIPTRA_ROOT}/src/keyvault/rtl/kv.sv
+${CALIPTRA_ROOT}/src/keyvault/rtl/kv_fsm.sv
+${CALIPTRA_ROOT}/src/keyvault/rtl/kv_read_client.sv
+${CALIPTRA_ROOT}/src/keyvault/rtl/kv_write_client.sv
+${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg_pkg.sv
+${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg.sv
+${CALIPTRA_ROOT}/src/pcrvault/rtl/pv.sv
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg_pkg.sv
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_params_pkg.sv
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_ctrl.sv
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512.sv
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_core.v
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_h_constants.v
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_k_constants.v
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_w_mem.v
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg.sv
\ No newline at end of file
diff --git a/src/sha512/config/sha512_ctrl.vf b/src/sha512/config/sha512_ctrl.vf
index 85f207651..71a30643d 100644
--- a/src/sha512/config/sha512_ctrl.vf
+++ b/src/sha512/config/sha512_ctrl.vf
@@ -14,6 +14,7 @@ ${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
 ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_defines_pkg.sv
 ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_macros.svh
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_defines_pkg.sv
@@ -30,9 +31,9 @@ ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg.sv
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg_pkg.sv
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_params_pkg.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_ctrl.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512.sv
-${CALIPTRA_ROOT}/src/sha512/rtl/sha512_param.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_core.v
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_h_constants.v
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_k_constants.v
diff --git a/src/sha512/config/sha512_ctrl_32bit_tb.vf b/src/sha512/config/sha512_ctrl_32bit_tb.vf
index 10b2319ca..621c83d2e 100644
--- a/src/sha512/config/sha512_ctrl_32bit_tb.vf
+++ b/src/sha512/config/sha512_ctrl_32bit_tb.vf
@@ -2,6 +2,7 @@
 +incdir+${CALIPTRA_ROOT}/src/libs/rtl
 +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl
 +incdir+${CALIPTRA_ROOT}/src/pcrvault/rtl
++incdir+${CALIPTRA_ROOT}/src/sha512/coverage
 +incdir+${CALIPTRA_ROOT}/src/sha512/tb
 +incdir+${CALIPTRA_ROOT}/src/sha512/rtl
 ${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh
@@ -15,11 +16,14 @@ ${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
 ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_defines_pkg.sv
 ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_macros.svh
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_defines_pkg.sv
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_macros.svh
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_gen_hash.sv
+${CALIPTRA_ROOT}/src/sha512/coverage/sha512_ctrl_cov_if.sv
+${CALIPTRA_ROOT}/src/sha512/coverage/sha512_ctrl_cov_bind.sv
 ${CALIPTRA_ROOT}/src/sha512/tb/sha512_ctrl_32bit_tb.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
 ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg_pkg.sv
@@ -32,9 +36,9 @@ ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg.sv
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg_pkg.sv
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_params_pkg.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_ctrl.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512.sv
-${CALIPTRA_ROOT}/src/sha512/rtl/sha512_param.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_core.v
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_h_constants.v
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_k_constants.v
diff --git a/src/sha512/coverage/sha512_ctrl_cov_bind.sv b/src/sha512/coverage/sha512_ctrl_cov_bind.sv
new file mode 100644
index 000000000..8917d105b
--- /dev/null
+++ b/src/sha512/coverage/sha512_ctrl_cov_bind.sv
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+module sha512_ctrl_cov_bind;
+    `ifdef FCOV
+    bind sha512_ctrl sha512_ctrl_cov_if i_sha512_ctrl_cov_if(.*);
+    `endif
+endmodule
diff --git a/src/sha512/coverage/sha512_ctrl_cov_if.sv b/src/sha512/coverage/sha512_ctrl_cov_if.sv
new file mode 100644
index 000000000..9484d5608
--- /dev/null
+++ b/src/sha512/coverage/sha512_ctrl_cov_if.sv
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+`ifndef VERILATOR
+
+interface sha512_ctrl_cov_if     
+    (
+    input logic           clk,
+    input logic           reset_n,
+    input logic           cptra_pwrgood
+
+);
+
+    logic init;
+    logic next;
+    logic [1 : 0] mode;
+    logic zeroize;
+    logic ready;
+    logic valid;
+    
+    logic pcr_sign_we;
+    logic gen_hash_start;
+    logic gen_hash_ip;
+    logic dest_data_avail;
+
+    logic [1 : 0] hash_cmd;
+    
+    assign init = sha512_ctrl.sha512_inst.init_reg;
+    assign next = sha512_ctrl.sha512_inst.next_reg;
+    assign mode = sha512_ctrl.sha512_inst.mode_reg;
+    assign zeroize = sha512_ctrl.sha512_inst.zeroize_reg;
+    assign ready = sha512_ctrl.sha512_inst.ready_reg;
+    assign valid = sha512_ctrl.sha512_inst.digest_valid_reg;
+
+    assign pcr_sign_we = sha512_ctrl.sha512_inst.pcr_sign_we;
+    assign gen_hash_start = sha512_ctrl.sha512_inst.gen_hash_start;
+    assign gen_hash_ip = sha512_ctrl.sha512_inst.gen_hash_ip;
+    assign dest_data_avail = sha512_ctrl.sha512_inst.dest_data_avail;
+
+    assign hash_cmd = {next, init};
+
+    covergroup sha512_ctrl_cov_grp @(posedge clk);
+        reset_cp: coverpoint reset_n;
+        cptra_pwrgood_cp: coverpoint cptra_pwrgood;
+
+        init_cp: coverpoint init;
+        next_cp: coverpoint next;
+        mode_cp: coverpoint mode;
+        zeroize_cp: coverpoint zeroize;
+        ready_cp: coverpoint ready;
+        valid_cp: coverpoint valid;
+
+        pcr_sign_we_cp: coverpoint pcr_sign_we;
+        gen_hash_start_cp: coverpoint gen_hash_start;
+        gen_hash_ip_cp: coverpoint gen_hash_ip;
+        dest_data_avail_cp: coverpoint dest_data_avail;
+
+        hash_cmd_cp: coverpoint hash_cmd  {bins cmd[]   = (0, 0 => 1, 2 => 0, 0);}
+
+        init_ready_cp: cross ready, init;
+        next_ready_cp: cross ready, next;
+        zeroize_ready_cp: cross ready, zeroize;
+        mode_ready_cp: cross ready, mode;
+        pcr_ready_cp: cross ready, gen_hash_start;
+        pcr_init_cp: cross gen_hash_start, init;
+        pcr_next_cp: cross gen_hash_start, next;
+        zeroize_pcr_cp: cross zeroize, gen_hash_start;
+        zeroize_init_cp: cross zeroize, init;
+        zeroize_next_cp: cross zeroize, next;
+
+    endgroup
+
+    sha512_ctrl_cov_grp sha512_ctrl_cov_grp1 = new();
+
+endinterface
+
+`endif
\ No newline at end of file
diff --git a/src/sha512/formal/model/PriniTestBench/sc_main.cpp b/src/sha512/formal/model/PriniTestBench/sc_main.cpp
new file mode 100644
index 000000000..7bf012fe0
--- /dev/null
+++ b/src/sha512/formal/model/PriniTestBench/sc_main.cpp
@@ -0,0 +1,23 @@
+#include "systemc.h"
+#include "../Interfaces/Interfaces.h"
+#include "../sha512.h"
+#include "tb.h"
+
+
+int sc_main(int argc, char **argv) {
+  Blocking<SHA_Args> in_channel("in_channel");
+  MasterSlave<sc_biguint<512>> out_channel("out_channel");
+
+  testbench tb("tb");
+  tb.in_testdata(in_channel);
+  tb.out_testdata(out_channel);
+  
+  SHA512 dut("dut");
+  dut.SHA_Input(in_channel);
+  dut.out(out_channel);
+
+
+
+  sc_start();
+  return 0;
+}
diff --git a/src/sha512/formal/model/PriniTestBench/tb.cpp b/src/sha512/formal/model/PriniTestBench/tb.cpp
new file mode 100644
index 000000000..a4202ddf2
--- /dev/null
+++ b/src/sha512/formal/model/PriniTestBench/tb.cpp
@@ -0,0 +1,33 @@
+using namespace std;
+#include <array>
+#include "systemc.h"
+#include "../common/Interfaces.h" 
+#include "sha512.h"
+#include "tb.h"
+
+int main() {
+    // Instantiate the DUT
+    // Instantiate the TB
+    SHA512 dut("dut");
+    testbench tb("tb");
+
+    // Channels & connections
+    Blocking<SHA_Args> SHA_in("SHA_in");
+    MasterSlave<sc_biguint<512>> hash("hash");
+
+    dut.SHA_Input(SHA_in);
+    tb.in_testdata(SHA_in);
+    dut.out(hash);
+    tb.out_testdata(hash);
+
+    // Start the simulation
+    sc_start();
+    return 0;
+};
+
+
+
+
+
+
+
diff --git a/src/sha512/formal/model/PriniTestBench/tb.h b/src/sha512/formal/model/PriniTestBench/tb.h
new file mode 100644
index 000000000..14218adcd
--- /dev/null
+++ b/src/sha512/formal/model/PriniTestBench/tb.h
@@ -0,0 +1,93 @@
+#ifndef TB_H
+#define TB_H
+
+
+#include "systemc.h"
+#include "../Interfaces/Interfaces.h"
+#include <fstream>
+#include <string>
+#include "../sha512.h"
+
+SC_MODULE(testbench) {
+public:
+  SC_CTOR(testbench) {
+   // read_test_vectors(file_path);
+    SC_THREAD(tests)
+  }
+
+  blocking_out <SHA_Args> in_testdata;
+  slave_in<sc_biguint<512>> out_testdata;
+
+private:
+  void tests() {
+
+    wait(0, SC_PS);
+
+    sc_biguint<512> test_result;
+    SHA_Args test_input;
+    sc_biguint<104000> MSG_raw; 
+    sc_biguint<104000> MSG_padded; 
+    sc_uint<32>  MSG_Length;
+    sc_biguint<512> expected_result;
+    int num = 1;
+    int zero_pad_len, MSG_chnks,i; 
+    bool success = false;
+    std::string line;
+    std::ifstream myfile;
+
+    myfile.open ("./testvectors/512_long_msg.txt");
+    
+    while (myfile)
+    {
+      myfile >> MSG_Length;
+      myfile >> std::hex >> MSG_raw;
+      myfile >> expected_result;
+     
+      zero_pad_len = (896 - MSG_Length - 1) % 1024;
+      MSG_chnks = static_cast<int> ((MSG_Length + 1 + 128 +  zero_pad_len) / 1024); 
+      MSG_padded = static_cast<sc_biguint<104000>> (static_cast<sc_biguint<104000>> (MSG_raw << (1 + 128 +  zero_pad_len)) + (static_cast<sc_biguint<104000>> (8) << ((125 + zero_pad_len))) + static_cast<sc_biguint<104000>> (MSG_Length));      
+
+      test_input.SHA_Mode = 512;
+      test_input.init = 1;
+      test_input.next = 0;
+
+      //To Do: use   assert ( parsed.hasError == false ) instead
+      for (i=0; i <MSG_chnks; i++) {   
+         
+        test_input.in = static_cast<sc_biguint<1024>>(MSG_padded >> (1024*(MSG_chnks-1)));
+        if (i>0)
+          test_input.next = 1;
+        in_testdata->write(test_input);  
+        MSG_padded = static_cast<sc_biguint<104000>> (MSG_padded << 1024);
+        test_input.init = 0;
+        success = false;
+        while(!success)
+        {
+          wait(0, SC_PS);
+          out_testdata->slave_read(test_result, success);
+        }
+        
+      };
+
+      if (test_result != expected_result){ 
+        std::cout << "Test " << num++ << " Failed!" << std::endl;
+        std::cout << std::hex << "Output:   " << test_result << std::endl;
+        std::cout << std::hex << "Expected: " << expected_result << std::endl;
+        //sc_stop();
+      } 
+      else {
+          std::cout << "Test " << num++ << " Passed!" << std::endl;
+      }
+
+      
+    }
+
+    myfile.close();
+    sc_stop();
+
+  }
+};
+
+
+#endif
+
diff --git a/src/sha512/formal/model/PriniTestBench/testvectors/224.txt b/src/sha512/formal/model/PriniTestBench/testvectors/224.txt
new file mode 100644
index 000000000..46c5c6092
--- /dev/null
+++ b/src/sha512/formal/model/PriniTestBench/testvectors/224.txt
@@ -0,0 +1,388 @@
+0
+0x00
+0x6ed0dd02806fa89e25de060c19d3ac86cabb87d6a0ddd05c333b84f4
+8
+0xcf
+0x4199239e87d47b6feda016802bf367fb6e8b5655eff6225cb2668f4a
+16
+0xca2d
+0x392b99b593b85e147f031986c2a9edfdb4ffd9f24c77c452d339c9fc
+24
+0x497604
+0xa9c345d58a959af20a42c84e28523ba47e3bf8fad8e8c3f32b7a72ae
+32
+0xc2eb0c88
+0xc5b97f1e46d91c3940be8cfef1e49baa77b475db943e49f00cddbe72
+40
+0xd28bc2aa3f
+0xe79de552120a87585e7313e24ecd74139a3be9ba2812936c4b33ca23
+48
+0xb4142ca79f6d
+0x2a0ed8eb0e18bc189f5c836dc6a5825baa6f7286fa5b9689b641bb3b
+56
+0x8daedf3c420c8c
+0x4edac91a8eba35a1431ef4d49705db12da382a786d15636774cbd708
+64
+0x6963446913771410
+0x21f6c373637e6a5e89d6e88811110c5c3fa12e497144912914c546e1
+72
+0x6f316ab2b40f096819
+0x5899542e9a78d1403929c4346993e213b83c32f91274bddbc63e4192
+80
+0x5819a77fa1a8f9c35d17
+0x2e944a5c534b80922f6c21e97277b4a01a4a0fa652d6d40b37fb0fc9
+88
+0x3c7e038401fa74c6c06e41
+0xa74af68819afe81bcdaceba64201c0d41f843e4b08e4002a375be761
+96
+0xe243b9f901855447fa2af302
+0x330c77ed20dc93cabf0df3442c620c9df5c7a02d7c79fc1d2ff7ff94
+104
+0xc5f942edc46407c6019cd926a0
+0xe180a0d83683cb7e79d812ab5d4288399c78895c6a918e99a2839155
+112
+0xe57d4c478ad6a64b8bf3352e75b6
+0x18b3e8f5a1fb603c67060c12a736e57c5ccc0b89fc62c90b02dd926b
+120
+0x32d049928a583b5b954785805d8b26
+0x18f87e8e6b54ec4336442f76eda0b32dcb64d463c0be69e348f86c34
+128
+0x3b2542cb3fa560dd0d796d59ee151fee
+0xdc4ab34db241b3fc2055c54f70a8fd304523d8c4202852f5f077644f
+136
+0xecbe367959a91b15eb08048b33752ef76d
+0xb76eaa7dde45ed50c07b5bafafbfdcc0959c1a64eca7adc391aba245
+144
+0x40bd7d47b636c2a749a247fdda75807c238b
+0x087ed68f1db90ffb2fb4ff7dc4b17fe08100b64383850378ef543339
+152
+0x331c8939ef685ae0efcd4030378a8b0ab720c7
+0x97874d56296a28f8df280448f76a9e806605da257a6083598f232e4d
+160
+0x26634d1eb3cc2793830c97f49674bda74743eb8f
+0x8294b112588dfb9c553ac88fbd8441722cec6a1d435311fe72e0110c
+168
+0x62ed23ab88c30fe1350f702f3b6d45253a0fc6aec1
+0x309db70638771e2eec309abfda219e5f13bac5fa9d5e84e727764bca
+176
+0x827dbbe36fb2663c95eaf81c7ce441dca66405050ad8
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diff --git a/src/sha512/formal/model/PriniTestBench/testvectors/256.txt b/src/sha512/formal/model/PriniTestBench/testvectors/256.txt
new file mode 100644
index 000000000..e134f2816
--- /dev/null
+++ b/src/sha512/formal/model/PriniTestBench/testvectors/256.txt
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diff --git a/src/sha512/formal/model/PriniTestBench/testvectors/384.txt b/src/sha512/formal/model/PriniTestBench/testvectors/384.txt
new file mode 100644
index 000000000..48258687f
--- /dev/null
+++ b/src/sha512/formal/model/PriniTestBench/testvectors/384.txt
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diff --git a/src/sha512/formal/model/PriniTestBench/testvectors/384_long_msg.txt b/src/sha512/formal/model/PriniTestBench/testvectors/384_long_msg.txt
new file mode 100644
index 000000000..35e341b93
--- /dev/null
+++ b/src/sha512/formal/model/PriniTestBench/testvectors/384_long_msg.txt
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diff --git a/src/sha512/formal/model/PriniTestBench/testvectors/512.txt b/src/sha512/formal/model/PriniTestBench/testvectors/512.txt
new file mode 100644
index 000000000..89ed268f9
--- /dev/null
+++ b/src/sha512/formal/model/PriniTestBench/testvectors/512.txt
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\ No newline at end of file
diff --git a/src/sha512/formal/model/PriniTestBench/testvectors/512_long_msg.txt b/src/sha512/formal/model/PriniTestBench/testvectors/512_long_msg.txt
new file mode 100644
index 000000000..2cf6bbb17
--- /dev/null
+++ b/src/sha512/formal/model/PriniTestBench/testvectors/512_long_msg.txt
@@ -0,0 +1,384 @@
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+0x26263445024bbdbd0518b331a7ab88e7bdc8d8344a3480d1c19ad0e7c7cb22447cf88e53d2536fd215e25c5158dbc52ef56585f7ab5b771387811a9f9afbdb7f
diff --git a/src/sha512/formal/model/SHA512.luref b/src/sha512/formal/model/SHA512.luref
new file mode 100644
index 000000000..262cdb555
--- /dev/null
+++ b/src/sha512/formal/model/SHA512.luref
@@ -0,0 +1,490 @@
+{
+    "version": 17,
+    "module": {
+        "name": "SHA512",
+        "reset_signal": {
+            "signal": "(sha512_core.reset_n)  && !(sha512_core.zeroize)",
+            "is_active_low": true
+        },
+        "clock_signal": {
+            "signal": "clk",
+            "is_falling_edge": false
+        },
+        "next_shift_amount": 0,
+        "rtl_module_name": "sha512_core",
+        "instance_name": "inst",
+        "default_assertion_duration": 1,
+        "default_disable_iff": "",
+        "reset": {
+            "documentation_comment": ""
+        },
+        "additional_includes": "fv_constraints.sv",
+        "additional_imports": "",
+        "sync_macros": [
+            {
+                "name": "SHA_Input_sync",
+                "datatype": "bool",
+                "refinement": "((sha512_core.init_cmd) || (sha512_core.next_cmd))",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            }
+        ],
+        "notify_macros": [
+            {
+                "name": "out_notify",
+                "datatype": "bool",
+                "refinement": "(sha512_core.digest_valid) && ((sha512_core.sha512_ctrl_reg==2'h0) && $past(sha512_core.sha512_ctrl_reg==2'h2) )",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            },
+            {
+                "name": "SHA_Input_notify",
+                "datatype": "bool",
+                "refinement": "sha512_core.ready",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            }
+        ],
+        "input_datapath_macros": [
+            {
+                "name": "SHA_Input_sig_in",
+                "datatype": "sc_big_unsigned_1024",
+                "refinement": "sha512_core.block_msg",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            },
+            {
+                "name": "SHA_Input_sig_init",
+                "datatype": "bool",
+                "refinement": "sha512_core.init_cmd",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            },
+            {
+                "name": "SHA_Input_sig_next",
+                "datatype": "bool",
+                "refinement": "sha512_core.next_cmd",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            },
+            {
+                "name": "SHA_Input_sig_SHA_Mode",
+                "datatype": "signed_32",
+                "refinement": "if(sha512_core.mode==0)\n\treturn 224;\nelse if(sha512_core.mode==1)\n\treturn 256;\nelse if(sha512_core.mode==2)\n\treturn 384;\nelse\n\treturn 512;",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            },
+            {
+                "name": "SHA_Input_sig_zeroize",
+                "datatype": "bool",
+                "refinement": "sha512_core.zeroize",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            }
+        ],
+        "output_datapath_macros": [
+            {
+                "name": "out_sig",
+                "datatype": "sc_big_unsigned_512",
+                "refinement": "sha512_core.digest",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            }
+        ],
+        "state_macros": [
+            {
+                "name": "DONE",
+                "datatype": "bool",
+                "refinement": "sha512_core.sha512_ctrl_reg==2'h2",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            },
+            {
+                "name": "IDLE",
+                "datatype": "bool",
+                "refinement": "sha512_core.sha512_ctrl_reg==2'h0",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            },
+            {
+                "name": "SHA_Rounds",
+                "datatype": "bool",
+                "refinement": "sha512_core.sha512_ctrl_reg==2'h1",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            }
+        ],
+        "register_macros": [
+            {
+                "name": "a",
+                "datatype": "sc_big_unsigned_64",
+                "refinement": "sha512_core.a_reg",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            },
+            {
+                "name": "b",
+                "datatype": "sc_big_unsigned_64",
+                "refinement": "sha512_core.b_reg",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            },
+            {
+                "name": "c",
+                "datatype": "sc_big_unsigned_64",
+                "refinement": "sha512_core.c_reg",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            },
+            {
+                "name": "d",
+                "datatype": "sc_big_unsigned_64",
+                "refinement": "sha512_core.d_reg",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            },
+            {
+                "name": "e",
+                "datatype": "sc_big_unsigned_64",
+                "refinement": "sha512_core.e_reg",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            },
+            {
+                "name": "f",
+                "datatype": "sc_big_unsigned_64",
+                "refinement": "sha512_core.f_reg",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            },
+            {
+                "name": "g",
+                "datatype": "sc_big_unsigned_64",
+                "refinement": "sha512_core.g_reg",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            },
+            {
+                "name": "h",
+                "datatype": "sc_big_unsigned_64",
+                "refinement": "sha512_core.h_reg",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            },
+            {
+                "name": "H_0",
+                "datatype": "sc_big_unsigned_64",
+                "refinement": "sha512_core.H0_reg",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            },
+            {
+                "name": "H_1",
+                "datatype": "sc_big_unsigned_64",
+                "refinement": "sha512_core.H1_reg",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            },
+            {
+                "name": "H_2",
+                "datatype": "sc_big_unsigned_64",
+                "refinement": "sha512_core.H2_reg",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            },
+            {
+                "name": "H_3",
+                "datatype": "sc_big_unsigned_64",
+                "refinement": "sha512_core.H3_reg",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            },
+            {
+                "name": "H_4",
+                "datatype": "sc_big_unsigned_64",
+                "refinement": "sha512_core.H4_reg",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            },
+            {
+                "name": "H_5",
+                "datatype": "sc_big_unsigned_64",
+                "refinement": "sha512_core.H5_reg",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            },
+            {
+                "name": "H_6",
+                "datatype": "sc_big_unsigned_64",
+                "refinement": "sha512_core.H6_reg",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            },
+            {
+                "name": "H_7",
+                "datatype": "sc_big_unsigned_64",
+                "refinement": "sha512_core.H7_reg",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            },
+            {
+                "name": "i",
+                "datatype": "signed_32",
+                "refinement": "sha512_core.round_ctr_reg",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            },
+            {
+                "name": "W_0",
+                "datatype": "sc_big_unsigned_64",
+                "refinement": "sha512_core.w_mem_inst.w_mem[00]",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            },
+            {
+                "name": "W_1",
+                "datatype": "sc_big_unsigned_64",
+                "refinement": "sha512_core.w_mem_inst.w_mem[01]",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            },
+            {
+                "name": "W_10",
+                "datatype": "sc_big_unsigned_64",
+                "refinement": "sha512_core.w_mem_inst.w_mem[10]",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            },
+            {
+                "name": "W_11",
+                "datatype": "sc_big_unsigned_64",
+                "refinement": "sha512_core.w_mem_inst.w_mem[11]",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            },
+            {
+                "name": "W_12",
+                "datatype": "sc_big_unsigned_64",
+                "refinement": "sha512_core.w_mem_inst.w_mem[12]",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            },
+            {
+                "name": "W_13",
+                "datatype": "sc_big_unsigned_64",
+                "refinement": "sha512_core.w_mem_inst.w_mem[13]",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            },
+            {
+                "name": "W_14",
+                "datatype": "sc_big_unsigned_64",
+                "refinement": "sha512_core.w_mem_inst.w_mem[14]",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            },
+            {
+                "name": "W_15",
+                "datatype": "sc_big_unsigned_64",
+                "refinement": "sha512_core.w_mem_inst.w_mem[15]",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            },
+            {
+                "name": "W_2",
+                "datatype": "sc_big_unsigned_64",
+                "refinement": "sha512_core.w_mem_inst.w_mem[02]",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            },
+            {
+                "name": "W_3",
+                "datatype": "sc_big_unsigned_64",
+                "refinement": "sha512_core.w_mem_inst.w_mem[03]",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            },
+            {
+                "name": "W_4",
+                "datatype": "sc_big_unsigned_64",
+                "refinement": "sha512_core.w_mem_inst.w_mem[04]",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            },
+            {
+                "name": "W_5",
+                "datatype": "sc_big_unsigned_64",
+                "refinement": "sha512_core.w_mem_inst.w_mem[05]",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            },
+            {
+                "name": "W_6",
+                "datatype": "sc_big_unsigned_64",
+                "refinement": "sha512_core.w_mem_inst.w_mem[06]",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            },
+            {
+                "name": "W_7",
+                "datatype": "sc_big_unsigned_64",
+                "refinement": "sha512_core.w_mem_inst.w_mem[07]",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            },
+            {
+                "name": "W_8",
+                "datatype": "sc_big_unsigned_64",
+                "refinement": "sha512_core.w_mem_inst.w_mem[08]",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            },
+            {
+                "name": "W_9",
+                "datatype": "sc_big_unsigned_64",
+                "refinement": "sha512_core.w_mem_inst.w_mem[09]",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": false
+            },
+            {
+                "name": "MSG_digest",
+                "datatype": "sc_big_unsigned_512",
+                "refinement": "",
+                "create_commitments": true,
+                "timing": 0,
+                "unused": true
+            }
+        ],
+        "assertions": [
+            {
+                "name": "DONE_to_IDLE",
+                "disable_iff": "",
+                "duration": -1,
+                "documentation_comment": "",
+                "unused": false
+            },
+            {
+                "name": "IDLE_to_SHA_Rounds",
+                "disable_iff": "",
+                "duration": -1,
+                "documentation_comment": "",
+                "unused": false
+            },
+            {
+                "name": "IDLE_to_SHA_Rounds_1",
+                "disable_iff": "",
+                "duration": -1,
+                "documentation_comment": "",
+                "unused": false
+            },
+            {
+                "name": "IDLE_to_SHA_Rounds_2",
+                "disable_iff": "",
+                "duration": -1,
+                "documentation_comment": "",
+                "unused": false
+            },
+            {
+                "name": "IDLE_to_SHA_Rounds_3",
+                "disable_iff": "",
+                "duration": -1,
+                "documentation_comment": "",
+                "unused": false
+            },
+            {
+                "name": "IDLE_to_SHA_Rounds_4",
+                "disable_iff": "",
+                "duration": -1,
+                "documentation_comment": "",
+                "unused": false
+            },
+            {
+                "name": "SHA_Rounds_to_DONE",
+                "disable_iff": "",
+                "duration": -1,
+                "documentation_comment": "",
+                "unused": false
+            },
+            {
+                "name": "SHA_Rounds_to_SHA_Rounds",
+                "disable_iff": "",
+                "duration": -1,
+                "documentation_comment": "",
+                "unused": false
+            },
+            {
+                "name": "SHA_Rounds_to_SHA_Rounds_1",
+                "disable_iff": "",
+                "duration": -1,
+                "documentation_comment": "",
+                "unused": false
+            },
+            {
+                "name": "IDLE_to_IDLE",
+                "disable_iff": "",
+                "duration": -1,
+                "documentation_comment": "",
+                "unused": true
+            },
+            {
+                "name": "IDLE_to_SHA_Rounds_5",
+                "disable_iff": "",
+                "duration": -1,
+                "documentation_comment": "",
+                "unused": true
+            }
+        ],
+        "waits": [
+            {
+                "name": "IDLE_wait",
+                "documentation_comment": "",
+                "unused": false
+            }
+        ]
+    }
+}
\ No newline at end of file
diff --git a/src/sha512/formal/model/refinement.luctrl b/src/sha512/formal/model/refinement.luctrl
new file mode 100644
index 000000000..7b7979b22
--- /dev/null
+++ b/src/sha512/formal/model/refinement.luctrl
@@ -0,0 +1,9 @@
+{
+    "version": 13,
+    "modules": [
+        {
+            "name": "SHA512",
+            "path": "SHA512.luref"
+        }
+    ]
+}
\ No newline at end of file
diff --git a/src/sha512/formal/model/sha512.h b/src/sha512/formal/model/sha512.h
new file mode 100644
index 000000000..357080d88
--- /dev/null
+++ b/src/sha512/formal/model/sha512.h
@@ -0,0 +1,393 @@
+#ifndef SHA
+#define SHA
+
+#include <array>
+#include "systemc.h"
+#include "string.h"
+#include "Interfaces.h" 
+using    namespace std;
+#define  NUM_ROUNDS  80
+
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+
+ sc_biguint<64> slicer(sc_biguint<1024> block, int index) {
+    switch (index){
+        case 0:
+            return static_cast<sc_biguint<64>> (block >> sc_biguint<1024>(64 * 0));
+            break;
+        case 1:
+            return static_cast<sc_biguint<64>> (block >> sc_biguint<1024>(64 * 1));
+            break;
+        case 2:
+            return static_cast<sc_biguint<64>> (block >> sc_biguint<1024>(64 * 2));
+            break;
+        case 3:
+            return static_cast<sc_biguint<64>> (block >> sc_biguint<1024>(64 * 3));
+            break;
+        case 4:
+            return static_cast<sc_biguint<64>> (block >> sc_biguint<1024>(64 * 4));
+            break;
+        case 5:
+            return static_cast<sc_biguint<64>> (block >> sc_biguint<1024>(64 * 5));
+            break;
+        case 6:
+            return static_cast<sc_biguint<64>> (block >> sc_biguint<1024>(64 * 6));
+            break;
+        case 7:
+            return static_cast<sc_biguint<64>> (block >> sc_biguint<1024>(64 * 7));
+            break;
+        case 8:
+            return static_cast<sc_biguint<64>> (block >> sc_biguint<1024>(64 * 8));
+            break;
+        case 9:
+            return static_cast<sc_biguint<64>> (block >> sc_biguint<1024>(64 * 9));
+            break;
+        case 10:
+            return static_cast<sc_biguint<64>> (block >> sc_biguint<1024>(64 * 10));
+            break;
+        case 11:
+            return static_cast<sc_biguint<64>> (block >> sc_biguint<1024>(64 * 11));
+            break;
+        case 12:
+            return static_cast<sc_biguint<64>> (block >> sc_biguint<1024>(64 * 12));
+            break;
+        case 13:
+            return static_cast<sc_biguint<64>> (block >> sc_biguint<1024>(64 * 13));
+            break;
+        case 14:
+            return static_cast<sc_biguint<64>> (block >> sc_biguint<1024>(64 * 14));
+            break;
+        case 15:
+            return static_cast<sc_biguint<64>> (block >> sc_biguint<1024>(64 * 15));
+            break;
+        default:
+            return static_cast<sc_biguint<64>> (block >> sc_biguint<1024>(64 * 15));
+            break;
+    }  
+}
+
+sc_biguint<64> Ch(sc_biguint<64> a, sc_biguint<64> b, sc_biguint<64> c)  {
+    return static_cast<sc_biguint<64>>((a & b) ^ (~a & c));
+}
+
+sc_biguint<64> Maj(sc_biguint<64> x, sc_biguint<64> y, sc_biguint<64> z)  {
+    return static_cast<sc_biguint<64>>((x & y) ^ (x & z) ^ (y & z));
+}
+
+sc_biguint<64> shr6(sc_biguint<64> n)  {  
+    return static_cast<sc_biguint<64>>(n >> sc_biguint<64>(6));
+}
+
+sc_biguint<64> shr7(sc_biguint<64> n)  {  
+    return static_cast<sc_biguint<64>>(n >> sc_biguint<64>(7));
+}
+
+sc_biguint<64> rotr1(sc_biguint<64> n)  {
+    return static_cast<sc_biguint<64>>((n >> (sc_biguint<64>(1)))  | (n << (sc_biguint<64>(63))));
+}
+
+sc_biguint<64> rotr8(sc_biguint<64> n)  {
+    return static_cast<sc_biguint<64>>((n >> (sc_biguint<64>(8)))  | (n << (sc_biguint<64>(56))));
+}
+
+sc_biguint<64> rotr14(sc_biguint<64> n)  {
+    return static_cast<sc_biguint<64>>((n >> (sc_biguint<64>(14))) | (n << (sc_biguint<64>(50))));
+}
+
+sc_biguint<64> rotr18(sc_biguint<64> n)  {
+    return static_cast<sc_biguint<64>>((n >> (sc_biguint<64>(18))) | (n << (sc_biguint<64>(46))));
+}
+
+sc_biguint<64> rotr19(sc_biguint<64> n)  {
+    return static_cast<sc_biguint<64>>((n >> (sc_biguint<64>(19))) | (n << (sc_biguint<64>(45))));
+}
+
+sc_biguint<64> rotr28(sc_biguint<64> n)  {
+    return static_cast<sc_biguint<64>>((n >> (sc_biguint<64>(28))) | (n << (sc_biguint<64>(36))));
+}
+
+sc_biguint<64> rotr34(sc_biguint<64> n)  {
+    return static_cast<sc_biguint<64>>((n >> (sc_biguint<64>(34))) | (n << (sc_biguint<64>(30))));
+}
+
+sc_biguint<64> rotr39(sc_biguint<64> n)  {
+    return static_cast<sc_biguint<64>>((n >> (sc_biguint<64>(39))) | (n << (sc_biguint<64>(25))));
+}
+
+sc_biguint<64> rotr41(sc_biguint<64> n)  {
+    return static_cast<sc_biguint<64>>((n >> (sc_biguint<64>(41))) | (n << (sc_biguint<64>(23))));
+}
+
+sc_biguint<64> rotr61(sc_biguint<64> n)  {
+    return static_cast<sc_biguint<64>>((n >> (sc_biguint<64>(61))) | (n << (sc_biguint<64>(3))));
+}
+
+sc_biguint<64> sigma0(sc_biguint<64> x){
+    return static_cast<sc_biguint<64>> (rotr28(x) ^ rotr34(x) ^ rotr39(x));
+}
+
+sc_biguint<64> sigma1(sc_biguint<64> x)  {
+    return static_cast<sc_biguint<64>> (rotr14(x) ^ rotr18(x) ^ rotr41(x));
+}
+
+sc_biguint<64> delta0(sc_biguint<64> x)  { 
+    return static_cast<sc_biguint<64>> (rotr1(x) ^ rotr8(x) ^ shr7(x));
+}
+
+sc_biguint<64> delta1(sc_biguint<64> x)  { 
+    return static_cast<sc_biguint<64>> (rotr19(x) ^ rotr61(x) ^ shr6(x));
+}
+
+sc_biguint<64> T1(sc_biguint<64> e, sc_biguint<64> f, sc_biguint<64> g, sc_biguint<64> h, sc_biguint<64> k, sc_biguint<64> w)  {  
+    return static_cast<sc_biguint<64>>(h + sigma1(e) + Ch(e, f, g) + k + w);
+}
+
+sc_biguint<64> T2(sc_biguint<64> a, sc_biguint<64> b, sc_biguint<64> c)  { 
+    return static_cast<sc_biguint<64>>(sigma0(a) + Maj(a, b, c));
+}
+sc_biguint<64> compute_e(sc_biguint<64> d,sc_biguint<64> e, sc_biguint<64> f, sc_biguint<64> g, sc_biguint<64> h, sc_biguint<64> k, sc_biguint<64> w)  {  
+    return static_cast<sc_biguint<64>>(d+ h + sigma1(e) + Ch(e, f, g) + k + w);
+}
+sc_biguint<64> compute_a(sc_biguint<64> e, sc_biguint<64> f, sc_biguint<64> g, sc_biguint<64> h, sc_biguint<64> k, sc_biguint<64> w,sc_biguint<64> a, sc_biguint<64> b, sc_biguint<64> c)  {
+    return static_cast<sc_biguint<64>>((static_cast<sc_biguint<64>>(h + sigma1(e) + Ch(e, f, g) + k + w))+(static_cast<sc_biguint<64>>(sigma0(a) + Maj(a, b, c))));
+}
+
+sc_biguint<64> compute_w(sc_biguint<64> w14, sc_biguint<64> w9, sc_biguint<64> w1, sc_biguint<64> w0) {
+    return static_cast<sc_biguint<64>>(delta1(w14) + w9 + delta0(w1) + w0);
+}
+
+sc_biguint<512> compute_dig (sc_biguint<512> dig,sc_biguint<64> h7, sc_biguint<64> h6, sc_biguint<64> h5, sc_biguint<64> h4,sc_biguint<64> h3,sc_biguint<64> h2, sc_biguint<64> h1, sc_biguint<64> h0){
+            dig += static_cast<sc_biguint<512>> (h6 << sc_biguint<64>(448));
+            dig = static_cast<sc_biguint<512>> (dig >> sc_biguint<512>(64));
+            dig += static_cast<sc_biguint<512>> (h6 << sc_biguint<64>(448));
+            dig = static_cast<sc_biguint<512>> (dig >> sc_biguint<512>(64));
+            dig += static_cast<sc_biguint<512>> (h5 << sc_biguint<64>(448));
+            dig = static_cast<sc_biguint<512>> (dig >> sc_biguint<512>(64));
+            dig += static_cast<sc_biguint<512>> (h4 << sc_biguint<64>(448));
+            dig = static_cast<sc_biguint<512>> (dig >> sc_biguint<512>(64));
+            dig += static_cast<sc_biguint<512>> (h3 << sc_biguint<64>(448));
+            dig = static_cast<sc_biguint<512>> (dig >> sc_biguint<512>(64));
+            dig += static_cast<sc_biguint<512>> (h2 << sc_biguint<64>(448));
+            dig = static_cast<sc_biguint<512>> (dig >> sc_biguint<512>(64));
+            dig += static_cast<sc_biguint<512>> (h1 << sc_biguint<64>(448));
+            dig = static_cast<sc_biguint<512>> (dig >> sc_biguint<512>(64));
+            dig += static_cast<sc_biguint<512>> (h0 << sc_biguint<64>(448));
+            
+            return(dig);
+        
+}
+struct SHA_Args{
+    sc_biguint<1024> in;
+    int SHA_Mode;
+    bool init;
+    bool next;
+    bool zeroize; 
+};
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+   const array   <sc_biguint<64>, 80> K =
+     {sc_biguint<64>(0x428a2f98d728ae22), sc_biguint<64>(0x7137449123ef65cd), sc_biguint<64>(0xb5c0fbcfec4d3b2f),\
+      sc_biguint<64>(0xe9b5dba58189dbbc), sc_biguint<64>(0x3956c25bf348b538), sc_biguint<64>(0x59f111f1b605d019),\
+      sc_biguint<64>(0x923f82a4af194f9b), sc_biguint<64>(0xab1c5ed5da6d8118), sc_biguint<64>(0xd807aa98a3030242),\
+      sc_biguint<64>(0x12835b0145706fbe), sc_biguint<64>(0x243185be4ee4b28c), sc_biguint<64>(0x550c7dc3d5ffb4e2),\
+      sc_biguint<64>(0x72be5d74f27b896f), sc_biguint<64>(0x80deb1fe3b1696b1), sc_biguint<64>(0x9bdc06a725c71235),\
+      sc_biguint<64>(0xc19bf174cf692694), sc_biguint<64>(0xe49b69c19ef14ad2), sc_biguint<64>(0xefbe4786384f25e3),\
+      sc_biguint<64>(0x0fc19dc68b8cd5b5), sc_biguint<64>(0x240ca1cc77ac9c65), sc_biguint<64>(0x2de92c6f592b0275),\
+      sc_biguint<64>(0x4a7484aa6ea6e483), sc_biguint<64>(0x5cb0a9dcbd41fbd4), sc_biguint<64>(0x76f988da831153b5),\
+      sc_biguint<64>(0x983e5152ee66dfab), sc_biguint<64>(0xa831c66d2db43210), sc_biguint<64>(0xb00327c898fb213f),\
+      sc_biguint<64>(0xbf597fc7beef0ee4), sc_biguint<64>(0xc6e00bf33da88fc2), sc_biguint<64>(0xd5a79147930aa725),\
+      sc_biguint<64>(0x06ca6351e003826f), sc_biguint<64>(0x142929670a0e6e70), sc_biguint<64>(0x27b70a8546d22ffc),\
+      sc_biguint<64>(0x2e1b21385c26c926), sc_biguint<64>(0x4d2c6dfc5ac42aed), sc_biguint<64>(0x53380d139d95b3df),\
+      sc_biguint<64>(0x650a73548baf63de), sc_biguint<64>(0x766a0abb3c77b2a8), sc_biguint<64>(0x81c2c92e47edaee6),\
+      sc_biguint<64>(0x92722c851482353b), sc_biguint<64>(0xa2bfe8a14cf10364), sc_biguint<64>(0xa81a664bbc423001),\
+      sc_biguint<64>(0xc24b8b70d0f89791), sc_biguint<64>(0xc76c51a30654be30), sc_biguint<64>(0xd192e819d6ef5218),\
+      sc_biguint<64>(0xd69906245565a910), sc_biguint<64>(0xf40e35855771202a), sc_biguint<64>(0x106aa07032bbd1b8),\
+      sc_biguint<64>(0x19a4c116b8d2d0c8), sc_biguint<64>(0x1e376c085141ab53), sc_biguint<64>(0x2748774cdf8eeb99),\
+      sc_biguint<64>(0x34b0bcb5e19b48a8), sc_biguint<64>(0x391c0cb3c5c95a63), sc_biguint<64>(0x4ed8aa4ae3418acb),\
+      sc_biguint<64>(0x5b9cca4f7763e373), sc_biguint<64>(0x682e6ff3d6b2b8a3), sc_biguint<64>(0x748f82ee5defb2fc),\
+      sc_biguint<64>(0x78a5636f43172f60), sc_biguint<64>(0x84c87814a1f0ab72), sc_biguint<64>(0x8cc702081a6439ec),\
+      sc_biguint<64>(0x90befffa23631e28), sc_biguint<64>(0xa4506cebde82bde9), sc_biguint<64>(0xbef9a3f7b2c67915),\
+      sc_biguint<64>(0xc67178f2e372532b), sc_biguint<64>(0xca273eceea26619c), sc_biguint<64>(0xd186b8c721c0c207),\
+      sc_biguint<64>(0xeada7dd6cde0eb1e), sc_biguint<64>(0xf57d4f7fee6ed178), sc_biguint<64>(0x06f067aa72176fba),\
+      sc_biguint<64>(0x0a637dc5a2c898a6), sc_biguint<64>(0x113f9804bef90dae), sc_biguint<64>(0x1b710b35131c471b),\
+      sc_biguint<64>(0x28db77f523047d84), sc_biguint<64>(0x32caab7b40c72493), sc_biguint<64>(0x3c9ebe0a15c9bebc),\
+      sc_biguint<64>(0x431d67c49c100d4c), sc_biguint<64>(0x4cc5d4becb3e42b6), sc_biguint<64>(0x597f299cfc657e2a),\
+      sc_biguint<64>(0x5fcb6fab3ad6faec), sc_biguint<64>(0x6c44198c4a475817)};;
+
+SC_MODULE(SHA512) {
+   
+    blocking_in <SHA_Args> SHA_Input;
+    master_out <sc_biguint<512>> out; 
+
+    array   <sc_biguint<64>, 16> W;
+    array   <sc_biguint<64>, 8>  H;
+ 
+    sc_biguint<64> t1 = sc_biguint<64> (0), t2 = sc_biguint<64> (0), 
+                    a = sc_biguint<64> (0),  b = sc_biguint<64> (0), 
+                    c = sc_biguint<64> (0),  d = sc_biguint<64> (0),
+                    e = sc_biguint<64> (0),  f = sc_biguint<64> (0), 
+                    g = sc_biguint<64> (0),  h = sc_biguint<64> (0), 
+                    w = sc_biguint<64> (0),  k = sc_biguint<64> (0);
+    sc_biguint<64> tmp_w;  
+
+    sc_biguint<1024> block_in; 
+    sc_biguint<1024> block_copy; 
+    sc_biguint<512> MSG_digest;
+
+    SHA_Args SHA_in;
+    int SHA_Mode_in;
+    bool init, next, success, zeroize;
+
+    int i, j, m=0;
+
+    void fsm();
+
+    SC_CTOR(SHA512){
+        SC_THREAD(fsm);
+    }  
+};
+
+void SHA512::fsm(){
+
+while(true){
+    
+        SHA_Input->read(SHA_in, "IDLE");
+
+        block_in = SHA_in.in;
+        SHA_Mode_in = SHA_in.SHA_Mode;
+        init = SHA_in.init;
+        next = SHA_in.next;
+        zeroize = SHA_in.zeroize; 
+    
+        if (init){
+            switch (SHA_Mode_in){
+                case 224:
+                    H ={sc_biguint<64>(0x8c3d37c819544da2), sc_biguint<64>(0x73e1996689dcd4d6),\
+                        sc_biguint<64>(0x1dfab7ae32ff9c82), sc_biguint<64>(0x679dd514582f9fcf),\
+                        sc_biguint<64>(0x0f6d2b697bd44da8), sc_biguint<64>(0x77e36f7304c48942),\
+                        sc_biguint<64>(0x3f9d85a86a1d36c8), sc_biguint<64>(0x1112e6ad91d692a1)};
+                    break;
+                case 256:
+                    H ={sc_biguint<64>(0x22312194fc2bf72c), sc_biguint<64>(0x9f555fa3c84c64c2),\
+                        sc_biguint<64>(0x2393b86b6f53b151), sc_biguint<64>(0x963877195940eabd),\
+                        sc_biguint<64>(0x96283ee2a88effe3), sc_biguint<64>(0xbe5e1e2553863992),\
+                        sc_biguint<64>(0x2b0199fc2c85b8aa), sc_biguint<64>(0x0eb72ddc81c52ca2)};
+                    break;
+                /*case 384:
+                    H ={sc_biguint<64>(0xcbbb9d5dc1059ed8), sc_biguint<64>(0x629a292a367cd507),\
+                        sc_biguint<64>(0x9159015a3070dd17), sc_biguint<64>(0x152fecd8f70e5939),\
+                        sc_biguint<64>(0x67332667ffc00b31), sc_biguint<64>(0x8eb44a8768581511),\
+                        sc_biguint<64>(0xdb0c2e0d64f98fa7), sc_biguint<64>(0x47b5481dbefa4fa4)};
+                    break;*/
+                case 512:
+                    H ={sc_biguint<64>(0x6a09e667f3bcc908), sc_biguint<64>(0xbb67ae8584caa73b),\
+                        sc_biguint<64>(0x3c6ef372fe94f82b), sc_biguint<64>(0xa54ff53a5f1d36f1),\
+                        sc_biguint<64>(0x510e527fade682d1), sc_biguint<64>(0x9b05688c2b3e6c1f),\
+                        sc_biguint<64>(0x1f83d9abfb41bd6b), sc_biguint<64>(0x5be0cd19137e2179)};
+
+                    break;
+                default:
+                    H ={sc_biguint<64>(0xcbbb9d5dc1059ed8), sc_biguint<64>(0x629a292a367cd507),\
+                        sc_biguint<64>(0x9159015a3070dd17), sc_biguint<64>(0x152fecd8f70e5939),\
+                        sc_biguint<64>(0x67332667ffc00b31), sc_biguint<64>(0x8eb44a8768581511),\
+                        sc_biguint<64>(0xdb0c2e0d64f98fa7), sc_biguint<64>(0x47b5481dbefa4fa4)};
+                    break;
+            }
+
+            t1 = sc_biguint<64> (0); t2 = sc_biguint<64> (0); 
+            a  = sc_biguint<64> (0); b  = sc_biguint<64> (0); 
+            c  = sc_biguint<64> (0); d  = sc_biguint<64> (0);
+            e  = sc_biguint<64> (0); f  = sc_biguint<64> (0); 
+            g  = sc_biguint<64> (0); h  = sc_biguint<64> (0); 
+            w  = sc_biguint<64> (0); k  = sc_biguint<64> (0);
+            W  = {sc_biguint<64>(0)};
+        }
+
+        //next(block_in);
+        //W_schedule(block_in);
+        block_copy = block_in;  
+
+        for (j=0; j<16; ++j) {    
+            W[15-j] = slicer(block_copy, j);
+        };
+
+        //copy_digest();           
+        a = H[0]; b = H[1];c = H[2]; d = H[3]; 
+        e = H[4]; f = H[5];g = H[6]; h = H[7];
+        
+        for (i=0; i<NUM_ROUNDS; ++i) { 
+            insert_state("SHA_Rounds");
+            //sha512_round(i);
+            k = K[i];
+            //w = next_w(i);
+        
+            if (i < 16){
+                w = W[i];   
+                  
+            }   
+            else {   
+                //tmp_w = delta1(W[14]) + W[9] + delta0(W[1]) + W[0];
+                tmp_w = compute_w(W[14],W[9],W[1],W[0]);
+                for (j=0; j<15; ++j) { 
+                    W[j] = W[(j+1)];
+                }
+                W[15] = tmp_w;
+                w = tmp_w;                 
+            }
+
+            t1 = T1(e, f, g, h, K[i],w);  
+            t2 = T2(a, b, c);
+            h = g;
+            g = f;
+            f = e;
+            e = (d + t1);
+            //e = compute_e(d,e, f, g, h, K[i],W[15]);
+            d = c; 
+            c = b;
+            b = a;
+            //a = compute_a(e,f,g,h,K[i],W[15],a,b,c);
+            a = (t1 + t2);        
+        } 
+        insert_state("DONE"); 
+        //update_digest(); 
+        H[0] = (H[0] + a) ;
+        H[1] = (H[1] + b) ;
+        H[2] = (H[2] + c) ;
+        H[3] = (H[3] + d) ;
+        H[4] = (H[4] + e) ;
+        H[5] = (H[5] + f) ;
+        H[6] = (H[6] + g) ;
+        H[7] = (H[7] + h) ;                 
+        
+         MSG_digest = static_cast<sc_biguint<512>> (H[7] << (sc_biguint<64>(448)));
+        for (j=6; j > -1; --j) {         
+            MSG_digest = static_cast<sc_biguint<512>> (MSG_digest >> sc_biguint<512>(64));
+            MSG_digest += static_cast<sc_biguint<512>> (H[j] << sc_biguint<64>(448));
+        }
+        //MSG_digest = compute_dig(static_cast<sc_biguint<512>>(0),H[7],H[6],H[5],H[4],H[3],H[2],H[1],H[0]);
+        //MSG_digest = concati(MSG_digest, H, j); 
+        /*   BYME: to comply with rtl
+        switch (SHA_Mode_in){
+            case 224:
+                MSG_digest = static_cast<sc_biguint<512>> (MSG_digest >> sc_biguint<512>(288)); 
+                break;
+            case 256:
+                MSG_digest = static_cast<sc_biguint<512>> (MSG_digest >> sc_biguint<512>(256)); 
+                break;
+            case 384:
+                MSG_digest = static_cast<sc_biguint<512>> (MSG_digest >> sc_biguint<512>(128)); 
+                break;
+            default:
+                MSG_digest = static_cast<sc_biguint<512>> (MSG_digest); 
+                break;
+        }*/
+        
+        out->master_write(static_cast<sc_biguint<512>> (MSG_digest)); 
+        
+    //}; 
+    
+    //out->write(static_cast<sc_biguint<512>> (MSG_digest >> static_cast<sc_biguint<512>>(512-SHA_Mode_in))); 
+    }
+};
+#endif
diff --git a/src/sha512/formal/properties/fv_constraints.sv b/src/sha512/formal/properties/fv_constraints.sv
new file mode 100644
index 000000000..2ffc12032
--- /dev/null
+++ b/src/sha512/formal/properties/fv_constraints.sv
@@ -0,0 +1,49 @@
+// -------------------------------------------------
+// Contact: contact@lubis-eda.com
+// Author: Tobias Ludwig, Michael Schwarz
+// -------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+module fv_constraints_m(init_cmd, next_cmd, reset_n, clk);
+    input bit init_cmd, next_cmd, reset_n, clk;
+    reg init_reg;
+default clocking default_clk @(posedge clk); endclocking
+
+    remove_init_next_together_a: assume property (remove_init_next_together);
+    property remove_init_next_together;
+        !(init_cmd && next_cmd);
+    endproperty
+
+    init_next_order_a: assume property (init_next_order);
+    property init_next_order;
+        !init_reg |-> !next_cmd;
+    endproperty
+
+    always @ (posedge clk or negedge reset_n)
+        begin : init_reg_order
+            if (!reset_n)
+                init_reg <= 1'b0;
+            else if (init_cmd)
+                init_reg <= 1'b1;
+        end
+
+endmodule
+
+bind sha512_core fv_constraints_m fv_constraints(
+  .init_cmd(init_cmd),
+  .next_cmd(next_cmd),
+  .reset_n(reset_n),
+  .clk(clk)
+);
\ No newline at end of file
diff --git a/src/sha512/formal/properties/fv_sha512.sv b/src/sha512/formal/properties/fv_sha512.sv
new file mode 100644
index 000000000..f36f06ff0
--- /dev/null
+++ b/src/sha512/formal/properties/fv_sha512.sv
@@ -0,0 +1,644 @@
+// -------------------------------------------------
+// Contact: contact@lubis-eda.com
+// Author: Tobias Ludwig, Michael Schwarz
+// -------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+
+import fv_sha512_pkg::*;
+
+
+module fv_sha_512_m(
+  input bit rst,
+  input bit clk,
+  input bit unsigned [1023:0] block_in,
+  input bit unsigned [31:0] block_sha_mode,
+  input bit block_init,
+  input bit block_next,
+  input bit block_zeroize,
+  input bit unsigned [511:0] digest_out,
+  input bit block_in_valid,
+  input bit block_in_ready,
+  input bit digest_valid,
+  input bit unsigned [63:0] H_0,
+  input bit unsigned [63:0] H_1,
+  input bit unsigned [63:0] H_2,
+  input bit unsigned [63:0] H_3,
+  input bit unsigned [63:0] H_4,
+  input bit unsigned [63:0] H_5,
+  input bit unsigned [63:0] H_6,
+  input bit unsigned [63:0] H_7,
+  input bit unsigned [63:0] W_0,
+  input bit unsigned [63:0] W_1,
+  input bit unsigned [63:0] W_2,
+  input bit unsigned [63:0] W_3,
+  input bit unsigned [63:0] W_4,
+  input bit unsigned [63:0] W_5,
+  input bit unsigned [63:0] W_6,
+  input bit unsigned [63:0] W_7,
+  input bit unsigned [63:0] W_8,
+  input bit unsigned [63:0] W_9,
+  input bit unsigned [63:0] W_10,
+  input bit unsigned [63:0] W_11,
+  input bit unsigned [63:0] W_12,
+  input bit unsigned [63:0] W_13,
+  input bit unsigned [63:0] W_14,
+  input bit unsigned [63:0] W_15,
+  input bit unsigned [63:0] a,
+  input bit unsigned [63:0] b,
+  input bit unsigned [63:0] c,
+  input bit unsigned [63:0] d,
+  input bit unsigned [63:0] e,
+  input bit unsigned [63:0] f,
+  input bit unsigned [63:0] g,
+  input bit unsigned [63:0] h,
+  input bit unsigned [6:0] i,
+  input bit IDLE,
+  input bit SHA_Rounds,
+  input bit DONE
+);
+
+
+default clocking default_clk @(posedge clk); endclocking
+
+logic [15:0][63:0] W;
+logic [3:0] j;
+
+assign j = i[3:0];
+assign W = {W_15,W_14,W_13,W_12,W_11,W_10,W_9,W_8,W_7,W_6,W_5,W_4,W_3,W_2,W_1,W_0};
+
+
+sequence reset_sequence;
+  !rst ##1 rst;
+endsequence
+
+
+reset_a: assert property (reset_p);
+property reset_p;
+  reset_sequence |->
+  IDLE &&
+  H_0 == 64'd0 &&
+  H_1 == 64'd0 &&
+  H_2 == 64'd0 &&
+  H_3 == 64'd0 &&
+  H_4 == 64'd0 &&
+  H_5 == 64'd0 &&
+  H_6 == 64'd0 &&
+  H_7 == 64'd0 &&
+  W_0 == 64'd0 &&
+  W_10 == 64'd0 &&
+  W_11 == 64'd0 &&
+  W_12 == 64'd0 &&
+  W_13 == 64'd0 &&
+  W_14 == 64'd0 &&
+  W_15 == 64'd0 &&
+  W_1 == 64'd0 &&
+  W_2 == 64'd0 &&
+  W_3 == 64'd0 &&
+  W_4 == 64'd0 &&
+  W_5 == 64'd0 &&
+  W_6 == 64'd0 &&
+  W_7 == 64'd0 &&
+  W_8 == 64'd0 &&
+  W_9 == 64'd0 &&
+  a == 64'd0 &&
+  b == 64'd0 &&
+  c == 64'd0 &&
+  d == 64'd0 &&
+  e == 64'd0 &&
+  f == 64'd0 &&
+  g == 64'd0 &&
+  h == 64'd0 &&
+  i == 'sd0 &&
+  block_in_ready == 1 &&
+  digest_valid == 0;
+endproperty
+
+
+DONE_to_IDLE_a: assert property (disable iff(!rst) DONE_to_IDLE_p);
+property DONE_to_IDLE_p;
+  DONE
+|->
+  ##1
+  IDLE &&
+  H_0 == 64'(($past(H_0, 1) + $past(a, 1))) &&
+  H_1 == 64'(($past(H_1, 1) + $past(b, 1))) &&
+  H_2 == 64'(($past(H_2, 1) + $past(c, 1))) &&
+  H_3 == 64'(($past(H_3, 1) + $past(d, 1))) &&
+  H_4 == 64'(($past(H_4, 1) + $past(e, 1))) &&
+  H_5 == 64'(($past(H_5, 1) + $past(f, 1))) &&
+  H_6 == 64'(($past(H_6, 1) + $past(g, 1))) &&
+  H_7 == 64'(($past(H_7, 1) + $past(h, 1))) &&
+  W_0 == $past(W_0, 1) &&
+  W_10 == $past(W_10, 1) &&
+  W_11 == $past(W_11, 1) &&
+  W_12 == $past(W_12, 1) &&
+  W_13 == $past(W_13, 1) &&
+  W_14 == $past(W_14, 1) &&
+  W_15 == $past(W_15, 1) &&
+  W_1 == $past(W_1, 1) &&
+  W_2 == $past(W_2, 1) &&
+  W_3 == $past(W_3, 1) &&
+  W_4 == $past(W_4, 1) &&
+  W_5 == $past(W_5, 1) &&
+  W_6 == $past(W_6, 1) &&
+  W_7 == $past(W_7, 1) &&
+  W_8 == $past(W_8, 1) &&
+  W_9 == $past(W_9, 1) &&
+  a == $past(a, 1) &&
+  b == $past(b, 1) &&
+  c == $past(c, 1) &&
+  d == $past(d, 1) &&
+  e == $past(e, 1) &&
+  f == $past(f, 1) &&
+  g == $past(g, 1) &&
+  h == $past(h, 1) &&
+  i == $past(i, 1) &&
+  digest_out == $past(compute_digest(H_7,h,H_6,g,H_5,f,H_4,e,H_3,d,H_2,c,H_1,b,H_0,a)) &&
+  block_in_ready == 1 &&
+  digest_valid == 1;
+endproperty
+
+
+IDLE_to_SHA_Rounds_a: assert property (disable iff(!rst) IDLE_to_SHA_Rounds_p);
+property IDLE_to_SHA_Rounds_p;
+  IDLE &&
+  block_in_valid &&
+  block_init &&
+  (block_sha_mode == 'sd224)
+|->
+  ##1 (block_in_ready == 0) and
+  ##1 (digest_valid == 0) and
+  ##1
+  SHA_Rounds &&
+  H_0 == 64'd10105294471447203234 &&
+  H_1 == 64'd8350123849800275158 &&
+  H_2 == 64'd2160240930085379202 &&
+  H_3 == 64'd7466358040605728719 &&
+  H_4 == 64'd1111592415079452072 &&
+  H_5 == 64'd8638871050018654530 &&
+  H_6 == 64'd4583966954114332360 &&
+  H_7 == 64'd1230299281376055969 &&
+  W_0 == slicer($past(block_in, 1), 32'sd15) &&
+  W_10 == slicer($past(block_in, 1),32'sd5) &&
+  W_11 == slicer($past(block_in, 1),32'sd4) &&
+  W_12 == slicer($past(block_in, 1),32'sd3) &&
+  W_13 == slicer($past(block_in, 1),32'sd2) &&
+  W_14 == slicer($past(block_in, 1),32'sd1) &&
+  W_15 == slicer($past(block_in, 1),32'sd0) &&
+  W_1 == slicer($past(block_in, 1), 32'sd14) &&
+  W_2 == slicer($past(block_in, 1), 32'sd13) &&
+  W_3 == slicer($past(block_in, 1), 32'sd12) &&
+  W_4 == slicer($past(block_in, 1), 32'sd11) &&
+  W_5 == slicer($past(block_in, 1), 32'sd10) &&
+  W_6 == slicer($past(block_in, 1), 32'sd9) &&
+  W_7 == slicer($past(block_in, 1), 32'sd8) &&
+  W_8 == slicer($past(block_in, 1), 32'sd7) &&
+  W_9 == slicer($past(block_in, 1), 32'sd6) &&
+  a == 64'd10105294471447203234 &&
+  b == 64'd8350123849800275158 &&
+  c == 64'd2160240930085379202 &&
+  d == 64'd7466358040605728719 &&
+  e == 64'd1111592415079452072 &&
+  f == 64'd8638871050018654530 &&
+  g == 64'd4583966954114332360 &&
+  h == 64'd1230299281376055969 &&
+  i == 'sd0;
+endproperty
+
+
+IDLE_to_SHA_Rounds_1_a: assert property (disable iff(!rst) IDLE_to_SHA_Rounds_1_p);
+property IDLE_to_SHA_Rounds_1_p;
+  IDLE &&
+  block_in_valid &&
+  block_init &&
+  (block_sha_mode == 'sd256)
+|->
+  ##1 (block_in_ready == 0) and
+  ##1 (digest_valid == 0) and
+  ##1
+  SHA_Rounds &&
+  H_0 == 64'd2463787394917988140 &&
+  H_1 == 64'd11481187982095705282 &&
+  H_2 == 64'd2563595384472711505 &&
+  H_3 == 64'd10824532655140301501 &&
+  H_4 == 64'd10819967247969091555 &&
+  H_5 == 64'd13717434660681038226 &&
+  H_6 == 64'd3098927326965381290 &&
+  H_7 == 64'd1060366662362279074 &&
+  W_0 == slicer($past(block_in, 1), 32'sd15) &&
+  W_10 == slicer($past(block_in, 1),32'sd5) &&
+  W_11 == slicer($past(block_in, 1),32'sd4) &&
+  W_12 == slicer($past(block_in, 1),32'sd3) &&
+  W_13 == slicer($past(block_in, 1),32'sd2) &&
+  W_14 == slicer($past(block_in, 1),32'sd1) &&
+  W_15 == slicer($past(block_in, 1),32'sd0) &&
+  W_1 == slicer($past(block_in, 1), 32'sd14) &&
+  W_2 == slicer($past(block_in, 1), 32'sd13) &&
+  W_3 == slicer($past(block_in, 1), 32'sd12) &&
+  W_4 == slicer($past(block_in, 1), 32'sd11) &&
+  W_5 == slicer($past(block_in, 1), 32'sd10) &&
+  W_6 == slicer($past(block_in, 1), 32'sd9) &&
+  W_7 == slicer($past(block_in, 1), 32'sd8) &&
+  W_8 == slicer($past(block_in, 1), 32'sd7) &&
+  W_9 == slicer($past(block_in, 1), 32'sd6) &&
+  a == 64'd2463787394917988140 &&
+  b == 64'd11481187982095705282 &&
+  c == 64'd2563595384472711505 &&
+  d == 64'd10824532655140301501 &&
+  e == 64'd10819967247969091555 &&
+  f == 64'd13717434660681038226 &&
+  g == 64'd3098927326965381290 &&
+  h == 64'd1060366662362279074 &&
+  i == 'sd0;
+endproperty
+
+
+IDLE_to_SHA_Rounds_2_a: assert property (disable iff(!rst) IDLE_to_SHA_Rounds_2_p);
+property IDLE_to_SHA_Rounds_2_p;
+  IDLE &&
+  block_in_valid &&
+  block_init &&
+  (block_sha_mode == 'sd512)
+|->
+  ##1 (block_in_ready == 0) and
+  ##1 (digest_valid == 0) and
+  ##1
+  SHA_Rounds &&
+  H_0 == 64'd7640891576956012808 &&
+  H_1 == 64'd13503953896175478587 &&
+  H_2 == 64'd4354685564936845355 &&
+  H_3 == 64'd11912009170470909681 &&
+  H_4 == 64'd5840696475078001361 &&
+  H_5 == 64'd11170449401992604703 &&
+  H_6 == 64'd2270897969802886507 &&
+  H_7 == 64'd6620516959819538809 &&
+  W_0 == slicer($past(block_in, 1), 32'sd15) &&
+  W_10 == slicer($past(block_in, 1),32'sd5) &&
+  W_11 == slicer($past(block_in, 1),32'sd4) &&
+  W_12 == slicer($past(block_in, 1),32'sd3) &&
+  W_13 == slicer($past(block_in, 1),32'sd2) &&
+  W_14 == slicer($past(block_in, 1),32'sd1) &&
+  W_15 == slicer($past(block_in, 1),32'sd0) &&
+  W_1 == slicer($past(block_in, 1), 32'sd14) &&
+  W_2 == slicer($past(block_in, 1), 32'sd13) &&
+  W_3 == slicer($past(block_in, 1), 32'sd12) &&
+  W_4 == slicer($past(block_in, 1), 32'sd11) &&
+  W_5 == slicer($past(block_in, 1), 32'sd10) &&
+  W_6 == slicer($past(block_in, 1), 32'sd9) &&
+  W_7 == slicer($past(block_in, 1), 32'sd8) &&
+  W_8 == slicer($past(block_in, 1), 32'sd7) &&
+  W_9 == slicer($past(block_in, 1), 32'sd6) &&
+  a == 64'd7640891576956012808 &&
+  b == 64'd13503953896175478587 &&
+  c == 64'd4354685564936845355 &&
+  d == 64'd11912009170470909681 &&
+  e == 64'd5840696475078001361 &&
+  f == 64'd11170449401992604703 &&
+  g == 64'd2270897969802886507 &&
+  h == 64'd6620516959819538809 &&
+  i == 'sd0;
+endproperty
+
+
+IDLE_to_SHA_Rounds_3_a: assert property (disable iff(!rst) IDLE_to_SHA_Rounds_3_p);
+property IDLE_to_SHA_Rounds_3_p;
+  IDLE &&
+  block_in_valid &&
+  block_init &&
+  (block_sha_mode != 'sd224) &&
+  (block_sha_mode != 'sd256) &&
+  (block_sha_mode != 'sd512)
+|->
+  ##1 (block_in_ready == 0) and
+  ##1 (digest_valid == 0) and
+  ##1
+  SHA_Rounds &&
+  H_0 == 64'd14680500436340154072 &&
+  H_1 == 64'd7105036623409894663 &&
+  H_2 == 64'd10473403895298186519 &&
+  H_3 == 64'd1526699215303891257 &&
+  H_4 == 64'd7436329637833083697 &&
+  H_5 == 64'd10282925794625328401 &&
+  H_6 == 64'd15784041429090275239 &&
+  H_7 == 64'd5167115440072839076 &&
+  W_0 == slicer($past(block_in, 1), 32'sd15) &&
+  W_10 == slicer($past(block_in, 1),32'sd5) &&
+  W_11 == slicer($past(block_in, 1),32'sd4) &&
+  W_12 == slicer($past(block_in, 1),32'sd3) &&
+  W_13 == slicer($past(block_in, 1),32'sd2) &&
+  W_14 == slicer($past(block_in, 1),32'sd1) &&
+  W_15 == slicer($past(block_in, 1),32'sd0) &&
+  W_1 == slicer($past(block_in, 1), 32'sd14) &&
+  W_2 == slicer($past(block_in, 1), 32'sd13) &&
+  W_3 == slicer($past(block_in, 1), 32'sd12) &&
+  W_4 == slicer($past(block_in, 1), 32'sd11) &&
+  W_5 == slicer($past(block_in, 1), 32'sd10) &&
+  W_6 == slicer($past(block_in, 1), 32'sd9) &&
+  W_7 == slicer($past(block_in, 1), 32'sd8) &&
+  W_8 == slicer($past(block_in, 1), 32'sd7) &&
+  W_9 == slicer($past(block_in, 1), 32'sd6) &&
+  a == 64'd14680500436340154072 &&
+  b == 64'd7105036623409894663 &&
+  c == 64'd10473403895298186519 &&
+  d == 64'd1526699215303891257 &&
+  e == 64'd7436329637833083697 &&
+  f == 64'd10282925794625328401 &&
+  g == 64'd15784041429090275239 &&
+  h == 64'd5167115440072839076 &&
+  i == 'sd0;
+endproperty
+
+
+IDLE_to_SHA_Rounds_4_a: assert property (disable iff(!rst) IDLE_to_SHA_Rounds_4_p);
+property IDLE_to_SHA_Rounds_4_p;
+  IDLE &&
+  block_in_valid &&
+  !block_init
+|->
+  ##1 (block_in_ready == 0) and
+  ##1 (digest_valid == 0) and
+  ##1
+  SHA_Rounds &&
+  H_0 == $past(H_0, 1) &&
+  H_1 == $past(H_1, 1) &&
+  H_2 == $past(H_2, 1) &&
+  H_3 == $past(H_3, 1) &&
+  H_4 == $past(H_4, 1) &&
+  H_5 == $past(H_5, 1) &&
+  H_6 == $past(H_6, 1) &&
+  H_7 == $past(H_7, 1) &&
+  W_0 == slicer($past(block_in, 1), 32'sd15) &&
+  W_10 == slicer($past(block_in, 1),32'sd5) &&
+  W_11 == slicer($past(block_in, 1),32'sd4) &&
+  W_12 == slicer($past(block_in, 1),32'sd3) &&
+  W_13 == slicer($past(block_in, 1),32'sd2) &&
+  W_14 == slicer($past(block_in, 1),32'sd1) &&
+  W_15 == slicer($past(block_in, 1),32'sd0) &&
+  W_1 == slicer($past(block_in, 1), 32'sd14) &&
+  W_2 == slicer($past(block_in, 1), 32'sd13) &&
+  W_3 == slicer($past(block_in, 1), 32'sd12) &&
+  W_4 == slicer($past(block_in, 1), 32'sd11) &&
+  W_5 == slicer($past(block_in, 1), 32'sd10) &&
+  W_6 == slicer($past(block_in, 1), 32'sd9) &&
+  W_7 == slicer($past(block_in, 1), 32'sd8) &&
+  W_8 == slicer($past(block_in, 1), 32'sd7) &&
+  W_9 == slicer($past(block_in, 1), 32'sd6) &&
+  a == $past(H_0, 1) &&
+  b == $past(H_1, 1) &&
+  c == $past(H_2, 1) &&
+  d == $past(H_3, 1) &&
+  e == $past(H_4, 1) &&
+  f == $past(H_5, 1) &&
+  g == $past(H_6, 1) &&
+  h == $past(H_7, 1) &&
+  i == 'sd0;
+endproperty
+
+
+SHA_Rounds_to_DONE_a: assert property (disable iff(!rst) SHA_Rounds_to_DONE_p);
+property SHA_Rounds_to_DONE_p;
+  SHA_Rounds &&
+  (i >= 'sd16) &&
+  (('sd1 + i) >= 'sd80)
+|->
+  ##1 (block_in_ready == 0) and
+  ##1 (digest_valid == 0) and
+  ##1
+  DONE &&
+  H_0 == $past(H_0, 1) &&
+  H_1 == $past(H_1, 1) &&
+  H_2 == $past(H_2, 1) &&
+  H_3 == $past(H_3, 1) &&
+  H_4 == $past(H_4, 1) &&
+  H_5 == $past(H_5, 1) &&
+  H_6 == $past(H_6, 1) &&
+  H_7 == $past(H_7, 1) &&
+  W_0 == $past(W_1, 1) &&
+  W_10 == $past(W_11, 1) &&
+  W_11 == $past(W_12, 1) &&
+  W_12 == $past(W_13, 1) &&
+  W_13 == $past(W_14, 1) &&
+  W_14 == $past(W_15, 1) &&
+  W_15 == $past(compute_w(W_14,W_9,W_1,W_0)) &&
+  W_1 == $past(W_2, 1) &&
+  W_2 == $past(W_3, 1) &&
+  W_3 == $past(W_4, 1) &&
+  W_4 == $past(W_5, 1) &&
+  W_5 == $past(W_6, 1) &&
+  W_6 == $past(W_7, 1) &&
+  W_7 == $past(W_8, 1) &&
+  W_8 == $past(W_9, 1) &&
+  W_9 == $past(W_10, 1) &&
+  a == $past(64'(T1(e,f,g,h,K[i],compute_w(W_14,W_9,W_1,W_0))+T2(a,b,c))) &&
+  b == $past(a, 1) &&
+  c == $past(b, 1) &&
+  d == $past(c, 1) &&
+  e == $past(64'(d+T1(e,f,g,h,K[i],compute_w(W_14,W_9,W_1,W_0)))) &&
+  f == $past(e, 1) &&
+  g == $past(f, 1) &&
+  h == $past(g, 1) &&
+  i == ('sd1 + $past(i, 1));
+endproperty
+
+
+SHA_Rounds_to_SHA_Rounds_a: assert property (disable iff(!rst) SHA_Rounds_to_SHA_Rounds_p);
+property SHA_Rounds_to_SHA_Rounds_p;
+  SHA_Rounds &&
+  (i < 'sd16)
+|->
+  ##1 (block_in_ready == 0) and
+  ##1 (digest_valid == 0) and
+  ##1
+  SHA_Rounds &&
+  H_0 == $past(H_0, 1) &&
+  H_1 == $past(H_1, 1) &&
+  H_2 == $past(H_2, 1) &&
+  H_3 == $past(H_3, 1) &&
+  H_4 == $past(H_4, 1) &&
+  H_5 == $past(H_5, 1) &&
+  H_6 == $past(H_6, 1) &&
+  H_7 == $past(H_7, 1) &&
+  W_0 == $past(W_0, 1) &&
+  W_10 == $past(W_10, 1) &&
+  W_11 == $past(W_11, 1) &&
+  W_12 == $past(W_12, 1) &&
+  W_13 == $past(W_13, 1) &&
+  W_14 == $past(W_14, 1) &&
+  W_15 == $past(W_15, 1) &&
+  W_1 == $past(W_1, 1) &&
+  W_2 == $past(W_2, 1) &&
+  W_3 == $past(W_3, 1) &&
+  W_4 == $past(W_4, 1) &&
+  W_5 == $past(W_5, 1) &&
+  W_6 == $past(W_6, 1) &&
+  W_7 == $past(W_7, 1) &&
+  W_8 == $past(W_8, 1) &&
+  W_9 == $past(W_9, 1) &&
+  a == $past(64'(T1(e,f,g,h,K[i],W[j])+T2(a,b,c))) &&
+  b == $past(a, 1) &&
+  c == $past(b, 1) &&
+  d == $past(c, 1) &&
+  e == $past(64'(d+T1(e,f,g,h,K[i],W[j]))) &&
+  f == $past(e, 1) &&
+  g == $past(f, 1) &&
+  h == $past(g, 1) &&
+  i == ('sd1 + $past(i, 1));
+endproperty
+
+
+SHA_Rounds_to_SHA_Rounds_1_a: assert property (disable iff(!rst) SHA_Rounds_to_SHA_Rounds_1_p);
+property SHA_Rounds_to_SHA_Rounds_1_p;
+  SHA_Rounds &&
+  (i >= 'sd16) &&
+  (('sd1 + i) < 'sd80)
+|->
+  ##1 (block_in_ready == 0) and
+  ##1 (digest_valid == 0) and
+  ##1
+  SHA_Rounds &&
+  H_0 == $past(H_0, 1) &&
+  H_1 == $past(H_1, 1) &&
+  H_2 == $past(H_2, 1) &&
+  H_3 == $past(H_3, 1) &&
+  H_4 == $past(H_4, 1) &&
+  H_5 == $past(H_5, 1) &&
+  H_6 == $past(H_6, 1) &&
+  H_7 == $past(H_7, 1) &&
+  W_0 == $past(W_1, 1) &&
+  W_10 == $past(W_11, 1) &&
+  W_11 == $past(W_12, 1) &&
+  W_12 == $past(W_13, 1) &&
+  W_13 == $past(W_14, 1) &&
+  W_14 == $past(W_15, 1) &&
+  W_15 == $past(compute_w(W_14,W_9,W_1,W_0)) &&
+  W_1 == $past(W_2, 1) &&
+  W_2 == $past(W_3, 1) &&
+  W_3 == $past(W_4, 1) &&
+  W_4 == $past(W_5, 1) &&
+  W_5 == $past(W_6, 1) &&
+  W_6 == $past(W_7, 1) &&
+  W_7 == $past(W_8, 1) &&
+  W_8 == $past(W_9, 1) &&
+  W_9 == $past(W_10, 1) &&
+  a == $past(64'(T1(e,f,g,h,K[i],compute_w(W_14,W_9,W_1,W_0))+T2(a,b,c))) &&
+  b == $past(a, 1) &&
+  c == $past(b, 1) &&
+  d == $past(c, 1) &&
+  e == $past(64'(d+T1(e,f,g,h,K[i],compute_w(W_14,W_9,W_1,W_0)))) &&
+  f == $past(e, 1) &&
+  g == $past(f, 1) &&
+  h == $past(g, 1) &&
+  i == ('sd1 + $past(i, 1));
+endproperty
+
+
+IDLE_wait_a: assert property (disable iff(!rst) IDLE_wait_p);
+property IDLE_wait_p;
+  IDLE &&
+  !block_in_valid
+|->
+  ##1
+  IDLE &&
+  H_0 == $past(H_0, 1) &&
+  H_1 == $past(H_1, 1) &&
+  H_2 == $past(H_2, 1) &&
+  H_3 == $past(H_3, 1) &&
+  H_4 == $past(H_4, 1) &&
+  H_5 == $past(H_5, 1) &&
+  H_6 == $past(H_6, 1) &&
+  H_7 == $past(H_7, 1) &&
+  W_0 == $past(W_0, 1) &&
+  W_10 == $past(W_10, 1) &&
+  W_11 == $past(W_11, 1) &&
+  W_12 == $past(W_12, 1) &&
+  W_13 == $past(W_13, 1) &&
+  W_14 == $past(W_14, 1) &&
+  W_15 == $past(W_15, 1) &&
+  W_1 == $past(W_1, 1) &&
+  W_2 == $past(W_2, 1) &&
+  W_3 == $past(W_3, 1) &&
+  W_4 == $past(W_4, 1) &&
+  W_5 == $past(W_5, 1) &&
+  W_6 == $past(W_6, 1) &&
+  W_7 == $past(W_7, 1) &&
+  W_8 == $past(W_8, 1) &&
+  W_9 == $past(W_9, 1) &&
+  a == $past(a, 1) &&
+  b == $past(b, 1) &&
+  c == $past(c, 1) &&
+  d == $past(d, 1) &&
+  e == $past(e, 1) &&
+  f == $past(f, 1) &&
+  g == $past(g, 1) &&
+  h == $past(h, 1) &&
+  i == $past(i, 1) &&
+  block_in_ready == 1 &&
+  digest_valid == $past(digest_valid);
+endproperty
+
+
+endmodule
+
+ bind sha512_core fv_sha_512_m fv_sha512(
+  .rst((sha512_core.reset_n)  && !(sha512_core.zeroize)),
+  .clk(sha512_core.clk),
+  .block_in(sha512_core.block_msg),
+  .block_sha_mode(get_block_sha_mode(sha512_core.mode)),
+  .block_init(sha512_core.init_cmd),
+  .block_next(sha512_core.next_cmd),
+  .block_zeroize(sha512_core.zeroize),
+  .digest_out(sha512_core.digest),
+  .block_in_valid(((sha512_core.init_cmd) || (sha512_core.next_cmd))),
+  .block_in_ready(sha512_core.ready),
+  .digest_valid((sha512_core.digest_valid) ),
+  .H_0(sha512_core.H0_reg),
+  .H_1(sha512_core.H1_reg),
+  .H_2(sha512_core.H2_reg),
+  .H_3(sha512_core.H3_reg),
+  .H_4(sha512_core.H4_reg),
+  .H_5(sha512_core.H5_reg),
+  .H_6(sha512_core.H6_reg),
+  .H_7(sha512_core.H7_reg),
+  .W_0(sha512_core.w_mem_inst.w_mem[00]),
+  .W_1(sha512_core.w_mem_inst.w_mem[01]),
+  .W_2(sha512_core.w_mem_inst.w_mem[02]),
+  .W_3(sha512_core.w_mem_inst.w_mem[03]),
+  .W_4(sha512_core.w_mem_inst.w_mem[04]),
+  .W_5(sha512_core.w_mem_inst.w_mem[05]),
+  .W_6(sha512_core.w_mem_inst.w_mem[06]),
+  .W_7(sha512_core.w_mem_inst.w_mem[07]),
+  .W_8(sha512_core.w_mem_inst.w_mem[08]),
+  .W_9(sha512_core.w_mem_inst.w_mem[09]),
+  .W_10(sha512_core.w_mem_inst.w_mem[10]),
+  .W_11(sha512_core.w_mem_inst.w_mem[11]),
+  .W_12(sha512_core.w_mem_inst.w_mem[12]),
+  .W_13(sha512_core.w_mem_inst.w_mem[13]),
+  .W_14(sha512_core.w_mem_inst.w_mem[14]),
+  .W_15(sha512_core.w_mem_inst.w_mem[15]),
+  .a(sha512_core.a_reg),
+  .b(sha512_core.b_reg),
+  .c(sha512_core.c_reg),
+  .d(sha512_core.d_reg),
+  .e(sha512_core.e_reg),
+  .f(sha512_core.f_reg),
+  .g(sha512_core.g_reg),
+  .h(sha512_core.h_reg),
+  .i(sha512_core.round_ctr_reg),
+  .IDLE(sha512_core.sha512_ctrl_reg==2'h0),
+  .SHA_Rounds(sha512_core.sha512_ctrl_reg==2'h1),
+  .DONE(sha512_core.sha512_ctrl_reg==2'h2)
+);
+
diff --git a/src/sha512/formal/properties/fv_sha512_pkg.sv b/src/sha512/formal/properties/fv_sha512_pkg.sv
new file mode 100644
index 000000000..45ab5eb0c
--- /dev/null
+++ b/src/sha512/formal/properties/fv_sha512_pkg.sv
@@ -0,0 +1,183 @@
+// -------------------------------------------------
+// Contact: contact@lubis-eda.com
+// Author: Tobias Ludwig, Michael Schwarz
+// -------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+
+package fv_sha512_pkg;
+
+
+typedef bit unsigned [63:0] a_sc_big_unsigned_64_80 [79:0];
+
+
+// Constants
+
+parameter a_sc_big_unsigned_64_80 K = '{ 0:64'd4794697086780616226, 1:64'd8158064640168781261, 2:64'd13096744586834688815, 3:64'd16840607885511220156, 4:64'd4131703408338449720, 5:64'd6480981068601479193, 6:64'd10538285296894168987, 7:64'd12329834152419229976, 8:64'd15566598209576043074, 9:64'd1334009975649890238, 10:64'd2608012711638119052, 11:64'd6128411473006802146, 12:64'd8268148722764581231, 13:64'd9286055187155687089, 14:64'd11230858885718282805, 15:64'd13951009754708518548, 16:64'd16472876342353939154, 17:64'd17275323862435702243, 18:64'd1135362057144423861, 19:64'd2597628984639134821, 20:64'd3308224258029322869, 21:64'd5365058923640841347, 22:64'd6679025012923562964, 23:64'd8573033837759648693, 24:64'd10970295158949994411, 25:64'd12119686244451234320, 26:64'd12683024718118986047, 27:64'd13788192230050041572, 28:64'd14330467153632333762, 29:64'd15395433587784984357, 30:64'd489312712824947311, 31:64'd1452737877330783856, 32:64'd2861767655752347644, 33:64'd3322285676063803686, 34:64'd5560940570517711597, 35:64'd5996557281743188959, 36:64'd7280758554555802590, 37:64'd8532644243296465576, 38:64'd9350256976987008742, 39:64'd10552545826968843579, 40:64'd11727347734174303076, 41:64'd12113106623233404929, 42:64'd14000437183269869457, 43:64'd14369950271660146224, 44:64'd15101387698204529176, 45:64'd15463397548674623760, 46:64'd17586052441742319658, 47:64'd1182934255886127544, 48:64'd1847814050463011016, 49:64'd2177327727835720531, 50:64'd2830643537854262169, 51:64'd3796741975233480872, 52:64'd4115178125766777443, 53:64'd5681478168544905931, 54:64'd6601373596472566643, 55:64'd7507060721942968483, 56:64'd8399075790359081724, 57:64'd8693463985226723168, 58:64'd9568029438360202098, 59:64'd10144078919501101548, 60:64'd10430055236837252648, 61:64'd11840083180663258601, 62:64'd13761210420658862357, 63:64'd14299343276471374635, 64:64'd14566680578165727644, 65:64'd15097957966210449927, 66:64'd16922976911328602910, 67:64'd17689382322260857208, 68:64'd500013540394364858, 69:64'd748580250866718886, 70:64'd1242879168328830382, 71:64'd1977374033974150939, 72:64'd2944078676154940804, 73:64'd3659926193048069267, 74:64'd4368137639120453308, 75:64'd4836135668995329356, 76:64'd5532061633213252278, 77:64'd6448918945643986474, 78:64'd6902733635092675308, 79:64'd7801388544844847127 };
+
+
+// Functions
+
+function bit unsigned [63:0] Ch(bit unsigned [63:0] a, bit unsigned [63:0] b, bit unsigned [63:0] c);
+  return ((a & b) ^ (~a & c));
+endfunction
+
+function bit unsigned [63:0] Maj(bit unsigned [63:0] x, bit unsigned [63:0] y, bit unsigned [63:0] z);
+  return (((x & y) ^ (x & z)) ^ (y & z));
+endfunction
+
+function bit unsigned [63:0] T1(bit unsigned [63:0] e, bit unsigned [63:0] f, bit unsigned [63:0] g, bit unsigned [63:0] h, bit unsigned [63:0] k, bit unsigned [63:0] w);
+  return 64'(((((h + sigma1(e)) + Ch(e, f, g)) + k) + w));
+endfunction
+
+function bit unsigned [63:0] T2(bit unsigned [63:0] a, bit unsigned [63:0] b, bit unsigned [63:0] c);
+  return 64'((sigma0(a) + Maj(a, b, c)));
+endfunction
+
+function bit unsigned [63:0] compute_w(bit unsigned [63:0] w14, bit unsigned [63:0] w9, bit unsigned [63:0] w1, bit unsigned [63:0] w0);
+  return 64'((((delta1(w14) + w9) + delta0(w1)) + w0));
+endfunction
+
+function bit unsigned [511:0] compute_digest(bit unsigned [63:0] H_7,bit unsigned [63:0] h,bit unsigned [63:0] H_6,bit unsigned [63:0] g,bit unsigned [63:0] H_5,bit unsigned [63:0] f,bit unsigned [63:0] H_4,bit unsigned [63:0] e,bit unsigned [63:0] H_3,bit unsigned [63:0] d,bit unsigned [63:0] H_2,bit unsigned [63:0] c,bit unsigned [63:0] H_1,bit unsigned [63:0] b,bit unsigned [63:0] H_0,bit unsigned [63:0] a);
+  bit unsigned [511:0] temp;
+    temp[63:0] = 64'(H_7+h);
+    temp[127:64] = 64'(H_6+g);
+    temp[191:128] = 64'(H_5+f);
+    temp[255:192] = 64'(H_4+e);
+    temp[319:256] = 64'(H_3+d);
+    temp[383:320] = 64'(H_2+c);
+    temp[447:384] = 64'(H_1+b);
+    temp[511:448] = 64'(H_0+a);
+  return temp;
+ endfunction
+
+function bit unsigned [63:0] delta0(bit unsigned [63:0] x);
+  return ((rotr1(x) ^ rotr8(x)) ^ shr7(x));
+endfunction
+
+function bit unsigned [63:0] delta1(bit unsigned [63:0] x);
+  return ((rotr19(x) ^ rotr61(x)) ^ shr6(x));
+endfunction
+
+function bit unsigned [31:0] get_block_sha_mode(input logic[1:0] mode );
+if(mode==0)
+	return 224;
+else if(mode==1)
+	return 256;
+else if(mode==2)
+	return 384;
+else
+	return 512;
+endfunction
+
+function bit unsigned [63:0] past_w(bit unsigned [6:0]i,bit unsigned [63:0]W_0,bit unsigned [63:0]W_1,bit unsigned [63:0]W_2,bit unsigned [63:0]W_3,bit unsigned [63:0]W_4,bit unsigned [63:0]W_5,bit unsigned [63:0]W_6,bit unsigned [63:0]W_7,bit unsigned [63:0]W_8,bit unsigned [63:0]W_9,bit unsigned [63:0]W_10,bit unsigned [63:0]W_11,bit unsigned [63:0]W_12,bit unsigned [63:0]W_13,bit unsigned [63:0]W_14,bit unsigned [63:0]W_15);
+  return ((i == 'sd0) ? W_0 : ((i == 'sd1) ? W_1 : ((i == 'sd2) ? W_2 : ((i == 'sd3) ? W_3 : ((i == 'sd4) ? W_4 : ((i == 'sd5) ? W_5 : ((i == 'sd6) ? W_6 : ((i == 'sd7) ? W_7 : ((i == 'sd8) ? W_8 : ((i == 'sd9) ? W_9 : ((i == 'sd10) ? W_10 : ((i == 'sd11) ? W_11 : ((i == 'sd12) ? W_12 : ((i == 'sd13) ? W_13 : ((i == 'sd14) ? W_14 : W_15)))))))))))))));
+endfunction
+
+function bit unsigned [63:0] rotr1(bit unsigned [63:0] n);
+  return 64'(((n >> 64'd1) | (n << 64'd63)));
+endfunction
+
+function bit unsigned [63:0] rotr14(bit unsigned [63:0] n);
+  return 64'(((n >> 64'd14) | (n << 64'd50)));
+endfunction
+
+function bit unsigned [63:0] rotr18(bit unsigned [63:0] n);
+  return 64'(((n >> 64'd18) | (n << 64'd46)));
+endfunction
+
+function bit unsigned [63:0] rotr19(bit unsigned [63:0] n);
+  return 64'(((n >> 64'd19) | (n << 64'd45)));
+endfunction
+
+function bit unsigned [63:0] rotr28(bit unsigned [63:0] n);
+  return 64'(((n >> 64'd28) | (n << 64'd36)));
+endfunction
+
+function bit unsigned [63:0] rotr34(bit unsigned [63:0] n);
+  return 64'(((n >> 64'd34) | (n << 64'd30)));
+endfunction
+
+function bit unsigned [63:0] rotr39(bit unsigned [63:0] n);
+  return 64'(((n >> 64'd39) | (n << 64'd25)));
+endfunction
+
+function bit unsigned [63:0] rotr41(bit unsigned [63:0] n);
+  return 64'(((n >> 64'd41) | (n << 64'd23)));
+endfunction
+
+function bit unsigned [63:0] rotr61(bit unsigned [63:0] n);
+  return 64'(((n >> 64'd61) | (n << 64'd3)));
+endfunction
+
+function bit unsigned [63:0] rotr8(bit unsigned [63:0] n);
+  return 64'(((n >> 64'd8) | (n << 64'd56)));
+endfunction
+
+function bit unsigned [63:0] shr6(bit unsigned [63:0] n);
+  return (n >> 64'd6);
+endfunction
+
+function bit unsigned [63:0] shr7(bit unsigned [63:0] n);
+  return (n >> 64'd7);
+endfunction
+
+function bit unsigned [63:0] sigma0(bit unsigned [63:0] x);
+  return ((rotr28(x) ^ rotr34(x)) ^ rotr39(x));
+endfunction
+
+function bit unsigned [63:0] sigma1(bit unsigned [63:0] x);
+  return ((rotr14(x) ^ rotr18(x)) ^ rotr41(x));
+endfunction
+
+function bit unsigned [63:0] slicer(bit unsigned [1023:0] block, bit signed [31:0] index);
+  if ((index == 'sd0))
+    return 64'((block >> 1024'd0));
+  else if ((index == 'sd1))
+    return 64'((block >> 1024'd64));
+  else if ((index == 'sd2))
+    return 64'((block >> 1024'd128));
+  else if ((index == 'sd3))
+    return 64'((block >> 1024'd192));
+  else if ((index == 'sd4))
+    return 64'((block >> 1024'd256));
+  else if ((index == 'sd5))
+    return 64'((block >> 1024'd320));
+  else if ((index == 'sd6))
+    return 64'((block >> 1024'd384));
+  else if ((index == 'sd7))
+    return 64'((block >> 1024'd448));
+  else if ((index == 'sd8))
+    return 64'((block >> 1024'd512));
+  else if ((index == 'sd9))
+    return 64'((block >> 1024'd576));
+  else if ((index == 'sd10))
+    return 64'((block >> 1024'd640));
+  else if ((index == 'sd11))
+    return 64'((block >> 1024'd704));
+  else if ((index == 'sd12))
+    return 64'((block >> 1024'd768));
+  else if ((index == 'sd13))
+    return 64'((block >> 1024'd832));
+  else if ((index == 'sd14))
+    return 64'((block >> 1024'd896));
+  else if ((index == 'sd15))
+    return 64'((block >> 1024'd960));
+  else
+    return 64'((block >> 1024'd960));
+endfunction
+
+
+endpackage
diff --git a/src/sha512/formal/readme.md b/src/sha512/formal/readme.md
new file mode 100644
index 000000000..8bfb89433
--- /dev/null
+++ b/src/sha512/formal/readme.md
@@ -0,0 +1,72 @@
+# SHA512
+Date: 28-06-2023
+Author: LUBIS EDA
+
+## Folder Structure
+The following subdirectories are part of the main directory **formal**
+
+- model: Contains the high level abstracted model 
+- properties: Contains the assertion IP(AIP) named as **fv_sha512.sv** and the constraints in place for the respective AIP **fv_constraints.sv**
+
+
+## DUT Overview
+
+The DUT sha512_core has the primary inputs and primary outputs as shown below.
+
+| S.No | Port              | Direction | Description                                                                       |
+| ---- | ----------------- | --------- | --------------------------------------------------------------------------------- |
+| 1    | clk               | input     | The positive edge of the clk is used for all the signals                          |
+| 2    | reset_n           | input     | The reset signal is active low and resets the core                                |
+| 3    | zeroize           | input     | The core is reseted when this signal is triggered.                               |
+| 4    | init              | input     | The core is initialised with respective mode constants and processes the message. |
+| 5    | next              | input     | The core processes the message block with the previously computed results         |
+| 6    | mode[1:0]         | input     | Define which hash function: SHA512,SHA384,SHA224,SHA256                           |
+| 7    | block_msg[1023:0] | input     | The padded block message                                                          |
+| 8    | ready             | output    | When triggered indicates that the core is ready                                      |
+| 9    | digest[511:0]     | output    | The hashed value of the given message block                                       |
+| 10   | digest_valid      | output    | When triggered indicates that the computed digest is ready                        |
+
+When the respective mode is selected and initalised the core iterates for 80 rounds to process the hash value, if the next is triggered then the previous values of the **H** registers are in place for processing the hash value. The digest is always generated of 512 bits, in which if the mode changes to 384 then from MSB 384 bits is a valid output and rest is garbage value.
+## Assertion IP Overview
+
+The Assertion IP signals are bound with the respective signals in the dut, where for the **rst** reset_n && !zeroize is used, which ensures the reset functionality. And another AIP signal block_in_valid is triggered whenever the init or next is high.
+
+- reset_a: Checks that all the resgiters are resetted and the state is idle, with the ready to high.
+
+- DONE_to_IDLE_a: Checks the necessary registers,outputs holds the values when state transits from Done to idle, 
+
+- IDLE_to_SHA_Rounds_a: Checks if the state is in idle ,the mode choosen as 224,the init is triggered then the registers should be initialised with the respective constants of 224.
+
+- IDLE_to_SHA_Rounds_1_a: Checks if the state is in idle ,the mode choosen as 256,the init is triggered then the registers should be initialised with the respective constants of 256.
+
+- IDLE_to_SHA_Rounds_2_a: Checks if the state is in idle ,the mode choosen as 512,the init is triggered then the registers should be initialised with the respective constants of 512.
+
+- IDLE_to_SHA_Rounds_3_a: Checks if the state is in idle ,the mode choosen is neither 512,256 nor 224,the init is triggered then the registers should be initialised with the respective constants of default, which covers 384 mode also.
+
+- IDLE_to_SHA_Rounds_4_a: Checks if the state is in idle and there is no init signal and the next signal asserts then the register holds the past values.
+
+- SHA_Rounds_to_DONE_a: Checks if the rounds are done then the registers are updated correctly.
+
+- SHA_Rounds_to_SHA_Rounds_a: Checks if the the rounds less than 16 then the necessary registers are updated correctly and the round increments.
+
+- SHA_Rounds_to_SHA_Rounds_1_a: Checks if the rounds are greater than 16 and less than 80 then the respective registers are updated correctly and the round increments.
+
+- IDLE_wait_a: Checks if there isn't either init or next signal triggered in idle state then the state stays in idle and holds the past values and the core is ready.
+- 
+## Loading the AIP
+
+
+For onespin:<br>
+    1. Open onespin, select file, run source.<br>
+    2. Select the prove.tcl in onespin folder for running the properties. <br>
+
+For VCformal:<br>
+    1. Navigate to the vcf folder containing tcl scripts.<br>
+    2. open terminal <br>
+    3. run the cmd vcf -f  prove.tcl (for running the properties).<br>
+
+For JasperGold: 
+    1. Open Jaspergold, click on file ->  Tcl scripts -> Source.<br>
+    2. Now Navigate to the script location and select the prove.tcl.<br>
+    3. All the checkers and constraints would be loaded to the interface, right click on them and click on prove task.<br>
+
diff --git a/src/sha512/rtl/sha512.sv b/src/sha512/rtl/sha512.sv
index ca975fbbe..95d8690d0 100644
--- a/src/sha512/rtl/sha512.sv
+++ b/src/sha512/rtl/sha512.sv
@@ -41,6 +41,7 @@
 
 module sha512
     import sha512_reg_pkg::*;
+    import sha512_params_pkg::*;
     import kv_defines_pkg::*;  
     import pv_defines_pkg::*;    
     #(
@@ -77,14 +78,10 @@ module sha512
 
         // Interrupts
         output wire error_intr,
-        output wire notif_intr
+        output wire notif_intr,
+        input  logic debugUnlock_or_scan_mode_switch
     );
 
-  //----------------------------------------------------------------
-  // Internal constant and parameter definitions.
-  //----------------------------------------------------------------
-  `include "sha512_param.sv"
-
   //----------------------------------------------------------------
   // Registers including update variables and write enable.
   //----------------------------------------------------------------
@@ -100,6 +97,7 @@ module sha512
 
   localparam BLOCK_NUM_DWORDS = BLOCK_SIZE / DATA_WIDTH;
   localparam DIG_NUM_DWORDS = DIG_SIZE / DATA_WIDTH;
+  localparam NONCE_NUM_DWORDS = PV_SIZE_OF_NONCE / DATA_WIDTH;
 
   reg [DATA_WIDTH-1 : 0][BLOCK_NUM_DWORDS-1 : 0]    block_reg ;
   reg [DIG_NUM_DWORDS-1 : 0][DATA_WIDTH-1 : 0]      digest_reg;
@@ -137,6 +135,9 @@ module sha512
   kv_write_ctrl_reg_t kv_write_ctrl_reg_q;
   kv_read_ctrl_reg_t kv_read_ctrl_reg;
 
+  //KV Read Data Present 
+  logic kv_read_data_present;
+  logic kv_read_data_present_set, kv_read_data_present_reset;
   //PCR Hash Extend Function
   logic pcr_hash_extend_ip;
   logic pcr_hash_extend_set, pcr_hash_extend_reset;
@@ -152,6 +153,8 @@ module sha512
   logic gen_hash_block_write_en;
   logic [4:0] gen_hash_block_write_offset;
   logic [31:0] gen_hash_block_write_data;
+
+  logic [NONCE_NUM_DWORDS-1 : 0][DATA_WIDTH-1 : 0] pv_nonce;
   //----------------------------------------------------------------
   // Wires.
   //----------------------------------------------------------------
@@ -210,29 +213,31 @@ module sha512
   //----------------------------------------------------------------
   always @ (posedge clk or negedge reset_n) begin : reg_update
     if (!reset_n) begin
-      ready_reg           <= '0;
-      digest_reg          <= '0;
-      digest_valid_reg    <= '0;
-      kv_reg              <= '0;
-      pcr_sign_reg        <= '0;
-      block_reg_lock      <= '0;
-      pcr_hash_extend_ip  <= '0;
-      hash_extend_entry   <= '0;
+      ready_reg            <= '0;
+      digest_reg           <= '0;
+      digest_valid_reg     <= '0;
+      kv_reg               <= '0;
+      pcr_sign_reg         <= '0;
+      block_reg_lock       <= '0;
+      pcr_hash_extend_ip   <= '0;
+      hash_extend_entry    <= '0;
+      kv_read_data_present <= '0;
     end
     else if (zeroize_reg) begin
-      ready_reg           <= '0;
-      digest_reg          <= '0;
-      digest_valid_reg    <= '0;
-      kv_reg              <= '0;
-      pcr_sign_reg        <= '0;
+      ready_reg            <= '0;
+      digest_reg           <= '0;
+      digest_valid_reg     <= '0;
+      kv_reg               <= '0;
+      pcr_sign_reg         <= '0;
+      kv_read_data_present <= '0;
     end
     else begin
       ready_reg        <= core_ready;
       digest_valid_reg <= core_digest_valid;
 
-      if (core_digest_valid & ~digest_valid_reg & ~dest_keyvault)
+      if (core_digest_valid & ~digest_valid_reg & ~(dest_keyvault | kv_read_data_present))
         digest_reg <= core_digest & get_mask;
-      if (core_digest_valid & ~digest_valid_reg & dest_keyvault)
+      if (core_digest_valid & ~digest_valid_reg & (dest_keyvault | kv_read_data_present))
         kv_reg <= core_digest[DIG_NUM_DWORDS-1:DIG_NUM_DWORDS-KV_NUM_DWORDS] & get_mask[DIG_NUM_DWORDS-1:DIG_NUM_DWORDS-KV_NUM_DWORDS];
       if (pcr_sign_we)
         pcr_sign_reg <= pcr_sign;
@@ -241,6 +246,8 @@ module sha512
       pcr_hash_extend_ip <= pcr_hash_extend_set ? '1 :
                             pcr_hash_extend_reset ? '0 : pcr_hash_extend_ip;
       hash_extend_entry <= pcr_hash_extend_set ? kv_read_ctrl_reg.read_entry : hash_extend_entry;
+      kv_read_data_present <= kv_read_data_present_set ? '1 :
+                              kv_read_data_present_reset ? '0 : kv_read_data_present;
     end
   end // reg_update
 
@@ -262,16 +269,16 @@ module sha512
   //register hw interface
   always_comb begin
 
-    hwif_in.SHA512_NAME[0].NAME.next = CORE_NAME0;
-    hwif_in.SHA512_NAME[1].NAME.next = CORE_NAME1;
+    hwif_in.SHA512_NAME[0].NAME.next = SHA512_CORE_NAME0;
+    hwif_in.SHA512_NAME[1].NAME.next = SHA512_CORE_NAME1;
 
-    hwif_in.SHA512_VERSION[0].VERSION.next = CORE_VERSION0;
-    hwif_in.SHA512_VERSION[1].VERSION.next = CORE_VERSION1;
+    hwif_in.SHA512_VERSION[0].VERSION.next = SHA512_CORE_VERSION0;
+    hwif_in.SHA512_VERSION[1].VERSION.next = SHA512_CORE_VERSION1;
 
     init_reg = gen_hash_ip ? gen_hash_init_reg : hwif_out.SHA512_CTRL.INIT.value;
     next_reg = gen_hash_ip ? gen_hash_next_reg : hwif_out.SHA512_CTRL.NEXT.value;
     mode_reg = gen_hash_ip ? 2'b10 : hwif_out.SHA512_CTRL.MODE.value;
-    zeroize_reg = hwif_out.SHA512_CTRL.ZEROIZE.value;
+    zeroize_reg = hwif_out.SHA512_CTRL.ZEROIZE.value || debugUnlock_or_scan_mode_switch;
     last_reg = gen_hash_ip ? gen_hash_last_reg : hwif_out.SHA512_CTRL.LAST.value;
     hwif_in.SHA512_CTRL.LAST.hwclr = core_digest_valid & ~digest_valid_reg;
 
@@ -291,10 +298,11 @@ module sha512
 
     for (int dword=0; dword< BLOCK_NUM_DWORDS; dword++) begin
       block_reg[dword] = hwif_out.SHA512_BLOCK[dword].BLOCK.value;
-      hwif_in.SHA512_BLOCK[dword].BLOCK.we = gen_hash_ip ? gen_hash_block_write_en & (gen_hash_block_write_offset == dword) :
+      hwif_in.SHA512_BLOCK[dword].BLOCK.we = zeroize_reg? 0 : 
+                                             gen_hash_ip ? gen_hash_block_write_en & (gen_hash_block_write_offset == dword) :
                                              (kv_src_write_en & (kv_src_write_offset == dword));
       hwif_in.SHA512_BLOCK[dword].BLOCK.next = gen_hash_ip ? gen_hash_block_write_data : kv_src_write_data;
-      hwif_in.SHA512_BLOCK[dword].BLOCK.hwclr = zeroize_reg & ~block_reg_lock[dword];
+      hwif_in.SHA512_BLOCK[dword].BLOCK.hwclr = (zeroize_reg & ~block_reg_lock[dword]) | kv_read_data_present_reset;
       hwif_in.SHA512_BLOCK[dword].BLOCK.swwel = block_reg_lock[dword];
     end
     //Set valid when fsm is done
@@ -323,6 +331,10 @@ module sha512
   `CALIPTRA_KV_WRITE_CTRL_REG2STRUCT(kv_write_ctrl_reg, SHA512_KV_WR_CTRL)
   `CALIPTRA_KV_READ_CTRL_REG2STRUCT(kv_read_ctrl_reg, SHA512_VAULT_RD_CTRL)
 
+//Force result into KV reg whenever source came from KV
+  always_comb kv_read_data_present_set = kv_read_ctrl_reg.read_en & ~kv_read_ctrl_reg.pcr_hash_extend;
+  always_comb kv_read_data_present_reset = kv_read_data_present & dest_data_avail;
+
 //Hash extend logic
   always_comb pcr_hash_extend_set = kv_read_ctrl_reg.read_en & kv_read_ctrl_reg.pcr_hash_extend;
   always_comb pcr_hash_extend_reset = pcr_hash_extend_ip & kv_dest_done;
@@ -389,6 +401,7 @@ sha512_block_kv_read
 (
     .clk(clk),
     .rst_b(reset_n),
+    .zeroize(zeroize_reg),
 
     //client control register
     .read_ctrl_reg(kv_read_ctrl_reg),
@@ -428,6 +441,12 @@ end
 //write out the dest data to KV or PCR on last iteration of SHA
 always_comb dest_data_avail = core_digest_valid & ~digest_valid_reg & last_reg;
 
+always_comb begin
+  for (int dword=0; dword< NONCE_NUM_DWORDS; dword++) begin
+      pv_nonce[dword] = hwif_out.SHA512_GEN_PCR_HASH_NONCE[dword].NONCE.value;
+  end
+end
+
 kv_write_client #(
   .DATA_WIDTH(384)
 )
@@ -435,6 +454,7 @@ sha512_result_kv_write
 (
   .clk(clk),
   .rst_b(reset_n),
+  .zeroize(zeroize_reg),
 
   //client control register
   .write_ctrl_reg(kv_write_ctrl_reg_q),
@@ -463,7 +483,7 @@ pv_gen_hash1
   .core_digest_valid(gen_hash_ip & dest_data_avail),
 
   .start(gen_hash_start),
-  .nonce(hwif_out.SHA512_GEN_PCR_HASH_NONCE.NONCE.value),
+  .nonce(pv_nonce),
 
   .gen_hash_ip(gen_hash_ip),
   .gen_hash_init_reg(gen_hash_init_reg),
diff --git a/src/sha512/rtl/sha512_ctrl.sv b/src/sha512/rtl/sha512_ctrl.sv
index fd8e17bbd..310a26244 100644
--- a/src/sha512/rtl/sha512_ctrl.sv
+++ b/src/sha512/rtl/sha512_ctrl.sv
@@ -64,7 +64,8 @@ module sha512_ctrl
 
     // Interrupt
     output logic error_intr,
-    output logic notif_intr
+    output logic notif_intr,
+    input  logic debugUnlock_or_scan_mode_switch
 );
 
     //----------------------------------------------------------------
@@ -101,7 +102,8 @@ module sha512_ctrl
         .pv_wr_resp(pv_wr_resp),
         .pcr_signing_hash(pcr_signing_hash),
         .error_intr(error_intr),
-        .notif_intr(notif_intr)
+        .notif_intr(notif_intr),
+        .debugUnlock_or_scan_mode_switch(debugUnlock_or_scan_mode_switch)
     );
 
     //instantiate ahb lite module
diff --git a/src/sha512/rtl/sha512_param.sv b/src/sha512/rtl/sha512_param.sv
deleted file mode 100644
index 74219698c..000000000
--- a/src/sha512/rtl/sha512_param.sv
+++ /dev/null
@@ -1,59 +0,0 @@
-// SPDX-License-Identifier: Apache-2.0
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-//
-  //----------------------------------------------------------------
-  // Internal constant and parameter definitions.
-  //----------------------------------------------------------------
-  localparam ADDR_NAME0           = 32'h00000000;
-  localparam ADDR_NAME1           = 32'h00000004;
-  localparam ADDR_VERSION0        = 32'h00000008;
-  localparam ADDR_VERSION1        = 32'h0000000c;
-
-  localparam ADDR_CTRL            = 32'h00000010;
-  localparam CTRL_INIT_BIT        = 0;
-  localparam CTRL_NEXT_BIT        = 1;
-  localparam CTRL_MODE_LOW_BIT    = 2;
-  localparam CTRL_MODE_HIGH_BIT   = 3;
-  localparam CTRL_WORK_FACTOR_BIT = 7;
-
-  localparam ADDR_STATUS          = 32'h00000018;
-  //localparam STATUS_READY_BIT     = 0;
-  //localparam STATUS_VALID_BIT     = 1;
-
-  localparam ADDR_WORK_FACTOR_NUM = 32'h00000020;
-
-  localparam ADDR_BLOCK_START     = 32'h00000080;
-  localparam ADDR_BLOCK_END       = 32'h000000ff;
-
-  localparam ADDR_DIGEST_START    = 32'h00000100;
-  localparam ADDR_DIGEST_END      = 32'h0000013f;
-
-  localparam SHA512_ADDR_INTR_START    = 32'h00000800;
-  localparam SHA512_ADDR_INTR_END      = 32'h00000BFC;
-
-  localparam CORE_NAME0           = 32'h61327368; // "sha2"
-  localparam CORE_NAME1           = 32'h31322d35; // "-512"
-  localparam CORE_VERSION0        = 32'h3830302e; // "0.80"
-  localparam CORE_VERSION1        = 32'h00000000; // "0"
-
-  localparam MODE_SHA_512_224     = 2'h0;
-  localparam MODE_SHA_512_256     = 2'h1;
-  localparam MODE_SHA_384         = 2'h2;
-  localparam MODE_SHA_512         = 2'h3;
-
-  localparam DEFAULT_WORK_FACTOR_NUM = 32'h000f0000;
-
-//======================================================================
-// EOF sha512_param.sv
-//======================================================================
diff --git a/src/sha512/rtl/sha512_params_pkg.sv b/src/sha512/rtl/sha512_params_pkg.sv
new file mode 100644
index 000000000..292503a66
--- /dev/null
+++ b/src/sha512/rtl/sha512_params_pkg.sv
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//  
+package sha512_params_pkg;
+
+  localparam SHA512_CORE_NAME0           = 32'h61327368; // "sha2"
+  localparam SHA512_CORE_NAME1           = 32'h31322d35; // "-512"
+  localparam SHA512_CORE_VERSION0        = 32'h3830302e; // "0.80"
+  localparam SHA512_CORE_VERSION1        = 32'h00000000; // "0"
+
+  localparam MODE_SHA_512_224     = 2'h0;
+  localparam MODE_SHA_512_256     = 2'h1;
+  localparam MODE_SHA_384         = 2'h2;
+  localparam MODE_SHA_512         = 2'h3;
+
+endpackage
+//======================================================================
+// EOF sha512_params_pkg.sv
+//======================================================================
diff --git a/src/sha512/rtl/sha512_reg.rdl b/src/sha512/rtl/sha512_reg.rdl
index 3b383c2f2..71ec241ae 100644
--- a/src/sha512/rtl/sha512_reg.rdl
+++ b/src/sha512/rtl/sha512_reg.rdl
@@ -84,8 +84,8 @@ addrmap sha512_reg {
         field {desc = "Control next command bit"; singlepulse;} NEXT = 1'b0;
         field {desc = "Control mode command bits";} MODE[2] = 2'b10;
         field {desc = "Zeroize all internal registers"; singlepulse;} ZEROIZE = 1'b0;
-        field {desc = "Indicates last iteration for hash extend function. 
-                       Result of this INIT or NEXT cycle will be written back to PCR"; hwclr;} LAST = 1'b0;
+        field {desc = "Indicates last iteration for keyvault or hash extend function. 
+                       Result of this INIT or NEXT cycle will be written back to the appropriate vault"; hwclr;} LAST = 1'b0;
     
     } SHA512_CTRL @0x00000010;
 
@@ -100,7 +100,7 @@ addrmap sha512_reg {
                 This register is located at SHA512_base_address + 0x0000_0018.";
 
         default sw = r;
-        default hw = rw;
+        default hw = w;
         default resetsignal = reset_b;
         field {desc = "Status ready bit";} READY = 1'b0;
         field {desc = "Status valid bit";} VALID = 1'b0;
@@ -150,7 +150,7 @@ addrmap sha512_reg {
         default hw = r;
         default resetsignal = reset_b;
         field {desc = "Nonce value for PCR Gen Hash Function";} NONCE[32] = 32'b0;
-    } SHA512_GEN_PCR_HASH_NONCE;
+    } SHA512_GEN_PCR_HASH_NONCE[8];
     reg {
         name = "SHA512 PCR Hash Control";
         desc = "Control register for PCR Gen Hash Function";
diff --git a/src/sha512/rtl/sha512_reg.sv b/src/sha512/rtl/sha512_reg.sv
index 229e3545c..bd97bf079 100644
--- a/src/sha512/rtl/sha512_reg.sv
+++ b/src/sha512/rtl/sha512_reg.sv
@@ -74,7 +74,7 @@ module sha512_reg (
         logic SHA512_VAULT_RD_STATUS;
         logic SHA512_KV_WR_CTRL;
         logic SHA512_KV_WR_STATUS;
-        logic SHA512_GEN_PCR_HASH_NONCE;
+        logic [8-1:0]SHA512_GEN_PCR_HASH_NONCE;
         logic SHA512_GEN_PCR_HASH_CTRL;
         logic SHA512_GEN_PCR_HASH_STATUS;
         logic [12-1:0]SHA512_GEN_PCR_HASH_DIGEST;
@@ -125,11 +125,13 @@ module sha512_reg (
         decoded_reg_strb.SHA512_VAULT_RD_STATUS = cpuif_req_masked & (cpuif_addr == 'h604);
         decoded_reg_strb.SHA512_KV_WR_CTRL = cpuif_req_masked & (cpuif_addr == 'h608);
         decoded_reg_strb.SHA512_KV_WR_STATUS = cpuif_req_masked & (cpuif_addr == 'h60c);
-        decoded_reg_strb.SHA512_GEN_PCR_HASH_NONCE = cpuif_req_masked & (cpuif_addr == 'h610);
-        decoded_reg_strb.SHA512_GEN_PCR_HASH_CTRL = cpuif_req_masked & (cpuif_addr == 'h614);
-        decoded_reg_strb.SHA512_GEN_PCR_HASH_STATUS = cpuif_req_masked & (cpuif_addr == 'h618);
+        for(int i0=0; i0<8; i0++) begin
+            decoded_reg_strb.SHA512_GEN_PCR_HASH_NONCE[i0] = cpuif_req_masked & (cpuif_addr == 'h610 + i0*'h4);
+        end
+        decoded_reg_strb.SHA512_GEN_PCR_HASH_CTRL = cpuif_req_masked & (cpuif_addr == 'h630);
+        decoded_reg_strb.SHA512_GEN_PCR_HASH_STATUS = cpuif_req_masked & (cpuif_addr == 'h634);
         for(int i0=0; i0<12; i0++) begin
-            decoded_reg_strb.SHA512_GEN_PCR_HASH_DIGEST[i0] = cpuif_req_masked & (cpuif_addr == 'h61c + i0*'h4);
+            decoded_reg_strb.SHA512_GEN_PCR_HASH_DIGEST[i0] = cpuif_req_masked & (cpuif_addr == 'h638 + i0*'h4);
         end
         decoded_reg_strb.intr_block_rf.global_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h800);
         decoded_reg_strb.intr_block_rf.error_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h804);
@@ -188,16 +190,6 @@ module sha512_reg (
                 logic load_next;
             } LAST;
         } SHA512_CTRL;
-        struct packed{
-            struct packed{
-                logic next;
-                logic load_next;
-            } READY;
-            struct packed{
-                logic next;
-                logic load_next;
-            } VALID;
-        } SHA512_STATUS;
         struct packed{
             struct packed{
                 logic [31:0] next;
@@ -279,7 +271,7 @@ module sha512_reg (
                 logic [31:0] next;
                 logic load_next;
             } NONCE;
-        } SHA512_GEN_PCR_HASH_NONCE;
+        } [8-1:0]SHA512_GEN_PCR_HASH_NONCE;
         struct packed{
             struct packed{
                 logic next;
@@ -495,14 +487,6 @@ module sha512_reg (
                 logic value;
             } LAST;
         } SHA512_CTRL;
-        struct packed{
-            struct packed{
-                logic value;
-            } READY;
-            struct packed{
-                logic value;
-            } VALID;
-        } SHA512_STATUS;
         struct packed{
             struct packed{
                 logic [31:0] value;
@@ -567,7 +551,7 @@ module sha512_reg (
             struct packed{
                 logic [31:0] value;
             } NONCE;
-        } SHA512_GEN_PCR_HASH_NONCE;
+        } [8-1:0]SHA512_GEN_PCR_HASH_NONCE;
         struct packed{
             struct packed{
                 logic value;
@@ -820,44 +804,6 @@ module sha512_reg (
         end
     end
     assign hwif_out.SHA512_CTRL.LAST.value = field_storage.SHA512_CTRL.LAST.value;
-    // Field: sha512_reg.SHA512_STATUS.READY
-    always_comb begin
-        automatic logic [0:0] next_c = field_storage.SHA512_STATUS.READY.value;
-        automatic logic load_next_c = '0;
-        if(1) begin // HW Write
-            next_c = hwif_in.SHA512_STATUS.READY.next;
-            load_next_c = '1;
-        end
-        field_combo.SHA512_STATUS.READY.next = next_c;
-        field_combo.SHA512_STATUS.READY.load_next = load_next_c;
-    end
-    always_ff @(posedge clk or negedge hwif_in.reset_b) begin
-        if(~hwif_in.reset_b) begin
-            field_storage.SHA512_STATUS.READY.value <= 'h0;
-        end else if(field_combo.SHA512_STATUS.READY.load_next) begin
-            field_storage.SHA512_STATUS.READY.value <= field_combo.SHA512_STATUS.READY.next;
-        end
-    end
-    assign hwif_out.SHA512_STATUS.READY.value = field_storage.SHA512_STATUS.READY.value;
-    // Field: sha512_reg.SHA512_STATUS.VALID
-    always_comb begin
-        automatic logic [0:0] next_c = field_storage.SHA512_STATUS.VALID.value;
-        automatic logic load_next_c = '0;
-        if(1) begin // HW Write
-            next_c = hwif_in.SHA512_STATUS.VALID.next;
-            load_next_c = '1;
-        end
-        field_combo.SHA512_STATUS.VALID.next = next_c;
-        field_combo.SHA512_STATUS.VALID.load_next = load_next_c;
-    end
-    always_ff @(posedge clk or negedge hwif_in.reset_b) begin
-        if(~hwif_in.reset_b) begin
-            field_storage.SHA512_STATUS.VALID.value <= 'h0;
-        end else if(field_combo.SHA512_STATUS.VALID.load_next) begin
-            field_storage.SHA512_STATUS.VALID.value <= field_combo.SHA512_STATUS.VALID.next;
-        end
-    end
-    assign hwif_out.SHA512_STATUS.VALID.value = field_storage.SHA512_STATUS.VALID.value;
     for(genvar i0=0; i0<32; i0++) begin
         // Field: sha512_reg.SHA512_BLOCK[].BLOCK
         always_comb begin
@@ -1184,25 +1130,27 @@ module sha512_reg (
             field_storage.SHA512_KV_WR_STATUS.VALID.value <= field_combo.SHA512_KV_WR_STATUS.VALID.next;
         end
     end
-    // Field: sha512_reg.SHA512_GEN_PCR_HASH_NONCE.NONCE
-    always_comb begin
-        automatic logic [31:0] next_c = field_storage.SHA512_GEN_PCR_HASH_NONCE.NONCE.value;
-        automatic logic load_next_c = '0;
-        if(decoded_reg_strb.SHA512_GEN_PCR_HASH_NONCE && decoded_req_is_wr) begin // SW write
-            next_c = (field_storage.SHA512_GEN_PCR_HASH_NONCE.NONCE.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
-            load_next_c = '1;
+    for(genvar i0=0; i0<8; i0++) begin
+        // Field: sha512_reg.SHA512_GEN_PCR_HASH_NONCE[].NONCE
+        always_comb begin
+            automatic logic [31:0] next_c = field_storage.SHA512_GEN_PCR_HASH_NONCE[i0].NONCE.value;
+            automatic logic load_next_c = '0;
+            if(decoded_reg_strb.SHA512_GEN_PCR_HASH_NONCE[i0] && decoded_req_is_wr) begin // SW write
+                next_c = (field_storage.SHA512_GEN_PCR_HASH_NONCE[i0].NONCE.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+                load_next_c = '1;
+            end
+            field_combo.SHA512_GEN_PCR_HASH_NONCE[i0].NONCE.next = next_c;
+            field_combo.SHA512_GEN_PCR_HASH_NONCE[i0].NONCE.load_next = load_next_c;
         end
-        field_combo.SHA512_GEN_PCR_HASH_NONCE.NONCE.next = next_c;
-        field_combo.SHA512_GEN_PCR_HASH_NONCE.NONCE.load_next = load_next_c;
-    end
-    always_ff @(posedge clk or negedge hwif_in.reset_b) begin
-        if(~hwif_in.reset_b) begin
-            field_storage.SHA512_GEN_PCR_HASH_NONCE.NONCE.value <= 'h0;
-        end else if(field_combo.SHA512_GEN_PCR_HASH_NONCE.NONCE.load_next) begin
-            field_storage.SHA512_GEN_PCR_HASH_NONCE.NONCE.value <= field_combo.SHA512_GEN_PCR_HASH_NONCE.NONCE.next;
+        always_ff @(posedge clk or negedge hwif_in.reset_b) begin
+            if(~hwif_in.reset_b) begin
+                field_storage.SHA512_GEN_PCR_HASH_NONCE[i0].NONCE.value <= 'h0;
+            end else if(field_combo.SHA512_GEN_PCR_HASH_NONCE[i0].NONCE.load_next) begin
+                field_storage.SHA512_GEN_PCR_HASH_NONCE[i0].NONCE.value <= field_combo.SHA512_GEN_PCR_HASH_NONCE[i0].NONCE.next;
+            end
         end
+        assign hwif_out.SHA512_GEN_PCR_HASH_NONCE[i0].NONCE.value = field_storage.SHA512_GEN_PCR_HASH_NONCE[i0].NONCE.value;
     end
-    assign hwif_out.SHA512_GEN_PCR_HASH_NONCE.NONCE.value = field_storage.SHA512_GEN_PCR_HASH_NONCE.NONCE.value;
     // Field: sha512_reg.SHA512_GEN_PCR_HASH_CTRL.START
     always_comb begin
         automatic logic [0:0] next_c = field_storage.SHA512_GEN_PCR_HASH_CTRL.START.value;
@@ -1987,8 +1935,8 @@ module sha512_reg (
     for(genvar i0=0; i0<2; i0++) begin
         assign readback_array[i0*1 + 2][31:0] = (decoded_reg_strb.SHA512_VERSION[i0] && !decoded_req_is_wr) ? hwif_in.SHA512_VERSION[i0].VERSION.next : '0;
     end
-    assign readback_array[4][0:0] = (decoded_reg_strb.SHA512_STATUS && !decoded_req_is_wr) ? field_storage.SHA512_STATUS.READY.value : '0;
-    assign readback_array[4][1:1] = (decoded_reg_strb.SHA512_STATUS && !decoded_req_is_wr) ? field_storage.SHA512_STATUS.VALID.value : '0;
+    assign readback_array[4][0:0] = (decoded_reg_strb.SHA512_STATUS && !decoded_req_is_wr) ? hwif_in.SHA512_STATUS.READY.next : '0;
+    assign readback_array[4][1:1] = (decoded_reg_strb.SHA512_STATUS && !decoded_req_is_wr) ? hwif_in.SHA512_STATUS.VALID.next : '0;
     assign readback_array[4][31:2] = '0;
     for(genvar i0=0; i0<16; i0++) begin
         assign readback_array[i0*1 + 5][31:0] = (decoded_reg_strb.SHA512_DIGEST[i0] && !decoded_req_is_wr) ? field_storage.SHA512_DIGEST[i0].DIGEST.value : '0;
diff --git a/src/sha512/rtl/sha512_reg_pkg.sv b/src/sha512/rtl/sha512_reg_pkg.sv
index 8038ef5a3..6d2cfe3a6 100644
--- a/src/sha512/rtl/sha512_reg_pkg.sv
+++ b/src/sha512/rtl/sha512_reg_pkg.sv
@@ -199,19 +199,6 @@ package sha512_reg_pkg;
         sha512_reg__SHA512_CTRL__LAST__out_t LAST;
     } sha512_reg__SHA512_CTRL__out_t;
 
-    typedef struct packed{
-        logic value;
-    } sha512_reg__SHA512_STATUS__READY__out_t;
-
-    typedef struct packed{
-        logic value;
-    } sha512_reg__SHA512_STATUS__VALID__out_t;
-
-    typedef struct packed{
-        sha512_reg__SHA512_STATUS__READY__out_t READY;
-        sha512_reg__SHA512_STATUS__VALID__out_t VALID;
-    } sha512_reg__SHA512_STATUS__out_t;
-
     typedef struct packed{
         logic [31:0] value;
     } sha512_reg__SHA512_BLOCK__BLOCK__out_t;
@@ -327,11 +314,10 @@ package sha512_reg_pkg;
 
     typedef struct packed{
         sha512_reg__SHA512_CTRL__out_t SHA512_CTRL;
-        sha512_reg__SHA512_STATUS__out_t SHA512_STATUS;
         sha512_reg__SHA512_BLOCK__out_t [32-1:0]SHA512_BLOCK;
         __kv_read_ctrl_reg__out_t SHA512_VAULT_RD_CTRL;
         __kv_write_ctrl_reg__out_t SHA512_KV_WR_CTRL;
-        sha512_reg__SHA512_GEN_PCR_HASH_NONCE__out_t SHA512_GEN_PCR_HASH_NONCE;
+        sha512_reg__SHA512_GEN_PCR_HASH_NONCE__out_t [8-1:0]SHA512_GEN_PCR_HASH_NONCE;
         sha512_reg__SHA512_GEN_PCR_HASH_CTRL__out_t SHA512_GEN_PCR_HASH_CTRL;
         sha512_reg__intr_block_t__out_t intr_block_rf;
     } sha512_reg__out_t;
diff --git a/src/sha512/rtl/sha512_reg_uvm.sv b/src/sha512/rtl/sha512_reg_uvm.sv
index 43974f339..3e6d35748 100644
--- a/src/sha512/rtl/sha512_reg_uvm.sv
+++ b/src/sha512/rtl/sha512_reg_uvm.sv
@@ -3,37 +3,79 @@
 package sha512_reg_uvm;
     `include "uvm_macros.svh"
     import uvm_pkg::*;
-    
+    `include "sha512_reg_covergroups.svh"
     // Reg - sha512_reg::SHA512_NAME
     class sha512_reg__SHA512_NAME extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_reg__SHA512_NAME_bit_cg NAME_bit_cg[32];
+        sha512_reg__SHA512_NAME_fld_cg fld_cg;
         rand uvm_reg_field NAME;
 
         function new(string name = "sha512_reg__SHA512_NAME");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.NAME = new("NAME");
             this.NAME.configure(this, 32, 0, "RO", 1, 'h0, 0, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(NAME_bit_cg[bt]) NAME_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_reg__SHA512_NAME
 
     // Reg - sha512_reg::SHA512_VERSION
     class sha512_reg__SHA512_VERSION extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_reg__SHA512_VERSION_bit_cg VERSION_bit_cg[32];
+        sha512_reg__SHA512_VERSION_fld_cg fld_cg;
         rand uvm_reg_field VERSION;
 
         function new(string name = "sha512_reg__SHA512_VERSION");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.VERSION = new("VERSION");
             this.VERSION.configure(this, 32, 0, "RO", 1, 'h0, 0, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(VERSION_bit_cg[bt]) VERSION_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_reg__SHA512_VERSION
 
     // Reg - sha512_reg::SHA512_CTRL
     class sha512_reg__SHA512_CTRL extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_reg__SHA512_CTRL_bit_cg INIT_bit_cg[1];
+        sha512_reg__SHA512_CTRL_bit_cg NEXT_bit_cg[1];
+        sha512_reg__SHA512_CTRL_bit_cg MODE_bit_cg[2];
+        sha512_reg__SHA512_CTRL_bit_cg ZEROIZE_bit_cg[1];
+        sha512_reg__SHA512_CTRL_bit_cg LAST_bit_cg[1];
+        sha512_reg__SHA512_CTRL_fld_cg fld_cg;
         rand uvm_reg_field INIT;
         rand uvm_reg_field NEXT;
         rand uvm_reg_field MODE;
@@ -41,8 +83,13 @@ package sha512_reg_uvm;
         rand uvm_reg_field LAST;
 
         function new(string name = "sha512_reg__SHA512_CTRL");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.INIT = new("INIT");
@@ -55,64 +102,137 @@ package sha512_reg_uvm;
             this.ZEROIZE.configure(this, 1, 4, "WO", 0, 'h0, 1, 1, 0);
             this.LAST = new("LAST");
             this.LAST.configure(this, 1, 5, "WO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(INIT_bit_cg[bt]) INIT_bit_cg[bt] = new();
+                foreach(NEXT_bit_cg[bt]) NEXT_bit_cg[bt] = new();
+                foreach(MODE_bit_cg[bt]) MODE_bit_cg[bt] = new();
+                foreach(ZEROIZE_bit_cg[bt]) ZEROIZE_bit_cg[bt] = new();
+                foreach(LAST_bit_cg[bt]) LAST_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_reg__SHA512_CTRL
 
     // Reg - sha512_reg::SHA512_STATUS
     class sha512_reg__SHA512_STATUS extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_reg__SHA512_STATUS_bit_cg READY_bit_cg[1];
+        sha512_reg__SHA512_STATUS_bit_cg VALID_bit_cg[1];
+        sha512_reg__SHA512_STATUS_fld_cg fld_cg;
         rand uvm_reg_field READY;
         rand uvm_reg_field VALID;
 
         function new(string name = "sha512_reg__SHA512_STATUS");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.READY = new("READY");
             this.READY.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
             this.VALID = new("VALID");
             this.VALID.configure(this, 1, 1, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(READY_bit_cg[bt]) READY_bit_cg[bt] = new();
+                foreach(VALID_bit_cg[bt]) VALID_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_reg__SHA512_STATUS
 
     // Reg - sha512_reg::SHA512_BLOCK
     class sha512_reg__SHA512_BLOCK extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_reg__SHA512_BLOCK_bit_cg BLOCK_bit_cg[32];
+        sha512_reg__SHA512_BLOCK_fld_cg fld_cg;
         rand uvm_reg_field BLOCK;
 
         function new(string name = "sha512_reg__SHA512_BLOCK");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.BLOCK = new("BLOCK");
             this.BLOCK.configure(this, 32, 0, "WO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(BLOCK_bit_cg[bt]) BLOCK_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_reg__SHA512_BLOCK
 
     // Reg - sha512_reg::SHA512_DIGEST
     class sha512_reg__SHA512_DIGEST extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_reg__SHA512_DIGEST_bit_cg DIGEST_bit_cg[32];
+        sha512_reg__SHA512_DIGEST_fld_cg fld_cg;
         rand uvm_reg_field DIGEST;
 
         function new(string name = "sha512_reg__SHA512_DIGEST");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.DIGEST = new("DIGEST");
             this.DIGEST.configure(this, 32, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(DIGEST_bit_cg[bt]) DIGEST_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_reg__SHA512_DIGEST
 
     // Reg - kv_read_ctrl_reg
     class kv_read_ctrl_reg extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        kv_read_ctrl_reg_bit_cg read_en_bit_cg[1];
+        kv_read_ctrl_reg_bit_cg read_entry_bit_cg[5];
+        kv_read_ctrl_reg_bit_cg pcr_hash_extend_bit_cg[1];
+        kv_read_ctrl_reg_bit_cg rsvd_bit_cg[25];
+        kv_read_ctrl_reg_fld_cg fld_cg;
         rand uvm_reg_field read_en;
         rand uvm_reg_field read_entry;
         rand uvm_reg_field pcr_hash_extend;
         rand uvm_reg_field rsvd;
 
         function new(string name = "kv_read_ctrl_reg");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.read_en = new("read_en");
@@ -123,18 +243,39 @@ package sha512_reg_uvm;
             this.pcr_hash_extend.configure(this, 1, 6, "RW", 0, 'h0, 1, 1, 0);
             this.rsvd = new("rsvd");
             this.rsvd.configure(this, 25, 7, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(read_en_bit_cg[bt]) read_en_bit_cg[bt] = new();
+                foreach(read_entry_bit_cg[bt]) read_entry_bit_cg[bt] = new();
+                foreach(pcr_hash_extend_bit_cg[bt]) pcr_hash_extend_bit_cg[bt] = new();
+                foreach(rsvd_bit_cg[bt]) rsvd_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : kv_read_ctrl_reg
 
     // Reg - kv_status_reg
     class kv_status_reg extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        kv_status_reg_bit_cg READY_bit_cg[1];
+        kv_status_reg_bit_cg VALID_bit_cg[1];
+        kv_status_reg_bit_cg ERROR_bit_cg[8];
+        kv_status_reg_fld_cg fld_cg;
         rand uvm_reg_field READY;
         rand uvm_reg_field VALID;
         rand uvm_reg_field ERROR;
 
         function new(string name = "kv_status_reg");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.READY = new("READY");
@@ -143,11 +284,31 @@ package sha512_reg_uvm;
             this.VALID.configure(this, 1, 1, "RO", 1, 'h0, 1, 1, 0);
             this.ERROR = new("ERROR");
             this.ERROR.configure(this, 8, 2, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(READY_bit_cg[bt]) READY_bit_cg[bt] = new();
+                foreach(VALID_bit_cg[bt]) VALID_bit_cg[bt] = new();
+                foreach(ERROR_bit_cg[bt]) ERROR_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : kv_status_reg
 
     // Reg - kv_write_ctrl_reg
     class kv_write_ctrl_reg extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        kv_write_ctrl_reg_bit_cg write_en_bit_cg[1];
+        kv_write_ctrl_reg_bit_cg write_entry_bit_cg[5];
+        kv_write_ctrl_reg_bit_cg hmac_key_dest_valid_bit_cg[1];
+        kv_write_ctrl_reg_bit_cg hmac_block_dest_valid_bit_cg[1];
+        kv_write_ctrl_reg_bit_cg sha_block_dest_valid_bit_cg[1];
+        kv_write_ctrl_reg_bit_cg ecc_pkey_dest_valid_bit_cg[1];
+        kv_write_ctrl_reg_bit_cg ecc_seed_dest_valid_bit_cg[1];
+        kv_write_ctrl_reg_bit_cg rsvd_bit_cg[21];
+        kv_write_ctrl_reg_fld_cg fld_cg;
         rand uvm_reg_field write_en;
         rand uvm_reg_field write_entry;
         rand uvm_reg_field hmac_key_dest_valid;
@@ -158,8 +319,13 @@ package sha512_reg_uvm;
         rand uvm_reg_field rsvd;
 
         function new(string name = "kv_write_ctrl_reg");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.write_en = new("write_en");
@@ -178,95 +344,205 @@ package sha512_reg_uvm;
             this.ecc_seed_dest_valid.configure(this, 1, 10, "RW", 0, 'h0, 1, 1, 0);
             this.rsvd = new("rsvd");
             this.rsvd.configure(this, 21, 11, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(write_en_bit_cg[bt]) write_en_bit_cg[bt] = new();
+                foreach(write_entry_bit_cg[bt]) write_entry_bit_cg[bt] = new();
+                foreach(hmac_key_dest_valid_bit_cg[bt]) hmac_key_dest_valid_bit_cg[bt] = new();
+                foreach(hmac_block_dest_valid_bit_cg[bt]) hmac_block_dest_valid_bit_cg[bt] = new();
+                foreach(sha_block_dest_valid_bit_cg[bt]) sha_block_dest_valid_bit_cg[bt] = new();
+                foreach(ecc_pkey_dest_valid_bit_cg[bt]) ecc_pkey_dest_valid_bit_cg[bt] = new();
+                foreach(ecc_seed_dest_valid_bit_cg[bt]) ecc_seed_dest_valid_bit_cg[bt] = new();
+                foreach(rsvd_bit_cg[bt]) rsvd_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : kv_write_ctrl_reg
 
     // Reg - sha512_reg::SHA512_GEN_PCR_HASH_NONCE
     class sha512_reg__SHA512_GEN_PCR_HASH_NONCE extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_reg__SHA512_GEN_PCR_HASH_NONCE_bit_cg NONCE_bit_cg[32];
+        sha512_reg__SHA512_GEN_PCR_HASH_NONCE_fld_cg fld_cg;
         rand uvm_reg_field NONCE;
 
         function new(string name = "sha512_reg__SHA512_GEN_PCR_HASH_NONCE");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.NONCE = new("NONCE");
             this.NONCE.configure(this, 32, 0, "WO", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(NONCE_bit_cg[bt]) NONCE_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_reg__SHA512_GEN_PCR_HASH_NONCE
 
     // Reg - sha512_reg::SHA512_GEN_PCR_HASH_CTRL
     class sha512_reg__SHA512_GEN_PCR_HASH_CTRL extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_reg__SHA512_GEN_PCR_HASH_CTRL_bit_cg START_bit_cg[1];
+        sha512_reg__SHA512_GEN_PCR_HASH_CTRL_fld_cg fld_cg;
         rand uvm_reg_field START;
 
         function new(string name = "sha512_reg__SHA512_GEN_PCR_HASH_CTRL");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.START = new("START");
             this.START.configure(this, 1, 0, "WO", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(START_bit_cg[bt]) START_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_reg__SHA512_GEN_PCR_HASH_CTRL
 
     // Reg - sha512_reg::SHA512_GEN_PCR_HASH_STATUS
     class sha512_reg__SHA512_GEN_PCR_HASH_STATUS extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_reg__SHA512_GEN_PCR_HASH_STATUS_bit_cg READY_bit_cg[1];
+        sha512_reg__SHA512_GEN_PCR_HASH_STATUS_bit_cg VALID_bit_cg[1];
+        sha512_reg__SHA512_GEN_PCR_HASH_STATUS_fld_cg fld_cg;
         rand uvm_reg_field READY;
         rand uvm_reg_field VALID;
 
         function new(string name = "sha512_reg__SHA512_GEN_PCR_HASH_STATUS");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.READY = new("READY");
             this.READY.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
             this.VALID = new("VALID");
             this.VALID.configure(this, 1, 1, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(READY_bit_cg[bt]) READY_bit_cg[bt] = new();
+                foreach(VALID_bit_cg[bt]) VALID_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_reg__SHA512_GEN_PCR_HASH_STATUS
 
     // Reg - sha512_reg::SHA512_GEN_PCR_HASH_DIGEST
     class sha512_reg__SHA512_GEN_PCR_HASH_DIGEST extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_reg__SHA512_GEN_PCR_HASH_DIGEST_bit_cg DIGEST_bit_cg[32];
+        sha512_reg__SHA512_GEN_PCR_HASH_DIGEST_fld_cg fld_cg;
         rand uvm_reg_field DIGEST;
 
         function new(string name = "sha512_reg__SHA512_GEN_PCR_HASH_DIGEST");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.DIGEST = new("DIGEST");
             this.DIGEST.configure(this, 32, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(DIGEST_bit_cg[bt]) DIGEST_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_reg__SHA512_GEN_PCR_HASH_DIGEST
 
     // Reg - sha512_reg::global_intr_en_t
     class sha512_reg__global_intr_en_t extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_reg__global_intr_en_t_bit_cg error_en_bit_cg[1];
+        sha512_reg__global_intr_en_t_bit_cg notif_en_bit_cg[1];
+        sha512_reg__global_intr_en_t_fld_cg fld_cg;
         rand uvm_reg_field error_en;
         rand uvm_reg_field notif_en;
 
         function new(string name = "sha512_reg__global_intr_en_t");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.error_en = new("error_en");
             this.error_en.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
             this.notif_en = new("notif_en");
             this.notif_en.configure(this, 1, 1, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(error_en_bit_cg[bt]) error_en_bit_cg[bt] = new();
+                foreach(notif_en_bit_cg[bt]) notif_en_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_reg__global_intr_en_t
 
     // Reg - sha512_reg::error_intr_en_t
     class sha512_reg__error_intr_en_t extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_reg__error_intr_en_t_bit_cg error0_en_bit_cg[1];
+        sha512_reg__error_intr_en_t_bit_cg error1_en_bit_cg[1];
+        sha512_reg__error_intr_en_t_bit_cg error2_en_bit_cg[1];
+        sha512_reg__error_intr_en_t_bit_cg error3_en_bit_cg[1];
+        sha512_reg__error_intr_en_t_fld_cg fld_cg;
         rand uvm_reg_field error0_en;
         rand uvm_reg_field error1_en;
         rand uvm_reg_field error2_en;
         rand uvm_reg_field error3_en;
 
         function new(string name = "sha512_reg__error_intr_en_t");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.error0_en = new("error0_en");
@@ -277,61 +553,131 @@ package sha512_reg_uvm;
             this.error2_en.configure(this, 1, 2, "RW", 0, 'h0, 1, 1, 0);
             this.error3_en = new("error3_en");
             this.error3_en.configure(this, 1, 3, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(error0_en_bit_cg[bt]) error0_en_bit_cg[bt] = new();
+                foreach(error1_en_bit_cg[bt]) error1_en_bit_cg[bt] = new();
+                foreach(error2_en_bit_cg[bt]) error2_en_bit_cg[bt] = new();
+                foreach(error3_en_bit_cg[bt]) error3_en_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_reg__error_intr_en_t
 
     // Reg - sha512_reg::notif_intr_en_t
     class sha512_reg__notif_intr_en_t extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_reg__notif_intr_en_t_bit_cg notif_cmd_done_en_bit_cg[1];
+        sha512_reg__notif_intr_en_t_fld_cg fld_cg;
         rand uvm_reg_field notif_cmd_done_en;
 
         function new(string name = "sha512_reg__notif_intr_en_t");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.notif_cmd_done_en = new("notif_cmd_done_en");
             this.notif_cmd_done_en.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(notif_cmd_done_en_bit_cg[bt]) notif_cmd_done_en_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_reg__notif_intr_en_t
 
     // Reg - sha512_reg::global_intr_t_agg_sts_dd3dcf0a
     class sha512_reg__global_intr_t_agg_sts_dd3dcf0a extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_reg__global_intr_t_agg_sts_dd3dcf0a_bit_cg agg_sts_bit_cg[1];
+        sha512_reg__global_intr_t_agg_sts_dd3dcf0a_fld_cg fld_cg;
         rand uvm_reg_field agg_sts;
 
         function new(string name = "sha512_reg__global_intr_t_agg_sts_dd3dcf0a");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.agg_sts = new("agg_sts");
             this.agg_sts.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(agg_sts_bit_cg[bt]) agg_sts_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_reg__global_intr_t_agg_sts_dd3dcf0a
 
     // Reg - sha512_reg::global_intr_t_agg_sts_e6399b4a
     class sha512_reg__global_intr_t_agg_sts_e6399b4a extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_reg__global_intr_t_agg_sts_e6399b4a_bit_cg agg_sts_bit_cg[1];
+        sha512_reg__global_intr_t_agg_sts_e6399b4a_fld_cg fld_cg;
         rand uvm_reg_field agg_sts;
 
         function new(string name = "sha512_reg__global_intr_t_agg_sts_e6399b4a");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.agg_sts = new("agg_sts");
             this.agg_sts.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(agg_sts_bit_cg[bt]) agg_sts_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_reg__global_intr_t_agg_sts_e6399b4a
 
     // Reg - sha512_reg::error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378
     class sha512_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378_bit_cg error0_sts_bit_cg[1];
+        sha512_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378_bit_cg error1_sts_bit_cg[1];
+        sha512_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378_bit_cg error2_sts_bit_cg[1];
+        sha512_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378_bit_cg error3_sts_bit_cg[1];
+        sha512_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378_fld_cg fld_cg;
         rand uvm_reg_field error0_sts;
         rand uvm_reg_field error1_sts;
         rand uvm_reg_field error2_sts;
         rand uvm_reg_field error3_sts;
 
         function new(string name = "sha512_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.error0_sts = new("error0_sts");
@@ -342,33 +688,71 @@ package sha512_reg_uvm;
             this.error2_sts.configure(this, 1, 2, "W1C", 1, 'h0, 1, 1, 0);
             this.error3_sts = new("error3_sts");
             this.error3_sts.configure(this, 1, 3, "W1C", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(error0_sts_bit_cg[bt]) error0_sts_bit_cg[bt] = new();
+                foreach(error1_sts_bit_cg[bt]) error1_sts_bit_cg[bt] = new();
+                foreach(error2_sts_bit_cg[bt]) error2_sts_bit_cg[bt] = new();
+                foreach(error3_sts_bit_cg[bt]) error3_sts_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378
 
     // Reg - sha512_reg::notif_intr_t_notif_cmd_done_sts_1c68637e
     class sha512_reg__notif_intr_t_notif_cmd_done_sts_1c68637e extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_reg__notif_intr_t_notif_cmd_done_sts_1c68637e_bit_cg notif_cmd_done_sts_bit_cg[1];
+        sha512_reg__notif_intr_t_notif_cmd_done_sts_1c68637e_fld_cg fld_cg;
         rand uvm_reg_field notif_cmd_done_sts;
 
         function new(string name = "sha512_reg__notif_intr_t_notif_cmd_done_sts_1c68637e");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.notif_cmd_done_sts = new("notif_cmd_done_sts");
             this.notif_cmd_done_sts.configure(this, 1, 0, "W1C", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(notif_cmd_done_sts_bit_cg[bt]) notif_cmd_done_sts_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_reg__notif_intr_t_notif_cmd_done_sts_1c68637e
 
     // Reg - sha512_reg::error_intr_trig_t
     class sha512_reg__error_intr_trig_t extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_reg__error_intr_trig_t_bit_cg error0_trig_bit_cg[1];
+        sha512_reg__error_intr_trig_t_bit_cg error1_trig_bit_cg[1];
+        sha512_reg__error_intr_trig_t_bit_cg error2_trig_bit_cg[1];
+        sha512_reg__error_intr_trig_t_bit_cg error3_trig_bit_cg[1];
+        sha512_reg__error_intr_trig_t_fld_cg fld_cg;
         rand uvm_reg_field error0_trig;
         rand uvm_reg_field error1_trig;
         rand uvm_reg_field error2_trig;
         rand uvm_reg_field error3_trig;
 
         function new(string name = "sha512_reg__error_intr_trig_t");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.error0_trig = new("error0_trig");
@@ -379,160 +763,344 @@ package sha512_reg_uvm;
             this.error2_trig.configure(this, 1, 2, "W1S", 0, 'h0, 1, 1, 0);
             this.error3_trig = new("error3_trig");
             this.error3_trig.configure(this, 1, 3, "W1S", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(error0_trig_bit_cg[bt]) error0_trig_bit_cg[bt] = new();
+                foreach(error1_trig_bit_cg[bt]) error1_trig_bit_cg[bt] = new();
+                foreach(error2_trig_bit_cg[bt]) error2_trig_bit_cg[bt] = new();
+                foreach(error3_trig_bit_cg[bt]) error3_trig_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_reg__error_intr_trig_t
 
     // Reg - sha512_reg::notif_intr_trig_t
     class sha512_reg__notif_intr_trig_t extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_reg__notif_intr_trig_t_bit_cg notif_cmd_done_trig_bit_cg[1];
+        sha512_reg__notif_intr_trig_t_fld_cg fld_cg;
         rand uvm_reg_field notif_cmd_done_trig;
 
         function new(string name = "sha512_reg__notif_intr_trig_t");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.notif_cmd_done_trig = new("notif_cmd_done_trig");
             this.notif_cmd_done_trig.configure(this, 1, 0, "W1S", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(notif_cmd_done_trig_bit_cg[bt]) notif_cmd_done_trig_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_reg__notif_intr_trig_t
 
     // Reg - sha512_reg::intr_count_t_cnt_35ace267
     class sha512_reg__intr_count_t_cnt_35ace267 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_reg__intr_count_t_cnt_35ace267_bit_cg cnt_bit_cg[32];
+        sha512_reg__intr_count_t_cnt_35ace267_fld_cg fld_cg;
         rand uvm_reg_field cnt;
 
         function new(string name = "sha512_reg__intr_count_t_cnt_35ace267");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.cnt = new("cnt");
             this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_reg__intr_count_t_cnt_35ace267
 
     // Reg - sha512_reg::intr_count_t_cnt_73c42c28
     class sha512_reg__intr_count_t_cnt_73c42c28 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_reg__intr_count_t_cnt_73c42c28_bit_cg cnt_bit_cg[32];
+        sha512_reg__intr_count_t_cnt_73c42c28_fld_cg fld_cg;
         rand uvm_reg_field cnt;
 
         function new(string name = "sha512_reg__intr_count_t_cnt_73c42c28");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.cnt = new("cnt");
             this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_reg__intr_count_t_cnt_73c42c28
 
     // Reg - sha512_reg::intr_count_t_cnt_d8af96ff
     class sha512_reg__intr_count_t_cnt_d8af96ff extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_reg__intr_count_t_cnt_d8af96ff_bit_cg cnt_bit_cg[32];
+        sha512_reg__intr_count_t_cnt_d8af96ff_fld_cg fld_cg;
         rand uvm_reg_field cnt;
 
         function new(string name = "sha512_reg__intr_count_t_cnt_d8af96ff");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.cnt = new("cnt");
             this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_reg__intr_count_t_cnt_d8af96ff
 
     // Reg - sha512_reg::intr_count_t_cnt_9bd7f809
     class sha512_reg__intr_count_t_cnt_9bd7f809 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_reg__intr_count_t_cnt_9bd7f809_bit_cg cnt_bit_cg[32];
+        sha512_reg__intr_count_t_cnt_9bd7f809_fld_cg fld_cg;
         rand uvm_reg_field cnt;
 
         function new(string name = "sha512_reg__intr_count_t_cnt_9bd7f809");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.cnt = new("cnt");
             this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_reg__intr_count_t_cnt_9bd7f809
 
     // Reg - sha512_reg::intr_count_t_cnt_be67d6d5
     class sha512_reg__intr_count_t_cnt_be67d6d5 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_reg__intr_count_t_cnt_be67d6d5_bit_cg cnt_bit_cg[32];
+        sha512_reg__intr_count_t_cnt_be67d6d5_fld_cg fld_cg;
         rand uvm_reg_field cnt;
 
         function new(string name = "sha512_reg__intr_count_t_cnt_be67d6d5");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.cnt = new("cnt");
             this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_reg__intr_count_t_cnt_be67d6d5
 
     // Reg - sha512_reg::intr_count_incr_t_pulse_37026c97
     class sha512_reg__intr_count_incr_t_pulse_37026c97 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_reg__intr_count_incr_t_pulse_37026c97_bit_cg pulse_bit_cg[1];
+        sha512_reg__intr_count_incr_t_pulse_37026c97_fld_cg fld_cg;
         rand uvm_reg_field pulse;
 
         function new(string name = "sha512_reg__intr_count_incr_t_pulse_37026c97");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.pulse = new("pulse");
             this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_reg__intr_count_incr_t_pulse_37026c97
 
     // Reg - sha512_reg::intr_count_incr_t_pulse_d860d977
     class sha512_reg__intr_count_incr_t_pulse_d860d977 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_reg__intr_count_incr_t_pulse_d860d977_bit_cg pulse_bit_cg[1];
+        sha512_reg__intr_count_incr_t_pulse_d860d977_fld_cg fld_cg;
         rand uvm_reg_field pulse;
 
         function new(string name = "sha512_reg__intr_count_incr_t_pulse_d860d977");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.pulse = new("pulse");
             this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_reg__intr_count_incr_t_pulse_d860d977
 
     // Reg - sha512_reg::intr_count_incr_t_pulse_87b45fe7
     class sha512_reg__intr_count_incr_t_pulse_87b45fe7 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_reg__intr_count_incr_t_pulse_87b45fe7_bit_cg pulse_bit_cg[1];
+        sha512_reg__intr_count_incr_t_pulse_87b45fe7_fld_cg fld_cg;
         rand uvm_reg_field pulse;
 
         function new(string name = "sha512_reg__intr_count_incr_t_pulse_87b45fe7");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.pulse = new("pulse");
             this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_reg__intr_count_incr_t_pulse_87b45fe7
 
     // Reg - sha512_reg::intr_count_incr_t_pulse_c1689ee6
     class sha512_reg__intr_count_incr_t_pulse_c1689ee6 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_reg__intr_count_incr_t_pulse_c1689ee6_bit_cg pulse_bit_cg[1];
+        sha512_reg__intr_count_incr_t_pulse_c1689ee6_fld_cg fld_cg;
         rand uvm_reg_field pulse;
 
         function new(string name = "sha512_reg__intr_count_incr_t_pulse_c1689ee6");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.pulse = new("pulse");
             this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_reg__intr_count_incr_t_pulse_c1689ee6
 
     // Reg - sha512_reg::intr_count_incr_t_pulse_6173128e
     class sha512_reg__intr_count_incr_t_pulse_6173128e extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_reg__intr_count_incr_t_pulse_6173128e_bit_cg pulse_bit_cg[1];
+        sha512_reg__intr_count_incr_t_pulse_6173128e_fld_cg fld_cg;
         rand uvm_reg_field pulse;
 
         function new(string name = "sha512_reg__intr_count_incr_t_pulse_6173128e");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.pulse = new("pulse");
             this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_reg__intr_count_incr_t_pulse_6173128e
 
@@ -674,7 +1242,7 @@ package sha512_reg_uvm;
         rand kv_status_reg SHA512_VAULT_RD_STATUS;
         rand kv_write_ctrl_reg SHA512_KV_WR_CTRL;
         rand kv_status_reg SHA512_KV_WR_STATUS;
-        rand sha512_reg__SHA512_GEN_PCR_HASH_NONCE SHA512_GEN_PCR_HASH_NONCE;
+        rand sha512_reg__SHA512_GEN_PCR_HASH_NONCE SHA512_GEN_PCR_HASH_NONCE[8];
         rand sha512_reg__SHA512_GEN_PCR_HASH_CTRL SHA512_GEN_PCR_HASH_CTRL;
         rand sha512_reg__SHA512_GEN_PCR_HASH_STATUS SHA512_GEN_PCR_HASH_STATUS;
         rand sha512_reg__SHA512_GEN_PCR_HASH_DIGEST SHA512_GEN_PCR_HASH_DIGEST[12];
@@ -744,27 +1312,29 @@ package sha512_reg_uvm;
 
             this.SHA512_KV_WR_STATUS.build();
             this.default_map.add_reg(this.SHA512_KV_WR_STATUS, 'h60c);
-            this.SHA512_GEN_PCR_HASH_NONCE = new("SHA512_GEN_PCR_HASH_NONCE");
-            this.SHA512_GEN_PCR_HASH_NONCE.configure(this);
-
-            this.SHA512_GEN_PCR_HASH_NONCE.build();
-            this.default_map.add_reg(this.SHA512_GEN_PCR_HASH_NONCE, 'h610);
+            foreach(this.SHA512_GEN_PCR_HASH_NONCE[i0]) begin
+                this.SHA512_GEN_PCR_HASH_NONCE[i0] = new($sformatf("SHA512_GEN_PCR_HASH_NONCE[%0d]", i0));
+                this.SHA512_GEN_PCR_HASH_NONCE[i0].configure(this);
+                
+                this.SHA512_GEN_PCR_HASH_NONCE[i0].build();
+                this.default_map.add_reg(this.SHA512_GEN_PCR_HASH_NONCE[i0], 'h610 + i0*'h4);
+            end
             this.SHA512_GEN_PCR_HASH_CTRL = new("SHA512_GEN_PCR_HASH_CTRL");
             this.SHA512_GEN_PCR_HASH_CTRL.configure(this);
 
             this.SHA512_GEN_PCR_HASH_CTRL.build();
-            this.default_map.add_reg(this.SHA512_GEN_PCR_HASH_CTRL, 'h614);
+            this.default_map.add_reg(this.SHA512_GEN_PCR_HASH_CTRL, 'h630);
             this.SHA512_GEN_PCR_HASH_STATUS = new("SHA512_GEN_PCR_HASH_STATUS");
             this.SHA512_GEN_PCR_HASH_STATUS.configure(this);
 
             this.SHA512_GEN_PCR_HASH_STATUS.build();
-            this.default_map.add_reg(this.SHA512_GEN_PCR_HASH_STATUS, 'h618);
+            this.default_map.add_reg(this.SHA512_GEN_PCR_HASH_STATUS, 'h634);
             foreach(this.SHA512_GEN_PCR_HASH_DIGEST[i0]) begin
                 this.SHA512_GEN_PCR_HASH_DIGEST[i0] = new($sformatf("SHA512_GEN_PCR_HASH_DIGEST[%0d]", i0));
                 this.SHA512_GEN_PCR_HASH_DIGEST[i0].configure(this);
                 
                 this.SHA512_GEN_PCR_HASH_DIGEST[i0].build();
-                this.default_map.add_reg(this.SHA512_GEN_PCR_HASH_DIGEST[i0], 'h61c + i0*'h4);
+                this.default_map.add_reg(this.SHA512_GEN_PCR_HASH_DIGEST[i0], 'h638 + i0*'h4);
             end
             this.intr_block_rf = new("intr_block_rf");
             this.intr_block_rf.configure(this);
@@ -773,4 +1343,5 @@ package sha512_reg_uvm;
         endfunction : build
     endclass : sha512_reg
 
+    `include "sha512_reg_sample.svh"
 endpackage: sha512_reg_uvm
diff --git a/src/sha512/tb/sha512_ctrl_32bit_tb.sv b/src/sha512/tb/sha512_ctrl_32bit_tb.sv
index cc212f031..adc8ddc1e 100644
--- a/src/sha512/tb/sha512_ctrl_32bit_tb.sv
+++ b/src/sha512/tb/sha512_ctrl_32bit_tb.sv
@@ -160,6 +160,9 @@ module sha512_ctrl_32bit_tb
   reg [31 : 0]  read_data;
   reg [511 : 0] digest_data;
 
+  //bind coverage file
+  sha512_ctrl_cov_bind i_sha512_ctrl_cov_bind();
+
   //----------------------------------------------------------------
   // Device Under Test.
   //----------------------------------------------------------------
@@ -195,7 +198,8 @@ module sha512_ctrl_32bit_tb
              .pv_wr_resp(pv_wr_resp_tb),
 
              .error_intr(error_intr_tb),
-             .notif_intr(notif_intr_tb)
+             .notif_intr(notif_intr_tb),
+             .debugUnlock_or_scan_mode_switch('0)
             );
 
   //----------------------------------------------------------------
@@ -564,6 +568,8 @@ module sha512_ctrl_32bit_tb
       end_time = cycle_ctr - start_time;
       $display("*** Single block test processing time = %01d cycles", end_time);
 
+      write_single_word(ADDR_CTRL, {27'h0, 1'b1, 4'b0}); //zeroize
+
       mask = get_mask(mode);
       masked_data = digest_data & mask;
 
@@ -651,7 +657,8 @@ module sha512_ctrl_32bit_tb
       $display("*** Double block test processing time = %01d cycles", end_time);
       read_digest();
 
-      
+      write_single_word(ADDR_CTRL, {27'h0, 1'b1, 4'b0}); //zeroize
+
       masked_data1 = digest_data & mask;
 
       if (masked_data1 == expected1)
@@ -736,6 +743,203 @@ module sha512_ctrl_32bit_tb
   endtask // double_block_test
 
 
+  //----------------------------------------------------------------
+  // continuous_cmd_test()
+  //
+  //
+  // Perform test of a double block digest.
+  //----------------------------------------------------------------
+  task continuous_cmd_test(input [7 : 0]    tc_number,
+                         input [1 : 0]    mode,
+                         input [1023 : 0] block0,
+                         input [1023 : 0] block1,
+                         input [511 : 0]  expected
+                        );
+    reg [511 : 0] mask;
+    reg [511 : 0] masked_data;
+    reg [31 : 0] start_time;
+    reg [31 : 0] end_time;
+
+    begin
+      $display("*** TC%01d - continuous command test started.", tc_ctr);
+
+      // First block
+      write_block(block0);
+      write_single_word(ADDR_CTRL, {28'h0, mode, CTRL_INIT_VALUE});
+      start_time = cycle_ctr;
+      #CLK_PERIOD;
+      hsel_i_tb       = 0;
+
+      #(CLK_PERIOD);
+
+      for (int i=0; i<10; i++)
+        begin
+          write_single_word(ADDR_CTRL, {28'h0, mode, CTRL_INIT_VALUE});
+          #CLK_PERIOD;
+          write_single_word(ADDR_CTRL, {28'h0, mode, CTRL_NEXT_VALUE});
+          #CLK_PERIOD;
+        end
+
+      wait_ready();
+
+      write_block(block1);
+
+      // Final block
+      write_single_word(ADDR_CTRL, {28'h0, mode, CTRL_NEXT_VALUE});
+      #CLK_PERIOD;
+      hsel_i_tb       = 0;
+
+      #(CLK_PERIOD);
+
+      for (int i=0; i<10; i++)
+        begin
+          write_single_word(ADDR_CTRL, {28'h0, mode, CTRL_INIT_VALUE});
+          #CLK_PERIOD;
+          write_single_word(ADDR_CTRL, {28'h0, mode, CTRL_NEXT_VALUE});
+          #CLK_PERIOD;
+        end
+
+      wait_ready();
+
+      end_time = cycle_ctr - start_time;
+      $display("*** Continuous command test processing time = %01d cycles", end_time);
+      read_digest();
+
+      mask = get_mask(mode);
+      masked_data = digest_data & mask;
+
+      if (masked_data == expected)
+        begin
+          $display("TC%01d final block: OK.", tc_ctr);
+        end
+      else
+        begin
+          $display("TC%01d: ERROR in final digest", tc_ctr);
+          $display("TC%01d: Expected: 0x%0128x", tc_ctr, expected);
+          $display("TC%01d: Got:      0x%0128x", tc_ctr, masked_data);
+          error_ctr = error_ctr + 1;
+        end
+
+      $display("*** TC%01d - Continuous command test done.", tc_ctr);
+      tc_ctr = tc_ctr + 1;
+    end
+  endtask // continuous_cmd_test
+
+
+  //----------------------------------------------------------------
+  // zeroize_test()
+  //
+  //----------------------------------------------------------------
+  task zeroize_test(input [7 : 0]    tc_number,
+                    input [1 : 0]    mode,
+                    input [1023 : 0] block0,
+                    input [1023 : 0] block1,
+                    input [511 : 0]  expected
+                  );
+    begin
+
+      $display("*** TC%01d - zeroize test started.", tc_ctr);
+
+      // First test: assert zeroize when engine is working 
+      write_block(block0);
+
+      write_single_word(ADDR_CTRL, {27'h0, 1'b0, mode, CTRL_INIT_VALUE});
+      #(10 * CLK_PERIOD);
+
+      write_single_word(ADDR_CTRL, {27'h0, 1'b1, 4'b0}); //zeroize
+      #CLK_PERIOD;
+      hsel_i_tb       = 0;
+
+      wait_ready();
+      read_digest();
+      if (digest_data == 0)
+        begin
+          $display("TC%01d final block: OK.", tc_ctr);
+        end
+      else
+        begin
+          $display("TC%01d: ERROR in final digest", tc_ctr);
+          $display("TC%01d: Expected: 0x%128x", tc_ctr, 0);
+          $display("TC%01d: Got:      0x%128x", tc_ctr, digest_data);
+          error_ctr = error_ctr + 1;
+        end
+      tc_ctr = tc_ctr + 1;
+
+      // Second test: assert zeroize with INIT
+      write_block(block0);
+
+      write_single_word(ADDR_CTRL, {27'h0, 1'b1, mode, CTRL_INIT_VALUE}); //zeroize
+      #CLK_PERIOD;
+      hsel_i_tb       = 0;
+      #(CLK_PERIOD);
+
+      wait_ready();
+      read_digest();
+      if (digest_data == 0)
+        begin
+          $display("TC%01d final block: OK.", tc_ctr);
+        end
+      else
+        begin
+          $display("TC%01d: ERROR in final digest", tc_ctr);
+          $display("TC%01d: Expected: 0x%128x", tc_ctr, 0);
+          $display("TC%01d: Got:      0x%128x", tc_ctr, digest_data);
+          error_ctr = error_ctr + 1;
+        end
+      tc_ctr = tc_ctr + 1;
+
+      // Third test: assert zeroize with NEXT      
+      write_block(block0);
+
+      write_single_word(ADDR_CTRL, {27'h0, 1'b1, mode, CTRL_NEXT_VALUE}); //zeroize
+      #CLK_PERIOD;
+      hsel_i_tb       = 0;
+      #(CLK_PERIOD);
+
+      wait_ready();
+      read_digest();
+      if (digest_data == 0)
+        begin
+          $display("TC%01d final block: OK.", tc_ctr);
+        end
+      else
+        begin
+          $display("TC%01d: ERROR in final digest", tc_ctr);
+          $display("TC%01d: Expected: 0x%128x", tc_ctr, 0);
+          $display("TC%01d: Got:      0x%128x", tc_ctr, digest_data);
+          error_ctr = error_ctr + 1;
+        end
+      tc_ctr = tc_ctr + 1;
+
+      // Forth test: assert zeroize after NEXT      
+      write_block(block0);
+
+      write_single_word(ADDR_CTRL, {27'h0, 1'b0, mode, CTRL_NEXT_VALUE});
+      #(10 * CLK_PERIOD);
+
+      write_single_word(ADDR_CTRL, {27'h0, 1'b1, 4'b0}); //zeroize
+      #CLK_PERIOD;
+      hsel_i_tb       = 0;
+
+      wait_ready();
+      read_digest();
+      if (digest_data == 0)
+        begin
+          $display("TC%01d final block: OK.", tc_ctr);
+        end
+      else
+        begin
+          $display("TC%01d: ERROR in final digest", tc_ctr);
+          $display("TC%01d: Expected: 0x%128x", tc_ctr, 0);
+          $display("TC%01d: Got:      0x%128x", tc_ctr, digest_data);
+          error_ctr = error_ctr + 1;
+        end
+
+      $display("*** TC%01d - zeroize test done.", tc_ctr);
+      tc_ctr = tc_ctr + 1;
+    end
+  endtask // zeroize_test
+
   //----------------------------------------------------------------
   // sha512_test
   // The main test functionality.
@@ -815,6 +1019,10 @@ module sha512_ctrl_32bit_tb
 
       double_block_test_pipelined(8'h09, MODE_SHA_512, double_block_one, double_block_two, tc6_expected);
 
+      continuous_cmd_test(8'h0a, MODE_SHA_384, double_block_one, double_block_two, tc12_expected);
+
+      zeroize_test(8'h0b, MODE_SHA_384, double_block_one, double_block_two, tc12_expected);
+
       display_test_result();
       
       $display("   -- Testbench for sha512 done. --");
diff --git a/src/sha512/uvmf_sha512/config/compile.yml b/src/sha512/uvmf_sha512/config/compile.yml
index a6cf5f361..04c377aaa 100644
--- a/src/sha512/uvmf_sha512/config/compile.yml
+++ b/src/sha512/uvmf_sha512/config/compile.yml
@@ -4,6 +4,7 @@ schema_version: 2.4.0
 requires:
   - uvmf_lib
   - sha512_ctrl
+  - sha512_coverage
 targets:
   tb:
     directories:
diff --git a/src/sha512/uvmf_sha512/uvmf_template_output/project_benches/SHA512/tb/testbench/hdl_top.sv b/src/sha512/uvmf_sha512/uvmf_template_output/project_benches/SHA512/tb/testbench/hdl_top.sv
index 295f78d9a..bf5448523 100644
--- a/src/sha512/uvmf_sha512/uvmf_template_output/project_benches/SHA512/tb/testbench/hdl_top.sv
+++ b/src/sha512/uvmf_sha512/uvmf_template_output/project_benches/SHA512/tb/testbench/hdl_top.sv
@@ -96,7 +96,19 @@ import uvmf_base_pkg_hdl::*;
 
              .hresp_o(SHA512_out_agent_bus.hresp),
              .hreadyout_o(SHA512_out_agent_bus.hreadyout),
-             .hrdata_o(SHA512_out_agent_bus.hrdata)
+             .hrdata_o(SHA512_out_agent_bus.hrdata),
+             .kv_read   (),
+             .kv_write  (),
+             .kv_rd_resp(),
+             .kv_wr_resp(),
+             .pv_read   (),
+             .pv_write  (),
+             .pv_rd_resp(),
+             .pv_wr_resp(),
+             .pcr_signing_hash(),
+             .error_intr(),
+             .notif_intr(),
+             .debugUnlock_or_scan_mode_switch('0)
             );
   // pragma uvmf custom dut_instantiation end
 
diff --git a/src/sha512_masked/config/sha512_masked_core.vf b/src/sha512_masked/config/sha512_masked_core.vf
index 70acd2d05..e9d04af99 100644
--- a/src/sha512_masked/config/sha512_masked_core.vf
+++ b/src/sha512_masked/config/sha512_masked_core.vf
@@ -15,6 +15,7 @@ ${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
 ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_defines_pkg.sv
 ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_macros.svh
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_defines_pkg.sv
@@ -31,9 +32,9 @@ ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg.sv
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg_pkg.sv
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_params_pkg.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_ctrl.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512.sv
-${CALIPTRA_ROOT}/src/sha512/rtl/sha512_param.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_core.v
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_h_constants.v
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_k_constants.v
diff --git a/src/sha512_masked/config/sha512_masked_core_tb.vf b/src/sha512_masked/config/sha512_masked_core_tb.vf
index f0139b6d1..b9fa2a419 100644
--- a/src/sha512_masked/config/sha512_masked_core_tb.vf
+++ b/src/sha512_masked/config/sha512_masked_core_tb.vf
@@ -16,6 +16,7 @@ ${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
 ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_defines_pkg.sv
 ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_macros.svh
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_defines_pkg.sv
@@ -33,9 +34,9 @@ ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg.sv
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg_pkg.sv
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_params_pkg.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_ctrl.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512.sv
-${CALIPTRA_ROOT}/src/sha512/rtl/sha512_param.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_core.v
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_h_constants.v
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_k_constants.v
diff --git a/src/soc_ifc/.gitignore b/src/soc_ifc/.gitignore
new file mode 100644
index 000000000..dac06b307
--- /dev/null
+++ b/src/soc_ifc/.gitignore
@@ -0,0 +1,8 @@
+# This file tells git which files and/or directories to ignore in the repo
+# Read the docs here: https://git-scm.com/docs/gitignore
+
+# Explicitly ignore html docs folder after removing it
+# since it is now maintained in GitHub automatically
+docs
+
+tb/EXP
diff --git a/src/soc_ifc/config/compile.yml b/src/soc_ifc/config/compile.yml
index 06b1e056a..203ddb636 100644
--- a/src/soc_ifc/config/compile.yml
+++ b/src/soc_ifc/config/compile.yml
@@ -13,12 +13,9 @@ targets:
   tb:
     directories: 
       - $COMPILE_ROOT/rtl
-      - $COMPILE_ROOT/coverage
     files:
       - $COMPILE_ROOT/rtl/soc_ifc_pkg.sv
       - $COMPILE_ROOT/rtl/soc_ifc_reg_pkg.sv
-      - $COMPILE_ROOT/coverage/soc_ifc_cov_if.sv
-      - $COMPILE_ROOT/coverage/soc_ifc_cov_bind.sv
 ---
 provides: [soc_ifc_uvm_pkg]
 schema_version: 2.4.0
@@ -32,6 +29,19 @@ targets:
       - $COMPILE_ROOT/rtl/sha512_acc_csr_uvm.sv
       - $COMPILE_ROOT/rtl/soc_ifc_reg_uvm.sv
 ---
+provides: [soc_ifc_coverage]
+schema_version: 2.4.0
+requires:
+  - libs
+  - soc_ifc_pkg
+targets:
+  tb:
+    directories: 
+      - $COMPILE_ROOT/coverage
+    files:
+      - $COMPILE_ROOT/coverage/soc_ifc_cov_if.sv
+      - $COMPILE_ROOT/coverage/soc_ifc_cov_bind.sv
+---
 provides: [soc_ifc_top]
 schema_version: 2.4.0
 requires:
@@ -40,6 +50,7 @@ requires:
   - el2_veer_pkg
   - soc_ifc_pkg
   - sha512_ctrl
+  - caliptra_top_defines 
 targets:
   rtl:
     directories:
@@ -73,6 +84,7 @@ targets:
 provides: [soc_ifc_tb]
 schema_version: 2.4.0
 requires:
+  - soc_ifc_coverage
   - soc_ifc_top
   - caliptra_top_defines
 targets:
diff --git a/src/soc_ifc/config/soc_ifc_cov.vf b/src/soc_ifc/config/soc_ifc_cov.vf
deleted file mode 100644
index e166015ce..000000000
--- a/src/soc_ifc/config/soc_ifc_cov.vf
+++ /dev/null
@@ -1,3 +0,0 @@
-+incdir+${CALIPTRA_ROOT}/src/soc_ifc/coverage
-${CALIPTRA_ROOT}/src/soc_ifc/coverage/soc_ifc_cov_if.sv
-${CALIPTRA_ROOT}/src/soc_ifc/coverage/soc_ifc_cov_bind.sv
\ No newline at end of file
diff --git a/src/soc_ifc/config/soc_ifc_coverage.vf b/src/soc_ifc/config/soc_ifc_coverage.vf
new file mode 100644
index 000000000..59f66f789
--- /dev/null
+++ b/src/soc_ifc/config/soc_ifc_coverage.vf
@@ -0,0 +1,23 @@
++incdir+${CALIPTRA_ROOT}/src/integration/rtl
++incdir+${CALIPTRA_ROOT}/src/libs/rtl
++incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl
++incdir+${CALIPTRA_ROOT}/src/soc_ifc/coverage
+${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh
+${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sva.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_macros.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sram.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_defines_pkg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_ahb_srom.sv
+${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
+${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv
+${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv
+${CALIPTRA_ROOT}/src/soc_ifc/coverage/soc_ifc_cov_if.sv
+${CALIPTRA_ROOT}/src/soc_ifc/coverage/soc_ifc_cov_bind.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
+${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_pkg.sv
+${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv
+${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv
\ No newline at end of file
diff --git a/src/soc_ifc/config/soc_ifc_pkg.vf b/src/soc_ifc/config/soc_ifc_pkg.vf
index 06d681ba8..0ba5a33ba 100644
--- a/src/soc_ifc/config/soc_ifc_pkg.vf
+++ b/src/soc_ifc/config/soc_ifc_pkg.vf
@@ -1,9 +1,6 @@
 +incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl
-+incdir+${CALIPTRA_ROOT}/src/soc_ifc/coverage
 ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv
 ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv
-${CALIPTRA_ROOT}/src/soc_ifc/coverage/soc_ifc_cov_if.sv
-${CALIPTRA_ROOT}/src/soc_ifc/coverage/soc_ifc_cov_bind.sv
 ${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_pkg.sv
 ${CALIPTRA_ROOT}/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv
 ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv
\ No newline at end of file
diff --git a/src/soc_ifc/config/soc_ifc_tb.vf b/src/soc_ifc/config/soc_ifc_tb.vf
index db6ea3cff..55dbfb700 100644
--- a/src/soc_ifc/config/soc_ifc_tb.vf
+++ b/src/soc_ifc/config/soc_ifc_tb.vf
@@ -18,6 +18,7 @@ ${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
 ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv
 ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/soc_ifc/coverage/soc_ifc_cov_if.sv
@@ -46,9 +47,9 @@ ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg.sv
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg_pkg.sv
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_params_pkg.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_ctrl.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512.sv
-${CALIPTRA_ROOT}/src/sha512/rtl/sha512_param.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_core.v
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_h_constants.v
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_k_constants.v
diff --git a/src/soc_ifc/config/soc_ifc_top.vf b/src/soc_ifc/config/soc_ifc_top.vf
index 03566f14d..4e1965ce5 100644
--- a/src/soc_ifc/config/soc_ifc_top.vf
+++ b/src/soc_ifc/config/soc_ifc_top.vf
@@ -1,7 +1,6 @@
 +incdir+${CALIPTRA_ROOT}/src/integration/rtl
 +incdir+${CALIPTRA_ROOT}/src/libs/rtl
 +incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl
-+incdir+${CALIPTRA_ROOT}/src/soc_ifc/coverage
 +incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl
 +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl
 +incdir+${CALIPTRA_ROOT}/src/pcrvault/rtl
@@ -17,10 +16,9 @@ ${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
 ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv
 ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv
-${CALIPTRA_ROOT}/src/soc_ifc/coverage/soc_ifc_cov_if.sv
-${CALIPTRA_ROOT}/src/soc_ifc/coverage/soc_ifc_cov_bind.sv
 ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pdef.vh
 ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/include/el2_def.sv
 ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/common_defines.sv
@@ -43,9 +41,9 @@ ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg.sv
 ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_reg_pkg.sv
+${CALIPTRA_ROOT}/src/sha512/rtl/sha512_params_pkg.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_ctrl.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512.sv
-${CALIPTRA_ROOT}/src/sha512/rtl/sha512_param.sv
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_core.v
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_h_constants.v
 ${CALIPTRA_ROOT}/src/sha512/rtl/sha512_k_constants.v
diff --git a/src/soc_ifc/coverage/soc_ifc_cov_bind.sv b/src/soc_ifc/coverage/soc_ifc_cov_bind.sv
index 45c07393a..47a39dbf2 100644
--- a/src/soc_ifc/coverage/soc_ifc_cov_bind.sv
+++ b/src/soc_ifc/coverage/soc_ifc_cov_bind.sv
@@ -15,6 +15,13 @@
 
 module soc_ifc_cov_bind;
     `ifdef FCOV
-    bind soc_ifc_top soc_ifc_cov_if i_soc_ifc_cov_if(.*);
+    bind soc_ifc_top soc_ifc_cov_if #(
+        .AHB_ADDR_WIDTH(`CALIPTRA_SLAVE_ADDR_WIDTH(`CALIPTRA_SLAVE_SEL_SOC_IFC)),
+        .AHB_DATA_WIDTH(`CALIPTRA_AHB_HDATA_SIZE),
+        .APB_ADDR_WIDTH(`CALIPTRA_SLAVE_ADDR_WIDTH(`CALIPTRA_SLAVE_SEL_SOC_IFC)),
+        .APB_DATA_WIDTH(`CALIPTRA_APB_DATA_WIDTH),
+        .APB_USER_WIDTH(`CALIPTRA_APB_USER_WIDTH)
+        )
+        i_soc_ifc_cov_if (.*);
     `endif
 endmodule
diff --git a/src/soc_ifc/coverage/soc_ifc_cov_if.sv b/src/soc_ifc/coverage/soc_ifc_cov_if.sv
index 48a80457f..74d9d4177 100644
--- a/src/soc_ifc/coverage/soc_ifc_cov_if.sv
+++ b/src/soc_ifc/coverage/soc_ifc_cov_if.sv
@@ -12,31 +12,3099 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
+
+
+// -- What the section under 'SCRIPT_OUTPUT' output covers --
+// 
+// Covergroups. 
+//   - One per register; array of wide registers are under a single covergroup. 
+//
+// Coverpoints:
+//   - Bins for total addressible space per register (including all fields)
+//   - Transition bins: An APB or AHB Write followed by APB or AHB Read within 1000 cycles
+//   - Ignore bins: IDLE (no read/write activity), simultaneous RD and WR over APB or AHB. 
+//
+// Not covered and TODO.   
+//   - Bins for individual fields within a register for special behavior. 
+//   - New covergroups likely needed for cross coverage of related registers.
+//   - Registers that don't have storage allocated (CPTRA_SECURITY_STATE, CPTRA_HW_REV_ID, CPTRA_HW_CONFIG)
+//   - Possibly reduce the number of unique covergroup definitions
+
+
 `ifndef VERILATOR
 
 interface soc_ifc_cov_if     
     import soc_ifc_pkg::*;
     import soc_ifc_reg_pkg::*;
+    #(
+        parameter APB_ADDR_WIDTH = 18
+       ,parameter APB_DATA_WIDTH = 32
+       ,parameter APB_USER_WIDTH = 32
+       ,parameter AHB_ADDR_WIDTH = 18
+       ,parameter AHB_DATA_WIDTH = 32
+    )
     (
     input logic clk,
-    input logic trng_req,
+    input logic clk_cg,
+    input logic soc_ifc_clk_cg,
+
+    //SoC boot signals
+    input logic cptra_pwrgood,
+    input logic cptra_rst_b,
+    input logic uc_req_dv,
+    input soc_ifc_req_t uc_req,
+    input logic soc_req_dv,
+    input soc_ifc_req_t soc_req,
+    input soc_ifc_req_t soc_ifc_reg_req_data,
+
     input logic ready_for_fuses,
     input logic ready_for_fw_push,
-    input logic ready_for_runtime
+    input logic ready_for_runtime,
+
+    input logic mailbox_data_avail,
+    input logic mailbox_flow_done,
+
+    input var security_state_t security_state,
+
+    input logic  [1:0][31:0] generic_input_wires,
+    input logic BootFSM_BrkPoint,
+    input logic [1:0][31:0] generic_output_wires,
+
+    //SoC APB Interface
+    input logic [APB_ADDR_WIDTH-1:0]     paddr_i,
+    input logic                          psel_i,
+    input logic                          penable_i,
+    input logic                          pwrite_i,
+    input logic [APB_DATA_WIDTH-1:0]     pwdata_i,
+    input logic [APB_USER_WIDTH-1:0]     pauser_i,
+    input logic                         pready_o,
+    input logic [APB_DATA_WIDTH-1:0]    prdata_o,
+    input logic                         pslverr_o,
+
+    //uC AHB Lite Interface
+    input logic [AHB_ADDR_WIDTH-1:0]  haddr_i,
+    input logic [AHB_DATA_WIDTH-1:0]  hwdata_i,
+    input logic                       hsel_i,
+    input logic                       hwrite_i,
+    input logic                       hready_i,
+    input logic [1:0]                 htrans_i,
+    input logic [2:0]                 hsize_i,
+
+    input logic                      hresp_o,
+    input logic                      hreadyout_o,
+    input logic [AHB_DATA_WIDTH-1:0] hrdata_o,
+
+    //SoC Interrupts
+    input logic             cptra_error_fatal,
+    input logic             cptra_error_non_fatal,
+    input logic             trng_req,
+
+    //uC Interrupts
+    input wire              soc_ifc_error_intr,
+    input wire              soc_ifc_notif_intr,
+    input wire              sha_error_intr,
+    input wire              sha_notif_intr,
+
+    //SRAM interface
+    input mbox_sram_req_t  mbox_sram_req,
+    input mbox_sram_resp_t mbox_sram_resp,
+
+    //Obfuscated UDS and FE
+    input logic clear_obf_secrets,
+    input logic scan_mode_f,
+    input logic [`CLP_OBF_KEY_DWORDS-1:0][31:0] cptra_obf_key,
+    input logic [`CLP_OBF_KEY_DWORDS-1:0][31:0] cptra_obf_key_reg,
+    input logic [`CLP_OBF_FE_DWORDS-1 :0][31:0] obf_field_entropy,
+    input logic [`CLP_OBF_UDS_DWORDS-1:0][31:0] obf_uds_seed,
+
+    // NMI Vector 
+    input logic [31:0] nmi_vector,
+    input logic nmi_intr,
+
+    // ICCM Lock
+    input logic iccm_lock,
+    input logic iccm_axs_blocked,
+
+    //Other blocks reset
+    input logic cptra_noncore_rst_b,
+    //uC reset
+    input logic cptra_uc_rst_b,
+    //Clock gating
+    input logic clk_gating_en
 );
 
-    logic req_collision = i_soc_ifc_arb.req_collision;
+  enum bit [3:0] {IDLE = '0, AHB_RD = 4'h8, AHB_WR = 4'h4,  APB_RD = 4'h2, APB_WR = 4'h1} bus_event_e;  
+
+  logic uc_rd, uc_wr, soc_rd, soc_wr;
+
+  assign uc_rd = uc_req_dv & ~uc_req.write;
+  assign uc_wr = uc_req_dv & uc_req.write;
+  assign soc_rd = soc_req_dv & ~soc_req.write;
+  assign soc_wr = soc_req_dv & soc_req.write;
 
     covergroup soc_ifc_top_cov_grp @(posedge clk);
-        trng_req_cp: coverpoint trng_req;
+        //IO
+        cptra_pwrgood_cp: coverpoint cptra_pwrgood;
+        cptra_rst_b_cp: coverpoint cptra_rst_b;
+        cptra_noncore_rst_b_cp: coverpoint cptra_noncore_rst_b;
+        cptra_uc_rst_b_cp: coverpoint cptra_uc_rst_b;
+        clk_gating_en_cp: coverpoint clk_gating_en;
+        security_state_cp: coverpoint security_state;
+        scan_mode_f_cp: coverpoint scan_mode_f;
         ready_for_fuses_cp: coverpoint ready_for_fuses;
         ready_for_fw_push_cp: coverpoint ready_for_fw_push;
         ready_for_runtime_cp: coverpoint ready_for_runtime;
-        req_collision_cp: coverpoint req_collision;
+        mailbox_data_avail_cp: coverpoint mailbox_data_avail;
+        mailbox_flow_done_cp: coverpoint mailbox_flow_done;
+        cptra_error_fatal_cp: coverpoint cptra_error_fatal;
+        cptra_error_non_fatal_cp: coverpoint cptra_error_non_fatal;
+        trng_req_cp: coverpoint trng_req;
+        BootFSM_BrkPoint_cp: coverpoint BootFSM_BrkPoint;
+        generic_input_wires_cp: coverpoint generic_input_wires;
+        generic_output_wires_cp: coverpoint generic_output_wires;
+        nmi_vector_cp: coverpoint nmi_vector;
+        nmi_intr_cp: coverpoint nmi_intr;
+        soc_ifc_error_intr_cp: coverpoint soc_ifc_error_intr;
+        soc_ifc_notif_intr_cp: coverpoint soc_ifc_notif_intr;
+        sha_error_intr_cp: coverpoint sha_error_intr;
+        sha_notif_intr_cp: coverpoint sha_notif_intr;
+        mbox_sram_req_cp: coverpoint mbox_sram_req;
+        mbox_sram_resp_cp: coverpoint mbox_sram_resp;
+        clear_obf_secrets_cp: coverpoint clear_obf_secrets;
+        cptra_obf_key_reg_cp: coverpoint cptra_obf_key_reg;
+        obf_field_entropy_cp: coverpoint obf_field_entropy;
+        obf_uds_seed_cp: coverpoint obf_uds_seed;
+        iccm_lock_cp: coverpoint iccm_lock;
+        iccm_axs_blocked_cp: coverpoint iccm_axs_blocked;
+
     endgroup
 
+    logic valid_arb_cycle;
+    assign valid_arb_cycle = i_soc_ifc_arb.uc_req_dv | i_soc_ifc_arb.soc_req_dv;
+
+    covergroup soc_ifc_arb_cov_grp @(posedge clk iff (cptra_rst_b & valid_arb_cycle));
+        req_collision_cp: coverpoint i_soc_ifc_arb.req_collision;
+        soc_has_priority_cp: coverpoint i_soc_ifc_arb.soc_has_priority;
+        valid_mbox_req_cp: coverpoint i_soc_ifc_arb.valid_mbox_req;
+        soc_mbox_addr_cp: coverpoint i_soc_ifc_arb.soc_req_data.addr inside {[MBOX_REG_START_ADDR:MBOX_REG_END_ADDR]};
+
+        soc_mbox_req_ip_cp: coverpoint i_soc_ifc_arb.soc_mbox_req_ip;
+        soc_reg_req_ip_cp: coverpoint i_soc_ifc_arb.soc_reg_req_ip;
+        soc_sha_req_ip_cp: coverpoint i_soc_ifc_arb.soc_sha_req_ip;
+
+        uc_mbox_req_ip_cp: coverpoint i_soc_ifc_arb.uc_mbox_req_ip;
+        uc_reg_req_ip_cp: coverpoint i_soc_ifc_arb.uc_reg_req_ip;
+        uc_sha_req_ip_cp: coverpoint i_soc_ifc_arb.uc_sha_req_ip;
+
+        uc_mbox_reg_req_cp: coverpoint i_soc_ifc_arb.uc_mbox_reg_req;
+        uc_mbox_dir_req_cp: coverpoint i_soc_ifc_arb.uc_mbox_dir_req;
+        soc_mbox_req_cp: coverpoint i_soc_ifc_arb.soc_mbox_req;
+
+        uc_reg_req_cp: coverpoint i_soc_ifc_arb.uc_reg_req;
+        soc_reg_req_cp: coverpoint i_soc_ifc_arb.soc_reg_req;
+
+        uc_sha_req_cp: coverpoint i_soc_ifc_arb.uc_sha_req;
+        soc_sha_req_cp: coverpoint i_soc_ifc_arb.soc_sha_req;
+
+        //Cover soc req to mbox addr range with and without valid pauser.
+        soc_mbox_reqXvalid_mbox_req: cross soc_mbox_addr_cp, valid_mbox_req_cp;
+
+
+
+    endgroup
+
+    covergroup soc_ifc_boot_fsm_cov_grp @(posedge clk iff cptra_rst_b);
+        //FSM
+        boot_fsm_ps_cp: coverpoint i_soc_ifc_boot_fsm.boot_fsm_ps;
+        arc_BOOT_FUSE_BOOT_DONE_cp: coverpoint i_soc_ifc_boot_fsm.arc_BOOT_FUSE_BOOT_DONE;
+        arc_BOOT_FUSE_BOOT_WAIT_cp: coverpoint i_soc_ifc_boot_fsm.arc_BOOT_FUSE_BOOT_WAIT;
+        arc_BOOT_DONE_BOOT_IDLE_cp: coverpoint i_soc_ifc_boot_fsm.arc_BOOT_DONE_BOOT_IDLE;
+        arc_BOOT_DONE_BOOT_FWRST_cp: coverpoint i_soc_ifc_boot_fsm.arc_BOOT_DONE_BOOT_FWRST;
+        arc_BOOT_WAIT_BOOT_DONE_cp: coverpoint i_soc_ifc_boot_fsm.arc_BOOT_WAIT_BOOT_DONE;
+        fsm_iccm_unlock_cp: coverpoint i_soc_ifc_boot_fsm.fsm_iccm_unlock;
+
+
+    endgroup
+
+    sha_fsm_state_e sha_fsm_ps;
+    assign sha_fsm_ps = sha_fsm_state_e'(i_sha512_acc_top.sha_fsm_ps);
+
+    covergroup sha512_acc_cov_grp @(posedge clk iff cptra_rst_b);
+        //FSM
+        sha_fsm_ps_cp: coverpoint sha_fsm_ps;
+        arc_SHA_IDLE_SHA_BLOCK_0_cp: coverpoint i_sha512_acc_top.arc_SHA_IDLE_SHA_BLOCK_0;
+        arc_SHA_BLOCK_0_SHA_BLOCK_N_cp: coverpoint i_sha512_acc_top.arc_SHA_BLOCK_0_SHA_BLOCK_N;
+        arc_SHA_BLOCK_0_SHA_PAD0_cp: coverpoint i_sha512_acc_top.arc_SHA_BLOCK_0_SHA_PAD0;
+        arc_SHA_BLOCK_N_SHA_BLOCK_N_cp: coverpoint i_sha512_acc_top.arc_SHA_BLOCK_N_SHA_BLOCK_N;
+        arc_SHA_BLOCK_N_SHA_PAD0_cp: coverpoint i_sha512_acc_top.arc_SHA_BLOCK_N_SHA_PAD0;
+        arc_SHA_PAD0_SHA_PAD1_cp: coverpoint i_sha512_acc_top.arc_SHA_PAD0_SHA_PAD1;
+        arc_SHA_PAD0_SHA_DONE_cp: coverpoint i_sha512_acc_top.arc_SHA_PAD0_SHA_DONE;
+        arc_SHA_PAD1_SHA_DONE_cp: coverpoint i_sha512_acc_top.arc_SHA_PAD1_SHA_DONE;
+        arc_IDLE_cp: coverpoint (i_sha512_acc_top.arc_IDLE & (sha_fsm_ps != SHA_IDLE));
+
+        //controls
+        extra_pad_block_required_cp: coverpoint i_sha512_acc_top.extra_pad_block_required;
+        num_bytes_data_cp: coverpoint i_sha512_acc_top.num_bytes_data;
+        mailbox_mode_cp: coverpoint i_sha512_acc_top.mailbox_mode;
+        sha_mode_cp: coverpoint i_sha512_acc_top.sha_mode {
+          option.comment = "SHA Mode Encoding";
+          bins MODE_SHA_384 = {2'h2};
+          bins MODE_SHA_512 = {2'h3};
+        }
+
+        //crosses
+        mailbox_modeXextra_pad: cross mailbox_mode_cp, extra_pad_block_required_cp;
+        mailbox_modeXnum_bytes_data: cross mailbox_mode_cp, num_bytes_data_cp;
+        mailbox_modeXsha_mode_cpXsha_fsm_ps: cross mailbox_mode_cp, sha_mode_cp, sha_fsm_ps_cp;
+
+    endgroup
+
+    mbox_fsm_state_e mbox_fsm_ps;
+    assign mbox_fsm_ps = mbox_fsm_state_e'(i_mbox.mbox_fsm_ps);
+
+    covergroup mbox_cov_grp @(posedge clk iff cptra_rst_b);
+        //FSM
+        mbox_fsm_ps_cp: coverpoint mbox_fsm_ps;
+        arc_FORCE_MBOX_UNLOCK_cp: coverpoint i_mbox.arc_FORCE_MBOX_UNLOCK;
+        arc_MBOX_IDLE_MBOX_RDY_FOR_CMD_cp: coverpoint i_mbox.arc_MBOX_IDLE_MBOX_RDY_FOR_CMD;
+        arc_MBOX_RDY_FOR_CMD_MBOX_RDY_FOR_DLEN_cp: coverpoint i_mbox.arc_MBOX_RDY_FOR_CMD_MBOX_RDY_FOR_DLEN;
+        arc_MBOX_RDY_FOR_DLEN_MBOX_RDY_FOR_DATA_cp: coverpoint i_mbox.arc_MBOX_RDY_FOR_DLEN_MBOX_RDY_FOR_DATA;
+        arc_MBOX_RDY_FOR_DATA_MBOX_EXECUTE_UC_cp: coverpoint i_mbox.arc_MBOX_RDY_FOR_DATA_MBOX_EXECUTE_UC;
+        arc_MBOX_RDY_FOR_DATA_MBOX_EXECUTE_SOC_cp: coverpoint i_mbox.arc_MBOX_RDY_FOR_DATA_MBOX_EXECUTE_SOC;
+        arc_MBOX_EXECUTE_UC_MBOX_IDLE_cp: coverpoint i_mbox.arc_MBOX_EXECUTE_UC_MBOX_IDLE;
+        arc_MBOX_EXECUTE_SOC_MBOX_IDLE_cp: coverpoint i_mbox.arc_MBOX_EXECUTE_SOC_MBOX_IDLE;
+        arc_MBOX_EXECUTE_UC_MBOX_EXECUTE_SOC_cp: coverpoint i_mbox.arc_MBOX_EXECUTE_UC_MBOX_EXECUTE_SOC;
+        arc_MBOX_EXECUTE_SOC_MBOX_EXECUTE_UC_cp: coverpoint i_mbox.arc_MBOX_EXECUTE_SOC_MBOX_EXECUTE_UC;
+
+        //controls
+        soc_has_lock_cp: coverpoint i_mbox.soc_has_lock;
+        mask_rdata_cp: coverpoint i_mbox.mask_rdata;
+        dlen_in_dws_cp: coverpoint i_mbox.dlen_in_dws {
+          bins zero = {0};
+          bins one = {1};
+          bins range[32] = {[2:MBOX_SIZE_DWORDS-2]};
+          bins almost_full = {MBOX_SIZE_DWORDS-1};
+          bins full = {MBOX_SIZE_DWORDS};}
+
+        sram_single_ecc_error_cp: coverpoint i_mbox.sram_single_ecc_error;
+        sram_double_ecc_error_cp: coverpoint i_mbox.sram_double_ecc_error;
+
+        //req hold varieties
+        req_hold0_cp: coverpoint i_mbox.req_dv & (i_mbox.dir_req_dv_q & ~i_mbox.req_data.write);
+        req_hold1_cp: coverpoint i_mbox.req_dv & (i_mbox.dir_req_dv & i_mbox.sha_sram_req_dv);
+        req_hold2_cp: coverpoint i_mbox.req_dv & (i_mbox.hwif_out.mbox_dataout.dataout.swacc & i_mbox.mbox_protocol_sram_rd_f);
+        sha_sram_hold_cp: coverpoint i_mbox.sha_sram_hold;
+
+        //special scenarios - only care about bin of 1
+        dlen_gt_mbox_size_cp: coverpoint i_mbox.hwif_out.mbox_dlen.length.value > MBOX_SIZE_BYTES {
+            option.comment = "DLEN is programmed greater than mailbox size";
+            bins one = {1};}
+        req_wrptr_gt_dlen_cp: coverpoint (mbox_fsm_ps == MBOX_RDY_FOR_DATA) & (i_mbox.mbox_wrptr > i_mbox.dlen_in_dws) {
+            option.comment = "Requester caused write pointer to increment past DLEN";
+            bins one = {1};}
+        resp_wrptr_gt_dlen_cp: coverpoint (mbox_fsm_ps inside {MBOX_EXECUTE_UC,MBOX_EXECUTE_SOC}) & (i_mbox.mbox_wrptr > i_mbox.dlen_in_dws) {
+            option.comment = "Receiver caused write pointer to increment past DLEN";
+            bins one = {1};}
+        wrptr_rollover_cp: coverpoint i_mbox.inc_wrptr & ~i_mbox.wrptr_inc_valid {
+            option.comment = "Write pointer tried to increment past mailbox size";
+            bins one = {1};}
+        rdptr_gt_dlen_cp: coverpoint i_mbox.inc_rdptr & ~(i_mbox.mbox_rdptr <= i_mbox.dlen_in_dws) {
+            option.comment = "Read pointer tried to increment passed DLEN";
+            bins one = {1};}
+        rdptr_rollover_cp: coverpoint i_mbox.inc_rdptr & ~(i_mbox.mbox_rdptr < (MBOX_SIZE_DWORDS-1)) {
+            option.comment = "Read pointer tried to increment passed mailbox size";
+            bins one = {1};}
+
+    endgroup
+   
     soc_ifc_top_cov_grp soc_ifc_top_cov_grp1 = new();
+    soc_ifc_arb_cov_grp soc_ifc_arb_cov_grp1 = new();
+    soc_ifc_boot_fsm_cov_grp soc_ifc_boot_fsm_cov_grp1 = new();
+    sha512_acc_cov_grp sha512_acc_cov_grp1 = new();
+    mbox_cov_grp mbox_cov_grp1 = new();
+
+/*  -- Working Reference -- 
+    for(genvar i = 0; i < 4; i++) begin : fuse_runtime_svn_blk
+      covergroup soc_ifc_fuse_runtime_svn_cg @(posedge clk);
+        option.comment =  {"fuse_runtime_svn", "_cp"};
+        coverpoint i_soc_ifc_reg.field_storage.fuse_runtime_svn[i]; 
+      endgroup
+      soc_ifc_fuse_runtime_svn_cg fuse_runtime_svn_cg = new();
+    end 
+*/   
+
+
+
+
+  // ------------------------------------------------------------------- 
+  // begin SCRIPT_OUTPUT
+  // ------------------------------------------------------------------- 
+
+
+  // ------------------- COVERGROUP related signals & assigns -------------------
+
+  logic          hit_CPTRA_HW_ERROR_FATAL;
+  logic [3:0]    bus_CPTRA_HW_ERROR_FATAL;
+  logic [31:0]   full_addr_CPTRA_HW_ERROR_FATAL = `CLP_SOC_IFC_REG_CPTRA_HW_ERROR_FATAL;
+
+  logic          hit_CPTRA_HW_ERROR_NON_FATAL;
+  logic [3:0]    bus_CPTRA_HW_ERROR_NON_FATAL;
+  logic [31:0]   full_addr_CPTRA_HW_ERROR_NON_FATAL = `CLP_SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL;
+
+  logic          hit_CPTRA_FW_ERROR_FATAL;
+  logic [3:0]    bus_CPTRA_FW_ERROR_FATAL;
+  logic [31:0]   full_addr_CPTRA_FW_ERROR_FATAL = `CLP_SOC_IFC_REG_CPTRA_FW_ERROR_FATAL;
+
+  logic          hit_CPTRA_FW_ERROR_NON_FATAL;
+  logic [3:0]    bus_CPTRA_FW_ERROR_NON_FATAL;
+  logic [31:0]   full_addr_CPTRA_FW_ERROR_NON_FATAL = `CLP_SOC_IFC_REG_CPTRA_FW_ERROR_NON_FATAL;
+
+  logic          hit_CPTRA_HW_ERROR_ENC;
+  logic [3:0]    bus_CPTRA_HW_ERROR_ENC;
+  logic [31:0]   full_addr_CPTRA_HW_ERROR_ENC = `CLP_SOC_IFC_REG_CPTRA_HW_ERROR_ENC;
+
+  logic          hit_CPTRA_FW_ERROR_ENC;
+  logic [3:0]    bus_CPTRA_FW_ERROR_ENC;
+  logic [31:0]   full_addr_CPTRA_FW_ERROR_ENC = `CLP_SOC_IFC_REG_CPTRA_FW_ERROR_ENC;
+
+  logic          hit_CPTRA_FW_EXTENDED_ERROR_INFO[0:7];
+  logic [3:0]    bus_CPTRA_FW_EXTENDED_ERROR_INFO[0:7];
+  logic [31:0]   full_addr_CPTRA_FW_EXTENDED_ERROR_INFO[0:7];
+  assign         full_addr_CPTRA_FW_EXTENDED_ERROR_INFO[0] = `CLP_SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_0;
+  assign         full_addr_CPTRA_FW_EXTENDED_ERROR_INFO[1] = `CLP_SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_1;
+  assign         full_addr_CPTRA_FW_EXTENDED_ERROR_INFO[2] = `CLP_SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_2;
+  assign         full_addr_CPTRA_FW_EXTENDED_ERROR_INFO[3] = `CLP_SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_3;
+  assign         full_addr_CPTRA_FW_EXTENDED_ERROR_INFO[4] = `CLP_SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_4;
+  assign         full_addr_CPTRA_FW_EXTENDED_ERROR_INFO[5] = `CLP_SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_5;
+  assign         full_addr_CPTRA_FW_EXTENDED_ERROR_INFO[6] = `CLP_SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_6;
+  assign         full_addr_CPTRA_FW_EXTENDED_ERROR_INFO[7] = `CLP_SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_7;
+
+  logic          hit_CPTRA_BOOT_STATUS;
+  logic [3:0]    bus_CPTRA_BOOT_STATUS;
+  logic [31:0]   full_addr_CPTRA_BOOT_STATUS = `CLP_SOC_IFC_REG_CPTRA_BOOT_STATUS;
+
+  logic          hit_CPTRA_FLOW_STATUS;
+  logic [3:0]    bus_CPTRA_FLOW_STATUS;
+  logic [31:0]   full_addr_CPTRA_FLOW_STATUS = `CLP_SOC_IFC_REG_CPTRA_FLOW_STATUS;
+
+  logic          hit_CPTRA_RESET_REASON;
+  logic [3:0]    bus_CPTRA_RESET_REASON;
+  logic [31:0]   full_addr_CPTRA_RESET_REASON = `CLP_SOC_IFC_REG_CPTRA_RESET_REASON;
+
+  // logic          hit_CPTRA_SECURITY_STATE;
+  // logic [3:0]    bus_CPTRA_SECURITY_STATE;
+  // logic [31:0]   full_addr_CPTRA_SECURITY_STATE = `CLP_SOC_IFC_REG_CPTRA_SECURITY_STATE;
+
+  logic          hit_CPTRA_MBOX_VALID_PAUSER[0:4];
+  logic [3:0]    bus_CPTRA_MBOX_VALID_PAUSER[0:4];
+  logic [31:0]   full_addr_CPTRA_MBOX_VALID_PAUSER[0:4];
+  assign         full_addr_CPTRA_MBOX_VALID_PAUSER[0] = `CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_0;
+  assign         full_addr_CPTRA_MBOX_VALID_PAUSER[1] = `CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_1;
+  assign         full_addr_CPTRA_MBOX_VALID_PAUSER[2] = `CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_2;
+  assign         full_addr_CPTRA_MBOX_VALID_PAUSER[3] = `CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_3;
+  assign         full_addr_CPTRA_MBOX_VALID_PAUSER[4] = `CLP_SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_4;
+
+  logic          hit_CPTRA_MBOX_PAUSER_LOCK[0:4];
+  logic [3:0]    bus_CPTRA_MBOX_PAUSER_LOCK[0:4];
+  logic [31:0]   full_addr_CPTRA_MBOX_PAUSER_LOCK[0:4];
+  assign         full_addr_CPTRA_MBOX_PAUSER_LOCK[0] = `CLP_SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_0;
+  assign         full_addr_CPTRA_MBOX_PAUSER_LOCK[1] = `CLP_SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_1;
+  assign         full_addr_CPTRA_MBOX_PAUSER_LOCK[2] = `CLP_SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_2;
+  assign         full_addr_CPTRA_MBOX_PAUSER_LOCK[3] = `CLP_SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_3;
+  assign         full_addr_CPTRA_MBOX_PAUSER_LOCK[4] = `CLP_SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_4;
+
+  logic          hit_CPTRA_TRNG_VALID_PAUSER;
+  logic [3:0]    bus_CPTRA_TRNG_VALID_PAUSER;
+  logic [31:0]   full_addr_CPTRA_TRNG_VALID_PAUSER = `CLP_SOC_IFC_REG_CPTRA_TRNG_VALID_PAUSER;
+
+  logic          hit_CPTRA_TRNG_PAUSER_LOCK;
+  logic [3:0]    bus_CPTRA_TRNG_PAUSER_LOCK;
+  logic [31:0]   full_addr_CPTRA_TRNG_PAUSER_LOCK = `CLP_SOC_IFC_REG_CPTRA_TRNG_PAUSER_LOCK;
+
+  logic          hit_CPTRA_TRNG_DATA[0:11];
+  logic [3:0]    bus_CPTRA_TRNG_DATA[0:11];
+  logic [31:0]   full_addr_CPTRA_TRNG_DATA[0:11];
+  assign         full_addr_CPTRA_TRNG_DATA[0] = `CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_0;
+  assign         full_addr_CPTRA_TRNG_DATA[1] = `CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_1;
+  assign         full_addr_CPTRA_TRNG_DATA[2] = `CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_2;
+  assign         full_addr_CPTRA_TRNG_DATA[3] = `CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_3;
+  assign         full_addr_CPTRA_TRNG_DATA[4] = `CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_4;
+  assign         full_addr_CPTRA_TRNG_DATA[5] = `CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_5;
+  assign         full_addr_CPTRA_TRNG_DATA[6] = `CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_6;
+  assign         full_addr_CPTRA_TRNG_DATA[7] = `CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_7;
+  assign         full_addr_CPTRA_TRNG_DATA[8] = `CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_8;
+  assign         full_addr_CPTRA_TRNG_DATA[9] = `CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_9;
+  assign         full_addr_CPTRA_TRNG_DATA[10] = `CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_10;
+  assign         full_addr_CPTRA_TRNG_DATA[11] = `CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_11;
+
+  logic          hit_CPTRA_TRNG_CTRL;
+  logic [3:0]    bus_CPTRA_TRNG_CTRL;
+  logic [31:0]   full_addr_CPTRA_TRNG_CTRL = `CLP_SOC_IFC_REG_CPTRA_TRNG_CTRL;
+
+  logic          hit_CPTRA_TRNG_STATUS;
+  logic [3:0]    bus_CPTRA_TRNG_STATUS;
+  logic [31:0]   full_addr_CPTRA_TRNG_STATUS = `CLP_SOC_IFC_REG_CPTRA_TRNG_STATUS;
+
+  logic          hit_CPTRA_FUSE_WR_DONE;
+  logic [3:0]    bus_CPTRA_FUSE_WR_DONE;
+  logic [31:0]   full_addr_CPTRA_FUSE_WR_DONE = `CLP_SOC_IFC_REG_CPTRA_FUSE_WR_DONE;
+
+  logic          hit_CPTRA_TIMER_CONFIG;
+  logic [3:0]    bus_CPTRA_TIMER_CONFIG;
+  logic [31:0]   full_addr_CPTRA_TIMER_CONFIG = `CLP_SOC_IFC_REG_CPTRA_TIMER_CONFIG;
+
+  logic          hit_CPTRA_BOOTFSM_GO;
+  logic [3:0]    bus_CPTRA_BOOTFSM_GO;
+  logic [31:0]   full_addr_CPTRA_BOOTFSM_GO = `CLP_SOC_IFC_REG_CPTRA_BOOTFSM_GO;
+
+  logic          hit_CPTRA_DBG_MANUF_SERVICE_REG;
+  logic [3:0]    bus_CPTRA_DBG_MANUF_SERVICE_REG;
+  logic [31:0]   full_addr_CPTRA_DBG_MANUF_SERVICE_REG = `CLP_SOC_IFC_REG_CPTRA_DBG_MANUF_SERVICE_REG;
+
+  logic          hit_CPTRA_CLK_GATING_EN;
+  logic [3:0]    bus_CPTRA_CLK_GATING_EN;
+  logic [31:0]   full_addr_CPTRA_CLK_GATING_EN = `CLP_SOC_IFC_REG_CPTRA_CLK_GATING_EN;
+
+  logic          hit_CPTRA_GENERIC_INPUT_WIRES[0:1];
+  logic [3:0]    bus_CPTRA_GENERIC_INPUT_WIRES[0:1];
+  logic [31:0]   full_addr_CPTRA_GENERIC_INPUT_WIRES[0:1];
+  assign         full_addr_CPTRA_GENERIC_INPUT_WIRES[0] = `CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0;
+  assign         full_addr_CPTRA_GENERIC_INPUT_WIRES[1] = `CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_1;
+
+  logic          hit_CPTRA_GENERIC_OUTPUT_WIRES[0:1];
+  logic [3:0]    bus_CPTRA_GENERIC_OUTPUT_WIRES[0:1];
+  logic [31:0]   full_addr_CPTRA_GENERIC_OUTPUT_WIRES[0:1];
+  assign         full_addr_CPTRA_GENERIC_OUTPUT_WIRES[0] = `CLP_SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_0;
+  assign         full_addr_CPTRA_GENERIC_OUTPUT_WIRES[1] = `CLP_SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_1;
+
+  // logic          hit_CPTRA_HW_REV_ID;
+  // logic [3:0]    bus_CPTRA_HW_REV_ID;
+  // logic [31:0]   full_addr_CPTRA_HW_REV_ID = `CLP_SOC_IFC_REG_CPTRA_HW_REV_ID;
+
+  logic          hit_CPTRA_FW_REV_ID[0:1];
+  logic [3:0]    bus_CPTRA_FW_REV_ID[0:1];
+  logic [31:0]   full_addr_CPTRA_FW_REV_ID[0:1];
+  assign         full_addr_CPTRA_FW_REV_ID[0] = `CLP_SOC_IFC_REG_CPTRA_FW_REV_ID_0;
+  assign         full_addr_CPTRA_FW_REV_ID[1] = `CLP_SOC_IFC_REG_CPTRA_FW_REV_ID_1;
+
+  // logic          hit_CPTRA_HW_CONFIG;
+  // logic [3:0]    bus_CPTRA_HW_CONFIG;
+  // logic [31:0]   full_addr_CPTRA_HW_CONFIG = `CLP_SOC_IFC_REG_CPTRA_HW_CONFIG;
+
+  logic          hit_CPTRA_WDT_TIMER1_EN;
+  logic [3:0]    bus_CPTRA_WDT_TIMER1_EN;
+  logic [31:0]   full_addr_CPTRA_WDT_TIMER1_EN = `CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_EN;
+
+  logic          hit_CPTRA_WDT_TIMER1_CTRL;
+  logic [3:0]    bus_CPTRA_WDT_TIMER1_CTRL;
+  logic [31:0]   full_addr_CPTRA_WDT_TIMER1_CTRL = `CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL;
+
+  logic          hit_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[0:1];
+  logic [3:0]    bus_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[0:1];
+  logic [31:0]   full_addr_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[0:1];
+  assign         full_addr_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[0] = `CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0;
+  assign         full_addr_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[1] = `CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1;
+
+  logic          hit_CPTRA_WDT_TIMER2_EN;
+  logic [3:0]    bus_CPTRA_WDT_TIMER2_EN;
+  logic [31:0]   full_addr_CPTRA_WDT_TIMER2_EN = `CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_EN;
+
+  logic          hit_CPTRA_WDT_TIMER2_CTRL;
+  logic [3:0]    bus_CPTRA_WDT_TIMER2_CTRL;
+  logic [31:0]   full_addr_CPTRA_WDT_TIMER2_CTRL = `CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL;
+
+  logic          hit_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[0:1];
+  logic [3:0]    bus_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[0:1];
+  logic [31:0]   full_addr_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[0:1];
+  assign         full_addr_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[0] = `CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0;
+  assign         full_addr_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[1] = `CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1;
+
+  logic          hit_CPTRA_WDT_STATUS;
+  logic [3:0]    bus_CPTRA_WDT_STATUS;
+  logic [31:0]   full_addr_CPTRA_WDT_STATUS = `CLP_SOC_IFC_REG_CPTRA_WDT_STATUS;
+
+  logic          hit_CPTRA_FUSE_VALID_PAUSER;
+  logic [3:0]    bus_CPTRA_FUSE_VALID_PAUSER;
+  logic [31:0]   full_addr_CPTRA_FUSE_VALID_PAUSER = `CLP_SOC_IFC_REG_CPTRA_FUSE_VALID_PAUSER;
+
+  logic          hit_CPTRA_FUSE_PAUSER_LOCK;
+  logic [3:0]    bus_CPTRA_FUSE_PAUSER_LOCK;
+  logic [31:0]   full_addr_CPTRA_FUSE_PAUSER_LOCK = `CLP_SOC_IFC_REG_CPTRA_FUSE_PAUSER_LOCK;
+
+  logic          hit_CPTRA_WDT_CFG[0:1];
+  logic [3:0]    bus_CPTRA_WDT_CFG[0:1];
+  logic [31:0]   full_addr_CPTRA_WDT_CFG[0:1];
+  assign         full_addr_CPTRA_WDT_CFG[0] = `CLP_SOC_IFC_REG_CPTRA_WDT_CFG_0;
+  assign         full_addr_CPTRA_WDT_CFG[1] = `CLP_SOC_IFC_REG_CPTRA_WDT_CFG_1;
+
+  logic          hit_CPTRA_iTRNG_ENTROPY_CONFIG_0;
+  logic [3:0]    bus_CPTRA_iTRNG_ENTROPY_CONFIG_0;
+  logic [31:0]   full_addr_CPTRA_iTRNG_ENTROPY_CONFIG_0 = `CLP_SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0;
+
+  logic          hit_CPTRA_iTRNG_ENTROPY_CONFIG_1;
+  logic [3:0]    bus_CPTRA_iTRNG_ENTROPY_CONFIG_1;
+  logic [31:0]   full_addr_CPTRA_iTRNG_ENTROPY_CONFIG_1 = `CLP_SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1;
+
+  logic          hit_CPTRA_RSVD_REG[0:1];
+  logic [3:0]    bus_CPTRA_RSVD_REG[0:1];
+  logic [31:0]   full_addr_CPTRA_RSVD_REG[0:1];
+  assign         full_addr_CPTRA_RSVD_REG[0] = `CLP_SOC_IFC_REG_CPTRA_RSVD_REG_0;
+  assign         full_addr_CPTRA_RSVD_REG[1] = `CLP_SOC_IFC_REG_CPTRA_RSVD_REG_1;
+
+  logic          hit_fuse_uds_seed[0:11];
+  logic [3:0]    bus_fuse_uds_seed[0:11];
+  logic [31:0]   full_addr_fuse_uds_seed[0:11];
+  assign         full_addr_fuse_uds_seed[0] = `CLP_SOC_IFC_REG_FUSE_UDS_SEED_0;
+  assign         full_addr_fuse_uds_seed[1] = `CLP_SOC_IFC_REG_FUSE_UDS_SEED_1;
+  assign         full_addr_fuse_uds_seed[2] = `CLP_SOC_IFC_REG_FUSE_UDS_SEED_2;
+  assign         full_addr_fuse_uds_seed[3] = `CLP_SOC_IFC_REG_FUSE_UDS_SEED_3;
+  assign         full_addr_fuse_uds_seed[4] = `CLP_SOC_IFC_REG_FUSE_UDS_SEED_4;
+  assign         full_addr_fuse_uds_seed[5] = `CLP_SOC_IFC_REG_FUSE_UDS_SEED_5;
+  assign         full_addr_fuse_uds_seed[6] = `CLP_SOC_IFC_REG_FUSE_UDS_SEED_6;
+  assign         full_addr_fuse_uds_seed[7] = `CLP_SOC_IFC_REG_FUSE_UDS_SEED_7;
+  assign         full_addr_fuse_uds_seed[8] = `CLP_SOC_IFC_REG_FUSE_UDS_SEED_8;
+  assign         full_addr_fuse_uds_seed[9] = `CLP_SOC_IFC_REG_FUSE_UDS_SEED_9;
+  assign         full_addr_fuse_uds_seed[10] = `CLP_SOC_IFC_REG_FUSE_UDS_SEED_10;
+  assign         full_addr_fuse_uds_seed[11] = `CLP_SOC_IFC_REG_FUSE_UDS_SEED_11;
+
+  logic          hit_fuse_field_entropy[0:7];
+  logic [3:0]    bus_fuse_field_entropy[0:7];
+  logic [31:0]   full_addr_fuse_field_entropy[0:7];
+  assign         full_addr_fuse_field_entropy[0] = `CLP_SOC_IFC_REG_FUSE_FIELD_ENTROPY_0;
+  assign         full_addr_fuse_field_entropy[1] = `CLP_SOC_IFC_REG_FUSE_FIELD_ENTROPY_1;
+  assign         full_addr_fuse_field_entropy[2] = `CLP_SOC_IFC_REG_FUSE_FIELD_ENTROPY_2;
+  assign         full_addr_fuse_field_entropy[3] = `CLP_SOC_IFC_REG_FUSE_FIELD_ENTROPY_3;
+  assign         full_addr_fuse_field_entropy[4] = `CLP_SOC_IFC_REG_FUSE_FIELD_ENTROPY_4;
+  assign         full_addr_fuse_field_entropy[5] = `CLP_SOC_IFC_REG_FUSE_FIELD_ENTROPY_5;
+  assign         full_addr_fuse_field_entropy[6] = `CLP_SOC_IFC_REG_FUSE_FIELD_ENTROPY_6;
+  assign         full_addr_fuse_field_entropy[7] = `CLP_SOC_IFC_REG_FUSE_FIELD_ENTROPY_7;
+
+  logic          hit_fuse_key_manifest_pk_hash[0:11];
+  logic [3:0]    bus_fuse_key_manifest_pk_hash[0:11];
+  logic [31:0]   full_addr_fuse_key_manifest_pk_hash[0:11];
+  assign         full_addr_fuse_key_manifest_pk_hash[0] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_0;
+  assign         full_addr_fuse_key_manifest_pk_hash[1] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_1;
+  assign         full_addr_fuse_key_manifest_pk_hash[2] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_2;
+  assign         full_addr_fuse_key_manifest_pk_hash[3] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_3;
+  assign         full_addr_fuse_key_manifest_pk_hash[4] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_4;
+  assign         full_addr_fuse_key_manifest_pk_hash[5] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_5;
+  assign         full_addr_fuse_key_manifest_pk_hash[6] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_6;
+  assign         full_addr_fuse_key_manifest_pk_hash[7] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_7;
+  assign         full_addr_fuse_key_manifest_pk_hash[8] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_8;
+  assign         full_addr_fuse_key_manifest_pk_hash[9] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_9;
+  assign         full_addr_fuse_key_manifest_pk_hash[10] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_10;
+  assign         full_addr_fuse_key_manifest_pk_hash[11] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_11;
+
+  logic          hit_fuse_key_manifest_pk_hash_mask;
+  logic [3:0]    bus_fuse_key_manifest_pk_hash_mask;
+  logic [31:0]   full_addr_fuse_key_manifest_pk_hash_mask = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK;
+
+  logic          hit_fuse_owner_pk_hash[0:11];
+  logic [3:0]    bus_fuse_owner_pk_hash[0:11];
+  logic [31:0]   full_addr_fuse_owner_pk_hash[0:11];
+  assign         full_addr_fuse_owner_pk_hash[0] = `CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_0;
+  assign         full_addr_fuse_owner_pk_hash[1] = `CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_1;
+  assign         full_addr_fuse_owner_pk_hash[2] = `CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_2;
+  assign         full_addr_fuse_owner_pk_hash[3] = `CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_3;
+  assign         full_addr_fuse_owner_pk_hash[4] = `CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_4;
+  assign         full_addr_fuse_owner_pk_hash[5] = `CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_5;
+  assign         full_addr_fuse_owner_pk_hash[6] = `CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_6;
+  assign         full_addr_fuse_owner_pk_hash[7] = `CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_7;
+  assign         full_addr_fuse_owner_pk_hash[8] = `CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_8;
+  assign         full_addr_fuse_owner_pk_hash[9] = `CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_9;
+  assign         full_addr_fuse_owner_pk_hash[10] = `CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_10;
+  assign         full_addr_fuse_owner_pk_hash[11] = `CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_11;
+
+  logic          hit_fuse_fmc_key_manifest_svn;
+  logic [3:0]    bus_fuse_fmc_key_manifest_svn;
+  logic [31:0]   full_addr_fuse_fmc_key_manifest_svn = `CLP_SOC_IFC_REG_FUSE_FMC_KEY_MANIFEST_SVN;
+
+  logic          hit_fuse_runtime_svn[0:3];
+  logic [3:0]    bus_fuse_runtime_svn[0:3];
+  logic [31:0]   full_addr_fuse_runtime_svn[0:3];
+  assign         full_addr_fuse_runtime_svn[0] = `CLP_SOC_IFC_REG_FUSE_RUNTIME_SVN_0;
+  assign         full_addr_fuse_runtime_svn[1] = `CLP_SOC_IFC_REG_FUSE_RUNTIME_SVN_1;
+  assign         full_addr_fuse_runtime_svn[2] = `CLP_SOC_IFC_REG_FUSE_RUNTIME_SVN_2;
+  assign         full_addr_fuse_runtime_svn[3] = `CLP_SOC_IFC_REG_FUSE_RUNTIME_SVN_3;
+
+  logic          hit_fuse_anti_rollback_disable;
+  logic [3:0]    bus_fuse_anti_rollback_disable;
+  logic [31:0]   full_addr_fuse_anti_rollback_disable = `CLP_SOC_IFC_REG_FUSE_ANTI_ROLLBACK_DISABLE;
+
+  logic          hit_fuse_idevid_cert_attr[0:23];
+  logic [3:0]    bus_fuse_idevid_cert_attr[0:23];
+  logic [31:0]   full_addr_fuse_idevid_cert_attr[0:23];
+  assign         full_addr_fuse_idevid_cert_attr[0] = `CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_0;
+  assign         full_addr_fuse_idevid_cert_attr[1] = `CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_1;
+  assign         full_addr_fuse_idevid_cert_attr[2] = `CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_2;
+  assign         full_addr_fuse_idevid_cert_attr[3] = `CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_3;
+  assign         full_addr_fuse_idevid_cert_attr[4] = `CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_4;
+  assign         full_addr_fuse_idevid_cert_attr[5] = `CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_5;
+  assign         full_addr_fuse_idevid_cert_attr[6] = `CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_6;
+  assign         full_addr_fuse_idevid_cert_attr[7] = `CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_7;
+  assign         full_addr_fuse_idevid_cert_attr[8] = `CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_8;
+  assign         full_addr_fuse_idevid_cert_attr[9] = `CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_9;
+  assign         full_addr_fuse_idevid_cert_attr[10] = `CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_10;
+  assign         full_addr_fuse_idevid_cert_attr[11] = `CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_11;
+  assign         full_addr_fuse_idevid_cert_attr[12] = `CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_12;
+  assign         full_addr_fuse_idevid_cert_attr[13] = `CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_13;
+  assign         full_addr_fuse_idevid_cert_attr[14] = `CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_14;
+  assign         full_addr_fuse_idevid_cert_attr[15] = `CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_15;
+  assign         full_addr_fuse_idevid_cert_attr[16] = `CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_16;
+  assign         full_addr_fuse_idevid_cert_attr[17] = `CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_17;
+  assign         full_addr_fuse_idevid_cert_attr[18] = `CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_18;
+  assign         full_addr_fuse_idevid_cert_attr[19] = `CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_19;
+  assign         full_addr_fuse_idevid_cert_attr[20] = `CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_20;
+  assign         full_addr_fuse_idevid_cert_attr[21] = `CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_21;
+  assign         full_addr_fuse_idevid_cert_attr[22] = `CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_22;
+  assign         full_addr_fuse_idevid_cert_attr[23] = `CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_23;
+
+  logic          hit_fuse_idevid_manuf_hsm_id[0:3];
+  logic [3:0]    bus_fuse_idevid_manuf_hsm_id[0:3];
+  logic [31:0]   full_addr_fuse_idevid_manuf_hsm_id[0:3];
+  assign         full_addr_fuse_idevid_manuf_hsm_id[0] = `CLP_SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_0;
+  assign         full_addr_fuse_idevid_manuf_hsm_id[1] = `CLP_SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_1;
+  assign         full_addr_fuse_idevid_manuf_hsm_id[2] = `CLP_SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_2;
+  assign         full_addr_fuse_idevid_manuf_hsm_id[3] = `CLP_SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_3;
+
+  logic          hit_fuse_life_cycle;
+  logic [3:0]    bus_fuse_life_cycle;
+  logic [31:0]   full_addr_fuse_life_cycle = `CLP_SOC_IFC_REG_FUSE_LIFE_CYCLE;
+
+  logic          hit_fuse_lms_verify;
+  logic [3:0]    bus_fuse_lms_verify;
+  logic [31:0]   full_addr_fuse_lms_verify = `CLP_SOC_IFC_REG_FUSE_LMS_VERIFY;
+
+  logic          hit_fuse_lms_revocation;
+  logic [3:0]    bus_fuse_lms_revocation;
+  logic [31:0]   full_addr_fuse_lms_revocation = `CLP_SOC_IFC_REG_FUSE_LMS_REVOCATION;
+
+  logic          hit_fuse_soc_stepping_id;
+  logic [3:0]    bus_fuse_soc_stepping_id;
+  logic [31:0]   full_addr_fuse_soc_stepping_id = `CLP_SOC_IFC_REG_FUSE_SOC_STEPPING_ID;
+
+  logic          hit_internal_obf_key[0:7];
+  logic [3:0]    bus_internal_obf_key[0:7];
+  logic [31:0]   full_addr_internal_obf_key[0:7];
+  assign         full_addr_internal_obf_key[0] = `CLP_SOC_IFC_REG_INTERNAL_OBF_KEY_0;
+  assign         full_addr_internal_obf_key[1] = `CLP_SOC_IFC_REG_INTERNAL_OBF_KEY_1;
+  assign         full_addr_internal_obf_key[2] = `CLP_SOC_IFC_REG_INTERNAL_OBF_KEY_2;
+  assign         full_addr_internal_obf_key[3] = `CLP_SOC_IFC_REG_INTERNAL_OBF_KEY_3;
+  assign         full_addr_internal_obf_key[4] = `CLP_SOC_IFC_REG_INTERNAL_OBF_KEY_4;
+  assign         full_addr_internal_obf_key[5] = `CLP_SOC_IFC_REG_INTERNAL_OBF_KEY_5;
+  assign         full_addr_internal_obf_key[6] = `CLP_SOC_IFC_REG_INTERNAL_OBF_KEY_6;
+  assign         full_addr_internal_obf_key[7] = `CLP_SOC_IFC_REG_INTERNAL_OBF_KEY_7;
+
+  logic          hit_internal_iccm_lock;
+  logic [3:0]    bus_internal_iccm_lock;
+  logic [31:0]   full_addr_internal_iccm_lock = `CLP_SOC_IFC_REG_INTERNAL_ICCM_LOCK;
+
+  logic          hit_internal_fw_update_reset;
+  logic [3:0]    bus_internal_fw_update_reset;
+  logic [31:0]   full_addr_internal_fw_update_reset = `CLP_SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET;
+
+  logic          hit_internal_fw_update_reset_wait_cycles;
+  logic [3:0]    bus_internal_fw_update_reset_wait_cycles;
+  logic [31:0]   full_addr_internal_fw_update_reset_wait_cycles = `CLP_SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES;
+
+  logic          hit_internal_nmi_vector;
+  logic [3:0]    bus_internal_nmi_vector;
+  logic [31:0]   full_addr_internal_nmi_vector = `CLP_SOC_IFC_REG_INTERNAL_NMI_VECTOR;
+
+  logic          hit_internal_hw_error_fatal_mask;
+  logic [3:0]    bus_internal_hw_error_fatal_mask;
+  logic [31:0]   full_addr_internal_hw_error_fatal_mask = `CLP_SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK;
+
+  logic          hit_internal_hw_error_non_fatal_mask;
+  logic [3:0]    bus_internal_hw_error_non_fatal_mask;
+  logic [31:0]   full_addr_internal_hw_error_non_fatal_mask = `CLP_SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK;
+
+  logic          hit_internal_fw_error_fatal_mask;
+  logic [3:0]    bus_internal_fw_error_fatal_mask;
+  logic [31:0]   full_addr_internal_fw_error_fatal_mask = `CLP_SOC_IFC_REG_INTERNAL_FW_ERROR_FATAL_MASK;
+
+  logic          hit_internal_fw_error_non_fatal_mask;
+  logic [3:0]    bus_internal_fw_error_non_fatal_mask;
+  logic [31:0]   full_addr_internal_fw_error_non_fatal_mask = `CLP_SOC_IFC_REG_INTERNAL_FW_ERROR_NON_FATAL_MASK;
+
+  logic          hit_internal_rv_mtime_l;
+  logic [3:0]    bus_internal_rv_mtime_l;
+  logic [31:0]   full_addr_internal_rv_mtime_l = `CLP_SOC_IFC_REG_INTERNAL_RV_MTIME_L;
+
+  logic          hit_internal_rv_mtime_h;
+  logic [3:0]    bus_internal_rv_mtime_h;
+  logic [31:0]   full_addr_internal_rv_mtime_h = `CLP_SOC_IFC_REG_INTERNAL_RV_MTIME_H;
+
+  logic          hit_internal_rv_mtimecmp_l;
+  logic [3:0]    bus_internal_rv_mtimecmp_l;
+  logic [31:0]   full_addr_internal_rv_mtimecmp_l = `CLP_SOC_IFC_REG_INTERNAL_RV_MTIMECMP_L;
+
+  logic          hit_internal_rv_mtimecmp_h;
+  logic [3:0]    bus_internal_rv_mtimecmp_h;
+  logic [31:0]   full_addr_internal_rv_mtimecmp_h = `CLP_SOC_IFC_REG_INTERNAL_RV_MTIMECMP_H;
+
+  logic          hit_intr_brf_global_intr_en_r;
+  logic [3:0]    bus_intr_brf_global_intr_en_r;
+  logic [31:0]   full_addr_intr_brf_global_intr_en_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R;
+
+  logic          hit_intr_brf_error_intr_en_r;
+  logic [3:0]    bus_intr_brf_error_intr_en_r;
+  logic [31:0]   full_addr_intr_brf_error_intr_en_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R;
+
+  logic          hit_intr_brf_notif_intr_en_r;
+  logic [3:0]    bus_intr_brf_notif_intr_en_r;
+  logic [31:0]   full_addr_intr_brf_notif_intr_en_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R;
+
+  logic          hit_intr_brf_error_global_intr_r;
+  logic [3:0]    bus_intr_brf_error_global_intr_r;
+  logic [31:0]   full_addr_intr_brf_error_global_intr_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R;
+
+  logic          hit_intr_brf_notif_global_intr_r;
+  logic [3:0]    bus_intr_brf_notif_global_intr_r;
+  logic [31:0]   full_addr_intr_brf_notif_global_intr_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R;
+
+  logic          hit_intr_brf_error_internal_intr_r;
+  logic [3:0]    bus_intr_brf_error_internal_intr_r;
+  logic [31:0]   full_addr_intr_brf_error_internal_intr_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R;
+
+  logic          hit_intr_brf_notif_internal_intr_r;
+  logic [3:0]    bus_intr_brf_notif_internal_intr_r;
+  logic [31:0]   full_addr_intr_brf_notif_internal_intr_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R;
+
+  logic          hit_intr_brf_error_intr_trig_r;
+  logic [3:0]    bus_intr_brf_error_intr_trig_r;
+  logic [31:0]   full_addr_intr_brf_error_intr_trig_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R;
+
+  logic          hit_intr_brf_notif_intr_trig_r;
+  logic [3:0]    bus_intr_brf_notif_intr_trig_r;
+  logic [31:0]   full_addr_intr_brf_notif_intr_trig_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R;
+
+  logic          hit_intr_brf_error_internal_intr_count_r;
+  logic [3:0]    bus_intr_brf_error_internal_intr_count_r;
+  logic [31:0]   full_addr_intr_brf_error_internal_intr_count_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_R;
+
+  logic          hit_intr_brf_error_inv_dev_intr_count_r;
+  logic [3:0]    bus_intr_brf_error_inv_dev_intr_count_r;
+  logic [31:0]   full_addr_intr_brf_error_inv_dev_intr_count_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INV_DEV_INTR_COUNT_R;
+
+  logic          hit_intr_brf_error_cmd_fail_intr_count_r;
+  logic [3:0]    bus_intr_brf_error_cmd_fail_intr_count_r;
+  logic [31:0]   full_addr_intr_brf_error_cmd_fail_intr_count_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_CMD_FAIL_INTR_COUNT_R;
+
+  logic          hit_intr_brf_error_bad_fuse_intr_count_r;
+  logic [3:0]    bus_intr_brf_error_bad_fuse_intr_count_r;
+  logic [31:0]   full_addr_intr_brf_error_bad_fuse_intr_count_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_BAD_FUSE_INTR_COUNT_R;
+
+  logic          hit_intr_brf_error_iccm_blocked_intr_count_r;
+  logic [3:0]    bus_intr_brf_error_iccm_blocked_intr_count_r;
+  logic [31:0]   full_addr_intr_brf_error_iccm_blocked_intr_count_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_ICCM_BLOCKED_INTR_COUNT_R;
+
+  logic          hit_intr_brf_error_mbox_ecc_unc_intr_count_r;
+  logic [3:0]    bus_intr_brf_error_mbox_ecc_unc_intr_count_r;
+  logic [31:0]   full_addr_intr_brf_error_mbox_ecc_unc_intr_count_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_MBOX_ECC_UNC_INTR_COUNT_R;
+
+  logic          hit_intr_brf_error_wdt_timer1_timeout_intr_count_r;
+  logic [3:0]    bus_intr_brf_error_wdt_timer1_timeout_intr_count_r;
+  logic [31:0]   full_addr_intr_brf_error_wdt_timer1_timeout_intr_count_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_R;
+
+  logic          hit_intr_brf_error_wdt_timer2_timeout_intr_count_r;
+  logic [3:0]    bus_intr_brf_error_wdt_timer2_timeout_intr_count_r;
+  logic [31:0]   full_addr_intr_brf_error_wdt_timer2_timeout_intr_count_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_R;
+
+  logic          hit_intr_brf_notif_cmd_avail_intr_count_r;
+  logic [3:0]    bus_intr_brf_notif_cmd_avail_intr_count_r;
+  logic [31:0]   full_addr_intr_brf_notif_cmd_avail_intr_count_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_CMD_AVAIL_INTR_COUNT_R;
+
+  logic          hit_intr_brf_notif_mbox_ecc_cor_intr_count_r;
+  logic [3:0]    bus_intr_brf_notif_mbox_ecc_cor_intr_count_r;
+  logic [31:0]   full_addr_intr_brf_notif_mbox_ecc_cor_intr_count_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_R;
+
+  logic          hit_intr_brf_notif_debug_locked_intr_count_r;
+  logic [3:0]    bus_intr_brf_notif_debug_locked_intr_count_r;
+  logic [31:0]   full_addr_intr_brf_notif_debug_locked_intr_count_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_R;
+
+  logic          hit_intr_brf_notif_scan_mode_intr_count_r;
+  logic [3:0]    bus_intr_brf_notif_scan_mode_intr_count_r;
+  logic [31:0]   full_addr_intr_brf_notif_scan_mode_intr_count_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_R;
+
+  logic          hit_intr_brf_notif_soc_req_lock_intr_count_r;
+  logic [3:0]    bus_intr_brf_notif_soc_req_lock_intr_count_r;
+  logic [31:0]   full_addr_intr_brf_notif_soc_req_lock_intr_count_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_R;
+
+  logic          hit_intr_brf_notif_gen_in_toggle_intr_count_r;
+  logic [3:0]    bus_intr_brf_notif_gen_in_toggle_intr_count_r;
+  logic [31:0]   full_addr_intr_brf_notif_gen_in_toggle_intr_count_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_R;
+
+  logic          hit_intr_brf_error_internal_intr_count_incr_r;
+  logic [3:0]    bus_intr_brf_error_internal_intr_count_incr_r;
+  logic [31:0]   full_addr_intr_brf_error_internal_intr_count_incr_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R;
+
+  logic          hit_intr_brf_error_inv_dev_intr_count_incr_r;
+  logic [3:0]    bus_intr_brf_error_inv_dev_intr_count_incr_r;
+  logic [31:0]   full_addr_intr_brf_error_inv_dev_intr_count_incr_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INV_DEV_INTR_COUNT_INCR_R;
+
+  logic          hit_intr_brf_error_cmd_fail_intr_count_incr_r;
+  logic [3:0]    bus_intr_brf_error_cmd_fail_intr_count_incr_r;
+  logic [31:0]   full_addr_intr_brf_error_cmd_fail_intr_count_incr_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_CMD_FAIL_INTR_COUNT_INCR_R;
+
+  logic          hit_intr_brf_error_bad_fuse_intr_count_incr_r;
+  logic [3:0]    bus_intr_brf_error_bad_fuse_intr_count_incr_r;
+  logic [31:0]   full_addr_intr_brf_error_bad_fuse_intr_count_incr_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_BAD_FUSE_INTR_COUNT_INCR_R;
+
+  logic          hit_intr_brf_error_iccm_blocked_intr_count_incr_r;
+  logic [3:0]    bus_intr_brf_error_iccm_blocked_intr_count_incr_r;
+  logic [31:0]   full_addr_intr_brf_error_iccm_blocked_intr_count_incr_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_ICCM_BLOCKED_INTR_COUNT_INCR_R;
+
+  logic          hit_intr_brf_error_mbox_ecc_unc_intr_count_incr_r;
+  logic [3:0]    bus_intr_brf_error_mbox_ecc_unc_intr_count_incr_r;
+  logic [31:0]   full_addr_intr_brf_error_mbox_ecc_unc_intr_count_incr_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_MBOX_ECC_UNC_INTR_COUNT_INCR_R;
+
+  logic          hit_intr_brf_error_wdt_timer1_timeout_intr_count_incr_r;
+  logic [3:0]    bus_intr_brf_error_wdt_timer1_timeout_intr_count_incr_r;
+  logic [31:0]   full_addr_intr_brf_error_wdt_timer1_timeout_intr_count_incr_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_INCR_R;
+
+  logic          hit_intr_brf_error_wdt_timer2_timeout_intr_count_incr_r;
+  logic [3:0]    bus_intr_brf_error_wdt_timer2_timeout_intr_count_incr_r;
+  logic [31:0]   full_addr_intr_brf_error_wdt_timer2_timeout_intr_count_incr_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_INCR_R;
+
+  logic          hit_intr_brf_notif_cmd_avail_intr_count_incr_r;
+  logic [3:0]    bus_intr_brf_notif_cmd_avail_intr_count_incr_r;
+  logic [31:0]   full_addr_intr_brf_notif_cmd_avail_intr_count_incr_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_CMD_AVAIL_INTR_COUNT_INCR_R;
+
+  logic          hit_intr_brf_notif_mbox_ecc_cor_intr_count_incr_r;
+  logic [3:0]    bus_intr_brf_notif_mbox_ecc_cor_intr_count_incr_r;
+  logic [31:0]   full_addr_intr_brf_notif_mbox_ecc_cor_intr_count_incr_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_INCR_R;
+
+  logic          hit_intr_brf_notif_debug_locked_intr_count_incr_r;
+  logic [3:0]    bus_intr_brf_notif_debug_locked_intr_count_incr_r;
+  logic [31:0]   full_addr_intr_brf_notif_debug_locked_intr_count_incr_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_INCR_R;
+
+  logic          hit_intr_brf_notif_soc_req_lock_intr_count_incr_r;
+  logic [3:0]    bus_intr_brf_notif_soc_req_lock_intr_count_incr_r;
+  logic [31:0]   full_addr_intr_brf_notif_soc_req_lock_intr_count_incr_r = `CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R;
+
+
+  assign hit_CPTRA_HW_ERROR_FATAL = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_HW_ERROR_FATAL[APB_ADDR_WIDTH-1:0]);
+  assign bus_CPTRA_HW_ERROR_FATAL = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_HW_ERROR_FATAL}};
+
+  assign hit_CPTRA_HW_ERROR_NON_FATAL = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_HW_ERROR_NON_FATAL[APB_ADDR_WIDTH-1:0]);
+  assign bus_CPTRA_HW_ERROR_NON_FATAL = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_HW_ERROR_NON_FATAL}};
+
+  assign hit_CPTRA_FW_ERROR_FATAL = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_FW_ERROR_FATAL[APB_ADDR_WIDTH-1:0]);
+  assign bus_CPTRA_FW_ERROR_FATAL = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_FW_ERROR_FATAL}};
+
+  assign hit_CPTRA_FW_ERROR_NON_FATAL = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_FW_ERROR_NON_FATAL[APB_ADDR_WIDTH-1:0]);
+  assign bus_CPTRA_FW_ERROR_NON_FATAL = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_FW_ERROR_NON_FATAL}};
+
+  assign hit_CPTRA_HW_ERROR_ENC = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_HW_ERROR_ENC[APB_ADDR_WIDTH-1:0]);
+  assign bus_CPTRA_HW_ERROR_ENC = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_HW_ERROR_ENC}};
+
+  assign hit_CPTRA_FW_ERROR_ENC = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_FW_ERROR_ENC[APB_ADDR_WIDTH-1:0]);
+  assign bus_CPTRA_FW_ERROR_ENC = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_FW_ERROR_ENC}};
+
+  assign hit_CPTRA_FW_EXTENDED_ERROR_INFO[0] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_FW_EXTENDED_ERROR_INFO[0][18-1:0]);
+  assign bus_CPTRA_FW_EXTENDED_ERROR_INFO[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_FW_EXTENDED_ERROR_INFO[0]}};
+
+  assign hit_CPTRA_FW_EXTENDED_ERROR_INFO[1] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_FW_EXTENDED_ERROR_INFO[1][18-1:0]);
+  assign bus_CPTRA_FW_EXTENDED_ERROR_INFO[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_FW_EXTENDED_ERROR_INFO[1]}};
+
+  assign hit_CPTRA_FW_EXTENDED_ERROR_INFO[2] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_FW_EXTENDED_ERROR_INFO[2][18-1:0]);
+  assign bus_CPTRA_FW_EXTENDED_ERROR_INFO[2] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_FW_EXTENDED_ERROR_INFO[2]}};
+
+  assign hit_CPTRA_FW_EXTENDED_ERROR_INFO[3] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_FW_EXTENDED_ERROR_INFO[3][18-1:0]);
+  assign bus_CPTRA_FW_EXTENDED_ERROR_INFO[3] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_FW_EXTENDED_ERROR_INFO[3]}};
+
+  assign hit_CPTRA_FW_EXTENDED_ERROR_INFO[4] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_FW_EXTENDED_ERROR_INFO[4][18-1:0]);
+  assign bus_CPTRA_FW_EXTENDED_ERROR_INFO[4] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_FW_EXTENDED_ERROR_INFO[4]}};
+
+  assign hit_CPTRA_FW_EXTENDED_ERROR_INFO[5] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_FW_EXTENDED_ERROR_INFO[5][18-1:0]);
+  assign bus_CPTRA_FW_EXTENDED_ERROR_INFO[5] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_FW_EXTENDED_ERROR_INFO[5]}};
+
+  assign hit_CPTRA_FW_EXTENDED_ERROR_INFO[6] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_FW_EXTENDED_ERROR_INFO[6][18-1:0]);
+  assign bus_CPTRA_FW_EXTENDED_ERROR_INFO[6] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_FW_EXTENDED_ERROR_INFO[6]}};
+
+  assign hit_CPTRA_FW_EXTENDED_ERROR_INFO[7] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_FW_EXTENDED_ERROR_INFO[7][18-1:0]);
+  assign bus_CPTRA_FW_EXTENDED_ERROR_INFO[7] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_FW_EXTENDED_ERROR_INFO[7]}};
+
+  assign hit_CPTRA_BOOT_STATUS = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_BOOT_STATUS[APB_ADDR_WIDTH-1:0]);
+  assign bus_CPTRA_BOOT_STATUS = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_BOOT_STATUS}};
+
+  assign hit_CPTRA_FLOW_STATUS = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_FLOW_STATUS[APB_ADDR_WIDTH-1:0]);
+  assign bus_CPTRA_FLOW_STATUS = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_FLOW_STATUS}};
+
+  assign hit_CPTRA_RESET_REASON = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_RESET_REASON[APB_ADDR_WIDTH-1:0]);
+  assign bus_CPTRA_RESET_REASON = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_RESET_REASON}};
+
+  // assign hit_CPTRA_SECURITY_STATE = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_SECURITY_STATE[APB_ADDR_WIDTH-1:0]);
+  // assign bus_CPTRA_SECURITY_STATE = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_SECURITY_STATE}};
+
+  assign hit_CPTRA_MBOX_VALID_PAUSER[0] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_VALID_PAUSER[0][18-1:0]);
+  assign bus_CPTRA_MBOX_VALID_PAUSER[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_VALID_PAUSER[0]}};
+
+  assign hit_CPTRA_MBOX_VALID_PAUSER[1] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_VALID_PAUSER[1][18-1:0]);
+  assign bus_CPTRA_MBOX_VALID_PAUSER[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_VALID_PAUSER[1]}};
+
+  assign hit_CPTRA_MBOX_VALID_PAUSER[2] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_VALID_PAUSER[2][18-1:0]);
+  assign bus_CPTRA_MBOX_VALID_PAUSER[2] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_VALID_PAUSER[2]}};
+
+  assign hit_CPTRA_MBOX_VALID_PAUSER[3] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_VALID_PAUSER[3][18-1:0]);
+  assign bus_CPTRA_MBOX_VALID_PAUSER[3] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_VALID_PAUSER[3]}};
+
+  assign hit_CPTRA_MBOX_VALID_PAUSER[4] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_VALID_PAUSER[4][18-1:0]);
+  assign bus_CPTRA_MBOX_VALID_PAUSER[4] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_VALID_PAUSER[4]}};
+
+  assign hit_CPTRA_MBOX_PAUSER_LOCK[0] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_PAUSER_LOCK[0][18-1:0]);
+  assign bus_CPTRA_MBOX_PAUSER_LOCK[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_PAUSER_LOCK[0]}};
+
+  assign hit_CPTRA_MBOX_PAUSER_LOCK[1] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_PAUSER_LOCK[1][18-1:0]);
+  assign bus_CPTRA_MBOX_PAUSER_LOCK[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_PAUSER_LOCK[1]}};
+
+  assign hit_CPTRA_MBOX_PAUSER_LOCK[2] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_PAUSER_LOCK[2][18-1:0]);
+  assign bus_CPTRA_MBOX_PAUSER_LOCK[2] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_PAUSER_LOCK[2]}};
+
+  assign hit_CPTRA_MBOX_PAUSER_LOCK[3] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_PAUSER_LOCK[3][18-1:0]);
+  assign bus_CPTRA_MBOX_PAUSER_LOCK[3] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_PAUSER_LOCK[3]}};
+
+  assign hit_CPTRA_MBOX_PAUSER_LOCK[4] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_MBOX_PAUSER_LOCK[4][18-1:0]);
+  assign bus_CPTRA_MBOX_PAUSER_LOCK[4] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_MBOX_PAUSER_LOCK[4]}};
+
+  assign hit_CPTRA_TRNG_VALID_PAUSER = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_TRNG_VALID_PAUSER[APB_ADDR_WIDTH-1:0]);
+  assign bus_CPTRA_TRNG_VALID_PAUSER = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_TRNG_VALID_PAUSER}};
+
+  assign hit_CPTRA_TRNG_PAUSER_LOCK = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_TRNG_PAUSER_LOCK[APB_ADDR_WIDTH-1:0]);
+  assign bus_CPTRA_TRNG_PAUSER_LOCK = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_TRNG_PAUSER_LOCK}};
+
+  assign hit_CPTRA_TRNG_DATA[0] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_TRNG_DATA[0][18-1:0]);
+  assign bus_CPTRA_TRNG_DATA[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_TRNG_DATA[0]}};
+
+  assign hit_CPTRA_TRNG_DATA[1] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_TRNG_DATA[1][18-1:0]);
+  assign bus_CPTRA_TRNG_DATA[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_TRNG_DATA[1]}};
+
+  assign hit_CPTRA_TRNG_DATA[2] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_TRNG_DATA[2][18-1:0]);
+  assign bus_CPTRA_TRNG_DATA[2] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_TRNG_DATA[2]}};
+
+  assign hit_CPTRA_TRNG_DATA[3] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_TRNG_DATA[3][18-1:0]);
+  assign bus_CPTRA_TRNG_DATA[3] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_TRNG_DATA[3]}};
+
+  assign hit_CPTRA_TRNG_DATA[4] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_TRNG_DATA[4][18-1:0]);
+  assign bus_CPTRA_TRNG_DATA[4] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_TRNG_DATA[4]}};
+
+  assign hit_CPTRA_TRNG_DATA[5] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_TRNG_DATA[5][18-1:0]);
+  assign bus_CPTRA_TRNG_DATA[5] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_TRNG_DATA[5]}};
+
+  assign hit_CPTRA_TRNG_DATA[6] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_TRNG_DATA[6][18-1:0]);
+  assign bus_CPTRA_TRNG_DATA[6] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_TRNG_DATA[6]}};
+
+  assign hit_CPTRA_TRNG_DATA[7] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_TRNG_DATA[7][18-1:0]);
+  assign bus_CPTRA_TRNG_DATA[7] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_TRNG_DATA[7]}};
+
+  assign hit_CPTRA_TRNG_DATA[8] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_TRNG_DATA[8][18-1:0]);
+  assign bus_CPTRA_TRNG_DATA[8] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_TRNG_DATA[8]}};
+
+  assign hit_CPTRA_TRNG_DATA[9] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_TRNG_DATA[9][18-1:0]);
+  assign bus_CPTRA_TRNG_DATA[9] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_TRNG_DATA[9]}};
+
+  assign hit_CPTRA_TRNG_DATA[10] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_TRNG_DATA[10][18-1:0]);
+  assign bus_CPTRA_TRNG_DATA[10] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_TRNG_DATA[10]}};
+
+  assign hit_CPTRA_TRNG_DATA[11] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_TRNG_DATA[11][18-1:0]);
+  assign bus_CPTRA_TRNG_DATA[11] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_TRNG_DATA[11]}};
+
+  assign hit_CPTRA_TRNG_CTRL = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_TRNG_CTRL[APB_ADDR_WIDTH-1:0]);
+  assign bus_CPTRA_TRNG_CTRL = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_TRNG_CTRL}};
+
+  assign hit_CPTRA_TRNG_STATUS = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_TRNG_STATUS[APB_ADDR_WIDTH-1:0]);
+  assign bus_CPTRA_TRNG_STATUS = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_TRNG_STATUS}};
+
+  assign hit_CPTRA_FUSE_WR_DONE = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_FUSE_WR_DONE[APB_ADDR_WIDTH-1:0]);
+  assign bus_CPTRA_FUSE_WR_DONE = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_FUSE_WR_DONE}};
+
+  assign hit_CPTRA_TIMER_CONFIG = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_TIMER_CONFIG[APB_ADDR_WIDTH-1:0]);
+  assign bus_CPTRA_TIMER_CONFIG = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_TIMER_CONFIG}};
+
+  assign hit_CPTRA_BOOTFSM_GO = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_BOOTFSM_GO[APB_ADDR_WIDTH-1:0]);
+  assign bus_CPTRA_BOOTFSM_GO = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_BOOTFSM_GO}};
+
+  assign hit_CPTRA_DBG_MANUF_SERVICE_REG = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_DBG_MANUF_SERVICE_REG[APB_ADDR_WIDTH-1:0]);
+  assign bus_CPTRA_DBG_MANUF_SERVICE_REG = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_DBG_MANUF_SERVICE_REG}};
+
+  assign hit_CPTRA_CLK_GATING_EN = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_CLK_GATING_EN[APB_ADDR_WIDTH-1:0]);
+  assign bus_CPTRA_CLK_GATING_EN = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_CLK_GATING_EN}};
+
+  assign hit_CPTRA_GENERIC_INPUT_WIRES[0] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_GENERIC_INPUT_WIRES[0][18-1:0]);
+  assign bus_CPTRA_GENERIC_INPUT_WIRES[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_GENERIC_INPUT_WIRES[0]}};
+
+  assign hit_CPTRA_GENERIC_INPUT_WIRES[1] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_GENERIC_INPUT_WIRES[1][18-1:0]);
+  assign bus_CPTRA_GENERIC_INPUT_WIRES[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_GENERIC_INPUT_WIRES[1]}};
+
+  assign hit_CPTRA_GENERIC_OUTPUT_WIRES[0] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_GENERIC_OUTPUT_WIRES[0][18-1:0]);
+  assign bus_CPTRA_GENERIC_OUTPUT_WIRES[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_GENERIC_OUTPUT_WIRES[0]}};
+
+  assign hit_CPTRA_GENERIC_OUTPUT_WIRES[1] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_GENERIC_OUTPUT_WIRES[1][18-1:0]);
+  assign bus_CPTRA_GENERIC_OUTPUT_WIRES[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_GENERIC_OUTPUT_WIRES[1]}};
+
+  // assign hit_CPTRA_HW_REV_ID = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_HW_REV_ID[APB_ADDR_WIDTH-1:0]);
+  // assign bus_CPTRA_HW_REV_ID = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_HW_REV_ID}};
+
+  assign hit_CPTRA_FW_REV_ID[0] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_FW_REV_ID[0][18-1:0]);
+  assign bus_CPTRA_FW_REV_ID[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_FW_REV_ID[0]}};
+
+  assign hit_CPTRA_FW_REV_ID[1] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_FW_REV_ID[1][18-1:0]);
+  assign bus_CPTRA_FW_REV_ID[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_FW_REV_ID[1]}};
+
+  // assign hit_CPTRA_HW_CONFIG = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_HW_CONFIG[APB_ADDR_WIDTH-1:0]);
+  // assign bus_CPTRA_HW_CONFIG = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_HW_CONFIG}};
+
+  assign hit_CPTRA_WDT_TIMER1_EN = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_WDT_TIMER1_EN[APB_ADDR_WIDTH-1:0]);
+  assign bus_CPTRA_WDT_TIMER1_EN = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_WDT_TIMER1_EN}};
+
+  assign hit_CPTRA_WDT_TIMER1_CTRL = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_WDT_TIMER1_CTRL[APB_ADDR_WIDTH-1:0]);
+  assign bus_CPTRA_WDT_TIMER1_CTRL = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_WDT_TIMER1_CTRL}};
+
+  assign hit_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[0] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[0][18-1:0]);
+  assign bus_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[0]}};
+
+  assign hit_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[1] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[1][18-1:0]);
+  assign bus_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[1]}};
+
+  assign hit_CPTRA_WDT_TIMER2_EN = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_WDT_TIMER2_EN[APB_ADDR_WIDTH-1:0]);
+  assign bus_CPTRA_WDT_TIMER2_EN = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_WDT_TIMER2_EN}};
+
+  assign hit_CPTRA_WDT_TIMER2_CTRL = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_WDT_TIMER2_CTRL[APB_ADDR_WIDTH-1:0]);
+  assign bus_CPTRA_WDT_TIMER2_CTRL = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_WDT_TIMER2_CTRL}};
+
+  assign hit_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[0] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[0][18-1:0]);
+  assign bus_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[0]}};
+
+  assign hit_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[1] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[1][18-1:0]);
+  assign bus_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[1]}};
+
+  assign hit_CPTRA_WDT_STATUS = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_WDT_STATUS[APB_ADDR_WIDTH-1:0]);
+  assign bus_CPTRA_WDT_STATUS = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_WDT_STATUS}};
+
+  assign hit_CPTRA_FUSE_VALID_PAUSER = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_FUSE_VALID_PAUSER[APB_ADDR_WIDTH-1:0]);
+  assign bus_CPTRA_FUSE_VALID_PAUSER = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_FUSE_VALID_PAUSER}};
+
+  assign hit_CPTRA_FUSE_PAUSER_LOCK = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_FUSE_PAUSER_LOCK[APB_ADDR_WIDTH-1:0]);
+  assign bus_CPTRA_FUSE_PAUSER_LOCK = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_FUSE_PAUSER_LOCK}};
+
+  assign hit_CPTRA_WDT_CFG[0] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_WDT_CFG[0][18-1:0]);
+  assign bus_CPTRA_WDT_CFG[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_WDT_CFG[0]}};
+
+  assign hit_CPTRA_WDT_CFG[1] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_WDT_CFG[1][18-1:0]);
+  assign bus_CPTRA_WDT_CFG[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_WDT_CFG[1]}};
+
+  assign hit_CPTRA_iTRNG_ENTROPY_CONFIG_0 = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_iTRNG_ENTROPY_CONFIG_0[APB_ADDR_WIDTH-1:0]);
+  assign bus_CPTRA_iTRNG_ENTROPY_CONFIG_0 = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_iTRNG_ENTROPY_CONFIG_0}};
+
+  assign hit_CPTRA_iTRNG_ENTROPY_CONFIG_1 = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_iTRNG_ENTROPY_CONFIG_1[APB_ADDR_WIDTH-1:0]);
+  assign bus_CPTRA_iTRNG_ENTROPY_CONFIG_1 = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_iTRNG_ENTROPY_CONFIG_1}};
+
+  assign hit_CPTRA_RSVD_REG[0] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_RSVD_REG[0][18-1:0]);
+  assign bus_CPTRA_RSVD_REG[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_RSVD_REG[0]}};
+
+  assign hit_CPTRA_RSVD_REG[1] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_RSVD_REG[1][18-1:0]);
+  assign bus_CPTRA_RSVD_REG[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_RSVD_REG[1]}};
+
+  assign hit_fuse_uds_seed[0] = (soc_ifc_reg_req_data.addr == full_addr_fuse_uds_seed[0][18-1:0]);
+  assign bus_fuse_uds_seed[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_uds_seed[0]}};
+
+  assign hit_fuse_uds_seed[1] = (soc_ifc_reg_req_data.addr == full_addr_fuse_uds_seed[1][18-1:0]);
+  assign bus_fuse_uds_seed[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_uds_seed[1]}};
+
+  assign hit_fuse_uds_seed[2] = (soc_ifc_reg_req_data.addr == full_addr_fuse_uds_seed[2][18-1:0]);
+  assign bus_fuse_uds_seed[2] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_uds_seed[2]}};
+
+  assign hit_fuse_uds_seed[3] = (soc_ifc_reg_req_data.addr == full_addr_fuse_uds_seed[3][18-1:0]);
+  assign bus_fuse_uds_seed[3] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_uds_seed[3]}};
+
+  assign hit_fuse_uds_seed[4] = (soc_ifc_reg_req_data.addr == full_addr_fuse_uds_seed[4][18-1:0]);
+  assign bus_fuse_uds_seed[4] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_uds_seed[4]}};
+
+  assign hit_fuse_uds_seed[5] = (soc_ifc_reg_req_data.addr == full_addr_fuse_uds_seed[5][18-1:0]);
+  assign bus_fuse_uds_seed[5] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_uds_seed[5]}};
+
+  assign hit_fuse_uds_seed[6] = (soc_ifc_reg_req_data.addr == full_addr_fuse_uds_seed[6][18-1:0]);
+  assign bus_fuse_uds_seed[6] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_uds_seed[6]}};
+
+  assign hit_fuse_uds_seed[7] = (soc_ifc_reg_req_data.addr == full_addr_fuse_uds_seed[7][18-1:0]);
+  assign bus_fuse_uds_seed[7] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_uds_seed[7]}};
+
+  assign hit_fuse_uds_seed[8] = (soc_ifc_reg_req_data.addr == full_addr_fuse_uds_seed[8][18-1:0]);
+  assign bus_fuse_uds_seed[8] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_uds_seed[8]}};
+
+  assign hit_fuse_uds_seed[9] = (soc_ifc_reg_req_data.addr == full_addr_fuse_uds_seed[9][18-1:0]);
+  assign bus_fuse_uds_seed[9] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_uds_seed[9]}};
+
+  assign hit_fuse_uds_seed[10] = (soc_ifc_reg_req_data.addr == full_addr_fuse_uds_seed[10][18-1:0]);
+  assign bus_fuse_uds_seed[10] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_uds_seed[10]}};
+
+  assign hit_fuse_uds_seed[11] = (soc_ifc_reg_req_data.addr == full_addr_fuse_uds_seed[11][18-1:0]);
+  assign bus_fuse_uds_seed[11] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_uds_seed[11]}};
+
+  assign hit_fuse_field_entropy[0] = (soc_ifc_reg_req_data.addr == full_addr_fuse_field_entropy[0][18-1:0]);
+  assign bus_fuse_field_entropy[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_field_entropy[0]}};
+
+  assign hit_fuse_field_entropy[1] = (soc_ifc_reg_req_data.addr == full_addr_fuse_field_entropy[1][18-1:0]);
+  assign bus_fuse_field_entropy[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_field_entropy[1]}};
+
+  assign hit_fuse_field_entropy[2] = (soc_ifc_reg_req_data.addr == full_addr_fuse_field_entropy[2][18-1:0]);
+  assign bus_fuse_field_entropy[2] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_field_entropy[2]}};
+
+  assign hit_fuse_field_entropy[3] = (soc_ifc_reg_req_data.addr == full_addr_fuse_field_entropy[3][18-1:0]);
+  assign bus_fuse_field_entropy[3] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_field_entropy[3]}};
+
+  assign hit_fuse_field_entropy[4] = (soc_ifc_reg_req_data.addr == full_addr_fuse_field_entropy[4][18-1:0]);
+  assign bus_fuse_field_entropy[4] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_field_entropy[4]}};
+
+  assign hit_fuse_field_entropy[5] = (soc_ifc_reg_req_data.addr == full_addr_fuse_field_entropy[5][18-1:0]);
+  assign bus_fuse_field_entropy[5] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_field_entropy[5]}};
+
+  assign hit_fuse_field_entropy[6] = (soc_ifc_reg_req_data.addr == full_addr_fuse_field_entropy[6][18-1:0]);
+  assign bus_fuse_field_entropy[6] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_field_entropy[6]}};
+
+  assign hit_fuse_field_entropy[7] = (soc_ifc_reg_req_data.addr == full_addr_fuse_field_entropy[7][18-1:0]);
+  assign bus_fuse_field_entropy[7] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_field_entropy[7]}};
+
+  assign hit_fuse_key_manifest_pk_hash[0] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash[0][18-1:0]);
+  assign bus_fuse_key_manifest_pk_hash[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash[0]}};
+
+  assign hit_fuse_key_manifest_pk_hash[1] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash[1][18-1:0]);
+  assign bus_fuse_key_manifest_pk_hash[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash[1]}};
+
+  assign hit_fuse_key_manifest_pk_hash[2] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash[2][18-1:0]);
+  assign bus_fuse_key_manifest_pk_hash[2] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash[2]}};
+
+  assign hit_fuse_key_manifest_pk_hash[3] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash[3][18-1:0]);
+  assign bus_fuse_key_manifest_pk_hash[3] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash[3]}};
+
+  assign hit_fuse_key_manifest_pk_hash[4] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash[4][18-1:0]);
+  assign bus_fuse_key_manifest_pk_hash[4] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash[4]}};
+
+  assign hit_fuse_key_manifest_pk_hash[5] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash[5][18-1:0]);
+  assign bus_fuse_key_manifest_pk_hash[5] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash[5]}};
+
+  assign hit_fuse_key_manifest_pk_hash[6] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash[6][18-1:0]);
+  assign bus_fuse_key_manifest_pk_hash[6] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash[6]}};
+
+  assign hit_fuse_key_manifest_pk_hash[7] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash[7][18-1:0]);
+  assign bus_fuse_key_manifest_pk_hash[7] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash[7]}};
+
+  assign hit_fuse_key_manifest_pk_hash[8] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash[8][18-1:0]);
+  assign bus_fuse_key_manifest_pk_hash[8] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash[8]}};
+
+  assign hit_fuse_key_manifest_pk_hash[9] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash[9][18-1:0]);
+  assign bus_fuse_key_manifest_pk_hash[9] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash[9]}};
+
+  assign hit_fuse_key_manifest_pk_hash[10] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash[10][18-1:0]);
+  assign bus_fuse_key_manifest_pk_hash[10] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash[10]}};
+
+  assign hit_fuse_key_manifest_pk_hash[11] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash[11][18-1:0]);
+  assign bus_fuse_key_manifest_pk_hash[11] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash[11]}};
+
+  assign hit_fuse_key_manifest_pk_hash_mask = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash_mask[APB_ADDR_WIDTH-1:0]);
+  assign bus_fuse_key_manifest_pk_hash_mask = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash_mask}};
+
+  assign hit_fuse_owner_pk_hash[0] = (soc_ifc_reg_req_data.addr == full_addr_fuse_owner_pk_hash[0][18-1:0]);
+  assign bus_fuse_owner_pk_hash[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_owner_pk_hash[0]}};
+
+  assign hit_fuse_owner_pk_hash[1] = (soc_ifc_reg_req_data.addr == full_addr_fuse_owner_pk_hash[1][18-1:0]);
+  assign bus_fuse_owner_pk_hash[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_owner_pk_hash[1]}};
+
+  assign hit_fuse_owner_pk_hash[2] = (soc_ifc_reg_req_data.addr == full_addr_fuse_owner_pk_hash[2][18-1:0]);
+  assign bus_fuse_owner_pk_hash[2] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_owner_pk_hash[2]}};
+
+  assign hit_fuse_owner_pk_hash[3] = (soc_ifc_reg_req_data.addr == full_addr_fuse_owner_pk_hash[3][18-1:0]);
+  assign bus_fuse_owner_pk_hash[3] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_owner_pk_hash[3]}};
+
+  assign hit_fuse_owner_pk_hash[4] = (soc_ifc_reg_req_data.addr == full_addr_fuse_owner_pk_hash[4][18-1:0]);
+  assign bus_fuse_owner_pk_hash[4] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_owner_pk_hash[4]}};
+
+  assign hit_fuse_owner_pk_hash[5] = (soc_ifc_reg_req_data.addr == full_addr_fuse_owner_pk_hash[5][18-1:0]);
+  assign bus_fuse_owner_pk_hash[5] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_owner_pk_hash[5]}};
+
+  assign hit_fuse_owner_pk_hash[6] = (soc_ifc_reg_req_data.addr == full_addr_fuse_owner_pk_hash[6][18-1:0]);
+  assign bus_fuse_owner_pk_hash[6] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_owner_pk_hash[6]}};
+
+  assign hit_fuse_owner_pk_hash[7] = (soc_ifc_reg_req_data.addr == full_addr_fuse_owner_pk_hash[7][18-1:0]);
+  assign bus_fuse_owner_pk_hash[7] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_owner_pk_hash[7]}};
+
+  assign hit_fuse_owner_pk_hash[8] = (soc_ifc_reg_req_data.addr == full_addr_fuse_owner_pk_hash[8][18-1:0]);
+  assign bus_fuse_owner_pk_hash[8] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_owner_pk_hash[8]}};
+
+  assign hit_fuse_owner_pk_hash[9] = (soc_ifc_reg_req_data.addr == full_addr_fuse_owner_pk_hash[9][18-1:0]);
+  assign bus_fuse_owner_pk_hash[9] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_owner_pk_hash[9]}};
+
+  assign hit_fuse_owner_pk_hash[10] = (soc_ifc_reg_req_data.addr == full_addr_fuse_owner_pk_hash[10][18-1:0]);
+  assign bus_fuse_owner_pk_hash[10] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_owner_pk_hash[10]}};
+
+  assign hit_fuse_owner_pk_hash[11] = (soc_ifc_reg_req_data.addr == full_addr_fuse_owner_pk_hash[11][18-1:0]);
+  assign bus_fuse_owner_pk_hash[11] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_owner_pk_hash[11]}};
+
+  assign hit_fuse_fmc_key_manifest_svn = (soc_ifc_reg_req_data.addr == full_addr_fuse_fmc_key_manifest_svn[APB_ADDR_WIDTH-1:0]);
+  assign bus_fuse_fmc_key_manifest_svn = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_fmc_key_manifest_svn}};
+
+  assign hit_fuse_runtime_svn[0] = (soc_ifc_reg_req_data.addr == full_addr_fuse_runtime_svn[0][18-1:0]);
+  assign bus_fuse_runtime_svn[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_runtime_svn[0]}};
+
+  assign hit_fuse_runtime_svn[1] = (soc_ifc_reg_req_data.addr == full_addr_fuse_runtime_svn[1][18-1:0]);
+  assign bus_fuse_runtime_svn[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_runtime_svn[1]}};
+
+  assign hit_fuse_runtime_svn[2] = (soc_ifc_reg_req_data.addr == full_addr_fuse_runtime_svn[2][18-1:0]);
+  assign bus_fuse_runtime_svn[2] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_runtime_svn[2]}};
+
+  assign hit_fuse_runtime_svn[3] = (soc_ifc_reg_req_data.addr == full_addr_fuse_runtime_svn[3][18-1:0]);
+  assign bus_fuse_runtime_svn[3] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_runtime_svn[3]}};
+
+  assign hit_fuse_anti_rollback_disable = (soc_ifc_reg_req_data.addr == full_addr_fuse_anti_rollback_disable[APB_ADDR_WIDTH-1:0]);
+  assign bus_fuse_anti_rollback_disable = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_anti_rollback_disable}};
+
+  assign hit_fuse_idevid_cert_attr[0] = (soc_ifc_reg_req_data.addr == full_addr_fuse_idevid_cert_attr[0][18-1:0]);
+  assign bus_fuse_idevid_cert_attr[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_idevid_cert_attr[0]}};
+
+  assign hit_fuse_idevid_cert_attr[1] = (soc_ifc_reg_req_data.addr == full_addr_fuse_idevid_cert_attr[1][18-1:0]);
+  assign bus_fuse_idevid_cert_attr[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_idevid_cert_attr[1]}};
+
+  assign hit_fuse_idevid_cert_attr[2] = (soc_ifc_reg_req_data.addr == full_addr_fuse_idevid_cert_attr[2][18-1:0]);
+  assign bus_fuse_idevid_cert_attr[2] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_idevid_cert_attr[2]}};
+
+  assign hit_fuse_idevid_cert_attr[3] = (soc_ifc_reg_req_data.addr == full_addr_fuse_idevid_cert_attr[3][18-1:0]);
+  assign bus_fuse_idevid_cert_attr[3] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_idevid_cert_attr[3]}};
+
+  assign hit_fuse_idevid_cert_attr[4] = (soc_ifc_reg_req_data.addr == full_addr_fuse_idevid_cert_attr[4][18-1:0]);
+  assign bus_fuse_idevid_cert_attr[4] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_idevid_cert_attr[4]}};
+
+  assign hit_fuse_idevid_cert_attr[5] = (soc_ifc_reg_req_data.addr == full_addr_fuse_idevid_cert_attr[5][18-1:0]);
+  assign bus_fuse_idevid_cert_attr[5] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_idevid_cert_attr[5]}};
+
+  assign hit_fuse_idevid_cert_attr[6] = (soc_ifc_reg_req_data.addr == full_addr_fuse_idevid_cert_attr[6][18-1:0]);
+  assign bus_fuse_idevid_cert_attr[6] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_idevid_cert_attr[6]}};
+
+  assign hit_fuse_idevid_cert_attr[7] = (soc_ifc_reg_req_data.addr == full_addr_fuse_idevid_cert_attr[7][18-1:0]);
+  assign bus_fuse_idevid_cert_attr[7] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_idevid_cert_attr[7]}};
+
+  assign hit_fuse_idevid_cert_attr[8] = (soc_ifc_reg_req_data.addr == full_addr_fuse_idevid_cert_attr[8][18-1:0]);
+  assign bus_fuse_idevid_cert_attr[8] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_idevid_cert_attr[8]}};
+
+  assign hit_fuse_idevid_cert_attr[9] = (soc_ifc_reg_req_data.addr == full_addr_fuse_idevid_cert_attr[9][18-1:0]);
+  assign bus_fuse_idevid_cert_attr[9] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_idevid_cert_attr[9]}};
+
+  assign hit_fuse_idevid_cert_attr[10] = (soc_ifc_reg_req_data.addr == full_addr_fuse_idevid_cert_attr[10][18-1:0]);
+  assign bus_fuse_idevid_cert_attr[10] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_idevid_cert_attr[10]}};
+
+  assign hit_fuse_idevid_cert_attr[11] = (soc_ifc_reg_req_data.addr == full_addr_fuse_idevid_cert_attr[11][18-1:0]);
+  assign bus_fuse_idevid_cert_attr[11] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_idevid_cert_attr[11]}};
+
+  assign hit_fuse_idevid_cert_attr[12] = (soc_ifc_reg_req_data.addr == full_addr_fuse_idevid_cert_attr[12][18-1:0]);
+  assign bus_fuse_idevid_cert_attr[12] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_idevid_cert_attr[12]}};
+
+  assign hit_fuse_idevid_cert_attr[13] = (soc_ifc_reg_req_data.addr == full_addr_fuse_idevid_cert_attr[13][18-1:0]);
+  assign bus_fuse_idevid_cert_attr[13] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_idevid_cert_attr[13]}};
+
+  assign hit_fuse_idevid_cert_attr[14] = (soc_ifc_reg_req_data.addr == full_addr_fuse_idevid_cert_attr[14][18-1:0]);
+  assign bus_fuse_idevid_cert_attr[14] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_idevid_cert_attr[14]}};
+
+  assign hit_fuse_idevid_cert_attr[15] = (soc_ifc_reg_req_data.addr == full_addr_fuse_idevid_cert_attr[15][18-1:0]);
+  assign bus_fuse_idevid_cert_attr[15] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_idevid_cert_attr[15]}};
+
+  assign hit_fuse_idevid_cert_attr[16] = (soc_ifc_reg_req_data.addr == full_addr_fuse_idevid_cert_attr[16][18-1:0]);
+  assign bus_fuse_idevid_cert_attr[16] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_idevid_cert_attr[16]}};
+
+  assign hit_fuse_idevid_cert_attr[17] = (soc_ifc_reg_req_data.addr == full_addr_fuse_idevid_cert_attr[17][18-1:0]);
+  assign bus_fuse_idevid_cert_attr[17] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_idevid_cert_attr[17]}};
+
+  assign hit_fuse_idevid_cert_attr[18] = (soc_ifc_reg_req_data.addr == full_addr_fuse_idevid_cert_attr[18][18-1:0]);
+  assign bus_fuse_idevid_cert_attr[18] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_idevid_cert_attr[18]}};
+
+  assign hit_fuse_idevid_cert_attr[19] = (soc_ifc_reg_req_data.addr == full_addr_fuse_idevid_cert_attr[19][18-1:0]);
+  assign bus_fuse_idevid_cert_attr[19] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_idevid_cert_attr[19]}};
+
+  assign hit_fuse_idevid_cert_attr[20] = (soc_ifc_reg_req_data.addr == full_addr_fuse_idevid_cert_attr[20][18-1:0]);
+  assign bus_fuse_idevid_cert_attr[20] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_idevid_cert_attr[20]}};
+
+  assign hit_fuse_idevid_cert_attr[21] = (soc_ifc_reg_req_data.addr == full_addr_fuse_idevid_cert_attr[21][18-1:0]);
+  assign bus_fuse_idevid_cert_attr[21] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_idevid_cert_attr[21]}};
+
+  assign hit_fuse_idevid_cert_attr[22] = (soc_ifc_reg_req_data.addr == full_addr_fuse_idevid_cert_attr[22][18-1:0]);
+  assign bus_fuse_idevid_cert_attr[22] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_idevid_cert_attr[22]}};
+
+  assign hit_fuse_idevid_cert_attr[23] = (soc_ifc_reg_req_data.addr == full_addr_fuse_idevid_cert_attr[23][18-1:0]);
+  assign bus_fuse_idevid_cert_attr[23] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_idevid_cert_attr[23]}};
+
+  assign hit_fuse_idevid_manuf_hsm_id[0] = (soc_ifc_reg_req_data.addr == full_addr_fuse_idevid_manuf_hsm_id[0][18-1:0]);
+  assign bus_fuse_idevid_manuf_hsm_id[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_idevid_manuf_hsm_id[0]}};
+
+  assign hit_fuse_idevid_manuf_hsm_id[1] = (soc_ifc_reg_req_data.addr == full_addr_fuse_idevid_manuf_hsm_id[1][18-1:0]);
+  assign bus_fuse_idevid_manuf_hsm_id[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_idevid_manuf_hsm_id[1]}};
+
+  assign hit_fuse_idevid_manuf_hsm_id[2] = (soc_ifc_reg_req_data.addr == full_addr_fuse_idevid_manuf_hsm_id[2][18-1:0]);
+  assign bus_fuse_idevid_manuf_hsm_id[2] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_idevid_manuf_hsm_id[2]}};
+
+  assign hit_fuse_idevid_manuf_hsm_id[3] = (soc_ifc_reg_req_data.addr == full_addr_fuse_idevid_manuf_hsm_id[3][18-1:0]);
+  assign bus_fuse_idevid_manuf_hsm_id[3] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_idevid_manuf_hsm_id[3]}};
+
+  assign hit_fuse_life_cycle = (soc_ifc_reg_req_data.addr == full_addr_fuse_life_cycle[APB_ADDR_WIDTH-1:0]);
+  assign bus_fuse_life_cycle = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_life_cycle}};
+
+  assign hit_fuse_lms_verify = (soc_ifc_reg_req_data.addr == full_addr_fuse_lms_verify[APB_ADDR_WIDTH-1:0]);
+  assign bus_fuse_lms_verify = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_lms_verify}};
+
+  assign hit_fuse_lms_revocation = (soc_ifc_reg_req_data.addr == full_addr_fuse_lms_revocation[APB_ADDR_WIDTH-1:0]);
+  assign bus_fuse_lms_revocation = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_lms_revocation}};
+
+  assign hit_fuse_soc_stepping_id = (soc_ifc_reg_req_data.addr == full_addr_fuse_soc_stepping_id[APB_ADDR_WIDTH-1:0]);
+  assign bus_fuse_soc_stepping_id = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_soc_stepping_id}};
+
+  assign hit_internal_obf_key[0] = (soc_ifc_reg_req_data.addr == full_addr_internal_obf_key[0][18-1:0]);
+  assign bus_internal_obf_key[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_obf_key[0]}};
+
+  assign hit_internal_obf_key[1] = (soc_ifc_reg_req_data.addr == full_addr_internal_obf_key[1][18-1:0]);
+  assign bus_internal_obf_key[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_obf_key[1]}};
+
+  assign hit_internal_obf_key[2] = (soc_ifc_reg_req_data.addr == full_addr_internal_obf_key[2][18-1:0]);
+  assign bus_internal_obf_key[2] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_obf_key[2]}};
+
+  assign hit_internal_obf_key[3] = (soc_ifc_reg_req_data.addr == full_addr_internal_obf_key[3][18-1:0]);
+  assign bus_internal_obf_key[3] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_obf_key[3]}};
+
+  assign hit_internal_obf_key[4] = (soc_ifc_reg_req_data.addr == full_addr_internal_obf_key[4][18-1:0]);
+  assign bus_internal_obf_key[4] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_obf_key[4]}};
+
+  assign hit_internal_obf_key[5] = (soc_ifc_reg_req_data.addr == full_addr_internal_obf_key[5][18-1:0]);
+  assign bus_internal_obf_key[5] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_obf_key[5]}};
+
+  assign hit_internal_obf_key[6] = (soc_ifc_reg_req_data.addr == full_addr_internal_obf_key[6][18-1:0]);
+  assign bus_internal_obf_key[6] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_obf_key[6]}};
+
+  assign hit_internal_obf_key[7] = (soc_ifc_reg_req_data.addr == full_addr_internal_obf_key[7][18-1:0]);
+  assign bus_internal_obf_key[7] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_obf_key[7]}};
+
+  assign hit_internal_iccm_lock = (soc_ifc_reg_req_data.addr == full_addr_internal_iccm_lock[APB_ADDR_WIDTH-1:0]);
+  assign bus_internal_iccm_lock = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_iccm_lock}};
+
+  assign hit_internal_fw_update_reset = (soc_ifc_reg_req_data.addr == full_addr_internal_fw_update_reset[APB_ADDR_WIDTH-1:0]);
+  assign bus_internal_fw_update_reset = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_fw_update_reset}};
+
+  assign hit_internal_fw_update_reset_wait_cycles = (soc_ifc_reg_req_data.addr == full_addr_internal_fw_update_reset_wait_cycles[APB_ADDR_WIDTH-1:0]);
+  assign bus_internal_fw_update_reset_wait_cycles = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_fw_update_reset_wait_cycles}};
+
+  assign hit_internal_nmi_vector = (soc_ifc_reg_req_data.addr == full_addr_internal_nmi_vector[APB_ADDR_WIDTH-1:0]);
+  assign bus_internal_nmi_vector = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_nmi_vector}};
+
+  assign hit_internal_hw_error_fatal_mask = (soc_ifc_reg_req_data.addr == full_addr_internal_hw_error_fatal_mask[APB_ADDR_WIDTH-1:0]);
+  assign bus_internal_hw_error_fatal_mask = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_hw_error_fatal_mask}};
+
+  assign hit_internal_hw_error_non_fatal_mask = (soc_ifc_reg_req_data.addr == full_addr_internal_hw_error_non_fatal_mask[APB_ADDR_WIDTH-1:0]);
+  assign bus_internal_hw_error_non_fatal_mask = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_hw_error_non_fatal_mask}};
+
+  assign hit_internal_fw_error_fatal_mask = (soc_ifc_reg_req_data.addr == full_addr_internal_fw_error_fatal_mask[APB_ADDR_WIDTH-1:0]);
+  assign bus_internal_fw_error_fatal_mask = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_fw_error_fatal_mask}};
+
+  assign hit_internal_fw_error_non_fatal_mask = (soc_ifc_reg_req_data.addr == full_addr_internal_fw_error_non_fatal_mask[APB_ADDR_WIDTH-1:0]);
+  assign bus_internal_fw_error_non_fatal_mask = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_fw_error_non_fatal_mask}};
+
+  assign hit_internal_rv_mtime_l = (soc_ifc_reg_req_data.addr == full_addr_internal_rv_mtime_l[APB_ADDR_WIDTH-1:0]);
+  assign bus_internal_rv_mtime_l = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_rv_mtime_l}};
+
+  assign hit_internal_rv_mtime_h = (soc_ifc_reg_req_data.addr == full_addr_internal_rv_mtime_h[APB_ADDR_WIDTH-1:0]);
+  assign bus_internal_rv_mtime_h = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_rv_mtime_h}};
+
+  assign hit_internal_rv_mtimecmp_l = (soc_ifc_reg_req_data.addr == full_addr_internal_rv_mtimecmp_l[APB_ADDR_WIDTH-1:0]);
+  assign bus_internal_rv_mtimecmp_l = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_rv_mtimecmp_l}};
+
+  assign hit_internal_rv_mtimecmp_h = (soc_ifc_reg_req_data.addr == full_addr_internal_rv_mtimecmp_h[APB_ADDR_WIDTH-1:0]);
+  assign bus_internal_rv_mtimecmp_h = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_internal_rv_mtimecmp_h}};
+
+  assign hit_intr_brf_global_intr_en_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_global_intr_en_r[APB_ADDR_WIDTH-1:0]);
+  assign bus_intr_brf_global_intr_en_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_global_intr_en_r}};
+
+  assign hit_intr_brf_error_intr_en_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_intr_en_r[APB_ADDR_WIDTH-1:0]);
+  assign bus_intr_brf_error_intr_en_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_intr_en_r}};
+
+  assign hit_intr_brf_notif_intr_en_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_intr_en_r[APB_ADDR_WIDTH-1:0]);
+  assign bus_intr_brf_notif_intr_en_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_intr_en_r}};
+
+  assign hit_intr_brf_error_global_intr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_global_intr_r[APB_ADDR_WIDTH-1:0]);
+  assign bus_intr_brf_error_global_intr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_global_intr_r}};
+
+  assign hit_intr_brf_notif_global_intr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_global_intr_r[APB_ADDR_WIDTH-1:0]);
+  assign bus_intr_brf_notif_global_intr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_global_intr_r}};
+
+  assign hit_intr_brf_error_internal_intr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_internal_intr_r[APB_ADDR_WIDTH-1:0]);
+  assign bus_intr_brf_error_internal_intr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_internal_intr_r}};
+
+  assign hit_intr_brf_notif_internal_intr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_internal_intr_r[APB_ADDR_WIDTH-1:0]);
+  assign bus_intr_brf_notif_internal_intr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_internal_intr_r}};
+
+  assign hit_intr_brf_error_intr_trig_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_intr_trig_r[APB_ADDR_WIDTH-1:0]);
+  assign bus_intr_brf_error_intr_trig_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_intr_trig_r}};
+
+  assign hit_intr_brf_notif_intr_trig_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_intr_trig_r[APB_ADDR_WIDTH-1:0]);
+  assign bus_intr_brf_notif_intr_trig_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_intr_trig_r}};
+
+  assign hit_intr_brf_error_internal_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_internal_intr_count_r[APB_ADDR_WIDTH-1:0]);
+  assign bus_intr_brf_error_internal_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_internal_intr_count_r}};
+
+  assign hit_intr_brf_error_inv_dev_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_inv_dev_intr_count_r[APB_ADDR_WIDTH-1:0]);
+  assign bus_intr_brf_error_inv_dev_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_inv_dev_intr_count_r}};
+
+  assign hit_intr_brf_error_cmd_fail_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_cmd_fail_intr_count_r[APB_ADDR_WIDTH-1:0]);
+  assign bus_intr_brf_error_cmd_fail_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_cmd_fail_intr_count_r}};
+
+  assign hit_intr_brf_error_bad_fuse_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_bad_fuse_intr_count_r[APB_ADDR_WIDTH-1:0]);
+  assign bus_intr_brf_error_bad_fuse_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_bad_fuse_intr_count_r}};
+
+  assign hit_intr_brf_error_iccm_blocked_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_iccm_blocked_intr_count_r[APB_ADDR_WIDTH-1:0]);
+  assign bus_intr_brf_error_iccm_blocked_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_iccm_blocked_intr_count_r}};
+
+  assign hit_intr_brf_error_mbox_ecc_unc_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_mbox_ecc_unc_intr_count_r[APB_ADDR_WIDTH-1:0]);
+  assign bus_intr_brf_error_mbox_ecc_unc_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_mbox_ecc_unc_intr_count_r}};
+
+  assign hit_intr_brf_error_wdt_timer1_timeout_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_wdt_timer1_timeout_intr_count_r[APB_ADDR_WIDTH-1:0]);
+  assign bus_intr_brf_error_wdt_timer1_timeout_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_wdt_timer1_timeout_intr_count_r}};
+
+  assign hit_intr_brf_error_wdt_timer2_timeout_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_wdt_timer2_timeout_intr_count_r[APB_ADDR_WIDTH-1:0]);
+  assign bus_intr_brf_error_wdt_timer2_timeout_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_wdt_timer2_timeout_intr_count_r}};
+
+  assign hit_intr_brf_notif_cmd_avail_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_cmd_avail_intr_count_r[APB_ADDR_WIDTH-1:0]);
+  assign bus_intr_brf_notif_cmd_avail_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_cmd_avail_intr_count_r}};
+
+  assign hit_intr_brf_notif_mbox_ecc_cor_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_mbox_ecc_cor_intr_count_r[APB_ADDR_WIDTH-1:0]);
+  assign bus_intr_brf_notif_mbox_ecc_cor_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_mbox_ecc_cor_intr_count_r}};
+
+  assign hit_intr_brf_notif_debug_locked_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_debug_locked_intr_count_r[APB_ADDR_WIDTH-1:0]);
+  assign bus_intr_brf_notif_debug_locked_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_debug_locked_intr_count_r}};
+
+  assign hit_intr_brf_notif_scan_mode_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_scan_mode_intr_count_r[APB_ADDR_WIDTH-1:0]);
+  assign bus_intr_brf_notif_scan_mode_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_scan_mode_intr_count_r}};
+
+  assign hit_intr_brf_notif_soc_req_lock_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_soc_req_lock_intr_count_r[APB_ADDR_WIDTH-1:0]);
+  assign bus_intr_brf_notif_soc_req_lock_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_soc_req_lock_intr_count_r}};
+
+  assign hit_intr_brf_notif_gen_in_toggle_intr_count_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_gen_in_toggle_intr_count_r[APB_ADDR_WIDTH-1:0]);
+  assign bus_intr_brf_notif_gen_in_toggle_intr_count_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_gen_in_toggle_intr_count_r}};
+
+  assign hit_intr_brf_error_internal_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_internal_intr_count_incr_r[APB_ADDR_WIDTH-1:0]);
+  assign bus_intr_brf_error_internal_intr_count_incr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_internal_intr_count_incr_r}};
+
+  assign hit_intr_brf_error_inv_dev_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_inv_dev_intr_count_incr_r[APB_ADDR_WIDTH-1:0]);
+  assign bus_intr_brf_error_inv_dev_intr_count_incr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_inv_dev_intr_count_incr_r}};
+
+  assign hit_intr_brf_error_cmd_fail_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_cmd_fail_intr_count_incr_r[APB_ADDR_WIDTH-1:0]);
+  assign bus_intr_brf_error_cmd_fail_intr_count_incr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_cmd_fail_intr_count_incr_r}};
+
+  assign hit_intr_brf_error_bad_fuse_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_bad_fuse_intr_count_incr_r[APB_ADDR_WIDTH-1:0]);
+  assign bus_intr_brf_error_bad_fuse_intr_count_incr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_bad_fuse_intr_count_incr_r}};
+
+  assign hit_intr_brf_error_iccm_blocked_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_iccm_blocked_intr_count_incr_r[APB_ADDR_WIDTH-1:0]);
+  assign bus_intr_brf_error_iccm_blocked_intr_count_incr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_iccm_blocked_intr_count_incr_r}};
+
+  assign hit_intr_brf_error_mbox_ecc_unc_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_mbox_ecc_unc_intr_count_incr_r[APB_ADDR_WIDTH-1:0]);
+  assign bus_intr_brf_error_mbox_ecc_unc_intr_count_incr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_mbox_ecc_unc_intr_count_incr_r}};
+
+  assign hit_intr_brf_error_wdt_timer1_timeout_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_wdt_timer1_timeout_intr_count_incr_r[APB_ADDR_WIDTH-1:0]);
+  assign bus_intr_brf_error_wdt_timer1_timeout_intr_count_incr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_wdt_timer1_timeout_intr_count_incr_r}};
+
+  assign hit_intr_brf_error_wdt_timer2_timeout_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_error_wdt_timer2_timeout_intr_count_incr_r[APB_ADDR_WIDTH-1:0]);
+  assign bus_intr_brf_error_wdt_timer2_timeout_intr_count_incr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_error_wdt_timer2_timeout_intr_count_incr_r}};
+
+  assign hit_intr_brf_notif_cmd_avail_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_cmd_avail_intr_count_incr_r[APB_ADDR_WIDTH-1:0]);
+  assign bus_intr_brf_notif_cmd_avail_intr_count_incr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_cmd_avail_intr_count_incr_r}};
+
+  assign hit_intr_brf_notif_mbox_ecc_cor_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_mbox_ecc_cor_intr_count_incr_r[APB_ADDR_WIDTH-1:0]);
+  assign bus_intr_brf_notif_mbox_ecc_cor_intr_count_incr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_mbox_ecc_cor_intr_count_incr_r}};
+
+  assign hit_intr_brf_notif_debug_locked_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_debug_locked_intr_count_incr_r[APB_ADDR_WIDTH-1:0]);
+  assign bus_intr_brf_notif_debug_locked_intr_count_incr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_debug_locked_intr_count_incr_r}};
+
+  assign hit_intr_brf_notif_soc_req_lock_intr_count_incr_r = (soc_ifc_reg_req_data.addr == full_addr_intr_brf_notif_soc_req_lock_intr_count_incr_r[APB_ADDR_WIDTH-1:0]);
+  assign bus_intr_brf_notif_soc_req_lock_intr_count_incr_r = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_intr_brf_notif_soc_req_lock_intr_count_incr_r}};
+
+  // ----------------------- COVERGROUP CPTRA_HW_ERROR_FATAL -----------------------
+  covergroup soc_ifc_CPTRA_HW_ERROR_FATAL_cg (ref logic [3:0] bus_event) @(posedge clk);
+    CPTRA_HW_ERROR_FATAL_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_HW_ERROR_FATAL;
+    bus_CPTRA_HW_ERROR_FATAL_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP CPTRA_HW_ERROR_NON_FATAL -----------------------
+  covergroup soc_ifc_CPTRA_HW_ERROR_NON_FATAL_cg (ref logic [3:0] bus_event) @(posedge clk);
+    CPTRA_HW_ERROR_NON_FATAL_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_HW_ERROR_NON_FATAL;
+    bus_CPTRA_HW_ERROR_NON_FATAL_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP CPTRA_FW_ERROR_FATAL -----------------------
+  covergroup soc_ifc_CPTRA_FW_ERROR_FATAL_cg (ref logic [3:0] bus_event) @(posedge clk);
+    CPTRA_FW_ERROR_FATAL_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_FW_ERROR_FATAL;
+    bus_CPTRA_FW_ERROR_FATAL_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP CPTRA_FW_ERROR_NON_FATAL -----------------------
+  covergroup soc_ifc_CPTRA_FW_ERROR_NON_FATAL_cg (ref logic [3:0] bus_event) @(posedge clk);
+    CPTRA_FW_ERROR_NON_FATAL_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_FW_ERROR_NON_FATAL;
+    bus_CPTRA_FW_ERROR_NON_FATAL_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP CPTRA_HW_ERROR_ENC -----------------------
+  covergroup soc_ifc_CPTRA_HW_ERROR_ENC_cg (ref logic [3:0] bus_event) @(posedge clk);
+    CPTRA_HW_ERROR_ENC_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_HW_ERROR_ENC;
+    bus_CPTRA_HW_ERROR_ENC_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP CPTRA_FW_ERROR_ENC -----------------------
+  covergroup soc_ifc_CPTRA_FW_ERROR_ENC_cg (ref logic [3:0] bus_event) @(posedge clk);
+    CPTRA_FW_ERROR_ENC_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_FW_ERROR_ENC;
+    bus_CPTRA_FW_ERROR_ENC_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP CPTRA_FW_EXTENDED_ERROR_INFO [0:7] -----------------------
+  covergroup soc_ifc_CPTRA_FW_EXTENDED_ERROR_INFO_cg (ref logic [3:0] bus_event[0:7]) @(posedge clk);
+    CPTRA_FW_EXTENDED_ERROR_INFO0_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_FW_EXTENDED_ERROR_INFO[0];
+    bus_CPTRA_FW_EXTENDED_ERROR_INFO0_cp : coverpoint bus_event[0] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    CPTRA_FW_EXTENDED_ERROR_INFO1_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_FW_EXTENDED_ERROR_INFO[1];
+    bus_CPTRA_FW_EXTENDED_ERROR_INFO1_cp : coverpoint bus_event[1] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    CPTRA_FW_EXTENDED_ERROR_INFO2_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_FW_EXTENDED_ERROR_INFO[2];
+    bus_CPTRA_FW_EXTENDED_ERROR_INFO2_cp : coverpoint bus_event[2] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    CPTRA_FW_EXTENDED_ERROR_INFO3_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_FW_EXTENDED_ERROR_INFO[3];
+    bus_CPTRA_FW_EXTENDED_ERROR_INFO3_cp : coverpoint bus_event[3] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    CPTRA_FW_EXTENDED_ERROR_INFO4_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_FW_EXTENDED_ERROR_INFO[4];
+    bus_CPTRA_FW_EXTENDED_ERROR_INFO4_cp : coverpoint bus_event[4] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    CPTRA_FW_EXTENDED_ERROR_INFO5_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_FW_EXTENDED_ERROR_INFO[5];
+    bus_CPTRA_FW_EXTENDED_ERROR_INFO5_cp : coverpoint bus_event[5] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    CPTRA_FW_EXTENDED_ERROR_INFO6_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_FW_EXTENDED_ERROR_INFO[6];
+    bus_CPTRA_FW_EXTENDED_ERROR_INFO6_cp : coverpoint bus_event[6] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    CPTRA_FW_EXTENDED_ERROR_INFO7_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_FW_EXTENDED_ERROR_INFO[7];
+    bus_CPTRA_FW_EXTENDED_ERROR_INFO7_cp : coverpoint bus_event[7] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP CPTRA_BOOT_STATUS -----------------------
+  covergroup soc_ifc_CPTRA_BOOT_STATUS_cg (ref logic [3:0] bus_event) @(posedge clk);
+    CPTRA_BOOT_STATUS_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_BOOT_STATUS;
+    bus_CPTRA_BOOT_STATUS_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP CPTRA_FLOW_STATUS -----------------------
+  covergroup soc_ifc_CPTRA_FLOW_STATUS_cg (ref logic [3:0] bus_event) @(posedge clk);
+    CPTRA_FLOW_STATUS_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_FLOW_STATUS;
+    bus_CPTRA_FLOW_STATUS_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP CPTRA_RESET_REASON -----------------------
+  covergroup soc_ifc_CPTRA_RESET_REASON_cg (ref logic [3:0] bus_event) @(posedge clk);
+    CPTRA_RESET_REASON_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_RESET_REASON;
+    bus_CPTRA_RESET_REASON_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // // ----------------------- COVERGROUP CPTRA_SECURITY_STATE -----------------------
+  // covergroup soc_ifc_CPTRA_SECURITY_STATE_cg (ref logic [3:0] bus_event) @(posedge clk);
+    // CPTRA_SECURITY_STATE_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_SECURITY_STATE;
+    // bus_CPTRA_SECURITY_STATE_cp : coverpoint bus_event {
+      // bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      // ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+  //   }
+  // endgroup
+
+  // ----------------------- COVERGROUP CPTRA_MBOX_VALID_PAUSER [0:4] -----------------------
+  covergroup soc_ifc_CPTRA_MBOX_VALID_PAUSER_cg (ref logic [3:0] bus_event[0:4]) @(posedge clk);
+    CPTRA_MBOX_VALID_PAUSER0_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_VALID_PAUSER[0];
+    bus_CPTRA_MBOX_VALID_PAUSER0_cp : coverpoint bus_event[0] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    CPTRA_MBOX_VALID_PAUSER1_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_VALID_PAUSER[1];
+    bus_CPTRA_MBOX_VALID_PAUSER1_cp : coverpoint bus_event[1] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    CPTRA_MBOX_VALID_PAUSER2_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_VALID_PAUSER[2];
+    bus_CPTRA_MBOX_VALID_PAUSER2_cp : coverpoint bus_event[2] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    CPTRA_MBOX_VALID_PAUSER3_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_VALID_PAUSER[3];
+    bus_CPTRA_MBOX_VALID_PAUSER3_cp : coverpoint bus_event[3] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    CPTRA_MBOX_VALID_PAUSER4_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_VALID_PAUSER[4];
+    bus_CPTRA_MBOX_VALID_PAUSER4_cp : coverpoint bus_event[4] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP CPTRA_MBOX_PAUSER_LOCK [0:4] -----------------------
+  covergroup soc_ifc_CPTRA_MBOX_PAUSER_LOCK_cg (ref logic [3:0] bus_event[0:4]) @(posedge clk);
+    CPTRA_MBOX_PAUSER_LOCK0_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_PAUSER_LOCK[0];
+    bus_CPTRA_MBOX_PAUSER_LOCK0_cp : coverpoint bus_event[0] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    CPTRA_MBOX_PAUSER_LOCK1_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_PAUSER_LOCK[1];
+    bus_CPTRA_MBOX_PAUSER_LOCK1_cp : coverpoint bus_event[1] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    CPTRA_MBOX_PAUSER_LOCK2_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_PAUSER_LOCK[2];
+    bus_CPTRA_MBOX_PAUSER_LOCK2_cp : coverpoint bus_event[2] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    CPTRA_MBOX_PAUSER_LOCK3_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_PAUSER_LOCK[3];
+    bus_CPTRA_MBOX_PAUSER_LOCK3_cp : coverpoint bus_event[3] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    CPTRA_MBOX_PAUSER_LOCK4_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_MBOX_PAUSER_LOCK[4];
+    bus_CPTRA_MBOX_PAUSER_LOCK4_cp : coverpoint bus_event[4] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP CPTRA_TRNG_VALID_PAUSER -----------------------
+  covergroup soc_ifc_CPTRA_TRNG_VALID_PAUSER_cg (ref logic [3:0] bus_event) @(posedge clk);
+    CPTRA_TRNG_VALID_PAUSER_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TRNG_VALID_PAUSER;
+    bus_CPTRA_TRNG_VALID_PAUSER_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP CPTRA_TRNG_PAUSER_LOCK -----------------------
+  covergroup soc_ifc_CPTRA_TRNG_PAUSER_LOCK_cg (ref logic [3:0] bus_event) @(posedge clk);
+    CPTRA_TRNG_PAUSER_LOCK_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TRNG_PAUSER_LOCK;
+    bus_CPTRA_TRNG_PAUSER_LOCK_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP CPTRA_TRNG_DATA [0:11] -----------------------
+  covergroup soc_ifc_CPTRA_TRNG_DATA_cg (ref logic [3:0] bus_event[0:11]) @(posedge clk);
+    CPTRA_TRNG_DATA0_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TRNG_DATA[0];
+    bus_CPTRA_TRNG_DATA0_cp : coverpoint bus_event[0] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    CPTRA_TRNG_DATA1_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TRNG_DATA[1];
+    bus_CPTRA_TRNG_DATA1_cp : coverpoint bus_event[1] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    CPTRA_TRNG_DATA2_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TRNG_DATA[2];
+    bus_CPTRA_TRNG_DATA2_cp : coverpoint bus_event[2] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    CPTRA_TRNG_DATA3_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TRNG_DATA[3];
+    bus_CPTRA_TRNG_DATA3_cp : coverpoint bus_event[3] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    CPTRA_TRNG_DATA4_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TRNG_DATA[4];
+    bus_CPTRA_TRNG_DATA4_cp : coverpoint bus_event[4] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    CPTRA_TRNG_DATA5_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TRNG_DATA[5];
+    bus_CPTRA_TRNG_DATA5_cp : coverpoint bus_event[5] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    CPTRA_TRNG_DATA6_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TRNG_DATA[6];
+    bus_CPTRA_TRNG_DATA6_cp : coverpoint bus_event[6] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    CPTRA_TRNG_DATA7_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TRNG_DATA[7];
+    bus_CPTRA_TRNG_DATA7_cp : coverpoint bus_event[7] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    CPTRA_TRNG_DATA8_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TRNG_DATA[8];
+    bus_CPTRA_TRNG_DATA8_cp : coverpoint bus_event[8] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    CPTRA_TRNG_DATA9_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TRNG_DATA[9];
+    bus_CPTRA_TRNG_DATA9_cp : coverpoint bus_event[9] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    CPTRA_TRNG_DATA10_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TRNG_DATA[10];
+    bus_CPTRA_TRNG_DATA10_cp : coverpoint bus_event[10] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    CPTRA_TRNG_DATA11_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TRNG_DATA[11];
+    bus_CPTRA_TRNG_DATA11_cp : coverpoint bus_event[11] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP CPTRA_TRNG_CTRL -----------------------
+  covergroup soc_ifc_CPTRA_TRNG_CTRL_cg (ref logic [3:0] bus_event) @(posedge clk);
+    CPTRA_TRNG_CTRL_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TRNG_CTRL;
+    bus_CPTRA_TRNG_CTRL_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP CPTRA_TRNG_STATUS -----------------------
+  covergroup soc_ifc_CPTRA_TRNG_STATUS_cg (ref logic [3:0] bus_event) @(posedge clk);
+    CPTRA_TRNG_STATUS_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TRNG_STATUS;
+    bus_CPTRA_TRNG_STATUS_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP CPTRA_FUSE_WR_DONE -----------------------
+  covergroup soc_ifc_CPTRA_FUSE_WR_DONE_cg (ref logic [3:0] bus_event) @(posedge clk);
+    CPTRA_FUSE_WR_DONE_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_FUSE_WR_DONE;
+    bus_CPTRA_FUSE_WR_DONE_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP CPTRA_TIMER_CONFIG -----------------------
+  covergroup soc_ifc_CPTRA_TIMER_CONFIG_cg (ref logic [3:0] bus_event) @(posedge clk);
+    CPTRA_TIMER_CONFIG_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_TIMER_CONFIG;
+    bus_CPTRA_TIMER_CONFIG_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP CPTRA_BOOTFSM_GO -----------------------
+  covergroup soc_ifc_CPTRA_BOOTFSM_GO_cg (ref logic [3:0] bus_event) @(posedge clk);
+    CPTRA_BOOTFSM_GO_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_BOOTFSM_GO;
+    bus_CPTRA_BOOTFSM_GO_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP CPTRA_DBG_MANUF_SERVICE_REG -----------------------
+  covergroup soc_ifc_CPTRA_DBG_MANUF_SERVICE_REG_cg (ref logic [3:0] bus_event) @(posedge clk);
+    CPTRA_DBG_MANUF_SERVICE_REG_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_DBG_MANUF_SERVICE_REG;
+    bus_CPTRA_DBG_MANUF_SERVICE_REG_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP CPTRA_CLK_GATING_EN -----------------------
+  covergroup soc_ifc_CPTRA_CLK_GATING_EN_cg (ref logic [3:0] bus_event) @(posedge clk);
+    CPTRA_CLK_GATING_EN_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_CLK_GATING_EN;
+    bus_CPTRA_CLK_GATING_EN_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP CPTRA_GENERIC_INPUT_WIRES [0:1] -----------------------
+  covergroup soc_ifc_CPTRA_GENERIC_INPUT_WIRES_cg (ref logic [3:0] bus_event[0:1]) @(posedge clk);
+    CPTRA_GENERIC_INPUT_WIRES0_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_GENERIC_INPUT_WIRES[0];
+    bus_CPTRA_GENERIC_INPUT_WIRES0_cp : coverpoint bus_event[0] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    CPTRA_GENERIC_INPUT_WIRES1_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_GENERIC_INPUT_WIRES[1];
+    bus_CPTRA_GENERIC_INPUT_WIRES1_cp : coverpoint bus_event[1] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP CPTRA_GENERIC_OUTPUT_WIRES [0:1] -----------------------
+  covergroup soc_ifc_CPTRA_GENERIC_OUTPUT_WIRES_cg (ref logic [3:0] bus_event[0:1]) @(posedge clk);
+    CPTRA_GENERIC_OUTPUT_WIRES0_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_GENERIC_OUTPUT_WIRES[0];
+    bus_CPTRA_GENERIC_OUTPUT_WIRES0_cp : coverpoint bus_event[0] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    CPTRA_GENERIC_OUTPUT_WIRES1_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_GENERIC_OUTPUT_WIRES[1];
+    bus_CPTRA_GENERIC_OUTPUT_WIRES1_cp : coverpoint bus_event[1] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // // ----------------------- COVERGROUP CPTRA_HW_REV_ID -----------------------
+  // covergroup soc_ifc_CPTRA_HW_REV_ID_cg (ref logic [3:0] bus_event) @(posedge clk);
+    // CPTRA_HW_REV_ID_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_HW_REV_ID;
+    // bus_CPTRA_HW_REV_ID_cp : coverpoint bus_event {
+      // bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      // ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+  //   }
+  // endgroup
+
+  // ----------------------- COVERGROUP CPTRA_FW_REV_ID [0:1] -----------------------
+  covergroup soc_ifc_CPTRA_FW_REV_ID_cg (ref logic [3:0] bus_event[0:1]) @(posedge clk);
+    CPTRA_FW_REV_ID0_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_FW_REV_ID[0];
+    bus_CPTRA_FW_REV_ID0_cp : coverpoint bus_event[0] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    CPTRA_FW_REV_ID1_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_FW_REV_ID[1];
+    bus_CPTRA_FW_REV_ID1_cp : coverpoint bus_event[1] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // // ----------------------- COVERGROUP CPTRA_HW_CONFIG -----------------------
+  // covergroup soc_ifc_CPTRA_HW_CONFIG_cg (ref logic [3:0] bus_event) @(posedge clk);
+    // CPTRA_HW_CONFIG_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_HW_CONFIG;
+    // bus_CPTRA_HW_CONFIG_cp : coverpoint bus_event {
+      // bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      // ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+  //   }
+  // endgroup
+
+  // ----------------------- COVERGROUP CPTRA_WDT_TIMER1_EN -----------------------
+  covergroup soc_ifc_CPTRA_WDT_TIMER1_EN_cg (ref logic [3:0] bus_event) @(posedge clk);
+    CPTRA_WDT_TIMER1_EN_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_WDT_TIMER1_EN;
+    bus_CPTRA_WDT_TIMER1_EN_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP CPTRA_WDT_TIMER1_CTRL -----------------------
+  covergroup soc_ifc_CPTRA_WDT_TIMER1_CTRL_cg (ref logic [3:0] bus_event) @(posedge clk);
+    CPTRA_WDT_TIMER1_CTRL_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_WDT_TIMER1_CTRL;
+    bus_CPTRA_WDT_TIMER1_CTRL_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP CPTRA_WDT_TIMER1_TIMEOUT_PERIOD [0:1] -----------------------
+  covergroup soc_ifc_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_cg (ref logic [3:0] bus_event[0:1]) @(posedge clk);
+    CPTRA_WDT_TIMER1_TIMEOUT_PERIOD0_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[0];
+    bus_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD0_cp : coverpoint bus_event[0] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    CPTRA_WDT_TIMER1_TIMEOUT_PERIOD1_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[1];
+    bus_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD1_cp : coverpoint bus_event[1] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP CPTRA_WDT_TIMER2_EN -----------------------
+  covergroup soc_ifc_CPTRA_WDT_TIMER2_EN_cg (ref logic [3:0] bus_event) @(posedge clk);
+    CPTRA_WDT_TIMER2_EN_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_WDT_TIMER2_EN;
+    bus_CPTRA_WDT_TIMER2_EN_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP CPTRA_WDT_TIMER2_CTRL -----------------------
+  covergroup soc_ifc_CPTRA_WDT_TIMER2_CTRL_cg (ref logic [3:0] bus_event) @(posedge clk);
+    CPTRA_WDT_TIMER2_CTRL_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_WDT_TIMER2_CTRL;
+    bus_CPTRA_WDT_TIMER2_CTRL_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP CPTRA_WDT_TIMER2_TIMEOUT_PERIOD [0:1] -----------------------
+  covergroup soc_ifc_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_cg (ref logic [3:0] bus_event[0:1]) @(posedge clk);
+    CPTRA_WDT_TIMER2_TIMEOUT_PERIOD0_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[0];
+    bus_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD0_cp : coverpoint bus_event[0] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    CPTRA_WDT_TIMER2_TIMEOUT_PERIOD1_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[1];
+    bus_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD1_cp : coverpoint bus_event[1] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP CPTRA_WDT_STATUS -----------------------
+  covergroup soc_ifc_CPTRA_WDT_STATUS_cg (ref logic [3:0] bus_event) @(posedge clk);
+    CPTRA_WDT_STATUS_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_WDT_STATUS;
+    bus_CPTRA_WDT_STATUS_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP CPTRA_FUSE_VALID_PAUSER -----------------------
+  covergroup soc_ifc_CPTRA_FUSE_VALID_PAUSER_cg (ref logic [3:0] bus_event) @(posedge clk);
+    CPTRA_FUSE_VALID_PAUSER_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_FUSE_VALID_PAUSER;
+    bus_CPTRA_FUSE_VALID_PAUSER_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP CPTRA_FUSE_PAUSER_LOCK -----------------------
+  covergroup soc_ifc_CPTRA_FUSE_PAUSER_LOCK_cg (ref logic [3:0] bus_event) @(posedge clk);
+    CPTRA_FUSE_PAUSER_LOCK_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_FUSE_PAUSER_LOCK;
+    bus_CPTRA_FUSE_PAUSER_LOCK_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP CPTRA_WDT_CFG [0:1] -----------------------
+  covergroup soc_ifc_CPTRA_WDT_CFG_cg (ref logic [3:0] bus_event[0:1]) @(posedge clk);
+    CPTRA_WDT_CFG0_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_WDT_CFG[0];
+    bus_CPTRA_WDT_CFG0_cp : coverpoint bus_event[0] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    CPTRA_WDT_CFG1_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_WDT_CFG[1];
+    bus_CPTRA_WDT_CFG1_cp : coverpoint bus_event[1] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP CPTRA_iTRNG_ENTROPY_CONFIG_0 -----------------------
+  covergroup soc_ifc_CPTRA_iTRNG_ENTROPY_CONFIG_0_cg (ref logic [3:0] bus_event) @(posedge clk);
+    CPTRA_iTRNG_ENTROPY_CONFIG_0_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_0;
+    bus_CPTRA_iTRNG_ENTROPY_CONFIG_0_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP CPTRA_iTRNG_ENTROPY_CONFIG_1 -----------------------
+  covergroup soc_ifc_CPTRA_iTRNG_ENTROPY_CONFIG_1_cg (ref logic [3:0] bus_event) @(posedge clk);
+    CPTRA_iTRNG_ENTROPY_CONFIG_1_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_1;
+    bus_CPTRA_iTRNG_ENTROPY_CONFIG_1_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP CPTRA_RSVD_REG [0:1] -----------------------
+  covergroup soc_ifc_CPTRA_RSVD_REG_cg (ref logic [3:0] bus_event[0:1]) @(posedge clk);
+    CPTRA_RSVD_REG0_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_RSVD_REG[0];
+    bus_CPTRA_RSVD_REG0_cp : coverpoint bus_event[0] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    CPTRA_RSVD_REG1_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_RSVD_REG[1];
+    bus_CPTRA_RSVD_REG1_cp : coverpoint bus_event[1] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP fuse_uds_seed [0:11] -----------------------
+  covergroup soc_ifc_fuse_uds_seed_cg (ref logic [3:0] bus_event[0:11]) @(posedge clk);
+    fuse_uds_seed0_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_uds_seed[0];
+    bus_fuse_uds_seed0_cp : coverpoint bus_event[0] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_uds_seed1_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_uds_seed[1];
+    bus_fuse_uds_seed1_cp : coverpoint bus_event[1] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_uds_seed2_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_uds_seed[2];
+    bus_fuse_uds_seed2_cp : coverpoint bus_event[2] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_uds_seed3_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_uds_seed[3];
+    bus_fuse_uds_seed3_cp : coverpoint bus_event[3] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_uds_seed4_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_uds_seed[4];
+    bus_fuse_uds_seed4_cp : coverpoint bus_event[4] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_uds_seed5_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_uds_seed[5];
+    bus_fuse_uds_seed5_cp : coverpoint bus_event[5] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_uds_seed6_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_uds_seed[6];
+    bus_fuse_uds_seed6_cp : coverpoint bus_event[6] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_uds_seed7_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_uds_seed[7];
+    bus_fuse_uds_seed7_cp : coverpoint bus_event[7] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_uds_seed8_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_uds_seed[8];
+    bus_fuse_uds_seed8_cp : coverpoint bus_event[8] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_uds_seed9_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_uds_seed[9];
+    bus_fuse_uds_seed9_cp : coverpoint bus_event[9] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_uds_seed10_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_uds_seed[10];
+    bus_fuse_uds_seed10_cp : coverpoint bus_event[10] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_uds_seed11_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_uds_seed[11];
+    bus_fuse_uds_seed11_cp : coverpoint bus_event[11] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP fuse_field_entropy [0:7] -----------------------
+  covergroup soc_ifc_fuse_field_entropy_cg (ref logic [3:0] bus_event[0:7]) @(posedge clk);
+    fuse_field_entropy0_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_field_entropy[0];
+    bus_fuse_field_entropy0_cp : coverpoint bus_event[0] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_field_entropy1_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_field_entropy[1];
+    bus_fuse_field_entropy1_cp : coverpoint bus_event[1] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_field_entropy2_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_field_entropy[2];
+    bus_fuse_field_entropy2_cp : coverpoint bus_event[2] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_field_entropy3_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_field_entropy[3];
+    bus_fuse_field_entropy3_cp : coverpoint bus_event[3] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_field_entropy4_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_field_entropy[4];
+    bus_fuse_field_entropy4_cp : coverpoint bus_event[4] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_field_entropy5_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_field_entropy[5];
+    bus_fuse_field_entropy5_cp : coverpoint bus_event[5] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_field_entropy6_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_field_entropy[6];
+    bus_fuse_field_entropy6_cp : coverpoint bus_event[6] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_field_entropy7_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_field_entropy[7];
+    bus_fuse_field_entropy7_cp : coverpoint bus_event[7] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP fuse_key_manifest_pk_hash [0:11] -----------------------
+  covergroup soc_ifc_fuse_key_manifest_pk_hash_cg (ref logic [3:0] bus_event[0:11]) @(posedge clk);
+    fuse_key_manifest_pk_hash0_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash[0];
+    bus_fuse_key_manifest_pk_hash0_cp : coverpoint bus_event[0] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_key_manifest_pk_hash1_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash[1];
+    bus_fuse_key_manifest_pk_hash1_cp : coverpoint bus_event[1] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_key_manifest_pk_hash2_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash[2];
+    bus_fuse_key_manifest_pk_hash2_cp : coverpoint bus_event[2] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_key_manifest_pk_hash3_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash[3];
+    bus_fuse_key_manifest_pk_hash3_cp : coverpoint bus_event[3] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_key_manifest_pk_hash4_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash[4];
+    bus_fuse_key_manifest_pk_hash4_cp : coverpoint bus_event[4] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_key_manifest_pk_hash5_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash[5];
+    bus_fuse_key_manifest_pk_hash5_cp : coverpoint bus_event[5] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_key_manifest_pk_hash6_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash[6];
+    bus_fuse_key_manifest_pk_hash6_cp : coverpoint bus_event[6] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_key_manifest_pk_hash7_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash[7];
+    bus_fuse_key_manifest_pk_hash7_cp : coverpoint bus_event[7] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_key_manifest_pk_hash8_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash[8];
+    bus_fuse_key_manifest_pk_hash8_cp : coverpoint bus_event[8] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_key_manifest_pk_hash9_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash[9];
+    bus_fuse_key_manifest_pk_hash9_cp : coverpoint bus_event[9] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_key_manifest_pk_hash10_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash[10];
+    bus_fuse_key_manifest_pk_hash10_cp : coverpoint bus_event[10] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_key_manifest_pk_hash11_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash[11];
+    bus_fuse_key_manifest_pk_hash11_cp : coverpoint bus_event[11] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP fuse_key_manifest_pk_hash_mask -----------------------
+  covergroup soc_ifc_fuse_key_manifest_pk_hash_mask_cg (ref logic [3:0] bus_event) @(posedge clk);
+    fuse_key_manifest_pk_hash_mask_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_key_manifest_pk_hash_mask;
+    bus_fuse_key_manifest_pk_hash_mask_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP fuse_owner_pk_hash [0:11] -----------------------
+  covergroup soc_ifc_fuse_owner_pk_hash_cg (ref logic [3:0] bus_event[0:11]) @(posedge clk);
+    fuse_owner_pk_hash0_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_owner_pk_hash[0];
+    bus_fuse_owner_pk_hash0_cp : coverpoint bus_event[0] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_owner_pk_hash1_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_owner_pk_hash[1];
+    bus_fuse_owner_pk_hash1_cp : coverpoint bus_event[1] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_owner_pk_hash2_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_owner_pk_hash[2];
+    bus_fuse_owner_pk_hash2_cp : coverpoint bus_event[2] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_owner_pk_hash3_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_owner_pk_hash[3];
+    bus_fuse_owner_pk_hash3_cp : coverpoint bus_event[3] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_owner_pk_hash4_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_owner_pk_hash[4];
+    bus_fuse_owner_pk_hash4_cp : coverpoint bus_event[4] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_owner_pk_hash5_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_owner_pk_hash[5];
+    bus_fuse_owner_pk_hash5_cp : coverpoint bus_event[5] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_owner_pk_hash6_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_owner_pk_hash[6];
+    bus_fuse_owner_pk_hash6_cp : coverpoint bus_event[6] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_owner_pk_hash7_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_owner_pk_hash[7];
+    bus_fuse_owner_pk_hash7_cp : coverpoint bus_event[7] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_owner_pk_hash8_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_owner_pk_hash[8];
+    bus_fuse_owner_pk_hash8_cp : coverpoint bus_event[8] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_owner_pk_hash9_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_owner_pk_hash[9];
+    bus_fuse_owner_pk_hash9_cp : coverpoint bus_event[9] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_owner_pk_hash10_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_owner_pk_hash[10];
+    bus_fuse_owner_pk_hash10_cp : coverpoint bus_event[10] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_owner_pk_hash11_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_owner_pk_hash[11];
+    bus_fuse_owner_pk_hash11_cp : coverpoint bus_event[11] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP fuse_fmc_key_manifest_svn -----------------------
+  covergroup soc_ifc_fuse_fmc_key_manifest_svn_cg (ref logic [3:0] bus_event) @(posedge clk);
+    fuse_fmc_key_manifest_svn_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_fmc_key_manifest_svn;
+    bus_fuse_fmc_key_manifest_svn_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP fuse_runtime_svn [0:3] -----------------------
+  covergroup soc_ifc_fuse_runtime_svn_cg (ref logic [3:0] bus_event[0:3]) @(posedge clk);
+    fuse_runtime_svn0_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_runtime_svn[0];
+    bus_fuse_runtime_svn0_cp : coverpoint bus_event[0] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_runtime_svn1_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_runtime_svn[1];
+    bus_fuse_runtime_svn1_cp : coverpoint bus_event[1] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_runtime_svn2_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_runtime_svn[2];
+    bus_fuse_runtime_svn2_cp : coverpoint bus_event[2] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_runtime_svn3_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_runtime_svn[3];
+    bus_fuse_runtime_svn3_cp : coverpoint bus_event[3] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP fuse_anti_rollback_disable -----------------------
+  covergroup soc_ifc_fuse_anti_rollback_disable_cg (ref logic [3:0] bus_event) @(posedge clk);
+    fuse_anti_rollback_disable_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_anti_rollback_disable;
+    bus_fuse_anti_rollback_disable_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP fuse_idevid_cert_attr [0:23] -----------------------
+  covergroup soc_ifc_fuse_idevid_cert_attr_cg (ref logic [3:0] bus_event[0:23]) @(posedge clk);
+    fuse_idevid_cert_attr0_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[0];
+    bus_fuse_idevid_cert_attr0_cp : coverpoint bus_event[0] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_idevid_cert_attr1_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[1];
+    bus_fuse_idevid_cert_attr1_cp : coverpoint bus_event[1] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_idevid_cert_attr2_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[2];
+    bus_fuse_idevid_cert_attr2_cp : coverpoint bus_event[2] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_idevid_cert_attr3_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[3];
+    bus_fuse_idevid_cert_attr3_cp : coverpoint bus_event[3] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_idevid_cert_attr4_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[4];
+    bus_fuse_idevid_cert_attr4_cp : coverpoint bus_event[4] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_idevid_cert_attr5_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[5];
+    bus_fuse_idevid_cert_attr5_cp : coverpoint bus_event[5] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_idevid_cert_attr6_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[6];
+    bus_fuse_idevid_cert_attr6_cp : coverpoint bus_event[6] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_idevid_cert_attr7_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[7];
+    bus_fuse_idevid_cert_attr7_cp : coverpoint bus_event[7] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_idevid_cert_attr8_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[8];
+    bus_fuse_idevid_cert_attr8_cp : coverpoint bus_event[8] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_idevid_cert_attr9_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[9];
+    bus_fuse_idevid_cert_attr9_cp : coverpoint bus_event[9] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_idevid_cert_attr10_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[10];
+    bus_fuse_idevid_cert_attr10_cp : coverpoint bus_event[10] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_idevid_cert_attr11_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[11];
+    bus_fuse_idevid_cert_attr11_cp : coverpoint bus_event[11] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_idevid_cert_attr12_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[12];
+    bus_fuse_idevid_cert_attr12_cp : coverpoint bus_event[12] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_idevid_cert_attr13_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[13];
+    bus_fuse_idevid_cert_attr13_cp : coverpoint bus_event[13] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_idevid_cert_attr14_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[14];
+    bus_fuse_idevid_cert_attr14_cp : coverpoint bus_event[14] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_idevid_cert_attr15_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[15];
+    bus_fuse_idevid_cert_attr15_cp : coverpoint bus_event[15] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_idevid_cert_attr16_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[16];
+    bus_fuse_idevid_cert_attr16_cp : coverpoint bus_event[16] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_idevid_cert_attr17_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[17];
+    bus_fuse_idevid_cert_attr17_cp : coverpoint bus_event[17] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_idevid_cert_attr18_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[18];
+    bus_fuse_idevid_cert_attr18_cp : coverpoint bus_event[18] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_idevid_cert_attr19_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[19];
+    bus_fuse_idevid_cert_attr19_cp : coverpoint bus_event[19] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_idevid_cert_attr20_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[20];
+    bus_fuse_idevid_cert_attr20_cp : coverpoint bus_event[20] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_idevid_cert_attr21_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[21];
+    bus_fuse_idevid_cert_attr21_cp : coverpoint bus_event[21] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_idevid_cert_attr22_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[22];
+    bus_fuse_idevid_cert_attr22_cp : coverpoint bus_event[22] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_idevid_cert_attr23_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_cert_attr[23];
+    bus_fuse_idevid_cert_attr23_cp : coverpoint bus_event[23] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP fuse_idevid_manuf_hsm_id [0:3] -----------------------
+  covergroup soc_ifc_fuse_idevid_manuf_hsm_id_cg (ref logic [3:0] bus_event[0:3]) @(posedge clk);
+    fuse_idevid_manuf_hsm_id0_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_manuf_hsm_id[0];
+    bus_fuse_idevid_manuf_hsm_id0_cp : coverpoint bus_event[0] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_idevid_manuf_hsm_id1_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_manuf_hsm_id[1];
+    bus_fuse_idevid_manuf_hsm_id1_cp : coverpoint bus_event[1] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_idevid_manuf_hsm_id2_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_manuf_hsm_id[2];
+    bus_fuse_idevid_manuf_hsm_id2_cp : coverpoint bus_event[2] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    fuse_idevid_manuf_hsm_id3_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_idevid_manuf_hsm_id[3];
+    bus_fuse_idevid_manuf_hsm_id3_cp : coverpoint bus_event[3] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP fuse_life_cycle -----------------------
+  covergroup soc_ifc_fuse_life_cycle_cg (ref logic [3:0] bus_event) @(posedge clk);
+    fuse_life_cycle_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_life_cycle;
+    bus_fuse_life_cycle_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP fuse_lms_verify -----------------------
+  covergroup soc_ifc_fuse_lms_verify_cg (ref logic [3:0] bus_event) @(posedge clk);
+    fuse_lms_verify_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_lms_verify;
+    bus_fuse_lms_verify_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP fuse_lms_revocation -----------------------
+  covergroup soc_ifc_fuse_lms_revocation_cg (ref logic [3:0] bus_event) @(posedge clk);
+    fuse_lms_revocation_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_lms_revocation;
+    bus_fuse_lms_revocation_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP fuse_soc_stepping_id -----------------------
+  covergroup soc_ifc_fuse_soc_stepping_id_cg (ref logic [3:0] bus_event) @(posedge clk);
+    fuse_soc_stepping_id_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_soc_stepping_id;
+    bus_fuse_soc_stepping_id_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP internal_obf_key [0:7] -----------------------
+  covergroup soc_ifc_internal_obf_key_cg (ref logic [3:0] bus_event[0:7]) @(posedge clk);
+    internal_obf_key0_cp : coverpoint i_soc_ifc_reg.field_storage.internal_obf_key[0];
+    bus_internal_obf_key0_cp : coverpoint bus_event[0] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    internal_obf_key1_cp : coverpoint i_soc_ifc_reg.field_storage.internal_obf_key[1];
+    bus_internal_obf_key1_cp : coverpoint bus_event[1] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    internal_obf_key2_cp : coverpoint i_soc_ifc_reg.field_storage.internal_obf_key[2];
+    bus_internal_obf_key2_cp : coverpoint bus_event[2] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    internal_obf_key3_cp : coverpoint i_soc_ifc_reg.field_storage.internal_obf_key[3];
+    bus_internal_obf_key3_cp : coverpoint bus_event[3] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    internal_obf_key4_cp : coverpoint i_soc_ifc_reg.field_storage.internal_obf_key[4];
+    bus_internal_obf_key4_cp : coverpoint bus_event[4] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    internal_obf_key5_cp : coverpoint i_soc_ifc_reg.field_storage.internal_obf_key[5];
+    bus_internal_obf_key5_cp : coverpoint bus_event[5] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    internal_obf_key6_cp : coverpoint i_soc_ifc_reg.field_storage.internal_obf_key[6];
+    bus_internal_obf_key6_cp : coverpoint bus_event[6] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+    internal_obf_key7_cp : coverpoint i_soc_ifc_reg.field_storage.internal_obf_key[7];
+    bus_internal_obf_key7_cp : coverpoint bus_event[7] {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP internal_iccm_lock -----------------------
+  covergroup soc_ifc_internal_iccm_lock_cg (ref logic [3:0] bus_event) @(posedge clk);
+    internal_iccm_lock_cp : coverpoint i_soc_ifc_reg.field_storage.internal_iccm_lock;
+    bus_internal_iccm_lock_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP internal_fw_update_reset -----------------------
+  covergroup soc_ifc_internal_fw_update_reset_cg (ref logic [3:0] bus_event) @(posedge clk);
+    internal_fw_update_reset_cp : coverpoint i_soc_ifc_reg.field_storage.internal_fw_update_reset;
+    bus_internal_fw_update_reset_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP internal_fw_update_reset_wait_cycles -----------------------
+  covergroup soc_ifc_internal_fw_update_reset_wait_cycles_cg (ref logic [3:0] bus_event) @(posedge clk);
+    internal_fw_update_reset_wait_cycles_cp : coverpoint i_soc_ifc_reg.field_storage.internal_fw_update_reset_wait_cycles;
+    bus_internal_fw_update_reset_wait_cycles_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP internal_nmi_vector -----------------------
+  covergroup soc_ifc_internal_nmi_vector_cg (ref logic [3:0] bus_event) @(posedge clk);
+    internal_nmi_vector_cp : coverpoint i_soc_ifc_reg.field_storage.internal_nmi_vector;
+    bus_internal_nmi_vector_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP internal_hw_error_fatal_mask -----------------------
+  covergroup soc_ifc_internal_hw_error_fatal_mask_cg (ref logic [3:0] bus_event) @(posedge clk);
+    internal_hw_error_fatal_mask_cp : coverpoint i_soc_ifc_reg.field_storage.internal_hw_error_fatal_mask;
+    bus_internal_hw_error_fatal_mask_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP internal_hw_error_non_fatal_mask -----------------------
+  covergroup soc_ifc_internal_hw_error_non_fatal_mask_cg (ref logic [3:0] bus_event) @(posedge clk);
+    internal_hw_error_non_fatal_mask_cp : coverpoint i_soc_ifc_reg.field_storage.internal_hw_error_non_fatal_mask;
+    bus_internal_hw_error_non_fatal_mask_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP internal_fw_error_fatal_mask -----------------------
+  covergroup soc_ifc_internal_fw_error_fatal_mask_cg (ref logic [3:0] bus_event) @(posedge clk);
+    internal_fw_error_fatal_mask_cp : coverpoint i_soc_ifc_reg.field_storage.internal_fw_error_fatal_mask;
+    bus_internal_fw_error_fatal_mask_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP internal_fw_error_non_fatal_mask -----------------------
+  covergroup soc_ifc_internal_fw_error_non_fatal_mask_cg (ref logic [3:0] bus_event) @(posedge clk);
+    internal_fw_error_non_fatal_mask_cp : coverpoint i_soc_ifc_reg.field_storage.internal_fw_error_non_fatal_mask;
+    bus_internal_fw_error_non_fatal_mask_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP internal_rv_mtime_l -----------------------
+  covergroup soc_ifc_internal_rv_mtime_l_cg (ref logic [3:0] bus_event) @(posedge clk);
+    internal_rv_mtime_l_cp : coverpoint i_soc_ifc_reg.field_storage.internal_rv_mtime_l;
+    bus_internal_rv_mtime_l_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP internal_rv_mtime_h -----------------------
+  covergroup soc_ifc_internal_rv_mtime_h_cg (ref logic [3:0] bus_event) @(posedge clk);
+    internal_rv_mtime_h_cp : coverpoint i_soc_ifc_reg.field_storage.internal_rv_mtime_h;
+    bus_internal_rv_mtime_h_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP internal_rv_mtimecmp_l -----------------------
+  covergroup soc_ifc_internal_rv_mtimecmp_l_cg (ref logic [3:0] bus_event) @(posedge clk);
+    internal_rv_mtimecmp_l_cp : coverpoint i_soc_ifc_reg.field_storage.internal_rv_mtimecmp_l;
+    bus_internal_rv_mtimecmp_l_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP internal_rv_mtimecmp_h -----------------------
+  covergroup soc_ifc_internal_rv_mtimecmp_h_cg (ref logic [3:0] bus_event) @(posedge clk);
+    internal_rv_mtimecmp_h_cp : coverpoint i_soc_ifc_reg.field_storage.internal_rv_mtimecmp_h;
+    bus_internal_rv_mtimecmp_h_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP intr_brf_global_intr_en_r -----------------------
+  covergroup soc_ifc_intr_brf_global_intr_en_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+    intr_brf_global_intr_en_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.global_intr_en_r;
+    bus_intr_brf_global_intr_en_r_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP intr_brf_error_intr_en_r -----------------------
+  covergroup soc_ifc_intr_brf_error_intr_en_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+    intr_brf_error_intr_en_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_intr_en_r;
+    bus_intr_brf_error_intr_en_r_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP intr_brf_notif_intr_en_r -----------------------
+  covergroup soc_ifc_intr_brf_notif_intr_en_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+    intr_brf_notif_intr_en_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_en_r;
+    bus_intr_brf_notif_intr_en_r_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP intr_brf_error_global_intr_r -----------------------
+  covergroup soc_ifc_intr_brf_error_global_intr_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+    intr_brf_error_global_intr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_global_intr_r;
+    bus_intr_brf_error_global_intr_r_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP intr_brf_notif_global_intr_r -----------------------
+  covergroup soc_ifc_intr_brf_notif_global_intr_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+    intr_brf_notif_global_intr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_global_intr_r;
+    bus_intr_brf_notif_global_intr_r_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP intr_brf_error_internal_intr_r -----------------------
+  covergroup soc_ifc_intr_brf_error_internal_intr_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+    intr_brf_error_internal_intr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_internal_intr_r;
+    bus_intr_brf_error_internal_intr_r_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP intr_brf_notif_internal_intr_r -----------------------
+  covergroup soc_ifc_intr_brf_notif_internal_intr_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+    intr_brf_notif_internal_intr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_internal_intr_r;
+    bus_intr_brf_notif_internal_intr_r_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP intr_brf_error_intr_trig_r -----------------------
+  covergroup soc_ifc_intr_brf_error_intr_trig_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+    intr_brf_error_intr_trig_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_intr_trig_r;
+    bus_intr_brf_error_intr_trig_r_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP intr_brf_notif_intr_trig_r -----------------------
+  covergroup soc_ifc_intr_brf_notif_intr_trig_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+    intr_brf_notif_intr_trig_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_trig_r;
+    bus_intr_brf_notif_intr_trig_r_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP intr_brf_error_internal_intr_count_r -----------------------
+  covergroup soc_ifc_intr_brf_error_internal_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+    intr_brf_error_internal_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_internal_intr_count_r;
+    bus_intr_brf_error_internal_intr_count_r_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP intr_brf_error_inv_dev_intr_count_r -----------------------
+  covergroup soc_ifc_intr_brf_error_inv_dev_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+    intr_brf_error_inv_dev_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_inv_dev_intr_count_r;
+    bus_intr_brf_error_inv_dev_intr_count_r_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP intr_brf_error_cmd_fail_intr_count_r -----------------------
+  covergroup soc_ifc_intr_brf_error_cmd_fail_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+    intr_brf_error_cmd_fail_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_cmd_fail_intr_count_r;
+    bus_intr_brf_error_cmd_fail_intr_count_r_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP intr_brf_error_bad_fuse_intr_count_r -----------------------
+  covergroup soc_ifc_intr_brf_error_bad_fuse_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+    intr_brf_error_bad_fuse_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_bad_fuse_intr_count_r;
+    bus_intr_brf_error_bad_fuse_intr_count_r_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP intr_brf_error_iccm_blocked_intr_count_r -----------------------
+  covergroup soc_ifc_intr_brf_error_iccm_blocked_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+    intr_brf_error_iccm_blocked_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_iccm_blocked_intr_count_r;
+    bus_intr_brf_error_iccm_blocked_intr_count_r_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP intr_brf_error_mbox_ecc_unc_intr_count_r -----------------------
+  covergroup soc_ifc_intr_brf_error_mbox_ecc_unc_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+    intr_brf_error_mbox_ecc_unc_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_r;
+    bus_intr_brf_error_mbox_ecc_unc_intr_count_r_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP intr_brf_error_wdt_timer1_timeout_intr_count_r -----------------------
+  covergroup soc_ifc_intr_brf_error_wdt_timer1_timeout_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+    intr_brf_error_wdt_timer1_timeout_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_r;
+    bus_intr_brf_error_wdt_timer1_timeout_intr_count_r_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP intr_brf_error_wdt_timer2_timeout_intr_count_r -----------------------
+  covergroup soc_ifc_intr_brf_error_wdt_timer2_timeout_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+    intr_brf_error_wdt_timer2_timeout_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_r;
+    bus_intr_brf_error_wdt_timer2_timeout_intr_count_r_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP intr_brf_notif_cmd_avail_intr_count_r -----------------------
+  covergroup soc_ifc_intr_brf_notif_cmd_avail_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+    intr_brf_notif_cmd_avail_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_cmd_avail_intr_count_r;
+    bus_intr_brf_notif_cmd_avail_intr_count_r_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP intr_brf_notif_mbox_ecc_cor_intr_count_r -----------------------
+  covergroup soc_ifc_intr_brf_notif_mbox_ecc_cor_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+    intr_brf_notif_mbox_ecc_cor_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_r;
+    bus_intr_brf_notif_mbox_ecc_cor_intr_count_r_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP intr_brf_notif_debug_locked_intr_count_r -----------------------
+  covergroup soc_ifc_intr_brf_notif_debug_locked_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+    intr_brf_notif_debug_locked_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_debug_locked_intr_count_r;
+    bus_intr_brf_notif_debug_locked_intr_count_r_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP intr_brf_notif_scan_mode_intr_count_r -----------------------
+  covergroup soc_ifc_intr_brf_notif_scan_mode_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+    intr_brf_notif_scan_mode_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_scan_mode_intr_count_r;
+    bus_intr_brf_notif_scan_mode_intr_count_r_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP intr_brf_notif_soc_req_lock_intr_count_r -----------------------
+  covergroup soc_ifc_intr_brf_notif_soc_req_lock_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+    intr_brf_notif_soc_req_lock_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_soc_req_lock_intr_count_r;
+    bus_intr_brf_notif_soc_req_lock_intr_count_r_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP intr_brf_notif_gen_in_toggle_intr_count_r -----------------------
+  covergroup soc_ifc_intr_brf_notif_gen_in_toggle_intr_count_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+    intr_brf_notif_gen_in_toggle_intr_count_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_r;
+    bus_intr_brf_notif_gen_in_toggle_intr_count_r_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP intr_brf_error_internal_intr_count_incr_r -----------------------
+  covergroup soc_ifc_intr_brf_error_internal_intr_count_incr_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+    intr_brf_error_internal_intr_count_incr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_internal_intr_count_incr_r;
+    bus_intr_brf_error_internal_intr_count_incr_r_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP intr_brf_error_inv_dev_intr_count_incr_r -----------------------
+  covergroup soc_ifc_intr_brf_error_inv_dev_intr_count_incr_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+    intr_brf_error_inv_dev_intr_count_incr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_inv_dev_intr_count_incr_r;
+    bus_intr_brf_error_inv_dev_intr_count_incr_r_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP intr_brf_error_cmd_fail_intr_count_incr_r -----------------------
+  covergroup soc_ifc_intr_brf_error_cmd_fail_intr_count_incr_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+    intr_brf_error_cmd_fail_intr_count_incr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_cmd_fail_intr_count_incr_r;
+    bus_intr_brf_error_cmd_fail_intr_count_incr_r_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP intr_brf_error_bad_fuse_intr_count_incr_r -----------------------
+  covergroup soc_ifc_intr_brf_error_bad_fuse_intr_count_incr_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+    intr_brf_error_bad_fuse_intr_count_incr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_bad_fuse_intr_count_incr_r;
+    bus_intr_brf_error_bad_fuse_intr_count_incr_r_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP intr_brf_error_iccm_blocked_intr_count_incr_r -----------------------
+  covergroup soc_ifc_intr_brf_error_iccm_blocked_intr_count_incr_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+    intr_brf_error_iccm_blocked_intr_count_incr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_iccm_blocked_intr_count_incr_r;
+    bus_intr_brf_error_iccm_blocked_intr_count_incr_r_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP intr_brf_error_mbox_ecc_unc_intr_count_incr_r -----------------------
+  covergroup soc_ifc_intr_brf_error_mbox_ecc_unc_intr_count_incr_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+    intr_brf_error_mbox_ecc_unc_intr_count_incr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r;
+    bus_intr_brf_error_mbox_ecc_unc_intr_count_incr_r_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP intr_brf_error_wdt_timer1_timeout_intr_count_incr_r -----------------------
+  covergroup soc_ifc_intr_brf_error_wdt_timer1_timeout_intr_count_incr_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+    intr_brf_error_wdt_timer1_timeout_intr_count_incr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r;
+    bus_intr_brf_error_wdt_timer1_timeout_intr_count_incr_r_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP intr_brf_error_wdt_timer2_timeout_intr_count_incr_r -----------------------
+  covergroup soc_ifc_intr_brf_error_wdt_timer2_timeout_intr_count_incr_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+    intr_brf_error_wdt_timer2_timeout_intr_count_incr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r;
+    bus_intr_brf_error_wdt_timer2_timeout_intr_count_incr_r_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP intr_brf_notif_cmd_avail_intr_count_incr_r -----------------------
+  covergroup soc_ifc_intr_brf_notif_cmd_avail_intr_count_incr_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+    intr_brf_notif_cmd_avail_intr_count_incr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_cmd_avail_intr_count_incr_r;
+    bus_intr_brf_notif_cmd_avail_intr_count_incr_r_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP intr_brf_notif_mbox_ecc_cor_intr_count_incr_r -----------------------
+  covergroup soc_ifc_intr_brf_notif_mbox_ecc_cor_intr_count_incr_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+    intr_brf_notif_mbox_ecc_cor_intr_count_incr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r;
+    bus_intr_brf_notif_mbox_ecc_cor_intr_count_incr_r_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP intr_brf_notif_debug_locked_intr_count_incr_r -----------------------
+  covergroup soc_ifc_intr_brf_notif_debug_locked_intr_count_incr_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+    intr_brf_notif_debug_locked_intr_count_incr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_debug_locked_intr_count_incr_r;
+    bus_intr_brf_notif_debug_locked_intr_count_incr_r_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+  // ----------------------- COVERGROUP intr_brf_notif_soc_req_lock_intr_count_incr_r -----------------------
+  covergroup soc_ifc_intr_brf_notif_soc_req_lock_intr_count_incr_r_cg (ref logic [3:0] bus_event) @(posedge clk);
+    intr_brf_notif_soc_req_lock_intr_count_incr_r_cp : coverpoint i_soc_ifc_reg.field_storage.intr_block_rf.notif_soc_req_lock_intr_count_incr_r;
+    bus_intr_brf_notif_soc_req_lock_intr_count_incr_r_cp : coverpoint bus_event {
+      bins wr_rd[] = (AHB_WR, APB_WR => IDLE [*1:1000] => AHB_RD, APB_RD);
+      ignore_bins dont_care = {IDLE, 4'hf, (APB_RD | APB_WR), (AHB_RD | AHB_WR)};
+    }
+  endgroup
+
+
+  // ----------------------- COVERGROUP Instantiations -----------------------
+
+  soc_ifc_CPTRA_HW_ERROR_FATAL_cg CPTRA_HW_ERROR_FATAL_cg = new(bus_CPTRA_HW_ERROR_FATAL);
+  soc_ifc_CPTRA_HW_ERROR_NON_FATAL_cg CPTRA_HW_ERROR_NON_FATAL_cg = new(bus_CPTRA_HW_ERROR_NON_FATAL);
+  soc_ifc_CPTRA_FW_ERROR_FATAL_cg CPTRA_FW_ERROR_FATAL_cg = new(bus_CPTRA_FW_ERROR_FATAL);
+  soc_ifc_CPTRA_FW_ERROR_NON_FATAL_cg CPTRA_FW_ERROR_NON_FATAL_cg = new(bus_CPTRA_FW_ERROR_NON_FATAL);
+  soc_ifc_CPTRA_HW_ERROR_ENC_cg CPTRA_HW_ERROR_ENC_cg = new(bus_CPTRA_HW_ERROR_ENC);
+  soc_ifc_CPTRA_FW_ERROR_ENC_cg CPTRA_FW_ERROR_ENC_cg = new(bus_CPTRA_FW_ERROR_ENC);
+  soc_ifc_CPTRA_FW_EXTENDED_ERROR_INFO_cg CPTRA_FW_EXTENDED_ERROR_INFO_cg = new(bus_CPTRA_FW_EXTENDED_ERROR_INFO);
+  soc_ifc_CPTRA_BOOT_STATUS_cg CPTRA_BOOT_STATUS_cg = new(bus_CPTRA_BOOT_STATUS);
+  soc_ifc_CPTRA_FLOW_STATUS_cg CPTRA_FLOW_STATUS_cg = new(bus_CPTRA_FLOW_STATUS);
+  soc_ifc_CPTRA_RESET_REASON_cg CPTRA_RESET_REASON_cg = new(bus_CPTRA_RESET_REASON);
+  // soc_ifc_CPTRA_SECURITY_STATE_cg CPTRA_SECURITY_STATE_cg = new(bus_CPTRA_SECURITY_STATE);
+  soc_ifc_CPTRA_MBOX_VALID_PAUSER_cg CPTRA_MBOX_VALID_PAUSER_cg = new(bus_CPTRA_MBOX_VALID_PAUSER);
+  soc_ifc_CPTRA_MBOX_PAUSER_LOCK_cg CPTRA_MBOX_PAUSER_LOCK_cg = new(bus_CPTRA_MBOX_PAUSER_LOCK);
+  soc_ifc_CPTRA_TRNG_VALID_PAUSER_cg CPTRA_TRNG_VALID_PAUSER_cg = new(bus_CPTRA_TRNG_VALID_PAUSER);
+  soc_ifc_CPTRA_TRNG_PAUSER_LOCK_cg CPTRA_TRNG_PAUSER_LOCK_cg = new(bus_CPTRA_TRNG_PAUSER_LOCK);
+  soc_ifc_CPTRA_TRNG_DATA_cg CPTRA_TRNG_DATA_cg = new(bus_CPTRA_TRNG_DATA);
+  soc_ifc_CPTRA_TRNG_CTRL_cg CPTRA_TRNG_CTRL_cg = new(bus_CPTRA_TRNG_CTRL);
+  soc_ifc_CPTRA_TRNG_STATUS_cg CPTRA_TRNG_STATUS_cg = new(bus_CPTRA_TRNG_STATUS);
+  soc_ifc_CPTRA_FUSE_WR_DONE_cg CPTRA_FUSE_WR_DONE_cg = new(bus_CPTRA_FUSE_WR_DONE);
+  soc_ifc_CPTRA_TIMER_CONFIG_cg CPTRA_TIMER_CONFIG_cg = new(bus_CPTRA_TIMER_CONFIG);
+  soc_ifc_CPTRA_BOOTFSM_GO_cg CPTRA_BOOTFSM_GO_cg = new(bus_CPTRA_BOOTFSM_GO);
+  soc_ifc_CPTRA_DBG_MANUF_SERVICE_REG_cg CPTRA_DBG_MANUF_SERVICE_REG_cg = new(bus_CPTRA_DBG_MANUF_SERVICE_REG);
+  soc_ifc_CPTRA_CLK_GATING_EN_cg CPTRA_CLK_GATING_EN_cg = new(bus_CPTRA_CLK_GATING_EN);
+  soc_ifc_CPTRA_GENERIC_INPUT_WIRES_cg CPTRA_GENERIC_INPUT_WIRES_cg = new(bus_CPTRA_GENERIC_INPUT_WIRES);
+  soc_ifc_CPTRA_GENERIC_OUTPUT_WIRES_cg CPTRA_GENERIC_OUTPUT_WIRES_cg = new(bus_CPTRA_GENERIC_OUTPUT_WIRES);
+  // soc_ifc_CPTRA_HW_REV_ID_cg CPTRA_HW_REV_ID_cg = new(bus_CPTRA_HW_REV_ID);
+  soc_ifc_CPTRA_FW_REV_ID_cg CPTRA_FW_REV_ID_cg = new(bus_CPTRA_FW_REV_ID);
+  // soc_ifc_CPTRA_HW_CONFIG_cg CPTRA_HW_CONFIG_cg = new(bus_CPTRA_HW_CONFIG);
+  soc_ifc_CPTRA_WDT_TIMER1_EN_cg CPTRA_WDT_TIMER1_EN_cg = new(bus_CPTRA_WDT_TIMER1_EN);
+  soc_ifc_CPTRA_WDT_TIMER1_CTRL_cg CPTRA_WDT_TIMER1_CTRL_cg = new(bus_CPTRA_WDT_TIMER1_CTRL);
+  soc_ifc_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_cg CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_cg = new(bus_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD);
+  soc_ifc_CPTRA_WDT_TIMER2_EN_cg CPTRA_WDT_TIMER2_EN_cg = new(bus_CPTRA_WDT_TIMER2_EN);
+  soc_ifc_CPTRA_WDT_TIMER2_CTRL_cg CPTRA_WDT_TIMER2_CTRL_cg = new(bus_CPTRA_WDT_TIMER2_CTRL);
+  soc_ifc_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_cg CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_cg = new(bus_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD);
+  soc_ifc_CPTRA_WDT_STATUS_cg CPTRA_WDT_STATUS_cg = new(bus_CPTRA_WDT_STATUS);
+  soc_ifc_CPTRA_FUSE_VALID_PAUSER_cg CPTRA_FUSE_VALID_PAUSER_cg = new(bus_CPTRA_FUSE_VALID_PAUSER);
+  soc_ifc_CPTRA_FUSE_PAUSER_LOCK_cg CPTRA_FUSE_PAUSER_LOCK_cg = new(bus_CPTRA_FUSE_PAUSER_LOCK);
+  soc_ifc_CPTRA_WDT_CFG_cg CPTRA_WDT_CFG_cg = new(bus_CPTRA_WDT_CFG);
+  soc_ifc_CPTRA_iTRNG_ENTROPY_CONFIG_0_cg CPTRA_iTRNG_ENTROPY_CONFIG_0_cg = new(bus_CPTRA_iTRNG_ENTROPY_CONFIG_0);
+  soc_ifc_CPTRA_iTRNG_ENTROPY_CONFIG_1_cg CPTRA_iTRNG_ENTROPY_CONFIG_1_cg = new(bus_CPTRA_iTRNG_ENTROPY_CONFIG_1);
+  soc_ifc_CPTRA_RSVD_REG_cg CPTRA_RSVD_REG_cg = new(bus_CPTRA_RSVD_REG);
+  soc_ifc_fuse_uds_seed_cg fuse_uds_seed_cg = new(bus_fuse_uds_seed);
+  soc_ifc_fuse_field_entropy_cg fuse_field_entropy_cg = new(bus_fuse_field_entropy);
+  soc_ifc_fuse_key_manifest_pk_hash_cg fuse_key_manifest_pk_hash_cg = new(bus_fuse_key_manifest_pk_hash);
+  soc_ifc_fuse_key_manifest_pk_hash_mask_cg fuse_key_manifest_pk_hash_mask_cg = new(bus_fuse_key_manifest_pk_hash_mask);
+  soc_ifc_fuse_owner_pk_hash_cg fuse_owner_pk_hash_cg = new(bus_fuse_owner_pk_hash);
+  soc_ifc_fuse_fmc_key_manifest_svn_cg fuse_fmc_key_manifest_svn_cg = new(bus_fuse_fmc_key_manifest_svn);
+  soc_ifc_fuse_runtime_svn_cg fuse_runtime_svn_cg = new(bus_fuse_runtime_svn);
+  soc_ifc_fuse_anti_rollback_disable_cg fuse_anti_rollback_disable_cg = new(bus_fuse_anti_rollback_disable);
+  soc_ifc_fuse_idevid_cert_attr_cg fuse_idevid_cert_attr_cg = new(bus_fuse_idevid_cert_attr);
+  soc_ifc_fuse_idevid_manuf_hsm_id_cg fuse_idevid_manuf_hsm_id_cg = new(bus_fuse_idevid_manuf_hsm_id);
+  soc_ifc_fuse_life_cycle_cg fuse_life_cycle_cg = new(bus_fuse_life_cycle);
+  soc_ifc_fuse_lms_verify_cg fuse_lms_verify_cg = new(bus_fuse_lms_verify);
+  soc_ifc_fuse_lms_revocation_cg fuse_lms_revocation_cg = new(bus_fuse_lms_revocation);
+  soc_ifc_fuse_soc_stepping_id_cg fuse_soc_stepping_id_cg = new(bus_fuse_soc_stepping_id);
+  soc_ifc_internal_obf_key_cg internal_obf_key_cg = new(bus_internal_obf_key);
+  soc_ifc_internal_iccm_lock_cg internal_iccm_lock_cg = new(bus_internal_iccm_lock);
+  soc_ifc_internal_fw_update_reset_cg internal_fw_update_reset_cg = new(bus_internal_fw_update_reset);
+  soc_ifc_internal_fw_update_reset_wait_cycles_cg internal_fw_update_reset_wait_cycles_cg = new(bus_internal_fw_update_reset_wait_cycles);
+  soc_ifc_internal_nmi_vector_cg internal_nmi_vector_cg = new(bus_internal_nmi_vector);
+  soc_ifc_internal_hw_error_fatal_mask_cg internal_hw_error_fatal_mask_cg = new(bus_internal_hw_error_fatal_mask);
+  soc_ifc_internal_hw_error_non_fatal_mask_cg internal_hw_error_non_fatal_mask_cg = new(bus_internal_hw_error_non_fatal_mask);
+  soc_ifc_internal_fw_error_fatal_mask_cg internal_fw_error_fatal_mask_cg = new(bus_internal_fw_error_fatal_mask);
+  soc_ifc_internal_fw_error_non_fatal_mask_cg internal_fw_error_non_fatal_mask_cg = new(bus_internal_fw_error_non_fatal_mask);
+  soc_ifc_internal_rv_mtime_l_cg internal_rv_mtime_l_cg = new(bus_internal_rv_mtime_l);
+  soc_ifc_internal_rv_mtime_h_cg internal_rv_mtime_h_cg = new(bus_internal_rv_mtime_h);
+  soc_ifc_internal_rv_mtimecmp_l_cg internal_rv_mtimecmp_l_cg = new(bus_internal_rv_mtimecmp_l);
+  soc_ifc_internal_rv_mtimecmp_h_cg internal_rv_mtimecmp_h_cg = new(bus_internal_rv_mtimecmp_h);
+  soc_ifc_intr_brf_global_intr_en_r_cg intr_brf_global_intr_en_r_cg = new(bus_intr_brf_global_intr_en_r);
+  soc_ifc_intr_brf_error_intr_en_r_cg intr_brf_error_intr_en_r_cg = new(bus_intr_brf_error_intr_en_r);
+  soc_ifc_intr_brf_notif_intr_en_r_cg intr_brf_notif_intr_en_r_cg = new(bus_intr_brf_notif_intr_en_r);
+  soc_ifc_intr_brf_error_global_intr_r_cg intr_brf_error_global_intr_r_cg = new(bus_intr_brf_error_global_intr_r);
+  soc_ifc_intr_brf_notif_global_intr_r_cg intr_brf_notif_global_intr_r_cg = new(bus_intr_brf_notif_global_intr_r);
+  soc_ifc_intr_brf_error_internal_intr_r_cg intr_brf_error_internal_intr_r_cg = new(bus_intr_brf_error_internal_intr_r);
+  soc_ifc_intr_brf_notif_internal_intr_r_cg intr_brf_notif_internal_intr_r_cg = new(bus_intr_brf_notif_internal_intr_r);
+  soc_ifc_intr_brf_error_intr_trig_r_cg intr_brf_error_intr_trig_r_cg = new(bus_intr_brf_error_intr_trig_r);
+  soc_ifc_intr_brf_notif_intr_trig_r_cg intr_brf_notif_intr_trig_r_cg = new(bus_intr_brf_notif_intr_trig_r);
+  soc_ifc_intr_brf_error_internal_intr_count_r_cg intr_brf_error_internal_intr_count_r_cg = new(bus_intr_brf_error_internal_intr_count_r);
+  soc_ifc_intr_brf_error_inv_dev_intr_count_r_cg intr_brf_error_inv_dev_intr_count_r_cg = new(bus_intr_brf_error_inv_dev_intr_count_r);
+  soc_ifc_intr_brf_error_cmd_fail_intr_count_r_cg intr_brf_error_cmd_fail_intr_count_r_cg = new(bus_intr_brf_error_cmd_fail_intr_count_r);
+  soc_ifc_intr_brf_error_bad_fuse_intr_count_r_cg intr_brf_error_bad_fuse_intr_count_r_cg = new(bus_intr_brf_error_bad_fuse_intr_count_r);
+  soc_ifc_intr_brf_error_iccm_blocked_intr_count_r_cg intr_brf_error_iccm_blocked_intr_count_r_cg = new(bus_intr_brf_error_iccm_blocked_intr_count_r);
+  soc_ifc_intr_brf_error_mbox_ecc_unc_intr_count_r_cg intr_brf_error_mbox_ecc_unc_intr_count_r_cg = new(bus_intr_brf_error_mbox_ecc_unc_intr_count_r);
+  soc_ifc_intr_brf_error_wdt_timer1_timeout_intr_count_r_cg intr_brf_error_wdt_timer1_timeout_intr_count_r_cg = new(bus_intr_brf_error_wdt_timer1_timeout_intr_count_r);
+  soc_ifc_intr_brf_error_wdt_timer2_timeout_intr_count_r_cg intr_brf_error_wdt_timer2_timeout_intr_count_r_cg = new(bus_intr_brf_error_wdt_timer2_timeout_intr_count_r);
+  soc_ifc_intr_brf_notif_cmd_avail_intr_count_r_cg intr_brf_notif_cmd_avail_intr_count_r_cg = new(bus_intr_brf_notif_cmd_avail_intr_count_r);
+  soc_ifc_intr_brf_notif_mbox_ecc_cor_intr_count_r_cg intr_brf_notif_mbox_ecc_cor_intr_count_r_cg = new(bus_intr_brf_notif_mbox_ecc_cor_intr_count_r);
+  soc_ifc_intr_brf_notif_debug_locked_intr_count_r_cg intr_brf_notif_debug_locked_intr_count_r_cg = new(bus_intr_brf_notif_debug_locked_intr_count_r);
+  soc_ifc_intr_brf_notif_scan_mode_intr_count_r_cg intr_brf_notif_scan_mode_intr_count_r_cg = new(bus_intr_brf_notif_scan_mode_intr_count_r);
+  soc_ifc_intr_brf_notif_soc_req_lock_intr_count_r_cg intr_brf_notif_soc_req_lock_intr_count_r_cg = new(bus_intr_brf_notif_soc_req_lock_intr_count_r);
+  soc_ifc_intr_brf_notif_gen_in_toggle_intr_count_r_cg intr_brf_notif_gen_in_toggle_intr_count_r_cg = new(bus_intr_brf_notif_gen_in_toggle_intr_count_r);
+  soc_ifc_intr_brf_error_internal_intr_count_incr_r_cg intr_brf_error_internal_intr_count_incr_r_cg = new(bus_intr_brf_error_internal_intr_count_incr_r);
+  soc_ifc_intr_brf_error_inv_dev_intr_count_incr_r_cg intr_brf_error_inv_dev_intr_count_incr_r_cg = new(bus_intr_brf_error_inv_dev_intr_count_incr_r);
+  soc_ifc_intr_brf_error_cmd_fail_intr_count_incr_r_cg intr_brf_error_cmd_fail_intr_count_incr_r_cg = new(bus_intr_brf_error_cmd_fail_intr_count_incr_r);
+  soc_ifc_intr_brf_error_bad_fuse_intr_count_incr_r_cg intr_brf_error_bad_fuse_intr_count_incr_r_cg = new(bus_intr_brf_error_bad_fuse_intr_count_incr_r);
+  soc_ifc_intr_brf_error_iccm_blocked_intr_count_incr_r_cg intr_brf_error_iccm_blocked_intr_count_incr_r_cg = new(bus_intr_brf_error_iccm_blocked_intr_count_incr_r);
+  soc_ifc_intr_brf_error_mbox_ecc_unc_intr_count_incr_r_cg intr_brf_error_mbox_ecc_unc_intr_count_incr_r_cg = new(bus_intr_brf_error_mbox_ecc_unc_intr_count_incr_r);
+  soc_ifc_intr_brf_error_wdt_timer1_timeout_intr_count_incr_r_cg intr_brf_error_wdt_timer1_timeout_intr_count_incr_r_cg = new(bus_intr_brf_error_wdt_timer1_timeout_intr_count_incr_r);
+  soc_ifc_intr_brf_error_wdt_timer2_timeout_intr_count_incr_r_cg intr_brf_error_wdt_timer2_timeout_intr_count_incr_r_cg = new(bus_intr_brf_error_wdt_timer2_timeout_intr_count_incr_r);
+  soc_ifc_intr_brf_notif_cmd_avail_intr_count_incr_r_cg intr_brf_notif_cmd_avail_intr_count_incr_r_cg = new(bus_intr_brf_notif_cmd_avail_intr_count_incr_r);
+  soc_ifc_intr_brf_notif_mbox_ecc_cor_intr_count_incr_r_cg intr_brf_notif_mbox_ecc_cor_intr_count_incr_r_cg = new(bus_intr_brf_notif_mbox_ecc_cor_intr_count_incr_r);
+  soc_ifc_intr_brf_notif_debug_locked_intr_count_incr_r_cg intr_brf_notif_debug_locked_intr_count_incr_r_cg = new(bus_intr_brf_notif_debug_locked_intr_count_incr_r);
+  soc_ifc_intr_brf_notif_soc_req_lock_intr_count_incr_r_cg intr_brf_notif_soc_req_lock_intr_count_incr_r_cg = new(bus_intr_brf_notif_soc_req_lock_intr_count_incr_r);
+
+  // ------------------------------------------------------------------- 
+  // end SCRIPT_OUTPUT
+  // ------------------------------------------------------------------- 
 
 endinterface
 
-`endif
\ No newline at end of file
+
+`endif
+
diff --git a/src/soc_ifc/rtl/caliptra_top_reg.h b/src/soc_ifc/rtl/caliptra_top_reg.h
index 90c555aa1..e2c597f16 100644
--- a/src/soc_ifc/rtl/caliptra_top_reg.h
+++ b/src/soc_ifc/rtl/caliptra_top_reg.h
@@ -47,6 +47,8 @@
 #define MBOX_CSR_MBOX_STATUS_MBOX_FSM_PS_MASK                                                       (0x1c0)
 #define MBOX_CSR_MBOX_STATUS_SOC_HAS_LOCK_LOW                                                       (9)
 #define MBOX_CSR_MBOX_STATUS_SOC_HAS_LOCK_MASK                                                      (0x200)
+#define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_LOW                                                         (10)
+#define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_MASK                                                        (0x1fffc00)
 #define CALIPTRA_TOP_REG_MBOX_CSR_MBOX_UNLOCK                                                       (0x30020020)
 #define MBOX_CSR_MBOX_UNLOCK                                                                        (0x20)
 #define MBOX_CSR_MBOX_UNLOCK_UNLOCK_LOW                                                             (0)
@@ -78,6 +80,8 @@
 #define SHA512_ACC_CSR_STATUS                                                                       (0x1c)
 #define SHA512_ACC_CSR_STATUS_VALID_LOW                                                             (0)
 #define SHA512_ACC_CSR_STATUS_VALID_MASK                                                            (0x1)
+#define SHA512_ACC_CSR_STATUS_SOC_HAS_LOCK_LOW                                                      (1)
+#define SHA512_ACC_CSR_STATUS_SOC_HAS_LOCK_MASK                                                     (0x2)
 #define CALIPTRA_TOP_REG_SHA512_ACC_CSR_DIGEST_0                                                    (0x30021020)
 #define SHA512_ACC_CSR_DIGEST_0                                                                     (0x20)
 #define CALIPTRA_TOP_REG_SHA512_ACC_CSR_DIGEST_1                                                    (0x30021024)
@@ -117,8 +121,20 @@
 #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_BASE_ADDR                                             (0x30030000)
 #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL                                  (0x30030000)
 #define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL                                                   (0x0)
+#define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_ICCM_ECC_UNC_LOW                                  (0)
+#define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_ICCM_ECC_UNC_MASK                                 (0x1)
+#define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_DCCM_ECC_UNC_LOW                                  (1)
+#define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_DCCM_ECC_UNC_MASK                                 (0x2)
+#define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_NMI_PIN_LOW                                       (2)
+#define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_NMI_PIN_MASK                                      (0x4)
 #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL                              (0x30030004)
 #define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL                                               (0x4)
+#define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_NO_LOCK_LOW                         (0)
+#define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_NO_LOCK_MASK                        (0x1)
+#define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_OOO_LOW                             (1)
+#define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_OOO_MASK                            (0x2)
+#define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_ECC_UNC_LOW                              (2)
+#define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_ECC_UNC_MASK                             (0x4)
 #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_ERROR_FATAL                                  (0x30030008)
 #define GENERIC_AND_FUSE_REG_CPTRA_FW_ERROR_FATAL                                                   (0x8)
 #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_ERROR_NON_FATAL                              (0x3003000c)
@@ -148,7 +164,11 @@
 #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS                                     (0x3003003c)
 #define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS                                                      (0x3c)
 #define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_STATUS_LOW                                           (0)
-#define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_STATUS_MASK                                          (0xfffffff)
+#define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_STATUS_MASK                                          (0xffffff)
+#define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_IDEVID_CSR_READY_LOW                                 (24)
+#define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_IDEVID_CSR_READY_MASK                                (0x1000000)
+#define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_BOOT_FSM_PS_LOW                                      (25)
+#define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_BOOT_FSM_PS_MASK                                     (0xe000000)
 #define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_LOW                                     (28)
 #define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_MASK                                    (0x10000000)
 #define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_RUNTIME_LOW                                (29)
@@ -233,80 +253,116 @@
 #define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_10                                                     (0xa0)
 #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_11                                    (0x300300a4)
 #define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_11                                                     (0xa4)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_STATUS                                     (0x300300a8)
-#define GENERIC_AND_FUSE_REG_CPTRA_TRNG_STATUS                                                      (0xa8)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_CTRL                                       (0x300300a8)
+#define GENERIC_AND_FUSE_REG_CPTRA_TRNG_CTRL                                                        (0xa8)
+#define GENERIC_AND_FUSE_REG_CPTRA_TRNG_CTRL_CLEAR_LOW                                              (0)
+#define GENERIC_AND_FUSE_REG_CPTRA_TRNG_CTRL_CLEAR_MASK                                             (0x1)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_STATUS                                     (0x300300ac)
+#define GENERIC_AND_FUSE_REG_CPTRA_TRNG_STATUS                                                      (0xac)
 #define GENERIC_AND_FUSE_REG_CPTRA_TRNG_STATUS_DATA_REQ_LOW                                         (0)
 #define GENERIC_AND_FUSE_REG_CPTRA_TRNG_STATUS_DATA_REQ_MASK                                        (0x1)
 #define GENERIC_AND_FUSE_REG_CPTRA_TRNG_STATUS_DATA_WR_DONE_LOW                                     (1)
 #define GENERIC_AND_FUSE_REG_CPTRA_TRNG_STATUS_DATA_WR_DONE_MASK                                    (0x2)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FUSE_WR_DONE                                    (0x300300ac)
-#define GENERIC_AND_FUSE_REG_CPTRA_FUSE_WR_DONE                                                     (0xac)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FUSE_WR_DONE                                    (0x300300b0)
+#define GENERIC_AND_FUSE_REG_CPTRA_FUSE_WR_DONE                                                     (0xb0)
 #define GENERIC_AND_FUSE_REG_CPTRA_FUSE_WR_DONE_DONE_LOW                                            (0)
 #define GENERIC_AND_FUSE_REG_CPTRA_FUSE_WR_DONE_DONE_MASK                                           (0x1)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TIMER_CONFIG                                    (0x300300b0)
-#define GENERIC_AND_FUSE_REG_CPTRA_TIMER_CONFIG                                                     (0xb0)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_BOOTFSM_GO                                      (0x300300b4)
-#define GENERIC_AND_FUSE_REG_CPTRA_BOOTFSM_GO                                                       (0xb4)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TIMER_CONFIG                                    (0x300300b4)
+#define GENERIC_AND_FUSE_REG_CPTRA_TIMER_CONFIG                                                     (0xb4)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_BOOTFSM_GO                                      (0x300300b8)
+#define GENERIC_AND_FUSE_REG_CPTRA_BOOTFSM_GO                                                       (0xb8)
 #define GENERIC_AND_FUSE_REG_CPTRA_BOOTFSM_GO_GO_LOW                                                (0)
 #define GENERIC_AND_FUSE_REG_CPTRA_BOOTFSM_GO_GO_MASK                                               (0x1)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_DBG_MANUF_SERVICE_REG                           (0x300300b8)
-#define GENERIC_AND_FUSE_REG_CPTRA_DBG_MANUF_SERVICE_REG                                            (0xb8)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_CLK_GATING_EN                                   (0x300300bc)
-#define GENERIC_AND_FUSE_REG_CPTRA_CLK_GATING_EN                                                    (0xbc)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_DBG_MANUF_SERVICE_REG                           (0x300300bc)
+#define GENERIC_AND_FUSE_REG_CPTRA_DBG_MANUF_SERVICE_REG                                            (0xbc)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_CLK_GATING_EN                                   (0x300300c0)
+#define GENERIC_AND_FUSE_REG_CPTRA_CLK_GATING_EN                                                    (0xc0)
 #define GENERIC_AND_FUSE_REG_CPTRA_CLK_GATING_EN_CLK_GATING_EN_LOW                                  (0)
 #define GENERIC_AND_FUSE_REG_CPTRA_CLK_GATING_EN_CLK_GATING_EN_MASK                                 (0x1)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_GENERIC_INPUT_WIRES_0                           (0x300300c0)
-#define GENERIC_AND_FUSE_REG_CPTRA_GENERIC_INPUT_WIRES_0                                            (0xc0)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_GENERIC_INPUT_WIRES_1                           (0x300300c4)
-#define GENERIC_AND_FUSE_REG_CPTRA_GENERIC_INPUT_WIRES_1                                            (0xc4)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_GENERIC_OUTPUT_WIRES_0                          (0x300300c8)
-#define GENERIC_AND_FUSE_REG_CPTRA_GENERIC_OUTPUT_WIRES_0                                           (0xc8)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_GENERIC_OUTPUT_WIRES_1                          (0x300300cc)
-#define GENERIC_AND_FUSE_REG_CPTRA_GENERIC_OUTPUT_WIRES_1                                           (0xcc)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_HW_REV_ID                                       (0x300300d0)
-#define GENERIC_AND_FUSE_REG_CPTRA_HW_REV_ID                                                        (0xd0)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_REV_ID_0                                     (0x300300d4)
-#define GENERIC_AND_FUSE_REG_CPTRA_FW_REV_ID_0                                                      (0xd4)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_REV_ID_1                                     (0x300300d8)
-#define GENERIC_AND_FUSE_REG_CPTRA_FW_REV_ID_1                                                      (0xd8)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG                                       (0x300300dc)
-#define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG                                                        (0xdc)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_GENERIC_INPUT_WIRES_0                           (0x300300c4)
+#define GENERIC_AND_FUSE_REG_CPTRA_GENERIC_INPUT_WIRES_0                                            (0xc4)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_GENERIC_INPUT_WIRES_1                           (0x300300c8)
+#define GENERIC_AND_FUSE_REG_CPTRA_GENERIC_INPUT_WIRES_1                                            (0xc8)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_GENERIC_OUTPUT_WIRES_0                          (0x300300cc)
+#define GENERIC_AND_FUSE_REG_CPTRA_GENERIC_OUTPUT_WIRES_0                                           (0xcc)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_GENERIC_OUTPUT_WIRES_1                          (0x300300d0)
+#define GENERIC_AND_FUSE_REG_CPTRA_GENERIC_OUTPUT_WIRES_1                                           (0xd0)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_HW_REV_ID                                       (0x300300d4)
+#define GENERIC_AND_FUSE_REG_CPTRA_HW_REV_ID                                                        (0xd4)
+#define GENERIC_AND_FUSE_REG_CPTRA_HW_REV_ID_CPTRA_GENERATION_LOW                                   (0)
+#define GENERIC_AND_FUSE_REG_CPTRA_HW_REV_ID_CPTRA_GENERATION_MASK                                  (0xffff)
+#define GENERIC_AND_FUSE_REG_CPTRA_HW_REV_ID_SOC_STEPPING_ID_LOW                                    (16)
+#define GENERIC_AND_FUSE_REG_CPTRA_HW_REV_ID_SOC_STEPPING_ID_MASK                                   (0xffff0000)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_REV_ID_0                                     (0x300300d8)
+#define GENERIC_AND_FUSE_REG_CPTRA_FW_REV_ID_0                                                      (0xd8)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_REV_ID_1                                     (0x300300dc)
+#define GENERIC_AND_FUSE_REG_CPTRA_FW_REV_ID_1                                                      (0xdc)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG                                       (0x300300e0)
+#define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG                                                        (0xe0)
 #define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_ITRNG_EN_LOW                                           (0)
 #define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_ITRNG_EN_MASK                                          (0x1)
 #define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_QSPI_EN_LOW                                            (1)
 #define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_QSPI_EN_MASK                                           (0x2)
 #define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_I3C_EN_LOW                                             (2)
 #define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_I3C_EN_MASK                                            (0x4)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN                                   (0x300300e0)
-#define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN                                                    (0xe0)
+#define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_UART_EN_LOW                                            (3)
+#define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_UART_EN_MASK                                           (0x8)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN                                   (0x300300e4)
+#define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN                                                    (0xe4)
 #define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_LOW                                      (0)
 #define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_MASK                                     (0x1)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_CTRL                                 (0x300300e4)
-#define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_CTRL                                                  (0xe4)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_CTRL                                 (0x300300e8)
+#define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_CTRL                                                  (0xe8)
 #define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART_LOW                               (0)
 #define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART_MASK                              (0x1)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0                     (0x300300e8)
-#define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0                                      (0xe8)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1                     (0x300300ec)
-#define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1                                      (0xec)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_EN                                   (0x300300f0)
-#define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_EN                                                    (0xf0)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0                     (0x300300ec)
+#define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0                                      (0xec)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1                     (0x300300f0)
+#define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1                                      (0xf0)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_EN                                   (0x300300f4)
+#define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_EN                                                    (0xf4)
 #define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_EN_TIMER2_EN_LOW                                      (0)
 #define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_EN_TIMER2_EN_MASK                                     (0x1)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_CTRL                                 (0x300300f4)
-#define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_CTRL                                                  (0xf4)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_CTRL                                 (0x300300f8)
+#define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_CTRL                                                  (0xf8)
 #define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART_LOW                               (0)
 #define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART_MASK                              (0x1)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0                     (0x300300f8)
-#define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0                                      (0xf8)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1                     (0x300300fc)
-#define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1                                      (0xfc)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS                                      (0x30030100)
-#define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS                                                       (0x100)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0                     (0x300300fc)
+#define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0                                      (0xfc)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1                     (0x30030100)
+#define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1                                      (0x100)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS                                      (0x30030104)
+#define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS                                                       (0x104)
 #define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_LOW                                        (0)
 #define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_MASK                                       (0x1)
 #define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_LOW                                        (1)
 #define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_MASK                                       (0x2)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FUSE_VALID_PAUSER                               (0x30030108)
+#define GENERIC_AND_FUSE_REG_CPTRA_FUSE_VALID_PAUSER                                                (0x108)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FUSE_PAUSER_LOCK                                (0x3003010c)
+#define GENERIC_AND_FUSE_REG_CPTRA_FUSE_PAUSER_LOCK                                                 (0x10c)
+#define GENERIC_AND_FUSE_REG_CPTRA_FUSE_PAUSER_LOCK_LOCK_LOW                                        (0)
+#define GENERIC_AND_FUSE_REG_CPTRA_FUSE_PAUSER_LOCK_LOCK_MASK                                       (0x1)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_CFG_0                                       (0x30030110)
+#define GENERIC_AND_FUSE_REG_CPTRA_WDT_CFG_0                                                        (0x110)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_CFG_1                                       (0x30030114)
+#define GENERIC_AND_FUSE_REG_CPTRA_WDT_CFG_1                                                        (0x114)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0                          (0x30030118)
+#define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0                                           (0x118)
+#define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_LOW_THRESHOLD_LOW                         (0)
+#define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_LOW_THRESHOLD_MASK                        (0xffff)
+#define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_HIGH_THRESHOLD_LOW                        (16)
+#define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_HIGH_THRESHOLD_MASK                       (0xffff0000)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1                          (0x3003011c)
+#define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1                                           (0x11c)
+#define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_REPETITION_COUNT_LOW                      (0)
+#define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_REPETITION_COUNT_MASK                     (0xffff)
+#define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_RSVD_LOW                                  (16)
+#define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_RSVD_MASK                                 (0xffff0000)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_RSVD_REG_0                                      (0x30030120)
+#define GENERIC_AND_FUSE_REG_CPTRA_RSVD_REG_0                                                       (0x120)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_RSVD_REG_1                                      (0x30030124)
+#define GENERIC_AND_FUSE_REG_CPTRA_RSVD_REG_1                                                       (0x124)
 #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_0                                       (0x30030200)
 #define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_0                                                        (0x200)
 #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_1                                       (0x30030204)
@@ -473,6 +529,16 @@
 #define GENERIC_AND_FUSE_REG_FUSE_LIFE_CYCLE                                                        (0x33c)
 #define GENERIC_AND_FUSE_REG_FUSE_LIFE_CYCLE_LIFE_CYCLE_LOW                                         (0)
 #define GENERIC_AND_FUSE_REG_FUSE_LIFE_CYCLE_LIFE_CYCLE_MASK                                        (0x3)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_LMS_VERIFY                                       (0x30030340)
+#define GENERIC_AND_FUSE_REG_FUSE_LMS_VERIFY                                                        (0x340)
+#define GENERIC_AND_FUSE_REG_FUSE_LMS_VERIFY_LMS_VERIFY_LOW                                         (0)
+#define GENERIC_AND_FUSE_REG_FUSE_LMS_VERIFY_LMS_VERIFY_MASK                                        (0x1)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_LMS_REVOCATION                                   (0x30030344)
+#define GENERIC_AND_FUSE_REG_FUSE_LMS_REVOCATION                                                    (0x344)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID                                  (0x30030348)
+#define GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID                                                   (0x348)
+#define GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID_SOC_STEPPING_ID_LOW                               (0)
+#define GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID_SOC_STEPPING_ID_MASK                              (0xffff)
 
 
 #endif
diff --git a/src/soc_ifc/rtl/caliptra_top_reg_defines.svh b/src/soc_ifc/rtl/caliptra_top_reg_defines.svh
index 4eb915d3e..9677a065e 100644
--- a/src/soc_ifc/rtl/caliptra_top_reg_defines.svh
+++ b/src/soc_ifc/rtl/caliptra_top_reg_defines.svh
@@ -48,6 +48,8 @@
 `define MBOX_CSR_MBOX_STATUS_MBOX_FSM_PS_MASK                                                       (32'h1c0)
 `define MBOX_CSR_MBOX_STATUS_SOC_HAS_LOCK_LOW                                                       (9)
 `define MBOX_CSR_MBOX_STATUS_SOC_HAS_LOCK_MASK                                                      (32'h200)
+`define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_LOW                                                         (10)
+`define MBOX_CSR_MBOX_STATUS_MBOX_RDPTR_MASK                                                        (32'h1fffc00)
 `define CALIPTRA_TOP_REG_MBOX_CSR_MBOX_UNLOCK                                                       (32'h30020020)
 `define MBOX_CSR_MBOX_UNLOCK                                                                        (32'h20)
 `define MBOX_CSR_MBOX_UNLOCK_UNLOCK_LOW                                                             (0)
@@ -79,6 +81,8 @@
 `define SHA512_ACC_CSR_STATUS                                                                       (32'h1c)
 `define SHA512_ACC_CSR_STATUS_VALID_LOW                                                             (0)
 `define SHA512_ACC_CSR_STATUS_VALID_MASK                                                            (32'h1)
+`define SHA512_ACC_CSR_STATUS_SOC_HAS_LOCK_LOW                                                      (1)
+`define SHA512_ACC_CSR_STATUS_SOC_HAS_LOCK_MASK                                                     (32'h2)
 `define CALIPTRA_TOP_REG_SHA512_ACC_CSR_DIGEST_0                                                    (32'h30021020)
 `define SHA512_ACC_CSR_DIGEST_0                                                                     (32'h20)
 `define CALIPTRA_TOP_REG_SHA512_ACC_CSR_DIGEST_1                                                    (32'h30021024)
@@ -118,8 +122,20 @@
 `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_BASE_ADDR                                             (32'h30030000)
 `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL                                  (32'h30030000)
 `define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL                                                   (32'h0)
+`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_ICCM_ECC_UNC_LOW                                  (0)
+`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_ICCM_ECC_UNC_MASK                                 (32'h1)
+`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_DCCM_ECC_UNC_LOW                                  (1)
+`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_DCCM_ECC_UNC_MASK                                 (32'h2)
+`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_NMI_PIN_LOW                                       (2)
+`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_NMI_PIN_MASK                                      (32'h4)
 `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL                              (32'h30030004)
 `define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL                                               (32'h4)
+`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_NO_LOCK_LOW                         (0)
+`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_NO_LOCK_MASK                        (32'h1)
+`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_OOO_LOW                             (1)
+`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_OOO_MASK                            (32'h2)
+`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_ECC_UNC_LOW                              (2)
+`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_ECC_UNC_MASK                             (32'h4)
 `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_ERROR_FATAL                                  (32'h30030008)
 `define GENERIC_AND_FUSE_REG_CPTRA_FW_ERROR_FATAL                                                   (32'h8)
 `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_ERROR_NON_FATAL                              (32'h3003000c)
@@ -149,7 +165,11 @@
 `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS                                     (32'h3003003c)
 `define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS                                                      (32'h3c)
 `define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_STATUS_LOW                                           (0)
-`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_STATUS_MASK                                          (32'hfffffff)
+`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_STATUS_MASK                                          (32'hffffff)
+`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_IDEVID_CSR_READY_LOW                                 (24)
+`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_IDEVID_CSR_READY_MASK                                (32'h1000000)
+`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_BOOT_FSM_PS_LOW                                      (25)
+`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_BOOT_FSM_PS_MASK                                     (32'he000000)
 `define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_LOW                                     (28)
 `define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_MASK                                    (32'h10000000)
 `define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_RUNTIME_LOW                                (29)
@@ -234,44 +254,52 @@
 `define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_10                                                     (32'ha0)
 `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_11                                    (32'h300300a4)
 `define GENERIC_AND_FUSE_REG_CPTRA_TRNG_DATA_11                                                     (32'ha4)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_STATUS                                     (32'h300300a8)
-`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_STATUS                                                      (32'ha8)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_CTRL                                       (32'h300300a8)
+`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_CTRL                                                        (32'ha8)
+`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_CTRL_CLEAR_LOW                                              (0)
+`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_CTRL_CLEAR_MASK                                             (32'h1)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TRNG_STATUS                                     (32'h300300ac)
+`define GENERIC_AND_FUSE_REG_CPTRA_TRNG_STATUS                                                      (32'hac)
 `define GENERIC_AND_FUSE_REG_CPTRA_TRNG_STATUS_DATA_REQ_LOW                                         (0)
 `define GENERIC_AND_FUSE_REG_CPTRA_TRNG_STATUS_DATA_REQ_MASK                                        (32'h1)
 `define GENERIC_AND_FUSE_REG_CPTRA_TRNG_STATUS_DATA_WR_DONE_LOW                                     (1)
 `define GENERIC_AND_FUSE_REG_CPTRA_TRNG_STATUS_DATA_WR_DONE_MASK                                    (32'h2)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FUSE_WR_DONE                                    (32'h300300ac)
-`define GENERIC_AND_FUSE_REG_CPTRA_FUSE_WR_DONE                                                     (32'hac)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FUSE_WR_DONE                                    (32'h300300b0)
+`define GENERIC_AND_FUSE_REG_CPTRA_FUSE_WR_DONE                                                     (32'hb0)
 `define GENERIC_AND_FUSE_REG_CPTRA_FUSE_WR_DONE_DONE_LOW                                            (0)
 `define GENERIC_AND_FUSE_REG_CPTRA_FUSE_WR_DONE_DONE_MASK                                           (32'h1)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TIMER_CONFIG                                    (32'h300300b0)
-`define GENERIC_AND_FUSE_REG_CPTRA_TIMER_CONFIG                                                     (32'hb0)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_BOOTFSM_GO                                      (32'h300300b4)
-`define GENERIC_AND_FUSE_REG_CPTRA_BOOTFSM_GO                                                       (32'hb4)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_TIMER_CONFIG                                    (32'h300300b4)
+`define GENERIC_AND_FUSE_REG_CPTRA_TIMER_CONFIG                                                     (32'hb4)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_BOOTFSM_GO                                      (32'h300300b8)
+`define GENERIC_AND_FUSE_REG_CPTRA_BOOTFSM_GO                                                       (32'hb8)
 `define GENERIC_AND_FUSE_REG_CPTRA_BOOTFSM_GO_GO_LOW                                                (0)
 `define GENERIC_AND_FUSE_REG_CPTRA_BOOTFSM_GO_GO_MASK                                               (32'h1)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_DBG_MANUF_SERVICE_REG                           (32'h300300b8)
-`define GENERIC_AND_FUSE_REG_CPTRA_DBG_MANUF_SERVICE_REG                                            (32'hb8)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_CLK_GATING_EN                                   (32'h300300bc)
-`define GENERIC_AND_FUSE_REG_CPTRA_CLK_GATING_EN                                                    (32'hbc)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_DBG_MANUF_SERVICE_REG                           (32'h300300bc)
+`define GENERIC_AND_FUSE_REG_CPTRA_DBG_MANUF_SERVICE_REG                                            (32'hbc)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_CLK_GATING_EN                                   (32'h300300c0)
+`define GENERIC_AND_FUSE_REG_CPTRA_CLK_GATING_EN                                                    (32'hc0)
 `define GENERIC_AND_FUSE_REG_CPTRA_CLK_GATING_EN_CLK_GATING_EN_LOW                                  (0)
 `define GENERIC_AND_FUSE_REG_CPTRA_CLK_GATING_EN_CLK_GATING_EN_MASK                                 (32'h1)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_GENERIC_INPUT_WIRES_0                           (32'h300300c0)
-`define GENERIC_AND_FUSE_REG_CPTRA_GENERIC_INPUT_WIRES_0                                            (32'hc0)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_GENERIC_INPUT_WIRES_1                           (32'h300300c4)
-`define GENERIC_AND_FUSE_REG_CPTRA_GENERIC_INPUT_WIRES_1                                            (32'hc4)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_GENERIC_OUTPUT_WIRES_0                          (32'h300300c8)
-`define GENERIC_AND_FUSE_REG_CPTRA_GENERIC_OUTPUT_WIRES_0                                           (32'hc8)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_GENERIC_OUTPUT_WIRES_1                          (32'h300300cc)
-`define GENERIC_AND_FUSE_REG_CPTRA_GENERIC_OUTPUT_WIRES_1                                           (32'hcc)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_HW_REV_ID                                       (32'h300300d0)
-`define GENERIC_AND_FUSE_REG_CPTRA_HW_REV_ID                                                        (32'hd0)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_REV_ID_0                                     (32'h300300d4)
-`define GENERIC_AND_FUSE_REG_CPTRA_FW_REV_ID_0                                                      (32'hd4)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_REV_ID_1                                     (32'h300300d8)
-`define GENERIC_AND_FUSE_REG_CPTRA_FW_REV_ID_1                                                      (32'hd8)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG                                       (32'h300300dc)
-`define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG                                                        (32'hdc)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_GENERIC_INPUT_WIRES_0                           (32'h300300c4)
+`define GENERIC_AND_FUSE_REG_CPTRA_GENERIC_INPUT_WIRES_0                                            (32'hc4)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_GENERIC_INPUT_WIRES_1                           (32'h300300c8)
+`define GENERIC_AND_FUSE_REG_CPTRA_GENERIC_INPUT_WIRES_1                                            (32'hc8)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_GENERIC_OUTPUT_WIRES_0                          (32'h300300cc)
+`define GENERIC_AND_FUSE_REG_CPTRA_GENERIC_OUTPUT_WIRES_0                                           (32'hcc)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_GENERIC_OUTPUT_WIRES_1                          (32'h300300d0)
+`define GENERIC_AND_FUSE_REG_CPTRA_GENERIC_OUTPUT_WIRES_1                                           (32'hd0)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_HW_REV_ID                                       (32'h300300d4)
+`define GENERIC_AND_FUSE_REG_CPTRA_HW_REV_ID                                                        (32'hd4)
+`define GENERIC_AND_FUSE_REG_CPTRA_HW_REV_ID_CPTRA_GENERATION_LOW                                   (0)
+`define GENERIC_AND_FUSE_REG_CPTRA_HW_REV_ID_CPTRA_GENERATION_MASK                                  (32'hffff)
+`define GENERIC_AND_FUSE_REG_CPTRA_HW_REV_ID_SOC_STEPPING_ID_LOW                                    (16)
+`define GENERIC_AND_FUSE_REG_CPTRA_HW_REV_ID_SOC_STEPPING_ID_MASK                                   (32'hffff0000)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_REV_ID_0                                     (32'h300300d8)
+`define GENERIC_AND_FUSE_REG_CPTRA_FW_REV_ID_0                                                      (32'hd8)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_REV_ID_1                                     (32'h300300dc)
+`define GENERIC_AND_FUSE_REG_CPTRA_FW_REV_ID_1                                                      (32'hdc)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG                                       (32'h300300e0)
+`define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG                                                        (32'he0)
 `define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_ITRNG_EN_LOW                                           (0)
 `define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_ITRNG_EN_MASK                                          (32'h1)
 `define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_QSPI_EN_LOW                                            (1)
@@ -280,36 +308,62 @@
 `define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_I3C_EN_MASK                                            (32'h4)
 `define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_UART_EN_LOW                                            (3)
 `define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_UART_EN_MASK                                           (32'h8)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN                                   (32'h300300e0)
-`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN                                                    (32'he0)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN                                   (32'h300300e4)
+`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN                                                    (32'he4)
 `define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_LOW                                      (0)
 `define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_MASK                                     (32'h1)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_CTRL                                 (32'h300300e4)
-`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_CTRL                                                  (32'he4)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_CTRL                                 (32'h300300e8)
+`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_CTRL                                                  (32'he8)
 `define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART_LOW                               (0)
 `define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART_MASK                              (32'h1)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0                     (32'h300300e8)
-`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0                                      (32'he8)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1                     (32'h300300ec)
-`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1                                      (32'hec)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_EN                                   (32'h300300f0)
-`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_EN                                                    (32'hf0)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0                     (32'h300300ec)
+`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0                                      (32'hec)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1                     (32'h300300f0)
+`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1                                      (32'hf0)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_EN                                   (32'h300300f4)
+`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_EN                                                    (32'hf4)
 `define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_EN_TIMER2_EN_LOW                                      (0)
 `define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_EN_TIMER2_EN_MASK                                     (32'h1)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_CTRL                                 (32'h300300f4)
-`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_CTRL                                                  (32'hf4)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_CTRL                                 (32'h300300f8)
+`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_CTRL                                                  (32'hf8)
 `define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART_LOW                               (0)
 `define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART_MASK                              (32'h1)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0                     (32'h300300f8)
-`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0                                      (32'hf8)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1                     (32'h300300fc)
-`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1                                      (32'hfc)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS                                      (32'h30030100)
-`define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS                                                       (32'h100)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0                     (32'h300300fc)
+`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0                                      (32'hfc)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1                     (32'h30030100)
+`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1                                      (32'h100)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS                                      (32'h30030104)
+`define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS                                                       (32'h104)
 `define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_LOW                                        (0)
 `define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_MASK                                       (32'h1)
 `define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_LOW                                        (1)
 `define GENERIC_AND_FUSE_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_MASK                                       (32'h2)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FUSE_VALID_PAUSER                               (32'h30030108)
+`define GENERIC_AND_FUSE_REG_CPTRA_FUSE_VALID_PAUSER                                                (32'h108)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FUSE_PAUSER_LOCK                                (32'h3003010c)
+`define GENERIC_AND_FUSE_REG_CPTRA_FUSE_PAUSER_LOCK                                                 (32'h10c)
+`define GENERIC_AND_FUSE_REG_CPTRA_FUSE_PAUSER_LOCK_LOCK_LOW                                        (0)
+`define GENERIC_AND_FUSE_REG_CPTRA_FUSE_PAUSER_LOCK_LOCK_MASK                                       (32'h1)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_CFG_0                                       (32'h30030110)
+`define GENERIC_AND_FUSE_REG_CPTRA_WDT_CFG_0                                                        (32'h110)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_CFG_1                                       (32'h30030114)
+`define GENERIC_AND_FUSE_REG_CPTRA_WDT_CFG_1                                                        (32'h114)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0                          (32'h30030118)
+`define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0                                           (32'h118)
+`define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_LOW_THRESHOLD_LOW                         (0)
+`define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_LOW_THRESHOLD_MASK                        (32'hffff)
+`define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_HIGH_THRESHOLD_LOW                        (16)
+`define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0_HIGH_THRESHOLD_MASK                       (32'hffff0000)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1                          (32'h3003011c)
+`define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1                                           (32'h11c)
+`define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_REPETITION_COUNT_LOW                      (0)
+`define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_REPETITION_COUNT_MASK                     (32'hffff)
+`define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_RSVD_LOW                                  (16)
+`define GENERIC_AND_FUSE_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1_RSVD_MASK                                 (32'hffff0000)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_RSVD_REG_0                                      (32'h30030120)
+`define GENERIC_AND_FUSE_REG_CPTRA_RSVD_REG_0                                                       (32'h120)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_RSVD_REG_1                                      (32'h30030124)
+`define GENERIC_AND_FUSE_REG_CPTRA_RSVD_REG_1                                                       (32'h124)
 `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_0                                       (32'h30030200)
 `define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_0                                                        (32'h200)
 `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_1                                       (32'h30030204)
@@ -476,6 +530,16 @@
 `define GENERIC_AND_FUSE_REG_FUSE_LIFE_CYCLE                                                        (32'h33c)
 `define GENERIC_AND_FUSE_REG_FUSE_LIFE_CYCLE_LIFE_CYCLE_LOW                                         (0)
 `define GENERIC_AND_FUSE_REG_FUSE_LIFE_CYCLE_LIFE_CYCLE_MASK                                        (32'h3)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_LMS_VERIFY                                       (32'h30030340)
+`define GENERIC_AND_FUSE_REG_FUSE_LMS_VERIFY                                                        (32'h340)
+`define GENERIC_AND_FUSE_REG_FUSE_LMS_VERIFY_LMS_VERIFY_LOW                                         (0)
+`define GENERIC_AND_FUSE_REG_FUSE_LMS_VERIFY_LMS_VERIFY_MASK                                        (32'h1)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_LMS_REVOCATION                                   (32'h30030344)
+`define GENERIC_AND_FUSE_REG_FUSE_LMS_REVOCATION                                                    (32'h344)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID                                  (32'h30030348)
+`define GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID                                                   (32'h348)
+`define GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID_SOC_STEPPING_ID_LOW                               (0)
+`define GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID_SOC_STEPPING_ID_MASK                              (32'hffff)
 
 
 `endif
diff --git a/src/soc_ifc/rtl/mbox.sv b/src/soc_ifc/rtl/mbox.sv
index 8ab16b1b8..2413f6954 100644
--- a/src/soc_ifc/rtl/mbox.sv
+++ b/src/soc_ifc/rtl/mbox.sv
@@ -33,6 +33,7 @@ module mbox
     output logic        mbox_error,
 
     output logic [DATA_W-1:0] rdata,
+    output logic [DATA_W-1:0] dir_rdata,
 
     input logic sha_sram_req_dv,
     input logic [MBOX_ADDR_W-1:0] sha_sram_req_addr,
@@ -51,6 +52,8 @@ module mbox
     output logic uc_mbox_data_avail,
     output logic soc_mbox_data_avail,
     output logic soc_req_mbox_lock,
+    output mbox_protocol_error_t mbox_protocol_error,
+    output logic mbox_inv_pauser_axs,
 
     //DMI reg access
     input logic dmi_inc_rdptr,
@@ -58,8 +61,9 @@ module mbox
 
 );
 
-localparam DEPTH = (SIZE_KB * 1024 * 8) / DATA_W;
-localparam MBOX_SIZE_IN_DW = (SIZE_KB*1024)/4;
+localparam MBOX_SIZE_IN_BYTES = SIZE_KB*1024;
+localparam MBOX_SIZE_IN_DW = (MBOX_SIZE_IN_BYTES)/4;
+localparam DEPTH = (MBOX_SIZE_IN_DW * 32) / DATA_W;
 
 //this module is used to instantiate a single mailbox instance
 //requests within the address space of this mailbox are routed here from the top level
@@ -84,18 +88,26 @@ logic arc_MBOX_EXECUTE_UC_MBOX_IDLE;
 logic arc_MBOX_EXECUTE_SOC_MBOX_IDLE;
 logic arc_MBOX_EXECUTE_UC_MBOX_EXECUTE_SOC;
 logic arc_MBOX_EXECUTE_SOC_MBOX_EXECUTE_UC;
+logic arc_MBOX_RDY_FOR_CMD_MBOX_ERROR;
+logic arc_MBOX_RDY_FOR_DLEN_MBOX_ERROR;
+logic arc_MBOX_RDY_FOR_DATA_MBOX_ERROR;
+logic arc_MBOX_EXECUTE_UC_MBOX_ERROR;
+logic arc_MBOX_EXECUTE_SOC_MBOX_ERROR;
 
 //sram
 logic [DATA_W-1:0] sram_wdata;
 logic [MBOX_ECC_DATA_W-1:0] sram_wdata_ecc;
 logic [$clog2(DEPTH)-1:0] sram_waddr;
 logic [$clog2(DEPTH)-1:0] mbox_wrptr, mbox_wrptr_nxt;
+logic mbox_wr_full, mbox_wr_full_nxt;
 logic inc_wrptr;
 logic [$clog2(DEPTH)-1:0] sram_rdaddr;
 logic [$clog2(DEPTH)-1:0] mbox_rdptr, mbox_rdptr_nxt;
+logic mbox_rd_full, mbox_rd_full_nxt;
 logic inc_rdptr;
 logic rst_mbox_rdptr;
 logic rst_mbox_wrptr;
+logic sram_rd_ecc_en;
 logic [DATA_W-1:0] sram_rdata;
 logic [MBOX_ECC_DATA_W-1:0] sram_rdata_ecc;
 logic [DATA_W-1:0] sram_rdata_cor;
@@ -103,8 +115,6 @@ logic [MBOX_ECC_DATA_W-1:0] sram_rdata_cor_ecc;
 logic sram_we;
 logic mbox_protocol_sram_we;
 logic mbox_protocol_sram_rd, mbox_protocol_sram_rd_f;
-logic sram_ecc_cor_we;
-logic [$clog2(DEPTH)-1:0] sram_ecc_cor_waddr;
 logic dir_req_dv_q, dir_req_rd_phase;
 logic dir_req_wr_ph;
 logic mask_rdata;
@@ -114,6 +124,15 @@ logic soc_has_lock, soc_has_lock_nxt;
 logic valid_requester;
 logic valid_receiver;
 
+logic [$clog2(DEPTH):0] mbox_dlen_in_dws;
+logic latch_dlen_in_dws;
+logic [$clog2(DEPTH):0] dlen_in_dws, dlen_in_dws_nxt;
+logic rdptr_inc_valid;
+logic mbox_rd_valid, mbox_rd_valid_f;
+logic wrptr_inc_valid;
+
+mbox_protocol_error_t mbox_protocol_error_nxt;
+
 //csr
 logic [DATA_W-1:0] csr_rdata;
 logic read_error;
@@ -133,14 +152,16 @@ always_comb valid_requester = hwif_out.mbox_lock.lock.value &
 
 //Determine if this is a valid request from the receiver side
 always_comb valid_receiver = hwif_out.mbox_lock.lock.value &
-                             //Receiver is valid when they don't have the lock
-                             ((~req_data.soc_req & soc_has_lock) | (req_data.soc_req & ~soc_has_lock) |
+                             //Receiver is valid when in their execute state
+                             //if they don't have the lock
+                             ((~req_data.soc_req &  soc_has_lock & (mbox_fsm_ps == MBOX_EXECUTE_UC )) |
+                              ( req_data.soc_req & ~soc_has_lock & (mbox_fsm_ps == MBOX_EXECUTE_SOC)) |
                              //Receiver is valid when they are reading a response to their request
                              (valid_requester & ((soc_has_lock & (mbox_fsm_ps == MBOX_EXECUTE_SOC)) |
                                                  (~soc_has_lock & (mbox_fsm_ps == MBOX_EXECUTE_UC)))));
 
 //We want to mask read data when
-//Invalid user is trying to access the mailbox data, or we're not in execute state
+//Invalid user is trying to access the mailbox data
 always_comb mask_rdata = hwif_out.mbox_dataout.dataout.swacc & ~valid_receiver;
 
 //move from idle to rdy for command when lock is acquired
@@ -162,27 +183,55 @@ always_comb arc_MBOX_EXECUTE_SOC_MBOX_IDLE = (mbox_fsm_ps == MBOX_EXECUTE_SOC) &
 always_comb arc_MBOX_EXECUTE_SOC_MBOX_EXECUTE_UC = (mbox_fsm_ps == MBOX_EXECUTE_SOC) & ~soc_has_lock & (hwif_out.mbox_status.status.value != CMD_BUSY);
 //move back to IDLE and unlock when force unlock is set
 always_comb arc_FORCE_MBOX_UNLOCK = hwif_out.mbox_unlock.unlock.value;
-
-logic [$clog2(DEPTH)-1:0] mbox_dlen_in_dws;
-logic latch_dlen_in_dws;
-logic [$clog2(DEPTH)-1:0] dlen_in_dws, dlen_in_dws_nxt;
-logic rdptr_inc_valid;
-logic mbox_rd_valid;
-logic wrptr_inc_valid;
+// Detect error conditions and peg to the error state until serviced.
+// Any register write (or read from mbox_dataout) by a VALID agent
+// while in the incorrect state for access to that register results
+// in transition to MBOX_ERROR and assertion of the protocol_error.
+// Any register write or read by an INVALID agent results in the access
+// being silently dropped.
+// Assumption: uC (ROM, FMC, RT) will never make an invalid request.
+// NOTE: Any APB agent can trigger the error at any point during a uC->SOC flow
+//       by writing to mbox_status (since it's a valid_receiver).
+//       FIXED! valid_receiver is restricted by FSM state now.
+always_comb arc_MBOX_RDY_FOR_CMD_MBOX_ERROR  = (mbox_fsm_ps == MBOX_RDY_FOR_CMD) &&
+                                               req_dv && req_data.soc_req && ~req_hold && valid_requester &&
+                                              (req_data.write ? (!hwif_out.mbox_cmd.command.swmod) :
+                                                                (hwif_out.mbox_dataout.dataout.swacc));
+always_comb arc_MBOX_RDY_FOR_DLEN_MBOX_ERROR = (mbox_fsm_ps == MBOX_RDY_FOR_DLEN) &&
+                                               req_dv && req_data.soc_req && ~req_hold && valid_requester &&
+                                              (req_data.write ? (!hwif_out.mbox_dlen.length.swmod) :
+                                                                (hwif_out.mbox_dataout.dataout.swacc));
+always_comb arc_MBOX_RDY_FOR_DATA_MBOX_ERROR = (mbox_fsm_ps == MBOX_RDY_FOR_DATA) &&
+                                               req_dv && req_data.soc_req && ~req_hold && valid_requester &&
+                                              (req_data.write ? (!(hwif_out.mbox_datain.datain.swmod || hwif_out.mbox_execute.execute.swmod)) :
+                                                                (hwif_out.mbox_dataout.dataout.swacc));
+always_comb arc_MBOX_EXECUTE_UC_MBOX_ERROR   = (mbox_fsm_ps == MBOX_EXECUTE_UC) &&
+                                               req_dv && req_data.soc_req && ~req_hold && valid_requester &&
+                                              (req_data.write ? (1'b1/* any write by 'valid' soc is illegal here */) :
+                                                                (hwif_out.mbox_dataout.dataout.swacc));
+always_comb arc_MBOX_EXECUTE_SOC_MBOX_ERROR  = (mbox_fsm_ps == MBOX_EXECUTE_SOC) &&
+                                               req_dv && req_data.soc_req && ~req_hold &&
+                                              (req_data.write ? ((valid_requester && !(hwif_out.mbox_execute.execute.swmod)) ||
+                                                                 (~soc_has_lock   && !(hwif_out.mbox_status.status.swmod))) :
+                                                                (1'b0 /* any read allowed by SoC during this stage; dataout consumption is expected */));
 
 //capture the dlen when we change to execute states, this ensures that only the dlen programmed
 //by the client filling the mailbox is used for masking the data
 //Store the dlen as a ptr to the last entry
 always_comb latch_dlen_in_dws = arc_MBOX_RDY_FOR_DATA_MBOX_EXECUTE_UC | arc_MBOX_RDY_FOR_DATA_MBOX_EXECUTE_SOC | arc_MBOX_EXECUTE_UC_MBOX_EXECUTE_SOC;
-always_comb mbox_dlen_in_dws = (hwif_out.mbox_dlen.length.value >> 2) + (hwif_out.mbox_dlen.length.value[0] | hwif_out.mbox_dlen.length.value[1]) - 1;
-//latched dlen is the smaller of the programmed dlen or the actual write pointer
+always_comb mbox_dlen_in_dws = (hwif_out.mbox_dlen.length.value >= MBOX_SIZE_IN_BYTES) ? MBOX_SIZE_IN_DW :
+                               (hwif_out.mbox_dlen.length.value >> 2) + (hwif_out.mbox_dlen.length.value[0] | hwif_out.mbox_dlen.length.value[1]);
+//latched dlen is the smaller of the programmed dlen or the current wrptr
 //this avoids a case where a sender writes less than programmed and the receiver can read beyond that
-always_comb dlen_in_dws_nxt = (mbox_wrptr < mbox_dlen_in_dws) ? mbox_wrptr : mbox_dlen_in_dws;
+//if the mailbox is full (flag set when writing last entry), always take the programmed dlen
+always_comb dlen_in_dws_nxt = (~mbox_wr_full & ({1'b0,mbox_wrptr} < mbox_dlen_in_dws)) ? {1'b0,mbox_wrptr} : mbox_dlen_in_dws;
 
 // Restrict the read pointer from passing the dlen or rolling over
-always_comb rdptr_inc_valid = (mbox_rdptr <= dlen_in_dws) & (mbox_rdptr < (MBOX_SIZE_IN_DW-1));
+always_comb rdptr_inc_valid = ({1'b0,mbox_rdptr} < dlen_in_dws) & (mbox_rdptr < (MBOX_SIZE_IN_DW-1));
+// No more valid reads if we read the last entry
+// On pre-load of entry 0, ensure that next dlen isn't 0
 // Restrict reads once read pointer has passed the dlen
-always_comb mbox_rd_valid = mbox_rdptr <= dlen_in_dws;
+always_comb mbox_rd_valid = (rst_mbox_rdptr & (dlen_in_dws_nxt != 0)) | (~rst_mbox_rdptr & ~mbox_rd_full & ({1'b0,mbox_rdptr} < dlen_in_dws));
 // Restrict the write pointer from rolling over
 always_comb wrptr_inc_valid = mbox_wrptr < (MBOX_SIZE_IN_DW-1);
 
@@ -191,9 +240,11 @@ always_comb begin : mbox_fsm_combo
     soc_has_lock_nxt = 0;
     rst_mbox_rdptr = 0; //resetting the read pointer will pre-load dataout
     rst_mbox_wrptr = 0;
-    inc_rdptr = 0; inc_wrptr = 0;
+    inc_rdptr = 0;
+    inc_wrptr = 0;
     uc_mbox_data_avail = 0;
     soc_mbox_data_avail = 0;
+    mbox_protocol_error_nxt = '{default: 0};
     mbox_fsm_ns = mbox_fsm_ps;
 
     unique casez (mbox_fsm_ps)
@@ -202,25 +253,40 @@ always_comb begin : mbox_fsm_combo
                 mbox_fsm_ns = MBOX_RDY_FOR_CMD;
                 soc_has_lock_nxt = req_data.soc_req; //remember if soc or uc requested the lock
             end
+            // Flag a non-fatal error, but don't change states, if mbox is already IDLE
+            // when an unexpected SOC access happens
+            if (req_dv && req_data.soc_req && !req_hold && (req_data.write || hwif_out.mbox_dataout.dataout.swacc)) begin
+                mbox_protocol_error_nxt.axs_without_lock = 1'b1;
+            end
         end
         MBOX_RDY_FOR_CMD: begin
             if (arc_MBOX_RDY_FOR_CMD_MBOX_RDY_FOR_DLEN) begin
                 mbox_fsm_ns = MBOX_RDY_FOR_DLEN;
             end
+            else if (arc_MBOX_RDY_FOR_CMD_MBOX_ERROR) begin
+                mbox_fsm_ns = MBOX_ERROR;
+                mbox_protocol_error_nxt.axs_incorrect_order = 1'b1;
+            end
             if (arc_FORCE_MBOX_UNLOCK) begin
                 mbox_fsm_ns = MBOX_IDLE;
                 rst_mbox_wrptr = 1;
                 rst_mbox_rdptr = 1;
+                mbox_protocol_error_nxt = '{default: 0};
             end
         end
         MBOX_RDY_FOR_DLEN: begin
             if (arc_MBOX_RDY_FOR_DLEN_MBOX_RDY_FOR_DATA) begin
                 mbox_fsm_ns = MBOX_RDY_FOR_DATA;
             end
+            else if (arc_MBOX_RDY_FOR_DLEN_MBOX_ERROR) begin
+                mbox_fsm_ns = MBOX_ERROR;
+                mbox_protocol_error_nxt.axs_incorrect_order = 1'b1;
+            end
             if (arc_FORCE_MBOX_UNLOCK) begin
                 mbox_fsm_ns = MBOX_IDLE;
                 rst_mbox_wrptr = 1;
                 rst_mbox_rdptr = 1;
+                mbox_protocol_error_nxt = '{default: 0};
             end
         end
         MBOX_RDY_FOR_DATA: begin
@@ -238,10 +304,17 @@ always_comb begin : mbox_fsm_combo
                 rst_mbox_wrptr = 1;
                 rst_mbox_rdptr = 1;
             end
+            else if (arc_MBOX_RDY_FOR_DATA_MBOX_ERROR) begin
+                mbox_fsm_ns = MBOX_ERROR;
+                mbox_protocol_error_nxt.axs_incorrect_order = 1'b1;
+            end
             if (arc_FORCE_MBOX_UNLOCK) begin
                 mbox_fsm_ns = MBOX_IDLE;
+                inc_wrptr = 0;
+                inc_rdptr = 0;
                 rst_mbox_wrptr = 1;
                 rst_mbox_rdptr = 1;
+                mbox_protocol_error_nxt = '{default: 0};
             end
         end
         //SoC set execute, data is for the uC
@@ -261,10 +334,17 @@ always_comb begin : mbox_fsm_combo
                 rst_mbox_wrptr = 1;
                 rst_mbox_rdptr = 1;
             end
+            else if (arc_MBOX_EXECUTE_UC_MBOX_ERROR) begin
+                mbox_fsm_ns = MBOX_ERROR;
+                mbox_protocol_error_nxt.axs_incorrect_order = 1'b1;
+            end
             if (arc_FORCE_MBOX_UNLOCK) begin
                 mbox_fsm_ns = MBOX_IDLE;
+                inc_wrptr = 0;
+                inc_rdptr = 0;
                 rst_mbox_wrptr = 1;
                 rst_mbox_rdptr = 1;
+                mbox_protocol_error_nxt = '{default: 0};
             end
         end
         //uC set execute, data is for the SoC
@@ -284,10 +364,26 @@ always_comb begin : mbox_fsm_combo
                 rst_mbox_wrptr = 1;
                 rst_mbox_rdptr = 1;
             end
+            else if (arc_MBOX_EXECUTE_SOC_MBOX_ERROR) begin
+                mbox_fsm_ns = MBOX_ERROR;
+                mbox_protocol_error_nxt.axs_incorrect_order = 1'b1;
+            end
             if (arc_FORCE_MBOX_UNLOCK) begin
                 mbox_fsm_ns = MBOX_IDLE;
+                inc_wrptr = 0;
+                inc_rdptr = 0;
                 rst_mbox_wrptr = 1;
                 rst_mbox_rdptr = 1;
+                mbox_protocol_error_nxt = '{default: 0};
+            end
+        end
+        MBOX_ERROR: begin
+            mbox_protocol_error_nxt = '{default: 0};
+            if (arc_FORCE_MBOX_UNLOCK) begin
+                mbox_fsm_ns = MBOX_IDLE;
+                rst_mbox_wrptr = 1;
+                rst_mbox_rdptr = 1;
+                mbox_protocol_error_nxt = '{default: 0};
             end
         end
 
@@ -297,10 +393,17 @@ always_comb begin : mbox_fsm_combo
     endcase
 end
 
+// Any ol' PAUSER is fine for reg-reads (except dataout)
+// NOTE: This only captures accesses by APB agents that are valid, but do not
+//       have lock. Invalid agent accesses are blocked by arbiter.
+assign mbox_inv_pauser_axs = req_dv && req_data.soc_req && !req_hold &&
+                             !valid_requester && !valid_receiver &&
+                             (req_data.write || hwif_out.mbox_dataout.dataout.swacc);
+
 
 //increment read ptr only if its allowed
-always_comb mbox_protocol_sram_rd = (inc_rdptr & mbox_rd_valid) | rst_mbox_rdptr;
-always_comb mbox_protocol_sram_we = inc_wrptr;
+always_comb mbox_protocol_sram_rd = inc_rdptr | rst_mbox_rdptr;
+always_comb mbox_protocol_sram_we = inc_wrptr & ~mbox_wr_full;
 
 //flops
 always_ff @(posedge clk or negedge rst_b) begin
@@ -309,10 +412,13 @@ always_ff @(posedge clk or negedge rst_b) begin
         soc_has_lock <= '0;
         dir_req_rd_phase <= '0;
         mbox_wrptr <= '0;
+        mbox_wr_full <= '0;
         mbox_rdptr <= '0;
+        mbox_rd_full <= '0;
         mbox_protocol_sram_rd_f <= '0;
-        sram_ecc_cor_waddr <= '0;
         dlen_in_dws <= '0;
+        mbox_protocol_error <= '0;
+        sram_rd_ecc_en <= '0;
     end
     else begin
         mbox_fsm_ps <= mbox_fsm_ns;
@@ -320,12 +426,16 @@ always_ff @(posedge clk or negedge rst_b) begin
                         hwif_out.mbox_lock.lock.value ? soc_has_lock : '0;
         dir_req_rd_phase <= dir_req_dv_q & ~sha_sram_req_dv & ~req_data.write;
         mbox_wrptr <= ((inc_wrptr & wrptr_inc_valid) | rst_mbox_wrptr) ? mbox_wrptr_nxt : mbox_wrptr;
+        mbox_wr_full <= (inc_wrptr | rst_mbox_wrptr) ? mbox_wr_full_nxt : mbox_wr_full;
         mbox_rdptr <= (mbox_protocol_sram_rd) ? mbox_rdptr_nxt : mbox_rdptr;
-        mbox_protocol_sram_rd_f <= (mbox_protocol_sram_rd | mbox_protocol_sram_rd_f) ? (mbox_protocol_sram_rd) : mbox_protocol_sram_rd_f;
-        sram_ecc_cor_waddr <= /*dir_req_rd_phase ? sram_ecc_cor_waddr :*/
-                                                 sram_rdaddr;
+        mbox_protocol_sram_rd_f <= (mbox_protocol_sram_rd | mbox_protocol_sram_rd_f) ? mbox_protocol_sram_rd : mbox_protocol_sram_rd_f;
+        mbox_rd_full <= (inc_rdptr | rst_mbox_rdptr) ? mbox_rd_full_nxt : mbox_rd_full;
+        mbox_rd_valid_f <= (mbox_rd_valid | mbox_rd_valid_f) ? mbox_rd_valid : mbox_rd_valid_f;
                              
         dlen_in_dws <= latch_dlen_in_dws ? dlen_in_dws_nxt : dlen_in_dws;                    
+        mbox_protocol_error <= mbox_protocol_error_nxt;
+        //enable ecc for mbox protocol, direct reads, or SHA direct reads
+        sram_rd_ecc_en <= mbox_protocol_sram_rd | (dir_req_dv_q & ~sha_sram_req_dv & ~req_data.write) | sha_sram_req_dv;
     end
 end
 
@@ -345,27 +455,26 @@ always_comb req_hold = (dir_req_dv_q & ~req_data.write) |
                        (dir_req_dv & sha_sram_req_dv) |
                        (hwif_out.mbox_dataout.dataout.swacc & mbox_protocol_sram_rd_f);
 
-always_comb sha_sram_hold = sram_single_ecc_error/* || sram_ecc_cor_we*/;
+always_comb sha_sram_hold = 1'b0;
 
 //SRAM interface
-always_comb sram_ecc_cor_we = sram_single_ecc_error; // TODO we probably want this to be a reg-stage to reduce combo logic SRAM -> rdata -> wdata -> SRAM
-always_comb sram_we = dir_req_wr_ph | mbox_protocol_sram_we | sram_ecc_cor_we;
+always_comb sram_we = dir_req_wr_ph | mbox_protocol_sram_we;
 //align the direct address to a word
 always_comb sram_rdaddr = dir_req_dv_q ? dir_req_addr : 
                           rst_mbox_rdptr ? 'd0 : mbox_rdptr;
-always_comb sram_waddr = sram_ecc_cor_we ? sram_ecc_cor_waddr :
-                         dir_req_dv_q    ? dir_req_addr : mbox_wrptr;
+always_comb sram_waddr = dir_req_dv_q    ? dir_req_addr : mbox_wrptr;
 //data phase after request for direct access
 //We want to mask the read data for certain accesses
-always_comb rdata = dir_req_rd_phase ? sram_rdata_cor : ({DATA_W{~mask_rdata}} & csr_rdata);
+always_comb rdata = ({DATA_W{~mask_rdata}} & csr_rdata);
+always_comb dir_rdata = dir_req_rd_phase ? sram_rdata_cor : '0;
 
 always_comb begin: mbox_sram_inf
     //read live on direct access, or when pointer has been incremented, for pre-load on read pointer reset, or ecc correction
-    mbox_sram_req.cs = dir_req_dv_q | mbox_protocol_sram_we | mbox_protocol_sram_rd | sram_ecc_cor_we;
+    mbox_sram_req.cs = dir_req_dv_q | mbox_protocol_sram_we | mbox_protocol_sram_rd;
     mbox_sram_req.we = sram_we;
     mbox_sram_req.addr = sram_we ? sram_waddr : sram_rdaddr;
-    mbox_sram_req.wdata.data = sram_ecc_cor_we ? sram_rdata_cor     : sram_wdata;
-    mbox_sram_req.wdata.ecc  = sram_ecc_cor_we ? sram_rdata_cor_ecc : sram_wdata_ecc;
+    mbox_sram_req.wdata.data = sram_wdata;
+    mbox_sram_req.wdata.ecc  = sram_wdata_ecc;
 
     sram_rdata     = mbox_sram_resp.rdata.data;
     sram_rdata_ecc = mbox_sram_resp.rdata.ecc;
@@ -384,7 +493,7 @@ initial assert(DATA_W == 32) else
     $error("%m::rvecc_encode supports 32-bit data width; must change SRAM ECC implementation to support DATA_W = %d", DATA_W);
 // synthesis translate_on
 rvecc_decode ecc_decode (
-    .en              (dir_req_rd_phase | mbox_protocol_sram_rd_f),
+    .en              (sram_rd_ecc_en       ),
     .sed_ded         ( 1'b0                ),    // 1 : means only detection
     .din             (sram_rdata           ),
     .ecc_in          (sram_rdata_ecc       ),
@@ -404,12 +513,15 @@ always_comb mbox_wrptr_nxt = rst_mbox_wrptr ? '0 :
                              (inc_wrptr & wrptr_inc_valid) ? mbox_wrptr + 'd1 : 
                                                              mbox_wrptr;
 
+always_comb mbox_wr_full_nxt = rst_mbox_wrptr ? '0 : inc_wrptr & (mbox_wrptr == (DEPTH-1));
 
 //in execute state we increment the pointer each time we write
 always_comb mbox_rdptr_nxt = rst_mbox_rdptr ? 'd1 :
                              (inc_rdptr & rdptr_inc_valid) ? mbox_rdptr + 'd1 : 
                                                              mbox_rdptr;
 
+always_comb mbox_rd_full_nxt = rst_mbox_rdptr ? '0 : inc_rdptr & (mbox_rdptr == (DEPTH-1));
+
 //Intterupts
 //Notify uC when it has the lock and SoC is requesting the lock
 always_comb soc_req_mbox_lock = hwif_out.mbox_lock.lock.value & ~soc_has_lock & hwif_out.mbox_lock.lock.swmod & req_data.soc_req;
@@ -434,7 +546,7 @@ always_comb hwif_in.mbox_dataout.dataout.swwe = '0; //no sw write enable, but ne
 //update dataout whenever we read from the sram for a dataout access
 //we load the first entry on the arc to execute
 always_comb hwif_in.mbox_dataout.dataout.we = mbox_protocol_sram_rd_f;
-always_comb hwif_in.mbox_dataout.dataout.next = sram_rdata_cor;
+always_comb hwif_in.mbox_dataout.dataout.next = mbox_rd_valid_f ? sram_rdata_cor : '0;
 //clear the lock when moving from execute to idle
 always_comb hwif_in.mbox_lock.lock.hwclr = arc_MBOX_EXECUTE_SOC_MBOX_IDLE | arc_MBOX_EXECUTE_UC_MBOX_IDLE | arc_FORCE_MBOX_UNLOCK;
 //clear the mailbox status when we go back to IDLE
@@ -445,10 +557,12 @@ always_comb hwif_in.mbox_execute.execute.hwclr = arc_FORCE_MBOX_UNLOCK;
 always_comb hwif_in.mbox_status.ecc_single_error.hwset = sram_single_ecc_error;
 always_comb hwif_in.mbox_status.ecc_double_error.hwset = sram_double_ecc_error;
 always_comb hwif_in.mbox_status.soc_has_lock.next = soc_has_lock;
+always_comb hwif_in.mbox_status.mbox_rdptr.next = mbox_rdptr;
 
 always_comb dmi_reg.MBOX_DLEN = hwif_out.mbox_dlen.length.value;
 always_comb dmi_reg.MBOX_DOUT = hwif_out.mbox_dataout.dataout.value;
-always_comb dmi_reg.MBOX_STATUS = {22'd0,                                       /* [31:10] */
+always_comb dmi_reg.MBOX_STATUS = {7'd0,                                        /* [31:25] */
+                                   hwif_out.mbox_status.mbox_rdptr.value,       /* [24:10]*/
                                    hwif_out.mbox_status.soc_has_lock.value,     /* [9] */
                                    hwif_out.mbox_status.mbox_fsm_ps.value,      /* [8:6] */
                                    hwif_out.mbox_status.ecc_double_error.value, /* [5] */
@@ -483,7 +597,8 @@ mbox_csr1(
     .hwif_out(hwif_out)
 );
 
-`CALIPTRA_ASSERT_MUTEX(ERR_MBOX_ACCESS_MUTEX, {dir_req_dv_q | mbox_protocol_sram_we | mbox_protocol_sram_rd | sram_ecc_cor_we}, clk, rst_b)
+`CALIPTRA_ASSERT_MUTEX(ERR_MBOX_ACCESS_MUTEX, {dir_req_dv_q , mbox_protocol_sram_we , mbox_protocol_sram_rd }, clk, rst_b)
 `CALIPTRA_ASSERT_MUTEX(ERR_MBOX_DIR_SHA_COLLISION, {dir_req_dv, sha_sram_req_dv}, clk, rst_b)
+`CALIPTRA_ASSERT_NEVER(ERR_MBOX_DIR_REQ_FROM_SOC, (dir_req_dv & req_data.soc_req), clk, rst_b)
 
 endmodule
diff --git a/src/soc_ifc/rtl/mbox_csr.rdl b/src/soc_ifc/rtl/mbox_csr.rdl
index 02223d3a4..8a67121be 100644
--- a/src/soc_ifc/rtl/mbox_csr.rdl
+++ b/src/soc_ifc/rtl/mbox_csr.rdl
@@ -36,7 +36,7 @@ addrmap mbox_csr {
         desc="Mailbox lock register for mailbox access, reading 0 will set the lock
         [br]Caliptra Access: RO
         [br]SOC Access:      RO";
-        field {rset; sw=r; hw=r; hwclr=true; swmod=true;} lock=0;
+        field {rset; sw=r; hw=r; hwclr=true; precedence=hw; swmod=true;} lock=0;
     } mbox_lock;
 
     // user register
@@ -88,7 +88,7 @@ addrmap mbox_csr {
         desc="Mailbox execute register indicates to receiver that the sender is done
         [br]Caliptra Access: RW
         [br]SOC Access:      RW";
-        field {sw=rw; hw=r; swwe=valid_requester; hwclr;} execute=0;
+        field {sw=rw; hw=r; swwe=valid_requester; hwclr; precedence=hw; swmod=true;} execute=0;
     } mbox_execute;
 
     reg {
@@ -115,7 +115,7 @@ addrmap mbox_csr {
                     desc = "The requested command experienced a failure.";
                 };
             };
-            sw=rw; hw=r; swwe=valid_receiver; encode = mbox_status_e; hwclr;} status[4]=0;
+            sw=rw; hw=r; swwe=valid_receiver; encode = mbox_status_e; hwclr; precedence=hw; swmod=true;} status[4]=0;
         field {
             name = "Mailbox ECC Single Error";
             desc = "Indicates a correctable ECC single-bit error was
@@ -164,6 +164,9 @@ addrmap mbox_csr {
                 MBOX_EXECUTE_SOC = 3'b100 {
                     desc = "Mailbox has data for SoC";
                 };
+                MBOX_ERROR = 3'b111 {
+                    desc = "Mailbox Protocol Error detected";
+                };
             };
             sw=r; hw=rw; encode = mbox_fsm_e;
         } mbox_fsm_ps[3] = 0;
@@ -174,6 +177,13 @@ addrmap mbox_csr {
                     [br]SOC Access:      RO
                     [br]TAP Access [in debug/manuf mode]: RO";
             sw=r; hw=rw;} soc_has_lock=1'b0;
+        field {
+            name = "Current Mailbox Read Pointer";
+            desc = "Returns the current read pointer for the mailbox
+                    [br]Caliptra Access: RO
+                    [br]SOC Access:      RO
+                    [br]TAP Access [in debug/manuf mode]: RO";
+            sw=r; hw=rw;} mbox_rdptr[15] = 0;
     } mbox_status;
 
     reg {
diff --git a/src/soc_ifc/rtl/mbox_csr.sv b/src/soc_ifc/rtl/mbox_csr.sv
index 543af60b3..cefd5b73d 100644
--- a/src/soc_ifc/rtl/mbox_csr.sv
+++ b/src/soc_ifc/rtl/mbox_csr.sv
@@ -169,6 +169,10 @@ module mbox_csr (
                 logic next;
                 logic load_next;
             } soc_has_lock;
+            struct packed{
+                logic [14:0] next;
+                logic load_next;
+            } mbox_rdptr;
         } mbox_status;
         struct packed{
             struct packed{
@@ -231,6 +235,9 @@ module mbox_csr (
             struct packed{
                 logic value;
             } soc_has_lock;
+            struct packed{
+                logic [14:0] value;
+            } mbox_rdptr;
         } mbox_status;
         struct packed{
             struct packed{
@@ -244,12 +251,12 @@ module mbox_csr (
     always_comb begin
         automatic logic [0:0] next_c = field_storage.mbox_lock.lock.value;
         automatic logic load_next_c = '0;
-        if(decoded_reg_strb.mbox_lock && !decoded_req_is_wr) begin // SW set on read
-            next_c = '1;
-            load_next_c = '1;
-        end else if(hwif_in.mbox_lock.lock.hwclr) begin // HW Clear
+        if(hwif_in.mbox_lock.lock.hwclr) begin // HW Clear
             next_c = '0;
             load_next_c = '1;
+        end else if(decoded_reg_strb.mbox_lock && !decoded_req_is_wr) begin // SW set on read
+            next_c = '1;
+            load_next_c = '1;
         end
         field_combo.mbox_lock.lock.next = next_c;
         field_combo.mbox_lock.lock.load_next = load_next_c;
@@ -367,12 +374,12 @@ module mbox_csr (
     always_comb begin
         automatic logic [0:0] next_c = field_storage.mbox_execute.execute.value;
         automatic logic load_next_c = '0;
-        if(decoded_reg_strb.mbox_execute && decoded_req_is_wr && hwif_in.valid_requester) begin // SW write
-            next_c = (field_storage.mbox_execute.execute.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
-            load_next_c = '1;
-        end else if(hwif_in.mbox_execute.execute.hwclr) begin // HW Clear
+        if(hwif_in.mbox_execute.execute.hwclr) begin // HW Clear
             next_c = '0;
             load_next_c = '1;
+        end else if(decoded_reg_strb.mbox_execute && decoded_req_is_wr && hwif_in.valid_requester) begin // SW write
+            next_c = (field_storage.mbox_execute.execute.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
+            load_next_c = '1;
         end
         field_combo.mbox_execute.execute.next = next_c;
         field_combo.mbox_execute.execute.load_next = load_next_c;
@@ -385,16 +392,17 @@ module mbox_csr (
         end
     end
     assign hwif_out.mbox_execute.execute.value = field_storage.mbox_execute.execute.value;
+    assign hwif_out.mbox_execute.execute.swmod = decoded_reg_strb.mbox_execute && decoded_req_is_wr;
     // Field: mbox_csr.mbox_status.status
     always_comb begin
         automatic logic [3:0] next_c = field_storage.mbox_status.status.value;
         automatic logic load_next_c = '0;
-        if(decoded_reg_strb.mbox_status && decoded_req_is_wr && hwif_in.valid_receiver) begin // SW write
-            next_c = (field_storage.mbox_status.status.value & ~decoded_wr_biten[3:0]) | (decoded_wr_data[3:0] & decoded_wr_biten[3:0]);
-            load_next_c = '1;
-        end else if(hwif_in.mbox_status.status.hwclr) begin // HW Clear
+        if(hwif_in.mbox_status.status.hwclr) begin // HW Clear
             next_c = '0;
             load_next_c = '1;
+        end else if(decoded_reg_strb.mbox_status && decoded_req_is_wr && hwif_in.valid_receiver) begin // SW write
+            next_c = (field_storage.mbox_status.status.value & ~decoded_wr_biten[3:0]) | (decoded_wr_data[3:0] & decoded_wr_biten[3:0]);
+            load_next_c = '1;
         end
         field_combo.mbox_status.status.next = next_c;
         field_combo.mbox_status.status.load_next = load_next_c;
@@ -407,6 +415,7 @@ module mbox_csr (
         end
     end
     assign hwif_out.mbox_status.status.value = field_storage.mbox_status.status.value;
+    assign hwif_out.mbox_status.status.swmod = decoded_reg_strb.mbox_status && decoded_req_is_wr;
     // Field: mbox_csr.mbox_status.ecc_single_error
     always_comb begin
         automatic logic [0:0] next_c = field_storage.mbox_status.ecc_single_error.value;
@@ -489,6 +498,25 @@ module mbox_csr (
         end
     end
     assign hwif_out.mbox_status.soc_has_lock.value = field_storage.mbox_status.soc_has_lock.value;
+    // Field: mbox_csr.mbox_status.mbox_rdptr
+    always_comb begin
+        automatic logic [14:0] next_c = field_storage.mbox_status.mbox_rdptr.value;
+        automatic logic load_next_c = '0;
+        if(1) begin // HW Write
+            next_c = hwif_in.mbox_status.mbox_rdptr.next;
+            load_next_c = '1;
+        end
+        field_combo.mbox_status.mbox_rdptr.next = next_c;
+        field_combo.mbox_status.mbox_rdptr.load_next = load_next_c;
+    end
+    always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+        if(~hwif_in.cptra_rst_b) begin
+            field_storage.mbox_status.mbox_rdptr.value <= 'h0;
+        end else if(field_combo.mbox_status.mbox_rdptr.load_next) begin
+            field_storage.mbox_status.mbox_rdptr.value <= field_combo.mbox_status.mbox_rdptr.next;
+        end
+    end
+    assign hwif_out.mbox_status.mbox_rdptr.value = field_storage.mbox_status.mbox_rdptr.value;
     // Field: mbox_csr.mbox_unlock.unlock
     always_comb begin
         automatic logic [0:0] next_c = field_storage.mbox_unlock.unlock.value;
@@ -534,7 +562,8 @@ module mbox_csr (
     assign readback_array[7][5:5] = (decoded_reg_strb.mbox_status && !decoded_req_is_wr) ? field_storage.mbox_status.ecc_double_error.value : '0;
     assign readback_array[7][8:6] = (decoded_reg_strb.mbox_status && !decoded_req_is_wr) ? field_storage.mbox_status.mbox_fsm_ps.value : '0;
     assign readback_array[7][9:9] = (decoded_reg_strb.mbox_status && !decoded_req_is_wr) ? field_storage.mbox_status.soc_has_lock.value : '0;
-    assign readback_array[7][31:10] = '0;
+    assign readback_array[7][24:10] = (decoded_reg_strb.mbox_status && !decoded_req_is_wr) ? field_storage.mbox_status.mbox_rdptr.value : '0;
+    assign readback_array[7][31:25] = '0;
     assign readback_array[8][0:0] = (decoded_reg_strb.mbox_unlock && !decoded_req_is_wr) ? field_storage.mbox_unlock.unlock.value : '0;
     assign readback_array[8][31:1] = '0;
 
diff --git a/src/soc_ifc/rtl/mbox_csr_covergroups.svh b/src/soc_ifc/rtl/mbox_csr_covergroups.svh
new file mode 100644
index 000000000..3664e1fc3
--- /dev/null
+++ b/src/soc_ifc/rtl/mbox_csr_covergroups.svh
@@ -0,0 +1,324 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+`ifndef MBOX_CSR_COVERGROUPS
+    `define MBOX_CSR_COVERGROUPS
+
+    import soc_ifc_pkg::*;
+    
+    /*----------------------- MBOX_CSR__MBOX_LOCK COVERGROUPS -----------------------*/
+    covergroup mbox_csr__mbox_lock_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup mbox_csr__mbox_lock_fld_cg with function sample(
+    input bit [1-1:0] lock
+    );
+        option.per_instance = 1;
+        lock_cp : coverpoint lock;
+        lock_edge_cp : coverpoint lock {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+
+    /*----------------------- MBOX_CSR__MBOX_USER COVERGROUPS -----------------------*/
+    covergroup mbox_csr__mbox_user_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup mbox_csr__mbox_user_fld_cg with function sample(
+    input bit [32-1:0] user
+    );
+        option.per_instance = 1;
+        user_cp : coverpoint user {
+            bins zero_val = {32'h0};
+            bins rand_val[64] = {[1:32'hFFFF_FFFE]};
+            bins ones_val = {{32{1'b1}}};
+            wildcard bins set = (0 => 32'h????_????);
+            wildcard bins clr = (32'h????_???? => 0);
+        }
+
+    endgroup
+
+    /*----------------------- MBOX_CSR__MBOX_CMD COVERGROUPS -----------------------*/
+    covergroup mbox_csr__mbox_cmd_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup mbox_csr__mbox_cmd_fld_cg with function sample(
+    input bit [32-1:0] command
+    );
+        option.per_instance = 1;
+        command_cp : coverpoint command {
+            bins zero_val = {32'h0};
+            bins rand_val[64] = {[1:32'hFFFF_FFFE]};
+            bins ones_val = {{32{1'b1}}};
+            wildcard bins set = (0 => 32'h????_????);
+            wildcard bins clr = (32'h????_???? => 0);
+        }
+
+    endgroup
+
+    /*----------------------- MBOX_CSR__MBOX_DLEN COVERGROUPS -----------------------*/
+    covergroup mbox_csr__mbox_dlen_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup mbox_csr__mbox_dlen_fld_cg with function sample(
+    input bit [32-1:0] length
+    );
+        option.per_instance = 1;
+        // TODO These need a cross with lock/execute/fsm state to properly get coverage...
+        length_cp : coverpoint length {
+            bins zero_val = {32'h0};
+            bins tiny_val = {[1:3]};
+            bins small_val = {[4:15]};
+            bins medium_val = {[16:4095]};
+            bins large_val = {[4096:32768]};
+            bins legal_word_aligned_val  = {[1:32'h8000]} with (~|item[0]);
+            bins legal_dword_aligned_val = {[1:32'h8000]} with (~|item[1:0]);
+            bins legal_qword_aligned_val = {[1:32'h8000]} with (~|item[2:0]);
+            bins legal_oword_aligned_val = {[1:32'h8000]} with (~|item[3:0]);
+            bins oversize_val = {[32769:32'hFFFF_FFFE]}; /* Value larger than mailbox size */
+            bins ones_val = {{32{1'b1}}};
+            wildcard bins set = (0 => 32'h????_????);
+            wildcard bins clr = (32'h????_???? => 0);
+        }
+
+    endgroup
+
+    /*----------------------- MBOX_CSR__MBOX_DATAIN COVERGROUPS -----------------------*/
+    covergroup mbox_csr__mbox_datain_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup mbox_csr__mbox_datain_fld_cg with function sample(
+    input bit [32-1:0] datain
+    );
+        option.per_instance = 1;
+        datain_cp : coverpoint datain {
+            bins zero_val = {32'h0};
+            bins rand_val[64] = {[1:32'hFFFF_FFFE]};
+            bins ones_val = {{32{1'b1}}};
+            wildcard bins set = (0 => 32'h????_????);
+            wildcard bins clr = (32'h????_???? => 0);
+        }
+
+    endgroup
+
+    /*----------------------- MBOX_CSR__MBOX_DATAOUT COVERGROUPS -----------------------*/
+    covergroup mbox_csr__mbox_dataout_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup mbox_csr__mbox_dataout_fld_cg with function sample(
+    input bit [32-1:0] dataout
+    );
+        option.per_instance = 1;
+        dataout_cp : coverpoint dataout {
+            bins zero_val = {32'h0};
+            bins rand_val[64] = {[1:32'hFFFF_FFFE]};
+            bins ones_val = {{32{1'b1}}};
+            wildcard bins set = (0 => 32'h????_????);
+            wildcard bins clr = (32'h????_???? => 0);
+        }
+
+    endgroup
+
+    /*----------------------- MBOX_CSR__MBOX_EXECUTE COVERGROUPS -----------------------*/
+    covergroup mbox_csr__mbox_execute_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup mbox_csr__mbox_execute_fld_cg with function sample(
+    input bit [1-1:0] execute
+    );
+        option.per_instance = 1;
+        execute_cp : coverpoint execute;
+        execute_edge_cp : coverpoint execute {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+
+    /*----------------------- MBOX_CSR__MBOX_STATUS_ECC_DOUBLE_ERROR_38CEC4B0_ECC_SINGLE_ERROR_9C62B760 COVERGROUPS -----------------------*/
+    covergroup mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760_fld_cg with function sample(
+    input bit [4-1:0] status,
+    input bit [1-1:0] ecc_single_error,
+    input bit [1-1:0] ecc_double_error,
+    input bit [3-1:0] mbox_fsm_ps,
+    input bit [1-1:0] soc_has_lock
+    );
+        option.per_instance = 1;
+        status_cp : coverpoint status;
+        ecc_single_error_cp : coverpoint ecc_single_error;
+        ecc_double_error_cp : coverpoint ecc_double_error;
+        mbox_fsm_ps_cp : coverpoint mbox_fsm_ps {
+            bins MBOX_IDLE                                    = {mbox_fsm_state_e'(MBOX_IDLE        )};
+            bins MBOX_RDY_FOR_CMD                             = {mbox_fsm_state_e'(MBOX_RDY_FOR_CMD )};
+            bins MBOX_RDY_FOR_DLEN                            = {mbox_fsm_state_e'(MBOX_RDY_FOR_DLEN)};
+            bins MBOX_RDY_FOR_DATA                            = {mbox_fsm_state_e'(MBOX_RDY_FOR_DATA)};
+            bins MBOX_EXECUTE_UC                              = {mbox_fsm_state_e'(MBOX_EXECUTE_UC  )};
+            bins MBOX_EXECUTE_SOC                             = {mbox_fsm_state_e'(MBOX_EXECUTE_SOC )};
+            bins MBOX_ERROR                                   = {mbox_fsm_state_e'(MBOX_ERROR       )};
+        }
+        mbox_fsm_ps_edge_cp : coverpoint mbox_fsm_ps {
+            bins TRANSITION_IDLE_RDY_FOR_CMD                  = (mbox_fsm_state_e'(MBOX_IDLE)         => mbox_fsm_state_e'(MBOX_RDY_FOR_CMD));
+            bins TRANSITION_RDY_FOR_CMD_RDY_FOR_DLEN          = (mbox_fsm_state_e'(MBOX_RDY_FOR_CMD)  => mbox_fsm_state_e'(MBOX_RDY_FOR_DLEN));
+            bins TRANSITION_RDY_FOR_DLEN_RDY_FOR_DATA         = (mbox_fsm_state_e'(MBOX_RDY_FOR_DLEN) => mbox_fsm_state_e'(MBOX_RDY_FOR_DATA));
+            bins TRANSITION_RDY_FOR_DATA_EXECUTE_UC           = (mbox_fsm_state_e'(MBOX_RDY_FOR_DATA) => mbox_fsm_state_e'(MBOX_EXECUTE_UC));
+            bins TRANSITION_RDY_FOR_DATA_EXECUTE_SOC          = (mbox_fsm_state_e'(MBOX_RDY_FOR_DATA) => mbox_fsm_state_e'(MBOX_EXECUTE_SOC));
+            bins TRANSITION_EXECUTE_UC_EXECUTE_SOC            = (mbox_fsm_state_e'(MBOX_EXECUTE_UC)   => mbox_fsm_state_e'(MBOX_EXECUTE_SOC));
+            bins TRANSITION_EXECUTE_SOC_EXECUTE_UC            = (mbox_fsm_state_e'(MBOX_EXECUTE_SOC)  => mbox_fsm_state_e'(MBOX_EXECUTE_UC));
+            bins TRANSITION_EXECUTE_UC_IDLE                   = (mbox_fsm_state_e'(MBOX_EXECUTE_UC)   => mbox_fsm_state_e'(MBOX_IDLE));
+            bins TRANSITION_EXECUTE_SOC_IDLE                  = (mbox_fsm_state_e'(MBOX_EXECUTE_SOC)  => mbox_fsm_state_e'(MBOX_IDLE));
+            bins TRANSITION_RDY_FOR_CMD_ERROR                 = (mbox_fsm_state_e'(MBOX_RDY_FOR_CMD)  => mbox_fsm_state_e'(MBOX_ERROR));
+            bins TRANSITION_RDY_FOR_DLEN_ERROR                = (mbox_fsm_state_e'(MBOX_RDY_FOR_DLEN) => mbox_fsm_state_e'(MBOX_ERROR));
+            bins TRANSITION_RDY_FOR_DATA_ERROR                = (mbox_fsm_state_e'(MBOX_RDY_FOR_DATA) => mbox_fsm_state_e'(MBOX_ERROR));
+            bins TRANSITION_EXECUTE_UC_ERROR                  = (mbox_fsm_state_e'(MBOX_EXECUTE_UC)   => mbox_fsm_state_e'(MBOX_ERROR));
+            bins TRANSITION_EXECUTE_SOC_ERROR                 = (mbox_fsm_state_e'(MBOX_EXECUTE_SOC)  => mbox_fsm_state_e'(MBOX_ERROR));
+            bins TRANSITION_ERROR_IDLE                        = (mbox_fsm_state_e'(MBOX_ERROR)        => mbox_fsm_state_e'(MBOX_IDLE));
+//            illegal_bins TRANSITION_IDLE_ERROR                = (mbox_fsm_state_e'(MBOX_IDLE)         => mbox_fsm_state_e'(MBOX_ERROR));
+//            illegal_bins TRANSITION_IDLE_RDY_FOR_DLEN         = (mbox_fsm_state_e'(MBOX_IDLE)         => mbox_fsm_state_e'(MBOX_RDY_FOR_DLEN));
+//            illegal_bins TRANSITION_IDLE_RDY_FOR_DATA         = (mbox_fsm_state_e'(MBOX_IDLE)         => mbox_fsm_state_e'(MBOX_RDY_FOR_DATA));
+//            illegal_bins TRANSITION_IDLE_EXECUTE_UC           = (mbox_fsm_state_e'(MBOX_IDLE)         => mbox_fsm_state_e'(MBOX_EXECUTE_UC));
+//            illegal_bins TRANSITION_IDLE_EXECUTE_SOC          = (mbox_fsm_state_e'(MBOX_IDLE)         => mbox_fsm_state_e'(MBOX_EXECUTE_SOC));
+//            illegal_bins TRANSITION_RDY_FOR_CMD_RDY_FOR_DATA  = (mbox_fsm_state_e'(MBOX_RDY_FOR_CMD)  => mbox_fsm_state_e'(MBOX_RDY_FOR_DATA));
+//            illegal_bins TRANSITION_RDY_FOR_CMD_EXECUTE_UC    = (mbox_fsm_state_e'(MBOX_RDY_FOR_CMD)  => mbox_fsm_state_e'(MBOX_EXECUTE_UC));
+//            illegal_bins TRANSITION_RDY_FOR_CMD_EXECUTE_SOC   = (mbox_fsm_state_e'(MBOX_RDY_FOR_CMD)  => mbox_fsm_state_e'(MBOX_EXECUTE_SOC));
+//            illegal_bins TRANSITION_RDY_FOR_DLEN_RDY_FOR_CMD  = (mbox_fsm_state_e'(MBOX_RDY_FOR_DLEN) => mbox_fsm_state_e'(MBOX_RDY_FOR_CMD));
+//            illegal_bins TRANSITION_RDY_FOR_DLEN_EXECUTE_UC   = (mbox_fsm_state_e'(MBOX_RDY_FOR_DLEN) => mbox_fsm_state_e'(MBOX_EXECUTE_UC));
+//            illegal_bins TRANSITION_RDY_FOR_DLEN_EXECUTE_SOC  = (mbox_fsm_state_e'(MBOX_RDY_FOR_DLEN) => mbox_fsm_state_e'(MBOX_EXECUTE_SOC));
+//            illegal_bins TRANSITION_RDY_FOR_DATA_RDY_FOR_CMD  = (mbox_fsm_state_e'(MBOX_RDY_FOR_DATA) => mbox_fsm_state_e'(MBOX_RDY_FOR_CMD));
+//            illegal_bins TRANSITION_RDY_FOR_DATA_RDY_FOR_DLEN = (mbox_fsm_state_e'(MBOX_RDY_FOR_DATA) => mbox_fsm_state_e'(MBOX_RDY_FOR_DLEN));
+//            illegal_bins TRANSITION_EXECUTE_UC_RDY_FOR_CMD    = (mbox_fsm_state_e'(MBOX_EXECUTE_UC)   => mbox_fsm_state_e'(MBOX_RDY_FOR_CMD));
+//            illegal_bins TRANSITION_EXECUTE_UC_RDY_FOR_DLEN   = (mbox_fsm_state_e'(MBOX_EXECUTE_UC)   => mbox_fsm_state_e'(MBOX_RDY_FOR_DLEN));
+//            illegal_bins TRANSITION_EXECUTE_UC_RDY_FOR_DATA   = (mbox_fsm_state_e'(MBOX_EXECUTE_UC)   => mbox_fsm_state_e'(MBOX_RDY_FOR_DATA));
+//            illegal_bins TRANSITION_EXECUTE_SOC_RDY_FOR_CMD   = (mbox_fsm_state_e'(MBOX_EXECUTE_SOC)  => mbox_fsm_state_e'(MBOX_RDY_FOR_CMD));
+//            illegal_bins TRANSITION_EXECUTE_SOC_RDY_FOR_DLEN  = (mbox_fsm_state_e'(MBOX_EXECUTE_SOC)  => mbox_fsm_state_e'(MBOX_RDY_FOR_DLEN));
+//            illegal_bins TRANSITION_EXECUTE_SOC_RDY_FOR_DATA  = (mbox_fsm_state_e'(MBOX_EXECUTE_SOC)  => mbox_fsm_state_e'(MBOX_RDY_FOR_DATA));
+//            illegal_bins TRANSITION_ERROR_RDY_FOR_CMD         = (mbox_fsm_state_e'(MBOX_ERROR)        => mbox_fsm_state_e'(MBOX_RDY_FOR_CMD));
+//            illegal_bins TRANSITION_ERROR_RDY_FOR_DLEN        = (mbox_fsm_state_e'(MBOX_ERROR)        => mbox_fsm_state_e'(MBOX_RDY_FOR_DLEN));
+//            illegal_bins TRANSITION_ERROR_RDY_FOR_DATA        = (mbox_fsm_state_e'(MBOX_ERROR)        => mbox_fsm_state_e'(MBOX_RDY_FOR_DATA));
+//            illegal_bins TRANSITION_ERROR_EXECUTE_UC          = (mbox_fsm_state_e'(MBOX_ERROR)        => mbox_fsm_state_e'(MBOX_EXECUTE_UC));
+//            illegal_bins TRANSITION_ERROR_EXECUTE_SOC         = (mbox_fsm_state_e'(MBOX_ERROR)        => mbox_fsm_state_e'(MBOX_EXECUTE_SOC));
+        }
+        soc_has_lock_cp : coverpoint soc_has_lock;
+        status_edge_cp : coverpoint status {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+        ecc_single_error_edge_cp : coverpoint ecc_single_error {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+        ecc_double_error_edge_cp : coverpoint ecc_double_error {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+        soc_has_lock_edge_cp : coverpoint soc_has_lock {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+
+    /*----------------------- MBOX_CSR__MBOX_UNLOCK COVERGROUPS -----------------------*/
+    covergroup mbox_csr__mbox_unlock_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup mbox_csr__mbox_unlock_fld_cg with function sample(
+    input bit [1-1:0] unlock
+    );
+        option.per_instance = 1;
+        unlock_cp : coverpoint unlock;
+        unlock_edge_cp : coverpoint unlock {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+
+`endif
diff --git a/src/soc_ifc/rtl/mbox_csr_pkg.sv b/src/soc_ifc/rtl/mbox_csr_pkg.sv
index a44b467db..1c9766e24 100644
--- a/src/soc_ifc/rtl/mbox_csr_pkg.sv
+++ b/src/soc_ifc/rtl/mbox_csr_pkg.sv
@@ -56,12 +56,17 @@ package mbox_csr_pkg;
         logic next;
     } mbox_csr__mbox_status__soc_has_lock__in_t;
 
+    typedef struct packed{
+        logic [14:0] next;
+    } mbox_csr__mbox_status__mbox_rdptr__in_t;
+
     typedef struct packed{
         mbox_csr__mbox_status__status__in_t status;
         mbox_csr__mbox_status__ecc_single_error_next_e066e214_wel_e066e214__in_t ecc_single_error;
         mbox_csr__mbox_status__ecc_double_error_next_e066e214_wel_e066e214__in_t ecc_double_error;
         mbox_csr__mbox_status__mbox_fsm_ps__in_t mbox_fsm_ps;
         mbox_csr__mbox_status__soc_has_lock__in_t soc_has_lock;
+        mbox_csr__mbox_status__mbox_rdptr__in_t mbox_rdptr;
     } mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__in_t;
 
     typedef struct packed{
@@ -130,6 +135,7 @@ package mbox_csr_pkg;
 
     typedef struct packed{
         logic value;
+        logic swmod;
     } mbox_csr__mbox_execute__execute__out_t;
 
     typedef struct packed{
@@ -138,6 +144,7 @@ package mbox_csr_pkg;
 
     typedef struct packed{
         logic [3:0] value;
+        logic swmod;
     } mbox_csr__mbox_status__status__out_t;
 
     typedef struct packed{
@@ -156,12 +163,17 @@ package mbox_csr_pkg;
         logic value;
     } mbox_csr__mbox_status__soc_has_lock__out_t;
 
+    typedef struct packed{
+        logic [14:0] value;
+    } mbox_csr__mbox_status__mbox_rdptr__out_t;
+
     typedef struct packed{
         mbox_csr__mbox_status__status__out_t status;
         mbox_csr__mbox_status__ecc_single_error_next_e066e214_wel_e066e214__out_t ecc_single_error;
         mbox_csr__mbox_status__ecc_double_error_next_e066e214_wel_e066e214__out_t ecc_double_error;
         mbox_csr__mbox_status__mbox_fsm_ps__out_t mbox_fsm_ps;
         mbox_csr__mbox_status__soc_has_lock__out_t soc_has_lock;
+        mbox_csr__mbox_status__mbox_rdptr__out_t mbox_rdptr;
     } mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__out_t;
 
     typedef struct packed{
diff --git a/src/soc_ifc/rtl/mbox_csr_sample.svh b/src/soc_ifc/rtl/mbox_csr_sample.svh
new file mode 100644
index 000000000..29ef7be05
--- /dev/null
+++ b/src/soc_ifc/rtl/mbox_csr_sample.svh
@@ -0,0 +1,251 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+`ifndef MBOX_CSR_SAMPLE
+    `define MBOX_CSR_SAMPLE
+    
+    /*----------------------- MBOX_CSR__MBOX_LOCK SAMPLE FUNCTIONS -----------------------*/
+    function void mbox_csr__mbox_lock::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(lock_bit_cg[bt]) this.lock_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*lock*/   );
+        end
+    endfunction
+
+    function void mbox_csr__mbox_lock::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(lock_bit_cg[bt]) this.lock_bit_cg[bt].sample(lock.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( lock.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- MBOX_CSR__MBOX_USER SAMPLE FUNCTIONS -----------------------*/
+    function void mbox_csr__mbox_user::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(user_bit_cg[bt]) this.user_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*user*/   );
+        end
+    endfunction
+
+    function void mbox_csr__mbox_user::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(user_bit_cg[bt]) this.user_bit_cg[bt].sample(user.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( user.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- MBOX_CSR__MBOX_CMD SAMPLE FUNCTIONS -----------------------*/
+    function void mbox_csr__mbox_cmd::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(command_bit_cg[bt]) this.command_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*command*/   );
+        end
+    endfunction
+
+    function void mbox_csr__mbox_cmd::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(command_bit_cg[bt]) this.command_bit_cg[bt].sample(command.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( command.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- MBOX_CSR__MBOX_DLEN SAMPLE FUNCTIONS -----------------------*/
+    function void mbox_csr__mbox_dlen::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(length_bit_cg[bt]) this.length_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*length*/   );
+        end
+    endfunction
+
+    function void mbox_csr__mbox_dlen::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(length_bit_cg[bt]) this.length_bit_cg[bt].sample(length.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( length.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- MBOX_CSR__MBOX_DATAIN SAMPLE FUNCTIONS -----------------------*/
+    function void mbox_csr__mbox_datain::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(datain_bit_cg[bt]) this.datain_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*datain*/   );
+        end
+    endfunction
+
+    function void mbox_csr__mbox_datain::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(datain_bit_cg[bt]) this.datain_bit_cg[bt].sample(datain.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( datain.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- MBOX_CSR__MBOX_DATAOUT SAMPLE FUNCTIONS -----------------------*/
+    function void mbox_csr__mbox_dataout::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(dataout_bit_cg[bt]) this.dataout_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*dataout*/   );
+        end
+    endfunction
+
+    function void mbox_csr__mbox_dataout::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(dataout_bit_cg[bt]) this.dataout_bit_cg[bt].sample(dataout.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( dataout.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- MBOX_CSR__MBOX_EXECUTE SAMPLE FUNCTIONS -----------------------*/
+    function void mbox_csr__mbox_execute::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(execute_bit_cg[bt]) this.execute_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*execute*/   );
+        end
+    endfunction
+
+    function void mbox_csr__mbox_execute::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(execute_bit_cg[bt]) this.execute_bit_cg[bt].sample(execute.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( execute.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- MBOX_CSR__MBOX_STATUS_ECC_DOUBLE_ERROR_38CEC4B0_ECC_SINGLE_ERROR_9C62B760 SAMPLE FUNCTIONS -----------------------*/
+    function void mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(status_bit_cg[bt]) this.status_bit_cg[bt].sample(data[0 + bt]);
+            foreach(ecc_single_error_bit_cg[bt]) this.ecc_single_error_bit_cg[bt].sample(data[4 + bt]);
+            foreach(ecc_double_error_bit_cg[bt]) this.ecc_double_error_bit_cg[bt].sample(data[5 + bt]);
+            foreach(mbox_fsm_ps_bit_cg[bt]) this.mbox_fsm_ps_bit_cg[bt].sample(data[6 + bt]);
+            foreach(soc_has_lock_bit_cg[bt]) this.soc_has_lock_bit_cg[bt].sample(data[9 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[3:0]/*status*/  ,  data[4:4]/*ecc_single_error*/  ,  data[5:5]/*ecc_double_error*/  ,  data[8:6]/*mbox_fsm_ps*/  ,  data[9:9]/*soc_has_lock*/   );
+        end
+    endfunction
+
+    function void mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(status_bit_cg[bt]) this.status_bit_cg[bt].sample(status.get_mirrored_value() >> bt);
+            foreach(ecc_single_error_bit_cg[bt]) this.ecc_single_error_bit_cg[bt].sample(ecc_single_error.get_mirrored_value() >> bt);
+            foreach(ecc_double_error_bit_cg[bt]) this.ecc_double_error_bit_cg[bt].sample(ecc_double_error.get_mirrored_value() >> bt);
+            foreach(mbox_fsm_ps_bit_cg[bt]) this.mbox_fsm_ps_bit_cg[bt].sample(mbox_fsm_ps.get_mirrored_value() >> bt);
+            foreach(soc_has_lock_bit_cg[bt]) this.soc_has_lock_bit_cg[bt].sample(soc_has_lock.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( status.get_mirrored_value()  ,  ecc_single_error.get_mirrored_value()  ,  ecc_double_error.get_mirrored_value()  ,  mbox_fsm_ps.get_mirrored_value()  ,  soc_has_lock.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- MBOX_CSR__MBOX_UNLOCK SAMPLE FUNCTIONS -----------------------*/
+    function void mbox_csr__mbox_unlock::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(unlock_bit_cg[bt]) this.unlock_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*unlock*/   );
+        end
+    endfunction
+
+    function void mbox_csr__mbox_unlock::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(unlock_bit_cg[bt]) this.unlock_bit_cg[bt].sample(unlock.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( unlock.get_mirrored_value()   );
+        end
+    endfunction
+
+`endif
\ No newline at end of file
diff --git a/src/soc_ifc/rtl/mbox_csr_uvm.sv b/src/soc_ifc/rtl/mbox_csr_uvm.sv
index 97f3e3ae5..760853a1a 100644
--- a/src/soc_ifc/rtl/mbox_csr_uvm.sv
+++ b/src/soc_ifc/rtl/mbox_csr_uvm.sv
@@ -3,116 +3,245 @@
 package mbox_csr_uvm;
     `include "uvm_macros.svh"
     import uvm_pkg::*;
-    
+    `include "mbox_csr_covergroups.svh"
     // Reg - mbox_csr::mbox_lock
     class mbox_csr__mbox_lock extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        mbox_csr__mbox_lock_bit_cg lock_bit_cg[1];
+        mbox_csr__mbox_lock_fld_cg fld_cg;
         rand uvm_reg_field lock;
 
         function new(string name = "mbox_csr__mbox_lock");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.lock = new("lock");
             this.lock.configure(this, 1, 0, "RS", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(lock_bit_cg[bt]) lock_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : mbox_csr__mbox_lock
 
     // Reg - mbox_csr::mbox_user
     class mbox_csr__mbox_user extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        mbox_csr__mbox_user_bit_cg user_bit_cg[32];
+        mbox_csr__mbox_user_fld_cg fld_cg;
         rand uvm_reg_field user;
 
         function new(string name = "mbox_csr__mbox_user");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.user = new("user");
             this.user.configure(this, 32, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(user_bit_cg[bt]) user_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : mbox_csr__mbox_user
 
     // Reg - mbox_csr::mbox_cmd
     class mbox_csr__mbox_cmd extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        mbox_csr__mbox_cmd_bit_cg command_bit_cg[32];
+        mbox_csr__mbox_cmd_fld_cg fld_cg;
         rand uvm_reg_field command;
 
         function new(string name = "mbox_csr__mbox_cmd");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.command = new("command");
             this.command.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(command_bit_cg[bt]) command_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : mbox_csr__mbox_cmd
 
     // Reg - mbox_csr::mbox_dlen
     class mbox_csr__mbox_dlen extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        mbox_csr__mbox_dlen_bit_cg length_bit_cg[32];
+        mbox_csr__mbox_dlen_fld_cg fld_cg;
         rand uvm_reg_field length;
 
         function new(string name = "mbox_csr__mbox_dlen");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.length = new("length");
             this.length.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(length_bit_cg[bt]) length_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : mbox_csr__mbox_dlen
 
     // Reg - mbox_csr::mbox_datain
     class mbox_csr__mbox_datain extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        mbox_csr__mbox_datain_bit_cg datain_bit_cg[32];
+        mbox_csr__mbox_datain_fld_cg fld_cg;
         rand uvm_reg_field datain;
 
         function new(string name = "mbox_csr__mbox_datain");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.datain = new("datain");
             this.datain.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(datain_bit_cg[bt]) datain_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : mbox_csr__mbox_datain
 
     // Reg - mbox_csr::mbox_dataout
     class mbox_csr__mbox_dataout extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        mbox_csr__mbox_dataout_bit_cg dataout_bit_cg[32];
+        mbox_csr__mbox_dataout_fld_cg fld_cg;
         rand uvm_reg_field dataout;
 
         function new(string name = "mbox_csr__mbox_dataout");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.dataout = new("dataout");
             this.dataout.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(dataout_bit_cg[bt]) dataout_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : mbox_csr__mbox_dataout
 
     // Reg - mbox_csr::mbox_execute
     class mbox_csr__mbox_execute extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        mbox_csr__mbox_execute_bit_cg execute_bit_cg[1];
+        mbox_csr__mbox_execute_fld_cg fld_cg;
         rand uvm_reg_field execute;
 
         function new(string name = "mbox_csr__mbox_execute");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.execute = new("execute");
             this.execute.configure(this, 1, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(execute_bit_cg[bt]) execute_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : mbox_csr__mbox_execute
 
     // Reg - mbox_csr::mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760
     class mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760_bit_cg status_bit_cg[4];
+        mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760_bit_cg ecc_single_error_bit_cg[1];
+        mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760_bit_cg ecc_double_error_bit_cg[1];
+        mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760_bit_cg mbox_fsm_ps_bit_cg[3];
+        mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760_bit_cg soc_has_lock_bit_cg[1];
+        mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760_bit_cg mbox_rdptr_bit_cg[15];
+        mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760_fld_cg fld_cg;
         rand uvm_reg_field status;
         rand uvm_reg_field ecc_single_error;
         rand uvm_reg_field ecc_double_error;
         rand uvm_reg_field mbox_fsm_ps;
         rand uvm_reg_field soc_has_lock;
+        rand uvm_reg_field mbox_rdptr;
 
         function new(string name = "mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.status = new("status");
@@ -125,20 +254,48 @@ package mbox_csr_uvm;
             this.mbox_fsm_ps.configure(this, 3, 6, "RO", 1, 'h0, 1, 1, 0);
             this.soc_has_lock = new("soc_has_lock");
             this.soc_has_lock.configure(this, 1, 9, "RO", 1, 'h0, 1, 1, 0);
+            this.mbox_rdptr = new("mbox_rdptr");
+            this.mbox_rdptr.configure(this, 15, 10, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(status_bit_cg[bt]) status_bit_cg[bt] = new();
+                foreach(ecc_single_error_bit_cg[bt]) ecc_single_error_bit_cg[bt] = new();
+                foreach(ecc_double_error_bit_cg[bt]) ecc_double_error_bit_cg[bt] = new();
+                foreach(mbox_fsm_ps_bit_cg[bt]) mbox_fsm_ps_bit_cg[bt] = new();
+                foreach(soc_has_lock_bit_cg[bt]) soc_has_lock_bit_cg[bt] = new();
+                foreach(mbox_rdptr_bit_cg[bt]) mbox_rdptr_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760
 
     // Reg - mbox_csr::mbox_unlock
     class mbox_csr__mbox_unlock extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        mbox_csr__mbox_unlock_bit_cg unlock_bit_cg[1];
+        mbox_csr__mbox_unlock_fld_cg fld_cg;
         rand uvm_reg_field unlock;
 
         function new(string name = "mbox_csr__mbox_unlock");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.unlock = new("unlock");
             this.unlock.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(unlock_bit_cg[bt]) unlock_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : mbox_csr__mbox_unlock
 
@@ -208,4 +365,5 @@ package mbox_csr_uvm;
         endfunction : build
     endclass : mbox_csr
 
+    `include "mbox_csr_sample.svh"
 endpackage: mbox_csr_uvm
diff --git a/src/soc_ifc/rtl/sha512_acc_csr.sv b/src/soc_ifc/rtl/sha512_acc_csr.sv
index c5b3c22fa..1188e3192 100644
--- a/src/soc_ifc/rtl/sha512_acc_csr.sv
+++ b/src/soc_ifc/rtl/sha512_acc_csr.sv
@@ -201,6 +201,10 @@ module sha512_acc_csr (
                 logic next;
                 logic load_next;
             } VALID;
+            struct packed{
+                logic next;
+                logic load_next;
+            } SOC_HAS_LOCK;
         } STATUS;
         struct packed{
             struct packed{
@@ -436,6 +440,9 @@ module sha512_acc_csr (
             struct packed{
                 logic value;
             } VALID;
+            struct packed{
+                logic value;
+            } SOC_HAS_LOCK;
         } STATUS;
         struct packed{
             struct packed{
@@ -593,7 +600,7 @@ module sha512_acc_csr (
     end
     always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
         if(~hwif_in.cptra_rst_b) begin
-            field_storage.LOCK.LOCK.value <= 'h0;
+            field_storage.LOCK.LOCK.value <= 'h1;
         end else if(field_combo.LOCK.LOCK.load_next) begin
             field_storage.LOCK.LOCK.value <= field_combo.LOCK.LOCK.next;
         end
@@ -719,7 +726,7 @@ module sha512_acc_csr (
     always_comb begin
         automatic logic [0:0] next_c = field_storage.EXECUTE.EXECUTE.value;
         automatic logic load_next_c = '0;
-        if(decoded_reg_strb.EXECUTE && decoded_req_is_wr) begin // SW write
+        if(decoded_reg_strb.EXECUTE && decoded_req_is_wr && hwif_in.valid_user) begin // SW write
             next_c = (field_storage.EXECUTE.EXECUTE.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
             load_next_c = '1;
         end else if(hwif_in.EXECUTE.EXECUTE.hwclr) begin // HW Clear
@@ -756,6 +763,25 @@ module sha512_acc_csr (
         end
     end
     assign hwif_out.STATUS.VALID.value = field_storage.STATUS.VALID.value;
+    // Field: sha512_acc_csr.STATUS.SOC_HAS_LOCK
+    always_comb begin
+        automatic logic [0:0] next_c = field_storage.STATUS.SOC_HAS_LOCK.value;
+        automatic logic load_next_c = '0;
+        if(1) begin // HW Write
+            next_c = hwif_in.STATUS.SOC_HAS_LOCK.next;
+            load_next_c = '1;
+        end
+        field_combo.STATUS.SOC_HAS_LOCK.next = next_c;
+        field_combo.STATUS.SOC_HAS_LOCK.load_next = load_next_c;
+    end
+    always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+        if(~hwif_in.cptra_rst_b) begin
+            field_storage.STATUS.SOC_HAS_LOCK.value <= 'h0;
+        end else if(field_combo.STATUS.SOC_HAS_LOCK.load_next) begin
+            field_storage.STATUS.SOC_HAS_LOCK.value <= field_combo.STATUS.SOC_HAS_LOCK.next;
+        end
+    end
+    assign hwif_out.STATUS.SOC_HAS_LOCK.value = field_storage.STATUS.SOC_HAS_LOCK.value;
     for(genvar i0=0; i0<16; i0++) begin
         // Field: sha512_acc_csr.DIGEST[].DIGEST
         always_comb begin
@@ -1525,7 +1551,8 @@ module sha512_acc_csr (
     assign readback_array[6][0:0] = (decoded_reg_strb.EXECUTE && !decoded_req_is_wr) ? field_storage.EXECUTE.EXECUTE.value : '0;
     assign readback_array[6][31:1] = '0;
     assign readback_array[7][0:0] = (decoded_reg_strb.STATUS && !decoded_req_is_wr) ? field_storage.STATUS.VALID.value : '0;
-    assign readback_array[7][31:1] = '0;
+    assign readback_array[7][1:1] = (decoded_reg_strb.STATUS && !decoded_req_is_wr) ? field_storage.STATUS.SOC_HAS_LOCK.value : '0;
+    assign readback_array[7][31:2] = '0;
     for(genvar i0=0; i0<16; i0++) begin
         assign readback_array[i0*1 + 8][31:0] = (decoded_reg_strb.DIGEST[i0] && !decoded_req_is_wr) ? field_storage.DIGEST[i0].DIGEST.value : '0;
     end
diff --git a/src/soc_ifc/rtl/sha512_acc_csr_covergroups.svh b/src/soc_ifc/rtl/sha512_acc_csr_covergroups.svh
new file mode 100644
index 000000000..68cab6060
--- /dev/null
+++ b/src/soc_ifc/rtl/sha512_acc_csr_covergroups.svh
@@ -0,0 +1,640 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+`ifndef SHA512_ACC_CSR_COVERGROUPS
+    `define SHA512_ACC_CSR_COVERGROUPS
+    
+    /*----------------------- SHA512_ACC_CSR__LOCK COVERGROUPS -----------------------*/
+    covergroup sha512_acc_csr__LOCK_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup sha512_acc_csr__LOCK_fld_cg with function sample(
+    input bit [1-1:0] LOCK
+    );
+        option.per_instance = 1;
+        LOCK_cp : coverpoint LOCK;
+
+    endgroup
+
+    /*----------------------- SHA512_ACC_CSR__USER COVERGROUPS -----------------------*/
+    covergroup sha512_acc_csr__USER_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup sha512_acc_csr__USER_fld_cg with function sample(
+    input bit [32-1:0] USER
+    );
+        option.per_instance = 1;
+        USER_cp : coverpoint USER;
+
+    endgroup
+
+    /*----------------------- SHA512_ACC_CSR__MODE COVERGROUPS -----------------------*/
+    covergroup sha512_acc_csr__MODE_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup sha512_acc_csr__MODE_fld_cg with function sample(
+    input bit [2-1:0] MODE,
+    input bit [1-1:0] ENDIAN_TOGGLE
+    );
+        option.per_instance = 1;
+        MODE_cp : coverpoint MODE;
+        ENDIAN_TOGGLE_cp : coverpoint ENDIAN_TOGGLE;
+
+    endgroup
+
+    /*----------------------- SHA512_ACC_CSR__START_ADDRESS COVERGROUPS -----------------------*/
+    covergroup sha512_acc_csr__START_ADDRESS_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup sha512_acc_csr__START_ADDRESS_fld_cg with function sample(
+    input bit [32-1:0] ADDR
+    );
+        option.per_instance = 1;
+        ADDR_cp : coverpoint ADDR {
+            bins zero_val = {32'h0};
+            bins legal_val = {[1:32'h7FFF]};
+            bins illegal_val = {[32'h8000:32'hFFFF_FFFE]};
+            bins ones_val = {{32{1'b1}}};
+            wildcard bins set = (0 => 32'h????_????);
+            wildcard bins clr = (32'h????_???? => 0);
+        }
+
+    endgroup
+
+    /*----------------------- SHA512_ACC_CSR__DLEN COVERGROUPS -----------------------*/
+    covergroup sha512_acc_csr__DLEN_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup sha512_acc_csr__DLEN_fld_cg with function sample(
+    input bit [32-1:0] LENGTH
+    );
+        option.per_instance = 1;
+        LENGTH_cp : coverpoint LENGTH {
+            bins zero_val = {32'h0};
+            bins legal_byte_aligned_val  = {[1:32'h8000]};
+            bins legal_word_aligned_val  = {[1:32'h8000]} with (~|item[0]);
+            bins legal_dword_aligned_val = {[1:32'h8000]} with (~|item[1:0]);
+            bins legal_qword_aligned_val = {[1:32'h8000]} with (~|item[2:0]);
+            bins legal_oword_aligned_val = {[1:32'h8000]} with (~|item[3:0]);
+            bins illegal_val = {[32'h8001:32'hFFFF_FFFE]};
+            bins ones_val = {{32{1'b1}}};
+            wildcard bins set = (0 => 32'h????_????);
+            wildcard bins clr = (32'h????_???? => 0);
+        }
+
+    endgroup
+
+    /*----------------------- SHA512_ACC_CSR__DATAIN COVERGROUPS -----------------------*/
+    covergroup sha512_acc_csr__DATAIN_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup sha512_acc_csr__DATAIN_fld_cg with function sample(
+    input bit [32-1:0] DATAIN
+    );
+        option.per_instance = 1;
+        DATAIN_cp : coverpoint DATAIN;
+
+    endgroup
+
+    /*----------------------- SHA512_ACC_CSR__EXECUTE COVERGROUPS -----------------------*/
+    covergroup sha512_acc_csr__EXECUTE_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup sha512_acc_csr__EXECUTE_fld_cg with function sample(
+    input bit [1-1:0] EXECUTE
+    );
+        option.per_instance = 1;
+        EXECUTE_cp : coverpoint EXECUTE;
+
+    endgroup
+
+    /*----------------------- SHA512_ACC_CSR__STATUS COVERGROUPS -----------------------*/
+    covergroup sha512_acc_csr__STATUS_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup sha512_acc_csr__STATUS_fld_cg with function sample(
+    input bit [1-1:0] VALID,
+    input bit [1-1:0] SOC_HAS_LOCK
+    );
+        option.per_instance = 1;
+        VALID_cp : coverpoint VALID;
+        SOC_HAS_LOCK_cp : coverpoint SOC_HAS_LOCK;
+
+    endgroup
+
+    /*----------------------- SHA512_ACC_CSR__DIGEST COVERGROUPS -----------------------*/
+    covergroup sha512_acc_csr__DIGEST_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup sha512_acc_csr__DIGEST_fld_cg with function sample(
+    input bit [32-1:0] DIGEST
+    );
+        option.per_instance = 1;
+        DIGEST_cp : coverpoint DIGEST;
+
+    endgroup
+
+    /*----------------------- SHA512_ACC_CSR__CONTROL COVERGROUPS -----------------------*/
+    covergroup sha512_acc_csr__CONTROL_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup sha512_acc_csr__CONTROL_fld_cg with function sample(
+    input bit [1-1:0] ZEROIZE
+    );
+        option.per_instance = 1;
+        ZEROIZE_cp : coverpoint ZEROIZE;
+
+    endgroup
+
+    /*----------------------- SHA512_ACC_CSR__GLOBAL_INTR_EN_T COVERGROUPS -----------------------*/
+    covergroup sha512_acc_csr__global_intr_en_t_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup sha512_acc_csr__global_intr_en_t_fld_cg with function sample(
+    input bit [1-1:0] error_en,
+    input bit [1-1:0] notif_en
+    );
+        option.per_instance = 1;
+        error_en_cp : coverpoint error_en;
+        notif_en_cp : coverpoint notif_en;
+
+    endgroup
+
+    /*----------------------- SHA512_ACC_CSR__ERROR_INTR_EN_T COVERGROUPS -----------------------*/
+    covergroup sha512_acc_csr__error_intr_en_t_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup sha512_acc_csr__error_intr_en_t_fld_cg with function sample(
+    input bit [1-1:0] error0_en,
+    input bit [1-1:0] error1_en,
+    input bit [1-1:0] error2_en,
+    input bit [1-1:0] error3_en
+    );
+        option.per_instance = 1;
+        error0_en_cp : coverpoint error0_en;
+        error1_en_cp : coverpoint error1_en;
+        error2_en_cp : coverpoint error2_en;
+        error3_en_cp : coverpoint error3_en;
+
+    endgroup
+
+    /*----------------------- SHA512_ACC_CSR__NOTIF_INTR_EN_T COVERGROUPS -----------------------*/
+    covergroup sha512_acc_csr__notif_intr_en_t_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup sha512_acc_csr__notif_intr_en_t_fld_cg with function sample(
+    input bit [1-1:0] notif_cmd_done_en
+    );
+        option.per_instance = 1;
+        notif_cmd_done_en_cp : coverpoint notif_cmd_done_en;
+
+    endgroup
+
+    /*----------------------- SHA512_ACC_CSR__GLOBAL_INTR_T_AGG_STS_DD3DCF0A COVERGROUPS -----------------------*/
+    covergroup sha512_acc_csr__global_intr_t_agg_sts_dd3dcf0a_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup sha512_acc_csr__global_intr_t_agg_sts_dd3dcf0a_fld_cg with function sample(
+    input bit [1-1:0] agg_sts
+    );
+        option.per_instance = 1;
+        agg_sts_cp : coverpoint agg_sts;
+
+    endgroup
+
+    /*----------------------- SHA512_ACC_CSR__GLOBAL_INTR_T_AGG_STS_E6399B4A COVERGROUPS -----------------------*/
+    covergroup sha512_acc_csr__global_intr_t_agg_sts_e6399b4a_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup sha512_acc_csr__global_intr_t_agg_sts_e6399b4a_fld_cg with function sample(
+    input bit [1-1:0] agg_sts
+    );
+        option.per_instance = 1;
+        agg_sts_cp : coverpoint agg_sts;
+
+    endgroup
+
+    /*----------------------- SHA512_ACC_CSR__ERROR_INTR_T_ERROR0_STS_5EE134BF_ERROR1_STS_AAD9583F_ERROR2_STS_6CAD4575_ERROR3_STS_735BBEBA COVERGROUPS -----------------------*/
+    covergroup sha512_acc_csr__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup sha512_acc_csr__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba_fld_cg with function sample(
+    input bit [1-1:0] error0_sts,
+    input bit [1-1:0] error1_sts,
+    input bit [1-1:0] error2_sts,
+    input bit [1-1:0] error3_sts
+    );
+        option.per_instance = 1;
+        error0_sts_cp : coverpoint error0_sts;
+        error1_sts_cp : coverpoint error1_sts;
+        error2_sts_cp : coverpoint error2_sts;
+        error3_sts_cp : coverpoint error3_sts;
+
+    endgroup
+
+    /*----------------------- SHA512_ACC_CSR__NOTIF_INTR_T_NOTIF_CMD_DONE_STS_1C68637E COVERGROUPS -----------------------*/
+    covergroup sha512_acc_csr__notif_intr_t_notif_cmd_done_sts_1c68637e_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup sha512_acc_csr__notif_intr_t_notif_cmd_done_sts_1c68637e_fld_cg with function sample(
+    input bit [1-1:0] notif_cmd_done_sts
+    );
+        option.per_instance = 1;
+        notif_cmd_done_sts_cp : coverpoint notif_cmd_done_sts;
+
+    endgroup
+
+    /*----------------------- SHA512_ACC_CSR__ERROR_INTR_TRIG_T COVERGROUPS -----------------------*/
+    covergroup sha512_acc_csr__error_intr_trig_t_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup sha512_acc_csr__error_intr_trig_t_fld_cg with function sample(
+    input bit [1-1:0] error0_trig,
+    input bit [1-1:0] error1_trig,
+    input bit [1-1:0] error2_trig,
+    input bit [1-1:0] error3_trig
+    );
+        option.per_instance = 1;
+        error0_trig_cp : coverpoint error0_trig;
+        error1_trig_cp : coverpoint error1_trig;
+        error2_trig_cp : coverpoint error2_trig;
+        error3_trig_cp : coverpoint error3_trig;
+
+    endgroup
+
+    /*----------------------- SHA512_ACC_CSR__NOTIF_INTR_TRIG_T COVERGROUPS -----------------------*/
+    covergroup sha512_acc_csr__notif_intr_trig_t_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup sha512_acc_csr__notif_intr_trig_t_fld_cg with function sample(
+    input bit [1-1:0] notif_cmd_done_trig
+    );
+        option.per_instance = 1;
+        notif_cmd_done_trig_cp : coverpoint notif_cmd_done_trig;
+
+    endgroup
+
+    /*----------------------- SHA512_ACC_CSR__INTR_COUNT_T_CNT_130AB269 COVERGROUPS -----------------------*/
+    covergroup sha512_acc_csr__intr_count_t_cnt_130ab269_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup sha512_acc_csr__intr_count_t_cnt_130ab269_fld_cg with function sample(
+    input bit [32-1:0] cnt
+    );
+        option.per_instance = 1;
+        cnt_cp : coverpoint cnt;
+
+    endgroup
+
+    /*----------------------- SHA512_ACC_CSR__INTR_COUNT_T_CNT_324DFC53 COVERGROUPS -----------------------*/
+    covergroup sha512_acc_csr__intr_count_t_cnt_324dfc53_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup sha512_acc_csr__intr_count_t_cnt_324dfc53_fld_cg with function sample(
+    input bit [32-1:0] cnt
+    );
+        option.per_instance = 1;
+        cnt_cp : coverpoint cnt;
+
+    endgroup
+
+    /*----------------------- SHA512_ACC_CSR__INTR_COUNT_T_CNT_791A4799 COVERGROUPS -----------------------*/
+    covergroup sha512_acc_csr__intr_count_t_cnt_791a4799_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup sha512_acc_csr__intr_count_t_cnt_791a4799_fld_cg with function sample(
+    input bit [32-1:0] cnt
+    );
+        option.per_instance = 1;
+        cnt_cp : coverpoint cnt;
+
+    endgroup
+
+    /*----------------------- SHA512_ACC_CSR__INTR_COUNT_T_CNT_E9DE7334 COVERGROUPS -----------------------*/
+    covergroup sha512_acc_csr__intr_count_t_cnt_e9de7334_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup sha512_acc_csr__intr_count_t_cnt_e9de7334_fld_cg with function sample(
+    input bit [32-1:0] cnt
+    );
+        option.per_instance = 1;
+        cnt_cp : coverpoint cnt;
+
+    endgroup
+
+    /*----------------------- SHA512_ACC_CSR__INTR_COUNT_T_CNT_BE67D6D5 COVERGROUPS -----------------------*/
+    covergroup sha512_acc_csr__intr_count_t_cnt_be67d6d5_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup sha512_acc_csr__intr_count_t_cnt_be67d6d5_fld_cg with function sample(
+    input bit [32-1:0] cnt
+    );
+        option.per_instance = 1;
+        cnt_cp : coverpoint cnt;
+
+    endgroup
+
+    /*----------------------- SHA512_ACC_CSR__INTR_COUNT_INCR_T_PULSE_37026C97 COVERGROUPS -----------------------*/
+    covergroup sha512_acc_csr__intr_count_incr_t_pulse_37026c97_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup sha512_acc_csr__intr_count_incr_t_pulse_37026c97_fld_cg with function sample(
+    input bit [1-1:0] pulse
+    );
+        option.per_instance = 1;
+        pulse_cp : coverpoint pulse;
+
+    endgroup
+
+    /*----------------------- SHA512_ACC_CSR__INTR_COUNT_INCR_T_PULSE_D860D977 COVERGROUPS -----------------------*/
+    covergroup sha512_acc_csr__intr_count_incr_t_pulse_d860d977_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup sha512_acc_csr__intr_count_incr_t_pulse_d860d977_fld_cg with function sample(
+    input bit [1-1:0] pulse
+    );
+        option.per_instance = 1;
+        pulse_cp : coverpoint pulse;
+
+    endgroup
+
+    /*----------------------- SHA512_ACC_CSR__INTR_COUNT_INCR_T_PULSE_87B45FE7 COVERGROUPS -----------------------*/
+    covergroup sha512_acc_csr__intr_count_incr_t_pulse_87b45fe7_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup sha512_acc_csr__intr_count_incr_t_pulse_87b45fe7_fld_cg with function sample(
+    input bit [1-1:0] pulse
+    );
+        option.per_instance = 1;
+        pulse_cp : coverpoint pulse;
+
+    endgroup
+
+    /*----------------------- SHA512_ACC_CSR__INTR_COUNT_INCR_T_PULSE_C1689EE6 COVERGROUPS -----------------------*/
+    covergroup sha512_acc_csr__intr_count_incr_t_pulse_c1689ee6_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup sha512_acc_csr__intr_count_incr_t_pulse_c1689ee6_fld_cg with function sample(
+    input bit [1-1:0] pulse
+    );
+        option.per_instance = 1;
+        pulse_cp : coverpoint pulse;
+
+    endgroup
+
+    /*----------------------- SHA512_ACC_CSR__INTR_COUNT_INCR_T_PULSE_6173128E COVERGROUPS -----------------------*/
+    covergroup sha512_acc_csr__intr_count_incr_t_pulse_6173128e_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup sha512_acc_csr__intr_count_incr_t_pulse_6173128e_fld_cg with function sample(
+    input bit [1-1:0] pulse
+    );
+        option.per_instance = 1;
+        pulse_cp : coverpoint pulse;
+
+    endgroup
+
+`endif
diff --git a/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv b/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv
index fd30268ab..6cb6af010 100644
--- a/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv
+++ b/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv
@@ -22,8 +22,13 @@ package sha512_acc_csr_pkg;
         logic next;
     } sha512_acc_csr__STATUS__VALID__in_t;
 
+    typedef struct packed{
+        logic next;
+    } sha512_acc_csr__STATUS__SOC_HAS_LOCK__in_t;
+
     typedef struct packed{
         sha512_acc_csr__STATUS__VALID__in_t VALID;
+        sha512_acc_csr__STATUS__SOC_HAS_LOCK__in_t SOC_HAS_LOCK;
     } sha512_acc_csr__STATUS__in_t;
 
     typedef struct packed{
@@ -151,8 +156,13 @@ package sha512_acc_csr_pkg;
         logic value;
     } sha512_acc_csr__STATUS__VALID__out_t;
 
+    typedef struct packed{
+        logic value;
+    } sha512_acc_csr__STATUS__SOC_HAS_LOCK__out_t;
+
     typedef struct packed{
         sha512_acc_csr__STATUS__VALID__out_t VALID;
+        sha512_acc_csr__STATUS__SOC_HAS_LOCK__out_t SOC_HAS_LOCK;
     } sha512_acc_csr__STATUS__out_t;
 
     typedef struct packed{
diff --git a/src/soc_ifc/rtl/sha512_acc_csr_sample.svh b/src/soc_ifc/rtl/sha512_acc_csr_sample.svh
new file mode 100644
index 000000000..cb752d1e8
--- /dev/null
+++ b/src/soc_ifc/rtl/sha512_acc_csr_sample.svh
@@ -0,0 +1,767 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+`ifndef SHA512_ACC_CSR_SAMPLE
+    `define SHA512_ACC_CSR_SAMPLE
+    
+    /*----------------------- SHA512_ACC_CSR__LOCK SAMPLE FUNCTIONS -----------------------*/
+    function void sha512_acc_csr__LOCK::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(LOCK_bit_cg[bt]) this.LOCK_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*LOCK*/   );
+        end
+    endfunction
+
+    function void sha512_acc_csr__LOCK::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(LOCK_bit_cg[bt]) this.LOCK_bit_cg[bt].sample(LOCK.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( LOCK.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SHA512_ACC_CSR__USER SAMPLE FUNCTIONS -----------------------*/
+    function void sha512_acc_csr__USER::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(USER_bit_cg[bt]) this.USER_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*USER*/   );
+        end
+    endfunction
+
+    function void sha512_acc_csr__USER::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(USER_bit_cg[bt]) this.USER_bit_cg[bt].sample(USER.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( USER.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SHA512_ACC_CSR__MODE SAMPLE FUNCTIONS -----------------------*/
+    function void sha512_acc_csr__MODE::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(MODE_bit_cg[bt]) this.MODE_bit_cg[bt].sample(data[0 + bt]);
+            foreach(ENDIAN_TOGGLE_bit_cg[bt]) this.ENDIAN_TOGGLE_bit_cg[bt].sample(data[2 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[1:0]/*MODE*/  ,  data[2:2]/*ENDIAN_TOGGLE*/   );
+        end
+    endfunction
+
+    function void sha512_acc_csr__MODE::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(MODE_bit_cg[bt]) this.MODE_bit_cg[bt].sample(MODE.get_mirrored_value() >> bt);
+            foreach(ENDIAN_TOGGLE_bit_cg[bt]) this.ENDIAN_TOGGLE_bit_cg[bt].sample(ENDIAN_TOGGLE.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( MODE.get_mirrored_value()  ,  ENDIAN_TOGGLE.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SHA512_ACC_CSR__START_ADDRESS SAMPLE FUNCTIONS -----------------------*/
+    function void sha512_acc_csr__START_ADDRESS::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(ADDR_bit_cg[bt]) this.ADDR_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*ADDR*/   );
+        end
+    endfunction
+
+    function void sha512_acc_csr__START_ADDRESS::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(ADDR_bit_cg[bt]) this.ADDR_bit_cg[bt].sample(ADDR.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( ADDR.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SHA512_ACC_CSR__DLEN SAMPLE FUNCTIONS -----------------------*/
+    function void sha512_acc_csr__DLEN::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(LENGTH_bit_cg[bt]) this.LENGTH_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*LENGTH*/   );
+        end
+    endfunction
+
+    function void sha512_acc_csr__DLEN::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(LENGTH_bit_cg[bt]) this.LENGTH_bit_cg[bt].sample(LENGTH.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( LENGTH.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SHA512_ACC_CSR__DATAIN SAMPLE FUNCTIONS -----------------------*/
+    function void sha512_acc_csr__DATAIN::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(DATAIN_bit_cg[bt]) this.DATAIN_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*DATAIN*/   );
+        end
+    endfunction
+
+    function void sha512_acc_csr__DATAIN::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(DATAIN_bit_cg[bt]) this.DATAIN_bit_cg[bt].sample(DATAIN.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( DATAIN.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SHA512_ACC_CSR__EXECUTE SAMPLE FUNCTIONS -----------------------*/
+    function void sha512_acc_csr__EXECUTE::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(EXECUTE_bit_cg[bt]) this.EXECUTE_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*EXECUTE*/   );
+        end
+    endfunction
+
+    function void sha512_acc_csr__EXECUTE::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(EXECUTE_bit_cg[bt]) this.EXECUTE_bit_cg[bt].sample(EXECUTE.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( EXECUTE.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SHA512_ACC_CSR__STATUS SAMPLE FUNCTIONS -----------------------*/
+    function void sha512_acc_csr__STATUS::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(VALID_bit_cg[bt]) this.VALID_bit_cg[bt].sample(data[0 + bt]);
+            foreach(SOC_HAS_LOCK_bit_cg[bt]) this.SOC_HAS_LOCK_bit_cg[bt].sample(data[1 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*VALID*/  ,  data[1:1]/*SOC_HAS_LOCK*/   );
+        end
+    endfunction
+
+    function void sha512_acc_csr__STATUS::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(VALID_bit_cg[bt]) this.VALID_bit_cg[bt].sample(VALID.get_mirrored_value() >> bt);
+            foreach(SOC_HAS_LOCK_bit_cg[bt]) this.SOC_HAS_LOCK_bit_cg[bt].sample(SOC_HAS_LOCK.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( VALID.get_mirrored_value()  ,  SOC_HAS_LOCK.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SHA512_ACC_CSR__DIGEST SAMPLE FUNCTIONS -----------------------*/
+    function void sha512_acc_csr__DIGEST::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(DIGEST_bit_cg[bt]) this.DIGEST_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*DIGEST*/   );
+        end
+    endfunction
+
+    function void sha512_acc_csr__DIGEST::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(DIGEST_bit_cg[bt]) this.DIGEST_bit_cg[bt].sample(DIGEST.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( DIGEST.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SHA512_ACC_CSR__CONTROL SAMPLE FUNCTIONS -----------------------*/
+    function void sha512_acc_csr__CONTROL::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(ZEROIZE_bit_cg[bt]) this.ZEROIZE_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*ZEROIZE*/   );
+        end
+    endfunction
+
+    function void sha512_acc_csr__CONTROL::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(ZEROIZE_bit_cg[bt]) this.ZEROIZE_bit_cg[bt].sample(ZEROIZE.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( ZEROIZE.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SHA512_ACC_CSR__GLOBAL_INTR_EN_T SAMPLE FUNCTIONS -----------------------*/
+    function void sha512_acc_csr__global_intr_en_t::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(error_en_bit_cg[bt]) this.error_en_bit_cg[bt].sample(data[0 + bt]);
+            foreach(notif_en_bit_cg[bt]) this.notif_en_bit_cg[bt].sample(data[1 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*error_en*/  ,  data[1:1]/*notif_en*/   );
+        end
+    endfunction
+
+    function void sha512_acc_csr__global_intr_en_t::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(error_en_bit_cg[bt]) this.error_en_bit_cg[bt].sample(error_en.get_mirrored_value() >> bt);
+            foreach(notif_en_bit_cg[bt]) this.notif_en_bit_cg[bt].sample(notif_en.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( error_en.get_mirrored_value()  ,  notif_en.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SHA512_ACC_CSR__ERROR_INTR_EN_T SAMPLE FUNCTIONS -----------------------*/
+    function void sha512_acc_csr__error_intr_en_t::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(error0_en_bit_cg[bt]) this.error0_en_bit_cg[bt].sample(data[0 + bt]);
+            foreach(error1_en_bit_cg[bt]) this.error1_en_bit_cg[bt].sample(data[1 + bt]);
+            foreach(error2_en_bit_cg[bt]) this.error2_en_bit_cg[bt].sample(data[2 + bt]);
+            foreach(error3_en_bit_cg[bt]) this.error3_en_bit_cg[bt].sample(data[3 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*error0_en*/  ,  data[1:1]/*error1_en*/  ,  data[2:2]/*error2_en*/  ,  data[3:3]/*error3_en*/   );
+        end
+    endfunction
+
+    function void sha512_acc_csr__error_intr_en_t::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(error0_en_bit_cg[bt]) this.error0_en_bit_cg[bt].sample(error0_en.get_mirrored_value() >> bt);
+            foreach(error1_en_bit_cg[bt]) this.error1_en_bit_cg[bt].sample(error1_en.get_mirrored_value() >> bt);
+            foreach(error2_en_bit_cg[bt]) this.error2_en_bit_cg[bt].sample(error2_en.get_mirrored_value() >> bt);
+            foreach(error3_en_bit_cg[bt]) this.error3_en_bit_cg[bt].sample(error3_en.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( error0_en.get_mirrored_value()  ,  error1_en.get_mirrored_value()  ,  error2_en.get_mirrored_value()  ,  error3_en.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SHA512_ACC_CSR__NOTIF_INTR_EN_T SAMPLE FUNCTIONS -----------------------*/
+    function void sha512_acc_csr__notif_intr_en_t::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(notif_cmd_done_en_bit_cg[bt]) this.notif_cmd_done_en_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*notif_cmd_done_en*/   );
+        end
+    endfunction
+
+    function void sha512_acc_csr__notif_intr_en_t::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(notif_cmd_done_en_bit_cg[bt]) this.notif_cmd_done_en_bit_cg[bt].sample(notif_cmd_done_en.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( notif_cmd_done_en.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SHA512_ACC_CSR__GLOBAL_INTR_T_AGG_STS_DD3DCF0A SAMPLE FUNCTIONS -----------------------*/
+    function void sha512_acc_csr__global_intr_t_agg_sts_dd3dcf0a::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(agg_sts_bit_cg[bt]) this.agg_sts_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*agg_sts*/   );
+        end
+    endfunction
+
+    function void sha512_acc_csr__global_intr_t_agg_sts_dd3dcf0a::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(agg_sts_bit_cg[bt]) this.agg_sts_bit_cg[bt].sample(agg_sts.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( agg_sts.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SHA512_ACC_CSR__GLOBAL_INTR_T_AGG_STS_E6399B4A SAMPLE FUNCTIONS -----------------------*/
+    function void sha512_acc_csr__global_intr_t_agg_sts_e6399b4a::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(agg_sts_bit_cg[bt]) this.agg_sts_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*agg_sts*/   );
+        end
+    endfunction
+
+    function void sha512_acc_csr__global_intr_t_agg_sts_e6399b4a::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(agg_sts_bit_cg[bt]) this.agg_sts_bit_cg[bt].sample(agg_sts.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( agg_sts.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SHA512_ACC_CSR__ERROR_INTR_T_ERROR0_STS_5EE134BF_ERROR1_STS_AAD9583F_ERROR2_STS_6CAD4575_ERROR3_STS_735BBEBA SAMPLE FUNCTIONS -----------------------*/
+    function void sha512_acc_csr__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(error0_sts_bit_cg[bt]) this.error0_sts_bit_cg[bt].sample(data[0 + bt]);
+            foreach(error1_sts_bit_cg[bt]) this.error1_sts_bit_cg[bt].sample(data[1 + bt]);
+            foreach(error2_sts_bit_cg[bt]) this.error2_sts_bit_cg[bt].sample(data[2 + bt]);
+            foreach(error3_sts_bit_cg[bt]) this.error3_sts_bit_cg[bt].sample(data[3 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*error0_sts*/  ,  data[1:1]/*error1_sts*/  ,  data[2:2]/*error2_sts*/  ,  data[3:3]/*error3_sts*/   );
+        end
+    endfunction
+
+    function void sha512_acc_csr__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(error0_sts_bit_cg[bt]) this.error0_sts_bit_cg[bt].sample(error0_sts.get_mirrored_value() >> bt);
+            foreach(error1_sts_bit_cg[bt]) this.error1_sts_bit_cg[bt].sample(error1_sts.get_mirrored_value() >> bt);
+            foreach(error2_sts_bit_cg[bt]) this.error2_sts_bit_cg[bt].sample(error2_sts.get_mirrored_value() >> bt);
+            foreach(error3_sts_bit_cg[bt]) this.error3_sts_bit_cg[bt].sample(error3_sts.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( error0_sts.get_mirrored_value()  ,  error1_sts.get_mirrored_value()  ,  error2_sts.get_mirrored_value()  ,  error3_sts.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SHA512_ACC_CSR__NOTIF_INTR_T_NOTIF_CMD_DONE_STS_1C68637E SAMPLE FUNCTIONS -----------------------*/
+    function void sha512_acc_csr__notif_intr_t_notif_cmd_done_sts_1c68637e::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(notif_cmd_done_sts_bit_cg[bt]) this.notif_cmd_done_sts_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*notif_cmd_done_sts*/   );
+        end
+    endfunction
+
+    function void sha512_acc_csr__notif_intr_t_notif_cmd_done_sts_1c68637e::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(notif_cmd_done_sts_bit_cg[bt]) this.notif_cmd_done_sts_bit_cg[bt].sample(notif_cmd_done_sts.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( notif_cmd_done_sts.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SHA512_ACC_CSR__ERROR_INTR_TRIG_T SAMPLE FUNCTIONS -----------------------*/
+    function void sha512_acc_csr__error_intr_trig_t::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(error0_trig_bit_cg[bt]) this.error0_trig_bit_cg[bt].sample(data[0 + bt]);
+            foreach(error1_trig_bit_cg[bt]) this.error1_trig_bit_cg[bt].sample(data[1 + bt]);
+            foreach(error2_trig_bit_cg[bt]) this.error2_trig_bit_cg[bt].sample(data[2 + bt]);
+            foreach(error3_trig_bit_cg[bt]) this.error3_trig_bit_cg[bt].sample(data[3 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*error0_trig*/  ,  data[1:1]/*error1_trig*/  ,  data[2:2]/*error2_trig*/  ,  data[3:3]/*error3_trig*/   );
+        end
+    endfunction
+
+    function void sha512_acc_csr__error_intr_trig_t::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(error0_trig_bit_cg[bt]) this.error0_trig_bit_cg[bt].sample(error0_trig.get_mirrored_value() >> bt);
+            foreach(error1_trig_bit_cg[bt]) this.error1_trig_bit_cg[bt].sample(error1_trig.get_mirrored_value() >> bt);
+            foreach(error2_trig_bit_cg[bt]) this.error2_trig_bit_cg[bt].sample(error2_trig.get_mirrored_value() >> bt);
+            foreach(error3_trig_bit_cg[bt]) this.error3_trig_bit_cg[bt].sample(error3_trig.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( error0_trig.get_mirrored_value()  ,  error1_trig.get_mirrored_value()  ,  error2_trig.get_mirrored_value()  ,  error3_trig.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SHA512_ACC_CSR__NOTIF_INTR_TRIG_T SAMPLE FUNCTIONS -----------------------*/
+    function void sha512_acc_csr__notif_intr_trig_t::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(notif_cmd_done_trig_bit_cg[bt]) this.notif_cmd_done_trig_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*notif_cmd_done_trig*/   );
+        end
+    endfunction
+
+    function void sha512_acc_csr__notif_intr_trig_t::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(notif_cmd_done_trig_bit_cg[bt]) this.notif_cmd_done_trig_bit_cg[bt].sample(notif_cmd_done_trig.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( notif_cmd_done_trig.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SHA512_ACC_CSR__INTR_COUNT_T_CNT_130AB269 SAMPLE FUNCTIONS -----------------------*/
+    function void sha512_acc_csr__intr_count_t_cnt_130ab269::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*cnt*/   );
+        end
+    endfunction
+
+    function void sha512_acc_csr__intr_count_t_cnt_130ab269::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(cnt.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( cnt.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SHA512_ACC_CSR__INTR_COUNT_T_CNT_324DFC53 SAMPLE FUNCTIONS -----------------------*/
+    function void sha512_acc_csr__intr_count_t_cnt_324dfc53::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*cnt*/   );
+        end
+    endfunction
+
+    function void sha512_acc_csr__intr_count_t_cnt_324dfc53::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(cnt.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( cnt.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SHA512_ACC_CSR__INTR_COUNT_T_CNT_791A4799 SAMPLE FUNCTIONS -----------------------*/
+    function void sha512_acc_csr__intr_count_t_cnt_791a4799::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*cnt*/   );
+        end
+    endfunction
+
+    function void sha512_acc_csr__intr_count_t_cnt_791a4799::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(cnt.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( cnt.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SHA512_ACC_CSR__INTR_COUNT_T_CNT_E9DE7334 SAMPLE FUNCTIONS -----------------------*/
+    function void sha512_acc_csr__intr_count_t_cnt_e9de7334::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*cnt*/   );
+        end
+    endfunction
+
+    function void sha512_acc_csr__intr_count_t_cnt_e9de7334::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(cnt.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( cnt.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SHA512_ACC_CSR__INTR_COUNT_T_CNT_BE67D6D5 SAMPLE FUNCTIONS -----------------------*/
+    function void sha512_acc_csr__intr_count_t_cnt_be67d6d5::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*cnt*/   );
+        end
+    endfunction
+
+    function void sha512_acc_csr__intr_count_t_cnt_be67d6d5::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(cnt.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( cnt.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SHA512_ACC_CSR__INTR_COUNT_INCR_T_PULSE_37026C97 SAMPLE FUNCTIONS -----------------------*/
+    function void sha512_acc_csr__intr_count_incr_t_pulse_37026c97::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*pulse*/   );
+        end
+    endfunction
+
+    function void sha512_acc_csr__intr_count_incr_t_pulse_37026c97::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(pulse.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( pulse.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SHA512_ACC_CSR__INTR_COUNT_INCR_T_PULSE_D860D977 SAMPLE FUNCTIONS -----------------------*/
+    function void sha512_acc_csr__intr_count_incr_t_pulse_d860d977::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*pulse*/   );
+        end
+    endfunction
+
+    function void sha512_acc_csr__intr_count_incr_t_pulse_d860d977::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(pulse.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( pulse.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SHA512_ACC_CSR__INTR_COUNT_INCR_T_PULSE_87B45FE7 SAMPLE FUNCTIONS -----------------------*/
+    function void sha512_acc_csr__intr_count_incr_t_pulse_87b45fe7::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*pulse*/   );
+        end
+    endfunction
+
+    function void sha512_acc_csr__intr_count_incr_t_pulse_87b45fe7::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(pulse.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( pulse.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SHA512_ACC_CSR__INTR_COUNT_INCR_T_PULSE_C1689EE6 SAMPLE FUNCTIONS -----------------------*/
+    function void sha512_acc_csr__intr_count_incr_t_pulse_c1689ee6::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*pulse*/   );
+        end
+    endfunction
+
+    function void sha512_acc_csr__intr_count_incr_t_pulse_c1689ee6::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(pulse.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( pulse.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SHA512_ACC_CSR__INTR_COUNT_INCR_T_PULSE_6173128E SAMPLE FUNCTIONS -----------------------*/
+    function void sha512_acc_csr__intr_count_incr_t_pulse_6173128e::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*pulse*/   );
+        end
+    endfunction
+
+    function void sha512_acc_csr__intr_count_incr_t_pulse_6173128e::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(pulse.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( pulse.get_mirrored_value()   );
+        end
+    endfunction
+
+`endif
\ No newline at end of file
diff --git a/src/soc_ifc/rtl/sha512_acc_csr_uvm.sv b/src/soc_ifc/rtl/sha512_acc_csr_uvm.sv
index ec1ea1517..d5f30e46e 100644
--- a/src/soc_ifc/rtl/sha512_acc_csr_uvm.sv
+++ b/src/soc_ifc/rtl/sha512_acc_csr_uvm.sv
@@ -3,177 +3,376 @@
 package sha512_acc_csr_uvm;
     `include "uvm_macros.svh"
     import uvm_pkg::*;
-    
+    `include "sha512_acc_csr_covergroups.svh"
     // Reg - sha512_acc_csr::LOCK
     class sha512_acc_csr__LOCK extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_acc_csr__LOCK_bit_cg LOCK_bit_cg[1];
+        sha512_acc_csr__LOCK_fld_cg fld_cg;
         rand uvm_reg_field LOCK;
 
         function new(string name = "sha512_acc_csr__LOCK");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.LOCK = new("LOCK");
-            this.LOCK.configure(this, 1, 0, "W1CRS", 0, 'h0, 1, 1, 0);
+            this.LOCK.configure(this, 1, 0, "W1CRS", 0, 'h1, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(LOCK_bit_cg[bt]) LOCK_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_acc_csr__LOCK
 
     // Reg - sha512_acc_csr::USER
     class sha512_acc_csr__USER extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_acc_csr__USER_bit_cg USER_bit_cg[32];
+        sha512_acc_csr__USER_fld_cg fld_cg;
         rand uvm_reg_field USER;
 
         function new(string name = "sha512_acc_csr__USER");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.USER = new("USER");
             this.USER.configure(this, 32, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(USER_bit_cg[bt]) USER_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_acc_csr__USER
 
     // Reg - sha512_acc_csr::MODE
     class sha512_acc_csr__MODE extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_acc_csr__MODE_bit_cg MODE_bit_cg[2];
+        sha512_acc_csr__MODE_bit_cg ENDIAN_TOGGLE_bit_cg[1];
+        sha512_acc_csr__MODE_fld_cg fld_cg;
         rand uvm_reg_field MODE;
         rand uvm_reg_field ENDIAN_TOGGLE;
 
         function new(string name = "sha512_acc_csr__MODE");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.MODE = new("MODE");
             this.MODE.configure(this, 2, 0, "RW", 0, 'h0, 1, 1, 0);
             this.ENDIAN_TOGGLE = new("ENDIAN_TOGGLE");
             this.ENDIAN_TOGGLE.configure(this, 1, 2, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(MODE_bit_cg[bt]) MODE_bit_cg[bt] = new();
+                foreach(ENDIAN_TOGGLE_bit_cg[bt]) ENDIAN_TOGGLE_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_acc_csr__MODE
 
     // Reg - sha512_acc_csr::START_ADDRESS
     class sha512_acc_csr__START_ADDRESS extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_acc_csr__START_ADDRESS_bit_cg ADDR_bit_cg[32];
+        sha512_acc_csr__START_ADDRESS_fld_cg fld_cg;
         rand uvm_reg_field ADDR;
 
         function new(string name = "sha512_acc_csr__START_ADDRESS");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.ADDR = new("ADDR");
             this.ADDR.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(ADDR_bit_cg[bt]) ADDR_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_acc_csr__START_ADDRESS
 
     // Reg - sha512_acc_csr::DLEN
     class sha512_acc_csr__DLEN extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_acc_csr__DLEN_bit_cg LENGTH_bit_cg[32];
+        sha512_acc_csr__DLEN_fld_cg fld_cg;
         rand uvm_reg_field LENGTH;
 
         function new(string name = "sha512_acc_csr__DLEN");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.LENGTH = new("LENGTH");
             this.LENGTH.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(LENGTH_bit_cg[bt]) LENGTH_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_acc_csr__DLEN
 
     // Reg - sha512_acc_csr::DATAIN
     class sha512_acc_csr__DATAIN extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_acc_csr__DATAIN_bit_cg DATAIN_bit_cg[32];
+        sha512_acc_csr__DATAIN_fld_cg fld_cg;
         rand uvm_reg_field DATAIN;
 
         function new(string name = "sha512_acc_csr__DATAIN");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.DATAIN = new("DATAIN");
             this.DATAIN.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(DATAIN_bit_cg[bt]) DATAIN_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_acc_csr__DATAIN
 
     // Reg - sha512_acc_csr::EXECUTE
     class sha512_acc_csr__EXECUTE extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_acc_csr__EXECUTE_bit_cg EXECUTE_bit_cg[1];
+        sha512_acc_csr__EXECUTE_fld_cg fld_cg;
         rand uvm_reg_field EXECUTE;
 
         function new(string name = "sha512_acc_csr__EXECUTE");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.EXECUTE = new("EXECUTE");
             this.EXECUTE.configure(this, 1, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(EXECUTE_bit_cg[bt]) EXECUTE_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_acc_csr__EXECUTE
 
     // Reg - sha512_acc_csr::STATUS
     class sha512_acc_csr__STATUS extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_acc_csr__STATUS_bit_cg VALID_bit_cg[1];
+        sha512_acc_csr__STATUS_bit_cg SOC_HAS_LOCK_bit_cg[1];
+        sha512_acc_csr__STATUS_fld_cg fld_cg;
         rand uvm_reg_field VALID;
+        rand uvm_reg_field SOC_HAS_LOCK;
 
         function new(string name = "sha512_acc_csr__STATUS");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.VALID = new("VALID");
             this.VALID.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            this.SOC_HAS_LOCK = new("SOC_HAS_LOCK");
+            this.SOC_HAS_LOCK.configure(this, 1, 1, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(VALID_bit_cg[bt]) VALID_bit_cg[bt] = new();
+                foreach(SOC_HAS_LOCK_bit_cg[bt]) SOC_HAS_LOCK_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_acc_csr__STATUS
 
     // Reg - sha512_acc_csr::DIGEST
     class sha512_acc_csr__DIGEST extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_acc_csr__DIGEST_bit_cg DIGEST_bit_cg[32];
+        sha512_acc_csr__DIGEST_fld_cg fld_cg;
         rand uvm_reg_field DIGEST;
 
         function new(string name = "sha512_acc_csr__DIGEST");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.DIGEST = new("DIGEST");
             this.DIGEST.configure(this, 32, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(DIGEST_bit_cg[bt]) DIGEST_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_acc_csr__DIGEST
 
     // Reg - sha512_acc_csr::CONTROL
     class sha512_acc_csr__CONTROL extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_acc_csr__CONTROL_bit_cg ZEROIZE_bit_cg[1];
+        sha512_acc_csr__CONTROL_fld_cg fld_cg;
         rand uvm_reg_field ZEROIZE;
 
         function new(string name = "sha512_acc_csr__CONTROL");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.ZEROIZE = new("ZEROIZE");
             this.ZEROIZE.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(ZEROIZE_bit_cg[bt]) ZEROIZE_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_acc_csr__CONTROL
 
     // Reg - sha512_acc_csr::global_intr_en_t
     class sha512_acc_csr__global_intr_en_t extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_acc_csr__global_intr_en_t_bit_cg error_en_bit_cg[1];
+        sha512_acc_csr__global_intr_en_t_bit_cg notif_en_bit_cg[1];
+        sha512_acc_csr__global_intr_en_t_fld_cg fld_cg;
         rand uvm_reg_field error_en;
         rand uvm_reg_field notif_en;
 
         function new(string name = "sha512_acc_csr__global_intr_en_t");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.error_en = new("error_en");
             this.error_en.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
             this.notif_en = new("notif_en");
             this.notif_en.configure(this, 1, 1, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(error_en_bit_cg[bt]) error_en_bit_cg[bt] = new();
+                foreach(notif_en_bit_cg[bt]) notif_en_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_acc_csr__global_intr_en_t
 
     // Reg - sha512_acc_csr::error_intr_en_t
     class sha512_acc_csr__error_intr_en_t extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_acc_csr__error_intr_en_t_bit_cg error0_en_bit_cg[1];
+        sha512_acc_csr__error_intr_en_t_bit_cg error1_en_bit_cg[1];
+        sha512_acc_csr__error_intr_en_t_bit_cg error2_en_bit_cg[1];
+        sha512_acc_csr__error_intr_en_t_bit_cg error3_en_bit_cg[1];
+        sha512_acc_csr__error_intr_en_t_fld_cg fld_cg;
         rand uvm_reg_field error0_en;
         rand uvm_reg_field error1_en;
         rand uvm_reg_field error2_en;
         rand uvm_reg_field error3_en;
 
         function new(string name = "sha512_acc_csr__error_intr_en_t");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.error0_en = new("error0_en");
@@ -184,61 +383,131 @@ package sha512_acc_csr_uvm;
             this.error2_en.configure(this, 1, 2, "RW", 0, 'h0, 1, 1, 0);
             this.error3_en = new("error3_en");
             this.error3_en.configure(this, 1, 3, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(error0_en_bit_cg[bt]) error0_en_bit_cg[bt] = new();
+                foreach(error1_en_bit_cg[bt]) error1_en_bit_cg[bt] = new();
+                foreach(error2_en_bit_cg[bt]) error2_en_bit_cg[bt] = new();
+                foreach(error3_en_bit_cg[bt]) error3_en_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_acc_csr__error_intr_en_t
 
     // Reg - sha512_acc_csr::notif_intr_en_t
     class sha512_acc_csr__notif_intr_en_t extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_acc_csr__notif_intr_en_t_bit_cg notif_cmd_done_en_bit_cg[1];
+        sha512_acc_csr__notif_intr_en_t_fld_cg fld_cg;
         rand uvm_reg_field notif_cmd_done_en;
 
         function new(string name = "sha512_acc_csr__notif_intr_en_t");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.notif_cmd_done_en = new("notif_cmd_done_en");
             this.notif_cmd_done_en.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(notif_cmd_done_en_bit_cg[bt]) notif_cmd_done_en_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_acc_csr__notif_intr_en_t
 
     // Reg - sha512_acc_csr::global_intr_t_agg_sts_dd3dcf0a
     class sha512_acc_csr__global_intr_t_agg_sts_dd3dcf0a extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_acc_csr__global_intr_t_agg_sts_dd3dcf0a_bit_cg agg_sts_bit_cg[1];
+        sha512_acc_csr__global_intr_t_agg_sts_dd3dcf0a_fld_cg fld_cg;
         rand uvm_reg_field agg_sts;
 
         function new(string name = "sha512_acc_csr__global_intr_t_agg_sts_dd3dcf0a");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.agg_sts = new("agg_sts");
             this.agg_sts.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(agg_sts_bit_cg[bt]) agg_sts_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_acc_csr__global_intr_t_agg_sts_dd3dcf0a
 
     // Reg - sha512_acc_csr::global_intr_t_agg_sts_e6399b4a
     class sha512_acc_csr__global_intr_t_agg_sts_e6399b4a extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_acc_csr__global_intr_t_agg_sts_e6399b4a_bit_cg agg_sts_bit_cg[1];
+        sha512_acc_csr__global_intr_t_agg_sts_e6399b4a_fld_cg fld_cg;
         rand uvm_reg_field agg_sts;
 
         function new(string name = "sha512_acc_csr__global_intr_t_agg_sts_e6399b4a");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.agg_sts = new("agg_sts");
             this.agg_sts.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(agg_sts_bit_cg[bt]) agg_sts_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_acc_csr__global_intr_t_agg_sts_e6399b4a
 
     // Reg - sha512_acc_csr::error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba
     class sha512_acc_csr__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_acc_csr__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba_bit_cg error0_sts_bit_cg[1];
+        sha512_acc_csr__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba_bit_cg error1_sts_bit_cg[1];
+        sha512_acc_csr__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba_bit_cg error2_sts_bit_cg[1];
+        sha512_acc_csr__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba_bit_cg error3_sts_bit_cg[1];
+        sha512_acc_csr__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba_fld_cg fld_cg;
         rand uvm_reg_field error0_sts;
         rand uvm_reg_field error1_sts;
         rand uvm_reg_field error2_sts;
         rand uvm_reg_field error3_sts;
 
         function new(string name = "sha512_acc_csr__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.error0_sts = new("error0_sts");
@@ -249,33 +518,71 @@ package sha512_acc_csr_uvm;
             this.error2_sts.configure(this, 1, 2, "W1C", 1, 'h0, 1, 1, 0);
             this.error3_sts = new("error3_sts");
             this.error3_sts.configure(this, 1, 3, "W1C", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(error0_sts_bit_cg[bt]) error0_sts_bit_cg[bt] = new();
+                foreach(error1_sts_bit_cg[bt]) error1_sts_bit_cg[bt] = new();
+                foreach(error2_sts_bit_cg[bt]) error2_sts_bit_cg[bt] = new();
+                foreach(error3_sts_bit_cg[bt]) error3_sts_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_acc_csr__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba
 
     // Reg - sha512_acc_csr::notif_intr_t_notif_cmd_done_sts_1c68637e
     class sha512_acc_csr__notif_intr_t_notif_cmd_done_sts_1c68637e extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_acc_csr__notif_intr_t_notif_cmd_done_sts_1c68637e_bit_cg notif_cmd_done_sts_bit_cg[1];
+        sha512_acc_csr__notif_intr_t_notif_cmd_done_sts_1c68637e_fld_cg fld_cg;
         rand uvm_reg_field notif_cmd_done_sts;
 
         function new(string name = "sha512_acc_csr__notif_intr_t_notif_cmd_done_sts_1c68637e");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.notif_cmd_done_sts = new("notif_cmd_done_sts");
             this.notif_cmd_done_sts.configure(this, 1, 0, "W1C", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(notif_cmd_done_sts_bit_cg[bt]) notif_cmd_done_sts_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_acc_csr__notif_intr_t_notif_cmd_done_sts_1c68637e
 
     // Reg - sha512_acc_csr::error_intr_trig_t
     class sha512_acc_csr__error_intr_trig_t extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_acc_csr__error_intr_trig_t_bit_cg error0_trig_bit_cg[1];
+        sha512_acc_csr__error_intr_trig_t_bit_cg error1_trig_bit_cg[1];
+        sha512_acc_csr__error_intr_trig_t_bit_cg error2_trig_bit_cg[1];
+        sha512_acc_csr__error_intr_trig_t_bit_cg error3_trig_bit_cg[1];
+        sha512_acc_csr__error_intr_trig_t_fld_cg fld_cg;
         rand uvm_reg_field error0_trig;
         rand uvm_reg_field error1_trig;
         rand uvm_reg_field error2_trig;
         rand uvm_reg_field error3_trig;
 
         function new(string name = "sha512_acc_csr__error_intr_trig_t");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.error0_trig = new("error0_trig");
@@ -286,160 +593,344 @@ package sha512_acc_csr_uvm;
             this.error2_trig.configure(this, 1, 2, "W1S", 0, 'h0, 1, 1, 0);
             this.error3_trig = new("error3_trig");
             this.error3_trig.configure(this, 1, 3, "W1S", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(error0_trig_bit_cg[bt]) error0_trig_bit_cg[bt] = new();
+                foreach(error1_trig_bit_cg[bt]) error1_trig_bit_cg[bt] = new();
+                foreach(error2_trig_bit_cg[bt]) error2_trig_bit_cg[bt] = new();
+                foreach(error3_trig_bit_cg[bt]) error3_trig_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_acc_csr__error_intr_trig_t
 
     // Reg - sha512_acc_csr::notif_intr_trig_t
     class sha512_acc_csr__notif_intr_trig_t extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_acc_csr__notif_intr_trig_t_bit_cg notif_cmd_done_trig_bit_cg[1];
+        sha512_acc_csr__notif_intr_trig_t_fld_cg fld_cg;
         rand uvm_reg_field notif_cmd_done_trig;
 
         function new(string name = "sha512_acc_csr__notif_intr_trig_t");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.notif_cmd_done_trig = new("notif_cmd_done_trig");
             this.notif_cmd_done_trig.configure(this, 1, 0, "W1S", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(notif_cmd_done_trig_bit_cg[bt]) notif_cmd_done_trig_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_acc_csr__notif_intr_trig_t
 
     // Reg - sha512_acc_csr::intr_count_t_cnt_130ab269
     class sha512_acc_csr__intr_count_t_cnt_130ab269 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_acc_csr__intr_count_t_cnt_130ab269_bit_cg cnt_bit_cg[32];
+        sha512_acc_csr__intr_count_t_cnt_130ab269_fld_cg fld_cg;
         rand uvm_reg_field cnt;
 
         function new(string name = "sha512_acc_csr__intr_count_t_cnt_130ab269");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.cnt = new("cnt");
             this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_acc_csr__intr_count_t_cnt_130ab269
 
     // Reg - sha512_acc_csr::intr_count_t_cnt_324dfc53
     class sha512_acc_csr__intr_count_t_cnt_324dfc53 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_acc_csr__intr_count_t_cnt_324dfc53_bit_cg cnt_bit_cg[32];
+        sha512_acc_csr__intr_count_t_cnt_324dfc53_fld_cg fld_cg;
         rand uvm_reg_field cnt;
 
         function new(string name = "sha512_acc_csr__intr_count_t_cnt_324dfc53");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.cnt = new("cnt");
             this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_acc_csr__intr_count_t_cnt_324dfc53
 
     // Reg - sha512_acc_csr::intr_count_t_cnt_791a4799
     class sha512_acc_csr__intr_count_t_cnt_791a4799 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_acc_csr__intr_count_t_cnt_791a4799_bit_cg cnt_bit_cg[32];
+        sha512_acc_csr__intr_count_t_cnt_791a4799_fld_cg fld_cg;
         rand uvm_reg_field cnt;
 
         function new(string name = "sha512_acc_csr__intr_count_t_cnt_791a4799");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.cnt = new("cnt");
             this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_acc_csr__intr_count_t_cnt_791a4799
 
     // Reg - sha512_acc_csr::intr_count_t_cnt_e9de7334
     class sha512_acc_csr__intr_count_t_cnt_e9de7334 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_acc_csr__intr_count_t_cnt_e9de7334_bit_cg cnt_bit_cg[32];
+        sha512_acc_csr__intr_count_t_cnt_e9de7334_fld_cg fld_cg;
         rand uvm_reg_field cnt;
 
         function new(string name = "sha512_acc_csr__intr_count_t_cnt_e9de7334");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.cnt = new("cnt");
             this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_acc_csr__intr_count_t_cnt_e9de7334
 
     // Reg - sha512_acc_csr::intr_count_t_cnt_be67d6d5
     class sha512_acc_csr__intr_count_t_cnt_be67d6d5 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_acc_csr__intr_count_t_cnt_be67d6d5_bit_cg cnt_bit_cg[32];
+        sha512_acc_csr__intr_count_t_cnt_be67d6d5_fld_cg fld_cg;
         rand uvm_reg_field cnt;
 
         function new(string name = "sha512_acc_csr__intr_count_t_cnt_be67d6d5");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.cnt = new("cnt");
             this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_acc_csr__intr_count_t_cnt_be67d6d5
 
     // Reg - sha512_acc_csr::intr_count_incr_t_pulse_37026c97
     class sha512_acc_csr__intr_count_incr_t_pulse_37026c97 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_acc_csr__intr_count_incr_t_pulse_37026c97_bit_cg pulse_bit_cg[1];
+        sha512_acc_csr__intr_count_incr_t_pulse_37026c97_fld_cg fld_cg;
         rand uvm_reg_field pulse;
 
         function new(string name = "sha512_acc_csr__intr_count_incr_t_pulse_37026c97");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.pulse = new("pulse");
             this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_acc_csr__intr_count_incr_t_pulse_37026c97
 
     // Reg - sha512_acc_csr::intr_count_incr_t_pulse_d860d977
     class sha512_acc_csr__intr_count_incr_t_pulse_d860d977 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_acc_csr__intr_count_incr_t_pulse_d860d977_bit_cg pulse_bit_cg[1];
+        sha512_acc_csr__intr_count_incr_t_pulse_d860d977_fld_cg fld_cg;
         rand uvm_reg_field pulse;
 
         function new(string name = "sha512_acc_csr__intr_count_incr_t_pulse_d860d977");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.pulse = new("pulse");
             this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_acc_csr__intr_count_incr_t_pulse_d860d977
 
     // Reg - sha512_acc_csr::intr_count_incr_t_pulse_87b45fe7
     class sha512_acc_csr__intr_count_incr_t_pulse_87b45fe7 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_acc_csr__intr_count_incr_t_pulse_87b45fe7_bit_cg pulse_bit_cg[1];
+        sha512_acc_csr__intr_count_incr_t_pulse_87b45fe7_fld_cg fld_cg;
         rand uvm_reg_field pulse;
 
         function new(string name = "sha512_acc_csr__intr_count_incr_t_pulse_87b45fe7");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.pulse = new("pulse");
             this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_acc_csr__intr_count_incr_t_pulse_87b45fe7
 
     // Reg - sha512_acc_csr::intr_count_incr_t_pulse_c1689ee6
     class sha512_acc_csr__intr_count_incr_t_pulse_c1689ee6 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_acc_csr__intr_count_incr_t_pulse_c1689ee6_bit_cg pulse_bit_cg[1];
+        sha512_acc_csr__intr_count_incr_t_pulse_c1689ee6_fld_cg fld_cg;
         rand uvm_reg_field pulse;
 
         function new(string name = "sha512_acc_csr__intr_count_incr_t_pulse_c1689ee6");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.pulse = new("pulse");
             this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_acc_csr__intr_count_incr_t_pulse_c1689ee6
 
     // Reg - sha512_acc_csr::intr_count_incr_t_pulse_6173128e
     class sha512_acc_csr__intr_count_incr_t_pulse_6173128e extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        sha512_acc_csr__intr_count_incr_t_pulse_6173128e_bit_cg pulse_bit_cg[1];
+        sha512_acc_csr__intr_count_incr_t_pulse_6173128e_fld_cg fld_cg;
         rand uvm_reg_field pulse;
 
         function new(string name = "sha512_acc_csr__intr_count_incr_t_pulse_6173128e");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.pulse = new("pulse");
             this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : sha512_acc_csr__intr_count_incr_t_pulse_6173128e
 
@@ -648,4 +1139,5 @@ package sha512_acc_csr_uvm;
         endfunction : build
     endclass : sha512_acc_csr
 
+    `include "sha512_acc_csr_sample.svh"
 endpackage: sha512_acc_csr_uvm
diff --git a/src/soc_ifc/rtl/sha512_acc_external_csr.rdl b/src/soc_ifc/rtl/sha512_acc_external_csr.rdl
index 5a80b3757..4f273224a 100644
--- a/src/soc_ifc/rtl/sha512_acc_external_csr.rdl
+++ b/src/soc_ifc/rtl/sha512_acc_external_csr.rdl
@@ -19,7 +19,7 @@ reg {
     desc="SHA lock register for SHA access, reading 0 will set the lock, Write 1 to clear the lock
           [br]Caliptra Access: RW
           [br]SOC Access:      RW";
-    field {rset; woclr; sw=rw; hw=r; swwe=valid_user; swmod=true;} LOCK=0;
+    field {rset; woclr; sw=rw; hw=r; swwe=valid_user; swmod=true;} LOCK=1;
 } LOCK;
 
 reg {
@@ -95,7 +95,7 @@ reg {
           For the Mailbox SHA Function, indicates that the SHA can begin execution.
           [br]Caliptra Access: RW
           [br]SOC Access:      RW";
-    field {sw=rw; hw=r; hwclr;} EXECUTE=0;
+    field {sw=rw; hw=r; hwclr; swwe=valid_user;} EXECUTE=0;
 } EXECUTE;
 
 reg {
@@ -108,6 +108,8 @@ reg {
     default hw = rw;
     default resetsignal = cptra_rst_b;
     field {desc = "Valid bit, indicating that the digest is complete";} VALID = 1'b0;
+    field {name = "SoC Acquired the Lock";
+           desc = "Indicates that the current lock was acquired by the SoC";} SOC_HAS_LOCK=1'b0;
 
 } STATUS;
 
diff --git a/src/soc_ifc/rtl/sha512_acc_top.sv b/src/soc_ifc/rtl/sha512_acc_top.sv
index fd8032c62..79b52410a 100644
--- a/src/soc_ifc/rtl/sha512_acc_top.sv
+++ b/src/soc_ifc/rtl/sha512_acc_top.sv
@@ -14,7 +14,8 @@
 
 module sha512_acc_top
     import soc_ifc_pkg::*;
-    import sha512_acc_csr_pkg::*;   
+    import sha512_acc_csr_pkg::*;
+    import sha512_params_pkg::*; 
   #(
     parameter DATA_WIDTH = 32
     )(
@@ -44,22 +45,12 @@ module sha512_acc_top
   //----------------------------------------------------------------
   // Internal constant and parameter definitions.
   //----------------------------------------------------------------
-  `include "sha512_param.sv"
   localparam DATA_NUM_BYTES = DATA_WIDTH / 8;
   localparam BLOCK_NO = 1024 / DATA_WIDTH;
   localparam BYTE_NO = 1024 / 8;
   localparam BLOCK_OFFSET_W = $clog2(BLOCK_NO);
   localparam BYTE_OFFSET_W = $clog2(1024/8);
 
-  typedef enum logic [2:0] {
-    SHA_IDLE    = 3'b000,
-    SHA_BLOCK_0 = 3'b001,
-    SHA_BLOCK_N = 3'b011,
-    SHA_PAD0    = 3'b010,
-    SHA_PAD1    = 3'b110,
-    SHA_DONE    = 3'b100
-  } sha_fsm_state_e;
-
   logic lock_set;
   logic datain_write;
   logic stall_write;
@@ -102,7 +93,6 @@ module sha512_acc_top
   logic block_we;
   logic mbox_mode_last_dword_wr;
   logic block_full;
-  logic pad_last_block;
   logic [31:0] num_bytes_wr;
   logic [BLOCK_OFFSET_W:0] block_wptr;
   logic [DATA_NUM_BYTES-1:0][7:0] mbox_rdata;
@@ -189,17 +179,17 @@ always_comb core_digest_valid_q = core_digest_valid & ~(init_reg | next_reg);
   always_comb hwif_in.valid_user = hwif_out.LOCK.LOCK.value & ((~soc_has_lock & ~req_data.soc_req) |
                                                                 (soc_has_lock & req_data.soc_req & (req_data.user == hwif_out.USER.USER.value)));
   always_comb hwif_in.soc_req = req_data.soc_req;
-
+  always_comb hwif_in.STATUS.SOC_HAS_LOCK.next = soc_has_lock;
+  
   always_comb mode = hwif_out.MODE.MODE.value;
   //mode encoding bit 0 determines 512 or 384.
   always_comb sha_mode = mode[0] ? MODE_SHA_512 : MODE_SHA_384;
-  always_comb streaming_mode = ~mode[1];
-  always_comb mailbox_mode = mode[1];
+  //determine streaming or mailbox mode - SoC is limited to streaming mode only
+  always_comb streaming_mode = ~mode[1] | soc_has_lock;
+  always_comb mailbox_mode = mode[1] & ~soc_has_lock;
   //Detect writes to datain register
   always_comb datain_write = hwif_in.valid_user & hwif_out.DATAIN.DATAIN.swmod;
   always_comb execute_set = hwif_out.EXECUTE.EXECUTE.value;
-  //flag to indicate that our last block will need the padding added to it
-  always_comb pad_last_block = (|hwif_out.DLEN.LENGTH.value[1:0]);
 
   //When we reach the end of a block we indicate block full
   //If this is also the end of the entire DLEN, mask block full so that we properly pad the last dword
diff --git a/src/soc_ifc/rtl/soc_ifc_arb.sv b/src/soc_ifc/rtl/soc_ifc_arb.sv
index b1d273cb8..8660009a9 100644
--- a/src/soc_ifc/rtl/soc_ifc_arb.sv
+++ b/src/soc_ifc/rtl/soc_ifc_arb.sv
@@ -21,6 +21,7 @@ module soc_ifc_arb
     input  logic rst_b,
 
     input logic [4:0][APB_USER_WIDTH-1:0] valid_mbox_users,
+    input logic valid_fuse_user,
     //UC inf
     input  logic uc_req_dv,
     output logic uc_req_hold,
@@ -39,6 +40,7 @@ module soc_ifc_arb
     input  logic mbox_req_hold,
     output soc_ifc_req_t mbox_req_data,
     input  logic [SOC_IFC_DATA_W-1:0] mbox_rdata,
+    input  logic [SOC_IFC_DATA_W-1:0] mbox_dir_rdata,
     input  logic mbox_error,
     //SHA inf
     output logic sha_req_dv,
@@ -135,8 +137,11 @@ always_comb uc_mbox_dir_req = (uc_req_dv & (uc_req_data.addr inside {[MBOX_DIR_S
 //SoC requests to mailbox
 always_comb soc_mbox_req = (valid_mbox_req & (soc_req_data.addr inside {[MBOX_REG_START_ADDR:MBOX_REG_END_ADDR]}));
 //Requests to arch/fuse register block
+//Ensure that requests to fuse block match the appropriate user value
 always_comb uc_reg_req = (uc_req_dv & (uc_req_data.addr inside {[SOC_IFC_REG_START_ADDR:SOC_IFC_REG_END_ADDR]}));
-always_comb soc_reg_req = (soc_req_dv & (soc_req_data.addr inside {[SOC_IFC_REG_START_ADDR:SOC_IFC_REG_END_ADDR]}));
+always_comb soc_reg_req = (soc_req_dv & (soc_req_data.addr inside {[SOC_IFC_REG_START_ADDR:SOC_IFC_REG_END_ADDR]}) &
+                                        (~(soc_req_data.addr inside {[SOC_IFC_FUSE_START_ADDR:SOC_IFC_FUSE_END_ADDR]}) | valid_fuse_user));
+
 //Requests to SHA
 always_comb uc_sha_req = (uc_req_dv & (uc_req_data.addr inside {[SHA_REG_START_ADDR:SHA_REG_END_ADDR]}));
 always_comb soc_sha_req = (soc_req_dv & (soc_req_data.addr inside {[SHA_REG_START_ADDR:SHA_REG_END_ADDR]}));
@@ -153,19 +158,21 @@ always_comb begin
 end
 
 //check for collisions
-always_comb req_collision = (uc_mbox_req & soc_mbox_req) |
-                            (uc_reg_req & soc_reg_req) |
-                            (uc_sha_req & soc_sha_req);
+//don't toggle priority if the request was held
+always_comb req_collision = (uc_mbox_req & soc_mbox_req & ~mbox_req_hold) |
+                            (uc_reg_req & soc_reg_req & ~soc_ifc_reg_req_hold) |
+                            (uc_sha_req & soc_sha_req & ~sha_req_hold);
 
 //drive the dv to the appropriate destination if either client is trying to 
 always_comb mbox_req_dv = uc_mbox_reg_req | soc_mbox_req;
-always_comb mbox_dir_req_dv = uc_mbox_dir_req;
+always_comb mbox_dir_req_dv = uc_mbox_dir_req & uc_mbox_gnt;
 always_comb soc_ifc_reg_req_dv = uc_reg_req | soc_reg_req;
 always_comb sha_req_dv = uc_sha_req | soc_sha_req;
 
 //determine which requests get granted
 //if a request is colliding with another, grant the one with priority
 //ignore priority if one of the requests was already in progress
+//this prevents the "priority" request from interrupting an in progress request
 always_comb soc_mbox_gnt = soc_mbox_req & (~uc_mbox_req | soc_has_priority) & ~uc_mbox_req_ip;
 always_comb soc_reg_gnt  = soc_reg_req  & (~uc_reg_req | soc_has_priority)  & ~uc_reg_req_ip;
 always_comb soc_sha_gnt  = soc_sha_req  & (~uc_sha_req | soc_has_priority)  & ~uc_sha_req_ip;
@@ -186,7 +193,8 @@ always_comb sha_req_data = ({$bits(soc_ifc_req_t){soc_sha_gnt}} & soc_req_data)
 
 //drive the appropriate read data back to uc or soc
 //AND/OR mux here, assert that requests are always mutex
-always_comb uc_rdata = ({MBOX_DATA_W{uc_mbox_req}} & mbox_rdata) | 
+always_comb uc_rdata = ({MBOX_DATA_W{uc_mbox_reg_req}} & mbox_rdata) |
+                       ({MBOX_DATA_W{uc_mbox_dir_req}} & mbox_dir_rdata) |
                        ({MBOX_DATA_W{uc_reg_req}} & soc_ifc_reg_rdata) | 
                        ({MBOX_DATA_W{uc_sha_req}} & sha_rdata);
 
diff --git a/src/soc_ifc/rtl/soc_ifc_boot_fsm.sv b/src/soc_ifc/rtl/soc_ifc_boot_fsm.sv
index c869a1988..e5b522184 100644
--- a/src/soc_ifc/rtl/soc_ifc_boot_fsm.sv
+++ b/src/soc_ifc/rtl/soc_ifc_boot_fsm.sv
@@ -19,6 +19,7 @@ module soc_ifc_boot_fsm
     input logic clk,
     input logic cptra_pwrgood,
     input logic cptra_rst_b,
+    input logic scan_mode,
     input logic fw_update_rst,
     input logic [7:0] fw_update_rst_wait_cycles,
 
@@ -27,6 +28,7 @@ module soc_ifc_boot_fsm
     input logic BootFSM_Continue,
 
     output logic ready_for_fuses,
+    output boot_fsm_state_e boot_fsm_ps,
 
     input logic fuse_done,
     input logic fuse_wr_done_observed,
@@ -34,25 +36,31 @@ module soc_ifc_boot_fsm
     output logic cptra_noncore_rst_b, //Global rst that goes to all other blocks
     output logic cptra_uc_rst_b, //Global + fw update rst that goes to VeeR core only,
     output logic iccm_unlock,
-    output logic fw_upd_rst_executed
+    output logic fw_upd_rst_executed,
+    output logic rdc_clk_dis,
+    output logic fw_update_rst_window
 );
 
 `include "caliptra_sva.svh"
 
+logic cptra_uc_rst_b_nq;
+logic cptra_noncore_rst_b_nq;
+
 //present and next state
 boot_fsm_state_e boot_fsm_ns;
-boot_fsm_state_e boot_fsm_ps;
 //arcs between states - global rst
+logic arc_BOOT_IDLE_BOOT_FUSE;
 logic arc_BOOT_FUSE_BOOT_DONE;
 logic arc_BOOT_FUSE_BOOT_WAIT;
 logic arc_BOOT_DONE_BOOT_IDLE;
 //arcs for fw update rst
 logic arc_BOOT_DONE_BOOT_FWRST;
+logic arc_BOOT_FWRST_BOOT_WAIT;
 logic arc_BOOT_WAIT_BOOT_DONE;
+logic arc_IDLE;
 //reset generation
-logic propagate_reset_en;
-logic propagate_uc_reset_en;
 logic fsm_synch_noncore_rst_b;
+logic synch_noncore_rst_b;
 logic fsm_synch_uc_rst_b;
 logic synch_uc_rst_b;
 
@@ -61,8 +69,11 @@ logic [7:0] wait_count;
 logic wait_count_rst;
 logic wait_count_decr;
 
-//move to fuse state when SoC de-asserts reset
+logic cptra_rst_window;
+logic cptra_rst_window_sync, cptra_rst_window_sync_f, cptra_rst_window_sync_2f;
 
+//move to fuse state when SoC de-asserts reset
+always_comb arc_BOOT_IDLE_BOOT_FUSE = (boot_fsm_ps == BOOT_IDLE) & ~cptra_rst_window_sync & ~cptra_rst_window_sync_f & ~cptra_rst_window_sync_2f;
 //move from fuse state to done when fuse done register is set OR
 //if it was already set (since its locked across warm reset), that the write was observed from SOC
 always_comb arc_BOOT_FUSE_BOOT_DONE = fuse_done & fuse_wr_done_observed;
@@ -73,59 +84,72 @@ always_comb arc_BOOT_FUSE_BOOT_WAIT = BootFSM_BrkPoint;
 //dummy arc for terminal state lint check
 always_comb arc_BOOT_DONE_BOOT_IDLE = '0;
 
+always_comb arc_IDLE = cptra_rst_window_sync;
+
+//Masks combo paths from uc reset flops into other reset domains
+always_comb fw_update_rst_window = boot_fsm_ps inside {BOOT_FW_RST,BOOT_WAIT};
+//clock gate all flops on warm reset to prevent RDC metastability issues
+//cover 2 clocks after synchronized reset assertion (cptra_rst_window_sync) to handle bootfsm transitions
+always_comb rdc_clk_dis = cptra_rst_window_sync | cptra_rst_window_sync_f | cptra_rst_window_sync_2f;
+
+//move to rst state when reg bit is set to 1. This state will assert fw_rst to uc
+always_comb arc_BOOT_DONE_BOOT_FWRST = (boot_fsm_ps == BOOT_DONE) & fw_update_rst;
+//advance to boot wait when reset starts to propagate
+always_comb arc_BOOT_FWRST_BOOT_WAIT = ~synch_uc_rst_b;
+
+// TODO: Capture BootFSM_BrkPoint only at the point of cold or warm reset exit
+// Move to BOOT_DONE state when
+// a fixed time is met AND
+// if the BootFSM breakpoint is asserted and the BootFSM continue is not set, stay put in WAIT state
+always_comb arc_BOOT_WAIT_BOOT_DONE = (wait_count == '0) & ~(BootFSM_BrkPoint & ~BootFSM_Continue);
 
-always_comb begin
-    //move to rst state when reg bit is set to 1. This state will assert fw_rst to uc
-    arc_BOOT_DONE_BOOT_FWRST = fw_update_rst;
-
-    // TODO: Capture BootFSM_BrkPoint only at the point of cold or warm reset exit
-    // Move to BOOT_DONE state when
-          // a fixed time is met AND
-          // if the BootFSM breakpoint is asserted and the BootFSM continue is not set, stay put in WAIT state
-    arc_BOOT_WAIT_BOOT_DONE = (wait_count == '0) & ~(BootFSM_BrkPoint & ~BootFSM_Continue);
-end
 
 always_comb begin
     boot_fsm_ns = boot_fsm_ps;
-    ready_for_fuses = '0;
-    propagate_reset_en = '0;
-    propagate_uc_reset_en = '0;
-    fw_upd_rst_executed = 0;
+    fw_upd_rst_executed = '0;
+    fsm_synch_noncore_rst_b = '0;
+    fsm_iccm_unlock = '0;
+    fsm_synch_uc_rst_b = '0;
+    wait_count_decr = 0;
+    wait_count_rst = 0;
 
-    unique casez (boot_fsm_ps)
+    unique case (boot_fsm_ps) inside
         BOOT_IDLE: begin
-            boot_fsm_ns = BOOT_FUSE;
-
+            if (arc_BOOT_IDLE_BOOT_FUSE) begin
+                boot_fsm_ns = BOOT_FUSE;
+            end
             //reset flags in IDLE
             // NOTE: FSM is only in BOOT_IDLE when system reset is asserted, so
             //       also assert the internal core/noncore resets
             fsm_synch_uc_rst_b = '0;
+            fsm_synch_noncore_rst_b = '0;
             fsm_iccm_unlock = '0;
             wait_count_decr = 0;
             wait_count_rst = 0;
         end
         BOOT_FUSE: begin
             if (arc_BOOT_FUSE_BOOT_DONE) begin
-               if (arc_BOOT_FUSE_BOOT_WAIT) begin
-                  boot_fsm_ns = BOOT_WAIT;
-               end
-               else begin
-                   boot_fsm_ns = BOOT_DONE;
-               end
+                if (arc_BOOT_FUSE_BOOT_WAIT) begin
+                    boot_fsm_ns = BOOT_WAIT;
+                end
+                else begin
+                    boot_fsm_ns = BOOT_DONE;
+                end
             end
-            ready_for_fuses = 1'b1;
 
             //reset flags
             fsm_synch_uc_rst_b = '0;
+            fsm_synch_noncore_rst_b = '1;
             fsm_iccm_unlock = '0;
             wait_count_decr = 0;
             wait_count_rst = 0;
         end
         BOOT_FW_RST: begin
-            boot_fsm_ns = BOOT_WAIT;
+            if (arc_BOOT_FWRST_BOOT_WAIT) boot_fsm_ns = BOOT_WAIT;
 
             //Assert core reset
             fsm_synch_uc_rst_b = '0;
+            fsm_synch_noncore_rst_b = '1;
             //Keep ICCM locked until end of fw rst
             fsm_iccm_unlock = '0;
             //Start timer
@@ -143,6 +167,7 @@ always_comb begin
                 fsm_iccm_unlock = '0;
             end
             fsm_synch_uc_rst_b = '0;
+            fsm_synch_noncore_rst_b = '1;
             wait_count_decr = 1;
             wait_count_rst = 0;
         end
@@ -159,11 +184,9 @@ always_comb begin
                 fw_upd_rst_executed = 1;
             end
 
-            //propagate reset de-assertion from synchronizer when boot fsm is in BOOT_DONE state
-            propagate_reset_en = 1'b1;
-            propagate_uc_reset_en = 1'b1;
-            //Deassert core reset
+            //Deassert reset
             fsm_synch_uc_rst_b = '1;
+            fsm_synch_noncore_rst_b = '1;
             fsm_iccm_unlock = '0;
             //Timer re-init
             wait_count_rst = 0;
@@ -171,48 +194,82 @@ always_comb begin
         end
         default: begin
             boot_fsm_ns = boot_fsm_ps;
-            fsm_synch_uc_rst_b = '1;
+            fw_upd_rst_executed = '0;
+            fsm_synch_noncore_rst_b = '0;
             fsm_iccm_unlock = '0;
+            fsm_synch_uc_rst_b = '0;
             wait_count_decr = 0;
             wait_count_rst = 0;
         end
     endcase
 end
 
-//uC reset generation
-
 //next state -> present state
-//reset boot fsm to idle on cptra_rst_b
+//reset boot fsm to idle on cptra_pwrgood
+always_ff @(posedge clk or negedge cptra_pwrgood) begin
+    if (~cptra_pwrgood) begin
+        boot_fsm_ps <= BOOT_IDLE;
+        synch_noncore_rst_b <= '0;
+        synch_uc_rst_b <= 0;
+        cptra_noncore_rst_b_nq <= '0;
+        cptra_uc_rst_b_nq <= '0;
+
+        cptra_rst_window_sync_f <= '1;
+        cptra_rst_window_sync_2f <= '1;
+    end
+    else begin
+        boot_fsm_ps <= arc_IDLE ? BOOT_IDLE : boot_fsm_ns;
+        synch_noncore_rst_b <= fsm_synch_noncore_rst_b;
+        synch_uc_rst_b <= fsm_synch_uc_rst_b;
+        cptra_noncore_rst_b_nq <= synch_noncore_rst_b;
+        cptra_uc_rst_b_nq <= synch_noncore_rst_b && synch_uc_rst_b; //uc comes out of rst only when both global and fw rsts are deasserted (through 2FF sync)
+
+        cptra_rst_window_sync_f <= cptra_rst_window_sync;
+        cptra_rst_window_sync_2f <= cptra_rst_window_sync_f;
+    end
+end
+
+//protect resets during scan mode
+//TODO dft override for reset?
+assign cptra_noncore_rst_b = cptra_noncore_rst_b_nq | scan_mode;
+assign cptra_uc_rst_b = cptra_uc_rst_b_nq | scan_mode;
+
+//uC reset generation
 always_ff @(posedge clk or negedge cptra_rst_b) begin
     if (~cptra_rst_b) begin
-        boot_fsm_ps <= BOOT_IDLE;
-        fsm_synch_noncore_rst_b <= '0;
-        cptra_noncore_rst_b <= '0;
-        cptra_uc_rst_b <= '0;
+        cptra_rst_window <= '1;
+    end
+    else begin
+        cptra_rst_window <= 0;
+    end
+end
+
+// Ready for fuses output signal
+always_ff @(posedge clk or negedge cptra_noncore_rst_b) begin
+    if (~cptra_noncore_rst_b) begin
+        ready_for_fuses <= 1'b0;
         wait_count <= '0;
-        synch_uc_rst_b <= 0;
         iccm_unlock <= 0;
     end
     else begin
-        boot_fsm_ps <= boot_fsm_ns;
-        fsm_synch_noncore_rst_b <= propagate_reset_en ? '1 : fsm_synch_noncore_rst_b;
-        synch_uc_rst_b <= propagate_uc_reset_en ? '1 : fsm_synch_uc_rst_b;
-        cptra_noncore_rst_b <= fsm_synch_noncore_rst_b;
-        cptra_uc_rst_b <= fsm_synch_noncore_rst_b && fsm_synch_uc_rst_b && synch_uc_rst_b; //uc comes out of rst only when both global and fw rsts are deasserted (through 2FF sync)
-
-        wait_count <= (wait_count_decr && (wait_count != '0)) ? wait_count - 1
-                                      : wait_count_rst ? fw_update_rst_wait_cycles
-                                                        : wait_count ;
+        ready_for_fuses <= (boot_fsm_ps == BOOT_FUSE) && !fuse_wr_done_observed;
+        wait_count <= (wait_count_decr && (wait_count != '0)) ? wait_count - 1 :
+                                               wait_count_rst ? fw_update_rst_wait_cycles :
+                                                                wait_count ;
         iccm_unlock <= fsm_iccm_unlock;
     end
 end
 
+caliptra_2ff_sync #(.WIDTH(1), .RST_VAL('d1)) i_rst_window_sync (.clk(clk), .rst_b(cptra_pwrgood), .din(cptra_rst_window), .dout(cptra_rst_window_sync));
+
+//Check for x prop
 `CALIPTRA_ASSERT_KNOWN(ERR_FSM_ARC_X, {arc_BOOT_FUSE_BOOT_DONE, arc_BOOT_DONE_BOOT_FWRST, arc_BOOT_WAIT_BOOT_DONE}, clk, cptra_rst_b)
 `CALIPTRA_ASSERT_KNOWN(ERR_FSM_STATE_X, boot_fsm_ps, clk, cptra_rst_b)
 `CALIPTRA_ASSERT_KNOWN(ERR_UC_RST_X, cptra_noncore_rst_b, clk, cptra_rst_b)
 `CALIPTRA_ASSERT_KNOWN(ERR_UC_FWRST_X, cptra_uc_rst_b, clk, cptra_rst_b)
-`CALIPTRA_ASSERT_NEVER(ERR_UC_RST_ASSERT_AND_BOOT_NOT_DONE, cptra_noncore_rst_b && ((boot_fsm_ps == BOOT_IDLE) || (boot_fsm_ps == BOOT_FUSE)), clk, cptra_rst_b)
-`CALIPTRA_ASSERT(ERR_UC_RST_ASSERT_AND_BOOT_NOT_DONE2, ~cptra_noncore_rst_b || (boot_fsm_ps == BOOT_DONE) || (boot_fsm_ps == BOOT_FW_RST) || (boot_fsm_ps == BOOT_WAIT), clk, cptra_rst_b)
-`CALIPTRA_ASSERT_NEVER(ERR_UC_FWRST_ASSERT_AND_BOOT_NOT_DONE, cptra_uc_rst_b && (boot_fsm_ps == BOOT_WAIT), clk, cptra_rst_b)
+
+//Reset got asserted, but cptra rst window wasn't asserted to protect RDC
+`CALIPTRA_ASSERT_NEVER(ERR_RST_ASSERT_NO_WINDOW, $fell(cptra_noncore_rst_b) && ~rdc_clk_dis, clk, cptra_pwrgood)
+`CALIPTRA_ASSERT_NEVER(ERR_UC_RST_ASSERT_NO_WINDOW, $fell(cptra_uc_rst_b) && ~(fw_update_rst_window || rdc_clk_dis), clk, cptra_pwrgood)
 
 endmodule
diff --git a/src/soc_ifc/rtl/soc_ifc_external_reg.rdl b/src/soc_ifc/rtl/soc_ifc_external_reg.rdl
index 4e6e12a98..bd3aa0ac3 100644
--- a/src/soc_ifc/rtl/soc_ifc_external_reg.rdl
+++ b/src/soc_ifc/rtl/soc_ifc_external_reg.rdl
@@ -17,16 +17,20 @@
 reg {
     name = "Hardware Error Fatal";
     desc = "Indicates fatal hardware error.
-            [br]Caliptra Access: RW
-            [br]SOC Access:      RW";
-    rw_rw_sticky_hw error_code[32]=0; 
+            [br]Caliptra Access: RW1C
+            [br]SOC Access:      RW1C";
+    rw_rw_sticky_hw iccm_ecc_unc=0;     /* Uncorrectable double-bit error in ICCM */
+    rw_rw_sticky_hw dccm_ecc_unc=0;     /* Uncorrectable double-bit error in DCCM */
+    rw_rw_sticky_hw nmi_pin=0;          /* Non-Maskable Interrupt due to WDT timeout */
 } CPTRA_HW_ERROR_FATAL;
 reg {
     name = "Hardware Error Non-Fatal";
     desc = "Indicates non-fatal hardware error.
-            [br]Caliptra Access: RW
-            [br]SOC Access:      RW";
-    rw_rw_sticky_hw error_code[32]=0; 
+            [br]Caliptra Access: RW1C
+            [br]SOC Access:      RW1C";
+    rw_rw_sticky_hw mbox_prot_no_lock=0; /* SOC access while not locked */
+    rw_rw_sticky_hw mbox_prot_ooo=0;     /* Register access out-of-order */
+    rw_rw_sticky_hw mbox_ecc_unc=0;      /* Uncorrectable double-bit error in DCCM */
 } CPTRA_HW_ERROR_NON_FATAL;
 reg {
     name = "Firmware Error Fatal";
@@ -78,13 +82,14 @@ reg {
     desc = "Reports the status of the firmware flows.
             [br]Caliptra Access: RW
             [br]SOC Access:      RO";
-    rw_ro status[28]=0;
-    //TRNG request bit
-     field {desc="Indicates Caliptra is ready for Firmware Download";         sw=rw; swwel = soc_req; hw=r ; resetsignal = cptra_rst_b;} ready_for_fw[1]=0;
-     field {desc="Indicates Caliptra is ready for Runtime Firmware Download"; sw=rw; swwel = soc_req; hw=r ; resetsignal = cptra_rst_b;} ready_for_runtime[1]=0;
-     field {desc="Indicates Caliptra is ready for Fuses to be programmed.
-                  Read-only to both Caliptra and SOC.";                       sw=r;                   hw=rw; resetsignal = cptra_rst_b;} ready_for_fuses[1];
-     field {desc="Indicates Caliptra is has completed Mailbox Flow.";         sw=rw; swwel = soc_req; hw=r ; resetsignal = cptra_rst_b;} mailbox_flow_done[1]=0;
+    rw_ro status[24]=0;
+    field {desc="DEV ID CSR ready";                                          sw=rw; swwel = soc_req; hw=r ; resetsignal = cptra_rst_b;} idevid_csr_ready[1]=0;
+    field {desc="Boot FSM State";                                            sw=r;                   hw=w ; /* no storage, no reset */} boot_fsm_ps[3];
+    field {desc="Indicates Caliptra is ready for Firmware Download";         sw=rw; swwel = soc_req; hw=r ; resetsignal = cptra_rst_b;} ready_for_fw[1]=0;
+    field {desc="Indicates Caliptra is ready for RT flows";                  sw=rw; swwel = soc_req; hw=r ; resetsignal = cptra_rst_b;} ready_for_runtime[1]=0;
+    field {desc="Indicates Caliptra is ready for Fuses to be programmed.
+                 Read-only to both Caliptra and SOC.";                       sw=r;                   hw=w ; /* no storage, no reset */} ready_for_fuses[1];
+    field {desc="Indicates Caliptra is has completed Mailbox Flow.";         sw=rw; swwel = soc_req; hw=r ; resetsignal = cptra_rst_b;} mailbox_flow_done[1]=0;
 } CPTRA_FLOW_STATUS;
 reg {
     name = "Reset Reason";
@@ -167,9 +172,17 @@ reg {
     desc = "Storage for the requested TRNG Data.
             [br]Caliptra Access: RO
             [br]SOC Access:      RW";
-    field {sw=rw; hw=na; swwe; swacc; resetsignal=cptra_rst_b;} DATA[32]=0;
+    field {sw=rw; hw=na; swwe; swacc; hwclr; resetsignal=cptra_rst_b;} DATA[32]=0;
  } CPTRA_TRNG_DATA[12];
 
+ reg {
+    name = "TRNG Ctrl";
+    desc = "TRNG Control register to clear data registers";
+    field {desc = "Indicates that TRNG Data can be cleared
+            [br]Caliptra Access: RW
+            [br]SOC Access:      RO";  sw=rw; hw=r; singlepulse; swwel=soc_req; resetsignal=cptra_rst_b;} clear=0;
+} CPTRA_TRNG_CTRL;
+
 reg {
     name = "TRNG Status";
     desc = "TRNG Status register to indicate request and done";
@@ -244,9 +257,11 @@ reg {
 reg {
     name = "Caliptra HW RevID";
     desc = "Caliptra HW revision ID that matches the official final release milestone
+            SoC stepping ID is repopulated with the value in the fuse register on every warm reset
             [br]Caliptra Access: RO
             [br]SOC Access:      RO";
-    field {sw=r; hw=r; resetsignal = cptra_rst_b;} REV_ID[32]=1;
+    field {sw=r; resetsignal = cptra_rst_b;} CPTRA_GENERATION[16]=1;
+    field {sw=r; hw=w; resetsignal = cptra_rst_b;} SOC_STEPPING_ID[16]=0;
 } CPTRA_HW_REV_ID;
 reg {
     name = "Caliptra FW RevID";
@@ -322,8 +337,55 @@ reg {
 reg {
     name = "Caliptra WDT STATUS register";
     desc = "Caliptra watchdog timer status register
-            [br]Caliptra Access: RO
+            [br]Caliptra Access: RW
             [br]SOC Access:      RO";
     field {desc = "Timer1 timed out, timer2 enabled"; hw = rw; sw = rw; swwel = soc_req; resetsignal = cptra_rst_b;} t1_timeout = 1'b0;
     field {desc = "Timer2 timed out"; hw = rw; sw = rw; swwel = soc_req; resetsignal = cptra_rst_b;} t2_timeout = 1'b0;
-} CPTRA_WDT_STATUS;
\ No newline at end of file
+} CPTRA_WDT_STATUS;
+
+reg {
+    name = "Valid User for FUSE";
+    desc = "Valid PAUSER attributes for FUSE on SoC APB Interface. Only valid once LOCK is set.
+            [br]Caliptra Access: RW
+            [br]SOC Access:      RW
+            [br]Read-Only once locked by FUSE_PAUSER_LOCK.";
+    field {sw=rw; hw=r; swwel; resetsignal = cptra_pwrgood;} PAUSER[32]=0xFFFF_FFFF;
+ } CPTRA_FUSE_VALID_PAUSER;
+
+reg {
+    name = "Valid User for FUSE PAUSER Lock";
+    desc = "Valid PAUSER attributes for requests from SoC APB Interface.
+            [br]Each bit corresponds to locking the associated FUSE_VALID_PAUSER register.
+            [br]Associated FUSE_VALID_PAUSER register is only valid once locked by this bit.
+            [br]Caliptra FW RW access for survivability but cannot unlock once locked
+            [br]Caliptra Access: RW
+            [br]SOC Access:      RW
+            [br]Read-Only once locked.";
+    field {sw=rw; hw=r; swwel; resetsignal=cptra_pwrgood;} LOCK=0;
+ } CPTRA_FUSE_PAUSER_LOCK;
+
+reg {
+    name = "Caliptra WDT1 Config";
+    desc = "SOC provided count in cycles for WDT1 timeout.";
+    field {sw=rw; hw=na; resetsignal = cptra_pwrgood;} TIMEOUT[32]=0;
+ } CPTRA_WDT_CFG[2];
+
+reg {
+    name = "Caliptra iTRNG Entropy Configuration 0";
+    desc = "Adaptive threshold values for entropy source health tests.";
+    field {sw=rw; resetsignal=cptra_rst_b;} low_threshold[16]=0;
+    field {sw=rw; resetsignal=cptra_rst_b;} high_threshold[16]=0;
+ } CPTRA_iTRNG_ENTROPY_CONFIG_0;
+
+reg {
+    name = "Caliptra iTRNG Entropy Configuration 1";
+    desc = "Repetition count value for entropy source health tests.";
+    field {sw=rw; resetsignal=cptra_rst_b;} repetition_count[16]=0;
+    field {sw=rw; resetsignal=cptra_rst_b;} RSVD[16]=0;
+ } CPTRA_iTRNG_ENTROPY_CONFIG_1;
+
+reg {
+    name = "Caliptra Reserved Registers";
+    desc = "Set of reserved registers for survivability";
+    field {sw=rw; resetsignal=cptra_rst_b;} RSVD[32]=0;
+ } CPTRA_RSVD_REG[2];
\ No newline at end of file
diff --git a/src/soc_ifc/rtl/soc_ifc_fuse_reg.rdl b/src/soc_ifc/rtl/soc_ifc_fuse_reg.rdl
index f9f84ef3c..3ab2cf632 100644
--- a/src/soc_ifc/rtl/soc_ifc_fuse_reg.rdl
+++ b/src/soc_ifc/rtl/soc_ifc_fuse_reg.rdl
@@ -88,3 +88,22 @@ reg {
              [br]SOC Access:      RWL-S";
     Fuse life_cycle[2]=0;
 } fuse_life_cycle;
+reg {
+    desc = "0 - Verify Caliptra firmware images with ECDSA-only; 1 - Verify Caliptra firmware images with both ECDSA and LMS 
+             [br]Caliptra Access: RO
+             [br]SOC Access:      RWL-S";
+    Fuse lms_verify[1]=0;
+} fuse_lms_verify;
+reg {
+    desc = "Bits for revoking LMS public keys in the key manifest
+             [br]Caliptra Access: RO
+             [br]SOC Access:      RWL-S";
+    Fuse lms_revocation[32]=0;
+} fuse_lms_revocation;
+reg {
+    desc = "SOC stepping ID
+             [br]Caliptra Access: RO
+             [br]SOC Access:      RWL-S";
+    Fuse soc_stepping_id[16]=0;
+} fuse_soc_stepping_id;
+
diff --git a/src/soc_ifc/rtl/soc_ifc_internal_reg.rdl b/src/soc_ifc/rtl/soc_ifc_internal_reg.rdl
index e067d86f6..47d8b1c75 100644
--- a/src/soc_ifc/rtl/soc_ifc_internal_reg.rdl
+++ b/src/soc_ifc/rtl/soc_ifc_internal_reg.rdl
@@ -65,6 +65,93 @@ reg {
     field {desc = "NMI Vector"; hw = r; sw = rw; swwel = soc_req; resetsignal = cptra_rst_b;} vec[32] = 32'h0;
 } internal_nmi_vector;
 
+reg {
+    name = "Hardware Error Fatal Mask";
+    desc = "Bit mask for the register CPTRA_HW_ERROR_FATAL to determine
+            which bits are disabled for interrupt generation on the
+            cptra_error_fatal output signal.
+            A value of 1 in a field of this register means the corresponding bit
+            position in CPTRA_HW_ERROR_FATAL will not produce an interrupt
+            output assertion.
+            [br]Caliptra Access: RW
+            [br]SOC Access:      RO";
+    rw_ro_hw mask_iccm_ecc_unc=0;     /* Uncorrectable double-bit error in ICCM */
+    rw_ro_hw mask_dccm_ecc_unc=0;     /* Uncorrectable double-bit error in DCCM */
+    rw_ro_hw mask_nmi_pin=0;          /* Non-Maskable Interrupt due to WDT timeout */
+} internal_hw_error_fatal_mask;
+reg {
+    name = "Hardware Error Non-Fatal Mask";
+    desc = "Bit mask for the register CPTRA_HW_ERROR_NON_FATAL to determine
+            which bits are disabled for interrupt generation on the
+            cptra_error_non_fatal output signal.
+            A value of 1 in a field of this register means the corresponding bit
+            position in CPTRA_HW_ERROR_NON_FATAL will not produce an interrupt
+            output assertion.
+            [br]Caliptra Access: RW
+            [br]SOC Access:      RO";
+    rw_ro_hw mask_mbox_prot_no_lock=0; /* SOC access while not locked */
+    rw_ro_hw mask_mbox_prot_ooo=0;     /* Register access out-of-order */
+    rw_ro_hw mask_mbox_ecc_unc=0;      /* Uncorrectable double-bit error in DCCM */
+} internal_hw_error_non_fatal_mask;
+reg {
+    name = "Firmware Error Fatal Mask";
+    desc = "Bit mask for the register CPTRA_FW_ERROR_FATAL to determine
+            which bits are disabled for interrupt generation on the
+            cptra_error_fatal output signal.
+            A value of 1 in a field of this register means the corresponding bit
+            position in CPTRA_FW_ERROR_FATAL will not produce an interrupt
+            output assertion.
+            [br]Caliptra Access: RW
+            [br]SOC Access:      RO";
+    rw_ro_hw mask[32]=0; 
+} internal_fw_error_fatal_mask;
+reg {
+    name = "Firmware Error Non-Fatal Mask";
+    desc = "Bit mask for the register CPTRA_FW_ERROR_NON_FATAL to determine
+            which bits are disabled for interrupt generation on the
+            cptra_error_non_fatal output signal.
+            A value of 1 in a field of this register means the corresponding bit
+            position in CPTRA_FW_ERROR_NON_FATAL will not produce an interrupt
+            output assertion.
+            [br]Caliptra Access: RW
+            [br]SOC Access:      RO";
+    rw_ro_hw mask[32]=0; 
+} internal_fw_error_non_fatal_mask;
+
+reg {
+    name = "mtime low";
+    desc = "RISC-V Standard Machine-mode Time Counter, lower 32-bits.
+            [br]Frequency of counter is indicated in CPTRA_TIMER_CONFIG.clk_period.
+            [br]Caliptra Access: RW
+            [br]SOC Access:      RO";
+    field {desc = "Counter Low" ; sw = rw; precedence = sw; swmod = true; hw = r; swwel = soc_req; counter = true; incrvalue = 1; overflow = true; resetsignal = cptra_pwrgood;} count_l[32] = 32'h0;
+} internal_rv_mtime_l;
+
+reg {
+    name = "mtime high";
+    desc = "RISC-V Standard Machine-mode Time Counter, upper 32-bits.
+            [br]Frequency of counter is indicated in CPTRA_TIMER_CONFIG.clk_period.
+            [br]Caliptra Access: RW
+            [br]SOC Access:      RO";
+    field {desc = "Counter High"; sw = rw; precedence = sw; swmod = true; hw = r; swwel = soc_req; counter = true; incrvalue = 1;                  resetsignal = cptra_pwrgood;} count_h[32] = 32'h0;
+} internal_rv_mtime_h;
+
+reg {
+    name = "mtimecmp low";
+    desc = "RISC-V Standard Machine-mode Time Counter Compare Value, lower 32-bits.
+            [br]Caliptra Access: RW
+            [br]SOC Access:      RO";
+    field {desc = "Count Compare Low" ; sw = rw; hw = r; swwel = soc_req; resetsignal = cptra_pwrgood;} compare_l[32] = 32'h0;
+} internal_rv_mtimecmp_l;
+
+reg {
+    name = "mtimecmp high";
+    desc = "RISC-V Standard Machine-mode Time Counter Compare Value, upper 32-bits.
+            [br]Caliptra Access: RW
+            [br]SOC Access:      RO";
+    field {desc = "Count Compare High"; sw = rw; hw = r; swwel = soc_req; resetsignal = cptra_pwrgood;} compare_h[32] = 32'h0;
+} internal_rv_mtimecmp_h;
+
 
 ////////////////////////////////////////////////////////////////
 // Interrupts
@@ -123,13 +210,13 @@ regfile intr_block_t {
 
         // Specific enables for the events defined in this
         // event type in the instantiating peripheral.
-        field {desc = "Enable bit for Internal Errors";                             } error_internal_en = 1'b0;
-        field {desc = "Enable bit for Invalid Device in Pauser field";              } error_inv_dev_en  = 1'b0;
-        field {desc = "Enable bit for Failed Commands";                             } error_cmd_fail_en = 1'b0;
-        field {desc = "Enable bit for Bad Fuse received from SoC";                  } error_bad_fuse_en = 1'b0;
-        field {desc = "Enable bit for ICCM access blocked by lock";                 } error_iccm_blocked_en = 1'b0;
-        field {desc = "Enable bit for Mailbox ECC Double-bit Error (uncorrectable)";} error_mbox_ecc_unc_en = 1'b0;
-        field {desc = "Enable bit for WDT Timer1 timeout";                          } error_wdt_timer1_timeout_en = 1'b0;
+        field {desc = "Enable bit for Internal Errors";                                                            } error_internal_en = 1'b0;
+        field {desc = "Enable bit for Invalid Device in Pauser field";                                             } error_inv_dev_en  = 1'b0;
+        field {desc = "Enable bit for Failed Commands (invalid protocol or FW Fail Status)";                       } error_cmd_fail_en = 1'b0;
+        field {desc = "Enable bit for Bad Fuse received from SoC";                                                 } error_bad_fuse_en = 1'b0;
+        field {desc = "Enable bit for ICCM access blocked by lock";                                                } error_iccm_blocked_en = 1'b0;
+        field {desc = "Enable bit for Mailbox ECC Double-bit Error (uncorrectable)";                               } error_mbox_ecc_unc_en = 1'b0;
+        field {desc = "Enable bit for WDT Timer1 timeout";                                                         } error_wdt_timer1_timeout_en = 1'b0;
         field {desc = "Enable bit for WDT Timer2 timeout, applicable if timer2 is enabled as an independent timer";} error_wdt_timer2_timeout_en = 1'b0;
     };
 
@@ -146,7 +233,9 @@ regfile intr_block_t {
         field {desc = "Enable bit for Command Available";                         } notif_cmd_avail_en = 1'b0;
         field {desc = "Enable bit for Mailbox ECC Single-bit Error (correctable)";} notif_mbox_ecc_cor_en = 1'b0;
         field {desc = "Enable bit for Security State, Debug Locked transition";   } notif_debug_locked_en = 1'b0;
+        field {desc = "Enable bit for Scan mode";                                 } notif_scan_mode_en = 1'b0;
         field {desc = "Enable bit for SoC requested the mailbox while locked";    } notif_soc_req_lock_en = 1'b0;
+        field {desc = "Enable bit for Generic Input Wires Toggle";                } notif_gen_in_toggle_en = 1'b0;
     };
 
     /* ---- Error Interrupt Status ---- */
@@ -162,14 +251,14 @@ regfile intr_block_t {
         default woclr = true;
         default level intr;
 
-        field {desc = "Internal Errors status bit";                             } error_internal_sts = 1'b0;
-        field {desc = "Invalid Device in Pauser field status bit";              } error_inv_dev_sts = 1'b0;
-        field {desc = "Failed Commands status bit";                             } error_cmd_fail_sts = 1'b0;
-        field {desc = "Bad Fuse received from SoC status bit";                  } error_bad_fuse_sts = 1'b0;
-        field {desc = "ICCM access blocked by lock status bit";                 } error_iccm_blocked_sts = 1'b0;
-        field {desc = "Mailbox ECC Double-bit Error (uncorrectable) status bit";} error_mbox_ecc_unc_sts = 1'b0;
-        field {desc = "WDT Timer1 timeout status bit";                          } error_wdt_timer1_timeout_sts = 1'b0;
-        field {desc = "WDT Timer2 timeout status bit";                          } error_wdt_timer2_timeout_sts = 1'b0;
+        field {desc = "Internal Errors status bit";                                      } error_internal_sts = 1'b0;
+        field {desc = "Invalid Device in Pauser field status bit";                       } error_inv_dev_sts = 1'b0;
+        field {desc = "Failed Commands status bit (invalid protocol or FW Fail Status)"; } error_cmd_fail_sts = 1'b0;
+        field {desc = "Bad Fuse received from SoC status bit";                           } error_bad_fuse_sts = 1'b0;
+        field {desc = "ICCM access blocked by lock status bit";                          } error_iccm_blocked_sts = 1'b0;
+        field {desc = "Mailbox ECC Double-bit Error (uncorrectable) status bit";         } error_mbox_ecc_unc_sts = 1'b0;
+        field {desc = "WDT Timer1 timeout status bit";                                   } error_wdt_timer1_timeout_sts = 1'b0;
+        field {desc = "WDT Timer2 timeout status bit";                                   } error_wdt_timer2_timeout_sts = 1'b0;
     };
 
     /* ---- Notification Interrupt Status ---- */
@@ -185,10 +274,12 @@ regfile intr_block_t {
         default woclr = true;
         default level intr;
 
-        field {desc = "Command Available status bit";} notif_cmd_avail_sts = 1'b0;
+        field {desc = "Command Available status bit";                         } notif_cmd_avail_sts = 1'b0;
         field {desc = "Mailbox ECC Single-bit Error (correctable) status bit";} notif_mbox_ecc_cor_sts = 1'b0;
         field {desc = "Security State, Debug Locked transition status bit";   } notif_debug_locked_sts = 1'b0;
+        field {desc = "Scan mode status bit";                                 } notif_scan_mode_sts = 1'b0;
         field {desc = "SoC requested the mailbox while locked status bit";    } notif_soc_req_lock_sts = 1'b0;
+        field {desc = "Generic Input Wires Toggle status bit";                } notif_gen_in_toggle_sts = 1'b0;
     };
 
     /* ---- Aggregated Interrupt Status ---- */
@@ -250,7 +341,9 @@ regfile intr_block_t {
         field {desc = "Command Available trigger bit";                         } notif_cmd_avail_trig = 1'b0;
         field {desc = "Mailbox ECC Single-bit Error (correctable) trigger bit";} notif_mbox_ecc_cor_trig = 1'b0;
         field {desc = "Security State, Debug Locked transition trigger bit";   } notif_debug_locked_trig = 1'b0;
+        field {desc = "Scan mode trigger bit";                                 } notif_scan_mode_trig = 1'b0;
         field {desc = "SoC requested the mailbox while locked trigger bit";    } notif_soc_req_lock_trig = 1'b0;
+        field {desc = "Generic Input Wires Toggle trigger bit";                } notif_gen_in_toggle_trig = 1'b0;
     };
 
     /* ---- Interrupt Statistics Counter Incrementor ---- */
@@ -315,7 +408,9 @@ regfile intr_block_t {
     intr_count_t      notif_cmd_avail_intr_count_r @0x180; /* Per notification */                                    //
     intr_count_t      notif_mbox_ecc_cor_intr_count_r;     /* Per notification */                                    //
     intr_count_t      notif_debug_locked_intr_count_r;     /* Per notification */                                    //
+    intr_count_t      notif_scan_mode_intr_count_r;        /* Per notification */                                    //
     intr_count_t      notif_soc_req_lock_intr_count_r;     /* Per notification */                                    //
+    intr_count_t      notif_gen_in_toggle_intr_count_r;    /* Per notification */                                    //
                                                                                                                      //
     // These registers should be treated by SW as reserved, and ignored.                                             //
     // Offset at 0x200 gives enough space for 32 Errors and 32 Notifications                                         //
@@ -333,7 +428,9 @@ regfile intr_block_t {
     intr_count_incr_t notif_cmd_avail_intr_count_incr_r;       /* Per notification count incrementor pulse */        //
     intr_count_incr_t notif_mbox_ecc_cor_intr_count_incr_r;    /* Per notification count incrementor pulse */        //
     intr_count_incr_t notif_debug_locked_intr_count_incr_r;    /* Per notification count incrementor pulse */        //
+    intr_count_incr_t notif_scan_mode_intr_count_incr_r;       /* Per notification count incrementor pulse */        //
     intr_count_incr_t notif_soc_req_lock_intr_count_incr_r;    /* Per notification count incrementor pulse */        //
+    intr_count_incr_t notif_gen_in_toggle_intr_count_incr_r;   /* Per notification count incrementor pulse */        //
     /* ------------------------------------------------------------------------------------------------------------- */
 
     /* ---- Reset assignment for Error Events ---- */
@@ -364,10 +461,12 @@ regfile intr_block_t {
     error_internal_intr_r.error_mbox_ecc_unc_sts -> enable = error_intr_en_r.error_mbox_ecc_unc_en;
     error_internal_intr_r.error_wdt_timer1_timeout_sts -> enable = error_intr_en_r.error_wdt_timer1_timeout_en;
     error_internal_intr_r.error_wdt_timer2_timeout_sts -> enable = error_intr_en_r.error_wdt_timer2_timeout_en;
-    notif_internal_intr_r.notif_cmd_avail_sts    -> enable = notif_intr_en_r.notif_cmd_avail_en;
-    notif_internal_intr_r.notif_mbox_ecc_cor_sts -> enable = notif_intr_en_r.notif_mbox_ecc_cor_en;
-    notif_internal_intr_r.notif_debug_locked_sts -> enable = notif_intr_en_r.notif_debug_locked_en;
-    notif_internal_intr_r.notif_soc_req_lock_sts -> enable = notif_intr_en_r.notif_soc_req_lock_en;
+    notif_internal_intr_r.notif_cmd_avail_sts     -> enable = notif_intr_en_r.notif_cmd_avail_en;
+    notif_internal_intr_r.notif_mbox_ecc_cor_sts  -> enable = notif_intr_en_r.notif_mbox_ecc_cor_en;
+    notif_internal_intr_r.notif_debug_locked_sts  -> enable = notif_intr_en_r.notif_debug_locked_en;
+    notif_internal_intr_r.notif_scan_mode_sts     -> enable = notif_intr_en_r.notif_scan_mode_en;
+    notif_internal_intr_r.notif_soc_req_lock_sts  -> enable = notif_intr_en_r.notif_soc_req_lock_en;
+    notif_internal_intr_r.notif_gen_in_toggle_sts -> enable = notif_intr_en_r.notif_gen_in_toggle_en;
 
     error_internal_intr_r.error_internal_sts     -> next   = error_intr_trig_r.error_internal_trig;
     error_internal_intr_r.error_inv_dev_sts      -> next   = error_intr_trig_r.error_inv_dev_trig;
@@ -377,10 +476,12 @@ regfile intr_block_t {
     error_internal_intr_r.error_mbox_ecc_unc_sts -> next   = error_intr_trig_r.error_mbox_ecc_unc_trig;
     error_internal_intr_r.error_wdt_timer1_timeout_sts -> next   = error_intr_trig_r.error_wdt_timer1_timeout_trig;
     error_internal_intr_r.error_wdt_timer2_timeout_sts -> next   = error_intr_trig_r.error_wdt_timer2_timeout_trig;
-    notif_internal_intr_r.notif_cmd_avail_sts    -> next   = notif_intr_trig_r.notif_cmd_avail_trig;
-    notif_internal_intr_r.notif_mbox_ecc_cor_sts -> next   = notif_intr_trig_r.notif_mbox_ecc_cor_trig;
-    notif_internal_intr_r.notif_debug_locked_sts -> next   = notif_intr_trig_r.notif_debug_locked_trig;
-    notif_internal_intr_r.notif_soc_req_lock_sts -> next   = notif_intr_trig_r.notif_soc_req_lock_trig;
+    notif_internal_intr_r.notif_cmd_avail_sts     -> next   = notif_intr_trig_r.notif_cmd_avail_trig;
+    notif_internal_intr_r.notif_mbox_ecc_cor_sts  -> next   = notif_intr_trig_r.notif_mbox_ecc_cor_trig;
+    notif_internal_intr_r.notif_debug_locked_sts  -> next   = notif_intr_trig_r.notif_debug_locked_trig;
+    notif_internal_intr_r.notif_scan_mode_sts     -> next   = notif_intr_trig_r.notif_scan_mode_trig;
+    notif_internal_intr_r.notif_soc_req_lock_sts  -> next   = notif_intr_trig_r.notif_soc_req_lock_trig;
+    notif_internal_intr_r.notif_gen_in_toggle_sts -> next   = notif_intr_trig_r.notif_gen_in_toggle_trig;
 
     // NOTE: hwset for events is implicitly defined as module input
 
@@ -463,12 +564,24 @@ regfile intr_block_t {
     notif_debug_locked_intr_count_incr_r.pulse -> decr  = notif_debug_locked_intr_count_incr_r.pulse; // Auto-clear to generate pulse output
     notif_debug_locked_intr_count_r.cnt        -> incr  = notif_debug_locked_intr_count_incr_r.pulse; // Increment coincides with rising edge of interrupt sts bit
 
+    notif_scan_mode_intr_count_incr_r.pulse -> hwset = notif_internal_intr_r.notif_scan_mode_sts -> hwset; // \_____ Capture both firmware and hardware triggered events
+    notif_scan_mode_intr_count_incr_r.pulse -> next  = notif_internal_intr_r.notif_scan_mode_sts -> next;  // /      as a pulse to increment the intr_count_r register
+    notif_scan_mode_intr_count_incr_r.pulse -> we    = notif_internal_intr_r.notif_scan_mode_sts -> next;  // Generate a pulse from SW trigger, if set, or default to use the hwset input
+    notif_scan_mode_intr_count_incr_r.pulse -> decr  = notif_scan_mode_intr_count_incr_r.pulse; // Auto-clear to generate pulse output
+    notif_scan_mode_intr_count_r.cnt        -> incr  = notif_scan_mode_intr_count_incr_r.pulse; // Increment coincides with rising edge of interrupt sts bit
+
     notif_soc_req_lock_intr_count_incr_r.pulse -> hwset = notif_internal_intr_r.notif_soc_req_lock_sts -> hwset; // \_____ Capture both firmware and hardware triggered events
     notif_soc_req_lock_intr_count_incr_r.pulse -> next  = notif_internal_intr_r.notif_soc_req_lock_sts -> next;  // /      as a pulse to increment the intr_count_r register
     notif_soc_req_lock_intr_count_incr_r.pulse -> we    = notif_internal_intr_r.notif_soc_req_lock_sts -> next;  // Generate a pulse from SW trigger, if set, or default to use the hwset input
     notif_soc_req_lock_intr_count_incr_r.pulse -> decr  = notif_soc_req_lock_intr_count_incr_r.pulse; // Auto-clear to generate pulse output
     notif_soc_req_lock_intr_count_r.cnt        -> incr  = notif_soc_req_lock_intr_count_incr_r.pulse; // Increment coincides with rising edge of interrupt sts bit
 
+    notif_gen_in_toggle_intr_count_incr_r.pulse -> hwset = notif_internal_intr_r.notif_gen_in_toggle_sts -> hwset; // \_____ Capture both firmware and hardware triggered events
+    notif_gen_in_toggle_intr_count_incr_r.pulse -> next  = notif_internal_intr_r.notif_gen_in_toggle_sts -> next;  // /      as a pulse to increment the intr_count_r register
+    notif_gen_in_toggle_intr_count_incr_r.pulse -> we    = notif_internal_intr_r.notif_gen_in_toggle_sts -> next;  // Generate a pulse from SW trigger, if set, or default to use the hwset input
+    notif_gen_in_toggle_intr_count_incr_r.pulse -> decr  = notif_gen_in_toggle_intr_count_incr_r.pulse; // Auto-clear to generate pulse output
+    notif_gen_in_toggle_intr_count_r.cnt        -> incr  = notif_gen_in_toggle_intr_count_incr_r.pulse; // Increment coincides with rising edge of interrupt sts bit
+
 
 };
 
diff --git a/src/soc_ifc/rtl/soc_ifc_pkg.sv b/src/soc_ifc/rtl/soc_ifc_pkg.sv
index dcd60b425..8934bdb55 100644
--- a/src/soc_ifc/rtl/soc_ifc_pkg.sv
+++ b/src/soc_ifc/rtl/soc_ifc_pkg.sv
@@ -15,6 +15,8 @@
 `ifndef SOC_IFC_PKG
 `define SOC_IFC_PKG
 
+`include "caliptra_top_reg_defines.svh"
+
 package soc_ifc_pkg;
     
     parameter SOC_IFC_ADDR_W = 18;
@@ -22,7 +24,8 @@ package soc_ifc_pkg;
     parameter SOC_IFC_USER_W = 32;
     
     parameter MBOX_SIZE_KB = 128;
-    parameter MBOX_SIZE_BYTES = 128 * 1024;
+    parameter MBOX_SIZE_BYTES = MBOX_SIZE_KB * 1024;
+    parameter MBOX_SIZE_DWORDS = MBOX_SIZE_BYTES/4;
     parameter MBOX_DATA_W = 32;
     parameter MBOX_ECC_DATA_W = 7;
     parameter MBOX_DATA_AND_ECC_W = MBOX_DATA_W + MBOX_ECC_DATA_W;
@@ -32,15 +35,19 @@ package soc_ifc_pkg;
     parameter WDT_TIMEOUT_PERIOD_NUM_DWORDS = 2;
     parameter WDT_TIMEOUT_PERIOD_W = WDT_TIMEOUT_PERIOD_NUM_DWORDS * 32;
 
+    parameter SOC_IFC_REG_OFFSET = 32'h3000_0000;
+
     //memory map
-    parameter MBOX_DIR_START_ADDR    = 18'h0_0000;
-    parameter MBOX_DIR_END_ADDR      = 18'h1_FFFF;
-    parameter MBOX_REG_START_ADDR    = 18'h2_0000;
-    parameter MBOX_REG_END_ADDR      = 18'h2_0FFF;
-    parameter SHA_REG_START_ADDR     = 18'h2_1000;
-    parameter SHA_REG_END_ADDR       = 18'h2_1FFF;
-    parameter SOC_IFC_REG_START_ADDR = 18'h3_0000;
-    parameter SOC_IFC_REG_END_ADDR   = 18'h3_FFFF;
+    parameter MBOX_DIR_START_ADDR     = 32'h0000_0000;
+    parameter MBOX_DIR_END_ADDR       = 32'h0001_FFFF;
+    parameter MBOX_REG_START_ADDR     = `CALIPTRA_TOP_REG_MBOX_CSR_BASE_ADDR - SOC_IFC_REG_OFFSET;
+    parameter MBOX_REG_END_ADDR       = MBOX_REG_START_ADDR + 32'h0000_0FFF;
+    parameter SHA_REG_START_ADDR      = `CALIPTRA_TOP_REG_SHA512_ACC_CSR_BASE_ADDR - SOC_IFC_REG_OFFSET;
+    parameter SHA_REG_END_ADDR        = SHA_REG_START_ADDR + 32'h0000_0FFF;
+    parameter SOC_IFC_REG_START_ADDR  = `CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_BASE_ADDR - SOC_IFC_REG_OFFSET;
+    parameter SOC_IFC_REG_END_ADDR    = SOC_IFC_REG_START_ADDR + 32'h0000_FFFF;
+    parameter SOC_IFC_FUSE_START_ADDR = SOC_IFC_REG_START_ADDR + 32'h0000_0200;
+    parameter SOC_IFC_FUSE_END_ADDR   = SOC_IFC_REG_START_ADDR + 32'h0000_05FF;
 
     //Valid PAUSER
     //Lock the PAUSER values from integration time
@@ -48,6 +55,9 @@ package soc_ifc_pkg;
     parameter [4:0][31:0] CPTRA_MBOX_VALID_PAUSER = {32'h4444_4444, 32'h3333_3333, 32'h2222_2222, 32'h1111_1111, 32'h0000_0000};
     parameter [31:0] CPTRA_DEF_MBOX_VALID_PAUSER  = 32'hFFFF_FFFF;
 
+    parameter CPTRA_SET_FUSE_PAUSER_INTEG = 1'b0;
+    parameter [31:0] CPTRA_FUSE_VALID_PAUSER = 32'h0000_0000;
+
     //DMI Register encodings
     //Read only registers
     parameter DMI_REG_MBOX_DLEN = 7'h50;
@@ -60,6 +70,14 @@ package soc_ifc_pkg;
     parameter DMI_REG_CPTRA_DBG_MANUF_SERVICE_REG = 7'h60;
     parameter DMI_REG_BOOTFSM_GO = 7'h61;
     
+    // This parameter describes the hard-coded implementation in the BOOT FSM
+    // that results in noncore reset assertion being delayed from the soft reset
+    // (cptra_rst_b) by some integer number of clock cycles, due to synchronization
+    // stages and the rst window signaling.
+    // This is useful in validation environments for controlling the predicted
+    // timing in a reset event.
+    parameter SOC_IFC_CPTRA_RST_NONCORE_RST_DELAY = 4;
+
     //BOOT FSM
     typedef enum logic [2:0] {
         BOOT_IDLE   = 3'b000,
@@ -76,9 +94,20 @@ package soc_ifc_pkg;
         MBOX_RDY_FOR_DLEN = 3'b011,
         MBOX_RDY_FOR_DATA = 3'b010,
         MBOX_EXECUTE_UC   = 3'b110,
-        MBOX_EXECUTE_SOC  = 3'b100
+        MBOX_EXECUTE_SOC  = 3'b100,
+        MBOX_ERROR        = 3'b111
     } mbox_fsm_state_e;
 
+    //SHA FSM
+    typedef enum logic [2:0] {
+        SHA_IDLE    = 3'b000,
+        SHA_BLOCK_0 = 3'b001,
+        SHA_BLOCK_N = 3'b011,
+        SHA_PAD0    = 3'b010,
+        SHA_PAD1    = 3'b110,
+        SHA_DONE    = 3'b100
+      } sha_fsm_state_e;
+
     //MAILBOX Status
     typedef enum logic [3:0] {
         CMD_BUSY      = 4'd0,
@@ -112,6 +141,18 @@ package soc_ifc_pkg;
         mbox_sram_data_t rdata;
     } mbox_sram_resp_t;
 
+    typedef struct packed {
+        logic cptra_iccm_ecc_single_error;
+        logic cptra_iccm_ecc_double_error;
+        logic cptra_dccm_ecc_single_error;
+        logic cptra_dccm_ecc_double_error;
+    } rv_ecc_sts_t;
+
+    typedef struct packed {
+        logic axs_without_lock;
+        logic axs_incorrect_order;
+    } mbox_protocol_error_t;
+
     typedef enum logic [1:0] {
         DEVICE_UNPROVISIONED = 2'b00,
         DEVICE_MANUFACTURING = 2'b01,
diff --git a/src/soc_ifc/rtl/soc_ifc_reg.sv b/src/soc_ifc/rtl/soc_ifc_reg.sv
index 88e8b9e8b..c81364f56 100644
--- a/src/soc_ifc/rtl/soc_ifc_reg.sv
+++ b/src/soc_ifc/rtl/soc_ifc_reg.sv
@@ -80,6 +80,7 @@ module soc_ifc_reg (
         logic CPTRA_TRNG_VALID_PAUSER;
         logic CPTRA_TRNG_PAUSER_LOCK;
         logic [12-1:0]CPTRA_TRNG_DATA;
+        logic CPTRA_TRNG_CTRL;
         logic CPTRA_TRNG_STATUS;
         logic CPTRA_FUSE_WR_DONE;
         logic CPTRA_TIMER_CONFIG;
@@ -98,6 +99,12 @@ module soc_ifc_reg (
         logic CPTRA_WDT_TIMER2_CTRL;
         logic [2-1:0]CPTRA_WDT_TIMER2_TIMEOUT_PERIOD;
         logic CPTRA_WDT_STATUS;
+        logic CPTRA_FUSE_VALID_PAUSER;
+        logic CPTRA_FUSE_PAUSER_LOCK;
+        logic [2-1:0]CPTRA_WDT_CFG;
+        logic CPTRA_iTRNG_ENTROPY_CONFIG_0;
+        logic CPTRA_iTRNG_ENTROPY_CONFIG_1;
+        logic [2-1:0]CPTRA_RSVD_REG;
         logic [12-1:0]fuse_uds_seed;
         logic [8-1:0]fuse_field_entropy;
         logic [12-1:0]fuse_key_manifest_pk_hash;
@@ -109,11 +116,22 @@ module soc_ifc_reg (
         logic [24-1:0]fuse_idevid_cert_attr;
         logic [4-1:0]fuse_idevid_manuf_hsm_id;
         logic fuse_life_cycle;
+        logic fuse_lms_verify;
+        logic fuse_lms_revocation;
+        logic fuse_soc_stepping_id;
         logic [8-1:0]internal_obf_key;
         logic internal_iccm_lock;
         logic internal_fw_update_reset;
         logic internal_fw_update_reset_wait_cycles;
         logic internal_nmi_vector;
+        logic internal_hw_error_fatal_mask;
+        logic internal_hw_error_non_fatal_mask;
+        logic internal_fw_error_fatal_mask;
+        logic internal_fw_error_non_fatal_mask;
+        logic internal_rv_mtime_l;
+        logic internal_rv_mtime_h;
+        logic internal_rv_mtimecmp_l;
+        logic internal_rv_mtimecmp_h;
         struct packed{
             logic global_intr_en_r;
             logic error_intr_en_r;
@@ -135,7 +153,9 @@ module soc_ifc_reg (
             logic notif_cmd_avail_intr_count_r;
             logic notif_mbox_ecc_cor_intr_count_r;
             logic notif_debug_locked_intr_count_r;
+            logic notif_scan_mode_intr_count_r;
             logic notif_soc_req_lock_intr_count_r;
+            logic notif_gen_in_toggle_intr_count_r;
             logic error_internal_intr_count_incr_r;
             logic error_inv_dev_intr_count_incr_r;
             logic error_cmd_fail_intr_count_incr_r;
@@ -147,7 +167,9 @@ module soc_ifc_reg (
             logic notif_cmd_avail_intr_count_incr_r;
             logic notif_mbox_ecc_cor_intr_count_incr_r;
             logic notif_debug_locked_intr_count_incr_r;
+            logic notif_scan_mode_intr_count_incr_r;
             logic notif_soc_req_lock_intr_count_incr_r;
+            logic notif_gen_in_toggle_intr_count_incr_r;
         } intr_block_rf;
     } decoded_reg_strb_t;
     decoded_reg_strb_t decoded_reg_strb;
@@ -181,34 +203,45 @@ module soc_ifc_reg (
         for(int i0=0; i0<12; i0++) begin
             decoded_reg_strb.CPTRA_TRNG_DATA[i0] = cpuif_req_masked & (cpuif_addr == 'h78 + i0*'h4);
         end
-        decoded_reg_strb.CPTRA_TRNG_STATUS = cpuif_req_masked & (cpuif_addr == 'ha8);
-        decoded_reg_strb.CPTRA_FUSE_WR_DONE = cpuif_req_masked & (cpuif_addr == 'hac);
-        decoded_reg_strb.CPTRA_TIMER_CONFIG = cpuif_req_masked & (cpuif_addr == 'hb0);
-        decoded_reg_strb.CPTRA_BOOTFSM_GO = cpuif_req_masked & (cpuif_addr == 'hb4);
-        decoded_reg_strb.CPTRA_DBG_MANUF_SERVICE_REG = cpuif_req_masked & (cpuif_addr == 'hb8);
-        decoded_reg_strb.CPTRA_CLK_GATING_EN = cpuif_req_masked & (cpuif_addr == 'hbc);
+        decoded_reg_strb.CPTRA_TRNG_CTRL = cpuif_req_masked & (cpuif_addr == 'ha8);
+        decoded_reg_strb.CPTRA_TRNG_STATUS = cpuif_req_masked & (cpuif_addr == 'hac);
+        decoded_reg_strb.CPTRA_FUSE_WR_DONE = cpuif_req_masked & (cpuif_addr == 'hb0);
+        decoded_reg_strb.CPTRA_TIMER_CONFIG = cpuif_req_masked & (cpuif_addr == 'hb4);
+        decoded_reg_strb.CPTRA_BOOTFSM_GO = cpuif_req_masked & (cpuif_addr == 'hb8);
+        decoded_reg_strb.CPTRA_DBG_MANUF_SERVICE_REG = cpuif_req_masked & (cpuif_addr == 'hbc);
+        decoded_reg_strb.CPTRA_CLK_GATING_EN = cpuif_req_masked & (cpuif_addr == 'hc0);
         for(int i0=0; i0<2; i0++) begin
-            decoded_reg_strb.CPTRA_GENERIC_INPUT_WIRES[i0] = cpuif_req_masked & (cpuif_addr == 'hc0 + i0*'h4);
+            decoded_reg_strb.CPTRA_GENERIC_INPUT_WIRES[i0] = cpuif_req_masked & (cpuif_addr == 'hc4 + i0*'h4);
         end
         for(int i0=0; i0<2; i0++) begin
-            decoded_reg_strb.CPTRA_GENERIC_OUTPUT_WIRES[i0] = cpuif_req_masked & (cpuif_addr == 'hc8 + i0*'h4);
+            decoded_reg_strb.CPTRA_GENERIC_OUTPUT_WIRES[i0] = cpuif_req_masked & (cpuif_addr == 'hcc + i0*'h4);
         end
-        decoded_reg_strb.CPTRA_HW_REV_ID = cpuif_req_masked & (cpuif_addr == 'hd0);
+        decoded_reg_strb.CPTRA_HW_REV_ID = cpuif_req_masked & (cpuif_addr == 'hd4);
         for(int i0=0; i0<2; i0++) begin
-            decoded_reg_strb.CPTRA_FW_REV_ID[i0] = cpuif_req_masked & (cpuif_addr == 'hd4 + i0*'h4);
+            decoded_reg_strb.CPTRA_FW_REV_ID[i0] = cpuif_req_masked & (cpuif_addr == 'hd8 + i0*'h4);
         end
-        decoded_reg_strb.CPTRA_HW_CONFIG = cpuif_req_masked & (cpuif_addr == 'hdc);
-        decoded_reg_strb.CPTRA_WDT_TIMER1_EN = cpuif_req_masked & (cpuif_addr == 'he0);
-        decoded_reg_strb.CPTRA_WDT_TIMER1_CTRL = cpuif_req_masked & (cpuif_addr == 'he4);
+        decoded_reg_strb.CPTRA_HW_CONFIG = cpuif_req_masked & (cpuif_addr == 'he0);
+        decoded_reg_strb.CPTRA_WDT_TIMER1_EN = cpuif_req_masked & (cpuif_addr == 'he4);
+        decoded_reg_strb.CPTRA_WDT_TIMER1_CTRL = cpuif_req_masked & (cpuif_addr == 'he8);
         for(int i0=0; i0<2; i0++) begin
-            decoded_reg_strb.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i0] = cpuif_req_masked & (cpuif_addr == 'he8 + i0*'h4);
+            decoded_reg_strb.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i0] = cpuif_req_masked & (cpuif_addr == 'hec + i0*'h4);
         end
-        decoded_reg_strb.CPTRA_WDT_TIMER2_EN = cpuif_req_masked & (cpuif_addr == 'hf0);
-        decoded_reg_strb.CPTRA_WDT_TIMER2_CTRL = cpuif_req_masked & (cpuif_addr == 'hf4);
+        decoded_reg_strb.CPTRA_WDT_TIMER2_EN = cpuif_req_masked & (cpuif_addr == 'hf4);
+        decoded_reg_strb.CPTRA_WDT_TIMER2_CTRL = cpuif_req_masked & (cpuif_addr == 'hf8);
         for(int i0=0; i0<2; i0++) begin
-            decoded_reg_strb.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i0] = cpuif_req_masked & (cpuif_addr == 'hf8 + i0*'h4);
+            decoded_reg_strb.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i0] = cpuif_req_masked & (cpuif_addr == 'hfc + i0*'h4);
+        end
+        decoded_reg_strb.CPTRA_WDT_STATUS = cpuif_req_masked & (cpuif_addr == 'h104);
+        decoded_reg_strb.CPTRA_FUSE_VALID_PAUSER = cpuif_req_masked & (cpuif_addr == 'h108);
+        decoded_reg_strb.CPTRA_FUSE_PAUSER_LOCK = cpuif_req_masked & (cpuif_addr == 'h10c);
+        for(int i0=0; i0<2; i0++) begin
+            decoded_reg_strb.CPTRA_WDT_CFG[i0] = cpuif_req_masked & (cpuif_addr == 'h110 + i0*'h4);
+        end
+        decoded_reg_strb.CPTRA_iTRNG_ENTROPY_CONFIG_0 = cpuif_req_masked & (cpuif_addr == 'h118);
+        decoded_reg_strb.CPTRA_iTRNG_ENTROPY_CONFIG_1 = cpuif_req_masked & (cpuif_addr == 'h11c);
+        for(int i0=0; i0<2; i0++) begin
+            decoded_reg_strb.CPTRA_RSVD_REG[i0] = cpuif_req_masked & (cpuif_addr == 'h120 + i0*'h4);
         end
-        decoded_reg_strb.CPTRA_WDT_STATUS = cpuif_req_masked & (cpuif_addr == 'h100);
         for(int i0=0; i0<12; i0++) begin
             decoded_reg_strb.fuse_uds_seed[i0] = cpuif_req_masked & (cpuif_addr == 'h200 + i0*'h4);
         end
@@ -234,6 +267,9 @@ module soc_ifc_reg (
             decoded_reg_strb.fuse_idevid_manuf_hsm_id[i0] = cpuif_req_masked & (cpuif_addr == 'h32c + i0*'h4);
         end
         decoded_reg_strb.fuse_life_cycle = cpuif_req_masked & (cpuif_addr == 'h33c);
+        decoded_reg_strb.fuse_lms_verify = cpuif_req_masked & (cpuif_addr == 'h340);
+        decoded_reg_strb.fuse_lms_revocation = cpuif_req_masked & (cpuif_addr == 'h344);
+        decoded_reg_strb.fuse_soc_stepping_id = cpuif_req_masked & (cpuif_addr == 'h348);
         for(int i0=0; i0<8; i0++) begin
             decoded_reg_strb.internal_obf_key[i0] = cpuif_req_masked & (cpuif_addr == 'h600 + i0*'h4);
         end
@@ -241,6 +277,14 @@ module soc_ifc_reg (
         decoded_reg_strb.internal_fw_update_reset = cpuif_req_masked & (cpuif_addr == 'h624);
         decoded_reg_strb.internal_fw_update_reset_wait_cycles = cpuif_req_masked & (cpuif_addr == 'h628);
         decoded_reg_strb.internal_nmi_vector = cpuif_req_masked & (cpuif_addr == 'h62c);
+        decoded_reg_strb.internal_hw_error_fatal_mask = cpuif_req_masked & (cpuif_addr == 'h630);
+        decoded_reg_strb.internal_hw_error_non_fatal_mask = cpuif_req_masked & (cpuif_addr == 'h634);
+        decoded_reg_strb.internal_fw_error_fatal_mask = cpuif_req_masked & (cpuif_addr == 'h638);
+        decoded_reg_strb.internal_fw_error_non_fatal_mask = cpuif_req_masked & (cpuif_addr == 'h63c);
+        decoded_reg_strb.internal_rv_mtime_l = cpuif_req_masked & (cpuif_addr == 'h640);
+        decoded_reg_strb.internal_rv_mtime_h = cpuif_req_masked & (cpuif_addr == 'h644);
+        decoded_reg_strb.internal_rv_mtimecmp_l = cpuif_req_masked & (cpuif_addr == 'h648);
+        decoded_reg_strb.internal_rv_mtimecmp_h = cpuif_req_masked & (cpuif_addr == 'h64c);
         decoded_reg_strb.intr_block_rf.global_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h800);
         decoded_reg_strb.intr_block_rf.error_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h804);
         decoded_reg_strb.intr_block_rf.notif_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h808);
@@ -261,7 +305,9 @@ module soc_ifc_reg (
         decoded_reg_strb.intr_block_rf.notif_cmd_avail_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h980);
         decoded_reg_strb.intr_block_rf.notif_mbox_ecc_cor_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h984);
         decoded_reg_strb.intr_block_rf.notif_debug_locked_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h988);
-        decoded_reg_strb.intr_block_rf.notif_soc_req_lock_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h98c);
+        decoded_reg_strb.intr_block_rf.notif_scan_mode_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h98c);
+        decoded_reg_strb.intr_block_rf.notif_soc_req_lock_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h990);
+        decoded_reg_strb.intr_block_rf.notif_gen_in_toggle_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h994);
         decoded_reg_strb.intr_block_rf.error_internal_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha00);
         decoded_reg_strb.intr_block_rf.error_inv_dev_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha04);
         decoded_reg_strb.intr_block_rf.error_cmd_fail_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha08);
@@ -273,7 +319,9 @@ module soc_ifc_reg (
         decoded_reg_strb.intr_block_rf.notif_cmd_avail_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha20);
         decoded_reg_strb.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha24);
         decoded_reg_strb.intr_block_rf.notif_debug_locked_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha28);
-        decoded_reg_strb.intr_block_rf.notif_soc_req_lock_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha2c);
+        decoded_reg_strb.intr_block_rf.notif_scan_mode_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha2c);
+        decoded_reg_strb.intr_block_rf.notif_soc_req_lock_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha30);
+        decoded_reg_strb.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha34);
     end
 
     // Pass down signals to next stage
@@ -292,15 +340,31 @@ module soc_ifc_reg (
     typedef struct packed{
         struct packed{
             struct packed{
-                logic [31:0] next;
+                logic next;
                 logic load_next;
-            } error_code;
+            } iccm_ecc_unc;
+            struct packed{
+                logic next;
+                logic load_next;
+            } dccm_ecc_unc;
+            struct packed{
+                logic next;
+                logic load_next;
+            } nmi_pin;
         } CPTRA_HW_ERROR_FATAL;
         struct packed{
             struct packed{
-                logic [31:0] next;
+                logic next;
                 logic load_next;
-            } error_code;
+            } mbox_prot_no_lock;
+            struct packed{
+                logic next;
+                logic load_next;
+            } mbox_prot_ooo;
+            struct packed{
+                logic next;
+                logic load_next;
+            } mbox_ecc_unc;
         } CPTRA_HW_ERROR_NON_FATAL;
         struct packed{
             struct packed{
@@ -340,21 +404,21 @@ module soc_ifc_reg (
         } CPTRA_BOOT_STATUS;
         struct packed{
             struct packed{
-                logic [27:0] next;
+                logic [23:0] next;
                 logic load_next;
             } status;
             struct packed{
                 logic next;
                 logic load_next;
-            } ready_for_fw;
+            } idevid_csr_ready;
             struct packed{
                 logic next;
                 logic load_next;
-            } ready_for_runtime;
+            } ready_for_fw;
             struct packed{
                 logic next;
                 logic load_next;
-            } ready_for_fuses;
+            } ready_for_runtime;
             struct packed{
                 logic next;
                 logic load_next;
@@ -400,6 +464,12 @@ module soc_ifc_reg (
                 logic load_next;
             } DATA;
         } [12-1:0]CPTRA_TRNG_DATA;
+        struct packed{
+            struct packed{
+                logic next;
+                logic load_next;
+            } clear;
+        } CPTRA_TRNG_CTRL;
         struct packed{
             struct packed{
                 logic next;
@@ -504,6 +574,50 @@ module soc_ifc_reg (
                 logic load_next;
             } t2_timeout;
         } CPTRA_WDT_STATUS;
+        struct packed{
+            struct packed{
+                logic [31:0] next;
+                logic load_next;
+            } PAUSER;
+        } CPTRA_FUSE_VALID_PAUSER;
+        struct packed{
+            struct packed{
+                logic next;
+                logic load_next;
+            } LOCK;
+        } CPTRA_FUSE_PAUSER_LOCK;
+        struct packed{
+            struct packed{
+                logic [31:0] next;
+                logic load_next;
+            } TIMEOUT;
+        } [2-1:0]CPTRA_WDT_CFG;
+        struct packed{
+            struct packed{
+                logic [15:0] next;
+                logic load_next;
+            } low_threshold;
+            struct packed{
+                logic [15:0] next;
+                logic load_next;
+            } high_threshold;
+        } CPTRA_iTRNG_ENTROPY_CONFIG_0;
+        struct packed{
+            struct packed{
+                logic [15:0] next;
+                logic load_next;
+            } repetition_count;
+            struct packed{
+                logic [15:0] next;
+                logic load_next;
+            } RSVD;
+        } CPTRA_iTRNG_ENTROPY_CONFIG_1;
+        struct packed{
+            struct packed{
+                logic [31:0] next;
+                logic load_next;
+            } RSVD;
+        } [2-1:0]CPTRA_RSVD_REG;
         struct packed{
             struct packed{
                 logic [31:0] next;
@@ -570,6 +684,24 @@ module soc_ifc_reg (
                 logic load_next;
             } life_cycle;
         } fuse_life_cycle;
+        struct packed{
+            struct packed{
+                logic next;
+                logic load_next;
+            } lms_verify;
+        } fuse_lms_verify;
+        struct packed{
+            struct packed{
+                logic [31:0] next;
+                logic load_next;
+            } lms_revocation;
+        } fuse_lms_revocation;
+        struct packed{
+            struct packed{
+                logic [15:0] next;
+                logic load_next;
+            } soc_stepping_id;
+        } fuse_soc_stepping_id;
         struct packed{
             struct packed{
                 logic [31:0] next;
@@ -600,6 +732,74 @@ module soc_ifc_reg (
                 logic load_next;
             } vec;
         } internal_nmi_vector;
+        struct packed{
+            struct packed{
+                logic next;
+                logic load_next;
+            } mask_iccm_ecc_unc;
+            struct packed{
+                logic next;
+                logic load_next;
+            } mask_dccm_ecc_unc;
+            struct packed{
+                logic next;
+                logic load_next;
+            } mask_nmi_pin;
+        } internal_hw_error_fatal_mask;
+        struct packed{
+            struct packed{
+                logic next;
+                logic load_next;
+            } mask_mbox_prot_no_lock;
+            struct packed{
+                logic next;
+                logic load_next;
+            } mask_mbox_prot_ooo;
+            struct packed{
+                logic next;
+                logic load_next;
+            } mask_mbox_ecc_unc;
+        } internal_hw_error_non_fatal_mask;
+        struct packed{
+            struct packed{
+                logic [31:0] next;
+                logic load_next;
+            } mask;
+        } internal_fw_error_fatal_mask;
+        struct packed{
+            struct packed{
+                logic [31:0] next;
+                logic load_next;
+            } mask;
+        } internal_fw_error_non_fatal_mask;
+        struct packed{
+            struct packed{
+                logic [31:0] next;
+                logic load_next;
+                logic incrthreshold;
+                logic overflow;
+            } count_l;
+        } internal_rv_mtime_l;
+        struct packed{
+            struct packed{
+                logic [31:0] next;
+                logic load_next;
+                logic incrthreshold;
+                logic overflow;
+            } count_h;
+        } internal_rv_mtime_h;
+        struct packed{
+            struct packed{
+                logic [31:0] next;
+                logic load_next;
+            } compare_l;
+        } internal_rv_mtimecmp_l;
+        struct packed{
+            struct packed{
+                logic [31:0] next;
+                logic load_next;
+            } compare_h;
+        } internal_rv_mtimecmp_h;
         struct packed{
             struct packed{
                 struct packed{
@@ -658,10 +858,18 @@ module soc_ifc_reg (
                     logic next;
                     logic load_next;
                 } notif_debug_locked_en;
+                struct packed{
+                    logic next;
+                    logic load_next;
+                } notif_scan_mode_en;
                 struct packed{
                     logic next;
                     logic load_next;
                 } notif_soc_req_lock_en;
+                struct packed{
+                    logic next;
+                    logic load_next;
+                } notif_gen_in_toggle_en;
             } notif_intr_en_r;
             struct packed{
                 struct packed{
@@ -722,10 +930,18 @@ module soc_ifc_reg (
                     logic next;
                     logic load_next;
                 } notif_debug_locked_sts;
+                struct packed{
+                    logic next;
+                    logic load_next;
+                } notif_scan_mode_sts;
                 struct packed{
                     logic next;
                     logic load_next;
                 } notif_soc_req_lock_sts;
+                struct packed{
+                    logic next;
+                    logic load_next;
+                } notif_gen_in_toggle_sts;
             } notif_internal_intr_r;
             struct packed{
                 struct packed{
@@ -774,10 +990,18 @@ module soc_ifc_reg (
                     logic next;
                     logic load_next;
                 } notif_debug_locked_trig;
+                struct packed{
+                    logic next;
+                    logic load_next;
+                } notif_scan_mode_trig;
                 struct packed{
                     logic next;
                     logic load_next;
                 } notif_soc_req_lock_trig;
+                struct packed{
+                    logic next;
+                    logic load_next;
+                } notif_gen_in_toggle_trig;
             } notif_intr_trig_r;
             struct packed{
                 struct packed{
@@ -867,6 +1091,14 @@ module soc_ifc_reg (
                     logic incrsaturate;
                 } cnt;
             } notif_debug_locked_intr_count_r;
+            struct packed{
+                struct packed{
+                    logic [31:0] next;
+                    logic load_next;
+                    logic incrthreshold;
+                    logic incrsaturate;
+                } cnt;
+            } notif_scan_mode_intr_count_r;
             struct packed{
                 struct packed{
                     logic [31:0] next;
@@ -875,6 +1107,14 @@ module soc_ifc_reg (
                     logic incrsaturate;
                 } cnt;
             } notif_soc_req_lock_intr_count_r;
+            struct packed{
+                struct packed{
+                    logic [31:0] next;
+                    logic load_next;
+                    logic incrthreshold;
+                    logic incrsaturate;
+                } cnt;
+            } notif_gen_in_toggle_intr_count_r;
             struct packed{
                 struct packed{
                     logic next;
@@ -963,6 +1203,14 @@ module soc_ifc_reg (
                     logic underflow;
                 } pulse;
             } notif_debug_locked_intr_count_incr_r;
+            struct packed{
+                struct packed{
+                    logic next;
+                    logic load_next;
+                    logic decrthreshold;
+                    logic underflow;
+                } pulse;
+            } notif_scan_mode_intr_count_incr_r;
             struct packed{
                 struct packed{
                     logic next;
@@ -971,6 +1219,14 @@ module soc_ifc_reg (
                     logic underflow;
                 } pulse;
             } notif_soc_req_lock_intr_count_incr_r;
+            struct packed{
+                struct packed{
+                    logic next;
+                    logic load_next;
+                    logic decrthreshold;
+                    logic underflow;
+                } pulse;
+            } notif_gen_in_toggle_intr_count_incr_r;
         } intr_block_rf;
     } field_combo_t;
     field_combo_t field_combo;
@@ -978,13 +1234,25 @@ module soc_ifc_reg (
     typedef struct packed{
         struct packed{
             struct packed{
-                logic [31:0] value;
-            } error_code;
+                logic value;
+            } iccm_ecc_unc;
+            struct packed{
+                logic value;
+            } dccm_ecc_unc;
+            struct packed{
+                logic value;
+            } nmi_pin;
         } CPTRA_HW_ERROR_FATAL;
         struct packed{
             struct packed{
-                logic [31:0] value;
-            } error_code;
+                logic value;
+            } mbox_prot_no_lock;
+            struct packed{
+                logic value;
+            } mbox_prot_ooo;
+            struct packed{
+                logic value;
+            } mbox_ecc_unc;
         } CPTRA_HW_ERROR_NON_FATAL;
         struct packed{
             struct packed{
@@ -1018,17 +1286,17 @@ module soc_ifc_reg (
         } CPTRA_BOOT_STATUS;
         struct packed{
             struct packed{
-                logic [27:0] value;
+                logic [23:0] value;
             } status;
             struct packed{
                 logic value;
-            } ready_for_fw;
+            } idevid_csr_ready;
             struct packed{
                 logic value;
-            } ready_for_runtime;
+            } ready_for_fw;
             struct packed{
                 logic value;
-            } ready_for_fuses;
+            } ready_for_runtime;
             struct packed{
                 logic value;
             } mailbox_flow_done;
@@ -1066,6 +1334,11 @@ module soc_ifc_reg (
                 logic [31:0] value;
             } DATA;
         } [12-1:0]CPTRA_TRNG_DATA;
+        struct packed{
+            struct packed{
+                logic value;
+            } clear;
+        } CPTRA_TRNG_CTRL;
         struct packed{
             struct packed{
                 logic value;
@@ -1152,6 +1425,42 @@ module soc_ifc_reg (
                 logic value;
             } t2_timeout;
         } CPTRA_WDT_STATUS;
+        struct packed{
+            struct packed{
+                logic [31:0] value;
+            } PAUSER;
+        } CPTRA_FUSE_VALID_PAUSER;
+        struct packed{
+            struct packed{
+                logic value;
+            } LOCK;
+        } CPTRA_FUSE_PAUSER_LOCK;
+        struct packed{
+            struct packed{
+                logic [31:0] value;
+            } TIMEOUT;
+        } [2-1:0]CPTRA_WDT_CFG;
+        struct packed{
+            struct packed{
+                logic [15:0] value;
+            } low_threshold;
+            struct packed{
+                logic [15:0] value;
+            } high_threshold;
+        } CPTRA_iTRNG_ENTROPY_CONFIG_0;
+        struct packed{
+            struct packed{
+                logic [15:0] value;
+            } repetition_count;
+            struct packed{
+                logic [15:0] value;
+            } RSVD;
+        } CPTRA_iTRNG_ENTROPY_CONFIG_1;
+        struct packed{
+            struct packed{
+                logic [31:0] value;
+            } RSVD;
+        } [2-1:0]CPTRA_RSVD_REG;
         struct packed{
             struct packed{
                 logic [31:0] value;
@@ -1207,6 +1516,21 @@ module soc_ifc_reg (
                 logic [1:0] value;
             } life_cycle;
         } fuse_life_cycle;
+        struct packed{
+            struct packed{
+                logic value;
+            } lms_verify;
+        } fuse_lms_verify;
+        struct packed{
+            struct packed{
+                logic [31:0] value;
+            } lms_revocation;
+        } fuse_lms_revocation;
+        struct packed{
+            struct packed{
+                logic [15:0] value;
+            } soc_stepping_id;
+        } fuse_soc_stepping_id;
         struct packed{
             struct packed{
                 logic [31:0] value;
@@ -1232,6 +1556,58 @@ module soc_ifc_reg (
                 logic [31:0] value;
             } vec;
         } internal_nmi_vector;
+        struct packed{
+            struct packed{
+                logic value;
+            } mask_iccm_ecc_unc;
+            struct packed{
+                logic value;
+            } mask_dccm_ecc_unc;
+            struct packed{
+                logic value;
+            } mask_nmi_pin;
+        } internal_hw_error_fatal_mask;
+        struct packed{
+            struct packed{
+                logic value;
+            } mask_mbox_prot_no_lock;
+            struct packed{
+                logic value;
+            } mask_mbox_prot_ooo;
+            struct packed{
+                logic value;
+            } mask_mbox_ecc_unc;
+        } internal_hw_error_non_fatal_mask;
+        struct packed{
+            struct packed{
+                logic [31:0] value;
+            } mask;
+        } internal_fw_error_fatal_mask;
+        struct packed{
+            struct packed{
+                logic [31:0] value;
+            } mask;
+        } internal_fw_error_non_fatal_mask;
+        struct packed{
+            struct packed{
+                logic [31:0] value;
+            } count_l;
+        } internal_rv_mtime_l;
+        struct packed{
+            struct packed{
+                logic [31:0] value;
+            } count_h;
+        } internal_rv_mtime_h;
+        struct packed{
+            struct packed{
+                logic [31:0] value;
+            } compare_l;
+        } internal_rv_mtimecmp_l;
+        struct packed{
+            struct packed{
+                logic [31:0] value;
+            } compare_h;
+        } internal_rv_mtimecmp_h;
         struct packed{
             struct packed{
                 struct packed{
@@ -1277,9 +1653,15 @@ module soc_ifc_reg (
                 struct packed{
                     logic value;
                 } notif_debug_locked_en;
+                struct packed{
+                    logic value;
+                } notif_scan_mode_en;
                 struct packed{
                     logic value;
                 } notif_soc_req_lock_en;
+                struct packed{
+                    logic value;
+                } notif_gen_in_toggle_en;
             } notif_intr_en_r;
             struct packed{
                 struct packed{
@@ -1327,9 +1709,15 @@ module soc_ifc_reg (
                 struct packed{
                     logic value;
                 } notif_debug_locked_sts;
+                struct packed{
+                    logic value;
+                } notif_scan_mode_sts;
                 struct packed{
                     logic value;
                 } notif_soc_req_lock_sts;
+                struct packed{
+                    logic value;
+                } notif_gen_in_toggle_sts;
             } notif_internal_intr_r;
             struct packed{
                 struct packed{
@@ -1367,9 +1755,15 @@ module soc_ifc_reg (
                 struct packed{
                     logic value;
                 } notif_debug_locked_trig;
+                struct packed{
+                    logic value;
+                } notif_scan_mode_trig;
                 struct packed{
                     logic value;
                 } notif_soc_req_lock_trig;
+                struct packed{
+                    logic value;
+                } notif_gen_in_toggle_trig;
             } notif_intr_trig_r;
             struct packed{
                 struct packed{
@@ -1426,11 +1820,21 @@ module soc_ifc_reg (
                     logic [31:0] value;
                 } cnt;
             } notif_debug_locked_intr_count_r;
+            struct packed{
+                struct packed{
+                    logic [31:0] value;
+                } cnt;
+            } notif_scan_mode_intr_count_r;
             struct packed{
                 struct packed{
                     logic [31:0] value;
                 } cnt;
             } notif_soc_req_lock_intr_count_r;
+            struct packed{
+                struct packed{
+                    logic [31:0] value;
+                } cnt;
+            } notif_gen_in_toggle_intr_count_r;
             struct packed{
                 struct packed{
                     logic value;
@@ -1486,59 +1890,157 @@ module soc_ifc_reg (
                     logic value;
                 } pulse;
             } notif_debug_locked_intr_count_incr_r;
+            struct packed{
+                struct packed{
+                    logic value;
+                } pulse;
+            } notif_scan_mode_intr_count_incr_r;
             struct packed{
                 struct packed{
                     logic value;
                 } pulse;
             } notif_soc_req_lock_intr_count_incr_r;
+            struct packed{
+                struct packed{
+                    logic value;
+                } pulse;
+            } notif_gen_in_toggle_intr_count_incr_r;
         } intr_block_rf;
     } field_storage_t;
     field_storage_t field_storage;
 
-    // Field: soc_ifc_reg.CPTRA_HW_ERROR_FATAL.error_code
+    // Field: soc_ifc_reg.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc
     always_comb begin
-        automatic logic [31:0] next_c = field_storage.CPTRA_HW_ERROR_FATAL.error_code.value;
+        automatic logic [0:0] next_c = field_storage.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.value;
         automatic logic load_next_c = '0;
         if(decoded_reg_strb.CPTRA_HW_ERROR_FATAL && decoded_req_is_wr) begin // SW write 1 clear
-            next_c = field_storage.CPTRA_HW_ERROR_FATAL.error_code.value & ~(decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+            next_c = field_storage.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.value & ~(decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
+            load_next_c = '1;
+        end else if(hwif_in.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.we) begin // HW Write - we
+            next_c = hwif_in.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.next;
+            load_next_c = '1;
+        end
+        field_combo.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.next = next_c;
+        field_combo.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.load_next = load_next_c;
+    end
+    always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
+        if(~hwif_in.cptra_pwrgood) begin
+            field_storage.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.value <= 'h0;
+        end else if(field_combo.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.load_next) begin
+            field_storage.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.value <= field_combo.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.next;
+        end
+    end
+    assign hwif_out.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.value = field_storage.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.value;
+    // Field: soc_ifc_reg.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc
+    always_comb begin
+        automatic logic [0:0] next_c = field_storage.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.value;
+        automatic logic load_next_c = '0;
+        if(decoded_reg_strb.CPTRA_HW_ERROR_FATAL && decoded_req_is_wr) begin // SW write 1 clear
+            next_c = field_storage.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.value & ~(decoded_wr_data[1:1] & decoded_wr_biten[1:1]);
+            load_next_c = '1;
+        end else if(hwif_in.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.we) begin // HW Write - we
+            next_c = hwif_in.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.next;
+            load_next_c = '1;
+        end
+        field_combo.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.next = next_c;
+        field_combo.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.load_next = load_next_c;
+    end
+    always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
+        if(~hwif_in.cptra_pwrgood) begin
+            field_storage.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.value <= 'h0;
+        end else if(field_combo.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.load_next) begin
+            field_storage.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.value <= field_combo.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.next;
+        end
+    end
+    assign hwif_out.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.value = field_storage.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.value;
+    // Field: soc_ifc_reg.CPTRA_HW_ERROR_FATAL.nmi_pin
+    always_comb begin
+        automatic logic [0:0] next_c = field_storage.CPTRA_HW_ERROR_FATAL.nmi_pin.value;
+        automatic logic load_next_c = '0;
+        if(decoded_reg_strb.CPTRA_HW_ERROR_FATAL && decoded_req_is_wr) begin // SW write 1 clear
+            next_c = field_storage.CPTRA_HW_ERROR_FATAL.nmi_pin.value & ~(decoded_wr_data[2:2] & decoded_wr_biten[2:2]);
+            load_next_c = '1;
+        end else if(hwif_in.CPTRA_HW_ERROR_FATAL.nmi_pin.we) begin // HW Write - we
+            next_c = hwif_in.CPTRA_HW_ERROR_FATAL.nmi_pin.next;
+            load_next_c = '1;
+        end
+        field_combo.CPTRA_HW_ERROR_FATAL.nmi_pin.next = next_c;
+        field_combo.CPTRA_HW_ERROR_FATAL.nmi_pin.load_next = load_next_c;
+    end
+    always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
+        if(~hwif_in.cptra_pwrgood) begin
+            field_storage.CPTRA_HW_ERROR_FATAL.nmi_pin.value <= 'h0;
+        end else if(field_combo.CPTRA_HW_ERROR_FATAL.nmi_pin.load_next) begin
+            field_storage.CPTRA_HW_ERROR_FATAL.nmi_pin.value <= field_combo.CPTRA_HW_ERROR_FATAL.nmi_pin.next;
+        end
+    end
+    assign hwif_out.CPTRA_HW_ERROR_FATAL.nmi_pin.value = field_storage.CPTRA_HW_ERROR_FATAL.nmi_pin.value;
+    // Field: soc_ifc_reg.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock
+    always_comb begin
+        automatic logic [0:0] next_c = field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.value;
+        automatic logic load_next_c = '0;
+        if(decoded_reg_strb.CPTRA_HW_ERROR_NON_FATAL && decoded_req_is_wr) begin // SW write 1 clear
+            next_c = field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.value & ~(decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
+            load_next_c = '1;
+        end else if(hwif_in.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.we) begin // HW Write - we
+            next_c = hwif_in.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.next;
+            load_next_c = '1;
+        end
+        field_combo.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.next = next_c;
+        field_combo.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.load_next = load_next_c;
+    end
+    always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
+        if(~hwif_in.cptra_pwrgood) begin
+            field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.value <= 'h0;
+        end else if(field_combo.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.load_next) begin
+            field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.value <= field_combo.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.next;
+        end
+    end
+    assign hwif_out.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.value = field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.value;
+    // Field: soc_ifc_reg.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo
+    always_comb begin
+        automatic logic [0:0] next_c = field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo.value;
+        automatic logic load_next_c = '0;
+        if(decoded_reg_strb.CPTRA_HW_ERROR_NON_FATAL && decoded_req_is_wr) begin // SW write 1 clear
+            next_c = field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo.value & ~(decoded_wr_data[1:1] & decoded_wr_biten[1:1]);
             load_next_c = '1;
-        end else if(hwif_in.CPTRA_HW_ERROR_FATAL.error_code.we) begin // HW Write - we
-            next_c = hwif_in.CPTRA_HW_ERROR_FATAL.error_code.next;
+        end else if(hwif_in.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo.we) begin // HW Write - we
+            next_c = hwif_in.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo.next;
             load_next_c = '1;
         end
-        field_combo.CPTRA_HW_ERROR_FATAL.error_code.next = next_c;
-        field_combo.CPTRA_HW_ERROR_FATAL.error_code.load_next = load_next_c;
+        field_combo.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo.next = next_c;
+        field_combo.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo.load_next = load_next_c;
     end
     always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
         if(~hwif_in.cptra_pwrgood) begin
-            field_storage.CPTRA_HW_ERROR_FATAL.error_code.value <= 'h0;
-        end else if(field_combo.CPTRA_HW_ERROR_FATAL.error_code.load_next) begin
-            field_storage.CPTRA_HW_ERROR_FATAL.error_code.value <= field_combo.CPTRA_HW_ERROR_FATAL.error_code.next;
+            field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo.value <= 'h0;
+        end else if(field_combo.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo.load_next) begin
+            field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo.value <= field_combo.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo.next;
         end
     end
-    assign hwif_out.CPTRA_HW_ERROR_FATAL.error_code.value = field_storage.CPTRA_HW_ERROR_FATAL.error_code.value;
-    // Field: soc_ifc_reg.CPTRA_HW_ERROR_NON_FATAL.error_code
+    assign hwif_out.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo.value = field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo.value;
+    // Field: soc_ifc_reg.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc
     always_comb begin
-        automatic logic [31:0] next_c = field_storage.CPTRA_HW_ERROR_NON_FATAL.error_code.value;
+        automatic logic [0:0] next_c = field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc.value;
         automatic logic load_next_c = '0;
         if(decoded_reg_strb.CPTRA_HW_ERROR_NON_FATAL && decoded_req_is_wr) begin // SW write 1 clear
-            next_c = field_storage.CPTRA_HW_ERROR_NON_FATAL.error_code.value & ~(decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+            next_c = field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc.value & ~(decoded_wr_data[2:2] & decoded_wr_biten[2:2]);
             load_next_c = '1;
-        end else if(hwif_in.CPTRA_HW_ERROR_NON_FATAL.error_code.we) begin // HW Write - we
-            next_c = hwif_in.CPTRA_HW_ERROR_NON_FATAL.error_code.next;
+        end else if(hwif_in.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc.we) begin // HW Write - we
+            next_c = hwif_in.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc.next;
             load_next_c = '1;
         end
-        field_combo.CPTRA_HW_ERROR_NON_FATAL.error_code.next = next_c;
-        field_combo.CPTRA_HW_ERROR_NON_FATAL.error_code.load_next = load_next_c;
+        field_combo.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc.next = next_c;
+        field_combo.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc.load_next = load_next_c;
     end
     always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
         if(~hwif_in.cptra_pwrgood) begin
-            field_storage.CPTRA_HW_ERROR_NON_FATAL.error_code.value <= 'h0;
-        end else if(field_combo.CPTRA_HW_ERROR_NON_FATAL.error_code.load_next) begin
-            field_storage.CPTRA_HW_ERROR_NON_FATAL.error_code.value <= field_combo.CPTRA_HW_ERROR_NON_FATAL.error_code.next;
+            field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc.value <= 'h0;
+        end else if(field_combo.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc.load_next) begin
+            field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc.value <= field_combo.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc.next;
         end
     end
-    assign hwif_out.CPTRA_HW_ERROR_NON_FATAL.error_code.value = field_storage.CPTRA_HW_ERROR_NON_FATAL.error_code.value;
+    assign hwif_out.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc.value = field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc.value;
     // Field: soc_ifc_reg.CPTRA_FW_ERROR_FATAL.error_code
     always_comb begin
         automatic logic [31:0] next_c = field_storage.CPTRA_FW_ERROR_FATAL.error_code.value;
@@ -1561,6 +2063,7 @@ module soc_ifc_reg (
         end
     end
     assign hwif_out.CPTRA_FW_ERROR_FATAL.error_code.value = field_storage.CPTRA_FW_ERROR_FATAL.error_code.value;
+    assign hwif_out.CPTRA_FW_ERROR_FATAL.error_code.swmod = decoded_reg_strb.CPTRA_FW_ERROR_FATAL && decoded_req_is_wr;
     // Field: soc_ifc_reg.CPTRA_FW_ERROR_NON_FATAL.error_code
     always_comb begin
         automatic logic [31:0] next_c = field_storage.CPTRA_FW_ERROR_NON_FATAL.error_code.value;
@@ -1583,6 +2086,7 @@ module soc_ifc_reg (
         end
     end
     assign hwif_out.CPTRA_FW_ERROR_NON_FATAL.error_code.value = field_storage.CPTRA_FW_ERROR_NON_FATAL.error_code.value;
+    assign hwif_out.CPTRA_FW_ERROR_NON_FATAL.error_code.swmod = decoded_reg_strb.CPTRA_FW_ERROR_NON_FATAL && decoded_req_is_wr;
     // Field: soc_ifc_reg.CPTRA_HW_ERROR_ENC.error_code
     always_comb begin
         automatic logic [31:0] next_c = field_storage.CPTRA_HW_ERROR_ENC.error_code.value;
@@ -1663,10 +2167,10 @@ module soc_ifc_reg (
     assign hwif_out.CPTRA_BOOT_STATUS.status.value = field_storage.CPTRA_BOOT_STATUS.status.value;
     // Field: soc_ifc_reg.CPTRA_FLOW_STATUS.status
     always_comb begin
-        automatic logic [27:0] next_c = field_storage.CPTRA_FLOW_STATUS.status.value;
+        automatic logic [23:0] next_c = field_storage.CPTRA_FLOW_STATUS.status.value;
         automatic logic load_next_c = '0;
         if(decoded_reg_strb.CPTRA_FLOW_STATUS && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write
-            next_c = (field_storage.CPTRA_FLOW_STATUS.status.value & ~decoded_wr_biten[27:0]) | (decoded_wr_data[27:0] & decoded_wr_biten[27:0]);
+            next_c = (field_storage.CPTRA_FLOW_STATUS.status.value & ~decoded_wr_biten[23:0]) | (decoded_wr_data[23:0] & decoded_wr_biten[23:0]);
             load_next_c = '1;
         end
         field_combo.CPTRA_FLOW_STATUS.status.next = next_c;
@@ -1679,6 +2183,25 @@ module soc_ifc_reg (
             field_storage.CPTRA_FLOW_STATUS.status.value <= field_combo.CPTRA_FLOW_STATUS.status.next;
         end
     end
+    // Field: soc_ifc_reg.CPTRA_FLOW_STATUS.idevid_csr_ready
+    always_comb begin
+        automatic logic [0:0] next_c = field_storage.CPTRA_FLOW_STATUS.idevid_csr_ready.value;
+        automatic logic load_next_c = '0;
+        if(decoded_reg_strb.CPTRA_FLOW_STATUS && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write
+            next_c = (field_storage.CPTRA_FLOW_STATUS.idevid_csr_ready.value & ~decoded_wr_biten[24:24]) | (decoded_wr_data[24:24] & decoded_wr_biten[24:24]);
+            load_next_c = '1;
+        end
+        field_combo.CPTRA_FLOW_STATUS.idevid_csr_ready.next = next_c;
+        field_combo.CPTRA_FLOW_STATUS.idevid_csr_ready.load_next = load_next_c;
+    end
+    always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+        if(~hwif_in.cptra_rst_b) begin
+            field_storage.CPTRA_FLOW_STATUS.idevid_csr_ready.value <= 'h0;
+        end else if(field_combo.CPTRA_FLOW_STATUS.idevid_csr_ready.load_next) begin
+            field_storage.CPTRA_FLOW_STATUS.idevid_csr_ready.value <= field_combo.CPTRA_FLOW_STATUS.idevid_csr_ready.next;
+        end
+    end
+    assign hwif_out.CPTRA_FLOW_STATUS.idevid_csr_ready.value = field_storage.CPTRA_FLOW_STATUS.idevid_csr_ready.value;
     // Field: soc_ifc_reg.CPTRA_FLOW_STATUS.ready_for_fw
     always_comb begin
         automatic logic [0:0] next_c = field_storage.CPTRA_FLOW_STATUS.ready_for_fw.value;
@@ -1717,23 +2240,6 @@ module soc_ifc_reg (
         end
     end
     assign hwif_out.CPTRA_FLOW_STATUS.ready_for_runtime.value = field_storage.CPTRA_FLOW_STATUS.ready_for_runtime.value;
-    // Field: soc_ifc_reg.CPTRA_FLOW_STATUS.ready_for_fuses
-    always_comb begin
-        automatic logic [0:0] next_c = field_storage.CPTRA_FLOW_STATUS.ready_for_fuses.value;
-        automatic logic load_next_c = '0;
-        if(1) begin // HW Write
-            next_c = hwif_in.CPTRA_FLOW_STATUS.ready_for_fuses.next;
-            load_next_c = '1;
-        end
-        field_combo.CPTRA_FLOW_STATUS.ready_for_fuses.next = next_c;
-        field_combo.CPTRA_FLOW_STATUS.ready_for_fuses.load_next = load_next_c;
-    end
-    always_ff @(posedge clk) begin
-        if(field_combo.CPTRA_FLOW_STATUS.ready_for_fuses.load_next) begin
-            field_storage.CPTRA_FLOW_STATUS.ready_for_fuses.value <= field_combo.CPTRA_FLOW_STATUS.ready_for_fuses.next;
-        end
-    end
-    assign hwif_out.CPTRA_FLOW_STATUS.ready_for_fuses.value = field_storage.CPTRA_FLOW_STATUS.ready_for_fuses.value;
     // Field: soc_ifc_reg.CPTRA_FLOW_STATUS.mailbox_flow_done
     always_comb begin
         automatic logic [0:0] next_c = field_storage.CPTRA_FLOW_STATUS.mailbox_flow_done.value;
@@ -1879,6 +2385,9 @@ module soc_ifc_reg (
             if(decoded_reg_strb.CPTRA_TRNG_DATA[i0] && decoded_req_is_wr && hwif_in.CPTRA_TRNG_DATA[i0].DATA.swwe) begin // SW write
                 next_c = (field_storage.CPTRA_TRNG_DATA[i0].DATA.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
                 load_next_c = '1;
+            end else if(hwif_in.CPTRA_TRNG_DATA[i0].DATA.hwclr) begin // HW Clear
+                next_c = '0;
+                load_next_c = '1;
             end
             field_combo.CPTRA_TRNG_DATA[i0].DATA.next = next_c;
             field_combo.CPTRA_TRNG_DATA[i0].DATA.load_next = load_next_c;
@@ -1892,6 +2401,28 @@ module soc_ifc_reg (
         end
         assign hwif_out.CPTRA_TRNG_DATA[i0].DATA.swacc = decoded_reg_strb.CPTRA_TRNG_DATA[i0];
     end
+    // Field: soc_ifc_reg.CPTRA_TRNG_CTRL.clear
+    always_comb begin
+        automatic logic [0:0] next_c = field_storage.CPTRA_TRNG_CTRL.clear.value;
+        automatic logic load_next_c = '0;
+        if(decoded_reg_strb.CPTRA_TRNG_CTRL && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write
+            next_c = (field_storage.CPTRA_TRNG_CTRL.clear.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
+            load_next_c = '1;
+        end else if(1) begin // singlepulse clears back to 0
+            next_c = '0;
+            load_next_c = '1;
+        end
+        field_combo.CPTRA_TRNG_CTRL.clear.next = next_c;
+        field_combo.CPTRA_TRNG_CTRL.clear.load_next = load_next_c;
+    end
+    always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+        if(~hwif_in.cptra_rst_b) begin
+            field_storage.CPTRA_TRNG_CTRL.clear.value <= 'h0;
+        end else if(field_combo.CPTRA_TRNG_CTRL.clear.load_next) begin
+            field_storage.CPTRA_TRNG_CTRL.clear.value <= field_combo.CPTRA_TRNG_CTRL.clear.next;
+        end
+    end
+    assign hwif_out.CPTRA_TRNG_CTRL.clear.value = field_storage.CPTRA_TRNG_CTRL.clear.value;
     // Field: soc_ifc_reg.CPTRA_TRNG_STATUS.DATA_REQ
     always_comb begin
         automatic logic [0:0] next_c = field_storage.CPTRA_TRNG_STATUS.DATA_REQ.value;
@@ -2075,7 +2606,6 @@ module soc_ifc_reg (
         end
         assign hwif_out.CPTRA_GENERIC_OUTPUT_WIRES[i0].generic_wires.value = field_storage.CPTRA_GENERIC_OUTPUT_WIRES[i0].generic_wires.value;
     end
-    assign hwif_out.CPTRA_HW_REV_ID.REV_ID.value = 'h1;
     for(genvar i0=0; i0<2; i0++) begin
         // Field: soc_ifc_reg.CPTRA_FW_REV_ID[].REV_ID
         always_comb begin
@@ -2265,6 +2795,156 @@ module soc_ifc_reg (
         end
     end
     assign hwif_out.CPTRA_WDT_STATUS.t2_timeout.value = field_storage.CPTRA_WDT_STATUS.t2_timeout.value;
+    // Field: soc_ifc_reg.CPTRA_FUSE_VALID_PAUSER.PAUSER
+    always_comb begin
+        automatic logic [31:0] next_c = field_storage.CPTRA_FUSE_VALID_PAUSER.PAUSER.value;
+        automatic logic load_next_c = '0;
+        if(decoded_reg_strb.CPTRA_FUSE_VALID_PAUSER && decoded_req_is_wr && !(hwif_in.CPTRA_FUSE_VALID_PAUSER.PAUSER.swwel)) begin // SW write
+            next_c = (field_storage.CPTRA_FUSE_VALID_PAUSER.PAUSER.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+            load_next_c = '1;
+        end
+        field_combo.CPTRA_FUSE_VALID_PAUSER.PAUSER.next = next_c;
+        field_combo.CPTRA_FUSE_VALID_PAUSER.PAUSER.load_next = load_next_c;
+    end
+    always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
+        if(~hwif_in.cptra_pwrgood) begin
+            field_storage.CPTRA_FUSE_VALID_PAUSER.PAUSER.value <= 'hffffffff;
+        end else if(field_combo.CPTRA_FUSE_VALID_PAUSER.PAUSER.load_next) begin
+            field_storage.CPTRA_FUSE_VALID_PAUSER.PAUSER.value <= field_combo.CPTRA_FUSE_VALID_PAUSER.PAUSER.next;
+        end
+    end
+    assign hwif_out.CPTRA_FUSE_VALID_PAUSER.PAUSER.value = field_storage.CPTRA_FUSE_VALID_PAUSER.PAUSER.value;
+    // Field: soc_ifc_reg.CPTRA_FUSE_PAUSER_LOCK.LOCK
+    always_comb begin
+        automatic logic [0:0] next_c = field_storage.CPTRA_FUSE_PAUSER_LOCK.LOCK.value;
+        automatic logic load_next_c = '0;
+        if(decoded_reg_strb.CPTRA_FUSE_PAUSER_LOCK && decoded_req_is_wr && !(hwif_in.CPTRA_FUSE_PAUSER_LOCK.LOCK.swwel)) begin // SW write
+            next_c = (field_storage.CPTRA_FUSE_PAUSER_LOCK.LOCK.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
+            load_next_c = '1;
+        end
+        field_combo.CPTRA_FUSE_PAUSER_LOCK.LOCK.next = next_c;
+        field_combo.CPTRA_FUSE_PAUSER_LOCK.LOCK.load_next = load_next_c;
+    end
+    always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
+        if(~hwif_in.cptra_pwrgood) begin
+            field_storage.CPTRA_FUSE_PAUSER_LOCK.LOCK.value <= 'h0;
+        end else if(field_combo.CPTRA_FUSE_PAUSER_LOCK.LOCK.load_next) begin
+            field_storage.CPTRA_FUSE_PAUSER_LOCK.LOCK.value <= field_combo.CPTRA_FUSE_PAUSER_LOCK.LOCK.next;
+        end
+    end
+    assign hwif_out.CPTRA_FUSE_PAUSER_LOCK.LOCK.value = field_storage.CPTRA_FUSE_PAUSER_LOCK.LOCK.value;
+    for(genvar i0=0; i0<2; i0++) begin
+        // Field: soc_ifc_reg.CPTRA_WDT_CFG[].TIMEOUT
+        always_comb begin
+            automatic logic [31:0] next_c = field_storage.CPTRA_WDT_CFG[i0].TIMEOUT.value;
+            automatic logic load_next_c = '0;
+            if(decoded_reg_strb.CPTRA_WDT_CFG[i0] && decoded_req_is_wr) begin // SW write
+                next_c = (field_storage.CPTRA_WDT_CFG[i0].TIMEOUT.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+                load_next_c = '1;
+            end
+            field_combo.CPTRA_WDT_CFG[i0].TIMEOUT.next = next_c;
+            field_combo.CPTRA_WDT_CFG[i0].TIMEOUT.load_next = load_next_c;
+        end
+        always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
+            if(~hwif_in.cptra_pwrgood) begin
+                field_storage.CPTRA_WDT_CFG[i0].TIMEOUT.value <= 'h0;
+            end else if(field_combo.CPTRA_WDT_CFG[i0].TIMEOUT.load_next) begin
+                field_storage.CPTRA_WDT_CFG[i0].TIMEOUT.value <= field_combo.CPTRA_WDT_CFG[i0].TIMEOUT.next;
+            end
+        end
+    end
+    // Field: soc_ifc_reg.CPTRA_iTRNG_ENTROPY_CONFIG_0.low_threshold
+    always_comb begin
+        automatic logic [15:0] next_c = field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_0.low_threshold.value;
+        automatic logic load_next_c = '0;
+        if(decoded_reg_strb.CPTRA_iTRNG_ENTROPY_CONFIG_0 && decoded_req_is_wr) begin // SW write
+            next_c = (field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_0.low_threshold.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]);
+            load_next_c = '1;
+        end
+        field_combo.CPTRA_iTRNG_ENTROPY_CONFIG_0.low_threshold.next = next_c;
+        field_combo.CPTRA_iTRNG_ENTROPY_CONFIG_0.low_threshold.load_next = load_next_c;
+    end
+    always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+        if(~hwif_in.cptra_rst_b) begin
+            field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_0.low_threshold.value <= 'h0;
+        end else if(field_combo.CPTRA_iTRNG_ENTROPY_CONFIG_0.low_threshold.load_next) begin
+            field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_0.low_threshold.value <= field_combo.CPTRA_iTRNG_ENTROPY_CONFIG_0.low_threshold.next;
+        end
+    end
+    // Field: soc_ifc_reg.CPTRA_iTRNG_ENTROPY_CONFIG_0.high_threshold
+    always_comb begin
+        automatic logic [15:0] next_c = field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_0.high_threshold.value;
+        automatic logic load_next_c = '0;
+        if(decoded_reg_strb.CPTRA_iTRNG_ENTROPY_CONFIG_0 && decoded_req_is_wr) begin // SW write
+            next_c = (field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_0.high_threshold.value & ~decoded_wr_biten[31:16]) | (decoded_wr_data[31:16] & decoded_wr_biten[31:16]);
+            load_next_c = '1;
+        end
+        field_combo.CPTRA_iTRNG_ENTROPY_CONFIG_0.high_threshold.next = next_c;
+        field_combo.CPTRA_iTRNG_ENTROPY_CONFIG_0.high_threshold.load_next = load_next_c;
+    end
+    always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+        if(~hwif_in.cptra_rst_b) begin
+            field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_0.high_threshold.value <= 'h0;
+        end else if(field_combo.CPTRA_iTRNG_ENTROPY_CONFIG_0.high_threshold.load_next) begin
+            field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_0.high_threshold.value <= field_combo.CPTRA_iTRNG_ENTROPY_CONFIG_0.high_threshold.next;
+        end
+    end
+    // Field: soc_ifc_reg.CPTRA_iTRNG_ENTROPY_CONFIG_1.repetition_count
+    always_comb begin
+        automatic logic [15:0] next_c = field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_1.repetition_count.value;
+        automatic logic load_next_c = '0;
+        if(decoded_reg_strb.CPTRA_iTRNG_ENTROPY_CONFIG_1 && decoded_req_is_wr) begin // SW write
+            next_c = (field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_1.repetition_count.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]);
+            load_next_c = '1;
+        end
+        field_combo.CPTRA_iTRNG_ENTROPY_CONFIG_1.repetition_count.next = next_c;
+        field_combo.CPTRA_iTRNG_ENTROPY_CONFIG_1.repetition_count.load_next = load_next_c;
+    end
+    always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+        if(~hwif_in.cptra_rst_b) begin
+            field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_1.repetition_count.value <= 'h0;
+        end else if(field_combo.CPTRA_iTRNG_ENTROPY_CONFIG_1.repetition_count.load_next) begin
+            field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_1.repetition_count.value <= field_combo.CPTRA_iTRNG_ENTROPY_CONFIG_1.repetition_count.next;
+        end
+    end
+    // Field: soc_ifc_reg.CPTRA_iTRNG_ENTROPY_CONFIG_1.RSVD
+    always_comb begin
+        automatic logic [15:0] next_c = field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_1.RSVD.value;
+        automatic logic load_next_c = '0;
+        if(decoded_reg_strb.CPTRA_iTRNG_ENTROPY_CONFIG_1 && decoded_req_is_wr) begin // SW write
+            next_c = (field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_1.RSVD.value & ~decoded_wr_biten[31:16]) | (decoded_wr_data[31:16] & decoded_wr_biten[31:16]);
+            load_next_c = '1;
+        end
+        field_combo.CPTRA_iTRNG_ENTROPY_CONFIG_1.RSVD.next = next_c;
+        field_combo.CPTRA_iTRNG_ENTROPY_CONFIG_1.RSVD.load_next = load_next_c;
+    end
+    always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+        if(~hwif_in.cptra_rst_b) begin
+            field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_1.RSVD.value <= 'h0;
+        end else if(field_combo.CPTRA_iTRNG_ENTROPY_CONFIG_1.RSVD.load_next) begin
+            field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_1.RSVD.value <= field_combo.CPTRA_iTRNG_ENTROPY_CONFIG_1.RSVD.next;
+        end
+    end
+    for(genvar i0=0; i0<2; i0++) begin
+        // Field: soc_ifc_reg.CPTRA_RSVD_REG[].RSVD
+        always_comb begin
+            automatic logic [31:0] next_c = field_storage.CPTRA_RSVD_REG[i0].RSVD.value;
+            automatic logic load_next_c = '0;
+            if(decoded_reg_strb.CPTRA_RSVD_REG[i0] && decoded_req_is_wr) begin // SW write
+                next_c = (field_storage.CPTRA_RSVD_REG[i0].RSVD.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+                load_next_c = '1;
+            end
+            field_combo.CPTRA_RSVD_REG[i0].RSVD.next = next_c;
+            field_combo.CPTRA_RSVD_REG[i0].RSVD.load_next = load_next_c;
+        end
+        always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+            if(~hwif_in.cptra_rst_b) begin
+                field_storage.CPTRA_RSVD_REG[i0].RSVD.value <= 'h0;
+            end else if(field_combo.CPTRA_RSVD_REG[i0].RSVD.load_next) begin
+                field_storage.CPTRA_RSVD_REG[i0].RSVD.value <= field_combo.CPTRA_RSVD_REG[i0].RSVD.next;
+            end
+        end
+    end
     for(genvar i0=0; i0<12; i0++) begin
         // Field: soc_ifc_reg.fuse_uds_seed[].seed
         always_comb begin
@@ -2473,134 +3153,438 @@ module soc_ifc_reg (
                 field_storage.fuse_idevid_manuf_hsm_id[i0].hsm_id.value <= field_combo.fuse_idevid_manuf_hsm_id[i0].hsm_id.next;
             end
         end
-        assign hwif_out.fuse_idevid_manuf_hsm_id[i0].hsm_id.value = field_storage.fuse_idevid_manuf_hsm_id[i0].hsm_id.value;
+        assign hwif_out.fuse_idevid_manuf_hsm_id[i0].hsm_id.value = field_storage.fuse_idevid_manuf_hsm_id[i0].hsm_id.value;
+    end
+    // Field: soc_ifc_reg.fuse_life_cycle.life_cycle
+    always_comb begin
+        automatic logic [1:0] next_c = field_storage.fuse_life_cycle.life_cycle.value;
+        automatic logic load_next_c = '0;
+        if(decoded_reg_strb.fuse_life_cycle && decoded_req_is_wr && !(hwif_in.fuse_life_cycle.life_cycle.swwel)) begin // SW write
+            next_c = (field_storage.fuse_life_cycle.life_cycle.value & ~decoded_wr_biten[1:0]) | (decoded_wr_data[1:0] & decoded_wr_biten[1:0]);
+            load_next_c = '1;
+        end
+        field_combo.fuse_life_cycle.life_cycle.next = next_c;
+        field_combo.fuse_life_cycle.life_cycle.load_next = load_next_c;
+    end
+    always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
+        if(~hwif_in.cptra_pwrgood) begin
+            field_storage.fuse_life_cycle.life_cycle.value <= 'h0;
+        end else if(field_combo.fuse_life_cycle.life_cycle.load_next) begin
+            field_storage.fuse_life_cycle.life_cycle.value <= field_combo.fuse_life_cycle.life_cycle.next;
+        end
+    end
+    assign hwif_out.fuse_life_cycle.life_cycle.value = field_storage.fuse_life_cycle.life_cycle.value;
+    // Field: soc_ifc_reg.fuse_lms_verify.lms_verify
+    always_comb begin
+        automatic logic [0:0] next_c = field_storage.fuse_lms_verify.lms_verify.value;
+        automatic logic load_next_c = '0;
+        if(decoded_reg_strb.fuse_lms_verify && decoded_req_is_wr && !(hwif_in.fuse_lms_verify.lms_verify.swwel)) begin // SW write
+            next_c = (field_storage.fuse_lms_verify.lms_verify.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
+            load_next_c = '1;
+        end
+        field_combo.fuse_lms_verify.lms_verify.next = next_c;
+        field_combo.fuse_lms_verify.lms_verify.load_next = load_next_c;
+    end
+    always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
+        if(~hwif_in.cptra_pwrgood) begin
+            field_storage.fuse_lms_verify.lms_verify.value <= 'h0;
+        end else if(field_combo.fuse_lms_verify.lms_verify.load_next) begin
+            field_storage.fuse_lms_verify.lms_verify.value <= field_combo.fuse_lms_verify.lms_verify.next;
+        end
+    end
+    assign hwif_out.fuse_lms_verify.lms_verify.value = field_storage.fuse_lms_verify.lms_verify.value;
+    // Field: soc_ifc_reg.fuse_lms_revocation.lms_revocation
+    always_comb begin
+        automatic logic [31:0] next_c = field_storage.fuse_lms_revocation.lms_revocation.value;
+        automatic logic load_next_c = '0;
+        if(decoded_reg_strb.fuse_lms_revocation && decoded_req_is_wr && !(hwif_in.fuse_lms_revocation.lms_revocation.swwel)) begin // SW write
+            next_c = (field_storage.fuse_lms_revocation.lms_revocation.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+            load_next_c = '1;
+        end
+        field_combo.fuse_lms_revocation.lms_revocation.next = next_c;
+        field_combo.fuse_lms_revocation.lms_revocation.load_next = load_next_c;
+    end
+    always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
+        if(~hwif_in.cptra_pwrgood) begin
+            field_storage.fuse_lms_revocation.lms_revocation.value <= 'h0;
+        end else if(field_combo.fuse_lms_revocation.lms_revocation.load_next) begin
+            field_storage.fuse_lms_revocation.lms_revocation.value <= field_combo.fuse_lms_revocation.lms_revocation.next;
+        end
+    end
+    assign hwif_out.fuse_lms_revocation.lms_revocation.value = field_storage.fuse_lms_revocation.lms_revocation.value;
+    // Field: soc_ifc_reg.fuse_soc_stepping_id.soc_stepping_id
+    always_comb begin
+        automatic logic [15:0] next_c = field_storage.fuse_soc_stepping_id.soc_stepping_id.value;
+        automatic logic load_next_c = '0;
+        if(decoded_reg_strb.fuse_soc_stepping_id && decoded_req_is_wr && !(hwif_in.fuse_soc_stepping_id.soc_stepping_id.swwel)) begin // SW write
+            next_c = (field_storage.fuse_soc_stepping_id.soc_stepping_id.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]);
+            load_next_c = '1;
+        end
+        field_combo.fuse_soc_stepping_id.soc_stepping_id.next = next_c;
+        field_combo.fuse_soc_stepping_id.soc_stepping_id.load_next = load_next_c;
+    end
+    always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
+        if(~hwif_in.cptra_pwrgood) begin
+            field_storage.fuse_soc_stepping_id.soc_stepping_id.value <= 'h0;
+        end else if(field_combo.fuse_soc_stepping_id.soc_stepping_id.load_next) begin
+            field_storage.fuse_soc_stepping_id.soc_stepping_id.value <= field_combo.fuse_soc_stepping_id.soc_stepping_id.next;
+        end
+    end
+    assign hwif_out.fuse_soc_stepping_id.soc_stepping_id.value = field_storage.fuse_soc_stepping_id.soc_stepping_id.value;
+    for(genvar i0=0; i0<8; i0++) begin
+        // Field: soc_ifc_reg.internal_obf_key[].key
+        always_comb begin
+            automatic logic [31:0] next_c = field_storage.internal_obf_key[i0].key.value;
+            automatic logic load_next_c = '0;
+            if(decoded_reg_strb.internal_obf_key[i0] && decoded_req_is_wr && hwif_in.internal_obf_key[i0].key.swwe) begin // SW write
+                next_c = (field_storage.internal_obf_key[i0].key.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+                load_next_c = '1;
+            end else if(!hwif_in.internal_obf_key[i0].key.wel) begin // HW Write - wel
+                next_c = hwif_in.internal_obf_key[i0].key.next;
+                load_next_c = '1;
+            end else if(hwif_in.internal_obf_key[i0].key.hwclr) begin // HW Clear
+                next_c = '0;
+                load_next_c = '1;
+            end
+            field_combo.internal_obf_key[i0].key.next = next_c;
+            field_combo.internal_obf_key[i0].key.load_next = load_next_c;
+        end
+        always_ff @(posedge clk) begin
+            if(field_combo.internal_obf_key[i0].key.load_next) begin
+                field_storage.internal_obf_key[i0].key.value <= field_combo.internal_obf_key[i0].key.next;
+            end
+        end
+        assign hwif_out.internal_obf_key[i0].key.value = field_storage.internal_obf_key[i0].key.value;
+    end
+    // Field: soc_ifc_reg.internal_iccm_lock.lock
+    always_comb begin
+        automatic logic [0:0] next_c = field_storage.internal_iccm_lock.lock.value;
+        automatic logic load_next_c = '0;
+        if(hwif_in.internal_iccm_lock.lock.hwclr) begin // HW Clear
+            next_c = '0;
+            load_next_c = '1;
+        end else if(decoded_reg_strb.internal_iccm_lock && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set
+            next_c = field_storage.internal_iccm_lock.lock.value | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
+            load_next_c = '1;
+        end
+        field_combo.internal_iccm_lock.lock.next = next_c;
+        field_combo.internal_iccm_lock.lock.load_next = load_next_c;
+    end
+    always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+        if(~hwif_in.cptra_rst_b) begin
+            field_storage.internal_iccm_lock.lock.value <= 'h0;
+        end else if(field_combo.internal_iccm_lock.lock.load_next) begin
+            field_storage.internal_iccm_lock.lock.value <= field_combo.internal_iccm_lock.lock.next;
+        end
+    end
+    assign hwif_out.internal_iccm_lock.lock.value = field_storage.internal_iccm_lock.lock.value;
+    // Field: soc_ifc_reg.internal_fw_update_reset.core_rst
+    always_comb begin
+        automatic logic [0:0] next_c = field_storage.internal_fw_update_reset.core_rst.value;
+        automatic logic load_next_c = '0;
+        if(decoded_reg_strb.internal_fw_update_reset && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write
+            next_c = (field_storage.internal_fw_update_reset.core_rst.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
+            load_next_c = '1;
+        end else if(1) begin // singlepulse clears back to 0
+            next_c = '0;
+            load_next_c = '1;
+        end
+        field_combo.internal_fw_update_reset.core_rst.next = next_c;
+        field_combo.internal_fw_update_reset.core_rst.load_next = load_next_c;
+    end
+    always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+        if(~hwif_in.cptra_rst_b) begin
+            field_storage.internal_fw_update_reset.core_rst.value <= 'h0;
+        end else if(field_combo.internal_fw_update_reset.core_rst.load_next) begin
+            field_storage.internal_fw_update_reset.core_rst.value <= field_combo.internal_fw_update_reset.core_rst.next;
+        end
+    end
+    assign hwif_out.internal_fw_update_reset.core_rst.value = field_storage.internal_fw_update_reset.core_rst.value;
+    // Field: soc_ifc_reg.internal_fw_update_reset_wait_cycles.wait_cycles
+    always_comb begin
+        automatic logic [7:0] next_c = field_storage.internal_fw_update_reset_wait_cycles.wait_cycles.value;
+        automatic logic load_next_c = '0;
+        if(decoded_reg_strb.internal_fw_update_reset_wait_cycles && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write
+            next_c = (field_storage.internal_fw_update_reset_wait_cycles.wait_cycles.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+            load_next_c = '1;
+        end
+        field_combo.internal_fw_update_reset_wait_cycles.wait_cycles.next = next_c;
+        field_combo.internal_fw_update_reset_wait_cycles.wait_cycles.load_next = load_next_c;
+    end
+    always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+        if(~hwif_in.cptra_rst_b) begin
+            field_storage.internal_fw_update_reset_wait_cycles.wait_cycles.value <= 'h5;
+        end else if(field_combo.internal_fw_update_reset_wait_cycles.wait_cycles.load_next) begin
+            field_storage.internal_fw_update_reset_wait_cycles.wait_cycles.value <= field_combo.internal_fw_update_reset_wait_cycles.wait_cycles.next;
+        end
+    end
+    assign hwif_out.internal_fw_update_reset_wait_cycles.wait_cycles.value = field_storage.internal_fw_update_reset_wait_cycles.wait_cycles.value;
+    // Field: soc_ifc_reg.internal_nmi_vector.vec
+    always_comb begin
+        automatic logic [31:0] next_c = field_storage.internal_nmi_vector.vec.value;
+        automatic logic load_next_c = '0;
+        if(decoded_reg_strb.internal_nmi_vector && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write
+            next_c = (field_storage.internal_nmi_vector.vec.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+            load_next_c = '1;
+        end
+        field_combo.internal_nmi_vector.vec.next = next_c;
+        field_combo.internal_nmi_vector.vec.load_next = load_next_c;
+    end
+    always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+        if(~hwif_in.cptra_rst_b) begin
+            field_storage.internal_nmi_vector.vec.value <= 'h0;
+        end else if(field_combo.internal_nmi_vector.vec.load_next) begin
+            field_storage.internal_nmi_vector.vec.value <= field_combo.internal_nmi_vector.vec.next;
+        end
+    end
+    assign hwif_out.internal_nmi_vector.vec.value = field_storage.internal_nmi_vector.vec.value;
+    // Field: soc_ifc_reg.internal_hw_error_fatal_mask.mask_iccm_ecc_unc
+    always_comb begin
+        automatic logic [0:0] next_c = field_storage.internal_hw_error_fatal_mask.mask_iccm_ecc_unc.value;
+        automatic logic load_next_c = '0;
+        if(decoded_reg_strb.internal_hw_error_fatal_mask && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write
+            next_c = (field_storage.internal_hw_error_fatal_mask.mask_iccm_ecc_unc.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
+            load_next_c = '1;
+        end
+        field_combo.internal_hw_error_fatal_mask.mask_iccm_ecc_unc.next = next_c;
+        field_combo.internal_hw_error_fatal_mask.mask_iccm_ecc_unc.load_next = load_next_c;
+    end
+    always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+        if(~hwif_in.cptra_rst_b) begin
+            field_storage.internal_hw_error_fatal_mask.mask_iccm_ecc_unc.value <= 'h0;
+        end else if(field_combo.internal_hw_error_fatal_mask.mask_iccm_ecc_unc.load_next) begin
+            field_storage.internal_hw_error_fatal_mask.mask_iccm_ecc_unc.value <= field_combo.internal_hw_error_fatal_mask.mask_iccm_ecc_unc.next;
+        end
+    end
+    assign hwif_out.internal_hw_error_fatal_mask.mask_iccm_ecc_unc.value = field_storage.internal_hw_error_fatal_mask.mask_iccm_ecc_unc.value;
+    // Field: soc_ifc_reg.internal_hw_error_fatal_mask.mask_dccm_ecc_unc
+    always_comb begin
+        automatic logic [0:0] next_c = field_storage.internal_hw_error_fatal_mask.mask_dccm_ecc_unc.value;
+        automatic logic load_next_c = '0;
+        if(decoded_reg_strb.internal_hw_error_fatal_mask && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write
+            next_c = (field_storage.internal_hw_error_fatal_mask.mask_dccm_ecc_unc.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]);
+            load_next_c = '1;
+        end
+        field_combo.internal_hw_error_fatal_mask.mask_dccm_ecc_unc.next = next_c;
+        field_combo.internal_hw_error_fatal_mask.mask_dccm_ecc_unc.load_next = load_next_c;
+    end
+    always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+        if(~hwif_in.cptra_rst_b) begin
+            field_storage.internal_hw_error_fatal_mask.mask_dccm_ecc_unc.value <= 'h0;
+        end else if(field_combo.internal_hw_error_fatal_mask.mask_dccm_ecc_unc.load_next) begin
+            field_storage.internal_hw_error_fatal_mask.mask_dccm_ecc_unc.value <= field_combo.internal_hw_error_fatal_mask.mask_dccm_ecc_unc.next;
+        end
+    end
+    assign hwif_out.internal_hw_error_fatal_mask.mask_dccm_ecc_unc.value = field_storage.internal_hw_error_fatal_mask.mask_dccm_ecc_unc.value;
+    // Field: soc_ifc_reg.internal_hw_error_fatal_mask.mask_nmi_pin
+    always_comb begin
+        automatic logic [0:0] next_c = field_storage.internal_hw_error_fatal_mask.mask_nmi_pin.value;
+        automatic logic load_next_c = '0;
+        if(decoded_reg_strb.internal_hw_error_fatal_mask && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write
+            next_c = (field_storage.internal_hw_error_fatal_mask.mask_nmi_pin.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]);
+            load_next_c = '1;
+        end
+        field_combo.internal_hw_error_fatal_mask.mask_nmi_pin.next = next_c;
+        field_combo.internal_hw_error_fatal_mask.mask_nmi_pin.load_next = load_next_c;
+    end
+    always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+        if(~hwif_in.cptra_rst_b) begin
+            field_storage.internal_hw_error_fatal_mask.mask_nmi_pin.value <= 'h0;
+        end else if(field_combo.internal_hw_error_fatal_mask.mask_nmi_pin.load_next) begin
+            field_storage.internal_hw_error_fatal_mask.mask_nmi_pin.value <= field_combo.internal_hw_error_fatal_mask.mask_nmi_pin.next;
+        end
+    end
+    assign hwif_out.internal_hw_error_fatal_mask.mask_nmi_pin.value = field_storage.internal_hw_error_fatal_mask.mask_nmi_pin.value;
+    // Field: soc_ifc_reg.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock
+    always_comb begin
+        automatic logic [0:0] next_c = field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock.value;
+        automatic logic load_next_c = '0;
+        if(decoded_reg_strb.internal_hw_error_non_fatal_mask && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write
+            next_c = (field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
+            load_next_c = '1;
+        end
+        field_combo.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock.next = next_c;
+        field_combo.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock.load_next = load_next_c;
+    end
+    always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+        if(~hwif_in.cptra_rst_b) begin
+            field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock.value <= 'h0;
+        end else if(field_combo.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock.load_next) begin
+            field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock.value <= field_combo.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock.next;
+        end
+    end
+    assign hwif_out.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock.value = field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock.value;
+    // Field: soc_ifc_reg.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo
+    always_comb begin
+        automatic logic [0:0] next_c = field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo.value;
+        automatic logic load_next_c = '0;
+        if(decoded_reg_strb.internal_hw_error_non_fatal_mask && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write
+            next_c = (field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]);
+            load_next_c = '1;
+        end
+        field_combo.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo.next = next_c;
+        field_combo.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo.load_next = load_next_c;
+    end
+    always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+        if(~hwif_in.cptra_rst_b) begin
+            field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo.value <= 'h0;
+        end else if(field_combo.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo.load_next) begin
+            field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo.value <= field_combo.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo.next;
+        end
+    end
+    assign hwif_out.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo.value = field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo.value;
+    // Field: soc_ifc_reg.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc
+    always_comb begin
+        automatic logic [0:0] next_c = field_storage.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc.value;
+        automatic logic load_next_c = '0;
+        if(decoded_reg_strb.internal_hw_error_non_fatal_mask && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write
+            next_c = (field_storage.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]);
+            load_next_c = '1;
+        end
+        field_combo.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc.next = next_c;
+        field_combo.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc.load_next = load_next_c;
+    end
+    always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+        if(~hwif_in.cptra_rst_b) begin
+            field_storage.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc.value <= 'h0;
+        end else if(field_combo.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc.load_next) begin
+            field_storage.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc.value <= field_combo.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc.next;
+        end
     end
-    // Field: soc_ifc_reg.fuse_life_cycle.life_cycle
+    assign hwif_out.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc.value = field_storage.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc.value;
+    // Field: soc_ifc_reg.internal_fw_error_fatal_mask.mask
     always_comb begin
-        automatic logic [1:0] next_c = field_storage.fuse_life_cycle.life_cycle.value;
+        automatic logic [31:0] next_c = field_storage.internal_fw_error_fatal_mask.mask.value;
         automatic logic load_next_c = '0;
-        if(decoded_reg_strb.fuse_life_cycle && decoded_req_is_wr && !(hwif_in.fuse_life_cycle.life_cycle.swwel)) begin // SW write
-            next_c = (field_storage.fuse_life_cycle.life_cycle.value & ~decoded_wr_biten[1:0]) | (decoded_wr_data[1:0] & decoded_wr_biten[1:0]);
+        if(decoded_reg_strb.internal_fw_error_fatal_mask && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write
+            next_c = (field_storage.internal_fw_error_fatal_mask.mask.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
             load_next_c = '1;
         end
-        field_combo.fuse_life_cycle.life_cycle.next = next_c;
-        field_combo.fuse_life_cycle.life_cycle.load_next = load_next_c;
+        field_combo.internal_fw_error_fatal_mask.mask.next = next_c;
+        field_combo.internal_fw_error_fatal_mask.mask.load_next = load_next_c;
     end
-    always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
-        if(~hwif_in.cptra_pwrgood) begin
-            field_storage.fuse_life_cycle.life_cycle.value <= 'h0;
-        end else if(field_combo.fuse_life_cycle.life_cycle.load_next) begin
-            field_storage.fuse_life_cycle.life_cycle.value <= field_combo.fuse_life_cycle.life_cycle.next;
+    always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+        if(~hwif_in.cptra_rst_b) begin
+            field_storage.internal_fw_error_fatal_mask.mask.value <= 'h0;
+        end else if(field_combo.internal_fw_error_fatal_mask.mask.load_next) begin
+            field_storage.internal_fw_error_fatal_mask.mask.value <= field_combo.internal_fw_error_fatal_mask.mask.next;
         end
     end
-    assign hwif_out.fuse_life_cycle.life_cycle.value = field_storage.fuse_life_cycle.life_cycle.value;
-    for(genvar i0=0; i0<8; i0++) begin
-        // Field: soc_ifc_reg.internal_obf_key[].key
-        always_comb begin
-            automatic logic [31:0] next_c = field_storage.internal_obf_key[i0].key.value;
-            automatic logic load_next_c = '0;
-            if(decoded_reg_strb.internal_obf_key[i0] && decoded_req_is_wr && hwif_in.internal_obf_key[i0].key.swwe) begin // SW write
-                next_c = (field_storage.internal_obf_key[i0].key.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
-                load_next_c = '1;
-            end else if(!hwif_in.internal_obf_key[i0].key.wel) begin // HW Write - wel
-                next_c = hwif_in.internal_obf_key[i0].key.next;
-                load_next_c = '1;
-            end else if(hwif_in.internal_obf_key[i0].key.hwclr) begin // HW Clear
-                next_c = '0;
-                load_next_c = '1;
-            end
-            field_combo.internal_obf_key[i0].key.next = next_c;
-            field_combo.internal_obf_key[i0].key.load_next = load_next_c;
+    assign hwif_out.internal_fw_error_fatal_mask.mask.value = field_storage.internal_fw_error_fatal_mask.mask.value;
+    // Field: soc_ifc_reg.internal_fw_error_non_fatal_mask.mask
+    always_comb begin
+        automatic logic [31:0] next_c = field_storage.internal_fw_error_non_fatal_mask.mask.value;
+        automatic logic load_next_c = '0;
+        if(decoded_reg_strb.internal_fw_error_non_fatal_mask && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write
+            next_c = (field_storage.internal_fw_error_non_fatal_mask.mask.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+            load_next_c = '1;
         end
-        always_ff @(posedge clk) begin
-            if(field_combo.internal_obf_key[i0].key.load_next) begin
-                field_storage.internal_obf_key[i0].key.value <= field_combo.internal_obf_key[i0].key.next;
-            end
+        field_combo.internal_fw_error_non_fatal_mask.mask.next = next_c;
+        field_combo.internal_fw_error_non_fatal_mask.mask.load_next = load_next_c;
+    end
+    always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+        if(~hwif_in.cptra_rst_b) begin
+            field_storage.internal_fw_error_non_fatal_mask.mask.value <= 'h0;
+        end else if(field_combo.internal_fw_error_non_fatal_mask.mask.load_next) begin
+            field_storage.internal_fw_error_non_fatal_mask.mask.value <= field_combo.internal_fw_error_non_fatal_mask.mask.next;
         end
-        assign hwif_out.internal_obf_key[i0].key.value = field_storage.internal_obf_key[i0].key.value;
     end
-    // Field: soc_ifc_reg.internal_iccm_lock.lock
+    assign hwif_out.internal_fw_error_non_fatal_mask.mask.value = field_storage.internal_fw_error_non_fatal_mask.mask.value;
+    // Field: soc_ifc_reg.internal_rv_mtime_l.count_l
     always_comb begin
-        automatic logic [0:0] next_c = field_storage.internal_iccm_lock.lock.value;
+        automatic logic [31:0] next_c = field_storage.internal_rv_mtime_l.count_l.value;
         automatic logic load_next_c = '0;
-        if(hwif_in.internal_iccm_lock.lock.hwclr) begin // HW Clear
-            next_c = '0;
+        if(decoded_reg_strb.internal_rv_mtime_l && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write
+            next_c = (field_storage.internal_rv_mtime_l.count_l.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
             load_next_c = '1;
-        end else if(decoded_reg_strb.internal_iccm_lock && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set
-            next_c = field_storage.internal_iccm_lock.lock.value | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
+        end
+        if(hwif_in.internal_rv_mtime_l.count_l.incr) begin // increment
+            field_combo.internal_rv_mtime_l.count_l.overflow = (((33)'(next_c) + 'h1) > 'hffffffff);
+            next_c = next_c + 'h1;
             load_next_c = '1;
+        end else begin
+            field_combo.internal_rv_mtime_l.count_l.overflow = '0;
         end
-        field_combo.internal_iccm_lock.lock.next = next_c;
-        field_combo.internal_iccm_lock.lock.load_next = load_next_c;
+        field_combo.internal_rv_mtime_l.count_l.incrthreshold = (field_storage.internal_rv_mtime_l.count_l.value >= 'hffffffff);
+        field_combo.internal_rv_mtime_l.count_l.next = next_c;
+        field_combo.internal_rv_mtime_l.count_l.load_next = load_next_c;
     end
-    always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
-        if(~hwif_in.cptra_rst_b) begin
-            field_storage.internal_iccm_lock.lock.value <= 'h0;
-        end else if(field_combo.internal_iccm_lock.lock.load_next) begin
-            field_storage.internal_iccm_lock.lock.value <= field_combo.internal_iccm_lock.lock.next;
+    always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
+        if(~hwif_in.cptra_pwrgood) begin
+            field_storage.internal_rv_mtime_l.count_l.value <= 'h0;
+        end else if(field_combo.internal_rv_mtime_l.count_l.load_next) begin
+            field_storage.internal_rv_mtime_l.count_l.value <= field_combo.internal_rv_mtime_l.count_l.next;
         end
     end
-    assign hwif_out.internal_iccm_lock.lock.value = field_storage.internal_iccm_lock.lock.value;
-    // Field: soc_ifc_reg.internal_fw_update_reset.core_rst
+    assign hwif_out.internal_rv_mtime_l.count_l.value = field_storage.internal_rv_mtime_l.count_l.value;
+    assign hwif_out.internal_rv_mtime_l.count_l.swmod = decoded_reg_strb.internal_rv_mtime_l && decoded_req_is_wr;
+    assign hwif_out.internal_rv_mtime_l.count_l.overflow = field_combo.internal_rv_mtime_l.count_l.overflow;
+    // Field: soc_ifc_reg.internal_rv_mtime_h.count_h
     always_comb begin
-        automatic logic [0:0] next_c = field_storage.internal_fw_update_reset.core_rst.value;
+        automatic logic [31:0] next_c = field_storage.internal_rv_mtime_h.count_h.value;
         automatic logic load_next_c = '0;
-        if(decoded_reg_strb.internal_fw_update_reset && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write
-            next_c = (field_storage.internal_fw_update_reset.core_rst.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
+        if(decoded_reg_strb.internal_rv_mtime_h && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write
+            next_c = (field_storage.internal_rv_mtime_h.count_h.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
             load_next_c = '1;
-        end else if(1) begin // singlepulse clears back to 0
-            next_c = '0;
+        end
+        if(hwif_in.internal_rv_mtime_h.count_h.incr) begin // increment
+            field_combo.internal_rv_mtime_h.count_h.overflow = (((33)'(next_c) + 'h1) > 'hffffffff);
+            next_c = next_c + 'h1;
             load_next_c = '1;
+        end else begin
+            field_combo.internal_rv_mtime_h.count_h.overflow = '0;
         end
-        field_combo.internal_fw_update_reset.core_rst.next = next_c;
-        field_combo.internal_fw_update_reset.core_rst.load_next = load_next_c;
+        field_combo.internal_rv_mtime_h.count_h.incrthreshold = (field_storage.internal_rv_mtime_h.count_h.value >= 'hffffffff);
+        field_combo.internal_rv_mtime_h.count_h.next = next_c;
+        field_combo.internal_rv_mtime_h.count_h.load_next = load_next_c;
     end
-    always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
-        if(~hwif_in.cptra_rst_b) begin
-            field_storage.internal_fw_update_reset.core_rst.value <= 'h0;
-        end else if(field_combo.internal_fw_update_reset.core_rst.load_next) begin
-            field_storage.internal_fw_update_reset.core_rst.value <= field_combo.internal_fw_update_reset.core_rst.next;
+    always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
+        if(~hwif_in.cptra_pwrgood) begin
+            field_storage.internal_rv_mtime_h.count_h.value <= 'h0;
+        end else if(field_combo.internal_rv_mtime_h.count_h.load_next) begin
+            field_storage.internal_rv_mtime_h.count_h.value <= field_combo.internal_rv_mtime_h.count_h.next;
         end
     end
-    assign hwif_out.internal_fw_update_reset.core_rst.value = field_storage.internal_fw_update_reset.core_rst.value;
-    // Field: soc_ifc_reg.internal_fw_update_reset_wait_cycles.wait_cycles
+    assign hwif_out.internal_rv_mtime_h.count_h.value = field_storage.internal_rv_mtime_h.count_h.value;
+    assign hwif_out.internal_rv_mtime_h.count_h.swmod = decoded_reg_strb.internal_rv_mtime_h && decoded_req_is_wr;
+    // Field: soc_ifc_reg.internal_rv_mtimecmp_l.compare_l
     always_comb begin
-        automatic logic [7:0] next_c = field_storage.internal_fw_update_reset_wait_cycles.wait_cycles.value;
+        automatic logic [31:0] next_c = field_storage.internal_rv_mtimecmp_l.compare_l.value;
         automatic logic load_next_c = '0;
-        if(decoded_reg_strb.internal_fw_update_reset_wait_cycles && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write
-            next_c = (field_storage.internal_fw_update_reset_wait_cycles.wait_cycles.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]);
+        if(decoded_reg_strb.internal_rv_mtimecmp_l && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write
+            next_c = (field_storage.internal_rv_mtimecmp_l.compare_l.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
             load_next_c = '1;
         end
-        field_combo.internal_fw_update_reset_wait_cycles.wait_cycles.next = next_c;
-        field_combo.internal_fw_update_reset_wait_cycles.wait_cycles.load_next = load_next_c;
+        field_combo.internal_rv_mtimecmp_l.compare_l.next = next_c;
+        field_combo.internal_rv_mtimecmp_l.compare_l.load_next = load_next_c;
     end
-    always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
-        if(~hwif_in.cptra_rst_b) begin
-            field_storage.internal_fw_update_reset_wait_cycles.wait_cycles.value <= 'h5;
-        end else if(field_combo.internal_fw_update_reset_wait_cycles.wait_cycles.load_next) begin
-            field_storage.internal_fw_update_reset_wait_cycles.wait_cycles.value <= field_combo.internal_fw_update_reset_wait_cycles.wait_cycles.next;
+    always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
+        if(~hwif_in.cptra_pwrgood) begin
+            field_storage.internal_rv_mtimecmp_l.compare_l.value <= 'h0;
+        end else if(field_combo.internal_rv_mtimecmp_l.compare_l.load_next) begin
+            field_storage.internal_rv_mtimecmp_l.compare_l.value <= field_combo.internal_rv_mtimecmp_l.compare_l.next;
         end
     end
-    assign hwif_out.internal_fw_update_reset_wait_cycles.wait_cycles.value = field_storage.internal_fw_update_reset_wait_cycles.wait_cycles.value;
-    // Field: soc_ifc_reg.internal_nmi_vector.vec
+    assign hwif_out.internal_rv_mtimecmp_l.compare_l.value = field_storage.internal_rv_mtimecmp_l.compare_l.value;
+    // Field: soc_ifc_reg.internal_rv_mtimecmp_h.compare_h
     always_comb begin
-        automatic logic [31:0] next_c = field_storage.internal_nmi_vector.vec.value;
+        automatic logic [31:0] next_c = field_storage.internal_rv_mtimecmp_h.compare_h.value;
         automatic logic load_next_c = '0;
-        if(decoded_reg_strb.internal_nmi_vector && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write
-            next_c = (field_storage.internal_nmi_vector.vec.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+        if(decoded_reg_strb.internal_rv_mtimecmp_h && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write
+            next_c = (field_storage.internal_rv_mtimecmp_h.compare_h.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
             load_next_c = '1;
         end
-        field_combo.internal_nmi_vector.vec.next = next_c;
-        field_combo.internal_nmi_vector.vec.load_next = load_next_c;
+        field_combo.internal_rv_mtimecmp_h.compare_h.next = next_c;
+        field_combo.internal_rv_mtimecmp_h.compare_h.load_next = load_next_c;
     end
-    always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
-        if(~hwif_in.cptra_rst_b) begin
-            field_storage.internal_nmi_vector.vec.value <= 'h0;
-        end else if(field_combo.internal_nmi_vector.vec.load_next) begin
-            field_storage.internal_nmi_vector.vec.value <= field_combo.internal_nmi_vector.vec.next;
+    always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
+        if(~hwif_in.cptra_pwrgood) begin
+            field_storage.internal_rv_mtimecmp_h.compare_h.value <= 'h0;
+        end else if(field_combo.internal_rv_mtimecmp_h.compare_h.load_next) begin
+            field_storage.internal_rv_mtimecmp_h.compare_h.value <= field_combo.internal_rv_mtimecmp_h.compare_h.next;
         end
     end
-    assign hwif_out.internal_nmi_vector.vec.value = field_storage.internal_nmi_vector.vec.value;
+    assign hwif_out.internal_rv_mtimecmp_h.compare_h.value = field_storage.internal_rv_mtimecmp_h.compare_h.value;
     // Field: soc_ifc_reg.intr_block_rf.global_intr_en_r.error_en
     always_comb begin
         automatic logic [0:0] next_c = field_storage.intr_block_rf.global_intr_en_r.error_en.value;
@@ -2835,12 +3819,30 @@ module soc_ifc_reg (
             field_storage.intr_block_rf.notif_intr_en_r.notif_debug_locked_en.value <= field_combo.intr_block_rf.notif_intr_en_r.notif_debug_locked_en.next;
         end
     end
+    // Field: soc_ifc_reg.intr_block_rf.notif_intr_en_r.notif_scan_mode_en
+    always_comb begin
+        automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_scan_mode_en.value;
+        automatic logic load_next_c = '0;
+        if(decoded_reg_strb.intr_block_rf.notif_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write
+            next_c = (field_storage.intr_block_rf.notif_intr_en_r.notif_scan_mode_en.value & ~decoded_wr_biten[3:3]) | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]);
+            load_next_c = '1;
+        end
+        field_combo.intr_block_rf.notif_intr_en_r.notif_scan_mode_en.next = next_c;
+        field_combo.intr_block_rf.notif_intr_en_r.notif_scan_mode_en.load_next = load_next_c;
+    end
+    always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+        if(~hwif_in.cptra_rst_b) begin
+            field_storage.intr_block_rf.notif_intr_en_r.notif_scan_mode_en.value <= 'h0;
+        end else if(field_combo.intr_block_rf.notif_intr_en_r.notif_scan_mode_en.load_next) begin
+            field_storage.intr_block_rf.notif_intr_en_r.notif_scan_mode_en.value <= field_combo.intr_block_rf.notif_intr_en_r.notif_scan_mode_en.next;
+        end
+    end
     // Field: soc_ifc_reg.intr_block_rf.notif_intr_en_r.notif_soc_req_lock_en
     always_comb begin
         automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_soc_req_lock_en.value;
         automatic logic load_next_c = '0;
         if(decoded_reg_strb.intr_block_rf.notif_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write
-            next_c = (field_storage.intr_block_rf.notif_intr_en_r.notif_soc_req_lock_en.value & ~decoded_wr_biten[3:3]) | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]);
+            next_c = (field_storage.intr_block_rf.notif_intr_en_r.notif_soc_req_lock_en.value & ~decoded_wr_biten[4:4]) | (decoded_wr_data[4:4] & decoded_wr_biten[4:4]);
             load_next_c = '1;
         end
         field_combo.intr_block_rf.notif_intr_en_r.notif_soc_req_lock_en.next = next_c;
@@ -2853,6 +3855,24 @@ module soc_ifc_reg (
             field_storage.intr_block_rf.notif_intr_en_r.notif_soc_req_lock_en.value <= field_combo.intr_block_rf.notif_intr_en_r.notif_soc_req_lock_en.next;
         end
     end
+    // Field: soc_ifc_reg.intr_block_rf.notif_intr_en_r.notif_gen_in_toggle_en
+    always_comb begin
+        automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_gen_in_toggle_en.value;
+        automatic logic load_next_c = '0;
+        if(decoded_reg_strb.intr_block_rf.notif_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write
+            next_c = (field_storage.intr_block_rf.notif_intr_en_r.notif_gen_in_toggle_en.value & ~decoded_wr_biten[5:5]) | (decoded_wr_data[5:5] & decoded_wr_biten[5:5]);
+            load_next_c = '1;
+        end
+        field_combo.intr_block_rf.notif_intr_en_r.notif_gen_in_toggle_en.next = next_c;
+        field_combo.intr_block_rf.notif_intr_en_r.notif_gen_in_toggle_en.load_next = load_next_c;
+    end
+    always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+        if(~hwif_in.cptra_rst_b) begin
+            field_storage.intr_block_rf.notif_intr_en_r.notif_gen_in_toggle_en.value <= 'h0;
+        end else if(field_combo.intr_block_rf.notif_intr_en_r.notif_gen_in_toggle_en.load_next) begin
+            field_storage.intr_block_rf.notif_intr_en_r.notif_gen_in_toggle_en.value <= field_combo.intr_block_rf.notif_intr_en_r.notif_gen_in_toggle_en.next;
+        end
+    end
     // Field: soc_ifc_reg.intr_block_rf.error_global_intr_r.agg_sts
     always_comb begin
         automatic logic [0:0] next_c = field_storage.intr_block_rf.error_global_intr_r.agg_sts.value;
@@ -3166,6 +4186,30 @@ module soc_ifc_reg (
             field_storage.intr_block_rf.notif_internal_intr_r.notif_debug_locked_sts.value <= field_combo.intr_block_rf.notif_internal_intr_r.notif_debug_locked_sts.next;
         end
     end
+    // Field: soc_ifc_reg.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts
+    always_comb begin
+        automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts.value;
+        automatic logic load_next_c = '0;
+        if(field_storage.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.value) begin // stickybit
+            next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts.value | field_storage.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.value;
+            load_next_c = '1;
+        end else if(hwif_in.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts.hwset) begin // HW Set
+            next_c = '1;
+            load_next_c = '1;
+        end else if(decoded_reg_strb.intr_block_rf.notif_internal_intr_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 clear
+            next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts.value & ~(decoded_wr_data[3:3] & decoded_wr_biten[3:3]);
+            load_next_c = '1;
+        end
+        field_combo.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts.next = next_c;
+        field_combo.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts.load_next = load_next_c;
+    end
+    always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+        if(~hwif_in.cptra_rst_b) begin
+            field_storage.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts.value <= 'h0;
+        end else if(field_combo.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts.load_next) begin
+            field_storage.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts.value <= field_combo.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts.next;
+        end
+    end
     // Field: soc_ifc_reg.intr_block_rf.notif_internal_intr_r.notif_soc_req_lock_sts
     always_comb begin
         automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_soc_req_lock_sts.value;
@@ -3177,7 +4221,7 @@ module soc_ifc_reg (
             next_c = '1;
             load_next_c = '1;
         end else if(decoded_reg_strb.intr_block_rf.notif_internal_intr_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 clear
-            next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_soc_req_lock_sts.value & ~(decoded_wr_data[3:3] & decoded_wr_biten[3:3]);
+            next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_soc_req_lock_sts.value & ~(decoded_wr_data[4:4] & decoded_wr_biten[4:4]);
             load_next_c = '1;
         end
         field_combo.intr_block_rf.notif_internal_intr_r.notif_soc_req_lock_sts.next = next_c;
@@ -3190,11 +4234,37 @@ module soc_ifc_reg (
             field_storage.intr_block_rf.notif_internal_intr_r.notif_soc_req_lock_sts.value <= field_combo.intr_block_rf.notif_internal_intr_r.notif_soc_req_lock_sts.next;
         end
     end
+    // Field: soc_ifc_reg.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts
+    always_comb begin
+        automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.value;
+        automatic logic load_next_c = '0;
+        if(field_storage.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.value) begin // stickybit
+            next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.value | field_storage.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.value;
+            load_next_c = '1;
+        end else if(hwif_in.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.hwset) begin // HW Set
+            next_c = '1;
+            load_next_c = '1;
+        end else if(decoded_reg_strb.intr_block_rf.notif_internal_intr_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 clear
+            next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.value & ~(decoded_wr_data[5:5] & decoded_wr_biten[5:5]);
+            load_next_c = '1;
+        end
+        field_combo.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.next = next_c;
+        field_combo.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.load_next = load_next_c;
+    end
+    always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+        if(~hwif_in.cptra_rst_b) begin
+            field_storage.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.value <= 'h0;
+        end else if(field_combo.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.load_next) begin
+            field_storage.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.value <= field_combo.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.next;
+        end
+    end
     assign hwif_out.intr_block_rf.notif_internal_intr_r.intr =
         |(field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_avail_sts.value & field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_avail_en.value)
         || |(field_storage.intr_block_rf.notif_internal_intr_r.notif_mbox_ecc_cor_sts.value & field_storage.intr_block_rf.notif_intr_en_r.notif_mbox_ecc_cor_en.value)
         || |(field_storage.intr_block_rf.notif_internal_intr_r.notif_debug_locked_sts.value & field_storage.intr_block_rf.notif_intr_en_r.notif_debug_locked_en.value)
-        || |(field_storage.intr_block_rf.notif_internal_intr_r.notif_soc_req_lock_sts.value & field_storage.intr_block_rf.notif_intr_en_r.notif_soc_req_lock_en.value);
+        || |(field_storage.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts.value & field_storage.intr_block_rf.notif_intr_en_r.notif_scan_mode_en.value)
+        || |(field_storage.intr_block_rf.notif_internal_intr_r.notif_soc_req_lock_sts.value & field_storage.intr_block_rf.notif_intr_en_r.notif_soc_req_lock_en.value)
+        || |(field_storage.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.value & field_storage.intr_block_rf.notif_intr_en_r.notif_gen_in_toggle_en.value);
     // Field: soc_ifc_reg.intr_block_rf.error_intr_trig_r.error_internal_trig
     always_comb begin
         automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value;
@@ -3426,12 +4496,33 @@ module soc_ifc_reg (
             field_storage.intr_block_rf.notif_intr_trig_r.notif_debug_locked_trig.value <= field_combo.intr_block_rf.notif_intr_trig_r.notif_debug_locked_trig.next;
         end
     end
+    // Field: soc_ifc_reg.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig
+    always_comb begin
+        automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.value;
+        automatic logic load_next_c = '0;
+        if(decoded_reg_strb.intr_block_rf.notif_intr_trig_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set
+            next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.value | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]);
+            load_next_c = '1;
+        end else if(1) begin // singlepulse clears back to 0
+            next_c = '0;
+            load_next_c = '1;
+        end
+        field_combo.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.next = next_c;
+        field_combo.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.load_next = load_next_c;
+    end
+    always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+        if(~hwif_in.cptra_rst_b) begin
+            field_storage.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.value <= 'h0;
+        end else if(field_combo.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.load_next) begin
+            field_storage.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.value <= field_combo.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.next;
+        end
+    end
     // Field: soc_ifc_reg.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig
     always_comb begin
         automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.value;
         automatic logic load_next_c = '0;
         if(decoded_reg_strb.intr_block_rf.notif_intr_trig_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set
-            next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.value | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]);
+            next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.value | (decoded_wr_data[4:4] & decoded_wr_biten[4:4]);
             load_next_c = '1;
         end else if(1) begin // singlepulse clears back to 0
             next_c = '0;
@@ -3447,6 +4538,27 @@ module soc_ifc_reg (
             field_storage.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.value <= field_combo.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.next;
         end
     end
+    // Field: soc_ifc_reg.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig
+    always_comb begin
+        automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.value;
+        automatic logic load_next_c = '0;
+        if(decoded_reg_strb.intr_block_rf.notif_intr_trig_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set
+            next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.value | (decoded_wr_data[5:5] & decoded_wr_biten[5:5]);
+            load_next_c = '1;
+        end else if(1) begin // singlepulse clears back to 0
+            next_c = '0;
+            load_next_c = '1;
+        end
+        field_combo.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.next = next_c;
+        field_combo.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.load_next = load_next_c;
+    end
+    always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+        if(~hwif_in.cptra_rst_b) begin
+            field_storage.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.value <= 'h0;
+        end else if(field_combo.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.load_next) begin
+            field_storage.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.value <= field_combo.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.next;
+        end
+    end
     // Field: soc_ifc_reg.intr_block_rf.error_internal_intr_count_r.cnt
     always_comb begin
         automatic logic [31:0] next_c = field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value;
@@ -3799,6 +4911,38 @@ module soc_ifc_reg (
             field_storage.intr_block_rf.notif_debug_locked_intr_count_r.cnt.value <= field_combo.intr_block_rf.notif_debug_locked_intr_count_r.cnt.next;
         end
     end
+    // Field: soc_ifc_reg.intr_block_rf.notif_scan_mode_intr_count_r.cnt
+    always_comb begin
+        automatic logic [31:0] next_c = field_storage.intr_block_rf.notif_scan_mode_intr_count_r.cnt.value;
+        automatic logic load_next_c = '0;
+        if(decoded_reg_strb.intr_block_rf.notif_scan_mode_intr_count_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write
+            next_c = (field_storage.intr_block_rf.notif_scan_mode_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+            load_next_c = '1;
+        end
+        if(field_storage.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.value) begin // increment
+            if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated
+                next_c = 'hffffffff;
+            end else begin
+                next_c = next_c + 'h1;
+            end
+            load_next_c = '1;
+        end
+        field_combo.intr_block_rf.notif_scan_mode_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_scan_mode_intr_count_r.cnt.value >= 'hffffffff);
+        field_combo.intr_block_rf.notif_scan_mode_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_scan_mode_intr_count_r.cnt.value >= 'hffffffff);
+        if(next_c > 'hffffffff) begin
+            next_c = 'hffffffff;
+            load_next_c = '1;
+        end
+        field_combo.intr_block_rf.notif_scan_mode_intr_count_r.cnt.next = next_c;
+        field_combo.intr_block_rf.notif_scan_mode_intr_count_r.cnt.load_next = load_next_c;
+    end
+    always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+        if(~hwif_in.cptra_rst_b) begin
+            field_storage.intr_block_rf.notif_scan_mode_intr_count_r.cnt.value <= 'h0;
+        end else if(field_combo.intr_block_rf.notif_scan_mode_intr_count_r.cnt.load_next) begin
+            field_storage.intr_block_rf.notif_scan_mode_intr_count_r.cnt.value <= field_combo.intr_block_rf.notif_scan_mode_intr_count_r.cnt.next;
+        end
+    end
     // Field: soc_ifc_reg.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt
     always_comb begin
         automatic logic [31:0] next_c = field_storage.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.value;
@@ -3831,6 +4975,38 @@ module soc_ifc_reg (
             field_storage.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.value <= field_combo.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.next;
         end
     end
+    // Field: soc_ifc_reg.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt
+    always_comb begin
+        automatic logic [31:0] next_c = field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.value;
+        automatic logic load_next_c = '0;
+        if(decoded_reg_strb.intr_block_rf.notif_gen_in_toggle_intr_count_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write
+            next_c = (field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+            load_next_c = '1;
+        end
+        if(field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.value) begin // increment
+            if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated
+                next_c = 'hffffffff;
+            end else begin
+                next_c = next_c + 'h1;
+            end
+            load_next_c = '1;
+        end
+        field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.value >= 'hffffffff);
+        field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.value >= 'hffffffff);
+        if(next_c > 'hffffffff) begin
+            next_c = 'hffffffff;
+            load_next_c = '1;
+        end
+        field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.next = next_c;
+        field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.load_next = load_next_c;
+    end
+    always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+        if(~hwif_in.cptra_rst_b) begin
+            field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.value <= 'h0;
+        end else if(field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.load_next) begin
+            field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.value <= field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.next;
+        end
+    end
     // Field: soc_ifc_reg.intr_block_rf.error_internal_intr_count_incr_r.pulse
     always_comb begin
         automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value;
@@ -4150,6 +5326,35 @@ module soc_ifc_reg (
             field_storage.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.next;
         end
     end
+    // Field: soc_ifc_reg.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse
+    always_comb begin
+        automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.value;
+        automatic logic load_next_c = '0;
+        if(field_storage.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.value) begin // HW Write - we
+            next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.value;
+            load_next_c = '1;
+        end else if(hwif_in.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts.hwset) begin // HW Set
+            next_c = '1;
+            load_next_c = '1;
+        end
+        if(field_storage.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.value) begin // decrement
+            field_combo.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.underflow = (next_c < ('h1));
+            next_c = next_c - 'h1;
+            load_next_c = '1;
+        end else begin
+            field_combo.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.underflow = '0;
+        end
+        field_combo.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.value <= 'd0);
+        field_combo.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.next = next_c;
+        field_combo.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.load_next = load_next_c;
+    end
+    always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+        if(~hwif_in.cptra_rst_b) begin
+            field_storage.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.value <= 'h0;
+        end else if(field_combo.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.load_next) begin
+            field_storage.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.next;
+        end
+    end
     // Field: soc_ifc_reg.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse
     always_comb begin
         automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.value;
@@ -4179,6 +5384,35 @@ module soc_ifc_reg (
             field_storage.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.next;
         end
     end
+    // Field: soc_ifc_reg.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse
+    always_comb begin
+        automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.value;
+        automatic logic load_next_c = '0;
+        if(field_storage.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.value) begin // HW Write - we
+            next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.value;
+            load_next_c = '1;
+        end else if(hwif_in.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.hwset) begin // HW Set
+            next_c = '1;
+            load_next_c = '1;
+        end
+        if(field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.value) begin // decrement
+            field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.underflow = (next_c < ('h1));
+            next_c = next_c - 'h1;
+            load_next_c = '1;
+        end else begin
+            field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.underflow = '0;
+        end
+        field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.value <= 'd0);
+        field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.next = next_c;
+        field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.load_next = load_next_c;
+    end
+    always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+        if(~hwif_in.cptra_rst_b) begin
+            field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.value <= 'h0;
+        end else if(field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.load_next) begin
+            field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.next;
+        end
+    end
     //--------------------------------------------------------------------------
     // Readback
     //--------------------------------------------------------------------------
@@ -4187,9 +5421,15 @@ module soc_ifc_reg (
     logic [31:0] readback_data;
     
     // Assign readback values to a flattened array
-    logic [162-1:0][31:0] readback_array;
-    assign readback_array[0][31:0] = (decoded_reg_strb.CPTRA_HW_ERROR_FATAL && !decoded_req_is_wr) ? field_storage.CPTRA_HW_ERROR_FATAL.error_code.value : '0;
-    assign readback_array[1][31:0] = (decoded_reg_strb.CPTRA_HW_ERROR_NON_FATAL && !decoded_req_is_wr) ? field_storage.CPTRA_HW_ERROR_NON_FATAL.error_code.value : '0;
+    logic [186-1:0][31:0] readback_array;
+    assign readback_array[0][0:0] = (decoded_reg_strb.CPTRA_HW_ERROR_FATAL && !decoded_req_is_wr) ? field_storage.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.value : '0;
+    assign readback_array[0][1:1] = (decoded_reg_strb.CPTRA_HW_ERROR_FATAL && !decoded_req_is_wr) ? field_storage.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.value : '0;
+    assign readback_array[0][2:2] = (decoded_reg_strb.CPTRA_HW_ERROR_FATAL && !decoded_req_is_wr) ? field_storage.CPTRA_HW_ERROR_FATAL.nmi_pin.value : '0;
+    assign readback_array[0][31:3] = '0;
+    assign readback_array[1][0:0] = (decoded_reg_strb.CPTRA_HW_ERROR_NON_FATAL && !decoded_req_is_wr) ? field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.value : '0;
+    assign readback_array[1][1:1] = (decoded_reg_strb.CPTRA_HW_ERROR_NON_FATAL && !decoded_req_is_wr) ? field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo.value : '0;
+    assign readback_array[1][2:2] = (decoded_reg_strb.CPTRA_HW_ERROR_NON_FATAL && !decoded_req_is_wr) ? field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc.value : '0;
+    assign readback_array[1][31:3] = '0;
     assign readback_array[2][31:0] = (decoded_reg_strb.CPTRA_FW_ERROR_FATAL && !decoded_req_is_wr) ? field_storage.CPTRA_FW_ERROR_FATAL.error_code.value : '0;
     assign readback_array[3][31:0] = (decoded_reg_strb.CPTRA_FW_ERROR_NON_FATAL && !decoded_req_is_wr) ? field_storage.CPTRA_FW_ERROR_NON_FATAL.error_code.value : '0;
     assign readback_array[4][31:0] = (decoded_reg_strb.CPTRA_HW_ERROR_ENC && !decoded_req_is_wr) ? field_storage.CPTRA_HW_ERROR_ENC.error_code.value : '0;
@@ -4198,10 +5438,12 @@ module soc_ifc_reg (
         assign readback_array[i0*1 + 6][31:0] = (decoded_reg_strb.CPTRA_FW_EXTENDED_ERROR_INFO[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_FW_EXTENDED_ERROR_INFO[i0].error_info.value : '0;
     end
     assign readback_array[14][31:0] = (decoded_reg_strb.CPTRA_BOOT_STATUS && !decoded_req_is_wr) ? field_storage.CPTRA_BOOT_STATUS.status.value : '0;
-    assign readback_array[15][27:0] = (decoded_reg_strb.CPTRA_FLOW_STATUS && !decoded_req_is_wr) ? field_storage.CPTRA_FLOW_STATUS.status.value : '0;
+    assign readback_array[15][23:0] = (decoded_reg_strb.CPTRA_FLOW_STATUS && !decoded_req_is_wr) ? field_storage.CPTRA_FLOW_STATUS.status.value : '0;
+    assign readback_array[15][24:24] = (decoded_reg_strb.CPTRA_FLOW_STATUS && !decoded_req_is_wr) ? field_storage.CPTRA_FLOW_STATUS.idevid_csr_ready.value : '0;
+    assign readback_array[15][27:25] = (decoded_reg_strb.CPTRA_FLOW_STATUS && !decoded_req_is_wr) ? hwif_in.CPTRA_FLOW_STATUS.boot_fsm_ps.next : '0;
     assign readback_array[15][28:28] = (decoded_reg_strb.CPTRA_FLOW_STATUS && !decoded_req_is_wr) ? field_storage.CPTRA_FLOW_STATUS.ready_for_fw.value : '0;
     assign readback_array[15][29:29] = (decoded_reg_strb.CPTRA_FLOW_STATUS && !decoded_req_is_wr) ? field_storage.CPTRA_FLOW_STATUS.ready_for_runtime.value : '0;
-    assign readback_array[15][30:30] = (decoded_reg_strb.CPTRA_FLOW_STATUS && !decoded_req_is_wr) ? field_storage.CPTRA_FLOW_STATUS.ready_for_fuses.value : '0;
+    assign readback_array[15][30:30] = (decoded_reg_strb.CPTRA_FLOW_STATUS && !decoded_req_is_wr) ? hwif_in.CPTRA_FLOW_STATUS.ready_for_fuses.next : '0;
     assign readback_array[15][31:31] = (decoded_reg_strb.CPTRA_FLOW_STATUS && !decoded_req_is_wr) ? field_storage.CPTRA_FLOW_STATUS.mailbox_flow_done.value : '0;
     assign readback_array[16][0:0] = (decoded_reg_strb.CPTRA_RESET_REASON && !decoded_req_is_wr) ? field_storage.CPTRA_RESET_REASON.FW_UPD_RESET.value : '0;
     assign readback_array[16][1:1] = (decoded_reg_strb.CPTRA_RESET_REASON && !decoded_req_is_wr) ? field_storage.CPTRA_RESET_REASON.WARM_RESET.value : '0;
@@ -4223,163 +5465,210 @@ module soc_ifc_reg (
     for(genvar i0=0; i0<12; i0++) begin
         assign readback_array[i0*1 + 30][31:0] = (decoded_reg_strb.CPTRA_TRNG_DATA[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_TRNG_DATA[i0].DATA.value : '0;
     end
-    assign readback_array[42][0:0] = (decoded_reg_strb.CPTRA_TRNG_STATUS && !decoded_req_is_wr) ? field_storage.CPTRA_TRNG_STATUS.DATA_REQ.value : '0;
-    assign readback_array[42][1:1] = (decoded_reg_strb.CPTRA_TRNG_STATUS && !decoded_req_is_wr) ? field_storage.CPTRA_TRNG_STATUS.DATA_WR_DONE.value : '0;
-    assign readback_array[42][31:2] = '0;
-    assign readback_array[43][0:0] = (decoded_reg_strb.CPTRA_FUSE_WR_DONE && !decoded_req_is_wr) ? field_storage.CPTRA_FUSE_WR_DONE.done.value : '0;
-    assign readback_array[43][31:1] = '0;
-    assign readback_array[44][31:0] = (decoded_reg_strb.CPTRA_TIMER_CONFIG && !decoded_req_is_wr) ? field_storage.CPTRA_TIMER_CONFIG.clk_period.value : '0;
-    assign readback_array[45][0:0] = (decoded_reg_strb.CPTRA_BOOTFSM_GO && !decoded_req_is_wr) ? field_storage.CPTRA_BOOTFSM_GO.GO.value : '0;
-    assign readback_array[45][31:1] = '0;
-    assign readback_array[46][31:0] = (decoded_reg_strb.CPTRA_DBG_MANUF_SERVICE_REG && !decoded_req_is_wr) ? field_storage.CPTRA_DBG_MANUF_SERVICE_REG.DATA.value : '0;
-    assign readback_array[47][0:0] = (decoded_reg_strb.CPTRA_CLK_GATING_EN && !decoded_req_is_wr) ? field_storage.CPTRA_CLK_GATING_EN.clk_gating_en.value : '0;
-    assign readback_array[47][31:1] = '0;
+    assign readback_array[42][0:0] = (decoded_reg_strb.CPTRA_TRNG_CTRL && !decoded_req_is_wr) ? field_storage.CPTRA_TRNG_CTRL.clear.value : '0;
+    assign readback_array[42][31:1] = '0;
+    assign readback_array[43][0:0] = (decoded_reg_strb.CPTRA_TRNG_STATUS && !decoded_req_is_wr) ? field_storage.CPTRA_TRNG_STATUS.DATA_REQ.value : '0;
+    assign readback_array[43][1:1] = (decoded_reg_strb.CPTRA_TRNG_STATUS && !decoded_req_is_wr) ? field_storage.CPTRA_TRNG_STATUS.DATA_WR_DONE.value : '0;
+    assign readback_array[43][31:2] = '0;
+    assign readback_array[44][0:0] = (decoded_reg_strb.CPTRA_FUSE_WR_DONE && !decoded_req_is_wr) ? field_storage.CPTRA_FUSE_WR_DONE.done.value : '0;
+    assign readback_array[44][31:1] = '0;
+    assign readback_array[45][31:0] = (decoded_reg_strb.CPTRA_TIMER_CONFIG && !decoded_req_is_wr) ? field_storage.CPTRA_TIMER_CONFIG.clk_period.value : '0;
+    assign readback_array[46][0:0] = (decoded_reg_strb.CPTRA_BOOTFSM_GO && !decoded_req_is_wr) ? field_storage.CPTRA_BOOTFSM_GO.GO.value : '0;
+    assign readback_array[46][31:1] = '0;
+    assign readback_array[47][31:0] = (decoded_reg_strb.CPTRA_DBG_MANUF_SERVICE_REG && !decoded_req_is_wr) ? field_storage.CPTRA_DBG_MANUF_SERVICE_REG.DATA.value : '0;
+    assign readback_array[48][0:0] = (decoded_reg_strb.CPTRA_CLK_GATING_EN && !decoded_req_is_wr) ? field_storage.CPTRA_CLK_GATING_EN.clk_gating_en.value : '0;
+    assign readback_array[48][31:1] = '0;
     for(genvar i0=0; i0<2; i0++) begin
-        assign readback_array[i0*1 + 48][31:0] = (decoded_reg_strb.CPTRA_GENERIC_INPUT_WIRES[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_GENERIC_INPUT_WIRES[i0].generic_wires.value : '0;
+        assign readback_array[i0*1 + 49][31:0] = (decoded_reg_strb.CPTRA_GENERIC_INPUT_WIRES[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_GENERIC_INPUT_WIRES[i0].generic_wires.value : '0;
     end
     for(genvar i0=0; i0<2; i0++) begin
-        assign readback_array[i0*1 + 50][31:0] = (decoded_reg_strb.CPTRA_GENERIC_OUTPUT_WIRES[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_GENERIC_OUTPUT_WIRES[i0].generic_wires.value : '0;
+        assign readback_array[i0*1 + 51][31:0] = (decoded_reg_strb.CPTRA_GENERIC_OUTPUT_WIRES[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_GENERIC_OUTPUT_WIRES[i0].generic_wires.value : '0;
     end
-    assign readback_array[52][31:0] = (decoded_reg_strb.CPTRA_HW_REV_ID && !decoded_req_is_wr) ? 'h1 : '0;
+    assign readback_array[53][15:0] = (decoded_reg_strb.CPTRA_HW_REV_ID && !decoded_req_is_wr) ? 'h1 : '0;
+    assign readback_array[53][31:16] = (decoded_reg_strb.CPTRA_HW_REV_ID && !decoded_req_is_wr) ? hwif_in.CPTRA_HW_REV_ID.SOC_STEPPING_ID.next : '0;
     for(genvar i0=0; i0<2; i0++) begin
-        assign readback_array[i0*1 + 53][31:0] = (decoded_reg_strb.CPTRA_FW_REV_ID[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_FW_REV_ID[i0].REV_ID.value : '0;
-    end
-    assign readback_array[55][0:0] = (decoded_reg_strb.CPTRA_HW_CONFIG && !decoded_req_is_wr) ? hwif_in.CPTRA_HW_CONFIG.iTRNG_en.next : '0;
-    assign readback_array[55][1:1] = (decoded_reg_strb.CPTRA_HW_CONFIG && !decoded_req_is_wr) ? hwif_in.CPTRA_HW_CONFIG.QSPI_en.next : '0;
-    assign readback_array[55][2:2] = (decoded_reg_strb.CPTRA_HW_CONFIG && !decoded_req_is_wr) ? hwif_in.CPTRA_HW_CONFIG.I3C_en.next : '0;
-    assign readback_array[55][3:3] = (decoded_reg_strb.CPTRA_HW_CONFIG && !decoded_req_is_wr) ? hwif_in.CPTRA_HW_CONFIG.UART_en.next : '0;
-    assign readback_array[55][31:4] = '0;
-    assign readback_array[56][0:0] = (decoded_reg_strb.CPTRA_WDT_TIMER1_EN && !decoded_req_is_wr) ? field_storage.CPTRA_WDT_TIMER1_EN.timer1_en.value : '0;
-    assign readback_array[56][31:1] = '0;
-    assign readback_array[57][0:0] = (decoded_reg_strb.CPTRA_WDT_TIMER1_CTRL && !decoded_req_is_wr) ? field_storage.CPTRA_WDT_TIMER1_CTRL.timer1_restart.value : '0;
+        assign readback_array[i0*1 + 54][31:0] = (decoded_reg_strb.CPTRA_FW_REV_ID[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_FW_REV_ID[i0].REV_ID.value : '0;
+    end
+    assign readback_array[56][0:0] = (decoded_reg_strb.CPTRA_HW_CONFIG && !decoded_req_is_wr) ? hwif_in.CPTRA_HW_CONFIG.iTRNG_en.next : '0;
+    assign readback_array[56][1:1] = (decoded_reg_strb.CPTRA_HW_CONFIG && !decoded_req_is_wr) ? hwif_in.CPTRA_HW_CONFIG.QSPI_en.next : '0;
+    assign readback_array[56][2:2] = (decoded_reg_strb.CPTRA_HW_CONFIG && !decoded_req_is_wr) ? hwif_in.CPTRA_HW_CONFIG.I3C_en.next : '0;
+    assign readback_array[56][3:3] = (decoded_reg_strb.CPTRA_HW_CONFIG && !decoded_req_is_wr) ? hwif_in.CPTRA_HW_CONFIG.UART_en.next : '0;
+    assign readback_array[56][31:4] = '0;
+    assign readback_array[57][0:0] = (decoded_reg_strb.CPTRA_WDT_TIMER1_EN && !decoded_req_is_wr) ? field_storage.CPTRA_WDT_TIMER1_EN.timer1_en.value : '0;
     assign readback_array[57][31:1] = '0;
+    assign readback_array[58][0:0] = (decoded_reg_strb.CPTRA_WDT_TIMER1_CTRL && !decoded_req_is_wr) ? field_storage.CPTRA_WDT_TIMER1_CTRL.timer1_restart.value : '0;
+    assign readback_array[58][31:1] = '0;
     for(genvar i0=0; i0<2; i0++) begin
-        assign readback_array[i0*1 + 58][31:0] = (decoded_reg_strb.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i0].timer1_timeout_period.value : '0;
+        assign readback_array[i0*1 + 59][31:0] = (decoded_reg_strb.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i0].timer1_timeout_period.value : '0;
     end
-    assign readback_array[60][0:0] = (decoded_reg_strb.CPTRA_WDT_TIMER2_EN && !decoded_req_is_wr) ? field_storage.CPTRA_WDT_TIMER2_EN.timer2_en.value : '0;
-    assign readback_array[60][31:1] = '0;
-    assign readback_array[61][0:0] = (decoded_reg_strb.CPTRA_WDT_TIMER2_CTRL && !decoded_req_is_wr) ? field_storage.CPTRA_WDT_TIMER2_CTRL.timer2_restart.value : '0;
+    assign readback_array[61][0:0] = (decoded_reg_strb.CPTRA_WDT_TIMER2_EN && !decoded_req_is_wr) ? field_storage.CPTRA_WDT_TIMER2_EN.timer2_en.value : '0;
     assign readback_array[61][31:1] = '0;
+    assign readback_array[62][0:0] = (decoded_reg_strb.CPTRA_WDT_TIMER2_CTRL && !decoded_req_is_wr) ? field_storage.CPTRA_WDT_TIMER2_CTRL.timer2_restart.value : '0;
+    assign readback_array[62][31:1] = '0;
+    for(genvar i0=0; i0<2; i0++) begin
+        assign readback_array[i0*1 + 63][31:0] = (decoded_reg_strb.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i0].timer2_timeout_period.value : '0;
+    end
+    assign readback_array[65][0:0] = (decoded_reg_strb.CPTRA_WDT_STATUS && !decoded_req_is_wr) ? field_storage.CPTRA_WDT_STATUS.t1_timeout.value : '0;
+    assign readback_array[65][1:1] = (decoded_reg_strb.CPTRA_WDT_STATUS && !decoded_req_is_wr) ? field_storage.CPTRA_WDT_STATUS.t2_timeout.value : '0;
+    assign readback_array[65][31:2] = '0;
+    assign readback_array[66][31:0] = (decoded_reg_strb.CPTRA_FUSE_VALID_PAUSER && !decoded_req_is_wr) ? field_storage.CPTRA_FUSE_VALID_PAUSER.PAUSER.value : '0;
+    assign readback_array[67][0:0] = (decoded_reg_strb.CPTRA_FUSE_PAUSER_LOCK && !decoded_req_is_wr) ? field_storage.CPTRA_FUSE_PAUSER_LOCK.LOCK.value : '0;
+    assign readback_array[67][31:1] = '0;
     for(genvar i0=0; i0<2; i0++) begin
-        assign readback_array[i0*1 + 62][31:0] = (decoded_reg_strb.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i0].timer2_timeout_period.value : '0;
+        assign readback_array[i0*1 + 68][31:0] = (decoded_reg_strb.CPTRA_WDT_CFG[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_WDT_CFG[i0].TIMEOUT.value : '0;
+    end
+    assign readback_array[70][15:0] = (decoded_reg_strb.CPTRA_iTRNG_ENTROPY_CONFIG_0 && !decoded_req_is_wr) ? field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_0.low_threshold.value : '0;
+    assign readback_array[70][31:16] = (decoded_reg_strb.CPTRA_iTRNG_ENTROPY_CONFIG_0 && !decoded_req_is_wr) ? field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_0.high_threshold.value : '0;
+    assign readback_array[71][15:0] = (decoded_reg_strb.CPTRA_iTRNG_ENTROPY_CONFIG_1 && !decoded_req_is_wr) ? field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_1.repetition_count.value : '0;
+    assign readback_array[71][31:16] = (decoded_reg_strb.CPTRA_iTRNG_ENTROPY_CONFIG_1 && !decoded_req_is_wr) ? field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_1.RSVD.value : '0;
+    for(genvar i0=0; i0<2; i0++) begin
+        assign readback_array[i0*1 + 72][31:0] = (decoded_reg_strb.CPTRA_RSVD_REG[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_RSVD_REG[i0].RSVD.value : '0;
     end
-    assign readback_array[64][0:0] = (decoded_reg_strb.CPTRA_WDT_STATUS && !decoded_req_is_wr) ? field_storage.CPTRA_WDT_STATUS.t1_timeout.value : '0;
-    assign readback_array[64][1:1] = (decoded_reg_strb.CPTRA_WDT_STATUS && !decoded_req_is_wr) ? field_storage.CPTRA_WDT_STATUS.t2_timeout.value : '0;
-    assign readback_array[64][31:2] = '0;
     for(genvar i0=0; i0<12; i0++) begin
-        assign readback_array[i0*1 + 65][31:0] = (decoded_reg_strb.fuse_key_manifest_pk_hash[i0] && !decoded_req_is_wr) ? field_storage.fuse_key_manifest_pk_hash[i0].hash.value : '0;
+        assign readback_array[i0*1 + 74][31:0] = (decoded_reg_strb.fuse_key_manifest_pk_hash[i0] && !decoded_req_is_wr) ? field_storage.fuse_key_manifest_pk_hash[i0].hash.value : '0;
     end
-    assign readback_array[77][3:0] = (decoded_reg_strb.fuse_key_manifest_pk_hash_mask && !decoded_req_is_wr) ? field_storage.fuse_key_manifest_pk_hash_mask.mask.value : '0;
-    assign readback_array[77][31:4] = '0;
+    assign readback_array[86][3:0] = (decoded_reg_strb.fuse_key_manifest_pk_hash_mask && !decoded_req_is_wr) ? field_storage.fuse_key_manifest_pk_hash_mask.mask.value : '0;
+    assign readback_array[86][31:4] = '0;
     for(genvar i0=0; i0<12; i0++) begin
-        assign readback_array[i0*1 + 78][31:0] = (decoded_reg_strb.fuse_owner_pk_hash[i0] && !decoded_req_is_wr) ? field_storage.fuse_owner_pk_hash[i0].hash.value : '0;
+        assign readback_array[i0*1 + 87][31:0] = (decoded_reg_strb.fuse_owner_pk_hash[i0] && !decoded_req_is_wr) ? field_storage.fuse_owner_pk_hash[i0].hash.value : '0;
     end
-    assign readback_array[90][31:0] = (decoded_reg_strb.fuse_fmc_key_manifest_svn && !decoded_req_is_wr) ? field_storage.fuse_fmc_key_manifest_svn.svn.value : '0;
+    assign readback_array[99][31:0] = (decoded_reg_strb.fuse_fmc_key_manifest_svn && !decoded_req_is_wr) ? field_storage.fuse_fmc_key_manifest_svn.svn.value : '0;
     for(genvar i0=0; i0<4; i0++) begin
-        assign readback_array[i0*1 + 91][31:0] = (decoded_reg_strb.fuse_runtime_svn[i0] && !decoded_req_is_wr) ? field_storage.fuse_runtime_svn[i0].svn.value : '0;
+        assign readback_array[i0*1 + 100][31:0] = (decoded_reg_strb.fuse_runtime_svn[i0] && !decoded_req_is_wr) ? field_storage.fuse_runtime_svn[i0].svn.value : '0;
     end
-    assign readback_array[95][0:0] = (decoded_reg_strb.fuse_anti_rollback_disable && !decoded_req_is_wr) ? field_storage.fuse_anti_rollback_disable.dis.value : '0;
-    assign readback_array[95][31:1] = '0;
+    assign readback_array[104][0:0] = (decoded_reg_strb.fuse_anti_rollback_disable && !decoded_req_is_wr) ? field_storage.fuse_anti_rollback_disable.dis.value : '0;
+    assign readback_array[104][31:1] = '0;
     for(genvar i0=0; i0<24; i0++) begin
-        assign readback_array[i0*1 + 96][31:0] = (decoded_reg_strb.fuse_idevid_cert_attr[i0] && !decoded_req_is_wr) ? field_storage.fuse_idevid_cert_attr[i0].cert.value : '0;
+        assign readback_array[i0*1 + 105][31:0] = (decoded_reg_strb.fuse_idevid_cert_attr[i0] && !decoded_req_is_wr) ? field_storage.fuse_idevid_cert_attr[i0].cert.value : '0;
     end
     for(genvar i0=0; i0<4; i0++) begin
-        assign readback_array[i0*1 + 120][31:0] = (decoded_reg_strb.fuse_idevid_manuf_hsm_id[i0] && !decoded_req_is_wr) ? field_storage.fuse_idevid_manuf_hsm_id[i0].hsm_id.value : '0;
-    end
-    assign readback_array[124][1:0] = (decoded_reg_strb.fuse_life_cycle && !decoded_req_is_wr) ? field_storage.fuse_life_cycle.life_cycle.value : '0;
-    assign readback_array[124][31:2] = '0;
-    assign readback_array[125][0:0] = (decoded_reg_strb.internal_iccm_lock && !decoded_req_is_wr) ? field_storage.internal_iccm_lock.lock.value : '0;
-    assign readback_array[125][31:1] = '0;
-    assign readback_array[126][0:0] = (decoded_reg_strb.internal_fw_update_reset && !decoded_req_is_wr) ? field_storage.internal_fw_update_reset.core_rst.value : '0;
-    assign readback_array[126][31:1] = '0;
-    assign readback_array[127][7:0] = (decoded_reg_strb.internal_fw_update_reset_wait_cycles && !decoded_req_is_wr) ? field_storage.internal_fw_update_reset_wait_cycles.wait_cycles.value : '0;
-    assign readback_array[127][31:8] = '0;
-    assign readback_array[128][31:0] = (decoded_reg_strb.internal_nmi_vector && !decoded_req_is_wr) ? field_storage.internal_nmi_vector.vec.value : '0;
-    assign readback_array[129][0:0] = (decoded_reg_strb.intr_block_rf.global_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.global_intr_en_r.error_en.value : '0;
-    assign readback_array[129][1:1] = (decoded_reg_strb.intr_block_rf.global_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.global_intr_en_r.notif_en.value : '0;
-    assign readback_array[129][31:2] = '0;
-    assign readback_array[130][0:0] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value : '0;
-    assign readback_array[130][1:1] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_inv_dev_en.value : '0;
-    assign readback_array[130][2:2] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_cmd_fail_en.value : '0;
-    assign readback_array[130][3:3] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_bad_fuse_en.value : '0;
-    assign readback_array[130][4:4] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_iccm_blocked_en.value : '0;
-    assign readback_array[130][5:5] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_mbox_ecc_unc_en.value : '0;
-    assign readback_array[130][6:6] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer1_timeout_en.value : '0;
-    assign readback_array[130][7:7] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer2_timeout_en.value : '0;
-    assign readback_array[130][31:8] = '0;
-    assign readback_array[131][0:0] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_avail_en.value : '0;
-    assign readback_array[131][1:1] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_mbox_ecc_cor_en.value : '0;
-    assign readback_array[131][2:2] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_debug_locked_en.value : '0;
-    assign readback_array[131][3:3] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_soc_req_lock_en.value : '0;
-    assign readback_array[131][31:4] = '0;
-    assign readback_array[132][0:0] = (decoded_reg_strb.intr_block_rf.error_global_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_global_intr_r.agg_sts.value : '0;
-    assign readback_array[132][31:1] = '0;
-    assign readback_array[133][0:0] = (decoded_reg_strb.intr_block_rf.notif_global_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value : '0;
-    assign readback_array[133][31:1] = '0;
-    assign readback_array[134][0:0] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value : '0;
-    assign readback_array[134][1:1] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_inv_dev_sts.value : '0;
-    assign readback_array[134][2:2] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_cmd_fail_sts.value : '0;
-    assign readback_array[134][3:3] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_bad_fuse_sts.value : '0;
-    assign readback_array[134][4:4] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_iccm_blocked_sts.value : '0;
-    assign readback_array[134][5:5] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_mbox_ecc_unc_sts.value : '0;
-    assign readback_array[134][6:6] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer1_timeout_sts.value : '0;
-    assign readback_array[134][7:7] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer2_timeout_sts.value : '0;
-    assign readback_array[134][31:8] = '0;
-    assign readback_array[135][0:0] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_avail_sts.value : '0;
-    assign readback_array[135][1:1] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_mbox_ecc_cor_sts.value : '0;
-    assign readback_array[135][2:2] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_debug_locked_sts.value : '0;
-    assign readback_array[135][3:3] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_soc_req_lock_sts.value : '0;
-    assign readback_array[135][31:4] = '0;
-    assign readback_array[136][0:0] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value : '0;
-    assign readback_array[136][1:1] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_inv_dev_trig.value : '0;
-    assign readback_array[136][2:2] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_cmd_fail_trig.value : '0;
-    assign readback_array[136][3:3] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_bad_fuse_trig.value : '0;
-    assign readback_array[136][4:4] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_iccm_blocked_trig.value : '0;
-    assign readback_array[136][5:5] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_mbox_ecc_unc_trig.value : '0;
-    assign readback_array[136][6:6] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer1_timeout_trig.value : '0;
-    assign readback_array[136][7:7] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer2_timeout_trig.value : '0;
-    assign readback_array[136][31:8] = '0;
-    assign readback_array[137][0:0] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_avail_trig.value : '0;
-    assign readback_array[137][1:1] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_mbox_ecc_cor_trig.value : '0;
-    assign readback_array[137][2:2] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_debug_locked_trig.value : '0;
-    assign readback_array[137][3:3] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.value : '0;
-    assign readback_array[137][31:4] = '0;
-    assign readback_array[138][31:0] = (decoded_reg_strb.intr_block_rf.error_internal_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value : '0;
-    assign readback_array[139][31:0] = (decoded_reg_strb.intr_block_rf.error_inv_dev_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_inv_dev_intr_count_r.cnt.value : '0;
-    assign readback_array[140][31:0] = (decoded_reg_strb.intr_block_rf.error_cmd_fail_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_cmd_fail_intr_count_r.cnt.value : '0;
-    assign readback_array[141][31:0] = (decoded_reg_strb.intr_block_rf.error_bad_fuse_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_bad_fuse_intr_count_r.cnt.value : '0;
-    assign readback_array[142][31:0] = (decoded_reg_strb.intr_block_rf.error_iccm_blocked_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.value : '0;
-    assign readback_array[143][31:0] = (decoded_reg_strb.intr_block_rf.error_mbox_ecc_unc_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.value : '0;
-    assign readback_array[144][31:0] = (decoded_reg_strb.intr_block_rf.error_wdt_timer1_timeout_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.value : '0;
-    assign readback_array[145][31:0] = (decoded_reg_strb.intr_block_rf.error_wdt_timer2_timeout_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.value : '0;
-    assign readback_array[146][31:0] = (decoded_reg_strb.intr_block_rf.notif_cmd_avail_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.value : '0;
-    assign readback_array[147][31:0] = (decoded_reg_strb.intr_block_rf.notif_mbox_ecc_cor_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.value : '0;
-    assign readback_array[148][31:0] = (decoded_reg_strb.intr_block_rf.notif_debug_locked_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_debug_locked_intr_count_r.cnt.value : '0;
-    assign readback_array[149][31:0] = (decoded_reg_strb.intr_block_rf.notif_soc_req_lock_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.value : '0;
-    assign readback_array[150][0:0] = (decoded_reg_strb.intr_block_rf.error_internal_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value : '0;
-    assign readback_array[150][31:1] = '0;
-    assign readback_array[151][0:0] = (decoded_reg_strb.intr_block_rf.error_inv_dev_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.value : '0;
-    assign readback_array[151][31:1] = '0;
-    assign readback_array[152][0:0] = (decoded_reg_strb.intr_block_rf.error_cmd_fail_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.value : '0;
+        assign readback_array[i0*1 + 129][31:0] = (decoded_reg_strb.fuse_idevid_manuf_hsm_id[i0] && !decoded_req_is_wr) ? field_storage.fuse_idevid_manuf_hsm_id[i0].hsm_id.value : '0;
+    end
+    assign readback_array[133][1:0] = (decoded_reg_strb.fuse_life_cycle && !decoded_req_is_wr) ? field_storage.fuse_life_cycle.life_cycle.value : '0;
+    assign readback_array[133][31:2] = '0;
+    assign readback_array[134][0:0] = (decoded_reg_strb.fuse_lms_verify && !decoded_req_is_wr) ? field_storage.fuse_lms_verify.lms_verify.value : '0;
+    assign readback_array[134][31:1] = '0;
+    assign readback_array[135][31:0] = (decoded_reg_strb.fuse_lms_revocation && !decoded_req_is_wr) ? field_storage.fuse_lms_revocation.lms_revocation.value : '0;
+    assign readback_array[136][15:0] = (decoded_reg_strb.fuse_soc_stepping_id && !decoded_req_is_wr) ? field_storage.fuse_soc_stepping_id.soc_stepping_id.value : '0;
+    assign readback_array[136][31:16] = '0;
+    assign readback_array[137][0:0] = (decoded_reg_strb.internal_iccm_lock && !decoded_req_is_wr) ? field_storage.internal_iccm_lock.lock.value : '0;
+    assign readback_array[137][31:1] = '0;
+    assign readback_array[138][0:0] = (decoded_reg_strb.internal_fw_update_reset && !decoded_req_is_wr) ? field_storage.internal_fw_update_reset.core_rst.value : '0;
+    assign readback_array[138][31:1] = '0;
+    assign readback_array[139][7:0] = (decoded_reg_strb.internal_fw_update_reset_wait_cycles && !decoded_req_is_wr) ? field_storage.internal_fw_update_reset_wait_cycles.wait_cycles.value : '0;
+    assign readback_array[139][31:8] = '0;
+    assign readback_array[140][31:0] = (decoded_reg_strb.internal_nmi_vector && !decoded_req_is_wr) ? field_storage.internal_nmi_vector.vec.value : '0;
+    assign readback_array[141][0:0] = (decoded_reg_strb.internal_hw_error_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_fatal_mask.mask_iccm_ecc_unc.value : '0;
+    assign readback_array[141][1:1] = (decoded_reg_strb.internal_hw_error_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_fatal_mask.mask_dccm_ecc_unc.value : '0;
+    assign readback_array[141][2:2] = (decoded_reg_strb.internal_hw_error_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_fatal_mask.mask_nmi_pin.value : '0;
+    assign readback_array[141][31:3] = '0;
+    assign readback_array[142][0:0] = (decoded_reg_strb.internal_hw_error_non_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock.value : '0;
+    assign readback_array[142][1:1] = (decoded_reg_strb.internal_hw_error_non_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo.value : '0;
+    assign readback_array[142][2:2] = (decoded_reg_strb.internal_hw_error_non_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc.value : '0;
+    assign readback_array[142][31:3] = '0;
+    assign readback_array[143][31:0] = (decoded_reg_strb.internal_fw_error_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_fw_error_fatal_mask.mask.value : '0;
+    assign readback_array[144][31:0] = (decoded_reg_strb.internal_fw_error_non_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_fw_error_non_fatal_mask.mask.value : '0;
+    assign readback_array[145][31:0] = (decoded_reg_strb.internal_rv_mtime_l && !decoded_req_is_wr) ? field_storage.internal_rv_mtime_l.count_l.value : '0;
+    assign readback_array[146][31:0] = (decoded_reg_strb.internal_rv_mtime_h && !decoded_req_is_wr) ? field_storage.internal_rv_mtime_h.count_h.value : '0;
+    assign readback_array[147][31:0] = (decoded_reg_strb.internal_rv_mtimecmp_l && !decoded_req_is_wr) ? field_storage.internal_rv_mtimecmp_l.compare_l.value : '0;
+    assign readback_array[148][31:0] = (decoded_reg_strb.internal_rv_mtimecmp_h && !decoded_req_is_wr) ? field_storage.internal_rv_mtimecmp_h.compare_h.value : '0;
+    assign readback_array[149][0:0] = (decoded_reg_strb.intr_block_rf.global_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.global_intr_en_r.error_en.value : '0;
+    assign readback_array[149][1:1] = (decoded_reg_strb.intr_block_rf.global_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.global_intr_en_r.notif_en.value : '0;
+    assign readback_array[149][31:2] = '0;
+    assign readback_array[150][0:0] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value : '0;
+    assign readback_array[150][1:1] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_inv_dev_en.value : '0;
+    assign readback_array[150][2:2] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_cmd_fail_en.value : '0;
+    assign readback_array[150][3:3] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_bad_fuse_en.value : '0;
+    assign readback_array[150][4:4] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_iccm_blocked_en.value : '0;
+    assign readback_array[150][5:5] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_mbox_ecc_unc_en.value : '0;
+    assign readback_array[150][6:6] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer1_timeout_en.value : '0;
+    assign readback_array[150][7:7] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer2_timeout_en.value : '0;
+    assign readback_array[150][31:8] = '0;
+    assign readback_array[151][0:0] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_avail_en.value : '0;
+    assign readback_array[151][1:1] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_mbox_ecc_cor_en.value : '0;
+    assign readback_array[151][2:2] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_debug_locked_en.value : '0;
+    assign readback_array[151][3:3] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_scan_mode_en.value : '0;
+    assign readback_array[151][4:4] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_soc_req_lock_en.value : '0;
+    assign readback_array[151][5:5] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_gen_in_toggle_en.value : '0;
+    assign readback_array[151][31:6] = '0;
+    assign readback_array[152][0:0] = (decoded_reg_strb.intr_block_rf.error_global_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_global_intr_r.agg_sts.value : '0;
     assign readback_array[152][31:1] = '0;
-    assign readback_array[153][0:0] = (decoded_reg_strb.intr_block_rf.error_bad_fuse_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.value : '0;
+    assign readback_array[153][0:0] = (decoded_reg_strb.intr_block_rf.notif_global_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value : '0;
     assign readback_array[153][31:1] = '0;
-    assign readback_array[154][0:0] = (decoded_reg_strb.intr_block_rf.error_iccm_blocked_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.value : '0;
-    assign readback_array[154][31:1] = '0;
-    assign readback_array[155][0:0] = (decoded_reg_strb.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.value : '0;
-    assign readback_array[155][31:1] = '0;
-    assign readback_array[156][0:0] = (decoded_reg_strb.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.value : '0;
-    assign readback_array[156][31:1] = '0;
-    assign readback_array[157][0:0] = (decoded_reg_strb.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.value : '0;
-    assign readback_array[157][31:1] = '0;
-    assign readback_array[158][0:0] = (decoded_reg_strb.intr_block_rf.notif_cmd_avail_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.value : '0;
-    assign readback_array[158][31:1] = '0;
-    assign readback_array[159][0:0] = (decoded_reg_strb.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.value : '0;
-    assign readback_array[159][31:1] = '0;
-    assign readback_array[160][0:0] = (decoded_reg_strb.intr_block_rf.notif_debug_locked_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.value : '0;
-    assign readback_array[160][31:1] = '0;
-    assign readback_array[161][0:0] = (decoded_reg_strb.intr_block_rf.notif_soc_req_lock_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.value : '0;
-    assign readback_array[161][31:1] = '0;
+    assign readback_array[154][0:0] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value : '0;
+    assign readback_array[154][1:1] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_inv_dev_sts.value : '0;
+    assign readback_array[154][2:2] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_cmd_fail_sts.value : '0;
+    assign readback_array[154][3:3] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_bad_fuse_sts.value : '0;
+    assign readback_array[154][4:4] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_iccm_blocked_sts.value : '0;
+    assign readback_array[154][5:5] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_mbox_ecc_unc_sts.value : '0;
+    assign readback_array[154][6:6] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer1_timeout_sts.value : '0;
+    assign readback_array[154][7:7] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer2_timeout_sts.value : '0;
+    assign readback_array[154][31:8] = '0;
+    assign readback_array[155][0:0] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_avail_sts.value : '0;
+    assign readback_array[155][1:1] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_mbox_ecc_cor_sts.value : '0;
+    assign readback_array[155][2:2] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_debug_locked_sts.value : '0;
+    assign readback_array[155][3:3] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts.value : '0;
+    assign readback_array[155][4:4] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_soc_req_lock_sts.value : '0;
+    assign readback_array[155][5:5] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.value : '0;
+    assign readback_array[155][31:6] = '0;
+    assign readback_array[156][0:0] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value : '0;
+    assign readback_array[156][1:1] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_inv_dev_trig.value : '0;
+    assign readback_array[156][2:2] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_cmd_fail_trig.value : '0;
+    assign readback_array[156][3:3] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_bad_fuse_trig.value : '0;
+    assign readback_array[156][4:4] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_iccm_blocked_trig.value : '0;
+    assign readback_array[156][5:5] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_mbox_ecc_unc_trig.value : '0;
+    assign readback_array[156][6:6] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer1_timeout_trig.value : '0;
+    assign readback_array[156][7:7] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer2_timeout_trig.value : '0;
+    assign readback_array[156][31:8] = '0;
+    assign readback_array[157][0:0] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_avail_trig.value : '0;
+    assign readback_array[157][1:1] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_mbox_ecc_cor_trig.value : '0;
+    assign readback_array[157][2:2] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_debug_locked_trig.value : '0;
+    assign readback_array[157][3:3] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.value : '0;
+    assign readback_array[157][4:4] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.value : '0;
+    assign readback_array[157][5:5] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.value : '0;
+    assign readback_array[157][31:6] = '0;
+    assign readback_array[158][31:0] = (decoded_reg_strb.intr_block_rf.error_internal_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value : '0;
+    assign readback_array[159][31:0] = (decoded_reg_strb.intr_block_rf.error_inv_dev_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_inv_dev_intr_count_r.cnt.value : '0;
+    assign readback_array[160][31:0] = (decoded_reg_strb.intr_block_rf.error_cmd_fail_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_cmd_fail_intr_count_r.cnt.value : '0;
+    assign readback_array[161][31:0] = (decoded_reg_strb.intr_block_rf.error_bad_fuse_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_bad_fuse_intr_count_r.cnt.value : '0;
+    assign readback_array[162][31:0] = (decoded_reg_strb.intr_block_rf.error_iccm_blocked_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.value : '0;
+    assign readback_array[163][31:0] = (decoded_reg_strb.intr_block_rf.error_mbox_ecc_unc_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.value : '0;
+    assign readback_array[164][31:0] = (decoded_reg_strb.intr_block_rf.error_wdt_timer1_timeout_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.value : '0;
+    assign readback_array[165][31:0] = (decoded_reg_strb.intr_block_rf.error_wdt_timer2_timeout_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.value : '0;
+    assign readback_array[166][31:0] = (decoded_reg_strb.intr_block_rf.notif_cmd_avail_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.value : '0;
+    assign readback_array[167][31:0] = (decoded_reg_strb.intr_block_rf.notif_mbox_ecc_cor_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.value : '0;
+    assign readback_array[168][31:0] = (decoded_reg_strb.intr_block_rf.notif_debug_locked_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_debug_locked_intr_count_r.cnt.value : '0;
+    assign readback_array[169][31:0] = (decoded_reg_strb.intr_block_rf.notif_scan_mode_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_scan_mode_intr_count_r.cnt.value : '0;
+    assign readback_array[170][31:0] = (decoded_reg_strb.intr_block_rf.notif_soc_req_lock_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.value : '0;
+    assign readback_array[171][31:0] = (decoded_reg_strb.intr_block_rf.notif_gen_in_toggle_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.value : '0;
+    assign readback_array[172][0:0] = (decoded_reg_strb.intr_block_rf.error_internal_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value : '0;
+    assign readback_array[172][31:1] = '0;
+    assign readback_array[173][0:0] = (decoded_reg_strb.intr_block_rf.error_inv_dev_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.value : '0;
+    assign readback_array[173][31:1] = '0;
+    assign readback_array[174][0:0] = (decoded_reg_strb.intr_block_rf.error_cmd_fail_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.value : '0;
+    assign readback_array[174][31:1] = '0;
+    assign readback_array[175][0:0] = (decoded_reg_strb.intr_block_rf.error_bad_fuse_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.value : '0;
+    assign readback_array[175][31:1] = '0;
+    assign readback_array[176][0:0] = (decoded_reg_strb.intr_block_rf.error_iccm_blocked_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.value : '0;
+    assign readback_array[176][31:1] = '0;
+    assign readback_array[177][0:0] = (decoded_reg_strb.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.value : '0;
+    assign readback_array[177][31:1] = '0;
+    assign readback_array[178][0:0] = (decoded_reg_strb.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.value : '0;
+    assign readback_array[178][31:1] = '0;
+    assign readback_array[179][0:0] = (decoded_reg_strb.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.value : '0;
+    assign readback_array[179][31:1] = '0;
+    assign readback_array[180][0:0] = (decoded_reg_strb.intr_block_rf.notif_cmd_avail_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.value : '0;
+    assign readback_array[180][31:1] = '0;
+    assign readback_array[181][0:0] = (decoded_reg_strb.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.value : '0;
+    assign readback_array[181][31:1] = '0;
+    assign readback_array[182][0:0] = (decoded_reg_strb.intr_block_rf.notif_debug_locked_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.value : '0;
+    assign readback_array[182][31:1] = '0;
+    assign readback_array[183][0:0] = (decoded_reg_strb.intr_block_rf.notif_scan_mode_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.value : '0;
+    assign readback_array[183][31:1] = '0;
+    assign readback_array[184][0:0] = (decoded_reg_strb.intr_block_rf.notif_soc_req_lock_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.value : '0;
+    assign readback_array[184][31:1] = '0;
+    assign readback_array[185][0:0] = (decoded_reg_strb.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.value : '0;
+    assign readback_array[185][31:1] = '0;
 
     // Reduce the array
     always_comb begin
@@ -4387,13 +5676,11 @@ module soc_ifc_reg (
         readback_done = decoded_req & ~decoded_req_is_wr;
         readback_err = '0;
         readback_data_var = '0;
-        for(int i=0; i<162; i++) readback_data_var |= readback_array[i];
+        for(int i=0; i<186; i++) readback_data_var |= readback_array[i];
         readback_data = readback_data_var;
     end
 
     assign cpuif_rd_ack = readback_done;
     assign cpuif_rd_data = readback_data;
     assign cpuif_rd_err = readback_err;
-
-endmodule
-
+endmodule
\ No newline at end of file
diff --git a/src/soc_ifc/rtl/soc_ifc_reg_covergroups.svh b/src/soc_ifc/rtl/soc_ifc_reg_covergroups.svh
new file mode 100644
index 000000000..0b835415e
--- /dev/null
+++ b/src/soc_ifc/rtl/soc_ifc_reg_covergroups.svh
@@ -0,0 +1,2376 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+`ifndef SOC_IFC_REG_COVERGROUPS
+    `define SOC_IFC_REG_COVERGROUPS
+    
+    /*----------------------- SOC_IFC_REG__CPTRA_HW_ERROR_FATAL COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__CPTRA_HW_ERROR_FATAL_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__CPTRA_HW_ERROR_FATAL_fld_cg with function sample(
+    input bit [1-1:0] iccm_ecc_unc,
+    input bit [1-1:0] dccm_ecc_unc,
+    input bit [1-1:0] nmi_pin
+    );
+        option.per_instance = 1;
+        iccm_ecc_unc_cp : coverpoint iccm_ecc_unc;
+        dccm_ecc_unc_cp : coverpoint dccm_ecc_unc;
+        nmi_pin_cp : coverpoint nmi_pin;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__CPTRA_HW_ERROR_NON_FATAL COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__CPTRA_HW_ERROR_NON_FATAL_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__CPTRA_HW_ERROR_NON_FATAL_fld_cg with function sample(
+    input bit [1-1:0] mbox_prot_no_lock,
+    input bit [1-1:0] mbox_prot_ooo,
+    input bit [1-1:0] mbox_ecc_unc
+    );
+        option.per_instance = 1;
+        mbox_prot_no_lock_cp : coverpoint mbox_prot_no_lock;
+        mbox_prot_ooo_cp : coverpoint mbox_prot_ooo;
+        mbox_ecc_unc_cp : coverpoint mbox_ecc_unc;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__CPTRA_FW_ERROR_FATAL COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__CPTRA_FW_ERROR_FATAL_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__CPTRA_FW_ERROR_FATAL_fld_cg with function sample(
+    input bit [32-1:0] error_code
+    );
+        option.per_instance = 1;
+        error_code_cp : coverpoint error_code;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__CPTRA_FW_ERROR_NON_FATAL COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__CPTRA_FW_ERROR_NON_FATAL_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__CPTRA_FW_ERROR_NON_FATAL_fld_cg with function sample(
+    input bit [32-1:0] error_code
+    );
+        option.per_instance = 1;
+        error_code_cp : coverpoint error_code;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__CPTRA_HW_ERROR_ENC COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__CPTRA_HW_ERROR_ENC_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__CPTRA_HW_ERROR_ENC_fld_cg with function sample(
+    input bit [32-1:0] error_code
+    );
+        option.per_instance = 1;
+        error_code_cp : coverpoint error_code;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__CPTRA_FW_ERROR_ENC COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__CPTRA_FW_ERROR_ENC_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__CPTRA_FW_ERROR_ENC_fld_cg with function sample(
+    input bit [32-1:0] error_code
+    );
+        option.per_instance = 1;
+        error_code_cp : coverpoint error_code;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__CPTRA_FW_EXTENDED_ERROR_INFO COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__CPTRA_FW_EXTENDED_ERROR_INFO_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__CPTRA_FW_EXTENDED_ERROR_INFO_fld_cg with function sample(
+    input bit [32-1:0] error_info
+    );
+        option.per_instance = 1;
+        error_info_cp : coverpoint error_info;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__CPTRA_BOOT_STATUS COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__CPTRA_BOOT_STATUS_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__CPTRA_BOOT_STATUS_fld_cg with function sample(
+    input bit [32-1:0] status
+    );
+        option.per_instance = 1;
+        status_cp : coverpoint status;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__CPTRA_FLOW_STATUS COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__CPTRA_FLOW_STATUS_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__CPTRA_FLOW_STATUS_fld_cg with function sample(
+    input bit [24-1:0] status,
+    input bit [1-1:0] idevid_csr_ready,
+    input bit [3-1:0] boot_fsm_ps,
+    input bit [1-1:0] ready_for_fw,
+    input bit [1-1:0] ready_for_runtime,
+    input bit [1-1:0] ready_for_fuses,
+    input bit [1-1:0] mailbox_flow_done
+    );
+        option.per_instance = 1;
+        status_cp : coverpoint status;
+        idevid_csr_ready_cp : coverpoint idevid_csr_ready;
+        boot_fsm_ps_cp : coverpoint boot_fsm_ps;
+        ready_for_fw_cp : coverpoint ready_for_fw;
+        ready_for_runtime_cp : coverpoint ready_for_runtime;
+        ready_for_fuses_cp : coverpoint ready_for_fuses;
+        mailbox_flow_done_cp : coverpoint mailbox_flow_done;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__CPTRA_RESET_REASON COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__CPTRA_RESET_REASON_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__CPTRA_RESET_REASON_fld_cg with function sample(
+    input bit [1-1:0] FW_UPD_RESET,
+    input bit [1-1:0] WARM_RESET
+    );
+        option.per_instance = 1;
+        FW_UPD_RESET_cp : coverpoint FW_UPD_RESET;
+        WARM_RESET_cp : coverpoint WARM_RESET;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__CPTRA_SECURITY_STATE COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__CPTRA_SECURITY_STATE_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__CPTRA_SECURITY_STATE_fld_cg with function sample(
+    input bit [2-1:0] device_lifecycle,
+    input bit [1-1:0] debug_locked,
+    input bit [1-1:0] scan_mode,
+    input bit [28-1:0] rsvd
+    );
+        option.per_instance = 1;
+        device_lifecycle_cp : coverpoint device_lifecycle;
+        debug_locked_cp : coverpoint debug_locked;
+        scan_mode_cp : coverpoint scan_mode;
+        rsvd_cp : coverpoint rsvd;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__CPTRA_MBOX_VALID_PAUSER COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER_fld_cg with function sample(
+    input bit [32-1:0] PAUSER
+    );
+        option.per_instance = 1;
+        PAUSER_cp : coverpoint PAUSER;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__CPTRA_MBOX_PAUSER_LOCK COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK_fld_cg with function sample(
+    input bit [1-1:0] LOCK
+    );
+        option.per_instance = 1;
+        LOCK_cp : coverpoint LOCK;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__CPTRA_TRNG_VALID_PAUSER COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER_fld_cg with function sample(
+    input bit [32-1:0] PAUSER
+    );
+        option.per_instance = 1;
+        PAUSER_cp : coverpoint PAUSER {
+            bins zero_val = {32'h0};
+            bins rand_val[64] = {[1:32'hFFFF_FFFE]};
+            bins ones_val = {{32{1'b1}}};
+            wildcard bins set = (0 => 32'h????_????);
+            wildcard bins clr = (32'h????_???? => 0);
+        }
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__CPTRA_TRNG_PAUSER_LOCK COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK_fld_cg with function sample(
+    input bit [1-1:0] LOCK
+    );
+        option.per_instance = 1;
+        LOCK_cp : coverpoint LOCK;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__CPTRA_TRNG_DATA COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__CPTRA_TRNG_DATA_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__CPTRA_TRNG_DATA_fld_cg with function sample(
+    input bit [32-1:0] DATA
+    );
+        option.per_instance = 1;
+        DATA_cp : coverpoint DATA {
+            bins zero_val = {32'h0};
+            bins rand_val[64] = {[1:32'hFFFF_FFFE]};
+            bins ones_val = {{32{1'b1}}};
+            wildcard bins set = (0 => 32'h????_????);
+            wildcard bins clr = (32'h????_???? => 0);
+        }
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__CPTRA_TRNG_CTRL COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__CPTRA_TRNG_CTRL_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__CPTRA_TRNG_CTRL_fld_cg with function sample(
+    input bit [1-1:0] clear
+    );
+        option.per_instance = 1;
+        clear_cp : coverpoint clear;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__CPTRA_TRNG_STATUS COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__CPTRA_TRNG_STATUS_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__CPTRA_TRNG_STATUS_fld_cg with function sample(
+    input bit [1-1:0] DATA_REQ,
+    input bit [1-1:0] DATA_WR_DONE
+    );
+        option.per_instance = 1;
+        DATA_REQ_cp : coverpoint DATA_REQ;
+        DATA_WR_DONE_cp : coverpoint DATA_WR_DONE;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__CPTRA_FUSE_WR_DONE COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__CPTRA_FUSE_WR_DONE_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__CPTRA_FUSE_WR_DONE_fld_cg with function sample(
+    input bit [1-1:0] done
+    );
+        option.per_instance = 1;
+        done_cp : coverpoint done;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__CPTRA_TIMER_CONFIG COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__CPTRA_TIMER_CONFIG_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__CPTRA_TIMER_CONFIG_fld_cg with function sample(
+    input bit [32-1:0] clk_period
+    );
+        option.per_instance = 1;
+        clk_period_cp : coverpoint clk_period;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__CPTRA_BOOTFSM_GO COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__CPTRA_BOOTFSM_GO_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__CPTRA_BOOTFSM_GO_fld_cg with function sample(
+    input bit [1-1:0] GO
+    );
+        option.per_instance = 1;
+        GO_cp : coverpoint GO;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__CPTRA_DBG_MANUF_SERVICE_REG COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__CPTRA_DBG_MANUF_SERVICE_REG_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__CPTRA_DBG_MANUF_SERVICE_REG_fld_cg with function sample(
+    input bit [32-1:0] DATA
+    );
+        option.per_instance = 1;
+        DATA_cp : coverpoint DATA {
+            bins zero_val = {32'h0};
+            bins rand_val[64] = {[1:32'hFFFF_FFFE]};
+            bins ones_val = {{32{1'b1}}};
+            wildcard bins set = (0 => 32'h????_????);
+            wildcard bins clr = (32'h????_???? => 0);
+        }
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__CPTRA_CLK_GATING_EN COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__CPTRA_CLK_GATING_EN_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__CPTRA_CLK_GATING_EN_fld_cg with function sample(
+    input bit [1-1:0] clk_gating_en
+    );
+        option.per_instance = 1;
+        clk_gating_en_cp : coverpoint clk_gating_en;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__CPTRA_GENERIC_INPUT_WIRES COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__CPTRA_GENERIC_INPUT_WIRES_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__CPTRA_GENERIC_INPUT_WIRES_fld_cg with function sample(
+    input bit [32-1:0] generic_wires
+    );
+        option.per_instance = 1;
+        generic_wires_cp : coverpoint generic_wires {
+            bins byte_none = {64'h0000_0000_0000_0000};
+            bins byte_0    = {[0:$]} with ($countones(item[ 7: 0] > 0));
+            bins byte_1    = {[0:$]} with ($countones(item[15: 8] > 0));
+            bins byte_2    = {[0:$]} with ($countones(item[23:16] > 0));
+            bins byte_3    = {[0:$]} with ($countones(item[31:24] > 0));
+        }
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__CPTRA_GENERIC_OUTPUT_WIRES COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__CPTRA_GENERIC_OUTPUT_WIRES_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__CPTRA_GENERIC_OUTPUT_WIRES_fld_cg with function sample(
+    input bit [32-1:0] generic_wires
+    );
+        option.per_instance = 1;
+        generic_wires_cp : coverpoint generic_wires {
+            bins byte_none = {64'h0000_0000_0000_0000};
+            bins byte_0    = {[0:$]} with ($countones(item[ 7: 0] > 0));
+            bins byte_1    = {[0:$]} with ($countones(item[15: 8] > 0));
+            bins byte_2    = {[0:$]} with ($countones(item[23:16] > 0));
+            bins byte_3    = {[0:$]} with ($countones(item[31:24] > 0));
+        }
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__CPTRA_HW_REV_ID COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__CPTRA_HW_REV_ID_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__CPTRA_HW_REV_ID_fld_cg with function sample(
+    input bit [16-1:0] CPTRA_GENERATION,
+    input bit [16-1:0] SOC_STEPPING_ID
+    );
+        option.per_instance = 1;
+        CPTRA_GENERATION_cp : coverpoint CPTRA_GENERATION; // FIXME
+        SOC_STEPPING_ID_cp : coverpoint SOC_STEPPING_ID; // FIXME
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__CPTRA_FW_REV_ID COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__CPTRA_FW_REV_ID_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__CPTRA_FW_REV_ID_fld_cg with function sample(
+    input bit [32-1:0] REV_ID
+    );
+        option.per_instance = 1;
+        REV_ID_cp : coverpoint REV_ID; // FIXME
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__CPTRA_HW_CONFIG COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__CPTRA_HW_CONFIG_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__CPTRA_HW_CONFIG_fld_cg with function sample(
+    input bit [1-1:0] iTRNG_en,
+    input bit [1-1:0] QSPI_en,
+    input bit [1-1:0] I3C_en,
+    input bit [1-1:0] UART_en
+    );
+        option.per_instance = 1;
+        iTRNG_en_cp : coverpoint iTRNG_en;
+        QSPI_en_cp : coverpoint QSPI_en;
+        I3C_en_cp : coverpoint I3C_en;
+        UART_en_cp : coverpoint UART_en;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__CPTRA_WDT_TIMER1_EN COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__CPTRA_WDT_TIMER1_EN_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__CPTRA_WDT_TIMER1_EN_fld_cg with function sample(
+    input bit [1-1:0] timer1_en
+    );
+        option.per_instance = 1;
+        timer1_en_cp : coverpoint timer1_en;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__CPTRA_WDT_TIMER1_CTRL COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__CPTRA_WDT_TIMER1_CTRL_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__CPTRA_WDT_TIMER1_CTRL_fld_cg with function sample(
+    input bit [1-1:0] timer1_restart
+    );
+        option.per_instance = 1;
+        timer1_restart_cp : coverpoint timer1_restart;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__CPTRA_WDT_TIMER1_TIMEOUT_PERIOD COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_fld_cg with function sample(
+    input bit [32-1:0] timer1_timeout_period
+    );
+        option.per_instance = 1;
+        timer1_timeout_period_cp : coverpoint timer1_timeout_period;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__CPTRA_WDT_TIMER2_EN COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__CPTRA_WDT_TIMER2_EN_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__CPTRA_WDT_TIMER2_EN_fld_cg with function sample(
+    input bit [1-1:0] timer2_en
+    );
+        option.per_instance = 1;
+        timer2_en_cp : coverpoint timer2_en;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__CPTRA_WDT_TIMER2_CTRL COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__CPTRA_WDT_TIMER2_CTRL_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__CPTRA_WDT_TIMER2_CTRL_fld_cg with function sample(
+    input bit [1-1:0] timer2_restart
+    );
+        option.per_instance = 1;
+        timer2_restart_cp : coverpoint timer2_restart;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__CPTRA_WDT_TIMER2_TIMEOUT_PERIOD COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_fld_cg with function sample(
+    input bit [32-1:0] timer2_timeout_period
+    );
+        option.per_instance = 1;
+        timer2_timeout_period_cp : coverpoint timer2_timeout_period;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__CPTRA_WDT_STATUS COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__CPTRA_WDT_STATUS_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__CPTRA_WDT_STATUS_fld_cg with function sample(
+    input bit [1-1:0] t1_timeout,
+    input bit [1-1:0] t2_timeout
+    );
+        option.per_instance = 1;
+        t1_timeout_cp : coverpoint t1_timeout;
+        t2_timeout_cp : coverpoint t2_timeout;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__CPTRA_FUSE_VALID_PAUSER COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER_fld_cg with function sample(
+    input bit [32-1:0] PAUSER
+    );
+        option.per_instance = 1;
+        PAUSER_cp : coverpoint PAUSER {
+            bins zero_val = {32'h0};
+            bins rand_val[64] = {[1:32'hFFFF_FFFE]};
+            bins ones_val = {{32{1'b1}}};
+            wildcard bins set = (0 => 32'h????_????);
+            wildcard bins clr = (32'h????_???? => 0);
+        }
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__CPTRA_FUSE_PAUSER_LOCK COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK_fld_cg with function sample(
+    input bit [1-1:0] LOCK
+    );
+        option.per_instance = 1;
+        LOCK_cp : coverpoint LOCK;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__CPTRA_WDT_CFG COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__CPTRA_WDT_CFG_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__CPTRA_WDT_CFG_fld_cg with function sample(
+    input bit [32-1:0] TIMEOUT
+    );
+        option.per_instance = 1;
+        TIMEOUT_cp : coverpoint TIMEOUT;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__CPTRA_ITRNG_ENTROPY_CONFIG_0 COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_0_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_0_fld_cg with function sample(
+    input bit [16-1:0] low_threshold,
+    input bit [16-1:0] high_threshold
+    );
+        option.per_instance = 1;
+        low_threshold_cp : coverpoint low_threshold;
+        high_threshold_cp : coverpoint high_threshold;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__CPTRA_ITRNG_ENTROPY_CONFIG_1 COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_1_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_1_fld_cg with function sample(
+    input bit [16-1:0] repetition_count,
+    input bit [16-1:0] RSVD
+    );
+        option.per_instance = 1;
+        repetition_count_cp : coverpoint repetition_count;
+        RSVD_cp : coverpoint RSVD;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__CPTRA_RSVD_REG COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__CPTRA_RSVD_REG_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__CPTRA_RSVD_REG_fld_cg with function sample(
+    input bit [32-1:0] RSVD
+    );
+        option.per_instance = 1;
+        RSVD_cp : coverpoint RSVD;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__FUSE_UDS_SEED COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__fuse_uds_seed_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__fuse_uds_seed_fld_cg with function sample(
+    input bit [32-1:0] seed
+    );
+        option.per_instance = 1;
+        seed_cp : coverpoint seed {
+            bins zero_val = {32'h0};
+            bins rand_val[64] = {[1:32'hFFFF_FFFE]};
+            bins ones_val = {{32{1'b1}}};
+            wildcard bins set = (0 => 32'h????_????);
+            wildcard bins clr = (32'h????_???? => 0);
+        }
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__FUSE_FIELD_ENTROPY COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__fuse_field_entropy_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__fuse_field_entropy_fld_cg with function sample(
+    input bit [32-1:0] seed
+    );
+        option.per_instance = 1;
+        seed_cp : coverpoint seed {
+            bins zero_val = {32'h0};
+            bins rand_val[64] = {[1:32'hFFFF_FFFE]};
+            bins ones_val = {{32{1'b1}}};
+            wildcard bins set = (0 => 32'h????_????);
+            wildcard bins clr = (32'h????_???? => 0);
+        }
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__FUSE_KEY_MANIFEST_PK_HASH COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__fuse_key_manifest_pk_hash_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__fuse_key_manifest_pk_hash_fld_cg with function sample(
+    input bit [32-1:0] hash
+    );
+        option.per_instance = 1;
+        hash_cp : coverpoint hash {
+            bins zero_val = {32'h0};
+            bins rand_val[64] = {[1:32'hFFFF_FFFE]};
+            bins ones_val = {{32{1'b1}}};
+            wildcard bins set = (0 => 32'h????_????);
+            wildcard bins clr = (32'h????_???? => 0);
+        }
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__FUSE_KEY_MANIFEST_PK_HASH_MASK COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__fuse_key_manifest_pk_hash_mask_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__fuse_key_manifest_pk_hash_mask_fld_cg with function sample(
+    input bit [4-1:0] mask
+    );
+        option.per_instance = 1;
+        mask_cp : coverpoint mask {
+            bins zero_val = {4'h0};
+            bins rand_val[4] = {[1:4'hE]};
+            bins ones_val = {{4{1'b1}}};
+            wildcard bins set = (0 => 4'h?);
+            wildcard bins clr = (4'h? => 0);
+        }
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__FUSE_OWNER_PK_HASH COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__fuse_owner_pk_hash_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__fuse_owner_pk_hash_fld_cg with function sample(
+    input bit [32-1:0] hash
+    );
+        option.per_instance = 1;
+        hash_cp : coverpoint hash {
+            bins zero_val = {32'h0};
+            bins rand_val[64] = {[1:32'hFFFF_FFFE]};
+            bins ones_val = {{32{1'b1}}};
+            wildcard bins set = (0 => 32'h????_????);
+            wildcard bins clr = (32'h????_???? => 0);
+        }
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__FUSE_FMC_KEY_MANIFEST_SVN COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__fuse_fmc_key_manifest_svn_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__fuse_fmc_key_manifest_svn_fld_cg with function sample(
+    input bit [32-1:0] svn
+    );
+        option.per_instance = 1;
+        svn_cp : coverpoint svn {
+            bins zero_val = {32'h0};
+            bins rand_val[64] = {[1:32'hFFFF_FFFE]};
+            bins ones_val = {{32{1'b1}}};
+            wildcard bins set = (0 => 32'h????_????);
+            wildcard bins clr = (32'h????_???? => 0);
+        }
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__FUSE_RUNTIME_SVN COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__fuse_runtime_svn_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__fuse_runtime_svn_fld_cg with function sample(
+    input bit [32-1:0] svn
+    );
+        option.per_instance = 1;
+        svn_cp : coverpoint svn {
+            bins zero_val = {32'h0};
+            bins rand_val[64] = {[1:32'hFFFF_FFFE]};
+            bins ones_val = {{32{1'b1}}};
+            wildcard bins set = (0 => 32'h????_????);
+            wildcard bins clr = (32'h????_???? => 0);
+        }
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__FUSE_ANTI_ROLLBACK_DISABLE COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__fuse_anti_rollback_disable_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__fuse_anti_rollback_disable_fld_cg with function sample(
+    input bit [1-1:0] dis
+    );
+        option.per_instance = 1;
+        dis_cp : coverpoint dis;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__FUSE_IDEVID_CERT_ATTR COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__fuse_idevid_cert_attr_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__fuse_idevid_cert_attr_fld_cg with function sample(
+    input bit [32-1:0] cert
+    );
+        option.per_instance = 1;
+        cert_cp : coverpoint cert {
+            bins zero_val = {32'h0};
+            bins rand_val[64] = {[1:32'hFFFF_FFFE]};
+            bins ones_val = {{32{1'b1}}};
+            wildcard bins set = (0 => 32'h????_????);
+            wildcard bins clr = (32'h????_???? => 0);
+        }
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__FUSE_IDEVID_MANUF_HSM_ID COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__fuse_idevid_manuf_hsm_id_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__fuse_idevid_manuf_hsm_id_fld_cg with function sample(
+    input bit [32-1:0] hsm_id
+    );
+        option.per_instance = 1;
+        hsm_id_cp : coverpoint hsm_id {
+            bins zero_val = {32'h0};
+            bins rand_val[64] = {[1:32'hFFFF_FFFE]};
+            bins ones_val = {{32{1'b1}}};
+            wildcard bins set = (0 => 32'h????_????);
+            wildcard bins clr = (32'h????_???? => 0);
+        }
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__FUSE_LIFE_CYCLE COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__fuse_life_cycle_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__fuse_life_cycle_fld_cg with function sample(
+    input bit [2-1:0] life_cycle
+    );
+        option.per_instance = 1;
+        life_cycle_cp : coverpoint life_cycle;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__FUSE_LMS_VERIFY COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__fuse_lms_verify_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__fuse_lms_verify_fld_cg with function sample(
+    input bit [1-1:0] lms_verify
+    );
+        option.per_instance = 1;
+        lms_verify_cp : coverpoint lms_verify;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__FUSE_LMS_REVOCATION COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__fuse_lms_revocation_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__fuse_lms_revocation_fld_cg with function sample(
+    input bit [32-1:0] lms_revocation
+    );
+        option.per_instance = 1;
+        lms_revocation_cp : coverpoint lms_revocation;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__FUSE_SOC_STEPPING_ID COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__fuse_soc_stepping_id_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__fuse_soc_stepping_id_fld_cg with function sample(
+    input bit [16-1:0] soc_stepping_id
+    );
+        option.per_instance = 1;
+        soc_stepping_id_cp : coverpoint soc_stepping_id;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTERNAL_OBF_KEY COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__internal_obf_key_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__internal_obf_key_fld_cg with function sample(
+    input bit [32-1:0] key
+    );
+        option.per_instance = 1;
+        key_cp : coverpoint key {
+            bins zero_val = {32'h0};
+            bins rand_val[64] = {[1:32'hFFFF_FFFE]};
+            bins ones_val = {{32{1'b1}}};
+            wildcard bins set = (0 => 32'h????_????);
+            wildcard bins clr = (32'h????_???? => 0);
+        }
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTERNAL_ICCM_LOCK COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__internal_iccm_lock_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__internal_iccm_lock_fld_cg with function sample(
+    input bit [1-1:0] lock
+    );
+        option.per_instance = 1;
+        lock_cp : coverpoint lock;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTERNAL_FW_UPDATE_RESET COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__internal_fw_update_reset_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__internal_fw_update_reset_fld_cg with function sample(
+    input bit [1-1:0] core_rst
+    );
+        option.per_instance = 1;
+        core_rst_cp : coverpoint core_rst;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__internal_fw_update_reset_wait_cycles_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__internal_fw_update_reset_wait_cycles_fld_cg with function sample(
+    input bit [8-1:0] wait_cycles
+    );
+        option.per_instance = 1;
+        wait_cycles_cp : coverpoint wait_cycles {
+            bins zero_val = {8'h0};
+            bins one_val = {1};
+            bins two_val = {2};
+            bins three_val = {3};
+            bins small_val = {[4:15]};
+            bins rand_val[16] = {[16:8'hFE]};
+            bins ones_val = {{8{1'b1}}};
+            wildcard bins set = (0 => 8'h??);
+            wildcard bins clr = (8'h?? => 0);
+        }
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTERNAL_NMI_VECTOR COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__internal_nmi_vector_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__internal_nmi_vector_fld_cg with function sample(
+    input bit [32-1:0] vec
+    );
+        option.per_instance = 1;
+        vec_cp : coverpoint vec {
+            wildcard bins ROM [16] = {32'h0000????};
+            wildcard bins ICCM0[16] = {32'h4000????};
+            wildcard bins ICCM1[16] = {32'h4001????};
+        }
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTERNAL_HW_ERROR_FATAL_MASK COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__internal_hw_error_fatal_mask_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__internal_hw_error_fatal_mask_fld_cg with function sample(
+    input bit [1-1:0] mask_iccm_ecc_unc,
+    input bit [1-1:0] mask_dccm_ecc_unc,
+    input bit [1-1:0] mask_nmi_pin
+    );
+        option.per_instance = 1;
+        option.auto_bin_max = 64;
+        mask_iccm_ecc_unc_cp : coverpoint mask_iccm_ecc_unc;
+        mask_dccm_ecc_unc_cp : coverpoint mask_dccm_ecc_unc;
+        mask_nmi_pin_cp : coverpoint mask_nmi_pin;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTERNAL_HW_ERROR_NON_FATAL_MASK COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__internal_hw_error_non_fatal_mask_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__internal_hw_error_non_fatal_mask_fld_cg with function sample(
+    input bit [1-1:0] mask_mbox_prot_no_lock,
+    input bit [1-1:0] mask_mbox_prot_ooo,
+    input bit [1-1:0] mask_mbox_ecc_unc
+    );
+        option.per_instance = 1;
+        option.auto_bin_max = 64;
+        mask_mbox_prot_no_lock_cp : coverpoint mask_mbox_prot_no_lock;
+        mask_mbox_prot_ooo_cp : coverpoint mask_mbox_prot_ooo;
+        mask_mbox_ecc_unc_cp : coverpoint mask_mbox_ecc_unc;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTERNAL_FW_ERROR_FATAL_MASK COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__internal_fw_error_fatal_mask_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__internal_fw_error_fatal_mask_fld_cg with function sample(
+    input bit [32-1:0] mask
+    );
+        option.per_instance = 1;
+        option.auto_bin_max = 64;
+        mask_cp : coverpoint mask;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTERNAL_FW_ERROR_NON_FATAL_MASK COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__internal_fw_error_non_fatal_mask_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__internal_fw_error_non_fatal_mask_fld_cg with function sample(
+    input bit [32-1:0] mask
+    );
+        option.per_instance = 1;
+        option.auto_bin_max = 64;
+        mask_cp : coverpoint mask;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTERNAL_RV_MTIME_L COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__internal_rv_mtime_l_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__internal_rv_mtime_l_fld_cg with function sample(
+    input bit [32-1:0] count_l
+    );
+        option.per_instance = 1;
+        option.auto_bin_max = 64;
+        count_l_cp : coverpoint count_l;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTERNAL_RV_MTIME_H COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__internal_rv_mtime_h_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__internal_rv_mtime_h_fld_cg with function sample(
+    input bit [32-1:0] count_h
+    );
+        option.per_instance = 1;
+        option.auto_bin_max = 4; /* Will have to manually force mtime to this, since it won't be reached normally in random sims */
+        count_h_cp : coverpoint count_h;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTERNAL_RV_MTIMECMP_L COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__internal_rv_mtimecmp_l_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__internal_rv_mtimecmp_l_fld_cg with function sample(
+    input bit [32-1:0] compare_l
+    );
+        option.per_instance = 1;
+        option.auto_bin_max = 4;
+        compare_l_cp : coverpoint compare_l;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTERNAL_RV_MTIMECMP_H COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__internal_rv_mtimecmp_h_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__internal_rv_mtimecmp_h_fld_cg with function sample(
+    input bit [32-1:0] compare_h
+    );
+        option.per_instance = 1;
+        option.auto_bin_max = 4;
+        compare_h_cp : coverpoint compare_h;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__GLOBAL_INTR_EN_T COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__intr_block_t__global_intr_en_t_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__intr_block_t__global_intr_en_t_fld_cg with function sample(
+    input bit [1-1:0] error_en,
+    input bit [1-1:0] notif_en
+    );
+        option.per_instance = 1;
+        error_en_cp : coverpoint error_en;
+        notif_en_cp : coverpoint notif_en;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__ERROR_INTR_EN_T COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__intr_block_t__error_intr_en_t_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__intr_block_t__error_intr_en_t_fld_cg with function sample(
+    input bit [1-1:0] error_internal_en,
+    input bit [1-1:0] error_inv_dev_en,
+    input bit [1-1:0] error_cmd_fail_en,
+    input bit [1-1:0] error_bad_fuse_en,
+    input bit [1-1:0] error_iccm_blocked_en,
+    input bit [1-1:0] error_mbox_ecc_unc_en,
+    input bit [1-1:0] error_wdt_timer1_timeout_en,
+    input bit [1-1:0] error_wdt_timer2_timeout_en
+    );
+        option.per_instance = 1;
+        error_internal_en_cp : coverpoint error_internal_en;
+        error_inv_dev_en_cp : coverpoint error_inv_dev_en;
+        error_cmd_fail_en_cp : coverpoint error_cmd_fail_en;
+        error_bad_fuse_en_cp : coverpoint error_bad_fuse_en;
+        error_iccm_blocked_en_cp : coverpoint error_iccm_blocked_en;
+        error_mbox_ecc_unc_en_cp : coverpoint error_mbox_ecc_unc_en;
+        error_wdt_timer1_timeout_en_cp : coverpoint error_wdt_timer1_timeout_en;
+        error_wdt_timer2_timeout_en_cp : coverpoint error_wdt_timer2_timeout_en;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__NOTIF_INTR_EN_T COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__intr_block_t__notif_intr_en_t_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__intr_block_t__notif_intr_en_t_fld_cg with function sample(
+    input bit [1-1:0] notif_cmd_avail_en,
+    input bit [1-1:0] notif_mbox_ecc_cor_en,
+    input bit [1-1:0] notif_debug_locked_en,
+    input bit [1-1:0] notif_scan_mode_en,
+    input bit [1-1:0] notif_soc_req_lock_en,
+    input bit [1-1:0] notif_gen_in_toggle_en
+    );
+        option.per_instance = 1;
+        notif_cmd_avail_en_cp : coverpoint notif_cmd_avail_en;
+        notif_mbox_ecc_cor_en_cp : coverpoint notif_mbox_ecc_cor_en;
+        notif_debug_locked_en_cp : coverpoint notif_debug_locked_en;
+        notif_scan_mode_en_cp : coverpoint notif_scan_mode_en;
+        notif_soc_req_lock_en_cp : coverpoint notif_soc_req_lock_en;
+        notif_gen_in_toggle_en_cp : coverpoint notif_gen_in_toggle_en;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__GLOBAL_INTR_T_AGG_STS_DD3DCF0A COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__intr_block_t__global_intr_t_agg_sts_dd3dcf0a_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__intr_block_t__global_intr_t_agg_sts_dd3dcf0a_fld_cg with function sample(
+    input bit [1-1:0] agg_sts
+    );
+        option.per_instance = 1;
+        agg_sts_cp : coverpoint agg_sts;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__GLOBAL_INTR_T_AGG_STS_E6399B4A COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__intr_block_t__global_intr_t_agg_sts_e6399b4a_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__intr_block_t__global_intr_t_agg_sts_e6399b4a_fld_cg with function sample(
+    input bit [1-1:0] agg_sts
+    );
+        option.per_instance = 1;
+        agg_sts_cp : coverpoint agg_sts;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__ERROR_INTR_T_ERROR_BAD_FUSE_STS_23F67582_ERROR_CMD_FAIL_STS_B85845F8_ERROR_ICCM_BLOCKED_STS_E81E6AD2_ERROR_INTERNAL_STS_CAAD62E2_ERROR_INV_DEV_STS_6693E7DB_ERROR_MBOX_ECC_UNC_STS_30BFF330_ERROR_WDT_TIMER1_TIMEOUT_STS_6AAA9655_ERROR_WDT_TIMER2_TIMEOUT_STS_CDA8789F COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f_fld_cg with function sample(
+    input bit [1-1:0] error_internal_sts,
+    input bit [1-1:0] error_inv_dev_sts,
+    input bit [1-1:0] error_cmd_fail_sts,
+    input bit [1-1:0] error_bad_fuse_sts,
+    input bit [1-1:0] error_iccm_blocked_sts,
+    input bit [1-1:0] error_mbox_ecc_unc_sts,
+    input bit [1-1:0] error_wdt_timer1_timeout_sts,
+    input bit [1-1:0] error_wdt_timer2_timeout_sts
+    );
+        option.per_instance = 1;
+        error_internal_sts_cp : coverpoint error_internal_sts;
+        error_inv_dev_sts_cp : coverpoint error_inv_dev_sts;
+        error_cmd_fail_sts_cp : coverpoint error_cmd_fail_sts;
+        error_bad_fuse_sts_cp : coverpoint error_bad_fuse_sts;
+        error_iccm_blocked_sts_cp : coverpoint error_iccm_blocked_sts;
+        error_mbox_ecc_unc_sts_cp : coverpoint error_mbox_ecc_unc_sts;
+        error_wdt_timer1_timeout_sts_cp : coverpoint error_wdt_timer1_timeout_sts;
+        error_wdt_timer2_timeout_sts_cp : coverpoint error_wdt_timer2_timeout_sts;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__NOTIF_INTR_T_NOTIF_CMD_AVAIL_STS_1871606B_NOTIF_DEBUG_LOCKED_STS_5F024102_NOTIF_GEN_IN_TOGGLE_STS_59F84B64_NOTIF_MBOX_ECC_COR_STS_5C3D26BB_NOTIF_SCAN_MODE_STS_122F6367_NOTIF_SOC_REQ_LOCK_STS_DEDDDE70 COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70_fld_cg with function sample(
+    input bit [1-1:0] notif_cmd_avail_sts,
+    input bit [1-1:0] notif_mbox_ecc_cor_sts,
+    input bit [1-1:0] notif_debug_locked_sts,
+    input bit [1-1:0] notif_scan_mode_sts,
+    input bit [1-1:0] notif_soc_req_lock_sts,
+    input bit [1-1:0] notif_gen_in_toggle_sts
+    );
+        option.per_instance = 1;
+        notif_cmd_avail_sts_cp : coverpoint notif_cmd_avail_sts;
+        notif_mbox_ecc_cor_sts_cp : coverpoint notif_mbox_ecc_cor_sts;
+        notif_debug_locked_sts_cp : coverpoint notif_debug_locked_sts;
+        notif_scan_mode_sts_cp : coverpoint notif_scan_mode_sts;
+        notif_soc_req_lock_sts_cp : coverpoint notif_soc_req_lock_sts;
+        notif_gen_in_toggle_sts_cp : coverpoint notif_gen_in_toggle_sts;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__ERROR_INTR_TRIG_T COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__intr_block_t__error_intr_trig_t_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__intr_block_t__error_intr_trig_t_fld_cg with function sample(
+    input bit [1-1:0] error_internal_trig,
+    input bit [1-1:0] error_inv_dev_trig,
+    input bit [1-1:0] error_cmd_fail_trig,
+    input bit [1-1:0] error_bad_fuse_trig,
+    input bit [1-1:0] error_iccm_blocked_trig,
+    input bit [1-1:0] error_mbox_ecc_unc_trig,
+    input bit [1-1:0] error_wdt_timer1_timeout_trig,
+    input bit [1-1:0] error_wdt_timer2_timeout_trig
+    );
+        option.per_instance = 1;
+        error_internal_trig_cp : coverpoint error_internal_trig;
+        error_inv_dev_trig_cp : coverpoint error_inv_dev_trig;
+        error_cmd_fail_trig_cp : coverpoint error_cmd_fail_trig;
+        error_bad_fuse_trig_cp : coverpoint error_bad_fuse_trig;
+        error_iccm_blocked_trig_cp : coverpoint error_iccm_blocked_trig;
+        error_mbox_ecc_unc_trig_cp : coverpoint error_mbox_ecc_unc_trig;
+        error_wdt_timer1_timeout_trig_cp : coverpoint error_wdt_timer1_timeout_trig;
+        error_wdt_timer2_timeout_trig_cp : coverpoint error_wdt_timer2_timeout_trig;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__NOTIF_INTR_TRIG_T COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__intr_block_t__notif_intr_trig_t_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__intr_block_t__notif_intr_trig_t_fld_cg with function sample(
+    input bit [1-1:0] notif_cmd_avail_trig,
+    input bit [1-1:0] notif_mbox_ecc_cor_trig,
+    input bit [1-1:0] notif_debug_locked_trig,
+    input bit [1-1:0] notif_scan_mode_trig,
+    input bit [1-1:0] notif_soc_req_lock_trig,
+    input bit [1-1:0] notif_gen_in_toggle_trig
+    );
+        option.per_instance = 1;
+        notif_cmd_avail_trig_cp : coverpoint notif_cmd_avail_trig;
+        notif_mbox_ecc_cor_trig_cp : coverpoint notif_mbox_ecc_cor_trig;
+        notif_debug_locked_trig_cp : coverpoint notif_debug_locked_trig;
+        notif_scan_mode_trig_cp : coverpoint notif_scan_mode_trig;
+        notif_soc_req_lock_trig_cp : coverpoint notif_soc_req_lock_trig;
+        notif_gen_in_toggle_trig_cp : coverpoint notif_gen_in_toggle_trig;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_T_CNT_608F1141 COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__intr_block_t__intr_count_t_cnt_608f1141_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__intr_block_t__intr_count_t_cnt_608f1141_fld_cg with function sample(
+    input bit [32-1:0] cnt
+    );
+        option.per_instance = 1;
+        option.auto_bin_max = 64;
+        cnt_cp : coverpoint cnt;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_T_CNT_916AB5DF COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__intr_block_t__intr_count_t_cnt_916ab5df_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__intr_block_t__intr_count_t_cnt_916ab5df_fld_cg with function sample(
+    input bit [32-1:0] cnt
+    );
+        option.per_instance = 1;
+        option.auto_bin_max = 64;
+        cnt_cp : coverpoint cnt;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_T_CNT_B2A56031 COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__intr_block_t__intr_count_t_cnt_b2a56031_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__intr_block_t__intr_count_t_cnt_b2a56031_fld_cg with function sample(
+    input bit [32-1:0] cnt
+    );
+        option.per_instance = 1;
+        option.auto_bin_max = 64;
+        cnt_cp : coverpoint cnt;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_T_CNT_FB7D2433 COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__intr_block_t__intr_count_t_cnt_fb7d2433_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__intr_block_t__intr_count_t_cnt_fb7d2433_fld_cg with function sample(
+    input bit [32-1:0] cnt
+    );
+        option.per_instance = 1;
+        option.auto_bin_max = 64;
+        cnt_cp : coverpoint cnt;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_T_CNT_25E76B6F COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__intr_block_t__intr_count_t_cnt_25e76b6f_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__intr_block_t__intr_count_t_cnt_25e76b6f_fld_cg with function sample(
+    input bit [32-1:0] cnt
+    );
+        option.per_instance = 1;
+        option.auto_bin_max = 64;
+        cnt_cp : coverpoint cnt;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_T_CNT_26B97E39 COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__intr_block_t__intr_count_t_cnt_26b97e39_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__intr_block_t__intr_count_t_cnt_26b97e39_fld_cg with function sample(
+    input bit [32-1:0] cnt
+    );
+        option.per_instance = 1;
+        option.auto_bin_max = 64;
+        cnt_cp : coverpoint cnt;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_T_CNT_A2F61F82 COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__intr_block_t__intr_count_t_cnt_a2f61f82_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__intr_block_t__intr_count_t_cnt_a2f61f82_fld_cg with function sample(
+    input bit [32-1:0] cnt
+    );
+        option.per_instance = 1;
+        option.auto_bin_max = 64;
+        cnt_cp : coverpoint cnt;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_T_CNT_D46457CD COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__intr_block_t__intr_count_t_cnt_d46457cd_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__intr_block_t__intr_count_t_cnt_d46457cd_fld_cg with function sample(
+    input bit [32-1:0] cnt
+    );
+        option.per_instance = 1;
+        option.auto_bin_max = 64;
+        cnt_cp : coverpoint cnt;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_T_CNT_A06F0954 COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__intr_block_t__intr_count_t_cnt_a06f0954_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__intr_block_t__intr_count_t_cnt_a06f0954_fld_cg with function sample(
+    input bit [32-1:0] cnt
+    );
+        option.per_instance = 1;
+        option.auto_bin_max = 64;
+        cnt_cp : coverpoint cnt;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_T_CNT_00E49272 COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__intr_block_t__intr_count_t_cnt_00e49272_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__intr_block_t__intr_count_t_cnt_00e49272_fld_cg with function sample(
+    input bit [32-1:0] cnt
+    );
+        option.per_instance = 1;
+        option.auto_bin_max = 64;
+        cnt_cp : coverpoint cnt;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_T_CNT_EE53DED8 COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__intr_block_t__intr_count_t_cnt_ee53ded8_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__intr_block_t__intr_count_t_cnt_ee53ded8_fld_cg with function sample(
+    input bit [32-1:0] cnt
+    );
+        option.per_instance = 1;
+        option.auto_bin_max = 64;
+        cnt_cp : coverpoint cnt;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_T_CNT_FBF3C714 COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__intr_block_t__intr_count_t_cnt_fbf3c714_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__intr_block_t__intr_count_t_cnt_fbf3c714_fld_cg with function sample(
+    input bit [32-1:0] cnt
+    );
+        option.per_instance = 1;
+        option.auto_bin_max = 64;
+        cnt_cp : coverpoint cnt;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_T_CNT_B9BDDABE COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__intr_block_t__intr_count_t_cnt_b9bddabe_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__intr_block_t__intr_count_t_cnt_b9bddabe_fld_cg with function sample(
+    input bit [32-1:0] cnt
+    );
+        option.per_instance = 1;
+        option.auto_bin_max = 64;
+        cnt_cp : coverpoint cnt;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_T_CNT_57528CC1 COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__intr_block_t__intr_count_t_cnt_57528cc1_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__intr_block_t__intr_count_t_cnt_57528cc1_fld_cg with function sample(
+    input bit [32-1:0] cnt
+    );
+        option.per_instance = 1;
+        option.auto_bin_max = 64;
+        cnt_cp : coverpoint cnt;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_15E6ED7E COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_15e6ed7e_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_15e6ed7e_fld_cg with function sample(
+    input bit [1-1:0] pulse
+    );
+        option.per_instance = 1;
+        pulse_cp : coverpoint pulse;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_F762EA9C COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_f762ea9c_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_f762ea9c_fld_cg with function sample(
+    input bit [1-1:0] pulse
+    );
+        option.per_instance = 1;
+        pulse_cp : coverpoint pulse;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_AA8718C6 COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_aa8718c6_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_aa8718c6_fld_cg with function sample(
+    input bit [1-1:0] pulse
+    );
+        option.per_instance = 1;
+        pulse_cp : coverpoint pulse;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_26FA5955 COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_26fa5955_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_26fa5955_fld_cg with function sample(
+    input bit [1-1:0] pulse
+    );
+        option.per_instance = 1;
+        pulse_cp : coverpoint pulse;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_3E43D258 COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_3e43d258_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_3e43d258_fld_cg with function sample(
+    input bit [1-1:0] pulse
+    );
+        option.per_instance = 1;
+        pulse_cp : coverpoint pulse;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_9F1632FD COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_9f1632fd_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_9f1632fd_fld_cg with function sample(
+    input bit [1-1:0] pulse
+    );
+        option.per_instance = 1;
+        pulse_cp : coverpoint pulse;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_AA999FDC COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_aa999fdc_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_aa999fdc_fld_cg with function sample(
+    input bit [1-1:0] pulse
+    );
+        option.per_instance = 1;
+        pulse_cp : coverpoint pulse;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_404E12DB COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_404e12db_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_404e12db_fld_cg with function sample(
+    input bit [1-1:0] pulse
+    );
+        option.per_instance = 1;
+        pulse_cp : coverpoint pulse;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_90D52137 COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_90d52137_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_90d52137_fld_cg with function sample(
+    input bit [1-1:0] pulse
+    );
+        option.per_instance = 1;
+        pulse_cp : coverpoint pulse;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_A6DB6FFF COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_a6db6fff_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_a6db6fff_fld_cg with function sample(
+    input bit [1-1:0] pulse
+    );
+        option.per_instance = 1;
+        pulse_cp : coverpoint pulse;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_51891FB1 COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_51891fb1_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_51891fb1_fld_cg with function sample(
+    input bit [1-1:0] pulse
+    );
+        option.per_instance = 1;
+        pulse_cp : coverpoint pulse;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_F5D8AFE0 COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_f5d8afe0_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_f5d8afe0_fld_cg with function sample(
+    input bit [1-1:0] pulse
+    );
+        option.per_instance = 1;
+        pulse_cp : coverpoint pulse;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_246489BD COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_246489bd_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_246489bd_fld_cg with function sample(
+    input bit [1-1:0] pulse
+    );
+        option.per_instance = 1;
+        pulse_cp : coverpoint pulse;
+
+    endgroup
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_D6ED4D1E COVERGROUPS -----------------------*/
+    covergroup soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_d6ed4d1e_bit_cg with function sample(input bit reg_bit);
+        option.per_instance = 1;
+        reg_bit_cp : coverpoint reg_bit {
+            bins value[2] = {0,1};
+        }
+        reg_bit_edge_cp : coverpoint reg_bit {
+            bins rise = (0 => 1);
+            bins fall = (1 => 0);
+        }
+
+    endgroup
+    covergroup soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_d6ed4d1e_fld_cg with function sample(
+    input bit [1-1:0] pulse
+    );
+        option.per_instance = 1;
+        pulse_cp : coverpoint pulse;
+
+    endgroup
+
+`endif
diff --git a/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv b/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv
index bda73281f..960293743 100644
--- a/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv
+++ b/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv
@@ -3,16 +3,20 @@
 
 package soc_ifc_reg_pkg;
     typedef struct packed{
-        logic [31:0] next;
+        logic next;
         logic we;
-    } soc_ifc_reg__rw_rw_sticky_hw_w32__in_t;
+    } soc_ifc_reg__rw_rw_sticky_hw__in_t;
 
     typedef struct packed{
-        soc_ifc_reg__rw_rw_sticky_hw_w32__in_t error_code;
+        soc_ifc_reg__rw_rw_sticky_hw__in_t iccm_ecc_unc;
+        soc_ifc_reg__rw_rw_sticky_hw__in_t dccm_ecc_unc;
+        soc_ifc_reg__rw_rw_sticky_hw__in_t nmi_pin;
     } soc_ifc_reg__CPTRA_HW_ERROR_FATAL__in_t;
 
     typedef struct packed{
-        soc_ifc_reg__rw_rw_sticky_hw_w32__in_t error_code;
+        soc_ifc_reg__rw_rw_sticky_hw__in_t mbox_prot_no_lock;
+        soc_ifc_reg__rw_rw_sticky_hw__in_t mbox_prot_ooo;
+        soc_ifc_reg__rw_rw_sticky_hw__in_t mbox_ecc_unc;
     } soc_ifc_reg__CPTRA_HW_ERROR_NON_FATAL__in_t;
 
     typedef struct packed{
@@ -28,11 +32,16 @@ package soc_ifc_reg_pkg;
         soc_ifc_reg__rw_rw_sticky_w32__in_t error_code;
     } soc_ifc_reg__CPTRA_FW_ERROR_NON_FATAL__in_t;
 
+    typedef struct packed{
+        logic [2:0] next;
+    } soc_ifc_reg__CPTRA_FLOW_STATUS__boot_fsm_ps__in_t;
+
     typedef struct packed{
         logic next;
     } soc_ifc_reg__CPTRA_FLOW_STATUS__ready_for_fuses__in_t;
 
     typedef struct packed{
+        soc_ifc_reg__CPTRA_FLOW_STATUS__boot_fsm_ps__in_t boot_fsm_ps;
         soc_ifc_reg__CPTRA_FLOW_STATUS__ready_for_fuses__in_t ready_for_fuses;
     } soc_ifc_reg__CPTRA_FLOW_STATUS__in_t;
 
@@ -102,6 +111,7 @@ package soc_ifc_reg_pkg;
 
     typedef struct packed{
         logic swwe;
+        logic hwclr;
     } soc_ifc_reg__CPTRA_TRNG_DATA__DATA__in_t;
 
     typedef struct packed{
@@ -151,6 +161,14 @@ package soc_ifc_reg_pkg;
         soc_ifc_reg__CPTRA_GENERIC_INPUT_WIRES__generic_wires__in_t generic_wires;
     } soc_ifc_reg__CPTRA_GENERIC_INPUT_WIRES__in_t;
 
+    typedef struct packed{
+        logic [15:0] next;
+    } soc_ifc_reg__CPTRA_HW_REV_ID__SOC_STEPPING_ID__in_t;
+
+    typedef struct packed{
+        soc_ifc_reg__CPTRA_HW_REV_ID__SOC_STEPPING_ID__in_t SOC_STEPPING_ID;
+    } soc_ifc_reg__CPTRA_HW_REV_ID__in_t;
+
     typedef struct packed{
         logic next;
     } soc_ifc_reg__CPTRA_HW_CONFIG__iTRNG_en__in_t;
@@ -187,6 +205,22 @@ package soc_ifc_reg_pkg;
         soc_ifc_reg__CPTRA_WDT_STATUS__t2_timeout__in_t t2_timeout;
     } soc_ifc_reg__CPTRA_WDT_STATUS__in_t;
 
+    typedef struct packed{
+        logic swwel;
+    } soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER__PAUSER__in_t;
+
+    typedef struct packed{
+        soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER__PAUSER__in_t PAUSER;
+    } soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER__in_t;
+
+    typedef struct packed{
+        logic swwel;
+    } soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK__LOCK__in_t;
+
+    typedef struct packed{
+        soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK__LOCK__in_t LOCK;
+    } soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK__in_t;
+
     typedef struct packed{
         logic swwel;
         logic hwclr;
@@ -252,6 +286,22 @@ package soc_ifc_reg_pkg;
         soc_ifc_reg__Fuse_w2__in_t life_cycle;
     } soc_ifc_reg__fuse_life_cycle__in_t;
 
+    typedef struct packed{
+        soc_ifc_reg__Fuse__in_t lms_verify;
+    } soc_ifc_reg__fuse_lms_verify__in_t;
+
+    typedef struct packed{
+        soc_ifc_reg__Fuse_w32__in_t lms_revocation;
+    } soc_ifc_reg__fuse_lms_revocation__in_t;
+
+    typedef struct packed{
+        logic swwel;
+    } soc_ifc_reg__Fuse_w16__in_t;
+
+    typedef struct packed{
+        soc_ifc_reg__Fuse_w16__in_t soc_stepping_id;
+    } soc_ifc_reg__fuse_soc_stepping_id__in_t;
+
     typedef struct packed{
         logic [31:0] next;
         logic wel;
@@ -271,6 +321,22 @@ package soc_ifc_reg_pkg;
         soc_ifc_reg__internal_iccm_lock__lock__in_t lock;
     } soc_ifc_reg__internal_iccm_lock__in_t;
 
+    typedef struct packed{
+        logic incr;
+    } soc_ifc_reg__internal_rv_mtime_l__count_l__in_t;
+
+    typedef struct packed{
+        soc_ifc_reg__internal_rv_mtime_l__count_l__in_t count_l;
+    } soc_ifc_reg__internal_rv_mtime_l__in_t;
+
+    typedef struct packed{
+        logic incr;
+    } soc_ifc_reg__internal_rv_mtime_h__count_h__in_t;
+
+    typedef struct packed{
+        soc_ifc_reg__internal_rv_mtime_h__count_h__in_t count_h;
+    } soc_ifc_reg__internal_rv_mtime_h__in_t;
+
     typedef struct packed{
         logic hwset;
     } soc_ifc_reg__intr_block_t__error_intr_t__error_internal_sts_enable_d33001bb_next_52b75ffa_resetsignal_f7aac87a__in_t;
@@ -326,20 +392,30 @@ package soc_ifc_reg_pkg;
         logic hwset;
     } soc_ifc_reg__intr_block_t__notif_intr_t__notif_debug_locked_sts_enable_097fcd5b_next_36fa44d8__in_t;
 
+    typedef struct packed{
+        logic hwset;
+    } soc_ifc_reg__intr_block_t__notif_intr_t__notif_scan_mode_sts_enable_ed1d9036_next_eb34855d__in_t;
+
     typedef struct packed{
         logic hwset;
     } soc_ifc_reg__intr_block_t__notif_intr_t__notif_soc_req_lock_sts_enable_52b75726_next_228b63de__in_t;
 
+    typedef struct packed{
+        logic hwset;
+    } soc_ifc_reg__intr_block_t__notif_intr_t__notif_gen_in_toggle_sts_enable_9918ab15_next_e02c99b9__in_t;
+
     typedef struct packed{
         soc_ifc_reg__intr_block_t__notif_intr_t__notif_cmd_avail_sts_enable_f40f37a0_next_6afe0a88__in_t notif_cmd_avail_sts;
         soc_ifc_reg__intr_block_t__notif_intr_t__notif_mbox_ecc_cor_sts_enable_c4f9db68_next_96c01bef__in_t notif_mbox_ecc_cor_sts;
         soc_ifc_reg__intr_block_t__notif_intr_t__notif_debug_locked_sts_enable_097fcd5b_next_36fa44d8__in_t notif_debug_locked_sts;
+        soc_ifc_reg__intr_block_t__notif_intr_t__notif_scan_mode_sts_enable_ed1d9036_next_eb34855d__in_t notif_scan_mode_sts;
         soc_ifc_reg__intr_block_t__notif_intr_t__notif_soc_req_lock_sts_enable_52b75726_next_228b63de__in_t notif_soc_req_lock_sts;
-    } soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_mbox_ecc_cor_sts_5c3d26bb_notif_soc_req_lock_sts_deddde70__in_t;
+        soc_ifc_reg__intr_block_t__notif_intr_t__notif_gen_in_toggle_sts_enable_9918ab15_next_e02c99b9__in_t notif_gen_in_toggle_sts;
+    } soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70__in_t;
 
     typedef struct packed{
         soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f__in_t error_internal_intr_r;
-        soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_mbox_ecc_cor_sts_5c3d26bb_notif_soc_req_lock_sts_deddde70__in_t notif_internal_intr_r;
+        soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70__in_t notif_internal_intr_r;
     } soc_ifc_reg__intr_block_t__in_t;
 
     typedef struct packed{
@@ -363,8 +439,11 @@ package soc_ifc_reg_pkg;
         soc_ifc_reg__CPTRA_BOOTFSM_GO__in_t CPTRA_BOOTFSM_GO;
         soc_ifc_reg__CPTRA_DBG_MANUF_SERVICE_REG__in_t CPTRA_DBG_MANUF_SERVICE_REG;
         soc_ifc_reg__CPTRA_GENERIC_INPUT_WIRES__in_t [2-1:0]CPTRA_GENERIC_INPUT_WIRES;
+        soc_ifc_reg__CPTRA_HW_REV_ID__in_t CPTRA_HW_REV_ID;
         soc_ifc_reg__CPTRA_HW_CONFIG__in_t CPTRA_HW_CONFIG;
         soc_ifc_reg__CPTRA_WDT_STATUS__in_t CPTRA_WDT_STATUS;
+        soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER__in_t CPTRA_FUSE_VALID_PAUSER;
+        soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK__in_t CPTRA_FUSE_PAUSER_LOCK;
         soc_ifc_reg__fuse_uds_seed__in_t [12-1:0]fuse_uds_seed;
         soc_ifc_reg__fuse_field_entropy__in_t [8-1:0]fuse_field_entropy;
         soc_ifc_reg__fuse_key_manifest_pk_hash__in_t [12-1:0]fuse_key_manifest_pk_hash;
@@ -376,25 +455,35 @@ package soc_ifc_reg_pkg;
         soc_ifc_reg__fuse_idevid_cert_attr__in_t [24-1:0]fuse_idevid_cert_attr;
         soc_ifc_reg__fuse_idevid_manuf_hsm_id__in_t [4-1:0]fuse_idevid_manuf_hsm_id;
         soc_ifc_reg__fuse_life_cycle__in_t fuse_life_cycle;
+        soc_ifc_reg__fuse_lms_verify__in_t fuse_lms_verify;
+        soc_ifc_reg__fuse_lms_revocation__in_t fuse_lms_revocation;
+        soc_ifc_reg__fuse_soc_stepping_id__in_t fuse_soc_stepping_id;
         soc_ifc_reg__internal_obf_key__in_t [8-1:0]internal_obf_key;
         soc_ifc_reg__internal_iccm_lock__in_t internal_iccm_lock;
+        soc_ifc_reg__internal_rv_mtime_l__in_t internal_rv_mtime_l;
+        soc_ifc_reg__internal_rv_mtime_h__in_t internal_rv_mtime_h;
         soc_ifc_reg__intr_block_t__in_t intr_block_rf;
     } soc_ifc_reg__in_t;
 
     typedef struct packed{
-        logic [31:0] value;
-    } soc_ifc_reg__rw_rw_sticky_hw_w32__out_t;
+        logic value;
+    } soc_ifc_reg__rw_rw_sticky_hw__out_t;
 
     typedef struct packed{
-        soc_ifc_reg__rw_rw_sticky_hw_w32__out_t error_code;
+        soc_ifc_reg__rw_rw_sticky_hw__out_t iccm_ecc_unc;
+        soc_ifc_reg__rw_rw_sticky_hw__out_t dccm_ecc_unc;
+        soc_ifc_reg__rw_rw_sticky_hw__out_t nmi_pin;
     } soc_ifc_reg__CPTRA_HW_ERROR_FATAL__out_t;
 
     typedef struct packed{
-        soc_ifc_reg__rw_rw_sticky_hw_w32__out_t error_code;
+        soc_ifc_reg__rw_rw_sticky_hw__out_t mbox_prot_no_lock;
+        soc_ifc_reg__rw_rw_sticky_hw__out_t mbox_prot_ooo;
+        soc_ifc_reg__rw_rw_sticky_hw__out_t mbox_ecc_unc;
     } soc_ifc_reg__CPTRA_HW_ERROR_NON_FATAL__out_t;
 
     typedef struct packed{
         logic [31:0] value;
+        logic swmod;
     } soc_ifc_reg__rw_rw_sticky_w32__out_t;
 
     typedef struct packed{
@@ -439,24 +528,24 @@ package soc_ifc_reg_pkg;
 
     typedef struct packed{
         logic value;
-    } soc_ifc_reg__CPTRA_FLOW_STATUS__ready_for_fw__out_t;
+    } soc_ifc_reg__CPTRA_FLOW_STATUS__idevid_csr_ready__out_t;
 
     typedef struct packed{
         logic value;
-    } soc_ifc_reg__CPTRA_FLOW_STATUS__ready_for_runtime__out_t;
+    } soc_ifc_reg__CPTRA_FLOW_STATUS__ready_for_fw__out_t;
 
     typedef struct packed{
         logic value;
-    } soc_ifc_reg__CPTRA_FLOW_STATUS__ready_for_fuses__out_t;
+    } soc_ifc_reg__CPTRA_FLOW_STATUS__ready_for_runtime__out_t;
 
     typedef struct packed{
         logic value;
     } soc_ifc_reg__CPTRA_FLOW_STATUS__mailbox_flow_done__out_t;
 
     typedef struct packed{
+        soc_ifc_reg__CPTRA_FLOW_STATUS__idevid_csr_ready__out_t idevid_csr_ready;
         soc_ifc_reg__CPTRA_FLOW_STATUS__ready_for_fw__out_t ready_for_fw;
         soc_ifc_reg__CPTRA_FLOW_STATUS__ready_for_runtime__out_t ready_for_runtime;
-        soc_ifc_reg__CPTRA_FLOW_STATUS__ready_for_fuses__out_t ready_for_fuses;
         soc_ifc_reg__CPTRA_FLOW_STATUS__mailbox_flow_done__out_t mailbox_flow_done;
     } soc_ifc_reg__CPTRA_FLOW_STATUS__out_t;
 
@@ -513,6 +602,14 @@ package soc_ifc_reg_pkg;
         soc_ifc_reg__CPTRA_TRNG_DATA__DATA__out_t DATA;
     } soc_ifc_reg__CPTRA_TRNG_DATA__out_t;
 
+    typedef struct packed{
+        logic value;
+    } soc_ifc_reg__CPTRA_TRNG_CTRL__clear__out_t;
+
+    typedef struct packed{
+        soc_ifc_reg__CPTRA_TRNG_CTRL__clear__out_t clear;
+    } soc_ifc_reg__CPTRA_TRNG_CTRL__out_t;
+
     typedef struct packed{
         logic value;
     } soc_ifc_reg__CPTRA_TRNG_STATUS__DATA_REQ__out_t;
@@ -570,14 +667,6 @@ package soc_ifc_reg_pkg;
         soc_ifc_reg__CPTRA_GENERIC_OUTPUT_WIRES__generic_wires__out_t generic_wires;
     } soc_ifc_reg__CPTRA_GENERIC_OUTPUT_WIRES__out_t;
 
-    typedef struct packed{
-        logic [31:0] value;
-    } soc_ifc_reg__CPTRA_HW_REV_ID__REV_ID__out_t;
-
-    typedef struct packed{
-        soc_ifc_reg__CPTRA_HW_REV_ID__REV_ID__out_t REV_ID;
-    } soc_ifc_reg__CPTRA_HW_REV_ID__out_t;
-
     typedef struct packed{
         logic [31:0] value;
     } soc_ifc_reg__CPTRA_FW_REV_ID__REV_ID__out_t;
@@ -647,6 +736,22 @@ package soc_ifc_reg_pkg;
         soc_ifc_reg__CPTRA_WDT_STATUS__t2_timeout__out_t t2_timeout;
     } soc_ifc_reg__CPTRA_WDT_STATUS__out_t;
 
+    typedef struct packed{
+        logic [31:0] value;
+    } soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER__PAUSER__out_t;
+
+    typedef struct packed{
+        soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER__PAUSER__out_t PAUSER;
+    } soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER__out_t;
+
+    typedef struct packed{
+        logic value;
+    } soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK__LOCK__out_t;
+
+    typedef struct packed{
+        soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK__LOCK__out_t LOCK;
+    } soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK__out_t;
+
     typedef struct packed{
         logic [31:0] value;
     } soc_ifc_reg__secret_w32__out_t;
@@ -711,6 +816,22 @@ package soc_ifc_reg_pkg;
         soc_ifc_reg__Fuse_w2__out_t life_cycle;
     } soc_ifc_reg__fuse_life_cycle__out_t;
 
+    typedef struct packed{
+        soc_ifc_reg__Fuse__out_t lms_verify;
+    } soc_ifc_reg__fuse_lms_verify__out_t;
+
+    typedef struct packed{
+        soc_ifc_reg__Fuse_w32__out_t lms_revocation;
+    } soc_ifc_reg__fuse_lms_revocation__out_t;
+
+    typedef struct packed{
+        logic [15:0] value;
+    } soc_ifc_reg__Fuse_w16__out_t;
+
+    typedef struct packed{
+        soc_ifc_reg__Fuse_w16__out_t soc_stepping_id;
+    } soc_ifc_reg__fuse_soc_stepping_id__out_t;
+
     typedef struct packed{
         logic [31:0] value;
     } soc_ifc_reg__key_w32__out_t;
@@ -751,6 +872,69 @@ package soc_ifc_reg_pkg;
         soc_ifc_reg__internal_nmi_vector__vec__out_t vec;
     } soc_ifc_reg__internal_nmi_vector__out_t;
 
+    typedef struct packed{
+        logic value;
+    } soc_ifc_reg__rw_ro_hw__out_t;
+
+    typedef struct packed{
+        soc_ifc_reg__rw_ro_hw__out_t mask_iccm_ecc_unc;
+        soc_ifc_reg__rw_ro_hw__out_t mask_dccm_ecc_unc;
+        soc_ifc_reg__rw_ro_hw__out_t mask_nmi_pin;
+    } soc_ifc_reg__internal_hw_error_fatal_mask__out_t;
+
+    typedef struct packed{
+        soc_ifc_reg__rw_ro_hw__out_t mask_mbox_prot_no_lock;
+        soc_ifc_reg__rw_ro_hw__out_t mask_mbox_prot_ooo;
+        soc_ifc_reg__rw_ro_hw__out_t mask_mbox_ecc_unc;
+    } soc_ifc_reg__internal_hw_error_non_fatal_mask__out_t;
+
+    typedef struct packed{
+        logic [31:0] value;
+    } soc_ifc_reg__rw_ro_hw_w32__out_t;
+
+    typedef struct packed{
+        soc_ifc_reg__rw_ro_hw_w32__out_t mask;
+    } soc_ifc_reg__internal_fw_error_fatal_mask__out_t;
+
+    typedef struct packed{
+        soc_ifc_reg__rw_ro_hw_w32__out_t mask;
+    } soc_ifc_reg__internal_fw_error_non_fatal_mask__out_t;
+
+    typedef struct packed{
+        logic [31:0] value;
+        logic swmod;
+        logic overflow;
+    } soc_ifc_reg__internal_rv_mtime_l__count_l__out_t;
+
+    typedef struct packed{
+        soc_ifc_reg__internal_rv_mtime_l__count_l__out_t count_l;
+    } soc_ifc_reg__internal_rv_mtime_l__out_t;
+
+    typedef struct packed{
+        logic [31:0] value;
+        logic swmod;
+    } soc_ifc_reg__internal_rv_mtime_h__count_h__out_t;
+
+    typedef struct packed{
+        soc_ifc_reg__internal_rv_mtime_h__count_h__out_t count_h;
+    } soc_ifc_reg__internal_rv_mtime_h__out_t;
+
+    typedef struct packed{
+        logic [31:0] value;
+    } soc_ifc_reg__internal_rv_mtimecmp_l__compare_l__out_t;
+
+    typedef struct packed{
+        soc_ifc_reg__internal_rv_mtimecmp_l__compare_l__out_t compare_l;
+    } soc_ifc_reg__internal_rv_mtimecmp_l__out_t;
+
+    typedef struct packed{
+        logic [31:0] value;
+    } soc_ifc_reg__internal_rv_mtimecmp_h__compare_h__out_t;
+
+    typedef struct packed{
+        soc_ifc_reg__internal_rv_mtimecmp_h__compare_h__out_t compare_h;
+    } soc_ifc_reg__internal_rv_mtimecmp_h__out_t;
+
     typedef struct packed{
         logic intr;
     } soc_ifc_reg__intr_block_t__global_intr_t_agg_sts_dd3dcf0a__out_t;
@@ -765,13 +949,13 @@ package soc_ifc_reg_pkg;
 
     typedef struct packed{
         logic intr;
-    } soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_mbox_ecc_cor_sts_5c3d26bb_notif_soc_req_lock_sts_deddde70__out_t;
+    } soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70__out_t;
 
     typedef struct packed{
         soc_ifc_reg__intr_block_t__global_intr_t_agg_sts_dd3dcf0a__out_t error_global_intr_r;
         soc_ifc_reg__intr_block_t__global_intr_t_agg_sts_e6399b4a__out_t notif_global_intr_r;
         soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f__out_t error_internal_intr_r;
-        soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_mbox_ecc_cor_sts_5c3d26bb_notif_soc_req_lock_sts_deddde70__out_t notif_internal_intr_r;
+        soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70__out_t notif_internal_intr_r;
     } soc_ifc_reg__intr_block_t__out_t;
 
     typedef struct packed{
@@ -790,6 +974,7 @@ package soc_ifc_reg_pkg;
         soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER__out_t CPTRA_TRNG_VALID_PAUSER;
         soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK__out_t CPTRA_TRNG_PAUSER_LOCK;
         soc_ifc_reg__CPTRA_TRNG_DATA__out_t [12-1:0]CPTRA_TRNG_DATA;
+        soc_ifc_reg__CPTRA_TRNG_CTRL__out_t CPTRA_TRNG_CTRL;
         soc_ifc_reg__CPTRA_TRNG_STATUS__out_t CPTRA_TRNG_STATUS;
         soc_ifc_reg__CPTRA_FUSE_WR_DONE__out_t CPTRA_FUSE_WR_DONE;
         soc_ifc_reg__CPTRA_BOOTFSM_GO__out_t CPTRA_BOOTFSM_GO;
@@ -797,7 +982,6 @@ package soc_ifc_reg_pkg;
         soc_ifc_reg__CPTRA_CLK_GATING_EN__out_t CPTRA_CLK_GATING_EN;
         soc_ifc_reg__CPTRA_GENERIC_INPUT_WIRES__out_t [2-1:0]CPTRA_GENERIC_INPUT_WIRES;
         soc_ifc_reg__CPTRA_GENERIC_OUTPUT_WIRES__out_t [2-1:0]CPTRA_GENERIC_OUTPUT_WIRES;
-        soc_ifc_reg__CPTRA_HW_REV_ID__out_t CPTRA_HW_REV_ID;
         soc_ifc_reg__CPTRA_FW_REV_ID__out_t [2-1:0]CPTRA_FW_REV_ID;
         soc_ifc_reg__CPTRA_WDT_TIMER1_EN__out_t CPTRA_WDT_TIMER1_EN;
         soc_ifc_reg__CPTRA_WDT_TIMER1_CTRL__out_t CPTRA_WDT_TIMER1_CTRL;
@@ -806,6 +990,8 @@ package soc_ifc_reg_pkg;
         soc_ifc_reg__CPTRA_WDT_TIMER2_CTRL__out_t CPTRA_WDT_TIMER2_CTRL;
         soc_ifc_reg__CPTRA_WDT_TIMER2_TIMEOUT_PERIOD__out_t [2-1:0]CPTRA_WDT_TIMER2_TIMEOUT_PERIOD;
         soc_ifc_reg__CPTRA_WDT_STATUS__out_t CPTRA_WDT_STATUS;
+        soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER__out_t CPTRA_FUSE_VALID_PAUSER;
+        soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK__out_t CPTRA_FUSE_PAUSER_LOCK;
         soc_ifc_reg__fuse_uds_seed__out_t [12-1:0]fuse_uds_seed;
         soc_ifc_reg__fuse_field_entropy__out_t [8-1:0]fuse_field_entropy;
         soc_ifc_reg__fuse_key_manifest_pk_hash__out_t [12-1:0]fuse_key_manifest_pk_hash;
@@ -817,11 +1003,22 @@ package soc_ifc_reg_pkg;
         soc_ifc_reg__fuse_idevid_cert_attr__out_t [24-1:0]fuse_idevid_cert_attr;
         soc_ifc_reg__fuse_idevid_manuf_hsm_id__out_t [4-1:0]fuse_idevid_manuf_hsm_id;
         soc_ifc_reg__fuse_life_cycle__out_t fuse_life_cycle;
+        soc_ifc_reg__fuse_lms_verify__out_t fuse_lms_verify;
+        soc_ifc_reg__fuse_lms_revocation__out_t fuse_lms_revocation;
+        soc_ifc_reg__fuse_soc_stepping_id__out_t fuse_soc_stepping_id;
         soc_ifc_reg__internal_obf_key__out_t [8-1:0]internal_obf_key;
         soc_ifc_reg__internal_iccm_lock__out_t internal_iccm_lock;
         soc_ifc_reg__internal_fw_update_reset__out_t internal_fw_update_reset;
         soc_ifc_reg__internal_fw_update_reset_wait_cycles__out_t internal_fw_update_reset_wait_cycles;
         soc_ifc_reg__internal_nmi_vector__out_t internal_nmi_vector;
+        soc_ifc_reg__internal_hw_error_fatal_mask__out_t internal_hw_error_fatal_mask;
+        soc_ifc_reg__internal_hw_error_non_fatal_mask__out_t internal_hw_error_non_fatal_mask;
+        soc_ifc_reg__internal_fw_error_fatal_mask__out_t internal_fw_error_fatal_mask;
+        soc_ifc_reg__internal_fw_error_non_fatal_mask__out_t internal_fw_error_non_fatal_mask;
+        soc_ifc_reg__internal_rv_mtime_l__out_t internal_rv_mtime_l;
+        soc_ifc_reg__internal_rv_mtime_h__out_t internal_rv_mtime_h;
+        soc_ifc_reg__internal_rv_mtimecmp_l__out_t internal_rv_mtimecmp_l;
+        soc_ifc_reg__internal_rv_mtimecmp_h__out_t internal_rv_mtimecmp_h;
         soc_ifc_reg__intr_block_t__out_t intr_block_rf;
     } soc_ifc_reg__out_t;
 
diff --git a/src/soc_ifc/rtl/soc_ifc_reg_properties.rdl b/src/soc_ifc/rtl/soc_ifc_reg_properties.rdl
index 07a3092ed..4738904d4 100644
--- a/src/soc_ifc/rtl/soc_ifc_reg_properties.rdl
+++ b/src/soc_ifc/rtl/soc_ifc_reg_properties.rdl
@@ -29,9 +29,10 @@
 
     //defined fields by access type
     //first is uc access type, second is soc access type
-    field rw_ro {swwel = soc_req;}; //writes enabled only for uc
-    field rw_rw_sticky_hw {hw = rw; sw = rw; we = true; woclr = true; resetsignal = cptra_pwrgood;}; //writes enabled for both uc and soc - used by HW ERROR regs
-    field rw_rw_sticky {hw = rw; sw = rw; we = true; resetsignal = cptra_pwrgood;}; //writes enabled for both uc and soc - used by FW ERROR regs
+    field rw_ro    {swwel = soc_req;}; //writes enabled only for uc
+    field rw_ro_hw {swwel = soc_req; hw = r;}; //writes enabled only for uc, hw readable
+    field rw_rw_sticky_hw {hw = rw; sw = rw; we = true; woclr = true; resetsignal = cptra_pwrgood;}; //W1C    enabled for both uc and soc - used by HW ERROR regs
+    field rw_rw_sticky    {hw = rw; sw = rw; we = true; swmod = true; resetsignal = cptra_pwrgood;}; //writes enabled for both uc and soc - used by FW ERROR regs
     field ro_rw {swwe  = soc_req;}; //writes enabled only for soc
     field ro_ro {sw = r;};
     field rw_rw { };
diff --git a/src/soc_ifc/rtl/soc_ifc_reg_sample.svh b/src/soc_ifc/rtl/soc_ifc_reg_sample.svh
new file mode 100644
index 000000000..e677131de
--- /dev/null
+++ b/src/soc_ifc/rtl/soc_ifc_reg_sample.svh
@@ -0,0 +1,2769 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+`ifndef SOC_IFC_REG_SAMPLE
+    `define SOC_IFC_REG_SAMPLE
+    
+    /*----------------------- SOC_IFC_REG__CPTRA_HW_ERROR_FATAL SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__CPTRA_HW_ERROR_FATAL::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(iccm_ecc_unc_bit_cg[bt]) this.iccm_ecc_unc_bit_cg[bt].sample(data[0 + bt]);
+            foreach(dccm_ecc_unc_bit_cg[bt]) this.dccm_ecc_unc_bit_cg[bt].sample(data[1 + bt]);
+            foreach(nmi_pin_bit_cg[bt]) this.nmi_pin_bit_cg[bt].sample(data[2 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*iccm_ecc_unc*/  ,  data[1:1]/*dccm_ecc_unc*/  ,  data[2:2]/*nmi_pin*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__CPTRA_HW_ERROR_FATAL::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(iccm_ecc_unc_bit_cg[bt]) this.iccm_ecc_unc_bit_cg[bt].sample(iccm_ecc_unc.get_mirrored_value() >> bt);
+            foreach(dccm_ecc_unc_bit_cg[bt]) this.dccm_ecc_unc_bit_cg[bt].sample(dccm_ecc_unc.get_mirrored_value() >> bt);
+            foreach(nmi_pin_bit_cg[bt]) this.nmi_pin_bit_cg[bt].sample(nmi_pin.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( iccm_ecc_unc.get_mirrored_value()  ,  dccm_ecc_unc.get_mirrored_value()  ,  nmi_pin.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__CPTRA_HW_ERROR_NON_FATAL SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__CPTRA_HW_ERROR_NON_FATAL::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(mbox_prot_no_lock_bit_cg[bt]) this.mbox_prot_no_lock_bit_cg[bt].sample(data[0 + bt]);
+            foreach(mbox_prot_ooo_bit_cg[bt]) this.mbox_prot_ooo_bit_cg[bt].sample(data[1 + bt]);
+            foreach(mbox_ecc_unc_bit_cg[bt]) this.mbox_ecc_unc_bit_cg[bt].sample(data[2 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*mbox_prot_no_lock*/  ,  data[1:1]/*mbox_prot_ooo*/  ,  data[2:2]/*mbox_ecc_unc*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__CPTRA_HW_ERROR_NON_FATAL::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(mbox_prot_no_lock_bit_cg[bt]) this.mbox_prot_no_lock_bit_cg[bt].sample(mbox_prot_no_lock.get_mirrored_value() >> bt);
+            foreach(mbox_prot_ooo_bit_cg[bt]) this.mbox_prot_ooo_bit_cg[bt].sample(mbox_prot_ooo.get_mirrored_value() >> bt);
+            foreach(mbox_ecc_unc_bit_cg[bt]) this.mbox_ecc_unc_bit_cg[bt].sample(mbox_ecc_unc.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( mbox_prot_no_lock.get_mirrored_value()  ,  mbox_prot_ooo.get_mirrored_value()  ,  mbox_ecc_unc.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__CPTRA_FW_ERROR_FATAL SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__CPTRA_FW_ERROR_FATAL::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(error_code_bit_cg[bt]) this.error_code_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*error_code*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__CPTRA_FW_ERROR_FATAL::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(error_code_bit_cg[bt]) this.error_code_bit_cg[bt].sample(error_code.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( error_code.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__CPTRA_FW_ERROR_NON_FATAL SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__CPTRA_FW_ERROR_NON_FATAL::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(error_code_bit_cg[bt]) this.error_code_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*error_code*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__CPTRA_FW_ERROR_NON_FATAL::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(error_code_bit_cg[bt]) this.error_code_bit_cg[bt].sample(error_code.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( error_code.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__CPTRA_HW_ERROR_ENC SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__CPTRA_HW_ERROR_ENC::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(error_code_bit_cg[bt]) this.error_code_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*error_code*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__CPTRA_HW_ERROR_ENC::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(error_code_bit_cg[bt]) this.error_code_bit_cg[bt].sample(error_code.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( error_code.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__CPTRA_FW_ERROR_ENC SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__CPTRA_FW_ERROR_ENC::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(error_code_bit_cg[bt]) this.error_code_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*error_code*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__CPTRA_FW_ERROR_ENC::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(error_code_bit_cg[bt]) this.error_code_bit_cg[bt].sample(error_code.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( error_code.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__CPTRA_FW_EXTENDED_ERROR_INFO SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__CPTRA_FW_EXTENDED_ERROR_INFO::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(error_info_bit_cg[bt]) this.error_info_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*error_info*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__CPTRA_FW_EXTENDED_ERROR_INFO::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(error_info_bit_cg[bt]) this.error_info_bit_cg[bt].sample(error_info.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( error_info.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__CPTRA_BOOT_STATUS SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__CPTRA_BOOT_STATUS::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(status_bit_cg[bt]) this.status_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*status*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__CPTRA_BOOT_STATUS::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(status_bit_cg[bt]) this.status_bit_cg[bt].sample(status.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( status.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__CPTRA_FLOW_STATUS SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__CPTRA_FLOW_STATUS::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(status_bit_cg[bt]) this.status_bit_cg[bt].sample(data[0 + bt]);
+            foreach(idevid_csr_ready_bit_cg[bt]) this.idevid_csr_ready_bit_cg[bt].sample(data[24 + bt]);
+            foreach(boot_fsm_ps_bit_cg[bt]) this.boot_fsm_ps_bit_cg[bt].sample(data[25 + bt]);
+            foreach(ready_for_fw_bit_cg[bt]) this.ready_for_fw_bit_cg[bt].sample(data[28 + bt]);
+            foreach(ready_for_runtime_bit_cg[bt]) this.ready_for_runtime_bit_cg[bt].sample(data[29 + bt]);
+            foreach(ready_for_fuses_bit_cg[bt]) this.ready_for_fuses_bit_cg[bt].sample(data[30 + bt]);
+            foreach(mailbox_flow_done_bit_cg[bt]) this.mailbox_flow_done_bit_cg[bt].sample(data[31 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[23:0]/*status*/  ,  data[24:24]/*idevid_csr_ready*/  ,  data[27:25]/*boot_fsm_ps*/  ,  data[28:28]/*ready_for_fw*/  ,  data[29:29]/*ready_for_runtime*/  ,  data[30:30]/*ready_for_fuses*/  ,  data[31:31]/*mailbox_flow_done*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__CPTRA_FLOW_STATUS::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(status_bit_cg[bt]) this.status_bit_cg[bt].sample(status.get_mirrored_value() >> bt);
+            foreach(idevid_csr_ready_bit_cg[bt]) this.idevid_csr_ready_bit_cg[bt].sample(idevid_csr_ready.get_mirrored_value() >> bt);
+            foreach(boot_fsm_ps_bit_cg[bt]) this.boot_fsm_ps_bit_cg[bt].sample(boot_fsm_ps.get_mirrored_value() >> bt);
+            foreach(ready_for_fw_bit_cg[bt]) this.ready_for_fw_bit_cg[bt].sample(ready_for_fw.get_mirrored_value() >> bt);
+            foreach(ready_for_runtime_bit_cg[bt]) this.ready_for_runtime_bit_cg[bt].sample(ready_for_runtime.get_mirrored_value() >> bt);
+            foreach(ready_for_fuses_bit_cg[bt]) this.ready_for_fuses_bit_cg[bt].sample(ready_for_fuses.get_mirrored_value() >> bt);
+            foreach(mailbox_flow_done_bit_cg[bt]) this.mailbox_flow_done_bit_cg[bt].sample(mailbox_flow_done.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( status.get_mirrored_value()  ,  idevid_csr_ready.get_mirrored_value()  ,  boot_fsm_ps.get_mirrored_value()  ,  ready_for_fw.get_mirrored_value()  ,  ready_for_runtime.get_mirrored_value()  ,  ready_for_fuses.get_mirrored_value()  ,  mailbox_flow_done.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__CPTRA_RESET_REASON SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__CPTRA_RESET_REASON::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(FW_UPD_RESET_bit_cg[bt]) this.FW_UPD_RESET_bit_cg[bt].sample(data[0 + bt]);
+            foreach(WARM_RESET_bit_cg[bt]) this.WARM_RESET_bit_cg[bt].sample(data[1 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*FW_UPD_RESET*/  ,  data[1:1]/*WARM_RESET*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__CPTRA_RESET_REASON::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(FW_UPD_RESET_bit_cg[bt]) this.FW_UPD_RESET_bit_cg[bt].sample(FW_UPD_RESET.get_mirrored_value() >> bt);
+            foreach(WARM_RESET_bit_cg[bt]) this.WARM_RESET_bit_cg[bt].sample(WARM_RESET.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( FW_UPD_RESET.get_mirrored_value()  ,  WARM_RESET.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__CPTRA_SECURITY_STATE SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__CPTRA_SECURITY_STATE::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(device_lifecycle_bit_cg[bt]) this.device_lifecycle_bit_cg[bt].sample(data[0 + bt]);
+            foreach(debug_locked_bit_cg[bt]) this.debug_locked_bit_cg[bt].sample(data[2 + bt]);
+            foreach(scan_mode_bit_cg[bt]) this.scan_mode_bit_cg[bt].sample(data[3 + bt]);
+            foreach(rsvd_bit_cg[bt]) this.rsvd_bit_cg[bt].sample(data[4 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[1:0]/*device_lifecycle*/  ,  data[2:2]/*debug_locked*/  ,  data[3:3]/*scan_mode*/  ,  data[31:4]/*rsvd*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__CPTRA_SECURITY_STATE::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(device_lifecycle_bit_cg[bt]) this.device_lifecycle_bit_cg[bt].sample(device_lifecycle.get_mirrored_value() >> bt);
+            foreach(debug_locked_bit_cg[bt]) this.debug_locked_bit_cg[bt].sample(debug_locked.get_mirrored_value() >> bt);
+            foreach(scan_mode_bit_cg[bt]) this.scan_mode_bit_cg[bt].sample(scan_mode.get_mirrored_value() >> bt);
+            foreach(rsvd_bit_cg[bt]) this.rsvd_bit_cg[bt].sample(rsvd.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( device_lifecycle.get_mirrored_value()  ,  debug_locked.get_mirrored_value()  ,  scan_mode.get_mirrored_value()  ,  rsvd.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__CPTRA_MBOX_VALID_PAUSER SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(PAUSER_bit_cg[bt]) this.PAUSER_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*PAUSER*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(PAUSER_bit_cg[bt]) this.PAUSER_bit_cg[bt].sample(PAUSER.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( PAUSER.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__CPTRA_MBOX_PAUSER_LOCK SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(LOCK_bit_cg[bt]) this.LOCK_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*LOCK*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(LOCK_bit_cg[bt]) this.LOCK_bit_cg[bt].sample(LOCK.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( LOCK.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__CPTRA_TRNG_VALID_PAUSER SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(PAUSER_bit_cg[bt]) this.PAUSER_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*PAUSER*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(PAUSER_bit_cg[bt]) this.PAUSER_bit_cg[bt].sample(PAUSER.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( PAUSER.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__CPTRA_TRNG_PAUSER_LOCK SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(LOCK_bit_cg[bt]) this.LOCK_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*LOCK*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(LOCK_bit_cg[bt]) this.LOCK_bit_cg[bt].sample(LOCK.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( LOCK.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__CPTRA_TRNG_DATA SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__CPTRA_TRNG_DATA::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(DATA_bit_cg[bt]) this.DATA_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*DATA*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__CPTRA_TRNG_DATA::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(DATA_bit_cg[bt]) this.DATA_bit_cg[bt].sample(DATA.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( DATA.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__CPTRA_TRNG_CTRL SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__CPTRA_TRNG_CTRL::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(clear_bit_cg[bt]) this.clear_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*clear*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__CPTRA_TRNG_CTRL::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(clear_bit_cg[bt]) this.clear_bit_cg[bt].sample(clear.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( clear.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__CPTRA_TRNG_STATUS SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__CPTRA_TRNG_STATUS::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(DATA_REQ_bit_cg[bt]) this.DATA_REQ_bit_cg[bt].sample(data[0 + bt]);
+            foreach(DATA_WR_DONE_bit_cg[bt]) this.DATA_WR_DONE_bit_cg[bt].sample(data[1 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*DATA_REQ*/  ,  data[1:1]/*DATA_WR_DONE*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__CPTRA_TRNG_STATUS::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(DATA_REQ_bit_cg[bt]) this.DATA_REQ_bit_cg[bt].sample(DATA_REQ.get_mirrored_value() >> bt);
+            foreach(DATA_WR_DONE_bit_cg[bt]) this.DATA_WR_DONE_bit_cg[bt].sample(DATA_WR_DONE.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( DATA_REQ.get_mirrored_value()  ,  DATA_WR_DONE.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__CPTRA_FUSE_WR_DONE SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__CPTRA_FUSE_WR_DONE::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(done_bit_cg[bt]) this.done_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*done*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__CPTRA_FUSE_WR_DONE::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(done_bit_cg[bt]) this.done_bit_cg[bt].sample(done.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( done.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__CPTRA_TIMER_CONFIG SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__CPTRA_TIMER_CONFIG::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(clk_period_bit_cg[bt]) this.clk_period_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*clk_period*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__CPTRA_TIMER_CONFIG::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(clk_period_bit_cg[bt]) this.clk_period_bit_cg[bt].sample(clk_period.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( clk_period.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__CPTRA_BOOTFSM_GO SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__CPTRA_BOOTFSM_GO::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(GO_bit_cg[bt]) this.GO_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*GO*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__CPTRA_BOOTFSM_GO::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(GO_bit_cg[bt]) this.GO_bit_cg[bt].sample(GO.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( GO.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__CPTRA_DBG_MANUF_SERVICE_REG SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__CPTRA_DBG_MANUF_SERVICE_REG::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(DATA_bit_cg[bt]) this.DATA_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*DATA*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__CPTRA_DBG_MANUF_SERVICE_REG::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(DATA_bit_cg[bt]) this.DATA_bit_cg[bt].sample(DATA.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( DATA.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__CPTRA_CLK_GATING_EN SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__CPTRA_CLK_GATING_EN::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(clk_gating_en_bit_cg[bt]) this.clk_gating_en_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*clk_gating_en*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__CPTRA_CLK_GATING_EN::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(clk_gating_en_bit_cg[bt]) this.clk_gating_en_bit_cg[bt].sample(clk_gating_en.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( clk_gating_en.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__CPTRA_GENERIC_INPUT_WIRES SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__CPTRA_GENERIC_INPUT_WIRES::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(generic_wires_bit_cg[bt]) this.generic_wires_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*generic_wires*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__CPTRA_GENERIC_INPUT_WIRES::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(generic_wires_bit_cg[bt]) this.generic_wires_bit_cg[bt].sample(generic_wires.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( generic_wires.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__CPTRA_GENERIC_OUTPUT_WIRES SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__CPTRA_GENERIC_OUTPUT_WIRES::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(generic_wires_bit_cg[bt]) this.generic_wires_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*generic_wires*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__CPTRA_GENERIC_OUTPUT_WIRES::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(generic_wires_bit_cg[bt]) this.generic_wires_bit_cg[bt].sample(generic_wires.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( generic_wires.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__CPTRA_HW_REV_ID SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__CPTRA_HW_REV_ID::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(CPTRA_GENERATION_bit_cg[bt]) this.CPTRA_GENERATION_bit_cg[bt].sample(data[0 + bt]);
+            foreach(SOC_STEPPING_ID_bit_cg[bt]) this.SOC_STEPPING_ID_bit_cg[bt].sample(data[16 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[15:0]/*CPTRA_GENERATION*/  ,  data[31:16]/*SOC_STEPPING_ID*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__CPTRA_HW_REV_ID::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(CPTRA_GENERATION_bit_cg[bt]) this.CPTRA_GENERATION_bit_cg[bt].sample(CPTRA_GENERATION.get_mirrored_value() >> bt);
+            foreach(SOC_STEPPING_ID_bit_cg[bt]) this.SOC_STEPPING_ID_bit_cg[bt].sample(SOC_STEPPING_ID.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( CPTRA_GENERATION.get_mirrored_value()  ,  SOC_STEPPING_ID.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__CPTRA_FW_REV_ID SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__CPTRA_FW_REV_ID::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(REV_ID_bit_cg[bt]) this.REV_ID_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*REV_ID*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__CPTRA_FW_REV_ID::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(REV_ID_bit_cg[bt]) this.REV_ID_bit_cg[bt].sample(REV_ID.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( REV_ID.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__CPTRA_HW_CONFIG SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__CPTRA_HW_CONFIG::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(iTRNG_en_bit_cg[bt]) this.iTRNG_en_bit_cg[bt].sample(data[0 + bt]);
+            foreach(QSPI_en_bit_cg[bt]) this.QSPI_en_bit_cg[bt].sample(data[1 + bt]);
+            foreach(I3C_en_bit_cg[bt]) this.I3C_en_bit_cg[bt].sample(data[2 + bt]);
+            foreach(UART_en_bit_cg[bt]) this.UART_en_bit_cg[bt].sample(data[3 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*iTRNG_en*/  ,  data[1:1]/*QSPI_en*/  ,  data[2:2]/*I3C_en*/  ,  data[3:3]/*UART_en*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__CPTRA_HW_CONFIG::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(iTRNG_en_bit_cg[bt]) this.iTRNG_en_bit_cg[bt].sample(iTRNG_en.get_mirrored_value() >> bt);
+            foreach(QSPI_en_bit_cg[bt]) this.QSPI_en_bit_cg[bt].sample(QSPI_en.get_mirrored_value() >> bt);
+            foreach(I3C_en_bit_cg[bt]) this.I3C_en_bit_cg[bt].sample(I3C_en.get_mirrored_value() >> bt);
+            foreach(UART_en_bit_cg[bt]) this.UART_en_bit_cg[bt].sample(UART_en.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( iTRNG_en.get_mirrored_value()  ,  QSPI_en.get_mirrored_value()  ,  I3C_en.get_mirrored_value()  ,  UART_en.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__CPTRA_WDT_TIMER1_EN SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__CPTRA_WDT_TIMER1_EN::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(timer1_en_bit_cg[bt]) this.timer1_en_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*timer1_en*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__CPTRA_WDT_TIMER1_EN::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(timer1_en_bit_cg[bt]) this.timer1_en_bit_cg[bt].sample(timer1_en.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( timer1_en.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__CPTRA_WDT_TIMER1_CTRL SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__CPTRA_WDT_TIMER1_CTRL::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(timer1_restart_bit_cg[bt]) this.timer1_restart_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*timer1_restart*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__CPTRA_WDT_TIMER1_CTRL::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(timer1_restart_bit_cg[bt]) this.timer1_restart_bit_cg[bt].sample(timer1_restart.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( timer1_restart.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__CPTRA_WDT_TIMER1_TIMEOUT_PERIOD SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__CPTRA_WDT_TIMER1_TIMEOUT_PERIOD::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(timer1_timeout_period_bit_cg[bt]) this.timer1_timeout_period_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*timer1_timeout_period*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__CPTRA_WDT_TIMER1_TIMEOUT_PERIOD::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(timer1_timeout_period_bit_cg[bt]) this.timer1_timeout_period_bit_cg[bt].sample(timer1_timeout_period.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( timer1_timeout_period.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__CPTRA_WDT_TIMER2_EN SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__CPTRA_WDT_TIMER2_EN::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(timer2_en_bit_cg[bt]) this.timer2_en_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*timer2_en*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__CPTRA_WDT_TIMER2_EN::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(timer2_en_bit_cg[bt]) this.timer2_en_bit_cg[bt].sample(timer2_en.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( timer2_en.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__CPTRA_WDT_TIMER2_CTRL SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__CPTRA_WDT_TIMER2_CTRL::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(timer2_restart_bit_cg[bt]) this.timer2_restart_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*timer2_restart*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__CPTRA_WDT_TIMER2_CTRL::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(timer2_restart_bit_cg[bt]) this.timer2_restart_bit_cg[bt].sample(timer2_restart.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( timer2_restart.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__CPTRA_WDT_TIMER2_TIMEOUT_PERIOD SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__CPTRA_WDT_TIMER2_TIMEOUT_PERIOD::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(timer2_timeout_period_bit_cg[bt]) this.timer2_timeout_period_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*timer2_timeout_period*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__CPTRA_WDT_TIMER2_TIMEOUT_PERIOD::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(timer2_timeout_period_bit_cg[bt]) this.timer2_timeout_period_bit_cg[bt].sample(timer2_timeout_period.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( timer2_timeout_period.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__CPTRA_WDT_STATUS SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__CPTRA_WDT_STATUS::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(t1_timeout_bit_cg[bt]) this.t1_timeout_bit_cg[bt].sample(data[0 + bt]);
+            foreach(t2_timeout_bit_cg[bt]) this.t2_timeout_bit_cg[bt].sample(data[1 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*t1_timeout*/  ,  data[1:1]/*t2_timeout*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__CPTRA_WDT_STATUS::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(t1_timeout_bit_cg[bt]) this.t1_timeout_bit_cg[bt].sample(t1_timeout.get_mirrored_value() >> bt);
+            foreach(t2_timeout_bit_cg[bt]) this.t2_timeout_bit_cg[bt].sample(t2_timeout.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( t1_timeout.get_mirrored_value()  ,  t2_timeout.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__CPTRA_FUSE_VALID_PAUSER SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(PAUSER_bit_cg[bt]) this.PAUSER_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*PAUSER*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(PAUSER_bit_cg[bt]) this.PAUSER_bit_cg[bt].sample(PAUSER.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( PAUSER.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__CPTRA_FUSE_PAUSER_LOCK SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(LOCK_bit_cg[bt]) this.LOCK_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*LOCK*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(LOCK_bit_cg[bt]) this.LOCK_bit_cg[bt].sample(LOCK.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( LOCK.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__CPTRA_WDT_CFG SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__CPTRA_WDT_CFG::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(TIMEOUT_bit_cg[bt]) this.TIMEOUT_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*TIMEOUT*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__CPTRA_WDT_CFG::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(TIMEOUT_bit_cg[bt]) this.TIMEOUT_bit_cg[bt].sample(TIMEOUT.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( TIMEOUT.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__CPTRA_ITRNG_ENTROPY_CONFIG_0 SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_0::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(low_threshold_bit_cg[bt]) this.low_threshold_bit_cg[bt].sample(data[0 + bt]);
+            foreach(high_threshold_bit_cg[bt]) this.high_threshold_bit_cg[bt].sample(data[16 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[15:0]/*low_threshold*/  ,  data[31:16]/*high_threshold*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_0::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(low_threshold_bit_cg[bt]) this.low_threshold_bit_cg[bt].sample(low_threshold.get_mirrored_value() >> bt);
+            foreach(high_threshold_bit_cg[bt]) this.high_threshold_bit_cg[bt].sample(high_threshold.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( low_threshold.get_mirrored_value()  ,  high_threshold.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__CPTRA_ITRNG_ENTROPY_CONFIG_1 SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_1::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(repetition_count_bit_cg[bt]) this.repetition_count_bit_cg[bt].sample(data[0 + bt]);
+            foreach(RSVD_bit_cg[bt]) this.RSVD_bit_cg[bt].sample(data[16 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[15:0]/*repetition_count*/  ,  data[31:16]/*RSVD*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_1::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(repetition_count_bit_cg[bt]) this.repetition_count_bit_cg[bt].sample(repetition_count.get_mirrored_value() >> bt);
+            foreach(RSVD_bit_cg[bt]) this.RSVD_bit_cg[bt].sample(RSVD.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( repetition_count.get_mirrored_value()  ,  RSVD.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__CPTRA_RSVD_REG SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__CPTRA_RSVD_REG::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(RSVD_bit_cg[bt]) this.RSVD_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*RSVD*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__CPTRA_RSVD_REG::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(RSVD_bit_cg[bt]) this.RSVD_bit_cg[bt].sample(RSVD.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( RSVD.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__FUSE_UDS_SEED SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__fuse_uds_seed::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(seed_bit_cg[bt]) this.seed_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*seed*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__fuse_uds_seed::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(seed_bit_cg[bt]) this.seed_bit_cg[bt].sample(seed.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( seed.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__FUSE_FIELD_ENTROPY SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__fuse_field_entropy::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(seed_bit_cg[bt]) this.seed_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*seed*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__fuse_field_entropy::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(seed_bit_cg[bt]) this.seed_bit_cg[bt].sample(seed.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( seed.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__FUSE_KEY_MANIFEST_PK_HASH SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__fuse_key_manifest_pk_hash::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(hash_bit_cg[bt]) this.hash_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*hash*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__fuse_key_manifest_pk_hash::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(hash_bit_cg[bt]) this.hash_bit_cg[bt].sample(hash.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( hash.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__FUSE_KEY_MANIFEST_PK_HASH_MASK SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__fuse_key_manifest_pk_hash_mask::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(mask_bit_cg[bt]) this.mask_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[3:0]/*mask*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__fuse_key_manifest_pk_hash_mask::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(mask_bit_cg[bt]) this.mask_bit_cg[bt].sample(mask.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( mask.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__FUSE_OWNER_PK_HASH SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__fuse_owner_pk_hash::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(hash_bit_cg[bt]) this.hash_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*hash*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__fuse_owner_pk_hash::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(hash_bit_cg[bt]) this.hash_bit_cg[bt].sample(hash.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( hash.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__FUSE_FMC_KEY_MANIFEST_SVN SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__fuse_fmc_key_manifest_svn::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(svn_bit_cg[bt]) this.svn_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*svn*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__fuse_fmc_key_manifest_svn::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(svn_bit_cg[bt]) this.svn_bit_cg[bt].sample(svn.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( svn.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__FUSE_RUNTIME_SVN SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__fuse_runtime_svn::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(svn_bit_cg[bt]) this.svn_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*svn*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__fuse_runtime_svn::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(svn_bit_cg[bt]) this.svn_bit_cg[bt].sample(svn.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( svn.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__FUSE_ANTI_ROLLBACK_DISABLE SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__fuse_anti_rollback_disable::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(dis_bit_cg[bt]) this.dis_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*dis*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__fuse_anti_rollback_disable::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(dis_bit_cg[bt]) this.dis_bit_cg[bt].sample(dis.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( dis.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__FUSE_IDEVID_CERT_ATTR SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__fuse_idevid_cert_attr::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(cert_bit_cg[bt]) this.cert_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*cert*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__fuse_idevid_cert_attr::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(cert_bit_cg[bt]) this.cert_bit_cg[bt].sample(cert.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( cert.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__FUSE_IDEVID_MANUF_HSM_ID SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__fuse_idevid_manuf_hsm_id::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(hsm_id_bit_cg[bt]) this.hsm_id_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*hsm_id*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__fuse_idevid_manuf_hsm_id::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(hsm_id_bit_cg[bt]) this.hsm_id_bit_cg[bt].sample(hsm_id.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( hsm_id.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__FUSE_LIFE_CYCLE SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__fuse_life_cycle::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(life_cycle_bit_cg[bt]) this.life_cycle_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[1:0]/*life_cycle*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__fuse_life_cycle::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(life_cycle_bit_cg[bt]) this.life_cycle_bit_cg[bt].sample(life_cycle.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( life_cycle.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__FUSE_LMS_VERIFY SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__fuse_lms_verify::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(lms_verify_bit_cg[bt]) this.lms_verify_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*lms_verify*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__fuse_lms_verify::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(lms_verify_bit_cg[bt]) this.lms_verify_bit_cg[bt].sample(lms_verify.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( lms_verify.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__FUSE_LMS_REVOCATION SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__fuse_lms_revocation::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(lms_revocation_bit_cg[bt]) this.lms_revocation_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*lms_revocation*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__fuse_lms_revocation::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(lms_revocation_bit_cg[bt]) this.lms_revocation_bit_cg[bt].sample(lms_revocation.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( lms_revocation.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__FUSE_SOC_STEPPING_ID SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__fuse_soc_stepping_id::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(soc_stepping_id_bit_cg[bt]) this.soc_stepping_id_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[15:0]/*soc_stepping_id*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__fuse_soc_stepping_id::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(soc_stepping_id_bit_cg[bt]) this.soc_stepping_id_bit_cg[bt].sample(soc_stepping_id.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( soc_stepping_id.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTERNAL_OBF_KEY SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__internal_obf_key::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(key_bit_cg[bt]) this.key_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*key*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__internal_obf_key::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(key_bit_cg[bt]) this.key_bit_cg[bt].sample(key.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( key.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTERNAL_ICCM_LOCK SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__internal_iccm_lock::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(lock_bit_cg[bt]) this.lock_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*lock*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__internal_iccm_lock::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(lock_bit_cg[bt]) this.lock_bit_cg[bt].sample(lock.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( lock.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTERNAL_FW_UPDATE_RESET SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__internal_fw_update_reset::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(core_rst_bit_cg[bt]) this.core_rst_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*core_rst*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__internal_fw_update_reset::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(core_rst_bit_cg[bt]) this.core_rst_bit_cg[bt].sample(core_rst.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( core_rst.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__internal_fw_update_reset_wait_cycles::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(wait_cycles_bit_cg[bt]) this.wait_cycles_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[7:0]/*wait_cycles*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__internal_fw_update_reset_wait_cycles::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(wait_cycles_bit_cg[bt]) this.wait_cycles_bit_cg[bt].sample(wait_cycles.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( wait_cycles.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTERNAL_NMI_VECTOR SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__internal_nmi_vector::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(vec_bit_cg[bt]) this.vec_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*vec*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__internal_nmi_vector::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(vec_bit_cg[bt]) this.vec_bit_cg[bt].sample(vec.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( vec.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTERNAL_HW_ERROR_FATAL_MASK SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__internal_hw_error_fatal_mask::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(mask_iccm_ecc_unc_bit_cg[bt]) this.mask_iccm_ecc_unc_bit_cg[bt].sample(data[0 + bt]);
+            foreach(mask_dccm_ecc_unc_bit_cg[bt]) this.mask_dccm_ecc_unc_bit_cg[bt].sample(data[1 + bt]);
+            foreach(mask_nmi_pin_bit_cg[bt]) this.mask_nmi_pin_bit_cg[bt].sample(data[2 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*mask_iccm_ecc_unc*/  ,  data[1:1]/*mask_dccm_ecc_unc*/  ,  data[2:2]/*mask_nmi_pin*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__internal_hw_error_fatal_mask::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(mask_iccm_ecc_unc_bit_cg[bt]) this.mask_iccm_ecc_unc_bit_cg[bt].sample(mask_iccm_ecc_unc.get_mirrored_value() >> bt);
+            foreach(mask_dccm_ecc_unc_bit_cg[bt]) this.mask_dccm_ecc_unc_bit_cg[bt].sample(mask_dccm_ecc_unc.get_mirrored_value() >> bt);
+            foreach(mask_nmi_pin_bit_cg[bt]) this.mask_nmi_pin_bit_cg[bt].sample(mask_nmi_pin.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( mask_iccm_ecc_unc.get_mirrored_value()  ,  mask_dccm_ecc_unc.get_mirrored_value()  ,  mask_nmi_pin.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTERNAL_HW_ERROR_NON_FATAL_MASK SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__internal_hw_error_non_fatal_mask::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(mask_mbox_prot_no_lock_bit_cg[bt]) this.mask_mbox_prot_no_lock_bit_cg[bt].sample(data[0 + bt]);
+            foreach(mask_mbox_prot_ooo_bit_cg[bt]) this.mask_mbox_prot_ooo_bit_cg[bt].sample(data[1 + bt]);
+            foreach(mask_mbox_ecc_unc_bit_cg[bt]) this.mask_mbox_ecc_unc_bit_cg[bt].sample(data[2 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*mask_mbox_prot_no_lock*/  ,  data[1:1]/*mask_mbox_prot_ooo*/  ,  data[2:2]/*mask_mbox_ecc_unc*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__internal_hw_error_non_fatal_mask::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(mask_mbox_prot_no_lock_bit_cg[bt]) this.mask_mbox_prot_no_lock_bit_cg[bt].sample(mask_mbox_prot_no_lock.get_mirrored_value() >> bt);
+            foreach(mask_mbox_prot_ooo_bit_cg[bt]) this.mask_mbox_prot_ooo_bit_cg[bt].sample(mask_mbox_prot_ooo.get_mirrored_value() >> bt);
+            foreach(mask_mbox_ecc_unc_bit_cg[bt]) this.mask_mbox_ecc_unc_bit_cg[bt].sample(mask_mbox_ecc_unc.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( mask_mbox_prot_no_lock.get_mirrored_value()  ,  mask_mbox_prot_ooo.get_mirrored_value()  ,  mask_mbox_ecc_unc.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTERNAL_FW_ERROR_FATAL_MASK SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__internal_fw_error_fatal_mask::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(mask_bit_cg[bt]) this.mask_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*mask*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__internal_fw_error_fatal_mask::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(mask_bit_cg[bt]) this.mask_bit_cg[bt].sample(mask.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( mask.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTERNAL_FW_ERROR_NON_FATAL_MASK SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__internal_fw_error_non_fatal_mask::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(mask_bit_cg[bt]) this.mask_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*mask*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__internal_fw_error_non_fatal_mask::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(mask_bit_cg[bt]) this.mask_bit_cg[bt].sample(mask.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( mask.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTERNAL_RV_MTIME_L SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__internal_rv_mtime_l::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(count_l_bit_cg[bt]) this.count_l_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*count_l*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__internal_rv_mtime_l::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(count_l_bit_cg[bt]) this.count_l_bit_cg[bt].sample(count_l.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( count_l.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTERNAL_RV_MTIME_H SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__internal_rv_mtime_h::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(count_h_bit_cg[bt]) this.count_h_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*count_h*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__internal_rv_mtime_h::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(count_h_bit_cg[bt]) this.count_h_bit_cg[bt].sample(count_h.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( count_h.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTERNAL_RV_MTIMECMP_L SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__internal_rv_mtimecmp_l::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(compare_l_bit_cg[bt]) this.compare_l_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*compare_l*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__internal_rv_mtimecmp_l::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(compare_l_bit_cg[bt]) this.compare_l_bit_cg[bt].sample(compare_l.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( compare_l.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTERNAL_RV_MTIMECMP_H SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__internal_rv_mtimecmp_h::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(compare_h_bit_cg[bt]) this.compare_h_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*compare_h*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__internal_rv_mtimecmp_h::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(compare_h_bit_cg[bt]) this.compare_h_bit_cg[bt].sample(compare_h.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( compare_h.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__GLOBAL_INTR_EN_T SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__intr_block_t__global_intr_en_t::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(error_en_bit_cg[bt]) this.error_en_bit_cg[bt].sample(data[0 + bt]);
+            foreach(notif_en_bit_cg[bt]) this.notif_en_bit_cg[bt].sample(data[1 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*error_en*/  ,  data[1:1]/*notif_en*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__intr_block_t__global_intr_en_t::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(error_en_bit_cg[bt]) this.error_en_bit_cg[bt].sample(error_en.get_mirrored_value() >> bt);
+            foreach(notif_en_bit_cg[bt]) this.notif_en_bit_cg[bt].sample(notif_en.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( error_en.get_mirrored_value()  ,  notif_en.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__ERROR_INTR_EN_T SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__intr_block_t__error_intr_en_t::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(error_internal_en_bit_cg[bt]) this.error_internal_en_bit_cg[bt].sample(data[0 + bt]);
+            foreach(error_inv_dev_en_bit_cg[bt]) this.error_inv_dev_en_bit_cg[bt].sample(data[1 + bt]);
+            foreach(error_cmd_fail_en_bit_cg[bt]) this.error_cmd_fail_en_bit_cg[bt].sample(data[2 + bt]);
+            foreach(error_bad_fuse_en_bit_cg[bt]) this.error_bad_fuse_en_bit_cg[bt].sample(data[3 + bt]);
+            foreach(error_iccm_blocked_en_bit_cg[bt]) this.error_iccm_blocked_en_bit_cg[bt].sample(data[4 + bt]);
+            foreach(error_mbox_ecc_unc_en_bit_cg[bt]) this.error_mbox_ecc_unc_en_bit_cg[bt].sample(data[5 + bt]);
+            foreach(error_wdt_timer1_timeout_en_bit_cg[bt]) this.error_wdt_timer1_timeout_en_bit_cg[bt].sample(data[6 + bt]);
+            foreach(error_wdt_timer2_timeout_en_bit_cg[bt]) this.error_wdt_timer2_timeout_en_bit_cg[bt].sample(data[7 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*error_internal_en*/  ,  data[1:1]/*error_inv_dev_en*/  ,  data[2:2]/*error_cmd_fail_en*/  ,  data[3:3]/*error_bad_fuse_en*/  ,  data[4:4]/*error_iccm_blocked_en*/  ,  data[5:5]/*error_mbox_ecc_unc_en*/  ,  data[6:6]/*error_wdt_timer1_timeout_en*/  ,  data[7:7]/*error_wdt_timer2_timeout_en*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__intr_block_t__error_intr_en_t::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(error_internal_en_bit_cg[bt]) this.error_internal_en_bit_cg[bt].sample(error_internal_en.get_mirrored_value() >> bt);
+            foreach(error_inv_dev_en_bit_cg[bt]) this.error_inv_dev_en_bit_cg[bt].sample(error_inv_dev_en.get_mirrored_value() >> bt);
+            foreach(error_cmd_fail_en_bit_cg[bt]) this.error_cmd_fail_en_bit_cg[bt].sample(error_cmd_fail_en.get_mirrored_value() >> bt);
+            foreach(error_bad_fuse_en_bit_cg[bt]) this.error_bad_fuse_en_bit_cg[bt].sample(error_bad_fuse_en.get_mirrored_value() >> bt);
+            foreach(error_iccm_blocked_en_bit_cg[bt]) this.error_iccm_blocked_en_bit_cg[bt].sample(error_iccm_blocked_en.get_mirrored_value() >> bt);
+            foreach(error_mbox_ecc_unc_en_bit_cg[bt]) this.error_mbox_ecc_unc_en_bit_cg[bt].sample(error_mbox_ecc_unc_en.get_mirrored_value() >> bt);
+            foreach(error_wdt_timer1_timeout_en_bit_cg[bt]) this.error_wdt_timer1_timeout_en_bit_cg[bt].sample(error_wdt_timer1_timeout_en.get_mirrored_value() >> bt);
+            foreach(error_wdt_timer2_timeout_en_bit_cg[bt]) this.error_wdt_timer2_timeout_en_bit_cg[bt].sample(error_wdt_timer2_timeout_en.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( error_internal_en.get_mirrored_value()  ,  error_inv_dev_en.get_mirrored_value()  ,  error_cmd_fail_en.get_mirrored_value()  ,  error_bad_fuse_en.get_mirrored_value()  ,  error_iccm_blocked_en.get_mirrored_value()  ,  error_mbox_ecc_unc_en.get_mirrored_value()  ,  error_wdt_timer1_timeout_en.get_mirrored_value()  ,  error_wdt_timer2_timeout_en.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__NOTIF_INTR_EN_T SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__intr_block_t__notif_intr_en_t::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(notif_cmd_avail_en_bit_cg[bt]) this.notif_cmd_avail_en_bit_cg[bt].sample(data[0 + bt]);
+            foreach(notif_mbox_ecc_cor_en_bit_cg[bt]) this.notif_mbox_ecc_cor_en_bit_cg[bt].sample(data[1 + bt]);
+            foreach(notif_debug_locked_en_bit_cg[bt]) this.notif_debug_locked_en_bit_cg[bt].sample(data[2 + bt]);
+            foreach(notif_scan_mode_en_bit_cg[bt]) this.notif_scan_mode_en_bit_cg[bt].sample(data[3 + bt]);
+            foreach(notif_soc_req_lock_en_bit_cg[bt]) this.notif_soc_req_lock_en_bit_cg[bt].sample(data[4 + bt]);
+            foreach(notif_gen_in_toggle_en_bit_cg[bt]) this.notif_gen_in_toggle_en_bit_cg[bt].sample(data[5 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*notif_cmd_avail_en*/  ,  data[1:1]/*notif_mbox_ecc_cor_en*/  ,  data[2:2]/*notif_debug_locked_en*/  ,  data[3:3]/*notif_scan_mode_en*/  ,  data[4:4]/*notif_soc_req_lock_en*/  ,  data[5:5]/*notif_gen_in_toggle_en*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__intr_block_t__notif_intr_en_t::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(notif_cmd_avail_en_bit_cg[bt]) this.notif_cmd_avail_en_bit_cg[bt].sample(notif_cmd_avail_en.get_mirrored_value() >> bt);
+            foreach(notif_mbox_ecc_cor_en_bit_cg[bt]) this.notif_mbox_ecc_cor_en_bit_cg[bt].sample(notif_mbox_ecc_cor_en.get_mirrored_value() >> bt);
+            foreach(notif_debug_locked_en_bit_cg[bt]) this.notif_debug_locked_en_bit_cg[bt].sample(notif_debug_locked_en.get_mirrored_value() >> bt);
+            foreach(notif_scan_mode_en_bit_cg[bt]) this.notif_scan_mode_en_bit_cg[bt].sample(notif_scan_mode_en.get_mirrored_value() >> bt);
+            foreach(notif_soc_req_lock_en_bit_cg[bt]) this.notif_soc_req_lock_en_bit_cg[bt].sample(notif_soc_req_lock_en.get_mirrored_value() >> bt);
+            foreach(notif_gen_in_toggle_en_bit_cg[bt]) this.notif_gen_in_toggle_en_bit_cg[bt].sample(notif_gen_in_toggle_en.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( notif_cmd_avail_en.get_mirrored_value()  ,  notif_mbox_ecc_cor_en.get_mirrored_value()  ,  notif_debug_locked_en.get_mirrored_value()  ,  notif_scan_mode_en.get_mirrored_value()  ,  notif_soc_req_lock_en.get_mirrored_value()  ,  notif_gen_in_toggle_en.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__GLOBAL_INTR_T_AGG_STS_DD3DCF0A SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__intr_block_t__global_intr_t_agg_sts_dd3dcf0a::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(agg_sts_bit_cg[bt]) this.agg_sts_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*agg_sts*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__intr_block_t__global_intr_t_agg_sts_dd3dcf0a::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(agg_sts_bit_cg[bt]) this.agg_sts_bit_cg[bt].sample(agg_sts.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( agg_sts.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__GLOBAL_INTR_T_AGG_STS_E6399B4A SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__intr_block_t__global_intr_t_agg_sts_e6399b4a::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(agg_sts_bit_cg[bt]) this.agg_sts_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*agg_sts*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__intr_block_t__global_intr_t_agg_sts_e6399b4a::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(agg_sts_bit_cg[bt]) this.agg_sts_bit_cg[bt].sample(agg_sts.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( agg_sts.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__ERROR_INTR_T_ERROR_BAD_FUSE_STS_23F67582_ERROR_CMD_FAIL_STS_B85845F8_ERROR_ICCM_BLOCKED_STS_E81E6AD2_ERROR_INTERNAL_STS_CAAD62E2_ERROR_INV_DEV_STS_6693E7DB_ERROR_MBOX_ECC_UNC_STS_30BFF330_ERROR_WDT_TIMER1_TIMEOUT_STS_6AAA9655_ERROR_WDT_TIMER2_TIMEOUT_STS_CDA8789F SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(error_internal_sts_bit_cg[bt]) this.error_internal_sts_bit_cg[bt].sample(data[0 + bt]);
+            foreach(error_inv_dev_sts_bit_cg[bt]) this.error_inv_dev_sts_bit_cg[bt].sample(data[1 + bt]);
+            foreach(error_cmd_fail_sts_bit_cg[bt]) this.error_cmd_fail_sts_bit_cg[bt].sample(data[2 + bt]);
+            foreach(error_bad_fuse_sts_bit_cg[bt]) this.error_bad_fuse_sts_bit_cg[bt].sample(data[3 + bt]);
+            foreach(error_iccm_blocked_sts_bit_cg[bt]) this.error_iccm_blocked_sts_bit_cg[bt].sample(data[4 + bt]);
+            foreach(error_mbox_ecc_unc_sts_bit_cg[bt]) this.error_mbox_ecc_unc_sts_bit_cg[bt].sample(data[5 + bt]);
+            foreach(error_wdt_timer1_timeout_sts_bit_cg[bt]) this.error_wdt_timer1_timeout_sts_bit_cg[bt].sample(data[6 + bt]);
+            foreach(error_wdt_timer2_timeout_sts_bit_cg[bt]) this.error_wdt_timer2_timeout_sts_bit_cg[bt].sample(data[7 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*error_internal_sts*/  ,  data[1:1]/*error_inv_dev_sts*/  ,  data[2:2]/*error_cmd_fail_sts*/  ,  data[3:3]/*error_bad_fuse_sts*/  ,  data[4:4]/*error_iccm_blocked_sts*/  ,  data[5:5]/*error_mbox_ecc_unc_sts*/  ,  data[6:6]/*error_wdt_timer1_timeout_sts*/  ,  data[7:7]/*error_wdt_timer2_timeout_sts*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(error_internal_sts_bit_cg[bt]) this.error_internal_sts_bit_cg[bt].sample(error_internal_sts.get_mirrored_value() >> bt);
+            foreach(error_inv_dev_sts_bit_cg[bt]) this.error_inv_dev_sts_bit_cg[bt].sample(error_inv_dev_sts.get_mirrored_value() >> bt);
+            foreach(error_cmd_fail_sts_bit_cg[bt]) this.error_cmd_fail_sts_bit_cg[bt].sample(error_cmd_fail_sts.get_mirrored_value() >> bt);
+            foreach(error_bad_fuse_sts_bit_cg[bt]) this.error_bad_fuse_sts_bit_cg[bt].sample(error_bad_fuse_sts.get_mirrored_value() >> bt);
+            foreach(error_iccm_blocked_sts_bit_cg[bt]) this.error_iccm_blocked_sts_bit_cg[bt].sample(error_iccm_blocked_sts.get_mirrored_value() >> bt);
+            foreach(error_mbox_ecc_unc_sts_bit_cg[bt]) this.error_mbox_ecc_unc_sts_bit_cg[bt].sample(error_mbox_ecc_unc_sts.get_mirrored_value() >> bt);
+            foreach(error_wdt_timer1_timeout_sts_bit_cg[bt]) this.error_wdt_timer1_timeout_sts_bit_cg[bt].sample(error_wdt_timer1_timeout_sts.get_mirrored_value() >> bt);
+            foreach(error_wdt_timer2_timeout_sts_bit_cg[bt]) this.error_wdt_timer2_timeout_sts_bit_cg[bt].sample(error_wdt_timer2_timeout_sts.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( error_internal_sts.get_mirrored_value()  ,  error_inv_dev_sts.get_mirrored_value()  ,  error_cmd_fail_sts.get_mirrored_value()  ,  error_bad_fuse_sts.get_mirrored_value()  ,  error_iccm_blocked_sts.get_mirrored_value()  ,  error_mbox_ecc_unc_sts.get_mirrored_value()  ,  error_wdt_timer1_timeout_sts.get_mirrored_value()  ,  error_wdt_timer2_timeout_sts.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__NOTIF_INTR_T_NOTIF_CMD_AVAIL_STS_1871606B_NOTIF_DEBUG_LOCKED_STS_5F024102_NOTIF_GEN_IN_TOGGLE_STS_59F84B64_NOTIF_MBOX_ECC_COR_STS_5C3D26BB_NOTIF_SCAN_MODE_STS_122F6367_NOTIF_SOC_REQ_LOCK_STS_DEDDDE70 SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(notif_cmd_avail_sts_bit_cg[bt]) this.notif_cmd_avail_sts_bit_cg[bt].sample(data[0 + bt]);
+            foreach(notif_mbox_ecc_cor_sts_bit_cg[bt]) this.notif_mbox_ecc_cor_sts_bit_cg[bt].sample(data[1 + bt]);
+            foreach(notif_debug_locked_sts_bit_cg[bt]) this.notif_debug_locked_sts_bit_cg[bt].sample(data[2 + bt]);
+            foreach(notif_scan_mode_sts_bit_cg[bt]) this.notif_scan_mode_sts_bit_cg[bt].sample(data[3 + bt]);
+            foreach(notif_soc_req_lock_sts_bit_cg[bt]) this.notif_soc_req_lock_sts_bit_cg[bt].sample(data[4 + bt]);
+            foreach(notif_gen_in_toggle_sts_bit_cg[bt]) this.notif_gen_in_toggle_sts_bit_cg[bt].sample(data[5 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*notif_cmd_avail_sts*/  ,  data[1:1]/*notif_mbox_ecc_cor_sts*/  ,  data[2:2]/*notif_debug_locked_sts*/  ,  data[3:3]/*notif_scan_mode_sts*/  ,  data[4:4]/*notif_soc_req_lock_sts*/  ,  data[5:5]/*notif_gen_in_toggle_sts*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(notif_cmd_avail_sts_bit_cg[bt]) this.notif_cmd_avail_sts_bit_cg[bt].sample(notif_cmd_avail_sts.get_mirrored_value() >> bt);
+            foreach(notif_mbox_ecc_cor_sts_bit_cg[bt]) this.notif_mbox_ecc_cor_sts_bit_cg[bt].sample(notif_mbox_ecc_cor_sts.get_mirrored_value() >> bt);
+            foreach(notif_debug_locked_sts_bit_cg[bt]) this.notif_debug_locked_sts_bit_cg[bt].sample(notif_debug_locked_sts.get_mirrored_value() >> bt);
+            foreach(notif_scan_mode_sts_bit_cg[bt]) this.notif_scan_mode_sts_bit_cg[bt].sample(notif_scan_mode_sts.get_mirrored_value() >> bt);
+            foreach(notif_soc_req_lock_sts_bit_cg[bt]) this.notif_soc_req_lock_sts_bit_cg[bt].sample(notif_soc_req_lock_sts.get_mirrored_value() >> bt);
+            foreach(notif_gen_in_toggle_sts_bit_cg[bt]) this.notif_gen_in_toggle_sts_bit_cg[bt].sample(notif_gen_in_toggle_sts.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( notif_cmd_avail_sts.get_mirrored_value()  ,  notif_mbox_ecc_cor_sts.get_mirrored_value()  ,  notif_debug_locked_sts.get_mirrored_value()  ,  notif_scan_mode_sts.get_mirrored_value()  ,  notif_soc_req_lock_sts.get_mirrored_value()  ,  notif_gen_in_toggle_sts.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__ERROR_INTR_TRIG_T SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__intr_block_t__error_intr_trig_t::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(error_internal_trig_bit_cg[bt]) this.error_internal_trig_bit_cg[bt].sample(data[0 + bt]);
+            foreach(error_inv_dev_trig_bit_cg[bt]) this.error_inv_dev_trig_bit_cg[bt].sample(data[1 + bt]);
+            foreach(error_cmd_fail_trig_bit_cg[bt]) this.error_cmd_fail_trig_bit_cg[bt].sample(data[2 + bt]);
+            foreach(error_bad_fuse_trig_bit_cg[bt]) this.error_bad_fuse_trig_bit_cg[bt].sample(data[3 + bt]);
+            foreach(error_iccm_blocked_trig_bit_cg[bt]) this.error_iccm_blocked_trig_bit_cg[bt].sample(data[4 + bt]);
+            foreach(error_mbox_ecc_unc_trig_bit_cg[bt]) this.error_mbox_ecc_unc_trig_bit_cg[bt].sample(data[5 + bt]);
+            foreach(error_wdt_timer1_timeout_trig_bit_cg[bt]) this.error_wdt_timer1_timeout_trig_bit_cg[bt].sample(data[6 + bt]);
+            foreach(error_wdt_timer2_timeout_trig_bit_cg[bt]) this.error_wdt_timer2_timeout_trig_bit_cg[bt].sample(data[7 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*error_internal_trig*/  ,  data[1:1]/*error_inv_dev_trig*/  ,  data[2:2]/*error_cmd_fail_trig*/  ,  data[3:3]/*error_bad_fuse_trig*/  ,  data[4:4]/*error_iccm_blocked_trig*/  ,  data[5:5]/*error_mbox_ecc_unc_trig*/  ,  data[6:6]/*error_wdt_timer1_timeout_trig*/  ,  data[7:7]/*error_wdt_timer2_timeout_trig*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__intr_block_t__error_intr_trig_t::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(error_internal_trig_bit_cg[bt]) this.error_internal_trig_bit_cg[bt].sample(error_internal_trig.get_mirrored_value() >> bt);
+            foreach(error_inv_dev_trig_bit_cg[bt]) this.error_inv_dev_trig_bit_cg[bt].sample(error_inv_dev_trig.get_mirrored_value() >> bt);
+            foreach(error_cmd_fail_trig_bit_cg[bt]) this.error_cmd_fail_trig_bit_cg[bt].sample(error_cmd_fail_trig.get_mirrored_value() >> bt);
+            foreach(error_bad_fuse_trig_bit_cg[bt]) this.error_bad_fuse_trig_bit_cg[bt].sample(error_bad_fuse_trig.get_mirrored_value() >> bt);
+            foreach(error_iccm_blocked_trig_bit_cg[bt]) this.error_iccm_blocked_trig_bit_cg[bt].sample(error_iccm_blocked_trig.get_mirrored_value() >> bt);
+            foreach(error_mbox_ecc_unc_trig_bit_cg[bt]) this.error_mbox_ecc_unc_trig_bit_cg[bt].sample(error_mbox_ecc_unc_trig.get_mirrored_value() >> bt);
+            foreach(error_wdt_timer1_timeout_trig_bit_cg[bt]) this.error_wdt_timer1_timeout_trig_bit_cg[bt].sample(error_wdt_timer1_timeout_trig.get_mirrored_value() >> bt);
+            foreach(error_wdt_timer2_timeout_trig_bit_cg[bt]) this.error_wdt_timer2_timeout_trig_bit_cg[bt].sample(error_wdt_timer2_timeout_trig.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( error_internal_trig.get_mirrored_value()  ,  error_inv_dev_trig.get_mirrored_value()  ,  error_cmd_fail_trig.get_mirrored_value()  ,  error_bad_fuse_trig.get_mirrored_value()  ,  error_iccm_blocked_trig.get_mirrored_value()  ,  error_mbox_ecc_unc_trig.get_mirrored_value()  ,  error_wdt_timer1_timeout_trig.get_mirrored_value()  ,  error_wdt_timer2_timeout_trig.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__NOTIF_INTR_TRIG_T SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__intr_block_t__notif_intr_trig_t::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(notif_cmd_avail_trig_bit_cg[bt]) this.notif_cmd_avail_trig_bit_cg[bt].sample(data[0 + bt]);
+            foreach(notif_mbox_ecc_cor_trig_bit_cg[bt]) this.notif_mbox_ecc_cor_trig_bit_cg[bt].sample(data[1 + bt]);
+            foreach(notif_debug_locked_trig_bit_cg[bt]) this.notif_debug_locked_trig_bit_cg[bt].sample(data[2 + bt]);
+            foreach(notif_scan_mode_trig_bit_cg[bt]) this.notif_scan_mode_trig_bit_cg[bt].sample(data[3 + bt]);
+            foreach(notif_soc_req_lock_trig_bit_cg[bt]) this.notif_soc_req_lock_trig_bit_cg[bt].sample(data[4 + bt]);
+            foreach(notif_gen_in_toggle_trig_bit_cg[bt]) this.notif_gen_in_toggle_trig_bit_cg[bt].sample(data[5 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*notif_cmd_avail_trig*/  ,  data[1:1]/*notif_mbox_ecc_cor_trig*/  ,  data[2:2]/*notif_debug_locked_trig*/  ,  data[3:3]/*notif_scan_mode_trig*/  ,  data[4:4]/*notif_soc_req_lock_trig*/  ,  data[5:5]/*notif_gen_in_toggle_trig*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__intr_block_t__notif_intr_trig_t::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(notif_cmd_avail_trig_bit_cg[bt]) this.notif_cmd_avail_trig_bit_cg[bt].sample(notif_cmd_avail_trig.get_mirrored_value() >> bt);
+            foreach(notif_mbox_ecc_cor_trig_bit_cg[bt]) this.notif_mbox_ecc_cor_trig_bit_cg[bt].sample(notif_mbox_ecc_cor_trig.get_mirrored_value() >> bt);
+            foreach(notif_debug_locked_trig_bit_cg[bt]) this.notif_debug_locked_trig_bit_cg[bt].sample(notif_debug_locked_trig.get_mirrored_value() >> bt);
+            foreach(notif_scan_mode_trig_bit_cg[bt]) this.notif_scan_mode_trig_bit_cg[bt].sample(notif_scan_mode_trig.get_mirrored_value() >> bt);
+            foreach(notif_soc_req_lock_trig_bit_cg[bt]) this.notif_soc_req_lock_trig_bit_cg[bt].sample(notif_soc_req_lock_trig.get_mirrored_value() >> bt);
+            foreach(notif_gen_in_toggle_trig_bit_cg[bt]) this.notif_gen_in_toggle_trig_bit_cg[bt].sample(notif_gen_in_toggle_trig.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( notif_cmd_avail_trig.get_mirrored_value()  ,  notif_mbox_ecc_cor_trig.get_mirrored_value()  ,  notif_debug_locked_trig.get_mirrored_value()  ,  notif_scan_mode_trig.get_mirrored_value()  ,  notif_soc_req_lock_trig.get_mirrored_value()  ,  notif_gen_in_toggle_trig.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_T_CNT_608F1141 SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__intr_block_t__intr_count_t_cnt_608f1141::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*cnt*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__intr_block_t__intr_count_t_cnt_608f1141::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(cnt.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( cnt.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_T_CNT_916AB5DF SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__intr_block_t__intr_count_t_cnt_916ab5df::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*cnt*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__intr_block_t__intr_count_t_cnt_916ab5df::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(cnt.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( cnt.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_T_CNT_B2A56031 SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__intr_block_t__intr_count_t_cnt_b2a56031::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*cnt*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__intr_block_t__intr_count_t_cnt_b2a56031::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(cnt.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( cnt.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_T_CNT_FB7D2433 SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__intr_block_t__intr_count_t_cnt_fb7d2433::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*cnt*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__intr_block_t__intr_count_t_cnt_fb7d2433::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(cnt.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( cnt.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_T_CNT_25E76B6F SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__intr_block_t__intr_count_t_cnt_25e76b6f::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*cnt*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__intr_block_t__intr_count_t_cnt_25e76b6f::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(cnt.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( cnt.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_T_CNT_26B97E39 SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__intr_block_t__intr_count_t_cnt_26b97e39::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*cnt*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__intr_block_t__intr_count_t_cnt_26b97e39::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(cnt.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( cnt.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_T_CNT_A2F61F82 SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__intr_block_t__intr_count_t_cnt_a2f61f82::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*cnt*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__intr_block_t__intr_count_t_cnt_a2f61f82::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(cnt.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( cnt.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_T_CNT_D46457CD SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__intr_block_t__intr_count_t_cnt_d46457cd::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*cnt*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__intr_block_t__intr_count_t_cnt_d46457cd::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(cnt.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( cnt.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_T_CNT_A06F0954 SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__intr_block_t__intr_count_t_cnt_a06f0954::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*cnt*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__intr_block_t__intr_count_t_cnt_a06f0954::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(cnt.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( cnt.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_T_CNT_00E49272 SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__intr_block_t__intr_count_t_cnt_00e49272::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*cnt*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__intr_block_t__intr_count_t_cnt_00e49272::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(cnt.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( cnt.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_T_CNT_EE53DED8 SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__intr_block_t__intr_count_t_cnt_ee53ded8::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*cnt*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__intr_block_t__intr_count_t_cnt_ee53ded8::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(cnt.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( cnt.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_T_CNT_FBF3C714 SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__intr_block_t__intr_count_t_cnt_fbf3c714::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*cnt*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__intr_block_t__intr_count_t_cnt_fbf3c714::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(cnt.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( cnt.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_T_CNT_B9BDDABE SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__intr_block_t__intr_count_t_cnt_b9bddabe::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*cnt*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__intr_block_t__intr_count_t_cnt_b9bddabe::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(cnt.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( cnt.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_T_CNT_57528CC1 SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__intr_block_t__intr_count_t_cnt_57528cc1::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[31:0]/*cnt*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__intr_block_t__intr_count_t_cnt_57528cc1::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(cnt.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( cnt.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_15E6ED7E SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_15e6ed7e::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*pulse*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_15e6ed7e::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(pulse.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( pulse.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_F762EA9C SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_f762ea9c::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*pulse*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_f762ea9c::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(pulse.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( pulse.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_AA8718C6 SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_aa8718c6::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*pulse*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_aa8718c6::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(pulse.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( pulse.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_26FA5955 SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_26fa5955::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*pulse*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_26fa5955::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(pulse.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( pulse.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_3E43D258 SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_3e43d258::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*pulse*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_3e43d258::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(pulse.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( pulse.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_9F1632FD SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_9f1632fd::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*pulse*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_9f1632fd::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(pulse.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( pulse.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_AA999FDC SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_aa999fdc::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*pulse*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_aa999fdc::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(pulse.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( pulse.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_404E12DB SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_404e12db::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*pulse*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_404e12db::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(pulse.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( pulse.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_90D52137 SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_90d52137::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*pulse*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_90d52137::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(pulse.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( pulse.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_A6DB6FFF SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_a6db6fff::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*pulse*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_a6db6fff::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(pulse.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( pulse.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_51891FB1 SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_51891fb1::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*pulse*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_51891fb1::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(pulse.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( pulse.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_F5D8AFE0 SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_f5d8afe0::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*pulse*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_f5d8afe0::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(pulse.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( pulse.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_246489BD SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_246489bd::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*pulse*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_246489bd::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(pulse.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( pulse.get_mirrored_value()   );
+        end
+    endfunction
+
+    /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_D6ED4D1E SAMPLE FUNCTIONS -----------------------*/
+    function void soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_d6ed4d1e::sample(uvm_reg_data_t  data,
+                                                   uvm_reg_data_t  byte_en,
+                                                   bit             is_read,
+                                                   uvm_reg_map     map);
+        m_current = get();
+        m_data    = data;
+        m_is_read = is_read;
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(data[0 + bt]);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( data[0:0]/*pulse*/   );
+        end
+    endfunction
+
+    function void soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_d6ed4d1e::sample_values();
+        if (get_coverage(UVM_CVR_REG_BITS)) begin
+            foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(pulse.get_mirrored_value() >> bt);
+        end
+        if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+            this.fld_cg.sample( pulse.get_mirrored_value()   );
+        end
+    endfunction
+
+`endif
\ No newline at end of file
diff --git a/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv b/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv
index e85e404c5..249f71bb5 100644
--- a/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv
+++ b/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv
@@ -3,134 +3,305 @@
 package soc_ifc_reg_uvm;
     `include "uvm_macros.svh"
     import uvm_pkg::*;
-    
+    `include "soc_ifc_reg_covergroups.svh"
     // Reg - soc_ifc_reg::CPTRA_HW_ERROR_FATAL
     class soc_ifc_reg__CPTRA_HW_ERROR_FATAL extends uvm_reg;
-        rand uvm_reg_field error_code;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__CPTRA_HW_ERROR_FATAL_bit_cg iccm_ecc_unc_bit_cg[1];
+        soc_ifc_reg__CPTRA_HW_ERROR_FATAL_bit_cg dccm_ecc_unc_bit_cg[1];
+        soc_ifc_reg__CPTRA_HW_ERROR_FATAL_bit_cg nmi_pin_bit_cg[1];
+        soc_ifc_reg__CPTRA_HW_ERROR_FATAL_fld_cg fld_cg;
+        rand uvm_reg_field iccm_ecc_unc;
+        rand uvm_reg_field dccm_ecc_unc;
+        rand uvm_reg_field nmi_pin;
 
         function new(string name = "soc_ifc_reg__CPTRA_HW_ERROR_FATAL");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
-            this.error_code = new("error_code");
-            this.error_code.configure(this, 32, 0, "W1C", 1, 'h0, 1, 1, 0);
+            this.iccm_ecc_unc = new("iccm_ecc_unc");
+            this.iccm_ecc_unc.configure(this, 1, 0, "W1C", 1, 'h0, 1, 1, 0);
+            this.dccm_ecc_unc = new("dccm_ecc_unc");
+            this.dccm_ecc_unc.configure(this, 1, 1, "W1C", 1, 'h0, 1, 1, 0);
+            this.nmi_pin = new("nmi_pin");
+            this.nmi_pin.configure(this, 1, 2, "W1C", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(iccm_ecc_unc_bit_cg[bt]) iccm_ecc_unc_bit_cg[bt] = new();
+                foreach(dccm_ecc_unc_bit_cg[bt]) dccm_ecc_unc_bit_cg[bt] = new();
+                foreach(nmi_pin_bit_cg[bt]) nmi_pin_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__CPTRA_HW_ERROR_FATAL
 
     // Reg - soc_ifc_reg::CPTRA_HW_ERROR_NON_FATAL
     class soc_ifc_reg__CPTRA_HW_ERROR_NON_FATAL extends uvm_reg;
-        rand uvm_reg_field error_code;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__CPTRA_HW_ERROR_NON_FATAL_bit_cg mbox_prot_no_lock_bit_cg[1];
+        soc_ifc_reg__CPTRA_HW_ERROR_NON_FATAL_bit_cg mbox_prot_ooo_bit_cg[1];
+        soc_ifc_reg__CPTRA_HW_ERROR_NON_FATAL_bit_cg mbox_ecc_unc_bit_cg[1];
+        soc_ifc_reg__CPTRA_HW_ERROR_NON_FATAL_fld_cg fld_cg;
+        rand uvm_reg_field mbox_prot_no_lock;
+        rand uvm_reg_field mbox_prot_ooo;
+        rand uvm_reg_field mbox_ecc_unc;
 
         function new(string name = "soc_ifc_reg__CPTRA_HW_ERROR_NON_FATAL");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
-            this.error_code = new("error_code");
-            this.error_code.configure(this, 32, 0, "W1C", 1, 'h0, 1, 1, 0);
+            this.mbox_prot_no_lock = new("mbox_prot_no_lock");
+            this.mbox_prot_no_lock.configure(this, 1, 0, "W1C", 1, 'h0, 1, 1, 0);
+            this.mbox_prot_ooo = new("mbox_prot_ooo");
+            this.mbox_prot_ooo.configure(this, 1, 1, "W1C", 1, 'h0, 1, 1, 0);
+            this.mbox_ecc_unc = new("mbox_ecc_unc");
+            this.mbox_ecc_unc.configure(this, 1, 2, "W1C", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(mbox_prot_no_lock_bit_cg[bt]) mbox_prot_no_lock_bit_cg[bt] = new();
+                foreach(mbox_prot_ooo_bit_cg[bt]) mbox_prot_ooo_bit_cg[bt] = new();
+                foreach(mbox_ecc_unc_bit_cg[bt]) mbox_ecc_unc_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__CPTRA_HW_ERROR_NON_FATAL
 
     // Reg - soc_ifc_reg::CPTRA_FW_ERROR_FATAL
     class soc_ifc_reg__CPTRA_FW_ERROR_FATAL extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__CPTRA_FW_ERROR_FATAL_bit_cg error_code_bit_cg[32];
+        soc_ifc_reg__CPTRA_FW_ERROR_FATAL_fld_cg fld_cg;
         rand uvm_reg_field error_code;
 
         function new(string name = "soc_ifc_reg__CPTRA_FW_ERROR_FATAL");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.error_code = new("error_code");
             this.error_code.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(error_code_bit_cg[bt]) error_code_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__CPTRA_FW_ERROR_FATAL
 
     // Reg - soc_ifc_reg::CPTRA_FW_ERROR_NON_FATAL
     class soc_ifc_reg__CPTRA_FW_ERROR_NON_FATAL extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__CPTRA_FW_ERROR_NON_FATAL_bit_cg error_code_bit_cg[32];
+        soc_ifc_reg__CPTRA_FW_ERROR_NON_FATAL_fld_cg fld_cg;
         rand uvm_reg_field error_code;
 
         function new(string name = "soc_ifc_reg__CPTRA_FW_ERROR_NON_FATAL");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.error_code = new("error_code");
             this.error_code.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(error_code_bit_cg[bt]) error_code_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__CPTRA_FW_ERROR_NON_FATAL
 
     // Reg - soc_ifc_reg::CPTRA_HW_ERROR_ENC
     class soc_ifc_reg__CPTRA_HW_ERROR_ENC extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__CPTRA_HW_ERROR_ENC_bit_cg error_code_bit_cg[32];
+        soc_ifc_reg__CPTRA_HW_ERROR_ENC_fld_cg fld_cg;
         rand uvm_reg_field error_code;
 
         function new(string name = "soc_ifc_reg__CPTRA_HW_ERROR_ENC");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.error_code = new("error_code");
             this.error_code.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(error_code_bit_cg[bt]) error_code_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__CPTRA_HW_ERROR_ENC
 
     // Reg - soc_ifc_reg::CPTRA_FW_ERROR_ENC
     class soc_ifc_reg__CPTRA_FW_ERROR_ENC extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__CPTRA_FW_ERROR_ENC_bit_cg error_code_bit_cg[32];
+        soc_ifc_reg__CPTRA_FW_ERROR_ENC_fld_cg fld_cg;
         rand uvm_reg_field error_code;
 
         function new(string name = "soc_ifc_reg__CPTRA_FW_ERROR_ENC");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.error_code = new("error_code");
             this.error_code.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(error_code_bit_cg[bt]) error_code_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__CPTRA_FW_ERROR_ENC
 
     // Reg - soc_ifc_reg::CPTRA_FW_EXTENDED_ERROR_INFO
     class soc_ifc_reg__CPTRA_FW_EXTENDED_ERROR_INFO extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__CPTRA_FW_EXTENDED_ERROR_INFO_bit_cg error_info_bit_cg[32];
+        soc_ifc_reg__CPTRA_FW_EXTENDED_ERROR_INFO_fld_cg fld_cg;
         rand uvm_reg_field error_info;
 
         function new(string name = "soc_ifc_reg__CPTRA_FW_EXTENDED_ERROR_INFO");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.error_info = new("error_info");
             this.error_info.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(error_info_bit_cg[bt]) error_info_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__CPTRA_FW_EXTENDED_ERROR_INFO
 
     // Reg - soc_ifc_reg::CPTRA_BOOT_STATUS
     class soc_ifc_reg__CPTRA_BOOT_STATUS extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__CPTRA_BOOT_STATUS_bit_cg status_bit_cg[32];
+        soc_ifc_reg__CPTRA_BOOT_STATUS_fld_cg fld_cg;
         rand uvm_reg_field status;
 
         function new(string name = "soc_ifc_reg__CPTRA_BOOT_STATUS");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.status = new("status");
             this.status.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(status_bit_cg[bt]) status_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__CPTRA_BOOT_STATUS
 
     // Reg - soc_ifc_reg::CPTRA_FLOW_STATUS
     class soc_ifc_reg__CPTRA_FLOW_STATUS extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__CPTRA_FLOW_STATUS_bit_cg status_bit_cg[24];
+        soc_ifc_reg__CPTRA_FLOW_STATUS_bit_cg idevid_csr_ready_bit_cg[1];
+        soc_ifc_reg__CPTRA_FLOW_STATUS_bit_cg boot_fsm_ps_bit_cg[3];
+        soc_ifc_reg__CPTRA_FLOW_STATUS_bit_cg ready_for_fw_bit_cg[1];
+        soc_ifc_reg__CPTRA_FLOW_STATUS_bit_cg ready_for_runtime_bit_cg[1];
+        soc_ifc_reg__CPTRA_FLOW_STATUS_bit_cg ready_for_fuses_bit_cg[1];
+        soc_ifc_reg__CPTRA_FLOW_STATUS_bit_cg mailbox_flow_done_bit_cg[1];
+        soc_ifc_reg__CPTRA_FLOW_STATUS_fld_cg fld_cg;
         rand uvm_reg_field status;
+        rand uvm_reg_field idevid_csr_ready;
+        rand uvm_reg_field boot_fsm_ps;
         rand uvm_reg_field ready_for_fw;
         rand uvm_reg_field ready_for_runtime;
         rand uvm_reg_field ready_for_fuses;
         rand uvm_reg_field mailbox_flow_done;
 
         function new(string name = "soc_ifc_reg__CPTRA_FLOW_STATUS");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.status = new("status");
-            this.status.configure(this, 28, 0, "RW", 0, 'h0, 1, 1, 0);
+            this.status.configure(this, 24, 0, "RW", 0, 'h0, 1, 1, 0);
+            this.idevid_csr_ready = new("idevid_csr_ready");
+            this.idevid_csr_ready.configure(this, 1, 24, "RW", 0, 'h0, 1, 1, 0);
+            this.boot_fsm_ps = new("boot_fsm_ps");
+            this.boot_fsm_ps.configure(this, 3, 25, "RO", 1, 'h0, 0, 1, 0);
             this.ready_for_fw = new("ready_for_fw");
             this.ready_for_fw.configure(this, 1, 28, "RW", 0, 'h0, 1, 1, 0);
             this.ready_for_runtime = new("ready_for_runtime");
@@ -139,36 +310,79 @@ package soc_ifc_reg_uvm;
             this.ready_for_fuses.configure(this, 1, 30, "RO", 1, 'h0, 0, 1, 0);
             this.mailbox_flow_done = new("mailbox_flow_done");
             this.mailbox_flow_done.configure(this, 1, 31, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(status_bit_cg[bt]) status_bit_cg[bt] = new();
+                foreach(idevid_csr_ready_bit_cg[bt]) idevid_csr_ready_bit_cg[bt] = new();
+                foreach(boot_fsm_ps_bit_cg[bt]) boot_fsm_ps_bit_cg[bt] = new();
+                foreach(ready_for_fw_bit_cg[bt]) ready_for_fw_bit_cg[bt] = new();
+                foreach(ready_for_runtime_bit_cg[bt]) ready_for_runtime_bit_cg[bt] = new();
+                foreach(ready_for_fuses_bit_cg[bt]) ready_for_fuses_bit_cg[bt] = new();
+                foreach(mailbox_flow_done_bit_cg[bt]) mailbox_flow_done_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__CPTRA_FLOW_STATUS
 
     // Reg - soc_ifc_reg::CPTRA_RESET_REASON
     class soc_ifc_reg__CPTRA_RESET_REASON extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__CPTRA_RESET_REASON_bit_cg FW_UPD_RESET_bit_cg[1];
+        soc_ifc_reg__CPTRA_RESET_REASON_bit_cg WARM_RESET_bit_cg[1];
+        soc_ifc_reg__CPTRA_RESET_REASON_fld_cg fld_cg;
         rand uvm_reg_field FW_UPD_RESET;
         rand uvm_reg_field WARM_RESET;
 
         function new(string name = "soc_ifc_reg__CPTRA_RESET_REASON");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.FW_UPD_RESET = new("FW_UPD_RESET");
             this.FW_UPD_RESET.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
             this.WARM_RESET = new("WARM_RESET");
             this.WARM_RESET.configure(this, 1, 1, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(FW_UPD_RESET_bit_cg[bt]) FW_UPD_RESET_bit_cg[bt] = new();
+                foreach(WARM_RESET_bit_cg[bt]) WARM_RESET_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__CPTRA_RESET_REASON
 
     // Reg - soc_ifc_reg::CPTRA_SECURITY_STATE
     class soc_ifc_reg__CPTRA_SECURITY_STATE extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__CPTRA_SECURITY_STATE_bit_cg device_lifecycle_bit_cg[2];
+        soc_ifc_reg__CPTRA_SECURITY_STATE_bit_cg debug_locked_bit_cg[1];
+        soc_ifc_reg__CPTRA_SECURITY_STATE_bit_cg scan_mode_bit_cg[1];
+        soc_ifc_reg__CPTRA_SECURITY_STATE_bit_cg rsvd_bit_cg[28];
+        soc_ifc_reg__CPTRA_SECURITY_STATE_fld_cg fld_cg;
         rand uvm_reg_field device_lifecycle;
         rand uvm_reg_field debug_locked;
         rand uvm_reg_field scan_mode;
         rand uvm_reg_field rsvd;
 
         function new(string name = "soc_ifc_reg__CPTRA_SECURITY_STATE");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.device_lifecycle = new("device_lifecycle");
@@ -179,232 +393,531 @@ package soc_ifc_reg_uvm;
             this.scan_mode.configure(this, 1, 3, "RO", 1, 'h0, 1, 1, 0);
             this.rsvd = new("rsvd");
             this.rsvd.configure(this, 28, 4, "RO", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(device_lifecycle_bit_cg[bt]) device_lifecycle_bit_cg[bt] = new();
+                foreach(debug_locked_bit_cg[bt]) debug_locked_bit_cg[bt] = new();
+                foreach(scan_mode_bit_cg[bt]) scan_mode_bit_cg[bt] = new();
+                foreach(rsvd_bit_cg[bt]) rsvd_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__CPTRA_SECURITY_STATE
 
     // Reg - soc_ifc_reg::CPTRA_MBOX_VALID_PAUSER
     class soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER_bit_cg PAUSER_bit_cg[32];
+        soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER_fld_cg fld_cg;
         rand uvm_reg_field PAUSER;
 
         function new(string name = "soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.PAUSER = new("PAUSER");
             this.PAUSER.configure(this, 32, 0, "RW", 0, 'hffffffff, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(PAUSER_bit_cg[bt]) PAUSER_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER
 
     // Reg - soc_ifc_reg::CPTRA_MBOX_PAUSER_LOCK
     class soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK_bit_cg LOCK_bit_cg[1];
+        soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK_fld_cg fld_cg;
         rand uvm_reg_field LOCK;
 
         function new(string name = "soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.LOCK = new("LOCK");
             this.LOCK.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(LOCK_bit_cg[bt]) LOCK_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK
 
     // Reg - soc_ifc_reg::CPTRA_TRNG_VALID_PAUSER
     class soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER_bit_cg PAUSER_bit_cg[32];
+        soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER_fld_cg fld_cg;
         rand uvm_reg_field PAUSER;
 
         function new(string name = "soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.PAUSER = new("PAUSER");
             this.PAUSER.configure(this, 32, 0, "RW", 0, 'hffffffff, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(PAUSER_bit_cg[bt]) PAUSER_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER
 
     // Reg - soc_ifc_reg::CPTRA_TRNG_PAUSER_LOCK
     class soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK_bit_cg LOCK_bit_cg[1];
+        soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK_fld_cg fld_cg;
         rand uvm_reg_field LOCK;
 
         function new(string name = "soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.LOCK = new("LOCK");
             this.LOCK.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(LOCK_bit_cg[bt]) LOCK_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK
 
     // Reg - soc_ifc_reg::CPTRA_TRNG_DATA
     class soc_ifc_reg__CPTRA_TRNG_DATA extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__CPTRA_TRNG_DATA_bit_cg DATA_bit_cg[32];
+        soc_ifc_reg__CPTRA_TRNG_DATA_fld_cg fld_cg;
         rand uvm_reg_field DATA;
 
         function new(string name = "soc_ifc_reg__CPTRA_TRNG_DATA");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.DATA = new("DATA");
-            this.DATA.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+            this.DATA.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(DATA_bit_cg[bt]) DATA_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__CPTRA_TRNG_DATA
 
+    // Reg - soc_ifc_reg::CPTRA_TRNG_CTRL
+    class soc_ifc_reg__CPTRA_TRNG_CTRL extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__CPTRA_TRNG_CTRL_bit_cg clear_bit_cg[1];
+        soc_ifc_reg__CPTRA_TRNG_CTRL_fld_cg fld_cg;
+        rand uvm_reg_field clear;
+
+        function new(string name = "soc_ifc_reg__CPTRA_TRNG_CTRL");
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
+        endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
+
+        virtual function void build();
+            this.clear = new("clear");
+            this.clear.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(clear_bit_cg[bt]) clear_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
+        endfunction : build
+    endclass : soc_ifc_reg__CPTRA_TRNG_CTRL
+
     // Reg - soc_ifc_reg::CPTRA_TRNG_STATUS
     class soc_ifc_reg__CPTRA_TRNG_STATUS extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__CPTRA_TRNG_STATUS_bit_cg DATA_REQ_bit_cg[1];
+        soc_ifc_reg__CPTRA_TRNG_STATUS_bit_cg DATA_WR_DONE_bit_cg[1];
+        soc_ifc_reg__CPTRA_TRNG_STATUS_fld_cg fld_cg;
         rand uvm_reg_field DATA_REQ;
         rand uvm_reg_field DATA_WR_DONE;
 
         function new(string name = "soc_ifc_reg__CPTRA_TRNG_STATUS");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.DATA_REQ = new("DATA_REQ");
             this.DATA_REQ.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
             this.DATA_WR_DONE = new("DATA_WR_DONE");
             this.DATA_WR_DONE.configure(this, 1, 1, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(DATA_REQ_bit_cg[bt]) DATA_REQ_bit_cg[bt] = new();
+                foreach(DATA_WR_DONE_bit_cg[bt]) DATA_WR_DONE_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__CPTRA_TRNG_STATUS
 
     // Reg - soc_ifc_reg::CPTRA_FUSE_WR_DONE
     class soc_ifc_reg__CPTRA_FUSE_WR_DONE extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__CPTRA_FUSE_WR_DONE_bit_cg done_bit_cg[1];
+        soc_ifc_reg__CPTRA_FUSE_WR_DONE_fld_cg fld_cg;
         rand uvm_reg_field done;
 
         function new(string name = "soc_ifc_reg__CPTRA_FUSE_WR_DONE");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.done = new("done");
             this.done.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(done_bit_cg[bt]) done_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__CPTRA_FUSE_WR_DONE
 
     // Reg - soc_ifc_reg::CPTRA_TIMER_CONFIG
     class soc_ifc_reg__CPTRA_TIMER_CONFIG extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__CPTRA_TIMER_CONFIG_bit_cg clk_period_bit_cg[32];
+        soc_ifc_reg__CPTRA_TIMER_CONFIG_fld_cg fld_cg;
         rand uvm_reg_field clk_period;
 
         function new(string name = "soc_ifc_reg__CPTRA_TIMER_CONFIG");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.clk_period = new("clk_period");
             this.clk_period.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(clk_period_bit_cg[bt]) clk_period_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__CPTRA_TIMER_CONFIG
 
     // Reg - soc_ifc_reg::CPTRA_BOOTFSM_GO
     class soc_ifc_reg__CPTRA_BOOTFSM_GO extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__CPTRA_BOOTFSM_GO_bit_cg GO_bit_cg[1];
+        soc_ifc_reg__CPTRA_BOOTFSM_GO_fld_cg fld_cg;
         rand uvm_reg_field GO;
 
         function new(string name = "soc_ifc_reg__CPTRA_BOOTFSM_GO");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.GO = new("GO");
             this.GO.configure(this, 1, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(GO_bit_cg[bt]) GO_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__CPTRA_BOOTFSM_GO
 
     // Reg - soc_ifc_reg::CPTRA_DBG_MANUF_SERVICE_REG
     class soc_ifc_reg__CPTRA_DBG_MANUF_SERVICE_REG extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__CPTRA_DBG_MANUF_SERVICE_REG_bit_cg DATA_bit_cg[32];
+        soc_ifc_reg__CPTRA_DBG_MANUF_SERVICE_REG_fld_cg fld_cg;
         rand uvm_reg_field DATA;
 
         function new(string name = "soc_ifc_reg__CPTRA_DBG_MANUF_SERVICE_REG");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.DATA = new("DATA");
             this.DATA.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(DATA_bit_cg[bt]) DATA_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__CPTRA_DBG_MANUF_SERVICE_REG
 
     // Reg - soc_ifc_reg::CPTRA_CLK_GATING_EN
     class soc_ifc_reg__CPTRA_CLK_GATING_EN extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__CPTRA_CLK_GATING_EN_bit_cg clk_gating_en_bit_cg[1];
+        soc_ifc_reg__CPTRA_CLK_GATING_EN_fld_cg fld_cg;
         rand uvm_reg_field clk_gating_en;
 
         function new(string name = "soc_ifc_reg__CPTRA_CLK_GATING_EN");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.clk_gating_en = new("clk_gating_en");
             this.clk_gating_en.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(clk_gating_en_bit_cg[bt]) clk_gating_en_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__CPTRA_CLK_GATING_EN
 
     // Reg - soc_ifc_reg::CPTRA_GENERIC_INPUT_WIRES
     class soc_ifc_reg__CPTRA_GENERIC_INPUT_WIRES extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__CPTRA_GENERIC_INPUT_WIRES_bit_cg generic_wires_bit_cg[32];
+        soc_ifc_reg__CPTRA_GENERIC_INPUT_WIRES_fld_cg fld_cg;
         rand uvm_reg_field generic_wires;
 
         function new(string name = "soc_ifc_reg__CPTRA_GENERIC_INPUT_WIRES");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.generic_wires = new("generic_wires");
             this.generic_wires.configure(this, 32, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(generic_wires_bit_cg[bt]) generic_wires_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__CPTRA_GENERIC_INPUT_WIRES
 
     // Reg - soc_ifc_reg::CPTRA_GENERIC_OUTPUT_WIRES
     class soc_ifc_reg__CPTRA_GENERIC_OUTPUT_WIRES extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__CPTRA_GENERIC_OUTPUT_WIRES_bit_cg generic_wires_bit_cg[32];
+        soc_ifc_reg__CPTRA_GENERIC_OUTPUT_WIRES_fld_cg fld_cg;
         rand uvm_reg_field generic_wires;
 
         function new(string name = "soc_ifc_reg__CPTRA_GENERIC_OUTPUT_WIRES");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.generic_wires = new("generic_wires");
             this.generic_wires.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(generic_wires_bit_cg[bt]) generic_wires_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__CPTRA_GENERIC_OUTPUT_WIRES
 
     // Reg - soc_ifc_reg::CPTRA_HW_REV_ID
     class soc_ifc_reg__CPTRA_HW_REV_ID extends uvm_reg;
-        rand uvm_reg_field REV_ID;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__CPTRA_HW_REV_ID_bit_cg CPTRA_GENERATION_bit_cg[16];
+        soc_ifc_reg__CPTRA_HW_REV_ID_bit_cg SOC_STEPPING_ID_bit_cg[16];
+        soc_ifc_reg__CPTRA_HW_REV_ID_fld_cg fld_cg;
+        rand uvm_reg_field CPTRA_GENERATION;
+        rand uvm_reg_field SOC_STEPPING_ID;
 
         function new(string name = "soc_ifc_reg__CPTRA_HW_REV_ID");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
-            this.REV_ID = new("REV_ID");
-            this.REV_ID.configure(this, 32, 0, "RO", 0, 'h1, 1, 1, 0);
+            this.CPTRA_GENERATION = new("CPTRA_GENERATION");
+            this.CPTRA_GENERATION.configure(this, 16, 0, "RO", 0, 'h1, 1, 1, 0);
+            this.SOC_STEPPING_ID = new("SOC_STEPPING_ID");
+            this.SOC_STEPPING_ID.configure(this, 16, 16, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(CPTRA_GENERATION_bit_cg[bt]) CPTRA_GENERATION_bit_cg[bt] = new();
+                foreach(SOC_STEPPING_ID_bit_cg[bt]) SOC_STEPPING_ID_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__CPTRA_HW_REV_ID
 
     // Reg - soc_ifc_reg::CPTRA_FW_REV_ID
     class soc_ifc_reg__CPTRA_FW_REV_ID extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__CPTRA_FW_REV_ID_bit_cg REV_ID_bit_cg[32];
+        soc_ifc_reg__CPTRA_FW_REV_ID_fld_cg fld_cg;
         rand uvm_reg_field REV_ID;
 
         function new(string name = "soc_ifc_reg__CPTRA_FW_REV_ID");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.REV_ID = new("REV_ID");
             this.REV_ID.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(REV_ID_bit_cg[bt]) REV_ID_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__CPTRA_FW_REV_ID
 
     // Reg - soc_ifc_reg::CPTRA_HW_CONFIG
     class soc_ifc_reg__CPTRA_HW_CONFIG extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__CPTRA_HW_CONFIG_bit_cg iTRNG_en_bit_cg[1];
+        soc_ifc_reg__CPTRA_HW_CONFIG_bit_cg QSPI_en_bit_cg[1];
+        soc_ifc_reg__CPTRA_HW_CONFIG_bit_cg I3C_en_bit_cg[1];
+        soc_ifc_reg__CPTRA_HW_CONFIG_bit_cg UART_en_bit_cg[1];
+        soc_ifc_reg__CPTRA_HW_CONFIG_fld_cg fld_cg;
         rand uvm_reg_field iTRNG_en;
         rand uvm_reg_field QSPI_en;
         rand uvm_reg_field I3C_en;
         rand uvm_reg_field UART_en;
 
         function new(string name = "soc_ifc_reg__CPTRA_HW_CONFIG");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.iTRNG_en = new("iTRNG_en");
@@ -415,353 +928,1302 @@ package soc_ifc_reg_uvm;
             this.I3C_en.configure(this, 1, 2, "RO", 1, 'h0, 0, 1, 0);
             this.UART_en = new("UART_en");
             this.UART_en.configure(this, 1, 3, "RO", 1, 'h0, 0, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(iTRNG_en_bit_cg[bt]) iTRNG_en_bit_cg[bt] = new();
+                foreach(QSPI_en_bit_cg[bt]) QSPI_en_bit_cg[bt] = new();
+                foreach(I3C_en_bit_cg[bt]) I3C_en_bit_cg[bt] = new();
+                foreach(UART_en_bit_cg[bt]) UART_en_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__CPTRA_HW_CONFIG
 
     // Reg - soc_ifc_reg::CPTRA_WDT_TIMER1_EN
     class soc_ifc_reg__CPTRA_WDT_TIMER1_EN extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__CPTRA_WDT_TIMER1_EN_bit_cg timer1_en_bit_cg[1];
+        soc_ifc_reg__CPTRA_WDT_TIMER1_EN_fld_cg fld_cg;
         rand uvm_reg_field timer1_en;
 
         function new(string name = "soc_ifc_reg__CPTRA_WDT_TIMER1_EN");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.timer1_en = new("timer1_en");
             this.timer1_en.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(timer1_en_bit_cg[bt]) timer1_en_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__CPTRA_WDT_TIMER1_EN
 
     // Reg - soc_ifc_reg::CPTRA_WDT_TIMER1_CTRL
     class soc_ifc_reg__CPTRA_WDT_TIMER1_CTRL extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__CPTRA_WDT_TIMER1_CTRL_bit_cg timer1_restart_bit_cg[1];
+        soc_ifc_reg__CPTRA_WDT_TIMER1_CTRL_fld_cg fld_cg;
         rand uvm_reg_field timer1_restart;
 
         function new(string name = "soc_ifc_reg__CPTRA_WDT_TIMER1_CTRL");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.timer1_restart = new("timer1_restart");
             this.timer1_restart.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(timer1_restart_bit_cg[bt]) timer1_restart_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__CPTRA_WDT_TIMER1_CTRL
 
     // Reg - soc_ifc_reg::CPTRA_WDT_TIMER1_TIMEOUT_PERIOD
     class soc_ifc_reg__CPTRA_WDT_TIMER1_TIMEOUT_PERIOD extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_bit_cg timer1_timeout_period_bit_cg[32];
+        soc_ifc_reg__CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_fld_cg fld_cg;
         rand uvm_reg_field timer1_timeout_period;
 
         function new(string name = "soc_ifc_reg__CPTRA_WDT_TIMER1_TIMEOUT_PERIOD");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.timer1_timeout_period = new("timer1_timeout_period");
             this.timer1_timeout_period.configure(this, 32, 0, "RW", 0, 'hffffffff, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(timer1_timeout_period_bit_cg[bt]) timer1_timeout_period_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__CPTRA_WDT_TIMER1_TIMEOUT_PERIOD
 
     // Reg - soc_ifc_reg::CPTRA_WDT_TIMER2_EN
     class soc_ifc_reg__CPTRA_WDT_TIMER2_EN extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__CPTRA_WDT_TIMER2_EN_bit_cg timer2_en_bit_cg[1];
+        soc_ifc_reg__CPTRA_WDT_TIMER2_EN_fld_cg fld_cg;
         rand uvm_reg_field timer2_en;
 
         function new(string name = "soc_ifc_reg__CPTRA_WDT_TIMER2_EN");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.timer2_en = new("timer2_en");
             this.timer2_en.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(timer2_en_bit_cg[bt]) timer2_en_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__CPTRA_WDT_TIMER2_EN
 
     // Reg - soc_ifc_reg::CPTRA_WDT_TIMER2_CTRL
     class soc_ifc_reg__CPTRA_WDT_TIMER2_CTRL extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__CPTRA_WDT_TIMER2_CTRL_bit_cg timer2_restart_bit_cg[1];
+        soc_ifc_reg__CPTRA_WDT_TIMER2_CTRL_fld_cg fld_cg;
         rand uvm_reg_field timer2_restart;
 
         function new(string name = "soc_ifc_reg__CPTRA_WDT_TIMER2_CTRL");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.timer2_restart = new("timer2_restart");
             this.timer2_restart.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(timer2_restart_bit_cg[bt]) timer2_restart_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__CPTRA_WDT_TIMER2_CTRL
 
     // Reg - soc_ifc_reg::CPTRA_WDT_TIMER2_TIMEOUT_PERIOD
     class soc_ifc_reg__CPTRA_WDT_TIMER2_TIMEOUT_PERIOD extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_bit_cg timer2_timeout_period_bit_cg[32];
+        soc_ifc_reg__CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_fld_cg fld_cg;
         rand uvm_reg_field timer2_timeout_period;
 
         function new(string name = "soc_ifc_reg__CPTRA_WDT_TIMER2_TIMEOUT_PERIOD");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.timer2_timeout_period = new("timer2_timeout_period");
             this.timer2_timeout_period.configure(this, 32, 0, "RW", 0, 'hffffffff, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(timer2_timeout_period_bit_cg[bt]) timer2_timeout_period_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__CPTRA_WDT_TIMER2_TIMEOUT_PERIOD
 
     // Reg - soc_ifc_reg::CPTRA_WDT_STATUS
     class soc_ifc_reg__CPTRA_WDT_STATUS extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__CPTRA_WDT_STATUS_bit_cg t1_timeout_bit_cg[1];
+        soc_ifc_reg__CPTRA_WDT_STATUS_bit_cg t2_timeout_bit_cg[1];
+        soc_ifc_reg__CPTRA_WDT_STATUS_fld_cg fld_cg;
         rand uvm_reg_field t1_timeout;
         rand uvm_reg_field t2_timeout;
 
         function new(string name = "soc_ifc_reg__CPTRA_WDT_STATUS");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.t1_timeout = new("t1_timeout");
             this.t1_timeout.configure(this, 1, 0, "RW", 1, 'h0, 1, 1, 0);
             this.t2_timeout = new("t2_timeout");
             this.t2_timeout.configure(this, 1, 1, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(t1_timeout_bit_cg[bt]) t1_timeout_bit_cg[bt] = new();
+                foreach(t2_timeout_bit_cg[bt]) t2_timeout_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__CPTRA_WDT_STATUS
 
+    // Reg - soc_ifc_reg::CPTRA_FUSE_VALID_PAUSER
+    class soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER_bit_cg PAUSER_bit_cg[32];
+        soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER_fld_cg fld_cg;
+        rand uvm_reg_field PAUSER;
+
+        function new(string name = "soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER");
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
+        endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
+
+        virtual function void build();
+            this.PAUSER = new("PAUSER");
+            this.PAUSER.configure(this, 32, 0, "RW", 0, 'hffffffff, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(PAUSER_bit_cg[bt]) PAUSER_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
+        endfunction : build
+    endclass : soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER
+
+    // Reg - soc_ifc_reg::CPTRA_FUSE_PAUSER_LOCK
+    class soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK_bit_cg LOCK_bit_cg[1];
+        soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK_fld_cg fld_cg;
+        rand uvm_reg_field LOCK;
+
+        function new(string name = "soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK");
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
+        endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
+
+        virtual function void build();
+            this.LOCK = new("LOCK");
+            this.LOCK.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(LOCK_bit_cg[bt]) LOCK_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
+        endfunction : build
+    endclass : soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK
+
+    // Reg - soc_ifc_reg::CPTRA_WDT_CFG
+    class soc_ifc_reg__CPTRA_WDT_CFG extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__CPTRA_WDT_CFG_bit_cg TIMEOUT_bit_cg[32];
+        soc_ifc_reg__CPTRA_WDT_CFG_fld_cg fld_cg;
+        rand uvm_reg_field TIMEOUT;
+
+        function new(string name = "soc_ifc_reg__CPTRA_WDT_CFG");
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
+        endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
+
+        virtual function void build();
+            this.TIMEOUT = new("TIMEOUT");
+            this.TIMEOUT.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(TIMEOUT_bit_cg[bt]) TIMEOUT_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
+        endfunction : build
+    endclass : soc_ifc_reg__CPTRA_WDT_CFG
+
+    // Reg - soc_ifc_reg::CPTRA_iTRNG_ENTROPY_CONFIG_0
+    class soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_0 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_0_bit_cg low_threshold_bit_cg[16];
+        soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_0_bit_cg high_threshold_bit_cg[16];
+        soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_0_fld_cg fld_cg;
+        rand uvm_reg_field low_threshold;
+        rand uvm_reg_field high_threshold;
+
+        function new(string name = "soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_0");
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
+        endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
+
+        virtual function void build();
+            this.low_threshold = new("low_threshold");
+            this.low_threshold.configure(this, 16, 0, "RW", 0, 'h0, 1, 1, 0);
+            this.high_threshold = new("high_threshold");
+            this.high_threshold.configure(this, 16, 16, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(low_threshold_bit_cg[bt]) low_threshold_bit_cg[bt] = new();
+                foreach(high_threshold_bit_cg[bt]) high_threshold_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
+        endfunction : build
+    endclass : soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_0
+
+    // Reg - soc_ifc_reg::CPTRA_iTRNG_ENTROPY_CONFIG_1
+    class soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_1 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_1_bit_cg repetition_count_bit_cg[16];
+        soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_1_bit_cg RSVD_bit_cg[16];
+        soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_1_fld_cg fld_cg;
+        rand uvm_reg_field repetition_count;
+        rand uvm_reg_field RSVD;
+
+        function new(string name = "soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_1");
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
+        endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
+
+        virtual function void build();
+            this.repetition_count = new("repetition_count");
+            this.repetition_count.configure(this, 16, 0, "RW", 0, 'h0, 1, 1, 0);
+            this.RSVD = new("RSVD");
+            this.RSVD.configure(this, 16, 16, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(repetition_count_bit_cg[bt]) repetition_count_bit_cg[bt] = new();
+                foreach(RSVD_bit_cg[bt]) RSVD_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
+        endfunction : build
+    endclass : soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_1
+
+    // Reg - soc_ifc_reg::CPTRA_RSVD_REG
+    class soc_ifc_reg__CPTRA_RSVD_REG extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__CPTRA_RSVD_REG_bit_cg RSVD_bit_cg[32];
+        soc_ifc_reg__CPTRA_RSVD_REG_fld_cg fld_cg;
+        rand uvm_reg_field RSVD;
+
+        function new(string name = "soc_ifc_reg__CPTRA_RSVD_REG");
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
+        endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
+
+        virtual function void build();
+            this.RSVD = new("RSVD");
+            this.RSVD.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(RSVD_bit_cg[bt]) RSVD_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
+        endfunction : build
+    endclass : soc_ifc_reg__CPTRA_RSVD_REG
+
     // Reg - soc_ifc_reg::fuse_uds_seed
     class soc_ifc_reg__fuse_uds_seed extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__fuse_uds_seed_bit_cg seed_bit_cg[32];
+        soc_ifc_reg__fuse_uds_seed_fld_cg fld_cg;
         rand uvm_reg_field seed;
 
         function new(string name = "soc_ifc_reg__fuse_uds_seed");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.seed = new("seed");
             this.seed.configure(this, 32, 0, "WO1", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(seed_bit_cg[bt]) seed_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__fuse_uds_seed
 
     // Reg - soc_ifc_reg::fuse_field_entropy
     class soc_ifc_reg__fuse_field_entropy extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__fuse_field_entropy_bit_cg seed_bit_cg[32];
+        soc_ifc_reg__fuse_field_entropy_fld_cg fld_cg;
         rand uvm_reg_field seed;
 
         function new(string name = "soc_ifc_reg__fuse_field_entropy");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.seed = new("seed");
             this.seed.configure(this, 32, 0, "WO1", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(seed_bit_cg[bt]) seed_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__fuse_field_entropy
 
     // Reg - soc_ifc_reg::fuse_key_manifest_pk_hash
     class soc_ifc_reg__fuse_key_manifest_pk_hash extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__fuse_key_manifest_pk_hash_bit_cg hash_bit_cg[32];
+        soc_ifc_reg__fuse_key_manifest_pk_hash_fld_cg fld_cg;
         rand uvm_reg_field hash;
 
         function new(string name = "soc_ifc_reg__fuse_key_manifest_pk_hash");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.hash = new("hash");
             this.hash.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(hash_bit_cg[bt]) hash_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__fuse_key_manifest_pk_hash
 
     // Reg - soc_ifc_reg::fuse_key_manifest_pk_hash_mask
     class soc_ifc_reg__fuse_key_manifest_pk_hash_mask extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__fuse_key_manifest_pk_hash_mask_bit_cg mask_bit_cg[4];
+        soc_ifc_reg__fuse_key_manifest_pk_hash_mask_fld_cg fld_cg;
         rand uvm_reg_field mask;
 
         function new(string name = "soc_ifc_reg__fuse_key_manifest_pk_hash_mask");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.mask = new("mask");
             this.mask.configure(this, 4, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(mask_bit_cg[bt]) mask_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__fuse_key_manifest_pk_hash_mask
 
     // Reg - soc_ifc_reg::fuse_owner_pk_hash
     class soc_ifc_reg__fuse_owner_pk_hash extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__fuse_owner_pk_hash_bit_cg hash_bit_cg[32];
+        soc_ifc_reg__fuse_owner_pk_hash_fld_cg fld_cg;
         rand uvm_reg_field hash;
 
         function new(string name = "soc_ifc_reg__fuse_owner_pk_hash");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.hash = new("hash");
             this.hash.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(hash_bit_cg[bt]) hash_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__fuse_owner_pk_hash
 
     // Reg - soc_ifc_reg::fuse_fmc_key_manifest_svn
     class soc_ifc_reg__fuse_fmc_key_manifest_svn extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__fuse_fmc_key_manifest_svn_bit_cg svn_bit_cg[32];
+        soc_ifc_reg__fuse_fmc_key_manifest_svn_fld_cg fld_cg;
         rand uvm_reg_field svn;
 
         function new(string name = "soc_ifc_reg__fuse_fmc_key_manifest_svn");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.svn = new("svn");
             this.svn.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(svn_bit_cg[bt]) svn_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__fuse_fmc_key_manifest_svn
 
     // Reg - soc_ifc_reg::fuse_runtime_svn
     class soc_ifc_reg__fuse_runtime_svn extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__fuse_runtime_svn_bit_cg svn_bit_cg[32];
+        soc_ifc_reg__fuse_runtime_svn_fld_cg fld_cg;
         rand uvm_reg_field svn;
 
         function new(string name = "soc_ifc_reg__fuse_runtime_svn");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.svn = new("svn");
             this.svn.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(svn_bit_cg[bt]) svn_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__fuse_runtime_svn
 
     // Reg - soc_ifc_reg::fuse_anti_rollback_disable
     class soc_ifc_reg__fuse_anti_rollback_disable extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__fuse_anti_rollback_disable_bit_cg dis_bit_cg[1];
+        soc_ifc_reg__fuse_anti_rollback_disable_fld_cg fld_cg;
         rand uvm_reg_field dis;
 
         function new(string name = "soc_ifc_reg__fuse_anti_rollback_disable");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.dis = new("dis");
             this.dis.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(dis_bit_cg[bt]) dis_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__fuse_anti_rollback_disable
 
     // Reg - soc_ifc_reg::fuse_idevid_cert_attr
     class soc_ifc_reg__fuse_idevid_cert_attr extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__fuse_idevid_cert_attr_bit_cg cert_bit_cg[32];
+        soc_ifc_reg__fuse_idevid_cert_attr_fld_cg fld_cg;
         rand uvm_reg_field cert;
 
         function new(string name = "soc_ifc_reg__fuse_idevid_cert_attr");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.cert = new("cert");
             this.cert.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cert_bit_cg[bt]) cert_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__fuse_idevid_cert_attr
 
     // Reg - soc_ifc_reg::fuse_idevid_manuf_hsm_id
     class soc_ifc_reg__fuse_idevid_manuf_hsm_id extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__fuse_idevid_manuf_hsm_id_bit_cg hsm_id_bit_cg[32];
+        soc_ifc_reg__fuse_idevid_manuf_hsm_id_fld_cg fld_cg;
         rand uvm_reg_field hsm_id;
 
         function new(string name = "soc_ifc_reg__fuse_idevid_manuf_hsm_id");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.hsm_id = new("hsm_id");
             this.hsm_id.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(hsm_id_bit_cg[bt]) hsm_id_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__fuse_idevid_manuf_hsm_id
 
     // Reg - soc_ifc_reg::fuse_life_cycle
     class soc_ifc_reg__fuse_life_cycle extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__fuse_life_cycle_bit_cg life_cycle_bit_cg[2];
+        soc_ifc_reg__fuse_life_cycle_fld_cg fld_cg;
         rand uvm_reg_field life_cycle;
 
         function new(string name = "soc_ifc_reg__fuse_life_cycle");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.life_cycle = new("life_cycle");
             this.life_cycle.configure(this, 2, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(life_cycle_bit_cg[bt]) life_cycle_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__fuse_life_cycle
 
+    // Reg - soc_ifc_reg::fuse_lms_verify
+    class soc_ifc_reg__fuse_lms_verify extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__fuse_lms_verify_bit_cg lms_verify_bit_cg[1];
+        soc_ifc_reg__fuse_lms_verify_fld_cg fld_cg;
+        rand uvm_reg_field lms_verify;
+
+        function new(string name = "soc_ifc_reg__fuse_lms_verify");
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
+        endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
+
+        virtual function void build();
+            this.lms_verify = new("lms_verify");
+            this.lms_verify.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(lms_verify_bit_cg[bt]) lms_verify_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
+        endfunction : build
+    endclass : soc_ifc_reg__fuse_lms_verify
+
+    // Reg - soc_ifc_reg::fuse_lms_revocation
+    class soc_ifc_reg__fuse_lms_revocation extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__fuse_lms_revocation_bit_cg lms_revocation_bit_cg[32];
+        soc_ifc_reg__fuse_lms_revocation_fld_cg fld_cg;
+        rand uvm_reg_field lms_revocation;
+
+        function new(string name = "soc_ifc_reg__fuse_lms_revocation");
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
+        endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
+
+        virtual function void build();
+            this.lms_revocation = new("lms_revocation");
+            this.lms_revocation.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(lms_revocation_bit_cg[bt]) lms_revocation_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
+        endfunction : build
+    endclass : soc_ifc_reg__fuse_lms_revocation
+
+    // Reg - soc_ifc_reg::fuse_soc_stepping_id
+    class soc_ifc_reg__fuse_soc_stepping_id extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__fuse_soc_stepping_id_bit_cg soc_stepping_id_bit_cg[16];
+        soc_ifc_reg__fuse_soc_stepping_id_fld_cg fld_cg;
+        rand uvm_reg_field soc_stepping_id;
+
+        function new(string name = "soc_ifc_reg__fuse_soc_stepping_id");
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
+        endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
+
+        virtual function void build();
+            this.soc_stepping_id = new("soc_stepping_id");
+            this.soc_stepping_id.configure(this, 16, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(soc_stepping_id_bit_cg[bt]) soc_stepping_id_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
+        endfunction : build
+    endclass : soc_ifc_reg__fuse_soc_stepping_id
+
     // Reg - soc_ifc_reg::internal_obf_key
     class soc_ifc_reg__internal_obf_key extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__internal_obf_key_bit_cg key_bit_cg[32];
+        soc_ifc_reg__internal_obf_key_fld_cg fld_cg;
         rand uvm_reg_field key;
 
         function new(string name = "soc_ifc_reg__internal_obf_key");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.key = new("key");
             this.key.configure(this, 32, 0, "WO", 1, 'h0, 0, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(key_bit_cg[bt]) key_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__internal_obf_key
 
     // Reg - soc_ifc_reg::internal_iccm_lock
     class soc_ifc_reg__internal_iccm_lock extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__internal_iccm_lock_bit_cg lock_bit_cg[1];
+        soc_ifc_reg__internal_iccm_lock_fld_cg fld_cg;
         rand uvm_reg_field lock;
 
         function new(string name = "soc_ifc_reg__internal_iccm_lock");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.lock = new("lock");
             this.lock.configure(this, 1, 0, "W1S", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(lock_bit_cg[bt]) lock_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__internal_iccm_lock
 
     // Reg - soc_ifc_reg::internal_fw_update_reset
     class soc_ifc_reg__internal_fw_update_reset extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__internal_fw_update_reset_bit_cg core_rst_bit_cg[1];
+        soc_ifc_reg__internal_fw_update_reset_fld_cg fld_cg;
         rand uvm_reg_field core_rst;
 
         function new(string name = "soc_ifc_reg__internal_fw_update_reset");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.core_rst = new("core_rst");
             this.core_rst.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(core_rst_bit_cg[bt]) core_rst_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__internal_fw_update_reset
 
     // Reg - soc_ifc_reg::internal_fw_update_reset_wait_cycles
     class soc_ifc_reg__internal_fw_update_reset_wait_cycles extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__internal_fw_update_reset_wait_cycles_bit_cg wait_cycles_bit_cg[8];
+        soc_ifc_reg__internal_fw_update_reset_wait_cycles_fld_cg fld_cg;
         rand uvm_reg_field wait_cycles;
 
         function new(string name = "soc_ifc_reg__internal_fw_update_reset_wait_cycles");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.wait_cycles = new("wait_cycles");
             this.wait_cycles.configure(this, 8, 0, "RW", 0, 'h5, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(wait_cycles_bit_cg[bt]) wait_cycles_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__internal_fw_update_reset_wait_cycles
 
     // Reg - soc_ifc_reg::internal_nmi_vector
     class soc_ifc_reg__internal_nmi_vector extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__internal_nmi_vector_bit_cg vec_bit_cg[32];
+        soc_ifc_reg__internal_nmi_vector_fld_cg fld_cg;
         rand uvm_reg_field vec;
 
         function new(string name = "soc_ifc_reg__internal_nmi_vector");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.vec = new("vec");
             this.vec.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(vec_bit_cg[bt]) vec_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__internal_nmi_vector
 
+    // Reg - soc_ifc_reg::internal_hw_error_fatal_mask
+    class soc_ifc_reg__internal_hw_error_fatal_mask extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__internal_hw_error_fatal_mask_bit_cg mask_iccm_ecc_unc_bit_cg[1];
+        soc_ifc_reg__internal_hw_error_fatal_mask_bit_cg mask_dccm_ecc_unc_bit_cg[1];
+        soc_ifc_reg__internal_hw_error_fatal_mask_bit_cg mask_nmi_pin_bit_cg[1];
+        soc_ifc_reg__internal_hw_error_fatal_mask_fld_cg fld_cg;
+        rand uvm_reg_field mask_iccm_ecc_unc;
+        rand uvm_reg_field mask_dccm_ecc_unc;
+        rand uvm_reg_field mask_nmi_pin;
+
+        function new(string name = "soc_ifc_reg__internal_hw_error_fatal_mask");
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
+        endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
+
+        virtual function void build();
+            this.mask_iccm_ecc_unc = new("mask_iccm_ecc_unc");
+            this.mask_iccm_ecc_unc.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
+            this.mask_dccm_ecc_unc = new("mask_dccm_ecc_unc");
+            this.mask_dccm_ecc_unc.configure(this, 1, 1, "RW", 0, 'h0, 1, 1, 0);
+            this.mask_nmi_pin = new("mask_nmi_pin");
+            this.mask_nmi_pin.configure(this, 1, 2, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(mask_iccm_ecc_unc_bit_cg[bt]) mask_iccm_ecc_unc_bit_cg[bt] = new();
+                foreach(mask_dccm_ecc_unc_bit_cg[bt]) mask_dccm_ecc_unc_bit_cg[bt] = new();
+                foreach(mask_nmi_pin_bit_cg[bt]) mask_nmi_pin_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
+        endfunction : build
+    endclass : soc_ifc_reg__internal_hw_error_fatal_mask
+
+    // Reg - soc_ifc_reg::internal_hw_error_non_fatal_mask
+    class soc_ifc_reg__internal_hw_error_non_fatal_mask extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__internal_hw_error_non_fatal_mask_bit_cg mask_mbox_prot_no_lock_bit_cg[1];
+        soc_ifc_reg__internal_hw_error_non_fatal_mask_bit_cg mask_mbox_prot_ooo_bit_cg[1];
+        soc_ifc_reg__internal_hw_error_non_fatal_mask_bit_cg mask_mbox_ecc_unc_bit_cg[1];
+        soc_ifc_reg__internal_hw_error_non_fatal_mask_fld_cg fld_cg;
+        rand uvm_reg_field mask_mbox_prot_no_lock;
+        rand uvm_reg_field mask_mbox_prot_ooo;
+        rand uvm_reg_field mask_mbox_ecc_unc;
+
+        function new(string name = "soc_ifc_reg__internal_hw_error_non_fatal_mask");
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
+        endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
+
+        virtual function void build();
+            this.mask_mbox_prot_no_lock = new("mask_mbox_prot_no_lock");
+            this.mask_mbox_prot_no_lock.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
+            this.mask_mbox_prot_ooo = new("mask_mbox_prot_ooo");
+            this.mask_mbox_prot_ooo.configure(this, 1, 1, "RW", 0, 'h0, 1, 1, 0);
+            this.mask_mbox_ecc_unc = new("mask_mbox_ecc_unc");
+            this.mask_mbox_ecc_unc.configure(this, 1, 2, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(mask_mbox_prot_no_lock_bit_cg[bt]) mask_mbox_prot_no_lock_bit_cg[bt] = new();
+                foreach(mask_mbox_prot_ooo_bit_cg[bt]) mask_mbox_prot_ooo_bit_cg[bt] = new();
+                foreach(mask_mbox_ecc_unc_bit_cg[bt]) mask_mbox_ecc_unc_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
+        endfunction : build
+    endclass : soc_ifc_reg__internal_hw_error_non_fatal_mask
+
+    // Reg - soc_ifc_reg::internal_fw_error_fatal_mask
+    class soc_ifc_reg__internal_fw_error_fatal_mask extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__internal_fw_error_fatal_mask_bit_cg mask_bit_cg[32];
+        soc_ifc_reg__internal_fw_error_fatal_mask_fld_cg fld_cg;
+        rand uvm_reg_field mask;
+
+        function new(string name = "soc_ifc_reg__internal_fw_error_fatal_mask");
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
+        endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
+
+        virtual function void build();
+            this.mask = new("mask");
+            this.mask.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(mask_bit_cg[bt]) mask_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
+        endfunction : build
+    endclass : soc_ifc_reg__internal_fw_error_fatal_mask
+
+    // Reg - soc_ifc_reg::internal_fw_error_non_fatal_mask
+    class soc_ifc_reg__internal_fw_error_non_fatal_mask extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__internal_fw_error_non_fatal_mask_bit_cg mask_bit_cg[32];
+        soc_ifc_reg__internal_fw_error_non_fatal_mask_fld_cg fld_cg;
+        rand uvm_reg_field mask;
+
+        function new(string name = "soc_ifc_reg__internal_fw_error_non_fatal_mask");
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
+        endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
+
+        virtual function void build();
+            this.mask = new("mask");
+            this.mask.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(mask_bit_cg[bt]) mask_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
+        endfunction : build
+    endclass : soc_ifc_reg__internal_fw_error_non_fatal_mask
+
+    // Reg - soc_ifc_reg::internal_rv_mtime_l
+    class soc_ifc_reg__internal_rv_mtime_l extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__internal_rv_mtime_l_bit_cg count_l_bit_cg[32];
+        soc_ifc_reg__internal_rv_mtime_l_fld_cg fld_cg;
+        rand uvm_reg_field count_l;
+
+        function new(string name = "soc_ifc_reg__internal_rv_mtime_l");
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
+        endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
+
+        virtual function void build();
+            this.count_l = new("count_l");
+            this.count_l.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(count_l_bit_cg[bt]) count_l_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
+        endfunction : build
+    endclass : soc_ifc_reg__internal_rv_mtime_l
+
+    // Reg - soc_ifc_reg::internal_rv_mtime_h
+    class soc_ifc_reg__internal_rv_mtime_h extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__internal_rv_mtime_h_bit_cg count_h_bit_cg[32];
+        soc_ifc_reg__internal_rv_mtime_h_fld_cg fld_cg;
+        rand uvm_reg_field count_h;
+
+        function new(string name = "soc_ifc_reg__internal_rv_mtime_h");
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
+        endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
+
+        virtual function void build();
+            this.count_h = new("count_h");
+            this.count_h.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(count_h_bit_cg[bt]) count_h_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
+        endfunction : build
+    endclass : soc_ifc_reg__internal_rv_mtime_h
+
+    // Reg - soc_ifc_reg::internal_rv_mtimecmp_l
+    class soc_ifc_reg__internal_rv_mtimecmp_l extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__internal_rv_mtimecmp_l_bit_cg compare_l_bit_cg[32];
+        soc_ifc_reg__internal_rv_mtimecmp_l_fld_cg fld_cg;
+        rand uvm_reg_field compare_l;
+
+        function new(string name = "soc_ifc_reg__internal_rv_mtimecmp_l");
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
+        endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
+
+        virtual function void build();
+            this.compare_l = new("compare_l");
+            this.compare_l.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(compare_l_bit_cg[bt]) compare_l_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
+        endfunction : build
+    endclass : soc_ifc_reg__internal_rv_mtimecmp_l
+
+    // Reg - soc_ifc_reg::internal_rv_mtimecmp_h
+    class soc_ifc_reg__internal_rv_mtimecmp_h extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__internal_rv_mtimecmp_h_bit_cg compare_h_bit_cg[32];
+        soc_ifc_reg__internal_rv_mtimecmp_h_fld_cg fld_cg;
+        rand uvm_reg_field compare_h;
+
+        function new(string name = "soc_ifc_reg__internal_rv_mtimecmp_h");
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
+        endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
+
+        virtual function void build();
+            this.compare_h = new("compare_h");
+            this.compare_h.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(compare_h_bit_cg[bt]) compare_h_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
+        endfunction : build
+    endclass : soc_ifc_reg__internal_rv_mtimecmp_h
+
     // Reg - soc_ifc_reg::intr_block_t::global_intr_en_t
     class soc_ifc_reg__intr_block_t__global_intr_en_t extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__intr_block_t__global_intr_en_t_bit_cg error_en_bit_cg[1];
+        soc_ifc_reg__intr_block_t__global_intr_en_t_bit_cg notif_en_bit_cg[1];
+        soc_ifc_reg__intr_block_t__global_intr_en_t_fld_cg fld_cg;
         rand uvm_reg_field error_en;
         rand uvm_reg_field notif_en;
 
         function new(string name = "soc_ifc_reg__intr_block_t__global_intr_en_t");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.error_en = new("error_en");
             this.error_en.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
             this.notif_en = new("notif_en");
             this.notif_en.configure(this, 1, 1, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(error_en_bit_cg[bt]) error_en_bit_cg[bt] = new();
+                foreach(notif_en_bit_cg[bt]) notif_en_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__intr_block_t__global_intr_en_t
 
     // Reg - soc_ifc_reg::intr_block_t::error_intr_en_t
     class soc_ifc_reg__intr_block_t__error_intr_en_t extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__intr_block_t__error_intr_en_t_bit_cg error_internal_en_bit_cg[1];
+        soc_ifc_reg__intr_block_t__error_intr_en_t_bit_cg error_inv_dev_en_bit_cg[1];
+        soc_ifc_reg__intr_block_t__error_intr_en_t_bit_cg error_cmd_fail_en_bit_cg[1];
+        soc_ifc_reg__intr_block_t__error_intr_en_t_bit_cg error_bad_fuse_en_bit_cg[1];
+        soc_ifc_reg__intr_block_t__error_intr_en_t_bit_cg error_iccm_blocked_en_bit_cg[1];
+        soc_ifc_reg__intr_block_t__error_intr_en_t_bit_cg error_mbox_ecc_unc_en_bit_cg[1];
+        soc_ifc_reg__intr_block_t__error_intr_en_t_bit_cg error_wdt_timer1_timeout_en_bit_cg[1];
+        soc_ifc_reg__intr_block_t__error_intr_en_t_bit_cg error_wdt_timer2_timeout_en_bit_cg[1];
+        soc_ifc_reg__intr_block_t__error_intr_en_t_fld_cg fld_cg;
         rand uvm_reg_field error_internal_en;
         rand uvm_reg_field error_inv_dev_en;
         rand uvm_reg_field error_cmd_fail_en;
@@ -772,8 +2234,13 @@ package soc_ifc_reg_uvm;
         rand uvm_reg_field error_wdt_timer2_timeout_en;
 
         function new(string name = "soc_ifc_reg__intr_block_t__error_intr_en_t");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.error_internal_en = new("error_internal_en");
@@ -792,19 +2259,49 @@ package soc_ifc_reg_uvm;
             this.error_wdt_timer1_timeout_en.configure(this, 1, 6, "RW", 0, 'h0, 1, 1, 0);
             this.error_wdt_timer2_timeout_en = new("error_wdt_timer2_timeout_en");
             this.error_wdt_timer2_timeout_en.configure(this, 1, 7, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(error_internal_en_bit_cg[bt]) error_internal_en_bit_cg[bt] = new();
+                foreach(error_inv_dev_en_bit_cg[bt]) error_inv_dev_en_bit_cg[bt] = new();
+                foreach(error_cmd_fail_en_bit_cg[bt]) error_cmd_fail_en_bit_cg[bt] = new();
+                foreach(error_bad_fuse_en_bit_cg[bt]) error_bad_fuse_en_bit_cg[bt] = new();
+                foreach(error_iccm_blocked_en_bit_cg[bt]) error_iccm_blocked_en_bit_cg[bt] = new();
+                foreach(error_mbox_ecc_unc_en_bit_cg[bt]) error_mbox_ecc_unc_en_bit_cg[bt] = new();
+                foreach(error_wdt_timer1_timeout_en_bit_cg[bt]) error_wdt_timer1_timeout_en_bit_cg[bt] = new();
+                foreach(error_wdt_timer2_timeout_en_bit_cg[bt]) error_wdt_timer2_timeout_en_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__intr_block_t__error_intr_en_t
 
     // Reg - soc_ifc_reg::intr_block_t::notif_intr_en_t
     class soc_ifc_reg__intr_block_t__notif_intr_en_t extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__intr_block_t__notif_intr_en_t_bit_cg notif_cmd_avail_en_bit_cg[1];
+        soc_ifc_reg__intr_block_t__notif_intr_en_t_bit_cg notif_mbox_ecc_cor_en_bit_cg[1];
+        soc_ifc_reg__intr_block_t__notif_intr_en_t_bit_cg notif_debug_locked_en_bit_cg[1];
+        soc_ifc_reg__intr_block_t__notif_intr_en_t_bit_cg notif_scan_mode_en_bit_cg[1];
+        soc_ifc_reg__intr_block_t__notif_intr_en_t_bit_cg notif_soc_req_lock_en_bit_cg[1];
+        soc_ifc_reg__intr_block_t__notif_intr_en_t_bit_cg notif_gen_in_toggle_en_bit_cg[1];
+        soc_ifc_reg__intr_block_t__notif_intr_en_t_fld_cg fld_cg;
         rand uvm_reg_field notif_cmd_avail_en;
         rand uvm_reg_field notif_mbox_ecc_cor_en;
         rand uvm_reg_field notif_debug_locked_en;
+        rand uvm_reg_field notif_scan_mode_en;
         rand uvm_reg_field notif_soc_req_lock_en;
+        rand uvm_reg_field notif_gen_in_toggle_en;
 
         function new(string name = "soc_ifc_reg__intr_block_t__notif_intr_en_t");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.notif_cmd_avail_en = new("notif_cmd_avail_en");
@@ -813,41 +2310,100 @@ package soc_ifc_reg_uvm;
             this.notif_mbox_ecc_cor_en.configure(this, 1, 1, "RW", 0, 'h0, 1, 1, 0);
             this.notif_debug_locked_en = new("notif_debug_locked_en");
             this.notif_debug_locked_en.configure(this, 1, 2, "RW", 0, 'h0, 1, 1, 0);
+            this.notif_scan_mode_en = new("notif_scan_mode_en");
+            this.notif_scan_mode_en.configure(this, 1, 3, "RW", 0, 'h0, 1, 1, 0);
             this.notif_soc_req_lock_en = new("notif_soc_req_lock_en");
-            this.notif_soc_req_lock_en.configure(this, 1, 3, "RW", 0, 'h0, 1, 1, 0);
+            this.notif_soc_req_lock_en.configure(this, 1, 4, "RW", 0, 'h0, 1, 1, 0);
+            this.notif_gen_in_toggle_en = new("notif_gen_in_toggle_en");
+            this.notif_gen_in_toggle_en.configure(this, 1, 5, "RW", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(notif_cmd_avail_en_bit_cg[bt]) notif_cmd_avail_en_bit_cg[bt] = new();
+                foreach(notif_mbox_ecc_cor_en_bit_cg[bt]) notif_mbox_ecc_cor_en_bit_cg[bt] = new();
+                foreach(notif_debug_locked_en_bit_cg[bt]) notif_debug_locked_en_bit_cg[bt] = new();
+                foreach(notif_scan_mode_en_bit_cg[bt]) notif_scan_mode_en_bit_cg[bt] = new();
+                foreach(notif_soc_req_lock_en_bit_cg[bt]) notif_soc_req_lock_en_bit_cg[bt] = new();
+                foreach(notif_gen_in_toggle_en_bit_cg[bt]) notif_gen_in_toggle_en_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__intr_block_t__notif_intr_en_t
 
     // Reg - soc_ifc_reg::intr_block_t::global_intr_t_agg_sts_dd3dcf0a
     class soc_ifc_reg__intr_block_t__global_intr_t_agg_sts_dd3dcf0a extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__intr_block_t__global_intr_t_agg_sts_dd3dcf0a_bit_cg agg_sts_bit_cg[1];
+        soc_ifc_reg__intr_block_t__global_intr_t_agg_sts_dd3dcf0a_fld_cg fld_cg;
         rand uvm_reg_field agg_sts;
 
         function new(string name = "soc_ifc_reg__intr_block_t__global_intr_t_agg_sts_dd3dcf0a");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.agg_sts = new("agg_sts");
             this.agg_sts.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(agg_sts_bit_cg[bt]) agg_sts_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__intr_block_t__global_intr_t_agg_sts_dd3dcf0a
 
     // Reg - soc_ifc_reg::intr_block_t::global_intr_t_agg_sts_e6399b4a
     class soc_ifc_reg__intr_block_t__global_intr_t_agg_sts_e6399b4a extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__intr_block_t__global_intr_t_agg_sts_e6399b4a_bit_cg agg_sts_bit_cg[1];
+        soc_ifc_reg__intr_block_t__global_intr_t_agg_sts_e6399b4a_fld_cg fld_cg;
         rand uvm_reg_field agg_sts;
 
         function new(string name = "soc_ifc_reg__intr_block_t__global_intr_t_agg_sts_e6399b4a");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.agg_sts = new("agg_sts");
             this.agg_sts.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(agg_sts_bit_cg[bt]) agg_sts_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__intr_block_t__global_intr_t_agg_sts_e6399b4a
 
     // Reg - soc_ifc_reg::intr_block_t::error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f
     class soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f_bit_cg error_internal_sts_bit_cg[1];
+        soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f_bit_cg error_inv_dev_sts_bit_cg[1];
+        soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f_bit_cg error_cmd_fail_sts_bit_cg[1];
+        soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f_bit_cg error_bad_fuse_sts_bit_cg[1];
+        soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f_bit_cg error_iccm_blocked_sts_bit_cg[1];
+        soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f_bit_cg error_mbox_ecc_unc_sts_bit_cg[1];
+        soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f_bit_cg error_wdt_timer1_timeout_sts_bit_cg[1];
+        soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f_bit_cg error_wdt_timer2_timeout_sts_bit_cg[1];
+        soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f_fld_cg fld_cg;
         rand uvm_reg_field error_internal_sts;
         rand uvm_reg_field error_inv_dev_sts;
         rand uvm_reg_field error_cmd_fail_sts;
@@ -858,8 +2414,13 @@ package soc_ifc_reg_uvm;
         rand uvm_reg_field error_wdt_timer2_timeout_sts;
 
         function new(string name = "soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.error_internal_sts = new("error_internal_sts");
@@ -878,19 +2439,49 @@ package soc_ifc_reg_uvm;
             this.error_wdt_timer1_timeout_sts.configure(this, 1, 6, "W1C", 1, 'h0, 1, 1, 0);
             this.error_wdt_timer2_timeout_sts = new("error_wdt_timer2_timeout_sts");
             this.error_wdt_timer2_timeout_sts.configure(this, 1, 7, "W1C", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(error_internal_sts_bit_cg[bt]) error_internal_sts_bit_cg[bt] = new();
+                foreach(error_inv_dev_sts_bit_cg[bt]) error_inv_dev_sts_bit_cg[bt] = new();
+                foreach(error_cmd_fail_sts_bit_cg[bt]) error_cmd_fail_sts_bit_cg[bt] = new();
+                foreach(error_bad_fuse_sts_bit_cg[bt]) error_bad_fuse_sts_bit_cg[bt] = new();
+                foreach(error_iccm_blocked_sts_bit_cg[bt]) error_iccm_blocked_sts_bit_cg[bt] = new();
+                foreach(error_mbox_ecc_unc_sts_bit_cg[bt]) error_mbox_ecc_unc_sts_bit_cg[bt] = new();
+                foreach(error_wdt_timer1_timeout_sts_bit_cg[bt]) error_wdt_timer1_timeout_sts_bit_cg[bt] = new();
+                foreach(error_wdt_timer2_timeout_sts_bit_cg[bt]) error_wdt_timer2_timeout_sts_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f
 
-    // Reg - soc_ifc_reg::intr_block_t::notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_mbox_ecc_cor_sts_5c3d26bb_notif_soc_req_lock_sts_deddde70
-    class soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_mbox_ecc_cor_sts_5c3d26bb_notif_soc_req_lock_sts_deddde70 extends uvm_reg;
+    // Reg - soc_ifc_reg::intr_block_t::notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70
+    class soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70_bit_cg notif_cmd_avail_sts_bit_cg[1];
+        soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70_bit_cg notif_mbox_ecc_cor_sts_bit_cg[1];
+        soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70_bit_cg notif_debug_locked_sts_bit_cg[1];
+        soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70_bit_cg notif_scan_mode_sts_bit_cg[1];
+        soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70_bit_cg notif_soc_req_lock_sts_bit_cg[1];
+        soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70_bit_cg notif_gen_in_toggle_sts_bit_cg[1];
+        soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70_fld_cg fld_cg;
         rand uvm_reg_field notif_cmd_avail_sts;
         rand uvm_reg_field notif_mbox_ecc_cor_sts;
         rand uvm_reg_field notif_debug_locked_sts;
+        rand uvm_reg_field notif_scan_mode_sts;
         rand uvm_reg_field notif_soc_req_lock_sts;
+        rand uvm_reg_field notif_gen_in_toggle_sts;
 
-        function new(string name = "soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_mbox_ecc_cor_sts_5c3d26bb_notif_soc_req_lock_sts_deddde70");
-            super.new(name, 32, UVM_NO_COVERAGE);
+        function new(string name = "soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70");
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.notif_cmd_avail_sts = new("notif_cmd_avail_sts");
@@ -899,13 +2490,40 @@ package soc_ifc_reg_uvm;
             this.notif_mbox_ecc_cor_sts.configure(this, 1, 1, "W1C", 1, 'h0, 1, 1, 0);
             this.notif_debug_locked_sts = new("notif_debug_locked_sts");
             this.notif_debug_locked_sts.configure(this, 1, 2, "W1C", 1, 'h0, 1, 1, 0);
+            this.notif_scan_mode_sts = new("notif_scan_mode_sts");
+            this.notif_scan_mode_sts.configure(this, 1, 3, "W1C", 1, 'h0, 1, 1, 0);
             this.notif_soc_req_lock_sts = new("notif_soc_req_lock_sts");
-            this.notif_soc_req_lock_sts.configure(this, 1, 3, "W1C", 1, 'h0, 1, 1, 0);
+            this.notif_soc_req_lock_sts.configure(this, 1, 4, "W1C", 1, 'h0, 1, 1, 0);
+            this.notif_gen_in_toggle_sts = new("notif_gen_in_toggle_sts");
+            this.notif_gen_in_toggle_sts.configure(this, 1, 5, "W1C", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(notif_cmd_avail_sts_bit_cg[bt]) notif_cmd_avail_sts_bit_cg[bt] = new();
+                foreach(notif_mbox_ecc_cor_sts_bit_cg[bt]) notif_mbox_ecc_cor_sts_bit_cg[bt] = new();
+                foreach(notif_debug_locked_sts_bit_cg[bt]) notif_debug_locked_sts_bit_cg[bt] = new();
+                foreach(notif_scan_mode_sts_bit_cg[bt]) notif_scan_mode_sts_bit_cg[bt] = new();
+                foreach(notif_soc_req_lock_sts_bit_cg[bt]) notif_soc_req_lock_sts_bit_cg[bt] = new();
+                foreach(notif_gen_in_toggle_sts_bit_cg[bt]) notif_gen_in_toggle_sts_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
-    endclass : soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_mbox_ecc_cor_sts_5c3d26bb_notif_soc_req_lock_sts_deddde70
+    endclass : soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70
 
     // Reg - soc_ifc_reg::intr_block_t::error_intr_trig_t
     class soc_ifc_reg__intr_block_t__error_intr_trig_t extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__intr_block_t__error_intr_trig_t_bit_cg error_internal_trig_bit_cg[1];
+        soc_ifc_reg__intr_block_t__error_intr_trig_t_bit_cg error_inv_dev_trig_bit_cg[1];
+        soc_ifc_reg__intr_block_t__error_intr_trig_t_bit_cg error_cmd_fail_trig_bit_cg[1];
+        soc_ifc_reg__intr_block_t__error_intr_trig_t_bit_cg error_bad_fuse_trig_bit_cg[1];
+        soc_ifc_reg__intr_block_t__error_intr_trig_t_bit_cg error_iccm_blocked_trig_bit_cg[1];
+        soc_ifc_reg__intr_block_t__error_intr_trig_t_bit_cg error_mbox_ecc_unc_trig_bit_cg[1];
+        soc_ifc_reg__intr_block_t__error_intr_trig_t_bit_cg error_wdt_timer1_timeout_trig_bit_cg[1];
+        soc_ifc_reg__intr_block_t__error_intr_trig_t_bit_cg error_wdt_timer2_timeout_trig_bit_cg[1];
+        soc_ifc_reg__intr_block_t__error_intr_trig_t_fld_cg fld_cg;
         rand uvm_reg_field error_internal_trig;
         rand uvm_reg_field error_inv_dev_trig;
         rand uvm_reg_field error_cmd_fail_trig;
@@ -916,8 +2534,13 @@ package soc_ifc_reg_uvm;
         rand uvm_reg_field error_wdt_timer2_timeout_trig;
 
         function new(string name = "soc_ifc_reg__intr_block_t__error_intr_trig_t");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.error_internal_trig = new("error_internal_trig");
@@ -936,19 +2559,49 @@ package soc_ifc_reg_uvm;
             this.error_wdt_timer1_timeout_trig.configure(this, 1, 6, "W1S", 0, 'h0, 1, 1, 0);
             this.error_wdt_timer2_timeout_trig = new("error_wdt_timer2_timeout_trig");
             this.error_wdt_timer2_timeout_trig.configure(this, 1, 7, "W1S", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(error_internal_trig_bit_cg[bt]) error_internal_trig_bit_cg[bt] = new();
+                foreach(error_inv_dev_trig_bit_cg[bt]) error_inv_dev_trig_bit_cg[bt] = new();
+                foreach(error_cmd_fail_trig_bit_cg[bt]) error_cmd_fail_trig_bit_cg[bt] = new();
+                foreach(error_bad_fuse_trig_bit_cg[bt]) error_bad_fuse_trig_bit_cg[bt] = new();
+                foreach(error_iccm_blocked_trig_bit_cg[bt]) error_iccm_blocked_trig_bit_cg[bt] = new();
+                foreach(error_mbox_ecc_unc_trig_bit_cg[bt]) error_mbox_ecc_unc_trig_bit_cg[bt] = new();
+                foreach(error_wdt_timer1_timeout_trig_bit_cg[bt]) error_wdt_timer1_timeout_trig_bit_cg[bt] = new();
+                foreach(error_wdt_timer2_timeout_trig_bit_cg[bt]) error_wdt_timer2_timeout_trig_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__intr_block_t__error_intr_trig_t
 
     // Reg - soc_ifc_reg::intr_block_t::notif_intr_trig_t
     class soc_ifc_reg__intr_block_t__notif_intr_trig_t extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__intr_block_t__notif_intr_trig_t_bit_cg notif_cmd_avail_trig_bit_cg[1];
+        soc_ifc_reg__intr_block_t__notif_intr_trig_t_bit_cg notif_mbox_ecc_cor_trig_bit_cg[1];
+        soc_ifc_reg__intr_block_t__notif_intr_trig_t_bit_cg notif_debug_locked_trig_bit_cg[1];
+        soc_ifc_reg__intr_block_t__notif_intr_trig_t_bit_cg notif_scan_mode_trig_bit_cg[1];
+        soc_ifc_reg__intr_block_t__notif_intr_trig_t_bit_cg notif_soc_req_lock_trig_bit_cg[1];
+        soc_ifc_reg__intr_block_t__notif_intr_trig_t_bit_cg notif_gen_in_toggle_trig_bit_cg[1];
+        soc_ifc_reg__intr_block_t__notif_intr_trig_t_fld_cg fld_cg;
         rand uvm_reg_field notif_cmd_avail_trig;
         rand uvm_reg_field notif_mbox_ecc_cor_trig;
         rand uvm_reg_field notif_debug_locked_trig;
+        rand uvm_reg_field notif_scan_mode_trig;
         rand uvm_reg_field notif_soc_req_lock_trig;
+        rand uvm_reg_field notif_gen_in_toggle_trig;
 
         function new(string name = "soc_ifc_reg__intr_block_t__notif_intr_trig_t");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.notif_cmd_avail_trig = new("notif_cmd_avail_trig");
@@ -957,347 +2610,865 @@ package soc_ifc_reg_uvm;
             this.notif_mbox_ecc_cor_trig.configure(this, 1, 1, "W1S", 0, 'h0, 1, 1, 0);
             this.notif_debug_locked_trig = new("notif_debug_locked_trig");
             this.notif_debug_locked_trig.configure(this, 1, 2, "W1S", 0, 'h0, 1, 1, 0);
+            this.notif_scan_mode_trig = new("notif_scan_mode_trig");
+            this.notif_scan_mode_trig.configure(this, 1, 3, "W1S", 0, 'h0, 1, 1, 0);
             this.notif_soc_req_lock_trig = new("notif_soc_req_lock_trig");
-            this.notif_soc_req_lock_trig.configure(this, 1, 3, "W1S", 0, 'h0, 1, 1, 0);
+            this.notif_soc_req_lock_trig.configure(this, 1, 4, "W1S", 0, 'h0, 1, 1, 0);
+            this.notif_gen_in_toggle_trig = new("notif_gen_in_toggle_trig");
+            this.notif_gen_in_toggle_trig.configure(this, 1, 5, "W1S", 0, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(notif_cmd_avail_trig_bit_cg[bt]) notif_cmd_avail_trig_bit_cg[bt] = new();
+                foreach(notif_mbox_ecc_cor_trig_bit_cg[bt]) notif_mbox_ecc_cor_trig_bit_cg[bt] = new();
+                foreach(notif_debug_locked_trig_bit_cg[bt]) notif_debug_locked_trig_bit_cg[bt] = new();
+                foreach(notif_scan_mode_trig_bit_cg[bt]) notif_scan_mode_trig_bit_cg[bt] = new();
+                foreach(notif_soc_req_lock_trig_bit_cg[bt]) notif_soc_req_lock_trig_bit_cg[bt] = new();
+                foreach(notif_gen_in_toggle_trig_bit_cg[bt]) notif_gen_in_toggle_trig_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__intr_block_t__notif_intr_trig_t
 
     // Reg - soc_ifc_reg::intr_block_t::intr_count_t_cnt_608f1141
     class soc_ifc_reg__intr_block_t__intr_count_t_cnt_608f1141 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__intr_block_t__intr_count_t_cnt_608f1141_bit_cg cnt_bit_cg[32];
+        soc_ifc_reg__intr_block_t__intr_count_t_cnt_608f1141_fld_cg fld_cg;
         rand uvm_reg_field cnt;
 
         function new(string name = "soc_ifc_reg__intr_block_t__intr_count_t_cnt_608f1141");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.cnt = new("cnt");
             this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__intr_block_t__intr_count_t_cnt_608f1141
 
     // Reg - soc_ifc_reg::intr_block_t::intr_count_t_cnt_916ab5df
     class soc_ifc_reg__intr_block_t__intr_count_t_cnt_916ab5df extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__intr_block_t__intr_count_t_cnt_916ab5df_bit_cg cnt_bit_cg[32];
+        soc_ifc_reg__intr_block_t__intr_count_t_cnt_916ab5df_fld_cg fld_cg;
         rand uvm_reg_field cnt;
 
         function new(string name = "soc_ifc_reg__intr_block_t__intr_count_t_cnt_916ab5df");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.cnt = new("cnt");
             this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__intr_block_t__intr_count_t_cnt_916ab5df
 
     // Reg - soc_ifc_reg::intr_block_t::intr_count_t_cnt_b2a56031
     class soc_ifc_reg__intr_block_t__intr_count_t_cnt_b2a56031 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__intr_block_t__intr_count_t_cnt_b2a56031_bit_cg cnt_bit_cg[32];
+        soc_ifc_reg__intr_block_t__intr_count_t_cnt_b2a56031_fld_cg fld_cg;
         rand uvm_reg_field cnt;
 
         function new(string name = "soc_ifc_reg__intr_block_t__intr_count_t_cnt_b2a56031");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.cnt = new("cnt");
             this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__intr_block_t__intr_count_t_cnt_b2a56031
 
     // Reg - soc_ifc_reg::intr_block_t::intr_count_t_cnt_fb7d2433
     class soc_ifc_reg__intr_block_t__intr_count_t_cnt_fb7d2433 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__intr_block_t__intr_count_t_cnt_fb7d2433_bit_cg cnt_bit_cg[32];
+        soc_ifc_reg__intr_block_t__intr_count_t_cnt_fb7d2433_fld_cg fld_cg;
         rand uvm_reg_field cnt;
 
         function new(string name = "soc_ifc_reg__intr_block_t__intr_count_t_cnt_fb7d2433");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.cnt = new("cnt");
             this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__intr_block_t__intr_count_t_cnt_fb7d2433
 
     // Reg - soc_ifc_reg::intr_block_t::intr_count_t_cnt_25e76b6f
     class soc_ifc_reg__intr_block_t__intr_count_t_cnt_25e76b6f extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__intr_block_t__intr_count_t_cnt_25e76b6f_bit_cg cnt_bit_cg[32];
+        soc_ifc_reg__intr_block_t__intr_count_t_cnt_25e76b6f_fld_cg fld_cg;
         rand uvm_reg_field cnt;
 
         function new(string name = "soc_ifc_reg__intr_block_t__intr_count_t_cnt_25e76b6f");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.cnt = new("cnt");
             this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__intr_block_t__intr_count_t_cnt_25e76b6f
 
     // Reg - soc_ifc_reg::intr_block_t::intr_count_t_cnt_26b97e39
     class soc_ifc_reg__intr_block_t__intr_count_t_cnt_26b97e39 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__intr_block_t__intr_count_t_cnt_26b97e39_bit_cg cnt_bit_cg[32];
+        soc_ifc_reg__intr_block_t__intr_count_t_cnt_26b97e39_fld_cg fld_cg;
         rand uvm_reg_field cnt;
 
         function new(string name = "soc_ifc_reg__intr_block_t__intr_count_t_cnt_26b97e39");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.cnt = new("cnt");
             this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__intr_block_t__intr_count_t_cnt_26b97e39
 
     // Reg - soc_ifc_reg::intr_block_t::intr_count_t_cnt_a2f61f82
     class soc_ifc_reg__intr_block_t__intr_count_t_cnt_a2f61f82 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__intr_block_t__intr_count_t_cnt_a2f61f82_bit_cg cnt_bit_cg[32];
+        soc_ifc_reg__intr_block_t__intr_count_t_cnt_a2f61f82_fld_cg fld_cg;
         rand uvm_reg_field cnt;
 
         function new(string name = "soc_ifc_reg__intr_block_t__intr_count_t_cnt_a2f61f82");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.cnt = new("cnt");
             this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__intr_block_t__intr_count_t_cnt_a2f61f82
 
     // Reg - soc_ifc_reg::intr_block_t::intr_count_t_cnt_d46457cd
     class soc_ifc_reg__intr_block_t__intr_count_t_cnt_d46457cd extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__intr_block_t__intr_count_t_cnt_d46457cd_bit_cg cnt_bit_cg[32];
+        soc_ifc_reg__intr_block_t__intr_count_t_cnt_d46457cd_fld_cg fld_cg;
         rand uvm_reg_field cnt;
 
         function new(string name = "soc_ifc_reg__intr_block_t__intr_count_t_cnt_d46457cd");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.cnt = new("cnt");
             this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__intr_block_t__intr_count_t_cnt_d46457cd
 
     // Reg - soc_ifc_reg::intr_block_t::intr_count_t_cnt_a06f0954
     class soc_ifc_reg__intr_block_t__intr_count_t_cnt_a06f0954 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__intr_block_t__intr_count_t_cnt_a06f0954_bit_cg cnt_bit_cg[32];
+        soc_ifc_reg__intr_block_t__intr_count_t_cnt_a06f0954_fld_cg fld_cg;
         rand uvm_reg_field cnt;
 
         function new(string name = "soc_ifc_reg__intr_block_t__intr_count_t_cnt_a06f0954");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.cnt = new("cnt");
             this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__intr_block_t__intr_count_t_cnt_a06f0954
 
     // Reg - soc_ifc_reg::intr_block_t::intr_count_t_cnt_00e49272
     class soc_ifc_reg__intr_block_t__intr_count_t_cnt_00e49272 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__intr_block_t__intr_count_t_cnt_00e49272_bit_cg cnt_bit_cg[32];
+        soc_ifc_reg__intr_block_t__intr_count_t_cnt_00e49272_fld_cg fld_cg;
         rand uvm_reg_field cnt;
 
         function new(string name = "soc_ifc_reg__intr_block_t__intr_count_t_cnt_00e49272");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.cnt = new("cnt");
             this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__intr_block_t__intr_count_t_cnt_00e49272
 
     // Reg - soc_ifc_reg::intr_block_t::intr_count_t_cnt_ee53ded8
     class soc_ifc_reg__intr_block_t__intr_count_t_cnt_ee53ded8 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__intr_block_t__intr_count_t_cnt_ee53ded8_bit_cg cnt_bit_cg[32];
+        soc_ifc_reg__intr_block_t__intr_count_t_cnt_ee53ded8_fld_cg fld_cg;
         rand uvm_reg_field cnt;
 
         function new(string name = "soc_ifc_reg__intr_block_t__intr_count_t_cnt_ee53ded8");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.cnt = new("cnt");
             this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__intr_block_t__intr_count_t_cnt_ee53ded8
 
+    // Reg - soc_ifc_reg::intr_block_t::intr_count_t_cnt_fbf3c714
+    class soc_ifc_reg__intr_block_t__intr_count_t_cnt_fbf3c714 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__intr_block_t__intr_count_t_cnt_fbf3c714_bit_cg cnt_bit_cg[32];
+        soc_ifc_reg__intr_block_t__intr_count_t_cnt_fbf3c714_fld_cg fld_cg;
+        rand uvm_reg_field cnt;
+
+        function new(string name = "soc_ifc_reg__intr_block_t__intr_count_t_cnt_fbf3c714");
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
+        endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
+
+        virtual function void build();
+            this.cnt = new("cnt");
+            this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
+        endfunction : build
+    endclass : soc_ifc_reg__intr_block_t__intr_count_t_cnt_fbf3c714
+
     // Reg - soc_ifc_reg::intr_block_t::intr_count_t_cnt_b9bddabe
     class soc_ifc_reg__intr_block_t__intr_count_t_cnt_b9bddabe extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__intr_block_t__intr_count_t_cnt_b9bddabe_bit_cg cnt_bit_cg[32];
+        soc_ifc_reg__intr_block_t__intr_count_t_cnt_b9bddabe_fld_cg fld_cg;
         rand uvm_reg_field cnt;
 
         function new(string name = "soc_ifc_reg__intr_block_t__intr_count_t_cnt_b9bddabe");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.cnt = new("cnt");
             this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__intr_block_t__intr_count_t_cnt_b9bddabe
 
+    // Reg - soc_ifc_reg::intr_block_t::intr_count_t_cnt_57528cc1
+    class soc_ifc_reg__intr_block_t__intr_count_t_cnt_57528cc1 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__intr_block_t__intr_count_t_cnt_57528cc1_bit_cg cnt_bit_cg[32];
+        soc_ifc_reg__intr_block_t__intr_count_t_cnt_57528cc1_fld_cg fld_cg;
+        rand uvm_reg_field cnt;
+
+        function new(string name = "soc_ifc_reg__intr_block_t__intr_count_t_cnt_57528cc1");
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
+        endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
+
+        virtual function void build();
+            this.cnt = new("cnt");
+            this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
+        endfunction : build
+    endclass : soc_ifc_reg__intr_block_t__intr_count_t_cnt_57528cc1
+
     // Reg - soc_ifc_reg::intr_block_t::intr_count_incr_t_pulse_15e6ed7e
     class soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_15e6ed7e extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_15e6ed7e_bit_cg pulse_bit_cg[1];
+        soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_15e6ed7e_fld_cg fld_cg;
         rand uvm_reg_field pulse;
 
         function new(string name = "soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_15e6ed7e");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.pulse = new("pulse");
             this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_15e6ed7e
 
     // Reg - soc_ifc_reg::intr_block_t::intr_count_incr_t_pulse_f762ea9c
     class soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_f762ea9c extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_f762ea9c_bit_cg pulse_bit_cg[1];
+        soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_f762ea9c_fld_cg fld_cg;
         rand uvm_reg_field pulse;
 
         function new(string name = "soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_f762ea9c");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.pulse = new("pulse");
             this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_f762ea9c
 
     // Reg - soc_ifc_reg::intr_block_t::intr_count_incr_t_pulse_aa8718c6
     class soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_aa8718c6 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_aa8718c6_bit_cg pulse_bit_cg[1];
+        soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_aa8718c6_fld_cg fld_cg;
         rand uvm_reg_field pulse;
 
         function new(string name = "soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_aa8718c6");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.pulse = new("pulse");
             this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_aa8718c6
 
     // Reg - soc_ifc_reg::intr_block_t::intr_count_incr_t_pulse_26fa5955
     class soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_26fa5955 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_26fa5955_bit_cg pulse_bit_cg[1];
+        soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_26fa5955_fld_cg fld_cg;
         rand uvm_reg_field pulse;
 
         function new(string name = "soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_26fa5955");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.pulse = new("pulse");
             this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_26fa5955
 
     // Reg - soc_ifc_reg::intr_block_t::intr_count_incr_t_pulse_3e43d258
     class soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_3e43d258 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_3e43d258_bit_cg pulse_bit_cg[1];
+        soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_3e43d258_fld_cg fld_cg;
         rand uvm_reg_field pulse;
 
         function new(string name = "soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_3e43d258");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.pulse = new("pulse");
             this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_3e43d258
 
     // Reg - soc_ifc_reg::intr_block_t::intr_count_incr_t_pulse_9f1632fd
     class soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_9f1632fd extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_9f1632fd_bit_cg pulse_bit_cg[1];
+        soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_9f1632fd_fld_cg fld_cg;
         rand uvm_reg_field pulse;
 
         function new(string name = "soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_9f1632fd");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.pulse = new("pulse");
             this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_9f1632fd
 
     // Reg - soc_ifc_reg::intr_block_t::intr_count_incr_t_pulse_aa999fdc
     class soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_aa999fdc extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_aa999fdc_bit_cg pulse_bit_cg[1];
+        soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_aa999fdc_fld_cg fld_cg;
         rand uvm_reg_field pulse;
 
         function new(string name = "soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_aa999fdc");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.pulse = new("pulse");
             this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_aa999fdc
 
     // Reg - soc_ifc_reg::intr_block_t::intr_count_incr_t_pulse_404e12db
     class soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_404e12db extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_404e12db_bit_cg pulse_bit_cg[1];
+        soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_404e12db_fld_cg fld_cg;
         rand uvm_reg_field pulse;
 
         function new(string name = "soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_404e12db");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.pulse = new("pulse");
             this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_404e12db
 
     // Reg - soc_ifc_reg::intr_block_t::intr_count_incr_t_pulse_90d52137
     class soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_90d52137 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_90d52137_bit_cg pulse_bit_cg[1];
+        soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_90d52137_fld_cg fld_cg;
         rand uvm_reg_field pulse;
 
         function new(string name = "soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_90d52137");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.pulse = new("pulse");
             this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_90d52137
 
     // Reg - soc_ifc_reg::intr_block_t::intr_count_incr_t_pulse_a6db6fff
     class soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_a6db6fff extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_a6db6fff_bit_cg pulse_bit_cg[1];
+        soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_a6db6fff_fld_cg fld_cg;
         rand uvm_reg_field pulse;
 
         function new(string name = "soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_a6db6fff");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.pulse = new("pulse");
             this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_a6db6fff
 
     // Reg - soc_ifc_reg::intr_block_t::intr_count_incr_t_pulse_51891fb1
     class soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_51891fb1 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_51891fb1_bit_cg pulse_bit_cg[1];
+        soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_51891fb1_fld_cg fld_cg;
         rand uvm_reg_field pulse;
 
         function new(string name = "soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_51891fb1");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.pulse = new("pulse");
             this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_51891fb1
 
+    // Reg - soc_ifc_reg::intr_block_t::intr_count_incr_t_pulse_f5d8afe0
+    class soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_f5d8afe0 extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_f5d8afe0_bit_cg pulse_bit_cg[1];
+        soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_f5d8afe0_fld_cg fld_cg;
+        rand uvm_reg_field pulse;
+
+        function new(string name = "soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_f5d8afe0");
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
+        endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
+
+        virtual function void build();
+            this.pulse = new("pulse");
+            this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
+        endfunction : build
+    endclass : soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_f5d8afe0
+
     // Reg - soc_ifc_reg::intr_block_t::intr_count_incr_t_pulse_246489bd
     class soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_246489bd extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_246489bd_bit_cg pulse_bit_cg[1];
+        soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_246489bd_fld_cg fld_cg;
         rand uvm_reg_field pulse;
 
         function new(string name = "soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_246489bd");
-            super.new(name, 32, UVM_NO_COVERAGE);
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
         endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
 
         virtual function void build();
             this.pulse = new("pulse");
             this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
         endfunction : build
     endclass : soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_246489bd
 
+    // Reg - soc_ifc_reg::intr_block_t::intr_count_incr_t_pulse_d6ed4d1e
+    class soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_d6ed4d1e extends uvm_reg;
+        protected uvm_reg_data_t m_current;
+        protected uvm_reg_data_t m_data;
+        protected bit            m_is_read;
+
+        soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_d6ed4d1e_bit_cg pulse_bit_cg[1];
+        soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_d6ed4d1e_fld_cg fld_cg;
+        rand uvm_reg_field pulse;
+
+        function new(string name = "soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_d6ed4d1e");
+            super.new(name, 32, build_coverage(UVM_CVR_ALL));
+        endfunction : new
+        extern virtual function void sample_values();
+        extern protected virtual function void sample(uvm_reg_data_t  data,
+                                                      uvm_reg_data_t  byte_en,
+                                                      bit             is_read,
+                                                      uvm_reg_map     map);
+
+        virtual function void build();
+            this.pulse = new("pulse");
+            this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
+            if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new();
+            end
+            if (has_coverage(UVM_CVR_FIELD_VALS))
+                fld_cg = new();
+        endfunction : build
+    endclass : soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_d6ed4d1e
+
     // Regfile - soc_ifc_reg::intr_block_t
     class soc_ifc_reg__intr_block_t extends uvm_reg_block;
         rand soc_ifc_reg__intr_block_t__global_intr_en_t global_intr_en_r;
@@ -1306,7 +3477,7 @@ package soc_ifc_reg_uvm;
         rand soc_ifc_reg__intr_block_t__global_intr_t_agg_sts_dd3dcf0a error_global_intr_r;
         rand soc_ifc_reg__intr_block_t__global_intr_t_agg_sts_e6399b4a notif_global_intr_r;
         rand soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f error_internal_intr_r;
-        rand soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_mbox_ecc_cor_sts_5c3d26bb_notif_soc_req_lock_sts_deddde70 notif_internal_intr_r;
+        rand soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70 notif_internal_intr_r;
         rand soc_ifc_reg__intr_block_t__error_intr_trig_t error_intr_trig_r;
         rand soc_ifc_reg__intr_block_t__notif_intr_trig_t notif_intr_trig_r;
         rand soc_ifc_reg__intr_block_t__intr_count_t_cnt_608f1141 error_internal_intr_count_r;
@@ -1320,7 +3491,9 @@ package soc_ifc_reg_uvm;
         rand soc_ifc_reg__intr_block_t__intr_count_t_cnt_a06f0954 notif_cmd_avail_intr_count_r;
         rand soc_ifc_reg__intr_block_t__intr_count_t_cnt_00e49272 notif_mbox_ecc_cor_intr_count_r;
         rand soc_ifc_reg__intr_block_t__intr_count_t_cnt_ee53ded8 notif_debug_locked_intr_count_r;
+        rand soc_ifc_reg__intr_block_t__intr_count_t_cnt_fbf3c714 notif_scan_mode_intr_count_r;
         rand soc_ifc_reg__intr_block_t__intr_count_t_cnt_b9bddabe notif_soc_req_lock_intr_count_r;
+        rand soc_ifc_reg__intr_block_t__intr_count_t_cnt_57528cc1 notif_gen_in_toggle_intr_count_r;
         rand soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_15e6ed7e error_internal_intr_count_incr_r;
         rand soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_f762ea9c error_inv_dev_intr_count_incr_r;
         rand soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_aa8718c6 error_cmd_fail_intr_count_incr_r;
@@ -1332,7 +3505,9 @@ package soc_ifc_reg_uvm;
         rand soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_90d52137 notif_cmd_avail_intr_count_incr_r;
         rand soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_a6db6fff notif_mbox_ecc_cor_intr_count_incr_r;
         rand soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_51891fb1 notif_debug_locked_intr_count_incr_r;
+        rand soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_f5d8afe0 notif_scan_mode_intr_count_incr_r;
         rand soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_246489bd notif_soc_req_lock_intr_count_incr_r;
+        rand soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_d6ed4d1e notif_gen_in_toggle_intr_count_incr_r;
 
         function new(string name = "soc_ifc_reg__intr_block_t");
             super.new(name);
@@ -1440,11 +3615,21 @@ package soc_ifc_reg_uvm;
 
             this.notif_debug_locked_intr_count_r.build();
             this.default_map.add_reg(this.notif_debug_locked_intr_count_r, 'h188);
+            this.notif_scan_mode_intr_count_r = new("notif_scan_mode_intr_count_r");
+            this.notif_scan_mode_intr_count_r.configure(this);
+
+            this.notif_scan_mode_intr_count_r.build();
+            this.default_map.add_reg(this.notif_scan_mode_intr_count_r, 'h18c);
             this.notif_soc_req_lock_intr_count_r = new("notif_soc_req_lock_intr_count_r");
             this.notif_soc_req_lock_intr_count_r.configure(this);
 
             this.notif_soc_req_lock_intr_count_r.build();
-            this.default_map.add_reg(this.notif_soc_req_lock_intr_count_r, 'h18c);
+            this.default_map.add_reg(this.notif_soc_req_lock_intr_count_r, 'h190);
+            this.notif_gen_in_toggle_intr_count_r = new("notif_gen_in_toggle_intr_count_r");
+            this.notif_gen_in_toggle_intr_count_r.configure(this);
+
+            this.notif_gen_in_toggle_intr_count_r.build();
+            this.default_map.add_reg(this.notif_gen_in_toggle_intr_count_r, 'h194);
             this.error_internal_intr_count_incr_r = new("error_internal_intr_count_incr_r");
             this.error_internal_intr_count_incr_r.configure(this);
 
@@ -1500,11 +3685,21 @@ package soc_ifc_reg_uvm;
 
             this.notif_debug_locked_intr_count_incr_r.build();
             this.default_map.add_reg(this.notif_debug_locked_intr_count_incr_r, 'h228);
+            this.notif_scan_mode_intr_count_incr_r = new("notif_scan_mode_intr_count_incr_r");
+            this.notif_scan_mode_intr_count_incr_r.configure(this);
+
+            this.notif_scan_mode_intr_count_incr_r.build();
+            this.default_map.add_reg(this.notif_scan_mode_intr_count_incr_r, 'h22c);
             this.notif_soc_req_lock_intr_count_incr_r = new("notif_soc_req_lock_intr_count_incr_r");
             this.notif_soc_req_lock_intr_count_incr_r.configure(this);
 
             this.notif_soc_req_lock_intr_count_incr_r.build();
-            this.default_map.add_reg(this.notif_soc_req_lock_intr_count_incr_r, 'h22c);
+            this.default_map.add_reg(this.notif_soc_req_lock_intr_count_incr_r, 'h230);
+            this.notif_gen_in_toggle_intr_count_incr_r = new("notif_gen_in_toggle_intr_count_incr_r");
+            this.notif_gen_in_toggle_intr_count_incr_r.configure(this);
+
+            this.notif_gen_in_toggle_intr_count_incr_r.build();
+            this.default_map.add_reg(this.notif_gen_in_toggle_intr_count_incr_r, 'h234);
         endfunction : build
     endclass : soc_ifc_reg__intr_block_t
 
@@ -1526,6 +3721,7 @@ package soc_ifc_reg_uvm;
         rand soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER CPTRA_TRNG_VALID_PAUSER;
         rand soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK CPTRA_TRNG_PAUSER_LOCK;
         rand soc_ifc_reg__CPTRA_TRNG_DATA CPTRA_TRNG_DATA[12];
+        rand soc_ifc_reg__CPTRA_TRNG_CTRL CPTRA_TRNG_CTRL;
         rand soc_ifc_reg__CPTRA_TRNG_STATUS CPTRA_TRNG_STATUS;
         rand soc_ifc_reg__CPTRA_FUSE_WR_DONE CPTRA_FUSE_WR_DONE;
         rand soc_ifc_reg__CPTRA_TIMER_CONFIG CPTRA_TIMER_CONFIG;
@@ -1544,6 +3740,12 @@ package soc_ifc_reg_uvm;
         rand soc_ifc_reg__CPTRA_WDT_TIMER2_CTRL CPTRA_WDT_TIMER2_CTRL;
         rand soc_ifc_reg__CPTRA_WDT_TIMER2_TIMEOUT_PERIOD CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[2];
         rand soc_ifc_reg__CPTRA_WDT_STATUS CPTRA_WDT_STATUS;
+        rand soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER CPTRA_FUSE_VALID_PAUSER;
+        rand soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK CPTRA_FUSE_PAUSER_LOCK;
+        rand soc_ifc_reg__CPTRA_WDT_CFG CPTRA_WDT_CFG[2];
+        rand soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_0 CPTRA_iTRNG_ENTROPY_CONFIG_0;
+        rand soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_1 CPTRA_iTRNG_ENTROPY_CONFIG_1;
+        rand soc_ifc_reg__CPTRA_RSVD_REG CPTRA_RSVD_REG[2];
         rand soc_ifc_reg__fuse_uds_seed fuse_uds_seed[12];
         rand soc_ifc_reg__fuse_field_entropy fuse_field_entropy[8];
         rand soc_ifc_reg__fuse_key_manifest_pk_hash fuse_key_manifest_pk_hash[12];
@@ -1555,11 +3757,22 @@ package soc_ifc_reg_uvm;
         rand soc_ifc_reg__fuse_idevid_cert_attr fuse_idevid_cert_attr[24];
         rand soc_ifc_reg__fuse_idevid_manuf_hsm_id fuse_idevid_manuf_hsm_id[4];
         rand soc_ifc_reg__fuse_life_cycle fuse_life_cycle;
+        rand soc_ifc_reg__fuse_lms_verify fuse_lms_verify;
+        rand soc_ifc_reg__fuse_lms_revocation fuse_lms_revocation;
+        rand soc_ifc_reg__fuse_soc_stepping_id fuse_soc_stepping_id;
         rand soc_ifc_reg__internal_obf_key internal_obf_key[8];
         rand soc_ifc_reg__internal_iccm_lock internal_iccm_lock;
         rand soc_ifc_reg__internal_fw_update_reset internal_fw_update_reset;
         rand soc_ifc_reg__internal_fw_update_reset_wait_cycles internal_fw_update_reset_wait_cycles;
         rand soc_ifc_reg__internal_nmi_vector internal_nmi_vector;
+        rand soc_ifc_reg__internal_hw_error_fatal_mask internal_hw_error_fatal_mask;
+        rand soc_ifc_reg__internal_hw_error_non_fatal_mask internal_hw_error_non_fatal_mask;
+        rand soc_ifc_reg__internal_fw_error_fatal_mask internal_fw_error_fatal_mask;
+        rand soc_ifc_reg__internal_fw_error_non_fatal_mask internal_fw_error_non_fatal_mask;
+        rand soc_ifc_reg__internal_rv_mtime_l internal_rv_mtime_l;
+        rand soc_ifc_reg__internal_rv_mtime_h internal_rv_mtime_h;
+        rand soc_ifc_reg__internal_rv_mtimecmp_l internal_rv_mtimecmp_l;
+        rand soc_ifc_reg__internal_rv_mtimecmp_h internal_rv_mtimecmp_h;
         rand soc_ifc_reg__intr_block_t intr_block_rf;
 
         function new(string name = "soc_ifc_reg");
@@ -1656,106 +3869,145 @@ package soc_ifc_reg_uvm;
                 this.CPTRA_TRNG_DATA[i0].build();
                 this.default_map.add_reg(this.CPTRA_TRNG_DATA[i0], 'h78 + i0*'h4);
             end
+            this.CPTRA_TRNG_CTRL = new("CPTRA_TRNG_CTRL");
+            this.CPTRA_TRNG_CTRL.configure(this);
+
+            this.CPTRA_TRNG_CTRL.build();
+            this.default_map.add_reg(this.CPTRA_TRNG_CTRL, 'ha8);
             this.CPTRA_TRNG_STATUS = new("CPTRA_TRNG_STATUS");
             this.CPTRA_TRNG_STATUS.configure(this);
 
             this.CPTRA_TRNG_STATUS.build();
-            this.default_map.add_reg(this.CPTRA_TRNG_STATUS, 'ha8);
+            this.default_map.add_reg(this.CPTRA_TRNG_STATUS, 'hac);
             this.CPTRA_FUSE_WR_DONE = new("CPTRA_FUSE_WR_DONE");
             this.CPTRA_FUSE_WR_DONE.configure(this);
 
             this.CPTRA_FUSE_WR_DONE.build();
-            this.default_map.add_reg(this.CPTRA_FUSE_WR_DONE, 'hac);
+            this.default_map.add_reg(this.CPTRA_FUSE_WR_DONE, 'hb0);
             this.CPTRA_TIMER_CONFIG = new("CPTRA_TIMER_CONFIG");
             this.CPTRA_TIMER_CONFIG.configure(this);
 
             this.CPTRA_TIMER_CONFIG.build();
-            this.default_map.add_reg(this.CPTRA_TIMER_CONFIG, 'hb0);
+            this.default_map.add_reg(this.CPTRA_TIMER_CONFIG, 'hb4);
             this.CPTRA_BOOTFSM_GO = new("CPTRA_BOOTFSM_GO");
             this.CPTRA_BOOTFSM_GO.configure(this);
 
             this.CPTRA_BOOTFSM_GO.build();
-            this.default_map.add_reg(this.CPTRA_BOOTFSM_GO, 'hb4);
+            this.default_map.add_reg(this.CPTRA_BOOTFSM_GO, 'hb8);
             this.CPTRA_DBG_MANUF_SERVICE_REG = new("CPTRA_DBG_MANUF_SERVICE_REG");
             this.CPTRA_DBG_MANUF_SERVICE_REG.configure(this);
 
             this.CPTRA_DBG_MANUF_SERVICE_REG.build();
-            this.default_map.add_reg(this.CPTRA_DBG_MANUF_SERVICE_REG, 'hb8);
+            this.default_map.add_reg(this.CPTRA_DBG_MANUF_SERVICE_REG, 'hbc);
             this.CPTRA_CLK_GATING_EN = new("CPTRA_CLK_GATING_EN");
             this.CPTRA_CLK_GATING_EN.configure(this);
 
             this.CPTRA_CLK_GATING_EN.build();
-            this.default_map.add_reg(this.CPTRA_CLK_GATING_EN, 'hbc);
+            this.default_map.add_reg(this.CPTRA_CLK_GATING_EN, 'hc0);
             foreach(this.CPTRA_GENERIC_INPUT_WIRES[i0]) begin
                 this.CPTRA_GENERIC_INPUT_WIRES[i0] = new($sformatf("CPTRA_GENERIC_INPUT_WIRES[%0d]", i0));
                 this.CPTRA_GENERIC_INPUT_WIRES[i0].configure(this);
                 
                 this.CPTRA_GENERIC_INPUT_WIRES[i0].build();
-                this.default_map.add_reg(this.CPTRA_GENERIC_INPUT_WIRES[i0], 'hc0 + i0*'h4);
+                this.default_map.add_reg(this.CPTRA_GENERIC_INPUT_WIRES[i0], 'hc4 + i0*'h4);
             end
             foreach(this.CPTRA_GENERIC_OUTPUT_WIRES[i0]) begin
                 this.CPTRA_GENERIC_OUTPUT_WIRES[i0] = new($sformatf("CPTRA_GENERIC_OUTPUT_WIRES[%0d]", i0));
                 this.CPTRA_GENERIC_OUTPUT_WIRES[i0].configure(this);
                 
                 this.CPTRA_GENERIC_OUTPUT_WIRES[i0].build();
-                this.default_map.add_reg(this.CPTRA_GENERIC_OUTPUT_WIRES[i0], 'hc8 + i0*'h4);
+                this.default_map.add_reg(this.CPTRA_GENERIC_OUTPUT_WIRES[i0], 'hcc + i0*'h4);
             end
             this.CPTRA_HW_REV_ID = new("CPTRA_HW_REV_ID");
             this.CPTRA_HW_REV_ID.configure(this);
 
             this.CPTRA_HW_REV_ID.build();
-            this.default_map.add_reg(this.CPTRA_HW_REV_ID, 'hd0);
+            this.default_map.add_reg(this.CPTRA_HW_REV_ID, 'hd4);
             foreach(this.CPTRA_FW_REV_ID[i0]) begin
                 this.CPTRA_FW_REV_ID[i0] = new($sformatf("CPTRA_FW_REV_ID[%0d]", i0));
                 this.CPTRA_FW_REV_ID[i0].configure(this);
                 
                 this.CPTRA_FW_REV_ID[i0].build();
-                this.default_map.add_reg(this.CPTRA_FW_REV_ID[i0], 'hd4 + i0*'h4);
+                this.default_map.add_reg(this.CPTRA_FW_REV_ID[i0], 'hd8 + i0*'h4);
             end
             this.CPTRA_HW_CONFIG = new("CPTRA_HW_CONFIG");
             this.CPTRA_HW_CONFIG.configure(this);
 
             this.CPTRA_HW_CONFIG.build();
-            this.default_map.add_reg(this.CPTRA_HW_CONFIG, 'hdc);
+            this.default_map.add_reg(this.CPTRA_HW_CONFIG, 'he0);
             this.CPTRA_WDT_TIMER1_EN = new("CPTRA_WDT_TIMER1_EN");
             this.CPTRA_WDT_TIMER1_EN.configure(this);
 
             this.CPTRA_WDT_TIMER1_EN.build();
-            this.default_map.add_reg(this.CPTRA_WDT_TIMER1_EN, 'he0);
+            this.default_map.add_reg(this.CPTRA_WDT_TIMER1_EN, 'he4);
             this.CPTRA_WDT_TIMER1_CTRL = new("CPTRA_WDT_TIMER1_CTRL");
             this.CPTRA_WDT_TIMER1_CTRL.configure(this);
 
             this.CPTRA_WDT_TIMER1_CTRL.build();
-            this.default_map.add_reg(this.CPTRA_WDT_TIMER1_CTRL, 'he4);
+            this.default_map.add_reg(this.CPTRA_WDT_TIMER1_CTRL, 'he8);
             foreach(this.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i0]) begin
                 this.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i0] = new($sformatf("CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[%0d]", i0));
                 this.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i0].configure(this);
                 
                 this.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i0].build();
-                this.default_map.add_reg(this.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i0], 'he8 + i0*'h4);
+                this.default_map.add_reg(this.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i0], 'hec + i0*'h4);
             end
             this.CPTRA_WDT_TIMER2_EN = new("CPTRA_WDT_TIMER2_EN");
             this.CPTRA_WDT_TIMER2_EN.configure(this);
 
             this.CPTRA_WDT_TIMER2_EN.build();
-            this.default_map.add_reg(this.CPTRA_WDT_TIMER2_EN, 'hf0);
+            this.default_map.add_reg(this.CPTRA_WDT_TIMER2_EN, 'hf4);
             this.CPTRA_WDT_TIMER2_CTRL = new("CPTRA_WDT_TIMER2_CTRL");
             this.CPTRA_WDT_TIMER2_CTRL.configure(this);
 
             this.CPTRA_WDT_TIMER2_CTRL.build();
-            this.default_map.add_reg(this.CPTRA_WDT_TIMER2_CTRL, 'hf4);
+            this.default_map.add_reg(this.CPTRA_WDT_TIMER2_CTRL, 'hf8);
             foreach(this.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i0]) begin
                 this.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i0] = new($sformatf("CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[%0d]", i0));
                 this.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i0].configure(this);
                 
                 this.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i0].build();
-                this.default_map.add_reg(this.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i0], 'hf8 + i0*'h4);
+                this.default_map.add_reg(this.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i0], 'hfc + i0*'h4);
             end
             this.CPTRA_WDT_STATUS = new("CPTRA_WDT_STATUS");
             this.CPTRA_WDT_STATUS.configure(this);
 
             this.CPTRA_WDT_STATUS.build();
-            this.default_map.add_reg(this.CPTRA_WDT_STATUS, 'h100);
+            this.default_map.add_reg(this.CPTRA_WDT_STATUS, 'h104);
+            this.CPTRA_FUSE_VALID_PAUSER = new("CPTRA_FUSE_VALID_PAUSER");
+            this.CPTRA_FUSE_VALID_PAUSER.configure(this);
+
+            this.CPTRA_FUSE_VALID_PAUSER.build();
+            this.default_map.add_reg(this.CPTRA_FUSE_VALID_PAUSER, 'h108);
+            this.CPTRA_FUSE_PAUSER_LOCK = new("CPTRA_FUSE_PAUSER_LOCK");
+            this.CPTRA_FUSE_PAUSER_LOCK.configure(this);
+
+            this.CPTRA_FUSE_PAUSER_LOCK.build();
+            this.default_map.add_reg(this.CPTRA_FUSE_PAUSER_LOCK, 'h10c);
+            foreach(this.CPTRA_WDT_CFG[i0]) begin
+                this.CPTRA_WDT_CFG[i0] = new($sformatf("CPTRA_WDT_CFG[%0d]", i0));
+                this.CPTRA_WDT_CFG[i0].configure(this);
+                
+                this.CPTRA_WDT_CFG[i0].build();
+                this.default_map.add_reg(this.CPTRA_WDT_CFG[i0], 'h110 + i0*'h4);
+            end
+            this.CPTRA_iTRNG_ENTROPY_CONFIG_0 = new("CPTRA_iTRNG_ENTROPY_CONFIG_0");
+            this.CPTRA_iTRNG_ENTROPY_CONFIG_0.configure(this);
+
+            this.CPTRA_iTRNG_ENTROPY_CONFIG_0.build();
+            this.default_map.add_reg(this.CPTRA_iTRNG_ENTROPY_CONFIG_0, 'h118);
+            this.CPTRA_iTRNG_ENTROPY_CONFIG_1 = new("CPTRA_iTRNG_ENTROPY_CONFIG_1");
+            this.CPTRA_iTRNG_ENTROPY_CONFIG_1.configure(this);
+
+            this.CPTRA_iTRNG_ENTROPY_CONFIG_1.build();
+            this.default_map.add_reg(this.CPTRA_iTRNG_ENTROPY_CONFIG_1, 'h11c);
+            foreach(this.CPTRA_RSVD_REG[i0]) begin
+                this.CPTRA_RSVD_REG[i0] = new($sformatf("CPTRA_RSVD_REG[%0d]", i0));
+                this.CPTRA_RSVD_REG[i0].configure(this);
+                
+                this.CPTRA_RSVD_REG[i0].build();
+                this.default_map.add_reg(this.CPTRA_RSVD_REG[i0], 'h120 + i0*'h4);
+            end
             foreach(this.fuse_uds_seed[i0]) begin
                 this.fuse_uds_seed[i0] = new($sformatf("fuse_uds_seed[%0d]", i0));
                 this.fuse_uds_seed[i0].configure(this);
@@ -1825,6 +4077,21 @@ package soc_ifc_reg_uvm;
 
             this.fuse_life_cycle.build();
             this.default_map.add_reg(this.fuse_life_cycle, 'h33c);
+            this.fuse_lms_verify = new("fuse_lms_verify");
+            this.fuse_lms_verify.configure(this);
+
+            this.fuse_lms_verify.build();
+            this.default_map.add_reg(this.fuse_lms_verify, 'h340);
+            this.fuse_lms_revocation = new("fuse_lms_revocation");
+            this.fuse_lms_revocation.configure(this);
+
+            this.fuse_lms_revocation.build();
+            this.default_map.add_reg(this.fuse_lms_revocation, 'h344);
+            this.fuse_soc_stepping_id = new("fuse_soc_stepping_id");
+            this.fuse_soc_stepping_id.configure(this);
+
+            this.fuse_soc_stepping_id.build();
+            this.default_map.add_reg(this.fuse_soc_stepping_id, 'h348);
             foreach(this.internal_obf_key[i0]) begin
                 this.internal_obf_key[i0] = new($sformatf("internal_obf_key[%0d]", i0));
                 this.internal_obf_key[i0].configure(this);
@@ -1852,6 +4119,46 @@ package soc_ifc_reg_uvm;
 
             this.internal_nmi_vector.build();
             this.default_map.add_reg(this.internal_nmi_vector, 'h62c);
+            this.internal_hw_error_fatal_mask = new("internal_hw_error_fatal_mask");
+            this.internal_hw_error_fatal_mask.configure(this);
+
+            this.internal_hw_error_fatal_mask.build();
+            this.default_map.add_reg(this.internal_hw_error_fatal_mask, 'h630);
+            this.internal_hw_error_non_fatal_mask = new("internal_hw_error_non_fatal_mask");
+            this.internal_hw_error_non_fatal_mask.configure(this);
+
+            this.internal_hw_error_non_fatal_mask.build();
+            this.default_map.add_reg(this.internal_hw_error_non_fatal_mask, 'h634);
+            this.internal_fw_error_fatal_mask = new("internal_fw_error_fatal_mask");
+            this.internal_fw_error_fatal_mask.configure(this);
+
+            this.internal_fw_error_fatal_mask.build();
+            this.default_map.add_reg(this.internal_fw_error_fatal_mask, 'h638);
+            this.internal_fw_error_non_fatal_mask = new("internal_fw_error_non_fatal_mask");
+            this.internal_fw_error_non_fatal_mask.configure(this);
+
+            this.internal_fw_error_non_fatal_mask.build();
+            this.default_map.add_reg(this.internal_fw_error_non_fatal_mask, 'h63c);
+            this.internal_rv_mtime_l = new("internal_rv_mtime_l");
+            this.internal_rv_mtime_l.configure(this);
+
+            this.internal_rv_mtime_l.build();
+            this.default_map.add_reg(this.internal_rv_mtime_l, 'h640);
+            this.internal_rv_mtime_h = new("internal_rv_mtime_h");
+            this.internal_rv_mtime_h.configure(this);
+
+            this.internal_rv_mtime_h.build();
+            this.default_map.add_reg(this.internal_rv_mtime_h, 'h644);
+            this.internal_rv_mtimecmp_l = new("internal_rv_mtimecmp_l");
+            this.internal_rv_mtimecmp_l.configure(this);
+
+            this.internal_rv_mtimecmp_l.build();
+            this.default_map.add_reg(this.internal_rv_mtimecmp_l, 'h648);
+            this.internal_rv_mtimecmp_h = new("internal_rv_mtimecmp_h");
+            this.internal_rv_mtimecmp_h.configure(this);
+
+            this.internal_rv_mtimecmp_h.build();
+            this.default_map.add_reg(this.internal_rv_mtimecmp_h, 'h64c);
             this.intr_block_rf = new("intr_block_rf");
             this.intr_block_rf.configure(this);
             this.intr_block_rf.build();
@@ -1859,4 +4166,5 @@ package soc_ifc_reg_uvm;
         endfunction : build
     endclass : soc_ifc_reg
 
+    `include "soc_ifc_reg_sample.svh"
 endpackage: soc_ifc_reg_uvm
diff --git a/src/soc_ifc/rtl/soc_ifc_top.sv b/src/soc_ifc/rtl/soc_ifc_top.sv
index 4347ec15a..5629dd4b5 100644
--- a/src/soc_ifc/rtl/soc_ifc_top.sv
+++ b/src/soc_ifc/rtl/soc_ifc_top.sv
@@ -14,6 +14,7 @@
 
 `include "caliptra_sva.svh"
 `include "caliptra_macros.svh"
+`include "caliptra_reg_defines.svh"
 
 module soc_ifc_top 
     import soc_ifc_pkg::*;
@@ -29,6 +30,7 @@ module soc_ifc_top
     input logic clk,
     input logic clk_cg,
     input logic soc_ifc_clk_cg,
+    input logic rdc_clk_cg,
 
     //SoC boot signals
     input logic cptra_pwrgood,
@@ -81,11 +83,15 @@ module soc_ifc_top
     output wire              soc_ifc_notif_intr,
     output wire              sha_error_intr,
     output wire              sha_notif_intr,
+    output wire              timer_intr,
 
     //SRAM interface
     output mbox_sram_req_t  mbox_sram_req,
     input  mbox_sram_resp_t mbox_sram_resp,
 
+    // RV ECC Status Interface
+    input rv_ecc_sts_t rv_ecc_sts,
+
     //Obfuscated UDS and FE
     input  logic clear_obf_secrets,
     input  logic scan_mode_f,
@@ -108,6 +114,8 @@ module soc_ifc_top
     output logic cptra_uc_rst_b,
     //Clock gating
     output logic clk_gating_en,
+    output logic rdc_clk_dis,
+    output logic fw_update_rst_window,
 
     //caliptra uncore jtag ports
     input  logic                            cptra_uncore_dmi_reg_en,
@@ -135,6 +143,7 @@ logic mbox_dir_req_dv;
 logic mbox_req_hold;
 soc_ifc_req_t mbox_req_data;
 logic [SOC_IFC_DATA_W-1:0] mbox_rdata;
+logic [SOC_IFC_DATA_W-1:0] mbox_dir_rdata;
 logic mbox_error;
 
 //sha req inf
@@ -165,18 +174,28 @@ logic uc_mbox_data_avail_d;
 logic uc_cmd_avail_p;
 logic security_state_debug_locked_d;
 logic security_state_debug_locked_p;
+logic scan_mode_d;
+logic scan_mode_p;
 logic sram_single_ecc_error;
 logic sram_double_ecc_error;
 logic soc_req_mbox_lock;
+logic [1:0] generic_input_toggle;
+mbox_protocol_error_t mbox_protocol_error;
+logic mbox_inv_user_p;
 
 logic iccm_unlock;
 logic fw_upd_rst_executed;
 logic fuse_wr_done_reg_write_observed;
 
+logic unmasked_hw_error_fatal_write;
+logic unmasked_hw_error_non_fatal_write;
+logic unmasked_hw_error_non_fatal_is_set;
+
 logic pwrgood_toggle_hint;
 logic Warm_Reset_Capture_Flag;
 
 logic BootFSM_BrkPoint_Latched;
+logic BootFSM_BrkPoint_valid;
 logic BootFSM_BrkPoint_Flag;
 
 logic dmi_inc_rdptr;
@@ -202,9 +221,11 @@ logic t2_timeout_f; //To generate interrupt pulse
 logic t2_timeout_p;
 logic wdt_error_t1_intr_serviced;
 logic wdt_error_t2_intr_serviced;
-logic soc_ifc_error_intr_f;
 
 logic valid_trng_user;
+logic valid_fuse_user;
+
+boot_fsm_state_e boot_fsm_ps;
 
 //Boot FSM
 //This module contains the logic required to control the Caliptra Boot Flow
@@ -214,20 +235,24 @@ soc_ifc_boot_fsm i_soc_ifc_boot_fsm (
     .clk(clk),
     .cptra_pwrgood(cptra_pwrgood),
     .cptra_rst_b (cptra_rst_b),
+    .scan_mode(scan_mode_f),
     .fw_update_rst (soc_ifc_reg_hwif_out.internal_fw_update_reset.core_rst.value),
     .fw_update_rst_wait_cycles (soc_ifc_reg_hwif_out.internal_fw_update_reset_wait_cycles.wait_cycles.value),
     .ready_for_fuses(ready_for_fuses),
+    .boot_fsm_ps(boot_fsm_ps),
 
     .fuse_done(soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value),
     .fuse_wr_done_observed(fuse_wr_done_reg_write_observed),
 
-    .BootFSM_BrkPoint(BootFSM_BrkPoint_Latched),
+    .BootFSM_BrkPoint(BootFSM_BrkPoint_valid),
     .BootFSM_Continue(soc_ifc_reg_hwif_out.CPTRA_BOOTFSM_GO.GO.value),
 
     .cptra_noncore_rst_b(cptra_noncore_rst_b), //goes to all other blocks
     .cptra_uc_rst_b(cptra_uc_rst_b), //goes to veer core
     .iccm_unlock(iccm_unlock),
-    .fw_upd_rst_executed(fw_upd_rst_executed)
+    .fw_upd_rst_executed(fw_upd_rst_executed),
+    .rdc_clk_dis(rdc_clk_dis),
+    .fw_update_rst_window(fw_update_rst_window)
 );
 
 always_comb soc_ifc_reg_hwif_in.CPTRA_RESET_REASON.FW_UPD_RESET.we = fw_upd_rst_executed;
@@ -245,7 +270,7 @@ apb_slv_sif #(
 i_apb_slv_sif_soc_ifc (
     //AMBA APB INF
     .PCLK(soc_ifc_clk_cg),
-    .PRESETn(cptra_rst_b),
+    .PRESETn(cptra_noncore_rst_b),
     .PADDR(paddr_i),
     .PPROT('0),
     .PSEL(psel_i),
@@ -320,8 +345,9 @@ soc_ifc_arb #(
     )
     i_soc_ifc_arb (
     .clk(soc_ifc_clk_cg),
-    .rst_b(cptra_rst_b),
+    .rst_b(cptra_noncore_rst_b),
     .valid_mbox_users(valid_mbox_users),
+    .valid_fuse_user(valid_fuse_user),
     //UC inf
     .uc_req_dv(uc_req_dv), 
     .uc_req_hold(uc_req_hold), 
@@ -340,6 +366,7 @@ soc_ifc_arb #(
     .mbox_req_hold(mbox_req_hold),
     .mbox_req_data(mbox_req_data),
     .mbox_rdata(mbox_rdata),
+    .mbox_dir_rdata(mbox_dir_rdata),
     .mbox_error(mbox_error),
     //SHA inf
     .sha_req_dv(sha_req_dv),
@@ -363,7 +390,7 @@ soc_ifc_arb #(
 //Read and Write permissions are controlled within this block
 always_comb soc_ifc_reg_error = soc_ifc_reg_read_error | soc_ifc_reg_write_error;
 
-always_comb soc_ifc_reg_hwif_in.cptra_rst_b = cptra_rst_b;
+always_comb soc_ifc_reg_hwif_in.cptra_rst_b = cptra_noncore_rst_b;
 always_comb soc_ifc_reg_hwif_in.cptra_pwrgood = cptra_pwrgood;
 always_comb soc_ifc_reg_hwif_in.soc_req = soc_ifc_reg_req_data.soc_req;
 
@@ -384,6 +411,11 @@ always_comb soc_ifc_reg_hwif_in.CPTRA_HW_CONFIG.UART_en.next = 1'b1;
 always_comb soc_ifc_reg_hwif_in.CPTRA_HW_CONFIG.UART_en.next = 1'b0;
 `endif
 
+//SOC Stepping ID update
+always_comb begin
+    soc_ifc_reg_hwif_in.CPTRA_HW_REV_ID.SOC_STEPPING_ID.next = soc_ifc_reg_hwif_out.fuse_soc_stepping_id.soc_stepping_id.value[15:0];
+end
+
 always_comb begin
     for (int i = 0; i < `CLP_OBF_KEY_DWORDS; i++) begin
         soc_ifc_reg_hwif_in.internal_obf_key[i].key.swwe = '0; //sw can't write to obf key
@@ -407,6 +439,7 @@ always_comb begin
     ready_for_fw_push = soc_ifc_reg_hwif_out.CPTRA_FLOW_STATUS.ready_for_fw.value;
     ready_for_runtime = soc_ifc_reg_hwif_out.CPTRA_FLOW_STATUS.ready_for_runtime.value;
     soc_ifc_reg_hwif_in.CPTRA_FLOW_STATUS.ready_for_fuses.next = ready_for_fuses;
+    soc_ifc_reg_hwif_in.CPTRA_FLOW_STATUS.boot_fsm_ps.next = boot_fsm_ps;
     soc_ifc_reg_hwif_in.CPTRA_SECURITY_STATE.device_lifecycle.next = security_state.device_lifecycle;
     soc_ifc_reg_hwif_in.CPTRA_SECURITY_STATE.debug_locked.next     = security_state.debug_locked;
     soc_ifc_reg_hwif_in.CPTRA_SECURITY_STATE.scan_mode.next        = scan_mode_f;
@@ -414,6 +447,12 @@ always_comb begin
     for (int i = 0; i < 2; i++) begin
         generic_output_wires[i] = soc_ifc_reg_hwif_out.CPTRA_GENERIC_OUTPUT_WIRES[i].generic_wires.value;
         soc_ifc_reg_hwif_in.CPTRA_GENERIC_INPUT_WIRES[i].generic_wires.next = generic_input_wires[i];
+        if (|(soc_ifc_reg_hwif_out.CPTRA_GENERIC_INPUT_WIRES[i].generic_wires.value ^ generic_input_wires[i])) begin
+            generic_input_toggle[i] = 1;
+        end
+        else begin
+            generic_input_toggle[i] = 0;
+        end
     end
 
 end
@@ -426,21 +465,23 @@ logic cptra_in_dbg_or_manuf_mode;
 assign cptra_in_dbg_or_manuf_mode = ~(security_state.debug_locked) | 
                                      ((security_state.debug_locked) & (security_state.device_lifecycle == DEVICE_MANUFACTURING));
 
-always_ff @(posedge clk or negedge cptra_rst_b) begin
-    if (~cptra_rst_b) begin
+always_ff @(posedge rdc_clk_cg or negedge cptra_noncore_rst_b) begin
+    if (~cptra_noncore_rst_b) begin
         BootFSM_BrkPoint_Latched <= 0;
         BootFSM_BrkPoint_Flag <= 0;
     end
     // Breakpoint value captured on a Caliptra reset deassertion (0->1 signal transition) and is reset on BootFSM_Continue is set
     // BootFSM_Continue's reset value is zero
     else if(!BootFSM_BrkPoint_Flag) begin
-        BootFSM_BrkPoint_Latched <= BootFSM_BrkPoint & cptra_in_dbg_or_manuf_mode;
+        BootFSM_BrkPoint_Latched <= BootFSM_BrkPoint;
         BootFSM_BrkPoint_Flag <= 1;
     end
 end
 
+assign BootFSM_BrkPoint_valid = BootFSM_BrkPoint_Latched & cptra_in_dbg_or_manuf_mode;
+
 // pwrgood_hint informs if the powergood toggled
-always_ff @(posedge clk or negedge cptra_pwrgood) begin
+always_ff @(posedge rdc_clk_cg or negedge cptra_pwrgood) begin
      if(~cptra_pwrgood) begin
         pwrgood_toggle_hint <= 1;
      end
@@ -450,8 +491,8 @@ always_ff @(posedge clk or negedge cptra_pwrgood) begin
      end
 end
 
-always_ff @(posedge clk or negedge cptra_rst_b) begin
-    if (~cptra_rst_b) begin
+always_ff @(posedge rdc_clk_cg or negedge cptra_noncore_rst_b) begin
+    if (~cptra_noncore_rst_b) begin
         Warm_Reset_Capture_Flag <= 0;
     end
     else if(!Warm_Reset_Capture_Flag) begin
@@ -476,7 +517,7 @@ end
 
 
 // Generate a pulse to set the interrupt bit
-always_ff @(posedge soc_ifc_clk_cg or negedge cptra_noncore_rst_b) begin
+always_ff @(posedge rdc_clk_cg or negedge cptra_noncore_rst_b) begin
     if (~cptra_noncore_rst_b) begin
         security_state_debug_locked_d <= '0;
     end
@@ -487,6 +528,18 @@ end
 
 always_comb security_state_debug_locked_p = security_state.debug_locked ^ security_state_debug_locked_d;
 
+// Generate a pulse to set the interrupt bit
+always_ff @(posedge clk or negedge cptra_noncore_rst_b) begin
+    if (~cptra_noncore_rst_b) begin
+        scan_mode_d <= '0;
+    end
+    else begin
+        scan_mode_d <= scan_mode_f;
+    end
+end
+
+always_comb scan_mode_p = scan_mode_f & ~scan_mode_d;
+
 //Filtering by PAUSER
 always_comb begin
     for (int i=0; i<5; i++) begin
@@ -500,16 +553,21 @@ always_comb begin
                               soc_ifc_reg_hwif_out.CPTRA_MBOX_VALID_PAUSER[i].PAUSER.value[APB_USER_WIDTH-1:0] : CPTRA_DEF_MBOX_VALID_PAUSER;
     end
 end
+
 //can't write to trng valid user after it is locked
 always_comb soc_ifc_reg_hwif_in.CPTRA_TRNG_VALID_PAUSER.PAUSER.swwel = soc_ifc_reg_hwif_out.CPTRA_TRNG_PAUSER_LOCK.LOCK.value;
 always_comb soc_ifc_reg_hwif_in.CPTRA_TRNG_PAUSER_LOCK.LOCK.swwel = soc_ifc_reg_hwif_out.CPTRA_TRNG_PAUSER_LOCK.LOCK.value;
 
+//fuse register pauser fields
+always_comb soc_ifc_reg_hwif_in.CPTRA_FUSE_VALID_PAUSER.PAUSER.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_PAUSER_LOCK.LOCK.value;
+always_comb soc_ifc_reg_hwif_in.CPTRA_FUSE_PAUSER_LOCK.LOCK.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_PAUSER_LOCK.LOCK.value;
+
 /////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 // Can't write to RW-able fuses once fuse_done is set (implies the register is being locked using the fuse_wr_done)
 /////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 
-always_ff @(posedge clk or negedge cptra_rst_b) begin
-    if(~cptra_rst_b) begin
+always_ff @(posedge soc_ifc_clk_cg or negedge cptra_noncore_rst_b) begin
+    if(~cptra_noncore_rst_b) begin
         fuse_wr_done_reg_write_observed <= 0;
     end
     else begin
@@ -550,6 +608,9 @@ always_comb soc_ifc_reg_hwif_in.fuse_key_manifest_pk_hash_mask.mask.swwel  = soc
 always_comb soc_ifc_reg_hwif_in.fuse_fmc_key_manifest_svn.svn.swwel        = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
 always_comb soc_ifc_reg_hwif_in.fuse_anti_rollback_disable.dis.swwel       = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
 always_comb soc_ifc_reg_hwif_in.fuse_life_cycle.life_cycle.swwel           = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
+always_comb soc_ifc_reg_hwif_in.fuse_lms_verify.lms_verify.swwel           = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
+always_comb soc_ifc_reg_hwif_in.fuse_lms_revocation.lms_revocation.swwel   = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
+always_comb soc_ifc_reg_hwif_in.fuse_soc_stepping_id.soc_stepping_id.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
 
 // Fuse write done can be written by SOC if it is already NOT '1. uController can only read this bit. The bit gets reset on cold reset
 always_comb soc_ifc_reg_hwif_in.CPTRA_FUSE_WR_DONE.done.swwe = soc_ifc_reg_req_data.soc_req & ~soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
@@ -565,12 +626,21 @@ always_comb soc_ifc_reg_hwif_in.CPTRA_TRNG_STATUS.DATA_WR_DONE.swwe = valid_trng
 always_comb begin 
     for (int i = 0; i < 12; i++) begin
         soc_ifc_reg_hwif_in.CPTRA_TRNG_DATA[i].DATA.swwe = valid_trng_user;
+        soc_ifc_reg_hwif_in.CPTRA_TRNG_DATA[i].DATA.hwclr = soc_ifc_reg_hwif_out.CPTRA_TRNG_CTRL.clear.value;
     end
 end
 
 //Clear the DATA_WR_DONE when FW clears the req bit
 always_comb soc_ifc_reg_hwif_in.CPTRA_TRNG_STATUS.DATA_WR_DONE.hwclr = ~soc_ifc_reg_hwif_out.CPTRA_TRNG_STATUS.DATA_REQ.value;
 
+generate
+    if (CPTRA_SET_FUSE_PAUSER_INTEG) begin
+        always_comb valid_fuse_user = soc_req_dv & (soc_req.user == CPTRA_FUSE_VALID_PAUSER);
+    end else begin
+        always_comb valid_fuse_user = soc_req_dv & (~soc_ifc_reg_hwif_out.CPTRA_FUSE_PAUSER_LOCK.LOCK.value | 
+                                     (soc_req.user == soc_ifc_reg_hwif_out.CPTRA_FUSE_VALID_PAUSER.PAUSER.value[APB_USER_WIDTH-1:0]));
+    end
+endgenerate
 // Generate a pulse to set the interrupt bit
 always_ff @(posedge soc_ifc_clk_cg or negedge cptra_noncore_rst_b) begin
     if (~cptra_noncore_rst_b) begin
@@ -583,16 +653,18 @@ end
 
 always_comb uc_cmd_avail_p = uc_mbox_data_avail & !uc_mbox_data_avail_d;
 // Pulse input to soc_ifc_reg to set the interrupt status bit and generate interrupt output (if enabled)
-always_comb soc_ifc_reg_hwif_in.intr_block_rf.error_internal_intr_r.error_internal_sts.hwset     = 1'b0; // TODO
-always_comb soc_ifc_reg_hwif_in.intr_block_rf.error_internal_intr_r.error_inv_dev_sts.hwset      = 1'b0; // TODO should decode from APB PAUSER
-always_comb soc_ifc_reg_hwif_in.intr_block_rf.error_internal_intr_r.error_cmd_fail_sts.hwset     = 1'b0; // TODO should this be set by write of "FAIL" to mbox_csr.status if soc_req is set? (i.e. SoC cmd execution failed)
-always_comb soc_ifc_reg_hwif_in.intr_block_rf.error_internal_intr_r.error_bad_fuse_sts.hwset     = 1'b0; // TODO
-always_comb soc_ifc_reg_hwif_in.intr_block_rf.error_internal_intr_r.error_iccm_blocked_sts.hwset = iccm_axs_blocked;
-always_comb soc_ifc_reg_hwif_in.intr_block_rf.error_internal_intr_r.error_mbox_ecc_unc_sts.hwset = sram_double_ecc_error;
-always_comb soc_ifc_reg_hwif_in.intr_block_rf.notif_internal_intr_r.notif_cmd_avail_sts.hwset    = uc_cmd_avail_p; // TODO confirm signal correctness
-always_comb soc_ifc_reg_hwif_in.intr_block_rf.notif_internal_intr_r.notif_mbox_ecc_cor_sts.hwset = sram_single_ecc_error;
-always_comb soc_ifc_reg_hwif_in.intr_block_rf.notif_internal_intr_r.notif_debug_locked_sts.hwset = security_state_debug_locked_p; // Any transition results in interrupt
-always_comb soc_ifc_reg_hwif_in.intr_block_rf.notif_internal_intr_r.notif_soc_req_lock_sts.hwset = soc_req_mbox_lock;
+always_comb soc_ifc_reg_hwif_in.intr_block_rf.error_internal_intr_r.error_internal_sts.hwset           = 1'b0; // TODO
+always_comb soc_ifc_reg_hwif_in.intr_block_rf.error_internal_intr_r.error_inv_dev_sts.hwset            = mbox_inv_user_p; // All invalid users, or only 'valid user but != mbox_user.user'?
+always_comb soc_ifc_reg_hwif_in.intr_block_rf.error_internal_intr_r.error_cmd_fail_sts.hwset           = |mbox_protocol_error; // Set by any protocol error violation (mirrors the bits in CPTRA_HW_ERROR_NON_FATAL)
+always_comb soc_ifc_reg_hwif_in.intr_block_rf.error_internal_intr_r.error_bad_fuse_sts.hwset           = 1'b0; // TODO
+always_comb soc_ifc_reg_hwif_in.intr_block_rf.error_internal_intr_r.error_iccm_blocked_sts.hwset       = iccm_axs_blocked;
+always_comb soc_ifc_reg_hwif_in.intr_block_rf.error_internal_intr_r.error_mbox_ecc_unc_sts.hwset       = sram_double_ecc_error;
+always_comb soc_ifc_reg_hwif_in.intr_block_rf.notif_internal_intr_r.notif_cmd_avail_sts.hwset          = uc_cmd_avail_p;
+always_comb soc_ifc_reg_hwif_in.intr_block_rf.notif_internal_intr_r.notif_mbox_ecc_cor_sts.hwset       = sram_single_ecc_error;
+always_comb soc_ifc_reg_hwif_in.intr_block_rf.notif_internal_intr_r.notif_debug_locked_sts.hwset       = security_state_debug_locked_p; // Any transition results in interrupt
+always_comb soc_ifc_reg_hwif_in.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts.hwset          = scan_mode_p; // Any transition results in interrupt
+always_comb soc_ifc_reg_hwif_in.intr_block_rf.notif_internal_intr_r.notif_soc_req_lock_sts.hwset       = soc_req_mbox_lock;
+always_comb soc_ifc_reg_hwif_in.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.hwset      = |generic_input_toggle;
 always_comb soc_ifc_reg_hwif_in.intr_block_rf.error_internal_intr_r.error_wdt_timer1_timeout_sts.hwset = t1_timeout_p;
 always_comb soc_ifc_reg_hwif_in.intr_block_rf.error_internal_intr_r.error_wdt_timer2_timeout_sts.hwset = t2_timeout_p && timer2_en;
 
@@ -607,7 +679,7 @@ logic s_cpuif_rd_ack_nc;
 logic s_cpuif_wr_ack_nc;
 
 soc_ifc_reg i_soc_ifc_reg (
-    .clk(soc_ifc_clk_cg),
+    .clk(rdc_clk_cg),
     .rst('0),
     //qualify request so no addresses alias
     .s_cpuif_req(soc_ifc_reg_req_dv & (soc_ifc_reg_req_data.addr[SOC_IFC_ADDR_W-1:SOC_IFC_REG_ADDR_WIDTH] == SOC_IFC_REG_START_ADDR[SOC_IFC_ADDR_W-1:SOC_IFC_REG_ADDR_WIDTH])),
@@ -645,12 +717,67 @@ assign nmi_vector = soc_ifc_reg_hwif_out.internal_nmi_vector.vec.value;
 assign iccm_lock  = soc_ifc_reg_hwif_out.internal_iccm_lock.lock.value;
 assign clk_gating_en = soc_ifc_reg_hwif_out.CPTRA_CLK_GATING_EN.clk_gating_en.value;
 assign nmi_intr = t2_timeout && !timer2_en;             //Only issue nmi if WDT timers are cascaded and t2 times out
-assign cptra_error_fatal = t2_timeout && !timer2_en;    //Only issue fatal error if WDT timers are cascaded and t2 times out
 
-// TODO
-assign cptra_error_non_fatal = 1'b0; // FIXME
+// Interrupt output is set, for any enabled conditions, when a new write
+// sets CPTRA_FW_ERROR_FATAL or when a HW condition occurs that sets a bit
+// in CPTRA_HW_ERROR_FATAL
+// Interrupt only deasserts on reset
+always_ff@(posedge rdc_clk_cg or negedge cptra_noncore_rst_b) begin
+    if(~cptra_noncore_rst_b) begin
+        cptra_error_fatal <= 1'b0;
+    end
+    // FW write that SETS a new (non-masked) bit results in interrupt assertion
+    else if (soc_ifc_reg_req_dv &&
+             soc_ifc_reg_hwif_out.CPTRA_FW_ERROR_FATAL.error_code.swmod &&
+             |(soc_ifc_reg_req_data.wdata & ~soc_ifc_reg_hwif_out.internal_fw_error_fatal_mask.mask.value & ~soc_ifc_reg_hwif_out.CPTRA_FW_ERROR_FATAL.error_code.value)) begin
+        cptra_error_fatal <= 1'b1;
+    end
+    // HW event that SETS a new (non-masked) bit results in interrupt assertion
+    else if (unmasked_hw_error_fatal_write) begin
+        cptra_error_fatal <= 1'b1;
+    end
+    // NOTE: There is no mechanism to clear interrupt assertion by design.
+    //       Platform MUST perform cptra_rst_b in order to clear cptra_error_fatal
+    //       output signal, per the integration spec.
+    else begin
+        cptra_error_fatal <= cptra_error_fatal;
+    end
+end
+always_ff@(posedge rdc_clk_cg or negedge cptra_noncore_rst_b) begin
+    if(~cptra_noncore_rst_b) begin
+        cptra_error_non_fatal <= 1'b0;
+    end
+    // FW write that SETS a new (non-masked) bit results in interrupt assertion
+    else if (soc_ifc_reg_req_dv &&
+             soc_ifc_reg_hwif_out.CPTRA_FW_ERROR_NON_FATAL.error_code.swmod &&
+             |(soc_ifc_reg_req_data.wdata & ~soc_ifc_reg_hwif_out.internal_fw_error_non_fatal_mask.mask.value  & ~soc_ifc_reg_hwif_out.CPTRA_FW_ERROR_NON_FATAL.error_code.value)) begin
+        cptra_error_non_fatal <= 1'b1;
+    end
+    // HW event that SETS a new (non-masked) bit results in interrupt assertion
+    else if (unmasked_hw_error_non_fatal_write) begin
+        cptra_error_non_fatal <= 1'b1;
+    end
+    // If FW performs a write that clears all outstanding (unmasked) ERROR_NON_FATAL events, deassert interrupt
+    else if (~unmasked_hw_error_non_fatal_is_set &&
+             ~|(~soc_ifc_reg_hwif_out.internal_fw_error_non_fatal_mask.mask.value & soc_ifc_reg_hwif_out.CPTRA_FW_ERROR_NON_FATAL.error_code.value)) begin
+        cptra_error_non_fatal <= 1'b0;
+    end
+    else begin
+        cptra_error_non_fatal <= cptra_error_non_fatal;
+    end
+end
+
 assign trng_req = soc_ifc_reg_hwif_out.CPTRA_TRNG_STATUS.DATA_REQ.value;
 
+// mtime always increments, but if it's being written by software the write
+// value will update the register. Deasserting incr in this case prevents the
+// SW write from being dropped (due to RDL compiler failing to give SW precedence properly).
+assign soc_ifc_reg_hwif_in.internal_rv_mtime_l.count_l.incr = !(soc_ifc_reg_req_dv && soc_ifc_reg_hwif_out.internal_rv_mtime_l.count_l.swmod);
+assign soc_ifc_reg_hwif_in.internal_rv_mtime_h.count_h.incr = !(soc_ifc_reg_req_dv && soc_ifc_reg_hwif_out.internal_rv_mtime_h.count_h.swmod) && soc_ifc_reg_hwif_out.internal_rv_mtime_l.count_l.overflow;
+assign timer_intr =  {soc_ifc_reg_hwif_out.internal_rv_mtime_h.count_h.value     ,soc_ifc_reg_hwif_out.internal_rv_mtime_l.count_l.value}
+                     >=
+                     {soc_ifc_reg_hwif_out.internal_rv_mtimecmp_h.compare_h.value,soc_ifc_reg_hwif_out.internal_rv_mtimecmp_l.compare_l.value};
+
 //SHA Accelerator
 sha512_acc_top #(
     .DATA_WIDTH(APB_DATA_WIDTH)
@@ -693,6 +820,7 @@ i_mbox (
     .req_data(mbox_req_data),
     .mbox_error(mbox_error),
     .rdata(mbox_rdata),
+    .dir_rdata(mbox_dir_rdata),
     .sha_sram_req_dv(sha_sram_req_dv),
     .sha_sram_req_addr(sha_sram_req_addr),
     .sha_sram_resp(sha_sram_resp),
@@ -704,6 +832,8 @@ i_mbox (
     .soc_mbox_data_avail(mailbox_data_avail),
     .uc_mbox_data_avail(uc_mbox_data_avail),
     .soc_req_mbox_lock(soc_req_mbox_lock),
+    .mbox_protocol_error(mbox_protocol_error),
+    .mbox_inv_pauser_axs(mbox_inv_user_p),
     .dmi_inc_rdptr(dmi_inc_rdptr),
     .dmi_reg(mbox_dmi_reg)
 );
@@ -728,8 +858,8 @@ always_comb begin
 end
 
 //Generate t1 and t2 timeout interrupt pulse
-always_ff @(posedge clk or negedge cptra_rst_b) begin
-    if(!cptra_rst_b) begin
+always_ff @(posedge rdc_clk_cg or negedge cptra_noncore_rst_b) begin
+    if(!cptra_noncore_rst_b) begin
         t1_timeout_f <= 'b0;
         t2_timeout_f <= 'b0;
     end
@@ -742,34 +872,28 @@ end
 always_comb t1_timeout_p = t1_timeout & ~t1_timeout_f;
 always_comb t2_timeout_p = t2_timeout & ~t2_timeout_f;
 
-//Detect falling edge on soc_ifc_error_intr to indicate that the interrupt has been serviced
-always_ff @(posedge clk or negedge cptra_rst_b) begin
-    if(!cptra_rst_b) begin
-        soc_ifc_error_intr_f <= 'b0;
+// NOTE: Since error_internal_intr_r is Write-1-to-clear, capture writes to the
+//       WDT interrupt bits to detect the interrupt being serviced.
+//       It would be preferable to decode this from interrupt signals somehow,
+//       but that would require modifying interrupt register RDL which has been
+//       standardized.
+always_ff @(posedge soc_ifc_clk_cg or negedge cptra_noncore_rst_b) begin
+    if(!cptra_noncore_rst_b) begin
+        wdt_error_t1_intr_serviced <= 1'b0;
+        wdt_error_t2_intr_serviced <= 1'b0;
+    end
+    else if (soc_ifc_reg_req_dv && soc_ifc_reg_req_data.write && (soc_ifc_reg_req_data.addr[SOC_IFC_REG_ADDR_WIDTH-1:0] == `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R)) begin
+        wdt_error_t1_intr_serviced <= soc_ifc_reg_req_data.wdata[`SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_LOW] && t1_timeout;
+        wdt_error_t2_intr_serviced <= soc_ifc_reg_req_data.wdata[`SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_LOW] && t2_timeout && timer2_en;
     end
     else begin
-        soc_ifc_error_intr_f <= soc_ifc_error_intr;
+        wdt_error_t1_intr_serviced <= 1'b0;
+        wdt_error_t2_intr_serviced <= 1'b0;
     end
 end
-assign wdt_error_t1_intr_serviced = !soc_ifc_error_intr && soc_ifc_error_intr_f && t1_timeout;
-assign wdt_error_t2_intr_serviced = !soc_ifc_error_intr && soc_ifc_error_intr_f && t2_timeout && timer2_en;
-
-//Set HW FATAL ERROR reg when timer2 times out in cascaded mode
-always_comb soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.error_code.we = cptra_error_fatal;
-always_comb soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.error_code.next = {31'b0, cptra_error_fatal}; //bit 0 will indicate if timer2 has timed out
-
-//TIE-OFFS
-always_comb begin
-    soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_NON_FATAL.error_code.we = 'b0;
-    soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_NON_FATAL.error_code.next = 'h0;
-    soc_ifc_reg_hwif_in.CPTRA_FW_ERROR_FATAL.error_code.we = 'b0;
-    soc_ifc_reg_hwif_in.CPTRA_FW_ERROR_FATAL.error_code.next = 'h0;
-    soc_ifc_reg_hwif_in.CPTRA_FW_ERROR_NON_FATAL.error_code.we = 'b0;
-    soc_ifc_reg_hwif_in.CPTRA_FW_ERROR_NON_FATAL.error_code.next = 'h0;
-end
 
 wdt i_wdt (
-    .clk(clk),
+    .clk(rdc_clk_cg),
     .cptra_rst_b(cptra_noncore_rst_b),
     .timer1_en(timer1_en),
     .timer2_en(timer2_en),
@@ -782,6 +906,48 @@ wdt i_wdt (
     .t1_timeout(t1_timeout),
     .t2_timeout(t2_timeout)
 );
+
+////////////////////////////////////////////////////////
+// Write-enables for CPTRA_HW_ERROR_FATAL and CPTRA_HW_ERROR_NON_FATAL
+// Also calculate whether or not an unmasked event is being set, so we can
+// trigger the SOC interrupt signal
+always_comb soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.we = rv_ecc_sts.cptra_iccm_ecc_double_error & ~fw_update_rst_window;
+always_comb soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.we = rv_ecc_sts.cptra_dccm_ecc_double_error & ~fw_update_rst_window;
+always_comb soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.nmi_pin     .we = nmi_intr;
+// Using we+next instead of hwset allows us to encode the reserved fields in some fashion
+// other than bit-hot in the future, if needed (e.g. we need to encode > 32 FATAL events)
+always_comb soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.next = 1'b1;
+always_comb soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.next = 1'b1;
+always_comb soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.nmi_pin     .next = 1'b1;
+// Flag the write even if the field being written to is already set to 1 - this is a new occurrence of the error and should trigger a new interrupt
+always_comb unmasked_hw_error_fatal_write = (soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.we && ~soc_ifc_reg_hwif_out.internal_hw_error_fatal_mask.mask_iccm_ecc_unc.value && |soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.next) ||
+                                            (soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.we && ~soc_ifc_reg_hwif_out.internal_hw_error_fatal_mask.mask_dccm_ecc_unc.value && |soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.next) ||
+                                            (soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.nmi_pin     .we && ~soc_ifc_reg_hwif_out.internal_hw_error_fatal_mask.mask_nmi_pin     .value && |soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.nmi_pin     .next);
+
+always_comb soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.we = mbox_protocol_error.axs_without_lock;
+always_comb soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo    .we = mbox_protocol_error.axs_incorrect_order;
+always_comb soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc     .we = sram_double_ecc_error;
+// Using we+next instead of hwset allows us to encode the reserved fields in some fashion
+// other than bit-hot in the future, if needed (e.g. we need to encode > 32 NON-FATAL events)
+always_comb soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.next = 1'b1;
+always_comb soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo    .next = 1'b1;
+always_comb soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc     .next = 1'b1;
+// Flag the write even if the field being written to is already set to 1 - this is a new occurrence of the error and should trigger a new interrupt
+always_comb unmasked_hw_error_non_fatal_write = (soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.we && ~soc_ifc_reg_hwif_out.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock.value && |soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.next) ||
+                                                (soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo    .we && ~soc_ifc_reg_hwif_out.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo    .value && |soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo    .next) ||
+                                                (soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc     .we && ~soc_ifc_reg_hwif_out.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc     .value && |soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc     .next);
+always_comb unmasked_hw_error_non_fatal_is_set = (soc_ifc_reg_hwif_out.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.value && ~soc_ifc_reg_hwif_out.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock.value) ||
+                                                 (soc_ifc_reg_hwif_out.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo    .value && ~soc_ifc_reg_hwif_out.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo    .value) ||
+                                                 (soc_ifc_reg_hwif_out.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc     .value && ~soc_ifc_reg_hwif_out.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc     .value);
+
+//TIE-OFFS
+always_comb begin
+    soc_ifc_reg_hwif_in.CPTRA_FW_ERROR_FATAL.error_code.we = 'b0;
+    soc_ifc_reg_hwif_in.CPTRA_FW_ERROR_FATAL.error_code.next = 'h0;
+    soc_ifc_reg_hwif_in.CPTRA_FW_ERROR_NON_FATAL.error_code.we = 'b0;
+    soc_ifc_reg_hwif_in.CPTRA_FW_ERROR_NON_FATAL.error_code.next = 'h0;
+end
+
 //DMI register writes
 always_comb soc_ifc_reg_hwif_in.CPTRA_BOOTFSM_GO.GO.we = cptra_uncore_dmi_reg_wr_en & cptra_uncore_dmi_reg_en & 
                                                          (cptra_uncore_dmi_reg_addr == DMI_REG_BOOTFSM_GO);
@@ -804,7 +970,7 @@ always_comb cptra_uncore_dmi_reg_rdata_in = ({32{(cptra_uncore_dmi_reg_addr == D
 //This assumes that reg_en goes low between read accesses
 always_comb dmi_inc_rdptr = cptra_uncore_dmi_reg_dout_access_f & ~cptra_uncore_dmi_reg_en;
 
-always_ff @(posedge clk or negedge cptra_pwrgood) begin
+always_ff @(posedge rdc_clk_cg or negedge cptra_pwrgood) begin
     if (~cptra_pwrgood) begin
         cptra_uncore_dmi_reg_rdata <= '0;
         cptra_uncore_dmi_reg_dout_access_f <= '0;
@@ -815,7 +981,7 @@ always_ff @(posedge clk or negedge cptra_pwrgood) begin
     end
 end
 
-`CALIPTRA_ASSERT_KNOWN(ERR_AHB_INF_X, {hreadyout_o,hresp_o}, soc_ifc_clk_cg, cptra_rst_b)
+`CALIPTRA_ASSERT_KNOWN(ERR_AHB_INF_X, {hreadyout_o,hresp_o}, clk, cptra_noncore_rst_b)
 //this generates an NMI in the core, but we don't have a handler so it just hangs
-`CALIPTRA_ASSERT_NEVER(ERR_SOC_IFC_AHB_ERR, hresp_o, soc_ifc_clk_cg, cptra_rst_b)
+`CALIPTRA_ASSERT_NEVER(ERR_SOC_IFC_AHB_ERR, hresp_o, clk, cptra_noncore_rst_b)
 endmodule
diff --git a/src/soc_ifc/stimulus/tests/directed/fuse_reg_pauser_test.yml b/src/soc_ifc/stimulus/tests/directed/fuse_reg_pauser_test.yml
new file mode 100644
index 000000000..9b06b5312
--- /dev/null
+++ b/src/soc_ifc/stimulus/tests/directed/fuse_reg_pauser_test.yml
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+---
+plusargs:
+  - +SOC_IFC_TEST='fuse_reg_pauser_test'
+
+testname: fuse_reg_pauser_test 
+seed: ${PLAYBOOK_RANDOM_SEED}
diff --git a/src/soc_ifc/stimulus/tests/directed/fuse_reg_perm_test.yml b/src/soc_ifc/stimulus/tests/directed/fuse_reg_perm_test.yml
index 768ed209f..014e9b8eb 100644
--- a/src/soc_ifc/stimulus/tests/directed/fuse_reg_perm_test.yml
+++ b/src/soc_ifc/stimulus/tests/directed/fuse_reg_perm_test.yml
@@ -17,4 +17,5 @@ plusargs:
   - +SOC_IFC_TEST='fuse_reg_perm_test'
 
 testname: fuse_reg_perm_test 
-seed: ${PLAYBOOK_RANDOM_SEED}
+# seed: ${PLAYBOOK_RANDOM_SEED}
+seed: 1692834441
diff --git a/src/soc_ifc/stimulus/tests/directed/rvtime_reg_test.yml b/src/soc_ifc/stimulus/tests/directed/rvtime_reg_test.yml
new file mode 100644
index 000000000..e9729ee2d
--- /dev/null
+++ b/src/soc_ifc/stimulus/tests/directed/rvtime_reg_test.yml
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+---
+plusargs:
+  - +SOC_IFC_TEST='rvtime_reg_test'
+
+testname: rvtime_reg_test
+seed: ${PLAYBOOK_RANDOM_SEED}
diff --git a/src/soc_ifc/stimulus/tests/directed/sha_acc_intrblk_test.yml b/src/soc_ifc/stimulus/tests/directed/sha_acc_intrblk_test.yml
new file mode 100644
index 000000000..44349ce5b
--- /dev/null
+++ b/src/soc_ifc/stimulus/tests/directed/sha_acc_intrblk_test.yml
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+---
+plusargs:
+  - +SOC_IFC_TEST='sha_acc_intrblk_test'
+
+testname: sha_acc_intrblk_test
+seed: ${PLAYBOOK_RANDOM_SEED}
diff --git a/src/soc_ifc/stimulus/tests/directed/single_socreg_test.yml b/src/soc_ifc/stimulus/tests/directed/single_socreg_test.yml
index c5606f968..d5c2b18d4 100644
--- a/src/soc_ifc/stimulus/tests/directed/single_socreg_test.yml
+++ b/src/soc_ifc/stimulus/tests/directed/single_socreg_test.yml
@@ -15,7 +15,10 @@
 ---
 plusargs:
   - +SOC_IFC_TEST='single_socreg_test'
-  - +SOCREG_METHOD_NAME='APB.CPTRA_TIMER_CONFIG'
+  # - +SOCREG_METHOD_NAME='APB.CPTRA_TIMER_CONFIG'
+  - +SOCREG_METHOD_NAME='AHB.INTR_BRF_NOTIF_INTERNAL_INTR_R'
+  - +SOCREG_WRCOUNT=20
 
 testname: single_socreg_test
-seed: ${PLAYBOOK_RANDOM_SEED}
+# seed: ${PLAYBOOK_RANDOM_SEED}
+seed: 1687838882
diff --git a/src/soc_ifc/stimulus/tests/directed/soc_reg_intrblk_test.yml b/src/soc_ifc/stimulus/tests/directed/soc_reg_intrblk_test.yml
new file mode 100644
index 000000000..a77dad5af
--- /dev/null
+++ b/src/soc_ifc/stimulus/tests/directed/soc_reg_intrblk_test.yml
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+---
+plusargs:
+  - +SOC_IFC_TEST='soc_reg_intrblk_test'
+
+testname: soc_reg_intrblk_test
+seed: ${PLAYBOOK_RANDOM_SEED}
+# seed: 1692153169 
diff --git a/src/soc_ifc/stimulus/tests/directed/soc_reg_test.yml b/src/soc_ifc/stimulus/tests/directed/soc_reg_test.yml
index bde3dabd0..3207db555 100644
--- a/src/soc_ifc/stimulus/tests/directed/soc_reg_test.yml
+++ b/src/soc_ifc/stimulus/tests/directed/soc_reg_test.yml
@@ -17,7 +17,6 @@ plusargs:
   - +SOC_IFC_TEST='soc_reg_test'
 
 testname: soc_reg_test
-seed: 1680126531
-# seed: ${PLAYBOOK_RANDOM_SEED}
-# seed: 1679445419 
-# seed: 1680126531
+seed: ${PLAYBOOK_RANDOM_SEED}
+#seed: 1680126531
+
diff --git a/src/soc_ifc/stimulus/testsuites/soc_ifc_commit_regress.yml b/src/soc_ifc/stimulus/testsuites/soc_ifc_commit_regress.yml
new file mode 100644
index 000000000..292d387ba
--- /dev/null
+++ b/src/soc_ifc/stimulus/testsuites/soc_ifc_commit_regress.yml
@@ -0,0 +1,20 @@
+document:
+  schema: 1.0
+
+contents:
+  - tests:
+      tags: ["L0", "directed", "SOC_IFC"]
+      paths:
+        - ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/soc_ifc_test.yml 
+        - ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/fuse_reg_pauser_test.yml
+        - ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/fuse_reg_prod_test.yml 
+        - ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/fuse_reg_perm_test.yml
+        - ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/fuse_reg_lifecycle_test.yml
+        - ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/soc_reg_test.yml
+        - ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/single_socreg_test.yml
+        - ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/soc_reg_pwron_test.yml
+        - ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/soc_reg_wrmrst_test.yml
+        - ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/soc_reg_invalid_test.yml
+        - ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/soc_reg_intrblk_test.yml
+        - ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/sha_acc_intrblk_test.yml
+        - ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/rvtime_reg_test.yml
diff --git a/src/soc_ifc/stimulus/testsuites/soc_ifc_nightly_directed_regression.yml b/src/soc_ifc/stimulus/testsuites/soc_ifc_nightly_directed_regression.yml
index f3b4789fa..430c2d8a2 100644
--- a/src/soc_ifc/stimulus/testsuites/soc_ifc_nightly_directed_regression.yml
+++ b/src/soc_ifc/stimulus/testsuites/soc_ifc_nightly_directed_regression.yml
@@ -2,14 +2,24 @@ document:
   schema: 1.0
 
 contents:
-  - tests:
+  - generator:
       tags: ["L0", "directed", "nightly", "SOC_IFC"]
-      paths:
-        - ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/soc_ifc_test.yml 
-        - ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/fuse_reg_prod_test.yml 
-        - ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/fuse_reg_perm_test.yml
-        - ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/fuse_reg_lifecycle_test.yml
-        - ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/soc_reg_test.yml
-        - ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/soc_reg_pwron_test.yml
-        - ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/soc_reg_wrmrst_test.yml
-        - ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/soc_reg_invalid_test.yml
+      path: ""
+      weight: 100 
+      generations: 100 
+      formats: 
+        generate: "reseed {template}.yml -seed {seed}"
+        path: "{template_basename}__{seed}.yml"
+      templates:        
+        ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/soc_ifc_test : {weight 12}
+        ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/fuse_reg_pauser_test : {weight 3}
+        ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/fuse_reg_prod_test : {weight 12}
+        ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/fuse_reg_perm_test: {weight 12}
+        ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/fuse_reg_lifecycle_test: {weight 6}
+        ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/soc_reg_test: {weight 16}
+        ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/soc_reg_pwron_test: {weight 12}
+        ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/soc_reg_wrmrst_test: {weight 12}
+        ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/soc_reg_invalid_test: {weight 6}
+        ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/rvtime_reg_test: {weight 3}
+        ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/sha_acc_intrblk_test: {weight 3}
+        ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/soc_reg_intrblk_test: {weight 3}
diff --git a/src/soc_ifc/stimulus/testsuites/soc_ifc_nightly_random_regression.yml b/src/soc_ifc/stimulus/testsuites/soc_ifc_nightly_random_regression.yml
index e875f32d0..2ab056642 100644
--- a/src/soc_ifc/stimulus/testsuites/soc_ifc_nightly_random_regression.yml
+++ b/src/soc_ifc/stimulus/testsuites/soc_ifc_nightly_random_regression.yml
@@ -5,11 +5,15 @@ contents:
   - generator:
       tags: ["L1", "SOC_IFC",  "random"]
       path: ""
+      config:
+        params:
+          # 12 hours to accommodate certain longer-running tests
+          timeout: 720
       weight: 100
-      generations: 100
+      generations: 500
       formats: 
         generate: "reseed {template}.yml -seed {seed}"
         path: "{template_basename}__{seed}.yml"
       templates:
-        $CALIPTRA_ROOT/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/tests/src/soc_ifc_rand_test   : { weight 75 }
-        $CALIPTRA_ROOT/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/tests/src/soc_ifc_trng_test   : { weight 25 }
+        $CALIPTRA_ROOT/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/tests/src/soc_ifc_rand_test   : { weight 95 }
+        $CALIPTRA_ROOT/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/tests/src/soc_ifc_trng_test   : { weight  5 }
diff --git a/src/soc_ifc/stimulus/testsuites/uvmf_soc_ifc_promote_regression.yml b/src/soc_ifc/stimulus/testsuites/uvmf_soc_ifc_promote_regression.yml
new file mode 100644
index 000000000..b49a59d56
--- /dev/null
+++ b/src/soc_ifc/stimulus/testsuites/uvmf_soc_ifc_promote_regression.yml
@@ -0,0 +1,15 @@
+document:
+  schema: 1.0
+
+contents:
+  - generator:
+      tags: ["L0", "SOC_IFC",  "directed", "smoke_test"]
+      path: ""
+      weight: 100
+      generations: 6
+      formats: 
+        generate: "reseed {template}.yml -seed {seed}"
+        path: "{template_basename}__{seed}.yml"
+      templates:
+        $CALIPTRA_ROOT/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/tests/src/soc_ifc_cmdline_test   : { weight 100 }
+        $CALIPTRA_ROOT/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/tests/src/soc_ifc_rand_test      : { weight 500 }
diff --git a/src/soc_ifc/tb/fuse_reg_pauser_test.svh b/src/soc_ifc/tb/fuse_reg_pauser_test.svh
new file mode 100644
index 000000000..6a8a979fa
--- /dev/null
+++ b/src/soc_ifc/tb/fuse_reg_pauser_test.svh
@@ -0,0 +1,342 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//======================================================================
+
+
+
+// Declarations for internal signal probing  
+logic [31:0] fuse_uds_seed [0:11]; 
+logic [31:0] fuse_field_entropy [0:7]; 
+logic [31:0] fuse_key_manifest_pk_hash [0:11]; 
+logic [3:0]  fuse_key_manifest_pk_hash_mask; 
+logic [31:0] fuse_owner_pk_hash [0:11]; 
+logic [31:0] fuse_fmc_key_manifest_svn; 
+logic [31:0] fuse_runtime_svn [0:3]; 
+logic        fuse_anti_rollback_disable; 
+logic [31:0] fuse_idevid_cert_attr [0:23]; 
+logic [31:0] fuse_idevid_manuf_hsm_id [0:3]; 
+logic [1:0]  fuse_life_cycle ; 
+logic        fuse_lms_verify ; 
+logic [31:0] fuse_lms_revocation; 
+
+
+`FORLOOP_COMB( 12 ) fuse_uds_seed[j]                  = `REG_HIER_PFX.fuse_uds_seed[j].seed.value;
+`FORLOOP_COMB( 8 )  fuse_field_entropy[j]             = `REG_HIER_PFX.fuse_field_entropy[j].seed.value;
+`FORLOOP_COMB( 12 ) fuse_key_manifest_pk_hash[j]      = `REG_HIER_PFX.fuse_key_manifest_pk_hash[j].hash.value;
+  always_comb       fuse_key_manifest_pk_hash_mask    = `REG_HIER_PFX.fuse_key_manifest_pk_hash_mask.mask.value;
+`FORLOOP_COMB( 12 ) fuse_owner_pk_hash[j]             = `REG_HIER_PFX.fuse_owner_pk_hash[j].hash.value;
+  always_comb       fuse_fmc_key_manifest_svn         = `REG_HIER_PFX.fuse_fmc_key_manifest_svn.svn.value;
+`FORLOOP_COMB( 4 )  fuse_runtime_svn[j]               = `REG_HIER_PFX.fuse_runtime_svn[j].svn.value;
+  always_comb       fuse_anti_rollback_disable        = `REG_HIER_PFX.fuse_anti_rollback_disable.dis.value;
+`FORLOOP_COMB( 24 ) fuse_idevid_cert_attr[j]          = `REG_HIER_PFX.fuse_idevid_cert_attr[j].cert.value;
+`FORLOOP_COMB( 4 )  fuse_idevid_manuf_hsm_id[j]       = `REG_HIER_PFX.fuse_idevid_manuf_hsm_id[j].hsm_id.value;
+  always_comb       fuse_life_cycle                   = `REG_HIER_PFX.fuse_life_cycle.life_cycle.value;
+  always_comb       fuse_lms_verify                   = `REG_HIER_PFX.fuse_lms_verify.lms_verify.value;
+  always_comb       fuse_lms_revocation               = `REG_HIER_PFX.fuse_lms_revocation.lms_revocation.value;
+
+
+//----------------------------------------------------------------
+// fuse_reg_pauser_test()
+// 
+// Checks fuse permission tests depending on PAUSER bit status 
+//----------------------------------------------------------------
+task fuse_reg_pauser_test;
+  // Fuse Register PA-USER Test 
+
+  automatic word_addr_t addr; 
+  automatic int tid = 0; // optional to increment UNLESS multiple writes to same address 
+  automatic strq_t fuse_regnames;  // ordered list of fuse register names
+  automatic dwordq_t fuse_regdata;  // corresponding data to fuse register names
+  automatic dword_t valid_pauser;  
+  automatic logic lock_status;
+  automatic WordTransaction wrtrans, rdtrans;
+  automatic string rname;
+  automatic dword_t fuse_regval_actual;  
+
+  begin
+    $display("Executing task fuse_reg_pauser_test"); 
+    $display("-----------------------------------\n");
+
+    $display("Current security state = 0b%03b", security_state);
+    tc_ctr = tc_ctr + 1;
+
+    wrtrans = new();
+    rdtrans = new();
+
+    fuse_regnames = get_fuse_regnames(); 
+
+    init_sim();
+    reset_dut();
+
+    wait (ready_for_fuses); 
+
+    //------------------------------------------------------------------------------------------- 
+    print_banner("1a. Default pauser and unlocked. APB write to registers, check values");
+    tphase = "1a";
+
+    write_regs(SET_APB, fuse_regnames, tid, 3);  // effect changes & 
+    repeat (5) @(posedge clk_tb);
+    read_regs(GET_APB, fuse_regnames, tid, 3);  // expect same values on read
+
+    //------------------------------------------------------------------------------------------- 
+    print_banner("1b. With unlocked non-default pauser, repeat 1a");
+    tphase = "1b";
+
+    // NOTE. simulate_caliptra_boot() is necessary for noncore_rst_b to be deasserted
+    //simulate_caliptra_boot();
+    //wait (cptra_noncore_rst_b_tb == 1'b1);
+
+    // Set pauser valid to non-default
+    wrtrans.update_byname("CPTRA_FUSE_VALID_PAUSER", 0, tid); 
+    wrtrans.randomize();
+    valid_pauser = wrtrans.data;
+    write_reg_trans(SET_APB, wrtrans);
+    repeat (3) @(posedge clk_tb);
+    rdtrans.update_byname("CPTRA_FUSE_VALID_PAUSER", 0, tid); 
+    read_reg_trans(GET_APB, rdtrans);
+    $display ("Pauser value programmed = 0x%08x", rdtrans.data); 
+    assert (rdtrans.data == valid_pauser) else begin
+      $display("TB ERROR. fuse_pauser_valid modfication failed"); 
+      error_ctr += 1;
+    end 
+
+    write_regs(SET_APB, fuse_regnames, tid, 3);  // effect changes & 
+    repeat (5) @(posedge clk_tb);
+    read_regs(GET_APB, fuse_regnames, tid, 3);  // expect same values on read
+
+    //------------------------------------------------------------------------------------------- 
+    print_banner("1c. Lock pauser with non-default value. repeat 1a but read with and w/o valid pauser"); 
+    tphase = "1c";
+
+    set_fuse_pauser_lock(1'b1, tid, lock_status);
+    if (lock_status == 1'b0) begin
+      $display("TB ERROR. Setting fuse_pauser_lock failed!"); 
+      error_ctr += 1;
+    end
+
+    $display ("TB INFO. Storing last modified fuse register values with valid pauser writes"); 
+    foreach (fuse_regnames[i]) begin   // store last-modified values
+      rname = fuse_regnames[i];
+      fuse_regval_actual = get_fuse_regval(rname);
+      fuse_regdata.push_back(fuse_regval_actual);
+      $display ("TB INFO. For %-30s storing last modified value 0x%08x", rname, fuse_regval_actual);
+    end 
+
+    write_regs(SET_APB, fuse_regnames, tid, 3);  // should be ineffectual 
+    repeat (5) @(posedge clk_tb);
+
+    // Read twice, with and without valid pauser
+    foreach (fuse_regnames[i]) begin
+      rname = fuse_regnames[i];
+      rdtrans.update_byname(rname,  0, tid); 
+      fuse_regval_actual = get_fuse_regval(rname);
+      read_reg_chk_inrange(GET_APB, rname, tid, '0, '0);  // get 0's on default pauser
+      repeat (3) @(posedge clk_tb);
+      read_reg_trans(GET_APB, rdtrans, valid_pauser); // expect older (stored) values
+      repeat (3) @(posedge clk_tb);
+
+      if (str_startswith(rname, "FUSE_UDS_SEED") || str_startswith(rname, "FUSE_FIELD_ENTROPY")) 
+        assert (rdtrans.data == '0) else error_ctr += 1;
+        continue;
+
+      if (rdtrans.data != fuse_regval_actual) begin
+        $display("TB ERROR. Mismatch on APB read w/valid pauser for reg %-30s (0x%08x). Read value = 0x%08x | expected probed = 0x%08x", 
+          rname, rdtrans.addr, rdtrans.data, fuse_regval_actual) ;
+        error_ctr += 1;
+      end
+      @(posedge clk_tb);
+    end
+
+
+    //------------------------------------------------------------------------------------------- 
+    print_banner("1d. With matching locked non-default pauser, repeat 1a"); 
+    tphase = "1d";
+
+    // Programming a non-default valid_pauser and locking it requires waiting for cptra_noncore_rst_b 
+    // to be deasserted after a reset, ie, Caliptra boot. 
+    //  
+    // At the same time ready_for_fuses drops low followed by cptra_noncore_rst_b goingh high, ergo 
+    // writes to fuse regs no longer work (for any pauser value) until a warm reset occurs. 
+    // HOWEVER, a warm reset also resets the valid_pauser register. 
+    // 
+    // The net result (a bug) is that fuse registers can ONLY be written using a default pauser value; 
+    // fuse registers can be read out though using any programmed and locked valid_pauser.  
+   
+    sb.del_all();  
+
+    foreach (fuse_regnames[i]) begin
+      rname = fuse_regnames[i];
+      wrtrans.update_byname(rname, 0, tid);
+      wrtrans.randomize();
+      rdtrans.update_byname(rname, 0, tid);
+
+      write_reg_trans(SET_APB, wrtrans, valid_pauser); 
+      @(posedge clk_tb);
+      read_reg_trans(GET_APB, rdtrans, valid_pauser); 
+      repeat (3) @(posedge clk_tb);
+
+      if (str_startswith(rname, "FUSE_UDS_SEED") || str_startswith(rname, "FUSE_FIELD_ENTROPY")) 
+        continue;
+
+      if (rdtrans.data != (get_mask(rname) & wrtrans.data)) begin
+        $display("TB ERROR. Mismatch on APB write and read w/valid pauser for reg %-30s (0x%08x). Read value = 0x%08x | expected value = 0x%08x", 
+          rname, rdtrans.addr, rdtrans.data, get_mask(rname) & wrtrans.data); 
+        error_ctr += 1;
+      end
+
+      repeat (3) @(posedge clk_tb);
+    end 
+
+
+    //------------------------------------------------------------------------------------------- 
+    print_banner("2a. for completeness try to unlock pauser by writing"); 
+    tphase = "2a";
+
+    set_fuse_pauser_lock(1'b0, tid, lock_status);
+    assert (lock_status == 1'b1) else begin
+      $display("TB ERROR. Resetting of fuse_pauser_lock via APB was allowed!"); 
+      error_ctr += 1;
+    end
+
+
+    //------------------------------------------------------------------------------------------- 
+    print_banner("2b. then attempt to unlock pauser by warm reseting"); 
+    tphase = "2b";
+
+    warm_reset_dut(); 
+    warm_reset_exp_data();
+    sb.del_all();
+
+    simulate_caliptra_boot();
+    wait (cptra_noncore_rst_b_tb == 1'b1);
+
+    // if (cptra_noncore_rst_b_tb == 1'b0) begin
+    //   $display("TB. WARNING Non core reset is not deasserted. Waiting 1000 cycles");
+    //   repeat (1000) @(posedge clk_tb);
+    //   $display("TB. DEBUG if status of cptra_noncore_rst_b_tb = 1'b%b", cptra_noncore_rst_b_tb); 
+    // end
+
+    read_reg_chk_inrange(GET_APB, "CPTRA_FUSE_PAUSER_LOCK", tid, 'd1, 'd1); 
+    @(posedge clk_tb);
+
+
+    //------------------------------------------------------------------------------------------- 
+    print_banner("2c. finally unlock pauser by cold reseting"); 
+    tphase = "2c";
+
+    reset_dut(); // expect to be clearing CPTRA_FUSE_WR_DONE effect 
+    reset_exp_data();
+    // simulate_caliptra_boot();
+    sb.del_all();
+
+    simulate_caliptra_boot();
+    wait (cptra_noncore_rst_b_tb == 1'b1);
+
+    // if (cptra_noncore_rst_b_tb == 1'b0) begin
+    //   $display("TB. WARNING Non core reset is not deasserted. Waiting 1000 cycles");
+    //   repeat (1000) @(posedge clk_tb);
+    //   $display("TB. DEBUG if status of cptra_noncore_rst_b_tb = 1'b%b", cptra_noncore_rst_b_tb); 
+    // end
+
+    read_reg_chk_inrange(GET_APB, "CPTRA_FUSE_PAUSER_LOCK", tid, '0, '0); 
+    @(posedge clk_tb);
+
+
+    error_ctr += sb.err_count;
+
+  end
+
+endtask // fuse_reg_pauser_test
+
+
+
+//----------------------------------------------------------------
+// function get_fuse_regval()
+//
+// Probes to get the intenral fuse register value inside dut 
+//----------------------------------------------------------------
+function dword_t get_fuse_regval(string rname);
+
+  automatic dword_t regval; 
+  string pfx = "unknown";
+  automatic int j; 
+
+  strq_t prefixes = {"FUSE_UDS_SEED", "FUSE_FIELD_ENTROPY", "FUSE_KEY_MANIFEST_PK_HASH",  
+   "FUSE_OWNER_PK_HASH", "FUSE_RUNTIME_SVN", "FUSE_IDEVID_CERT_ATTR", "FUSE_IDEVID_MANUF_HSM_ID"}; 
+
+  begin
+    case (rname) 
+      "FUSE_KEY_MANIFEST_PK_HASH_MASK"      :  regval = fuse_key_manifest_pk_hash_mask; 
+      "FUSE_FMC_KEY_MANIFEST_SVN"           :  regval = fuse_fmc_key_manifest_svn; 
+      "FUSE_ANTI_ROLLBACK_DISABLE"          :  regval = fuse_anti_rollback_disable; 
+      "FUSE_LIFE_CYCLE"                     :  regval = fuse_life_cycle ; 
+      "FUSE_LMS_VERIFY"                     :  regval = fuse_lms_verify ; 
+      "FUSE_LMS_REVOCATION"                 :  regval = fuse_lms_revocation; 
+
+      default: begin
+        foreach (prefixes[i]) begin
+          if (str_startswith(rname, prefixes[i])) begin
+            pfx = prefixes[i];
+            break;
+          end
+        end
+
+        if (pfx == "unknown") begin 
+          $display ("TB ERROR. Unknown prefix in fuse register name %s", rname);
+          error_ctr += 1;
+        end else begin
+          j = `STR_RMPFX(rname, pfx);
+          // $display ("prefix = %s, j = %d", pfx, j);
+          regval =  (pfx == "FUSE_UDS_SEED"            ) ? fuse_uds_seed[j]:
+                    (pfx == "FUSE_FIELD_ENTROPY"       ) ? fuse_field_entropy[j] :
+                    (pfx == "FUSE_KEY_MANIFEST_PK_HASH") ? fuse_key_manifest_pk_hash[j] :
+                    (pfx == "FUSE_OWNER_PK_HASH"       ) ? fuse_owner_pk_hash[j] :
+                    (pfx == "FUSE_RUNTIME_SVN"         ) ? fuse_runtime_svn[j] :
+                    (pfx == "FUSE_IDEVID_CERT_ATTR"    ) ? fuse_idevid_cert_attr[j] :
+                    (pfx == "FUSE_IDEVID_MANUF_HSM_ID" ) ? fuse_idevid_manuf_hsm_id[j] : 'x;
+        end
+      end
+
+    endcase
+
+    return regval;
+  end
+
+endfunction // get_fuse_regval
+
+
+//----------------------------------------------------------------
+// task set_fuse_pauser_lock()
+//
+// Sets fuse pauser lock register & checks value
+//----------------------------------------------------------------
+task set_fuse_pauser_lock(input logic lock_value, input int tid, output logic lock_status); 
+
+  automatic WordTransaction wrtrans, rdtrans;
+  begin
+    wrtrans = new();
+    rdtrans = new();
+
+    wrtrans.update_byname("CPTRA_FUSE_PAUSER_LOCK", lock_value, tid); 
+    write_reg_trans(SET_APB, wrtrans);
+    repeat (3) @(posedge clk_tb);
+    rdtrans.update_byname("CPTRA_FUSE_PAUSER_LOCK", 0, tid); 
+    read_reg_trans(GET_APB, rdtrans); // FIXME.
+    $display ("Pauser lock status = 0x%08x", rdtrans.data); 
+
+    lock_status = rdtrans.data[0];
+  end
+endtask // set_fuse_pauser_lock
+
diff --git a/src/soc_ifc/tb/fuse_reg_perm_test.svh b/src/soc_ifc/tb/fuse_reg_perm_test.svh
index 6a0728c43..88b60898b 100644
--- a/src/soc_ifc/tb/fuse_reg_perm_test.svh
+++ b/src/soc_ifc/tb/fuse_reg_perm_test.svh
@@ -17,6 +17,8 @@
 
 //----------------------------------------------------------------
 // fuse_reg_perm_test()
+// 
+// Checks fuse permission tests depending on lock status from FUSE_WR_DONE
 //----------------------------------------------------------------
 task fuse_reg_perm_test;
   // Fuse Register Test 
@@ -50,11 +52,13 @@ any subsequent writes to a fuse register will be dropped unless
 
     init_sim();
     reset_dut();
+    wait(ready_for_fuses);
 
     // -----------------------------------------------------------------
     // PHASE 1. Normal sequence 
     // -----------------------------------------------------------------
     $display ("1a. APB write twice to registers, lock fuses and attempt to modify\n");
+    tphase = "1a";
 
     write_regs(SET_APB, fuse_regnames, 0, 3);  // effect changes
     repeat (5) @(posedge clk_tb);
@@ -72,6 +76,7 @@ any subsequent writes to a fuse register will be dropped unless
     repeat (5) @(posedge clk_tb);
 
     $display ("\n1b. Following writes should have no effect on locked state -- which is still set!\n");
+    tphase = "1b";
 
     sb.del_all();
 
@@ -86,11 +91,14 @@ any subsequent writes to a fuse register will be dropped unless
     // -----------------------------------------------------------------
     // PHASE 2. Perform Cold Reset and Repeat APB Write & Read from 1a  
     // -----------------------------------------------------------------
+    $display ("\n2a. Write to registers after cold boot and check back writes");
+    tphase = "2a";
+
     reset_dut(); // expect to be clearing CPTRA_FUSE_WR_DONE effect 
     reset_exp_data();
     sb.del_all();
-
-    $display ("\n2a. Write to registers after cold boot and check back writes");
+    wait(ready_for_fuses);
+    @(posedge clk_tb);
 
     write_regs(SET_APB, fuse_regnames, 0, 3);
     read_regs(GET_APB, fuse_regnames, 0, 3);
@@ -105,9 +113,12 @@ any subsequent writes to a fuse register will be dropped unless
     // PHASE 3. Perform Warm Reset, read values & Repeat APB Write & Read from 1a  
     // -----------------------------------------------------------------
     $display ("\n3a. Perform a warm reset then repeat steps 1a (just APB)"); 
+    tphase = "3a";
 
     warm_reset_dut(); 
     warm_reset_exp_data();
+    wait(ready_for_fuses);
+    @(posedge clk_tb);
 
     read_regs(GET_APB, fuse_regnames, 0, 3);      // should be old sticky values
     sb.del_all();
diff --git a/src/soc_ifc/tb/rvtime_reg_test.svh b/src/soc_ifc/tb/rvtime_reg_test.svh
new file mode 100644
index 000000000..d2857fe88
--- /dev/null
+++ b/src/soc_ifc/tb/rvtime_reg_test.svh
@@ -0,0 +1,244 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//======================================================================
+
+
+  //----------------------------------------------------------------
+  // rvtime_reg_test()
+  // 
+  // Test writing & reading of RV_MTIME LOW/HIGH Registers 
+  //----------------------------------------------------------------
+  task rvtime_reg_test;
+    // Check RVTIME_L update operations, then effect on RVTIME_H
+    // These registers are treated differently from the scoreboard based checks
+    // since they are self-updated without a need for an external event  
+
+    string      rvtime_l = "INTERNAL_RV_MTIME_L";        
+    string      rvtime_h = "INTERNAL_RV_MTIME_H";        
+
+    word_addr_t rvtime_haddr, rvtime_laddr;
+    dword_t     rvtime_hval, rvtime_lval; // most recent value during a fetch or update
+
+    logic [31:0] update_ctr = 'h0; 
+    logic [31:0] fetch_ctr = 'h0; 
+
+    dword_t flow_status; 
+    dword_t reset_reason; 
+
+    int tid = 0; // TID is to be updated ONLY if multiple writes to an address 
+
+    WordTransaction wrtrans;
+
+
+    begin
+      $display();
+      $display("Executing task rvtime_reg_test"); 
+      $display("------------------------------\n");
+
+      // TODO. Randomize 
+      set_security_state('{device_lifecycle: DEVICE_PRODUCTION, debug_locked: DEBUG_UNLOCKED});
+
+      tc_ctr = tc_ctr + 1;
+
+      wrtrans = new();
+
+      rvtime_haddr = socregs.get_addr(rvtime_h);  
+      rvtime_laddr = socregs.get_addr(rvtime_l);  
+
+      // Skip wrting & reading over AHB until post reset sequencing is done 
+      // THEN, update scoreboard entry accordingly for a couple of registers which 
+      // are written using APB as part of Caliptra boot.  Scoreboard update not 
+      // needed for readonly fields which are set directly by wires.
+      simulate_caliptra_boot();
+
+      repeat (20) @(posedge clk_tb);
+      sb.del_all();
+      error_ctr = 0;
+
+      update_CPTRA_FLOW_STATUS(ready_for_fuses, `REG_HIER_BOOT_FSM_PS);
+
+
+      $display ("\n-------------------------------------------------------------");
+      $display ("1a. Writing/Reading using AHB/AHB");
+      $display ("-------------------------------------------------------------");
+
+      // ** Write & check RV_MTIME_H not close to overflow **
+      wrtrans.update(rvtime_haddr, 0, tid); 
+      wrtrans.randomize();
+      wrtrans.update_data(wrtrans.data & 32'h7fff_ffff); 
+
+      write_reg_trans(SET_AHB, wrtrans);  
+      read_regs(GET_AHB, {rvtime_h}, tid, 3);
+
+      // ** Write to RV_MTIME_L & check val not close to overflow **
+      wrtrans.update(rvtime_laddr, 0, tid); 
+      wrtrans.randomize();
+      wrtrans.update_data(wrtrans.data & 32'h7fff_ffff); 
+
+      rvtime_lval = wrtrans.data;
+      write_reg_trans(SET_AHB, wrtrans);  
+      update_ctr = cycle_ctr_since_pwrgood;  
+
+      repeat (3) @(posedge clk_tb);
+      read_reg_chk_inrange(GET_AHB, rvtime_l, tid, rvtime_lval + 'd3 , rvtime_lval + 'd23); 
+
+      // ** Write to RV_MTIME_L & check for overflow + update of both RV_MTIME_L + RV_MTIME_H **
+      rvtime_lval = 32'hffff_fff0;  // 16 cycles from wraparound 
+      wrtrans.update(rvtime_laddr, rvtime_lval, tid);  
+      update_ctr = cycle_ctr_since_pwrgood;  
+      write_reg_trans(SET_AHB, wrtrans);  
+
+      repeat (3) @(posedge clk_tb);
+      wrtrans.update(rvtime_haddr, 32'hffff_fffe, tid);  // < 16 cycles from increment 
+      write_reg_trans(SET_AHB, wrtrans);  
+
+      repeat (13) @(posedge clk_tb);
+      read_reg_chk_inrange(GET_AHB, rvtime_l, tid, 'h1, 'h14); 
+
+      repeat (3) @(posedge clk_tb);
+      read_reg_chk_inrange(GET_AHB, rvtime_h, tid, 32'hffff_ffff, 32'hffff_ffff);
+
+      @(posedge clk_tb);
+      rvtime_lval = 32'hffff_fff0 + (cycle_ctr_since_pwrgood - update_ctr);  
+      rvtime_hval = 32'hffff_ffff;
+
+      $display ("\n-------------------------------------------------------------");
+      $display ("1b. Writing/Reading using APB/APB + AHB"); 
+      $display ("-------------------------------------------------------------");
+
+      // ** Write & check RV_MTIME_H ** 
+      wrtrans.update(rvtime_haddr, 0, tid); 
+      wrtrans.randomize();
+
+      write_reg_trans(SET_APB, wrtrans);  
+      read_regs(GET_APB, {rvtime_h}, tid, 3); 
+
+      // ** Write to RV_MTIME_L & check val ** 
+      wrtrans.update(rvtime_laddr, 0, tid); 
+      wrtrans.randomize();
+
+      write_reg_trans(SET_APB, wrtrans);  
+
+      repeat (3) @(posedge clk_tb);
+      rvtime_lval = 32'hffff_fff0 + (cycle_ctr_since_pwrgood - update_ctr); 
+
+      read_reg_chk_inrange(GET_AHB, rvtime_l, tid, rvtime_lval - 'd5,  rvtime_lval + 'd15); 
+      @(posedge clk_tb);
+
+
+      // ** Repeat reads over AHB ** 
+      repeat (3) @(posedge clk_tb);
+      rvtime_lval = 32'hffff_fff0 + (cycle_ctr_since_pwrgood - update_ctr); 
+
+      read_reg_chk_inrange(GET_AHB, rvtime_l, tid, rvtime_lval - 'd5,  rvtime_lval + 'd15); 
+      @(posedge clk_tb);
+
+      read_reg_chk_inrange(GET_AHB, rvtime_h, tid, rvtime_hval, rvtime_hval); 
+      @(posedge clk_tb);
+
+      // There's no overflow of eiter MTIME register with APB writes since MTIME_L just 
+      // rolled passed 0. -- no check needed  
+
+
+      $display ("\n-------------------------------------------------------------");
+      $display ("1c. Writing/Reading using AHB/APB"); 
+      $display ("-------------------------------------------------------------");
+
+      // ** Write & check RV_MTIME_H this time preparing for rolloever ** 
+      wrtrans.update(rvtime_haddr, 32'hffff_ffff, tid); 
+      write_reg_trans(SET_AHB, wrtrans);  
+      repeat (3) @(posedge clk_tb);
+
+      // ** Write to RV_MTIME_L & check val ** 
+      wrtrans.update(rvtime_laddr, 32'hffff_ffff, tid); 
+      write_reg_trans(SET_AHB, wrtrans);  
+
+
+      repeat (3) @(posedge clk_tb);
+      read_reg_chk_inrange(GET_APB, rvtime_h, tid, 'h0, 'h0); 
+      repeat (3) @(posedge clk_tb);
+      read_reg_chk_inrange(GET_APB, rvtime_l, tid, 'h1, 'h20); 
+
+      // ** Write random values to RV_TIME_H/L preparing for warm reset **  
+      wrtrans.update(rvtime_haddr, 0, tid);
+      wrtrans.randomize();
+      write_reg_trans(SET_AHB, wrtrans);  
+      rvtime_hval = wrtrans.data;
+      repeat (3) @(posedge clk_tb);
+
+      wrtrans.update(rvtime_laddr, 0, tid);
+      wrtrans.randomize();
+      wrtrans.update_data(wrtrans.data & 32'h7fff_ffff);
+      write_reg_trans(SET_AHB, wrtrans);  
+      rvtime_lval = wrtrans.data;
+      update_ctr = cycle_ctr_since_pwrgood;
+      repeat (3) @(posedge clk_tb);
+
+      // There's no overflow of eiter MTIME register -- no check needed  
+
+
+      // -----------------------------------------------------------------
+      // Phase 2. Perform Warm Reset, read values over APB 
+      // -----------------------------------------------------------------
+      $display ("\n-------------------------------------------------------------");
+      $display ("2a. Perform a warm reset then just read regs"); 
+      $display ("-------------------------------------------------------------");
+
+      sb.del_all();
+      warm_reset_dut(); 
+
+      sb.record_reset_values(0, WARM_RESET);
+      wait (ready_for_fuses == 1'b1);
+
+      // Some registers need update for specific fields
+      flow_status = update_CPTRA_FLOW_STATUS(ready_for_fuses, `REG_HIER_BOOT_FSM_PS); 
+      reset_reason = update_CPTRA_RESET_REASON(1, 0);
+
+      // expect old sticky values which are different from power-on values
+      read_reg_chk_inrange(GET_APB, {rvtime_h}, tid, rvtime_hval, rvtime_hval);
+      @(posedge clk_tb);
+
+      rvtime_lval = rvtime_lval + (cycle_ctr_since_pwrgood - update_ctr);  
+      read_reg_chk_inrange(GET_APB, {rvtime_l}, tid, rvtime_lval - 'd5, rvtime_lval + 'd15); 
+      @(posedge clk_tb);
+
+      // -----------------------------------------------------------------
+      // Phase 3. Perform Cold Reset, read values over APB 
+      // -----------------------------------------------------------------
+      $display ("\n-------------------------------------------------------------");
+      $display ("3a. Perform a cold reset then just read regs"); 
+      $display ("-------------------------------------------------------------");
+
+      reset_dut();
+      sb.del_all();
+
+      sb.record_reset_values(0, COLD_RESET);
+      wait (ready_for_fuses == 1'b1);
+
+      // Some registers need update for specific fields
+      flow_status =  update_CPTRA_FLOW_STATUS(ready_for_fuses, `REG_HIER_BOOT_FSM_PS);
+      reset_reason = update_CPTRA_RESET_REASON(1, 0);
+
+      // expect old sticky values which are different from power-on values
+      read_reg_chk_inrange(GET_APB, {rvtime_h}, tid, 0, 0); 
+      @(posedge clk_tb);
+      read_reg_chk_inrange(GET_APB, {rvtime_l}, tid, 'd1, 'd20);
+      @(posedge clk_tb);
+
+      error_ctr += sb.err_count;
+
+    end
+
+  endtask // check_rvtime_regs
diff --git a/src/soc_ifc/tb/sha_acc_intrblk_test.svh b/src/soc_ifc/tb/sha_acc_intrblk_test.svh
new file mode 100644
index 000000000..84a39a9f4
--- /dev/null
+++ b/src/soc_ifc/tb/sha_acc_intrblk_test.svh
@@ -0,0 +1,236 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//======================================================================
+
+
+  //----------------------------------------------------------------
+  // sha_acc_intrblk_test()
+  // 
+  // Tests that SHA ACC Interrupt Block Registers are RO over APB  
+  //----------------------------------------------------------------
+
+
+  task sha_acc_intrblk_test; 
+
+    automatic word_addr_t addr; 
+    automatic int tid = 0; // TID is to be updated ONLY if multiple writes to an address 
+    automatic strq_t sha_acc_intrblk_regnames;
+    automatic strq_t nonmatching_regnames;
+    automatic dword_t rddata; 
+    automatic dwordq_t nonmatching_rddata;
+    automatic string rname;
+    automatic dword_t ahb_wrdata, exp_regval; 
+    automatic dword_t apb_wrdata, apb_rddata; 
+    automatic WordTransaction wrtrans, rdtrans;
+
+    // Interrupt Register Block Fields 
+    // --------------------------------
+    // logic global_intr_en_r.error_en;
+    // logic global_intr_en_r.notif_en;
+    // logic error_intr_en_r.error0_en;
+    // logic error_intr_en_r.error1_en;
+    // logic error_intr_en_r.error2_en;
+    // logic error_intr_en_r.error3_en;
+    // logic notif_intr_en_r.notif_cmd_done_en;
+    // logic error_global_intr_r.agg_sts;
+    // logic notif_global_intr_r.agg_sts;
+    logic [3:0] error_internal_intr_r;  // represent next 4 fields
+    // logic error_internal_intr_r.error0_sts;
+    // logic error_internal_intr_r.error1_sts;
+    // logic error_internal_intr_r.error2_sts;
+    // logic error_internal_intr_r.error3_sts;
+    logic notif_internal_intr_r;  // proxy for next field 
+    // logic notif_internal_intr_r.notif_cmd_done_sts;
+    logic [3:0] error_intr_trig_r;  // represent next 4 fields
+    // logic error_intr_trig_r.error0_trig;
+    // logic error_intr_trig_r.error1_trig;
+    // logic error_intr_trig_r.error2_trig;
+    // logic error_intr_trig_r.error3_trig;
+    logic notif_intr_trig_r;  // proxy for next field;
+    // logic notif_intr_trig_r.notif_cmd_done_trig;
+    // logic error0_intr_count_r.cnt;
+    // logic error1_intr_count_r.cnt;
+    // logic error2_intr_count_r.cnt;
+    // logic error3_intr_count_r.cnt;
+    // logic notif_cmd_done_intr_count_r.cnt;
+    // logic error0_intr_count_incr_r.pulse;
+    // logic error1_intr_count_incr_r.pulse;
+    // logic error2_intr_count_incr_r.pulse;
+    // logic error3_intr_count_incr_r.pulse;
+    // logic notif_cmd_done_intr_count_incr_r.pulse;
+
+    begin
+      $display("Executing task sha_acc_intrblk_test"); 
+      $display("---------------------------------\n");
+
+      // set_security_state_byname("DEBUG_UNLOCKED_PRODCUTION"); 
+
+      tc_ctr = tc_ctr + 1;
+      wrtrans = new();
+      rdtrans = new();
+
+      sha_acc_intrblk_regnames = get_sha_acc_intrblk_regnames();
+
+      // Skip wrting & reading over AHB until post reset sequencing is done 
+      // THEN, update scoreboard entry accordingly for a couple of registers which 
+      // are written using APB as part of Caliptra boot.  Scoreboard update not 
+      // needed for readonly fields which are set directly by wires.
+      simulate_caliptra_boot();
+
+      // PHASE I. 1a.  Write (AHB, then APB) and Read register over APB 
+      // ------------------------------------------------------------
+
+      repeat (20) @(posedge clk_tb);
+      sb.del_all();
+
+      update_CPTRA_FLOW_STATUS(ready_for_fuses, `REG_HIER_BOOT_FSM_PS);
+
+      $display ("\n1a. Writing over AHB, APB then reading back over APB"); 
+
+      foreach (sha_acc_intrblk_regnames[i]) begin
+        rname = sha_acc_intrblk_regnames[i];
+        addr = socregs.get_addr(rname);
+        wrtrans.update(addr, 0, tid);
+        wrtrans.randomize();
+
+        ahb_wrdata = wrtrans.data; 
+        apb_wrdata = ~ahb_wrdata; 
+
+        write_reg_trans(SET_AHB, wrtrans);  
+        repeat (3) @(posedge clk_tb);
+        wrtrans.update_data(apb_wrdata);
+        write_reg_trans(SET_APB, wrtrans);  
+        repeat (3) @(posedge clk_tb);
+
+        rdtrans.update(addr, 0, tid);
+        read_reg_trans(GET_APB, rdtrans);  
+        @(posedge clk_tb);
+
+        apb_rddata = rdtrans.data;
+        exp_regval = socregs.get_exp_regval(rname);
+
+        if (apb_rddata == exp_regval)
+          continue; // all good; move on to next
+
+        if (apb_rddata == apb_wrdata) begin
+          $display ("TB ERROR for addr 0x%08x (%s). apb_rddata matches apb_wrdata 0x%08x", addr, rname, apb_rddata);
+          error_ctr = error_ctr + 1;
+        end else if (apb_rddata != exp_regval) begin 
+          if (rddata != '0) begin 
+            $display ("TB ERROR for addr 0x%08x (%s). Unexpected non-zero apb_rddata 0x%08x", addr, rname, rddata);
+            error_ctr = error_ctr + 1;
+          end else begin
+            $display ("TB Warning for addr 0x%08x (%s). apb_rddata 0x%08x does not match exp_regval 0x%08x", addr, rname, apb_rddata, exp_regval);
+            nonmatching_regnames.push_back(rname);
+            nonmatching_rddata.push_back(apb_rddata);
+          end
+        end
+      end 
+
+      // control launch of assertions using directed writes
+      // Expect issues w/the 4 registers
+      assign error_internal_intr_r = {dut.i_sha512_acc_top.i_sha512_acc_csr.field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value , 
+                                      dut.i_sha512_acc_top.i_sha512_acc_csr.field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value , 
+                                      dut.i_sha512_acc_top.i_sha512_acc_csr.field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value ,
+                                      dut.i_sha512_acc_top.i_sha512_acc_csr.field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value}; 
+
+      assign notif_internal_intr_r = dut.i_sha512_acc_top.i_sha512_acc_csr.field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value; 	
+
+      assign error_intr_trig_r = {dut.i_sha512_acc_top.i_sha512_acc_csr.field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value ,
+                                 dut.i_sha512_acc_top.i_sha512_acc_csr.field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value ,
+                                 dut.i_sha512_acc_top.i_sha512_acc_csr.field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value ,
+                                 dut.i_sha512_acc_top.i_sha512_acc_csr.field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value};
+
+      assign notif_intr_trig_r = dut.i_sha512_acc_top.i_sha512_acc_csr.field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value;
+
+
+      foreach (nonmatching_regnames[i]) begin
+        rname = nonmatching_regnames[i];
+        rddata = nonmatching_rddata[i];
+
+        addr = socregs.get_addr(rname);
+        wrtrans.update(addr, 32'hffff_ffff, tid);
+        write_reg_trans(SET_AHB, wrtrans); // This should clear the register to all 0's
+        repeat (10) @(posedge clk_tb); 
+
+        fork    // Try to set again over apb - should be unsuccessful 
+          begin
+            write_reg_trans(SET_APB, wrtrans);  
+            repeat (10) @(posedge clk_tb); 
+          end
+
+          begin
+            repeat (10) begin
+              // $display ( "TB DEBUG. checking for assertion");
+              @(posedge clk_tb);
+              case (rname) 
+               "SHA_ACC_INTR_BRF_ERROR_INTERNAL_INTR_R": assert ((|error_internal_intr_r) == 1'b0)
+                  else begin
+                    $display ("TB ERROR aserted for addr 0x%08x (%s). Register bit-field(s) mutable over APB! agg value is 0b%b", addr, rname, error_internal_intr_r);
+                    error_ctr += 1;
+                    break;
+                  end
+
+                "SHA_ACC_INTR_BRF_NOTIF_INTERNAL_INTR_R": assert ((|notif_internal_intr_r) == 1'b0)
+                  else begin
+                    $display ("TB ERROR aserted for addr 0x%08x (%s). Register bit-field(s) mutable over APB! agg value is 0b%b", addr, rname, notif_internal_intr_r); 
+                    error_ctr += 1;
+                    break;
+                  end
+
+                "SHA_ACC_INTR_BRF_ERROR_INTR_TRIG_R": assert ((|error_intr_trig_r) == 1'b0)
+                  else begin
+                    $display ("TB ERROR aserted for addr 0x%08x (%s). Register bit-field(s) mutable over APB! agg value is 0b%b", addr, rname, error_intr_trig_r); 
+                    error_ctr += 1;
+                    break;
+                  end
+
+                "SHA_ACC_INTR_BRF_NOTIF_INTR_TRIG_R": assert ((|notif_intr_trig_r) == 1'b0)
+                  else begin
+                    $display ("TB ERROR aserted for addr 0x%08x (%s). Register bit-field(s) mutable over APB! agg value is 0b%b", addr, rname, notif_intr_trig_r); 
+                    error_ctr += 1;
+                    break;
+                  end
+
+                default: $display ("TB ERROR for addr 0x%08x (%s). Unexpected mismatch; no handler found", addr, rname); 
+              endcase
+            end 
+          end
+        join_any
+ 
+      end
+      
+    end
+
+  endtask // sha_acc_intrblk_test
+
+/* 
+// Placeholder for concurrent assertions in future
+
+sequence remain_low__sha_acc_error_internal_intr_r;
+  (| ({ dut.i_sha512_acc_top.i_sha512_acc_csr.field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value, 
+        dut.i_sha512_acc_top.i_sha512_acc_csr.field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value, 
+        dut.i_sha512_acc_top.i_sha512_acc_csr.field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value,
+        dut.i_sha512_acc_top.i_sha512_acc_csr.field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value }) == 1'b0); 
+endsequence 
+
+property reg_remains_low;
+  @(posedge clk_tb)
+  disable iff (reg_sva_off) remain_low__sha_acc_error_internal_intr_r;
+endproperty
+
+monitor_trans2ones: assert property(reg_remains_low);
+*/
+
diff --git a/src/soc_ifc/tb/single_soc_reg_test.svh b/src/soc_ifc/tb/single_soc_reg_test.svh
index 4711f0ded..d66a67338 100644
--- a/src/soc_ifc/tb/single_soc_reg_test.svh
+++ b/src/soc_ifc/tb/single_soc_reg_test.svh
@@ -20,16 +20,21 @@
   //
   // Tests out write/read single soc register test using same bus protocol 
   //----------------------------------------------------------------
-  task single_socreg_test(input string meth_name);
+  task single_socreg_test(input string meth_name, int wrcount);
+    // Example 
+    //   meth_name: AHB.CPTRA_TIMER_CONFIG -- for back2back AHB write+read
+    //   wrcount:   20 --  number of times to perform write-read pairs 
 
     access_t access;
     string meth, rname;
     word_addr_t addr; 
     int tid = 0; 
 
+    strq_t reglist;
     WordTransaction wrtrans, rdtrans;
  
     begin
+
       $display("Executing single_socreg_test: %s", meth_name);
       $display("----------------------------%s\n", {meth_name.len(){"-"}});
 
@@ -38,38 +43,48 @@
       wrtrans = new();
       rdtrans = new();
 
+      meth = meth_name.substr(0, 2);
       rname = meth_name.substr(4, meth_name.len()-1);
       addr = socregs.get_addr(rname); 
- 
-      // Write over a method & read over same method 
 
-      wrtrans.update(addr, 0, tid); 
-      wrtrans.randomize();
+      reglist.push_back(rname);
 
-      if (str_startswith(meth_name, "APB.")) begin
-        write_single_word_apb(addr, wrtrans.data); 
-        sb.record_entry(wrtrans, SET_APB);
+      if (wrcount < 1) begin
+        error_ctr = 1; 
+        $display("ERROR performing %s operations on register %s %d times -- wrcount MUST be > 0", meth, rname, wrcount);
+      end else begin
+        $display("-- Performing %s operations on register %s %d times --", meth, rname, wrcount);
+      end
 
-        repeat (10) @(posedge clk_tb);
-        read_single_word_apb(addr); 
-        $display("Read over APB:  addr = %30s (0x%08x), data = 0x%08x", rname, addr, prdata_o_tb);
 
-        rdtrans.update(addr, prdata_o_tb, tid); 
-        sb.check_entry(rdtrans);
+      if (meth == "AHB") begin // Perform Caliptra boot  
 
-      end  else if (str_startswith(meth_name, "AHB.")) begin
-        write_single_word_ahb(addr, wrtrans.data);
-        sb.record_entry(wrtrans, SET_AHB);
+        simulate_caliptra_boot();
+        repeat (20) @(posedge clk_tb);
+        sb.del_all();
+        update_CPTRA_FLOW_STATUS(ready_for_fuses, `REG_HIER_BOOT_FSM_PS);
 
-        repeat (10) @(posedge clk_tb);
-        read_single_word_apb(addr); 
-        $display("Read over AHB:  addr = %30s (0x%08x), data = 0x%08x", rname, addr, prdata_o_tb);
 
-        rdtrans.update(addr, hrdata_o_tb, tid); 
-        sb.check_entry(rdtrans);
       end 
-         
-      error_ctr = sb.err_count;
+
+      update_INTR_BRF_NOTIF_INTERNAL_INTR_R(gen_input_wire_toggle, security_state.debug_locked); 
+
+      // Write over a method & read over same method 
+
+      for (int i = 0; i < wrcount; i++) begin
+
+        wrtrans.update(addr, 0, tid); 
+        wrtrans.randomize();
+
+        if (str_startswith(meth_name, "APB.")) 
+          write_read_regs(SET_APB, GET_APB, reglist, tid, 1);
+        else if (str_startswith(meth_name, "AHB.")) 
+          write_read_regs(SET_AHB, GET_AHB, reglist, tid, 1);
+
+      end 
+
+    error_ctr = sb.err_count;
+
     end
 
   endtask // single_socreg_test
diff --git a/src/soc_ifc/tb/soc_ifc_tb.sv b/src/soc_ifc/tb/soc_ifc_tb.sv
index 4853d1eb4..7a50704d0 100644
--- a/src/soc_ifc/tb/soc_ifc_tb.sv
+++ b/src/soc_ifc/tb/soc_ifc_tb.sv
@@ -22,17 +22,19 @@
 // Probably should be deprecated and utilize UVMF environment only
 //======================================================================
 
-/*
-`define PRINT_TESTNAME(_SOC_IFC_TESTNAME) \ 
-    string tmpstr = `"_SOC_IFC_TESTNAME`";
-    $display(`"Executing test: _SOC_IFC_TESTNAME`"); 
-    $display({{tmpstr.len(){`"-`"}});
-//----------------------------------------------------------------
-*/
-
 
 import "DPI-C" function string getenv(input string env_name);
 
+`define AHB64_HI 63:32
+`define AHB64_LO 31:0 
+
+`define REG_HIER_BOOT_FSM_PS dut.boot_fsm_ps
+`define REG_HIER_PFX dut.i_soc_ifc_reg.field_storage
+
+`define FORLOOP_COMB(x) always_comb for (int j = 0; j < x; j++) 
+`define STR_RMPFX(astr, bstr) astr.substr(bstr.len(), astr.len() - 1).atoi()
+
+
 module soc_ifc_tb
   import soc_ifc_pkg::*;
   import soc_ifc_tb_pkg::*;
@@ -41,10 +43,13 @@ module soc_ifc_tb
 
   enum logic {DEBUG_UNLOCKED = 1'b0, DEBUG_LOCKED = 1'b1} debug_state_e;
 
-  // Strings for plusargs
+  // plusargs and other test related
   string soc_ifc_testname; 
   string socreg_method_name = ""; 
   string security_state_testname; 
+  int socreg_wrcount = 1;
+
+  string tphase;
 
 
   //----------------------------------------------------------------
@@ -69,21 +74,25 @@ module soc_ifc_tb
 
   parameter MBOX_DLEN_VAL         = 32'h0000001C;
 
-  parameter MBOX_UDS_ADDR         = 32'h3003_0200;
-  parameter MBOX_FE_ADDR          = 32'h3003_0230;
-  parameter MBOX_FUSE_DONE_ADDR   = 32'h3003_00ac;
+  parameter MBOX_UDS_ADDR         = SOCIFC_BASE + `SOC_IFC_REG_FUSE_UDS_SEED_0;
+  parameter MBOX_FE_ADDR          = SOCIFC_BASE + `SOC_IFC_REG_FUSE_FIELD_ENTROPY_0;
+  parameter MBOX_FUSE_DONE_ADDR   = SOCIFC_BASE + `SOC_IFC_REG_CPTRA_FUSE_WR_DONE;
+
+  parameter AHB_ADDR_WIDTH = `CALIPTRA_SLAVE_ADDR_WIDTH(`CALIPTRA_SLAVE_SEL_SOC_IFC); // 18 
+  parameter AHB_DATA_WIDTH = `CALIPTRA_AHB_HDATA_SIZE; // 32 
+  parameter APB_ADDR_WIDTH = `CALIPTRA_SLAVE_ADDR_WIDTH(`CALIPTRA_SLAVE_SEL_SOC_IFC); // 18 
+  parameter APB_DATA_WIDTH = `CALIPTRA_APB_DATA_WIDTH; // 32 
+  parameter APB_USER_WIDTH = `CALIPTRA_APB_USER_WIDTH; // 32 
 
-  parameter AHB_ADDR_WIDTH = 18;
-  parameter AHB_DATA_WIDTH = 32;
-  parameter APB_ADDR_WIDTH = 18;
-  parameter APB_DATA_WIDTH = 32;
-  parameter APB_USER_WIDTH = 32;
 
   parameter AHB_HTRANS_IDLE     = 0;
   parameter AHB_HTRANS_BUSY     = 1;
   parameter AHB_HTRANS_NONSEQ   = 2;
   parameter AHB_HTRANS_SEQ      = 3;
 
+  localparam PAUSER_DEFAULT = 32'hffff_ffff;
+
+
   //----------------------------------------------------------------
   // Register and Wire declarations.
   //----------------------------------------------------------------
@@ -153,6 +162,23 @@ module soc_ifc_tb
 
   //MH. Initialize to default device lifecycle later rather than TIE OFF
   security_state_t security_state, tmp_ss;  // '{device_lifecycle: DEVICE_PRODUCTION, debug_locked: DEBUG_LOCKED};
+  logic            gen_input_wire_toggle;  
+
+  logic [31:0]     generic_input_wires0_q; 
+  logic [31:0]     generic_input_wires1_q; 
+
+  //MH. Tick timers
+  logic [31:0]   cycle_ctr_since_pwrgood;
+  logic [31:0]   cycle_ctr_since_rst;
+
+  bit            reg_sva_off = 1'b1;  // Enable only during register assertion checks
+
+  logic [APB_DATA_WIDTH-1:0]    prdata_o_latched;
+
+
+  always @(negedge clk_tb) begin
+    prdata_o_latched <= prdata_o_tb;
+  end
 
   always_comb begin
     mbox_sram_cs = mbox_sram_req.cs;
@@ -171,19 +197,22 @@ module soc_ifc_tb
   // Device Under Test.
   //----------------------------------------------------------------
   soc_ifc_top #(
-             .AHB_DATA_WIDTH(32),
-             .AHB_ADDR_WIDTH(18),
-             .APB_USER_WIDTH(32),
-             .APB_ADDR_WIDTH(18),
-             .APB_DATA_WIDTH(32)
+             .AHB_DATA_WIDTH(AHB_DATA_WIDTH), 
+             .AHB_ADDR_WIDTH(AHB_ADDR_WIDTH), 
+             .APB_USER_WIDTH(APB_USER_WIDTH), 
+             .APB_ADDR_WIDTH(APB_ADDR_WIDTH), 
+             .APB_DATA_WIDTH(APB_DATA_WIDTH)  
             )
             dut (
              .clk(clk_tb),
              .clk_cg(clk_tb),
              .soc_ifc_clk_cg(clk_tb),
+             .rdc_clk_cg(clk_tb),
 
              .cptra_pwrgood(cptra_pwrgood_tb),
              .cptra_rst_b(cptra_rst_b_tb),
+             .rdc_clk_dis(),
+             .fw_update_rst_window(),
 
              .ready_for_fuses(ready_for_fuses),
              .ready_for_fw_push(ready_for_fw_push),
@@ -228,10 +257,13 @@ module soc_ifc_tb
              .soc_ifc_notif_intr(),
              .sha_error_intr(),
              .sha_notif_intr(),
+             .timer_intr(),
 
              .mbox_sram_req(mbox_sram_req),
              .mbox_sram_resp(mbox_sram_resp),
 
+             .rv_ecc_sts(rv_ecc_sts_t'{default:1'b0}),
+
              .clear_obf_secrets(clear_obf_secrets), 
              .scan_mode_f(scan_mode_f), 
              .cptra_obf_key('0),
@@ -278,6 +310,7 @@ module soc_ifc_tb
   );
 
 
+  // Other special and aggregate data type instantiations 
   struct {
     string reg_name;
     WordTransaction wr_trans;
@@ -323,6 +356,45 @@ module soc_ifc_tb
     end
 
 
+  //----------------------------------------------------------------
+  // tick_timer 
+  // 
+  // Counts number of clock ticks since power good and reset
+  //----------------------------------------------------------------
+  always @(posedge clk_tb or negedge cptra_pwrgood_tb) begin : tick_timer_pwrgood
+    if (!cptra_pwrgood_tb)
+      cycle_ctr_since_pwrgood <= '0;
+    else
+      cycle_ctr_since_pwrgood <= cycle_ctr_since_pwrgood + 1'b1; 
+  end 
+
+  always @(posedge clk_tb or negedge cptra_rst_b_tb) begin : tick_timer_outofrst
+    if (!cptra_rst_b_tb)
+      cycle_ctr_since_rst <= '0;
+    else
+      cycle_ctr_since_rst <= cycle_ctr_since_pwrgood + 1'b1; 
+  end
+
+
+  //----------------------------------------------------------------
+  // generic_input_detetor 
+  //
+  // pulses high when generic input wires change  
+  //----------------------------------------------------------------
+  always @(posedge clk_tb or negedge cptra_rst_b_tb) begin  : generic_input_detector
+    if (!cptra_rst_b_tb) begin
+      generic_input_wires0_q <= '0; 
+      generic_input_wires1_q <= '0;
+    end else begin 
+      generic_input_wires0_q <= cptra_noncore_rst_b_tb ? generic_input_wires0 : generic_input_wires0_q; 
+      generic_input_wires1_q <= cptra_noncore_rst_b_tb ? generic_input_wires1 : generic_input_wires1_q; 
+    end
+  end
+
+  assign gen_input_wire_toggle = (generic_input_wires0 != generic_input_wires0_q) | 
+                                 (generic_input_wires1 != generic_input_wires1_q);
+
+
   //----------------------------------------------------------------
   // pulse_trig_handler 
   //
@@ -350,11 +422,13 @@ module soc_ifc_tb
   // CPTRA SECUIRTY_STATE, FLOW_STATUS, GENERIC_INPUT_WIRES
   //----------------------------------------------------------------
 
-  always_comb begin 
-    update_CPTRA_SECURITY_STATE(scan_mode_f, security_state.debug_locked, security_state.device_lifecycle);
-    update_CPTRA_FLOW_STATUS(ready_for_fuses);
-    update_CPTRA_GENERIC_INPUT_WIRES(generic_input_wires1, generic_input_wires0);
-  end 
+  always_comb update_CPTRA_SECURITY_STATE(scan_mode_f, security_state.debug_locked, security_state.device_lifecycle);
+  always_comb update_CPTRA_FLOW_STATUS(ready_for_fuses, `REG_HIER_BOOT_FSM_PS);
+  always_comb update_CPTRA_GENERIC_INPUT_WIRES(generic_input_wires1_q, 1'b1); 
+  always_comb update_CPTRA_GENERIC_INPUT_WIRES(generic_input_wires0_q, 1'b0);
+  always_comb update_INTR_BRF_NOTIF_INTERNAL_INTR_R(gen_input_wire_toggle, security_state.debug_locked); 
+
+
 
   //----------------------------------------------------------------
   // reset_dut()
@@ -365,11 +439,14 @@ module soc_ifc_tb
     begin
       $display("*** Toggle reset.");
 
-      reset_generic_input_wires(-1, -1);
+      set_generic_input_wires(-1, -1);
 
       cptra_pwrgood_tb = '0;
       cptra_rst_b_tb = 0;
 
+      set_initval("CPTRA_GENERIC_INPUT_WIRES0", generic_input_wires0);  // The init val will take effect 
+      set_initval("CPTRA_GENERIC_INPUT_WIRES1", generic_input_wires1);  // after reset deassertion 
+
       repeat (5) @(posedge clk_tb);
 
       socregs.unlock_fuses();
@@ -379,6 +456,7 @@ module soc_ifc_tb
       repeat (5) @(posedge clk_tb);
       
       cptra_rst_b_tb = 1;
+      repeat (5) @(posedge clk_tb);
       $display("");
     end
   endtask // reset_dut
@@ -393,7 +471,7 @@ module soc_ifc_tb
     begin
       $display("*** Perform warm reset. ***");
 
-      reset_generic_input_wires(-1, -1);
+      set_generic_input_wires(-1, -1);
       reset_flow_status();
 
       cptra_rst_b_tb = 0;
@@ -401,6 +479,7 @@ module soc_ifc_tb
       repeat (5) @(posedge clk_tb);
 
       cptra_rst_b_tb = 1;
+      repeat (5) @(posedge clk_tb);
       $display("");
     end
   endtask // reset_dut
@@ -508,6 +587,7 @@ module soc_ifc_tb
   //----------------------------------------------------------------
   task write_single_word_ahb(input [31 : 0]  address,
                              input [31 : 0] word);
+
     begin
       hsel_i_tb       <= 1;
       haddr_i_tb      <= address;
@@ -517,7 +597,7 @@ module soc_ifc_tb
 
       @(posedge clk_tb);
       haddr_i_tb      <= 'Z;
-      hwdata_i_tb     <= word;
+      hwdata_i_tb     <= address[2] ? {word, 32'h0}: {32'h0, word}; 
       hwrite_i_tb     <= 0;
       htrans_i_tb     <= AHB_HTRANS_IDLE;
       wait(hreadyout_o_tb == 1'b1);
@@ -555,6 +635,33 @@ module soc_ifc_tb
   endtask // write_single_word_apb
 
 
+  //----------------------------------------------------------------
+  // write_single_word_apb_wpauser()
+  //
+  // Write the given word to the DUT using the APB interface setting pauser.
+  //----------------------------------------------------------------
+  task write_single_word_apb_wpauser(input [31 : 0] address,
+                                     input [31 : 0] word,
+                                     input [31 : 0] pauser);
+    begin
+      paddr_i_tb      <= address;
+      psel_i_tb       <= 1;
+      penable_i_tb    <= 0;
+      pwrite_i_tb     <= 1;
+      pwdata_i_tb     <= word;
+      pauser_i_tb     <= pauser; 
+      wait(pready_o_tb == 1'b1);
+      
+      @(posedge clk_tb);
+      penable_i_tb    <= 1;
+      wait(pready_o_tb == 1'b1);
+
+      @(posedge clk_tb);
+      psel_i_tb       <= 0;
+      penable_i_tb    <= 0;
+    end
+  endtask // write_single_word_apb_wpauser
+
 
   //----------------------------------------------------------------
   // write_block_ahb()
@@ -630,7 +737,34 @@ module soc_ifc_tb
       psel_i_tb       <= 0;
       penable_i_tb    <= 0;
     end
-  endtask // read_single_word_ahb
+  endtask // read_single_word_apb
+
+  //----------------------------------------------------------------
+  // read_single_word_apb_wpauser()
+  //
+  // Read the given word to the DUT using the APB interface setting pauser.
+  //----------------------------------------------------------------
+  task read_single_word_apb_wpauser(input [31 : 0] address,
+                                     input [31 : 0] word,
+                                     input [31 : 0] pauser);
+    begin
+      paddr_i_tb      <= address;
+      psel_i_tb       <= 1;
+      penable_i_tb    <= 0;
+      pwrite_i_tb     <= 0;
+      pwdata_i_tb     <= 0;
+      pauser_i_tb     <= pauser; 
+      wait(pready_o_tb == 1'b1);
+
+      @(posedge clk_tb);
+      penable_i_tb    <= 1;
+      wait(pready_o_tb == 1'b1);
+
+      @(posedge clk_tb);
+      psel_i_tb       <= 0;
+      penable_i_tb    <= 0;
+    end
+  endtask // read_single_word_apb_wpauser
 
   //----------------------------------------------------------------
   // read_result_ahb()
@@ -641,13 +775,13 @@ module soc_ifc_tb
     begin
       
       read_single_word_ahb(MBOX_ADDR_DATAOUT);
-      r_data[127 : 96] = hrdata_o_tb;
+      r_data[127 : 96] = MBOX_ADDR_DATAOUT[2] ? hrdata_o_tb[`AHB64_HI] : hrdata_o_tb[`AHB64_LO]; 
       read_single_word_ahb(MBOX_ADDR_DATAOUT);
-      r_data[95  : 64] = hrdata_o_tb;
+      r_data[95  : 64] = MBOX_ADDR_DATAOUT[2] ? hrdata_o_tb[`AHB64_HI] : hrdata_o_tb[`AHB64_LO]; 
       read_single_word_ahb(MBOX_ADDR_DATAOUT);
-      r_data[63  : 32] = hrdata_o_tb;
+      r_data[63  : 32] = MBOX_ADDR_DATAOUT[2] ? hrdata_o_tb[`AHB64_HI] : hrdata_o_tb[`AHB64_LO]; 
       read_single_word_ahb(MBOX_ADDR_DATAOUT);
-      r_data[31  :  0] = hrdata_o_tb;
+      r_data[31  :  0] = MBOX_ADDR_DATAOUT[2] ? hrdata_o_tb[`AHB64_HI] : hrdata_o_tb[`AHB64_LO]; 
     end
   endtask // read_result_ahb
 
@@ -677,11 +811,16 @@ module soc_ifc_tb
   // wait for the mailbox to unlock before send in anything
   //----------------------------------------------------------------
   task wait_unlock_ahb;
+      
+    automatic logic [31:0] valid_hrdata;
+
     begin
       read_single_word_ahb(MBOX_ADDR_LOCK);
-      while (hrdata_o_tb != 0)
+      valid_hrdata =  MBOX_ADDR_LOCK[2] ?  hrdata_o_tb[`AHB64_HI] :hrdata_o_tb[`AHB64_LO]; 
+      while (valid_hrdata != 0) 
         begin
           read_single_word_ahb(MBOX_ADDR_LOCK);
+          valid_hrdata =  MBOX_ADDR_LOCK[2] ?  hrdata_o_tb[`AHB64_HI] :hrdata_o_tb[`AHB64_LO]; 
         end
     end
   endtask // wait_unlock_ahb
@@ -702,50 +841,23 @@ module soc_ifc_tb
   endtask // wait_unlock_apb
 
 
-  //----------------------------------------------------------------
-  // set_security_state()
-  //
-  // sets the security state explicily to any valid value 
-  //----------------------------------------------------------------
-  task set_security_state(input security_state_t ss);
-  // TODO. Has hardwired mask bit positions in here. Ideally they should be pulled from tb package. 
-
-      dword_t intr_notif_val; 
-
-      begin
-          security_state = '{device_lifecycle: ss.device_lifecycle, debug_locked: ss.debug_locked};
-
-          set_initval("CPTRA_SECURITY_STATE", ss & 32'h7);  
-          update_exp_regval("CPTRA_SECURITY_STATE", ss & 32'h7, SET_DIRECT); 
-
-
-          intr_notif_val = get_initval("INTR_BRF_NOTIF_INTERNAL_INTR_R") & 32'hffff_fffb | ss.debug_locked & 32'h4;
-          set_initval("INTR_BRF_NOTIF_INTERNAL_INTR_R", intr_notif_val); 
-          update_exp_regval("INTR_BRF_NOTIF_INTERNAL_INTR_R", intr_notif_val, SET_DIRECT);  
-      end
-  endtask
-
-
 
   //----------------------------------------------------------------
-  // reset_generic_input_wires()
+  // set_generic_input_wires()
   //
   // sets the generic_input_wires to a predetermined or random value
   //----------------------------------------------------------------
-  task reset_generic_input_wires(input int v0, int v1);
+  task set_generic_input_wires(input int v0, int v1);
 
     begin
       generic_input_wires0 = (v0 < 0) ? $urandom() : v0;
       generic_input_wires1 = (v1 < 0) ? $urandom() : v1;
-      set_initval("CPTRA_GENERIC_INPUT_WIRES0", generic_input_wires0); 
-      set_initval("CPTRA_GENERIC_INPUT_WIRES1", generic_input_wires1); 
-      update_exp_regval("CPTRA_GENERIC_INPUT_WIRES0", generic_input_wires0, SET_DIRECT); 
-      update_exp_regval("CPTRA_GENERIC_INPUT_WIRES1", generic_input_wires1, SET_DIRECT); 
-
-      @(posedge clk_tb);
+      repeat (2) @(posedge clk_tb);
+      update_CPTRA_GENERIC_INPUT_WIRES(generic_input_wires0_q, 1'b0); 
+      update_CPTRA_GENERIC_INPUT_WIRES(generic_input_wires1_q, 1'b1); 
     end
 
-  endtask
+  endtask // set_generic_input_wires
 
 
   //----------------------------------------------------------------
@@ -757,7 +869,7 @@ module soc_ifc_tb
 
     begin
       set_initval("CPTRA_FLOW_STATUS", '0); 
-      update_CPTRA_FLOW_STATUS('0);
+      update_CPTRA_FLOW_STATUS('0, `REG_HIER_BOOT_FSM_PS);
     end
 
   endtask
@@ -918,11 +1030,16 @@ module soc_ifc_tb
   //----------------------------------------------------------------
   task sim_dut_init;
 
-    int sscode = -1;
+    // int sscode = -1;
+    string ssname = "UNSET"; 
 
     begin
-      sscode = int'(security_state);
-      if (!((sscode >= 0)  || (sscode <= 7))) 
+      // sscode = int'(security_state);
+      // if (!((sscode >= 0)  || (sscode <= 7))) 
+      //   $error("Have to explictily set security_state for soc_ifc_top for test to run!");
+
+      ssname = get_ss_name(int'(security_state)); 
+      if ((ssname == "") || (ssname == "UNSET"))
         $error("Have to explictily set security_state for soc_ifc_top for test to run!");
 
       else begin
@@ -930,8 +1047,9 @@ module soc_ifc_tb
         reset_dut();
 
         wait (ready_for_fuses == 1'b1);
-        set_initval("CPTRA_FLOW_STATUS", 32'h4000_0000); 
-        update_exp_regval("CPTRA_FLOW_STATUS", 32'h4000_0000, SET_DIRECT); 
+        update_CPTRA_FLOW_STATUS(ready_for_fuses, `REG_HIER_BOOT_FSM_PS);
+        // set_initval("CPTRA_FLOW_STATUS", 32'h4000_0000); 
+        // update_exp_regval("CPTRA_FLOW_STATUS", 32'h4000_0000, SET_DIRECT); 
 
         repeat (5) @(posedge clk_tb);
       end
@@ -1006,7 +1124,118 @@ module soc_ifc_tb
           repeat (wait_cycles) @(posedge clk_tb);
       end
     end
-  endtask
+  endtask // write_regs
+
+
+  //-----------------------------------------------------------------------------
+  // read_reg_chk_inrange()
+  //
+  // Utility for reading single register over APB/AHB and check if within range.
+  // NOTE. Wait times must be added explcitly outside routine
+  //-----------------------------------------------------------------------------
+  task read_reg_chk_inrange(input access_t modifier, string rname, int tid, int minval, int maxval); 
+
+    word_addr_t addr;
+    WordTransaction rdtrans;
+    automatic logic [31:0] valid_hrdata; 
+
+    begin
+      rdtrans = new();
+      addr = socregs.get_addr(rname);  
+
+      if (modifier == GET_AHB) begin 
+          read_single_word_ahb(addr);
+          valid_hrdata =  addr[2] ?  hrdata_o_tb[`AHB64_HI] :hrdata_o_tb[`AHB64_LO]; 
+          $display(" Read over AHB: addr =  %-40s (0x%08x), data = 0x%08x", rname, addr, valid_hrdata); 
+          rdtrans.update(addr, valid_hrdata, tid); 
+      end else if (modifier == GET_APB) begin
+        read_single_word_apb(addr);
+        $display(" Read over APB: addr =  %-40s (0x%08x), data = 0x%08x", rname, addr, prdata_o_tb); 
+        rdtrans.update_byname(rname, prdata_o_tb,  tid); 
+        end else 
+          $error("TB ERROR. Unsupported access modifier %s", modifier.name()); 
+
+      sb.record_entry(rdtrans, SET_DIRECT);
+      sb.check_entry_inrange(rdtrans, minval, maxval); 
+    end
+
+  endtask // read_reg_chk_inrange
+
+
+  //----------------------------------------------------------------
+  // write_reg_trans()
+  //
+  // Utility for tracking/writing transaction to a register over APB/AHB
+  // NOTE. Wait times must be added explcitly outside routine
+  //----------------------------------------------------------------
+  task write_reg_trans(access_t modifier, WordTransaction wrtrans, logic [31:0] pauser=PAUSER_DEFAULT);
+    string rname;
+    word_addr_t addr;
+
+    begin
+        addr = wrtrans.addr;
+        rname = socregs.get_name(addr); 
+
+        if (modifier == SET_AHB) begin
+          write_single_word_ahb(addr, wrtrans.data); 
+          $display("Write over AHB: addr = %-40s (0x%08x), data = 0x%08x", rname, addr, wrtrans.data);
+        end else if (modifier == SET_APB) begin
+          if (pauser != PAUSER_DEFAULT) begin
+            write_single_word_apb_wpauser(addr, wrtrans.data, pauser); 
+            $display("Write over APB with non-default pauser: addr = %-40s (0x%08x), data = 0x%08x", 
+              rname, addr, wrtrans.data);
+          end else begin
+            write_single_word_apb(addr, wrtrans.data); 
+            $display("Write over APB: addr = %-40s (0x%08x), data = 0x%08x", rname, addr, wrtrans.data);
+          end
+        end else 
+          $error("TB ERROR. Unsupported access modifier %s", modifier.name()); 
+
+        sb.record_entry(wrtrans, modifier);
+      end
+    endtask // write_reg_trans
+
+
+ //----------------------------------------------------------------
+  // read_reg_trans()
+  //
+  // Utility for reading transaction to a register over APB/AHB
+  // NOTES. 1. No scoreboard checking 
+  //        2. Wait times must be added explcitly outside routine
+  //----------------------------------------------------------------
+  task read_reg_trans(input access_t modifier, 
+                      inout WordTransaction rdtrans, 
+                      input logic [31:0] pauser=PAUSER_DEFAULT); 
+    string rname;
+    word_addr_t addr;
+    automatic logic [31:0] valid_hrdata; 
+
+    begin
+        addr = rdtrans.addr;
+        rname = socregs.get_name(addr); 
+
+        if (modifier == GET_AHB) begin
+          read_single_word_ahb(addr); 
+          valid_hrdata =  addr[2] ?  hrdata_o_tb[`AHB64_HI] :hrdata_o_tb[`AHB64_LO]; 
+          rdtrans.data = valid_hrdata; 
+          $display(" Read over AHB: addr = %-40s (0x%08x), data = 0x%08x", rname, addr, rdtrans.data);
+        end else if (modifier == GET_APB) begin
+          if (pauser != PAUSER_DEFAULT) begin
+            read_single_word_apb_wpauser(addr, rdtrans.data, pauser); 
+            rdtrans.data = prdata_o_tb;
+            $display(" Read over APB with explicit pauser: addr = %-40s (0x%08x), data = 0x%08x", 
+              rname, addr, rdtrans.data);
+          end else begin
+            read_single_word_apb(addr); 
+            rdtrans.data = prdata_o_tb;
+            $display(" Read over APB: addr = %-40s (0x%08x), data = 0x%08x", rname, addr, rdtrans.data);
+          end
+        end else 
+          $error("TB ERROR. Unsupported access modifier %s", modifier.name()); 
+
+        // sb.check_entry(rdtrans)
+    end
+  endtask // read_reg_trans
 
 
   //----------------------------------------------------------------
@@ -1020,6 +1249,7 @@ module soc_ifc_tb
     WordTransaction rdtrans;
 
     int tid_autoinc; 
+    automatic logic [31:0] valid_hrdata; 
 
     begin
       rdtrans = new();
@@ -1039,12 +1269,15 @@ module soc_ifc_tb
 
         if (modifier == GET_AHB) begin
           read_single_word_ahb(addr);
-          $display("Read over AHB: addr =  %-40s (0x%08x), data = 0x%08x", rname, addr, hrdata_o_tb); 
-          rdtrans.update(addr, hrdata_o_tb, tid); 
+          valid_hrdata =  addr[2] ?  hrdata_o_tb[`AHB64_HI] :hrdata_o_tb[`AHB64_LO]; 
+          $display(" Read over AHB: addr =  %-40s (0x%08x), data = 0x%08x on cycle %08d", rname, addr, valid_hrdata, cycle_ctr); 
+          rdtrans.update(addr, valid_hrdata, tid); 
         end else if (modifier == GET_APB) begin
           read_single_word_apb(addr);
-          $display("Read over APB: addr =  %-40s (0x%08x), data = 0x%08x", rname, addr, prdata_o_tb); 
-          rdtrans.update(addr, prdata_o_tb, tid); 
+          // $display(" Read over APB: addr =  %-40s (0x%08x), data = 0x%08x at time %12t (cycle %08d)", rname, addr, prdata_o_latched, $realtime, cycle_ctr); // used to be   prdata_o_tb
+          $display(" Read over APB: addr =  %-40s (0x%08x), data = 0x%08x on cycle %08d", rname, addr, prdata_o_tb, cycle_ctr); // used to be   prdata_o_tb
+          // rdtrans.update(addr, prdata_o_latched, tid);  // used to be prdata_o_tb
+          rdtrans.update(addr, prdata_o_tb, tid);  
         end else 
           $error("TB ERROR. Unsupported access modifier %s", modifier.name()); 
 
@@ -1056,7 +1289,7 @@ module soc_ifc_tb
 
       end
     end
-  endtask
+  endtask // read_regs
 
 
   //----------------------------------------------------------------
@@ -1072,6 +1305,7 @@ module soc_ifc_tb
     WordTransaction wrtrans;
 
     int tid_autoinc; 
+    automatic logic [31:0] valid_hrdata; 
 
     begin
       wrtrans = new();
@@ -1122,11 +1356,12 @@ module soc_ifc_tb
         // read phase
         if (rd_modifier == GET_AHB) begin
           read_single_word_ahb(addr);
-          $display("Read over AHB: addr =  %-40s (0x%08x), data = 0x%08x", rname, addr, hrdata_o_tb); 
-          rdtrans.update(addr, hrdata_o_tb, tid); 
+          valid_hrdata = addr[2] ? hrdata_o_tb[`AHB64_HI] : hrdata_o_tb[`AHB64_LO]; 
+          $display(" Read over AHB: addr =  %-40s (0x%08x), data = 0x%08x", rname, addr, valid_hrdata); 
+          rdtrans.update(addr, valid_hrdata, tid); 
         end else if (rd_modifier == GET_APB) begin
           read_single_word_apb(addr);
-          $display("Read over APB: addr =  %-40s (0x%08x), data = 0x%08x", rname, addr, prdata_o_tb); 
+          $display(" Read over APB: addr =  %-40s (0x%08x), data = 0x%08x", rname, addr, prdata_o_tb); 
           rdtrans.update(addr, prdata_o_tb, tid); 
         end else 
           $error("TB ERROR. Unsupported access rd_modifier %s", rd_modifier.name()); 
@@ -1143,6 +1378,50 @@ module soc_ifc_tb
 
   endtask // write_read_regs
 
+  //================================================================
+  // Function Definitions
+  //================================================================
+
+
+  //----------------------------------------------------------------
+  // set_security_state()
+  //
+  // sets the security state explicily to any value between 0..7
+  //----------------------------------------------------------------
+  function automatic void set_security_state(input security_state_t ss);
+
+      dword_t intr_notif_val; 
+
+      begin
+          security_state = '{device_lifecycle: ss.device_lifecycle, debug_locked: ss.debug_locked};
+
+          // TODO. Has hardwired mask bit positions in here. Ideally they should be pulled from tb package. 
+          //       Eg: in update_CPTRA_SECURITY_STATE(...)
+          set_initval("CPTRA_SECURITY_STATE", ss & 32'h7);  
+          update_exp_regval("CPTRA_SECURITY_STATE", ss & 32'h7, SET_DIRECT); 
+
+          intr_notif_val = get_initval("INTR_BRF_NOTIF_INTERNAL_INTR_R") & 32'hffff_fffb | ss.debug_locked & 32'h4;
+          set_initval("INTR_BRF_NOTIF_INTERNAL_INTR_R", intr_notif_val); 
+          update_exp_regval("INTR_BRF_NOTIF_INTERNAL_INTR_R", intr_notif_val, SET_DIRECT);  
+      end
+  endfunction // set_security_state
+
+
+  //----------------------------------------------------------------
+  // set_security_state_byname()
+  //
+  // sets security state by name, eg: "DEBUG_LOCKED_PRODUCTION", "RANDOM" 
+  //----------------------------------------------------------------
+  function automatic security_state_t set_security_state_byname(input string ss_name="RANDOM");         
+
+    bit [2:0] ss_code;
+
+    begin
+      ss_code = (ss_name == "RANDOM") ? $urandom_range(0, 7) : get_ss_code(ss_name);
+      set_security_state(security_state_t'(ss_code)); 
+      return security_state_t'(ss_code); 
+    end
+  endfunction // set_security_state_byname 
 
 
 //----------------------------------------------------------------
@@ -1150,14 +1429,17 @@ module soc_ifc_tb
 // or as programs. For now, this is the only modularization for 
 // directed tests planned.
 //----------------------------------------------------------------
-//
   `include "fuse_reg_lifecycle_test.svh"   
   `include "fuse_reg_perm_test.svh"     
+  `include "fuse_reg_pauser_test.svh"     
   `include "fuse_reg_test.svh"     
   `include "single_soc_reg_test.svh"   
   `include "soc_reg_reset_test.svh"     
   `include "soc_reg_test.svh"     
+  `include "rvtime_reg_test.svh"     
   `include "soc_reg_invalid_test.svh"     
+  `include "soc_reg_intrblk_test.svh" 
+  `include "sha_acc_intrblk_test.svh"
 //----------------------------------------------------------------
 
 
@@ -1172,8 +1454,8 @@ module soc_ifc_tb
 
     // common initialization steps for all tests 
 
-    // set_security_state(DEVICE_PRODUCTION, DEBUG_LOCKED);
-    // update_exp_regval(socregs.get_addr("CPTRA_SECURITY_STATE"), dword_t'(security_state), SET_DIRECT);
+    generic_input_wires0 = 32'h0; 
+    generic_input_wires1 = 32'h0; 
 
     $write("PLAYBOOK_RANDOM_SEED = %s\n", getenv("PLAYBOOK_RANDOM_SEED"));
 
@@ -1183,10 +1465,6 @@ module soc_ifc_tb
         $display("    Running SOC_IFC_TEST = %s", soc_ifc_testname);
         $display("    =================================================================");
 
-        //if (!($value$plusargs("SECURITY_STATE=%s", security_state_testname)))
-        //  security_state_testname = "RANDOM";
-        // soc_reg_pwron_test(security_state_testname);
-
         if (soc_ifc_testname == "soc_reg_pwron_test") begin 
           if (!($value$plusargs("SECURITY_STATE=%s", security_state_testname)))
             security_state_testname = "RANDOM";
@@ -1206,25 +1484,41 @@ module soc_ifc_tb
           if ($value$plusargs("SECURITY_STATE=%s", security_state_testname)) 
             fuse_reg_lifecycle_test(security_state_testname);
           else
-            fuse_reg_lifecycle_test("RANDOM"); // 'ALL' is the other option that isn't working fully 
+            fuse_reg_lifecycle_test("RANDOM"); 
  
         end else if (soc_ifc_testname == "soc_reg_test") begin 
           set_security_state('{device_lifecycle: DEVICE_PRODUCTION, debug_locked: DEBUG_LOCKED});
           sim_dut_init();
           soc_reg_test();
 
+        end else if (soc_ifc_testname == "rvtime_reg_test") begin 
+          set_security_state('{device_lifecycle: DEVICE_PRODUCTION, debug_locked: DEBUG_LOCKED});
+          sim_dut_init();
+          rvtime_reg_test();
+
         end else if (soc_ifc_testname == "soc_reg_invalid_test") begin 
           set_security_state('{device_lifecycle: DEVICE_PRODUCTION, debug_locked: DEBUG_LOCKED});
           sim_dut_init();
           soc_reg_invalid_test();
 
+        end else if (soc_ifc_testname == "soc_reg_intrblk_test") begin 
+          set_security_state('{device_lifecycle: DEVICE_PRODUCTION, debug_locked: DEBUG_LOCKED});
+          sim_dut_init();
+          soc_reg_intrblk_test();
+
+        end else if (soc_ifc_testname == "sha_acc_intrblk_test") begin 
+          set_security_state('{device_lifecycle: DEVICE_PRODUCTION, debug_locked: DEBUG_LOCKED});
+          sim_dut_init();
+          sha_acc_intrblk_test();
+
         end else if (soc_ifc_testname == "single_socreg_test") begin 
           if (!($value$plusargs("SOCREG_METHOD_NAME=%s", socreg_method_name))) 
             $display("ERROR with testing one soc_register; must provide method & name for +scoreg_method_name,eg. APB.CPTRA_TIMER_CONFIG");
           else begin
+            $value$plusargs("SOCREG_WRCOUNT=%d", socreg_wrcount);
             set_security_state('{device_lifecycle: DEVICE_PRODUCTION, debug_locked: DEBUG_LOCKED});
             sim_dut_init();
-            single_socreg_test(socreg_method_name);
+            single_socreg_test(socreg_method_name, socreg_wrcount);
           end
 
         end else if (soc_ifc_testname == "fuse_reg_perm_test") begin 
@@ -1232,6 +1526,11 @@ module soc_ifc_tb
           sim_dut_init();
           fuse_reg_perm_test();
 
+        end else if (soc_ifc_testname == "fuse_reg_pauser_test") begin 
+          set_security_state_byname("RANDOM");
+          sim_dut_init();
+          fuse_reg_pauser_test();
+
         end 
    
         @(posedge clk_tb);
@@ -1243,7 +1542,8 @@ module soc_ifc_tb
 
     else 
       begin : default_test  // Keeping original default test structure 
-        $display("    ==============================");
+
+        $display("    ==============================");  
         $display("   -= Testbench for MBOX started =-");
         $display("    ==============================");
         $display("");
diff --git a/src/soc_ifc/tb/soc_ifc_tb_pkg.sv b/src/soc_ifc/tb/soc_ifc_tb_pkg.sv
index 9ef6d1eb6..4115bdd98 100644
--- a/src/soc_ifc/tb/soc_ifc_tb_pkg.sv
+++ b/src/soc_ifc/tb/soc_ifc_tb_pkg.sv
@@ -24,6 +24,7 @@ package soc_ifc_tb_pkg;
   `include "caliptra_reg_defines.svh" // This is from integration/rtl level 
 
   localparam SOCIFC_BASE = `CLP_SOC_IFC_REG_BASE_ADDR;
+  localparam SHAACC_BASE = `CLP_SHA512_ACC_CSR_BASE_ADDR;
   localparam ADDR_WIDTH = 32; // SHould be 18; will let APB & AHB bus widths truncate as needed
 
 
@@ -46,9 +47,16 @@ package soc_ifc_tb_pkg;
     int         tid;    
   } transaction_t;
 
+  // Useful struct to qualify an int "d" with a valid "v" status
+  typedef struct {
+    int d;   
+    int v;   
+  } intpair_t; 
+
   typedef transaction_t transq_t [$];  
 
   typedef string strq_t [$];  
+  typedef dword_t dwordq_t [$];  
 
   typedef enum {
     COLD_RESET, WARM_RESET,
@@ -88,7 +96,6 @@ package soc_ifc_tb_pkg;
   // The whole thing could probably be done slickly using enums but dictionaries 
   // are easier to use and lookup stuff. To be updated if overhead is too high. 
 
-  // TODO. This will be merged into register dict at some point as a pair 
   word_addr_t _wide_register_dict [string] = {
     "CPTRA_FW_EXTENDED_ERROR_INFO"          : 8, 
     "CPTRA_MBOX_VALID_PAUSER"               : 5,  
@@ -97,6 +104,10 @@ package soc_ifc_tb_pkg;
     "CPTRA_GENERIC_INPUT_WIRES"             : 2,  
     "CPTRA_GENERIC_OUTPUT_WIRES"            : 2,  
     "CPTRA_FW_REV_ID"                       : 2,
+    "CPTRA_WDT_TIMER1_TIMEOUT_PERIOD"       : 2, 
+    "CPTRA_WDT_TIMER2_TIMEOUT_PERIOD"       : 2, 
+    "CPTRA_WDT_CFG"                         : 2, 
+    "CPTRA_RSVD_REG"                        : 2, 
     "FUSE_UDS_SEED"                         : 12,
     "FUSE_FIELD_ENTROPY"                    : 8,
     "FUSE_KEY_MANIFEST_PK_HASH"             : 12,
@@ -110,109 +121,153 @@ package soc_ifc_tb_pkg;
 
   // ** NOTE. INTR_BRF (== INTR_BLOCK_RF) registers are NOT explictly tested. Only provided to check for undefined ranges, and for future **
   //  
-  // Identifier                                       Base Addr      Offset                                                          // Offset   Description
+  // Identifier                                       Base Addr      Offset                                                            // Offset   Description
   word_addr_t _soc_register_dict [string] = {
-    "CPTRA_HW_ERROR_FATAL"                          : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_HW_ERROR_FATAL,                               // 0x000      Hardware Error Fatal 
-    "CPTRA_HW_ERROR_NON_FATAL"                      : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL,                           // 0x004      Hardware Error Non-Fatal 
-    "CPTRA_FW_ERROR_FATAL"                          : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_FW_ERROR_FATAL,                               // 0x008      Firmware Error Fatal 
-    "CPTRA_FW_ERROR_NON_FATAL"                      : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_FW_ERROR_NON_FATAL,                           // 0x00c      Firmware Error Non-Fatal 
-    "CPTRA_HW_ERROR_ENC"                            : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_HW_ERROR_ENC,                                 // 0x010      Hardware Error Encoding 
-    "CPTRA_FW_ERROR_ENC"                            : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_FW_ERROR_ENC,                                 // 0x014      Firmware Error Encoding 
-    "CPTRA_FW_EXTENDED_ERROR_INFO"                  : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_0,                     // 0x018 [8]  Firmware Extended Error Information 
-    "CPTRA_BOOT_STATUS"                             : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_BOOT_STATUS,                                  // 0x038      Boot Status 
-    "CPTRA_FLOW_STATUS"                             : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_FLOW_STATUS,                                  // 0x03c      Flow Status 
-    "CPTRA_RESET_REASON"                            : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_RESET_REASON,                                 // 0x040      Reset Reason 
-    "CPTRA_SECURITY_STATE"                          : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_SECURITY_STATE,                               // 0x044      Security State 
-    "CPTRA_MBOX_VALID_PAUSER"                       : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_0,                          // 0x048 [5]  Valid User Registers 
-    "CPTRA_MBOX_PAUSER_LOCK"                        : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_0,                           // 0x05c [5]  Valid User Register Lock 
-    "CPTRA_TRNG_VALID_PAUSER"                       : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_TRNG_VALID_PAUSER,                            // 0x070      Valid User for TRNG 
-    "CPTRA_TRNG_PAUSER_LOCK"                        : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_TRNG_PAUSER_LOCK,                             // 0x074      Valid User for TRNG PAUSER Lock 
-    "CPTRA_TRNG_DATA"                               : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_TRNG_DATA_0,                                  // 0x078 [12] TRNG Data 
-    "CPTRA_TRNG_STATUS"                             : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_TRNG_STATUS,                                  // 0x0a8      TRNG Status 
-    "CPTRA_FUSE_WR_DONE"                            : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_FUSE_WR_DONE,                                 // 0x0ac      Fuse Write Done 
-    "CPTRA_TIMER_CONFIG"                            : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_TIMER_CONFIG,                                 // 0x0b0      Timer Config 
-    "CPTRA_BOOTFSM_GO"                              : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_BOOTFSM_GO,                                   // 0x0b4      BOOTFSM GO 
-    "CPTRA_DBG_MANUF_SERVICE_REG"                   : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_DBG_MANUF_SERVICE_REG,                        // 0x0b8      DEBUG & MANUF SERVICE REG
-    "CPTRA_CLK_GATING_EN"                           : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_CLK_GATING_EN,                                // 0x0bc      Global Caliptra Clk gating enable 
-    "CPTRA_GENERIC_INPUT_WIRES"                     : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0,                        // 0x0c0 [2]  Generic Input Wires 
-    "CPTRA_GENERIC_OUTPUT_WIRES"                    : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_0,                       // 0x0c8 [2]  Generic Output Wires 
-    "CPTRA_HW_REV_ID"                               : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_HW_REV_ID,                                    // 0x0d0      Caliptra HW RevID 
-    "CPTRA_FW_REV_ID"                               : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_FW_REV_ID_0,                                  // 0x0d4      Caliptra FW RevID
-    "CPTRA_HW_CONFIG" 	                            : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_HW_CONFIG,                                    // 0x0dc      Caliptra HW Config
-    "CPTRA_WDT_TIMER1_EN"                           : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_WDT_TIMER1_EN,                                // 0x0e0      Caliptra WDT Timer1 EN register 	
-    "CPTRA_WDT_TIMER1_CTRL"                         : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL,                              // 0x0e4      Caliptra WDT Timer1 CTRL register 	
-    "CPTRA_WDT_TIMER1_TIMEOUT_PERIOD"               : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0,                  // 0x0e8 [2]  Caliptra WDT Timer1 Timeout Period register 	
-    "CPTRA_WDT_TIMER2_EN"                           : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_WDT_TIMER2_EN,                                // 0x0f0      Caliptra WDT Timer2 EN register 	
-    "CPTRA_WDT_TIMER2_CTRL"                         : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL,                              // 0x0f4      Caliptra WDT Timer2 CTRL register 	
-    "CPTRA_WDT_TIMER2_TIMEOUT_PERIOD"               : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0,                  // 0x0f8 [2]  Caliptra WDT Timer2 Timeout Period register 	
-    "CPTRA_WDT_STATUS"                              : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_WDT_STATUS,                                   // 0x100      Caliptra WDT STATUS register
-    // 0x104..0x1fc
-    "FUSE_UDS_SEED"                                 : SOCIFC_BASE + `SOC_IFC_REG_FUSE_UDS_SEED_0,                                    // 0x200 [12] Unique Device Secret 
-    "FUSE_FIELD_ENTROPY"                            : SOCIFC_BASE + `SOC_IFC_REG_FUSE_FIELD_ENTROPY_0,                               // 0x230 [8]  Field Entropy 
-    "FUSE_KEY_MANIFEST_PK_HASH"                     : SOCIFC_BASE + `SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_0,                        // 0x250 [12] - 
-    "FUSE_KEY_MANIFEST_PK_HASH_MASK"                : SOCIFC_BASE + `SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK,                     // 0x280      - 
-    "FUSE_OWNER_PK_HASH"                            : SOCIFC_BASE + `SOC_IFC_REG_FUSE_OWNER_PK_HASH_0,                               // 0x284 [12] - 
-    "FUSE_FMC_KEY_MANIFEST_SVN"                     : SOCIFC_BASE + `SOC_IFC_REG_FUSE_FMC_KEY_MANIFEST_SVN,                          // 0x2b4      - 
-    "FUSE_RUNTIME_SVN"                              : SOCIFC_BASE + `SOC_IFC_REG_FUSE_RUNTIME_SVN_0,                                 // 0x2b8 [4]  - 
-    "FUSE_ANTI_ROLLBACK_DISABLE"                    : SOCIFC_BASE + `SOC_IFC_REG_FUSE_ANTI_ROLLBACK_DISABLE,                         // 0x2c8      - 
-    "FUSE_IDEVID_CERT_ATTR"                         : SOCIFC_BASE + `SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_0,                            // 0x2cc [24] - 
-    "FUSE_IDEVID_MANUF_HSM_ID"                      : SOCIFC_BASE + `SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_0,                         // 0x32c [4]  - 
-    "FUSE_LIFE_CYCLE"                               : SOCIFC_BASE + `SOC_IFC_REG_FUSE_LIFE_CYCLE,                                    // 0x33c      - 
-    // 0x340..0x5fc           
-    "INTERNAL_OBF_KEY"                              : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_OBF_KEY_0,                                 // 0x600 [8]  De-Obfuscation Key 
-    "INTERNAL_ICCM_LOCK"                            : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_ICCM_LOCK,                                 // 0x620      ICCM Lock 
-    "INTERNAL_FW_UPDATE_RESET"                      : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET,                           // 0x624      FW Update Reset 
-    "INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES"          : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES,               // 0x628      FW Update Reset Wait Cycles 
-    "INTERNAL_NMI_VECTOR"                           : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_NMI_VECTOR,                                // 0x62c      NMI Vector 
-    // 0x630..0x7fc    
-    // "intr_block_rf"                         
-    "INTR_BRF_GLOBAL_INTR_EN_R"                     : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R,                     // 0x800
-    "INTR_BRF_ERROR_INTR_EN_R"                      : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R,                      // 0x804
-    "INTR_BRF_NOTIF_INTR_EN_R"                      : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R,                      // 0x808
-    "INTR_BRF_ERROR_GLOBAL_INTR_R"                  : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R,                  // 0x80c
-    "INTR_BRF_NOTIF_GLOBAL_INTR_R"                  : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R,                  // 0x810
-    "INTR_BRF_ERROR_INTERNAL_INTR_R"                : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R,                // 0x814
-    "INTR_BRF_NOTIF_INTERNAL_INTR_R"                : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R,                // 0x818
-    "INTR_BRF_ERROR_INTR_TRIG_R"                    : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R,                    // 0x81c
-    "INTR_BRF_NOTIF_INTR_TRIG_R"                    : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R,                    // 0x820
+    "CPTRA_HW_ERROR_FATAL"                          : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_HW_ERROR_FATAL,                                 // 0x000      Hardware Error Fatal 
+    "CPTRA_HW_ERROR_NON_FATAL"                      : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL,                             // 0x004      Hardware Error Non-Fatal 
+    "CPTRA_FW_ERROR_FATAL"                          : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_FW_ERROR_FATAL,                                 // 0x008      Firmware Error Fatal 
+    "CPTRA_FW_ERROR_NON_FATAL"                      : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_FW_ERROR_NON_FATAL,                             // 0x00c      Firmware Error Non-Fatal 
+    "CPTRA_HW_ERROR_ENC"                            : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_HW_ERROR_ENC,                                   // 0x010      Hardware Error Encoding 
+    "CPTRA_FW_ERROR_ENC"                            : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_FW_ERROR_ENC,                                   // 0x014      Firmware Error Encoding 
+    "CPTRA_FW_EXTENDED_ERROR_INFO"                  : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_FW_EXTENDED_ERROR_INFO_0,                       // 0x018 [8]  Firmware Extended Error Information 
+    "CPTRA_BOOT_STATUS"                             : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_BOOT_STATUS,                                    // 0x038      Boot Status 
+    "CPTRA_FLOW_STATUS"                             : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_FLOW_STATUS,                                    // 0x03c      Flow Status 
+    "CPTRA_RESET_REASON"                            : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_RESET_REASON,                                   // 0x040      Reset Reason 
+    "CPTRA_SECURITY_STATE"                          : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_SECURITY_STATE,                                 // 0x044      Security State 
+    "CPTRA_MBOX_VALID_PAUSER"                       : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_MBOX_VALID_PAUSER_0,                            // 0x048 [5]  Valid User Registers 
+    "CPTRA_MBOX_PAUSER_LOCK"                        : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_0,                             // 0x05c [5]  Valid User Register Lock 
+    "CPTRA_TRNG_VALID_PAUSER"                       : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_TRNG_VALID_PAUSER,                              // 0x070      Valid User for TRNG 
+    "CPTRA_TRNG_PAUSER_LOCK"                        : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_TRNG_PAUSER_LOCK,                               // 0x074      Valid User for TRNG PAUSER Lock 
+    "CPTRA_TRNG_DATA"                               : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_TRNG_DATA_0,                                    // 0x078 [12] TRNG Data 
+    "CPTRA_TRNG_CTRL"                               : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_TRNG_CTRL,                                      // 0x0a8      TRNG Ctrl 
+    "CPTRA_TRNG_STATUS"                             : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_TRNG_STATUS,                                    // 0x0ac      TRNG Status 
+    "CPTRA_FUSE_WR_DONE"                            : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_FUSE_WR_DONE,                                   // 0x0b0      Fuse Write Done 
+    "CPTRA_TIMER_CONFIG"                            : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_TIMER_CONFIG,                                   // 0x0b4      Timer Config 
+    "CPTRA_BOOTFSM_GO"                              : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_BOOTFSM_GO,                                     // 0x0b8      BOOTFSM GO 
+    "CPTRA_DBG_MANUF_SERVICE_REG"                   : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_DBG_MANUF_SERVICE_REG,                          // 0x0bc      DEBUG & MANUF SERVICE REG
+    "CPTRA_CLK_GATING_EN"                           : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_CLK_GATING_EN,                                  // 0x0c0      Global Caliptra Clk gating enable 
+    "CPTRA_GENERIC_INPUT_WIRES"                     : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0,                          // 0x0c8 [2]  Generic Input Wires 
+    "CPTRA_GENERIC_OUTPUT_WIRES"                    : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_0,                         // 0x0d0 [2]  Generic Output Wires 
+    "CPTRA_HW_REV_ID"                               : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_HW_REV_ID,                                      // 0x0d4      Caliptra HW RevID 
+    "CPTRA_FW_REV_ID"                               : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_FW_REV_ID_0,                                    // 0x0dc      Caliptra FW RevID
+    "CPTRA_HW_CONFIG"                               : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_HW_CONFIG,                                      // 0x0e0      Caliptra HW Config
+    "CPTRA_WDT_TIMER1_EN"                           : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_WDT_TIMER1_EN,                                  // 0x0e4      Caliptra WDT Timer1 EN register  
+    "CPTRA_WDT_TIMER1_CTRL"                         : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL,                                // 0x0e8      Caliptra WDT Timer1 CTRL register  
+    "CPTRA_WDT_TIMER1_TIMEOUT_PERIOD"               : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0,                    // 0x0f0 [2]  Caliptra WDT Timer1 Timeout Period register  
+    "CPTRA_WDT_TIMER2_EN"                           : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_WDT_TIMER2_EN,                                  // 0x0f4      Caliptra WDT Timer2 EN register  
+    "CPTRA_WDT_TIMER2_CTRL"                         : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL,                                // 0x0f8      Caliptra WDT Timer2 CTRL register  
+    "CPTRA_WDT_TIMER2_TIMEOUT_PERIOD"               : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0,                    // 0x100 [2]  Caliptra WDT Timer2 Timeout Period register  
+    "CPTRA_WDT_STATUS"                              : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_WDT_STATUS,                                     // 0x104      Caliptra WDT STATUS register
+    "CPTRA_FUSE_VALID_PAUSER"                       : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_FUSE_VALID_PAUSER,                              // 0x108      Valid User for FUSE 
+    "CPTRA_FUSE_PAUSER_LOCK"                        : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_FUSE_PAUSER_LOCK,                               // 0x10c      Valid User for FUSE PAUSER Lock
+    "CPTRA_WDT_CFG"                                 : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_WDT_CFG_0,                                      // 0x110 [2]  Caliptra WDT1 Config 	
+    "CPTRA_ITRNG_ENTROPY_CONFIG_0"	                : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0,                         // 0x118      Caliptra iTRNG Entropy Configuration 0 	                            
+    "CPTRA_ITRNG_ENTROPY_CONFIG_1"	                : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1,                         // 0x11c      Caliptra iTRNG Entropy Configuration 1    
+    "CPTRA_RSVD_REG"                                : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_RSVD_REG_0,                                     // 0x120 [2]  Caliptra Reserved Registers
+    // 0x128..0x1fc
+    "FUSE_UDS_SEED"                                 : SOCIFC_BASE + `SOC_IFC_REG_FUSE_UDS_SEED_0,                                      // 0x200 [12] Unique Device Secret 
+    "FUSE_FIELD_ENTROPY"                            : SOCIFC_BASE + `SOC_IFC_REG_FUSE_FIELD_ENTROPY_0,                                 // 0x230 [8]  Field Entropy 
+    "FUSE_KEY_MANIFEST_PK_HASH"                     : SOCIFC_BASE + `SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_0,                          // 0x250 [12] - 
+    "FUSE_KEY_MANIFEST_PK_HASH_MASK"                : SOCIFC_BASE + `SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK,                       // 0x280      - 
+    "FUSE_OWNER_PK_HASH"                            : SOCIFC_BASE + `SOC_IFC_REG_FUSE_OWNER_PK_HASH_0,                                 // 0x284 [12] - 
+    "FUSE_FMC_KEY_MANIFEST_SVN"                     : SOCIFC_BASE + `SOC_IFC_REG_FUSE_FMC_KEY_MANIFEST_SVN,                            // 0x2b4      - 
+    "FUSE_RUNTIME_SVN"                              : SOCIFC_BASE + `SOC_IFC_REG_FUSE_RUNTIME_SVN_0,                                   // 0x2b8 [4]  - 
+    "FUSE_ANTI_ROLLBACK_DISABLE"                    : SOCIFC_BASE + `SOC_IFC_REG_FUSE_ANTI_ROLLBACK_DISABLE,                           // 0x2c8      - 
+    "FUSE_IDEVID_CERT_ATTR"                         : SOCIFC_BASE + `SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_0,                              // 0x2cc [24] - 
+    "FUSE_IDEVID_MANUF_HSM_ID"                      : SOCIFC_BASE + `SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_0,                           // 0x32c [4]  - 
+    "FUSE_LIFE_CYCLE"                               : SOCIFC_BASE + `SOC_IFC_REG_FUSE_LIFE_CYCLE,                                      // 0x33c      - 
+    "FUSE_LMS_VERIFY"                               : SOCIFC_BASE + `SOC_IFC_REG_FUSE_LMS_VERIFY,                                      // 0x340      -
+    "FUSE_LMS_REVOCATION"                           : SOCIFC_BASE + `SOC_IFC_REG_FUSE_LMS_REVOCATION,                                  // 0x344      -
+    "FUSE_SOC_STEPPING_ID"                          : SOCIFC_BASE + `SOC_IFC_REG_FUSE_SOC_STEPPING_ID,                                 // 0x348      - 
+    // 0x34c..0x5fc           
+    "INTERNAL_OBF_KEY"                              : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_OBF_KEY_0,                                   // 0x600 [8]  De-Obfuscation Key 
+    "INTERNAL_ICCM_LOCK"                            : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_ICCM_LOCK,                                   // 0x620      ICCM Lock 
+    "INTERNAL_FW_UPDATE_RESET"                      : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET,                             // 0x624      FW Update Reset 
+    "INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES"          : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES,                 // 0x628      FW Update Reset Wait Cycles 
+    "INTERNAL_NMI_VECTOR"                           : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_NMI_VECTOR,                                  // 0x62c      NMI Vector 
+    "INTERNAL_HW_ERROR_FATAL_MASK"                  : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK,                         // 0x630      Hardware Error Fatal Mask   
+    "INTERNAL_HW_ERROR_NON_FATAL_MASK"              : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK,                     // 0x634      Hardware Error Non-Fatal Mask   
+    "INTERNAL_FW_ERROR_FATAL_MASK"                  : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_FW_ERROR_FATAL_MASK,                         // 0x638      Firmware Error Fatal Mask   
+    "INTERNAL_FW_ERROR_NON_FATAL_MASK"              : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_FW_ERROR_NON_FATAL_MASK,                     // 0x63C      Firmware Error Non-Fatal Mask 0
+    "INTERNAL_RV_MTIME_L"                           : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_RV_MTIME_L,                                  // 0x640      mtime low   
+    "INTERNAL_RV_MTIME_H"                           : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_RV_MTIME_H,                                  // 0x644      mtime high  
+    "INTERNAL_RV_MTIMECMP_L"                        : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_RV_MTIMECMP_L,                               // 0x648      mtimecmp low  
+    "INTERNAL_RV_MTIMECMP_H"                        : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_RV_MTIMECMP_H,                               // 0x64C      mtimecmp high
+    // 0x650..0x7fc    
+    // SoC IFC Interrupt Block Register 
+    "INTR_BRF_GLOBAL_INTR_EN_R"                     : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R,                       // 0x800
+    "INTR_BRF_ERROR_INTR_EN_R"                      : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R,                        // 0x804
+    "INTR_BRF_NOTIF_INTR_EN_R"                      : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R,                        // 0x808
+    "INTR_BRF_ERROR_GLOBAL_INTR_R"                  : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R,                    // 0x80c
+    "INTR_BRF_NOTIF_GLOBAL_INTR_R"                  : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R,                    // 0x810
+    "INTR_BRF_ERROR_INTERNAL_INTR_R"                : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R,                  // 0x814
+    "INTR_BRF_NOTIF_INTERNAL_INTR_R"                : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R,                  // 0x818
+    "INTR_BRF_ERROR_INTR_TRIG_R"                    : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R,                      // 0x81c
+    "INTR_BRF_NOTIF_INTR_TRIG_R"                    : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R,                      // 0x820
     // 0x824..0x8fc
-    "INTR_BRF_ERROR_INTERNAL_INTR_COUNT_R"          : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_R,          // 0x900
-    "INTR_BRF_ERROR_INV_DEV_INTR_COUNT_R"           : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INV_DEV_INTR_COUNT_R,           // 0x904
-    "INTR_BRF_ERROR_CMD_FAIL_INTR_COUNT_R"          : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_CMD_FAIL_INTR_COUNT_R,          // 0x908
-    "INTR_BRF_ERROR_BAD_FUSE_INTR_COUNT_R"          : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_BAD_FUSE_INTR_COUNT_R,          // 0x90c
-    "INTR_BRF_ERROR_ICCM_BLOCKED_INTR_COUNT_R"      : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_ICCM_BLOCKED_INTR_COUNT_R,      // 0x910
-    "INTR_BRF_ERROR_MBOX_ECC_UNC_INTR_COUNT_R"      : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_MBOX_ECC_UNC_INTR_COUNT_R,      // 0x914
-    "INTR_BRF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_R": SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_R,// 0x918 	
-    "INTR_BRF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_R": SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_R,// 0x91c 	
+    "INTR_BRF_ERROR_INTERNAL_INTR_COUNT_R"          : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_R,            // 0x900
+    "INTR_BRF_ERROR_INV_DEV_INTR_COUNT_R"           : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INV_DEV_INTR_COUNT_R,             // 0x904
+    "INTR_BRF_ERROR_CMD_FAIL_INTR_COUNT_R"          : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_CMD_FAIL_INTR_COUNT_R,            // 0x908
+    "INTR_BRF_ERROR_BAD_FUSE_INTR_COUNT_R"          : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_BAD_FUSE_INTR_COUNT_R,            // 0x90c
+    "INTR_BRF_ERROR_ICCM_BLOCKED_INTR_COUNT_R"      : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_ICCM_BLOCKED_INTR_COUNT_R,        // 0x910
+    "INTR_BRF_ERROR_MBOX_ECC_UNC_INTR_COUNT_R"      : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_MBOX_ECC_UNC_INTR_COUNT_R,        // 0x914
+    "INTR_BRF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_R": SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_R,  // 0x918   
+    "INTR_BRF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_R": SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_R,  // 0x91c   
     // 0x920..0x97c
-    "INTR_BRF_NOTIF_CMD_AVAIL_INTR_COUNT_R"         : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_CMD_AVAIL_INTR_COUNT_R,         // 0x980
-    "INTR_BRF_NOTIF_MBOX_ECC_COR_INTR_COUNT_R"      : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_R,      // 0x984
-    "INTR_BRF_NOTIF_DEBUG_LOCKED_INTR_COUNT_R"      : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_R,      // 0x988
-	  "INTR_BRF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_R" 	    : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_R,      // 0x98c 
-    // 0x990..0x9fc 
-    "INTR_BRF_ERROR_INTERNAL_INTR_COUNT_INCR_R"     : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R,     // 0xa00
-    "INTR_BRF_ERROR_INV_DEV_INTR_COUNT_INCR_R"      : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INV_DEV_INTR_COUNT_INCR_R,      // 0xa04
-    "INTR_BRF_ERROR_CMD_FAIL_INTR_COUNT_INCR_R"     : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_CMD_FAIL_INTR_COUNT_INCR_R,     // 0xa08
-    "INTR_BRF_ERROR_BAD_FUSE_INTR_COUNT_INCR_R"     : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_BAD_FUSE_INTR_COUNT_INCR_R,     // 0xa0c
-    "INTR_BRF_ERROR_ICCM_BLOCKED_INTR_COUNT_INCR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_ICCM_BLOCKED_INTR_COUNT_INCR_R, // 0xa10
-    "INTR_BRF_ERROR_MBOX_ECC_UNC_INTR_COUNT_INCR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_MBOX_ECC_UNC_INTR_COUNT_INCR_R, // 0xa14
-    "INTR_BRF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_INCR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_INCR_R,  // 0xa18 	
-    "INTR_BRF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_INCR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_INCR_R,  // 0xa1c 	
-    "INTR_BRF_NOTIF_CMD_AVAIL_INTR_COUNT_INCR_R"    : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_CMD_AVAIL_INTR_COUNT_INCR_R,    // 0xa20
-    "INTR_BRF_NOTIF_MBOX_ECC_COR_INTR_COUNT_INCR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_INCR_R, // 0xa24 	
-    "INTR_BRF_NOTIF_DEBUG_LOCKED_INTR_COUNT_INCR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_INCR_R, // 0xa28 
-    "INTR_BRF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R  //  0xa2c
+    "INTR_BRF_NOTIF_CMD_AVAIL_INTR_COUNT_R"         : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_CMD_AVAIL_INTR_COUNT_R,           // 0x980
+    "INTR_BRF_NOTIF_MBOX_ECC_COR_INTR_COUNT_R"      : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_R,        // 0x984
+    "INTR_BRF_NOTIF_DEBUG_LOCKED_INTR_COUNT_R"      : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_R,        // 0x988
+    "INTR_BRF_NOTIF_SCAN_MODE_INTR_COUNT_R"         : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_R,           // 0x98c 
+    "INTR_BRF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_R"      : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_R,        // 0x990 
+    "INTR_BRF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_R"     : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_R,       // 0x994
+    // 0x998..0x9fc 
+    "INTR_BRF_ERROR_INTERNAL_INTR_COUNT_INCR_R"     : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R,       // 0xa00
+    "INTR_BRF_ERROR_INV_DEV_INTR_COUNT_INCR_R"      : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INV_DEV_INTR_COUNT_INCR_R,        // 0xa04
+    "INTR_BRF_ERROR_CMD_FAIL_INTR_COUNT_INCR_R"     : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_CMD_FAIL_INTR_COUNT_INCR_R,       // 0xa08
+    "INTR_BRF_ERROR_BAD_FUSE_INTR_COUNT_INCR_R"     : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_BAD_FUSE_INTR_COUNT_INCR_R,       // 0xa0c
+    "INTR_BRF_ERROR_ICCM_BLOCKED_INTR_COUNT_INCR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_ICCM_BLOCKED_INTR_COUNT_INCR_R,   // 0xa10
+    "INTR_BRF_ERROR_MBOX_ECC_UNC_INTR_COUNT_INCR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_MBOX_ECC_UNC_INTR_COUNT_INCR_R,   // 0xa14
+    "INTR_BRF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_INCR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_INCR_R,  // 0xa18  
+    "INTR_BRF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_INCR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_INCR_R,  // 0xa1c  
+    "INTR_BRF_NOTIF_CMD_AVAIL_INTR_COUNT_INCR_R"       : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_CMD_AVAIL_INTR_COUNT_INCR_R,    // 0xa20
+    "INTR_BRF_NOTIF_MBOX_ECC_COR_INTR_COUNT_INCR_R"    : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_INCR_R, // 0xa24   
+    "INTR_BRF_NOTIF_DEBUG_LOCKED_INTR_COUNT_INCR_R"    : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_INCR_R, // 0xa28 
+    "INTR_BRF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R"    : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R, // 0xa2c
+
+    // SHA Accelerator Interrupt Block Registers
+    "SHA_ACC_INTR_BRF_GLOBAL_INTR_EN_R"                : SHAACC_BASE + `SHA512_ACC_CSR_INTR_BLOCK_RF_GLOBAL_INTR_EN_R,                  // 0x800   Per-Type Intr Enable Reg   
+    "SHA_ACC_INTR_BRF_ERROR_INTR_EN_R"                 : SHAACC_BASE + `SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_EN_R,                   // 0x804   Per-Event Intr Enable Reg  
+    "SHA_ACC_INTR_BRF_NOTIF_INTR_EN_R"                 : SHAACC_BASE + `SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTR_EN_R,                   // 0x808   Per-Event Intr Enable Reg  
+    "SHA_ACC_INTR_BRF_ERROR_GLOBAL_INTR_R"             : SHAACC_BASE + `SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R,               // 0x80C   Intr Status Agg Reg type def    
+    "SHA_ACC_INTR_BRF_NOTIF_GLOBAL_INTR_R"             : SHAACC_BASE + `SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R,               // 0x810   Intr Status Agg Reg type def    
+    "SHA_ACC_INTR_BRF_ERROR_INTERNAL_INTR_R"           : SHAACC_BASE + `SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R,             // 0x814   Intr Status Reg type def    
+    "SHA_ACC_INTR_BRF_NOTIF_INTERNAL_INTR_R"           : SHAACC_BASE + `SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R,             // 0x818   Intr Status Reg type def    
+    "SHA_ACC_INTR_BRF_ERROR_INTR_TRIG_R"               : SHAACC_BASE + `SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_TRIG_R,                 // 0x81C   Intr Trigger Reg type def   
+    "SHA_ACC_INTR_BRF_NOTIF_INTR_TRIG_R"               : SHAACC_BASE + `SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R,                 // 0x820   Intr Trigger Reg type def   
+    // 0x824..0x8fc   
+    "SHA_ACC_INTR_BRF_ERROR0_INTR_COUNT_R"             : SHAACC_BASE + `SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR0_INTR_COUNT_R,               // 0x900   Intr Event Counter  
+    "SHA_ACC_INTR_BRF_ERROR1_INTR_COUNT_R"             : SHAACC_BASE + `SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR1_INTR_COUNT_R,               // 0x904   Intr Event Counter  
+    "SHA_ACC_INTR_BRF_ERROR2_INTR_COUNT_R"             : SHAACC_BASE + `SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR2_INTR_COUNT_R,               // 0x908   Intr Event Counter  
+    "SHA_ACC_INTR_BRF_ERROR3_INTR_COUNT_R"             : SHAACC_BASE + `SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR3_INTR_COUNT_R,               // 0x90C   Intr Event Counter  
+    // 0x910..0x97c 
+    "SHA_ACC_INTR_BRF_NOTIF_CMD_DONE_INTR_COUNT_R"     : SHAACC_BASE + `SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_R,       // 0x980   Intr Event Counter  
+    // 0x984..0x9fc
+    "SHA_ACC_INTR_BRF_ERROR0_INTR_COUNT_INCR_R"        : SHAACC_BASE + `SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R,          // 0xa00   Intr Event Count Incr
+    "SHA_ACC_INTR_BRF_ERROR1_INTR_COUNT_INCR_R"        : SHAACC_BASE + `SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R,          // 0xa04   Intr Event Count Incr
+    "SHA_ACC_INTR_BRF_ERROR2_INTR_COUNT_INCR_R"        : SHAACC_BASE + `SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R,          // 0xa08   Intr Event Count Incr
+    "SHA_ACC_INTR_BRF_ERROR3_INTR_COUNT_INCR_R"        : SHAACC_BASE + `SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R,          // 0xa0C   Intr Event Count Incr
+    "SHA_ACC_INTR_BRF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R": SHAACC_BASE + `SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R   // 0xa10   Intr Event Count Incr
   };
-
-
+                                                                                        
+  
   // These address ranges (inclusive) in each extent have no definition 
   extent_t _undefined_addr_ranges [$] = {
-    '{addr_min: SOCIFC_BASE + 16'h0104, addr_max: SOCIFC_BASE + 16'h01fc},
-    '{addr_min: SOCIFC_BASE + 16'h0340, addr_max: SOCIFC_BASE + 16'h05fc},
-    '{addr_min: SOCIFC_BASE + 16'h0630, addr_max: SOCIFC_BASE + 16'h07fc},
+    '{addr_min: SOCIFC_BASE + 16'h0128, addr_max: SOCIFC_BASE + 16'h01fc},
+    '{addr_min: SOCIFC_BASE + 16'h034c, addr_max: SOCIFC_BASE + 16'h05fc},
+    '{addr_min: SOCIFC_BASE + 16'h0650, addr_max: SOCIFC_BASE + 16'h07fc},
     '{addr_min: SOCIFC_BASE + 16'h0824, addr_max: SOCIFC_BASE + 16'h08fc},
     '{addr_min: SOCIFC_BASE + 16'h0920, addr_max: SOCIFC_BASE + 16'h097c},
-    '{addr_min: SOCIFC_BASE + 16'h0990, addr_max: SOCIFC_BASE + 16'h09fc}
+    '{addr_min: SOCIFC_BASE + 16'h0998, addr_max: SOCIFC_BASE + 16'h09fc}
   };
  
 
@@ -223,29 +278,48 @@ package soc_ifc_tb_pkg;
     "INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES" : 32'h5,
     "CPTRA_HW_REV_ID"                      : 32'h1,
     "CPTRA_WDT_TIMER1_TIMEOUT_PERIOD"      : 32'hffff_ffff,
-    "CPTRA_WDT_TIMER2_TIMEOUT_PERIOD"      : 32'hffff_ffff
+    "CPTRA_WDT_TIMER2_TIMEOUT_PERIOD"      : 32'hffff_ffff,
+    "CPTRA_FUSE_VALID_PAUSER"              : 32'hffff_ffff
   };
 
 
   // Sticky registers preserve values across warm reset -- groups of regs might be populated by code
   // mask of all bits to be protected in case of warm reset
   word_addr_t _sticky_register_prefix_dict [string] = {
-    "FUSE_":                                           32'hffff_ffff, 
-    "CPTRA_HW_ERROR_":                                 32'hffff_ffff, // FATAL, NON_FATAL, ENC                          
-    "CPTRA_FW_ERROR_":                                 32'hffff_ffff, // FATAL, NON_FATAL, ENC                          
-    "CPTRA_FW_EXTENDED_ERROR_INFO":                    32'hffff_ffff,
-    "CPTRA_RESET_REASON":                              32'h2,         // field WARM_RESET 
-    "CPTRA_FUSE_WR_DONE":                              32'h1,         // field 0 
-    "CPTRA_TIMER_CONFIG":                              32'hffff_ffff,                           
-    "INTR_BRF_ERROR_INTERNAL_INTR_R":                  32'h3f,        // fields 5:0
-    "INTR_BRF_ERROR_INTERNAL_INTR_COUNT_R":            32'hffff_ffff,          
-    "INTR_BRF_ERROR_INV_DEV_INTR_COUNT_R":             32'hffff_ffff,
-    "INTR_BRF_ERROR_CMD_FAIL_INTR_COUNT_R":            32'hffff_ffff,
-    "INTR_BRF_ERROR_BAD_FUSE_INTR_COUNT_R":            32'hffff_ffff,
-    "INTR_BRF_ERROR_ICCM_BLOCKED_INTR_COUNT_R":        32'hffff_ffff,
-    "INTR_BRF_ERROR_MBOX_ECC_UNC_INTR_COUNT_R":        32'hffff_ffff,
-    "INTR_BRF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_R":  32'hffff_ffff,
-    "INTR_BRF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_R":  32'hffff_ffff
+    "FUSE_UDS_SEED"                                    : 32'hffff_ffff,
+    "FUSE_FIELD_ENTROPY"                               : 32'hffff_ffff,
+    "FUSE_KEY_MANIFEST_PK_HASH"                        : 32'hffff_ffff ,
+    "FUSE_KEY_MANIFEST_PK_HASH_MASK"                   : 32'hf,          // field 3:0
+    "FUSE_OWNER_PK_HASH"                               : 32'hffff_ffff, 
+    "FUSE_FMC_KEY_MANIFEST_SVN"                        : 32'hffff_ffff, 
+    "FUSE_RUNTIME_SVN"                                 : 32'hffff_ffff, 
+    "FUSE_ANTI_ROLLBACK_DISABLE"                       : 32'h1,          // field 0
+    "FUSE_IDEVID_CERT_ATTR"                            : 32'hffff_ffff, 
+    "FUSE_IDEVID_MANUF_HSM_ID"                         : 32'hffff_ffff, 
+    "FUSE_LIFE_CYCLE"                                  : 32'h3,          // field 1:0
+    "FUSE_LMS_VERIFY"                                  : 32'h1,          // field 0
+    "FUSE_LMS_REVOCATION"                              : 32'hffff_ffff,
+    "FUSE_SOC_STEPPING_ID"                             : 32'hffff,       // field 15:0
+    "CPTRA_HW_ERROR_"                                  : 32'hffff_ffff,  // FATAL, NON_FATAL, ENC                          
+    "CPTRA_FW_ERROR_"                                  : 32'hffff_ffff,  // FATAL, NON_FATAL, ENC                          
+    "CPTRA_FW_EXTENDED_ERROR_INFO"                     : 32'hffff_ffff,
+    "CPTRA_RESET_REASON"                               : 32'h2,          // field WARM_RESET 
+    "CPTRA_FUSE_WR_DONE"                               : 32'h1,          // field 0 
+    "CPTRA_HW_REV_ID"                                  : 32'hffff_ffff,  // field SOC_STEPPING_ID, CPTRA_GENERATION
+    "CPTRA_FUSE_VALID_PAUSER"                          : 32'hffff_ffff,
+    "CPTRA_FUSE_PAUSER_LOCK"                           : 32'h1,
+    "CPTRA_TIMER_CONFIG"                               : 32'hffff_ffff,                           
+    "CPTRA_WDT_CFG"                                    : 32'hffff_ffff,                           
+    "INTERNAL_RV_MTIME"                                : 32'hffff_ffff, // for MTIME_L/H, MTIMECMP_L/H
+    "INTR_BRF_ERROR_INTERNAL_INTR_R"                   : 32'hff,        // fields 5:0
+    "INTR_BRF_ERROR_INTERNAL_INTR_COUNT_R"             : 32'hffff_ffff,          
+    "INTR_BRF_ERROR_INV_DEV_INTR_COUNT_R"              : 32'hffff_ffff,
+    "INTR_BRF_ERROR_CMD_FAIL_INTR_COUNT_R"             : 32'hffff_ffff,
+    "INTR_BRF_ERROR_BAD_FUSE_INTR_COUNT_R"             : 32'hffff_ffff,
+    "INTR_BRF_ERROR_ICCM_BLOCKED_INTR_COUNT_R"         : 32'hffff_ffff,
+    "INTR_BRF_ERROR_MBOX_ECC_UNC_INTR_COUNT_R"         : 32'hffff_ffff,
+    "INTR_BRF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_R"   : 32'hffff_ffff,
+    "INTR_BRF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_R"   : 32'hffff_ffff
   };
 
 
@@ -254,44 +328,130 @@ package soc_ifc_tb_pkg;
     "CPTRA_HW_CONFIG"                                  : (`SOC_IFC_REG_CPTRA_HW_CONFIG_ITRNG_EN_MASK |
                                                           `SOC_IFC_REG_CPTRA_HW_CONFIG_QSPI_EN_MASK  |                                                  
                                                           `SOC_IFC_REG_CPTRA_HW_CONFIG_I3C_EN_MASK),
-    "FUSE_ANTI_ROLLBACK_DISABLE"                       : `SOC_IFC_REG_FUSE_ANTI_ROLLBACK_DISABLE_DIS_MASK, 
-    "FUSE_KEY_MANIFEST_PK_HASH_MASK"                   : `SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_MASK_MASK,
-    "FUSE_LIFE_CYCLE"                                  : `SOC_IFC_REG_FUSE_LIFE_CYCLE_LIFE_CYCLE_MASK, 
-    "CPTRA_FLOW_STATUS"                                : (`SOC_IFC_REG_CPTRA_FLOW_STATUS_STATUS_MASK              |
-                                                           `SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_MASK       |
-                                                           `SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_RUNTIME_MASK  |
-                                                           `SOC_IFC_REG_CPTRA_FLOW_STATUS_MAILBOX_FLOW_DONE_MASK), 
+    "CPTRA_FLOW_STATUS"                                : (`SOC_IFC_REG_CPTRA_FLOW_STATUS_STATUS_MASK             |
+                                                          `SOC_IFC_REG_CPTRA_FLOW_STATUS_IDEVID_CSR_READY_MASK   |
+                                                          //`SOC_IFC_REG_CPTRA_FLOW_STATUS_BOOT_FSM_PS_MASK        |
+                                                          `SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_MASK       |
+                                                          `SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_RUNTIME_MASK  |
+                                                          //`SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FUSES_MASK    |
+                                                          `SOC_IFC_REG_CPTRA_FLOW_STATUS_MAILBOX_FLOW_DONE_MASK),
     "CPTRA_MBOX_PAUSER_LOCK"                           : `SOC_IFC_REG_CPTRA_MBOX_PAUSER_LOCK_0_LOCK_MASK,   // same for all 5 pausers
     "CPTRA_TRNG_PAUSER_LOCK"                           : `SOC_IFC_REG_CPTRA_TRNG_PAUSER_LOCK_LOCK_MASK,
+    "CPTRA_TRNG_CTRL"                                  : `SOC_IFC_REG_CPTRA_TRNG_CTRL_CLEAR_MASK,
     "CPTRA_TRNG_STATUS.APB"                            : `SOC_IFC_REG_CPTRA_TRNG_STATUS_DATA_WR_DONE_MASK, 
     "CPTRA_TRNG_STATUS.AHB"                            : `SOC_IFC_REG_CPTRA_TRNG_STATUS_DATA_REQ_MASK,     
     "CPTRA_FUSE_WR_DONE"                               : `SOC_IFC_REG_CPTRA_FUSE_WR_DONE_DONE_MASK,
     "CPTRA_BOOTFSM_GO"                                 : `SOC_IFC_REG_CPTRA_BOOTFSM_GO_GO_MASK, 
-
-    "CPTRA_CLK_GATING_EN"                              : `SOC_IFC_REG_CPTRA_CLK_GATING_EN_CLK_GATING_EN_MASK ,
+    "CPTRA_CLK_GATING_EN"                              : `SOC_IFC_REG_CPTRA_CLK_GATING_EN_CLK_GATING_EN_MASK,
+    "CPTRA_HW_REV_ID"                                  : (`SOC_IFC_REG_CPTRA_HW_REV_ID_CPTRA_GENERATION_MASK |  
+                                                          `SOC_IFC_REG_CPTRA_HW_REV_ID_SOC_STEPPING_ID_MASK), 
     "CPTRA_WDT_TIMER1_EN"                              : `SOC_IFC_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_MASK,
     "CPTRA_WDT_TIMER1_CTRL"                            : `SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART_MASK,
     "CPTRA_WDT_TIMER2_EN"                              : `SOC_IFC_REG_CPTRA_WDT_TIMER2_EN_TIMER2_EN_MASK,
     "CPTRA_WDT_TIMER2_CTRL"                            : `SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART_MASK,
     "CPTRA_WDT_STATUS"                                 : (`SOC_IFC_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_MASK | 
-                                                           `SOC_IFC_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_MASK),
+                                                          `SOC_IFC_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_MASK),
+    "CPTRA_FUSE_PAUSER_LOCK"                           : `SOC_IFC_REG_CPTRA_FUSE_PAUSER_LOCK_LOCK_MASK, 
+    "FUSE_ANTI_ROLLBACK_DISABLE"                       : `SOC_IFC_REG_FUSE_ANTI_ROLLBACK_DISABLE_DIS_MASK, 
+    "FUSE_KEY_MANIFEST_PK_HASH_MASK"                   : `SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_MASK_MASK,
+    "FUSE_LIFE_CYCLE"                                  : `SOC_IFC_REG_FUSE_LIFE_CYCLE_LIFE_CYCLE_MASK, 
+    "FUSE_LMS_VERIFY"                                  : `SOC_IFC_REG_FUSE_LMS_VERIFY_LMS_VERIFY_MASK,
+    "FUSE_SOC_STEPPING_ID"                             : `SOC_IFC_REG_FUSE_SOC_STEPPING_ID_SOC_STEPPING_ID_MASK,
     "INTERNAL_ICCM_LOCK"                               : `SOC_IFC_REG_INTERNAL_ICCM_LOCK_LOCK_MASK, 
-    "INTERNAL_FW_UPDATE_RESET"                         : `SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_CORE_RST_MASK ,
+    "INTERNAL_FW_UPDATE_RESET"                         : `SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_CORE_RST_MASK,
     "INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES"             : `SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES_WAIT_CYCLES_MASK,
-    "INTR_BRF_ERROR_INTERNAL_INTR_COUNT_INCR_R"        : `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R_PULSE_MASK    ,   
-    "INTR_BRF_ERROR_INV_DEV_INTR_COUNT_INCR_R"         : `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INV_DEV_INTR_COUNT_INCR_R_PULSE_MASK     ,
-    "INTR_BRF_ERROR_CMD_FAIL_INTR_COUNT_INCR_R"        : `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_CMD_FAIL_INTR_COUNT_INCR_R_PULSE_MASK    ,
-    "INTR_BRF_ERROR_BAD_FUSE_INTR_COUNT_INCR_R"        : `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_BAD_FUSE_INTR_COUNT_INCR_R_PULSE_MASK    ,
+    "INTERNAL_HW_ERROR_FATAL_MASK"                     : (`SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_NMI_PIN_MASK      | 
+                                                          `SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_DCCM_ECC_UNC_MASK |
+                                                          `SOC_IFC_REG_INTERNAL_HW_ERROR_FATAL_MASK_MASK_ICCM_ECC_UNC_MASK), 
+    "INTERNAL_HW_ERROR_NON_FATAL_MASK"                 : (`SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK_MASK_MBOX_PROT_NO_LOCK_MASK | 
+                                                          `SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK_MASK_MBOX_PROT_OOO_MASK     | 
+                                                          `SOC_IFC_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK_MASK_MBOX_ECC_UNC_MASK),      
+    "INTR_BRF_GLOBAL_INTR_EN_R"                        : (`SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK | 
+                                                          `SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK),    
+    "INTR_BRF_ERROR_INTR_EN_R"                        :  (`SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_INTERNAL_EN_MASK           |
+                                                          `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_INV_DEV_EN_MASK            |
+                                                          `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_CMD_FAIL_EN_MASK           |
+                                                          `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_BAD_FUSE_EN_MASK           |
+                                                          `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_ICCM_BLOCKED_EN_MASK       |
+                                                          `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_MBOX_ECC_UNC_EN_MASK       |
+                                                          `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_WDT_TIMER1_TIMEOUT_EN_MASK |
+                                                          `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_WDT_TIMER2_TIMEOUT_EN_MASK ),
+    "INTR_BRF_NOTIF_INTR_EN_R" :                        (`SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_AVAIL_EN_MASK     |
+                                                         `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_MBOX_ECC_COR_EN_MASK  |
+                                                         `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_DEBUG_LOCKED_EN_MASK  |
+                                                         `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_SCAN_MODE_EN_MASK     |                     
+                                                         `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_SOC_REQ_LOCK_EN_MASK  |
+                                                         `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_GEN_IN_TOGGLE_EN_MASK ),
+    "INTR_BRF_ERROR_GLOBAL_INTR_R" :                     `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK,
+    "INTR_BRF_NOTIF_GLOBAL_INTR_R" :                     `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK, 
+    "INTR_BRF_ERROR_INTERNAL_INTR_R":                   (`SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INTERNAL_STS_MASK            |
+                                                         `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK             |
+                                                         `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK            |
+                                                         `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_BAD_FUSE_STS_MASK            |
+                                                         `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_ICCM_BLOCKED_STS_MASK        |
+                                                         `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK        |
+                                                         `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK  |
+                                                         `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK  ),
+    "INTR_BRF_NOTIF_INTERNAL_INTR_R":                   (`SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK        |
+                                                         `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK     |
+                                                         `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK     |
+                                                         `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SCAN_MODE_STS_MASK        |
+                                                         `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_SOC_REQ_LOCK_STS_MASK     |
+                                                         `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK    ),
+    "INTR_BRF_ERROR_INTR_TRIG_R":                       (`SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_INTERNAL_TRIG_MASK            |
+                                                         `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_INV_DEV_TRIG_MASK             |
+                                                         `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_CMD_FAIL_TRIG_MASK            |
+                                                         `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_BAD_FUSE_TRIG_MASK            |
+                                                         `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_ICCM_BLOCKED_TRIG_MASK        |
+                                                         `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_MBOX_ECC_UNC_TRIG_MASK        |
+                                                         `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_WDT_TIMER1_TIMEOUT_TRIG_MASK  |
+                                                         `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR_WDT_TIMER2_TIMEOUT_TRIG_MASK  ),
+    "INTR_BRF_NOTIF_INTR_TRIG_R":                       (`SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_AVAIL_TRIG_MASK           |
+                                                         `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_MBOX_ECC_COR_TRIG_MASK        |
+                                                         `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_DEBUG_LOCKED_TRIG_MASK        |
+                                                         `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_SCAN_MODE_TRIG_MASK           |
+                                                         `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_SOC_REQ_LOCK_TRIG_MASK        |
+                                                         `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_GEN_IN_TOGGLE_TRIG_MASK       ),
+    "INTR_BRF_ERROR_INTERNAL_INTR_COUNT_INCR_R"        : `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R_PULSE_MASK,   
+    "INTR_BRF_ERROR_INV_DEV_INTR_COUNT_INCR_R"         : `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INV_DEV_INTR_COUNT_INCR_R_PULSE_MASK,
+    "INTR_BRF_ERROR_CMD_FAIL_INTR_COUNT_INCR_R"        : `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_CMD_FAIL_INTR_COUNT_INCR_R_PULSE_MASK,
+    "INTR_BRF_ERROR_BAD_FUSE_INTR_COUNT_INCR_R"        : `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_BAD_FUSE_INTR_COUNT_INCR_R_PULSE_MASK,
     "INTR_BRF_ERROR_ICCM_BLOCKED_INTR_COUNT_INCR_R"    : `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_ICCM_BLOCKED_INTR_COUNT_INCR_R_PULSE_MASK,
     "INTR_BRF_ERROR_MBOX_ECC_UNC_INTR_COUNT_INCR_R"    : `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_MBOX_ECC_UNC_INTR_COUNT_INCR_R_PULSE_MASK,
     "INTR_BRF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_INCR_R" : `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER1_TIMEOUT_INTR_COUNT_INCR_R_PULSE_MASK,
     "INTR_BRF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_INCR_R" : `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_WDT_TIMER2_TIMEOUT_INTR_COUNT_INCR_R_PULSE_MASK,
-    "INTR_BRF_NOTIF_CMD_AVAIL_INTR_COUNT_INCR_R"       : `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_CMD_AVAIL_INTR_COUNT_INCR_R_PULSE_MASK   ,
+    "INTR_BRF_NOTIF_CMD_AVAIL_INTR_COUNT_INCR_R"       : `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_CMD_AVAIL_INTR_COUNT_INCR_R_PULSE_MASK,
     "INTR_BRF_NOTIF_MBOX_ECC_COR_INTR_COUNT_INCR_R"    : `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_INCR_R_PULSE_MASK,
     "INTR_BRF_NOTIF_DEBUG_LOCKED_INTR_COUNT_INCR_R"    : `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_INCR_R_PULSE_MASK, 
-    "INTR_BRF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R"       : `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R_PULSE_MASK 
+    "INTR_BRF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R"    : `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R_PULSE_MASK,
+    // SHA Accelerator Interrupt Block Registers
+    "SHA_ACC_INTR_BRF_GLOBAL_INTR_EN_R"                :(`SHA512_ACC_CSR_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK |    
+                                                         `SHA512_ACC_CSR_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_NOTIF_EN_MASK ),
+    "SHA_ACC_INTR_BRF_ERROR_INTR_EN_R"                 :(`SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR0_EN_MASK |                
+                                                         `SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR1_EN_MASK |                
+                                                         `SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR2_EN_MASK |                
+                                                         `SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR3_EN_MASK ),               
+    "SHA_ACC_INTR_BRF_NOTIF_INTR_EN_R"                 : `SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTR_EN_R_NOTIF_CMD_DONE_EN_MASK,
+    "SHA_ACC_INTR_BRF_ERROR_GLOBAL_INTR_R"             : `SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_GLOBAL_INTR_R_AGG_STS_MASK,         
+    "SHA_ACC_INTR_BRF_NOTIF_GLOBAL_INTR_R"             : `SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_GLOBAL_INTR_R_AGG_STS_MASK,               
+    "SHA_ACC_INTR_BRF_ERROR_INTERNAL_INTR_R"           :(`SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR0_STS_MASK |         
+                                                         `SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR1_STS_MASK |         
+                                                         `SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR2_STS_MASK |         
+                                                         `SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR3_STS_MASK ),        
+    "SHA_ACC_INTR_BRF_NOTIF_INTERNAL_INTR_R"           : `SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_DONE_STS_MASK,  
+    "SHA_ACC_INTR_BRF_ERROR_INTR_TRIG_R"               :(`SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR0_TRIG_MASK |         
+                                                         `SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR1_TRIG_MASK |         
+                                                         `SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR2_TRIG_MASK |         
+                                                         `SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR_INTR_TRIG_R_ERROR3_TRIG_MASK ),        
+    "SHA_ACC_INTR_BRF_NOTIF_INTR_TRIG_R"               : `SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTR_TRIG_R_NOTIF_CMD_DONE_TRIG_MASK,
+    "SHA_ACC_INTR_BRF_ERROR0_INTR_COUNT_INCR_R"        : `SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR0_INTR_COUNT_INCR_R_PULSE_MASK,            
+    "SHA_ACC_INTR_BRF_ERROR1_INTR_COUNT_INCR_R"        : `SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR1_INTR_COUNT_INCR_R_PULSE_MASK,            
+    "SHA_ACC_INTR_BRF_ERROR2_INTR_COUNT_INCR_R"        : `SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR2_INTR_COUNT_INCR_R_PULSE_MASK,            
+    "SHA_ACC_INTR_BRF_ERROR3_INTR_COUNT_INCR_R"        : `SHA512_ACC_CSR_INTR_BLOCK_RF_ERROR3_INTR_COUNT_INCR_R_PULSE_MASK,            
+    "SHA_ACC_INTR_BRF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R": `SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_CMD_DONE_INTR_COUNT_INCR_R_PULSE_MASK     
   };  
 
+
   // holds addr -> name inverse map of _soc_register_dict - populated by SocRegisters instantiation 
   string _imap_soc_register_dict [word_addr_t]; 
 
@@ -312,7 +472,8 @@ package soc_ifc_tb_pkg;
     "INTR_BRF_NOTIF_CMD_AVAIL_INTR_COUNT_INCR_R"     ,
     "INTR_BRF_NOTIF_MBOX_ECC_COR_INTR_COUNT_INCR_R"  ,
     "INTR_BRF_NOTIF_DEBUG_LOCKED_INTR_COUNT_INCR_R"  , 
-    "INTR_BRF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R"       
+    "INTR_BRF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_INCR_R"        
+    // "INTR_BRF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_R"    // TODO. Check for saturation!
   }; 
 
 
@@ -327,7 +488,7 @@ package soc_ifc_tb_pkg;
     else 
       return -1;
 
-  endfunction
+  endfunction // get_ss_code
 
 
   function string get_ss_name(input int ss_code);
@@ -340,22 +501,21 @@ package soc_ifc_tb_pkg;
     end
     return "";
 
-  endfunction
+  endfunction // get_ss_name
 
 
   function dword_t get_mask(string addr_name);
 
     return _soc_register_mask_dict.exists(addr_name) ? _soc_register_mask_dict[addr_name] : 32'hffff_ffff; 
 
-  endfunction
-
+  endfunction // get_mask
 
 
   function dword_t get_initval(string addr_name);
 
     return _soc_register_initval_dict.exists(addr_name) ? _soc_register_initval_dict[addr_name] : '0; 
 
-  endfunction
+  endfunction // get_initval
 
 
   function void set_initval(string addr_name, dword_t value); 
@@ -366,11 +526,11 @@ package soc_ifc_tb_pkg;
       $display("TB INFO. Adding new register init value for %s with value 0x%08x", addr_name, value);
     _soc_register_initval_dict[addr_name] = value;
     
-  endfunction
+  endfunction // set_initval
 
 
   // Needs RMW of register without APB or AHB writes 
-  function dword_t update_CPTRA_SECURITY_STATE(logic scan_mode, logic debug_state, logic [1:0] lifecycle); 
+  function automatic dword_t update_CPTRA_SECURITY_STATE(logic scan_mode, logic debug_state, logic [1:0] lifecycle); 
 
     begin
       update_exp_regval("CPTRA_SECURITY_STATE", 
@@ -383,34 +543,61 @@ package soc_ifc_tb_pkg;
       return _exp_register_data_dict["CPTRA_SECURITY_STATE"];
     end 
 
-  endfunction 
+  endfunction // update_CPTRA_SECURITY_STATE
+
+
+  // Can update only 1 GENERIC_INPUT_WIRE bus at a time 
+  function automatic dword_t update_CPTRA_GENERIC_INPUT_WIRES(logic [31:0] generic_wires, bit upper);
+
+    begin
+      if (upper) begin
+        update_exp_regval("CPTRA_GENERIC_INPUT_WIRES1", generic_wires, SET_DIRECT);
+        $display ("TB INFO. CPTRA_GENERIC_INPUT_WIRES1 changed to 0x%08x", _exp_register_data_dict["CPTRA_GENERIC_INPUT_WIRES1"]); 
+        return _exp_register_data_dict["CPTRA_GENERIC_INPUT_WIRES1"];
+      end else begin
+        update_exp_regval("CPTRA_GENERIC_INPUT_WIRES0", generic_wires, SET_DIRECT);
+        $display ("TB INFO. CPTRA_GENERIC_INPUT_WIRES0 changed to 0x%08x", _exp_register_data_dict["CPTRA_GENERIC_INPUT_WIRES0"]); 
+        return _exp_register_data_dict["CPTRA_GENERIC_INPUT_WIRES0"];
+      end
+    end
+
+  endfunction // update_CPTRA_GENERIC_INPUT_WIRES
 
 
   // Needs RMW of register without APB or AHB writes 
-  function logic [63:0] update_CPTRA_GENERIC_INPUT_WIRES(logic [31:0] wires1, logic [31:0] wires0);
+  function automatic logic [31:0] update_INTR_BRF_NOTIF_INTERNAL_INTR_R(logic gen_input_wire_toggle, logic debug_locked); 
+
+    dword_t tmp_data;
 
     begin
-      update_exp_regval("CPTRA_GENERIC_INPUT_WIRES0", wires0, SET_DIRECT);
-      update_exp_regval("CPTRA_GENERIC_INPUT_WIRES1", wires1, SET_DIRECT);
 
-      $display ("TB INFO. Fields for CPTRA_GENERIC_INPUT_WIRES0 changed to 0x%08x", _exp_register_data_dict["CPTRA_GENERIC_INPUT_WIRES0"]); 
-      $display ("TB INFO. Fields for CPTRA_GENERIC_INPUT_WIRES1 changed to 0x%08x", _exp_register_data_dict["CPTRA_GENERIC_INPUT_WIRES1"]); 
-      return {_exp_register_data_dict["CPTRA_GENERIC_INPUT_WIRES1"], _exp_register_data_dict["CPTRA_GENERIC_INPUT_WIRES0"]};
-    end
+      tmp_data = _exp_register_data_dict["INTR_BRF_NOTIF_INTERNAL_INTR_R"];
+      // tmp_data = tmp_data & (32'hffff_ffff ^ `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK)    
+      //                     & (32'hffff_ffff ^ `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK); 
+      tmp_data = tmp_data | mask_shifted(debug_locked, `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_DEBUG_LOCKED_STS_MASK)
+                          | mask_shifted(gen_input_wire_toggle, `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK);
+      update_exp_regval("INTR_BRF_NOTIF_INTERNAL_INTR_R", tmp_data, SET_DIRECT);
 
-  endfunction
+      $display( "TB INFO. Updated expected value of INTR_BRF_NOTIF_INTERNAL_INTR_R = 0x%08x", _exp_register_data_dict["INTR_BRF_NOTIF_INTERNAL_INTR_R"]);
+      return _exp_register_data_dict["INTR_BRF_NOTIF_INTERNAL_INTR_R"];
+    end 
+
+  endfunction // update_INTR_BRF_NOTIF_INTERNAL_INTR_R
 
 
   // Needs RMW of register without APB or AHB writes 
-  function dword_t update_CPTRA_FLOW_STATUS(int fuse_ready_val);
+  function automatic dword_t update_CPTRA_FLOW_STATUS(int fuse_ready_val, logic [2:0] boot_fsm_ps);
 
     dword_t tmp_data;
 
     begin
-      tmp_data = _exp_register_data_dict["CPTRA_FLOW_STATUS"];
+
+      tmp_data = _exp_register_data_dict["CPTRA_FLOW_STATUS"]; // then preserve read-only bit fields per masks 
       tmp_data = tmp_data & (32'hffff_ffff ^ `SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FUSES_MASK);
       tmp_data = tmp_data | mask_shifted(fuse_ready_val, `SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FUSES_MASK);
-      // $display( "TB INFO. update_CPTRA_FLOW_STATUS(%d) at time %t. new tmp_data = 0x%08x", fuse_ready_val, $realtime, tmp_data); 
+      tmp_data = tmp_data & (32'hffff_ffff ^ `SOC_IFC_REG_CPTRA_FLOW_STATUS_BOOT_FSM_PS_MASK);
+      tmp_data = tmp_data | mask_shifted(boot_fsm_ps, `SOC_IFC_REG_CPTRA_FLOW_STATUS_BOOT_FSM_PS_MASK);
+      // $display( "TB DEBUG. update_CPTRA_FLOW_STATUS(%x, %x) at time %t. new tmp_data = 0x%08x", fuse_ready_val, boot_fsm_ps, $realtime, tmp_data); 
 
       update_exp_regval("CPTRA_FLOW_STATUS", tmp_data, SET_DIRECT); 
 
@@ -418,11 +605,11 @@ package soc_ifc_tb_pkg;
       return _exp_register_data_dict["CPTRA_FLOW_STATUS"];
     end 
 
-  endfunction 
+  endfunction // update_CPTRA_FLOW_STATUS
 
 
   // Needs RMW of register without APB or AHB writes 
-  function dword_t update_CPTRA_RESET_REASON(int wrm_rst, int fw_upd);
+  function automatic dword_t update_CPTRA_RESET_REASON(int wrm_rst, int fw_upd);
 
     begin
       update_exp_regval("CPTRA_RESET_REASON", 
@@ -434,7 +621,7 @@ package soc_ifc_tb_pkg;
       return _exp_register_data_dict["CPTRA_RESET_REASON"];
     end 
 
-  endfunction 
+  endfunction // update_CPTRA_RESET_REASON
 
 
   function void update_exp_regval(string addr_name, dword_t indata, access_t modify);
@@ -451,12 +638,12 @@ package soc_ifc_tb_pkg;
 
     dword_t sscode;
     dword_t tmp_data;
+    dword_t mask;
 
     begin
 
       addr = _soc_register_dict[addr_name];
       sscode = _soc_register_initval_dict["CPTRA_SECURITY_STATE"];
-      // _exp_update_time = $realtime; 
 
       if (modify == COLD_RESET) begin
         reset_exp_data();
@@ -473,14 +660,14 @@ package soc_ifc_tb_pkg;
         return;
       end
 
-      addr_name = _imap_soc_register_dict[addr];  
-
       // With direct modification responsibility is on caller to ensure mask fields are respected!!  
       if (modify == SET_DIRECT) begin
         _exp_register_data_dict[addr_name] = indata;
         if ((addr_name == "INTERNAL_FW_UPDATE_RESET") &  (indata[0] == 1'b1)) begin
-            _exp_register_data_dict["INTERNAL_ICCM_LOCK"] = '0;  
-            $display ("TB INFO: Cross modification - Writing '1' to INTERNAL_FW_UPDATE_RESET also reset INTERNAL_ICCM_LOCK"); 
+            // NOTE. The expected value of  INTERNAL_ICCM_LOCK must be updated outside of package, or at least outside of 
+            //       a function call since there could be a significant delay 
+            // _exp_register_data_dict["INTERNAL_ICCM_LOCK"] = '0;  
+            // $display ("TB INFO: Cross modification - Writing '1' to INTERNAL_FW_UPDATE_RESET also reset INTERNAL_ICCM_LOCK"); 
 
             tmp_data = _exp_register_data_dict["CPTRA_RESET_REASON"]; 
             tmp_data = tmp_data & (32'hffff_ffff ^ `SOC_IFC_REG_CPTRA_RESET_REASON_FW_UPD_RESET_MASK)  |
@@ -513,7 +700,17 @@ package soc_ifc_tb_pkg;
       end else if ((str_startswith(addr_name, "FUSE_UDS_SEED")) || (str_startswith(addr_name, "FUSE_FIELD_ENTROPY")))
         exp_data = '0; // not accessible over APB or AHB 
 
-      else if (str_startswith(addr_name, "FUSE_"))
+      else if (addr_name == "FUSE_SOC_STEPPING_ID") begin // Normal fuse register operation + cross modification of register
+        exp_data = fuses_locked ? curr_data : (ahb_rodata | apb_indata & get_mask(addr_name)); // ahb-RO 
+        $display ("TB INFO: Cross modification - Updating FUSE_SOC_STEPPING_ID also updates CPTRA_HW_REV_ID"); 
+
+        tmp_data = _exp_register_data_dict["CPTRA_HW_REV_ID"] & 
+                    mask_shifted(16'hffff, `SOC_IFC_REG_CPTRA_HW_REV_ID_CPTRA_GENERATION_MASK); // pick out cptra_generation 
+        _exp_register_data_dict["CPTRA_HW_REV_ID"] = 
+                    mask_shifted(tmp_data, `SOC_IFC_REG_CPTRA_HW_REV_ID_CPTRA_GENERATION_MASK) |  // add back cptra_generation 
+                    mask_shifted(exp_data, `SOC_IFC_REG_CPTRA_HW_REV_ID_SOC_STEPPING_ID_MASK);    // and new stepping_id 
+
+      end else if (str_startswith(addr_name, "FUSE_"))
         exp_data = fuses_locked ? curr_data : (ahb_rodata | apb_indata & get_mask(addr_name)); // ahb-RO 
 
       else if (str_startswith(addr_name, "CPTRA_MBOX_VALID_PAUSER")) begin    // find equivalent pauser lock & if set, apb-RO 
@@ -537,25 +734,64 @@ package soc_ifc_tb_pkg;
       else if (str_startswith(addr_name, "CPTRA_HW_CONFIG"))
         exp_data = curr_data & get_mask("CPTRA_HW_CONFIG"); // all bits are RO 
 
-      else if (str_startswith(addr_name, "CPTRA_WDT_TIMER1_TIMEOUT_PERIOD"))
-        exp_data = ahb_indata | apb_rodata; 
-
-      else if (str_startswith(addr_name, "CPTRA_WDT_TIMER2_TIMEOUT_PERIOD"))
+      else if (str_startswith(addr_name, "CPTRA_WDT_TIMER1_TIMEOUT_PERIOD") ||           
+               str_startswith(addr_name, "CPTRA_WDT_TIMER2_TIMEOUT_PERIOD")) 
         exp_data = ahb_indata | apb_rodata; 
 
       else if (str_startswith(addr_name, "INTERNAL_OBF_KEY"))            
         exp_data = '0;  // not accessible over APB or AHB 
 
-      else if (str_startswith(addr_name, "INTR_BRF_")) 
-        exp_data = ahb_indata & get_mask(addr_name) | apb_rodata;
+      else if (str_startswith(addr_name, "SHA_ACC_INTR_BRF"))
+        if (str_endswith(addr_name, "INCR_R"))
+          exp_data = ahb_rodata | apb_rodata; 
+        else if ((addr_name == "SHA_ACC_INTR_BRF_ERROR_GLOBAL_INTR_R") || (addr_name == "SHA_ACC_INTR_BRF_NOTIF_GLOBAL_INTR_R"))
+          exp_data = ahb_rodata | apb_rodata; 
+        else
+          exp_data = ahb_indata & get_mask(addr_name) | apb_rodata; 
+
+      else if (str_startswith(addr_name, "INTR_BRF_")) begin // Interrupt block has its own sub-cases
+
+        if (is_pulsed_reg(addr_name)) begin
+          exp_data = '0;
+          
+        end else begin
+          case (addr_name)
+
+            "INTR_BRF_ERROR_GLOBAL_INTR_R":exp_data = ahb_rodata | apb_rodata; // set by HW  
+            "INTR_BRF_NOTIF_GLOBAL_INTR_R":exp_data = ahb_rodata | apb_rodata; // set by HW  
+            "INTR_BRF_ERROR_INTR_TRIG_R": exp_data = ((ahb_indata & get_mask(addr_name)) != 0) ? '0: apb_rodata; // TODO. Pulsed reg 
+            "INTR_BRF_NOTIF_INTR_TRIG_R": exp_data = ((ahb_indata & get_mask(addr_name)) != 0) ? '0: apb_rodata; // TODO. Pulsed reg 
+            "INTR_BRF_ERROR_INTERNAL_INTR_R": exp_data = apb_rodata | (~(ahb_indata & get_mask(addr_name)) & curr_data);
+            "INTR_BRF_NOTIF_INTERNAL_INTR_R": exp_data = apb_rodata | (~(ahb_indata & get_mask(addr_name)) & curr_data);
+
+            default: exp_data = ahb_indata & get_mask(addr_name) | apb_rodata;
+
+          endcase
+
+        end
 
-      else begin    
+      end else begin    
         
         case (addr_name)
+    
+          "CPTRA_HW_ERROR_FATAL", "CPTRA_HW_ERROR_NON_FATAL": begin
+            exp_data = ahb_indata | apb_indata;  
+            exp_data = '0; // write-one to clear -- effectively always 0
+          end
 
-          "CPTRA_FLOW_STATUS"                    : exp_data = ahb_indata & get_mask(addr_name) | apb_rodata; //  32'hbfff_ffff; // apb-RO 
-          "CPTRA_RESET_REASON"                   : exp_data = ahb_rodata | apb_rodata; //  bit 1:0 is RO 
-          "CPTRA_SECURITY_STATE"                 : exp_data = curr_data & get_mask(addr_name); // & sscode;  //  bit 3:0 is RO 
+          "CPTRA_FLOW_STATUS" : begin
+            if (modify == SET_APB) //  apb-RO 
+              exp_data = apb_rodata;
+            else if (modify == SET_AHB) begin // some fields are ro
+              mask = get_mask(addr_name);
+              exp_data = (mask & ahb_indata) | (~mask & curr_data); 
+              // $display ("TB DEBUG: for CPTRA_FLOW_STATUS ahb_indata = 0x%08x, curr_data = 0x%08x, exp_data = 0x%08x", 
+              //   ahb_indata, curr_data, exp_data); 
+            end
+          end
+
+          "CPTRA_RESET_REASON"                       : exp_data = ahb_rodata | apb_rodata; //  bit 1:0 is RO 
+          "CPTRA_SECURITY_STATE"                     : exp_data = curr_data & get_mask(addr_name); // & sscode;  //  bit 3:0 is RO 
 
           "CPTRA_TRNG_VALID_PAUSER" : begin // find equivalent pauser lock & if set, apb-RO 
             pauser_locked = _exp_register_data_dict["CPTRA_TRNG_PAUSER_LOCK"]; 
@@ -564,10 +800,12 @@ package soc_ifc_tb_pkg;
 
           "CPTRA_TRNG_PAUSER_LOCK": begin
             lock_mask = get_mask(addr_name); 
-            pauser_locked = curr_data & get_mask(addr_name); // FIXME. Is it?
+            pauser_locked = curr_data & get_mask(addr_name); // TODO. TRNG registers may need exclusion 
             exp_data = pauser_locked ? curr_data & lock_mask :  (ahb_indata | apb_indata) & lock_mask;  
           end
 
+          "CPTRA_TRNG_CTRL"                          : exp_data = apb_rodata; // pulsed w/ahb 
+
           "CPTRA_TRNG_STATUS": begin                                        //                   WR_DONE        REQ
             dword_t ahb_mask = get_mask("CPTRA_TRNG_STATUS.AHB"); 
             dword_t apb_mask = get_mask("CPTRA_TRNG_STATUS.APB"); 
@@ -575,16 +813,27 @@ package soc_ifc_tb_pkg;
                        (apb_rodata & ~apb_mask | apb_indata & apb_mask) ;   // SOC Access:            RW         RO
           end
 
-          "CPTRA_HW_REV_ID"                                 : exp_data = curr_data;  
-          "CPTRA_WDT_TIMER1_EN"                             : exp_data = ahb_indata & get_mask(addr_name) | apb_rodata;
-          "CPTRA_WDT_TIMER1_CTRL"                           : exp_data = ahb_indata & get_mask(addr_name) | apb_rodata;
-          "CPTRA_WDT_TIMER2_EN"                             : exp_data = ahb_indata & get_mask(addr_name) | apb_rodata;
-          "CPTRA_WDT_TIMER2_CTRL"                           : exp_data = ahb_indata & get_mask(addr_name) | apb_rodata;
-          "CPTRA_WDT_STATUS"                                : exp_data = curr_data; 
-          "CPTRA_FUSE_WR_DONE"                              : exp_data = fuses_locked ? curr_data : (ahb_rodata | apb_indata & get_mask(addr_name)); 
-          "CPTRA_BOOTFSM_GO"                                : exp_data = ahb_rodata | apb_indata & get_mask(addr_name) ; 
-          "CPTRA_BOOT_STATUS"                               : exp_data = ahb_indata | apb_rodata; 
-          "CPTRA_CLK_GATING_EN"                             : exp_data = ahb_rodata | apb_indata & get_mask(addr_name) ; 
+          "CPTRA_HW_REV_ID"                          : exp_data = curr_data;  
+          "CPTRA_WDT_TIMER1_EN"                      : exp_data = ahb_indata & get_mask(addr_name) | apb_rodata;
+          "CPTRA_WDT_TIMER1_CTRL"                    : exp_data = ((ahb_indata & get_mask(addr_name)) != 0) ? '0: apb_rodata; // TODO. Pulsed reg
+          "CPTRA_WDT_TIMER2_EN"                      : exp_data = ahb_indata & get_mask(addr_name) | apb_rodata;
+          "CPTRA_WDT_TIMER2_CTRL"                    : exp_data = ((ahb_indata & get_mask(addr_name)) != 0) ? '0: apb_rodata; // TODO. Pulsed reg 
+          "CPTRA_WDT_STATUS"                         : exp_data = curr_data; 
+          "CPTRA_FUSE_WR_DONE"                       : exp_data = fuses_locked ? curr_data : (ahb_rodata | apb_indata & get_mask(addr_name)); 
+          "CPTRA_BOOTFSM_GO"                         : exp_data = ahb_rodata | apb_indata & get_mask(addr_name) ; 
+          "CPTRA_BOOT_STATUS"                        : exp_data = ahb_indata | apb_rodata; 
+          "CPTRA_CLK_GATING_EN"                      : exp_data = ahb_rodata | apb_indata & get_mask(addr_name) ; 
+
+          "CPTRA_FUSE_VALID_PAUSER" : begin // find equivalent pauser lock & if set, apb-RO 
+            pauser_locked = _exp_register_data_dict["CPTRA_FUSE_PAUSER_LOCK"]; 
+            exp_data = pauser_locked ? curr_data : (ahb_indata | apb_indata); 
+          end
+
+          "CPTRA_FUSE_PAUSER_LOCK": begin
+            lock_mask = get_mask(addr_name); 
+            pauser_locked = curr_data & get_mask(addr_name); 
+            exp_data = pauser_locked ? curr_data & lock_mask :  (ahb_indata | apb_indata) & lock_mask;  
+          end 
 
           "INTERNAL_ICCM_LOCK"                              : begin
             iccm_locked = curr_data & get_mask(addr_name); 
@@ -594,22 +843,31 @@ package soc_ifc_tb_pkg;
           "INTERNAL_FW_UPDATE_RESET"                        : begin
             exp_data = ahb_indata & get_mask(addr_name) | apb_rodata; 
 
-            $display ("TB DEBUG: ahb_indata = 0x%x and exp_data for INTERNAL_FW_UPDATE_RESET = 0x%x", ahb_indata, exp_data); 
-            //TODO. Remove hardcoded fields and use bit masks instead
-            if (exp_data[0]) begin 
-              _exp_register_data_dict["INTERNAL_ICCM_LOCK"] = '0;  
-              $display ("TB INFO: Cross modification - Writing '1' to INTERNAL_FW_UPDATE_RESET also reset INTERNAL_ICCM_LOCK"); 
+            // $display ("TB DEBUG: ahb_indata = 0x%x and exp_data for INTERNAL_FW_UPDATE_RESET = 0x%x", ahb_indata, exp_data); 
+            if (exp_data[0]) begin  // write-one to clear
+            // NOTE. The expected value of  INTERNAL_ICCM_LOCK must be updated outside of package, or at least outside of 
+            //       a function call since there could be a significant delay
+            //  _exp_register_data_dict["INTERNAL_ICCM_LOCK"] = '0;  
+            //  $display ("TB INFO: Cross modification - Writing '1' to INTERNAL_FW_UPDATE_RESET also reset INTERNAL_ICCM_LOCK"); 
 
-              _exp_register_data_dict["CPTRA_RESET_REASON"] = 32'h1;  //FIXME. Ignoring warm reset for now 
+              _exp_register_data_dict["CPTRA_RESET_REASON"] = 32'h1;  //TODO. Ignoring warm reset for now 
               $display ("-- CPTRA_RESET_REASON is now %d", _exp_register_data_dict["CPTRA_RESET_REASON"]); 
               $display ("TB INFO: Cross modification - Writing '1' to INTERNAL_FW_UPDATE_RESET also sets CPTRA_RESET_REASON"); 
             end
           end
 
-          "INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES"            : exp_data = ahb_indata & get_mask(addr_name) | apb_rodata;  
-          "INTERNAL_NMI_VECTOR"                             : exp_data = ahb_indata | apb_rodata;  
+          "INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES"     : exp_data = ahb_indata & get_mask(addr_name) | apb_rodata;  
+          "INTERNAL_NMI_VECTOR"                      : exp_data = ahb_indata | apb_rodata;  
+          "INTERNAL_HW_ERROR_FATAL_MASK"             : exp_data = ahb_indata & get_mask(addr_name) | apb_rodata;  
+          "INTERNAL_HW_ERROR_NON_FATAL_MASK"         : exp_data = ahb_indata & get_mask(addr_name) | apb_rodata;  
+          "INTERNAL_FW_ERROR_FATAL_MASK"             : exp_data = ahb_indata | apb_rodata;  
+          "INTERNAL_FW_ERROR_NON_FATAL_MASK"         : exp_data = ahb_indata | apb_rodata;  
+          "INTERNAL_RV_MTIME_L"                      : exp_data = ahb_indata | apb_rodata;
+          "INTERNAL_RV_MTIME_H"                      : exp_data = ahb_indata | apb_rodata;
+          "INTERNAL_RV_MTIMECMP_L"                   : exp_data = ahb_indata | apb_rodata;
+          "INTERNAL_RV_MTIMECMP_H"                   : exp_data = ahb_indata | apb_rodata;
 
-          default: exp_data = indata;
+          default: exp_data = indata & get_mask(addr_name); 
 
         endcase
 
@@ -621,7 +879,7 @@ package soc_ifc_tb_pkg;
   endfunction // update_exp_regval
 
 
-  function strq_t get_soc_regnames();
+  function automatic strq_t get_soc_regnames();
 
     strq_t soc_regs; 
 
@@ -631,10 +889,10 @@ package soc_ifc_tb_pkg;
 
     return soc_regs;
 
-  endfunction
+  endfunction // get_soc_regnames
 
 
-  function strq_t get_fuse_regnames();
+  function automatic strq_t get_fuse_regnames();
 
     strq_t fuse_regs; 
 
@@ -645,24 +903,52 @@ package soc_ifc_tb_pkg;
 
     return fuse_regs;
 
-  endfunction
+  endfunction // get_fuse_regnames
 
 
-  function strq_t get_intr_block_regnames();
+  function automatic strq_t get_intrblk_regnames();
 
     strq_t intr_regs; 
 
     foreach (_soc_register_dict[rkey]) begin
-      if (rkey.substr(0,7) == "INTR_BRF")
+      if (str_startswith(rkey, "INTR_BRF"))
         intr_regs.push_back(rkey); 
     end 
 
     return intr_regs;
 
-  endfunction
+  endfunction // get_intrblk_regnames
+
+
+  function automatic strq_t get_sha_acc_intrblk_regnames();
+
+    strq_t sha_intr_regs; 
+
+    foreach (_soc_register_dict[rkey]) begin
+      if (str_startswith(rkey, "SHA_ACC_INTR_BRF"))
+        sha_intr_regs.push_back(rkey); 
+    end 
+
+    return sha_intr_regs;
+
+  endfunction // get_intrblk_regnames
+
+
+  function automatic strq_t get_intrblk_regnames_minus_incr();
 
+    strq_t intr_regs; 
+
+    foreach (_soc_register_dict[rkey]) begin
+      if (str_startswith(rkey, "INTR_BRF") && !str_endswith(rkey, "INCR_R"))
+        intr_regs.push_back(rkey); 
+    end 
+
+    return intr_regs;
+
+  endfunction // get_intrblk_regnames_minus_incr
 
-  function strq_t get_soc_regnames_minus_fuse();
+
+  function automatic strq_t get_soc_regnames_minus_fuse();
 
     strq_t soc_regs; 
 
@@ -673,10 +959,10 @@ package soc_ifc_tb_pkg;
 
     return soc_regs;
 
-  endfunction
+  endfunction // get_soc_regnames_minus_fuse
 
 
-  function strq_t get_soc_regnames_minus_intr();
+  function automatic strq_t get_soc_regnames_minus_intr();
 
     strq_t soc_regs; 
 
@@ -687,25 +973,27 @@ package soc_ifc_tb_pkg;
 
     return soc_regs;
 
-  endfunction
-
+  endfunction // get_soc_regnames_minus_intr
 
 
-  function strq_t get_soc_regnames_minus_fuse_intr();
+  function automatic strq_t get_soc_regnames_minus_fuse_intr();
 
     strq_t soc_regs; 
 
     foreach (_soc_register_dict[rkey]) begin
-      if ((rkey.substr(0,7) != "INTR_BRF") && (rkey.substr(0,3) != "FUSE"))
-        soc_regs.push_back(rkey); 
+      if (str_startswith(rkey, "INTR_BRF") || 
+          str_startswith(rkey, "SHA_ACC_INTR_BRF") || 
+          str_startswith(rkey, "FUSE")) 
+          continue;
+      soc_regs.push_back(rkey); 
     end 
 
     return soc_regs;
 
-  endfunction
+  endfunction // get_soc_regnames_minus_fuse_intr
 
 
-  function word_addrq_t get_undef_regs();
+  function automatic word_addrq_t get_undef_regs();
    // Just flattens and expands the extent ranges into a single queue 
 
     word_addrq_t undef_addrs; 
@@ -727,21 +1015,22 @@ package soc_ifc_tb_pkg;
 
     return undef_addrs;
 
-  endfunction 
+  endfunction  // get_undef_regs
         
 
-  function void reset_exp_data();
+  function automatic void reset_exp_data();
     // this peforms update for power-on reset
 
     begin
       $display ("** Clearing all expected reg values for cold reset **");
-      foreach (_soc_register_dict[rname]) 
+      foreach (_soc_register_dict[rname]) begin
         _exp_register_data_dict[rname] = get_initval(rname); 
+      end
     end
-  endfunction 
+  endfunction // reset_exp_data
 
 
-  function void warm_reset_exp_data();
+  function automatic void warm_reset_exp_data();
     // Unlike reset_exp_data which assumes cold boot, this preserves sticky bits 
 
     int wrmrst_pfx_match = 0;
@@ -770,10 +1059,10 @@ package soc_ifc_tb_pkg;
       end
     end 
 
-  endfunction 
+  endfunction // warm_reset_exp_data();
 
 
-  function int is_pulsed_reg(string rname);
+  function automatic int is_pulsed_reg(string rname);
 
     string tmplist [$];
 
@@ -782,116 +1071,172 @@ package soc_ifc_tb_pkg;
       return (tmplist.size() > 0);
     end 
 
-  endfunction
-
-
-  /* Placeholder. Implement if we have multiple registers
-  function void handle_cross_reg_mods (string rname, dword_t wr_data, access_t wr_modifier);
-
-  endfunction
-  */ 
+  endfunction // is_pulsed_reg
 
 
   // ---------------------------------------------------------------------------
   // -- Generic Utility functions that have less to do with custom data types
   // ---------------------------------------------------------------------------
-  function int str_startswith(string s1, string s2);
+  function automatic logic str_startswith(string s1, string s2);
 
     return (s2 == s1.substr(0, s2.len() - 1));
 
-  endfunction  
+  endfunction  // str_startswith
+
+
+  function automatic int str_endswith(string s1, string s2);
+
+    int s1_eix = s1.len() - 1;  
+    int s2_eix = s2.len() - 1;  
+
+    return (s2 == s1.substr(s1_eix - s2_eix, s1_eix));
+
+  endfunction  // str_endswith
+
+
+  function automatic del_from_strq(inout strq_t mutable_strq, input string name);  
+  // NOTE. This function works ONLY for a single name that matches one-index
+
+    int iq [$];
+    int j;
+
+    iq = mutable_strq.find_index with (item == name); 
+    j = iq[0];
+    
+    mutable_strq.delete(j);
+
+  endfunction // del_from_strq
+
+
+  function automatic delm_from_strq(inout strq_t mutable_strq, input string pfx);  
+  // NOTE. This function works by deleting multiple names with matching prefix
+
+    strq_t filtq;
+
+    foreach(mutable_strq[i])  begin
+      if (str_startswith(mutable_strq[i], pfx))
+        continue;
+      filtq.push_back(mutable_strq[i]);
+    end
+
+    mutable_strq = {}; 
+    mutable_strq = filtq;
+
+  endfunction // delm_from_strq
 
 
   function automatic dword_t mask_shifted(dword_t v, dword_t n);
-  /* 
-    Shift val by number of bits that mask n has zeros on right, eg:
-    mask_shifted(32'h1, 32'h100) -> 0x100 // 8-bit shift ;
-    mask_shifted(32'h1, 32'h8000_0000); -> 0x8000_0000 // 31-bit shift
-    mask_shifted(32'h2, 32'h0003_0000) -> 0x0002_0000 // 16 bit shift
-    mask_shifted(32'h2, 32'h0006_0000) -> 0x0004_0000 // 17 bit shift 
-  */
-
-    int k;
-    int ones = $countones(n); 
-    dword_t a = {ones{1'b1}};
 
-    begin
-      for (k = 0; k < (32 - ones + 1); k++) begin
-        if ((a << k) == n) 
-          break;
+    /* Shift 'v' by number of bits that mask 'n' has zeros on right. Example:
+        v (bin):                                         1001 (0x9)       value to move 
+        n (bin):      0000_0000_0001_1110_0000_0000_0000_0000 (0x1e0000)  4-bit mask 
+        Return (bin): 0000_0000_0001_0010_0000_0000_0000_0000 (0x120000)  moved to mask position 
+    */
+
+    return v << count_trailing_zeros(n);
+  endfunction // mask_shifted
+
+
+  function automatic int count_trailing_zeros(dword_t n);
+
+    int k = 0;
+    dword_t nshift = n;
+
+      if (n == 0)  
+          return 32; 
+
+      while (k < 32) begin
+        if (n[k] == 1'b1)
+          break; 
+        k += 1;
       end
+      return k;
+
+  endfunction // count_trailing_zeros
 
-      return (v << k);
-    end 
 
-  endfunction  
+  function automatic void print_banner(string txtstr, string s = "-");
 
+      int L = txtstr.len(); 
+      $display({L{s}}); 
+      $display(txtstr); 
+      $display({L{s}});
 
+  endfunction // print_banner
 
   // ================================================================================ 
   // Class definitions 
-  // ================================================================================ */
+  // ================================================================================ 
 
+  // -------------------------------------------------------------------------------- 
   class WordTransaction;
+  // -------------------------------------------------------------------------------- 
 
     word_addr_t    addr; 
     rand dword_t   data;
     int            tid;    
 
-    function void update(word_addr_t addr, dword_t data, int tid);    
-
-      this.addr = addr;
-      this.data = data;
-      this.tid = tid;    
-
-    endfunction 
+    extern function void update(word_addr_t addr, dword_t data, int tid);    
+    extern function void update_byname(string addr_name, dword_t data, int tid);    
+    extern function void update_tid(int tid);    
+    extern function void update_data(dword_t data);
+    extern function void display(); 
+    extern function void copy_from(WordTransaction atrans); 
 
+  endclass // WordTransaction
 
-    function void update_byname(string addr_name, dword_t data, int tid);    
 
-      word_addr_t addr;
+  function void WordTransaction::update(word_addr_t addr, dword_t data, int tid);    
 
-      this.addr = _soc_register_dict[addr_name];  
-      this.data = data;
-      this.tid = tid;    
+    this.addr = addr;
+    this.data = data;
+    this.tid = tid;    
 
-    endfunction 
+  endfunction 
 
+  
+  function void WordTransaction::update_byname(string addr_name, dword_t data, int tid);    
 
-    function void update_tid(int tid);    
+    word_addr_t addr;
 
-      this.tid = tid; 
+    this.addr = _soc_register_dict[addr_name];  
+    this.data = data;
+    this.tid = tid;    
 
-    endfunction 
+  endfunction 
 
 
-    function void update_data(dword_t data);
+  function void WordTransaction::update_tid(int tid);    
 
-      this.data = data; 
+    this.tid = tid; 
 
-    endfunction 
+  endfunction 
 
 
-    function void display(); 
+  function void WordTransaction::update_data(dword_t data);
 
-      $display("Addr: 0x%08x, Data: 0x%08x, TID: %03d", addr, data, tid); 
+    this.data = data; 
 
-    endfunction
+  endfunction 
 
-    
-    function void copy_from(WordTransaction atrans); 
 
-      this.update(atrans.addr, atrans.data, atrans.tid);    
+  function void WordTransaction::display(); 
 
-    endfunction 
+    $display("Addr: 0x%08x, Data: 0x%08x, TID: %03d", addr, data, tid); 
 
+  endfunction
 
-  endclass // WordTransaction
+  
+  function void WordTransaction::copy_from(WordTransaction atrans); 
 
+    this.update(atrans.addr, atrans.data, atrans.tid);    
 
+  endfunction 
 
-  // ================================================================================ //
+  
+  // -------------------------------------------------------------------------------- 
   class SocRegisters;
+  // -------------------------------------------------------------------------------- 
     
     // once these static vars have been set, assoicated modifier functions should have no effect
     static int widereg_expanded = 0; 
@@ -900,391 +1245,471 @@ package soc_ifc_tb_pkg;
     static string security_state_name = "UNDEFINED2"; 
     static int undef_addr_built = 0; 
 
-    function new();
-      if (!widereg_expanded) begin
-        init_regs();
-        widereg_expanded = 1;
-      end
+    extern function new();
+    extern function lock_fuses();
+    extern function unlock_fuses();
+    extern function void build_inverse_addr_map();
+    extern function void init_regs();
+    extern function word_addr_t get_addr(string name);
+    extern function string get_name(word_addr_t addr);
+    extern function void update_security_state(string ssname);
+    extern function void display_exp_regs();      
+    extern function dword_t get_exp_regval(string rname);      
 
-      if (!imap_built) begin
-        build_inverse_addr_map();
-        imap_built = 1;
-      end 
+  endclass // SocRegisters
 
-      reset_exp_data();
-   
-    endfunction   
 
+  function SocRegisters::new();
+    if (!widereg_expanded) begin
+      init_regs();
+      widereg_expanded = 1;
+    end
 
-    function lock_fuses();
-      // assume over APB or some other means. NOTE that CPTRA_FUSE_WR_DONE 
-      // may be set from 1 to 0, which will have no effect on this variable. 
-      
-      _fuses_locked = 1;  // set this global var for now 
+    if (!imap_built) begin
+      build_inverse_addr_map();
+      imap_built = 1;
+    end 
 
-    endfunction   
+    reset_exp_data();
+ 
+  endfunction  // new 
 
 
-    function unlock_fuses();
-      // unset global var; done over cold boot, warm reset or mailbox command  
+  function SocRegisters::lock_fuses();
+    // assume over APB or some other means. NOTE that CPTRA_FUSE_WR_DONE 
+    // may be set from 1 to 0, which will have no effect on this variable. 
+    
+    _fuses_locked = 1;  // set this global var for now 
 
-      _fuses_locked = 0; 
+  endfunction  // lock_fuses 
 
-    endfunction   
 
+  function SocRegisters::unlock_fuses();
+    // unset global var; done over cold boot, warm reset or mailbox command  
 
-    function void build_inverse_addr_map();
+    _fuses_locked = 0; 
 
-      if (imap_built) 
-        return;
+  endfunction  // unlock_fuses 
+ 
 
-      foreach (_soc_register_dict[tmpstr]) 
-        _imap_soc_register_dict[_soc_register_dict[tmpstr]] = tmpstr;   
+  function void SocRegisters::build_inverse_addr_map();
 
-    endfunction  // build_inverse_addr_map
+    if (imap_built) 
+      return;
 
+    foreach (_soc_register_dict[tmpstr]) 
+      _imap_soc_register_dict[_soc_register_dict[tmpstr]] = tmpstr;   
 
-    function void init_regs();
-      // The default _soc_register_dict only has root addr name-value mappings for 
-      // simple 32-bit registers. Wider registers implemented as array need to be 
-      // populated w/a function
+  endfunction  // build_inverse_addr_map
 
-      word_addr_t start_addr;
-      int i;
-      string istr;
-      dword_t initval;
 
-      if (widereg_expanded) 
-        return;
+  function void SocRegisters::init_regs();
+    // The default _soc_register_dict only has root addr name-value mappings for 
+    // simple 32-bit registers. Wider registers implemented as array need to be 
+    // populated w/a function
 
-      foreach (_wide_register_dict[rname]) begin 
-        if (_soc_register_dict.exists(rname)) begin 
-          start_addr = _soc_register_dict[rname];
-          for (i = 0; i < _wide_register_dict[rname]; i++) begin
-            istr.itoa(i);
-            _soc_register_dict[{rname, istr}] = start_addr + 4*i; 
-          end
-          _soc_register_dict.delete(rname);
-        end else 
-          $display ("TB ERROR. Soc register and wide register data structures incomplete!");
-      end 
+    word_addr_t start_addr;
+    int i;
+    string istr;
+    dword_t initval;
+
+    if (widereg_expanded) 
+      return;
+
+    foreach (_wide_register_dict[rname]) begin 
+      if (_soc_register_dict.exists(rname)) begin 
+        start_addr = _soc_register_dict[rname];
+        for (i = 0; i < _wide_register_dict[rname]; i++) begin
+          istr.itoa(i);
+          _soc_register_dict[{rname, istr}] = start_addr + 4*i; 
+        end
+        _soc_register_dict.delete(rname);
+      end else 
+        $display ("TB ERROR. Soc register and wide register data structures incomplete!");
+    end 
 
-      // The same is done for 'reset' values of registers 
-      // Names that don't exist in _soc_register_initval_dict assume "0" values
-      foreach (_wide_register_dict[rname]) begin 
-        if (_soc_register_initval_dict.exists(rname)) begin 
-          initval = _soc_register_initval_dict[rname];
-          for (i = 0; i < _wide_register_dict[rname]; i++) begin
-            istr.itoa(i);
-            _soc_register_initval_dict[{rname, istr}] = initval;
-          end
-          _soc_register_initval_dict.delete(rname);
+    // The same is done for 'reset' values of registers 
+    // Names that don't exist in _soc_register_initval_dict assume "0" values
+    foreach (_wide_register_dict[rname]) begin 
+      if (_soc_register_initval_dict.exists(rname)) begin 
+        initval = _soc_register_initval_dict[rname];
+        for (i = 0; i < _wide_register_dict[rname]; i++) begin
+          istr.itoa(i);
+          _soc_register_initval_dict[{rname, istr}] = initval;
         end
+        _soc_register_initval_dict.delete(rname);
       end
+    end
 
-      // foreach (_soc_register_initval_dict[rname]) 
-      //   $display ("-- INIT VAL %30s <= 0x%08x", rname, _soc_register_initval_dict[rname]);
-
-    endfunction  // init_regs
+    // foreach (_soc_register_initval_dict[rname]) 
+    //   $display ("-- INIT VAL %30s <= 0x%08x", rname, _soc_register_initval_dict[rname]);
 
+  endfunction  // init_regs
 
-    function word_addr_t get_addr(string name);
 
-      if (_soc_register_dict.exists(name))
-        return _soc_register_dict[name];
-      else begin
-        $display("TB WARNING. Address %s not found in reg name->addr map. Returning 0", name); 
-        return '0; 
-      end
+  function word_addr_t SocRegisters::get_addr(string name);
 
-    endfunction // get_addr
+    if (_soc_register_dict.exists(name))
+      return _soc_register_dict[name];
+    else begin
+      $display("TB WARNING. Address %s not found in reg name->addr map. Returning 0", name); 
+      return '0; 
+    end
 
+  endfunction // get_addr
 
-    function string get_name(word_addr_t addr);
 
-      if (_imap_soc_register_dict.exists(addr))
-        return _imap_soc_register_dict[addr];
-      else begin
-        $display("TB WARNING. Address 0x%08x not found in reg addr->name map. Returning empty str", addr); 
-        return ""; 
-      end
+  function string SocRegisters::get_name(word_addr_t addr);
 
-    endfunction // get_name
+    if (_imap_soc_register_dict.exists(addr))
+      return _imap_soc_register_dict[addr];
+    else begin
+      $display("TB WARNING. Address 0x%08x not found in reg addr->name map. Returning empty str", addr); 
+      return ""; 
+    end
 
+  endfunction // get_name
 
-    // TODO. Separate into byname version:
-    //  function void update_security_state_byname(string ssname);
-    //  function void update_security_state(int sscode);
 
-    function void update_security_state(string ssname);
+  function void SocRegisters::update_security_state(string ssname);
 
-      security_state_name = ssname; 
+    security_state_name = ssname; 
 
-    endfunction 
+  endfunction // update_security_state
 
 
-    function void display_exp_regs();      
+  function void SocRegisters::display_exp_regs();      
 
-      $display ("\n\n-- Current state of expected register values --\n");
-      foreach (_exp_register_data_dict[rname]) begin
-        $display (" -- expected value of addr %-40s (0x%08x) = 0x%08x", 
-          rname, get_addr(rname), _exp_register_data_dict[rname]);
-      end
-      $display (" ---------------------------------------------\n "); 
+    $display ("\n\n-- Current state of expected register values --\n");
+    foreach (_exp_register_data_dict[rname]) begin
+      $display (" -- expected value of addr %-40s (0x%08x) = 0x%08x", 
+        rname, get_addr(rname), _exp_register_data_dict[rname]);
+    end
+    $display (" ---------------------------------------------\n "); 
 
-    endfunction // displaY_exp_regs
+  endfunction // display_exp_regs
 
 
-  endclass // SocRegisters
+  function dword_t SocRegisters::get_exp_regval(string rname);      
 
+    // $display (" -- expected value of addr %-40s (0x%08x) = 0x%08x", 
+    //   rname, get_addr(rname), _exp_register_data_dict[rname]);
+    return _exp_register_data_dict[rname];
+  endfunction // get_exp_regval
 
 
-  // ================================================================================ //
+  // -------------------------------------------------------------------------------- 
   class RegScoreboard;
+  // -------------------------------------------------------------------------------- 
 
     int err_count;
     transq_t addr_table [word_addr_t];      // store a queue of transactions for each address
 
-    function new();
+    extern function new();
+    extern function void record_reset_values(tid, access_t modify); 
+    extern function void record_entry(WordTransaction transaction, access_t modify); 
+    extern function intpair_t find_matching_transaction(word_addr_t addr, int tid); 
+    extern function int check_entry(WordTransaction transaction);
+    extern function int check_entry_inrange(WordTransaction transaction, int minval, int maxval);
+    extern function transq_t get_entries (string addr_name);
+    extern function transq_t get_entries_withtid (string addr_name, int tid);
+    extern function void del_entry_withtid(string addr_name, int tid);
+    extern function void del_entries(string addr_name);
+    extern function void del_all();
+    extern function void display_all();      
 
-      string tmpstr;
+  endclass // RegScoreboard
 
-      begin
-        err_count = 0;
-      end 
-    endfunction
 
+  function RegScoreboard::new();
 
-    function void record_reset_values(tid, access_t modify); 
-      // useful for reset of all registers 
+    string tmpstr;
 
-      word_addr_t addr;
-      transaction_t new_trans; 
-      dword_t sscode;
+    begin
+      err_count = 0;
+    end 
+  endfunction // new
 
-      if (modify == COLD_RESET)
-        reset_exp_data();
-      else if (modify == WARM_RESET)
-        warm_reset_exp_data();
-      else begin
-        $display ("TB ERROR. Mass update of registers unsupported w/access type %s", modify.name());
-        return;
-      end
 
-      foreach (_soc_register_dict[rname]) begin
-     
-        addr = _soc_register_dict[rname];
-        new_trans = {addr: addr, data: _exp_register_data_dict[rname], tid: tid};
-
-        if (addr_table.exists(addr)) 
-          addr_table[addr].push_back(new_trans); 
-        else 
-          addr_table[addr] = {new_trans}; 
-      end
+  function void RegScoreboard::record_reset_values(tid, access_t modify); 
+    // useful for reset of all registers 
 
-    endfunction 
+    word_addr_t addr;
+    transaction_t new_trans; 
+    dword_t sscode;
 
+    if (modify == COLD_RESET)
+      reset_exp_data();
+    else if (modify == WARM_RESET)
+      warm_reset_exp_data();
+    else begin
+      $display ("TB ERROR. Mass update of registers unsupported w/access type %s", modify.name());
+      return;
+    end
 
-    function void record_entry(WordTransaction transaction, access_t modify); 
-      // NOTE. when an entry is recorded, instead of storing the transaction
-      // the expected data is stored, so that comparison can be made later on  
-      // for a previous 'tid'.
+    foreach (_soc_register_dict[rname]) begin
+   
+      addr = _soc_register_dict[rname];
+      new_trans = {addr: addr, data: _exp_register_data_dict[rname], tid: tid};
 
-      word_addr_t addr = transaction.addr;
-      dword_t data = transaction.data;
-      int tid = transaction.tid;
-      dword_t sscode; 
+      if (addr_table.exists(addr)) 
+        addr_table[addr].push_back(new_trans); 
+      else 
+        addr_table[addr] = {new_trans}; 
+    end
 
-      transaction_t new_trans; 
-      dword_t exp_data; 
-      string addr_name;
+  endfunction  // record_reset_vaules
 
-      addr_name = _imap_soc_register_dict[addr];
-      update_exp_regval(addr_name, data, modify);
-      exp_data = _exp_register_data_dict[addr_name];
 
-      new_trans = {addr: addr, data: exp_data, tid: tid};
-      
-      if (addr_table.exists(addr)) begin
-        // $display ("INFO. Pushing new transaction into existing queue"); 
-        addr_table[addr].push_back(new_trans); 
+  function void RegScoreboard::record_entry(WordTransaction transaction, access_t modify); 
+    // NOTE. when an entry is recorded, instead of storing the transaction
+    // the expected data is stored, so that comparison can be made later on  
+    // for a previous 'tid'.
+
+    word_addr_t addr = transaction.addr;
+    dword_t data = transaction.data;
+    int tid = transaction.tid;
+    dword_t sscode; 
+
+    transaction_t new_trans; 
+    dword_t exp_data; 
+    string addr_name;
+
+    addr_name = _imap_soc_register_dict[addr];
+    update_exp_regval(addr_name, data, modify);
+    exp_data = _exp_register_data_dict[addr_name];
+
+    new_trans = {addr: addr, data: exp_data, tid: tid};
+    
+    if (addr_table.exists(addr)) begin
+      // $display ("INFO. Pushing new transaction into existing queue"); 
+      addr_table[addr].push_back(new_trans); 
+    end else begin
+      // $display ("Adding transaction for addr %x", addr);
+      addr_table[addr] = {new_trans}; 
+    end
+
+  endfunction // record_entry
+
+
+  function intpair_t RegScoreboard::find_matching_transaction(word_addr_t addr, int tid); 
+    // returns {data, valid} struct pair  
+    // Ideally searches through scoreboard table to fine matching transaction.  For 
+    // all practical purposes, for a register model only the most recent modication matters. 
+    // The code is kept for reference/future usage.
+
+    transaction_t temp_trans; 
+    intpair_t matched_p; 
+    transq_t qr; 
+
+    int err_found = 0;
+    int matched_d = 0; 
+
+    if (!addr_table.exists(addr)) begin
+      $display ("TB fault. Address %x does not exist", addr);
+      err_found = 1;
+    end else begin
+      qr = addr_table[addr];
+      if (qr.size() == 0) begin
+        $display ("TB fault. qr size is 0 for addr %x", addr); 
+        err_found = 1; 
+      end else if (qr.size() == 1) begin
+        // FIXME. This needs a better change. If a write to a register modified register model
+        //    (_exp_register_data_dict) and then some other reg operation modified that, this 
+        //    transaction's entry in scoreboard is no longer valid! Need TIMESTAMP!
+        //
+        // temp_trans = qr[0]; 
+        // matched_d = int'(temp_trans.data);
+
+        matched_d = int'(_exp_register_data_dict[_imap_soc_register_dict[addr]]);
       end else begin
-        // $display ("Adding transaction for addr %x", addr);
-        addr_table[addr] = {new_trans}; 
+        qr = addr_table[addr].find_first with(item.tid == tid); 
+        if (qr.size() == 0)  begin
+          $display ("TB fault. No transaction with id %d found for addr %x", tid, addr);
+          err_found = 1; 
+        end else if (qr.size() > 1) begin
+          $display ("TB fault. Multiple transactions with id %d found for addr %x", tid, addr);
+          err_found = 1; 
+      end else begin
+          // TODO. Same issue related to FIXME above.
+          // temp_trans = qr[0];
+          // matched_d = int'(temp_trans.data);
+
+          matched_d = int'(_exp_register_data_dict[_imap_soc_register_dict[addr]]);
+        end
       end
 
-    endfunction
+      if (err_found) 
+          $display("ERROR. No matching transaction with tid %d in Reg Scoreboard for addr = %s(0x%08x)",
+            tid, _imap_soc_register_dict[addr], addr);
+    end
 
+    err_count += err_found;   
+    matched_p = {d: matched_d, v: int'(err_found == 0)};
+    return matched_p; 
 
-    // TODO. Consider implementing deletion along with checking
-    //      returns cumulative (object.)error count
-    //      don't check tid if only one transaction
-    // function int check_anddel_entry(WordTransaction transaction);
+  endfunction // find_matching_transaction
 
 
-    function int check_entry(WordTransaction transaction);
-      // returns cumulative (object.)error count
-      // don't check tid if only one transaction
+  function int RegScoreboard::check_entry(WordTransaction transaction);
+    // returns cumulative (object.)error count - ignore tid if only one transaction
 
-      word_addr_t addr = transaction.addr;
-      dword_t data = transaction.data;
-      int tid = transaction.tid;
+    word_addr_t addr = transaction.addr;
+    dword_t data = transaction.data;
+    int tid = transaction.tid;
 
-      transaction_t temp_trans; 
+    intpair_t matched_p;
+    int err_found = 1; 
 
-      transq_t qr; 
-      int err_found = 0;
+    matched_p = find_matching_transaction(addr, tid);
 
-      if (!addr_table.exists(addr)) 
-        $display ("TB fault. Address %x does not exist", addr);
-      else begin
-        qr = addr_table[addr];
-        if (qr.size() == 0) begin
-          $display ("TB fault. qr size is 0 for addr %x", addr); 
-          err_found = 1; 
-        end else if (qr.size() == 1) begin
-          temp_trans = qr[0]; 
-          // FIXME. This needs a better change. If a write to a register modified register model
-          // (_exp_register_data_dict) and then some other reg operation modified that, this 
-          // transaction's entry in scoreboard is no longer valid!  
-          // err_found = int'(temp_trans.data != data);
-          err_found = int'(_exp_register_data_dict[_imap_soc_register_dict[addr]] != data);
-        end else begin
-          qr = addr_table[addr].find_first with(item.tid == tid); 
-          if (qr.size() == 0)  begin
-            $display ("TB fault. No transaction with id %d found for addr %x", tid, addr);
-            err_found = 1; 
-          end else if (qr.size() == 0) begin
-            $display ("TB fault. Multiple transactions with id %d found for addr %x", tid, addr);
-            err_found = 1; 
-        end else begin
-            temp_trans = qr[0];
-            // Same issue related to FIXME above.
-            // err_found = int'(temp_trans.data != data);
-            err_found = int'(_exp_register_data_dict[_imap_soc_register_dict[addr]] != data);
-          end
-        end
+    if (matched_p.v) 
+      err_found = int'(matched_p.d != data);
 
-        if (err_found) 
-            $display("ERROR from Reg Scoreboard for addr = %s(0x%08x); observed data = 0x%08x | expected data = 0x%08x",
-              _imap_soc_register_dict[addr], addr, data, qr[0].data); 
-      end
+    if (err_found) begin
+      $display("ERROR from Reg Scoreboard for addr = %s(0x%08x); observed data = 0x%08x | expected data = 0x%08x",
+        _imap_soc_register_dict[addr], addr, data, matched_p.d); 
+    end
 
-      err_count += err_found;   
-      return err_count;
+    err_count += err_found;   
+    return err_count; 
 
-    endfunction 
+  endfunction // check_entry 
 
 
-    function transq_t get_entries (string addr_name);
+  function int RegScoreboard::check_entry_inrange(WordTransaction transaction, int minval, int maxval);
+    // Just like RegScoreboard::check_entry but has range to compare against
 
-      word_addr_t addr; 
-      transq_t entries; // queue of transactions 
+    word_addr_t addr = transaction.addr;
+    dword_t data = transaction.data;
+    int tid = transaction.tid;
 
-      addr = _soc_register_dict[addr_name]; 
+    intpair_t matched_p;
+    int err_found = 1; 
 
-      if (addr_table.exists(addr)) begin
-        entries = addr_table[addr];  
-      end else 
-        $display("TB WARNING. get_entries: No addr %s (0x%08x) found in scoreboard", addr_name, addr);
+    matched_p = find_matching_transaction(addr, tid);
 
-      return entries;
+    if (matched_p.v)  // NOTE. ignore matching data since range needed
+      err_found = int'((data < minval) || (data > maxval));
 
-    endfunction 
+    if (err_found) begin
+      $display("ERROR from Reg Scoreboard for addr = %s(0x%08x); observed data = 0x%08x | expected data in [0x%08x, 0x%08x]",
+        _imap_soc_register_dict[addr], addr, data, minval, maxval); 
+    end
 
+    err_count += err_found;   
+    return err_count; 
 
-    function transq_t get_entries_withtid (string addr_name, int tid);
+  endfunction  // check_entry_in_range
 
-      word_addr_t addr; 
-      transq_t entries; // queue of transactions 
 
-      addr = _soc_register_dict[addr_name]; 
+  function transq_t RegScoreboard::get_entries (string addr_name);
 
-      if (addr_table.exists(addr)) begin
-        entries = addr_table[addr].find with(item.tid == tid); 
-      end else 
-        $display("TB WARNING. get_entries_withtid: No addr %s (0x%08x) found in scoreboard", addr_name, addr);
+    word_addr_t addr; 
+    transq_t entries; // queue of transactions 
 
-      return entries;
+    addr = _soc_register_dict[addr_name]; 
 
-    endfunction 
+    if (addr_table.exists(addr)) begin
+      entries = addr_table[addr];  
+    end else 
+      $display("TB WARNING. get_entries: No addr %s (0x%08x) found in scoreboard", addr_name, addr);
 
+    return entries;
 
-    function void del_entry_withtid(string addr_name, int tid);
+  endfunction  // get_entries
 
-      int qi [$]; 
-      int err_found = 0;
 
-      word_addr_t addr; 
+  function transq_t RegScoreboard::get_entries_withtid (string addr_name, int tid);
 
-      addr = _soc_register_dict[addr_name]; 
+    word_addr_t addr; 
+    transq_t entries; // queue of transactions 
 
-      if (!(addr_table.exists(addr))) begin
-        $display("TB WARNING. del_entry_withtid: No addr %s (0x%08x) found in scoreboard", addr_name, addr);
-        return;
-      end 
+    addr = _soc_register_dict[addr_name]; 
 
-      qi = addr_table[addr].find_index with(item.tid == tid); 
-      if (qi.size() == 0) 
-        $display("TB WARNING. No tid %d / addr (0x%08x) combination found in scoreboard", tid, addr);
-      else if (qi.size() == 1) 
-        addr_table.delete(addr);
-      else begin 
-        $display("TB WARNING. Multiple tid %d found for addr (0x%08x) in scoreboard", tid, addr);
-        foreach (qi[i]) 
-          addr_table[addr].delete(qi[i]);
-      end
+    if (addr_table.exists(addr)) begin
+      entries = addr_table[addr].find with(item.tid == tid); 
+    end else 
+      $display("TB WARNING. get_entries_withtid: No addr %s (0x%08x) found in scoreboard", addr_name, addr);
 
-    endfunction 
+    return entries;
 
+  endfunction // get_entries_withtid 
 
-    function void del_entries(string addr_name);
-    
-      word_addr_t addr;
 
-      addr = _soc_register_dict[addr_name]; 
+  function void RegScoreboard::del_entry_withtid(string addr_name, int tid);
 
-      if (addr_table.exists(addr)) 
-        addr_table.delete(addr);
-      else   
-        $display("TB WARNING. del_entries: No addr %s (0x%08x) found in scoreboard", addr_name, addr);
+    int qi [$]; 
+    int err_found = 0;
 
-    endfunction 
+    word_addr_t addr; 
 
+    addr = _soc_register_dict[addr_name]; 
 
-    function void del_all();
+    if (!(addr_table.exists(addr))) begin
+      $display("TB WARNING. del_entry_withtid: No addr %s (0x%08x) found in scoreboard", addr_name, addr);
+      return;
+    end 
 
-      foreach (addr_table[addr])
-        addr_table.delete(addr);
+    qi = addr_table[addr].find_index with(item.tid == tid); 
+    if (qi.size() == 0) 
+      $display("TB WARNING. No tid %d / addr (0x%08x) combination found in scoreboard", tid, addr);
+    else if (qi.size() == 1) 
+      addr_table.delete(addr);
+    else begin 
+      $display("TB WARNING. Multiple tid %d found for addr (0x%08x) in scoreboard", tid, addr);
+      foreach (qi[i])  // Note. This works fine for a hash table, not a queue/array 
+        addr_table[addr].delete(qi[i]);
+    end
 
-    endfunction 
+  endfunction  // del_entry_withtid
 
 
-    function void display_all();      
+  function void RegScoreboard::del_entries(string addr_name);
+  
+    word_addr_t addr;
 
-      int i;
-      word_addr_t tmpkey;
-      transaction_t tmptrans; 
-      transq_t tmpq; 
+    addr = _soc_register_dict[addr_name]; 
 
-      $display ("\n\n-- Current state of scoreboard --\n");
-      foreach (addr_table[tmpkey]) begin
-        tmpq = addr_table[tmpkey]; 
-        foreach (tmpq[i]) begin 
-            tmptrans = tmpq[i]; 
-            $display (" -- Queue for addr %x[%03d]: {addr = %x, data = %x, tid = %x}", 
-              tmpkey, i , tmptrans.addr, tmptrans.data, tmptrans.tid);
-        end
-        $display (" --------------------------------------------- "); 
-      end
+    if (addr_table.exists(addr)) 
+      addr_table.delete(addr);
+    else   
+      $display("TB WARNING. del_entries: No addr %s (0x%08x) found in scoreboard", addr_name, addr);
 
-    endfunction
+  endfunction  // del_entries
 
 
-  endclass // RegScoreboard
+  function void RegScoreboard::del_all();
+
+    foreach (addr_table[addr])
+      addr_table.delete(addr);
+
+  endfunction  // del_all
+
+
+  function void RegScoreboard::display_all();      
+
+    int i;
+    word_addr_t tmpkey;
+    transaction_t tmptrans; 
+    transq_t tmpq; 
+
+    $display ("\n\n-- Current state of scoreboard --\n");
+    foreach (addr_table[tmpkey]) begin
+      tmpq = addr_table[tmpkey]; 
+      foreach (tmpq[i]) begin 
+          tmptrans = tmpq[i]; 
+          $display (" -- Queue for addr %x[%03d]: {addr = %x, data = %x, tid = %x}", 
+            tmpkey, i , tmptrans.addr, tmptrans.data, tmptrans.tid);
+      end
+      $display (" --------------------------------------------- "); 
+    end
+
+  endfunction // display_all
 
 
 endpackage // soc_ifc_tb_pkg
 
 `endif // SOC_IFC_TB_PKG
 
+
diff --git a/src/soc_ifc/tb/soc_reg_intrblk_test.svh b/src/soc_ifc/tb/soc_reg_intrblk_test.svh
new file mode 100644
index 000000000..85e92c8ef
--- /dev/null
+++ b/src/soc_ifc/tb/soc_reg_intrblk_test.svh
@@ -0,0 +1,405 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//======================================================================
+
+  // Keeping all declarations and assignments of internal signals for possibly future use
+  logic [1:0] global_intr_en_r;  
+  logic [7:0] error_intr_en_r;   
+  logic [5:0] notif_intr_en_r;   
+  logic error_global_intr_r;          // *RO* 
+  logic notif_global_intr_r;          // *RO* 
+  logic [7:0] error_internal_intr_r;  // *WO*
+  logic [5:0] notif_internal_intr_r;  // *WO*
+  logic [7:0] error_intr_trig_r;      // *WO*
+  logic [5:0] notif_intr_trig_r;      // *WO*
+  logic error_internal_intr_count_r;  
+  logic error_inv_dev_intr_count_r;             
+  logic error_cmd_fail_intr_count_r;            
+  logic error_bad_fuse_intr_count_r;            
+  logic error_iccm_blocked_intr_count_r;        
+  logic error_mbox_ecc_unc_intr_count_r;        
+  logic error_wdt_timer1_timeout_intr_count_r;  
+  logic error_wdt_timer2_timeout_intr_count_r;  
+  logic notif_cmd_avail_intr_count_r;           
+  logic notif_mbox_ecc_cor_intr_count_r;        
+  logic notif_debug_locked_intr_count_r;        
+  logic notif_soc_req_lock_intr_count_r;        
+  logic notif_gen_in_toggle_intr_count_r;       
+  // Following are already covered via other tests and implications; not needed for INTR_BLOCK 
+  // logic error_internal_intr_count_incr_r;       dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value;
+  // logic error_inv_dev_intr_count_incr_r;        dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.value;
+  // logic error_cmd_fail_intr_count_incr_r;       dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.value;
+  // logic error_bad_fuse_intr_count_incr_r;       dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.value;
+  // logic error_iccm_blocked_intr_count_incr_r;   dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.value;
+  // logic error_mbox_ecc_unc_intr_count_incr_r;   dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.value;
+  // logic error_wdt_timer1_timeout_intr_count_incr_r; dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.value;
+  // logic error_wdt_timer2_timeout_intr_count_incr_r; dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.value;
+  // logic notif_cmd_avail_intr_count_incr_r;      dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.value;
+  // logic notif_mbox_ecc_cor_intr_count_incr_r;   dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.value;
+  // logic notif_debug_locked_intr_count_incr_r;   dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.value;
+  // logic notif_soc_req_lock_intr_count_incr_r;   dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.value;
+  // logic notif_gen_in_toggle_intr_count_incr_r;  dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.value;
+
+  assign global_intr_en_r =        {dut.i_soc_ifc_reg.field_storage.intr_block_rf.global_intr_en_r.error_en.value,
+                                    dut.i_soc_ifc_reg.field_storage.intr_block_rf.global_intr_en_r.notif_en.value};
+  assign error_intr_en_r =         {dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value,
+                                    dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_intr_en_r.error_inv_dev_en.value,
+                                    dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_intr_en_r.error_cmd_fail_en.value,
+                                    dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_intr_en_r.error_bad_fuse_en.value,
+                                    dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_intr_en_r.error_iccm_blocked_en.value,
+                                    dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_intr_en_r.error_mbox_ecc_unc_en.value,
+                                    dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer1_timeout_en.value,
+                                    dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer2_timeout_en};
+  assign notif_intr_en_r =         {dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_avail_en.value,
+                                    dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_en_r.notif_mbox_ecc_cor_en.value,
+                                    dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_en_r.notif_debug_locked_en.value,
+                                    dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_en_r.notif_scan_mode_en.value,
+                                    dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_en_r.notif_soc_req_lock_en.value,
+                                    dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_en_r.notif_gen_in_toggle_en.value};
+  assign error_global_intr_r =      dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_global_intr_r.agg_sts.value; // *RO*
+  assign notif_global_intr_r =      dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value; // *RO*
+  assign error_internal_intr_r =   {dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value,
+                                    dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_internal_intr_r.error_inv_dev_sts.value,
+                                    dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_internal_intr_r.error_cmd_fail_sts.value,
+                                    dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_internal_intr_r.error_bad_fuse_sts.value,
+                                    dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_internal_intr_r.error_iccm_blocked_sts.value,
+                                    dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_internal_intr_r.error_mbox_ecc_unc_sts.value,
+                                    dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer1_timeout_sts.value,
+                                    dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer2_timeout_sts.value};
+  assign notif_internal_intr_r =   {dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_avail_sts.value,
+                                    dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_internal_intr_r.notif_mbox_ecc_cor_sts.value,
+                                    dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_internal_intr_r.notif_debug_locked_sts.value,
+                                    dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts.value,
+                                    dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_internal_intr_r.notif_soc_req_lock_sts.value,
+                                    dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.value};            
+  assign error_intr_trig_r =       {dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer2_timeout_trig.value,
+                                    dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer1_timeout_trig.value,
+                                    dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_intr_trig_r.error_mbox_ecc_unc_trig.value,
+                                    dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_intr_trig_r.error_iccm_blocked_trig.value,
+                                    dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_intr_trig_r.error_bad_fuse_trig.value,
+                                    dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_intr_trig_r.error_cmd_fail_trig.value,
+                                    dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_intr_trig_r.error_inv_dev_trig.value,
+                                    dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value};
+    assign notif_intr_trig_r =     {dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.value,
+                                    dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.value,
+                                    dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.value,
+                                    dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_trig_r.notif_debug_locked_trig.value,
+                                    dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_trig_r.notif_mbox_ecc_cor_trig.value,
+                                    dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_avail_trig.value};
+
+  assign error_internal_intr_count_r =            dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value;
+  assign error_inv_dev_intr_count_r =             dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_inv_dev_intr_count_r.cnt.value;
+  assign error_cmd_fail_intr_count_r =            dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_cmd_fail_intr_count_r.cnt.value;
+  assign error_bad_fuse_intr_count_r =            dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_bad_fuse_intr_count_r.cnt.value;
+  assign error_iccm_blocked_intr_count_r =        dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.value;
+  assign error_mbox_ecc_unc_intr_count_r =        dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.value;
+  assign error_wdt_timer1_timeout_intr_count_r =  dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.value;
+  assign error_wdt_timer2_timeout_intr_count_r =  dut.i_soc_ifc_reg.field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.value;
+  assign notif_cmd_avail_intr_count_r =           dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.value;
+  assign notif_mbox_ecc_cor_intr_count_r =        dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.value;
+  assign notif_debug_locked_intr_count_r =        dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_debug_locked_intr_count_r.cnt.value;
+  assign notif_soc_req_lock_intr_count_r =        dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.value;
+  assign notif_gen_in_toggle_intr_count_r =       dut.i_soc_ifc_reg.field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.value;
+
+
+  //----------------------------------------------------------------
+  // soc_reg_intrblk_test()
+  // 
+  // Test writing & reading of all soc ifc interrupt block registers 
+  //----------------------------------------------------------------
+  task soc_reg_intrblk_test; 
+    // SoC Register Interrupt Block Test excluding *INCR_R which are automatically tested elsewhere
+
+    word_addr_t addr; 
+    int tid = 0; // TID is to be updated ONLY if multiple writes to an address 
+    strq_t intrblk_regnames;
+    string rname, associated_rname;
+
+    WordTransaction wrtrans, rdtrans;
+    strq_t ro_regnames, wo_regnames, wo_associated_regnames;
+
+    logic [31:0] nonzero_cyc = '0; 
+    dword_t ahb_wrdata; 
+
+    int changeup; 
+    int changedn;
+    int changeup_cyc = 0;
+    int changedn_cyc = 0;
+    dword_t nonzero_regval;
+    dword_t final_regval; 
+    dword_t associated_regval; 
+
+
+    begin
+      $display("Executing task soc_reg_intrblk_test"); 
+      $display("-----------------------------------\n");
+
+      // set_security_state_byname("DEBUG_UNLOCKED_PRODCUTION"); 
+
+      tc_ctr = tc_ctr + 1;
+
+      wrtrans = new();
+      rdtrans  = new();
+
+      intrblk_regnames = get_intrblk_regnames_minus_incr();
+
+      // These are read-only registers
+      update_exp_regval("INTR_BRF_ERROR_GLOBAL_INTR_R", error_global_intr_r, SET_DIRECT); 
+      update_exp_regval("INTR_BRF_NOTIF_GLOBAL_INTR_R", error_global_intr_r, SET_DIRECT); 
+
+      // Write-one to clear regs need special handling
+      wo_regnames = { "INTR_BRF_ERROR_INTR_TRIG_R", "INTR_BRF_NOTIF_INTR_TRIG_R" };
+      wo_associated_regnames  = { "INTR_BRF_ERROR_INTERNAL_INTR_R",  "INTR_BRF_NOTIF_INTERNAL_INTR_R" };
+
+      repeat (5) @(posedge clk_tb);
+
+
+      // Skip wrting & reading over AHB until post reset sequencing is done 
+      // THEN, update scoreboard entry accordingly for a couple of registers which 
+      // are written using APB as part of Caliptra boot.  Scoreboard update not 
+      // needed for readonly fields which are set directly by wires.
+      simulate_caliptra_boot();
+      update_CPTRA_FLOW_STATUS(ready_for_fuses, `REG_HIER_BOOT_FSM_PS);
+
+      repeat (20) @(posedge clk_tb);
+      sb.del_all();
+
+
+      // PHASE I. 1a-d Write-Read register back2back 
+      // ------------------------------------------------------------
+
+      $display ("\n------------------------------------------------------------------------------");
+      $display ("1a. Writing/Reading back to back using AHB/AHB every 3 cycles");
+      $display ("------------------------------------------------------------------------------");
+      tphase = "1a";
+      write_read_regs(SET_AHB, GET_AHB, intrblk_regnames, tid, 3);
+
+      repeat (20) @(posedge clk_tb);
+      // sb.del_all(); // Keep scoreboard entries of writes for next phase 1b 
+
+
+      $display ("\n------------------------------------------------------------------------------");
+      $display ("1b. Read over AHB. Then Writing/Reading back to back using APB/APB every 3 cycles");
+      $display ("------------------------------------------------------------------------------");
+      tphase = "1b";
+
+      // Read out the data over AHB. Ensure APB writes cannot modify the registers 
+      // Implicity test neither can AHB reads. 
+      foreach (intrblk_regnames[i]) begin
+        $display("-- expect no modification over apb writes --");
+        rname = intrblk_regnames[i];
+        rdtrans.update(socregs.get_addr(rname), 32'hffff_ffff, tid); 
+        read_reg_trans(GET_AHB, rdtrans); 
+        update_exp_regval(rname, rdtrans.data, SET_DIRECT);  // what has been just read cannot be changed by APB 
+        write_regs(SET_APB, {rname}, tid, 3);
+      end 
+      read_regs(GET_APB, intrblk_regnames, tid, 3);
+
+      repeat (20) @(posedge clk_tb);
+      // sb.del_all();   // Keep scoreboard entries of AHB writes from 1a for next phase 1c
+
+
+      $display ("\n------------------------------------------------------------------------------");
+      $display ("1c. Read over APB. Then Writing/Reading back to back using APB/AHB every 3 cycles");
+      $display ("------------------------------------------------------------------------------");
+      tphase = "1c";
+
+      // Read out the data over APB. Ensure APB writes cannot modify the registers either 
+      // Implicity test neither can APB reads. 
+      foreach (intrblk_regnames[i]) begin
+        $display("-- expect no modification over apb writes --");
+        rname = intrblk_regnames[i];
+        rname = intrblk_regnames[i];
+        rdtrans.update(socregs.get_addr(rname), 32'hffff_ffff, tid); 
+        read_reg_trans(GET_APB, rdtrans); 
+        update_exp_regval(rname, rdtrans.data, SET_DIRECT);  // what has been read cannot be changed by APB 
+        write_regs(SET_APB, {rname}, tid, 3);
+      end 
+      read_regs(GET_AHB, intrblk_regnames, tid, 3);
+
+      repeat (20) @(posedge clk_tb);
+      sb.del_all();   
+
+      // Don't need to test AHB/APB write read anymore; included  in sequences above
+      // $display ("1d. Writing/Reading back to back using AHB/APB every 3 cycles");
+
+      $display ("\n------------------------------------------------------------------------------");
+      $display ("2a. Handle WO special registers"); 
+      $display ("------------------------------------------------------------------------------");
+      tphase = "2a";
+
+      // For WO_ASSOCIATED_REGNAMES. 
+      // First expect to clear all write-to-clear data (check it too) 
+      // Then randomly set bits and ensure only those bits are cleared.
+      foreach (wo_associated_regnames[i]) begin
+        rname = wo_associated_regnames[i];
+        addr = socregs.get_addr(rname);
+        $display ("\n-- Handling WO register 0x%08x (%s) --", addr, rname);
+
+        $display ("\n  -- First clear register and check --"); 
+        wrtrans.update_byname(rname, 32'hffff_ffff, tid); 
+        write_reg_trans(SET_AHB, wrtrans);
+        repeat (5) @(posedge clk_tb);
+
+        rdtrans.update_byname(rname, 0, tid); 
+        read_reg_trans(GET_AHB, rdtrans); 
+        if (rdtrans.data != '0)  begin
+          $display("TB ERROR. Expected a write ones to clear register for addr 0x%08x (%s). Instead received 0x%08x", 
+            addr, rname, rdtrans.data); 
+          error_ctr += 1; 
+          continue; 
+        end
+      end
+
+      // Repeat. Longer squence for WO_REGNAMES.
+      // First expect to clear all write-to-clear data (check it too) 
+      // Then randomly set bits and ensure only those bits are cleared.
+      foreach (wo_regnames[i]) begin
+        rname = wo_regnames[i];
+        addr = socregs.get_addr(rname);
+        $display ("\n-- Handling WO register 0x%08x (%s) --", addr, rname);
+
+        $display ("\n  -- First clear register and check --"); 
+        wrtrans.update_byname(rname, 32'hffff_ffff, tid); 
+        write_reg_trans(SET_AHB, wrtrans);
+        repeat (5) @(posedge clk_tb);
+
+        rdtrans.update_byname(rname, 0, tid); 
+        read_reg_trans(GET_AHB, rdtrans); 
+        if (rdtrans.data != '0)  begin
+          $display("TB ERROR. Expected a write ones to clear register for addr 0x%08x (%s). Instead received 0x%08x", 
+            addr, rname, rdtrans.data); 
+          error_ctr += 1; 
+          continue; 
+        end
+        
+        // Now randomly set bits after reg is all clear 
+        wrtrans.update_byname(rname, 0, tid); 
+        wrtrans.randomize();
+        ahb_wrdata = wrtrans.data & get_mask(rname);
+        // $display ("TB DEBUG. Now randomly set bits to write 0x%08x; w/masking expect to write 0x%08x",
+        //   wrtrans.data, ahb_wrdata); 
+
+        $display ("\n  -- Finally check for non-zero value and then transition to 0 --"); 
+
+
+        fork
+          begin : writing_over_ahb
+            write_reg_trans(SET_AHB, wrtrans);
+            repeat (10) @(posedge clk_tb);
+          end
+
+          begin : checking_for_transition 
+            monitor_pulsed_reg(rname, 10, nonzero_regval, final_regval, changeup, changedn);
+          end
+        join
+
+        $display("Inspecting rname %s = addr 0x%08x", rname, addr);
+        $display ("TB DEBUG. All said and done; from addr 0x%08x (%s). Directly probed non-zero val = 0x%08x and final val = 0x%08x| expected non-zero = 0x%08x", 
+          addr, rname, nonzero_regval, final_regval, ahb_wrdata);
+
+        associated_rname = "INTR_BRF_ERROR_INTR_TRIG_R" ? "INTR_BRF_ERROR_INTERNAL_INTR_R" :
+                           "INTR_BRF_NOTIF_INTR_TRIG_R" ? "INTR_BRF_NOTIF_INTERNAL_INTR_R" : 
+                           "UNDEFINED";
+
+        associated_regval = probe_reg(associated_rname);
+        $display ("TB INFO. Checking associated address %s related to trigger %s; associaated value = 0x%08x, trigger value %08x", 
+          associated_rname, rname, associated_regval, nonzero_regval);
+
+
+        if (changeup && changedn && (nonzero_regval == ahb_wrdata) && (final_regval == '0)) 
+          $display ("TB INFO. Both up and down transitions noted correctly; all good with addr 0x%08x (%s)!", addr, rname);
+        else begin
+          error_ctr += 1; 
+          if (!changeup) 
+            $display("TB ERROR did not see a transition to non-zero value for addr 0x%08x (%s)", addr, rname); 
+          else if (!changedn) 
+            $display("TB ERROR did not see a transition back to a zero value for addr 0x%08x (%s) and stayed at 0x%08x", addr, rname, final_regval); 
+          if (nonzero_regval != ahb_wrdata)  
+            $display("TB ERROR Nonzero value noted for addr 0x%08x (%s) is 0x%08x | expected 0x%08x", addr, rname, nonzero_regval, ahb_wrdata); 
+        end
+      end
+
+    end
+
+  endtask // soc_reg_intrblk_test;
+
+
+
+  task automatic monitor_pulsed_reg(input string regname, input int num_cycles, 
+                                    inout dword_t nonzero_val, inout dword_t final_val, inout up, inout dn);
+
+    dword_t probed_val = 32'hbead_face;
+    dword_t latched_val = 32'hbead_face;
+
+    begin
+
+      up = 0;
+      dn = 0;
+
+      repeat (num_cycles) begin                    
+        probed_val =  probe_reg(regname); 
+
+        if (up && dn) begin
+          $display("TB INFO. Saw both up and dn for register %s", regname);
+          break;
+        end
+
+        up = up | ((probed_val != latched_val)  &&  (latched_val == '0));  // Sticky transition up
+        dn = dn | ((probed_val == '0) &&  (latched_val != '0));  // Sticky transition down 
+      
+        if (probed_val != '0) 
+          nonzero_val = probed_val; 
+
+        @(posedge clk_tb);
+        latched_val = probed_val;
+      end
+
+      final_val = probe_reg(regname); 
+
+      // $display("TB DEBUG. For register %s Checking past initated ahb_write_trans. Probed regval = 0x%08x", rname, probed_val);
+    end
+
+  endtask // monitor_pulsed_reg
+
+
+  function automatic dword_t probe_reg(string regname);
+
+    return (regname == "INTR_BRF_ERROR_INTERNAL_INTR_R") ?  error_internal_intr_r :
+            (regname == "INTR_BRF_NOTIF_INTERNAL_INTR_R") ?  notif_internal_intr_r :
+            (regname == "INTR_BRF_ERROR_INTR_TRIG_R") ?  error_intr_trig_r :
+            (regname == "INTR_BRF_NOTIF_INTR_TRIG_R") ?  notif_intr_trig_r :  32'hdead_face; 
+
+  endfunction
+
+
+/* 
+// Placeholder reference
+
+sequence remain_low__sha_acc_error_internal_intr_r;
+  (| ({ dut.i_sha512_acc_top.i_sha512_acc_csr.field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value, 
+        dut.i_sha512_acc_top.i_sha512_acc_csr.field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value, 
+        dut.i_sha512_acc_top.i_sha512_acc_csr.field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value,
+        dut.i_sha512_acc_top.i_sha512_acc_csr.field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value }) == 1'b0); 
+endsequence 
+
+property reg_remains_low;
+  @(posedge clk_tb)
+  disable iff (reg_sva_off) remain_low__sha_acc_error_internal_intr_r;
+endproperty
+
+monitor_trans2ones: assert property(reg_remains_low);
+*/
+
diff --git a/src/soc_ifc/tb/soc_reg_invalid_test.svh b/src/soc_ifc/tb/soc_reg_invalid_test.svh
index cdd2f064b..bff53679f 100644
--- a/src/soc_ifc/tb/soc_reg_invalid_test.svh
+++ b/src/soc_ifc/tb/soc_reg_invalid_test.svh
@@ -35,6 +35,7 @@
     strq_t soc_regnames;
     word_addrq_t undef_regs; 
 
+    automatic dword_t valid_hrdata; 
 
     begin
       $display("Executing task soc_reg_invalid_test"); 
@@ -109,8 +110,9 @@
       write_single_word_ahb(addr, wdata);
       read_single_word_ahb(addr);
 
+      valid_hrdata =  addr[2] ?  hrdata_o_tb[`AHB64_HI] : hrdata_o_tb[`AHB64_LO]; 
       $display("Control condtion; test over AHB to aligned address (expect read to mirro write value) : addr = 0x%08x, wdata = 0x%08x, rdata = 0x%x", 
-        addr, wdata, hrdata_o_tb); 
+        addr, wdata, valid_hrdata); 
 
 
       foreach (undef_regs[i]) begin
@@ -120,10 +122,11 @@
         write_single_word_ahb(undef_addr, wdata);
         read_single_word_ahb(undef_addr);
 
-        $display("Write & read over AHB : undefined addr = 0x%08x, wdata = 0x%08x, rdata = 0x%x", undef_addr, wdata, hrdata_o_tb); 
+        valid_hrdata =  addr[2] ?  hrdata_o_tb[`AHB64_HI] : hrdata_o_tb[`AHB64_LO]; 
+        $display("Write & read over AHB : undefined addr = 0x%08x, wdata = 0x%08x, rdata = 0x%x", undef_addr, wdata, valid_hrdata); 
 
-        if (hrdata_o_tb != 0) begin 
-          $display("ERROR. undefined addr = 0x%08x, returns non-zero value 0x%08x over AHB!", undef_addr, hrdata_o_tb); 
+        if (valid_hrdata != 0) begin 
+          $display("ERROR. undefined addr = 0x%08x, returns non-zero value 0x%08x over AHB!", undef_addr, valid_hrdata); 
           error_ctr += 1;
         end
       end
@@ -143,10 +146,11 @@
         write_single_word_ahb(unaligned_addr, wdata);
         read_single_word_ahb(unaligned_addr);
 
-        $display("Write & read over AHB : unaligned addr = 0x%08x, wdata = 0x%08x, rdata = %x", unaligned_addr, wdata, hrdata_o_tb); 
+        valid_hrdata =  addr[2] ?  hrdata_o_tb[`AHB64_HI] : hrdata_o_tb[`AHB64_LO]; 
+        $display("Write & read over AHB : unaligned addr = 0x%08x, wdata = 0x%08x, rdata = %x", unaligned_addr, wdata, valid_hrdata); 
 
-        if (hrdata_o_tb != 0) begin 
-          $display("ERROR. unaligned addr = 0x%08x, returns non-zero value 0x%08x over AHB!", unaligned_addr, hrdata_o_tb); 
+        if (valid_hrdata != 0) begin 
+          $display("ERROR. unaligned addr = 0x%08x, returns non-zero value 0x%08x over AHB!", unaligned_addr, valid_hrdata); 
           error_ctr += 1;
         end
 
diff --git a/src/soc_ifc/tb/soc_reg_reset_test.svh b/src/soc_ifc/tb/soc_reg_reset_test.svh
index f7608cdd0..a73ed44fe 100644
--- a/src/soc_ifc/tb/soc_reg_reset_test.svh
+++ b/src/soc_ifc/tb/soc_reg_reset_test.svh
@@ -14,6 +14,7 @@
 //
 //======================================================================
 
+
   //----------------------------------------------------------------
   // soc_reg_pwron_test()
   // 
@@ -23,52 +24,73 @@
 
     int tid = 0; // TID is to be updated ONLY if multiple writes to an address 
     strq_t soc_regnames;
+    int iq [$];
 
     logic [2:0] random_security_state; 
 
+    WordTransaction rdtrans = new();
+    string rname_dyn; 
+    dword_t flow_status; 
+    dword_t regval; 
+
+    int tmp_i = 1000; // max 1000 cycle wait time
 
     begin
+      print_banner("\nExecuting task soc_reg_pwron_test", "="); 
 
-      $display("\nExecuting task soc_reg_pwron_test"); 
-      $display("---------------------------------\n");
-
-      // set_security_state('{device_lifecycle: DEVICE_PRODUCTION, debug_locked: DEBUG_LOCKED});
-      if (ss_name == "RANDOM") begin
-        random_security_state = $urandom_range(0, 7); 
-        set_security_state(security_state_t'(random_security_state)); 
-      end else begin
-        random_security_state = get_ss_code(ss_name);
-        set_security_state(security_state_t'(random_security_state)); 
-      end
+      set_security_state_byname(ss_name); 
       sim_dut_init();
 
       tc_ctr = tc_ctr + 1;
-
       $display("Current security state = 0b%03b", security_state);
 
       soc_regnames = get_soc_regnames_minus_intr();
+      del_from_strq(soc_regnames, "INTERNAL_RV_MTIME_L"); // Exclude CPTRA_RV_MTIME_L
+
 
       $display ("0a. Checking Power-on values\n"); 
 
-      // ---------------------------------------------------------------
-      // Phase 1. Inialize soc_regs ON COLD BOOT, then check values  
-      // ---------------------------------------------------------------
-      $display ("1. Init values beyond reset at start of simulation "); 
+      print_banner("Phase 1. Inialize soc_regs ON COLD BOOT, then check values");
+      // --------------------------------------------------------------------------
+
       sb.record_reset_values(0, COLD_RESET);
+      flow_status = update_CPTRA_FLOW_STATUS(ready_for_fuses, `REG_HIER_BOOT_FSM_PS); 
+      @(posedge clk_tb);
 
       read_regs(GET_APB, soc_regnames, 0, 3);
+      _read_special_register(GET_APB, "INTERNAL_RV_MTIME_L", 0); // *** special register ***
 
       simulate_caliptra_boot();
+      flow_status = update_CPTRA_FLOW_STATUS(ready_for_fuses, `REG_HIER_BOOT_FSM_PS); 
+
+      // *** begin - special registers GENERIC_INPUT_WIRES ***
+      if (cptra_noncore_rst_b_tb == 1'b0) begin
+        fork 
+          begin 
+            wait (cptra_noncore_rst_b_tb == 1'b1);
+            $display("TB. INFO Finished waiting for cptra_noncore_rst_b_tb; current value = 1'b%b", cptra_noncore_rst_b_tb);
+          end
+          begin
+            repeat(tmp_i) @(posedge clk_tb);
+            $display("TB. ERROR Timed out while waiting for cptra_noncore_rst_b_tb; current value = 1'b%b", cptra_noncore_rst_b_tb);
+          end
+        join_any
+      end
+
+      _read_special_register(GET_APB, "CPTRA_GENERIC_INPUT_WIRES0", 0);
+      _read_special_register(GET_APB, "CPTRA_GENERIC_INPUT_WIRES1", 0);
+      // *** end - special registers ***
+
 
       repeat (10) @(posedge clk_tb); 
       
       // FUSE_WR_DONE and BOOTFSM_GO are both 'h1
       // no point in checking over ahb; pwron is long done
 
-      // ---------------------------------------------------------------
-      // Phase 2. Repeat COLD BOOT, then check values  
-      // ---------------------------------------------------------------
-      $display ("1. Init values after asserting new cold reset"); 
+
+      print_banner("Phase 2. Repeat COLD BOOT, init explicitly as needed, then check values");
+      // ---------------------------------------------------------------------------------------
+
       reset_dut();
 
       sb.del_all();
@@ -76,6 +98,7 @@
       sb.record_reset_values(0, COLD_RESET);
 
       read_regs(GET_APB, soc_regnames, 0, 3);
+      _read_special_register(GET_APB, "INTERNAL_RV_MTIME_L", 0); // *** special register ***
 
       error_ctr = sb.err_count;
     end
@@ -92,7 +115,7 @@
   task soc_reg_wrmrst_test(input string ss_name="RANDOM");    
 
     int tid = 0; // TID is to be updated ONLY if multiple writes to an address 
-    strq_t soc_regnames;
+    strq_t soc_regnames, fuse_regnames;
 
     logic [2:0] random_security_state; 
 
@@ -101,51 +124,57 @@
 
     WordTransaction transaction; 
 
+    string rname_dyn; 
+
     begin
-      $display("\nExecuting task soc_reg_wrmrst_test"); 
-      $display("----------------------------------\n");
+      print_banner("\nExecuting task soc_reg_wrmrst_test", "="); 
 
       transaction = new(); 
 
-      // ---------------------------------------------------------------
-      // Phase 1. Inialize soc_regs ON COLD BOOT, overwrite w/new values 
-      // ---------------------------------------------------------------
-
-      if (ss_name == "RANDOM") begin 
-        random_security_state = $urandom_range(0, 7); 
-        set_security_state(security_state_t'(random_security_state)); 
-      end else begin
-        random_security_state = get_ss_code(ss_name);
-        set_security_state(security_state_t'(random_security_state)); 
-      end
-
+      set_security_state_byname("RANDOM");
       sim_dut_init();
 
       tc_ctr = tc_ctr + 1;
 
-      $display ("\n1a. Write to registers after cold boot and check back writes");
-
-      soc_regnames = get_soc_regnames_minus_intr();  
+      fuse_regnames = get_fuse_regnames();
+      soc_regnames = get_soc_regnames_minus_fuse_intr();
 
       foreach (soc_regnames[ix]) begin
-        if (soc_regnames[ix] == "CPTRA_FUSE_WR_DONE") begin
+        if ((soc_regnames[ix] == "CPTRA_FUSE_WR_DONE") || (soc_regnames[ix] == "CPTRA_TRNG_STATUS") || 
+            (soc_regnames[ix] == "CPTRA_TRNG_DATA")) begin 
           soc_regnames.delete(ix);  // can cause problem downstream if fuse_wr_done == True 
-          break;
+          continue; 
         end
       end
 
-      write_regs(SET_APB, soc_regnames, 0, 3);
-      read_regs(GET_APB, soc_regnames, 0, 3); // just so we see what was written
+      del_from_strq(soc_regnames, "INTERNAL_RV_MTIME_L"); // Exclude CPTRA_RV_MTIME_L
+
+
+      tphase = "1";
+      print_banner("\nPhase 1. Initialize registers after cold boot, overwrite and check");
+      // ---------------------------------------------------------------------------------
+
+      write_regs(SET_APB, fuse_regnames, 0, 3);
+      read_regs(GET_APB, fuse_regnames, 0, 3); // just so we see what was written
+
+      // Have to wait until after cptra_noncore_rst_b_tb is high
+      //  write_regs(SET_APB, soc_regnames, 0, 3);
+      //  read_regs(GET_APB, soc_regnames, 0, 3); // just so we see what was written
 
       simulate_caliptra_boot();
+      wait (cptra_noncore_rst_b_tb == 1'b1);
 
-      repeat (10) @(posedge clk_tb); 
+      repeat (5) @(posedge clk_tb); 
+
+      write_regs(SET_APB, soc_regnames, 0, 3);
+      read_regs(GET_APB, soc_regnames, 0, 3); // just so we see what was written
 
+      repeat (5) @(posedge clk_tb); 
 
-      // -----------------------------------------------------------------
-      // Phase 2. Perform Warm Reset, read values over APB & AHB 
-      // -----------------------------------------------------------------
-      $display ("\n2a. Perform a warm reset then just read regs"); 
+
+      tphase = "2a";
+      print_banner("\nPhase 2a. Perform a warm reset then just read regs over APB"); 
+      // --------------------------------------------------------------------------
 
       sb.del_all();
       warm_reset_dut(); 
@@ -154,9 +183,11 @@
       wait (ready_for_fuses == 1'b1);
 
       // Some registers need update for specific fields
-      flow_status = update_CPTRA_FLOW_STATUS(ready_for_fuses); 
+      flow_status = update_CPTRA_FLOW_STATUS(ready_for_fuses, `REG_HIER_BOOT_FSM_PS); 
       reset_reason = update_CPTRA_RESET_REASON(1, 0);
 
+
+      $display("TB DEBUG. -- caliptra flow status updated = 0x%08x --", flow_status);
       sb.del_entries("CPTRA_FLOW_STATUS");
       transaction.update_byname("CPTRA_FLOW_STATUS", flow_status, 0);    
       sb.record_entry(transaction, SET_DIRECT); 
@@ -165,18 +196,35 @@
       transaction.update_byname("CPTRA_RESET_REASON", reset_reason, 0);    
       sb.record_entry(transaction, SET_DIRECT); 
 
+      // Treat GENERIC_INPUT_WIRES slightly differently
+      del_from_strq(soc_regnames, "CPTRA_GENERIC_INPUT_WIRES0"); 
+      del_from_strq(soc_regnames, "CPTRA_GENERIC_INPUT_WIRES1"); 
+
 
       // expect old sticky values which are different from power-on values
+      read_regs(GET_APB, fuse_regnames, 0, 3);      
       read_regs(GET_APB, soc_regnames, 0, 3);      
 
+      // *** begin - special registers ***
+      _read_special_register(GET_APB, "INTERNAL_RV_MTIME_L", 0);
+      _read_special_register(GET_APB, "CPTRA_GENERIC_INPUT_WIRES0", 0);
+      _read_special_register(GET_APB, "CPTRA_GENERIC_INPUT_WIRES1", 0);
+      // *** end - special registers ***
+
+
+      tphase = "2b";
+      print_banner("\nPhase 2b. Simulate boot and read regs over AHB adjusting for boot regs"); 
+      // -------------------------------------------------------------------------------------
+
       simulate_caliptra_boot();
 
       $display ("WRM_RST_TEST: After caliptra boot, Ready for fuses = %d, Flow status value is %x", ready_for_fuses, flow_status);  // DEBUG
 
       sb.del_entries("CPTRA_FLOW_STATUS");
-      flow_status = update_CPTRA_FLOW_STATUS(ready_for_fuses); 
+      flow_status = update_CPTRA_FLOW_STATUS(ready_for_fuses, `REG_HIER_BOOT_FSM_PS); 
       transaction.update_byname("CPTRA_FLOW_STATUS", flow_status, 0);    
       transaction.display(); // DEBUG
+      sb.record_entry(transaction, SET_APB);
 
 
       // task above updates bootfsm_go so need to update scoreboard accordingly 
@@ -184,9 +232,49 @@
       transaction.update_byname("CPTRA_BOOTFSM_GO", 32'h1, 0);    
       sb.record_entry(transaction, SET_APB);
 
+      read_regs(GET_AHB, fuse_regnames, 0, 3);
       read_regs(GET_AHB, soc_regnames, 0, 3);
 
+      // *** begin - special registers ***
+      _read_special_register(GET_AHB, "INTERNAL_RV_MTIME_L", 0);
+      _read_special_register(GET_AHB, "CPTRA_GENERIC_INPUT_WIRES0", 0);
+      _read_special_register(GET_AHB, "CPTRA_GENERIC_INPUT_WIRES1", 0);
+      // *** end - special registers ***
+ 
       error_ctr = sb.err_count;
     end
 
   endtask // soc_reg_wrmrst_test;
+
+
+  //----------------------------------------------------------------
+  // _read_special_register()
+  // 
+  // Registers that have special read outcomes. Uses on global tb-level signals 
+  //----------------------------------------------------------------
+
+  task _read_special_register(access_t modifier, string regname, int tid);
+
+    begin
+      case (regname)
+        "INTERNAL_RV_MTIME_L": read_reg_chk_inrange(modifier, regname, tid, cycle_ctr_since_pwrgood - 'd1 , cycle_ctr_since_pwrgood + 'd20); 
+
+        "CPTRA_GENERIC_INPUT_WIRES0": 
+          if (cptra_noncore_rst_b_tb) 
+            read_reg_chk_inrange(modifier, regname, tid, generic_input_wires0_q,  generic_input_wires0_q);
+          else
+            read_reg_chk_inrange(modifier, regname, tid, '0, '0); 
+
+        "CPTRA_GENERIC_INPUT_WIRES1": 
+          if (cptra_noncore_rst_b_tb) 
+            read_reg_chk_inrange(modifier, regname, tid, generic_input_wires1_q,  generic_input_wires1_q);
+          else
+            read_reg_chk_inrange(modifier, regname, tid, '0, '0); 
+
+        default: $display( "TB ERROR. Unsupported special register %s", regname);
+
+      endcase
+
+      @(posedge clk_tb);
+    end
+  endtask 
\ No newline at end of file
diff --git a/src/soc_ifc/tb/soc_reg_test.svh b/src/soc_ifc/tb/soc_reg_test.svh
index 8abc6633c..cc2fdf33c 100644
--- a/src/soc_ifc/tb/soc_reg_test.svh
+++ b/src/soc_ifc/tb/soc_reg_test.svh
@@ -23,19 +23,10 @@
   task soc_reg_test;    
     // SoC Register Test excluding FUSE*, TRNG_DATA* and TRNG_STATUS registers 
 
-    word_addr_t addr; 
     int tid = 0; // TID is to be updated ONLY if multiple writes to an address 
     strq_t soc_regnames;
-    string rname;
-    logic [31:0] tmpdata;
     int iq [$]; 
 
-    transaction_t entry;
-    transq_t entries; 
-    WordTransaction wrtrans, tmptrans; 
-    
-    dword_t tmpval; 
-
     begin
       $display("Executing task soc_reg_test"); 
       $display("---------------------------\n");
@@ -43,23 +34,18 @@
       // TODO. Randomize 
       set_security_state('{device_lifecycle: DEVICE_PRODUCTION, debug_locked: DEBUG_UNLOCKED});
 
-      // $display("Current security state = 0b%03b", security_state);
-
-
       tc_ctr = tc_ctr + 1;
 
       soc_regnames = get_soc_regnames_minus_fuse_intr();
 
-      // Exclude CPTRA_TRNG_STATUS
-      iq = soc_regnames.find_index with (item == "CPTRA_TRNG_STATUS");
-      if (iq.size() == 1)
-        soc_regnames.delete(iq[0]);
-
-      // Exclude CPTRA_TRNG_DATA*
-      soc_regnames.find_index with (str_startswith(item, "CPTRA_TRNG_DATA"));
-      foreach(iq[i]) 
-        soc_regnames.delete(iq[i]);
+      // Exclude registers that are covered in separate tasks - fuse and intrblk regs
+      // -- Exclude CPTRA_TRNG_STATUS, INTERNAL_RV_MTIME_L/H
+      del_from_strq(soc_regnames, "INTERNAL_RV_MTIME_L");
+      del_from_strq(soc_regnames, "INTERNAL_RV_MTIME_H");
+      del_from_strq(soc_regnames, "CPTRA_TRNG_STATUS");
 
+      // -- Exclude CPTRA_TRNG_DATA*
+      delm_from_strq(soc_regnames, "CPTRA_TRNG_DATA");
 
       repeat (5) @(posedge clk_tb);
 
@@ -72,37 +58,55 @@
       // PHASE I. 1a-d Write-Read register back2back 
       // ------------------------------------------------------------
 
-
       repeat (20) @(posedge clk_tb);
       sb.del_all();
+      error_ctr = 0;
+
+      update_CPTRA_FLOW_STATUS(ready_for_fuses, `REG_HIER_BOOT_FSM_PS); 
+
 
-      update_CPTRA_FLOW_STATUS(ready_for_fuses); 
+      $display ("\n-------------------------------------------------------------");
+      $display ("1a. Writing/Reading back to back using AHB/AHB every 3 cycles");
+      $display ("-------------------------------------------------------------");
 
-      $display ("\n1a. Writing/Reading back to back using AHB/AHB every 3 cycles");
       write_read_regs(SET_AHB, GET_AHB, soc_regnames, tid, 3);
 
+      //FIXME. Need to add test for delayed cross modification of INTERNAL_ICCM_LOCK  
+      //        if ((addr_name == "INTERNAL_FW_UPDATE_RESET") &  (indata[0] == 1'b1)) begin
 
       repeat (20) @(posedge clk_tb);
       sb.del_all();
 
-      $display ("\n1b. Writing/Reading back to back using APB/APB every 3 cycles");
-      write_read_regs(SET_APB, GET_APB, soc_regnames, tid, 3);
+      $display ("\n-------------------------------------------------------------");
+      $display ("1b. Writing/Reading back to back using APB/APB every 3 cycles");
+      $display ("-------------------------------------------------------------");
 
+      write_read_regs(SET_APB, GET_APB, soc_regnames, tid, 3);
 
       repeat (20) @(posedge clk_tb);
       sb.del_all();
 
-      $display ("\n1c. Writing/Reading back to back using APB/AHB every 3 cycles");
-      write_read_regs(SET_APB, GET_AHB, soc_regnames, tid, 3);
 
+      $display ("\n-------------------------------------------------------------");
+      $display ("1c. Writing/Reading back to back using APB/AHB every 3 cycles");
+      $display ("-------------------------------------------------------------");
+
+      write_read_regs(SET_APB, GET_AHB, soc_regnames, tid, 3);
 
       repeat (20) @(posedge clk_tb);
       sb.del_all();
 
-      $display ("\n1d. Writing/Reading back to back using AHB/APB every 3 cycles");
+      $display ("\n-------------------------------------------------------------");
+      $display ("1d. Writing/Reading back to back using AHB/APB every 3 cycles");
+      $display ("-------------------------------------------------------------");
+
       write_read_regs(SET_AHB, GET_APB, soc_regnames, tid, 3);
+      
+      //FIXME. Need to add test for delayed cross modification of INTERNAL_ICCM_LOCK  
+      //        if ((addr_name == "INTERNAL_FW_UPDATE_RESET") &  (indata[0] == 1'b1)) begin
+
+      error_ctr += sb.err_count;
 
-      error_ctr = sb.err_count;
     end
   endtask // soc_reg_test
 
diff --git a/src/soc_ifc/uvmf_soc_ifc/config/compile.yml b/src/soc_ifc/uvmf_soc_ifc/config/compile.yml
index 02b0c1f87..1f9cf8295 100644
--- a/src/soc_ifc/uvmf_soc_ifc/config/compile.yml
+++ b/src/soc_ifc/uvmf_soc_ifc/config/compile.yml
@@ -16,6 +16,8 @@ targets:
       - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src
       - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg
       - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src
+      - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg
+      - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src
       - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg
       - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers
     files:
@@ -39,6 +41,11 @@ targets:
       - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_driver_bfm.sv
       - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_if.sv
       - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_monitor_bfm.sv
+      - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_pkg_hdl.sv
+      - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_pkg.sv
+      - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_driver_bfm.sv
+      - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_if.sv
+      - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_monitor_bfm.sv
       - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_model_top_pkg.sv
       - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/soc_ifc_env_pkg.sv
 ---
diff --git a/src/soc_ifc/uvmf_soc_ifc/coverage/config/uvmf_soc_ifc_cm_hier.cfg b/src/soc_ifc/uvmf_soc_ifc/coverage/config/uvmf_soc_ifc_cm_hier.cfg
index f8b1e528f..0a84804d7 100644
--- a/src/soc_ifc/uvmf_soc_ifc/coverage/config/uvmf_soc_ifc_cm_hier.cfg
+++ b/src/soc_ifc/uvmf_soc_ifc/coverage/config/uvmf_soc_ifc_cm_hier.cfg
@@ -1,4 +1,3 @@
 begin line+tgl+fsm+cond+branch
     +tree hdl_top.dut 0
 end
-
diff --git a/src/soc_ifc/uvmf_soc_ifc/mbox_sram_interface.yaml b/src/soc_ifc/uvmf_soc_ifc/mbox_sram_interface.yaml
new file mode 100644
index 000000000..52470e489
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/mbox_sram_interface.yaml
@@ -0,0 +1,67 @@
+uvmf:
+  interfaces:
+    mbox_sram:
+      clock: clk
+      reset: dummy
+      reset_assertion_level: 'False'
+
+      config_constraints: []
+      config_vars:
+      - name: "inject_ecc_error"
+        type: "bit [1:0]"
+        isrand: "False"
+        value: "2'b00"
+        comment: "Controls injection of ECC errors for write transactions. Bit[0]: Single Bit Error. Bit[1]: Double Bit Error"
+      - name: "auto_clear_ecc_error_injection"
+        type: "bit"
+        isrand: "False"
+        value: "1'b1"
+        comment: "When set, causes the mbox_sram_responder_sequence to clear the variable 'inject_ecc_error' after a single ECC error is injected"
+
+      hdl_typedefs: []
+      hvl_typedefs: []
+
+      # NOTE: This agent will be in RESPONDER mode, which inverts
+      #       all port's polarities
+      ports:
+      - name: mbox_sram_req
+        dir: output
+        width: '$bits(mbox_sram_req_t)'
+        # cs (1) + we (1) + addr (15) + data (32) + ecc (7) = 56
+      - name: mbox_sram_resp
+        dir: input
+        width: '$bits(mbox_sram_resp_t)'
+        # data (32) + ecc (7) = 39
+
+      transaction_constraints: []
+#      - name: wait_cycles_c
+#        value: '{ wait_cycles dist {[1:25] := 80, [25:100] := 15, [100:500] := 5}; }'
+
+      transaction_vars:
+      - name: is_read
+        type: bit
+        iscompare: 'True'
+        isrand: 'True'
+      - name: address
+        type: bit [MBOX_ADDR_W-1:0]
+        iscompare: 'True'
+        isrand: 'True'
+      - name: data
+        type: bit [MBOX_DATA_W-1:0]
+        iscompare: 'True'
+        isrand: 'True'
+        # ECC would be generated based on data, post_randomize, in the case where
+        # this transaction is generated as stimulus.
+        # We mostly expect to use this i/f as an observer though.
+      - name: data_ecc
+        type: bit [MBOX_ECC_DATA_W-1:0]
+        iscompare: 'True'
+        isrand: 'False'
+      - name: ecc_single_bit_error
+        type: bit
+        iscompare: 'True'
+        isrand: 'True'
+      - name: ecc_double_bit_error
+        type: bit
+        iscompare: 'True'
+        isrand: 'True'
diff --git a/src/soc_ifc/uvmf_soc_ifc/run_yaml_uvmf_scripts.sh b/src/soc_ifc/uvmf_soc_ifc/run_yaml_uvmf_scripts.sh
index 80497eeda..f0597c4d7 100755
--- a/src/soc_ifc/uvmf_soc_ifc/run_yaml_uvmf_scripts.sh
+++ b/src/soc_ifc/uvmf_soc_ifc/run_yaml_uvmf_scripts.sh
@@ -4,6 +4,7 @@ python ${UVMF_HOME}/scripts/yaml2uvmf.py --merge_source uvmf_template_output \
                                          soc_ifc_global.yaml \
                                          soc_ifc_ctrl_interface.yaml \
                                          soc_ifc_status_interface.yaml \
+                                         mbox_sram_interface.yaml \
                                          soc_ifc_util_comp_soc_ifc_predictor.yaml \
                                          soc_ifc_util_comp_soc_ifc_scoreboard.yaml \
                                          ../../libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/qvip_ahb_lite_slave_subenv_config.yaml \
diff --git a/src/soc_ifc/uvmf_soc_ifc/soc_ifc_bench.yaml b/src/soc_ifc/uvmf_soc_ifc/soc_ifc_bench.yaml
index 5b35bf45d..a5b3fbc4c 100755
--- a/src/soc_ifc/uvmf_soc_ifc/soc_ifc_bench.yaml
+++ b/src/soc_ifc/uvmf_soc_ifc/soc_ifc_bench.yaml
@@ -18,6 +18,8 @@ uvmf:
         value: ACTIVE
       - bfm_name: cptra_status_agent
         value: ACTIVE
+      - bfm_name: mbox_sram_agent
+        value: ACTIVE
 
       clock_half_period: 5ns
       clock_phase_offset: 0ns
diff --git a/src/soc_ifc/uvmf_soc_ifc/soc_ifc_ctrl_interface.yaml b/src/soc_ifc/uvmf_soc_ifc/soc_ifc_ctrl_interface.yaml
index 1f10609d8..c8e159db4 100755
--- a/src/soc_ifc/uvmf_soc_ifc/soc_ifc_ctrl_interface.yaml
+++ b/src/soc_ifc/uvmf_soc_ifc/soc_ifc_ctrl_interface.yaml
@@ -109,6 +109,10 @@ uvmf:
         dir: output
         width: '1'
 
+      - name: rv_ecc_sts
+        dir: output
+        width: '4'
+
       transaction_constraints: []
 
       transaction_vars:
@@ -120,3 +124,7 @@ uvmf:
         type: bit
         iscompare: 'False'
         isrand: 'False'
+      - name: pulse_rv_ecc_error
+        type: rv_ecc_sts_t
+        iscompare: 'False'
+        isrand: 'False'
diff --git a/src/soc_ifc/uvmf_soc_ifc/soc_ifc_environment.yaml b/src/soc_ifc/uvmf_soc_ifc/soc_ifc_environment.yaml
index ca462f3c2..468989270 100755
--- a/src/soc_ifc/uvmf_soc_ifc/soc_ifc_environment.yaml
+++ b/src/soc_ifc/uvmf_soc_ifc/soc_ifc_environment.yaml
@@ -17,6 +17,9 @@ uvmf:
       - name: cptra_status_agent
         type: cptra_status
         initiator_responder: "RESPONDER"
+      - name: mbox_sram_agent
+        type: mbox_sram
+        initiator_responder: "RESPONDER"
 
       analysis_components:
       - name: soc_ifc_pred
@@ -66,6 +69,8 @@ uvmf:
         receiver: soc_ifc_pred.soc_ifc_ctrl_agent_ae               #
       - driver: cptra_ctrl_agent.monitored_ap                      # Caliptra Control
         receiver: soc_ifc_pred.cptra_ctrl_agent_ae                 #
+      - driver: mbox_sram_agent.monitored_ap                       # Mailbox SRAM i/f
+        receiver: soc_ifc_pred.mbox_sram_agent_ae                  #
 #      - driver: qvip_ahb_lite_master_subenv.ahb_master_0.export_rw # AHB
 #        receiver: soc_ifc_pred.ahb_master_0_ae                     #
 #      - driver: qvip_apb5_master_subenv.apb5_master_0.export_rw    # APB
diff --git a/src/soc_ifc/uvmf_soc_ifc/soc_ifc_status_interface.yaml b/src/soc_ifc/uvmf_soc_ifc/soc_ifc_status_interface.yaml
index bc4e436b1..6f69cbd21 100755
--- a/src/soc_ifc/uvmf_soc_ifc/soc_ifc_status_interface.yaml
+++ b/src/soc_ifc/uvmf_soc_ifc/soc_ifc_status_interface.yaml
@@ -122,6 +122,9 @@ uvmf:
       - name: cptra_uc_rst_b
         dir: output
         width: '1'
+      - name: fw_update_rst_window
+        dir: output
+        width: '1'
 
       #Obfuscated UDS and FE
       - name: cptra_obf_key_reg
@@ -147,11 +150,17 @@ uvmf:
       - name: sha_notif_intr
         dir: output
         width: '1'
+      - name: timer_intr
+        dir: output
+        width: '1'
 
       # NMI Vector
       - name: nmi_vector
         dir: output
         width: '32'
+      - name: nmi_intr
+        dir: output
+        width: '1'
 
       # ICCM Lock
       - name: iccm_lock
@@ -177,6 +186,10 @@ uvmf:
         type: bit
         iscompare: 'True'
         isrand: 'False'
+      - name: timer_intr_pending
+        type: bit
+        iscompare: 'True'
+        isrand: 'False'
 
       # Subsystem reset
       - name: noncore_rst_asserted
@@ -187,6 +200,10 @@ uvmf:
         type: bit
         iscompare: 'True'
         isrand: 'False'
+      - name: fw_update_rst_window
+        type: bit
+        iscompare: 'True'
+        isrand: 'False'
 
       #Obfuscated UDS and FE
       - name: cptra_obf_key_reg
@@ -207,6 +224,10 @@ uvmf:
         type: bit [31:0]
         iscompare: 'True'
         isrand: 'False'
+      - name: nmi_intr_pending
+        type: bit
+        iscompare: 'True'
+        isrand: 'False'
 
       # ICCM Lock
       - name: iccm_locked
diff --git a/src/soc_ifc/uvmf_soc_ifc/soc_ifc_util_comp_soc_ifc_predictor.yaml b/src/soc_ifc/uvmf_soc_ifc/soc_ifc_util_comp_soc_ifc_predictor.yaml
index 692d4f915..8d8ce87cb 100755
--- a/src/soc_ifc/uvmf_soc_ifc/soc_ifc_util_comp_soc_ifc_predictor.yaml
+++ b/src/soc_ifc/uvmf_soc_ifc/soc_ifc_util_comp_soc_ifc_predictor.yaml
@@ -7,6 +7,8 @@ uvmf:
         type: 'soc_ifc_ctrl_transaction'
       - name: cptra_ctrl_agent_ae
         type: 'cptra_ctrl_transaction'
+      - name: mbox_sram_agent_ae
+        type: 'mbox_sram_transaction'
       - name: ahb_slave_0_ae
         type: 'mvc_sequence_item_base'
 #        type: 'ahb_master_burst_transfer #(ahb_lite_slave_0_params::AHB_NUM_MASTERS,
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/docs/interfaces.csv b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/docs/interfaces.csv
index dd76c8f8e..e411f7a9a 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/docs/interfaces.csv
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/docs/interfaces.csv
@@ -27,4 +27,5 @@ soc_ifc_ctrl_agent, soc_ifc_ctrl_driver_bfm soc_ifc_ctrl_monitor_bfm, soc_ifc_ct
 cptra_ctrl_agent, cptra_ctrl_driver_bfm cptra_ctrl_monitor_bfm, cptra_ctrl_transaction, cptra_ctrl_pkg_cptra_ctrl_agent_BFM,
 soc_ifc_status_agent, soc_ifc_status_driver_bfm soc_ifc_status_monitor_bfm, soc_ifc_status_transaction, soc_ifc_status_pkg_soc_ifc_status_agent_BFM,
 cptra_status_agent, cptra_status_driver_bfm cptra_status_monitor_bfm, cptra_status_transaction, cptra_status_pkg_cptra_status_agent_BFM,
+mbox_sram_agent, mbox_sram_driver_bfm mbox_sram_monitor_bfm, mbox_sram_transaction, mbox_sram_pkg_mbox_sram_agent_BFM,
 
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/sim/Makefile b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/sim/Makefile
index 1b5fcb327..6c3120c72 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/sim/Makefile
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/sim/Makefile
@@ -87,6 +87,7 @@ include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/soc_ifc_ctrl_pkg/Makefile
 include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/cptra_ctrl_pkg/Makefile
 include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/soc_ifc_status_pkg/Makefile
 include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/cptra_status_pkg/Makefile
+include $(UVMF_VIP_LIBRARY_HOME)/interface_packages/mbox_sram_pkg/Makefile
 
 # Include all requisite environment package targets for this bench
 include $(UVMF_VIP_LIBRARY_HOME)/environment_packages/soc_ifc_env_pkg/Makefile
@@ -196,7 +197,7 @@ comp_hvl : comp_hvl_core
 
 
 comp_hvl_core :  comp_qvip comp_qvip_utils_pkg   \
-	 comp_soc_ifc_ctrl_pkg  comp_cptra_ctrl_pkg  comp_soc_ifc_status_pkg  comp_cptra_status_pkg  \
+	 comp_soc_ifc_ctrl_pkg  comp_cptra_ctrl_pkg  comp_soc_ifc_status_pkg  comp_cptra_status_pkg  comp_mbox_sram_pkg  \
 	comp_soc_ifc_env_pkg \
 	comp_soc_ifc_parameters_pkg comp_soc_ifc_sequence_pkg comp_soc_ifc_tests_pkg 
 
@@ -204,7 +205,7 @@ comp_uvmf_core : comp_uvm_pkg comp_uvmf_base_pkg
 
 make_build: comp_soc_ifc_dut comp_uvmf_core comp_hvl comp_test_bench  
 
-hvl_build:  q_comp_soc_ifc_ctrl_pkg  q_comp_cptra_ctrl_pkg  q_comp_soc_ifc_status_pkg  q_comp_cptra_status_pkg  comp_soc_ifc_env_pkg comp_soc_ifc_sequence_pkg comp_soc_ifc_tests_pkg hvl_comp_testbench link optimize
+hvl_build:  q_comp_soc_ifc_ctrl_pkg  q_comp_cptra_ctrl_pkg  q_comp_soc_ifc_status_pkg  q_comp_cptra_status_pkg  q_comp_mbox_sram_pkg  comp_soc_ifc_env_pkg comp_soc_ifc_sequence_pkg comp_soc_ifc_tests_pkg hvl_comp_testbench link optimize
 
 
 vinfo_build: comp_qvip  comp_soc_ifc_vhdl_dut  build_hdl_vinfo build_hvl_vinfo $(VINFO_TGT)
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/sim/compile.do b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/sim/compile.do
index ea7be28a2..f45e56a43 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/sim/compile.do
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/sim/compile.do
@@ -58,6 +58,7 @@ do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/soc_ifc_ctrl_pkg/compile.do
 do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/cptra_ctrl_pkg/compile.do
 do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/soc_ifc_status_pkg/compile.do
 do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/cptra_status_pkg/compile.do
+do $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/mbox_sram_pkg/compile.do
 
 ###################################################################
 ## UVMF ENVIRONMENT COMPILATION
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/sim/viswave.do b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/sim/viswave.do
index 7fb0d70b7..58934106e 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/sim/viswave.do
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/sim/viswave.do
@@ -28,6 +28,12 @@ wave group cptra_status_agent_bus
 wave add -group cptra_status_agent_bus hdl_top.cptra_status_agent_bus.* -radix hexadecimal -tag F0
 wave group cptra_status_agent_bus -collapse
 wave insertion [expr [wave index insertpoint] +1]
+wave spacer -backgroundcolor Salmon { mbox_sram_agent }
+wave add uvm_test_top.environment.mbox_sram_agent.mbox_sram_agent_monitor.txn_stream -radix string -tag F0
+wave group mbox_sram_agent_bus
+wave add -group mbox_sram_agent_bus hdl_top.mbox_sram_agent_bus.* -radix hexadecimal -tag F0
+wave group mbox_sram_agent_bus -collapse
+wave insertion [expr [wave index insertpoint] +1]
 
 wave update on
 WaveSetStreamView
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/sim/wave.do b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/sim/wave.do
index 7e0fc1e33..1ba8a1615 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/sim/wave.do
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/sim/wave.do
@@ -15,6 +15,9 @@ add wave -noupdate -group soc_ifc_status_agent_bus /hdl_top/soc_ifc_status_agent
 add wave -noupdate -divider cptra_status_agent 
 add wave -noupdate /uvm_root/uvm_test_top/environment/cptra_status_agent/cptra_status_agent_monitor/txn_stream
 add wave -noupdate -group cptra_status_agent_bus /hdl_top/cptra_status_agent_bus/*
+add wave -noupdate -divider mbox_sram_agent 
+add wave -noupdate /uvm_root/uvm_test_top/environment/mbox_sram_agent/mbox_sram_agent_monitor/txn_stream
+add wave -noupdate -group mbox_sram_agent_bus /hdl_top/mbox_sram_agent_bus/*
 
 TreeUpdate [SetDefaultTree]
 quietly wave cursor active 0
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/soc_ifc_sve.F b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/soc_ifc_sve.F
index c88496249..2114f41e2 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/soc_ifc_sve.F
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/soc_ifc_sve.F
@@ -12,6 +12,7 @@
 -F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/cptra_ctrl_pkg/cptra_ctrl_pkg_sve.F
 -F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/soc_ifc_status_pkg/soc_ifc_status_pkg_sve.F
 -F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/cptra_status_pkg/cptra_status_pkg_sve.F
+-F ${UVMF_VIP_LIBRARY_HOME}/interface_packages/mbox_sram_pkg/mbox_sram_pkg_sve.F
 
 // Environment Files
 -F ${UVMF_VIP_LIBRARY_HOME}/environment_packages/soc_ifc_env_pkg/soc_ifc_env_pkg_sve.F
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/parameters/soc_ifc_parameters_pkg.sv b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/parameters/soc_ifc_parameters_pkg.sv
index d6e073e1e..af3cb9a50 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/parameters/soc_ifc_parameters_pkg.sv
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/parameters/soc_ifc_parameters_pkg.sv
@@ -45,6 +45,7 @@ package soc_ifc_parameters_pkg;
   parameter string cptra_ctrl_agent_BFM  = "cptra_ctrl_agent_BFM"; /* [3] */
   parameter string soc_ifc_status_agent_BFM  = "soc_ifc_status_agent_BFM"; /* [4] */
   parameter string cptra_status_agent_BFM  = "cptra_status_agent_BFM"; /* [5] */
+  parameter string mbox_sram_agent_BFM  = "mbox_sram_agent_BFM"; /* [6] */
 
   // pragma uvmf custom package_item_additional begin
   // pragma uvmf custom package_item_additional end
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/sequences/soc_ifc_sequences_pkg.compile b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/sequences/soc_ifc_sequences_pkg.compile
index 1243f5665..943dc7955 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/sequences/soc_ifc_sequences_pkg.compile
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/sequences/soc_ifc_sequences_pkg.compile
@@ -4,6 +4,7 @@ needs:
   - ../../../../verification_ip/interface_packages/cptra_ctrl_pkg/cptra_ctrl.compile
   - ../../../../verification_ip/interface_packages/soc_ifc_status_pkg/soc_ifc_status.compile
   - ../../../../verification_ip/interface_packages/cptra_status_pkg/cptra_status.compile
+  - ../../../../verification_ip/interface_packages/mbox_sram_pkg/mbox_sram.compile
   - ../../../../verification_ip/environment_packages/soc_ifc_env_pkg/soc_ifc_env_pkg.compile
   - ../parameters/soc_ifc_parameters_pkg.compile
 src:
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/sequences/soc_ifc_sequences_pkg.sv b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/sequences/soc_ifc_sequences_pkg.sv
index f109f898e..2c25d7490 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/sequences/soc_ifc_sequences_pkg.sv
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/sequences/soc_ifc_sequences_pkg.sv
@@ -47,6 +47,8 @@ package soc_ifc_sequences_pkg;
   import soc_ifc_status_pkg_hdl::*;
   import cptra_status_pkg::*;
   import cptra_status_pkg_hdl::*;
+  import mbox_sram_pkg::*;
+  import mbox_sram_pkg_hdl::*;
   import soc_ifc_parameters_pkg::*;
   import soc_ifc_env_pkg::*;
   import qvip_ahb_lite_slave_params_pkg::*;
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/sequences/soc_ifc_sequences_pkg.vinfo b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/sequences/soc_ifc_sequences_pkg.vinfo
index fea3885f7..035e660ea 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/sequences/soc_ifc_sequences_pkg.vinfo
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/sequences/soc_ifc_sequences_pkg.vinfo
@@ -3,6 +3,7 @@
 @use $UVMF_VIP_LIBRARY_HOME/interface_packages/cptra_ctrl_pkg/cptra_ctrl_pkg.vinfo
 @use $UVMF_VIP_LIBRARY_HOME/interface_packages/soc_ifc_status_pkg/soc_ifc_status_pkg.vinfo
 @use $UVMF_VIP_LIBRARY_HOME/interface_packages/cptra_status_pkg/cptra_status_pkg.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/interface_packages/mbox_sram_pkg/mbox_sram_pkg.vinfo
 @use $UVMF_VIP_LIBRARY_HOME/environment_packages/soc_ifc_env_pkg/soc_ifc_env_pkg.vinfo
 @use $UVMF_PROJECT_DIR/tb/parameters/soc_ifc_parameters_pkg.vinfo
 +incdir+@vinfodir
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/sequences/src/register_test_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/sequences/src/register_test_sequence.svh
index 09993ee2a..85a802e5d 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/sequences/src/register_test_sequence.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/sequences/src/register_test_sequence.svh
@@ -55,6 +55,7 @@ class register_test_sequence extends soc_ifc_bench_sequence_base;
       cptra_ctrl_agent_config.wait_for_reset();
       soc_ifc_status_agent_config.wait_for_reset();
       cptra_status_agent_config.wait_for_reset();
+      mbox_sram_agent_config.wait_for_reset();
       // pragma uvmf custom register_test_reset end
     join
 
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/sequences/src/soc_ifc_bench_sequence_base.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/sequences/src/soc_ifc_bench_sequence_base.svh
index d3465bf39..3dfaeaac9 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/sequences/src/soc_ifc_bench_sequence_base.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/sequences/src/soc_ifc_bench_sequence_base.svh
@@ -56,6 +56,8 @@ rand soc_ifc_env_sequence_base_t soc_ifc_env_seq;
   soc_ifc_status_agent_responder_seq_t soc_ifc_status_agent_responder_seq;
   typedef cptra_status_responder_sequence  cptra_status_agent_responder_seq_t;
   cptra_status_agent_responder_seq_t cptra_status_agent_responder_seq;
+  typedef mbox_sram_responder_sequence  mbox_sram_agent_responder_seq_t;
+  mbox_sram_agent_responder_seq_t mbox_sram_agent_responder_seq;
   // pragma uvmf custom sequences end
 
   // Sequencer handles for each active interface in the environment
@@ -67,6 +69,8 @@ rand soc_ifc_env_sequence_base_t soc_ifc_env_seq;
   uvm_sequencer #(soc_ifc_status_agent_transaction_t)  soc_ifc_status_agent_sequencer; 
   typedef cptra_status_transaction  cptra_status_agent_transaction_t;
   uvm_sequencer #(cptra_status_agent_transaction_t)  cptra_status_agent_sequencer; 
+  typedef mbox_sram_transaction  mbox_sram_agent_transaction_t;
+  uvm_sequencer #(mbox_sram_agent_transaction_t)  mbox_sram_agent_sequencer; 
 
   // Sequencer handles for each QVIP interface
   mvc_sequencer uvm_test_top_environment_qvip_ahb_lite_slave_subenv_ahb_lite_slave_0_sqr;
@@ -80,6 +84,7 @@ rand soc_ifc_env_sequence_base_t soc_ifc_env_seq;
   cptra_ctrl_configuration  cptra_ctrl_agent_config;
   soc_ifc_status_configuration  soc_ifc_status_agent_config;
   cptra_status_configuration  cptra_status_agent_config;
+  mbox_sram_configuration  mbox_sram_agent_config;
   // Local handle to register model for convenience
   soc_ifc_reg_model_top reg_model;
   uvm_status_e status;
@@ -107,12 +112,15 @@ rand soc_ifc_env_sequence_base_t soc_ifc_env_seq;
       `uvm_fatal("CFG" , "uvm_config_db #( soc_ifc_status_configuration )::get cannot find resource soc_ifc_status_agent_BFM" )
     if( !uvm_config_db #( cptra_status_configuration )::get( null , UVMF_CONFIGURATIONS , cptra_status_agent_BFM , cptra_status_agent_config ) ) 
       `uvm_fatal("CFG" , "uvm_config_db #( cptra_status_configuration )::get cannot find resource cptra_status_agent_BFM" )
+    if( !uvm_config_db #( mbox_sram_configuration )::get( null , UVMF_CONFIGURATIONS , mbox_sram_agent_BFM , mbox_sram_agent_config ) ) 
+      `uvm_fatal("CFG" , "uvm_config_db #( mbox_sram_configuration )::get cannot find resource mbox_sram_agent_BFM" )
 
     // Assign the sequencer handles from the handles within agent configurations
     soc_ifc_ctrl_agent_sequencer = soc_ifc_ctrl_agent_config.get_sequencer();
     cptra_ctrl_agent_sequencer = cptra_ctrl_agent_config.get_sequencer();
     soc_ifc_status_agent_sequencer = soc_ifc_status_agent_config.get_sequencer();
     cptra_status_agent_sequencer = cptra_status_agent_config.get_sequencer();
+    mbox_sram_agent_sequencer = mbox_sram_agent_config.get_sequencer();
 
     // Retrieve QVIP sequencer handles from the uvm_config_db
     if( !uvm_config_db #(mvc_sequencer)::get( null,UVMF_SEQUENCERS,"uvm_test_top.environment.qvip_ahb_lite_slave_subenv.ahb_lite_slave_0", uvm_test_top_environment_qvip_ahb_lite_slave_subenv_ahb_lite_slave_0_sqr) ) 
@@ -139,17 +147,20 @@ rand soc_ifc_env_sequence_base_t soc_ifc_env_seq;
     cptra_ctrl_agent_random_seq     = cptra_ctrl_agent_random_seq_t::type_id::create("cptra_ctrl_agent_random_seq");
     soc_ifc_status_agent_responder_seq  = soc_ifc_status_agent_responder_seq_t::type_id::create("soc_ifc_status_agent_responder_seq");
     cptra_status_agent_responder_seq  = cptra_status_agent_responder_seq_t::type_id::create("cptra_status_agent_responder_seq");
+    mbox_sram_agent_responder_seq  = mbox_sram_agent_responder_seq_t::type_id::create("mbox_sram_agent_responder_seq");
     fork
       soc_ifc_ctrl_agent_config.wait_for_reset();
       cptra_ctrl_agent_config.wait_for_reset();
       soc_ifc_status_agent_config.wait_for_reset();
       cptra_status_agent_config.wait_for_reset();
+      mbox_sram_agent_config.wait_for_reset();
     join
     reg_model.reset();
     // Start RESPONDER sequences here
     fork
       soc_ifc_status_agent_responder_seq.start(soc_ifc_status_agent_sequencer);
       cptra_status_agent_responder_seq.start(cptra_status_agent_sequencer);
+      mbox_sram_agent_responder_seq.start(mbox_sram_agent_sequencer);
     join_none
     // Start INITIATOR sequences here
     fork
@@ -167,6 +178,7 @@ soc_ifc_env_seq.start(top_configuration.vsqr);
       cptra_ctrl_agent_config.wait_for_num_clocks(400);
       soc_ifc_status_agent_config.wait_for_num_clocks(400);
       cptra_status_agent_config.wait_for_num_clocks(400);
+      mbox_sram_agent_config.wait_for_num_clocks(400);
     join
 
     // pragma uvmf custom body end
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/sequences/src/soc_ifc_cmdline_test_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/sequences/src/soc_ifc_cmdline_test_sequence.svh
index 2d04e5be8..75c9e8608 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/sequences/src/soc_ifc_cmdline_test_sequence.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/sequences/src/soc_ifc_cmdline_test_sequence.svh
@@ -36,6 +36,7 @@ class soc_ifc_cmdline_test_sequence extends soc_ifc_bench_sequence_base;
 
   rand soc_ifc_env_bringup_sequence_t soc_ifc_env_bringup_seq;
   rand soc_ifc_env_cptra_rst_wait_sequence_t soc_ifc_env_cptra_rst_wait_seq;
+  rand soc_ifc_env_cptra_init_interrupts_sequence_t soc_ifc_env_cptra_init_interrupts_seq;
 
   function new(string name = "" );
     super.new(name);
@@ -53,20 +54,25 @@ class soc_ifc_cmdline_test_sequence extends soc_ifc_bench_sequence_base;
     soc_ifc_env_bringup_seq        = soc_ifc_env_bringup_sequence_t::type_id::create("soc_ifc_env_bringup_seq");
     soc_ifc_env_cptra_rst_wait_seq = soc_ifc_env_cptra_rst_wait_sequence_t::type_id::create("soc_ifc_env_cptra_rst_wait_seq");
 
+    soc_ifc_env_cptra_init_interrupts_seq = soc_ifc_env_cptra_init_interrupts_sequence_t::type_id::create("soc_ifc_env_cptra_init_interrupts_seq");
+
     soc_ifc_ctrl_agent_random_seq      = soc_ifc_ctrl_agent_random_seq_t::type_id::create("soc_ifc_ctrl_agent_random_seq");
     cptra_ctrl_agent_random_seq        = cptra_ctrl_agent_random_seq_t::type_id::create("cptra_ctrl_agent_random_seq");
     soc_ifc_status_agent_responder_seq = soc_ifc_status_agent_responder_seq_t::type_id::create("soc_ifc_status_agent_responder_seq");
     cptra_status_agent_responder_seq   = cptra_status_agent_responder_seq_t::type_id::create("cptra_status_agent_responder_seq");
+    mbox_sram_agent_responder_seq      = mbox_sram_agent_responder_seq_t::type_id::create("mbox_sram_agent_responder_seq");
 
     // Handle to the responder sequence for getting response transactions
     soc_ifc_env_bringup_seq.soc_ifc_status_agent_rsp_seq = soc_ifc_status_agent_responder_seq;
     soc_ifc_env_cptra_rst_wait_seq.cptra_status_agent_rsp_seq = cptra_status_agent_responder_seq;
+    soc_ifc_env_cptra_init_interrupts_seq.cptra_status_agent_rsp_seq = cptra_status_agent_responder_seq;
 
     reg_model.reset();
     // Start RESPONDER sequences here
     fork
         soc_ifc_status_agent_responder_seq.start(soc_ifc_status_agent_sequencer);
         cptra_status_agent_responder_seq.start(cptra_status_agent_sequencer);
+        mbox_sram_agent_responder_seq.start(mbox_sram_agent_sequencer);
     join_none
 
     // Start INITIATOR sequences here
@@ -84,6 +90,12 @@ class soc_ifc_cmdline_test_sequence extends soc_ifc_bench_sequence_base;
     end
     join
 
+    // Always initialize interrupts
+    // TODO - if we make this random, we can test both interrupt-driven and
+    // polling behavior
+    soc_ifc_env_cptra_init_interrupts_seq.start(top_configuration.vsqr);
+    `uvm_info("SOC_IFC_CMDLINE_TEST", "Completed interrupt init", UVM_MEDIUM)
+
     // Run cmdline provided env sequences
     clp = uvm_cmdline_processor::get_inst();
     if (!clp.get_arg_values("+CLP_SEQ=", seq_names))
@@ -115,6 +127,7 @@ class soc_ifc_cmdline_test_sequence extends soc_ifc_bench_sequence_base;
       cptra_ctrl_agent_config.wait_for_num_clocks(400);
       soc_ifc_status_agent_config.wait_for_num_clocks(400);
       cptra_status_agent_config.wait_for_num_clocks(400);
+      mbox_sram_agent_config.wait_for_num_clocks(400);
     join
 
     // pragma uvmf custom body end
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/sequences/src/soc_ifc_rand_test_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/sequences/src/soc_ifc_rand_test_sequence.svh
index 0f1f2d6b9..d2ef25610 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/sequences/src/soc_ifc_rand_test_sequence.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/sequences/src/soc_ifc_rand_test_sequence.svh
@@ -34,6 +34,7 @@ class soc_ifc_rand_test_sequence extends soc_ifc_bench_sequence_base;
 
   rand soc_ifc_env_bringup_sequence_t soc_ifc_env_bringup_seq;
   rand soc_ifc_env_cptra_rst_wait_sequence_t soc_ifc_env_cptra_rst_wait_seq;
+  rand soc_ifc_env_cptra_init_interrupts_sequence_t soc_ifc_env_cptra_init_interrupts_seq;
   rand soc_ifc_env_pauser_init_sequence_t soc_ifc_env_pauser_init_seq;
   rand soc_ifc_env_sequence_base_t soc_ifc_env_seq_ii[];
   // TODO: To add new sequences to the randomized portion of this test:
@@ -43,16 +44,29 @@ class soc_ifc_rand_test_sequence extends soc_ifc_bench_sequence_base;
   rand enum int {
       IDX_SOC_IFC_ENV_MBOX_TOP_RAND_SMALL,
       IDX_SOC_IFC_ENV_MBOX_TOP_RAND_MEDIUM,
+      IDX_SOC_IFC_ENV_MBOX_TOP_RAND_LARGE,
+      IDX_SOC_IFC_ENV_MBOX_TOP_MIN,
+      IDX_SOC_IFC_ENV_MBOX_TOP_MAX,
       IDX_SOC_IFC_ENV_MBOX_TOP_RAND_SMALL_UNLOCK,
       IDX_SOC_IFC_ENV_MBOX_TOP_RAND_MEDIUM_UNLOCK,
+      IDX_SOC_IFC_ENV_MBOX_TOP_RAND_LARGE_UNLOCK,
       IDX_SOC_IFC_ENV_MBOX_TOP_CONTENTION,
       IDX_SOC_IFC_ENV_MBOX_TOP_RAND_PAUSER_SMALL,
       IDX_SOC_IFC_ENV_MBOX_TOP_RAND_PAUSER_MEDIUM,
+      IDX_SOC_IFC_ENV_MBOX_TOP_RAND_PAUSER_LARGE,
       IDX_SOC_IFC_ENV_MBOX_TOP_RAND_PAUSER_SMALL_UNLOCK,
       IDX_SOC_IFC_ENV_MBOX_TOP_RAND_PAUSER_MEDIUM_UNLOCK,
+      IDX_SOC_IFC_ENV_MBOX_TOP_RAND_PAUSER_LARGE_UNLOCK,
+      IDX_SOC_IFC_ENV_MBOX_TOP_RAND_DELAY_SMALL,
+      IDX_SOC_IFC_ENV_MBOX_TOP_RAND_DELAY_MEDIUM,
+      IDX_SOC_IFC_ENV_MBOX_TOP_RAND_DELAY_LARGE,
+      IDX_SOC_IFC_ENV_MBOX_TOP_REG_AXS_INV_SMALL,
+      IDX_SOC_IFC_ENV_MBOX_TOP_REG_AXS_INV_MEDIUM,
+      IDX_SOC_IFC_ENV_MBOX_TOP_REG_AXS_INV_LARGE,
       IDX_SOC_IFC_ENV_MBOX_TOP_DLEN_VIOLATION,
       IDX_SOC_IFC_ENV_MBOX_TOP_MULTI_AGENT,
       IDX_SOC_IFC_ENV_CPTRA_MBOX_TOP_RAND_SMALL,
+      IDX_SOC_IFC_ENV_CPTRA_MBOX_TOP_REG_AXS_INV_SMALL,
       IDX_SOC_IFC_ENV_RST_WARM,
       IDX_SOC_IFC_ENV_RST_COLD,
       IDX_SOC_IFC_ENV_MBOX_RST_WARM_RAND_MEDIUM,
@@ -66,34 +80,73 @@ class soc_ifc_rand_test_sequence extends soc_ifc_bench_sequence_base;
       rand_seq_idx dist {
           IDX_SOC_IFC_ENV_MBOX_TOP_RAND_SMALL                := 25,
           IDX_SOC_IFC_ENV_MBOX_TOP_RAND_MEDIUM               := 25,
+          IDX_SOC_IFC_ENV_MBOX_TOP_RAND_LARGE                := 1,
+          IDX_SOC_IFC_ENV_MBOX_TOP_MIN                       := 25,
+          IDX_SOC_IFC_ENV_MBOX_TOP_MAX                       := 1,
           IDX_SOC_IFC_ENV_MBOX_TOP_RAND_SMALL_UNLOCK         := 25,
           IDX_SOC_IFC_ENV_MBOX_TOP_RAND_MEDIUM_UNLOCK        := 25,
+          IDX_SOC_IFC_ENV_MBOX_TOP_RAND_LARGE_UNLOCK         := 1,
           IDX_SOC_IFC_ENV_MBOX_TOP_CONTENTION                := 25,
           IDX_SOC_IFC_ENV_MBOX_TOP_RAND_PAUSER_SMALL         := 25,
           IDX_SOC_IFC_ENV_MBOX_TOP_RAND_PAUSER_MEDIUM        := 25,
+          IDX_SOC_IFC_ENV_MBOX_TOP_RAND_PAUSER_LARGE         := 1,
           IDX_SOC_IFC_ENV_MBOX_TOP_RAND_PAUSER_SMALL_UNLOCK  := 25,
           IDX_SOC_IFC_ENV_MBOX_TOP_RAND_PAUSER_MEDIUM_UNLOCK := 25,
-          IDX_SOC_IFC_ENV_MBOX_TOP_DLEN_VIOLATION            := 0, /*FIXME re-enable this after resolving data mismatch error */
+          IDX_SOC_IFC_ENV_MBOX_TOP_RAND_PAUSER_LARGE_UNLOCK  := 1,
+          IDX_SOC_IFC_ENV_MBOX_TOP_RAND_DELAY_SMALL          := 25,
+          IDX_SOC_IFC_ENV_MBOX_TOP_RAND_DELAY_MEDIUM         := 25,
+          IDX_SOC_IFC_ENV_MBOX_TOP_RAND_DELAY_LARGE          := 1,
+          IDX_SOC_IFC_ENV_MBOX_TOP_REG_AXS_INV_SMALL         := 25,
+          IDX_SOC_IFC_ENV_MBOX_TOP_REG_AXS_INV_MEDIUM        := 25,
+          IDX_SOC_IFC_ENV_MBOX_TOP_REG_AXS_INV_LARGE         := 1,
+          IDX_SOC_IFC_ENV_MBOX_TOP_DLEN_VIOLATION            := 25,
           IDX_SOC_IFC_ENV_MBOX_TOP_MULTI_AGENT               := 10,
           IDX_SOC_IFC_ENV_CPTRA_MBOX_TOP_RAND_SMALL          := 25,
+          IDX_SOC_IFC_ENV_CPTRA_MBOX_TOP_REG_AXS_INV_SMALL   := 25,
           IDX_SOC_IFC_ENV_RST_WARM                           := 1,
           IDX_SOC_IFC_ENV_RST_COLD                           := 1,
           IDX_SOC_IFC_ENV_MBOX_RST_WARM_RAND_MEDIUM          := 10,
           IDX_SOC_IFC_ENV_MBOX_RST_COLD_RAND_MEDIUM          := 10
       };
   }
+  constraint disable_long_env_seqs_c {
+      !(rand_seq_idx inside {IDX_SOC_IFC_ENV_MBOX_TOP_RAND_LARGE,
+                             IDX_SOC_IFC_ENV_MBOX_TOP_MAX,
+                             IDX_SOC_IFC_ENV_MBOX_TOP_RAND_LARGE_UNLOCK,
+                             IDX_SOC_IFC_ENV_MBOX_TOP_RAND_PAUSER_LARGE,
+                             IDX_SOC_IFC_ENV_MBOX_TOP_RAND_PAUSER_LARGE_UNLOCK,
+                             IDX_SOC_IFC_ENV_MBOX_TOP_RAND_DELAY_MEDIUM,
+                             IDX_SOC_IFC_ENV_MBOX_TOP_RAND_DELAY_LARGE,
+                             IDX_SOC_IFC_ENV_MBOX_TOP_DLEN_VIOLATION,
+                             IDX_SOC_IFC_ENV_MBOX_TOP_REG_AXS_INV_LARGE,
+                             IDX_SOC_IFC_ENV_MBOX_TOP_MULTI_AGENT});
+  }
   // FIXME we're also running multiple iterations of this testcase in the regression.
   //       What is the criteria for iteration count WITHIN the sequence?
   constraint iter_count_c {
       iteration_count inside {[1:10]};
   }
+  constraint iter_count_short_c {
+      iteration_count < 5;
+  }
 
   function new(string name = "" );
     super.new(name);
+    // The short test suite is used in promote pipeline to quickly check for UVM issues
+    if ($test$plusargs("CLP_SHORT_SUITE")) begin
+        this.disable_long_env_seqs_c.constraint_mode(1);
+        this.iter_count_short_c.constraint_mode(1);
+    end
+    else begin
+        this.disable_long_env_seqs_c.constraint_mode(0);
+        this.iter_count_short_c.constraint_mode(0);
+    end
+    // Users can manually override the number of random iterations to any desired value
     if ($value$plusargs("SOC_IFC_RAND_ITER=%0d", iteration_count)) begin
         `uvm_info("SOC_IFC_RAND_TEST", $sformatf("Received Command Line Iteration Count Argument of %0d", iteration_count), UVM_LOW);
         iteration_count.rand_mode(0);
         this.iter_count_c.constraint_mode(0);
+        this.iter_count_short_c.constraint_mode(0);
     end
     else begin
         if (!this.randomize(iteration_count))
@@ -111,20 +164,25 @@ class soc_ifc_rand_test_sequence extends soc_ifc_bench_sequence_base;
     uvm_object obj;
     int ii;
     bit do_pauser_init;
+    int unsigned mbox_ecc_single_error_burst;
+    int unsigned mbox_ecc_single_error_delay_clocks;
 
     soc_ifc_env_bringup_seq        = soc_ifc_env_bringup_sequence_t::type_id::create("soc_ifc_env_bringup_seq");
     soc_ifc_env_cptra_rst_wait_seq = soc_ifc_env_cptra_rst_wait_sequence_t::type_id::create("soc_ifc_env_cptra_rst_wait_seq");
 
-    soc_ifc_env_pauser_init_seq        = soc_ifc_env_pauser_init_sequence_t::type_id::create("soc_ifc_env_pauser_init_seq");
+    soc_ifc_env_cptra_init_interrupts_seq = soc_ifc_env_cptra_init_interrupts_sequence_t::type_id::create("soc_ifc_env_cptra_init_interrupts_seq");
+    soc_ifc_env_pauser_init_seq           = soc_ifc_env_pauser_init_sequence_t::type_id::create("soc_ifc_env_pauser_init_seq");
 
     soc_ifc_ctrl_agent_random_seq      = soc_ifc_ctrl_agent_random_seq_t::type_id::create("soc_ifc_ctrl_agent_random_seq");
     cptra_ctrl_agent_random_seq        = cptra_ctrl_agent_random_seq_t::type_id::create("cptra_ctrl_agent_random_seq");
     soc_ifc_status_agent_responder_seq = soc_ifc_status_agent_responder_seq_t::type_id::create("soc_ifc_status_agent_responder_seq");
     cptra_status_agent_responder_seq   = cptra_status_agent_responder_seq_t::type_id::create("cptra_status_agent_responder_seq");
+    mbox_sram_agent_responder_seq      = mbox_sram_agent_responder_seq_t::type_id::create("mbox_sram_agent_responder_seq");
 
     // Handle to the responder sequence for getting response transactions
     soc_ifc_env_bringup_seq.soc_ifc_status_agent_rsp_seq = soc_ifc_status_agent_responder_seq;
     soc_ifc_env_cptra_rst_wait_seq.cptra_status_agent_rsp_seq = cptra_status_agent_responder_seq;
+    soc_ifc_env_cptra_init_interrupts_seq.cptra_status_agent_rsp_seq = cptra_status_agent_responder_seq;
     soc_ifc_env_pauser_init_seq.soc_ifc_status_agent_rsp_seq = soc_ifc_status_agent_responder_seq;
 
 //    fork
@@ -138,9 +196,25 @@ class soc_ifc_rand_test_sequence extends soc_ifc_bench_sequence_base;
     fork
         soc_ifc_status_agent_responder_seq.start(soc_ifc_status_agent_sequencer);
         cptra_status_agent_responder_seq.start(cptra_status_agent_sequencer);
+        mbox_sram_agent_responder_seq.start(mbox_sram_agent_sequencer);
     join_none
 
     // Start INITIATOR sequences here
+    fork
+        forever begin
+            if (!std::randomize(mbox_ecc_single_error_burst,mbox_ecc_single_error_delay_clocks) with {mbox_ecc_single_error_burst        dist {1 :/ 1000, [2:5] :/ 100, [6:31] :/ 20, [32:131071] :/ 1, [131072:524288] :/ 1};
+                                                                                                      mbox_ecc_single_error_delay_clocks dist {1 :/ 1, [2:31] :/ 3, [32:127] :/ 5, [128:1023] :/ 3, [1024:131072] :/ 1};    })
+                `uvm_fatal("SOC_IFC_RAND_TEST", "Failed to randomize mbox ecc bit flip injection parameters")
+            else
+                `uvm_info("SOC_IFC_RAND_TEST", $sformatf("Randomized mbox ecc bit flip injection parameters: burst [%0d] delay [%0d clocks]", mbox_ecc_single_error_burst, mbox_ecc_single_error_delay_clocks), UVM_DEBUG)
+            soc_ifc_ctrl_agent_config.wait_for_num_clocks(mbox_ecc_single_error_delay_clocks);
+            `uvm_info("SOC_IFC_RAND_TEST", $sformatf("Injecting mbox ecc error with burst [%0d]", mbox_ecc_single_error_burst), UVM_DEBUG)
+            repeat(mbox_ecc_single_error_burst) begin
+                mbox_sram_agent_config.inject_ecc_error |= 2'b01;
+                @mbox_sram_agent_responder_seq.new_rsp;
+            end
+        end
+    join_none
     fork
     begin
         // Bringup (set pwrgood, deassert cptra_rst_b, write fuses)
@@ -155,17 +229,26 @@ class soc_ifc_rand_test_sequence extends soc_ifc_bench_sequence_base;
     end
     join
 
-    // Choose whether or not to initialize/lock PAUSER valid values at random
-    if (!std::randomize(do_pauser_init) with { do_pauser_init dist {0:/25, 1:/75}; })
-        `uvm_error("SOC_IFC_RAND_TEST", "Failed to randomize do_pauser_init")
-    else if (do_pauser_init) begin
-        if(!soc_ifc_env_pauser_init_seq.randomize())
-            `uvm_fatal("SOC_IFC_RAND_TEST", "soc_ifc_rand_test_sequence::body() - soc_ifc_env_pauser_init_seq randomization failed");
-        soc_ifc_env_pauser_init_seq.start(top_configuration.vsqr);
-    end
-    else begin
-        `uvm_info("SOC_IFC_RAND_TEST", "Skipping PAUSER init", UVM_MEDIUM)
-    end
+    fork
+        // Choose whether or not to initialize/lock PAUSER valid values at random
+        if (!std::randomize(do_pauser_init) with { do_pauser_init dist {0:/25, 1:/75}; })
+            `uvm_error("SOC_IFC_RAND_TEST", "Failed to randomize do_pauser_init")
+        else if (do_pauser_init) begin
+            if(!soc_ifc_env_pauser_init_seq.randomize())
+                `uvm_fatal("SOC_IFC_RAND_TEST", "soc_ifc_rand_test_sequence::body() - soc_ifc_env_pauser_init_seq randomization failed");
+            soc_ifc_env_pauser_init_seq.start(top_configuration.vsqr);
+        end
+        else begin
+            `uvm_info("SOC_IFC_RAND_TEST", "Skipping PAUSER init", UVM_MEDIUM)
+        end
+        // Always initialize interrupts
+        // TODO - if we make this random, we can test both interrupt-driven and
+        // polling behavior
+        begin
+            soc_ifc_env_cptra_init_interrupts_seq.start(top_configuration.vsqr);
+            `uvm_info("SOC_IFC_RAND_TEST", "Completed interrupt init", UVM_MEDIUM)
+        end
+    join
 
     for (ii = 0; ii < iteration_count; ii++) begin: RAND_LOOP
         if(!this.randomize(rand_seq_idx)) `uvm_fatal("SOC_IFC_RAND_TEST", "Failed to randomize rand_seq_idx");
@@ -176,26 +259,52 @@ class soc_ifc_rand_test_sequence extends soc_ifc_bench_sequence_base;
                 obj = soc_ifc_env_top_mbox_rand_small_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
             IDX_SOC_IFC_ENV_MBOX_TOP_RAND_MEDIUM:
                 obj = soc_ifc_env_top_mbox_rand_medium_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
+            IDX_SOC_IFC_ENV_MBOX_TOP_RAND_LARGE:
+                obj = soc_ifc_env_top_mbox_rand_large_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
+            IDX_SOC_IFC_ENV_MBOX_TOP_MIN:
+                obj = soc_ifc_env_top_mbox_min_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
+            IDX_SOC_IFC_ENV_MBOX_TOP_MAX:
+                obj = soc_ifc_env_top_mbox_max_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
             IDX_SOC_IFC_ENV_MBOX_TOP_RAND_SMALL_UNLOCK:
                 obj = soc_ifc_env_top_mbox_rand_small_unlock_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
             IDX_SOC_IFC_ENV_MBOX_TOP_RAND_MEDIUM_UNLOCK:
                 obj = soc_ifc_env_top_mbox_rand_medium_unlock_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
+            IDX_SOC_IFC_ENV_MBOX_TOP_RAND_LARGE_UNLOCK:
+                obj = soc_ifc_env_top_mbox_rand_large_unlock_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
             IDX_SOC_IFC_ENV_MBOX_TOP_CONTENTION:
                 obj = soc_ifc_env_top_mbox_contention_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
             IDX_SOC_IFC_ENV_MBOX_TOP_RAND_PAUSER_SMALL:
                 obj = soc_ifc_env_top_mbox_rand_pauser_small_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
             IDX_SOC_IFC_ENV_MBOX_TOP_RAND_PAUSER_MEDIUM:
                 obj = soc_ifc_env_top_mbox_rand_pauser_medium_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
+            IDX_SOC_IFC_ENV_MBOX_TOP_RAND_PAUSER_LARGE:
+                obj = soc_ifc_env_top_mbox_rand_pauser_large_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
             IDX_SOC_IFC_ENV_MBOX_TOP_RAND_PAUSER_SMALL_UNLOCK:
                 obj = soc_ifc_env_top_mbox_rand_pauser_small_unlock_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
             IDX_SOC_IFC_ENV_MBOX_TOP_RAND_PAUSER_MEDIUM_UNLOCK:
                 obj = soc_ifc_env_top_mbox_rand_pauser_medium_unlock_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
+            IDX_SOC_IFC_ENV_MBOX_TOP_RAND_PAUSER_LARGE_UNLOCK:
+                obj = soc_ifc_env_top_mbox_rand_pauser_large_unlock_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
+            IDX_SOC_IFC_ENV_MBOX_TOP_RAND_DELAY_SMALL:
+                obj = soc_ifc_env_top_mbox_rand_delay_small_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
+            IDX_SOC_IFC_ENV_MBOX_TOP_RAND_DELAY_MEDIUM:
+                obj = soc_ifc_env_top_mbox_rand_delay_medium_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
+            IDX_SOC_IFC_ENV_MBOX_TOP_RAND_DELAY_LARGE:
+                obj = soc_ifc_env_top_mbox_rand_delay_large_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
+            IDX_SOC_IFC_ENV_MBOX_TOP_REG_AXS_INV_SMALL:
+                obj = soc_ifc_env_top_mbox_reg_axs_invalid_small_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
+            IDX_SOC_IFC_ENV_MBOX_TOP_REG_AXS_INV_MEDIUM:
+                obj = soc_ifc_env_top_mbox_reg_axs_invalid_medium_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
+            IDX_SOC_IFC_ENV_MBOX_TOP_REG_AXS_INV_LARGE:
+                obj = soc_ifc_env_top_mbox_reg_axs_invalid_large_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
             IDX_SOC_IFC_ENV_MBOX_TOP_DLEN_VIOLATION:
                 obj = soc_ifc_env_top_mbox_dlen_violation_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
             IDX_SOC_IFC_ENV_MBOX_TOP_MULTI_AGENT:
                 obj = soc_ifc_env_top_mbox_multi_agent_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
             IDX_SOC_IFC_ENV_CPTRA_MBOX_TOP_RAND_SMALL:
                 obj = soc_ifc_env_top_cptra_mbox_rand_small_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
+            IDX_SOC_IFC_ENV_CPTRA_MBOX_TOP_REG_AXS_INV_SMALL:
+                obj = soc_ifc_env_top_cptra_mbox_reg_axs_invalid_small_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
             IDX_SOC_IFC_ENV_RST_WARM:
                 obj = soc_ifc_env_top_reset_warm_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii));
             IDX_SOC_IFC_ENV_RST_COLD:
@@ -217,6 +326,20 @@ class soc_ifc_rand_test_sequence extends soc_ifc_bench_sequence_base;
         soc_ifc_env_seq_ii[ii].soc_ifc_status_agent_rsp_seq = soc_ifc_status_agent_responder_seq;
         soc_ifc_env_seq_ii[ii].cptra_status_agent_rsp_seq   = cptra_status_agent_responder_seq;
         soc_ifc_env_seq_ii[ii].start(top_configuration.vsqr);
+
+        // If the last run sequence triggered a reset, rerun interrupt initialization
+        case (rand_seq_idx) inside
+            IDX_SOC_IFC_ENV_RST_WARM,
+            IDX_SOC_IFC_ENV_RST_COLD,
+            IDX_SOC_IFC_ENV_MBOX_RST_WARM_RAND_MEDIUM,
+            IDX_SOC_IFC_ENV_MBOX_RST_COLD_RAND_MEDIUM: begin
+                `uvm_info("SOC_IFC_RAND_TEST", "Rerunning interrupt init after reset", UVM_MEDIUM)
+                soc_ifc_env_cptra_init_interrupts_seq = soc_ifc_env_cptra_init_interrupts_sequence_t::type_id::create($sformatf("soc_ifc_env_cptra_init_interrupts_seq[%0d]",ii));
+                soc_ifc_env_cptra_init_interrupts_seq.cptra_status_agent_rsp_seq = cptra_status_agent_responder_seq;
+                soc_ifc_env_cptra_init_interrupts_seq.start(top_configuration.vsqr);
+                `uvm_info("SOC_IFC_RAND_TEST", "Completed interrupt init", UVM_MEDIUM)
+            end
+        endcase
     end
 
     // UVMF_CHANGE_ME : Extend the simulation XXX number of clocks after 
@@ -227,6 +350,7 @@ class soc_ifc_rand_test_sequence extends soc_ifc_bench_sequence_base;
       cptra_ctrl_agent_config.wait_for_num_clocks(400);
       soc_ifc_status_agent_config.wait_for_num_clocks(400);
       cptra_status_agent_config.wait_for_num_clocks(400);
+      mbox_sram_agent_config.wait_for_num_clocks(400);
     join
 
     // pragma uvmf custom body end
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/sequences/src/soc_ifc_trng_test_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/sequences/src/soc_ifc_trng_test_sequence.svh
index 0e838834a..4c9999757 100755
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/sequences/src/soc_ifc_trng_test_sequence.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/sequences/src/soc_ifc_trng_test_sequence.svh
@@ -75,8 +75,6 @@ class soc_ifc_trng_test_sequence extends soc_ifc_bench_sequence_base;
 
   // ****************************************************************************
   virtual task body();
-    // pragma uvmf custom body begin
-    // Construct sequences here
     uvm_object obj;
     int ii;
 
@@ -89,6 +87,7 @@ class soc_ifc_trng_test_sequence extends soc_ifc_bench_sequence_base;
     cptra_ctrl_agent_random_seq        = cptra_ctrl_agent_random_seq_t::type_id::create("cptra_ctrl_agent_random_seq");
     soc_ifc_status_agent_responder_seq = soc_ifc_status_agent_responder_seq_t::type_id::create("soc_ifc_status_agent_responder_seq");
     cptra_status_agent_responder_seq   = cptra_status_agent_responder_seq_t::type_id::create("cptra_status_agent_responder_seq");
+    mbox_sram_agent_responder_seq      = mbox_sram_agent_responder_seq_t::type_id::create("mbox_sram_agent_responder_seq");
 
     // Handle to the responder sequence for getting response transactions
     soc_ifc_env_bringup_seq.soc_ifc_status_agent_rsp_seq = soc_ifc_status_agent_responder_seq;
@@ -100,6 +99,7 @@ class soc_ifc_trng_test_sequence extends soc_ifc_bench_sequence_base;
     fork
         soc_ifc_status_agent_responder_seq.start(soc_ifc_status_agent_sequencer);
         cptra_status_agent_responder_seq.start(cptra_status_agent_sequencer);
+        mbox_sram_agent_responder_seq.start(mbox_sram_agent_sequencer);
     join_none
 
     // Start INITIATOR sequences here
@@ -148,6 +148,7 @@ class soc_ifc_trng_test_sequence extends soc_ifc_bench_sequence_base;
         cptra_ctrl_agent_config.wait_for_num_clocks(400);
         soc_ifc_status_agent_config.wait_for_num_clocks(400);
         cptra_status_agent_config.wait_for_num_clocks(400);
+        mbox_sram_agent_config.wait_for_num_clocks(400);
     join
 
     if (1) // TODO -- how to properly choose which to print?
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/testbench/hdl_top.compile b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/testbench/hdl_top.compile
index 9c923c2dc..408eb4545 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/testbench/hdl_top.compile
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/testbench/hdl_top.compile
@@ -8,5 +8,6 @@ needs:
   - ../../../../verification_ip/interface_packages/cptra_ctrl_pkg/cptra_ctrl_hdl.compile
   - ../../../../verification_ip/interface_packages/soc_ifc_status_pkg/soc_ifc_status_hdl.compile
   - ../../../../verification_ip/interface_packages/cptra_status_pkg/cptra_status_hdl.compile
+  - ../../../../verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_hdl.compile
 src:
   - hdl_top.sv
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/testbench/hdl_top.sv b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/testbench/hdl_top.sv
index 9d8d6fdb5..621ee5af9 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/testbench/hdl_top.sv
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/testbench/hdl_top.sv
@@ -82,28 +82,6 @@ import uvmf_base_pkg_hdl::*;
 // pragma uvmf custom reset_generator end
 
   // pragma uvmf custom module_item_additional begin
-import soc_ifc_pkg::*;
-    mbox_sram_req_t  mbox_sram_req;
-    mbox_sram_resp_t mbox_sram_resp;
-
-    //SRAM for mbox
-    caliptra_sram 
-    #(
-        .DATA_WIDTH(MBOX_DATA_AND_ECC_W),
-        .DEPTH(MBOX_DEPTH)
-    )
-    i_mbox_ram
-    (
-        .clk_i(clk),
-        
-        .cs_i   (mbox_sram_req.cs   ),
-        .we_i   (mbox_sram_req.we   ),
-        .addr_i (mbox_sram_req.addr ),
-        .wdata_i(mbox_sram_req.wdata),
-        
-        .rdata_o(mbox_sram_resp.rdata)
-    );
-    initial i_mbox_ram.ram = '{default:8'h0};
   // pragma uvmf custom module_item_additional end
 
   // Instantiate the signal bundle, monitor bfm and driver bfm for each interface.
@@ -130,21 +108,28 @@ import soc_ifc_pkg::*;
      .clk(clk), .dummy(1'b1)
      // pragma uvmf custom cptra_status_agent_bus_connections end
      );
+  mbox_sram_if  mbox_sram_agent_bus(
+     // pragma uvmf custom mbox_sram_agent_bus_connections begin
+     .clk(clk), .dummy(1'b1)
+     // pragma uvmf custom mbox_sram_agent_bus_connections end
+     );
   soc_ifc_ctrl_monitor_bfm  soc_ifc_ctrl_agent_mon_bfm(soc_ifc_ctrl_agent_bus.monitor_port);
   cptra_ctrl_monitor_bfm  cptra_ctrl_agent_mon_bfm(cptra_ctrl_agent_bus.monitor_port);
   soc_ifc_status_monitor_bfm  soc_ifc_status_agent_mon_bfm(soc_ifc_status_agent_bus.monitor_port);
   cptra_status_monitor_bfm  cptra_status_agent_mon_bfm(cptra_status_agent_bus.monitor_port);
+  mbox_sram_monitor_bfm  mbox_sram_agent_mon_bfm(mbox_sram_agent_bus.monitor_port);
   soc_ifc_ctrl_driver_bfm  soc_ifc_ctrl_agent_drv_bfm(soc_ifc_ctrl_agent_bus.initiator_port);
   cptra_ctrl_driver_bfm  cptra_ctrl_agent_drv_bfm(cptra_ctrl_agent_bus.initiator_port);
   soc_ifc_status_driver_bfm  soc_ifc_status_agent_drv_bfm(soc_ifc_status_agent_bus.responder_port);
   cptra_status_driver_bfm  cptra_status_agent_drv_bfm(cptra_status_agent_bus.responder_port);
+  mbox_sram_driver_bfm  mbox_sram_agent_drv_bfm(mbox_sram_agent_bus.responder_port);
 
   // pragma uvmf custom dut_instantiation begin
   // AHB Clock/reset
   assign uvm_test_top_environment_qvip_ahb_lite_slave_subenv_qvip_hdl.default_clk_gen_CLK     = clk;
   assign uvm_test_top_environment_qvip_ahb_lite_slave_subenv_qvip_hdl.default_reset_gen_RESET = cptra_status_agent_bus.cptra_noncore_rst_b;
   assign uvm_test_top_environment_qvip_apb5_slave_subenv_qvip_hdl.default_clk_gen_CLK         = clk;
-  assign uvm_test_top_environment_qvip_apb5_slave_subenv_qvip_hdl.default_reset_gen_RESET     = soc_ifc_ctrl_agent_bus.cptra_rst_b;
+  assign uvm_test_top_environment_qvip_apb5_slave_subenv_qvip_hdl.default_reset_gen_RESET     = cptra_status_agent_bus.cptra_noncore_rst_b;
 
   // DUT
     soc_ifc_top #(
@@ -159,6 +144,9 @@ import soc_ifc_pkg::*;
         .clk               (clk               ),
         .clk_cg            (clk               ),
         .soc_ifc_clk_cg    (clk               ),
+        .rdc_clk_cg        (clk               ),
+        .rdc_clk_dis (),
+        .fw_update_rst_window (cptra_status_agent_bus.fw_update_rst_window),
         .cptra_pwrgood     (soc_ifc_ctrl_agent_bus.cptra_pwrgood     ),
         .cptra_rst_b       (soc_ifc_ctrl_agent_bus.cptra_rst_b       ),
         .ready_for_fuses   (soc_ifc_status_agent_bus.ready_for_fuses   ),
@@ -168,15 +156,14 @@ import soc_ifc_pkg::*;
         .mailbox_flow_done (soc_ifc_status_agent_bus.mailbox_flow_done ),
 
         .security_state    (soc_ifc_ctrl_agent_bus.security_state),
-        .scan_mode_f       (1'b0),
 
         .generic_input_wires (soc_ifc_ctrl_agent_bus.generic_input_wires ),
         .BootFSM_BrkPoint    (soc_ifc_ctrl_agent_bus.BootFSM_BrkPoint),
         .generic_output_wires(soc_ifc_status_agent_bus.generic_output_wires),
 
         //SRAM interface
-        .mbox_sram_req(mbox_sram_req),
-        .mbox_sram_resp(mbox_sram_resp),
+        .mbox_sram_req(mbox_sram_agent_bus.mbox_sram_req),
+        .mbox_sram_resp(mbox_sram_agent_bus.mbox_sram_resp),
 
         //APB Interface with SoC
         .paddr_i  (uvm_test_top_environment_qvip_apb5_slave_subenv_qvip_hdl.apb5_master_0_PADDR[17:0]),
@@ -209,14 +196,19 @@ import soc_ifc_pkg::*;
         .soc_ifc_notif_intr(cptra_status_agent_bus.soc_ifc_notif_intr),
         .sha_error_intr(cptra_status_agent_bus.sha_error_intr),
         .sha_notif_intr(cptra_status_agent_bus.sha_notif_intr),
+        .timer_intr(cptra_status_agent_bus.timer_intr),
+        // RV ECC Status Interface
+        .rv_ecc_sts(cptra_ctrl_agent_bus.rv_ecc_sts),
         //Obfuscated UDS and FE
+        .clear_obf_secrets(cptra_ctrl_agent_bus.clear_obf_secrets),
+        .scan_mode_f       (1'b0),
         .cptra_obf_key(soc_ifc_ctrl_agent_bus.cptra_obf_key),
         .cptra_obf_key_reg(cptra_status_agent_bus.cptra_obf_key_reg),
         .obf_field_entropy(cptra_status_agent_bus.obf_field_entropy),
         .obf_uds_seed(cptra_status_agent_bus.obf_uds_seed),
-        .clear_obf_secrets(cptra_ctrl_agent_bus.clear_obf_secrets),
         // NMI Vector 
         .nmi_vector(cptra_status_agent_bus.nmi_vector),
+        .nmi_intr(cptra_status_agent_bus.nmi_intr),
         // ICCM Lock
         .iccm_lock(cptra_status_agent_bus.iccm_lock),
         .iccm_axs_blocked(cptra_ctrl_agent_bus.iccm_axs_blocked),
@@ -273,10 +265,12 @@ import soc_ifc_pkg::*;
     uvm_config_db #( virtual cptra_ctrl_monitor_bfm  )::set( null , UVMF_VIRTUAL_INTERFACES , cptra_ctrl_agent_BFM , cptra_ctrl_agent_mon_bfm ); 
     uvm_config_db #( virtual soc_ifc_status_monitor_bfm  )::set( null , UVMF_VIRTUAL_INTERFACES , soc_ifc_status_agent_BFM , soc_ifc_status_agent_mon_bfm ); 
     uvm_config_db #( virtual cptra_status_monitor_bfm  )::set( null , UVMF_VIRTUAL_INTERFACES , cptra_status_agent_BFM , cptra_status_agent_mon_bfm ); 
+    uvm_config_db #( virtual mbox_sram_monitor_bfm  )::set( null , UVMF_VIRTUAL_INTERFACES , mbox_sram_agent_BFM , mbox_sram_agent_mon_bfm ); 
     uvm_config_db #( virtual soc_ifc_ctrl_driver_bfm  )::set( null , UVMF_VIRTUAL_INTERFACES , soc_ifc_ctrl_agent_BFM , soc_ifc_ctrl_agent_drv_bfm  );
     uvm_config_db #( virtual cptra_ctrl_driver_bfm  )::set( null , UVMF_VIRTUAL_INTERFACES , cptra_ctrl_agent_BFM , cptra_ctrl_agent_drv_bfm  );
     uvm_config_db #( virtual soc_ifc_status_driver_bfm  )::set( null , UVMF_VIRTUAL_INTERFACES , soc_ifc_status_agent_BFM , soc_ifc_status_agent_drv_bfm  );
     uvm_config_db #( virtual cptra_status_driver_bfm  )::set( null , UVMF_VIRTUAL_INTERFACES , cptra_status_agent_BFM , cptra_status_agent_drv_bfm  );
+    uvm_config_db #( virtual mbox_sram_driver_bfm  )::set( null , UVMF_VIRTUAL_INTERFACES , mbox_sram_agent_BFM , mbox_sram_agent_drv_bfm  );
   end
 
 endmodule
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/testbench/hdl_top.vinfo b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/testbench/hdl_top.vinfo
index 684e5069f..b4204c2c8 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/testbench/hdl_top.vinfo
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/testbench/hdl_top.vinfo
@@ -5,4 +5,5 @@
 @use $UVMF_VIP_LIBRARY_HOME/interface_packages/cptra_ctrl_pkg/cptra_ctrl_bfm.vinfo
 @use $UVMF_VIP_LIBRARY_HOME/interface_packages/soc_ifc_status_pkg/soc_ifc_status_bfm.vinfo
 @use $UVMF_VIP_LIBRARY_HOME/interface_packages/cptra_status_pkg/cptra_status_bfm.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/interface_packages/mbox_sram_pkg/mbox_sram_bfm.vinfo
 hdl_top.sv
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/tests/soc_ifc_tests_pkg.compile b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/tests/soc_ifc_tests_pkg.compile
index a98a9e77e..863735d42 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/tests/soc_ifc_tests_pkg.compile
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/tests/soc_ifc_tests_pkg.compile
@@ -4,6 +4,7 @@ needs:
   - ../../../../verification_ip/interface_packages/cptra_ctrl_pkg/cptra_ctrl.compile
   - ../../../../verification_ip/interface_packages/soc_ifc_status_pkg/soc_ifc_status.compile
   - ../../../../verification_ip/interface_packages/cptra_status_pkg/cptra_status.compile
+  - ../../../../verification_ip/interface_packages/mbox_sram_pkg/mbox_sram.compile
   - ../../../../verification_ip/environment_packages/soc_ifc_env_pkg/soc_ifc_env_pkg.compile
   - ../parameters/soc_ifc_parameters_pkg.compile
   - ../sequences/soc_ifc_sequences_pkg.compile
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/tests/soc_ifc_tests_pkg.sv b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/tests/soc_ifc_tests_pkg.sv
index 65cac7397..b06dc5f37 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/tests/soc_ifc_tests_pkg.sv
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/tests/soc_ifc_tests_pkg.sv
@@ -47,6 +47,8 @@ package soc_ifc_tests_pkg;
    import soc_ifc_status_pkg_hdl::*;
    import cptra_status_pkg::*;
    import cptra_status_pkg_hdl::*;
+   import mbox_sram_pkg::*;
+   import mbox_sram_pkg_hdl::*;
    import qvip_ahb_lite_slave_pkg::*;
    import qvip_apb5_slave_pkg::*;
    import QUESTA_MVC::*;
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/tests/soc_ifc_tests_pkg.vinfo b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/tests/soc_ifc_tests_pkg.vinfo
index f8d3f85bb..a9a3e891c 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/tests/soc_ifc_tests_pkg.vinfo
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/tests/soc_ifc_tests_pkg.vinfo
@@ -3,6 +3,7 @@
 @use $UVMF_VIP_LIBRARY_HOME/interface_packages/cptra_ctrl_pkg/cptra_ctrl_pkg.vinfo
 @use $UVMF_VIP_LIBRARY_HOME/interface_packages/soc_ifc_status_pkg/soc_ifc_status_pkg.vinfo
 @use $UVMF_VIP_LIBRARY_HOME/interface_packages/cptra_status_pkg/cptra_status_pkg.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/interface_packages/mbox_sram_pkg/mbox_sram_pkg.vinfo
 @use $UVMF_VIP_LIBRARY_HOME/environment_packages/soc_ifc_env_pkg/soc_ifc_env_pkg.vinfo
 @use $UVMF_PROJECT_DIR/tb/parameters/soc_ifc_parameters_pkg.vinfo
 @use $UVMF_PROJECT_DIR/tb/sequences/soc_ifc_sequences_pkg.vinfo
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/tests/src/soc_ifc_cmdline_test.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/tests/src/soc_ifc_cmdline_test.svh
index 751c66016..b58f42ed6 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/tests/src/soc_ifc_cmdline_test.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/tests/src/soc_ifc_cmdline_test.svh
@@ -50,4 +50,18 @@ class soc_ifc_cmdline_test extends test_top;
     // pragma uvmf custom configuration_settings_post_randomize end
   endfunction
 
+
+
+
+  virtual function void start_of_simulation_phase(uvm_phase phase);
+      super.start_of_simulation_phase(phase);
+      if ($test$plusargs("CLP_REGRESSION")) begin
+          uvm_top.set_report_verbosity_level_hier(UVM_NONE);
+//          this.environment.soc_ifc_pred.set_report_severity_action(UVM_WARNING,UVM_NO_ACTION);
+//          this.environment.soc_ifc_sb.set_report_severity_action(UVM_WARNING,UVM_NO_ACTION);
+          // Since en_sb is recently set to 0, this is unavailable and gives null-object
+          //this.environment.qvip_apb5_slave_subenv.apb5_master_0.get_analysis_component("checker").set_report_severity_id_action(UVM_WARNING,"scoreboard_debug",UVM_NO_ACTION);
+      end
+  endfunction
+
 endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/tests/src/soc_ifc_rand_test.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/tests/src/soc_ifc_rand_test.svh
index 14a9717fb..a8d6707ff 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/tests/src/soc_ifc_rand_test.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/tests/src/soc_ifc_rand_test.svh
@@ -65,8 +65,3 @@ class soc_ifc_rand_test extends test_top;
   endfunction
 
 endclass
-
-// pragma uvmf custom external begin
-// pragma uvmf custom external end
-
-
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/tests/src/test_top.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/tests/src/test_top.svh
index fa64454af..b5d8893a9 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/tests/src/test_top.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/tests/src/test_top.svh
@@ -52,7 +52,8 @@ qvip_memory_message_handler message_handler;
     soc_ifc_ctrl_agent_BFM /* soc_ifc_ctrl_agent     [2] */ , 
     cptra_ctrl_agent_BFM /* cptra_ctrl_agent     [3] */ , 
     soc_ifc_status_agent_BFM /* soc_ifc_status_agent     [4] */ , 
-    cptra_status_agent_BFM /* cptra_status_agent     [5] */ 
+    cptra_status_agent_BFM /* cptra_status_agent     [5] */ , 
+    mbox_sram_agent_BFM /* mbox_sram_agent     [6] */ 
 };
 
 uvmf_active_passive_t interface_activities[] = { 
@@ -61,7 +62,8 @@ uvmf_active_passive_t interface_activities[] = {
     ACTIVE /* soc_ifc_ctrl_agent     [2] */ , 
     ACTIVE /* cptra_ctrl_agent     [3] */ , 
     ACTIVE /* soc_ifc_status_agent     [4] */ , 
-    ACTIVE /* cptra_status_agent     [5] */   };
+    ACTIVE /* cptra_status_agent     [5] */ , 
+    ACTIVE /* mbox_sram_agent     [6] */   };
 
   // pragma uvmf custom class_item_additional begin
   // pragma uvmf custom class_item_additional end
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/yaml/soc_ifc_bench.yaml b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/yaml/soc_ifc_bench.yaml
index 956ac2c87..755953538 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/yaml/soc_ifc_bench.yaml
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/yaml/soc_ifc_bench.yaml
@@ -10,6 +10,8 @@ uvmf:
         value: ACTIVE
       - bfm_name: cptra_status_agent
         value: ACTIVE
+      - bfm_name: mbox_sram_agent
+        value: ACTIVE
       active_passive_default: ACTIVE
       clock_half_period: 5ns
       clock_phase_offset: 0ns
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_intr_block_rf_ext_error_internal_intr_r_base.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_intr_block_rf_ext_error_internal_intr_r_base.svh
index 2f69c01fb..6ce03ec1d 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_intr_block_rf_ext_error_internal_intr_r_base.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_intr_block_rf_ext_error_internal_intr_r_base.svh
@@ -21,6 +21,14 @@ class soc_ifc_reg_cbs_intr_block_rf_ext_error_internal_intr_r_base extends uvm_r
     string AHB_map_name = "soc_ifc_AHB_map";
     string APB_map_name = "soc_ifc_APB_map";
 
+    uvm_queue #(soc_ifc_reg_delay_job) delay_jobs;
+
+    function new(string name = "uvm_reg_cbs");
+        super.new(name);
+        if (!uvm_config_db#(uvm_queue#(soc_ifc_reg_delay_job))::get(null, "soc_ifc_reg_model_top", "delay_jobs", delay_jobs))
+            `uvm_error("SOC_IFC_REG_CBS", "Failed to get handle for 'delay_jobs' queue from config database!")
+    endfunction
+
     // Function: post_predict
     //
     // Called by the <uvm_reg_field::predict()> method
@@ -36,7 +44,11 @@ class soc_ifc_reg_cbs_intr_block_rf_ext_error_internal_intr_r_base extends uvm_r
                                        input uvm_predict_e  kind,
                                        input uvm_path_e     path,
                                        input uvm_reg_map    map);
+        soc_ifc_reg_delay_job_intr_block_rf_ext delay_job;
         uvm_reg_block rm;
+        soc_ifc_reg__intr_block_t_ext    sir_intr_rm;
+        sha512_acc_csr__intr_block_t_ext sac_intr_rm;
+        bit           fld_hwset_active = 1'b0;
         uvm_reg       sts_reg;
         string event_name    ;
         uvm_reg       en_reg ;
@@ -45,8 +57,21 @@ class soc_ifc_reg_cbs_intr_block_rf_ext_error_internal_intr_r_base extends uvm_r
         uvm_reg_field sts_glb;
         uvm_reg_field cnt_fld;
 
+        delay_job = soc_ifc_reg_delay_job_intr_block_rf_ext::type_id::create("delay_job");
+        delay_job.map = map;
         sts_reg = fld.get_parent();
         rm = sts_reg.get_parent(); /* intr_block_rf_ext */
+        if (rm.get_parent().get_name() == "sha512_acc_csr_rm") begin
+            if (!$cast(sac_intr_rm,rm)) `uvm_fatal("SOC_IFC_REG_CBS", {"Failed to get handle of expected sub-type for parent uvm_reg_block. ", fld.get_full_name()})
+            fld_hwset_active = sac_intr_rm.error_internal_intr_r_hwset_active[fld.get_lsb_pos()];
+        end
+        else if (rm.get_parent().get_name() == "soc_ifc_reg_rm") begin
+            if (!$cast(sir_intr_rm,rm)) `uvm_fatal("SOC_IFC_REG_CBS", {"Failed to get handle of expected sub-type for parent uvm_reg_block. ", fld.get_full_name()})
+            fld_hwset_active = sir_intr_rm.error_internal_intr_r_hwset_active[fld.get_lsb_pos()];
+        end
+        else begin
+            `uvm_fatal("SOC_IFC_REG_CBS", "Callback is registered to an unrecognized register block!")
+        end
         // Get a base-name for the event by truncating the '_sts' suffix
         event_name = fld.get_name().substr(0,fld.get_name().len()-5);
         en_reg     = rm.get_reg_by_name("error_intr_en_r");
@@ -56,8 +81,11 @@ class soc_ifc_reg_cbs_intr_block_rf_ext_error_internal_intr_r_base extends uvm_r
         cnt_fld    = rm.get_reg_by_name({event_name, "_intr_count_r"}).get_field_by_name("cnt");
 
         if (map.get_name() == this.APB_map_name) begin
-            if (kind == UVM_PREDICT_WRITE)
-                `uvm_warning("SOC_IFC_REG_CBS", "Unexpected write to interrupt register through APB interface!")
+            if (kind == UVM_PREDICT_WRITE) begin
+                `uvm_warning("SOC_IFC_REG_CBS", {"Unexpected write to interrupt register ", fld.get_full_name(), " through APB interface is blocked!"})
+                value = previous;
+                return;
+            end
             else
                 `uvm_info("SOC_IFC_REG_CBS", "Unexpected read to interrupt register through APB interface!", UVM_LOW)
         end
@@ -66,36 +94,87 @@ class soc_ifc_reg_cbs_intr_block_rf_ext_error_internal_intr_r_base extends uvm_r
         // Predict an increment to event interrupt counter
         // regardless of interrupt enablement (the sts reg being
         // set is all that is tracked by the interrupt counter)
+        // FIXME if a new interrupt event occurs while the interrupt sts is already 1,
+        // this won't increment the counter, even though it should.
         if (value & ~previous) begin
-            `uvm_info("SOC_IFC_REG_CBS", $sformatf("Write to %s triggers increment on %s from %d to %d", fld.get_name(), cnt_fld.get_name(), cnt_fld.get_mirrored_value(), cnt_fld.get_mirrored_value() + uvm_reg_data_t'(1)), UVM_HIGH)
-            cnt_fld.predict(cnt_fld.get_mirrored_value() + uvm_reg_data_t'(1));
+            `uvm_info("SOC_IFC_REG_CBS", $sformatf("hwset to %s triggers increment on %s from %d to %d", fld.get_name(), cnt_fld.get_name(), cnt_fld.get_mirrored_value(), cnt_fld.get_mirrored_value() + uvm_reg_data_t'(1)), UVM_HIGH)
+            cnt_fld.predict(cnt_fld.get_mirrored_value() + uvm_reg_data_t'(1), .kind(UVM_PREDICT_WRITE), .path(UVM_PREDICT), .map(map));
+        end
+
+        // Anytime an access intr sts register predicts a value of 1, we can treat
+        // that as a hwset (even if it's just an AHB/APB read) because we _know_ a
+        // W1C won't result in value=1, which is the case we're protecting against
+        // by tracking this hwset flag.
+        // We must track the hwset flag for all value=1 (not just the transitions
+        // where previous=0) because occasionally an actual hwset will occur when
+        // the interrupt is already pending, and we still must protect against W1C
+        // in that case.
+        if (value) begin
+            if (sir_intr_rm != null) begin
+                sir_intr_rm.error_internal_intr_r_hwset_active[fld.get_lsb_pos()] = 1'b1;
+                fork
+                    begin
+                    uvm_wait_for_nba_region();
+                    sir_intr_rm.error_internal_intr_r_hwset_active[fld.get_lsb_pos()] = 1'b0;
+                    end
+                join_none
+            end
+            else if (sac_intr_rm != null) begin
+                sac_intr_rm.error_internal_intr_r_hwset_active[fld.get_lsb_pos()] = 1'b1;
+                fork
+                    begin
+                    uvm_wait_for_nba_region();
+                    sac_intr_rm.error_internal_intr_r_hwset_active[fld.get_lsb_pos()] = 1'b0;
+                    end
+                join_none
+            end
+            else
+                `uvm_fatal("SOC_IFC_REG_CBS", "Bad handle")
         end
 
-        // On rising edge of field value, check if the interrupt output pin will
+        // On rising edge of field value, schedule a delay job to check if the
+        // interrupt output pin will
         // transition to high.
         // Global interrupt pin "agg_sts" is non-sticky
-        if ((value & ~previous) &&
-            en_glb.get_mirrored_value() &&
-            en_fld.get_mirrored_value() &&
-            ~sts_glb.get_mirrored_value())
+        if ((value & ~previous))
+        begin
+            `uvm_info("SOC_IFC_REG_CBS", {"Predicted update to ", fld.get_name(), " triggers interrupt output pin check delay job"}, UVM_MEDIUM)
+            delay_job.req_fld = fld;
+            delay_job.sts_reg = sts_reg;
+            delay_job.en_reg  = en_reg;
+            delay_job.sts_glb = sts_glb;
+            delay_job.en_glb  = en_glb;
+            delay_job.grab_values();
+            delay_jobs.push_back(delay_job);
+        end
+        // On falling edge of field value, caused by W1C, check if another thread
+        // is already attempting to perform hwset to this interrupt field (hwset is
+        // higher priority than W1C).
+        else if ((~value & previous) && fld_hwset_active)
         begin
-            `uvm_info("SOC_IFC_REG_CBS", {"Predicted update to ", fld.get_name(), " triggers interrupt output pin assertion"}, UVM_MEDIUM)
-            sts_glb.predict(1'b1);
+            `uvm_info("SOC_IFC_REG_CBS", {"Predicted update to ", fld.get_name(), " attempts to clear the interrupt bit but is preempted by an active hwset"}, UVM_MEDIUM)
+            value = previous;
+            // NOTE: No delay job is scheduled because no changes are predicted to
+            //       other interrupt register fields based on this activity
         end
-        // On falling edge of field value, check if the interrupt output pin will
+        // On falling edge of field value, schedule a delay job to
+        // check if the interrupt output pin will
         // transition from high to low.
         // Global interrupt pin "agg_sts" is non-sticky
-        else if ((~value & previous) &&
-                 ~|(en_reg.get_mirrored_value() &
-                    (sts_reg.get_mirrored_value() & ~(uvm_reg_data_t'(1) << fld.get_lsb_pos()))) &&
-                 sts_glb.get_mirrored_value())
+        else if ((~value & previous))
         begin
-            `uvm_info("SOC_IFC_REG_CBS", {"Predicted update to ", fld.get_name(), " triggers interrupt output pin deassertion"}, UVM_MEDIUM)
-            sts_glb.predict(1'b0);
+            `uvm_info("SOC_IFC_REG_CBS", {"Predicted update to ", fld.get_name(), " triggers interrupt output pin check delay job"}, UVM_MEDIUM)
+            delay_job.req_fld = fld;
+            delay_job.sts_reg = sts_reg;
+            delay_job.en_reg  = en_reg;
+            delay_job.sts_glb = sts_glb;
+            delay_job.en_glb  = en_glb;
+            delay_job.grab_values();
+            delay_jobs.push_back(delay_job);
         end
         else begin
             `uvm_info("SOC_IFC_REG_CBS",
-                      $sformatf("Write to %s does not trigger interrupt output transition due to %s: [%x], %s: [%x], masked %s: [%x], and %s: [%x]",
+                      $sformatf("Access to %s does not trigger interrupt output transition due to %s: [%x], %s: [%x], masked %s: [%x], and %s: [%x]",
                                 fld.get_name(),
                                 en_glb.get_name(),
                                 en_glb.get_mirrored_value(),
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_intr_block_rf_ext_error_intr_en_r_base.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_intr_block_rf_ext_error_intr_en_r_base.svh
index ad0aa350b..bc171833e 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_intr_block_rf_ext_error_intr_en_r_base.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_intr_block_rf_ext_error_intr_en_r_base.svh
@@ -21,6 +21,14 @@ class soc_ifc_reg_cbs_intr_block_rf_ext_error_intr_en_r_base extends uvm_reg_cbs
     string AHB_map_name = "soc_ifc_AHB_map";
     string APB_map_name = "soc_ifc_APB_map";
 
+    uvm_queue #(soc_ifc_reg_delay_job) delay_jobs;
+
+    function new(string name = "uvm_reg_cbs");
+        super.new(name);
+        if (!uvm_config_db#(uvm_queue#(soc_ifc_reg_delay_job))::get(null, "soc_ifc_reg_model_top", "delay_jobs", delay_jobs))
+            `uvm_error("SOC_IFC_REG_CBS", "Failed to get handle for 'delay_jobs' queue from config database!")
+    endfunction
+
     // Function: post_predict
     //
     // Called by the <uvm_reg_field::predict()> method
@@ -36,6 +44,7 @@ class soc_ifc_reg_cbs_intr_block_rf_ext_error_intr_en_r_base extends uvm_reg_cbs
                                        input uvm_predict_e  kind,
                                        input uvm_path_e     path,
                                        input uvm_reg_map    map);
+        soc_ifc_reg_delay_job_intr_block_rf_ext delay_job;
         uvm_reg       en_reg;
         uvm_reg_block rm;
         string        event_name;
@@ -44,6 +53,8 @@ class soc_ifc_reg_cbs_intr_block_rf_ext_error_intr_en_r_base extends uvm_reg_cbs
         uvm_reg_field en_glb ;
         uvm_reg_field sts_glb;
 
+        delay_job = soc_ifc_reg_delay_job_intr_block_rf_ext::type_id::create("delay_job");
+        delay_job.map = map;
         en_reg = fld.get_parent();
         rm     = en_reg.get_parent(); /* intr_block_rf_ext */
         // Get a base-name for the event by truncating the '_en' suffix
@@ -54,8 +65,11 @@ class soc_ifc_reg_cbs_intr_block_rf_ext_error_intr_en_r_base extends uvm_reg_cbs
         sts_glb = rm.get_reg_by_name("error_global_intr_r").get_field_by_name("agg_sts");
 
         if (map.get_name() == this.APB_map_name) begin
-            if (kind == UVM_PREDICT_WRITE)
-                `uvm_warning("SOC_IFC_REG_CBS", "Unexpected write to interrupt register through APB interface!")
+            if (kind == UVM_PREDICT_WRITE) begin
+                `uvm_warning("SOC_IFC_REG_CBS", {"Unexpected write to interrupt register ", fld.get_full_name(), " through APB interface is blocked!"})
+                value = previous;
+                return;
+            end
             else
                 `uvm_info("SOC_IFC_REG_CBS", "Unexpected read to interrupt register through APB interface!", UVM_LOW)
         end
@@ -64,24 +78,30 @@ class soc_ifc_reg_cbs_intr_block_rf_ext_error_intr_en_r_base extends uvm_reg_cbs
         // On rising edge of field value, check if the interrupt output pin will
         // transition to high.
         // Global interrupt pin "agg_sts" is non-sticky
-        if ((value & ~previous) &&
-            en_glb.get_mirrored_value() &&
-            sts_fld.get_mirrored_value() &&
-            ~sts_glb.get_mirrored_value())
+        if ((value & ~previous))
         begin
             `uvm_info("SOC_IFC_REG_CBS", {"Predicted update to ", fld.get_name(), " triggers interrupt output pin assertion"}, UVM_MEDIUM)
-            sts_glb.predict(1'b1);
+            delay_job.req_fld = fld;
+            delay_job.sts_reg = sts_reg;
+            delay_job.en_reg  = en_reg;
+            delay_job.sts_glb = sts_glb;
+            delay_job.en_glb  = en_glb;
+            delay_job.grab_values();
+            delay_jobs.push_back(delay_job);
         end
         // On falling edge of field value, check if the interrupt output pin will
         // transition from high to low.
         // Global interrupt pin "agg_sts" is non-sticky
-        else if ((~value & previous) &&
-                 ~|((en_reg.get_mirrored_value() & ~(value << fld.get_lsb_pos())) &
-                    sts_reg.get_mirrored_value()) &&
-                 sts_glb.get_mirrored_value())
+        else if ((~value & previous))
         begin
             `uvm_info("SOC_IFC_REG_CBS", {"Predicted update to ", fld.get_name(), " triggers interrupt output pin deassertion"}, UVM_MEDIUM)
-            sts_glb.predict(1'b0);
+            delay_job.req_fld = fld;
+            delay_job.sts_reg = sts_reg;
+            delay_job.en_reg  = en_reg;
+            delay_job.sts_glb = sts_glb;
+            delay_job.en_glb  = en_glb;
+            delay_job.grab_values();
+            delay_jobs.push_back(delay_job);
         end
         else begin
             `uvm_info("SOC_IFC_REG_CBS",
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_intr_block_rf_ext_error_intr_trig_r_base.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_intr_block_rf_ext_error_intr_trig_r_base.svh
index 007ffa230..b1c2a509f 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_intr_block_rf_ext_error_intr_trig_r_base.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_intr_block_rf_ext_error_intr_trig_r_base.svh
@@ -48,8 +48,11 @@ class soc_ifc_reg_cbs_intr_block_rf_ext_error_intr_trig_r_base extends uvm_reg_c
         sts_fld  = sts_reg.get_field_by_name({event_name, "_sts"});
 
         if (map.get_name() == this.APB_map_name) begin
-            if (kind == UVM_PREDICT_WRITE)
-                `uvm_warning("SOC_IFC_REG_CBS", "Unexpected write to interrupt register through APB interface!")
+            if (kind == UVM_PREDICT_WRITE) begin
+                `uvm_warning("SOC_IFC_REG_CBS", {"Unexpected write to interrupt register ", fld.get_full_name(), " through APB interface is blocked!"})
+                value = previous;
+                return;
+            end
             else
                 `uvm_info("SOC_IFC_REG_CBS", "Unexpected read to interrupt register through APB interface!", UVM_LOW)
         end
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_intr_block_rf_ext_global_intr_en_r_base.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_intr_block_rf_ext_global_intr_en_r_base.svh
index 995f6fefa..0d2e20c33 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_intr_block_rf_ext_global_intr_en_r_base.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_intr_block_rf_ext_global_intr_en_r_base.svh
@@ -51,46 +51,49 @@ class soc_ifc_reg_cbs_intr_block_rf_ext_global_intr_en_r_base extends uvm_reg_cb
         sts_glb    = rm.get_reg_by_name({event_type, "_global_intr_r"}).get_field_by_name("agg_sts");
 
         if (map.get_name() == this.APB_map_name) begin
-            if (kind == UVM_PREDICT_WRITE)
-                `uvm_warning("SOC_IFC_REG_CBS", "Unexpected write to interrupt register through APB interface!")
+            if (kind == UVM_PREDICT_WRITE) begin
+                `uvm_warning("SOC_IFC_REG_CBS", {"Unexpected write to interrupt register ", fld.get_full_name(), " through APB interface is blocked!"})
+                value = previous;
+                return;
+            end
             else
                 `uvm_info("SOC_IFC_REG_CBS", "Unexpected read to interrupt register through APB interface!", UVM_LOW)
         end
         `uvm_info("SOC_IFC_REG_CBS", $sformatf("Access to %s with path %p", fld.get_full_name(), path), UVM_FULL)
 
-        // On rising edge of field value, check if the interrupt output pin will
-        // transition to high.
-        // Global interrupt pin "agg_sts" is non-sticky
-        if ((value & ~previous) &&
-            |( en_reg.get_mirrored_value() &
-              sts_reg.get_mirrored_value()) &&
-            ~sts_glb.get_mirrored_value())
-        begin
-            `uvm_info("SOC_IFC_REG_CBS", {"Predicted update to ", fld.get_name(), " triggers interrupt output pin assertion"}, UVM_MEDIUM)
-            sts_glb.predict(1'b1);
-        end
-        // On falling edge of field value, check if the interrupt output pin will
-        // transition from high to low.
-        // Global interrupt pin "agg_sts" is non-sticky
-        else if ((~value & previous) &&
-                 sts_glb.get_mirrored_value())
-        begin
-            `uvm_info("SOC_IFC_REG_CBS", {"Predicted update to ", fld.get_name(), " triggers interrupt output pin deassertion"}, UVM_MEDIUM)
-            sts_glb.predict(1'b0);
-        end
-        else begin
-            `uvm_info("SOC_IFC_REG_CBS",
-                      $sformatf("Write to %s with value %0d does not trigger interrupt output transition due to %s: [0x%x], %s: [0x%x], and %s: [%x]",
-                                fld.get_name(),
-                                value,
-                                en_reg.get_name(),
-                                en_reg.get_mirrored_value(),
-                                sts_reg.get_name(),
-                                sts_reg.get_mirrored_value(),
-                                sts_glb.get_name(),
-                                sts_glb.get_mirrored_value()),
-                      UVM_HIGH)
-        end
+//        // On rising edge of field value, check if the interrupt output pin will
+//        // transition to high.
+//        // Global interrupt pin "agg_sts" is non-sticky
+//        if ((value & ~previous) &&
+//            |( en_reg.get_mirrored_value() &
+//              sts_reg.get_mirrored_value()) &&
+//            ~sts_glb.get_mirrored_value())
+//        begin
+//            `uvm_info("SOC_IFC_REG_CBS", {"Predicted update to ", fld.get_name(), " triggers interrupt output pin assertion"}, UVM_MEDIUM)
+//            sts_glb.predict(1'b1);
+//        end
+//        // On falling edge of field value, check if the interrupt output pin will
+//        // transition from high to low.
+//        // Global interrupt pin "agg_sts" is non-sticky
+//        else if ((~value & previous) &&
+//                 sts_glb.get_mirrored_value())
+//        begin
+//            `uvm_info("SOC_IFC_REG_CBS", {"Predicted update to ", fld.get_name(), " triggers interrupt output pin deassertion"}, UVM_MEDIUM)
+//            sts_glb.predict(1'b0);
+//        end
+//        else begin
+//            `uvm_info("SOC_IFC_REG_CBS",
+//                      $sformatf("Write to %s with value %0d does not trigger interrupt output transition due to %s: [0x%x], %s: [0x%x], and %s: [%x]",
+//                                fld.get_name(),
+//                                value,
+//                                en_reg.get_name(),
+//                                en_reg.get_mirrored_value(),
+//                                sts_reg.get_name(),
+//                                sts_reg.get_mirrored_value(),
+//                                sts_glb.get_name(),
+//                                sts_glb.get_mirrored_value()),
+//                      UVM_HIGH)
+//        end
     endfunction
 
 endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_intr_block_rf_ext_internal.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_intr_block_rf_ext_internal.svh
new file mode 100644
index 000000000..0ad25c667
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_intr_block_rf_ext_internal.svh
@@ -0,0 +1,69 @@
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//----------------------------------------------------------------------
+
+// General callback that implements the swwel=soc_req behavior for "internal" registers
+class soc_ifc_reg_cbs_intr_block_rf_ext_internal extends uvm_reg_cbs;
+
+    `uvm_object_utils(soc_ifc_reg_cbs_intr_block_rf_ext_internal)
+
+    string AHB_map_name = "soc_ifc_AHB_map";
+    string APB_map_name = "soc_ifc_APB_map";
+    
+    uvm_queue #(soc_ifc_reg_delay_job) delay_jobs;
+
+    function new(string name = "uvm_reg_cbs");
+        super.new(name);
+        if (!uvm_config_db#(uvm_queue#(soc_ifc_reg_delay_job))::get(null, "soc_ifc_reg_model_top", "delay_jobs", delay_jobs))
+            `uvm_error("SOC_IFC_REG_CBS", "Failed to get handle for 'delay_jobs' queue from config database!")
+    endfunction
+
+    // Function: post_predict
+    //
+    // Called by the <uvm_reg_field::predict()> method
+    // after a successful UVM_PREDICT_READ or UVM_PREDICT_WRITE prediction.
+    //
+    // ~previous~ is the previous value in the mirror and
+    // ~value~ is the latest predicted value. Any change to ~value~ will
+    // modify the predicted mirror value.
+    //
+    virtual function void post_predict(input uvm_reg_field  fld,
+                                       input uvm_reg_data_t previous,
+                                       inout uvm_reg_data_t value,
+                                       input uvm_predict_e  kind,
+                                       input uvm_path_e     path,
+                                       input uvm_reg_map    map);
+        uvm_reg_block blk = fld.get_parent().get_parent(); /* intr_block_rf_ext */
+        if (blk.get_name() != "intr_block_rf_ext") `uvm_fatal ("SOC_IFC_REG_CBS", "Failed to get valid parent class handle")
+        if (map.get_name() == this.AHB_map_name) begin
+            `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] on map [%s] has no effect on internal register field %s", kind, map.get_name(), fld.get_full_name()), UVM_FULL)
+        end
+        else if (map.get_name() == this.APB_map_name) begin
+            case (kind) inside
+                UVM_PREDICT_WRITE: begin
+                    `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict blocked write attempt to internal reg field %s on map %s. value: 0x%x previous: 0x%x", fld.get_full_name(), map.get_name(), value, previous), UVM_LOW)
+                    value = previous;
+                end
+                default: begin
+                    `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] on map [%s] has no effect on internal register field %s. value: 0x%x previous: 0x%x", kind, map.get_name(), fld.get_full_name(), value, previous), UVM_FULL)
+                end
+            endcase
+        end
+        else begin
+            `uvm_error("SOC_IFC_REG_CBS", {"post_predict called through unsupported reg map! ", map.get_name()})
+        end
+    endfunction
+
+endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_intr_block_rf_ext_notif_internal_intr_r_base.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_intr_block_rf_ext_notif_internal_intr_r_base.svh
index 3cdf9f807..6f194c35c 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_intr_block_rf_ext_notif_internal_intr_r_base.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_intr_block_rf_ext_notif_internal_intr_r_base.svh
@@ -21,6 +21,14 @@ class soc_ifc_reg_cbs_intr_block_rf_ext_notif_internal_intr_r_base extends uvm_r
     string AHB_map_name = "soc_ifc_AHB_map";
     string APB_map_name = "soc_ifc_APB_map";
 
+    uvm_queue #(soc_ifc_reg_delay_job) delay_jobs;
+
+    function new(string name = "uvm_reg_cbs");
+        super.new(name);
+        if (!uvm_config_db#(uvm_queue#(soc_ifc_reg_delay_job))::get(null, "soc_ifc_reg_model_top", "delay_jobs", delay_jobs))
+            `uvm_error("SOC_IFC_REG_CBS", "Failed to get handle for 'delay_jobs' queue from config database!")
+    endfunction
+
     // Function: post_predict
     //
     // Called by the <uvm_reg_field::predict()> method
@@ -36,7 +44,11 @@ class soc_ifc_reg_cbs_intr_block_rf_ext_notif_internal_intr_r_base extends uvm_r
                                        input uvm_predict_e  kind,
                                        input uvm_path_e     path,
                                        input uvm_reg_map    map);
+        soc_ifc_reg_delay_job_intr_block_rf_ext delay_job;
         uvm_reg_block rm;
+        soc_ifc_reg__intr_block_t_ext    sir_intr_rm;
+        sha512_acc_csr__intr_block_t_ext sac_intr_rm;
+        bit           fld_hwset_active = 1'b0;
         uvm_reg       sts_reg;
         string event_name    ;
         uvm_reg       en_reg ;
@@ -45,8 +57,21 @@ class soc_ifc_reg_cbs_intr_block_rf_ext_notif_internal_intr_r_base extends uvm_r
         uvm_reg_field sts_glb;
         uvm_reg_field cnt_fld;
 
+        delay_job = soc_ifc_reg_delay_job_intr_block_rf_ext::type_id::create("delay_job");
+        delay_job.map = map;
         sts_reg = fld.get_parent();
         rm = sts_reg.get_parent(); /* intr_block_rf_ext */
+        if (rm.get_parent().get_name() == "sha512_acc_csr_rm") begin
+            if (!$cast(sac_intr_rm,rm)) `uvm_fatal("SOC_IFC_REG_CBS", {"Failed to get handle of expected sub-type for parent uvm_reg_block. ", fld.get_full_name()})
+            fld_hwset_active = sac_intr_rm.notif_internal_intr_r_hwset_active[fld.get_lsb_pos()];
+        end
+        else if (rm.get_parent().get_name() == "soc_ifc_reg_rm") begin
+            if (!$cast(sir_intr_rm,rm)) `uvm_fatal("SOC_IFC_REG_CBS", {"Failed to get handle of expected sub-type for parent uvm_reg_block. ", fld.get_full_name()})
+            fld_hwset_active = sir_intr_rm.notif_internal_intr_r_hwset_active[fld.get_lsb_pos()];
+        end
+        else begin
+            `uvm_fatal("SOC_IFC_REG_CBS", "Callback is registered to an unrecognized register block!")
+        end
         // Get a base-name for the event by truncating the '_sts' suffix
         event_name = fld.get_name().substr(0,fld.get_name().len()-5);
         en_reg     = rm.get_reg_by_name("notif_intr_en_r");
@@ -56,8 +81,11 @@ class soc_ifc_reg_cbs_intr_block_rf_ext_notif_internal_intr_r_base extends uvm_r
         cnt_fld    = rm.get_reg_by_name({event_name, "_intr_count_r"}).get_field_by_name("cnt");
 
         if (map.get_name() == this.APB_map_name) begin
-            if (kind == UVM_PREDICT_WRITE)
-                `uvm_warning("SOC_IFC_REG_CBS", "Unexpected write to interrupt register through APB interface!")
+            if (kind == UVM_PREDICT_WRITE) begin
+                `uvm_warning("SOC_IFC_REG_CBS", {"Unexpected write to interrupt register ", fld.get_full_name(), " through APB interface is blocked!"})
+                value = previous;
+                return;
+            end
             else
                 `uvm_info("SOC_IFC_REG_CBS", "Unexpected read to interrupt register through APB interface!", UVM_LOW)
         end
@@ -66,36 +94,87 @@ class soc_ifc_reg_cbs_intr_block_rf_ext_notif_internal_intr_r_base extends uvm_r
         // Predict an increment to event interrupt counter
         // regardless of interrupt enablement (the sts reg being
         // set is all that is tracked by the interrupt counter)
+        // FIXME if a new interrupt event occurs while the interrupt sts is already 1,
+        // this won't increment the counter, even though it should.
         if (value & ~previous) begin
-            `uvm_info("SOC_IFC_REG_CBS", $sformatf("Write to %s triggers increment on %s from %d to %d", fld.get_name(), cnt_fld.get_name(), cnt_fld.get_mirrored_value(), cnt_fld.get_mirrored_value() + uvm_reg_data_t'(1)), UVM_HIGH)
-            cnt_fld.predict(cnt_fld.get_mirrored_value() + uvm_reg_data_t'(1));
+            `uvm_info("SOC_IFC_REG_CBS", $sformatf("hwset to %s triggers increment on %s from %d to %d", fld.get_name(), cnt_fld.get_name(), cnt_fld.get_mirrored_value(), cnt_fld.get_mirrored_value() + uvm_reg_data_t'(1)), UVM_HIGH)
+            cnt_fld.predict(cnt_fld.get_mirrored_value() + uvm_reg_data_t'(1), .kind(UVM_PREDICT_WRITE), .path(UVM_PREDICT), .map(map));
+        end
+
+        // Anytime an access intr sts register predicts a value of 1, we can treat
+        // that as a hwset (even if it's just an AHB/APB read) because we _know_ a
+        // W1C won't result in value=1, which is the case we're protecting against
+        // by tracking this hwset flag.
+        // We must track the hwset flag for all value=1 (not just the transitions
+        // where previous=0) because occasionally an actual hwset will occur when
+        // the interrupt is already pending, and we still must protect against W1C
+        // in that case.
+        if (value) begin
+            if (sir_intr_rm != null) begin
+                sir_intr_rm.notif_internal_intr_r_hwset_active[fld.get_lsb_pos()] = 1'b1;
+                fork
+                    begin
+                    uvm_wait_for_nba_region();
+                    sir_intr_rm.notif_internal_intr_r_hwset_active[fld.get_lsb_pos()] = 1'b0;
+                    end
+                join_none
+            end
+            else if (sac_intr_rm != null) begin
+                sac_intr_rm.notif_internal_intr_r_hwset_active[fld.get_lsb_pos()] = 1'b1;
+                fork
+                    begin
+                    uvm_wait_for_nba_region();
+                    sac_intr_rm.notif_internal_intr_r_hwset_active[fld.get_lsb_pos()] = 1'b0;
+                    end
+                join_none
+            end
+            else
+                `uvm_fatal("SOC_IFC_REG_CBS", "Bad handle")
         end
 
-        // On rising edge of field value, check if the interrupt output pin will
+        // On rising edge of field value, schedule a delay job to check if the
+        // interrupt output pin will
         // transition to high.
         // Global interrupt pin "agg_sts" is non-sticky
-        if ((value & ~previous) &&
-            en_glb.get_mirrored_value() &&
-            en_fld.get_mirrored_value() &&
-            ~sts_glb.get_mirrored_value())
+        if ((value & ~previous))
+        begin
+            delay_job.req_fld = fld;
+            delay_job.sts_reg = sts_reg;
+            delay_job.en_reg  = en_reg;
+            delay_job.sts_glb = sts_glb;
+            delay_job.en_glb  = en_glb;
+            delay_job.grab_values();
+            delay_jobs.push_back(delay_job);
+            `uvm_info("SOC_IFC_REG_CBS", {"Predicted update to ", fld.get_name(), " triggers interrupt output pin check delay job"}, UVM_MEDIUM)
+        end
+        // On falling edge of field value, caused by W1C, check if another thread
+        // is already attempting to perform hwset to this interrupt field (hwset is
+        // higher priority than W1C).
+        else if ((~value & previous) && fld_hwset_active)
         begin
-            `uvm_info("SOC_IFC_REG_CBS", {"Predicted update to ", fld.get_name(), " triggers interrupt output pin assertion"}, UVM_MEDIUM)
-            sts_glb.predict(1'b1);
+            value = previous;
+            `uvm_info("SOC_IFC_REG_CBS", {"Predicted update to ", fld.get_name(), " attempts to clear the interrupt bit but is preempted by an active hwset"}, UVM_MEDIUM)
+            // NOTE: No delay job is scheduled because no changes are predicted to
+            //       other interrupt register fields based on this activity
         end
-        // On falling edge of field value, check if the interrupt output pin will
+        // On falling edge of field value, schedule a delay job to
+        // check if the interrupt output pin will
         // transition from high to low.
         // Global interrupt pin "agg_sts" is non-sticky
-        else if ((~value & previous) &&
-                 ~|(en_reg.get_mirrored_value() &
-                    (sts_reg.get_mirrored_value() & ~(uvm_reg_data_t'(1) << fld.get_lsb_pos()))) &&
-                 sts_glb.get_mirrored_value())
+        else if ((~value & previous))
         begin
-            `uvm_info("SOC_IFC_REG_CBS", {"Predicted update to ", fld.get_name(), " triggers interrupt output pin deassertion"}, UVM_MEDIUM)
-            sts_glb.predict(1'b0);
+            delay_job.req_fld = fld;
+            delay_job.sts_reg = sts_reg;
+            delay_job.en_reg  = en_reg;
+            delay_job.sts_glb = sts_glb;
+            delay_job.en_glb  = en_glb;
+            delay_job.grab_values();
+            delay_jobs.push_back(delay_job);
+            `uvm_info("SOC_IFC_REG_CBS", {"Predicted update to ", fld.get_name(), " triggers interrupt output pin check delay job"}, UVM_MEDIUM)
         end
         else begin
             `uvm_info("SOC_IFC_REG_CBS",
-                      $sformatf("Write to %s does not trigger interrupt output transition due to %s: [%x], %s: [%x], masked %s: [%x], and %s: [%x]",
+                      $sformatf("Access to %s does not trigger interrupt output transition due to %s: [%x], %s: [%x], masked %s: [%x], and %s: [%x]",
                                 fld.get_name(),
                                 en_glb.get_name(),
                                 en_glb.get_mirrored_value(),
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_intr_block_rf_ext_notif_intr_en_r_base.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_intr_block_rf_ext_notif_intr_en_r_base.svh
index 2da22247e..bd138f03b 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_intr_block_rf_ext_notif_intr_en_r_base.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_intr_block_rf_ext_notif_intr_en_r_base.svh
@@ -21,6 +21,14 @@ class soc_ifc_reg_cbs_intr_block_rf_ext_notif_intr_en_r_base extends uvm_reg_cbs
     string AHB_map_name = "soc_ifc_AHB_map";
     string APB_map_name = "soc_ifc_APB_map";
 
+    uvm_queue #(soc_ifc_reg_delay_job) delay_jobs;
+
+    function new(string name = "uvm_reg_cbs");
+        super.new(name);
+        if (!uvm_config_db#(uvm_queue#(soc_ifc_reg_delay_job))::get(null, "soc_ifc_reg_model_top", "delay_jobs", delay_jobs))
+            `uvm_error("SOC_IFC_REG_CBS", "Failed to get handle for 'delay_jobs' queue from config database!")
+    endfunction
+
     // Function: post_predict
     //
     // Called by the <uvm_reg_field::predict()> method
@@ -36,6 +44,7 @@ class soc_ifc_reg_cbs_intr_block_rf_ext_notif_intr_en_r_base extends uvm_reg_cbs
                                        input uvm_predict_e  kind,
                                        input uvm_path_e     path,
                                        input uvm_reg_map    map);
+        soc_ifc_reg_delay_job_intr_block_rf_ext delay_job;
         uvm_reg       en_reg;
         uvm_reg_block rm;
         string        event_name;
@@ -44,6 +53,8 @@ class soc_ifc_reg_cbs_intr_block_rf_ext_notif_intr_en_r_base extends uvm_reg_cbs
         uvm_reg_field en_glb ;
         uvm_reg_field sts_glb;
 
+        delay_job = soc_ifc_reg_delay_job_intr_block_rf_ext::type_id::create("delay_job");
+        delay_job.map = map;
         en_reg = fld.get_parent();
         rm     = en_reg.get_parent(); /* intr_block_rf_ext */
         // Get a base-name for the event by truncating the '_en' suffix
@@ -54,8 +65,11 @@ class soc_ifc_reg_cbs_intr_block_rf_ext_notif_intr_en_r_base extends uvm_reg_cbs
         sts_glb = rm.get_reg_by_name("notif_global_intr_r").get_field_by_name("agg_sts");
 
         if (map.get_name() == this.APB_map_name) begin
-            if (kind == UVM_PREDICT_WRITE)
-                `uvm_warning("SOC_IFC_REG_CBS", "Unexpected write to interrupt register through APB interface!")
+            if (kind == UVM_PREDICT_WRITE) begin
+                `uvm_warning("SOC_IFC_REG_CBS", {"Unexpected write to interrupt register ", fld.get_full_name(), " through APB interface is blocked!"})
+                value = previous;
+                return;
+            end
             else
                 `uvm_info("SOC_IFC_REG_CBS", "Unexpected read to interrupt register through APB interface!", UVM_LOW)
         end
@@ -64,24 +78,30 @@ class soc_ifc_reg_cbs_intr_block_rf_ext_notif_intr_en_r_base extends uvm_reg_cbs
         // On rising edge of field value, check if the interrupt output pin will
         // transition to high.
         // Global interrupt pin "agg_sts" is non-sticky
-        if ((value & ~previous) &&
-            en_glb.get_mirrored_value() &&
-            sts_fld.get_mirrored_value() &&
-            ~sts_glb.get_mirrored_value())
+        if ((value & ~previous))
         begin
             `uvm_info("SOC_IFC_REG_CBS", {"Predicted update to ", fld.get_name(), " triggers interrupt output pin assertion"}, UVM_MEDIUM)
-            sts_glb.predict(1'b1);
+            delay_job.req_fld = fld;
+            delay_job.sts_reg = sts_reg;
+            delay_job.en_reg  = en_reg;
+            delay_job.sts_glb = sts_glb;
+            delay_job.en_glb  = en_glb;
+            delay_job.grab_values();
+            delay_jobs.push_back(delay_job);
         end
         // On falling edge of field value, check if the interrupt output pin will
         // transition from high to low.
         // Global interrupt pin "agg_sts" is non-sticky
-        else if ((~value & previous) &&
-                 ~|((en_reg.get_mirrored_value() & ~(value << fld.get_lsb_pos())) &
-                    sts_reg.get_mirrored_value()) &&
-                 sts_glb.get_mirrored_value())
+        else if ((~value & previous))
         begin
             `uvm_info("SOC_IFC_REG_CBS", {"Predicted update to ", fld.get_name(), " triggers interrupt output pin deassertion"}, UVM_MEDIUM)
-            sts_glb.predict(1'b0);
+            delay_job.req_fld = fld;
+            delay_job.sts_reg = sts_reg;
+            delay_job.en_reg  = en_reg;
+            delay_job.sts_glb = sts_glb;
+            delay_job.en_glb  = en_glb;
+            delay_job.grab_values();
+            delay_jobs.push_back(delay_job);
         end
         else begin
             `uvm_info("SOC_IFC_REG_CBS",
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_intr_block_rf_ext_notif_intr_trig_r_base.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_intr_block_rf_ext_notif_intr_trig_r_base.svh
index 0c221185c..360bd46dc 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_intr_block_rf_ext_notif_intr_trig_r_base.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_intr_block_rf_ext_notif_intr_trig_r_base.svh
@@ -48,8 +48,11 @@ class soc_ifc_reg_cbs_intr_block_rf_ext_notif_intr_trig_r_base extends uvm_reg_c
         sts_fld  = sts_reg.get_field_by_name({event_name, "_sts"});
 
         if (map.get_name() == this.APB_map_name) begin
-            if (kind == UVM_PREDICT_WRITE)
-                `uvm_warning("SOC_IFC_REG_CBS", "Unexpected write to interrupt register through APB interface!")
+            if (kind == UVM_PREDICT_WRITE) begin
+                `uvm_warning("SOC_IFC_REG_CBS", {"Unexpected write to interrupt register ", fld.get_full_name(), " through APB interface is blocked!"})
+                value = previous;
+                return;
+            end
             else
                 `uvm_info("SOC_IFC_REG_CBS", "Unexpected read to interrupt register through APB interface!", UVM_LOW)
         end
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr.svh
index 5132ac70c..50c780d9f 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr.svh
@@ -21,6 +21,14 @@ virtual class soc_ifc_reg_cbs_mbox_csr extends uvm_reg_cbs;
     string AHB_map_name = "soc_ifc_AHB_map";
     string APB_map_name = "soc_ifc_APB_map";
 
+    uvm_queue #(soc_ifc_reg_delay_job) delay_jobs;
+
+    function new(string name = "uvm_reg_cbs");
+        super.new(name);
+        if (!uvm_config_db#(uvm_queue#(soc_ifc_reg_delay_job))::get(null, "soc_ifc_reg_model_top", "delay_jobs", delay_jobs))
+            `uvm_error("SOC_IFC_REG_CBS", "Failed to get handle for 'delay_jobs' queue from config database!")
+    endfunction
+
     // Shorthand methods to make the 'post_predict' logic more readable
     // in descendant classes
     virtual function uvm_reg_data_t mbox_dlen_mirrored(mbox_csr_ext rm);
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_cmd_command.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_cmd_command.svh
index f8253bdf2..2fc026380 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_cmd_command.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_cmd_command.svh
@@ -14,6 +14,37 @@
 // limitations under the License.
 //----------------------------------------------------------------------
 
+// Reg predictions that will be scheduled on AHB write to mbox_cmd
+class soc_ifc_reg_delay_job_mbox_csr_mbox_cmd_command extends soc_ifc_reg_delay_job;
+    `uvm_object_utils( soc_ifc_reg_delay_job_mbox_csr_mbox_cmd_command )
+    mbox_csr_ext rm; /* mbox_csr_rm */
+    mbox_fsm_state_e state_nxt;
+    uvm_reg_map map;
+    virtual task do_job();
+        `uvm_info("SOC_IFC_REG_DELAY_JOB", "Running delayed job for mbox_csr.mbox_cmd.command", UVM_HIGH)
+        // Check mbox_unlock before predicting FSM change, since a force unlock
+        // has priority over normal flow
+        // mbox_unlock only 'activates' on the falling edge of the pulse; if we detect
+        // that, bail out of this prediction job
+        if (rm.mbox_unlock.unlock.get_mirrored_value()) begin
+            uvm_wait_for_nba_region();
+            if (!rm.mbox_unlock.unlock.get_mirrored_value()) begin
+                return;
+            end
+        end
+        if (rm.mbox_lock.lock.get_mirrored_value() && rm.mbox_fn_state_sigs.soc_cmd_stage) begin
+            rm.mbox_status.mbox_fsm_ps.predict(state_nxt, .kind(UVM_PREDICT_READ), .path(UVM_PREDICT), .map(map));
+            rm.mbox_fn_state_sigs = '{soc_dlen_stage: 1'b1, default: 1'b0};
+            `uvm_info("SOC_IFC_REG_DELAY_JOB", $sformatf("post_predict called through map [%p] on mbox_cmd results in state transition. Functional state tracker: [%p] mbox_fsm_ps transition [%p]", map.get_name(), rm.mbox_fn_state_sigs, state_nxt), UVM_FULL)
+        end
+        else if (rm.mbox_lock.lock.get_mirrored_value() && rm.mbox_fn_state_sigs.uc_cmd_stage) begin
+            rm.mbox_status.mbox_fsm_ps.predict(state_nxt, .kind(UVM_PREDICT_READ), .path(UVM_PREDICT), .map(map));
+            rm.mbox_fn_state_sigs = '{uc_dlen_stage: 1'b1, default: 1'b0};
+            `uvm_info("SOC_IFC_REG_DELAY_JOB", $sformatf("post_predict called through map [%p] on mbox_cmd results in state transition. Functional state tracker: [%p] mbox_fsm_ps transition [%p]", map.get_name(), rm.mbox_fn_state_sigs, state_nxt), UVM_FULL)
+        end
+    endtask
+endclass
+
 class soc_ifc_reg_cbs_mbox_csr_mbox_cmd_command extends soc_ifc_reg_cbs_mbox_csr;
 
     `uvm_object_utils(soc_ifc_reg_cbs_mbox_csr_mbox_cmd_command)
@@ -34,18 +65,44 @@ class soc_ifc_reg_cbs_mbox_csr_mbox_cmd_command extends soc_ifc_reg_cbs_mbox_csr
                                        input uvm_path_e     path,
                                        input uvm_reg_map    map);
         mbox_csr_ext rm; /* mbox_csr_rm */
+        soc_ifc_reg_delay_job_mbox_csr_mbox_cmd_command delay_job;
+        soc_ifc_reg_delay_job_mbox_csr_mbox_prot_error  error_job;
         uvm_reg_block blk = fld.get_parent().get_parent(); /* mbox_csr_rm */
         if (!$cast(rm,blk)) `uvm_fatal ("SOC_IFC_REG_CBS", "Failed to get valid class handle")
         if (map.get_name() == this.AHB_map_name) begin
             case (kind) inside
                 UVM_PREDICT_WRITE: begin
-                    if (rm.mbox_fn_state_sigs.uc_send_stage) begin
-                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("Predicting mbox_fsm_ps transition to [%p] on write to mbox_cmd", MBOX_RDY_FOR_DLEN), UVM_HIGH)
-                        rm.mbox_status.mbox_fsm_ps.predict(MBOX_RDY_FOR_DLEN);
-                    end
-                    else begin
-                        `uvm_warning("SOC_IFC_REG_CBS", $sformatf("Command written during unexpected mailbox state [%p]!", rm.mbox_fn_state_sigs))
+                    if (rm.mbox_fn_state_sigs.uc_cmd_stage) begin
+                        delay_job = soc_ifc_reg_delay_job_mbox_csr_mbox_cmd_command::type_id::create("delay_job");
+                        delay_job.rm = rm;
+                        delay_job.map = map;
+                        delay_job.set_delay_cycles(0);
+                        delay_job.state_nxt = MBOX_RDY_FOR_DLEN;
+                        delay_jobs.push_back(delay_job);
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("Write to %s on map [%s] with value [%x] predicts a state change. Delay job is queued to update DUT model.", fld.get_name(), map.get_name(), value), UVM_HIGH)
                     end
+//                    else if (rm.mbox_fn_state_sigs.mbox_idle) begin
+//                        error_job = soc_ifc_reg_delay_job_mbox_csr_mbox_prot_error::type_id::create("error_job");
+//                        error_job.rm = rm;
+//                        error_job.map = map;
+//                        error_job.fld = fld;
+//                        error_job.set_delay_cycles(0);
+//                        error_job.state_nxt = MBOX_IDLE;
+//                        error_job.error = '{axs_without_lock: 1'b1, default: 1'b0};
+//                        delay_jobs.push_back(error_job);
+//                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("Write to %s on map [%s] with value [%x] causes a mbox no_lock protocol error. Delay job is queued to update DUT model.", fld.get_name(), map.get_name(), value), UVM_HIGH)
+//                    end
+//                    else begin
+//                        error_job = soc_ifc_reg_delay_job_mbox_csr_mbox_prot_error::type_id::create("error_job");
+//                        error_job.rm = rm;
+//                        error_job.map = map;
+//                        error_job.fld = fld;
+//                        error_job.set_delay_cycles(0);
+//                        error_job.state_nxt = MBOX_ERROR;
+//                        error_job.error = '{axs_incorrect_order: 1'b1, default: 1'b0};
+//                        delay_jobs.push_back(error_job);
+//                        `uvm_warning("SOC_IFC_REG_CBS", $sformatf("Command written during unexpected mailbox state [%p] results in mbox ooo protocol error!", rm.mbox_fn_state_sigs))
+//                    end
                 end
                 default: begin
                     `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] has no effect", kind), UVM_FULL)
@@ -55,12 +112,40 @@ class soc_ifc_reg_cbs_mbox_csr_mbox_cmd_command extends soc_ifc_reg_cbs_mbox_csr
         else if (map.get_name() == this.APB_map_name) begin
             case (kind) inside
                 UVM_PREDICT_WRITE: begin
-                    if (rm.mbox_fn_state_sigs.soc_send_stage) begin
-                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("Predicting mbox_fsm_ps transition to [%p] on write to mbox_cmd", MBOX_RDY_FOR_DLEN), UVM_HIGH)
-                        rm.mbox_status.mbox_fsm_ps.predict(MBOX_RDY_FOR_DLEN);
+                    if (rm.mbox_fn_state_sigs.soc_cmd_stage/* && (rm.mbox_status.mbox_fsm_ps.get_mirrored_value() == MBOX_RDY_FOR_CMD)*/) begin
+                        delay_job = soc_ifc_reg_delay_job_mbox_csr_mbox_cmd_command::type_id::create("delay_job");
+                        delay_job.rm = rm;
+                        delay_job.map = map;
+                        delay_job.set_delay_cycles(0);
+                        delay_job.state_nxt = MBOX_RDY_FOR_DLEN;
+                        delay_jobs.push_back(delay_job);
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("Write to %s on map [%s] with value [%x] predicts a state change. Delay job is queued to update DUT model.", fld.get_name(), map.get_name(), value), UVM_HIGH)
+                    end
+                    else if (rm.mbox_fn_state_sigs.mbox_idle) begin
+                        error_job = soc_ifc_reg_delay_job_mbox_csr_mbox_prot_error::type_id::create("error_job");
+                        error_job.rm = rm;
+                        error_job.map = map;
+                        error_job.fld = fld;
+                        error_job.set_delay_cycles(0);
+                        error_job.state_nxt = MBOX_IDLE;
+                        error_job.error = '{axs_without_lock: 1'b1, default: 1'b0};
+                        delay_jobs.push_back(error_job);
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("Write to %s on map [%s] with value [%x] causes a mbox no_lock protocol violation. Delay job is queued to update DUT model.", fld.get_name(), map.get_name(), value), UVM_HIGH)
+                    end
+                    else if (rm.mbox_fn_state_sigs.mbox_error) begin
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("Write to %s on map [%s] with value [%x] during mailbox state [%p] has no additional side effects!", fld.get_name(), map.get_name(), value, rm.mbox_fn_state_sigs), UVM_LOW)
                     end
                     else begin
-                        `uvm_warning("SOC_IFC_REG_CBS", $sformatf("Command written during unexpected mailbox state [%p]!", rm.mbox_fn_state_sigs))
+                        error_job = soc_ifc_reg_delay_job_mbox_csr_mbox_prot_error::type_id::create("error_job");
+                        error_job.rm = rm;
+                        error_job.map = map;
+                        error_job.fld = fld;
+                        error_job.set_delay_cycles(0);
+                        error_job.state_nxt = MBOX_ERROR;
+                        error_job.error = '{axs_incorrect_order: 1'b1, default: 1'b0};
+                        delay_jobs.push_back(error_job);
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("Write to %s on map [%s] with value [%x] during unexpected mailbox state [%p] results in mbox ooo protocol violation!", fld.get_name(), map.get_name(), value, rm.mbox_fn_state_sigs), UVM_LOW)
+                        rm.mbox_fn_state_sigs = '{mbox_error: 1'b1, default: 1'b0};
                     end
                 end
                 default: begin
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_datain_datain.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_datain_datain.svh
index ecab0ac35..19cc7df57 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_datain_datain.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_datain_datain.svh
@@ -35,6 +35,7 @@ class soc_ifc_reg_cbs_mbox_csr_mbox_datain_datain extends soc_ifc_reg_cbs_mbox_c
                                        input uvm_reg_map    map);
         // Maximum allowable size for data transferred via mailbox
         int unsigned dlen_cap_dw;
+        soc_ifc_reg_delay_job_mbox_csr_mbox_prot_error  error_job;
         mbox_csr_ext rm; /* mbox_csr_rm */
         uvm_mem mm; /* mbox_mem_rm "mem model" */
         uvm_reg_block blk = fld.get_parent().get_parent(); /* mbox_csr_rm */
@@ -50,11 +51,12 @@ class soc_ifc_reg_cbs_mbox_csr_mbox_datain_datain extends soc_ifc_reg_cbs_mbox_c
                 //  - uC has lock (checked in soc_ifc_predictor)
                 //  - mbox state is in MBOX_RDY_FOR_DATA or EXECUTE_UC
                 UVM_PREDICT_WRITE: begin
-                    if (rm.mbox_fn_state_sigs.uc_send_stage) begin
+                    if (rm.mbox_fn_state_sigs.uc_data_stage) begin
                         `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called through map [%s] results in data entry push to mbox_data_q", map.get_name()), UVM_FULL)
                         // A potential issue because uC should have set dlen prior to pushing data
                         if (rm.mbox_data_q.size() >= dlen_cap_dw) begin
-                            `uvm_warning("SOC_IFC_REG_CBS", "Push to datain observed when mbox_data_q already contains the same number of entries as indicated in mbox_dlen or the mailbox maximum capacity!")
+//                            `uvm_warning("SOC_IFC_REG_CBS", "Push to datain observed when mbox_data_q already contains the same number of entries as indicated in mbox_dlen or the mailbox maximum capacity!")
+                            `uvm_info("SOC_IFC_REG_CBS", $sformatf("Push to datain observed when mbox_data_q already contains the same number of entries [%d] as indicated in mbox_dlen [%d bytes] or the mailbox maximum capacity!", rm.mbox_data_q.size(), mbox_dlen_mirrored(rm)), UVM_LOW)
                         end
                         rm.mbox_data_q.push_back(value);
                         if (rm.mbox_data_q.size() == 1) begin
@@ -64,7 +66,9 @@ class soc_ifc_reg_cbs_mbox_csr_mbox_datain_datain extends soc_ifc_reg_cbs_mbox_c
                             // The warning is safe to ignore because the mbox_dataout
                             // callback does post-prediction from data queue accordingly
                             rm.mbox_data_q.push_front(rm.mbox_dataout.dataout.get_mirrored_value()); /* Sacrificial entry will be immediately removed in mbox_dataout callback */
+                            rm.mbox_datain_to_dataout_predict.trigger();
                             rm.mbox_dataout.dataout.predict(value, .kind(UVM_PREDICT_READ), .path(UVM_PREDICT), .map(map));
+                            rm.mbox_datain_to_dataout_predict.reset();
                         end
                     end
                     else if (rm.mbox_fn_state_sigs.uc_receive_stage) begin
@@ -74,17 +78,6 @@ class soc_ifc_reg_cbs_mbox_csr_mbox_datain_datain extends soc_ifc_reg_cbs_mbox_c
                             `uvm_info("SOC_IFC_REG_CBS", "Push to datain observed when mbox_resp_q already contains the same number of entries as indicated in mbox_dlen or the mailbox maximum capacity!", UVM_HIGH)
                         end
                         rm.mbox_resp_q.push_back(value);
-                        if (rm.mbox_resp_q.size() == 1) begin
-                            `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called through map [%s] results in data entry updating dataout mirror", map.get_name()), UVM_FULL)
-                            // Use UVM_PREDICT_READ to workaround the warning that gets thrown (on
-                            // accesses while busy) when running UVM_PREDICT_DIRECT.
-                            // The warning is safe to ignore because the mbox_dataout
-                            // callback does post-prediction from data queue accordingly
-                            rm.mbox_data_q.push_front(value); /* Entry is used for value prediction if mbox_data_q is not empty, which might be the case depending on the test */
-                            rm.mbox_data_q.push_front(rm.mbox_dataout.dataout.get_mirrored_value()); /* Sacrificial entry will be immediately removed in mbox_dataout callback */
-                            rm.mbox_dataout.dataout.predict(value, .kind(UVM_PREDICT_READ), .path(UVM_PREDICT), .map(map));
-                            rm.mbox_data_q.pop_front(); /* Remove the value we put on the queue for prediction -- receiver might continue reading from dataout even after pushing to datain ??? */
-                        end
                     end
                     else begin
                         `uvm_error("SOC_IFC_REG_CBS", $sformatf("Attempted push to mbox_datain in unexpected mbox FSM state: [%p]", rm.mbox_fn_state_sigs))
@@ -104,10 +97,10 @@ class soc_ifc_reg_cbs_mbox_csr_mbox_datain_datain extends soc_ifc_reg_cbs_mbox_c
                 //  - mbox state is in MBOX_RDY_FOR_DATA
                 //  - if mbox state is EXECUTE_SOC, pushes not allowed because there is never resp data SOC->uC
                 UVM_PREDICT_WRITE: begin
-                    if (rm.mbox_fn_state_sigs.soc_send_stage) begin
+                    if (rm.mbox_fn_state_sigs.soc_data_stage) begin
                         `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called through map [%s] results in data entry push to mbox_data_q", map.get_name()), UVM_FULL)
                         if (rm.mbox_data_q.size() >= dlen_cap_dw) begin
-                            `uvm_info("SOC_IFC_REG_CBS", "Push to datain observed when mbox_data_q already contains the same number of entries as indicated in mbox_dlen or the mailbox maximum capacity!", UVM_HIGH)
+                            `uvm_info("SOC_IFC_REG_CBS", $sformatf("Push to datain observed when mbox_data_q already contains the same number of entries [%d] as indicated in mbox_dlen [%d bytes] or the mailbox maximum capacity!", rm.mbox_data_q.size(), mbox_dlen_mirrored(rm)), UVM_LOW)
                         end
                         rm.mbox_data_q.push_back(value);
                         if (rm.mbox_data_q.size() == 1) begin
@@ -117,11 +110,39 @@ class soc_ifc_reg_cbs_mbox_csr_mbox_datain_datain extends soc_ifc_reg_cbs_mbox_c
                             // The warning is safe to ignore because the mbox_dataout
                             // callback does post-prediction from data queue accordingly
                             rm.mbox_data_q.push_front(rm.mbox_dataout.dataout.get_mirrored_value()); /* Sacrificial entry will be immediately removed in mbox_dataout callback */
+                            rm.mbox_datain_to_dataout_predict.trigger();
                             rm.mbox_dataout.dataout.predict(value, .kind(UVM_PREDICT_READ), .path(UVM_PREDICT), .map(map));
+                            rm.mbox_datain_to_dataout_predict.reset();
                         end
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("After processing write to mbox_datain, mbox_data_q.size(): [%d]", rm.mbox_data_q.size()), UVM_DEBUG)
+                    end
+                    else if (rm.mbox_fn_state_sigs.mbox_idle) begin
+                        error_job = soc_ifc_reg_delay_job_mbox_csr_mbox_prot_error::type_id::create("error_job");
+                        error_job.rm = rm;
+                        error_job.map = map;
+                        error_job.fld = fld;
+                        error_job.set_delay_cycles(0);
+                        error_job.state_nxt = MBOX_IDLE;
+                        error_job.error = '{axs_without_lock: 1'b1, default: 1'b0};
+                        delay_jobs.push_back(error_job);
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("Write to [%s] on map [%s] with value [%x] causes a mbox no_lock protocol violation. Delay job is queued to update DUT model.", fld.get_name(), map.get_name(), value), UVM_HIGH)
+                    end
+                    else if (rm.mbox_fn_state_sigs.mbox_error) begin
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("Write to %s on map [%s] with value [%x] during mailbox state [%p] has no additional side effects!", fld.get_name(), map.get_name(), value, rm.mbox_fn_state_sigs), UVM_LOW)
                     end
                     else begin
-                        `uvm_error("SOC_IFC_REG_CBS", $sformatf("Attempted push to mbox_datain in unexpected mbox FSM state: [%p]", rm.mbox_fn_state_sigs))
+                        mbox_fsm_state_e mbox_fsm_ps;
+                        error_job = soc_ifc_reg_delay_job_mbox_csr_mbox_prot_error::type_id::create("error_job");
+                        error_job.rm = rm;
+                        error_job.map = map;
+                        error_job.fld = fld;
+                        error_job.set_delay_cycles(0);
+                        error_job.state_nxt = MBOX_ERROR;
+                        error_job.error = '{axs_incorrect_order: 1'b1, default: 1'b0};
+                        delay_jobs.push_back(error_job);
+                        mbox_fsm_ps = mbox_fsm_state_e'(rm.mbox_status.mbox_fsm_ps.get_mirrored_value());
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("Write to %s on map [%s] with value [%x] during unexpected mailbox state [%p] [%p] results in mbox ooo protocol violation!", fld.get_name(), map.get_name(), value, rm.mbox_fn_state_sigs, mbox_fsm_ps), UVM_LOW)
+                        rm.mbox_fn_state_sigs = '{mbox_error: 1'b1, default: 1'b0};
                     end
                 end
                 default: begin
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_dataout_dataout.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_dataout_dataout.svh
index 670a7123f..41a9a7c7d 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_dataout_dataout.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_dataout_dataout.svh
@@ -33,28 +33,52 @@ class soc_ifc_reg_cbs_mbox_csr_mbox_dataout_dataout extends soc_ifc_reg_cbs_mbox
                                        input uvm_predict_e  kind,
                                        input uvm_path_e     path,
                                        input uvm_reg_map    map);
+        soc_ifc_reg_delay_job_mbox_csr_mbox_prot_error  error_job;
         mbox_csr_ext rm; /* mbox_csr_rm */
         uvm_reg_block blk = fld.get_parent().get_parent(); /* mbox_csr_rm */
         if (!$cast(rm,blk)) `uvm_fatal ("SOC_IFC_REG_CBS", "Failed to get valid class handle")
-        if ((map.get_name() == this.AHB_map_name) ||
-            (map.get_name() == this.APB_map_name)) begin
-            // Flag unexpected accesses based on system state, leaving an exception
-            // for UVM_PREDICT calls via writes to mbox_datain
-            // (This winds up being an exception for _any_ READ from dataout,
-            // because this method is only called from the apb_reg_predictor
-            // with UVM_PREDICT. So this is not going to catch bad reads.)
-            case (map.get_name()) inside
-                this.AHB_map_name: begin
-                    if (!rm.mbox_fn_state_sigs.uc_receive_stage &&
-                        (path != UVM_PREDICT || kind != UVM_PREDICT_READ))
-                        `uvm_error("SOC_IFC_REG_CBS", $sformatf("Access to dataout of kind [%p] is unexpected on map [%s]! Mailbox state tracker: %p", kind, map.get_name(), rm.mbox_fn_state_sigs))
+        // Flag unexpected accesses based on system state, leaving an exception
+        // for UVM_PREDICT calls triggered by writes to mbox_datain
+        case (map.get_name()) inside
+            this.AHB_map_name: begin
+                if (!rm.mbox_fn_state_sigs.uc_receive_stage &&
+                    rm.mbox_datain_to_dataout_predict.is_off())
+                    `uvm_error("SOC_IFC_REG_CBS", $sformatf("Access to dataout of kind [%p] is unexpected on map [%s]! Mailbox state tracker: %p", kind, map.get_name(), rm.mbox_fn_state_sigs))
+            end
+            this.APB_map_name: begin
+                if (rm.mbox_fn_state_sigs.mbox_idle && rm.mbox_datain_to_dataout_predict.is_off()) begin
+                    error_job = soc_ifc_reg_delay_job_mbox_csr_mbox_prot_error::type_id::create("error_job");
+                    error_job.rm = rm;
+                    error_job.map = map;
+                    error_job.fld = fld;
+                    error_job.set_delay_cycles(0);
+                    error_job.state_nxt = MBOX_IDLE;
+                    error_job.error = '{axs_without_lock: 1'b1, default: 1'b0};
+                    delay_jobs.push_back(error_job);
                 end
-                this.APB_map_name: begin
-                    if (!rm.mbox_fn_state_sigs.soc_receive_stage && !rm.mbox_fn_state_sigs.soc_done_stage &&
-                        (path != UVM_PREDICT || kind != UVM_PREDICT_READ))
-                        `uvm_error("SOC_IFC_REG_CBS", $sformatf("Access to dataout of kind [%p] is unexpected on map [%s]! Mailbox state tracker: %p", kind, map.get_name(), rm.mbox_fn_state_sigs))
+                else if (rm.mbox_fn_state_sigs.mbox_error) begin
+                    `uvm_info("SOC_IFC_REG_CBS", $sformatf("Write to %s on map [%s] with value [%x] during mailbox state [%p] has no additional side effects!", fld.get_name(), map.get_name(), value, rm.mbox_fn_state_sigs), UVM_LOW)
                 end
-            endcase
+                // FIXME should we treat all writes to mbox_dataout as protocol error?
+                else if ((kind == UVM_PREDICT_WRITE) ||
+                         ((!rm.mbox_fn_state_sigs.soc_receive_stage && !rm.mbox_fn_state_sigs.soc_done_stage) &&
+                          rm.mbox_datain_to_dataout_predict.is_off())) begin
+                    error_job = soc_ifc_reg_delay_job_mbox_csr_mbox_prot_error::type_id::create("error_job");
+                    error_job.rm = rm;
+                    error_job.map = map;
+                    error_job.fld = fld;
+                    error_job.set_delay_cycles(0);
+                    error_job.state_nxt = MBOX_ERROR;
+                    error_job.error = '{axs_incorrect_order: 1'b1, default: 1'b0};
+                    delay_jobs.push_back(error_job);
+                    `uvm_error("SOC_IFC_REG_CBS", $sformatf("Access to dataout of kind [%p] is unexpected on map [%s]! Flagging mailbox protocol violation. Mailbox state tracker: %p", kind, map.get_name(), rm.mbox_fn_state_sigs))
+                    rm.mbox_fn_state_sigs = '{mbox_error: 1'b1, default: 1'b0};
+                end
+            end
+        endcase
+        // Update the data queue and modify predicted value for mbox_dataout
+        if ((map.get_name() == this.AHB_map_name) ||
+            (map.get_name() == this.APB_map_name)) begin
             case (kind) inside
                 UVM_PREDICT_WRITE: begin
                     if (value != previous) begin
@@ -68,6 +92,7 @@ class soc_ifc_reg_cbs_mbox_csr_mbox_dataout_dataout extends soc_ifc_reg_cbs_mbox
                     // Next entry in the queue is the predicted value for the
                     // subsequent access
                     if (rm.mbox_data_q.size() > 0) begin
+                        `uvm_info("SOC_IFC_REG_CBS", "On read from mbox_dataout, popping front entry from mbox_data_q and predicting next value of mbox_dataout register", UVM_DEBUG)
                         if (previous != rm.mbox_data_q[0])
                             `uvm_error("SOC_IFC_REG_CBS", $sformatf("Current mirrored value [0x%x] in %s does not match the element at the front of the mailbox data queue [0x%x]!", previous, fld.get_full_name(), rm.mbox_data_q[0]))
                         rm.mbox_data_q.pop_front();
@@ -78,9 +103,11 @@ class soc_ifc_reg_cbs_mbox_csr_mbox_dataout_dataout extends soc_ifc_reg_cbs_mbox
                         end
                         else begin
                             `uvm_info("SOC_IFC_REG_CBS", $sformatf("Read from %s gets the last available value in the mailbox", fld.get_full_name()), UVM_HIGH)
+                            value = 0;
                         end
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("After processing read from mbox_dataout, mbox_data_q.size(): [%d]", rm.mbox_data_q.size()), UVM_DEBUG)
                     end
-                    else begin
+                    else if (rm.mbox_datain_to_dataout_predict.is_off()) begin
                         // TODO escalate to uvm_warning?
                         // Some tests do this deliberately, we don't want those to fail
                         `uvm_info("SOC_IFC_REG_CBS", "Attempted read from mbox_dataout when mailbox_data_q is empty!", UVM_MEDIUM)
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_dlen_length.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_dlen_length.svh
index 7f76bd0fb..019df9fa3 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_dlen_length.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_dlen_length.svh
@@ -14,6 +14,37 @@
 // limitations under the License.
 //----------------------------------------------------------------------
 
+// Reg predictions that will be scheduled on AHB write to mbox_dlen
+class soc_ifc_reg_delay_job_mbox_csr_mbox_dlen_length extends soc_ifc_reg_delay_job;
+    `uvm_object_utils( soc_ifc_reg_delay_job_mbox_csr_mbox_dlen_length )
+    mbox_csr_ext rm; /* mbox_csr_rm */
+    mbox_fsm_state_e state_nxt;
+    uvm_reg_map map;
+    virtual task do_job();
+        `uvm_info("SOC_IFC_REG_DELAY_JOB", "Running delayed job for mbox_csr.mbox_dlen.length", UVM_HIGH)
+        // Check mbox_unlock before predicting FSM change, since a force unlock
+        // has priority over normal flow
+        // mbox_unlock only 'activates' on the falling edge of the pulse; if we detect
+        // that, bail out of this prediction job
+        if (rm.mbox_unlock.unlock.get_mirrored_value()) begin
+            uvm_wait_for_nba_region();
+            if (!rm.mbox_unlock.unlock.get_mirrored_value()) begin
+                return;
+            end
+        end
+        if (rm.mbox_lock.lock.get_mirrored_value() && rm.mbox_fn_state_sigs.soc_dlen_stage) begin
+            rm.mbox_status.mbox_fsm_ps.predict(state_nxt, .kind(UVM_PREDICT_READ), .path(UVM_PREDICT), .map(map));
+            rm.mbox_fn_state_sigs = '{soc_data_stage: 1'b1, default: 1'b0};
+            `uvm_info("SOC_IFC_REG_DELAY_JOB", $sformatf("post_predict called through map [%p] on mbox_dlen results in state transition. Functional state tracker: [%p] mbox_fsm_ps transition [%p]", map.get_name(), rm.mbox_fn_state_sigs, state_nxt), UVM_FULL)
+        end
+        else if (rm.mbox_lock.lock.get_mirrored_value() && rm.mbox_fn_state_sigs.uc_dlen_stage) begin
+            rm.mbox_status.mbox_fsm_ps.predict(state_nxt, .kind(UVM_PREDICT_READ), .path(UVM_PREDICT), .map(map));
+            rm.mbox_fn_state_sigs = '{uc_data_stage: 1'b1, default: 1'b0};
+            `uvm_info("SOC_IFC_REG_DELAY_JOB", $sformatf("post_predict called through map [%p] on mbox_dlen results in state transition. Functional state tracker: [%p] mbox_fsm_ps transition [%p]", map.get_name(), rm.mbox_fn_state_sigs, state_nxt), UVM_FULL)
+        end
+    endtask
+endclass
+
 class soc_ifc_reg_cbs_mbox_csr_mbox_dlen_length extends soc_ifc_reg_cbs_mbox_csr;
 
     `uvm_object_utils(soc_ifc_reg_cbs_mbox_csr_mbox_dlen_length)
@@ -34,14 +65,22 @@ class soc_ifc_reg_cbs_mbox_csr_mbox_dlen_length extends soc_ifc_reg_cbs_mbox_csr
                                        input uvm_path_e     path,
                                        input uvm_reg_map    map);
         mbox_csr_ext rm; /* mbox_csr_rm */
+        soc_ifc_reg_delay_job_mbox_csr_mbox_dlen_length delay_job;
+        soc_ifc_reg_delay_job_mbox_csr_mbox_prot_error  error_job;
         uvm_reg_block blk = fld.get_parent().get_parent(); /* mbox_csr_rm */
         if (!$cast(rm,blk)) `uvm_fatal ("SOC_IFC_REG_CBS", "Failed to get valid class handle")
+        delay_job = soc_ifc_reg_delay_job_mbox_csr_mbox_dlen_length::type_id::create("delay_job");
+        delay_job.rm = rm;
+        delay_job.map = map;
+        delay_job.set_delay_cycles(0);
         if (map.get_name() == this.AHB_map_name) begin
             case (kind) inside
                 UVM_PREDICT_WRITE: begin
-                    if (rm.mbox_fn_state_sigs.uc_send_stage) begin
+                    if (rm.mbox_fn_state_sigs.uc_dlen_stage) begin
                         `uvm_info("SOC_IFC_REG_CBS", $sformatf("Predicting mbox_fsm_ps transition to [%p] on write to mbox_dlen", MBOX_RDY_FOR_DATA), UVM_HIGH)
-                        rm.mbox_status.mbox_fsm_ps.predict(MBOX_RDY_FOR_DATA);
+                        delay_job.state_nxt = MBOX_RDY_FOR_DATA;
+                        delay_jobs.push_back(delay_job);
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("Write to mbox_dlen on map [%s] with value [%x] predicts a state change. Delay job is queued to update DUT model.", map.get_name(), value), UVM_HIGH)
                     end
                     // uC updates mbox_dlen to reflect size of response data
                     else if (rm.mbox_fn_state_sigs.uc_receive_stage) begin
@@ -59,12 +98,37 @@ class soc_ifc_reg_cbs_mbox_csr_mbox_dlen_length extends soc_ifc_reg_cbs_mbox_csr
         else if (map.get_name() == this.APB_map_name) begin
             case (kind) inside
                 UVM_PREDICT_WRITE: begin
-                    if (rm.mbox_fn_state_sigs.soc_send_stage) begin
+                    if (rm.mbox_fn_state_sigs.soc_dlen_stage) begin
                         `uvm_info("SOC_IFC_REG_CBS", $sformatf("Predicting mbox_fsm_ps transition to [%p] on write to mbox_dlen", MBOX_RDY_FOR_DATA), UVM_HIGH)
-                        rm.mbox_status.mbox_fsm_ps.predict(MBOX_RDY_FOR_DATA);
+                        delay_job.state_nxt = MBOX_RDY_FOR_DATA;
+                        delay_jobs.push_back(delay_job);
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("Write to mbox_dlen on map [%s] with value [%x] predicts a state change. Delay job is queued to update DUT model.", map.get_name(), value), UVM_HIGH)
+                    end
+                    else if (rm.mbox_fn_state_sigs.mbox_idle) begin
+                        error_job = soc_ifc_reg_delay_job_mbox_csr_mbox_prot_error::type_id::create("error_job");
+                        error_job.rm = rm;
+                        error_job.map = map;
+                        error_job.fld = fld;
+                        error_job.set_delay_cycles(0);
+                        error_job.state_nxt = MBOX_IDLE;
+                        error_job.error = '{axs_without_lock: 1'b1, default: 1'b0};
+                        delay_jobs.push_back(error_job);
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("DLEN written during unexpected mailbox state [%p]!", rm.mbox_fn_state_sigs), UVM_LOW)
+                    end
+                    else if (rm.mbox_fn_state_sigs.mbox_error) begin
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("Write to %s on map [%s] with value [%x] during mailbox state [%p] has no additional side effects!", fld.get_name(), map.get_name(), value, rm.mbox_fn_state_sigs), UVM_LOW)
                     end
                     else begin
-                        `uvm_warning("SOC_IFC_REG_CBS", $sformatf("DLEN written during unexpected mailbox state [%p]!", rm.mbox_fn_state_sigs))
+                        error_job = soc_ifc_reg_delay_job_mbox_csr_mbox_prot_error::type_id::create("error_job");
+                        error_job.rm = rm;
+                        error_job.map = map;
+                        error_job.fld = fld;
+                        error_job.set_delay_cycles(0);
+                        error_job.state_nxt = MBOX_ERROR;
+                        error_job.error = '{axs_incorrect_order: 1'b1, default: 1'b0};
+                        delay_jobs.push_back(error_job);
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("DLEN written during unexpected mailbox state [%p]!", rm.mbox_fn_state_sigs), UVM_LOW)
+                        rm.mbox_fn_state_sigs = '{mbox_error: 1'b1, default: 1'b0};
                     end
                 end
                 default: begin
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_execute_execute.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_execute_execute.svh
index d85962c04..aa25c9ad8 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_execute_execute.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_execute_execute.svh
@@ -14,6 +14,96 @@
 // limitations under the License.
 //----------------------------------------------------------------------
 
+// Reg predictions that will be scheduled on AHB write to mbox_execute
+class soc_ifc_reg_delay_job_mbox_csr_mbox_execute_execute extends soc_ifc_reg_delay_job;
+    `uvm_object_utils( soc_ifc_reg_delay_job_mbox_csr_mbox_execute_execute )
+    mbox_csr_ext rm; /* mbox_csr_rm */
+    mbox_fsm_state_e state_nxt;
+    uvm_reg_map map;
+    virtual task do_job();
+        bit skip = 0;
+        `uvm_info("SOC_IFC_REG_DELAY_JOB", "Running delayed job for mbox_csr.mbox_execute.execute", UVM_HIGH)
+        // Check mbox_unlock before predicting FSM change, since a force unlock
+        // has priority over normal flow
+        // mbox_unlock only 'activates' on the falling edge of the pulse; if we detect
+        // that, bail out of this prediction job
+        if (rm.mbox_unlock.unlock.get_mirrored_value()) begin
+            uvm_wait_for_nba_region();
+            if (!rm.mbox_unlock.unlock.get_mirrored_value()) begin
+                skip = 1;
+            end
+        end
+        if (rm.mbox_fn_state_sigs.mbox_error) begin
+            skip = 1;
+        end
+        if (rm.mbox_lock.lock.get_mirrored_value() && !skip) begin
+            rm.mbox_status.mbox_fsm_ps.predict(state_nxt, .kind(UVM_PREDICT_READ), .path(UVM_PREDICT), .map(map));
+            case (state_nxt) inside
+                MBOX_IDLE: begin
+                    rm.mbox_fn_state_sigs = '{mbox_idle: 1'b1, default: 1'b0};
+                    rm.mbox_status.status.predict(CMD_BUSY, .kind(UVM_PREDICT_READ), .path(UVM_PREDICT), .map(map));
+                    rm.mbox_status.soc_has_lock.predict(1'b0, .kind(UVM_PREDICT_READ), .path(UVM_PREDICT), .map(map));
+                    `uvm_info("SOC_IFC_REG_DELAY_JOB", $sformatf("post_predict called through map [%p] on mbox_execute results in state transition. Functional state tracker: [%p] mbox_fsm_ps transition [%p]", map.get_name(), rm.mbox_fn_state_sigs, state_nxt), UVM_FULL)
+                    if (rm.mbox_lock.is_busy()) begin
+                        `uvm_info("SOC_IFC_REG_DELAY_JOB", "Delay job for mbox_execute attempted to clear mbox_lock, but hit access collision! Flagging clear event in reg-model for mbox_lock callback to handle", UVM_LOW)
+                        rm.mbox_lock_clr_miss.trigger(null);
+                        uvm_wait_for_nba_region();
+                        // If the bus transfer is still in progress (it didn't terminate on the same
+                        // falling clock edge as when this delay job was run), then just override the 
+                        // mirrored value immediately. Clear is_busy to avoid a UVM_WARNING.
+                        // This use-case is definitely a hack, but it is necessary to synchronize
+                        // the mbox_lock mirror with the design, chronologically.
+                        if (rm.mbox_lock.is_busy()) begin
+                            rm.mbox_lock.Xset_busyX(0);
+                            rm.mbox_lock.lock.predict(0);
+                            rm.mbox_lock.Xset_busyX(1);
+                        end
+                        else begin
+                            fork
+                                begin
+                                    rm.mbox_lock_clr_miss.wait_off();
+                                    disable MBOX_CLR_TIMEOUT;
+                                end
+                                begin: MBOX_CLR_TIMEOUT
+                                    // If it takes any amount of time for the pending lock to be cleared, that
+                                    // means we've encountered some environment bug (since the accessing i/f
+                                    // completed it's transfer, the reg prediction should be instantaneous)
+                                    uvm_wait_for_nba_region();
+                                    `uvm_error("SOC_IFC_REG_DELAY_JOB", $sformatf("mbox_lock clear activity, originally requested by mbox_execute callback but unserviceable, was scheduled to be completed during mbox_lock callback but took longer than expected to finish!"))
+                                end
+                            join_any
+                        end
+                    end
+                    else begin
+                        rm.mbox_lock.lock.predict(0);
+                    end
+                end
+                MBOX_EXECUTE_SOC: begin
+                    rm.mbox_fn_state_sigs = '{soc_receive_stage: 1'b1, default: 1'b0};
+                    `uvm_info("SOC_IFC_REG_DELAY_JOB", $sformatf("post_predict called through map [%p] on mbox_execute results in state transition. Functional state tracker: [%p] mbox_fsm_ps transition [%p]", map.get_name(), rm.mbox_fn_state_sigs, state_nxt), UVM_FULL)
+                end
+                MBOX_EXECUTE_UC: begin
+                    rm.mbox_fn_state_sigs = '{uc_receive_stage: 1'b1, default: 1'b0};
+                    `uvm_info("SOC_IFC_REG_DELAY_JOB", $sformatf("post_predict called through map [%p] on mbox_execute results in state transition. Functional state tracker: [%p] mbox_fsm_ps transition [%p]", map.get_name(), rm.mbox_fn_state_sigs, state_nxt), UVM_FULL)
+                end
+                default: begin
+                    `uvm_warning("SOC_IFC_REG_DELAY_JOB", $sformatf("post_predict called through map [%p] on mbox_execute results in unexpected state transition. Functional state tracker: [%p] mbox_fsm_ps transition [%p]", map.get_name(), rm.mbox_fn_state_sigs, state_nxt))
+                end
+            endcase
+            `uvm_info("SOC_IFC_REG_DELAY_JOB", $sformatf("post_predict called through map [%p] on mbox_execute finished processing", map.get_name()), UVM_FULL)
+        end
+        else begin
+            `uvm_info("SOC_IFC_REG_DELAY_JOB",
+                      $sformatf("Delay job for mbox_execute does not predict any changes due to: mbox_lock mirror [%d] skip [%d] mbox_fsm_ps [%p] mbox_fn_state_sigs [%p]",
+                                rm.mbox_lock.lock.get_mirrored_value(),
+                                skip, /*rm.mbox_unlock.unlock.get_mirrored_value(),*/
+                                rm.mbox_status.mbox_fsm_ps.get_mirrored_value(),
+                                rm.mbox_fn_state_sigs),
+                      UVM_LOW)
+        end
+    endtask
+endclass
+
 class soc_ifc_reg_cbs_mbox_csr_mbox_execute_execute extends soc_ifc_reg_cbs_mbox_csr;
 
     `uvm_object_utils(soc_ifc_reg_cbs_mbox_csr_mbox_execute_execute)
@@ -33,15 +123,19 @@ class soc_ifc_reg_cbs_mbox_csr_mbox_execute_execute extends soc_ifc_reg_cbs_mbox
                                        input uvm_predict_e  kind,
                                        input uvm_path_e     path,
                                        input uvm_reg_map    map);
+        soc_ifc_reg_delay_job_mbox_csr_mbox_execute_execute delay_job;
+        soc_ifc_reg_delay_job_mbox_csr_mbox_prot_error      error_job;
         mbox_csr_ext rm; /* mbox_csr_rm */
         uvm_mem mm; /* mbox_mem_rm "mem model" */
-        uvm_reg_block blk = fld.get_parent().get_parent(); /* mbox_csr_rm */
         uvm_reg_block rm_top;
-        uvm_reg_field intr_fld;
+        uvm_reg_block blk = fld.get_parent().get_parent(); /* mbox_csr_rm */
         if (!$cast(rm,blk)) `uvm_fatal ("SOC_IFC_REG_CBS", "Failed to get valid class handle")
         rm_top = rm.get_parent();
         mm = rm_top.get_mem_by_name("mbox_mem_rm");
-        intr_fld = rm_top.get_block_by_name("soc_ifc_reg_rm").get_block_by_name("intr_block_rf_ext").get_field_by_name("notif_cmd_avail_sts");
+        delay_job = soc_ifc_reg_delay_job_mbox_csr_mbox_execute_execute::type_id::create("delay_job");
+        delay_job.rm = rm;
+        delay_job.map = map;
+        delay_job.set_delay_cycles(0);
         if (map.get_name() == this.AHB_map_name) begin
             case (kind) inside
                 UVM_PREDICT_WRITE: begin
@@ -53,30 +147,28 @@ class soc_ifc_reg_cbs_mbox_csr_mbox_execute_execute extends soc_ifc_reg_cbs_mbox
                         if (!rm.mbox_fn_state_sigs.uc_done_stage) begin
                             `uvm_error("SOC_IFC_REG_CBS", $sformatf("uC is clearing mbox_execute in unexpected mbox FSM state: [%p]", rm.mbox_fn_state_sigs))
                         end
+                        `uvm_info("SOC_IFC_REG_CBS", "Write to mbox_execute clears the field and ends a command", UVM_HIGH)
                         rm.mbox_data_q.delete();
                         rm.mbox_resp_q.delete();
-                        rm.mbox_status.mbox_fsm_ps.predict(MBOX_IDLE);
-                        rm.mbox_fn_state_sigs = '{mbox_idle: 1'b1, default: 1'b0};
-                        rm.mbox_lock.lock.predict(0);
-                        `uvm_info("SOC_IFC_REG_CBS", "Write to mbox_execute clears the field and ends a command", UVM_HIGH)
+                        delay_job.state_nxt = MBOX_IDLE;
+                        delay_jobs.push_back(delay_job);
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("Write to mbox_execute on map [%s] with value [%x] predicts a state change. Delay job is queued to update DUT model.", map.get_name(), value), UVM_HIGH)
                     end
                     // Setting 'execute' - Expect state transition to MBOX_EXECUTE_SOC
                     else if (value & !previous) begin
                         // Maximum allowable size for data transferred via mailbox
                         int unsigned dlen_cap_dw = (mbox_dlen_mirrored(rm) < (mm.get_size() * mm.get_n_bytes())) ? mbox_dlen_mirrored_dword_ceil(rm) :
                                                                                                                    (mm.get_size() * mm.get_n_bytes()) >> ($clog2(MBOX_DATA_W/8));
-                        if (!rm.mbox_fn_state_sigs.uc_send_stage)
+                        if (!rm.mbox_fn_state_sigs.uc_data_stage)
                             `uvm_error("SOC_IFC_REG_CBS", $sformatf("mbox_execute is set by uC when in an unexpected state [%p]!", rm.mbox_fn_state_sigs))
-                        rm.mbox_status.mbox_fsm_ps.predict(MBOX_EXECUTE_SOC);
-                        rm.mbox_fn_state_sigs = '{soc_receive_stage: 1'b1, default: 1'b0};
                         // Round dlen up to nearest dword boundary and compare with data queue size
                         // On transfer of control, remove extraneous entries from data_q since
                         // reads of these values will be gated for the receiver in DUT
                         if ((rm.mbox_data_q.size()) != mbox_dlen_mirrored_dword_ceil(rm)) begin
-                            `uvm_info("SOC_IFC_REG_CBS", $sformatf("Write to mbox_execute initiates mailbox command, but the data queue entry count [%0d dwords] does not match the value of dlen [%0d bytes]!", rm.mbox_data_q.size(), mbox_dlen_mirrored(rm)), UVM_MEDIUM)
+                            `uvm_info("SOC_IFC_REG_CBS", $sformatf("Write to mbox_execute initiates mailbox command, but the data queue entry count [%0d dwords] does not match the value of dlen [%0d bytes]!", rm.mbox_data_q.size(), mbox_dlen_mirrored(rm)), UVM_LOW)
                         end
                         if (rm.mbox_data_q.size > dlen_cap_dw) begin
-                            `uvm_info("SOC_IFC_REG_CBS", $sformatf("Extra entries detected in mbox_data_q on control transfer - deleting %d entries", rm.mbox_data_q.size() - dlen_cap_dw), UVM_FULL)
+                            `uvm_info("SOC_IFC_REG_CBS", $sformatf("Extra entries detected in mbox_data_q on control transfer - deleting %d entries", rm.mbox_data_q.size() - dlen_cap_dw), UVM_LOW)
                             while (rm.mbox_data_q.size > dlen_cap_dw) begin
                                 // Continuously remove last entry until size is equal to dlen, since entries are added with push_back
                                 rm.mbox_data_q.delete(rm.mbox_data_q.size()-1);
@@ -84,12 +176,15 @@ class soc_ifc_reg_cbs_mbox_csr_mbox_execute_execute extends soc_ifc_reg_cbs_mbox
                         end
                         else if (rm.mbox_data_q.size < dlen_cap_dw) begin
                             uvm_reg_data_t zeros [$];
-                            `uvm_info("SOC_IFC_REG_CBS", $sformatf("Insufficient entries detected in mbox_data_q on control transfer - 0-filling %d entries", dlen_cap_dw - rm.mbox_data_q.size()), UVM_FULL)
+                            `uvm_info("SOC_IFC_REG_CBS", $sformatf("Insufficient entries detected in mbox_data_q on control transfer - 0-filling %d entries", dlen_cap_dw - rm.mbox_data_q.size()), UVM_LOW)
                             zeros = '{MBOX_DEPTH{32'h0}};
                             zeros = zeros[0:dlen_cap_dw - rm.mbox_data_q.size() - 1];
                             rm.mbox_data_q = {rm.mbox_data_q, zeros};
                         end
                         `uvm_info("SOC_IFC_REG_CBS", "Write to mbox_execute sets the field and initiates a command", UVM_HIGH)
+                        delay_job.state_nxt = MBOX_EXECUTE_SOC;
+                        delay_jobs.push_back(delay_job);
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("Write to mbox_execute on map [%s] with value [%x] predicts a state change. Delay job is queued to update DUT model.", map.get_name(), value), UVM_HIGH)
                     end
                     else begin
                         `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] has no effect", kind), UVM_FULL)
@@ -103,46 +198,62 @@ class soc_ifc_reg_cbs_mbox_csr_mbox_execute_execute extends soc_ifc_reg_cbs_mbox
         else if (map.get_name() == this.APB_map_name) begin
             case (kind) inside
                 UVM_PREDICT_WRITE: begin
+                    // Check for protocol violations
+                    error_job = soc_ifc_reg_delay_job_mbox_csr_mbox_prot_error::type_id::create("error_job");
+                    if (rm.mbox_fn_state_sigs.mbox_idle) begin
+                        error_job.rm = rm;
+                        error_job.map = map;
+                        error_job.fld = fld;
+                        error_job.set_delay_cycles(0);
+                        error_job.state_nxt = MBOX_IDLE;
+                        error_job.error = '{axs_without_lock: 1'b1, default: 1'b0};
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("EXECUTE written during unexpected mailbox state [%p]!", rm.mbox_fn_state_sigs), UVM_LOW)
+                    end
+                    else if (rm.mbox_fn_state_sigs.mbox_error) begin
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("Write to %s on map [%s] with value [%x] during mailbox state [%p] has no additional side effects!", fld.get_name(), map.get_name(), value, rm.mbox_fn_state_sigs), UVM_LOW)
+                    end
+                    else if (!rm.mbox_fn_state_sigs.soc_done_stage &&
+                             !(rm.mbox_fn_state_sigs.soc_data_stage /*&& mbox_fsm_state_e'(rm.mbox_status.mbox_fsm_ps.get_mirrored_value()) == MBOX_RDY_FOR_DATA*/)) begin
+                        error_job.rm = rm;
+                        error_job.map = map;
+                        error_job.fld = fld;
+                        error_job.set_delay_cycles(0);
+                        error_job.state_nxt = MBOX_ERROR;
+                        error_job.error = '{axs_incorrect_order: 1'b1, default: 1'b0};
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("EXECUTE written during unexpected mailbox state [%p]! FSM mirror: [%p]", rm.mbox_fn_state_sigs, rm.mbox_status.mbox_fsm_ps.get_mirrored_value()), UVM_LOW)
+                        rm.mbox_fn_state_sigs = '{mbox_error: 1'b1, default: 1'b0};
+                    end
+
                     // Clearing 'execute' - Expect sts pin change
                     if (~value & previous) begin
                         if (rm.mbox_data_q.size() != 0 || rm.mbox_resp_q.size() != 0) begin
-                            `uvm_warning("SOC_IFC_REG_CBS", $sformatf("Clearing mbox_execute when data queues are not empty! Did the receiver fetch the amount of data it expected to? mbox_data_q.size() [%0d] mbox_resp_q.size() [%0d]", rm.mbox_data_q.size(), rm.mbox_resp_q.size()))
+                            `uvm_info("SOC_IFC_REG_CBS", $sformatf("Clearing mbox_execute when data queues are not empty! Did the receiver fetch the amount of data it expected to? mbox_data_q.size() [%0d] mbox_resp_q.size() [%0d]", rm.mbox_data_q.size(), rm.mbox_resp_q.size()), UVM_LOW)
                         end
                         if (!rm.mbox_fn_state_sigs.soc_done_stage) begin
-                            `uvm_error("SOC_IFC_REG_CBS", $sformatf("SOC is clearing mbox_execute in unexpected mbox FSM state: [%p]", rm.mbox_fn_state_sigs))
+                            `uvm_info("SOC_IFC_REG_CBS", $sformatf("mbox_execute is cleared by SOC in unexpected mbox FSM state: [%p]", rm.mbox_fn_state_sigs), UVM_LOW)
                         end
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("Write to mbox_execute clears the field and ends a command"), UVM_HIGH)
                         rm.mbox_data_q.delete();
                         rm.mbox_resp_q.delete();
-                        rm.mbox_status.mbox_fsm_ps.predict(MBOX_IDLE);
-                        rm.mbox_status.soc_has_lock.predict(1'b0);
-                        rm.mbox_fn_state_sigs = '{mbox_idle: 1'b1, default: 1'b0};
-                        rm.mbox_lock.lock.predict(0);
-                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("Write to mbox_execute clears the field and ends a command"), UVM_HIGH)
+                        delay_job.state_nxt = MBOX_IDLE;
+                        delay_jobs.push_back(delay_job);
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("Write to mbox_execute on map [%s] with value [%x] predicts a state change. Delay job is queued to update DUT model.", map.get_name(), value), UVM_HIGH)
                     end
                     // Setting 'execute' - Expect a uC interrupt if enabled
                     else if (value & !previous) begin
                         // Maximum allowable size for data transferred via mailbox
                         int unsigned dlen_cap_dw = (mbox_dlen_mirrored(rm) < (mm.get_size() * mm.get_n_bytes())) ? mbox_dlen_mirrored_dword_ceil(rm) :
                                                                                                                    (mm.get_size() * mm.get_n_bytes()) >> ($clog2(MBOX_DATA_W/8));
-                        if (!rm.mbox_fn_state_sigs.soc_send_stage)
-                            `uvm_error("SOC_IFC_REG_CBS", $sformatf("mbox_execute is set by SOC when in an unexpected state [%p]!", rm.mbox_fn_state_sigs))
-                        rm.mbox_status.mbox_fsm_ps.predict(MBOX_EXECUTE_UC);
-                        rm.mbox_fn_state_sigs = '{uc_receive_stage: 1'b1, default: 1'b0};
-                        // Predict intr sts register is set
-                        //  - Use UVM_PREDICT_READ kind so that all the callbacks associated with
-                        //    notif_cmd_avail_sts are also called to detect interrupt pin assertion
-                        //  - Use UVM_PREDICT_READ instead of UVM_PREDICT_WRITE so that
-                        //    "do_predict" bypasses the access-check and does not enforce W1C
-                        //    behavior on this attempt to set interrupt status to 1
-                        intr_fld.predict(1'b1, -1, UVM_PREDICT_READ, UVM_PREDICT, rm_top.get_map_by_name(this.AHB_map_name)); /* Intr reg access expected only via AHB i/f */
+                        if (!rm.mbox_fn_state_sigs.soc_data_stage)
+                            `uvm_info("SOC_IFC_REG_CBS", $sformatf("mbox_execute is set by SOC when in an unexpected state [%p]!", rm.mbox_fn_state_sigs), UVM_LOW)
                         // Round dlen up to nearest dword boundary and compare with data queue size
                         // On transfer of control, remove extraneous entries from data_q since
                         // reads of these values will be gated for the receiver in DUT
                         if (rm.mbox_data_q.size() != mbox_dlen_mirrored_dword_ceil(rm)) begin
-                            `uvm_info("SOC_IFC_REG_CBS", $sformatf("Write to mbox_execute initiates mailbox command, but the data queue entry count [%0d dwords] does not match the value of dlen [%0d bytes]!", rm.mbox_data_q.size(), mbox_dlen_mirrored(rm)), UVM_MEDIUM)
+                            `uvm_info("SOC_IFC_REG_CBS", $sformatf("Write to mbox_execute initiates mailbox command, but the data queue entry count [%0d dwords] does not match the value of dlen [%0d bytes]!", rm.mbox_data_q.size(), mbox_dlen_mirrored(rm)), UVM_LOW)
                         end
                         if (rm.mbox_data_q.size > dlen_cap_dw) begin
-                            `uvm_info("SOC_IFC_REG_CBS", $sformatf("Extra entries detected in mbox_data_q on control transfer - deleting %d entries", rm.mbox_data_q.size() - dlen_cap_dw), UVM_FULL)
+                            `uvm_info("SOC_IFC_REG_CBS", $sformatf("Extra entries detected in mbox_data_q on control transfer - deleting %d entries", rm.mbox_data_q.size() - dlen_cap_dw), UVM_LOW)
                             while (rm.mbox_data_q.size > dlen_cap_dw) begin
                                 // Continuously remove last entry until size is equal to dlen, since entries are added with push_back
                                 rm.mbox_data_q.delete(rm.mbox_data_q.size()-1);
@@ -150,16 +261,23 @@ class soc_ifc_reg_cbs_mbox_csr_mbox_execute_execute extends soc_ifc_reg_cbs_mbox
                         end
                         else if (rm.mbox_data_q.size < dlen_cap_dw) begin
                             uvm_reg_data_t zeros [$];
-                            `uvm_info("SOC_IFC_REG_CBS", $sformatf("Insufficient entries detected in mbox_data_q on control transfer - 0-filling %d entries", dlen_cap_dw - rm.mbox_data_q.size()), UVM_FULL)
+                            `uvm_info("SOC_IFC_REG_CBS", $sformatf("Insufficient entries detected in mbox_data_q on control transfer - 0-filling %d entries", dlen_cap_dw - rm.mbox_data_q.size()), UVM_LOW)
                             zeros = '{MBOX_DEPTH{32'h0}};
                             zeros = zeros[0:dlen_cap_dw - rm.mbox_data_q.size() - 1];
                             rm.mbox_data_q = {rm.mbox_data_q, zeros};
                         end
                         `uvm_info("SOC_IFC_REG_CBS", $sformatf("Write to mbox_execute sets the field and initiates a command"), UVM_HIGH)
+                        delay_job.state_nxt = MBOX_EXECUTE_UC;
+                        delay_jobs.push_back(delay_job);
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("Write to mbox_execute on map [%s] with value [%x] predicts a state change. Delay job is queued to update DUT model.", map.get_name(), value), UVM_HIGH)
                     end
                     else begin
                         `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] has no effect", kind), UVM_FULL)
                     end
+
+                    // Submit error job after delay job so that it executes later and takes precedence
+                    if (|error_job.error)
+                        delay_jobs.push_back(error_job);
                 end
                 default: begin
                     `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] has no effect", kind), UVM_FULL)
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_lock_lock.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_lock_lock.svh
index 4642a2314..f77f7c932 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_lock_lock.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_lock_lock.svh
@@ -14,6 +14,38 @@
 // limitations under the License.
 //----------------------------------------------------------------------
 
+// Reg predictions that will be scheduled on AHB write to mbox_lock
+class soc_ifc_reg_delay_job_mbox_csr_mbox_lock_lock extends soc_ifc_reg_delay_job;
+    `uvm_object_utils( soc_ifc_reg_delay_job_mbox_csr_mbox_lock_lock )
+    mbox_csr_ext rm; /* mbox_csr_rm */
+    mbox_fsm_state_e state_nxt;
+    uvm_reg_map map;
+    virtual task do_job();
+        `uvm_info("SOC_IFC_REG_DELAY_JOB", "Running delayed job for mbox_csr.mbox_lock.lock", UVM_HIGH)
+        if (rm.mbox_lock.lock.get_mirrored_value() && rm.mbox_fn_state_sigs.mbox_idle) begin
+            rm.mbox_status.mbox_fsm_ps.predict(state_nxt, .kind(UVM_PREDICT_READ), .path(UVM_PREDICT), .map(map));
+            if (map.get_name() == "soc_ifc_AHB_map") begin
+                rm.mbox_status.soc_has_lock.predict(uvm_reg_data_t'(0), .kind(UVM_PREDICT_READ), .path(UVM_PREDICT), .map(map));
+                rm.mbox_fn_state_sigs = '{uc_cmd_stage: 1'b1, default: 1'b0};
+            end
+            else if (map.get_name() == "soc_ifc_APB_map") begin
+                rm.mbox_status.soc_has_lock.predict(uvm_reg_data_t'(1), .kind(UVM_PREDICT_READ), .path(UVM_PREDICT), .map(map));
+                rm.mbox_fn_state_sigs = '{soc_cmd_stage: 1'b1, default: 1'b0};
+            end
+            `uvm_info("SOC_IFC_REG_DELAY_JOB", $sformatf("post_predict called through map [%p] on mbox_lock results in state transition. Functional state tracker: [%p] mbox_fsm_ps transition [%p]", map.get_name(), rm.mbox_fn_state_sigs, state_nxt), UVM_FULL)
+        end
+        else begin
+            `uvm_info("SOC_IFC_REG_DELAY_JOB",
+                      $sformatf("post_predict called through map [%p] on mbox_lock skipped due to lock mirror: [%x] mbox_fn_state_sigs [%p] mbox_fsm_ps mirror [%p]",
+                                map.get_name(),
+                                rm.mbox_lock.lock.get_mirrored_value(),
+                                rm.mbox_fn_state_sigs,
+                                rm.mbox_status.mbox_fsm_ps.get_mirrored_value()),
+                      UVM_FULL)
+        end
+    endtask
+endclass
+
 class soc_ifc_reg_cbs_mbox_csr_mbox_lock_lock extends soc_ifc_reg_cbs_mbox_csr;
 
     `uvm_object_utils(soc_ifc_reg_cbs_mbox_csr_mbox_lock_lock)
@@ -34,8 +66,29 @@ class soc_ifc_reg_cbs_mbox_csr_mbox_lock_lock extends soc_ifc_reg_cbs_mbox_csr;
                                        input uvm_path_e     path,
                                        input uvm_reg_map    map);
         mbox_csr_ext rm; /* mbox_csr_rm */
+        soc_ifc_reg_delay_job_mbox_csr_mbox_lock_lock delay_job;
+        soc_ifc_reg_delay_job_mbox_csr_mbox_prot_error error_job;
         uvm_reg_block blk = fld.get_parent().get_parent(); /* mbox_csr_rm */
         if (!$cast(rm,blk)) `uvm_fatal ("SOC_IFC_REG_CBS", "Failed to get valid class handle")
+        delay_job = soc_ifc_reg_delay_job_mbox_csr_mbox_lock_lock::type_id::create("delay_job");
+        delay_job.rm = rm;
+        delay_job.map = map;
+        delay_job.set_delay_cycles(0);
+
+        // If a scheduled job wanted to predict mbox_lock to 0, but couldn't (because
+        // of the active bus access that led to this callback being called), that job
+        // will trigger a 'miss' event. Service that here.
+        // This happens when mbox_execute or mbox_unlock is accessed and the result
+        // is a prediction for mbox_lock to be cleared, but a bus access to mbox_lock is
+        // active. See the callbacks for those registers.
+        if (rm.mbox_lock_clr_miss.is_on()) begin
+            previous = 0;
+            if (kind == UVM_PREDICT_WRITE)
+                value = previous;
+            `uvm_info("SOC_IFC_REG_CBS", "Completed mbox_lock deassert prediction (scheduled by mbox_execute) prior to performing mbox_lock reg prediction due to bus access", UVM_MEDIUM)
+            rm.mbox_lock_clr_miss.reset(0);
+        end
+
         if (map.get_name() == this.AHB_map_name) begin
             case (kind) inside
                 UVM_PREDICT_READ: begin
@@ -43,16 +96,24 @@ class soc_ifc_reg_cbs_mbox_csr_mbox_lock_lock extends soc_ifc_reg_cbs_mbox_csr;
                     // Reading mbox_lock when it is already locked has no effect, so
                     // only calculate predictions on acquiring lock
                     if (value & ~previous) begin
-                        rm.mbox_status.soc_has_lock.predict(uvm_reg_data_t'(0));
                         if (rm.mbox_fn_state_sigs.mbox_idle) begin
-                            rm.mbox_status.mbox_fsm_ps.predict(MBOX_RDY_FOR_CMD);
-                            rm.mbox_fn_state_sigs = '{uc_send_stage: 1'b1, default: 1'b0};
+                            delay_job.state_nxt = MBOX_RDY_FOR_CMD;
+                            delay_jobs.push_back(delay_job);
+                            `uvm_info("SOC_IFC_REG_CBS", $sformatf("Read from mbox_lock on map [%s] with value [%x] predicts a state change. Delay job is queued to update DUT model.", map.get_name(), value), UVM_HIGH)
                         end
                         else begin
                             `uvm_warning("SOC_IFC_REG_CBS", $sformatf("Lock acquired during unexpected mailbox state [%p]!", rm.mbox_fn_state_sigs))
                         end
                         rm.mbox_data_q.delete();
                         rm.mbox_resp_q.delete();
+                        // Emulate the rd/wr ptr reset + mbox_dataout pre-fill
+                        // logic. Since datain writes (later in the flow) will 
+                        // trigger non-0 data to mbox_dataout (if applicable),
+                        // all we need to do here is reset mbox_dataout to account for the 
+                        // cases where no data is written or dlen == 0.
+                        rm.mbox_datain_to_dataout_predict.trigger();
+                        rm.mbox_dataout.dataout.predict(0, .kind(UVM_PREDICT_READ), .path(UVM_PREDICT), .map(map));
+                        rm.mbox_datain_to_dataout_predict.reset();
                     end
                     else begin
                         `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] has no effect. value: 0x%x previous: 0x%x", kind, value, previous), UVM_FULL)
@@ -66,27 +127,58 @@ class soc_ifc_reg_cbs_mbox_csr_mbox_lock_lock extends soc_ifc_reg_cbs_mbox_csr;
         else if (map.get_name() == this.APB_map_name) begin
             case (kind) inside
                 UVM_PREDICT_READ: begin
+                    // Reading mbox_lock when it is already locked (by uC)
+                    // triggers a notification interrupt to the uC in Caliptra
+                    if (value & previous) begin
+                        if (rm.mbox_fn_state_sigs.mbox_idle) begin
+                            `uvm_error("SOC_IFC_REG_CBS", $sformatf("Read from mbox_lock on map [%s] with value [%x] and previous [%x] is unexpected in state [%p]!", map.get_name(), value, previous, rm.mbox_fn_state_sigs))
+                        end
+                        else if (!rm.mbox_status.soc_has_lock.get_mirrored_value()) begin
+                            `uvm_info("SOC_IFC_REG_CBS", $sformatf("Read from mbox_lock on map [%s] with value [%x] and previous [%x] in state [%p] triggers a notification interrupt for soc_req_lock!", map.get_name(), value, previous, rm.mbox_fn_state_sigs), UVM_HIGH)
+                            rm.get_parent().get_block_by_name("soc_ifc_reg_rm").get_block_by_name("intr_block_rf_ext").get_field_by_name("notif_soc_req_lock_sts").predict(1'b1, -1, UVM_PREDICT_READ, UVM_PREDICT, rm.get_parent().get_map_by_name(this.AHB_map_name)); /* AHB-access only, use AHB map*/
+                        end
+                        else begin
+                            `uvm_info("SOC_IFC_REG_CBS", $sformatf("Read from mbox_lock on map [%s] with value [%x] and previous [%x] in state [%p] has no effect due to soc_has_lock: [%0d]", map.get_name(), value, previous, rm.mbox_fn_state_sigs, rm.mbox_status.soc_has_lock.get_mirrored_value()), UVM_FULL)
+                        end
+                    end
                     // Rising edge on RS
-                    // Reading mbox_lock when it is already locked has no effect, so
-                    // only calculate predictions on acquiring lock
-                    if (value & ~previous) begin
-                        rm.mbox_status.soc_has_lock.predict(uvm_reg_data_t'(1));
+                    // Calculate predictions on acquiring lock
+                    else if (value & ~previous) begin
                         if (rm.mbox_fn_state_sigs.mbox_idle) begin
-                            rm.mbox_status.mbox_fsm_ps.predict(MBOX_RDY_FOR_CMD);
-                            rm.mbox_fn_state_sigs = '{soc_send_stage: 1'b1, default: 1'b0};
+                            delay_job.state_nxt = MBOX_RDY_FOR_CMD;
+                            delay_jobs.push_back(delay_job);
+                            `uvm_info("SOC_IFC_REG_CBS", $sformatf("Read from mbox_lock on map [%s] with value [%x] predicts a state change. Delay job is queued to update DUT model.", map.get_name(), value), UVM_HIGH)
                         end
                         else begin
                             `uvm_warning("SOC_IFC_REG_CBS", $sformatf("Lock acquired during unexpected mailbox state [%p]!", rm.mbox_fn_state_sigs))
                         end
                         rm.mbox_data_q.delete();
                         rm.mbox_resp_q.delete();
+                        // Emulate the rd/wr ptr reset + mbox_dataout pre-fill
+                        // logic. Since datain writes (later in the flow) will 
+                        // trigger non-0 data to mbox_dataout (if applicable),
+                        // all we need to do here is reset mbox_dataout to account for the 
+                        // cases where no data is written or dlen == 0.
+                        rm.mbox_datain_to_dataout_predict.trigger();
+                        rm.mbox_dataout.dataout.predict(0, .kind(UVM_PREDICT_READ), .path(UVM_PREDICT), .map(map));
+                        rm.mbox_datain_to_dataout_predict.reset();
                     end
                     else begin
                         `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] has no effect. value: 0x%x previous: 0x%x", kind, value, previous), UVM_FULL)
                     end
                 end
                 default: begin
-                    `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] has no effect", kind), UVM_FULL)
+                    // FIXME only do an error job if not idle?
+                    error_job = soc_ifc_reg_delay_job_mbox_csr_mbox_prot_error::type_id::create("error_job");
+                    error_job.rm = rm;
+                    error_job.map = map;
+                    error_job.fld = fld;
+                    error_job.set_delay_cycles(0);
+                    error_job.state_nxt = MBOX_ERROR;
+                    error_job.error = '{axs_incorrect_order: 1'b1, default: 1'b0};
+                    delay_jobs.push_back(error_job);
+                    `uvm_info("SOC_IFC_REG_CBS", $sformatf("Write attempt to %s is unexpected! mailbox state [%p], FSM mirror: [%p]", fld.get_name(), rm.mbox_fn_state_sigs, rm.mbox_status.mbox_fsm_ps.get_mirrored_value()), UVM_LOW)
+                    rm.mbox_fn_state_sigs = '{mbox_error: 1'b1, default: 1'b0};
                 end
             endcase
         end
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_status_mbox_fsm_ps.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_status_mbox_fsm_ps.svh
new file mode 100644
index 000000000..ec8591474
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_status_mbox_fsm_ps.svh
@@ -0,0 +1,83 @@
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//----------------------------------------------------------------------
+
+// Reg predictions that will be scheduled on mbox_fsm_ps state change
+class soc_ifc_reg_delay_job_mbox_csr_mbox_status_mbox_fsm_ps extends soc_ifc_reg_delay_job;
+    `uvm_object_utils( soc_ifc_reg_delay_job_mbox_csr_mbox_status_mbox_fsm_ps )
+
+    mbox_csr_ext rm; /* mbox_csr_rm */
+    uvm_reg_block rm_top;
+    uvm_reg_field intr_fld;
+    virtual task do_job();
+        `uvm_info("SOC_IFC_REG_DELAY_JOB", "Running delayed job for mbox_csr.mbox_status.mbox_fsm_ps", UVM_HIGH)
+        rm_top = rm.get_parent();
+        intr_fld = rm_top.get_block_by_name("soc_ifc_reg_rm").get_block_by_name("intr_block_rf_ext").get_field_by_name("notif_cmd_avail_sts");
+
+        // Predict intr sts register is set
+        //  - Use UVM_PREDICT_READ kind so that all the callbacks associated with
+        //    notif_cmd_avail_sts are also called to detect interrupt pin assertion
+        //  - Use UVM_PREDICT_READ instead of UVM_PREDICT_WRITE so that
+        //    "do_predict" bypasses the access-check and does not enforce W1C
+        //    behavior on this attempt to set interrupt status to 1
+        intr_fld.predict(1'b1, -1, UVM_PREDICT_READ, UVM_PREDICT, rm_top.get_map_by_name("soc_ifc_AHB_map")); /* Intr reg access expected only via AHB i/f */
+    endtask
+endclass
+
+class soc_ifc_reg_cbs_mbox_csr_mbox_status_mbox_fsm_ps extends soc_ifc_reg_cbs_mbox_csr;
+
+    `uvm_object_utils(soc_ifc_reg_cbs_mbox_csr_mbox_status_mbox_fsm_ps)
+
+    // Function: post_predict
+    //
+    // Called by the <uvm_reg_field::predict()> method
+    // after a successful UVM_PREDICT_READ or UVM_PREDICT_WRITE prediction.
+    //
+    // ~previous~ is the previous value in the mirror and
+    // ~value~ is the latest predicted value. Any change to ~value~ will
+    // modify the predicted mirror value.
+    //
+    virtual function void post_predict(input uvm_reg_field  fld,
+                                       input uvm_reg_data_t previous,
+                                       inout uvm_reg_data_t value,
+                                       input uvm_predict_e  kind,
+                                       input uvm_path_e     path,
+                                       input uvm_reg_map    map);
+        soc_ifc_reg_delay_job_mbox_csr_mbox_status_mbox_fsm_ps delay_job;
+        mbox_csr_ext rm; /* mbox_csr_rm */
+        mbox_fsm_state_e old_ps;
+        mbox_fsm_state_e new_ps;
+        uvm_reg_block blk = fld.get_parent().get_parent(); /* mbox_csr_rm */
+        if (!$cast(rm,blk)) `uvm_fatal ("SOC_IFC_REG_CBS", "Failed to get valid class handle")
+
+        old_ps = mbox_fsm_state_e'(previous);
+        new_ps = mbox_fsm_state_e'(value);
+        `uvm_info("SOC_IFC_REG_CBS", $sformatf("Prediction on mbox_status updates mbox_fsm_ps mirror to %p", new_ps), UVM_DEBUG)
+
+        // State change results in notification interrupt bit being set to uC
+        // Only if the functional state signals tracker in the reg-model still reports
+        // an old state (which means this is truly the first transition to MBOX_EXECUTE_UC,
+        // and not some spurious transition on the reg mirror after the RTL has already
+        // made the state transition).
+        if (old_ps != new_ps && new_ps == MBOX_EXECUTE_UC && (rm.mbox_fn_state_sigs.soc_data_stage || rm.mbox_fn_state_sigs.soc_receive_stage)) begin
+            delay_job = soc_ifc_reg_delay_job_mbox_csr_mbox_status_mbox_fsm_ps::type_id::create("delay_job");
+            delay_job.rm = rm;
+            delay_job.set_delay_cycles(0);
+            delay_jobs.push_back(delay_job);
+            `uvm_info("SOC_IFC_REG_CBS", $sformatf("Access to mbox_status.mbox_fsm_ps on map [%s] with value [%x] predicts a state change. Delay job is queued to update DUT model.", map.get_name(), value), UVM_HIGH)
+        end
+    endfunction
+
+endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_status_status.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_status_status.svh
index b0a28bd74..0e27ee264 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_status_status.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_status_status.svh
@@ -14,7 +14,7 @@
 // limitations under the License.
 //----------------------------------------------------------------------
 
-// Reg predictions that will be scheduled on AHB write to mbox_unlock
+// Reg predictions that will be scheduled on AHB write to mbox_status
 class soc_ifc_reg_delay_job_mbox_csr_mbox_status_status extends soc_ifc_reg_delay_job;
     `uvm_object_utils( soc_ifc_reg_delay_job_mbox_csr_mbox_status_status )
     mbox_csr_ext rm; /* mbox_csr_rm */
@@ -22,7 +22,26 @@ class soc_ifc_reg_delay_job_mbox_csr_mbox_status_status extends soc_ifc_reg_dela
     uvm_reg_map map;
     virtual task do_job();
         `uvm_info("SOC_IFC_REG_DELAY_JOB", "Running delayed job for mbox_csr.mbox_status.status", UVM_HIGH)
-        rm.mbox_status.mbox_fsm_ps.predict(state_nxt, .kind(UVM_PREDICT_READ), .path(UVM_PREDICT), .map(map));
+        // Check mbox_unlock before predicting FSM change, since a force unlock
+        // has priority over normal flow
+        // mbox_unlock only 'activates' on the falling edge of the pulse; if we detect
+        // that, bail out of this prediction job
+        if (rm.mbox_unlock.unlock.get_mirrored_value()) begin
+            uvm_wait_for_nba_region();
+            if (!rm.mbox_unlock.unlock.get_mirrored_value()) begin
+                return;
+            end
+        end
+        if (rm.mbox_lock.lock.get_mirrored_value()) begin
+            rm.mbox_status.mbox_fsm_ps.predict(state_nxt, .kind(UVM_PREDICT_READ), .path(UVM_PREDICT), .map(map));
+            if (state_nxt == MBOX_EXECUTE_SOC) begin
+                rm.mbox_fn_state_sigs = '{soc_done_stage: 1'b1, default: 1'b0};
+            end
+            else if (state_nxt == MBOX_EXECUTE_UC) begin
+                rm.mbox_fn_state_sigs = '{uc_done_stage: 1'b1, default: 1'b0};
+            end
+            `uvm_info("SOC_IFC_REG_DELAY_JOB", $sformatf("post_predict called through map [%p] on mbox_status results in state transition. Functional state tracker: %p", map.get_name(), rm.mbox_fn_state_sigs), UVM_FULL)
+        end
     endtask
 endclass
 
@@ -46,34 +65,46 @@ class soc_ifc_reg_cbs_mbox_csr_mbox_status_status extends soc_ifc_reg_cbs_mbox_c
                                        input uvm_path_e     path,
                                        input uvm_reg_map    map);
         soc_ifc_reg_delay_job_mbox_csr_mbox_status_status delay_job;
+        soc_ifc_reg_delay_job_mbox_csr_mbox_prot_error error_job;
         mbox_csr_ext rm; /* mbox_csr_rm */
         uvm_mem mm; /* mbox_mem_rm "mem model" */
         uvm_reg_block blk = fld.get_parent().get_parent(); /* mbox_csr_rm */
         mm = blk.get_parent().get_mem_by_name("mbox_mem_rm");
         if (!$cast(rm,blk)) `uvm_fatal ("SOC_IFC_REG_CBS", "Failed to get valid class handle")
+        delay_job = soc_ifc_reg_delay_job_mbox_csr_mbox_status_status::type_id::create("delay_job");
+        delay_job.rm = rm;
+        delay_job.map = map;
+        delay_job.set_delay_cycles(0);
         if (map.get_name() == this.AHB_map_name) begin
             case (kind) inside
                 UVM_PREDICT_WRITE: begin
-                    if (mbox_status_e'(value) != mbox_status_e'(previous) &&
+                    if (rm.mbox_fn_state_sigs.uc_receive_stage &&
+                        mbox_status_e'(value) != mbox_status_e'(previous) &&
                         mbox_status_e'(value) != CMD_BUSY) begin
                         if (!rm.mbox_status.soc_has_lock.get_mirrored_value()) begin
                             `uvm_warning("SOC_IFC_REG_CBS", $sformatf("Write to mbox_status in state [%p] on map [%s] is unexpected!", rm.mbox_fn_state_sigs, map.get_name()))
                         end
                         else begin
-                            uvm_queue #(soc_ifc_reg_delay_job) delay_jobs;
                             // Maximum allowable size for data transferred via mailbox
-                            int unsigned dlen_cap_dw = (mbox_dlen_mirrored(rm) < (mm.get_size() * mm.get_n_bytes())) ? mbox_dlen_mirrored_dword_ceil(rm) :
+                            int unsigned dlen_cap_dw = (mbox_status_e'(value) != DATA_READY)                         ? 0 : /* ignore DLEN if the uC is not sending response data to SOC */
+                                                       (mbox_dlen_mirrored(rm) < (mm.get_size() * mm.get_n_bytes())) ? mbox_dlen_mirrored_dword_ceil(rm) :
                                                                                                                        (mm.get_size() * mm.get_n_bytes()) >> ($clog2(MBOX_DATA_W/8));
                             if (rm.mbox_data_q.size() > 0) begin
                                 `uvm_info("SOC_IFC_REG_CBS", $sformatf("Write to mbox_status transfers control back to SOC, but mbox_data_q is not empty! Size: %0d", rm.mbox_data_q.size()), UVM_LOW) /* TODO: Make a warning that can be disabled for DLEN violation cases? */
+                                rm.mbox_data_q.delete();
                             end
+                            //Pre populated dataout with the first entry of the resp q
+                            rm.mbox_datain_to_dataout_predict.trigger();
+                            rm.mbox_dataout.dataout.predict(rm.mbox_resp_q[0], .kind(UVM_PREDICT_READ), .path(UVM_PREDICT), .map(map));
+                            rm.mbox_datain_to_dataout_predict.reset();
+                            //move resp q to data q
                             rm.mbox_data_q = rm.mbox_resp_q;
                             rm.mbox_resp_q.delete();
                             // On transfer of control, remove extraneous entries from data_q since
                             // reads of these values will be gated for the receiver
                             // in the DUT
                             if (rm.mbox_data_q.size > dlen_cap_dw) begin
-                                `uvm_info("SOC_IFC_REG_CBS", $sformatf("Extra entries detected in mbox_data_q on control transfer - deleting %d entries", rm.mbox_data_q.size() - dlen_cap_dw), UVM_FULL)
+                                `uvm_info("SOC_IFC_REG_CBS", $sformatf("Extra entries detected in mbox_data_q on control transfer - deleting %d entries", rm.mbox_data_q.size() - dlen_cap_dw), UVM_LOW)
                                 while (rm.mbox_data_q.size > dlen_cap_dw) begin
                                     // Continuously remove last entry until size is equal to dlen, since entries are added with push_back
                                     rm.mbox_data_q.delete(rm.mbox_data_q.size()-1);
@@ -81,24 +112,19 @@ class soc_ifc_reg_cbs_mbox_csr_mbox_status_status extends soc_ifc_reg_cbs_mbox_c
                             end
                             else if (rm.mbox_data_q.size < dlen_cap_dw) begin
                                 uvm_reg_data_t zeros [$];
-                                `uvm_info("SOC_IFC_REG_CBS", $sformatf("Insufficient entries detected in mbox_data_q on control transfer - 0-filling %d entries", dlen_cap_dw - rm.mbox_data_q.size()), UVM_FULL)
+                                `uvm_info("SOC_IFC_REG_CBS", $sformatf("Insufficient entries detected in mbox_data_q on control transfer - 0-filling %d entries", dlen_cap_dw - rm.mbox_data_q.size()), UVM_LOW)
                                 zeros = '{MBOX_DEPTH{32'h0}};
                                 zeros = zeros[0:dlen_cap_dw - rm.mbox_data_q.size() - 1];
                                 rm.mbox_data_q = {rm.mbox_data_q, zeros};
                             end
-                            if (!uvm_config_db#(uvm_queue#(soc_ifc_reg_delay_job))::get(null, "soc_ifc_reg_model_top", "delay_jobs", delay_jobs))
-                                `uvm_error("SOC_IFC_REG_CBS", "Failed to get handle for 'delay_jobs' queue from config database!")
-                            delay_job = soc_ifc_reg_delay_job_mbox_csr_mbox_status_status::type_id::create("delay_job");
-                            delay_job.rm = rm;
-                            delay_job.map = map;
-                            delay_job.set_delay_cycles(1);
                             delay_job.state_nxt = MBOX_EXECUTE_SOC;
                             delay_jobs.push_back(delay_job);
                             `uvm_info("SOC_IFC_REG_CBS", $sformatf("Write to mbox_status on map [%s] with value [%x] predicts a state change. Delay job is queued to update DUT model.", map.get_name(), value), UVM_HIGH)
-                            rm.mbox_fn_state_sigs = '{soc_done_stage: 1'b1, default: 1'b0};
-                            `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called through map [%p] with kind [%p] on mbox_status results in state transition. Functional state tracker: %p", map.get_name(), kind, rm.mbox_fn_state_sigs), UVM_FULL)
                         end
                     end
+                    else begin
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("Write to mbox_status on map [%s] with value [%x] during state [%p] does not update the status field (previous value [%x]), so no state change is predicted", map.get_name(), mbox_status_e'(value), rm.mbox_fn_state_sigs, mbox_status_e'(previous)), UVM_MEDIUM)
+                    end
                 end
                 default: begin
                     `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] has no effect", kind), UVM_FULL)
@@ -108,13 +134,13 @@ class soc_ifc_reg_cbs_mbox_csr_mbox_status_status extends soc_ifc_reg_cbs_mbox_c
         else if (map.get_name() == this.APB_map_name) begin
             case (kind) inside
                 UVM_PREDICT_WRITE: begin
-                    if (mbox_status_e'(value) != mbox_status_e'(previous) &&
+                    if (rm.mbox_fn_state_sigs.soc_receive_stage &&
+                        mbox_status_e'(value) != mbox_status_e'(previous) &&
                         mbox_status_e'(value) != CMD_BUSY) begin
                         if (rm.mbox_status.soc_has_lock.get_mirrored_value()) begin
-                            `uvm_warning("SOC_IFC_REG_CBS", $sformatf("Write to mbox_status in state [%p] on map [%s] is unexpected!", rm.mbox_fn_state_sigs, map.get_name()))
+                            `uvm_warning("SOC_IFC_REG_CBS", $sformatf("Write to mbox_status in state [%p] on map [%s] is unexpected! soc_has_lock is %x", rm.mbox_fn_state_sigs, map.get_name(), rm.mbox_status.soc_has_lock.get_mirrored_value()))
                         end
                         else begin
-                            uvm_queue #(soc_ifc_reg_delay_job) delay_jobs;
                             if (rm.mbox_data_q.size() > 0) begin
                                 `uvm_info("SOC_IFC_REG_CBS", $sformatf("Write to mbox_status transfers control back to uC, but mbox_data_q is not empty! Size: %0d", rm.mbox_data_q.size()), UVM_LOW) /* TODO: Make a warning that can be disabled for DLEN violation cases? */
                             end
@@ -123,19 +149,38 @@ class soc_ifc_reg_cbs_mbox_csr_mbox_status_status extends soc_ifc_reg_cbs_mbox_c
                             end
                             rm.mbox_data_q.delete();
                             rm.mbox_resp_q.delete();
-                            if (!uvm_config_db#(uvm_queue#(soc_ifc_reg_delay_job))::get(null, "soc_ifc_reg_model_top", "delay_jobs", delay_jobs))
-                                `uvm_error("SOC_IFC_REG_CBS", "Failed to get handle for 'delay_jobs' queue from config database!")
-                            delay_job = soc_ifc_reg_delay_job_mbox_csr_mbox_status_status::type_id::create("delay_job");
-                            delay_job.rm = rm;
-                            delay_job.map = map;
-                            delay_job.set_delay_cycles(1);
                             delay_job.state_nxt = MBOX_EXECUTE_UC;
                             delay_jobs.push_back(delay_job);
                             `uvm_info("SOC_IFC_REG_CBS", $sformatf("Write to mbox_status on map [%s] with value [%x] predicts a state change. Delay job is queued to update DUT model.", map.get_name(), value), UVM_HIGH)
-                            rm.mbox_fn_state_sigs = '{uc_done_stage: 1'b1, default: 1'b0};
-                            `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called through map [%p] with kind [%p] on mbox_status results in state transition. Functional state tracker: %p", map.get_name(), kind, rm.mbox_fn_state_sigs), UVM_FULL)
                         end
                     end
+                    // Check for protocol violations
+                    if (rm.mbox_fn_state_sigs.mbox_idle) begin
+                        error_job = soc_ifc_reg_delay_job_mbox_csr_mbox_prot_error::type_id::create("error_job");
+                        error_job.rm = rm;
+                        error_job.map = map;
+                        error_job.fld = fld;
+                        error_job.set_delay_cycles(0);
+                        error_job.state_nxt = MBOX_IDLE;
+                        error_job.error = '{axs_without_lock: 1'b1, default: 1'b0};
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("Write to %s on map [%s] with value [%x] causes a mbox no_lock protocol violation. Delay job is queued to update DUT model.", fld.get_name(), map.get_name(), value), UVM_HIGH)
+                        delay_jobs.push_back(error_job);
+                    end
+                    else if (rm.mbox_fn_state_sigs.mbox_error) begin
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("Write to %s on map [%s] with value [%x] during mailbox state [%p] has no additional side effects!", fld.get_name(), map.get_name(), value, rm.mbox_fn_state_sigs), UVM_LOW)
+                    end
+                    else if (!rm.mbox_fn_state_sigs.soc_receive_stage) begin
+                        error_job = soc_ifc_reg_delay_job_mbox_csr_mbox_prot_error::type_id::create("error_job");
+                        error_job.rm = rm;
+                        error_job.map = map;
+                        error_job.fld = fld;
+                        error_job.set_delay_cycles(0);
+                        error_job.state_nxt = MBOX_ERROR;
+                        error_job.error = '{axs_incorrect_order: 1'b1, default: 1'b0};
+                        delay_jobs.push_back(error_job);
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("Write to %s on map [%s] with value [%x] during unexpected mailbox state [%p] results in mbox ooo protocol violation!", fld.get_name(), map.get_name(), value, rm.mbox_fn_state_sigs), UVM_LOW)
+                        rm.mbox_fn_state_sigs = '{mbox_error: 1'b1, default: 1'b0};
+                    end
                 end
                 default: begin
                     `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] has no effect", kind), UVM_FULL)
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_unlock_unlock.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_unlock_unlock.svh
index 05fcb7e30..a4bb89cf6 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_unlock_unlock.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_unlock_unlock.svh
@@ -18,14 +18,48 @@
 class soc_ifc_reg_delay_job_mbox_csr_mbox_unlock_unlock extends soc_ifc_reg_delay_job;
     `uvm_object_utils( soc_ifc_reg_delay_job_mbox_csr_mbox_unlock_unlock )
     mbox_csr_ext rm; /* mbox_csr_rm */
+    uvm_reg_map map;
     virtual task do_job();
         `uvm_info("SOC_IFC_REG_DELAY_JOB", "Running delayed job for mbox_csr.mbox_unlock.unlock", UVM_HIGH)
-        rm.mbox_lock.lock.predict(1'b0);
-        rm.mbox_execute.execute.predict(1'b0);
-        rm.mbox_status.status.predict(CMD_BUSY);
-        rm.mbox_status.mbox_fsm_ps.predict(MBOX_IDLE);
-        rm.mbox_status.soc_has_lock.predict(1'b0);
+        rm.mbox_execute.execute.predict(1'b0, .kind(UVM_PREDICT_READ), .path(UVM_PREDICT), .map(map));
+        rm.mbox_status.status.predict(CMD_BUSY, .kind(UVM_PREDICT_READ), .path(UVM_PREDICT), .map(map));
+        rm.mbox_status.mbox_fsm_ps.predict(MBOX_IDLE, .kind(UVM_PREDICT_READ), .path(UVM_PREDICT), .map(map));
+        rm.mbox_status.soc_has_lock.predict(1'b0, .kind(UVM_PREDICT_READ), .path(UVM_PREDICT), .map(map));
         rm.mbox_fn_state_sigs = '{mbox_idle: 1'b1, default: 1'b0};
+        rm.mbox_unlock.unlock.predict(1'b0);
+        if (rm.mbox_lock.is_busy()) begin
+            `uvm_info("SOC_IFC_REG_DELAY_JOB", "Delay job for mbox_unlock attempted to clear mbox_lock, but hit access collision! Flagging clear event in reg-model for mbox_lock callback to handle", UVM_LOW)
+            rm.mbox_lock_clr_miss.trigger(null);
+            uvm_wait_for_nba_region();
+            // If the bus transfer is still in progress (it didn't terminate on the same
+            // falling clock edge as when this delay job was run), then just override the 
+            // mirrored value immediately. Clear is_busy to avoid a UVM_WARNING.
+            // This use-case is definitely a hack, but it is necessary to synchronize
+            // the mbox_lock mirror with the design, chronologically.
+            if (rm.mbox_lock.is_busy()) begin
+                rm.mbox_lock.Xset_busyX(0);
+                rm.mbox_lock.lock.predict(0);
+                rm.mbox_lock.Xset_busyX(1);
+            end
+            else begin
+                fork
+                    begin
+                        rm.mbox_lock_clr_miss.wait_off();
+                        disable MBOX_CLR_TIMEOUT;
+                    end
+                    begin: MBOX_CLR_TIMEOUT
+                        // If it takes any amount of time for the pending lock to be cleared, that
+                        // means we've encountered some environment bug (since the accessing i/f
+                        // completed it's transfer, the reg prediction should be instantaneous)
+                        uvm_wait_for_nba_region();
+                        `uvm_error("SOC_IFC_REG_DELAY_JOB", $sformatf("mbox_lock clear activity, originally requested by mbox_unlock callback but unserviceable, was scheduled to be completed during mbox_lock callback but took longer than expected to finish!"))
+                    end
+                join_any
+            end
+        end
+        else begin
+            rm.mbox_lock.lock.predict(0);
+        end
     endtask
 endclass
 
@@ -49,22 +83,23 @@ class soc_ifc_reg_cbs_mbox_csr_mbox_unlock_unlock extends soc_ifc_reg_cbs_mbox_c
                                        input uvm_path_e     path,
                                        input uvm_reg_map    map);
         soc_ifc_reg_delay_job_mbox_csr_mbox_unlock_unlock delay_job;
+        uvm_queue #(soc_ifc_reg_delay_job) delay_jobs;
         mbox_csr_ext rm; /* mbox_csr_rm */
         uvm_reg_block blk = fld.get_parent().get_parent(); /* mbox_csr_rm */
         if (!$cast(rm,blk)) `uvm_fatal ("SOC_IFC_REG_CBS", "Failed to get valid class handle")
+        if (!uvm_config_db#(uvm_queue#(soc_ifc_reg_delay_job))::get(null, "soc_ifc_reg_model_top", "delay_jobs", delay_jobs))
+            `uvm_error("SOC_IFC_REG_CBS", "Failed to get handle for 'delay_jobs' queue from config database!")
+        delay_job = soc_ifc_reg_delay_job_mbox_csr_mbox_unlock_unlock::type_id::create("delay_job");
+        delay_job.rm = rm;
+        delay_job.map = map;
+        delay_job.set_delay_cycles(0);
         if ((map.get_name() == this.AHB_map_name)) begin
             case (kind) inside
                 UVM_PREDICT_WRITE: begin
                     if (value) begin
-                        uvm_queue #(soc_ifc_reg_delay_job) delay_jobs;
-                        if (!uvm_config_db#(uvm_queue#(soc_ifc_reg_delay_job))::get(null, "soc_ifc_reg_model_top", "delay_jobs", delay_jobs))
-                            `uvm_error("SOC_IFC_REG_CBS", "Failed to get handle for 'delay_jobs' queue from config database!")
-                        delay_job = soc_ifc_reg_delay_job_mbox_csr_mbox_unlock_unlock::type_id::create("delay_job");
-                        delay_job.rm = rm;
-                        delay_job.set_delay_cycles(1);
                         delay_jobs.push_back(delay_job);
                         `uvm_info("SOC_IFC_REG_CBS", $sformatf("Write to mbox_unlock on map [%s] with value [%x] clears mbox_lock and auto-clears. Delay job is queued to update DUT model.", map.get_name(), value), UVM_HIGH)
-                        value = previous;
+                        //value = previous; // Delay this (field is 1 for 1-cycle)
                     end
                     else begin
                         `uvm_info("SOC_IFC_REG_CBS", $sformatf("Write to mbox_unlock on map [%s] with value [%x] has no effect", map.get_name(), value), UVM_FULL)
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_sample.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_sample.svh
new file mode 100644
index 000000000..099f6e14e
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_sample.svh
@@ -0,0 +1,64 @@
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//----------------------------------------------------------------------
+
+// Callback to add to all register fields.
+// This callback is used to sample coverage after every prediction
+// against the register field it is called on.
+// Expected to be run after any other post_predict callbacks complete
+
+class soc_ifc_reg_cbs_sample extends uvm_reg_cbs;
+
+    `uvm_object_utils(soc_ifc_reg_cbs_sample)
+
+    // Function: post_predict
+    //
+    // Called by the <uvm_reg_field::predict()> method
+    // after a successful UVM_PREDICT_READ or UVM_PREDICT_WRITE prediction.
+    //
+    // ~previous~ is the previous value in the mirror and
+    // ~value~ is the latest predicted value. Any change to ~value~ will
+    // modify the predicted mirror value.
+    //
+    virtual function void post_predict(input uvm_reg_field  fld,
+                                       input uvm_reg_data_t previous,
+                                       inout uvm_reg_data_t value,
+                                       input uvm_predict_e  kind,
+                                       input uvm_path_e     path,
+                                       input uvm_reg_map    map);
+        uvm_reg parent;
+        uvm_reg_data_t data;
+        uvm_reg_data_t mask;
+        bit is_read;
+        parent = fld.get_parent();
+        is_read = kind == UVM_PREDICT_READ;
+        mask = (1 << fld.get_n_bits()) - 1;
+        mask <<= fld.get_lsb_pos();
+        mask = ~mask;
+        data = (parent.get_mirrored_value() & mask) | (value << fld.get_lsb_pos());
+        // Only sample coverage for the field that is being modified.
+        // Since post-predict is called independently for every field in a register
+        // by the reg predictor, this ensures that coverage is only captured for
+        // the register with the new value.
+        if (value != previous) begin
+            parent.XsampleX(data, -1, is_read, map);
+            `uvm_info("SOC_IFC_REG_SAMPLE_CBS", $sformatf("post_predict called with kind [%p] path [%p] map [%s] on fld [%s] to sample coverage", kind, path, map.get_name(), fld.get_full_name()), UVM_DEBUG)
+        end
+        else begin
+            `uvm_info("SOC_IFC_REG_SAMPLE_CBS", $sformatf("post_predict called with kind [%p] path [%p] map [%s] on fld [%s] does not result in coverage sampling due to no value change", kind, path, map.get_name(), fld.get_full_name()), UVM_DEBUG)
+        end
+    endfunction
+
+endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_sha512_acc_csr_EXECUTE_EXECUTE.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_sha512_acc_csr_EXECUTE_EXECUTE.svh
new file mode 100644
index 000000000..950292c61
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_sha512_acc_csr_EXECUTE_EXECUTE.svh
@@ -0,0 +1,126 @@
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//----------------------------------------------------------------------
+
+// Reg predictions that will be scheduled on AHB write to mbox_execute
+class soc_ifc_reg_delay_job_sha512_acc_csr_EXECUTE_EXECUTE extends soc_ifc_reg_delay_job;
+    `uvm_object_utils( soc_ifc_reg_delay_job_sha512_acc_csr_EXECUTE_EXECUTE )
+    sha512_acc_csr_ext rm; /* sha512_acc_csr_rm */
+    uvm_reg_block rm_top;
+    uvm_reg_field intr_fld;
+    uvm_reg_map map;
+    virtual task do_job();
+        `uvm_info("SOC_IFC_REG_DELAY_JOB", "Running delayed job for sha512_acc_csr.EXECUTE.EXECUTE", UVM_HIGH)
+        rm_top = rm.get_parent();
+        intr_fld = rm_top.get_block_by_name("sha512_acc_csr_rm").get_block_by_name("intr_block_rf_ext").get_field_by_name("notif_cmd_done_sts");
+        // Check LOCK before predicting interrupt occurrence
+        if (rm.LOCK.LOCK.get_mirrored_value()) begin
+            // Predict intr sts register is set to indicate operation completes
+            //  - Use UVM_PREDICT_READ kind so that all the callbacks associated with
+            //    notif_cmd_done_sts are also called to detect interrupt pin assertion
+            //  - Use UVM_PREDICT_READ instead of UVM_PREDICT_WRITE so that
+            //    "do_predict" bypasses the access-check and does not enforce W1C
+            //    behavior on this attempt to set interrupt status to 1
+            intr_fld.predict(1'b1, -1, UVM_PREDICT_READ, UVM_PREDICT, rm_top.get_map_by_name("soc_ifc_AHB_map")); /* Intr reg access expected only via AHB i/f */
+            `uvm_info("SOC_IFC_REG_DELAY_JOB", $sformatf("post_predict called through map [%p] on EXECUTE results in interrupt status bit being set.", map.get_name()), UVM_FULL)
+        end
+        else begin
+            `uvm_error("SOC_IFC_REG_DELAY_JOB",
+                       $sformatf("Delay job for EXECUTE does not predict any changes due to: LOCK mirror [%d]",
+                                 rm.LOCK.LOCK.get_mirrored_value()))
+        end
+    endtask
+endclass
+
+class soc_ifc_reg_cbs_sha512_acc_csr_EXECUTE_EXECUTE extends uvm_reg_cbs;
+
+    `uvm_object_utils(soc_ifc_reg_cbs_sha512_acc_csr_EXECUTE_EXECUTE)
+
+    string AHB_map_name = "soc_ifc_AHB_map";
+    string APB_map_name = "soc_ifc_APB_map";
+    
+    uvm_queue #(soc_ifc_reg_delay_job) delay_jobs;
+
+    function new(string name = "uvm_reg_cbs");
+        super.new(name);
+        if (!uvm_config_db#(uvm_queue#(soc_ifc_reg_delay_job))::get(null, "soc_ifc_reg_model_top", "delay_jobs", delay_jobs))
+            `uvm_error("SOC_IFC_REG_CBS", "Failed to get handle for 'delay_jobs' queue from config database!")
+    endfunction
+
+    // Function: post_predict
+    //
+    // Called by the <uvm_reg_field::predict()> method
+    // after a successful UVM_PREDICT_READ or UVM_PREDICT_WRITE prediction.
+    //
+    // ~previous~ is the previous value in the mirror and
+    // ~value~ is the latest predicted value. Any change to ~value~ will
+    // modify the predicted mirror value.
+    //
+    virtual function void post_predict(input uvm_reg_field  fld,
+                                       input uvm_reg_data_t previous,
+                                       inout uvm_reg_data_t value,
+                                       input uvm_predict_e  kind,
+                                       input uvm_path_e     path,
+                                       input uvm_reg_map    map);
+        soc_ifc_reg_delay_job_sha512_acc_csr_EXECUTE_EXECUTE delay_job;
+        sha512_acc_csr_ext rm; /* sha512_acc_csr_rm */
+        uvm_reg_block blk = fld.get_parent().get_parent(); /* sha512_acc_csr_rm */
+        if (!$cast(rm,blk)) `uvm_fatal ("SOC_IFC_REG_CBS", "Failed to get valid class handle")
+        delay_job = soc_ifc_reg_delay_job_sha512_acc_csr_EXECUTE_EXECUTE::type_id::create("delay_job");
+        delay_job.rm = rm;
+        delay_job.map = map;
+        // 82 cycle delay based on waveform analysis of minimum delay from EXECUTE->DONE
+        // Commentary on a more sophisticated analysis:
+        // -----------------------------------------------------------
+        //   Streaming mode - 82 or 164 clocks after setting execute. If the
+        //   padding fits in the current block we pad and process, interrupt will
+        //   come 82 clocks later. If padding doesn't fit, we process the current
+        //   block and another block with the padding. 164 clocks. There may be a
+        //   clock or two for state transitions in there.
+        //    
+        //   Mailbox mode - DLEN/128 should tell you how many 1024 bit blocks
+        //   you have to process. We can read a block faster than process, so the
+        //   long pole is the process time. Something like 32 clocks to read
+        //   the first block + 82 clocks per block to process each. Total DLEN
+        //   could be less than 1024, so in that case the initial read would be
+        //   DLEN/4 clocks. There's also the case that the size requires an
+        //   additional padding block, which may be computed if necessary.
+        // -----------------------------------------------------------
+        delay_job.set_delay_cycles(81);
+        if (map.get_name() == this.AHB_map_name) begin
+            case (kind) inside
+                UVM_PREDICT_WRITE: begin
+                    if (value & ~previous) begin
+                        delay_jobs.push_back(delay_job);
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] on map [%s] results in predicted interrupt. Delay job queued. value: 0x%x previous: 0x%x", kind, map.get_name(), value, previous), UVM_FULL)
+                    end
+                    else begin
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] on map [%s] has no effect", kind, map.get_name()), UVM_FULL)
+                    end
+                end
+                default: begin
+                    `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] on map [%s] has no effect", kind, map.get_name()), UVM_FULL)
+                end
+            endcase
+        end
+        else if (map.get_name() == this.APB_map_name) begin
+                    `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] on map [%s] has no effect", kind, map.get_name()), UVM_FULL)
+        end
+        else begin
+            `uvm_error("SOC_IFC_REG_CBS", $sformatf("post_predict called through unsupported reg map %s!", map.get_name()))
+        end
+    endfunction
+
+endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_sha512_acc_csr_LOCK_LOCK.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_sha512_acc_csr_LOCK_LOCK.svh
new file mode 100644
index 000000000..18b2cbbda
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_sha512_acc_csr_LOCK_LOCK.svh
@@ -0,0 +1,131 @@
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//----------------------------------------------------------------------
+
+// Reg predictions that will be scheduled on write to clear LOCK
+class soc_ifc_reg_delay_job_sha512_acc_csr_LOCK_LOCK extends soc_ifc_reg_delay_job;
+    `uvm_object_utils( soc_ifc_reg_delay_job_sha512_acc_csr_LOCK_LOCK )
+    sha512_acc_csr_ext rm; /* sha512_acc_csr_rm */
+    uvm_reg_map map;
+    virtual task do_job();
+        `uvm_info("SOC_IFC_REG_DELAY_JOB", "Running delayed job for sha512_acc_csr.LOCK.LOCK", UVM_HIGH)
+        if (1) begin
+            rm.EXECUTE.EXECUTE.predict(1'b0, -1, UVM_PREDICT_WRITE, UVM_PREDICT, map);
+            `uvm_info("SOC_IFC_REG_DELAY_JOB", $sformatf("post_predict called through map [%p] on LOCK results in EXECUTE being cleared.", map.get_name()), UVM_FULL)
+        end
+        else begin
+            `uvm_error("SOC_IFC_REG_DELAY_JOB",
+                       $sformatf("Delay job for LOCK does not predict any changes due to: ???"))
+        end
+    endtask
+endclass
+
+class soc_ifc_reg_cbs_sha512_acc_csr_LOCK_LOCK extends uvm_reg_cbs;
+
+    `uvm_object_utils(soc_ifc_reg_cbs_sha512_acc_csr_LOCK_LOCK)
+
+    string AHB_map_name = "soc_ifc_AHB_map";
+    string APB_map_name = "soc_ifc_APB_map";
+    
+    uvm_queue #(soc_ifc_reg_delay_job) delay_jobs;
+
+    function new(string name = "uvm_reg_cbs");
+        super.new(name);
+        if (!uvm_config_db#(uvm_queue#(soc_ifc_reg_delay_job))::get(null, "soc_ifc_reg_model_top", "delay_jobs", delay_jobs))
+            `uvm_error("SOC_IFC_REG_CBS", "Failed to get handle for 'delay_jobs' queue from config database!")
+    endfunction
+
+    // Function: post_predict
+    //
+    // Called by the <uvm_reg_field::predict()> method
+    // after a successful UVM_PREDICT_READ or UVM_PREDICT_WRITE prediction.
+    //
+    // ~previous~ is the previous value in the mirror and
+    // ~value~ is the latest predicted value. Any change to ~value~ will
+    // modify the predicted mirror value.
+    //
+    virtual function void post_predict(input uvm_reg_field  fld,
+                                       input uvm_reg_data_t previous,
+                                       inout uvm_reg_data_t value,
+                                       input uvm_predict_e  kind,
+                                       input uvm_path_e     path,
+                                       input uvm_reg_map    map);
+        soc_ifc_reg_delay_job_sha512_acc_csr_LOCK_LOCK delay_job;
+        sha512_acc_csr_ext rm; /* sha512_acc_csr_rm */
+        uvm_reg_block blk = fld.get_parent().get_parent(); /* sha512_acc_csr_rm */
+        if (!$cast(rm,blk)) `uvm_fatal ("SOC_IFC_REG_CBS", "Failed to get valid class handle")
+        delay_job = soc_ifc_reg_delay_job_sha512_acc_csr_LOCK_LOCK::type_id::create("delay_job");
+        delay_job.rm = rm;
+        delay_job.map = map;
+        delay_job.set_delay_cycles(0);
+        if (map.get_name() == this.AHB_map_name) begin
+            case (kind) inside
+                UVM_PREDICT_READ: begin
+                    // Rising edge on RS
+                    // Reading lock when it is already locked has no effect, so
+                    // only calculate predictions on acquiring lock
+                    if (value & ~previous) begin
+                        rm.STATUS.SOC_HAS_LOCK.predict(uvm_reg_data_t'(0));
+                    end
+                    else begin
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] has no effect. value: 0x%x previous: 0x%x", kind, value, previous), UVM_FULL)
+                    end
+                end
+                UVM_PREDICT_WRITE: begin
+                    if (~value & previous) begin
+                        delay_jobs.push_back(delay_job);
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] on map [%s] results in predicted LOCK deassertion, which clears EXECUTE. Delay job queued. value: 0x%x previous: 0x%x", kind, map.get_name(), value, previous), UVM_FULL)
+                    end
+                    else begin
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] has no effect", kind), UVM_FULL)
+                    end
+                end
+                default: begin
+                    `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] has no effect", kind), UVM_FULL)
+                end
+            endcase
+        end
+        else if (map.get_name() == this.APB_map_name) begin
+            case (kind) inside
+                UVM_PREDICT_READ: begin
+                    // Rising edge on RS
+                    // Reading lock when it is already locked has no effect, so
+                    // only calculate predictions on acquiring lock
+                    if (value & ~previous) begin
+                        rm.STATUS.SOC_HAS_LOCK.predict(uvm_reg_data_t'(1));
+                    end
+                    else begin
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] has no effect. value: 0x%x previous: 0x%x", kind, value, previous), UVM_FULL)
+                    end
+                end
+                UVM_PREDICT_WRITE: begin
+                    if (~value & previous) begin
+                        delay_jobs.push_back(delay_job);
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] on map [%s] results in predicted LOCK deassertion, which clears EXECUTE. Delay job queued. value: 0x%x previous: 0x%x", kind, map.get_name(), value, previous), UVM_FULL)
+                    end
+                    else begin
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] has no effect", kind), UVM_FULL)
+                    end                end
+                default: begin
+                    `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] has no effect", kind), UVM_FULL)
+                end
+            endcase
+        end
+        else begin
+            `uvm_error("SOC_IFC_REG_CBS", "post_predict called through unsupported reg map!")
+        end
+    endfunction
+
+endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_HW_ERROR_FATAL.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_HW_ERROR_FATAL.svh
new file mode 100644
index 000000000..3fd9f3f02
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_HW_ERROR_FATAL.svh
@@ -0,0 +1,68 @@
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//----------------------------------------------------------------------
+
+class soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_HW_ERROR_FATAL extends uvm_reg_cbs;
+
+    `uvm_object_utils(soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_HW_ERROR_FATAL)
+
+    string AHB_map_name = "soc_ifc_AHB_map";
+    string APB_map_name = "soc_ifc_APB_map";
+
+    // Function: post_predict
+    //
+    // Called by the <uvm_reg_field::predict()> method
+    // after a successful UVM_PREDICT_READ or UVM_PREDICT_WRITE prediction.
+    //
+    // ~previous~ is the previous value in the mirror and
+    // ~value~ is the latest predicted value. Any change to ~value~ will
+    // modify the predicted mirror value.
+    //
+    virtual function void post_predict(input uvm_reg_field  fld,
+                                       input uvm_reg_data_t previous,
+                                       inout uvm_reg_data_t value,
+                                       input uvm_predict_e  kind,
+                                       input uvm_path_e     path,
+                                       input uvm_reg_map    map);
+        soc_ifc_reg_ext rm; /* soc_ifc_reg_rm */
+        uvm_reg_block blk = fld.get_parent().get_parent(); /* soc_ifc_reg_rm */
+        if (!$cast(rm,blk)) `uvm_fatal ("SOC_IFC_REG_CBS", "Failed to get valid class handle")
+        if (map.get_name() == this.AHB_map_name) begin
+            case (kind) inside
+                default: begin
+                    `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] has no effect. value: 0x%x previous: 0x%x", kind, value, previous), UVM_FULL)
+                end
+            endcase
+        end
+        else if (map.get_name() == this.APB_map_name) begin
+            case (kind) inside
+// SoC DOES have write privs
+//                UVM_PREDICT_WRITE: begin
+//                    if (value != previous) begin
+//                        value = previous;
+//                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("Writes to [%s] unsupported via map [%s], value prediction is dropped", fld.get_full_name(), map.get_name()), UVM_LOW)
+//                    end
+//                end
+                default: begin
+                    `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] has no effect. value: 0x%x previous: 0x%x", kind, value, previous), UVM_FULL)
+                end
+            endcase
+        end
+        else begin
+            `uvm_error("SOC_IFC_REG_CBS", "post_predict called through unsupported reg map!")
+        end
+    endfunction
+
+endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_HW_ERROR_NON_FATAL.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_HW_ERROR_NON_FATAL.svh
new file mode 100644
index 000000000..8fbb61989
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_HW_ERROR_NON_FATAL.svh
@@ -0,0 +1,68 @@
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//----------------------------------------------------------------------
+
+class soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_HW_ERROR_NON_FATAL extends uvm_reg_cbs;
+
+    `uvm_object_utils(soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_HW_ERROR_NON_FATAL)
+
+    string AHB_map_name = "soc_ifc_AHB_map";
+    string APB_map_name = "soc_ifc_APB_map";
+
+    // Function: post_predict
+    //
+    // Called by the <uvm_reg_field::predict()> method
+    // after a successful UVM_PREDICT_READ or UVM_PREDICT_WRITE prediction.
+    //
+    // ~previous~ is the previous value in the mirror and
+    // ~value~ is the latest predicted value. Any change to ~value~ will
+    // modify the predicted mirror value.
+    //
+    virtual function void post_predict(input uvm_reg_field  fld,
+                                       input uvm_reg_data_t previous,
+                                       inout uvm_reg_data_t value,
+                                       input uvm_predict_e  kind,
+                                       input uvm_path_e     path,
+                                       input uvm_reg_map    map);
+        soc_ifc_reg_ext rm; /* soc_ifc_reg_rm */
+        uvm_reg_block blk = fld.get_parent().get_parent(); /* soc_ifc_reg_rm */
+        if (!$cast(rm,blk)) `uvm_fatal ("SOC_IFC_REG_CBS", "Failed to get valid class handle")
+        if (map.get_name() == this.AHB_map_name) begin
+            case (kind) inside
+                default: begin
+                    `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] has no effect. value: 0x%x previous: 0x%x", kind, value, previous), UVM_FULL)
+                end
+            endcase
+        end
+        else if (map.get_name() == this.APB_map_name) begin
+            case (kind) inside
+// SoC DOES have write privs
+//                UVM_PREDICT_WRITE: begin
+//                    if (value != previous) begin
+//                        value = previous;
+//                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("Writes to [%s] unsupported via map [%s], value prediction is dropped", fld.get_full_name(), map.get_name()), UVM_LOW)
+//                    end
+//                end
+                default: begin
+                    `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] has no effect. value: 0x%x previous: 0x%x", kind, value, previous), UVM_FULL)
+                end
+            endcase
+        end
+        else begin
+            `uvm_error("SOC_IFC_REG_CBS", "post_predict called through unsupported reg map!")
+        end
+    endfunction
+
+endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_TRNG_CTRL_CLEAR.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_TRNG_CTRL_CLEAR.svh
new file mode 100644
index 000000000..6949ef358
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_TRNG_CTRL_CLEAR.svh
@@ -0,0 +1,119 @@
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//----------------------------------------------------------------------
+
+// Reg predictions that will be scheduled on AHB write to internal_fw_update_reset
+class soc_ifc_reg_delay_job_soc_ifc_reg_CPTRA_TRNG_CTRL_CLEAR extends soc_ifc_reg_delay_job;
+    `uvm_object_utils( soc_ifc_reg_delay_job_soc_ifc_reg_CPTRA_TRNG_CTRL_CLEAR )
+    soc_ifc_reg_ext rm; /* soc_ifc_reg_rm */
+    uvm_reg_block rm_top;
+    uvm_reg_map map;
+    bit clear_trng_data_regs;
+    int i;
+
+    virtual task do_job();
+        `uvm_info("SOC_IFC_REG_DELAY_JOB", "Running delayed job for soc_ifc_reg.CPTRA_TRNG_CTRL.clear", UVM_LOW)
+        rm_top = rm.get_parent();
+        for (i=0; i<$size(rm.CPTRA_TRNG_DATA); i++) begin
+            `uvm_info("SOC_IFC_REG_CBS", $sformatf("Before clear: TRNG data[%0d] value 0x%x", i, rm.CPTRA_TRNG_DATA[i].DATA.get_mirrored_value()), UVM_DEBUG)
+        end
+        if (clear_trng_data_regs) begin
+            for (i=0; i<$size(rm.CPTRA_TRNG_DATA); i++) begin
+                rm.CPTRA_TRNG_DATA[i].DATA.predict(uvm_reg_data_t'(0));
+            end
+        end
+        for (i=0; i<$size(rm.CPTRA_TRNG_DATA); i++) begin
+            `uvm_info("SOC_IFC_REG_CBS", $sformatf("After clear: TRNG data[%0d] value 0x%x", i, rm.CPTRA_TRNG_DATA[i].DATA.get_mirrored_value()), UVM_DEBUG)
+        end
+    endtask
+endclass
+
+// Callback for CPTRA TRNG CTRL register
+class soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_TRNG_CTRL_CLEAR extends uvm_reg_cbs;
+
+    `uvm_object_utils(soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_TRNG_CTRL_CLEAR)
+
+    string AHB_map_name = "soc_ifc_AHB_map";
+    string APB_map_name = "soc_ifc_APB_map";
+    uvm_queue #(soc_ifc_reg_delay_job) delay_jobs;
+
+    function new(string name = "uvm_reg_cbs");
+        super.new(name);
+        if (!uvm_config_db#(uvm_queue#(soc_ifc_reg_delay_job))::get(null, "soc_ifc_reg_model_top", "delay_jobs", delay_jobs))
+            `uvm_error("SOC_IFC_REG_CBS", "Failed to get handle for 'delay_jobs' queue from config database!")
+    endfunction
+
+    // Function: post_predict
+    //
+    // Called by the <uvm_reg_field::predict()> method
+    // after a successful UVM_PREDICT_READ or UVM_PREDICT_WRITE prediction.
+    //
+    // ~previous~ is the previous value in the mirror and
+    // ~value~ is the latest predicted value. Any change to ~value~ will
+    // modify the predicted mirror value.
+    //
+    virtual function void post_predict(input uvm_reg_field  fld,
+                                       input uvm_reg_data_t previous,
+                                       inout uvm_reg_data_t value,
+                                       input uvm_predict_e  kind,
+                                       input uvm_path_e     path,
+                                       input uvm_reg_map    map);
+
+        soc_ifc_reg_delay_job_soc_ifc_reg_CPTRA_TRNG_CTRL_CLEAR delay_job_clear_trng_data_regs;
+        soc_ifc_reg_ext rm; /* soc_ifc_reg_rm */
+        uvm_reg_block blk = fld.get_parent().get_parent(); /* soc_ifc_reg_rm */
+        if (!$cast(rm,blk)) `uvm_fatal ("SOC_IFC_REG_CBS", "Failed to get valid class handle")
+        delay_job_clear_trng_data_regs = soc_ifc_reg_delay_job_soc_ifc_reg_CPTRA_TRNG_CTRL_CLEAR::type_id::create("delay_job_clear_trng_data_regs");
+        delay_job_clear_trng_data_regs.rm = rm;
+        delay_job_clear_trng_data_regs.map = map;
+        delay_job_clear_trng_data_regs.clear_trng_data_regs = 1;
+        //account for state transitions + variable wait cycle time
+        delay_job_clear_trng_data_regs.set_delay_cycles(1);
+
+        if (map.get_name() == this.AHB_map_name) begin
+            case (kind) inside
+                UVM_PREDICT_WRITE: begin
+                    if (value & !previous) begin
+                        //push a delayed job for clearing of TRNG data regs
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("Sending delay job for internal register field %s with %0d clk delay", fld.get_full_name(), delay_job_clear_trng_data_regs.get_delay_cycles()), UVM_LOW)
+                        value = 1'b0; //TRNG_CTRL.clear is a pulse
+                        delay_jobs.push_back(delay_job_clear_trng_data_regs);
+                    end else begin
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] on map [%s] has no effect on internal register field %s", kind, map.get_name(), fld.get_full_name()), UVM_FULL)
+                    end
+                end
+                default: begin
+                    `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] on map [%s] has no effect on internal register field %s", kind, map.get_name(), fld.get_full_name()), UVM_FULL)
+        
+                end
+            endcase
+        end
+        else if (map.get_name() == this.APB_map_name) begin
+            case (kind) inside
+                UVM_PREDICT_WRITE: begin
+                    `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict blocked write attempt to internal reg field %s on map %s. value: 0x%x previous: 0x%x", fld.get_full_name(), map.get_name(), value, previous), UVM_LOW)
+                    value = previous;
+                end
+                default: begin
+                    `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] on map [%s] has no effect on internal register field %s. value: 0x%x previous: 0x%x", kind, map.get_name(), fld.get_full_name(), value, previous), UVM_FULL)
+                end
+            endcase
+        end
+        else begin
+            `uvm_error("SOC_IFC_REG_CBS", {"post_predict called through unsupported reg map! ", map.get_name()})
+        end
+    endfunction
+
+endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART.svh
new file mode 100644
index 000000000..bb2af36b0
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART.svh
@@ -0,0 +1,82 @@
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//----------------------------------------------------------------------
+
+class soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART extends uvm_reg_cbs;
+
+    `uvm_object_utils(soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART)
+
+    string AHB_map_name = "soc_ifc_AHB_map";
+    string APB_map_name = "soc_ifc_APB_map";
+
+    // Function: post_predict
+    //
+    // Called by the <uvm_reg_field::predict()> method
+    // after a successful UVM_PREDICT_READ or UVM_PREDICT_WRITE prediction.
+    //
+    // ~previous~ is the previous value in the mirror and
+    // ~value~ is the latest predicted value. Any change to ~value~ will
+    // modify the predicted mirror value.
+    //
+    virtual function void post_predict(input uvm_reg_field  fld,
+                                       input uvm_reg_data_t previous,
+                                       inout uvm_reg_data_t value,
+                                       input uvm_predict_e  kind,
+                                       input uvm_path_e     path,
+                                       input uvm_reg_map    map);
+        // uvm_reg_block rm;
+        // string        event_name;
+        // uvm_reg       sts_reg;
+        // uvm_reg_field sts_fld;
+
+        // rm = fld.get_parent().get_parent(); /* intr_block_rf_ext */
+        // // Get a base-name for the event by truncating the '_trig' suffix
+        // event_name = fld.get_name().substr(0,fld.get_name().len()-6);
+        // sts_reg  = rm.get_reg_by_name("error_internal_intr_r");
+        // sts_fld  = sts_reg.get_field_by_name({event_name, "_sts"});
+
+        if (map.get_name() == this.APB_map_name) begin
+            if (kind == UVM_PREDICT_WRITE)
+                `uvm_warning("SOC_IFC_REG_CBS", "Unexpected write to WDT_TIMER1_CTRL register through APB interface!")
+            else
+                `uvm_info("SOC_IFC_REG_CBS", "Unexpected read to WDT_TIMER1_CTRL register through APB interface!", UVM_LOW)
+        end
+        `uvm_info("SOC_IFC_REG_CBS", $sformatf("Access to %s with path %p", fld.get_full_name(), path), UVM_FULL)
+
+        if (kind == UVM_PREDICT_WRITE) begin
+            // On rising edge of field trigger value, predict interrupt status will
+            // be set
+            if (value & ~previous) begin
+                `uvm_info("SOC_IFC_REG_CBS", {"Predicted update to ", fld.get_name()}, UVM_MEDIUM)
+                //  - Use UVM_PREDICT_READ kind so that all the callbacks associated with
+                //    notif_<event>_sts are also called to detect interrupt pin assertion
+                //  - Use UVM_PREDICT_READ instead of UVM_PREDICT_WRITE so that
+                //    "do_predict" bypasses the access-check and does not enforce W1C
+                //    behavior on this attempt to set interrupt status to 1
+            end
+
+            // Because WDT timer restart is single-pulse, it should auto-clear immediately on
+            // being written.
+            // So set predicted value to 0.
+            value = 0;
+            `uvm_info("SOC_IFC_REG_CBS",
+                      $sformatf("Write to %s results in mirrored value forcibly predicted to [%x]",
+                                fld.get_name(),
+                                value),
+                      UVM_HIGH)
+        end
+    endfunction
+
+endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART.svh
new file mode 100644
index 000000000..129a5e19c
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART.svh
@@ -0,0 +1,82 @@
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//----------------------------------------------------------------------
+
+class soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART extends uvm_reg_cbs;
+
+    `uvm_object_utils(soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART)
+
+    string AHB_map_name = "soc_ifc_AHB_map";
+    string APB_map_name = "soc_ifc_APB_map";
+
+    // Function: post_predict
+    //
+    // Called by the <uvm_reg_field::predict()> method
+    // after a successful UVM_PREDICT_READ or UVM_PREDICT_WRITE prediction.
+    //
+    // ~previous~ is the previous value in the mirror and
+    // ~value~ is the latest predicted value. Any change to ~value~ will
+    // modify the predicted mirror value.
+    //
+    virtual function void post_predict(input uvm_reg_field  fld,
+                                       input uvm_reg_data_t previous,
+                                       inout uvm_reg_data_t value,
+                                       input uvm_predict_e  kind,
+                                       input uvm_path_e     path,
+                                       input uvm_reg_map    map);
+        // uvm_reg_block rm;
+        // string        event_name;
+        // uvm_reg       sts_reg;
+        // uvm_reg_field sts_fld;
+
+        // rm = fld.get_parent().get_parent(); /* intr_block_rf_ext */
+        // // Get a base-name for the event by truncating the '_trig' suffix
+        // event_name = fld.get_name().substr(0,fld.get_name().len()-6);
+        // sts_reg  = rm.get_reg_by_name("error_internal_intr_r");
+        // sts_fld  = sts_reg.get_field_by_name({event_name, "_sts"});
+
+        if (map.get_name() == this.APB_map_name) begin
+            if (kind == UVM_PREDICT_WRITE)
+                `uvm_warning("SOC_IFC_REG_CBS", "Unexpected write to WDT_TIMER2_CTRL register through APB interface!")
+            else
+                `uvm_info("SOC_IFC_REG_CBS", "Unexpected read to WDT_TIMER2_CTRL register through APB interface!", UVM_LOW)
+        end
+        `uvm_info("SOC_IFC_REG_CBS", $sformatf("Access to %s with path %p", fld.get_full_name(), path), UVM_FULL)
+
+        if (kind == UVM_PREDICT_WRITE) begin
+            // On rising edge of field trigger value, predict interrupt status will
+            // be set
+            if (value & ~previous) begin
+                `uvm_info("SOC_IFC_REG_CBS", {"Predicted update to ", fld.get_name(), " triggers interrupt output pin assertion"}, UVM_MEDIUM)
+                //  - Use UVM_PREDICT_READ kind so that all the callbacks associated with
+                //    notif_<event>_sts are also called to detect interrupt pin assertion
+                //  - Use UVM_PREDICT_READ instead of UVM_PREDICT_WRITE so that
+                //    "do_predict" bypasses the access-check and does not enforce W1C
+                //    behavior on this attempt to set interrupt status to 1
+            end
+
+            // Because WDT timer restart is single-pulse, it should auto-clear immediately on
+            // being written.
+            // So set predicted value to 0.
+            value = 0;
+            `uvm_info("SOC_IFC_REG_CBS",
+                      $sformatf("Write to %s results in mirrored value forcibly predicted to [%x]",
+                                fld.get_name(),
+                                value),
+                      UVM_HIGH)
+        end
+    endfunction
+
+endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_soc_ifc_reg_fuse.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_soc_ifc_reg_fuse.svh
new file mode 100644
index 000000000..24c76f02a
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_soc_ifc_reg_fuse.svh
@@ -0,0 +1,67 @@
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//----------------------------------------------------------------------
+
+class soc_ifc_reg_cbs_soc_ifc_reg_fuse extends uvm_reg_cbs;
+
+    `uvm_object_utils(soc_ifc_reg_cbs_soc_ifc_reg_fuse)
+
+    string AHB_map_name = "soc_ifc_AHB_map";
+    string APB_map_name = "soc_ifc_APB_map";
+
+    // Function: post_predict
+    //
+    // Called by the <uvm_reg_field::predict()> method
+    // after a successful UVM_PREDICT_READ or UVM_PREDICT_WRITE prediction.
+    //
+    // ~previous~ is the previous value in the mirror and
+    // ~value~ is the latest predicted value. Any change to ~value~ will
+    // modify the predicted mirror value.
+    //
+    virtual function void post_predict(input uvm_reg_field  fld,
+                                       input uvm_reg_data_t previous,
+                                       inout uvm_reg_data_t value,
+                                       input uvm_predict_e  kind,
+                                       input uvm_path_e     path,
+                                       input uvm_reg_map    map);
+        soc_ifc_reg_ext rm; /* soc_ifc_reg_rm */
+        uvm_reg_block blk = fld.get_parent().get_parent(); /* soc_ifc_reg_rm */
+        if (!$cast(rm,blk)) `uvm_fatal ("SOC_IFC_REG_CBS", "Failed to get valid class handle")
+        if (map.get_name() == this.AHB_map_name ||
+            map.get_name() == this.APB_map_name) begin
+            case (kind) inside
+                UVM_PREDICT_READ: begin
+                    `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] has no effect. value: 0x%x previous: 0x%x", kind, value, previous), UVM_FULL)
+                end
+                UVM_PREDICT_WRITE: begin
+                    if (rm.CPTRA_FUSE_WR_DONE.done.get_mirrored_value()) begin
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict blocked write attempt to field %s due to CPTRA_FUSE_WR_DONE. value: 0x%x previous: 0x%x", fld.get_full_name(), value, previous), UVM_LOW)
+                        value = previous;
+                    end
+                    else begin
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] has no effect. value: 0x%x previous: 0x%x", kind, value, previous), UVM_FULL)
+                    end
+                end
+                default: begin
+                    `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] has no effect", kind), UVM_FULL)
+                end
+            endcase
+        end
+        else begin
+            `uvm_error("SOC_IFC_REG_CBS", "post_predict called through unsupported reg map!")
+        end
+    endfunction
+
+endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_soc_ifc_reg_internal.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_soc_ifc_reg_internal.svh
new file mode 100644
index 000000000..4dcdc22ed
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_soc_ifc_reg_internal.svh
@@ -0,0 +1,70 @@
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//----------------------------------------------------------------------
+
+// General callback that implements the swwel=soc_req behavior for "internal" registers
+class soc_ifc_reg_cbs_soc_ifc_reg_internal extends uvm_reg_cbs;
+
+    `uvm_object_utils(soc_ifc_reg_cbs_soc_ifc_reg_internal)
+
+    string AHB_map_name = "soc_ifc_AHB_map";
+    string APB_map_name = "soc_ifc_APB_map";
+    
+    uvm_queue #(soc_ifc_reg_delay_job) delay_jobs;
+
+    function new(string name = "uvm_reg_cbs");
+        super.new(name);
+        if (!uvm_config_db#(uvm_queue#(soc_ifc_reg_delay_job))::get(null, "soc_ifc_reg_model_top", "delay_jobs", delay_jobs))
+            `uvm_error("SOC_IFC_REG_CBS", "Failed to get handle for 'delay_jobs' queue from config database!")
+    endfunction
+
+    // Function: post_predict
+    //
+    // Called by the <uvm_reg_field::predict()> method
+    // after a successful UVM_PREDICT_READ or UVM_PREDICT_WRITE prediction.
+    //
+    // ~previous~ is the previous value in the mirror and
+    // ~value~ is the latest predicted value. Any change to ~value~ will
+    // modify the predicted mirror value.
+    //
+    virtual function void post_predict(input uvm_reg_field  fld,
+                                       input uvm_reg_data_t previous,
+                                       inout uvm_reg_data_t value,
+                                       input uvm_predict_e  kind,
+                                       input uvm_path_e     path,
+                                       input uvm_reg_map    map);
+        soc_ifc_reg_ext rm; /* soc_ifc_reg_rm */
+        uvm_reg_block blk = fld.get_parent().get_parent(); /* soc_ifc_reg_rm */
+        if (!$cast(rm,blk)) `uvm_fatal ("SOC_IFC_REG_CBS", "Failed to get valid class handle")
+        if (map.get_name() == this.AHB_map_name) begin
+            `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] on map [%s] has no effect on internal register field %s", kind, map.get_name(), fld.get_full_name()), UVM_FULL)
+        end
+        else if (map.get_name() == this.APB_map_name) begin
+            case (kind) inside
+                UVM_PREDICT_WRITE: begin
+                    `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict blocked write attempt to internal reg field %s on map %s. value: 0x%x previous: 0x%x", fld.get_full_name(), map.get_name(), value, previous), UVM_LOW)
+                    value = previous;
+                end
+                default: begin
+                    `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] on map [%s] has no effect on internal register field %s. value: 0x%x previous: 0x%x", kind, map.get_name(), fld.get_full_name(), value, previous), UVM_FULL)
+                end
+            endcase
+        end
+        else begin
+            `uvm_error("SOC_IFC_REG_CBS", {"post_predict called through unsupported reg map! ", map.get_name()})
+        end
+    endfunction
+
+endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_soc_ifc_reg_internal_fw_update_reset.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_soc_ifc_reg_internal_fw_update_reset.svh
new file mode 100644
index 000000000..71d04dbff
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_soc_ifc_reg_internal_fw_update_reset.svh
@@ -0,0 +1,179 @@
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//----------------------------------------------------------------------
+
+// Reg predictions that will be scheduled on AHB write to internal_fw_update_reset
+class soc_ifc_reg_delay_job_soc_ifc_reg_internal_fw_update_reset_core_rst extends soc_ifc_reg_delay_job;
+    `uvm_object_utils( soc_ifc_reg_delay_job_soc_ifc_reg_internal_fw_update_reset_core_rst )
+    soc_ifc_reg_ext rm; /* soc_ifc_reg_rm */
+    uvm_reg_block rm_top;
+    uvm_reg_map map;
+    bit iccm_unlock = 1'b0;
+    bit fsm_done_to_rst = 1'b0;
+    bit fsm_rst_to_wait = 1'b0;
+    bit fsm_wait_to_done = 1'b0;
+
+    virtual task do_job();
+        `uvm_info("SOC_IFC_REG_DELAY_JOB", "Running delayed job for soc_ifc_reg.internal_fw_update_reset.core_rst", UVM_LOW)
+        rm_top = rm.get_parent();
+        `uvm_info("SOC_IFC_REG_CBS", $sformatf("iccm_lock value 0x%x, boot FSM tracker: [%p]", rm.internal_iccm_lock.lock.get_mirrored_value(), rm.boot_fn_state_sigs), UVM_LOW)
+        if (fsm_done_to_rst) begin
+            rm.boot_fn_state_sigs = '{boot_fw_rst: 1'b1, default: 1'b0};
+            `uvm_info("SOC_IFC_REG_CBS", $sformatf("iccm_lock value 0x%x, boot FSM tracker: [%p]", rm.internal_iccm_lock.lock.get_mirrored_value(), rm.boot_fn_state_sigs), UVM_LOW)
+        end
+        else if (fsm_rst_to_wait && rm.boot_fn_state_sigs.boot_fw_rst) begin
+            rm.boot_fn_state_sigs = '{boot_wait: 1'b1, default: 1'b0};
+            `uvm_info("SOC_IFC_REG_CBS", $sformatf("iccm_lock value 0x%x, boot FSM tracker: [%p]", rm.internal_iccm_lock.lock.get_mirrored_value(), rm.boot_fn_state_sigs), UVM_LOW)
+            // This delay job should also trigger the assertion of uC reset in the predictor
+        end
+        else if (fsm_wait_to_done && rm.boot_fn_state_sigs.boot_wait) begin
+            rm.boot_fn_state_sigs = '{boot_done: 1'b1, default: 1'b0};
+            `uvm_info("SOC_IFC_REG_CBS", $sformatf("iccm_lock value 0x%x, boot FSM tracker: [%p]", rm.internal_iccm_lock.lock.get_mirrored_value(), rm.boot_fn_state_sigs), UVM_LOW)
+            // This delay job should also trigger the de-assertion of fw_update_rst_window in the predictor
+        end
+        else if (iccm_unlock && rm.boot_fn_state_sigs.boot_done) begin
+            rm.internal_iccm_lock.lock.predict(uvm_reg_data_t'(0));
+            `uvm_info("SOC_IFC_REG_CBS", $sformatf("iccm_lock value 0x%x, boot FSM tracker: [%p]", rm.internal_iccm_lock.lock.get_mirrored_value(), rm.boot_fn_state_sigs), UVM_LOW)
+            // This delay job should also trigger the de-assertion of iccm_lock in the predictor
+        end
+        else if (rm.boot_fn_state_sigs.boot_done) begin
+            `uvm_info("SOC_IFC_REG_CBS", $sformatf("Delay job should trigger uC reset deassertion. iccm_lock value 0x%x, boot FSM tracker: [%p]", rm.internal_iccm_lock.lock.get_mirrored_value(), rm.boot_fn_state_sigs), UVM_LOW)
+            // This delay job should also trigger the de-assertion of uC reset in the predictor
+        end
+        else begin
+            `uvm_error("SOC_IFC_REG_CBS",
+                       $sformatf("Delay job for internal_fw_update_reset_core_rst ran with unexpected options and Boot FSM state! options: [iccm:%0x fwrst:%0x wait:%0x done:%0x] iccm_lock value 0x%x, boot FSM tracker: [%p]",
+                                 iccm_unlock     ,
+                                 fsm_done_to_rst ,
+                                 fsm_rst_to_wait ,
+                                 fsm_wait_to_done,
+                                 rm.internal_iccm_lock.lock.get_mirrored_value(),
+                                 rm.boot_fn_state_sigs))
+        end
+    endtask
+endclass
+
+// Callback for fw update reset register
+class soc_ifc_reg_cbs_soc_ifc_reg_internal_fw_update_reset extends soc_ifc_reg_cbs_soc_ifc_reg_internal;
+
+    `uvm_object_utils(soc_ifc_reg_cbs_soc_ifc_reg_internal_fw_update_reset)
+
+    string AHB_map_name = "soc_ifc_AHB_map";
+    string APB_map_name = "soc_ifc_APB_map";
+
+    // Function: post_predict
+    //
+    // Called by the <uvm_reg_field::predict()> method
+    // after a successful UVM_PREDICT_READ or UVM_PREDICT_WRITE prediction.
+    //
+    // ~previous~ is the previous value in the mirror and
+    // ~value~ is the latest predicted value. Any change to ~value~ will
+    // modify the predicted mirror value.
+    //
+    virtual function void post_predict(input uvm_reg_field  fld,
+                                       input uvm_reg_data_t previous,
+                                       inout uvm_reg_data_t value,
+                                       input uvm_predict_e  kind,
+                                       input uvm_path_e     path,
+                                       input uvm_reg_map    map);
+
+        soc_ifc_reg_delay_job_soc_ifc_reg_internal_fw_update_reset_core_rst delay_job_boot_fsm_fwrst;
+        soc_ifc_reg_delay_job_soc_ifc_reg_internal_fw_update_reset_core_rst delay_job_boot_fsm_wait;
+        soc_ifc_reg_delay_job_soc_ifc_reg_internal_fw_update_reset_core_rst delay_job_rst_window;
+        soc_ifc_reg_delay_job_soc_ifc_reg_internal_fw_update_reset_core_rst delay_job_iccm_unlock;
+        soc_ifc_reg_delay_job_soc_ifc_reg_internal_fw_update_reset_core_rst delay_job_uc_rst;
+        soc_ifc_reg_ext rm; /* soc_ifc_reg_rm */
+        uvm_reg_block blk = fld.get_parent().get_parent(); /* soc_ifc_reg_rm */
+        if (!$cast(rm,blk)) `uvm_fatal ("SOC_IFC_REG_CBS", "Failed to get valid class handle")
+
+        delay_job_boot_fsm_fwrst = soc_ifc_reg_delay_job_soc_ifc_reg_internal_fw_update_reset_core_rst::type_id::create("delay_job_boot_fsm_fwrst");
+        delay_job_boot_fsm_fwrst.rm = rm;
+        delay_job_boot_fsm_fwrst.map = map;
+        delay_job_boot_fsm_fwrst.fsm_done_to_rst = 1;
+        delay_job_boot_fsm_fwrst.set_delay_cycles(0); // transition to state boot_fw_rst occurs 1 clock after the reg write
+
+        delay_job_boot_fsm_wait = soc_ifc_reg_delay_job_soc_ifc_reg_internal_fw_update_reset_core_rst::type_id::create("delay_job_boot_fsm_wait");
+        delay_job_boot_fsm_wait.rm = rm;
+        delay_job_boot_fsm_wait.map = map;
+        delay_job_boot_fsm_wait.fsm_rst_to_wait = 1;
+        delay_job_boot_fsm_wait.set_delay_cycles(delay_job_boot_fsm_fwrst.get_delay_cycles() + 2); //transition to state boot_wait (and uC reset assertion) occurs 2 clocks after the boot_fw_rst state
+
+        delay_job_rst_window = soc_ifc_reg_delay_job_soc_ifc_reg_internal_fw_update_reset_core_rst::type_id::create("delay_job_rst_window");
+        delay_job_rst_window.rm = rm;
+        delay_job_rst_window.map = map;
+        delay_job_rst_window.fsm_wait_to_done = 1;
+        delay_job_rst_window.set_delay_cycles(delay_job_boot_fsm_wait.get_delay_cycles()+1+rm.internal_fw_update_reset_wait_cycles.wait_cycles.get_mirrored_value()); //calculate total delay until transition to state boot_done and deassertion of fw_update_rst_window
+
+        delay_job_iccm_unlock = soc_ifc_reg_delay_job_soc_ifc_reg_internal_fw_update_reset_core_rst::type_id::create("delay_job_iccm_unlock");
+        delay_job_iccm_unlock.rm = rm;
+        delay_job_iccm_unlock.map = map;
+        delay_job_iccm_unlock.iccm_unlock = 1;
+        delay_job_iccm_unlock.set_delay_cycles(delay_job_rst_window.get_delay_cycles()+1); //this iccm unlock comes 1 clock after state transition
+
+        delay_job_uc_rst = soc_ifc_reg_delay_job_soc_ifc_reg_internal_fw_update_reset_core_rst::type_id::create("delay_job_uc_rst");
+        delay_job_uc_rst.rm = rm;
+        delay_job_uc_rst.map = map;
+        delay_job_uc_rst.set_delay_cycles(delay_job_iccm_unlock.get_delay_cycles()+1); // Deassertion of uC reset is the last event triggered by this reg access
+
+        if (map.get_name() == this.AHB_map_name) begin
+            case (kind) inside
+                UVM_PREDICT_WRITE: begin
+                    if (value & !previous) begin
+                        //push a job to catch transition to boot_fw_rst state 1 clock later
+                        delay_jobs.push_back(delay_job_boot_fsm_fwrst);
+                        //push a job to catch transition to boot_wait state and assertion of uC reset 1 clock later
+                        delay_jobs.push_back(delay_job_boot_fsm_wait);
+                        //push another job to catch de-assertion of fw_update_rst_window on state transition to boot_done
+                        delay_jobs.push_back(delay_job_rst_window);
+                        //push a delayed job for de-assertion of iccm lock 1 clock later
+                        delay_jobs.push_back(delay_job_iccm_unlock);
+                        //push another job to catch de-assertion of reset 1 clock later
+                        delay_jobs.push_back(delay_job_uc_rst);
+                        `uvm_info("SOC_IFC_REG_CBS",
+                                  $sformatf("Sending 5 delay jobs for internal register field %s with clk delays: [%0d] [%0d] [%0d] [%0d] [%0d]",
+                                            fld.get_full_name(),
+                                            delay_job_boot_fsm_fwrst.get_delay_cycles(),
+                                            delay_job_boot_fsm_wait.get_delay_cycles(),
+                                            delay_job_rst_window.get_delay_cycles(),
+                                            delay_job_iccm_unlock.get_delay_cycles(),
+                                            delay_job_uc_rst.get_delay_cycles()),
+                                  UVM_LOW)
+                    end else begin
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] on map [%s] has no effect on internal register field %s", kind, map.get_name(), fld.get_full_name()), UVM_FULL)
+                    end
+                end
+                default: begin
+                    `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] on map [%s] has no effect on internal register field %s", kind, map.get_name(), fld.get_full_name()), UVM_FULL)
+        
+                end
+            endcase
+        end
+        else if (map.get_name() == this.APB_map_name) begin
+            case (kind) inside
+                UVM_PREDICT_WRITE: begin
+                    `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict blocked write attempt to internal reg field %s on map %s. value: 0x%x previous: 0x%x", fld.get_full_name(), map.get_name(), value, previous), UVM_LOW)
+                    value = previous;
+                end
+                default: begin
+                    `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] on map [%s] has no effect on internal register field %s. value: 0x%x previous: 0x%x", kind, map.get_name(), fld.get_full_name(), value, previous), UVM_FULL)
+                end
+            endcase
+        end
+        else begin
+            `uvm_error("SOC_IFC_REG_CBS", {"post_predict called through unsupported reg map! ", map.get_name()})
+        end
+    endfunction
+
+endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_soc_ifc_reg_key.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_soc_ifc_reg_key.svh
new file mode 100644
index 000000000..c981cba52
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_soc_ifc_reg_key.svh
@@ -0,0 +1,62 @@
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//----------------------------------------------------------------------
+
+class soc_ifc_reg_cbs_soc_ifc_reg_key extends uvm_reg_cbs;
+
+    `uvm_object_utils(soc_ifc_reg_cbs_soc_ifc_reg_key)
+
+    string AHB_map_name = "soc_ifc_AHB_map";
+    string APB_map_name = "soc_ifc_APB_map";
+
+    // Function: post_predict
+    //
+    // Called by the <uvm_reg_field::predict()> method
+    // after a successful UVM_PREDICT_READ or UVM_PREDICT_WRITE prediction.
+    //
+    // ~previous~ is the previous value in the mirror and
+    // ~value~ is the latest predicted value. Any change to ~value~ will
+    // modify the predicted mirror value.
+    //
+    virtual function void post_predict(input uvm_reg_field  fld,
+                                       input uvm_reg_data_t previous,
+                                       inout uvm_reg_data_t value,
+                                       input uvm_predict_e  kind,
+                                       input uvm_path_e     path,
+                                       input uvm_reg_map    map);
+        soc_ifc_reg_ext rm; /* soc_ifc_reg_rm */
+        uvm_reg_block blk = fld.get_parent().get_parent(); /* soc_ifc_reg_rm */
+        if (!$cast(rm,blk)) `uvm_fatal ("SOC_IFC_REG_CBS", "Failed to get valid class handle")
+        if (map.get_name() == this.AHB_map_name ||
+            map.get_name() == this.APB_map_name) begin
+            case (kind) inside
+                UVM_PREDICT_READ: begin
+                    `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] has no effect. value: 0x%x previous: 0x%x", kind, value, previous), UVM_FULL)
+                end
+                UVM_PREDICT_WRITE: begin
+                    `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict blocked write attempt to field %s since it is an unwritable key. value: 0x%x previous: 0x%x", fld.get_full_name(), value, previous), UVM_LOW)
+                    value = previous;
+                end
+                default: begin
+                    `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] has no effect", kind), UVM_FULL)
+                end
+            endcase
+        end
+        else begin
+            `uvm_error("SOC_IFC_REG_CBS", "post_predict called through unsupported reg map!")
+        end
+    endfunction
+
+endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_soc_ifc_reg_secret.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_soc_ifc_reg_secret.svh
new file mode 100644
index 000000000..8a72664cc
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_soc_ifc_reg_secret.svh
@@ -0,0 +1,67 @@
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//----------------------------------------------------------------------
+
+class soc_ifc_reg_cbs_soc_ifc_reg_secret extends uvm_reg_cbs;
+
+    `uvm_object_utils(soc_ifc_reg_cbs_soc_ifc_reg_secret)
+
+    string AHB_map_name = "soc_ifc_AHB_map";
+    string APB_map_name = "soc_ifc_APB_map";
+
+    // Function: post_predict
+    //
+    // Called by the <uvm_reg_field::predict()> method
+    // after a successful UVM_PREDICT_READ or UVM_PREDICT_WRITE prediction.
+    //
+    // ~previous~ is the previous value in the mirror and
+    // ~value~ is the latest predicted value. Any change to ~value~ will
+    // modify the predicted mirror value.
+    //
+    virtual function void post_predict(input uvm_reg_field  fld,
+                                       input uvm_reg_data_t previous,
+                                       inout uvm_reg_data_t value,
+                                       input uvm_predict_e  kind,
+                                       input uvm_path_e     path,
+                                       input uvm_reg_map    map);
+        soc_ifc_reg_ext rm; /* soc_ifc_reg_rm */
+        uvm_reg_block blk = fld.get_parent().get_parent(); /* soc_ifc_reg_rm */
+        if (!$cast(rm,blk)) `uvm_fatal ("SOC_IFC_REG_CBS", "Failed to get valid class handle")
+        if (map.get_name() == this.AHB_map_name ||
+            map.get_name() == this.APB_map_name) begin
+            case (kind) inside
+                UVM_PREDICT_READ: begin
+                    `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] has no effect. value: 0x%x previous: 0x%x", kind, value, previous), UVM_FULL)
+                end
+                UVM_PREDICT_WRITE: begin
+                    if (rm.CPTRA_FUSE_WR_DONE.done.get_mirrored_value()) begin
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict blocked write attempt to field %s due to CPTRA_FUSE_WR_DONE. value: 0x%x previous: 0x%x", fld.get_full_name(), value, previous), UVM_LOW)
+                        value = previous;
+                    end
+                    else begin
+                        `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] has no effect. value: 0x%x previous: 0x%x", kind, value, previous), UVM_FULL)
+                    end
+                end
+                default: begin
+                    `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called with kind [%p] has no effect", kind), UVM_FULL)
+                end
+            endcase
+        end
+        else begin
+            `uvm_error("SOC_IFC_REG_CBS", "post_predict called through unsupported reg map!")
+        end
+    endfunction
+
+endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_delay_job.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_delay_job.svh
index 9d2c35010..79b0ef63c 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_delay_job.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_delay_job.svh
@@ -28,6 +28,7 @@ class soc_ifc_reg_delay_job extends uvm_object;
 
     `uvm_object_utils( soc_ifc_reg_delay_job )
 
+    // 0's based value (1-cycle delay minimum imposed in soc_ifc_predictor)
     int unsigned delay_cycles = 0;
 
     virtual function void set_delay_cycles(int unsigned value);
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_delay_job_intr_block_rf_ext.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_delay_job_intr_block_rf_ext.svh
new file mode 100644
index 000000000..bc8f55aaf
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_delay_job_intr_block_rf_ext.svh
@@ -0,0 +1,85 @@
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//----------------------------------------------------------------------
+
+// Reg predictions that will be scheduled on value change in notif_internal_intr_r
+class soc_ifc_reg_delay_job_intr_block_rf_ext extends soc_ifc_reg_delay_job;
+    `uvm_object_utils( soc_ifc_reg_delay_job_intr_block_rf_ext )
+
+    uvm_reg_field req_fld; /* used to report the reg field that caused the delay job */
+    uvm_reg       sts_reg;
+    uvm_reg       en_reg ;
+    uvm_reg_field en_glb ;
+    uvm_reg_field sts_glb;
+    uvm_reg_map map;
+
+    uvm_reg_data_t val_sts_reg;
+    uvm_reg_data_t val_en_reg ;
+    uvm_reg_data_t val_en_glb ;
+    uvm_reg_data_t val_sts_glb;
+
+    virtual function void grab_values();
+        fork
+            begin
+            // Wait for all predictor callbacks to run for every intr bit accessed
+            // during the current clock cycle, so mirrors are up to date
+            uvm_wait_for_nba_region();
+            // Snapshot of current value, since next cycle may see value changes again
+            val_sts_reg = sts_reg.get_mirrored_value();
+            val_en_reg  = en_reg .get_mirrored_value();
+            val_en_glb  = en_glb .get_mirrored_value();
+            val_sts_glb = sts_glb.get_mirrored_value();
+            end
+        join_none
+    endfunction
+
+    virtual task do_job();
+        `uvm_info("SOC_IFC_REG_DELAY_JOB", $sformatf("Running delayed job for %s", req_fld.get_full_name()), UVM_MEDIUM)
+        if (!/*val_sts_glb*/sts_glb.get_mirrored_value() && |(val_sts_reg/*sts_reg.get_mirrored_value()*/ & val_en_reg/*en_reg.get_mirrored_value()*/) /*&& val_en_glb / * en_glb.get_mirrored_value()*/) begin
+            sts_glb.predict(1'b1);
+            `uvm_info("SOC_IFC_REG_DELAY_JOB",
+                      $sformatf("post_predict called through map [%p] on %s results in interrupt status bit being set to 0x%0x. Values: en_reg(latched) [0x%0x(0x%0x)] sts_reg [0x%0x(0x%0x)] en_glb [0x%0x(0x%0x)] sts_glb [0x%0x(0x%0x)]",
+                                map.get_name(), req_fld.get_full_name(), sts_glb.get_mirrored_value(),
+                                en_reg.get_mirrored_value(),  val_en_reg ,
+                                sts_reg.get_mirrored_value(), val_sts_reg,
+                                en_glb.get_mirrored_value(),  val_en_glb ,
+                                sts_glb.get_mirrored_value(), val_sts_glb),
+                      UVM_MEDIUM)
+        end
+        else if (/*val_sts_glb*/sts_glb.get_mirrored_value() && !(|(val_sts_reg/*sts_reg.get_mirrored_value()*/ & val_en_reg/*en_reg.get_mirrored_value()*/) /*&& val_en_glb / * en_glb.get_mirrored_value()*/)) begin
+            sts_glb.predict(1'b0);
+            `uvm_info("SOC_IFC_REG_DELAY_JOB",
+                      $sformatf("post_predict called through map [%p] on %s results in interrupt status bit being cleared to 0x%0x. Values: en_reg(latched) [0x%0x(0x%0x)] sts_reg [0x%0x(0x%0x)] en_glb [0x%0x(0x%0x)] sts_glb [0x%0x(0x%0x)]",
+                                map.get_name(), req_fld.get_full_name(), sts_glb.get_mirrored_value(),
+                                en_reg.get_mirrored_value(),  val_en_reg ,
+                                sts_reg.get_mirrored_value(), val_sts_reg,
+                                en_glb.get_mirrored_value(),  val_en_glb ,
+                                sts_glb.get_mirrored_value(), val_sts_glb),
+                      UVM_MEDIUM)
+        end
+        else begin
+            `uvm_info("SOC_IFC_REG_DELAY_JOB",
+                      $sformatf("Delay job for %s does not predict any changes due to: en_reg(latched) [0x%0x(0x%0x)] sts_reg [0x%0x(0x%0x)] en_glb [0x%0x(0x%0x)] sts_glb [0x%0x(0x%0x)]",
+                                req_fld.get_full_name(),
+                                en_reg.get_mirrored_value(),  val_en_reg ,
+                                sts_reg.get_mirrored_value(), val_sts_reg,
+                                en_glb.get_mirrored_value(),  val_en_glb ,
+                                sts_glb.get_mirrored_value(), val_sts_glb),
+                      UVM_HIGH)
+        end
+    endtask
+endclass
+
+
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_delay_job_mbox_csr_mbox_prot_error.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_delay_job_mbox_csr_mbox_prot_error.svh
new file mode 100644
index 000000000..bd57d181e
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_delay_job_mbox_csr_mbox_prot_error.svh
@@ -0,0 +1,63 @@
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//----------------------------------------------------------------------
+
+// Reg predictions that will be scheduled on any invalid access to trigger errors
+class soc_ifc_reg_delay_job_mbox_csr_mbox_prot_error extends soc_ifc_reg_delay_job;
+    `uvm_object_utils( soc_ifc_reg_delay_job_mbox_csr_mbox_prot_error )
+    mbox_csr_ext rm; /* mbox_csr_rm */
+    uvm_reg_field fld;
+    mbox_fsm_state_e state_nxt;
+    uvm_reg_map map;
+    mbox_protocol_error_t error = '{default: 1'b0};
+    virtual task do_job();
+        if (fld == null || map == null || rm == null)
+            `uvm_fatal("SOC_IFC_REG_DELAY_JOB", "Missing handle for fld, map, or rm")
+
+        `uvm_info("SOC_IFC_REG_DELAY_JOB", "Running delayed job for mbox_csr due to detected protocol error", UVM_HIGH)
+        if (error.axs_without_lock && (rm.mbox_lock.lock.get_mirrored_value() || !rm.mbox_fn_state_sigs.mbox_idle)) begin
+            `uvm_fatal("SOC_IFC_REG_DELAY_JOB", "no_lock mbox error while mbox is locked or not-idle! This shouldn't happen and I haven't thought of how to deal with this yet! FIXME!")
+        end
+        else if (error.axs_without_lock) begin
+            uvm_reg_block top;
+            uvm_reg_field intr_fld;
+            uvm_reg_field non_fatal_fld;
+
+            top           = rm.get_parent();
+            intr_fld      = top.get_block_by_name("soc_ifc_reg_rm").get_block_by_name("intr_block_rf_ext").get_field_by_name("error_cmd_fail_sts");
+            non_fatal_fld = top.get_block_by_name("soc_ifc_reg_rm").get_reg_by_name("CPTRA_HW_ERROR_NON_FATAL").get_field_by_name("mbox_prot_no_lock");
+
+            intr_fld     .predict(1'b1, .kind(UVM_PREDICT_READ), .path(UVM_PREDICT), .map(map.get_parent().get_map_by_name("soc_ifc_AHB_map")));
+            non_fatal_fld.predict(1'b1, .kind(UVM_PREDICT_READ), .path(UVM_PREDICT), .map(map));
+
+            `uvm_info("SOC_IFC_REG_DELAY_JOB", $sformatf("delay_job scheduled for access through map [%p] on [%s] results in Access Without Lock Error, and no state change. Functional state tracker: [%p] mbox_fsm_ps transition (ignored) [%p]", map.get_name(), fld.get_full_name(), rm.mbox_fn_state_sigs, state_nxt), UVM_FULL)
+        end
+        else if (error.axs_incorrect_order && rm.mbox_lock.lock.get_mirrored_value() && !rm.mbox_unlock.unlock.get_mirrored_value()) begin
+            uvm_reg_block top;
+            uvm_reg_field intr_fld;
+            uvm_reg_field non_fatal_fld;
+
+            top           = rm.get_parent();
+            intr_fld      = top.get_block_by_name("soc_ifc_reg_rm").get_block_by_name("intr_block_rf_ext").get_field_by_name("error_cmd_fail_sts");
+            non_fatal_fld = top.get_block_by_name("soc_ifc_reg_rm").get_reg_by_name("CPTRA_HW_ERROR_NON_FATAL").get_field_by_name("mbox_prot_ooo");
+
+            intr_fld     .predict(1'b1, .kind(UVM_PREDICT_READ), .path(UVM_PREDICT), .map(map.get_parent().get_map_by_name("soc_ifc_AHB_map")));
+            non_fatal_fld.predict(1'b1, .kind(UVM_PREDICT_READ), .path(UVM_PREDICT), .map(map));
+
+            rm.mbox_status.mbox_fsm_ps.predict(state_nxt, .kind(UVM_PREDICT_READ), .path(UVM_PREDICT), .map(map));
+            `uvm_info("SOC_IFC_REG_DELAY_JOB", $sformatf("delay_job scheduled for access through map [%p] on [%s] results in state transition. Functional state tracker: [%p] mbox_fsm_ps transition [%p]", map.get_name(), fld.get_full_name(), rm.mbox_fn_state_sigs, state_nxt), UVM_FULL)
+        end
+    endtask
+endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_model_top_pkg.sv b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_model_top_pkg.sv
index 57f4ef900..ed868206a 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_model_top_pkg.sv
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_model_top_pkg.sv
@@ -49,14 +49,27 @@ package soc_ifc_reg_model_top_pkg;
                               apb5_master_0_params::APB3_PWDATA_BIT_WIDTH,
                               apb5_master_0_params::APB3_PRDATA_BIT_WIDTH) apb_reg_adapter_t;
 
+    typedef struct packed {
+        bit boot_idle;
+        bit boot_fuse;
+        bit boot_fw_rst;
+        bit boot_wait;
+        bit boot_done;
+    } boot_fn_state_s;
+
     typedef struct packed {
         bit mbox_idle;
-        bit uc_send_stage;
+        bit uc_cmd_stage;
+        bit uc_dlen_stage;
+        bit uc_data_stage;
         bit uc_receive_stage;
         bit uc_done_stage;
-        bit soc_send_stage;
+        bit soc_cmd_stage;
+        bit soc_dlen_stage;
+        bit soc_data_stage;
         bit soc_receive_stage;
         bit soc_done_stage;
+        bit mbox_error;
     } mbox_fn_state_s;
 
 // pragma uvmf custom additional_imports end
@@ -65,50 +78,120 @@ package soc_ifc_reg_model_top_pkg;
 
    /* DEFINE REGISTER CLASSES */
 // pragma uvmf custom define_register_classes begin
+
+    // These macros are used to copy the "HARD" reset value to a new reset type, "NONCORE",
+    // and then track the configuration of the provided register.
+    // When called, these macros expect that a queue has already been created called "blk_flds".
+    // The queue tracks all extant registers within the enclosing uvm_reg_block.
+    // This macro removes from that queue the uvm_reg_field that was provided as an arguement.
+    // This allows the calling context to check that the queue of blk_flds is empty at the end,
+    // and thus enforce that a custom reset configuration is defined for all register fields.
+    // The "NO_CP" macros do not create a "NONCORE" reset type (e.g for regs on pwrgood domain)
+    // but they still remove the field from the check to confirm that a reset
+    // configuration has been assigned.
+    `define FLD_DO_CP_NONCORE_RST(fld_h) begin                   \
+        if (fld_h.has_reset("HARD"))                             \
+            fld_h.set_reset(fld_h.get_reset("HARD"), "NONCORE"); \
+    end
+    `define REG____CP_NONCORE_RST(reg_h) begin                                 \
+        uvm_reg_field reg_flds[$];                                             \
+        reg_h.get_fields(reg_flds);                                            \
+        foreach (reg_flds[ii]) begin                                           \
+            int del_idx[$];                                                    \
+            `FLD_DO_CP_NONCORE_RST(reg_flds[ii])                               \
+            del_idx = blk_flds.find_first_index(fl) with (fl == reg_flds[ii]); \
+            blk_flds.delete(del_idx.pop_front());                              \
+        end                                                                    \
+    end
+    `define REG_NO_CP_NONCORE_RST(reg_h) begin                                 \
+        uvm_reg_field reg_flds[$];                                             \
+        reg_h.get_fields(reg_flds);                                            \
+        foreach (reg_flds[ii]) begin                                           \
+            int del_idx[$];                                                    \
+            del_idx = blk_flds.find_first_index(fl) with (fl == reg_flds[ii]); \
+            blk_flds.delete(del_idx.pop_front());                              \
+        end                                                                    \
+    end
+    `define FLD____CP_NONCORE_RST(fld_h) begin                              \
+        int del_idx[$];                                                     \
+        `FLD_DO_CP_NONCORE_RST(fld_h)                                       \
+        del_idx = blk_flds.find_first_index(fl) with (fl == fld_h);         \
+        blk_flds.delete(del_idx.pop_front());                               \
+    end
+    `define FLD_NO_CP_NONCORE_RST(fld_h) begin                              \
+        int del_idx[$];                                                     \
+        del_idx = blk_flds.find_first_index(fl) with (fl == fld_h);         \
+        blk_flds.delete(del_idx.pop_front());                               \
+    end
+    // ------------------ END of reset config macros ------------------ //
+
     class soc_ifc_reg__intr_block_t_ext extends soc_ifc_reg__intr_block_t;
         uvm_reg_map soc_ifc_reg_intr_AHB_map;
         uvm_reg_map soc_ifc_reg_intr_APB_map;
 
+        // HWSET has precedence over SW W1C, so use these variables to track
+        // active hwset activity in case contention must be resolved
+        bit [31:0] notif_internal_intr_r_hwset_active = 0;
+        bit [31:0] error_internal_intr_r_hwset_active = 0;
+
         function new(string name = "soc_ifc_reg__intr_block_t_ext");
             super.new(name);
         endfunction : new
 
         // FIXME Manually maintaining a list here of registers that are configured
         //       as soft-resettable (i.e. cptra_rst_b instead of cptra_pwrgood)
+        //       or noncore-resettable (i.e. cptra_noncore_rst_b instead of cptra_pwrgood)
         //       Ideally would be auto-generated.
-        virtual function void set_soft_reset_values();
-            if ( this.global_intr_en_r                      .has_reset("HARD"   )) this.global_intr_en_r                      .set_reset(this.global_intr_en_r                    .get_reset("HARD"), "SOFT");
-            if ( this.error_intr_en_r                       .has_reset("HARD"   )) this.error_intr_en_r                       .set_reset(this.error_intr_en_r                     .get_reset("HARD"), "SOFT");
-            if ( this.notif_intr_en_r                       .has_reset("HARD"   )) this.notif_intr_en_r                       .set_reset(this.notif_intr_en_r                     .get_reset("HARD"), "SOFT");
-            if ( this.error_global_intr_r                   .has_reset("HARD"   )) this.error_global_intr_r                   .set_reset(this.error_global_intr_r                 .get_reset("HARD"), "SOFT");
-            if ( this.notif_global_intr_r                   .has_reset("HARD"   )) this.notif_global_intr_r                   .set_reset(this.notif_global_intr_r                 .get_reset("HARD"), "SOFT");
-//            this.error_internal_intr_r                 .set_reset(this.error_internal_intr_r               .get_reset("HARD"), "SOFT");
-            if ( this.notif_internal_intr_r                 .has_reset("HARD"   )) this.notif_internal_intr_r                 .set_reset(this.notif_internal_intr_r               .get_reset("HARD"), "SOFT");
-            if ( this.error_intr_trig_r                     .has_reset("HARD"   )) this.error_intr_trig_r                     .set_reset(this.error_intr_trig_r                   .get_reset("HARD"), "SOFT");
-            if ( this.notif_intr_trig_r                     .has_reset("HARD"   )) this.notif_intr_trig_r                     .set_reset(this.notif_intr_trig_r                   .get_reset("HARD"), "SOFT");
-//            if ( this.error_internal_intr_count_r           .has_reset("HARD"   )) this.error_internal_intr_count_r           .set_reset(this.error_internal_intr_count_r         .get_reset("HARD"), "SOFT");
-//            if ( this.error_inv_dev_intr_count_r            .has_reset("HARD"   )) this.error_inv_dev_intr_count_r            .set_reset(this.error_inv_dev_intr_count_r          .get_reset("HARD"), "SOFT");
-//            if ( this.error_cmd_fail_intr_count_r           .has_reset("HARD"   )) this.error_cmd_fail_intr_count_r           .set_reset(this.error_cmd_fail_intr_count_r         .get_reset("HARD"), "SOFT");
-//            if ( this.error_bad_fuse_intr_count_r           .has_reset("HARD"   )) this.error_bad_fuse_intr_count_r           .set_reset(this.error_bad_fuse_intr_count_r         .get_reset("HARD"), "SOFT");
-//            if ( this.error_iccm_blocked_intr_count_r       .has_reset("HARD"   )) this.error_iccm_blocked_intr_count_r       .set_reset(this.error_iccm_blocked_intr_count_r     .get_reset("HARD"), "SOFT");
-//            if ( this.error_mbox_ecc_unc_intr_count_r       .has_reset("HARD"   )) this.error_mbox_ecc_unc_intr_count_r       .set_reset(this.error_mbox_ecc_unc_intr_count_r     .get_reset("HARD"), "SOFT");
-            if ( this.notif_cmd_avail_intr_count_r          .has_reset("HARD"   )) this.notif_cmd_avail_intr_count_r          .set_reset(this.notif_cmd_avail_intr_count_r        .get_reset("HARD"), "SOFT");
-            if ( this.notif_mbox_ecc_cor_intr_count_r       .has_reset("HARD"   )) this.notif_mbox_ecc_cor_intr_count_r       .set_reset(this.notif_mbox_ecc_cor_intr_count_r     .get_reset("HARD"), "SOFT");
-            if ( this.notif_debug_locked_intr_count_r       .has_reset("HARD"   )) this.notif_debug_locked_intr_count_r       .set_reset(this.notif_debug_locked_intr_count_r     .get_reset("HARD"), "SOFT");
-            if ( this.error_internal_intr_count_incr_r      .has_reset("HARD"   )) this.error_internal_intr_count_incr_r      .set_reset(this.error_internal_intr_count_incr_r    .get_reset("HARD"), "SOFT");
-            if ( this.error_inv_dev_intr_count_incr_r       .has_reset("HARD"   )) this.error_inv_dev_intr_count_incr_r       .set_reset(this.error_inv_dev_intr_count_incr_r     .get_reset("HARD"), "SOFT");
-            if ( this.error_cmd_fail_intr_count_incr_r      .has_reset("HARD"   )) this.error_cmd_fail_intr_count_incr_r      .set_reset(this.error_cmd_fail_intr_count_incr_r    .get_reset("HARD"), "SOFT");
-            if ( this.error_bad_fuse_intr_count_incr_r      .has_reset("HARD"   )) this.error_bad_fuse_intr_count_incr_r      .set_reset(this.error_bad_fuse_intr_count_incr_r    .get_reset("HARD"), "SOFT");
-            if ( this.error_iccm_blocked_intr_count_incr_r  .has_reset("HARD"   )) this.error_iccm_blocked_intr_count_incr_r  .set_reset(this.error_iccm_blocked_intr_count_incr_r.get_reset("HARD"), "SOFT");
-            if ( this.error_mbox_ecc_unc_intr_count_incr_r  .has_reset("HARD"   )) this.error_mbox_ecc_unc_intr_count_incr_r  .set_reset(this.error_mbox_ecc_unc_intr_count_incr_r.get_reset("HARD"), "SOFT");
-            if ( this.notif_cmd_avail_intr_count_incr_r     .has_reset("HARD"   )) this.notif_cmd_avail_intr_count_incr_r     .set_reset(this.notif_cmd_avail_intr_count_incr_r   .get_reset("HARD"), "SOFT");
-            if ( this.notif_mbox_ecc_cor_intr_count_incr_r  .has_reset("HARD"   )) this.notif_mbox_ecc_cor_intr_count_incr_r  .set_reset(this.notif_mbox_ecc_cor_intr_count_incr_r.get_reset("HARD"), "SOFT");
-            if ( this.notif_debug_locked_intr_count_incr_r  .has_reset("HARD"   )) this.notif_debug_locked_intr_count_incr_r  .set_reset(this.notif_debug_locked_intr_count_incr_r.get_reset("HARD"), "SOFT");
+        virtual function void configure_reset_values();
+            // Track reset configuration against a queue of all registers in this block, to ensure each register is handled
+            uvm_reg_field blk_flds[$];
+            get_fields(blk_flds, UVM_NO_HIER);
+            `REG____CP_NONCORE_RST(this.global_intr_en_r                           )
+            `REG____CP_NONCORE_RST(this.error_intr_en_r                            )
+            `REG____CP_NONCORE_RST(this.notif_intr_en_r                            )
+            `REG____CP_NONCORE_RST(this.error_global_intr_r                        )
+            `REG____CP_NONCORE_RST(this.notif_global_intr_r                        )
+            `REG_NO_CP_NONCORE_RST(this.error_internal_intr_r                      )
+            `REG____CP_NONCORE_RST(this.notif_internal_intr_r                      )
+            `REG____CP_NONCORE_RST(this.error_intr_trig_r                          )
+            `REG____CP_NONCORE_RST(this.notif_intr_trig_r                          )
+            `REG_NO_CP_NONCORE_RST(this.error_internal_intr_count_r                )
+            `REG_NO_CP_NONCORE_RST(this.error_inv_dev_intr_count_r                 )
+            `REG_NO_CP_NONCORE_RST(this.error_cmd_fail_intr_count_r                )
+            `REG_NO_CP_NONCORE_RST(this.error_bad_fuse_intr_count_r                )
+            `REG_NO_CP_NONCORE_RST(this.error_iccm_blocked_intr_count_r            )
+            `REG_NO_CP_NONCORE_RST(this.error_mbox_ecc_unc_intr_count_r            )
+            `REG_NO_CP_NONCORE_RST(this.error_wdt_timer1_timeout_intr_count_r      )
+            `REG_NO_CP_NONCORE_RST(this.error_wdt_timer2_timeout_intr_count_r      )
+            `REG____CP_NONCORE_RST(this.notif_cmd_avail_intr_count_r               )
+            `REG____CP_NONCORE_RST(this.notif_mbox_ecc_cor_intr_count_r            )
+            `REG____CP_NONCORE_RST(this.notif_debug_locked_intr_count_r            )
+            `REG____CP_NONCORE_RST(this.notif_scan_mode_intr_count_r               )
+            `REG____CP_NONCORE_RST(this.notif_soc_req_lock_intr_count_r            )
+            `REG____CP_NONCORE_RST(this.notif_gen_in_toggle_intr_count_r           )
+            `REG____CP_NONCORE_RST(this.error_internal_intr_count_incr_r           )
+            `REG____CP_NONCORE_RST(this.error_inv_dev_intr_count_incr_r            )
+            `REG____CP_NONCORE_RST(this.error_cmd_fail_intr_count_incr_r           )
+            `REG____CP_NONCORE_RST(this.error_bad_fuse_intr_count_incr_r           )
+            `REG____CP_NONCORE_RST(this.error_iccm_blocked_intr_count_incr_r       )
+            `REG____CP_NONCORE_RST(this.error_mbox_ecc_unc_intr_count_incr_r       )
+            `REG____CP_NONCORE_RST(this.error_wdt_timer1_timeout_intr_count_incr_r )
+            `REG____CP_NONCORE_RST(this.error_wdt_timer2_timeout_intr_count_incr_r )
+            `REG____CP_NONCORE_RST(this.notif_cmd_avail_intr_count_incr_r          )
+            `REG____CP_NONCORE_RST(this.notif_mbox_ecc_cor_intr_count_incr_r       )
+            `REG____CP_NONCORE_RST(this.notif_debug_locked_intr_count_incr_r       )
+            `REG____CP_NONCORE_RST(this.notif_scan_mode_intr_count_incr_r          )
+            `REG____CP_NONCORE_RST(this.notif_soc_req_lock_intr_count_incr_r       )
+            `REG____CP_NONCORE_RST(this.notif_gen_in_toggle_intr_count_incr_r      )
+            while (blk_flds.size() != 0) begin
+                uvm_reg_field cur_fld = blk_flds.pop_front();
+                `uvm_error("SOC_IFC_REG__INTR_BLOCK_T_EXT", {"No extended reset configuration defined for ", cur_fld.get_full_name()})
+            end
         endfunction
 
         virtual function void build();
             super.build();
-            this.set_soft_reset_values();
+            this.configure_reset_values();
             this.soc_ifc_reg_intr_AHB_map = create_map("intr_AHB_reg_map", 0, 4, UVM_LITTLE_ENDIAN);
             this.soc_ifc_reg_intr_APB_map = create_map("intr_APB_reg_map", 0, 4, UVM_LITTLE_ENDIAN);
         endfunction
@@ -141,93 +224,113 @@ package soc_ifc_reg_model_top_pkg;
         // should never be used in practice
         rand soc_ifc_reg__intr_block_t_ext intr_block_rf_ext;
 
+        // Tracks functional state of Boot FSM internally, without reference to
+        // the value read from CPTRA_FLOW_STATUS
+        boot_fn_state_s boot_fn_state_sigs;
+
+        extern virtual function void reset(string kind = "HARD");
         function new(string name = "soc_ifc_reg_ext");
             super.new(name);
+            boot_fn_state_sigs = '{boot_idle: 1'b1, default: 1'b0};
         endfunction : new
 
         // FIXME Manually maintaining a list here of registers that are configured
         //       as soft-resettable (i.e. cptra_rst_b instead of cptra_pwrgood)
+        //       or noncore-resettable (i.e. cptra_noncore_rst_b instead of cptra_pwrgood)
         //       Ideally would be auto-generated.
-        virtual function void set_soft_reset_values();
-            byte ii;
-//            this.CPTRA_HW_ERROR_FATAL.                 set_reset(this.CPTRA_HW_ERROR_FATAL.                 get_reset("HARD"), "SOFT");
-//            this.CPTRA_HW_ERROR_NON_FATAL.             set_reset(this.CPTRA_HW_ERROR_NON_FATAL.             get_reset("HARD"), "SOFT");
-//            this.CPTRA_FW_ERROR_FATAL.                 set_reset(this.CPTRA_FW_ERROR_FATAL.                 get_reset("HARD"), "SOFT");
-//            this.CPTRA_FW_ERROR_NON_FATAL.             set_reset(this.CPTRA_FW_ERROR_NON_FATAL.             get_reset("HARD"), "SOFT");
-//            this.CPTRA_HW_ERROR_ENC.                   set_reset(this.CPTRA_HW_ERROR_ENC.                   get_reset("HARD"), "SOFT");
-//            this.CPTRA_FW_ERROR_ENC.                   set_reset(this.CPTRA_FW_ERROR_ENC.                   get_reset("HARD"), "SOFT");
-//            this.CPTRA_FW_EXTENDED_ERROR_INFO[8].      set_reset(this.CPTRA_FW_EXTENDED_ERROR_INFO[8].      get_reset("HARD"), "SOFT");
-            if ( this.CPTRA_BOOT_STATUS.                    has_reset("HARD"   )) this.CPTRA_BOOT_STATUS.                    set_reset(this.CPTRA_BOOT_STATUS.                    get_reset("HARD"), "SOFT");
-            if ( this.CPTRA_FLOW_STATUS.status.             has_reset("HARD"   )) this.CPTRA_FLOW_STATUS.status.             set_reset(this.CPTRA_FLOW_STATUS.status.             get_reset("HARD"), "SOFT");
-            if ( this.CPTRA_FLOW_STATUS.ready_for_fw.       has_reset("HARD"   )) this.CPTRA_FLOW_STATUS.ready_for_fw.       set_reset(this.CPTRA_FLOW_STATUS.ready_for_fw.       get_reset("HARD"), "SOFT");
-            if ( this.CPTRA_FLOW_STATUS.ready_for_runtime.  has_reset("HARD"   )) this.CPTRA_FLOW_STATUS.ready_for_runtime.  set_reset(this.CPTRA_FLOW_STATUS.ready_for_runtime.  get_reset("HARD"), "SOFT");
-            if ( this.CPTRA_FLOW_STATUS.ready_for_fuses.    has_reset("HARD"   )) this.CPTRA_FLOW_STATUS.ready_for_fuses.    set_reset(this.CPTRA_FLOW_STATUS.ready_for_fuses.    get_reset("HARD"), "SOFT");
-            if ( this.CPTRA_FLOW_STATUS.mailbox_flow_done.  has_reset("HARD"   )) this.CPTRA_FLOW_STATUS.mailbox_flow_done.  set_reset(this.CPTRA_FLOW_STATUS.mailbox_flow_done.  get_reset("HARD"), "SOFT");
-            if ( this.CPTRA_RESET_REASON.FW_UPD_RESET.      has_reset("HARD"   )) this.CPTRA_RESET_REASON.FW_UPD_RESET.      set_reset(this.CPTRA_RESET_REASON.FW_UPD_RESET.      get_reset("HARD"), "SOFT");
-//            this.CPTRA_RESET_REASON.WARM_RESET.        set_reset(this.CPTRA_RESET_REASON.WARM_RESET.        get_reset("HARD"), "SOFT");
-            if ( this.CPTRA_SECURITY_STATE.device_lifecycle.has_reset("HARD"   )) this.CPTRA_SECURITY_STATE.device_lifecycle.set_reset(this.CPTRA_SECURITY_STATE.device_lifecycle.get_reset("HARD"), "SOFT");
-            if ( this.CPTRA_SECURITY_STATE.debug_locked.    has_reset("HARD"   )) this.CPTRA_SECURITY_STATE.debug_locked.    set_reset(this.CPTRA_SECURITY_STATE.debug_locked.    get_reset("HARD"), "SOFT");
-            if ( this.CPTRA_SECURITY_STATE.scan_mode.       has_reset("HARD"   )) this.CPTRA_SECURITY_STATE.scan_mode.       set_reset(this.CPTRA_SECURITY_STATE.scan_mode.       get_reset("HARD"), "SOFT");
-            if ( this.CPTRA_SECURITY_STATE.rsvd.            has_reset("HARD"   )) this.CPTRA_SECURITY_STATE.rsvd.            set_reset(this.CPTRA_SECURITY_STATE.rsvd.            get_reset("HARD"), "SOFT");
-            for (ii=0; ii<$size(this.CPTRA_MBOX_VALID_PAUSER); ii++) begin
-                if ( this.CPTRA_MBOX_VALID_PAUSER[ii].                has_reset("HARD"   )) this.CPTRA_MBOX_VALID_PAUSER[ii].                set_reset(this.CPTRA_MBOX_VALID_PAUSER[ii].                get_reset("HARD"), "SOFT");
-                if ( this.CPTRA_MBOX_PAUSER_LOCK[ii].                 has_reset("HARD"   )) this.CPTRA_MBOX_PAUSER_LOCK[ii].                 set_reset(this.CPTRA_MBOX_PAUSER_LOCK[ii].                 get_reset("HARD"), "SOFT");
-            end
-            if ( this.CPTRA_TRNG_VALID_PAUSER.              has_reset("HARD"   )) this.CPTRA_TRNG_VALID_PAUSER.              set_reset(this.CPTRA_TRNG_VALID_PAUSER.              get_reset("HARD"), "SOFT");
-            if ( this.CPTRA_TRNG_PAUSER_LOCK.               has_reset("HARD"   )) this.CPTRA_TRNG_PAUSER_LOCK.               set_reset(this.CPTRA_TRNG_PAUSER_LOCK.               get_reset("HARD"), "SOFT");
-            for (ii=0; ii<$size(this.CPTRA_TRNG_DATA); ii++) begin
-                if ( this.CPTRA_TRNG_DATA[ii].                  has_reset("HARD"   )) this.CPTRA_TRNG_DATA[ii].                  set_reset(this.CPTRA_TRNG_DATA[ii].                  get_reset("HARD"), "SOFT");
+        virtual function void configure_reset_values();
+            // Track reset configuration against a queue of all fields in this block, to ensure each register is handled
+            uvm_reg_field blk_flds[$];
+            get_fields(blk_flds, UVM_NO_HIER);
+                                                              `REG_NO_CP_NONCORE_RST(this.CPTRA_HW_ERROR_FATAL                 )
+                                                              `REG_NO_CP_NONCORE_RST(this.CPTRA_HW_ERROR_NON_FATAL             )
+                                                              `REG_NO_CP_NONCORE_RST(this.CPTRA_FW_ERROR_FATAL                 )
+                                                              `REG_NO_CP_NONCORE_RST(this.CPTRA_FW_ERROR_NON_FATAL             )
+                                                              `REG_NO_CP_NONCORE_RST(this.CPTRA_HW_ERROR_ENC                   )
+                                                              `REG_NO_CP_NONCORE_RST(this.CPTRA_FW_ERROR_ENC                   )
+            foreach(this.CPTRA_FW_EXTENDED_ERROR_INFO[ii])    `REG_NO_CP_NONCORE_RST(this.CPTRA_FW_EXTENDED_ERROR_INFO[ii]     )
+                                                              `REG____CP_NONCORE_RST(this.CPTRA_BOOT_STATUS                    )
+                                                              `FLD____CP_NONCORE_RST(this.CPTRA_FLOW_STATUS.status             )
+                                                              `FLD____CP_NONCORE_RST(this.CPTRA_FLOW_STATUS.idevid_csr_ready   )
+                                                              `FLD____CP_NONCORE_RST(this.CPTRA_FLOW_STATUS.boot_fsm_ps        )
+                                                              `FLD____CP_NONCORE_RST(this.CPTRA_FLOW_STATUS.ready_for_fw       )
+                                                              `FLD____CP_NONCORE_RST(this.CPTRA_FLOW_STATUS.ready_for_runtime  )
+                                                              `FLD____CP_NONCORE_RST(this.CPTRA_FLOW_STATUS.ready_for_fuses    )
+                                                              `FLD____CP_NONCORE_RST(this.CPTRA_FLOW_STATUS.mailbox_flow_done  )
+                                                              `FLD____CP_NONCORE_RST(this.CPTRA_RESET_REASON.FW_UPD_RESET      )
+                                                              `FLD_NO_CP_NONCORE_RST(this.CPTRA_RESET_REASON.WARM_RESET        )
+                                                              `FLD____CP_NONCORE_RST(this.CPTRA_SECURITY_STATE.device_lifecycle)
+                                                              `FLD____CP_NONCORE_RST(this.CPTRA_SECURITY_STATE.debug_locked    )
+                                                              `FLD____CP_NONCORE_RST(this.CPTRA_SECURITY_STATE.scan_mode       )
+                                                              `FLD____CP_NONCORE_RST(this.CPTRA_SECURITY_STATE.rsvd            )
+            foreach(this.CPTRA_MBOX_VALID_PAUSER[ii])         `REG____CP_NONCORE_RST(this.CPTRA_MBOX_VALID_PAUSER[ii]          )
+            foreach(this.CPTRA_MBOX_PAUSER_LOCK[ii])          `REG____CP_NONCORE_RST(this.CPTRA_MBOX_PAUSER_LOCK[ii]           )
+                                                              `REG____CP_NONCORE_RST(this.CPTRA_TRNG_VALID_PAUSER              )
+                                                              `REG____CP_NONCORE_RST(this.CPTRA_TRNG_PAUSER_LOCK               )
+            foreach(this.CPTRA_TRNG_DATA[ii])                 `REG____CP_NONCORE_RST(this.CPTRA_TRNG_DATA[ii]                  )
+                                                              `FLD____CP_NONCORE_RST(this.CPTRA_TRNG_CTRL.clear                )
+                                                              `FLD____CP_NONCORE_RST(this.CPTRA_TRNG_STATUS.DATA_REQ           )
+                                                              `FLD____CP_NONCORE_RST(this.CPTRA_TRNG_STATUS.DATA_WR_DONE       )
+                                                              `REG_NO_CP_NONCORE_RST(this.CPTRA_FUSE_WR_DONE                   )
+                                                              `REG_NO_CP_NONCORE_RST(this.CPTRA_TIMER_CONFIG                   )
+                                                              `REG____CP_NONCORE_RST(this.CPTRA_BOOTFSM_GO                     )
+                                                              `REG____CP_NONCORE_RST(this.CPTRA_DBG_MANUF_SERVICE_REG          )
+                                                              `REG____CP_NONCORE_RST(this.CPTRA_CLK_GATING_EN                  )
+            foreach(this.CPTRA_GENERIC_INPUT_WIRES[ii])       `REG____CP_NONCORE_RST(this.CPTRA_GENERIC_INPUT_WIRES[ii]        )
+            foreach(this.CPTRA_GENERIC_OUTPUT_WIRES[ii])      `REG____CP_NONCORE_RST(this.CPTRA_GENERIC_OUTPUT_WIRES[ii]       )
+                                                              `FLD____CP_NONCORE_RST(this.CPTRA_HW_REV_ID.CPTRA_GENERATION     )
+                                                              `FLD____CP_NONCORE_RST(this.CPTRA_HW_REV_ID.SOC_STEPPING_ID      )
+            foreach(this.CPTRA_FW_REV_ID[ii])                 `REG____CP_NONCORE_RST(this.CPTRA_FW_REV_ID[ii]                  )
+                                                              `REG____CP_NONCORE_RST(this.CPTRA_HW_CONFIG                      )
+                                                              `REG____CP_NONCORE_RST(this.CPTRA_WDT_TIMER1_EN                  )
+                                                              `REG____CP_NONCORE_RST(this.CPTRA_WDT_TIMER1_CTRL                )
+            foreach(this.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[ii]) `REG____CP_NONCORE_RST(this.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[ii]  )
+                                                              `REG____CP_NONCORE_RST(this.CPTRA_WDT_TIMER2_EN                  )
+                                                              `REG____CP_NONCORE_RST(this.CPTRA_WDT_TIMER2_CTRL                )
+            foreach(this.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[ii]) `REG____CP_NONCORE_RST(this.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[ii]  )
+                                                              `REG____CP_NONCORE_RST(this.CPTRA_WDT_STATUS                     )
+                                                              `REG_NO_CP_NONCORE_RST(this.CPTRA_FUSE_VALID_PAUSER              )
+                                                              `REG_NO_CP_NONCORE_RST(this.CPTRA_FUSE_PAUSER_LOCK               )
+            foreach(this.CPTRA_WDT_CFG[ii])                   `REG_NO_CP_NONCORE_RST(this.CPTRA_WDT_CFG[ii]                    )
+                                                              `REG____CP_NONCORE_RST(this.CPTRA_iTRNG_ENTROPY_CONFIG_0         )
+                                                              `REG____CP_NONCORE_RST(this.CPTRA_iTRNG_ENTROPY_CONFIG_1         )
+            foreach(this.CPTRA_RSVD_REG[ii])                  `REG____CP_NONCORE_RST(this.CPTRA_RSVD_REG[ii]                   )
+            foreach(this.fuse_uds_seed[ii])                   `REG_NO_CP_NONCORE_RST(this.fuse_uds_seed[ii]                    )
+            foreach(this.fuse_field_entropy[ii])              `REG_NO_CP_NONCORE_RST(this.fuse_field_entropy[ii]               )
+            foreach(this.fuse_key_manifest_pk_hash[ii])       `REG_NO_CP_NONCORE_RST(this.fuse_key_manifest_pk_hash[ii]        )
+                                                              `REG_NO_CP_NONCORE_RST(this.fuse_key_manifest_pk_hash_mask       )
+            foreach(this.fuse_owner_pk_hash[ii])              `REG_NO_CP_NONCORE_RST(this.fuse_owner_pk_hash[ii]               )
+                                                              `REG_NO_CP_NONCORE_RST(this.fuse_fmc_key_manifest_svn            )
+            foreach(this.fuse_runtime_svn[ii])                `REG_NO_CP_NONCORE_RST(this.fuse_runtime_svn[ii]                 )
+                                                              `REG_NO_CP_NONCORE_RST(this.fuse_anti_rollback_disable           )
+            foreach(this.fuse_idevid_cert_attr[ii])           `REG_NO_CP_NONCORE_RST(this.fuse_idevid_cert_attr[ii]            )
+            foreach(this.fuse_idevid_manuf_hsm_id[ii])        `REG_NO_CP_NONCORE_RST(this.fuse_idevid_manuf_hsm_id[ii]         )
+                                                              `REG_NO_CP_NONCORE_RST(this.fuse_life_cycle                      )
+                                                              `REG_NO_CP_NONCORE_RST(this.fuse_lms_verify                      )
+                                                              `REG_NO_CP_NONCORE_RST(this.fuse_lms_revocation                  )
+                                                              `REG_NO_CP_NONCORE_RST(this.fuse_soc_stepping_id                 )
+            foreach(this.internal_obf_key[ii])                `REG_NO_CP_NONCORE_RST(this.internal_obf_key[ii]                 )
+                                                              `REG____CP_NONCORE_RST(this.internal_iccm_lock                   )/* TODO also FW reset */
+                                                              `REG____CP_NONCORE_RST(this.internal_fw_update_reset             )
+                                                              `REG____CP_NONCORE_RST(this.internal_fw_update_reset_wait_cycles )
+                                                              `REG____CP_NONCORE_RST(this.internal_nmi_vector                  )
+                                                              `REG____CP_NONCORE_RST(this.internal_hw_error_fatal_mask         )
+                                                              `REG____CP_NONCORE_RST(this.internal_hw_error_non_fatal_mask     )
+                                                              `REG____CP_NONCORE_RST(this.internal_fw_error_fatal_mask         )
+                                                              `REG____CP_NONCORE_RST(this.internal_fw_error_non_fatal_mask     )
+                                                              `REG_NO_CP_NONCORE_RST(this.internal_rv_mtime_l                  )
+                                                              `REG_NO_CP_NONCORE_RST(this.internal_rv_mtime_h                  )
+                                                              `REG_NO_CP_NONCORE_RST(this.internal_rv_mtimecmp_l               )
+                                                              `REG_NO_CP_NONCORE_RST(this.internal_rv_mtimecmp_h               )
+            while (blk_flds.size() != 0) begin
+                uvm_reg_field cur_fld = blk_flds.pop_front();
+                `uvm_error("SOC_IFC_REG_EXT", {"No extended reset configuration defined for ", cur_fld.get_full_name()})
             end
-            if ( this.CPTRA_TRNG_STATUS.DATA_REQ.           has_reset("HARD"   )) this.CPTRA_TRNG_STATUS.DATA_REQ.           set_reset(this.CPTRA_TRNG_STATUS.DATA_REQ.           get_reset("HARD"), "SOFT");
-            if ( this.CPTRA_TRNG_STATUS.DATA_WR_DONE.       has_reset("HARD"   )) this.CPTRA_TRNG_STATUS.DATA_WR_DONE.       set_reset(this.CPTRA_TRNG_STATUS.DATA_WR_DONE.       get_reset("HARD"), "SOFT");
-//            this.CPTRA_FUSE_WR_DONE.                   set_reset(this.CPTRA_FUSE_WR_DONE.                   get_reset("HARD"), "SOFT");
-//            this.CPTRA_TIMER_CONFIG.                   set_reset(this.CPTRA_TIMER_CONFIG.                   get_reset("HARD"), "SOFT");
-            if ( this.CPTRA_BOOTFSM_GO.                     has_reset("HARD"   )) this.CPTRA_BOOTFSM_GO.                     set_reset(this.CPTRA_BOOTFSM_GO.                     get_reset("HARD"), "SOFT");
-            if ( this.CPTRA_DBG_MANUF_SERVICE_REG.          has_reset("HARD"   )) this.CPTRA_DBG_MANUF_SERVICE_REG.          set_reset(this.CPTRA_DBG_MANUF_SERVICE_REG.          get_reset("HARD"), "SOFT");
-            if ( this.CPTRA_CLK_GATING_EN.                  has_reset("HARD"   )) this.CPTRA_CLK_GATING_EN.                  set_reset(this.CPTRA_CLK_GATING_EN.                  get_reset("HARD"), "SOFT");
-            for (ii=0; ii<$size(this.CPTRA_GENERIC_INPUT_WIRES); ii++) begin
-                if ( this.CPTRA_GENERIC_INPUT_WIRES[ii].         has_reset("HARD"   )) this.CPTRA_GENERIC_INPUT_WIRES[ii].         set_reset(this.CPTRA_GENERIC_INPUT_WIRES[ii].         get_reset("HARD"), "SOFT");
-            end
-            for (ii=0; ii<$size(this.CPTRA_GENERIC_OUTPUT_WIRES); ii++) begin
-                if ( this.CPTRA_GENERIC_OUTPUT_WIRES[ii].        has_reset("HARD"   )) this.CPTRA_GENERIC_OUTPUT_WIRES[ii].        set_reset(this.CPTRA_GENERIC_OUTPUT_WIRES[ii].        get_reset("HARD"), "SOFT");
-            end
-//            for (ii=0; ii<$size(this.fuse_uds_seed); ii++) begin
-//            if ( this.fuse_uds_seed[ii].                    has_reset("HARD"   )) this.fuse_uds_seed[ii].                    set_reset(this.fuse_uds_seed[ii].                    get_reset("HARD"), "SOFT");
-//            end
-//            for (ii=0; ii<$size(this.fuse_field_entropy); ii++) begin
-//            if ( this.fuse_field_entropy[ii].                has_reset("HARD"   )) this.fuse_field_entropy[ii].                set_reset(this.fuse_field_entropy[ii].                get_reset("HARD"), "SOFT");
-//            end
-//            for (ii=0; ii<$size(this.fuse_key_manifest_pk_hash); ii++) begin
-//            if ( this.fuse_key_manifest_pk_hash[ii].        has_reset("HARD"   )) this.fuse_key_manifest_pk_hash[ii].        set_reset(this.fuse_key_manifest_pk_hash[ii].        get_reset("HARD"), "SOFT");
-//            end
-//            if ( this.fuse_key_manifest_pk_hash_mask.       has_reset("HARD"   )) this.fuse_key_manifest_pk_hash_mask.       set_reset(this.fuse_key_manifest_pk_hash_mask.       get_reset("HARD"), "SOFT");
-//            for (ii=0; ii<$size(this.fuse_owner_pk_hash); ii++) begin
-//            if ( this.fuse_owner_pk_hash[ii].               has_reset("HARD"   )) this.fuse_owner_pk_hash[ii].               set_reset(this.fuse_owner_pk_hash[ii].               get_reset("HARD"), "SOFT");
-//            end
-//            if ( this.fuse_fmc_key_manifest_svn.            has_reset("HARD"   )) this.fuse_fmc_key_manifest_svn.            set_reset(this.fuse_fmc_key_manifest_svn.            get_reset("HARD"), "SOFT");
-//            for (ii=0; ii<$size(this.fuse_runtime_svn); ii++) begin
-//            if ( this.fuse_runtime_svn[ii].                  has_reset("HARD"   )) this.fuse_runtime_svn[ii].                  set_reset(this.fuse_runtime_svn[ii].                  get_reset("HARD"), "SOFT");
-//            end
-//            if ( this.fuse_anti_rollback_disable.           has_reset("HARD"   )) this.fuse_anti_rollback_disable.           set_reset(this.fuse_anti_rollback_disable.           get_reset("HARD"), "SOFT");
-//            for (ii=0; ii<$size(this.fuse_idevid_cert_attr); ii++) begin
-//            if ( this.fuse_idevid_cert_attr[ii].            has_reset("HARD"   )) this.fuse_idevid_cert_attr[ii].            set_reset(this.fuse_idevid_cert_attr[ii].            get_reset("HARD"), "SOFT");
-//            end
-//            for (ii=0; ii<$size(this.fuse_idevid_manuf_hsm_id); ii++) begin
-//            if ( this.fuse_idevid_manuf_hsm_id[ii].          has_reset("HARD"   )) this.fuse_idevid_manuf_hsm_id[ii].          set_reset(this.fuse_idevid_manuf_hsm_id[ii].          get_reset("HARD"), "SOFT");
-//            end
-//            if ( this.fuse_life_cycle.                      has_reset("HARD"   )) this.fuse_life_cycle.                      set_reset(this.fuse_life_cycle.                      get_reset("HARD"), "SOFT");
-//            for (ii=0; ii<$size(this.internal_obf_key); ii++) begin
-//            if ( this.internal_obf_key[ii].                  has_reset("HARD"   )) this.internal_obf_key[ii].                  set_reset(this.internal_obf_key[ii].                  get_reset("HARD"), "SOFT"); /* requires manual prediction based on a set of reset conditions */
-//            end
-            if ( this.internal_iccm_lock.                   has_reset("HARD"   )) this.internal_iccm_lock.                   set_reset(this.internal_iccm_lock.                   get_reset("HARD"), "SOFT"); /* TODO also FW reset */
-            if ( this.internal_fw_update_reset.             has_reset("HARD"   )) this.internal_fw_update_reset.             set_reset(this.internal_fw_update_reset.             get_reset("HARD"), "SOFT");
-            if ( this.internal_fw_update_reset_wait_cycles. has_reset("HARD"   )) this.internal_fw_update_reset_wait_cycles. set_reset(this.internal_fw_update_reset_wait_cycles. get_reset("HARD"), "SOFT");
-            if ( this.internal_nmi_vector.                  has_reset("HARD"   )) this.internal_nmi_vector.                  set_reset(this.internal_nmi_vector.                  get_reset("HARD"), "SOFT");
         endfunction
 
         virtual function void build();
             super.build();
-            this.set_soft_reset_values();
+            this.configure_reset_values();
             this.intr_block_rf_ext = new("intr_block_rf_ext");
             this.intr_block_rf_ext.configure(this);
             this.intr_block_rf_ext.build(); // This configures the default_map, which is used to find reg offsets for other maps
@@ -266,10 +369,23 @@ package soc_ifc_reg_model_top_pkg;
 
     endclass : soc_ifc_reg_ext
 
+    function void soc_ifc_reg_ext::reset(string kind = "HARD");
+        super.reset(kind);
+        // BOOT FSM State Changes
+        // "NONCORE" does not cause a state change - it results FROM state changes
+        // TODO what to do for FW update?
+        if (kind inside {"HARD", "SOFT"}) begin
+            boot_fn_state_sigs = '{boot_idle: 1'b1, default: 1'b0};
+        end
+    endfunction
+
     class mbox_csr_ext extends mbox_csr;
         uvm_reg_map mbox_csr_AHB_map;
         uvm_reg_map mbox_csr_APB_map;
 
+        uvm_event mbox_lock_clr_miss;
+        uvm_event mbox_datain_to_dataout_predict;
+
         // This tracks expected functionality of the mailbox in a way that is
         // agnostic to the internal state machine implementation and strictly
         // observes the mailbox specification. This is what a more rigorous
@@ -285,26 +401,36 @@ package soc_ifc_reg_model_top_pkg;
         function new(string name = "mbox_csr_ext");
             super.new(name);
             mbox_fn_state_sigs = '{mbox_idle: 1'b1, default: 1'b0};
+            mbox_lock_clr_miss = new("mbox_lock_clr_miss");
+            mbox_datain_to_dataout_predict = new("mbox_datain_to_dataout_predict");
         endfunction : new
 
         // FIXME Manually maintaining a list here of registers that are configured
         //       as soft-resettable (i.e. cptra_rst_b instead of cptra_pwrgood)
+        //       or noncore-resettable (i.e. cptra_noncore_rst_b instead of cptra_pwrgood)
         //       Ideally would be auto-generated.
-        virtual function void set_soft_reset_values();
-            if ( this.mbox_lock   .has_reset("HARD"   )) this.mbox_lock   .set_reset(this.mbox_lock   .get_reset("HARD"), "SOFT");
-            if ( this.mbox_user   .has_reset("HARD"   )) this.mbox_user   .set_reset(this.mbox_user   .get_reset("HARD"), "SOFT");
-            if ( this.mbox_cmd    .has_reset("HARD"   )) this.mbox_cmd    .set_reset(this.mbox_cmd    .get_reset("HARD"), "SOFT");
-            if ( this.mbox_dlen   .has_reset("HARD"   )) this.mbox_dlen   .set_reset(this.mbox_dlen   .get_reset("HARD"), "SOFT");
-            if ( this.mbox_datain .has_reset("HARD"   )) this.mbox_datain .set_reset(this.mbox_datain .get_reset("HARD"), "SOFT");
-            if ( this.mbox_dataout.has_reset("HARD"   )) this.mbox_dataout.set_reset(this.mbox_dataout.get_reset("HARD"), "SOFT");
-            if ( this.mbox_execute.has_reset("HARD"   )) this.mbox_execute.set_reset(this.mbox_execute.get_reset("HARD"), "SOFT");
-            if ( this.mbox_status .has_reset("HARD"   )) this.mbox_status .set_reset(this.mbox_status .get_reset("HARD"), "SOFT");
-            if ( this.mbox_unlock .has_reset("HARD"   )) this.mbox_unlock .set_reset(this.mbox_unlock .get_reset("HARD"), "SOFT");
+        virtual function void configure_reset_values();
+            // Track reset configuration against a queue of all registers in this block, to ensure each register is handled
+            uvm_reg_field blk_flds[$];
+            get_fields(blk_flds, UVM_NO_HIER);
+            `REG____CP_NONCORE_RST(this.mbox_lock   )
+            `REG____CP_NONCORE_RST(this.mbox_user   )
+            `REG____CP_NONCORE_RST(this.mbox_cmd    )
+            `REG____CP_NONCORE_RST(this.mbox_dlen   )
+            `REG____CP_NONCORE_RST(this.mbox_datain )
+            `REG____CP_NONCORE_RST(this.mbox_dataout)
+            `REG____CP_NONCORE_RST(this.mbox_execute)
+            `REG____CP_NONCORE_RST(this.mbox_status )
+            `REG____CP_NONCORE_RST(this.mbox_unlock )
+            while (blk_flds.size() != 0) begin
+                uvm_reg_field cur_fld = blk_flds.pop_front();
+                `uvm_error("MBOX_CSR_EXT", {"No extended reset configuration defined for ", cur_fld.get_full_name()})
+            end
         endfunction
 
         virtual function void build();
             super.build();
-            this.set_soft_reset_values();
+            this.configure_reset_values();
             this.mbox_csr_AHB_map = create_map("AHB_reg_map", 0, 4, UVM_LITTLE_ENDIAN);
             this.mbox_csr_APB_map = create_map("APB_reg_map", 0, 4, UVM_LITTLE_ENDIAN);
         endfunction
@@ -325,12 +451,19 @@ package soc_ifc_reg_model_top_pkg;
 
     function void mbox_csr_ext::reset(string kind = "HARD");
         super.reset(kind);
-        mbox_data_q.delete();
-        mbox_resp_q.delete();
-
-        // Mailbox State Changes
-        // TODO what to do for FW update?
-        mbox_fn_state_sigs = '{mbox_idle: 1'b1, default: 1'b0};
+        // "SOFT" reset doesn't impact mbox registers until it propagates to the NONCORE reset.
+        // Since there's a delay, wait until the NONCORE reset is called to clobber data queues and
+        // reg model internal semaphores
+        if (kind inside {"HARD", "NONCORE"}) begin
+            mbox_data_q.delete();
+            mbox_resp_q.delete();
+            mbox_lock_clr_miss.reset();
+            mbox_datain_to_dataout_predict.reset();
+
+            // Mailbox State Changes
+            // TODO what to do for FW update?
+            mbox_fn_state_sigs = '{mbox_idle: 1'b1, default: 1'b0};
+        end
 
     endfunction
 
@@ -338,38 +471,51 @@ package soc_ifc_reg_model_top_pkg;
         uvm_reg_map sha512_acc_csr_intr_AHB_map;
         uvm_reg_map sha512_acc_csr_intr_APB_map;
 
+        // HWSET has precedence over SW W1C, so use these variables to track
+        // active hwset activity in case contention must be resolved
+        bit [31:0] notif_internal_intr_r_hwset_active = 0;
+        bit [31:0] error_internal_intr_r_hwset_active = 0;
+
         function new(string name = "sha512_acc_csr__intr_block_t_ext");
             super.new(name);
         endfunction : new
 
         // FIXME Manually maintaining a list here of registers that are configured
         //       as soft-resettable (i.e. cptra_rst_b instead of cptra_pwrgood)
+        //       or noncore-resettable (i.e. cptra_noncore_rst_b instead of cptra_pwrgood)
         //       Ideally would be auto-generated.
-        virtual function void set_soft_reset_values();
-            if ( this.global_intr_en_r                      .has_reset("HARD"   )) this.global_intr_en_r                      .set_reset(this.global_intr_en_r                    .get_reset("HARD"), "SOFT");
-            if ( this.error_intr_en_r                       .has_reset("HARD"   )) this.error_intr_en_r                       .set_reset(this.error_intr_en_r                     .get_reset("HARD"), "SOFT");
-            if ( this.notif_intr_en_r                       .has_reset("HARD"   )) this.notif_intr_en_r                       .set_reset(this.notif_intr_en_r                     .get_reset("HARD"), "SOFT");
-            if ( this.error_global_intr_r                   .has_reset("HARD"   )) this.error_global_intr_r                   .set_reset(this.error_global_intr_r                 .get_reset("HARD"), "SOFT");
-            if ( this.notif_global_intr_r                   .has_reset("HARD"   )) this.notif_global_intr_r                   .set_reset(this.notif_global_intr_r                 .get_reset("HARD"), "SOFT");
-//            this.error_internal_intr_r                 .set_reset(this.error_internal_intr_r               .get_reset("HARD"), "SOFT");
-            if ( this.notif_internal_intr_r                 .has_reset("HARD"   )) this.notif_internal_intr_r                 .set_reset(this.notif_internal_intr_r               .get_reset("HARD"), "SOFT");
-            if ( this.error_intr_trig_r                     .has_reset("HARD"   )) this.error_intr_trig_r                     .set_reset(this.error_intr_trig_r                   .get_reset("HARD"), "SOFT");
-            if ( this.notif_intr_trig_r                     .has_reset("HARD"   )) this.notif_intr_trig_r                     .set_reset(this.notif_intr_trig_r                   .get_reset("HARD"), "SOFT");
-//            if ( this.error0_intr_count_r                   .has_reset("HARD"   )) this.error0_intr_count_r                   .set_reset(this.error0_intr_count_r                 .get_reset("HARD"), "SOFT");
-//            if ( this.error1_intr_count_r                   .has_reset("HARD"   )) this.error1_intr_count_r                   .set_reset(this.error1_intr_count_r                 .get_reset("HARD"), "SOFT");
-//            if ( this.error2_intr_count_r                   .has_reset("HARD"   )) this.error2_intr_count_r                   .set_reset(this.error2_intr_count_r                 .get_reset("HARD"), "SOFT");
-//            if ( this.error3_intr_count_r                   .has_reset("HARD"   )) this.error3_intr_count_r                   .set_reset(this.error3_intr_count_r                 .get_reset("HARD"), "SOFT");
-            if ( this.notif_cmd_done_intr_count_r           .has_reset("HARD"   )) this.notif_cmd_done_intr_count_r           .set_reset(this.notif_cmd_done_intr_count_r         .get_reset("HARD"), "SOFT");
-            if ( this.error0_intr_count_incr_r              .has_reset("HARD"   )) this.error0_intr_count_incr_r              .set_reset(this.error0_intr_count_incr_r            .get_reset("HARD"), "SOFT");
-            if ( this.error1_intr_count_incr_r              .has_reset("HARD"   )) this.error1_intr_count_incr_r              .set_reset(this.error1_intr_count_incr_r            .get_reset("HARD"), "SOFT");
-            if ( this.error2_intr_count_incr_r              .has_reset("HARD"   )) this.error2_intr_count_incr_r              .set_reset(this.error2_intr_count_incr_r            .get_reset("HARD"), "SOFT");
-            if ( this.error3_intr_count_incr_r              .has_reset("HARD"   )) this.error3_intr_count_incr_r              .set_reset(this.error3_intr_count_incr_r            .get_reset("HARD"), "SOFT");
-            if ( this.notif_cmd_done_intr_count_incr_r      .has_reset("HARD"   )) this.notif_cmd_done_intr_count_incr_r      .set_reset(this.notif_cmd_done_intr_count_incr_r    .get_reset("HARD"), "SOFT");
+        virtual function void configure_reset_values();
+            // Track reset configuration against a queue of all registers in this block, to ensure each register is handled
+            uvm_reg_field blk_flds[$];
+            get_fields(blk_flds, UVM_NO_HIER);
+            `REG____CP_NONCORE_RST(this.global_intr_en_r                 )
+            `REG____CP_NONCORE_RST(this.error_intr_en_r                  )
+            `REG____CP_NONCORE_RST(this.notif_intr_en_r                  )
+            `REG____CP_NONCORE_RST(this.error_global_intr_r              )
+            `REG____CP_NONCORE_RST(this.notif_global_intr_r              )
+            `REG_NO_CP_NONCORE_RST(this.error_internal_intr_r            )
+            `REG____CP_NONCORE_RST(this.notif_internal_intr_r            )
+            `REG____CP_NONCORE_RST(this.error_intr_trig_r                )
+            `REG____CP_NONCORE_RST(this.notif_intr_trig_r                )
+            `REG_NO_CP_NONCORE_RST(this.error0_intr_count_r              )
+            `REG_NO_CP_NONCORE_RST(this.error1_intr_count_r              )
+            `REG_NO_CP_NONCORE_RST(this.error2_intr_count_r              )
+            `REG_NO_CP_NONCORE_RST(this.error3_intr_count_r              )
+            `REG____CP_NONCORE_RST(this.notif_cmd_done_intr_count_r      )
+            `REG____CP_NONCORE_RST(this.error0_intr_count_incr_r         )
+            `REG____CP_NONCORE_RST(this.error1_intr_count_incr_r         )
+            `REG____CP_NONCORE_RST(this.error2_intr_count_incr_r         )
+            `REG____CP_NONCORE_RST(this.error3_intr_count_incr_r         )
+            `REG____CP_NONCORE_RST(this.notif_cmd_done_intr_count_incr_r )
+            while (blk_flds.size() != 0) begin
+                uvm_reg_field cur_fld = blk_flds.pop_front();
+                `uvm_error("SHA512_ACC_CSR__INTR_BLOCK_T_EXT", {"No extended reset configuration defined for ", cur_fld.get_full_name()})
+            end
         endfunction
 
         virtual function void build();
             super.build();
-            this.set_soft_reset_values();
+            this.configure_reset_values();
             this.sha512_acc_csr_intr_AHB_map = create_map("intr_AHB_reg_map", 0, 4, UVM_LITTLE_ENDIAN);
             this.sha512_acc_csr_intr_APB_map = create_map("intr_APB_reg_map", 0, 4, UVM_LITTLE_ENDIAN);
         endfunction
@@ -408,26 +554,31 @@ package soc_ifc_reg_model_top_pkg;
 
         // FIXME Manually maintaining a list here of registers that are configured
         //       as soft-resettable (i.e. cptra_rst_b instead of cptra_pwrgood)
+        //       or noncore-resettable (i.e. cptra_noncore_rst_b instead of cptra_pwrgood)
         //       Ideally would be auto-generated.
-        virtual function void set_soft_reset_values();
-            byte ii;
-            if ( this.LOCK          .has_reset("HARD"   )) this.LOCK          .set_reset(this.LOCK          .get_reset("HARD"), "SOFT");
-            if ( this.USER          .has_reset("HARD"   )) this.USER          .set_reset(this.USER          .get_reset("HARD"), "SOFT");
-            if ( this.MODE          .has_reset("HARD"   )) this.MODE          .set_reset(this.MODE          .get_reset("HARD"), "SOFT");
-            if ( this.START_ADDRESS .has_reset("HARD"   )) this.START_ADDRESS .set_reset(this.START_ADDRESS .get_reset("HARD"), "SOFT");
-            if ( this.DLEN          .has_reset("HARD"   )) this.DLEN          .set_reset(this.DLEN          .get_reset("HARD"), "SOFT");
-            if ( this.DATAIN        .has_reset("HARD"   )) this.DATAIN        .set_reset(this.DATAIN        .get_reset("HARD"), "SOFT");
-            if ( this.EXECUTE       .has_reset("HARD"   )) this.EXECUTE       .set_reset(this.EXECUTE       .get_reset("HARD"), "SOFT");
-            if ( this.STATUS        .has_reset("HARD"   )) this.STATUS        .set_reset(this.STATUS        .get_reset("HARD"), "SOFT");
-            for (ii=0; ii<$size(this.DIGEST); ii++) begin
-                if ( this.DIGEST[ii]    .has_reset("HARD"   )) this.DIGEST[ii]    .set_reset(this.DIGEST[ii]    .get_reset("HARD"), "SOFT");
+        virtual function void configure_reset_values();
+            // Track reset configuration against a queue of all fields in this block, to ensure each register is handled
+            uvm_reg_field blk_flds[$];
+            get_fields(blk_flds, UVM_NO_HIER);
+                                     `REG____CP_NONCORE_RST(this.LOCK          )
+                                     `REG____CP_NONCORE_RST(this.USER          )
+                                     `REG____CP_NONCORE_RST(this.MODE          )
+                                     `REG____CP_NONCORE_RST(this.START_ADDRESS )
+                                     `REG____CP_NONCORE_RST(this.DLEN          )
+                                     `REG____CP_NONCORE_RST(this.DATAIN        )
+                                     `REG____CP_NONCORE_RST(this.EXECUTE       )
+                                     `REG____CP_NONCORE_RST(this.STATUS        )
+            foreach(this.DIGEST[ii]) `REG____CP_NONCORE_RST(this.DIGEST[ii]    )
+                                     `REG____CP_NONCORE_RST(this.CONTROL       )
+            while (blk_flds.size() != 0) begin
+                uvm_reg_field cur_fld = blk_flds.pop_front();
+                `uvm_error("SHA512_ACC_CSR_EXT", {"No extended reset configuration defined for ", cur_fld.get_full_name()})
             end
-            if ( this.CONTROL       .has_reset("HARD"   )) this.CONTROL       .set_reset(this.CONTROL       .get_reset("HARD"), "SOFT");
         endfunction
 
         virtual function void build();
             super.build();
-            this.set_soft_reset_values();
+            this.configure_reset_values();
             this.intr_block_rf_ext = new("intr_block_rf_ext");
             this.intr_block_rf_ext.configure(this);
             this.intr_block_rf_ext.build(); // This configures the default_map, which is used to find reg offsets for other maps
@@ -469,6 +620,8 @@ package soc_ifc_reg_model_top_pkg;
 
     // Scheduling helper class for delayed callback tasks
     `include "soc_ifc_reg_delay_job.svh"
+    `include "soc_ifc_reg_delay_job_mbox_csr_mbox_prot_error.svh"
+    `include "soc_ifc_reg_delay_job_intr_block_rf_ext.svh"
 
     // Callbacks for predicting reg-field updates
     `include "soc_ifc_reg_cbs_mbox_csr.svh"
@@ -478,6 +631,7 @@ package soc_ifc_reg_model_top_pkg;
     `include "soc_ifc_reg_cbs_mbox_csr_mbox_datain_datain.svh"
     `include "soc_ifc_reg_cbs_mbox_csr_mbox_dataout_dataout.svh"
     `include "soc_ifc_reg_cbs_mbox_csr_mbox_status_status.svh"
+    `include "soc_ifc_reg_cbs_mbox_csr_mbox_status_mbox_fsm_ps.svh"
     `include "soc_ifc_reg_cbs_mbox_csr_mbox_execute_execute.svh"
     `include "soc_ifc_reg_cbs_mbox_csr_mbox_unlock_unlock.svh"
     `include "soc_ifc_reg_cbs_intr_block_rf_ext_global_intr_en_r_base.svh"
@@ -487,27 +641,81 @@ package soc_ifc_reg_model_top_pkg;
     `include "soc_ifc_reg_cbs_intr_block_rf_ext_notif_internal_intr_r_base.svh"
     `include "soc_ifc_reg_cbs_intr_block_rf_ext_notif_intr_en_r_base.svh"
     `include "soc_ifc_reg_cbs_intr_block_rf_ext_notif_intr_trig_r_base.svh"
+    `include "soc_ifc_reg_cbs_intr_block_rf_ext_internal.svh"
+    `include "soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_HW_ERROR_FATAL.svh"
+    `include "soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_HW_ERROR_NON_FATAL.svh"
     `include "soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_TRNG_DATA_DATA.svh"
     `include "soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_TRNG_PAUSER_LOCK_LOCK.svh"
+    `include "soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_TRNG_CTRL_CLEAR.svh"
     `include "soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_TRNG_STATUS_DATA_REQ.svh"
     `include "soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_TRNG_STATUS_DATA_WR_DONE.svh"
     `include "soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_TRNG_VALID_PAUSER_PAUSER.svh"
+    `include "soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART.svh"
+    `include "soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART.svh"
+    `include "soc_ifc_reg_cbs_soc_ifc_reg_secret.svh"
+    `include "soc_ifc_reg_cbs_soc_ifc_reg_fuse.svh"
+    `include "soc_ifc_reg_cbs_soc_ifc_reg_key.svh"
+    `include "soc_ifc_reg_cbs_soc_ifc_reg_internal.svh"
+    `include "soc_ifc_reg_cbs_soc_ifc_reg_internal_fw_update_reset.svh"
+    `include "soc_ifc_reg_cbs_sha512_acc_csr_LOCK_LOCK.svh"
+    `include "soc_ifc_reg_cbs_sha512_acc_csr_EXECUTE_EXECUTE.svh"
+
+    // Callback for sampling coverage
+    `include "soc_ifc_reg_cbs_sample.svh"
 
 // pragma uvmf custom define_register_classes end
 // pragma uvmf custom define_block_map_coverage_class begin
    //--------------------------------------------------------------------
-   // Class: soc_ifc_fixme_map_coverage
+   // Class: soc_ifc_AHB_map_coverage
+   // 
+   // Coverage for the 'AHB_map' in 'soc_ifc_reg_model'
+   //--------------------------------------------------------------------
+   class soc_ifc_AHB_map_coverage extends uvm_object;
+      `uvm_object_utils(soc_ifc_AHB_map_coverage)
+
+      covergroup ra_cov(string name) with function sample(uvm_reg_addr_t addr, bit is_read);
+
+         option.per_instance = 1;
+         option.name = name; 
+
+         // FIXME
+         ADDR: coverpoint addr {
+            bins example_reg0 = {'h0};
+            bins example_reg1 = {'h1};
+         }
+
+         RW: coverpoint is_read {
+            bins RD = {1};
+            bins WR = {0};
+         }
+
+         ACCESS: cross ADDR, RW;
+
+      endgroup: ra_cov
+
+      function new(string name = "soc_ifc_AHB_map_coverage");
+         ra_cov = new(name);
+      endfunction: new
+
+      function void sample(uvm_reg_addr_t offset, bit is_read);
+         ra_cov.sample(offset, is_read);
+      endfunction: sample
+
+   endclass: soc_ifc_AHB_map_coverage
+   //--------------------------------------------------------------------
+   // Class: soc_ifc_APB_map_coverage
    // 
-   // Coverage for the 'fixme_map' in 'soc_ifc_reg_model'
+   // Coverage for the 'APB_map' in 'soc_ifc_reg_model'
    //--------------------------------------------------------------------
-   class soc_ifc_fixme_map_coverage extends uvm_object;
-      `uvm_object_utils(soc_ifc_fixme_map_coverage)
+   class soc_ifc_APB_map_coverage extends uvm_object;
+      `uvm_object_utils(soc_ifc_APB_map_coverage)
 
       covergroup ra_cov(string name) with function sample(uvm_reg_addr_t addr, bit is_read);
 
          option.per_instance = 1;
          option.name = name; 
 
+         // FIXME
          ADDR: coverpoint addr {
             bins example_reg0 = {'h0};
             bins example_reg1 = {'h1};
@@ -522,7 +730,7 @@ package soc_ifc_reg_model_top_pkg;
 
       endgroup: ra_cov
 
-      function new(string name = "soc_ifc_fixme_map_coverage");
+      function new(string name = "soc_ifc_APB_map_coverage");
          ra_cov = new(name);
       endfunction: new
 
@@ -530,7 +738,7 @@ package soc_ifc_reg_model_top_pkg;
          ra_cov.sample(offset, is_read);
       endfunction: sample
 
-   endclass: soc_ifc_fixme_map_coverage
+   endclass: soc_ifc_APB_map_coverage
 // pragma uvmf custom define_block_map_coverage_class end
 
    //--------------------------------------------------------------------
@@ -556,6 +764,7 @@ package soc_ifc_reg_model_top_pkg;
         soc_ifc_reg_cbs_intr_block_rf_ext_notif_internal_intr_r_base soc_ifc_reg_intr_block_rf_ext_notif_internal_intr_r_base_cb;
         soc_ifc_reg_cbs_intr_block_rf_ext_notif_intr_en_r_base       soc_ifc_reg_intr_block_rf_ext_notif_intr_en_r_base_cb;
         soc_ifc_reg_cbs_intr_block_rf_ext_notif_intr_trig_r_base     soc_ifc_reg_intr_block_rf_ext_notif_intr_trig_r_base_cb;
+        soc_ifc_reg_cbs_intr_block_rf_ext_internal                   soc_ifc_reg_intr_block_rf_ext_internal_cb;
 
         soc_ifc_reg_cbs_intr_block_rf_ext_global_intr_en_r_base      sha512_acc_csr_intr_block_rf_ext_global_intr_en_r_base_cb;
         soc_ifc_reg_cbs_intr_block_rf_ext_error_internal_intr_r_base sha512_acc_csr_intr_block_rf_ext_error_internal_intr_r_base_cb;
@@ -564,34 +773,58 @@ package soc_ifc_reg_model_top_pkg;
         soc_ifc_reg_cbs_intr_block_rf_ext_notif_internal_intr_r_base sha512_acc_csr_intr_block_rf_ext_notif_internal_intr_r_base_cb;
         soc_ifc_reg_cbs_intr_block_rf_ext_notif_intr_en_r_base       sha512_acc_csr_intr_block_rf_ext_notif_intr_en_r_base_cb;
         soc_ifc_reg_cbs_intr_block_rf_ext_notif_intr_trig_r_base     sha512_acc_csr_intr_block_rf_ext_notif_intr_trig_r_base_cb;
+        soc_ifc_reg_cbs_intr_block_rf_ext_internal                   sha512_acc_csr_intr_block_rf_ext_internal_cb;
 
-        soc_ifc_reg_cbs_mbox_csr_mbox_lock_lock       mbox_csr_mbox_lock_lock_cb;
-        soc_ifc_reg_cbs_mbox_csr_mbox_cmd_command     mbox_csr_mbox_cmd_command_cb;
-        soc_ifc_reg_cbs_mbox_csr_mbox_dlen_length     mbox_csr_mbox_dlen_length_cb;
-        soc_ifc_reg_cbs_mbox_csr_mbox_datain_datain   mbox_csr_mbox_datain_datain_cb;
-        soc_ifc_reg_cbs_mbox_csr_mbox_dataout_dataout mbox_csr_mbox_dataout_dataout_cb;
-        soc_ifc_reg_cbs_mbox_csr_mbox_status_status   mbox_csr_mbox_status_status_cb;
-        soc_ifc_reg_cbs_mbox_csr_mbox_execute_execute mbox_csr_mbox_execute_execute_cb;
-        soc_ifc_reg_cbs_mbox_csr_mbox_unlock_unlock   mbox_csr_mbox_unlock_unlock_cb;
 
+        soc_ifc_reg_cbs_mbox_csr_mbox_lock_lock          mbox_csr_mbox_lock_lock_cb;
+        soc_ifc_reg_cbs_mbox_csr_mbox_cmd_command        mbox_csr_mbox_cmd_command_cb;
+        soc_ifc_reg_cbs_mbox_csr_mbox_dlen_length        mbox_csr_mbox_dlen_length_cb;
+        soc_ifc_reg_cbs_mbox_csr_mbox_datain_datain      mbox_csr_mbox_datain_datain_cb;
+        soc_ifc_reg_cbs_mbox_csr_mbox_dataout_dataout    mbox_csr_mbox_dataout_dataout_cb;
+        soc_ifc_reg_cbs_mbox_csr_mbox_status_status      mbox_csr_mbox_status_status_cb;
+        soc_ifc_reg_cbs_mbox_csr_mbox_status_mbox_fsm_ps mbox_csr_mbox_status_mbox_fsm_ps_cb;
+        soc_ifc_reg_cbs_mbox_csr_mbox_execute_execute    mbox_csr_mbox_execute_execute_cb;
+        soc_ifc_reg_cbs_mbox_csr_mbox_unlock_unlock      mbox_csr_mbox_unlock_unlock_cb;
+
+        soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_HW_ERROR_FATAL              soc_ifc_reg_CPTRA_HW_ERROR_FATAL_cb;
+        soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_HW_ERROR_NON_FATAL          soc_ifc_reg_CPTRA_HW_ERROR_NON_FATAL_cb;
         soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_TRNG_DATA_DATA              soc_ifc_reg_CPTRA_TRNG_DATA_DATA_cb;
         soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_TRNG_PAUSER_LOCK_LOCK       soc_ifc_reg_CPTRA_TRNG_PAUSER_LOCK_LOCK_cb;
+        soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_TRNG_CTRL_CLEAR             soc_ifc_reg_CPTRA_TRNG_CTRL_CLEAR_cb;
         soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_TRNG_STATUS_DATA_REQ        soc_ifc_reg_CPTRA_TRNG_STATUS_DATA_REQ_cb;
         soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_TRNG_STATUS_DATA_WR_DONE    soc_ifc_reg_CPTRA_TRNG_STATUS_DATA_WR_DONE_cb;
         soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_TRNG_VALID_PAUSER_PAUSER    soc_ifc_reg_CPTRA_TRNG_VALID_PAUSER_PAUSER_cb;
+        soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART soc_ifc_reg_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART_cb;
+        soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART soc_ifc_reg_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART_cb;
+
+        soc_ifc_reg_cbs_soc_ifc_reg_secret   soc_ifc_reg_secret_cb;
+        soc_ifc_reg_cbs_soc_ifc_reg_fuse     soc_ifc_reg_fuse_cb;
+        soc_ifc_reg_cbs_soc_ifc_reg_key      soc_ifc_reg_key_cb;
+        soc_ifc_reg_cbs_soc_ifc_reg_internal soc_ifc_reg_internal_cb;
+        soc_ifc_reg_cbs_soc_ifc_reg_internal_fw_update_reset soc_ifc_reg_internal_fw_update_reset_cb;
 
+        soc_ifc_reg_cbs_sha512_acc_csr_LOCK_LOCK       sha512_acc_csr_LOCK_LOCK_cb;
+        soc_ifc_reg_cbs_sha512_acc_csr_EXECUTE_EXECUTE sha512_acc_csr_EXECUTE_EXECUTE_cb;
+
+        soc_ifc_reg_cbs_sample sample_cb;
+
+        uvm_reg_field cptra_fatal_flds[$];
+        uvm_reg_field cptra_non_fatal_flds[$];
         uvm_reg_field error_en_flds[$];
         uvm_reg_field notif_en_flds[$];
         uvm_reg_field error_sts_flds[$];
         uvm_reg_field notif_sts_flds[$];
         uvm_reg_field error_trig_flds[$];
         uvm_reg_field notif_trig_flds[$];
+        uvm_reg_field all_fields[$];
+        uvm_reg       all_regs[$];
 
         uvm_queue #(soc_ifc_reg_delay_job) delay_jobs;
 
 // pragma uvmf custom instantiate_registers_within_block end
 
-      soc_ifc_fixme_map_coverage fixme_map_cg;
+      soc_ifc_AHB_map_coverage AHB_map_cg;
+      soc_ifc_APB_map_coverage APB_map_cg;
 
       // Function: new
       // 
@@ -599,12 +832,25 @@ package soc_ifc_reg_model_top_pkg;
          super.new(name, build_coverage(UVM_CVR_ALL));
       endfunction
 
+      // Function: reset
+      // 
+      function void reset(string kind = "HARD");
+          super.reset(kind);
+          if (kind inside {"HARD", "NONCORE"}) begin
+              // Purge all pending jobs to update the register model
+              `uvm_info("SOC_IFC_REG_MODEL_TOP", {"Reset of kind ", kind, " results in delay_jobs being cleared"}, UVM_HIGH)
+              delay_jobs.delete();
+          end
+      endfunction
+
       // Function: build
       // 
       virtual function void build();
       if(has_coverage(UVM_CVR_ADDR_MAP)) begin
-         fixme_map_cg = soc_ifc_fixme_map_coverage::type_id::create("fixme_map_cg");
-         fixme_map_cg.ra_cov.set_inst_name(this.get_full_name());
+         AHB_map_cg = soc_ifc_AHB_map_coverage::type_id::create("AHB_map_cg");
+         APB_map_cg = soc_ifc_APB_map_coverage::type_id::create("APB_map_cg");
+         AHB_map_cg.ra_cov.set_inst_name({this.get_full_name(),"_AHB_cg"});
+         APB_map_cg.ra_cov.set_inst_name({this.get_full_name(),"_APB_cg"});
          void'(set_coverage(UVM_CVR_ADDR_MAP));
       end
 
@@ -640,6 +886,7 @@ package soc_ifc_reg_model_top_pkg;
         soc_ifc_reg_intr_block_rf_ext_notif_internal_intr_r_base_cb = soc_ifc_reg_cbs_intr_block_rf_ext_notif_internal_intr_r_base::type_id::create("soc_ifc_reg_intr_block_rf_ext_notif_internal_intr_r_base_cb");
         soc_ifc_reg_intr_block_rf_ext_notif_intr_en_r_base_cb       = soc_ifc_reg_cbs_intr_block_rf_ext_notif_intr_en_r_base      ::type_id::create("soc_ifc_reg_intr_block_rf_ext_notif_intr_en_r_base_cb"      );
         soc_ifc_reg_intr_block_rf_ext_notif_intr_trig_r_base_cb     = soc_ifc_reg_cbs_intr_block_rf_ext_notif_intr_trig_r_base    ::type_id::create("soc_ifc_reg_intr_block_rf_ext_notif_intr_trig_r_base_cb"    );
+        soc_ifc_reg_intr_block_rf_ext_internal_cb                   = soc_ifc_reg_cbs_intr_block_rf_ext_internal                  ::type_id::create("soc_ifc_reg_intr_block_rf_ext_internal_cb"                  );
 
         sha512_acc_csr_intr_block_rf_ext_global_intr_en_r_base_cb      = soc_ifc_reg_cbs_intr_block_rf_ext_global_intr_en_r_base     ::type_id::create("sha512_acc_csr_intr_block_rf_ext_global_intr_en_r_base_cb"     );
         sha512_acc_csr_intr_block_rf_ext_error_internal_intr_r_base_cb = soc_ifc_reg_cbs_intr_block_rf_ext_error_internal_intr_r_base::type_id::create("sha512_acc_csr_intr_block_rf_ext_error_internal_intr_r_base_cb");
@@ -648,21 +895,39 @@ package soc_ifc_reg_model_top_pkg;
         sha512_acc_csr_intr_block_rf_ext_notif_internal_intr_r_base_cb = soc_ifc_reg_cbs_intr_block_rf_ext_notif_internal_intr_r_base::type_id::create("sha512_acc_csr_intr_block_rf_ext_notif_internal_intr_r_base_cb");
         sha512_acc_csr_intr_block_rf_ext_notif_intr_en_r_base_cb       = soc_ifc_reg_cbs_intr_block_rf_ext_notif_intr_en_r_base      ::type_id::create("sha512_acc_csr_intr_block_rf_ext_notif_intr_en_r_base_cb"      );
         sha512_acc_csr_intr_block_rf_ext_notif_intr_trig_r_base_cb     = soc_ifc_reg_cbs_intr_block_rf_ext_notif_intr_trig_r_base    ::type_id::create("sha512_acc_csr_intr_block_rf_ext_notif_intr_trig_r_base_cb"    );
-
-        mbox_csr_mbox_lock_lock_cb       = soc_ifc_reg_cbs_mbox_csr_mbox_lock_lock      ::type_id::create("mbox_csr_mbox_lock_lock_cb"      );
-        mbox_csr_mbox_cmd_command_cb     = soc_ifc_reg_cbs_mbox_csr_mbox_cmd_command    ::type_id::create("mbox_csr_mbox_cmd_command_cb"    );
-        mbox_csr_mbox_dlen_length_cb     = soc_ifc_reg_cbs_mbox_csr_mbox_dlen_length    ::type_id::create("mbox_csr_mbox_dlen_length_cb"    );
-        mbox_csr_mbox_datain_datain_cb   = soc_ifc_reg_cbs_mbox_csr_mbox_datain_datain  ::type_id::create("mbox_csr_mbox_datain_datain_cb"  );
-        mbox_csr_mbox_dataout_dataout_cb = soc_ifc_reg_cbs_mbox_csr_mbox_dataout_dataout::type_id::create("mbox_csr_mbox_dataout_dataout_cb");
-        mbox_csr_mbox_status_status_cb   = soc_ifc_reg_cbs_mbox_csr_mbox_status_status  ::type_id::create("mbox_csr_mbox_status_status_cb"  );
-        mbox_csr_mbox_execute_execute_cb = soc_ifc_reg_cbs_mbox_csr_mbox_execute_execute::type_id::create("mbox_csr_mbox_execute_execute_cb");
-        mbox_csr_mbox_unlock_unlock_cb   = soc_ifc_reg_cbs_mbox_csr_mbox_unlock_unlock  ::type_id::create("mbox_csr_mbox_unlock_unlock_cb"  );
-
+        sha512_acc_csr_intr_block_rf_ext_internal_cb                   = soc_ifc_reg_cbs_intr_block_rf_ext_internal                  ::type_id::create("sha512_acc_csr_intr_block_rf_ext_internal_cb"                  );
+
+        mbox_csr_mbox_lock_lock_cb          = soc_ifc_reg_cbs_mbox_csr_mbox_lock_lock         ::type_id::create("mbox_csr_mbox_lock_lock_cb"         );
+        mbox_csr_mbox_cmd_command_cb        = soc_ifc_reg_cbs_mbox_csr_mbox_cmd_command       ::type_id::create("mbox_csr_mbox_cmd_command_cb"       );
+        mbox_csr_mbox_dlen_length_cb        = soc_ifc_reg_cbs_mbox_csr_mbox_dlen_length       ::type_id::create("mbox_csr_mbox_dlen_length_cb"       );
+        mbox_csr_mbox_datain_datain_cb      = soc_ifc_reg_cbs_mbox_csr_mbox_datain_datain     ::type_id::create("mbox_csr_mbox_datain_datain_cb"     );
+        mbox_csr_mbox_dataout_dataout_cb    = soc_ifc_reg_cbs_mbox_csr_mbox_dataout_dataout   ::type_id::create("mbox_csr_mbox_dataout_dataout_cb"   );
+        mbox_csr_mbox_status_status_cb      = soc_ifc_reg_cbs_mbox_csr_mbox_status_status     ::type_id::create("mbox_csr_mbox_status_status_cb"     );
+        mbox_csr_mbox_status_mbox_fsm_ps_cb = soc_ifc_reg_cbs_mbox_csr_mbox_status_mbox_fsm_ps::type_id::create("mbox_csr_mbox_status_mbox_fsm_ps_cb");
+        mbox_csr_mbox_execute_execute_cb    = soc_ifc_reg_cbs_mbox_csr_mbox_execute_execute   ::type_id::create("mbox_csr_mbox_execute_execute_cb"   );
+        mbox_csr_mbox_unlock_unlock_cb      = soc_ifc_reg_cbs_mbox_csr_mbox_unlock_unlock     ::type_id::create("mbox_csr_mbox_unlock_unlock_cb"     );
+
+        soc_ifc_reg_CPTRA_HW_ERROR_FATAL_cb            = soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_HW_ERROR_FATAL          ::type_id::create("soc_ifc_reg_CPTRA_HW_ERROR_FATAL_cb"          );
+        soc_ifc_reg_CPTRA_HW_ERROR_NON_FATAL_cb        = soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_HW_ERROR_NON_FATAL      ::type_id::create("soc_ifc_reg_CPTRA_HW_ERROR_NON_FATAL_cb"      );
         soc_ifc_reg_CPTRA_TRNG_DATA_DATA_cb            = soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_TRNG_DATA_DATA          ::type_id::create("soc_ifc_reg_CPTRA_TRNG_DATA_DATA_cb"          );
         soc_ifc_reg_CPTRA_TRNG_PAUSER_LOCK_LOCK_cb     = soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_TRNG_PAUSER_LOCK_LOCK   ::type_id::create("soc_ifc_reg_CPTRA_TRNG_PAUSER_LOCK_LOCK_cb"   );
+        soc_ifc_reg_CPTRA_TRNG_CTRL_CLEAR_cb           = soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_TRNG_CTRL_CLEAR         ::type_id::create("soc_ifc_reg_CPTRA_TRNG_CTRL_CLEAR_cb"         );
         soc_ifc_reg_CPTRA_TRNG_STATUS_DATA_REQ_cb      = soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_TRNG_STATUS_DATA_REQ    ::type_id::create("soc_ifc_reg_CPTRA_TRNG_STATUS_DATA_REQ_cb"    );
         soc_ifc_reg_CPTRA_TRNG_STATUS_DATA_WR_DONE_cb  = soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_TRNG_STATUS_DATA_WR_DONE::type_id::create("soc_ifc_reg_CPTRA_TRNG_STATUS_DATA_WR_DONE_cb");
         soc_ifc_reg_CPTRA_TRNG_VALID_PAUSER_PAUSER_cb  = soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_TRNG_VALID_PAUSER_PAUSER::type_id::create("soc_ifc_reg_CPTRA_TRNG_VALID_PAUSER_PAUSER_cb");
+        soc_ifc_reg_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART_cb = soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART::type_id::create("soc_ifc_reg_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART_cb");
+        soc_ifc_reg_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART_cb = soc_ifc_reg_cbs_soc_ifc_reg_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART::type_id::create("soc_ifc_reg_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART_cb");
+
+        soc_ifc_reg_secret_cb   = soc_ifc_reg_cbs_soc_ifc_reg_secret  ::type_id::create("soc_ifc_reg_secret_cb");
+        soc_ifc_reg_fuse_cb     = soc_ifc_reg_cbs_soc_ifc_reg_fuse    ::type_id::create("soc_ifc_reg_fuse_cb");
+        soc_ifc_reg_key_cb      = soc_ifc_reg_cbs_soc_ifc_reg_key     ::type_id::create("soc_ifc_reg_key_cb");
+        soc_ifc_reg_internal_cb = soc_ifc_reg_cbs_soc_ifc_reg_internal::type_id::create("soc_ifc_reg_internal_cb");
+        soc_ifc_reg_internal_fw_update_reset_cb = soc_ifc_reg_cbs_soc_ifc_reg_internal_fw_update_reset::type_id::create("soc_ifc_reg_internal_fw_update_reset_cb");
+
+        sha512_acc_csr_LOCK_LOCK_cb       = soc_ifc_reg_cbs_sha512_acc_csr_LOCK_LOCK::type_id::create("sha512_acc_csr_LOCK_LOCK_cb");
+        sha512_acc_csr_EXECUTE_EXECUTE_cb = soc_ifc_reg_cbs_sha512_acc_csr_EXECUTE_EXECUTE::type_id::create("sha512_acc_csr_EXECUTE_EXECUTE_cb");
+
+        sample_cb = soc_ifc_reg_cbs_sample::type_id::create("sample_cb");
 
         // Callbacks compute side-effects to other registers in the reg-model
         // in response to 'do_predict'.
@@ -684,6 +949,34 @@ package soc_ifc_reg_model_top_pkg;
         foreach (notif_sts_flds [ii]) uvm_reg_field_cb::add(notif_sts_flds [ii], soc_ifc_reg_intr_block_rf_ext_notif_internal_intr_r_base_cb);
         foreach (error_trig_flds[ii]) uvm_reg_field_cb::add(error_trig_flds[ii], soc_ifc_reg_intr_block_rf_ext_error_intr_trig_r_base_cb    );
         foreach (notif_trig_flds[ii]) uvm_reg_field_cb::add(notif_trig_flds[ii], soc_ifc_reg_intr_block_rf_ext_notif_intr_trig_r_base_cb    );
+        uvm_reg_field_cb::add(this.soc_ifc_reg_rm.intr_block_rf_ext.error_internal_intr_count_r                 .cnt, soc_ifc_reg_intr_block_rf_ext_internal_cb);
+        uvm_reg_field_cb::add(this.soc_ifc_reg_rm.intr_block_rf_ext.error_inv_dev_intr_count_r                  .cnt, soc_ifc_reg_intr_block_rf_ext_internal_cb);
+        uvm_reg_field_cb::add(this.soc_ifc_reg_rm.intr_block_rf_ext.error_cmd_fail_intr_count_r                 .cnt, soc_ifc_reg_intr_block_rf_ext_internal_cb);
+        uvm_reg_field_cb::add(this.soc_ifc_reg_rm.intr_block_rf_ext.error_bad_fuse_intr_count_r                 .cnt, soc_ifc_reg_intr_block_rf_ext_internal_cb);
+        uvm_reg_field_cb::add(this.soc_ifc_reg_rm.intr_block_rf_ext.error_iccm_blocked_intr_count_r             .cnt, soc_ifc_reg_intr_block_rf_ext_internal_cb);
+        uvm_reg_field_cb::add(this.soc_ifc_reg_rm.intr_block_rf_ext.error_mbox_ecc_unc_intr_count_r             .cnt, soc_ifc_reg_intr_block_rf_ext_internal_cb);
+        uvm_reg_field_cb::add(this.soc_ifc_reg_rm.intr_block_rf_ext.error_wdt_timer1_timeout_intr_count_r       .cnt, soc_ifc_reg_intr_block_rf_ext_internal_cb);
+        uvm_reg_field_cb::add(this.soc_ifc_reg_rm.intr_block_rf_ext.error_wdt_timer2_timeout_intr_count_r       .cnt, soc_ifc_reg_intr_block_rf_ext_internal_cb);
+        uvm_reg_field_cb::add(this.soc_ifc_reg_rm.intr_block_rf_ext.notif_cmd_avail_intr_count_r                .cnt, soc_ifc_reg_intr_block_rf_ext_internal_cb);
+        uvm_reg_field_cb::add(this.soc_ifc_reg_rm.intr_block_rf_ext.notif_mbox_ecc_cor_intr_count_r             .cnt, soc_ifc_reg_intr_block_rf_ext_internal_cb);
+        uvm_reg_field_cb::add(this.soc_ifc_reg_rm.intr_block_rf_ext.notif_debug_locked_intr_count_r             .cnt, soc_ifc_reg_intr_block_rf_ext_internal_cb);
+        uvm_reg_field_cb::add(this.soc_ifc_reg_rm.intr_block_rf_ext.notif_scan_mode_intr_count_r                .cnt, soc_ifc_reg_intr_block_rf_ext_internal_cb);
+        uvm_reg_field_cb::add(this.soc_ifc_reg_rm.intr_block_rf_ext.notif_soc_req_lock_intr_count_r             .cnt, soc_ifc_reg_intr_block_rf_ext_internal_cb);
+        uvm_reg_field_cb::add(this.soc_ifc_reg_rm.intr_block_rf_ext.notif_gen_in_toggle_intr_count_r            .cnt, soc_ifc_reg_intr_block_rf_ext_internal_cb);
+        uvm_reg_field_cb::add(this.soc_ifc_reg_rm.intr_block_rf_ext.error_internal_intr_count_incr_r          .pulse, soc_ifc_reg_intr_block_rf_ext_internal_cb);
+        uvm_reg_field_cb::add(this.soc_ifc_reg_rm.intr_block_rf_ext.error_inv_dev_intr_count_incr_r           .pulse, soc_ifc_reg_intr_block_rf_ext_internal_cb);
+        uvm_reg_field_cb::add(this.soc_ifc_reg_rm.intr_block_rf_ext.error_cmd_fail_intr_count_incr_r          .pulse, soc_ifc_reg_intr_block_rf_ext_internal_cb);
+        uvm_reg_field_cb::add(this.soc_ifc_reg_rm.intr_block_rf_ext.error_bad_fuse_intr_count_incr_r          .pulse, soc_ifc_reg_intr_block_rf_ext_internal_cb);
+        uvm_reg_field_cb::add(this.soc_ifc_reg_rm.intr_block_rf_ext.error_iccm_blocked_intr_count_incr_r      .pulse, soc_ifc_reg_intr_block_rf_ext_internal_cb);
+        uvm_reg_field_cb::add(this.soc_ifc_reg_rm.intr_block_rf_ext.error_mbox_ecc_unc_intr_count_incr_r      .pulse, soc_ifc_reg_intr_block_rf_ext_internal_cb);
+        uvm_reg_field_cb::add(this.soc_ifc_reg_rm.intr_block_rf_ext.error_wdt_timer1_timeout_intr_count_incr_r.pulse, soc_ifc_reg_intr_block_rf_ext_internal_cb);
+        uvm_reg_field_cb::add(this.soc_ifc_reg_rm.intr_block_rf_ext.error_wdt_timer2_timeout_intr_count_incr_r.pulse, soc_ifc_reg_intr_block_rf_ext_internal_cb);
+        uvm_reg_field_cb::add(this.soc_ifc_reg_rm.intr_block_rf_ext.notif_cmd_avail_intr_count_incr_r         .pulse, soc_ifc_reg_intr_block_rf_ext_internal_cb);
+        uvm_reg_field_cb::add(this.soc_ifc_reg_rm.intr_block_rf_ext.notif_mbox_ecc_cor_intr_count_incr_r      .pulse, soc_ifc_reg_intr_block_rf_ext_internal_cb);
+        uvm_reg_field_cb::add(this.soc_ifc_reg_rm.intr_block_rf_ext.notif_debug_locked_intr_count_incr_r      .pulse, soc_ifc_reg_intr_block_rf_ext_internal_cb);
+        uvm_reg_field_cb::add(this.soc_ifc_reg_rm.intr_block_rf_ext.notif_scan_mode_intr_count_incr_r         .pulse, soc_ifc_reg_intr_block_rf_ext_internal_cb);
+        uvm_reg_field_cb::add(this.soc_ifc_reg_rm.intr_block_rf_ext.notif_soc_req_lock_intr_count_incr_r      .pulse, soc_ifc_reg_intr_block_rf_ext_internal_cb);
+        uvm_reg_field_cb::add(this.soc_ifc_reg_rm.intr_block_rf_ext.notif_gen_in_toggle_intr_count_incr_r     .pulse, soc_ifc_reg_intr_block_rf_ext_internal_cb);
 
         /* -- sha512_acc_csr interrupts -- */
         uvm_reg_field_cb::add(sha512_acc_csr_rm.intr_block_rf_ext.global_intr_en_r.error_en, sha512_acc_csr_intr_block_rf_ext_global_intr_en_r_base_cb     );
@@ -706,23 +999,81 @@ package soc_ifc_reg_model_top_pkg;
         foreach (notif_sts_flds [ii]) uvm_reg_field_cb::add(notif_sts_flds [ii], sha512_acc_csr_intr_block_rf_ext_notif_internal_intr_r_base_cb);
         foreach (error_trig_flds[ii]) uvm_reg_field_cb::add(error_trig_flds[ii], sha512_acc_csr_intr_block_rf_ext_error_intr_trig_r_base_cb    );
         foreach (notif_trig_flds[ii]) uvm_reg_field_cb::add(notif_trig_flds[ii], sha512_acc_csr_intr_block_rf_ext_notif_intr_trig_r_base_cb    );
+        uvm_reg_field_cb::add(this.sha512_acc_csr_rm.intr_block_rf_ext.error0_intr_count_r                .cnt, sha512_acc_csr_intr_block_rf_ext_internal_cb);
+        uvm_reg_field_cb::add(this.sha512_acc_csr_rm.intr_block_rf_ext.error1_intr_count_r                .cnt, sha512_acc_csr_intr_block_rf_ext_internal_cb);
+        uvm_reg_field_cb::add(this.sha512_acc_csr_rm.intr_block_rf_ext.error2_intr_count_r                .cnt, sha512_acc_csr_intr_block_rf_ext_internal_cb);
+        uvm_reg_field_cb::add(this.sha512_acc_csr_rm.intr_block_rf_ext.error3_intr_count_r                .cnt, sha512_acc_csr_intr_block_rf_ext_internal_cb);
+        uvm_reg_field_cb::add(this.sha512_acc_csr_rm.intr_block_rf_ext.notif_cmd_done_intr_count_r        .cnt, sha512_acc_csr_intr_block_rf_ext_internal_cb);
+        uvm_reg_field_cb::add(this.sha512_acc_csr_rm.intr_block_rf_ext.error0_intr_count_incr_r         .pulse, sha512_acc_csr_intr_block_rf_ext_internal_cb);
+        uvm_reg_field_cb::add(this.sha512_acc_csr_rm.intr_block_rf_ext.error1_intr_count_incr_r         .pulse, sha512_acc_csr_intr_block_rf_ext_internal_cb);
+        uvm_reg_field_cb::add(this.sha512_acc_csr_rm.intr_block_rf_ext.error2_intr_count_incr_r         .pulse, sha512_acc_csr_intr_block_rf_ext_internal_cb);
+        uvm_reg_field_cb::add(this.sha512_acc_csr_rm.intr_block_rf_ext.error3_intr_count_incr_r         .pulse, sha512_acc_csr_intr_block_rf_ext_internal_cb);
+        uvm_reg_field_cb::add(this.sha512_acc_csr_rm.intr_block_rf_ext.notif_cmd_done_intr_count_incr_r .pulse, sha512_acc_csr_intr_block_rf_ext_internal_cb);
 
         /* -- mbox_csr -- */
-        uvm_reg_field_cb::add(mbox_csr_rm.mbox_lock   .lock      , mbox_csr_mbox_lock_lock_cb       );
-        uvm_reg_field_cb::add(mbox_csr_rm.mbox_cmd    .command   , mbox_csr_mbox_cmd_command_cb     );
-        uvm_reg_field_cb::add(mbox_csr_rm.mbox_dlen   .length    , mbox_csr_mbox_dlen_length_cb     );
-        uvm_reg_field_cb::add(mbox_csr_rm.mbox_datain .datain    , mbox_csr_mbox_datain_datain_cb   );
-        uvm_reg_field_cb::add(mbox_csr_rm.mbox_dataout.dataout   , mbox_csr_mbox_dataout_dataout_cb );
-        uvm_reg_field_cb::add(mbox_csr_rm.mbox_status .status    , mbox_csr_mbox_status_status_cb   );
-        uvm_reg_field_cb::add(mbox_csr_rm.mbox_execute.execute   , mbox_csr_mbox_execute_execute_cb );
-        uvm_reg_field_cb::add(mbox_csr_rm.mbox_unlock .unlock    , mbox_csr_mbox_unlock_unlock_cb   );
+        uvm_reg_field_cb::add(mbox_csr_rm.mbox_lock   .lock       , mbox_csr_mbox_lock_lock_cb         );
+        uvm_reg_field_cb::add(mbox_csr_rm.mbox_cmd    .command    , mbox_csr_mbox_cmd_command_cb       );
+        uvm_reg_field_cb::add(mbox_csr_rm.mbox_dlen   .length     , mbox_csr_mbox_dlen_length_cb       );
+        uvm_reg_field_cb::add(mbox_csr_rm.mbox_datain .datain     , mbox_csr_mbox_datain_datain_cb     );
+        uvm_reg_field_cb::add(mbox_csr_rm.mbox_dataout.dataout    , mbox_csr_mbox_dataout_dataout_cb   );
+        uvm_reg_field_cb::add(mbox_csr_rm.mbox_status .status     , mbox_csr_mbox_status_status_cb     );
+        uvm_reg_field_cb::add(mbox_csr_rm.mbox_status .mbox_fsm_ps, mbox_csr_mbox_status_mbox_fsm_ps_cb);
+        uvm_reg_field_cb::add(mbox_csr_rm.mbox_execute.execute    , mbox_csr_mbox_execute_execute_cb   );
+        uvm_reg_field_cb::add(mbox_csr_rm.mbox_unlock .unlock     , mbox_csr_mbox_unlock_unlock_cb     );
 
         /* -- soc_ifc_reg -- */
+        soc_ifc_reg_rm.CPTRA_HW_ERROR_FATAL    .get_fields(cptra_fatal_flds    );
+        soc_ifc_reg_rm.CPTRA_HW_ERROR_NON_FATAL.get_fields(cptra_non_fatal_flds);
+        foreach (cptra_fatal_flds    [ii]) if (cptra_fatal_flds    [ii].get_name() == "rsvd") cptra_fatal_flds    .delete(ii);
+        foreach (cptra_non_fatal_flds[ii]) if (cptra_non_fatal_flds[ii].get_name() == "rsvd") cptra_non_fatal_flds.delete(ii);
+
+        foreach (cptra_fatal_flds    [ii])           uvm_reg_field_cb::add(cptra_fatal_flds    [ii]               , soc_ifc_reg_CPTRA_HW_ERROR_FATAL_cb    );
+        foreach (cptra_non_fatal_flds[ii])           uvm_reg_field_cb::add(cptra_non_fatal_flds[ii]               , soc_ifc_reg_CPTRA_HW_ERROR_NON_FATAL_cb);
+        uvm_reg_field_cb::add(soc_ifc_reg_rm.CPTRA_BOOT_STATUS.status             , soc_ifc_reg_internal_cb                       );
         foreach (soc_ifc_reg_rm.CPTRA_TRNG_DATA[ii]) uvm_reg_field_cb::add(soc_ifc_reg_rm.CPTRA_TRNG_DATA[ii].DATA, soc_ifc_reg_CPTRA_TRNG_DATA_DATA_cb);
         uvm_reg_field_cb::add(soc_ifc_reg_rm.CPTRA_TRNG_PAUSER_LOCK  .LOCK        , soc_ifc_reg_CPTRA_TRNG_PAUSER_LOCK_LOCK_cb    );
         uvm_reg_field_cb::add(soc_ifc_reg_rm.CPTRA_TRNG_STATUS       .DATA_REQ    , soc_ifc_reg_CPTRA_TRNG_STATUS_DATA_REQ_cb     );
         uvm_reg_field_cb::add(soc_ifc_reg_rm.CPTRA_TRNG_STATUS       .DATA_WR_DONE, soc_ifc_reg_CPTRA_TRNG_STATUS_DATA_WR_DONE_cb );
         uvm_reg_field_cb::add(soc_ifc_reg_rm.CPTRA_TRNG_VALID_PAUSER .PAUSER      , soc_ifc_reg_CPTRA_TRNG_VALID_PAUSER_PAUSER_cb );
+        uvm_reg_field_cb::add(soc_ifc_reg_rm.CPTRA_TRNG_CTRL         .clear       , soc_ifc_reg_CPTRA_TRNG_CTRL_CLEAR_cb );
+        uvm_reg_field_cb::add(soc_ifc_reg_rm.CPTRA_WDT_TIMER1_CTRL   .timer1_restart, soc_ifc_reg_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART_cb );
+        uvm_reg_field_cb::add(soc_ifc_reg_rm.CPTRA_WDT_TIMER2_CTRL   .timer2_restart, soc_ifc_reg_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART_cb );
+
+        foreach (soc_ifc_reg_rm.fuse_uds_seed[ii])             uvm_reg_field_cb::add(soc_ifc_reg_rm.fuse_uds_seed[ii].seed             , soc_ifc_reg_secret_cb);
+        foreach (soc_ifc_reg_rm.fuse_field_entropy[ii])        uvm_reg_field_cb::add(soc_ifc_reg_rm.fuse_field_entropy[ii].seed        , soc_ifc_reg_secret_cb);
+        foreach (soc_ifc_reg_rm.fuse_key_manifest_pk_hash[ii]) uvm_reg_field_cb::add(soc_ifc_reg_rm.fuse_key_manifest_pk_hash[ii].hash , soc_ifc_reg_fuse_cb);
+                                                               uvm_reg_field_cb::add(soc_ifc_reg_rm.fuse_key_manifest_pk_hash_mask.mask, soc_ifc_reg_fuse_cb);
+        foreach (soc_ifc_reg_rm.fuse_owner_pk_hash[ii])        uvm_reg_field_cb::add(soc_ifc_reg_rm.fuse_owner_pk_hash[ii].hash        , soc_ifc_reg_fuse_cb);
+                                                               uvm_reg_field_cb::add(soc_ifc_reg_rm.fuse_fmc_key_manifest_svn.svn      , soc_ifc_reg_fuse_cb);
+        foreach (soc_ifc_reg_rm.fuse_runtime_svn[ii])          uvm_reg_field_cb::add(soc_ifc_reg_rm.fuse_runtime_svn[ii].svn           , soc_ifc_reg_fuse_cb);
+                                                               uvm_reg_field_cb::add(soc_ifc_reg_rm.fuse_anti_rollback_disable.dis     , soc_ifc_reg_fuse_cb);
+        foreach (soc_ifc_reg_rm.fuse_idevid_cert_attr[ii])     uvm_reg_field_cb::add(soc_ifc_reg_rm.fuse_idevid_cert_attr[ii].cert     , soc_ifc_reg_fuse_cb);
+        foreach (soc_ifc_reg_rm.fuse_idevid_manuf_hsm_id[ii])  uvm_reg_field_cb::add(soc_ifc_reg_rm.fuse_idevid_manuf_hsm_id[ii].hsm_id, soc_ifc_reg_fuse_cb);
+                                                               uvm_reg_field_cb::add(soc_ifc_reg_rm.fuse_life_cycle.life_cycle         , soc_ifc_reg_fuse_cb);
+                                                               uvm_reg_field_cb::add(soc_ifc_reg_rm.fuse_lms_verify.lms_verify         , soc_ifc_reg_fuse_cb);
+                                                               uvm_reg_field_cb::add(soc_ifc_reg_rm.fuse_lms_revocation.lms_revocation , soc_ifc_reg_fuse_cb);
+                                                               uvm_reg_field_cb::add(soc_ifc_reg_rm.fuse_soc_stepping_id.soc_stepping_id, soc_ifc_reg_fuse_cb);
+        foreach (soc_ifc_reg_rm.internal_obf_key[ii])          uvm_reg_field_cb::add(soc_ifc_reg_rm.internal_obf_key[ii].key           , soc_ifc_reg_key_cb);
+                                                               uvm_reg_field_cb::add(soc_ifc_reg_rm.internal_iccm_lock.lock            , soc_ifc_reg_internal_cb);
+                                                               uvm_reg_field_cb::add(soc_ifc_reg_rm.internal_fw_update_reset.core_rst  , soc_ifc_reg_internal_fw_update_reset_cb) ;
+                                                               uvm_reg_field_cb::add(soc_ifc_reg_rm.internal_rv_mtime_l.count_l        , soc_ifc_reg_internal_cb);
+                                                               uvm_reg_field_cb::add(soc_ifc_reg_rm.internal_rv_mtime_h.count_h        , soc_ifc_reg_internal_cb);
+                                                               uvm_reg_field_cb::add(soc_ifc_reg_rm.internal_rv_mtimecmp_l.compare_l   , soc_ifc_reg_internal_cb);
+                                                               uvm_reg_field_cb::add(soc_ifc_reg_rm.internal_rv_mtimecmp_h.compare_h   , soc_ifc_reg_internal_cb);
+        /* -- sha512_acc_csr -- */
+        uvm_reg_field_cb::add(sha512_acc_csr_rm.LOCK.LOCK, sha512_acc_csr_LOCK_LOCK_cb);
+        uvm_reg_field_cb::add(sha512_acc_csr_rm.EXECUTE.EXECUTE, sha512_acc_csr_EXECUTE_EXECUTE_cb);
+
+        /* -- Coverage sampling callback for all registers */
+        // Add this callback after all other callbacks so it runs AFTER the prediction is finalized
+        get_registers(all_regs, UVM_HIER);
+        foreach (all_regs[ii]) begin
+            all_fields.delete();
+            all_regs[ii].get_fields(all_fields);
+            foreach (all_fields[jj]) begin
+                uvm_reg_field_cb::add(all_fields[jj], sample_cb);
+            end
+        end
 
 // pragma uvmf custom construct_configure_build_registers_within_block end
 // pragma uvmf custom add_registers_to_block_map begin
@@ -762,6 +1113,7 @@ package soc_ifc_reg_model_top_pkg;
         this.soc_ifc_AHB_map.add_submap(this.sha512_acc_csr_rm.sha512_acc_csr_AHB_map, 'h2_1000);
         this.soc_ifc_AHB_map.add_submap(this.soc_ifc_reg_rm.soc_ifc_reg_AHB_map, 'h3_0000);
 
+        void'(set_coverage(get_coverage() | UVM_CVR_REG_BITS | UVM_CVR_FIELD_VALS));
 // pragma uvmf custom add_registers_to_block_map end
 
 
@@ -771,8 +1123,11 @@ package soc_ifc_reg_model_top_pkg;
       //
       function void sample(uvm_reg_addr_t offset, bit is_read, uvm_reg_map  map);
          if(get_coverage(UVM_CVR_ADDR_MAP)) begin
-            if(map.get_name() == "fixme_map_cg") begin
-               fixme_map_cg.sample(offset, is_read);
+            if(map.get_name() == "soc_ifc_AHB_map") begin
+               AHB_map_cg.sample(offset, is_read);
+            end
+            if(map.get_name() == "soc_ifc_APB_map") begin
+               APB_map_cg.sample(offset, is_read);
             end
          end
       endfunction: sample
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/bringup/cptra/soc_ifc_env_cptra_init_interrupts_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/bringup/cptra/soc_ifc_env_cptra_init_interrupts_sequence.svh
new file mode 100644
index 000000000..e830f1173
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/bringup/cptra/soc_ifc_env_cptra_init_interrupts_sequence.svh
@@ -0,0 +1,87 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Sequence to initialize Caliptra SOC_IFC interrupts
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_cptra_init_interrupts_sequence extends soc_ifc_env_sequence_base #(.CONFIG_T(soc_ifc_env_configuration_t));
+
+
+  `uvm_object_utils( soc_ifc_env_cptra_init_interrupts_sequence );
+
+
+  uvm_status_e reg_sts;
+
+  function new(string name = "" );
+    super.new(name);
+
+  endfunction
+
+  virtual task body();
+
+    uvm_reg_data_t data;
+    uvm_reg_field flds[$];
+    int sts_rsp_count = 0;
+    reg_model = configuration.soc_ifc_rm;
+
+    if (cptra_status_agent_rsp_seq == null)
+        `uvm_fatal("CPTRA_INIT_INTR", "SOC_IFC ENV caliptra reset wait sequence expected a handle to the cptra status agent responder sequence (from bench-level sequence) but got null!")
+    fork
+        forever begin
+            @(cptra_status_agent_rsp_seq.new_rsp) sts_rsp_count++;
+        end
+    join_none
+
+    // Clear debug locked interrupt 
+    data = (uvm_reg_data_t'(1) << reg_model.soc_ifc_reg_rm.intr_block_rf_ext.notif_internal_intr_r.notif_debug_locked_sts.get_lsb_pos());
+    reg_model.soc_ifc_reg_rm.intr_block_rf_ext.notif_internal_intr_r.write(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
+
+    // Interrupt Enable (Global)
+    data = (uvm_reg_data_t'(1) << reg_model.soc_ifc_reg_rm.intr_block_rf_ext.global_intr_en_r.error_en.get_lsb_pos()) |
+           (uvm_reg_data_t'(1) << reg_model.soc_ifc_reg_rm.intr_block_rf_ext.global_intr_en_r.notif_en.get_lsb_pos());
+    reg_model.soc_ifc_reg_rm.intr_block_rf_ext.global_intr_en_r.write(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
+    if (reg_sts != UVM_IS_OK)
+        `uvm_error("CPTRA_INIT_INTR", $sformatf("Register access failed (%s)", "global_intr_en_r"))
+
+    // Interrupt Enable (Errors)
+    reg_model.soc_ifc_reg_rm.intr_block_rf_ext.error_intr_en_r.get_fields(flds);
+    data = 0;
+    foreach (flds[ii]) data |= (uvm_reg_data_t'(1) << flds[ii].get_lsb_pos());
+    flds.delete();
+    reg_model.soc_ifc_reg_rm.intr_block_rf_ext.error_intr_en_r.write(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
+    if (reg_sts != UVM_IS_OK)
+        `uvm_error("CPTRA_INIT_INTR", $sformatf("Register access failed (%s)", "error_intr_en_r"))
+
+    // Interrupt Enable (Notifications)
+    reg_model.soc_ifc_reg_rm.intr_block_rf_ext.notif_intr_en_r.get_fields(flds);
+    data = 0;
+    foreach (flds[ii]) data |= (uvm_reg_data_t'(1) << flds[ii].get_lsb_pos());
+    flds.delete();
+    reg_model.soc_ifc_reg_rm.intr_block_rf_ext.notif_intr_en_r.write(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
+    if (reg_sts != UVM_IS_OK)
+        `uvm_error("CPTRA_INIT_INTR", $sformatf("Register access failed (%s)", "notif_intr_en_r"))
+
+  endtask
+
+endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/bringup/soc_ifc/soc_ifc_env_reset_sequence_base.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/bringup/soc_ifc/soc_ifc_env_reset_sequence_base.svh
index 85fc555b1..5253bd642 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/bringup/soc_ifc/soc_ifc_env_reset_sequence_base.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/bringup/soc_ifc/soc_ifc_env_reset_sequence_base.svh
@@ -36,14 +36,24 @@ class soc_ifc_env_reset_sequence_base extends soc_ifc_env_sequence_base #(.CONFI
   caliptra_apb_user apb_user_obj;
 
   typedef struct packed {
-      bit set_bootfsm_breakpoint;
+      bit              set_bootfsm_breakpoint;
+      security_state_t security_state;
   } ctrl_reset_seq_context_t;
 
   rand uvm_reg_data_t uds_seed_rand      [12];
   rand uvm_reg_data_t field_entropy_rand [32];
+  rand uvm_reg_data_t owner_pk_hash_rand [12];
+  rand uvm_reg_data_t key_manifest_pk_hash_rand [12];
+  rand uvm_reg_data_t idevid_cert_attr_rand [24];
+  rand uvm_reg_data_t soc_stepping_id_rand;
   rand struct packed {
     bit uds;
     bit field_entropy;
+    bit [0:11] key_manifest_pk_hash;
+    bit [0:11] owner_pk_hash;
+    bit soc_stepping_id;
+    bit [0:23] idevid_cert_attr;
+    bit lms_verify;
   } fuses_to_set;
 
 
@@ -71,6 +81,8 @@ class soc_ifc_env_reset_sequence_base extends soc_ifc_env_sequence_base #(.CONFI
     else
         `uvm_error("SOC_IFC_RST", "soc_ifc_ctrl_agent_config.sequencer is null!")
     ctx.set_bootfsm_breakpoint = soc_ifc_ctrl_seq.set_bootfsm_breakpoint;
+    ctx.security_state         = soc_ifc_ctrl_seq.security_state;
+
   endtask
 
 
@@ -90,16 +102,18 @@ class soc_ifc_env_reset_sequence_base extends soc_ifc_env_sequence_base #(.CONFI
         end
     join_none
 
-    wait(sts_rsp_count > 0);
-    `uvm_info("SOC_IFC_RST", "Received response from status agent", UVM_MEDIUM)
-    if (sts_rsp_count > 1)
-        `uvm_error("SOC_IFC_RST", "Missed response activity during reset sequence")
-    fuse_ready = soc_ifc_status_agent_rsp_seq.rsp.ready_for_fuses;
-    sts_rsp_count--;
-    if (!fuse_ready)
-        `uvm_error("SOC_IFC_RST", "Unexpected status transition while waiting for Mailbox readiness for fuses")
-    else
-        `uvm_info("SOC_IFC_RST", "Fuse ready, initiating fuse download", UVM_LOW)
+    while (!fuse_ready) begin
+        wait(sts_rsp_count > 0);
+        `uvm_info("SOC_IFC_RST", "Received response from status agent", UVM_MEDIUM)
+        if (sts_rsp_count > 1)
+            `uvm_error("SOC_IFC_RST", "Missed response activity during reset sequence")
+        fuse_ready = soc_ifc_status_agent_rsp_seq.rsp.ready_for_fuses;
+        sts_rsp_count--;
+        if (!fuse_ready)
+            `uvm_info("SOC_IFC_RST", "Received status transition while waiting for Mailbox ready_for_fuses, ready_for_fuses still not set", UVM_MEDIUM)
+        else
+            `uvm_info("SOC_IFC_RST", $sformatf("Fuse ready, initiating fuse download with fuses_to_set: [%p]", this.fuses_to_set), UVM_LOW)
+    end
 
     // Write UDS
     if (this.fuses_to_set.uds) begin
@@ -119,6 +133,48 @@ class soc_ifc_env_reset_sequence_base extends soc_ifc_env_sequence_base #(.CONFI
         end
     end
 
+    // Key Manifest PK Hash (Vendor)
+    foreach (this.fuses_to_set.key_manifest_pk_hash[ii]) begin
+        if (this.fuses_to_set.key_manifest_pk_hash[ii]) begin
+            `uvm_info("SOC_IFC_RST", $sformatf("Writing Key Manifest PK Hash [%d] to fuse bank with value 0x%0x", ii, key_manifest_pk_hash_rand[ii]), UVM_LOW)
+            reg_model.soc_ifc_reg_rm.fuse_key_manifest_pk_hash[ii].write(sts, key_manifest_pk_hash_rand[ii], UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(apb_user_obj));
+            if (sts != UVM_IS_OK) `uvm_error("SOC_IFC_RST", $sformatf("Failed when writing to Key Manifest PK Hash [%d]", ii))
+        end
+    end
+
+    // Owner PK Hash
+    foreach (this.fuses_to_set.owner_pk_hash[ii]) begin
+        if (this.fuses_to_set.owner_pk_hash[ii]) begin
+            `uvm_info("SOC_IFC_RST", $sformatf("Writing Owner PK Hash [%d] to fuse bank with value 0x%0x", ii, owner_pk_hash_rand[ii]), UVM_LOW)
+            reg_model.soc_ifc_reg_rm.fuse_owner_pk_hash[ii].write(sts, owner_pk_hash_rand[ii], UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(apb_user_obj));
+            if (sts != UVM_IS_OK) `uvm_error("SOC_IFC_RST", $sformatf("Failed when writing to Owner PK Hash [%d]", ii))
+        end
+    end
+
+    // Write SoC Stepping ID
+    if (this.fuses_to_set.soc_stepping_id) begin
+      `uvm_info("SOC_IFC_RST", "Writing SOC Stepping ID to fuse bank", UVM_LOW)
+      reg_model.soc_ifc_reg_rm.fuse_soc_stepping_id.write(sts, {16'h0, soc_stepping_id_rand[15:0]}, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(apb_user_obj));
+      if (sts != UVM_IS_OK) `uvm_error("SOC_IFC_RST", "Failed when writing to soc_stepping_id")
+    end
+
+    // iDevID Cert Attr
+    foreach (this.fuses_to_set.idevid_cert_attr[ii]) begin
+        if (this.fuses_to_set.idevid_cert_attr[ii]) begin
+            `uvm_info("SOC_IFC_RST", $sformatf("Writing iDevID Certificate Attribute [%d] to fuse bank", ii), UVM_LOW)
+            reg_model.soc_ifc_reg_rm.fuse_idevid_cert_attr[ii].write(sts, idevid_cert_attr_rand[ii], UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(apb_user_obj));
+            if (sts != UVM_IS_OK) `uvm_error("SOC_IFC_RST", $sformatf("Failed when writing to iDevID Certificate Attribute [%d]", ii))
+        end
+    end
+
+    // Write LMS Verify Bit
+    if (this.fuses_to_set.lms_verify) begin
+      uvm_reg_data_t lms_verify_data = 1 << reg_model.soc_ifc_reg_rm.fuse_lms_verify.lms_verify.get_lsb_pos();
+      `uvm_info("SOC_IFC_RST", "Writing LMS Verify=1 to fuse bank", UVM_LOW)
+      reg_model.soc_ifc_reg_rm.fuse_lms_verify.write(sts, lms_verify_data, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(apb_user_obj));
+      if (sts != UVM_IS_OK) `uvm_error("SOC_IFC_RST", "Failed when writing to lms_verify")
+    end
+
     // Set Fuse Done
     reg_model.soc_ifc_reg_rm.CPTRA_FUSE_WR_DONE.write(sts, `UVM_REG_DATA_WIDTH'(1), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(apb_user_obj));
     `uvm_info("SOC_IFC_RST", $sformatf("Fuse download completed, status: %p", sts), UVM_MEDIUM)
@@ -132,14 +188,31 @@ class soc_ifc_env_reset_sequence_base extends soc_ifc_env_sequence_base #(.CONFI
   //==========================================
   virtual task configure_breakpoint(input ctrl_reset_seq_context_t ctrl_rst_ctx);
     uvm_status_e sts;
+    uvm_reg_data_t data;
+    uvm_reg_data_t data_mask;
+    uvm_reg_data_t data_check;
+
+    //create a mask for the read data, just for boot_fsm_ps
+    data_mask = (1 << reg_model.soc_ifc_reg_rm.CPTRA_FLOW_STATUS.boot_fsm_ps.get_n_bits()) - 1;
+    data_mask <<= reg_model.soc_ifc_reg_rm.CPTRA_FLOW_STATUS.boot_fsm_ps.get_lsb_pos();
+    //create a valid data for checking that matches masked read data
+    data_check = BOOT_WAIT << reg_model.soc_ifc_reg_rm.CPTRA_FLOW_STATUS.boot_fsm_ps.get_lsb_pos();
+
     // If set_bootfsm_breakpoint is randomized to 1, we need to release bootfsm by writing GO
-    if (ctrl_rst_ctx.set_bootfsm_breakpoint) begin
-        `uvm_info("SOC_IFC_RST", "BootFSM Breakpoint is set, writing GO", UVM_MEDIUM)
-        reg_model.soc_ifc_reg_rm.CPTRA_BOOTFSM_GO.write(sts, `UVM_REG_DATA_WIDTH'(1), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(apb_user_obj));
-        `uvm_info("SOC_IFC_RST", $sformatf("Write to BootFSM GO completed, status: %p", sts), UVM_MEDIUM)
+    // bootfsm_breakpoint is qualified by debug mode and device_lifecycle, so incorporate that here
+    if (ctrl_rst_ctx.set_bootfsm_breakpoint && (!ctrl_rst_ctx.security_state.debug_locked || (ctrl_rst_ctx.security_state.debug_locked && ctrl_rst_ctx.security_state.device_lifecycle == DEVICE_MANUFACTURING))) begin
+      //Poll boot status until we are in FSM state BOOT_WAIT
+      reg_model.soc_ifc_reg_rm.CPTRA_FLOW_STATUS.read(sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(apb_user_obj));
+      while ((data & data_mask) != data_check) begin
+        configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(20);
+        reg_model.soc_ifc_reg_rm.CPTRA_FLOW_STATUS.read(sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(apb_user_obj));
+      end
+      `uvm_info("SOC_IFC_RST", "BootFSM Breakpoint is set, writing GO", UVM_MEDIUM)
+      reg_model.soc_ifc_reg_rm.CPTRA_BOOTFSM_GO.write(sts, `UVM_REG_DATA_WIDTH'(1), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(apb_user_obj));
+      `uvm_info("SOC_IFC_RST", $sformatf("Write to BootFSM GO completed, status: %p", sts), UVM_MEDIUM)
     end
     else begin
-        `uvm_info("SOC_IFC_RST", "BootFSM Breakpoint not set, reset sequence complete", UVM_MEDIUM)
+        `uvm_info("SOC_IFC_RST", "BootFSM Breakpoint not set (or disabled based on security_state), reset sequence complete", UVM_MEDIUM)
     end
 
   endtask
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/bringup/soc_ifc/soc_ifc_env_rom_bringup_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/bringup/soc_ifc/soc_ifc_env_rom_bringup_sequence.svh
new file mode 100644
index 000000000..ac1f522f8
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/bringup/soc_ifc/soc_ifc_env_rom_bringup_sequence.svh
@@ -0,0 +1,85 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Bringup sequence for the SOC_IFC environment
+//              (essentially just a cold-reset sequence)
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_rom_bringup_sequence extends soc_ifc_env_reset_sequence_base;
+
+
+  `uvm_object_utils( soc_ifc_env_rom_bringup_sequence )
+
+  typedef soc_ifc_ctrl_rom_poweron_sequence soc_ifc_ctrl_agent_poweron_sequence_t;
+
+  // Decide which fuses to initialize
+  constraint always_set_uds_c { this.fuses_to_set.uds == 1'b1; }
+  constraint always_set_fe_c  { this.fuses_to_set.field_entropy == 1'b1; }
+  // Roughly once per week, assuming the nightly Directed regression isn't running every day (since it is triggered by a PR)
+  constraint infrequently_set_lms_verify_c { this.fuses_to_set.lms_verify dist {0 :/ 4, 1 :/ 1}; }
+  constraint always_set_key_manifest_pk_hash_c { this.fuses_to_set.key_manifest_pk_hash == {12{1'b1}}; }
+  constraint always_set_owner_pk_hash_c { this.fuses_to_set.owner_pk_hash == {12{1'b1}}; }
+  constraint always_set_idevid_c  { this.fuses_to_set.idevid_cert_attr[0] == 1'b1;
+                                    this.fuses_to_set.idevid_cert_attr[6] == 1'b1;
+                                    this.fuses_to_set.idevid_cert_attr[7] == 1'b1; }
+  // Configure the values to set to initialized fuses
+  constraint key_manifest_pk_hash_values_c { key_manifest_pk_hash_rand[0]  == 32'h6DC8DE16;
+                                             key_manifest_pk_hash_rand[1]  == 32'hD559D129;
+                                             key_manifest_pk_hash_rand[2]  == 32'h7BAB1E43;
+                                             key_manifest_pk_hash_rand[3]  == 32'hEBD7C533;
+                                             key_manifest_pk_hash_rand[4]  == 32'hDFE57001;
+                                             key_manifest_pk_hash_rand[5]  == 32'h1AA56220;
+                                             key_manifest_pk_hash_rand[6]  == 32'h0F66AD6D;
+                                             key_manifest_pk_hash_rand[7]  == 32'h87051086;
+                                             key_manifest_pk_hash_rand[8]  == 32'hC785E930;
+                                             key_manifest_pk_hash_rand[9]  == 32'hD3D947B4;
+                                             key_manifest_pk_hash_rand[10] == 32'h7495822E;
+                                             key_manifest_pk_hash_rand[11] == 32'hCB643FF1;
+                                             solve this.fuses_to_set before this.key_manifest_pk_hash_rand; }
+  constraint owner_pk_hash_values_c { owner_pk_hash_rand[0]  == 32'hF58D4920;
+                                      owner_pk_hash_rand[1]  == 32'hBA65DA44;
+                                      owner_pk_hash_rand[2]  == 32'hB0F728BC;
+                                      owner_pk_hash_rand[3]  == 32'hFB893202;
+                                      owner_pk_hash_rand[4]  == 32'hCFAAA942;
+                                      owner_pk_hash_rand[5]  == 32'hBC66A0C0;
+                                      owner_pk_hash_rand[6]  == 32'h007A2CE2;
+                                      owner_pk_hash_rand[7]  == 32'h29A8E08F;
+                                      owner_pk_hash_rand[8]  == 32'h9E8EEBAE;
+                                      owner_pk_hash_rand[9]  == 32'hB36E9CC0;
+                                      owner_pk_hash_rand[10] == 32'h962E4B7A;
+                                      owner_pk_hash_rand[11] == 32'h50214999;
+                                      solve this.fuses_to_set before this.owner_pk_hash_rand; }
+  constraint idevid_values_c { idevid_cert_attr_rand[0] == '0; /* SHA1 */
+                               idevid_cert_attr_rand[6] == 32'hFFFF_FFFF; /* UEID LSWord */
+                               idevid_cert_attr_rand[7] == 32'hFFFF_FFFF; /* MSWord */}
+
+  function new(string name = "" );
+    uvm_object obj;
+    super.new(name);
+    obj = soc_ifc_ctrl_agent_poweron_sequence_t::get_type().create_object("soc_ifc_ctrl_agent_poweron_seq");
+    if (!$cast(soc_ifc_ctrl_seq,obj))
+        `uvm_fatal("SOC_IFC_BRINGUP", "Failed to cast object as poweron sequence!")
+  endfunction
+
+endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_dlen_overread_handler_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_dlen_overread_handler_sequence.svh
index 8ff817a80..67ee7411b 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_dlen_overread_handler_sequence.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_dlen_overread_handler_sequence.svh
@@ -45,8 +45,9 @@ task soc_ifc_env_cptra_mbox_dlen_overread_handler_sequence::mbox_pop_dataout();
     int unsigned overrun_bytes;
     uvm_reg_data_t data;
 
-    if (!std::randomize(overrun_bytes) with {overrun_bytes + op.dlen <= (reg_model.mbox_mem_rm.get_size() * reg_model.mbox_mem_rm.get_n_bytes()); overrun_bytes < op.dlen * 4;})
-        `uvm_error("CPTRA_MBOX_HANDLER", "Failed to randomize overrun bytes")
+    if (!std::randomize(overrun_bytes) with {overrun_bytes >= 4; //always overrun by at least 1 dword
+                                             overrun_bytes <= (op.dlen+1)*4;}) //overrun small dlens by smaller amounts
+            `uvm_error("CPTRA_MBOX_HANDLER", "Failed to randomize overrun bytes")
     else
         `uvm_info("CPTRA_MBOX_HANDLER", $sformatf("Randomized overrun bytes to %d", overrun_bytes), UVM_MEDIUM)
 
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_dlen_underread_handler_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_dlen_underread_handler_sequence.svh
index 0068d5cdd..2a12920a0 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_dlen_underread_handler_sequence.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_dlen_underread_handler_sequence.svh
@@ -43,15 +43,25 @@ endclass
 task soc_ifc_env_cptra_mbox_dlen_underread_handler_sequence::mbox_pop_dataout();
     int ii;
     int unsigned underrun_bytes;
+    int unsigned bytes_to_read;
     uvm_reg_data_t data;
 
     // minimum 5 bytes so we can grab the resp dlen
-    if (!std::randomize(underrun_bytes) with {underrun_bytes < op.dlen - 4;})
+    if (!std::randomize(underrun_bytes) with {if (op.dlen > 4) underrun_bytes < op.dlen - 4;
+                                              else             underrun_bytes == 0;})
         `uvm_error("CPTRA_MBOX_HANDLER", "Failed to randomize overrun bytes")
     else
         `uvm_info("CPTRA_MBOX_HANDLER", $sformatf("Randomized underrun bytes to %d", underrun_bytes), UVM_MEDIUM)
 
-    for (ii=0; ii < op.dlen-underrun_bytes; ii+=4) begin
+    bytes_to_read = op.dlen-underrun_bytes;
+    if (bytes_to_read > 32'h8000_0000) begin
+        `uvm_warning("MBOX_SEQ", $sformatf("Bytes to read is calculated as a huge number - was this intentional? bytes_to_read: %d (0x%x)", bytes_to_read, bytes_to_read))
+    end
+    else begin
+        `uvm_info("MBOX_SEQ", $sformatf("Bytes to read is calculated as %d (0x%x)", bytes_to_read, bytes_to_read), UVM_HIGH)
+    end
+
+    for (ii=0; ii < bytes_to_read; ii+=4) begin
         reg_model.mbox_csr_rm.mbox_dataout.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
         if (reg_sts != UVM_IS_OK)
             `uvm_error("MBOX_SEQ", "Register access failed (mbox_dataout)")
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_handler_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_handler_sequence.svh
index 8d33810d9..608f241e2 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_handler_sequence.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_handler_sequence.svh
@@ -31,6 +31,9 @@ class soc_ifc_env_cptra_mbox_handler_sequence extends soc_ifc_env_sequence_base
 
   `uvm_object_utils( soc_ifc_env_cptra_mbox_handler_sequence )
 
+  int sts_rsp_count = 0;
+  int ntf_rsp_count = 0;
+  int err_rsp_count = 0;
   mbox_op_s op;
   int mbox_resp_expected_dlen = 0; // Number of response data bytes to provide
   uvm_status_e reg_sts;
@@ -38,9 +41,11 @@ class soc_ifc_env_cptra_mbox_handler_sequence extends soc_ifc_env_sequence_base
   rand longint unsigned force_unlock_delay_cycles;
 
   bit unlock_proc_active = 1'b0;
+  bit op_active = 1'b0;
   bit seq_done = 1'b0;
   uvm_event in_report_reg_sts;
 
+  extern virtual task handler_setup();
   extern virtual task mbox_wait_for_command(output op_sts_e op_sts);
   extern virtual task mbox_get_command();
   extern virtual task mbox_pop_dataout();
@@ -91,7 +96,6 @@ class soc_ifc_env_cptra_mbox_handler_sequence extends soc_ifc_env_sequence_base
   //==========================================
   virtual task body();
 
-    int sts_rsp_count = 0;
     op_sts_e op_sts;
     reg_model = configuration.soc_ifc_rm;
 
@@ -99,10 +103,17 @@ class soc_ifc_env_cptra_mbox_handler_sequence extends soc_ifc_env_sequence_base
         `uvm_fatal("CPTRA_MBOX_HANDLER", "SOC_IFC ENV caliptra mailbox handler sequence expected a handle to the cptra status agent responder sequence (from bench-level sequence) but got null!")
     fork
         forever begin
-            @(cptra_status_agent_rsp_seq.new_rsp) sts_rsp_count++;
+            @(cptra_status_agent_rsp_seq.new_rsp) begin
+                sts_rsp_count += (cptra_status_agent_rsp_seq.rsp.soc_ifc_notif_intr_pending ||
+                                  cptra_status_agent_rsp_seq.rsp.soc_ifc_err_intr_pending) ? 0 : 1;
+                ntf_rsp_count +=  cptra_status_agent_rsp_seq.rsp.soc_ifc_notif_intr_pending;
+                err_rsp_count +=  cptra_status_agent_rsp_seq.rsp.soc_ifc_err_intr_pending;
+            end
         end
     join_none
 
+    handler_setup();
+
     fork
         begin: ALL_TIME_CONSUMING_TASKS
             // Wait for a mailbox command to be received
@@ -119,7 +130,15 @@ class soc_ifc_env_cptra_mbox_handler_sequence extends soc_ifc_env_sequence_base
 
             // If resp data is required, set DATAIN
             if (op.cmd.cmd_s.resp_reqd) begin
-                mbox_push_datain();
+                if (mbox_resp_expected_dlen == 0) begin
+                    // We should only have 'resp_reqd' and 'exp_dlen == 0' if
+                    // a spurious write triggered MBOX_ERROR and caused us to fail
+                    // on reading back the dataout
+                    mbox_check_fsm();
+                end
+                else begin
+                    mbox_push_datain();
+                end
             end
 
             // Set STATUS
@@ -131,9 +150,15 @@ class soc_ifc_env_cptra_mbox_handler_sequence extends soc_ifc_env_sequence_base
 
             // Wait for the command to complete.
             // Either we clear the lock (via force_unlock), or the SOC requestor does.
+            // If the SOC requestor triggered a mbox protocol violation and this sequence
+            // is not randomly injecting force_unlock, the force_unlock thread will still set
+            // mbox_unlock to reset the mailbox state machine and service the error.
+            `uvm_info("CPTRA_MBOX_HANDLER", "Waiting for mbox_lock to deassert, indicating end of mailbox flow", UVM_MEDIUM)
             while (reg_model.mbox_csr_rm.mbox_lock.lock.get_mirrored_value()) begin
                 configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(1);
             end
+
+            `uvm_info("CPTRA_MBOX_HANDLER", "Observed mbox_lock deassertion, indicating end of mailbox flow", UVM_MEDIUM)
             seq_done = 1;
         end: ALL_TIME_CONSUMING_TASKS
         begin: DO_FORCE_UNLOCK
@@ -141,12 +166,16 @@ class soc_ifc_env_cptra_mbox_handler_sequence extends soc_ifc_env_sequence_base
             // After forcibly unlocking mailbox, kill any remaining activity.
             // If force unlock is randomized to "off" for this run
             // of the sequence, this won't ever run.
-            in_report_reg_sts.wait_on(); /* Wait for pending bus transfers (in ALL_TIME_CONSUMING_TASKS) to finish to avoid deadlock */
+            if (op_active)
+                in_report_reg_sts.wait_on(); /* Wait for pending bus transfers (in ALL_TIME_CONSUMING_TASKS) to finish to avoid deadlock */
             disable ALL_TIME_CONSUMING_TASKS;
             `uvm_info("CPTRA_MBOX_HANDLER", "Disabled ALL_TIME_CONSUMING_TASKS", UVM_HIGH)
         end: DO_FORCE_UNLOCK
     join_any
-    if (unlock_proc_active) in_report_reg_sts.wait_trigger(); /* Wait for pending bus transfers (in DO_FORCE_UNLOCK) to finish to avoid deadlock */
+    if (unlock_proc_active) begin
+        `uvm_info("CPTRA_MBOX_HANDLER", "Detected force-unlock in progress, waiting for current bus transfer to finish before continuing", UVM_MEDIUM)
+        in_report_reg_sts.wait_trigger(); /* Wait for pending bus transfers (in DO_FORCE_UNLOCK) to finish to avoid deadlock */
+    end
     disable DO_FORCE_UNLOCK;
 
     // Check new responses (might be an interrupt? Nothing else expected)
@@ -159,6 +188,46 @@ class soc_ifc_env_cptra_mbox_handler_sequence extends soc_ifc_env_sequence_base
 
 endclass
 
+//==========================================
+// Task:        handler_setup
+// Description: Prep the system to receive a new mailbox command.
+//              This includes servicing/clearing any interrupts already
+//              pending on sequence entry (except new command intr)
+//==========================================
+task soc_ifc_env_cptra_mbox_handler_sequence::handler_setup();
+    uvm_reg_data_t data;
+
+    if (sts_rsp_count) begin
+        `uvm_warning("CPTRA_MBOX_HANDLER", "Did not expect to receive any new cptra_status transactions at sequence entry!")
+        sts_rsp_count = 0;
+    end
+
+    // Clear notifications
+    if (ntf_rsp_count) begin
+        `uvm_warning("CPTRA_MBOX_HANDLER", "Did not expect to receive any new cptra_status notification interrupt transactions at sequence entry!")
+        ntf_rsp_count = 0;
+    end
+    reg_model.soc_ifc_reg_rm.intr_block_rf_ext.notif_internal_intr_r.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
+    report_reg_sts(reg_sts, "notif_internal_intr_r");
+    if (data[reg_model.soc_ifc_reg_rm.intr_block_rf_ext.notif_internal_intr_r.notif_cmd_avail_sts.get_lsb_pos()] &&
+        cptra_status_agent_rsp_seq.rsp.soc_ifc_notif_intr_pending) begin
+        ntf_rsp_count = 1; // Roll this interrupt event forward to 'mbox_wait_for_command'
+    end
+    // Clear all interrupts except for cmd available
+    data &= ~(uvm_reg_data_t'(1) << reg_model.soc_ifc_reg_rm.intr_block_rf_ext.notif_internal_intr_r.notif_cmd_avail_sts.get_lsb_pos());
+    reg_model.soc_ifc_reg_rm.intr_block_rf_ext.notif_internal_intr_r.write(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
+    report_reg_sts(reg_sts, "notif_internal_intr_r");
+    // Clear errors
+    if (err_rsp_count) begin
+        `uvm_warning("CPTRA_MBOX_HANDLER", "Did not expect to receive any new cptra_status err interrupt transactions at sequence entry!")
+        err_rsp_count = 0;
+    end
+    reg_model.soc_ifc_reg_rm.intr_block_rf_ext.error_internal_intr_r.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
+    report_reg_sts(reg_sts, "error_internal_intr_r");
+    reg_model.soc_ifc_reg_rm.intr_block_rf_ext.error_internal_intr_r.write(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
+    report_reg_sts(reg_sts, "error_internal_intr_r");
+endtask
+
 //==========================================
 // Task:        mbox_wait_for_command
 // Description: Poll for availability of new
@@ -169,12 +238,20 @@ endclass
 task soc_ifc_env_cptra_mbox_handler_sequence::mbox_wait_for_command(output op_sts_e op_sts);
     uvm_reg_data_t data;
     op_sts = CPTRA_TIMEOUT;
+    // Wait for notification interrupt indicating command is available
+    while (ntf_rsp_count == 0) begin
+        configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(1);
+        if (ntf_rsp_count != 0 && !cptra_status_agent_rsp_seq.rsp.soc_ifc_notif_intr_pending) begin
+            ntf_rsp_count = 0;
+        end
+    end
+    ntf_rsp_count = 0;
+    op_active = 1;
+    // Clear interrupt
     reg_model.soc_ifc_reg_rm.intr_block_rf_ext.notif_internal_intr_r.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
     report_reg_sts(reg_sts, "notif_internal_intr_r");
-    while (!data[reg_model.soc_ifc_reg_rm.intr_block_rf_ext.notif_internal_intr_r.notif_cmd_avail_sts.get_lsb_pos()]) begin
-        configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(200);
-        reg_model.soc_ifc_reg_rm.intr_block_rf_ext.notif_internal_intr_r.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
-        report_reg_sts(reg_sts, "notif_internal_intr_r");
+    if (!data[reg_model.soc_ifc_reg_rm.intr_block_rf_ext.notif_internal_intr_r.notif_cmd_avail_sts.get_lsb_pos()]) begin
+        `uvm_error("CPTRA_MBOX_HANDLER", "After receiving notification interrupt, notif_cmd_avail_sts is not set!")
     end
     data &= uvm_reg_data_t'(1) << reg_model.soc_ifc_reg_rm.intr_block_rf_ext.notif_internal_intr_r.notif_cmd_avail_sts.get_lsb_pos();
     reg_model.soc_ifc_reg_rm.intr_block_rf_ext.notif_internal_intr_r.write(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
@@ -265,7 +342,13 @@ task soc_ifc_env_cptra_mbox_handler_sequence::mbox_check_fsm();
     report_reg_sts(reg_sts, "mbox_status");
 
     fsm_state = mbox_fsm_state_e'(data >> reg_model.mbox_csr_rm.mbox_status.mbox_fsm_ps.get_lsb_pos());
-    if (op.cmd.cmd_s.resp_reqd && fsm_state != MBOX_EXECUTE_SOC) begin
+    // In the error state, simply wait for the force-unlock to reset the mailbox and end the sequence (killing this routine in the process)
+    if (fsm_state == MBOX_ERROR) begin
+        `uvm_info("CPTRA_MBOX_HANDLER", $sformatf("On detecting mailbox FSM state: %p, wait for force_unlock to end the sequence", fsm_state), UVM_MEDIUM)
+        op_active = 1'b0; // So the force-unlock branch knows it's safe to terminate this task
+        forever configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(10000);
+    end
+    else if (op.cmd.cmd_s.resp_reqd && fsm_state != MBOX_EXECUTE_SOC) begin
         `uvm_error("CPTRA_MBOX_HANDLER", $sformatf("Unexpected mailbox FSM state: %p", fsm_state))
     end
 endtask
@@ -278,13 +361,41 @@ endtask
 //==========================================
 task soc_ifc_env_cptra_mbox_handler_sequence::mbox_wait_and_force_unlock();
     uvm_reg_data_t data;
+    mbox_fsm_state_e state;
 
     // Wait...
-    if (!inject_force_unlock) begin
-        // This task never exits if force unlock is disabled
-        forever configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(1000);
+    // If force unlock is disabled, this task will only exit upon detecting
+    // an ERROR that requires servicing, whereupon force_unlock will still
+    // be set to recover. In either case, only an event resulting in force
+    // unlock causes this routine to break
+    while(!inject_force_unlock) begin
+        if (err_rsp_count > 0 && cptra_status_agent_rsp_seq.rsp.soc_ifc_err_intr_pending) begin
+            `uvm_info("CPTRA_MBOX_HANDLER", "Received soc_ifc_err_intr, clearing and (if needed) proceeding to mbox_unlock", UVM_MEDIUM)
+            // Read and clear any error interrupts
+            reg_model.soc_ifc_reg_rm.intr_block_rf_ext.error_internal_intr_r.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
+            report_reg_sts(reg_sts, "error_internal_intr_r");
+            configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(10/*TODO rand delays*/);
+            reg_model.soc_ifc_reg_rm.intr_block_rf_ext.error_internal_intr_r.write(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
+            report_reg_sts(reg_sts, "error_internal_intr_r");
+            err_rsp_count = 0;
+            // Next, check if we need to proceed to mbox_unlock step
+            if (!data[reg_model.soc_ifc_reg_rm.intr_block_rf_ext.error_internal_intr_r.error_cmd_fail_sts.get_lsb_pos()]) begin
+                continue;
+            end
+            reg_model.mbox_csr_rm.mbox_status.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
+            report_reg_sts(reg_sts, "mbox_status");
+            state = mbox_fsm_state_e'(data >> reg_model.mbox_csr_rm.mbox_status.mbox_fsm_ps.get_lsb_pos());
+            // If we're in the error state, the only recovery is by mbox_unlock - proceed to that step
+            if (state == MBOX_ERROR) begin
+                `uvm_info("CPTRA_MBOX_HANDLER", "After servicing soc_ifc_err_intr, proceeding with mbox_unlock", UVM_MEDIUM)
+                break;
+            end
+        end
+        configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(10/*TODO rand delays*/);
+    end
+    if (inject_force_unlock) begin
+        configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(force_unlock_delay_cycles);
     end
-    configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(force_unlock_delay_cycles);
 
     // Start the unlock proc
     unlock_proc_active = 1'b1;
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_interference_handler_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_interference_handler_sequence.svh
index d1be3b659..755c60628 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_interference_handler_sequence.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_interference_handler_sequence.svh
@@ -32,6 +32,8 @@ class soc_ifc_env_cptra_mbox_interference_handler_sequence extends soc_ifc_env_c
   `uvm_object_utils( soc_ifc_env_cptra_mbox_interference_handler_sequence )
 
   extern virtual task mbox_wait_for_command(output op_sts_e op_sts);
+  extern virtual task mbox_wait_and_force_unlock();
+  extern virtual task burst_random_reg_accesses(uvm_event stop);
 
   rand uvm_reg_data_t data;
   rand uvm_reg_addr_t mem_offset;
@@ -41,22 +43,39 @@ class soc_ifc_env_cptra_mbox_interference_handler_sequence extends soc_ifc_env_c
 
 endclass
 
+//==========================================
+// Task:        mbox_wait_for_command
+// Description: Poll for availability of new
+//              mailbox request, indicated by:
+//                - mbox_execute = 1
+//                - intr status = 1
+//==========================================
 task soc_ifc_env_cptra_mbox_interference_handler_sequence::mbox_wait_for_command(output op_sts_e op_sts);
     byte ii;
 
+    uvm_reg_data_t data;
     op_sts = CPTRA_TIMEOUT;
-    reg_model.soc_ifc_reg_rm.intr_block_rf_ext.notif_internal_intr_r.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
-    report_reg_sts(reg_sts, "notif_internal_intr_r");
-    while (!data[reg_model.soc_ifc_reg_rm.intr_block_rf_ext.notif_internal_intr_r.notif_cmd_avail_sts.get_lsb_pos()]) begin
+    op_active = 1;
+    // Wait for notification interrupt indicating command is available
+    while (ntf_rsp_count == 0) begin
+        uvm_reg_data_t dlen;
+        byte unsigned  mem_n_bytes;
+
+        dlen = reg_model.mbox_csr_rm.mbox_dlen.length.get_mirrored_value();
+        mem_n_bytes = reg_model.mbox_mem_rm.get_n_bytes();
+
         if(!this.randomize(xfers) with {xfers inside {[1:20]}; }) begin
             `uvm_error("CPTRA_MBOX_HANDLER", "Failed to randomize memory AHB transfer count in mbox_wait_for_command")
         end
         else begin
             for (ii=0; ii<xfers; ii++) begin: XFER_LOOP
                 // Do random access to mailbox memory to trigger arb logic as soc APB actor writes command data
+                // NOTE that RnW is forced to AHB_READ when the address falls inside the range of DLEN current value, so that
+                // data from the mailbox command is not corrupted.
                 // TODO also mix in some reg accesses?
                 if(!this.randomize(RnW, mem_offset, data, cycles) with {mem_offset inside {[0:reg_model.mbox_mem_rm.get_size()-1]};
-                                                                        cycles inside {[1:200]}; }) begin
+                                                                        cycles inside {[1:200]};
+                                                                        if(mem_offset * mem_n_bytes < dlen) RnW == AHB_READ; }) begin
                     `uvm_error("CPTRA_MBOX_HANDLER", "Failed to randomize memory AHB transfer in mbox_wait_for_command")
                 end
                 else begin
@@ -72,11 +91,184 @@ task soc_ifc_env_cptra_mbox_interference_handler_sequence::mbox_wait_for_command
             end
         end
         configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(cycles);
-        reg_model.soc_ifc_reg_rm.intr_block_rf_ext.notif_internal_intr_r.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
-        report_reg_sts(reg_sts, "notif_internal_intr_r");
+        if (ntf_rsp_count != 0 && !cptra_status_agent_rsp_seq.rsp.soc_ifc_notif_intr_pending) begin
+            ntf_rsp_count = 0;
+        end
+    end
+    ntf_rsp_count = 0;
+    // Clear interrupt
+    reg_model.soc_ifc_reg_rm.intr_block_rf_ext.notif_internal_intr_r.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
+    report_reg_sts(reg_sts, "notif_internal_intr_r");
+    if (!data[reg_model.soc_ifc_reg_rm.intr_block_rf_ext.notif_internal_intr_r.notif_cmd_avail_sts.get_lsb_pos()]) begin
+        `uvm_error("CPTRA_MBOX_HANDLER", "After receiving notification interrupt, notif_cmd_avail_sts is not set!")
     end
     data &= uvm_reg_data_t'(1) << reg_model.soc_ifc_reg_rm.intr_block_rf_ext.notif_internal_intr_r.notif_cmd_avail_sts.get_lsb_pos();
     reg_model.soc_ifc_reg_rm.intr_block_rf_ext.notif_internal_intr_r.write(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
     report_reg_sts(reg_sts, "notif_internal_intr_r");
     op_sts = CPTRA_SUCCESS;
 endtask
+
+//==========================================
+// Task:        mbox_wait_and_force_unlock
+// Description: If enabled, wait for some random amount of time and
+//              then do a write to mbox_unlock to forcibly end
+//              the current mailbox flow.
+//              In the interference sequence, use this routine to
+//              inject random reads (to non-mailbox registers)
+//              throughout the entire duration of the scenario.
+//==========================================
+task soc_ifc_env_cptra_mbox_interference_handler_sequence::mbox_wait_and_force_unlock();
+    uvm_reg_data_t data;
+    mbox_fsm_state_e state;
+    uvm_event force_unlock_delay_complete = new("force_unlock_delay_complete");
+
+    // Start the unlock proc prior to burst accesses so that the parent
+    // sequence knows to wait for AHB traffic to complete before ending the
+    // sequence
+    unlock_proc_active = 1'b1;
+
+    // Wait...
+    // If force unlock is disabled, this task will only exit upon detecting
+    // an ERROR that requires servicing, whereupon force_unlock will still
+    // be set to recover. In either case, only an event resulting in force
+    // unlock causes this routine to break
+    force_unlock_delay_complete.reset();
+    fork
+        begin
+            if (inject_force_unlock) begin
+                configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(force_unlock_delay_cycles);
+            end
+            else begin
+                `uvm_info("CPTRA_MBOX_HANDLER", "Not injecting force unlock - burst random reg accesses until any err interrupt is observed", UVM_HIGH)
+                forever begin
+                    if (err_rsp_count > 0 && cptra_status_agent_rsp_seq.rsp.soc_ifc_err_intr_pending) begin
+                        `uvm_info("CPTRA_MBOX_HANDLER", "Received soc_ifc_err_intr, clearing and (if needed) proceeding to mbox_unlock", UVM_MEDIUM)
+                        // Read and clear any error interrupts
+                        reg_model.soc_ifc_reg_rm.intr_block_rf_ext.error_internal_intr_r.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
+                        report_reg_sts(reg_sts, "error_internal_intr_r");
+                        configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(10/*TODO rand delays*/);
+                        reg_model.soc_ifc_reg_rm.intr_block_rf_ext.error_internal_intr_r.write(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
+                        report_reg_sts(reg_sts, "error_internal_intr_r");
+                        err_rsp_count = 0;
+                        // Next, check if we need to proceed to mbox_unlock step
+                        if (!data[reg_model.soc_ifc_reg_rm.intr_block_rf_ext.error_internal_intr_r.error_cmd_fail_sts.get_lsb_pos()]) begin
+                            continue;
+                        end
+                        reg_model.mbox_csr_rm.mbox_status.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
+                        report_reg_sts(reg_sts, "mbox_status");
+                        state = mbox_fsm_state_e'(data >> reg_model.mbox_csr_rm.mbox_status.mbox_fsm_ps.get_lsb_pos());
+                        // If we're in the error state, the only recovery is by mbox_unlock - proceed to that step
+                        if (state == MBOX_ERROR) begin
+                            `uvm_info("CPTRA_MBOX_HANDLER", "After servicing soc_ifc_err_intr, proceeding with mbox_unlock", UVM_MEDIUM)
+                            break;
+                        end
+                    end
+                    else begin
+                        configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(10/*TODO rand delays*/);
+                    end
+                end
+            end
+            force_unlock_delay_complete.trigger();
+        end
+        burst_random_reg_accesses(force_unlock_delay_complete);
+    join
+
+    // After waiting the requisite number of cycles, check mbox_status.
+    // If SOC doesn't currently have the lock, doing a force-unlock has no
+    // effect. Poll until soc_has_lock is set.
+    // NOTE: Making this check the reg-model mirror instead of actual polling
+    //       might be beneficial?
+    reg_model.mbox_csr_rm.mbox_status.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
+    report_reg_sts(reg_sts, "mbox_status");
+    while (!data[reg_model.mbox_csr_rm.mbox_status.soc_has_lock.get_lsb_pos()]) begin
+        configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(50); /* short 500ns between reads */
+        reg_model.mbox_csr_rm.mbox_status.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
+        report_reg_sts(reg_sts, "mbox_status");
+    end
+
+    // Write unlock reg
+    `uvm_info("CPTRA_MBOX_HANDLER","Executing force unlock of mailbox. CPTRA mbox flow handler will exit after unlock.", UVM_MEDIUM)
+    reg_model.mbox_csr_rm.mbox_unlock.write(reg_sts, uvm_reg_data_t'(1) << reg_model.mbox_csr_rm.mbox_unlock.unlock.get_lsb_pos(), UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
+    report_reg_sts(reg_sts, "mbox_unlock");
+
+    // Clear any interrupts as well, if they weren't cleared before unlock
+    data = uvm_reg_data_t'(1) << reg_model.soc_ifc_reg_rm.intr_block_rf_ext.notif_internal_intr_r.notif_cmd_avail_sts.get_lsb_pos();
+    `uvm_info("CPTRA_MBOX_HANDLER", "Doing clear notif intr", UVM_LOW)
+    reg_model.soc_ifc_reg_rm.intr_block_rf_ext.notif_internal_intr_r.write(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
+    report_reg_sts(reg_sts, "notif_internal_intr_r");
+    in_report_reg_sts.reset(); /* Clear the trigger from report_reg_sts so that DO_FORCE_UNLOCK can catch the end of a reg-write from ALL_TIME_CONSUMING_TASKS */
+
+    // End
+    unlock_proc_active = 1'b0;
+    seq_done = 1'b1;
+    `uvm_info("CPTRA_MBOX_HANDLER", "Done clearing notif intr", UVM_LOW)
+endtask
+
+//==========================================
+// Task:        burst_random_reg_accesses
+// Description: Continuously issue bursts (of random length)
+//              of bus reads to randomly selected SOC_IFC registers,
+//              intermixed with random delays, until the input event
+//              is triggered.
+//==========================================
+task soc_ifc_env_cptra_mbox_interference_handler_sequence::burst_random_reg_accesses(uvm_event stop);
+    int unsigned burst_length;
+    int unsigned delay_cycles;
+
+    uvm_reg regs[$];
+    uvm_reg blocklist[];
+    int     del_idx[$];
+
+    byte unsigned  ii;
+    int            reg_select;
+    ahb_rnw_e      rand_RnW;
+    uvm_reg_data_t rand_data;
+    uvm_status_e   rand_sts;
+
+    reg_model.soc_ifc_AHB_map.get_registers(regs, UVM_HIER);
+
+    // Registers we won't randomly access due to side-effects
+    // Don't include any mailbox registers
+    blocklist = '{reg_model.mbox_csr_rm.mbox_lock,
+                  reg_model.mbox_csr_rm.mbox_user,
+                  reg_model.mbox_csr_rm.mbox_cmd,
+                  reg_model.mbox_csr_rm.mbox_dlen,
+                  reg_model.mbox_csr_rm.mbox_datain,
+                  reg_model.mbox_csr_rm.mbox_dataout,
+                  reg_model.mbox_csr_rm.mbox_execute,
+                  reg_model.mbox_csr_rm.mbox_status,
+                  reg_model.mbox_csr_rm.mbox_unlock,
+                  reg_model.sha512_acc_csr_rm.LOCK};
+    foreach (blocklist[idx]) begin
+        del_idx = regs.find_first_index(found_reg) with (found_reg == blocklist[idx]);
+        regs.delete(del_idx.pop_front());
+    end
+
+    forever begin
+        if (!std::randomize(burst_length, delay_cycles) with {burst_length inside {[1:100]};
+                                                              delay_cycles inside {[1:500]};})
+            `uvm_error("CPTRA_MBOX_HANDLER", "Failed to randomize burst_length and delay_cycles")
+        else begin
+            for (ii=0; ii<burst_length; ii++) begin: XFER_LOOP
+                // Do random access to soc_ifc to trigger arb logic as cptra sequence processes
+                // incoming mailbox command
+                // TODO also mix in some reg writes?
+                if(!std::randomize(rand_RnW, reg_select, rand_data) with {rand_RnW == AHB_READ;
+                                                                          reg_select < regs.size(); }) begin
+                    `uvm_error("CPTRA_MBOX_HANDLER", "Failed to randomize reg AHB transfer in burst_random_reg_accesses")
+                end
+                else begin
+                    `uvm_info("CPTRA_MBOX_HANDLER", $sformatf("Doing random AHB access of type %p to %s, which has is_busy(): %d", rand_RnW, regs[reg_select].get_name(), regs[reg_select].is_busy()), UVM_DEBUG)
+                    if (rand_RnW == AHB_READ) regs[reg_select].read (rand_sts, rand_data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
+                    else                      regs[reg_select].write(rand_sts, rand_data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
+                    report_reg_sts(rand_sts, regs[reg_select].get_name());
+                end
+                if (stop.is_on()) return;
+            end
+        end
+        for (ii=delay_cycles; ii > 0; ii--) begin
+            configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(1);
+            if (stop.is_on()) return;
+        end
+    end
+endtask
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_req_sequence_base.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_req_sequence_base.svh
index 37a9b8e6a..46863df42 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_req_sequence_base.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_req_sequence_base.svh
@@ -39,6 +39,7 @@ class soc_ifc_env_cptra_mbox_req_sequence_base extends soc_ifc_env_sequence_base
   rand mbox_op_s mbox_op_rand;
   int sts_rsp_count;
   uvm_status_e reg_sts;
+  bit mbox_sts_is_error = 0;
   rand bit do_ahb_lock_check;
   rand bit retry_failed_reg_axs;
   // Certain random sequences force the command to be outside of the defined
@@ -58,7 +59,7 @@ class soc_ifc_env_cptra_mbox_req_sequence_base extends soc_ifc_env_sequence_base
   extern virtual task mbox_set_cmd(input mbox_op_s op);
   extern virtual task mbox_push_datain();
   extern virtual task mbox_execute();
-  extern virtual task mbox_check_status(output mbox_status_e data);
+  extern virtual task mbox_check_status(output mbox_status_e data, output mbox_fsm_state_e state);
   extern virtual task mbox_poll_status();
   extern virtual task mbox_clr_execute();
   extern virtual task mbox_teardown();
@@ -171,7 +172,32 @@ endclass
 //               - Any functionality implemented in derived classes
 //==========================================
 task soc_ifc_env_cptra_mbox_req_sequence_base::mbox_setup();
-    // TODO nothing to do yet
+    uvm_reg_data_t data;
+    uvm_reg_field  flds[$];
+
+    // Clear any interrupts already asserted at sequence start
+    // Notifications
+    reg_model.soc_ifc_reg_rm.intr_block_rf_ext.notif_internal_intr_r.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
+    report_reg_sts(reg_sts, "notif_internal_intr_r");
+    reg_model.soc_ifc_reg_rm.intr_block_rf_ext.notif_internal_intr_r.write(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
+    report_reg_sts(reg_sts, "notif_internal_intr_r");
+    reg_model.soc_ifc_reg_rm.intr_block_rf_ext.notif_internal_intr_r.get_fields(flds);
+    foreach (flds[ii]) begin
+        if (data[flds[ii].get_lsb_pos()])
+            `uvm_info("CPTRA_MBOX_SEQ", {"At sequence start, observed notification_interrupt for bit: ", flds[ii].get_name()}, UVM_HIGH)
+    end
+
+    // Errors
+    reg_model.soc_ifc_reg_rm.intr_block_rf_ext.error_internal_intr_r.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
+    report_reg_sts(reg_sts, "error_internal_intr_r");
+    reg_model.soc_ifc_reg_rm.intr_block_rf_ext.error_internal_intr_r.write(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
+    report_reg_sts(reg_sts, "error_internal_intr_r");
+    flds.delete();
+    reg_model.soc_ifc_reg_rm.intr_block_rf_ext.error_internal_intr_r.get_fields(flds);
+    foreach (flds[ii]) begin
+        if (data[flds[ii].get_lsb_pos()])
+            `uvm_info("CPTRA_MBOX_SEQ", {"At sequence start, observed error_interrupt for bit: ", flds[ii].get_name()}, UVM_HIGH)
+    end
 endtask
 
 //==========================================
@@ -313,7 +339,7 @@ endtask
 // Task:        mbox_check_status
 // Description: Read mbox_status
 //==========================================
-task soc_ifc_env_cptra_mbox_req_sequence_base::mbox_check_status(output mbox_status_e data);
+task soc_ifc_env_cptra_mbox_req_sequence_base::mbox_check_status(output mbox_status_e data, output mbox_fsm_state_e state);
     uvm_reg_data_t reg_data;
     reg_model.mbox_csr_rm.mbox_status.read(reg_sts, reg_data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
     report_reg_sts(reg_sts, "mbox_status");
@@ -323,6 +349,7 @@ task soc_ifc_env_cptra_mbox_req_sequence_base::mbox_check_status(output mbox_sta
     end
     else begin
         data = mbox_status_e'(reg_data >> reg_model.mbox_csr_rm.mbox_status.status.get_lsb_pos());
+        state = mbox_fsm_state_e'(reg_data >> reg_model.mbox_csr_rm.mbox_status.mbox_fsm_ps.get_lsb_pos());
     end
 endtask
 
@@ -330,17 +357,28 @@ endtask
 // Task:        mbox_poll_status
 // Description: Issue calls to mbox_check_status
 //              until status change indicates control is
-//              returned to SOC.
+//              returned to uC.
 //==========================================
 task soc_ifc_env_cptra_mbox_req_sequence_base::mbox_poll_status();
     mbox_status_e data;
+    mbox_fsm_state_e state;
     uvm_reg_data_t mask;
 
     // Poll mbox_status register
     do begin
         configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(200);
-        mbox_check_status(data);
-    end while (data == CMD_BUSY);
+        mbox_check_status(data, state);
+    end while (data == CMD_BUSY && !(state inside {MBOX_IDLE, MBOX_ERROR}));
+
+    // We should have an error interrupt in response to the ERROR state, which
+    // will be serviced at a later step.
+    // We do not expect the cmd_avail_sts interrupt, and there is no point in
+    // continuing this task (to report on the mbox_status field) when we've hit
+    // a protocol error.
+    if (state == MBOX_ERROR) begin
+        mbox_sts_is_error = 1;
+        return;
+    end
 
     // Clear Interrupt Status, which is set on transfer SOC->uC
     mask = uvm_reg_data_t'(1) << reg_model.soc_ifc_reg_rm.intr_block_rf_ext.notif_internal_intr_r.notif_cmd_avail_sts.get_lsb_pos();
@@ -351,25 +389,50 @@ task soc_ifc_env_cptra_mbox_req_sequence_base::mbox_poll_status();
 
     // Evaluate status field
     if (data == DATA_READY) begin
-        `uvm_error("CPTRA_MBOX_SEQ", $sformatf("Received status %p when not expecting any bytes of response data!", data))
+        `uvm_info("CPTRA_MBOX_SEQ", $sformatf("Received status %p when not expecting any bytes of response data!", data), UVM_LOW)
     end
     else if (data == CMD_FAILURE) begin
-        `uvm_error("CPTRA_MBOX_SEQ", $sformatf("Received unexpected mailbox status %p", data))
+        `uvm_info("CPTRA_MBOX_SEQ", $sformatf("Received unexpected mailbox status %p", data), UVM_LOW)
     end
     else if (data == CMD_COMPLETE) begin
         `uvm_info("CPTRA_MBOX_SEQ", $sformatf("Received status %p from SOC in response to command", data), UVM_FULL)
     end
     else begin
-        `uvm_error("CPTRA_MBOX_SEQ", $sformatf("Received unexpected mailbox status %p", data))
+        `uvm_info("CPTRA_MBOX_SEQ", $sformatf("Received unexpected mailbox status %p", data), UVM_LOW)
     end
 endtask
 
 //==========================================
 // Task:        mbox_clr_execute
 // Description: End the mailbox flow by writing
-//              0 to mbox_execute register
+//              0 to mbox_execute register (or
+//              by force-unlock if necessary)
 //==========================================
 task soc_ifc_env_cptra_mbox_req_sequence_base::mbox_clr_execute();
+    uvm_reg_data_t data;
+    // We have to stall a couple clocks to allow interrupts to assert in case
+    // we read the MBOX_ERROR status, since there is a small delay as the signal
+    // propagates through registers.
+    configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(2);
+    // Now, check for the expected error interrupt
+    if (sts_rsp_count > 0 && cptra_status_agent_rsp_seq.rsp.soc_ifc_err_intr_pending) begin
+        reg_model.soc_ifc_reg_rm.intr_block_rf_ext.error_internal_intr_r.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
+        report_reg_sts(reg_sts, "error_internal_intr_r");
+        reg_model.soc_ifc_reg_rm.intr_block_rf_ext.error_internal_intr_r.write(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
+        report_reg_sts(reg_sts, "error_internal_intr_r");
+        if (data[reg_model.soc_ifc_reg_rm.intr_block_rf_ext.error_internal_intr_r.error_cmd_fail_sts.get_lsb_pos()]) begin
+            // Force unlock to recover from error and reset mailbox to IDLE state
+            reg_model.mbox_csr_rm.mbox_unlock.write(reg_sts, uvm_reg_data_t'(1 << reg_model.mbox_csr_rm.mbox_unlock.unlock.get_lsb_pos()), UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
+            report_reg_sts(reg_sts, "mbox_unlock");
+            return; /* force unlock trumps the write to mbox_execute, so we're done at this point */
+        end
+        else if (mbox_sts_is_error) begin
+            `uvm_error("CPTRA_MBOX_SEQ", "Error interrupt following cmd failure does not have cmd_fail bit set!")
+        end
+    end
+    else if (mbox_sts_is_error) begin
+        `uvm_error("CPTRA_MBOX_SEQ", "Error encountered but no interrupt received")
+    end
     reg_model.mbox_csr_rm.mbox_execute.write(reg_sts, uvm_reg_data_t'(0), UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
     report_reg_sts(reg_sts, "mbox_execute");
 endtask
@@ -380,7 +443,26 @@ endtask
 //              to add any end-of-sequence functionality.
 //==========================================
 task soc_ifc_env_cptra_mbox_req_sequence_base::mbox_teardown();
+    uvm_reg_data_t data, mask;
+
+    // Clear any pending notification interrupts that made it through to the end of the sequence
+    reg_model.soc_ifc_reg_rm.intr_block_rf_ext.notif_internal_intr_r.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
+    report_reg_sts(reg_sts, "notif_internal_intr_r");
+    // Any unexpected interrupts should trigger a tb error
+    mask = ~((1 << reg_model.soc_ifc_reg_rm.intr_block_rf_ext.notif_internal_intr_r.notif_mbox_ecc_cor_sts.get_lsb_pos()) |
+             (1 << reg_model.soc_ifc_reg_rm.intr_block_rf_ext.notif_internal_intr_r.notif_debug_locked_sts.get_lsb_pos()) |
+             (1 << reg_model.soc_ifc_reg_rm.intr_block_rf_ext.notif_internal_intr_r.notif_soc_req_lock_sts.get_lsb_pos()));
+    if (data & mask) begin
+        `uvm_error("CPTRA_MBOX_SEQ", $sformatf("Received notification interrupt for unexpected event: 0x%0x", data))
+    end
+    else begin
+        reg_model.soc_ifc_reg_rm.intr_block_rf_ext.notif_internal_intr_r.write(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
+        report_reg_sts(reg_sts, "notif_internal_intr_r");
+        `uvm_info("CPTRA_MBOX_SEQ", $sformatf("Received and cleared notification interrupt for events: 0x%0x", data), UVM_HIGH)
+    end
+
     // Summary at sequence end
+    `uvm_info("CPTRA_MBOX_SEQ", $sformatf("uC initiated mailbox flow is completed. Ending status: %s", mbox_sts_is_error ? "hit protocol violation" : "no protocol violation"), UVM_LOW)
 endtask
 
 //==========================================
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_dir_read_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_dir_read_sequence.svh
new file mode 100644
index 000000000..bc4aba89e
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_dir_read_sequence.svh
@@ -0,0 +1,42 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Extended from mbox_base sequence to provide additional
+//              functionality in a test that sends mailbox commands
+//              of a size that exceeds mailbox capacity.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_mbox_dir_read_sequence extends soc_ifc_env_mbox_sequence_base;
+
+  `uvm_object_utils( soc_ifc_env_mbox_dir_read_sequence )
+
+  // Constrain command to undefined opcode
+  constraint mbox_cmd_dir_read_c { (mbox_op_rand.cmd.cmd_e == MBOX_CMD_DIR_RD); }
+
+  // Constrain size to something reasonable
+  constraint mbox_dlen_max_c { mbox_op_rand.dlen <= 2000; }
+
+  function new(string name = "" );
+    super.new(name);
+  endfunction
+
+endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_dlen_invalid_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_dlen_invalid_sequence.svh
new file mode 100644
index 000000000..7a19c843b
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_dlen_invalid_sequence.svh
@@ -0,0 +1,50 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Extended from mbox_base sequence to provide additional
+//              functionality in a test that sends mailbox commands
+//              of a size that exceeds mailbox capacity.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_mbox_dlen_invalid_sequence extends soc_ifc_env_mbox_sequence_base;
+
+  `uvm_object_utils( soc_ifc_env_mbox_dlen_invalid_sequence )
+
+  // Constrain command to undefined opcode
+  constraint mbox_cmd_undef_c { !(mbox_op_rand.cmd.cmd_s inside {defined_cmds}); }
+
+  // Constrain size to greater than 128KiB to test a command with invalid
+  // size (larger than mailbox).
+  // But keep a reasonable-ish size so the test can run to completion
+  constraint mbox_dlen_max_c { mbox_op_rand.dlen <= 4*MBOX_SIZE_BYTES; }
+  constraint mbox_dlen_min_c { mbox_op_rand.dlen >    MBOX_SIZE_BYTES; }
+  // Response data is only non-zero if a response is requested, and also must
+  // be large enough to exceed the mailbox capacity
+  constraint mbox_resp_dlen_c {                                      mbox_resp_expected_dlen <= 4*MBOX_SIZE_BYTES;
+                                !mbox_op_rand.cmd.cmd_s.resp_reqd -> mbox_resp_expected_dlen == 0;
+                                 mbox_op_rand.cmd.cmd_s.resp_reqd -> mbox_resp_expected_dlen >    MBOX_SIZE_BYTES; }
+
+  function new(string name = "" );
+    super.new(name);
+  endfunction
+
+endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_dlen_overflow_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_dlen_overflow_sequence.svh
index 801570ba2..9f06602ab 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_dlen_overflow_sequence.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_dlen_overflow_sequence.svh
@@ -44,8 +44,10 @@ task soc_ifc_env_mbox_dlen_overflow_sequence::mbox_push_datain();
     uvm_reg_data_t data;
     int unsigned overflow_bytes;
 
-    // Still fits inside the mailbox
-    if (!std::randomize(overflow_bytes) with {overflow_bytes <= (reg_model.mbox_mem_rm.get_size() * reg_model.mbox_mem_rm.get_n_bytes()) - mbox_op_rand.dlen; overflow_bytes < mbox_op_rand.dlen * 4;})
+    // Overflow the programmed DLEN by at least 1 dword, up to 4x the programmed DLEN
+    // Ensure the constraint is solvable with dlen 0
+    if (!std::randomize(overflow_bytes) with {overflow_bytes >= 4; 
+                                              overflow_bytes <= (mbox_op_rand.dlen+1) * 4;})
         `uvm_error("MBOX_OVERFLOW_SEQ", "Failed to randomize overflow bytes")
     else
         `uvm_info("MBOX_OVERFLOW_SEQ", $sformatf("Randomized overflow bytes to %0d", overflow_bytes), UVM_MEDIUM)
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_fw_upd_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_fw_upd_sequence.svh
new file mode 100644
index 000000000..af320de47
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_fw_upd_sequence.svh
@@ -0,0 +1,36 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Extended from mbox_base sequence to provide additional
+//              functionality that emulates the expected format of a
+//              FW update transfer.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_mbox_fw_upd_sequence extends soc_ifc_env_mbox_real_fw_sequence;
+
+  `uvm_object_utils( soc_ifc_env_mbox_fw_upd_sequence )
+
+  //Just send a RT update sequence
+  constraint mbox_cmd_c { mbox_op_rand.cmd.cmd_e == MBOX_CMD_RT_UPDATE; }
+
+endclass
+
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_max_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_max_sequence.svh
new file mode 100644
index 000000000..a57976374
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_max_sequence.svh
@@ -0,0 +1,63 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Extended from mbox_base sequence to provide additional
+//              functionality in a test that sends small mailbox commands.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_mbox_max_sequence extends soc_ifc_env_mbox_sequence_base;
+
+  `uvm_object_utils( soc_ifc_env_mbox_max_sequence )
+
+  extern virtual task mbox_push_datain();
+
+  // Constrain command to undefined opcodes with no response required.
+  constraint mbox_cmd_c { mbox_op_rand.cmd.cmd_e == MBOX_CMD_UC_OVERRUN;}
+
+  // Constrain dlen to reach max or max-1
+  constraint mbox_dlen_minmax_c { mbox_op_rand.dlen inside {32'h0002_0000,32'h0001_FFFF,32'h0001_FFFE,32'h0001_FFFD,
+                                                            32'h0001_FFFC,32'h0001_FFFB,32'h0001_FFFA,32'h0001_FFF9}; }
+
+endclass
+
+//==========================================
+// Task:        mbox_push_datain
+// Description: Write data in a loop to mbox_datain register
+// NOTE:        This should be overridden with real data to write
+//==========================================
+task soc_ifc_env_mbox_max_sequence::mbox_push_datain();
+  int ii;
+  uvm_reg_data_t data;
+  for (ii=0; ii < this.mbox_op_rand.dlen; ii+=4) begin
+
+    if (!std::randomize(data)) `uvm_error("MBOX_SEQ", "Failed to randomize data")
+
+    `uvm_info("MBOX_SEQ", $sformatf("[Iteration: %0d] Sending datain: 0x%x", ii/4, data), UVM_DEBUG)
+    reg_model.mbox_csr_rm.mbox_datain.write(reg_sts, uvm_reg_data_t'(data), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(PAUSER_PROB_DATAIN)));
+    report_reg_sts(reg_sts, "mbox_datain");
+    if (!pauser_used_is_valid() && retry_failed_reg_axs) begin
+        `uvm_info("MBOX_SEQ", "Re-do datain write with valid PAUSER", UVM_HIGH)
+        reg_model.mbox_csr_rm.mbox_datain.write(reg_sts, uvm_reg_data_t'(data), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(FORCE_VALID_PAUSER)));
+        report_reg_sts(reg_sts, "mbox_datain");
+    end
+  end
+endtask
\ No newline at end of file
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_min_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_min_sequence.svh
new file mode 100644
index 000000000..1cb78434c
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_min_sequence.svh
@@ -0,0 +1,62 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Extended from mbox_base sequence to provide additional
+//              functionality in a test that sends small mailbox commands.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_mbox_min_sequence extends soc_ifc_env_mbox_sequence_base;
+
+  `uvm_object_utils( soc_ifc_env_mbox_min_sequence )
+
+  extern virtual task mbox_push_datain();
+
+  // Constrain command to undefined opcodes with no response required.
+  constraint mbox_cmd_c { mbox_op_rand.cmd.cmd_e == MBOX_CMD_UC_OVERRUN;}
+
+  // Constrain dlen to be 0-1 dword
+  constraint mbox_dlen_minmax_c { mbox_op_rand.dlen inside {32'h0000_0000,32'h0000_0001,32'h0000_0002,32'h0000_0003}; }
+
+endclass
+
+//==========================================
+// Task:        mbox_push_datain
+// Description: Write data in a loop to mbox_datain register
+// NOTE:        This should be overridden with real data to write
+//==========================================
+task soc_ifc_env_mbox_min_sequence::mbox_push_datain();
+  int ii;
+  uvm_reg_data_t data;
+  for (ii=0; ii < this.mbox_op_rand.dlen; ii+=4) begin
+
+    if (!std::randomize(data)) `uvm_error("MBOX_SEQ", "Failed to randomize data")
+
+    `uvm_info("MBOX_SEQ", $sformatf("[Iteration: %0d] Sending datain: 0x%x", ii/4, data), UVM_DEBUG)
+    reg_model.mbox_csr_rm.mbox_datain.write(reg_sts, uvm_reg_data_t'(data), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(PAUSER_PROB_DATAIN)));
+    report_reg_sts(reg_sts, "mbox_datain");
+    if (!pauser_used_is_valid() && retry_failed_reg_axs) begin
+        `uvm_info("MBOX_SEQ", "Re-do datain write with valid PAUSER", UVM_HIGH)
+        reg_model.mbox_csr_rm.mbox_datain.write(reg_sts, uvm_reg_data_t'(data), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(FORCE_VALID_PAUSER)));
+        report_reg_sts(reg_sts, "mbox_datain");
+    end
+  end
+endtask
\ No newline at end of file
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_rand_delay_large_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_rand_delay_large_sequence.svh
new file mode 100644
index 000000000..9b46df7c9
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_rand_delay_large_sequence.svh
@@ -0,0 +1,39 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Extended from mbox delay sequence to exercise rand delays
+//              throughout the test.
+//              Tests large sized mailbox commands with delays.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_mbox_rand_delay_large_sequence extends soc_ifc_env_mbox_rand_delay_sequence;
+
+  `uvm_object_utils( soc_ifc_env_mbox_rand_delay_large_sequence )
+
+  // Constrain size to a large command
+  // Min. size: 16KiB
+  constraint mbox_dlen_min_large_c { mbox_op_rand.dlen > 32'h0000_4000; }
+  // Constrain response data size to also be large
+  // Min. size: 16KiB
+  constraint mbox_resp_dlen_min_large_c { mbox_op_rand.cmd.cmd_s.resp_reqd -> mbox_resp_expected_dlen >= 32'h0000_4000; }
+
+endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_rand_delay_medium_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_rand_delay_medium_sequence.svh
new file mode 100644
index 000000000..fca42cd4c
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_rand_delay_medium_sequence.svh
@@ -0,0 +1,43 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Extended from mbox delay sequence to exercise rand delays
+//              throughout the test.
+//              Tests medium sized mailbox commands with delays.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_mbox_rand_delay_medium_sequence extends soc_ifc_env_mbox_rand_delay_sequence;
+
+  `uvm_object_utils( soc_ifc_env_mbox_rand_delay_medium_sequence )
+
+  // Constrain dlen to be a medium command
+  // Max. size: 4096B
+  constraint mbox_dlen_max_medium_c { mbox_op_rand.dlen <= 32'h0000_1000; }
+  // Minimum 512B
+  constraint mbox_dlen_min_medium_c { mbox_op_rand.dlen >= 32'h0000_0200; }
+  // Constrain response data size to also be medium
+  // Max. size: 4096B
+  // Min. size: 512B
+  constraint mbox_resp_dlen_max_medium_c { mbox_resp_expected_dlen <= 32'h0000_1000; }
+  constraint mbox_resp_dlen_min_medium_c { mbox_op_rand.cmd.cmd_s.resp_reqd -> mbox_resp_expected_dlen >= 32'h0000_0200; }
+
+endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_rand_delay_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_rand_delay_sequence.svh
new file mode 100644
index 000000000..1c8d75a96
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_rand_delay_sequence.svh
@@ -0,0 +1,75 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Extended from mbox_base sequence to provide additional
+//              functionality in a test that sends small mailbox commands.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_mbox_rand_delay_sequence extends soc_ifc_env_mbox_sequence_base;
+
+  `uvm_object_utils( soc_ifc_env_mbox_rand_delay_sequence )
+
+
+  // Constrain command to undefined opcode
+  constraint mbox_cmd_undef_c { !(mbox_op_rand.cmd.cmd_s inside {defined_cmds}); }
+
+  // Force delays to be injected at every step
+  constraint rand_delay_en_c { rand_delay_en == 1'b1; };
+
+  extern virtual task do_rand_delay(input bit do_delay_randomize=1, input delay_scale_e scale=DLY_SMALL);
+
+  //==========================================
+  // Function:    new
+  // Description: Constructor
+  //==========================================
+  function new(string name = "" );
+    super.new(name);
+    // Disable this constraint to allow wider coverage on
+    // delay types in delay sequences
+    this.delay_scale_c.constraint_mode(0);
+  endfunction
+
+endclass
+
+//==========================================
+// Function:    do_rand_delay
+// Description: Use the class variable "rand_delay"
+//              to inject random stalls between various stages
+//              of the sequence.
+//              If do_delay_randomize is set to 1, the value
+//              of rand_delay is re-randomized (according to
+//              class constraints), otherwise the previous value
+//              is used.
+// ---------
+//              This sequence extends functionality of this task to also
+//              re-randomize the _scales_ that are used throughout the sequence
+//              to give even wider delay coverage.
+//==========================================
+task soc_ifc_env_mbox_rand_delay_sequence::do_rand_delay(input bit do_delay_randomize=1, input delay_scale_e scale=DLY_SMALL);
+    super.do_rand_delay(do_delay_randomize, scale);
+    if (do_delay_randomize) begin
+        if (!this.randomize(poll_delay, step_delay, data_delay))
+            `uvm_error("MBOX_SEQ", $sformatf("Failed to randomize delay scales"))
+        else
+            `uvm_info("MBOX_SEQ", $sformatf("Generated new delay scales: poll [%p] step [%p] data [%p]", poll_delay, step_delay, data_delay), UVM_DEBUG)
+    end
+endtask
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_rand_delay_small_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_rand_delay_small_sequence.svh
new file mode 100644
index 000000000..efe1606bf
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_rand_delay_small_sequence.svh
@@ -0,0 +1,39 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Extended from mbox delay sequence to exercise rand delays
+//              throughout the test.
+//              Tests small sized mailbox commands with delays.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_mbox_rand_delay_small_sequence extends soc_ifc_env_mbox_rand_delay_sequence;
+
+  `uvm_object_utils( soc_ifc_env_mbox_rand_delay_small_sequence )
+
+  // Constrain dlen to be a small command
+  // Max. size: 512B
+  constraint mbox_dlen_max_small_c { mbox_op_rand.dlen <= 32'h0000_0200; }
+  // Constrain response data size to also be small
+  // Max. size: 512B
+  constraint mbox_resp_dlen_max_small_c { mbox_resp_expected_dlen < 32'h0000_0200; }
+
+endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_rand_medium_interference_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_rand_medium_interference_sequence.svh
index 3c561da64..058454ca9 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_rand_medium_interference_sequence.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_rand_medium_interference_sequence.svh
@@ -73,6 +73,7 @@ task soc_ifc_env_mbox_rand_medium_interference_sequence::mbox_poll_status();
                     `uvm_error("MBOX_SEQ", "Failed to randomize memory APB transfer in mbox_wait_for_command")
                 end
                 else begin
+                    `uvm_info("MBOX_SEQ", $sformatf("Doing random APB access of type %p to %s, which has is_busy(): %d", RnW, regs[reg_select].get_name(), regs[reg_select].is_busy()), UVM_DEBUG)
                     if (RnW == APB3_TRANS_READ) regs[reg_select].read (reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(PAUSER_PROB_STATUS)));
                     else                        regs[reg_select].write(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(PAUSER_PROB_STATUS)));
                 end
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_rand_multi_agent_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_rand_multi_agent_sequence.svh
index 7916d98b4..fb54f67a7 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_rand_multi_agent_sequence.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_rand_multi_agent_sequence.svh
@@ -126,6 +126,17 @@ function soc_ifc_env_mbox_rand_multi_agent_sequence::create_seqs();
         SMALL,
         MEDIUM,
         LARGE,
+        OVERFLOW_SMALL,
+        OVERFLOW_MEDIUM,
+        OVERFLOW_LARGE,
+        UNDERFLOW_SMALL,
+        UNDERFLOW_MEDIUM,
+        UNDERFLOW_LARGE,
+        MIN,
+        MAX,
+        DELAY_SMALL,
+        DELAY_MEDIUM,
+        DELAY_LARGE,
         PAUSER_SMALL,
         PAUSER_MEDIUM,
         PAUSER_LARGE,
@@ -138,7 +149,18 @@ function soc_ifc_env_mbox_rand_multi_agent_sequence::create_seqs();
         void'(std::randomize(seq_type) with { seq_type dist { SMALL                 := 100,
                                                               MEDIUM                := 50,
                                                               LARGE                 := 1,
-                                                              PAUSER_SMALL          := 20,
+                                                              OVERFLOW_SMALL        := 50,
+                                                              OVERFLOW_MEDIUM       := 30,
+                                                              OVERFLOW_LARGE        := 1,
+                                                              UNDERFLOW_SMALL       := 50,
+                                                              UNDERFLOW_MEDIUM      := 30,
+                                                              UNDERFLOW_LARGE       := 1,
+                                                              MIN                   := 50,
+                                                              MAX                   := 50,
+                                                              DELAY_SMALL           := 100,
+                                                              DELAY_MEDIUM          := 50,
+                                                              DELAY_LARGE           := 1,
+                                                              PAUSER_SMALL          := 50,
                                                               PAUSER_MEDIUM         := 20,
                                                               PAUSER_LARGE          := 1,
                                                               INTERFERENCE_MEDIUM   := 10   }; });
@@ -148,7 +170,29 @@ function soc_ifc_env_mbox_rand_multi_agent_sequence::create_seqs();
             MEDIUM:
                 obj = soc_ifc_env_mbox_rand_medium_sequence_t::get_type().create_object($sformatf("soc_ifc_env_mbox_multi_agent_seq[%0d]",ii));
             LARGE:
-                obj = soc_ifc_env_mbox_rand_small_sequence_t::get_type().create_object($sformatf("soc_ifc_env_mbox_multi_agent_seq[%0d]",ii));
+                obj = soc_ifc_env_mbox_rand_large_sequence_t::get_type().create_object($sformatf("soc_ifc_env_mbox_multi_agent_seq[%0d]",ii));
+            OVERFLOW_SMALL:
+                obj = soc_ifc_env_mbox_dlen_overflow_small_sequence_t::get_type().create_object($sformatf("soc_ifc_env_mbox_multi_agent_seq[%0d]",ii));
+            OVERFLOW_MEDIUM:
+                obj = soc_ifc_env_mbox_dlen_overflow_medium_sequence_t::get_type().create_object($sformatf("soc_ifc_env_mbox_multi_agent_seq[%0d]",ii));
+            OVERFLOW_LARGE:
+                obj = soc_ifc_env_mbox_dlen_overflow_large_sequence_t::get_type().create_object($sformatf("soc_ifc_env_mbox_multi_agent_seq[%0d]",ii));
+            UNDERFLOW_SMALL:
+                obj = soc_ifc_env_mbox_dlen_underflow_small_sequence_t::get_type().create_object($sformatf("soc_ifc_env_mbox_multi_agent_seq[%0d]",ii));
+            UNDERFLOW_MEDIUM:
+                obj = soc_ifc_env_mbox_dlen_underflow_medium_sequence_t::get_type().create_object($sformatf("soc_ifc_env_mbox_multi_agent_seq[%0d]",ii));
+            UNDERFLOW_LARGE:
+                obj = soc_ifc_env_mbox_dlen_underflow_large_sequence_t::get_type().create_object($sformatf("soc_ifc_env_mbox_multi_agent_seq[%0d]",ii));
+            MIN:
+                obj = soc_ifc_env_mbox_min_sequence_t::get_type().create_object($sformatf("soc_ifc_env_mbox_multi_agent_seq[%0d]",ii));
+            MAX:
+                obj = soc_ifc_env_mbox_max_sequence_t::get_type().create_object($sformatf("soc_ifc_env_mbox_multi_agent_seq[%0d]",ii));
+            DELAY_SMALL:
+                obj = soc_ifc_env_mbox_rand_delay_small_sequence_t::get_type().create_object($sformatf("soc_ifc_env_mbox_multi_agent_seq[%0d]",ii));
+            DELAY_MEDIUM:
+                obj = soc_ifc_env_mbox_rand_delay_medium_sequence_t::get_type().create_object($sformatf("soc_ifc_env_mbox_multi_agent_seq[%0d]",ii));
+            DELAY_LARGE:
+                obj = soc_ifc_env_mbox_rand_delay_large_sequence_t::get_type().create_object($sformatf("soc_ifc_env_mbox_multi_agent_seq[%0d]",ii));
             PAUSER_SMALL:
                 obj = soc_ifc_env_mbox_rand_pauser_small_sequence_t::get_type().create_object($sformatf("soc_ifc_env_mbox_multi_agent_seq[%0d]",ii));
             PAUSER_MEDIUM:
@@ -183,7 +227,7 @@ task soc_ifc_env_mbox_rand_multi_agent_sequence::start_seqs();
 
     `uvm_info("SOC_IFC_MBOX", $sformatf("Initiating [%0d] mailbox sequences in parallel", agents), UVM_LOW)
     foreach (soc_ifc_env_mbox_multi_agent_seq[ii]) begin
-        if (!std::randomize(delay_clks[ii]) with {delay_clks[ii] < 4*soc_ifc_env_mbox_multi_agent_seq[ii].mbox_op_rand.dlen;}) begin
+        if (!std::randomize(delay_clks[ii]) with {delay_clks[ii] < 4*(soc_ifc_env_mbox_multi_agent_seq[ii].mbox_op_rand.dlen+20); delay_clks[ii] > 0;}) begin
             `uvm_fatal("SOC_IFC_MBOX", $sformatf("soc_ifc_env_mbox_rand_multi_agent_sequence::body() - %s randomization failed", "delay_clks"));
         end
         else
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_real_fw_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_real_fw_sequence.svh
index 5bb57d966..3b8134b3f 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_real_fw_sequence.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_real_fw_sequence.svh
@@ -76,7 +76,7 @@ task soc_ifc_env_mbox_real_fw_sequence::mbox_push_datain();
     `uvm_info("MBOX_SEQ", $sformatf("Starting FW push_datain, ICCM region ends at [0x%x] and DCCM region ends at [0x%x]", firmware_iccm_end, firmware_end), UVM_LOW)
     for (ii=0; ii < firmware_end_dw; ii++) begin
         data = uvm_reg_data_t'({fw_img[ii][3],fw_img[ii][2],fw_img[ii][1],fw_img[ii][0]});
-        `uvm_info("MBOX_SEQ", $sformatf("[Iteration: %0d] Sending datain: 0x%x", ii/4, data), UVM_DEBUG)
+        `uvm_info("MBOX_SEQ", $sformatf("[Iteration: %0d] Sending datain: 0x%x", ii, data), UVM_DEBUG)
         reg_model.mbox_csr_rm.mbox_datain.write(reg_sts, uvm_reg_data_t'(data), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(PAUSER_PROB_DATAIN)));
         report_reg_sts(reg_sts, "mbox_datain");
     end
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_reg_axs_invalid_large_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_reg_axs_invalid_large_sequence.svh
new file mode 100644
index 000000000..3be9c04ba
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_reg_axs_invalid_large_sequence.svh
@@ -0,0 +1,41 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Extended from mbox_base sequence to provide additional
+//              functionality in a test that sends large commands.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_mbox_reg_axs_invalid_large_sequence extends soc_ifc_env_mbox_reg_axs_invalid_sequence;
+
+  `uvm_object_utils( soc_ifc_env_mbox_reg_axs_invalid_large_sequence )
+
+  // Constrain size to a large command
+  // Min. size: 16KiB
+  constraint mbox_dlen_min_large_c { mbox_op_rand.dlen > 32'h0000_4000; }
+  // Constrain response data size to also be large
+  // Min. size: 16KiB
+  constraint mbox_resp_dlen_min_large_c { mbox_op_rand.cmd.cmd_s.resp_reqd -> mbox_resp_expected_dlen >= 32'h0000_4000; }
+  // Valid solution for the custom delay ruleset, to control random delays while
+  // waiting to inject random error accesses
+  constraint custom_delay_c { rand_delay > 0; rand_delay < (mbox_op_rand.dlen * 5); }
+
+endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_reg_axs_invalid_medium_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_reg_axs_invalid_medium_sequence.svh
new file mode 100644
index 000000000..674413d75
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_reg_axs_invalid_medium_sequence.svh
@@ -0,0 +1,45 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Extended from mbox_base sequence to provide additional
+//              functionality in a test that sends medium-sized mailbox commands.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_mbox_reg_axs_invalid_medium_sequence extends soc_ifc_env_mbox_reg_axs_invalid_sequence;
+
+  `uvm_object_utils( soc_ifc_env_mbox_reg_axs_invalid_medium_sequence )
+
+  // Constrain dlen to be a medium command
+  // Max. size: 4096B
+  constraint mbox_dlen_max_medium_c { mbox_op_rand.dlen <= 32'h0000_1000; }
+  // Minimum 512B
+  constraint mbox_dlen_min_medium_c { mbox_op_rand.dlen >= 32'h0000_0200; }
+  // Constrain response data size to also be medium
+  // Max. size: 4096B
+  // Min. size: 512B
+  constraint mbox_resp_dlen_max_medium_c { mbox_resp_expected_dlen <= 32'h0000_1000; }
+  constraint mbox_resp_dlen_min_medium_c { mbox_op_rand.cmd.cmd_s.resp_reqd -> mbox_resp_expected_dlen >= 32'h0000_0200; }
+  // Valid solution for the custom delay ruleset, to control random delays while
+  // waiting to inject random error accesses
+  constraint custom_delay_c { rand_delay > 0; rand_delay < (mbox_op_rand.dlen * 12); }
+
+endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_reg_axs_invalid_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_reg_axs_invalid_sequence.svh
new file mode 100644
index 000000000..e0112ea05
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_reg_axs_invalid_sequence.svh
@@ -0,0 +1,194 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Extended from mbox_base sequence to provide additional
+//              functionality in a test that sends mailbox commands
+//              of a size that exceeds mailbox capacity.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_mbox_reg_axs_invalid_sequence extends soc_ifc_env_mbox_sequence_base;
+
+  `uvm_object_utils( soc_ifc_env_mbox_reg_axs_invalid_sequence )
+
+  // Constrain command to undefined opcode
+  constraint mbox_cmd_undef_c { !(mbox_op_rand.cmd.cmd_s inside {defined_cmds}); }
+
+  extern virtual task                    mbox_do_random_reg_write(process mainline);
+  extern virtual function uvm_reg_data_t get_rand_wr_data(uvm_reg axs_reg);
+
+  function new(string name = "" );
+    super.new(name);
+  endfunction
+
+  //==========================================
+  // Task:        body
+  // Description: Implement main functionality for
+  //              SOC-side transmission of mailbox request.
+  //              Override default body to inject random
+  //              (deliberately erroneous) register accesses
+  //              throughout a normal test flow.
+  //==========================================
+  virtual task body();
+
+    op_sts_e op_sts;
+    process mbox_flow_proc;
+
+    sts_rsp_count = 0;
+
+    fork
+        forever begin
+            @(soc_ifc_status_agent_rsp_seq.new_rsp) sts_rsp_count++;
+        end
+    join_none
+
+    `uvm_info("MBOX_SEQ", $sformatf("Initiating command sequence to mailbox with cmd: [%p] dlen: [%p] resp_dlen: [%p]", mbox_op_rand.cmd.cmd_e, mbox_op_rand.dlen, mbox_resp_expected_dlen), UVM_MEDIUM)
+
+    fork
+        begin: MBOX_FLOW
+            mbox_flow_proc = process::self();
+            mbox_setup();               if (rand_delay_en) do_rand_delay(1, step_delay);
+            mbox_acquire_lock(op_sts);  if (rand_delay_en) do_rand_delay(1, step_delay);
+            mbox_set_cmd(mbox_op_rand); if (rand_delay_en) do_rand_delay(1, step_delay);
+            mbox_push_datain();         if (rand_delay_en) do_rand_delay(1, step_delay);
+            mbox_execute();             if (rand_delay_en) do_rand_delay(1, step_delay);
+            mbox_poll_status();         if (rand_delay_en) do_rand_delay(1, step_delay);
+        end
+        begin: ERR_INJECT_FLOW
+            wait(mbox_flow_proc != null);
+            mbox_do_random_reg_write(mbox_flow_proc);
+        end
+    join
+    mbox_clr_execute();         if (rand_delay_en) do_rand_delay(1, step_delay);
+    mbox_teardown();
+
+  endtask
+
+endclass
+
+//==========================================
+// Task:        mbox_do_random_reg_write
+// Description: Do some random reg write that will
+//              (most likely) be invalid and trigger
+//              the protocol error violation.
+//==========================================
+task soc_ifc_env_mbox_reg_axs_invalid_sequence::mbox_do_random_reg_write(process mainline);
+    uvm_reg mbox_regs[$];
+    int unsigned rand_idx;
+    uvm_reg_data_t rand_wr_data;
+    caliptra_apb_user local_apb_user_obj;
+    uvm_status_e local_reg_sts;
+
+    mbox_regs.push_back(reg_model.mbox_csr_rm.mbox_cmd    );
+    mbox_regs.push_back(reg_model.mbox_csr_rm.mbox_dlen   );
+    mbox_regs.push_back(reg_model.mbox_csr_rm.mbox_datain );
+    mbox_regs.push_back(reg_model.mbox_csr_rm.mbox_dataout);
+    mbox_regs.push_back(reg_model.mbox_csr_rm.mbox_execute);
+    mbox_regs.push_back(reg_model.mbox_csr_rm.mbox_status );
+
+    if (!std::randomize(rand_idx) with {rand_idx < mbox_regs.size(); })
+        `uvm_fatal("MBOX_SEQ", "Failed to randomize reg idx")
+
+    // Wait and do the reg write at some random point in the sequence
+    do_rand_delay(1, DLY_CUSTOM);
+    // Data used depends on which reg is being accessed to force invalid contents
+    rand_wr_data = get_rand_wr_data(mbox_regs[rand_idx]);
+    // Get a randomized PAUSER for this transaction - 50% chance of being valid
+    local_apb_user_obj = new();
+    if (!local_apb_user_obj.randomize() with {if (pauser_locked.locked)
+                                                       (addr_user == pauser_locked.pauser) dist
+                                                       {1 :/ 1,
+                                                        0 :/ 1};
+                                                   else
+                                                       (addr_user inside {mbox_valid_users}) dist
+                                                       {1 :/ 1,
+                                                        0 :/ 1}; })
+        `uvm_error("MBOX_SEQ", "Failed to randomize APB PAUSER override value")
+    else
+        `uvm_info("MBOX_SEQ", $sformatf("Randomized APB PAUSER override value to 0x%x", local_apb_user_obj.addr_user), UVM_HIGH)
+    // Pause the main mailbox flow to prevent race conditions (on accesses to the same register, triggering is_busy UVM_WARNING)
+    if (mainline.status() inside {process::RUNNING,process::WAITING}) begin
+        in_report_reg_sts.wait_on();
+        `uvm_info("MBOX_SEQ", $sformatf("Pausing main mailbox flow to allow random reg access injection"), UVM_HIGH)
+        mainline.suspend();
+        in_report_reg_sts.reset();
+    end
+    else begin
+        `uvm_info("MBOX_SEQ", $sformatf("Main mailbox flow is in state [%s], so it will not be suspended for random reg access injection", mainline.status().name()), UVM_HIGH)
+    end
+    if (mbox_regs[rand_idx].get_name() == "mbox_dataout") begin
+        `uvm_info("MBOX_SEQ", {"Performing random register access to ", mbox_regs[rand_idx].get_name()}, UVM_LOW)
+        mbox_regs[rand_idx].read(local_reg_sts, rand_wr_data, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(local_apb_user_obj));
+        report_reg_sts(local_reg_sts, mbox_regs[rand_idx].get_name(), local_apb_user_obj);
+    end
+    else if (mbox_regs[rand_idx].get_name() == "mbox_datain") begin
+        `uvm_info("MBOX_SEQ", {"Performing random register access to ", mbox_regs[rand_idx].get_name()}, UVM_LOW)
+        mbox_regs[rand_idx].write(local_reg_sts, rand_wr_data, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(local_apb_user_obj));
+        report_reg_sts(local_reg_sts, mbox_regs[rand_idx].get_name(), local_apb_user_obj);
+    end
+    else begin
+        `uvm_info("MBOX_SEQ", {"Performing random register access to ", mbox_regs[rand_idx].get_name()}, UVM_LOW)
+        mbox_regs[rand_idx].write(local_reg_sts, rand_wr_data, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(local_apb_user_obj));
+        report_reg_sts(local_reg_sts, mbox_regs[rand_idx].get_name(), local_apb_user_obj);
+    end
+    if (mainline.status() == process::SUSPENDED) begin
+        `uvm_info("MBOX_SEQ", $sformatf("Resuming main mailbox flow after random reg access injection"), UVM_HIGH)
+        mainline.resume();
+    end
+endtask
+
+//==========================================
+// Task:        get_rand_wr_data
+// Description: Generate random data according
+//              to a set of rules related to which register
+//              is being accessed, with intent to cause
+//              a protocol violation.
+//==========================================
+function uvm_reg_data_t soc_ifc_env_mbox_reg_axs_invalid_sequence::get_rand_wr_data(uvm_reg axs_reg);
+    uvm_reg_data_t tmp_data;
+    case (axs_reg.get_name()) inside
+        "mbox_cmd": begin
+            tmp_data = mbox_op_rand.cmd;
+        end
+        "mbox_dlen": begin
+            tmp_data = mbox_op_rand.dlen; 
+        end
+        "mbox_datain",
+        "mbox_dataout": begin
+            std::randomize(tmp_data);
+        end
+        "mbox_execute": begin
+            uvm_reg_data_t msk;
+            msk = ~(uvm_reg_data_t'(1) << reg_model.mbox_csr_rm.mbox_execute.execute.get_lsb_pos());
+            std::randomize(tmp_data) with {(tmp_data & msk) == 0;};
+        end
+        "mbox_status": begin
+            uvm_reg_data_t msk;
+            msk = ((uvm_reg_data_t'(1) << reg_model.mbox_csr_rm.mbox_status.status.get_n_bits()) - 1) << reg_model.mbox_csr_rm.mbox_status.status.get_lsb_pos();
+            msk = ~msk;
+            std::randomize(tmp_data) with {(tmp_data & msk) == 0;};
+        end
+        default: begin
+            `uvm_fatal("MBOX_SEQ", "Bad reg")
+        end
+    endcase
+    return tmp_data;
+endfunction
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_reg_axs_invalid_small_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_reg_axs_invalid_small_sequence.svh
new file mode 100644
index 000000000..33429c4e8
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_reg_axs_invalid_small_sequence.svh
@@ -0,0 +1,41 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Extended from mbox_base sequence to provide additional
+//              functionality in a test that sends small mailbox commands.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_mbox_reg_axs_invalid_small_sequence extends soc_ifc_env_mbox_reg_axs_invalid_sequence;
+
+  `uvm_object_utils( soc_ifc_env_mbox_reg_axs_invalid_small_sequence )
+
+  // Constrain dlen to be a small command
+  // Max. size: 512B
+  constraint mbox_dlen_max_small_c { mbox_op_rand.dlen <= 32'h0000_0200; }
+  // Constrain response data size to also be small
+  // Max. size: 512B
+  constraint mbox_resp_dlen_max_small_c { mbox_resp_expected_dlen < 32'h0000_0200; }
+  // Valid solution for the custom delay ruleset, to control random delays while
+  // waiting to inject random error accesses
+  constraint custom_delay_c { rand_delay > 0; rand_delay < (mbox_op_rand.dlen * 25); }
+
+endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_rom_fw_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_rom_fw_sequence.svh
new file mode 100644
index 000000000..5e265b325
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_rom_fw_sequence.svh
@@ -0,0 +1,73 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Extended from mbox_base sequence to complete a FW update
+//              against the actual (FW-team developed) ROM.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_mbox_rom_fw_sequence extends soc_ifc_env_mbox_sequence_base;
+
+  `uvm_object_utils( soc_ifc_env_mbox_rom_fw_sequence )
+
+  // 128KiB memory, with 32768 single-dword entries
+  bit [7:0] fw_img [soc_ifc_pkg::MBOX_DEPTH][soc_ifc_pkg::MBOX_DATA_W/8-1:0];    
+
+  extern virtual task mbox_setup();
+  extern virtual task mbox_push_datain();
+
+  // This shouldn't be randomized, specify it
+  constraint mbox_cmd_c { mbox_op_rand.cmd == mbox_cmd_e'(MBOX_CMD_ROM_FW_UPD); }
+  constraint mbox_dlen_c { mbox_op_rand.dlen == 13708; }
+  // Response data is only non-zero if a response is requested, and also must
+  // be small enough to fit in the mailbox
+  // Firmware team encodes commands differently from this environment; response
+  // bit is different, and ROM doesn't expect to provide a response for fw update.
+  // Override to force this to 0.
+  constraint mbox_resp_dlen_c { mbox_resp_expected_dlen == 0; }
+
+endclass
+
+task soc_ifc_env_mbox_rom_fw_sequence::mbox_setup();
+    super.mbox_setup();
+    //read FW from file to write to mailbox
+    $readmemh("fw_update.hex", fw_img);
+endtask
+
+// This should be overridden with real data to write
+task soc_ifc_env_mbox_rom_fw_sequence::mbox_push_datain();
+    int ii;
+    int firmware_end_dw;
+    uvm_reg_data_t data;
+
+    firmware_end_dw = this.mbox_op_rand.dlen / 4 + (this.mbox_op_rand.dlen%4 ? 1 : 0);
+
+    `uvm_info("MBOX_SEQ", $sformatf("Starting FW push_datain. Size: [0x%x] dwords", firmware_end_dw), UVM_LOW)
+    for (ii=0; ii < firmware_end_dw; ii++) begin
+        data = uvm_reg_data_t'({fw_img[ii][3],fw_img[ii][2],fw_img[ii][1],fw_img[ii][0]});
+        if (ii < 10)
+            `uvm_info("MBOX_SEQ", $sformatf("[Iteration: %0d] Sending datain: 0x%x", ii, data), UVM_LOW)
+        else
+            `uvm_info("MBOX_SEQ", $sformatf("[Iteration: %0d] Sending datain: 0x%x", ii, data), UVM_DEBUG)
+        reg_model.mbox_csr_rm.mbox_datain.write(reg_sts, uvm_reg_data_t'(data), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(PAUSER_PROB_DATAIN)));
+        report_reg_sts(reg_sts, "mbox_datain");
+    end
+endtask
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sequence_base.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sequence_base.svh
index db657059f..166e40bc7 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sequence_base.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sequence_base.svh
@@ -38,8 +38,22 @@ class soc_ifc_env_mbox_sequence_base extends soc_ifc_env_sequence_base #(.CONFIG
   rand int mbox_resp_expected_dlen; // Number of response data bytes to expect
   int sts_rsp_count;
   uvm_status_e reg_sts;
+  uvm_event in_report_reg_sts;
   rand bit do_apb_lock_check;
   rand bit retry_failed_reg_axs;
+
+  typedef enum byte {
+    DLY_ZERO,
+    DLY_SMALL,
+    DLY_MEDIUM,
+    DLY_LARGE,
+    DLY_CUSTOM
+  } delay_scale_e;
+
+  rand delay_scale_e poll_delay, step_delay, data_delay;
+  rand bit rand_delay_en = 0;
+  rand int unsigned rand_delay = 0;
+
   // Certain random sequences force the command to be outside of the defined
   // options from mbox_cmd_e, such that truly random behavior does not violate
   // expected activity for the command opcode. To do this, we need to be able
@@ -78,10 +92,11 @@ class soc_ifc_env_mbox_sequence_base extends soc_ifc_env_sequence_base #(.CONFIG
   extern virtual task mbox_clr_execute();
   extern virtual task mbox_teardown();
 
+  extern virtual task                       do_rand_delay(input bit do_delay_randomize=1, input delay_scale_e scale=DLY_SMALL);
   extern virtual function void              set_pauser_prob_vals();
-  extern virtual function bit               pauser_used_is_valid();
+  extern virtual function bit               pauser_used_is_valid(caliptra_apb_user user_handle = null);
   extern virtual function caliptra_apb_user get_rand_user(int unsigned invalid_prob = FORCE_VALID_PAUSER);
-  extern virtual function void              report_reg_sts(uvm_status_e reg_sts, string name);
+  extern virtual task                       report_reg_sts(uvm_status_e reg_sts, string name, caliptra_apb_user user_handle = null);
 
   // Constrain command to not be firmware or uC-initiated
   constraint mbox_cmd_c { mbox_op_rand.cmd.cmd_s.fw        == 1'b0;
@@ -89,13 +104,13 @@ class soc_ifc_env_mbox_sequence_base extends soc_ifc_env_sequence_base #(.CONFIG
 
   // Constrain size to less than 128KiB for now (mailbox size), but we will
   // recalculate this based on the command being sent
-  constraint mbox_dlen_max_c { mbox_op_rand.dlen <= 32'h0002_0000; }
+  constraint mbox_dlen_max_c { mbox_op_rand.dlen <= MBOX_SIZE_BYTES; }
   // Minimum 2 dwords to include dlen/mbox_resp_expected_dlen at the beginning
   // IFF the response data is required
   constraint mbox_dlen_min_c { mbox_op_rand.cmd.cmd_s.resp_reqd -> mbox_op_rand.dlen >= 32'h8; }
   // Response data is only non-zero if a response is requested, and also must
   // be small enough to fit in the mailbox
-  constraint mbox_resp_dlen_c {                                      mbox_resp_expected_dlen <= 32'h0002_0000;
+  constraint mbox_resp_dlen_c {                                      mbox_resp_expected_dlen <= MBOX_SIZE_BYTES;
                                 !mbox_op_rand.cmd.cmd_s.resp_reqd -> mbox_resp_expected_dlen == 0;
                                  mbox_op_rand.cmd.cmd_s.resp_reqd -> mbox_resp_expected_dlen >  0; }
 
@@ -106,6 +121,36 @@ class soc_ifc_env_mbox_sequence_base extends soc_ifc_env_sequence_base #(.CONFIG
   constraint apb_reg_check_c {do_apb_lock_check dist {0:/1, 1:/1};}
   constraint retry_failed_reg_c {retry_failed_reg_axs == 1'b1;}
 
+  // Constraint on the random delays injected between each step of the flow.
+  // By default, delays minimal to avoid protracting the test too much.
+  // Targeted sequences may override this constraint.
+  constraint delay_scale_c { poll_delay == DLY_MEDIUM;
+                             step_delay == DLY_SMALL;
+                             data_delay == DLY_ZERO; }
+  // Should not be overridden
+  constraint delay_scale_valid_c { poll_delay != DLY_CUSTOM;
+                                   step_delay != DLY_CUSTOM;
+                                   data_delay != DLY_CUSTOM; }
+  // These constraints conflict with each other - only the one that is applicable
+  // should be enabled; this is done in the definition of do_rand_delay
+  constraint zero_delay_c  { rand_delay == 0;}
+  constraint small_delay_c { rand_delay dist {   0  :/ 1000,
+                                              [1:3] :/ 100,
+                                              [4:7] :/ 25,
+                                              [8:31]:/ 1};}
+  constraint medium_delay_c { rand_delay dist {   0    :/ 10,
+                                               [1:7]   :/ 50,
+                                               [8:31]  :/ 100,
+                                               [32:255]:/ 50};}
+  constraint large_delay_c { rand_delay dist {        15  :/ 1,
+                                              [ 16 : 255] :/ 50,
+                                              [ 256:1023] :/ 100,
+                                              [1024:8191] :/ 25};}
+  // This deliberately intractable constraint must be overridden
+  // by a child sequence if random delays are expected to be driven
+  // by some custom rule set.
+  constraint custom_delay_c { rand_delay == 0; rand_delay == 1; }
+
   //==========================================
   // Function:    new
   // Description: Constructor
@@ -124,6 +169,16 @@ class soc_ifc_env_mbox_sequence_base extends soc_ifc_env_sequence_base #(.CONFIG
 
     // Assign probabilties of generating invalid PAUSER at different stages
     set_pauser_prob_vals();
+
+    // Default constraint mode is SMALL random delays, updated when doing
+    // the delay
+    this.zero_delay_c  .constraint_mode(0);
+    this.small_delay_c .constraint_mode(1);
+    this.medium_delay_c.constraint_mode(0);
+    this.large_delay_c .constraint_mode(0);
+    this.custom_delay_c.constraint_mode(0);
+
+    in_report_reg_sts = new("in_report_reg_sts");
   endfunction
 
   //==========================================
@@ -153,8 +208,10 @@ class soc_ifc_env_mbox_sequence_base extends soc_ifc_env_sequence_base #(.CONFIG
 
     // Randomization checker requires a valid handle to reg-model, which it gets
     // from the configuration object (which is not set until pre_body())
-    assert(mbox_op_rand.dlen <= (reg_model.mbox_mem_rm.get_size() * reg_model.mbox_mem_rm.get_n_bytes())) else
-        `uvm_error("MBOX_SEQ", $sformatf("Randomized SOC_IFC environment mailbox base sequence with bad dlen. Max: [0x%x] Got: [0x%x]. Cmd randomized to %p", (reg_model.mbox_mem_rm.get_size() * reg_model.mbox_mem_rm.get_n_bytes()), mbox_op_rand.dlen, mbox_op_rand.cmd.cmd_e))
+    // This is only an 'info' instead of an error because some tests do this
+    // deliberately
+    if (mbox_op_rand.dlen > (reg_model.mbox_mem_rm.get_size() * reg_model.mbox_mem_rm.get_n_bytes()))
+        `uvm_info("MBOX_SEQ", $sformatf("Randomized SOC_IFC environment mailbox base sequence with invalid dlen. Max: [0x%x] Got: [0x%x]. Cmd randomized to %p", (reg_model.mbox_mem_rm.get_size() * reg_model.mbox_mem_rm.get_n_bytes()), mbox_op_rand.dlen, mbox_op_rand.cmd.cmd_e), UVM_LOW)
   endtask
 
   //==========================================
@@ -176,13 +233,13 @@ class soc_ifc_env_mbox_sequence_base extends soc_ifc_env_sequence_base #(.CONFIG
 
     `uvm_info("MBOX_SEQ", $sformatf("Initiating command sequence to mailbox with cmd: [%p] dlen: [%p] resp_dlen: [%p]", mbox_op_rand.cmd.cmd_e, mbox_op_rand.dlen, mbox_resp_expected_dlen), UVM_MEDIUM)
 
-    mbox_setup();
-    mbox_acquire_lock(op_sts);
-    mbox_set_cmd(mbox_op_rand);
-    mbox_push_datain();
-    mbox_execute();
-    mbox_poll_status();
-    mbox_clr_execute();
+    mbox_setup();               if (rand_delay_en) do_rand_delay(1, step_delay);
+    mbox_acquire_lock(op_sts);  if (rand_delay_en) do_rand_delay(1, step_delay);
+    mbox_set_cmd(mbox_op_rand); if (rand_delay_en) do_rand_delay(1, step_delay);
+    mbox_push_datain();         if (rand_delay_en) do_rand_delay(1, step_delay);
+    mbox_execute();             if (rand_delay_en) do_rand_delay(1, step_delay);
+    mbox_poll_status();         if (rand_delay_en) do_rand_delay(1, step_delay);
+    mbox_clr_execute();         if (rand_delay_en) do_rand_delay(1, step_delay);
     mbox_teardown();
 
   endtask
@@ -240,7 +297,7 @@ task soc_ifc_env_mbox_sequence_base::mbox_acquire_lock(output op_sts_e op_sts);
     report_reg_sts(reg_sts, "mbox_lock");
     // Wait for read data to return with '0', indicating no other agent has lock
     while (data[reg_model.mbox_csr_rm.mbox_lock.lock.get_lsb_pos()]) begin
-        configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(200); // FIXME add more randomization on delay
+        do_rand_delay(1, poll_delay);
         reg_model.mbox_csr_rm.mbox_lock.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(PAUSER_PROB_LOCK)));
         report_reg_sts(reg_sts, "mbox_lock");
     end
@@ -279,7 +336,7 @@ task soc_ifc_env_mbox_sequence_base::mbox_acquire_lock(output op_sts_e op_sts);
             report_reg_sts(reg_sts, "mbox_lock");
             // Wait for read data to return with '0', indicating no other agent has lock
             while (data[reg_model.mbox_csr_rm.mbox_lock.lock.get_lsb_pos()]) begin
-                configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(200);
+                do_rand_delay(1, poll_delay);
                 reg_model.mbox_csr_rm.mbox_lock.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(this.apb_user_obj));
                 report_reg_sts(reg_sts, "mbox_lock");
             end
@@ -328,14 +385,16 @@ endtask
 //              mbox_cmd and mbox_dlen registers
 //==========================================
 task soc_ifc_env_mbox_sequence_base::mbox_set_cmd(input mbox_op_s op);
-    uvm_reg_data_t data;
+    uvm_reg_data_t data, prev_data;
 
+    prev_data = reg_model.mbox_csr_rm.mbox_cmd.get_mirrored_value();
     reg_model.mbox_csr_rm.mbox_cmd.write(reg_sts, uvm_reg_data_t'(op.cmd), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(PAUSER_PROB_CMD)));
     report_reg_sts(reg_sts, "mbox_cmd");
     if (!pauser_used_is_valid()) begin
+        if (rand_delay_en) do_rand_delay(1, step_delay);
         reg_model.mbox_csr_rm.mbox_cmd.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(FORCE_VALID_PAUSER)));
         report_reg_sts(reg_sts, "mbox_cmd");
-        if (mbox_cmd_u'(data) == op.cmd)
+        if (data != prev_data)
             `uvm_error("MBOX_SEQ", "Write to mbox_cmd succeeded unexpectedly with invalid PAUSER!")
         else if (retry_failed_reg_axs) begin
             reg_model.mbox_csr_rm.mbox_cmd.write(reg_sts, uvm_reg_data_t'(op.cmd), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(FORCE_VALID_PAUSER)));
@@ -343,12 +402,16 @@ task soc_ifc_env_mbox_sequence_base::mbox_set_cmd(input mbox_op_s op);
         end
     end
 
+    if (rand_delay_en) do_rand_delay(1, step_delay);
+
+    prev_data = reg_model.mbox_csr_rm.mbox_dlen.get_mirrored_value();
     reg_model.mbox_csr_rm.mbox_dlen.write(reg_sts, uvm_reg_data_t'(op.dlen), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(PAUSER_PROB_CMD)));
     report_reg_sts(reg_sts, "mbox_dlen");
     if (!pauser_used_is_valid()) begin
+        if (rand_delay_en) do_rand_delay(1, step_delay);
         reg_model.mbox_csr_rm.mbox_dlen.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(FORCE_VALID_PAUSER)));
         report_reg_sts(reg_sts, "mbox_dlen");
-        if (32'(data) == op.dlen)
+        if (32'(data) != prev_data)
             `uvm_error("MBOX_SEQ", "Write to mbox_dlen succeeded unexpectedly with invalid PAUSER!")
         else if (retry_failed_reg_axs)  begin
             reg_model.mbox_csr_rm.mbox_dlen.write(reg_sts, uvm_reg_data_t'(op.dlen), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(FORCE_VALID_PAUSER)));
@@ -379,10 +442,12 @@ task soc_ifc_env_mbox_sequence_base::mbox_push_datain();
         reg_model.mbox_csr_rm.mbox_datain.write(reg_sts, uvm_reg_data_t'(data), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(PAUSER_PROB_DATAIN)));
         report_reg_sts(reg_sts, "mbox_datain");
         if (!pauser_used_is_valid() && retry_failed_reg_axs) begin
+            if (rand_delay_en) do_rand_delay(1, data_delay);
             `uvm_info("MBOX_SEQ", "Re-do datain write with valid PAUSER", UVM_HIGH)
             reg_model.mbox_csr_rm.mbox_datain.write(reg_sts, uvm_reg_data_t'(data), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(FORCE_VALID_PAUSER)));
             report_reg_sts(reg_sts, "mbox_datain");
         end
+        if (rand_delay_en) do_rand_delay(1, data_delay);
     end
 endtask
 
@@ -396,6 +461,7 @@ task soc_ifc_env_mbox_sequence_base::mbox_execute();
     reg_model.mbox_csr_rm.mbox_execute.write(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(PAUSER_PROB_EXECUTE)));
     report_reg_sts(reg_sts, "mbox_execute");
     if (!pauser_used_is_valid() && retry_failed_reg_axs) begin
+        if (rand_delay_en) do_rand_delay(1, step_delay);
         reg_model.mbox_csr_rm.mbox_execute.write(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(FORCE_VALID_PAUSER)));
         report_reg_sts(reg_sts, "mbox_execute");
     end
@@ -430,15 +496,34 @@ endtask
 //==========================================
 task soc_ifc_env_mbox_sequence_base::mbox_read_resp_data();
     uvm_reg_data_t data;
+    uvm_reg_data_t dlen;
     int ii;
-    for (ii=0; ii < mbox_resp_expected_dlen; ii+=4) begin
+    reg_model.mbox_csr_rm.mbox_dlen.read(reg_sts, dlen, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(PAUSER_PROB_DATAOUT)));
+    report_reg_sts(reg_sts, "mbox_dlen");
+    if (!pauser_used_is_valid() && retry_failed_reg_axs) begin
+        reg_model.mbox_csr_rm.mbox_dlen.read(reg_sts, dlen, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(FORCE_VALID_PAUSER)));
+        report_reg_sts(reg_sts, "mbox_dlen");
+    end
+    if (dlen != mbox_resp_expected_dlen) begin
+        if (this.get_type_name() inside {"soc_ifc_env_mbox_reg_axs_invalid_sequence",
+                                         "soc_ifc_env_mbox_reg_axs_invalid_small_sequence",
+                                         "soc_ifc_env_mbox_reg_axs_invalid_medium_sequence",
+                                         "soc_ifc_env_mbox_reg_axs_invalid_large_sequence"})
+            `uvm_info("MBOX_SEQ", $sformatf("SOC received response data with mbox_dlen [%0d] that does not match the expected data amount [%0d]! Not flagging err since this is an invalid reg-access sequence [%s]", dlen, mbox_resp_expected_dlen, this.get_type_name()), UVM_LOW)
+        else
+            `uvm_error("MBOX_SEQ", $sformatf("SOC received response data with mbox_dlen [%0d] that does not match the expected data amount [%0d]!", dlen, mbox_resp_expected_dlen))
+    end
+    if (rand_delay_en) do_rand_delay(1, step_delay);
+    for (ii=0; ii < dlen; ii+=4) begin
         reg_model.mbox_csr_rm.mbox_dataout.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(PAUSER_PROB_DATAOUT)));
         report_reg_sts(reg_sts, "mbox_dataout");
         if (!pauser_used_is_valid() && retry_failed_reg_axs) begin
+            if (rand_delay_en) do_rand_delay(1, data_delay);
             `uvm_info("MBOX_SEQ", "Re-do dataout read with valid PAUSER", UVM_HIGH)
             reg_model.mbox_csr_rm.mbox_dataout.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(FORCE_VALID_PAUSER)));
             report_reg_sts(reg_sts, "mbox_dataout");
         end
+        if (rand_delay_en) do_rand_delay(1, data_delay);
     end
 endtask
 
@@ -456,7 +541,7 @@ task soc_ifc_env_mbox_sequence_base::mbox_poll_status();
 
     // A force-unlock would cause state->MBOX_IDLE, so we exit the polling loop
     do begin
-        configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(200);
+        do_rand_delay(1, poll_delay);
         mbox_check_status(data, state);
     end while (data == CMD_BUSY && state != MBOX_IDLE);
 
@@ -464,21 +549,34 @@ task soc_ifc_env_mbox_sequence_base::mbox_poll_status();
         `uvm_info("MBOX_SEQ", "Detected mailbox state transition to IDLE - was mbox_unlock expected?", UVM_HIGH)
     end
     else if (data == DATA_READY) begin
-        if (mbox_resp_expected_dlen == 0)
+        if (mbox_resp_expected_dlen == 0 && sts_rsp_count > 0 && soc_ifc_status_agent_rsp_seq.rsp.cptra_error_non_fatal_intr_pending) begin
+            `uvm_info("MBOX_SEQ", $sformatf("Unexpected status [%p] likely is the result of a spurious reg access injection specifically intended to cause a protocol violation", data), UVM_HIGH)
+        end
+        else if (mbox_resp_expected_dlen == 0)
             `uvm_error("MBOX_SEQ", $sformatf("Received status %p when not expecting any bytes of response data!", data))
         else begin
             mbox_read_resp_data();
         end
     end
     else if (data == CMD_FAILURE) begin
-        `uvm_error("MBOX_SEQ", $sformatf("Received unexpected mailbox status %p", data))
+        if (sts_rsp_count > 0 && soc_ifc_status_agent_rsp_seq.rsp.cptra_error_non_fatal_intr_pending) begin
+            `uvm_info("MBOX_SEQ", $sformatf("Unexpected mailbox status [%p] likely is the result of a spurious reg access injection specifically intended to cause a protocol violation or a mailbox SRAM double bit flip", data), UVM_HIGH)
+        end
+        else begin
+            `uvm_error("MBOX_SEQ", $sformatf("Received mailbox status %p unexpectedly, since there is no pending non_fatal error interrupt", data))
+        end
     end
     else if (data == CMD_COMPLETE) begin
-        if (mbox_resp_expected_dlen != 0)
+        if (mbox_resp_expected_dlen != 0 && sts_rsp_count > 0 && soc_ifc_status_agent_rsp_seq.rsp.cptra_error_non_fatal_intr_pending)
+            `uvm_info("MBOX_SEQ", $sformatf("Unexpected status [%p] when expecting 0x%x bytes of response data likely is the result of a spurious reg access injection specifically intended to cause a protocol violation", data, mbox_resp_expected_dlen), UVM_HIGH)
+        else if (mbox_resp_expected_dlen != 0)
             `uvm_error("MBOX_SEQ", $sformatf("Received status %p when expecting 0x%x bytes of response data!", data, mbox_resp_expected_dlen))
     end
     else begin
-        `uvm_error("MBOX_SEQ", $sformatf("Received unexpected mailbox status %p", data))
+        if (sts_rsp_count > 0 && soc_ifc_status_agent_rsp_seq.rsp.cptra_error_non_fatal_intr_pending)
+            `uvm_info("MBOX_SEQ", $sformatf("Unexpected mailbox status [%p] likely is the result of a spurious reg access injection specifically intended to cause a protocol violation", data), UVM_HIGH)
+        else
+            `uvm_error("MBOX_SEQ", $sformatf("Received unexpected mailbox status [%p]", data))
     end
 endtask
 
@@ -488,12 +586,32 @@ endtask
 //              0 to mbox_execute register
 //==========================================
 task soc_ifc_env_mbox_sequence_base::mbox_clr_execute();
+    uvm_reg_data_t err;
+
+    // Write 0 to mbox_execute to clear mbox_lock and end the test
     reg_model.mbox_csr_rm.mbox_execute.write(reg_sts, uvm_reg_data_t'(0), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(PAUSER_PROB_EXECUTE)));
     report_reg_sts(reg_sts, "mbox_execute");
     if (!pauser_used_is_valid() && retry_failed_reg_axs) begin
+        if (rand_delay_en) do_rand_delay(1, step_delay);
         reg_model.mbox_csr_rm.mbox_execute.write(reg_sts, uvm_reg_data_t'(0), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(FORCE_VALID_PAUSER)));
         report_reg_sts(reg_sts, "mbox_execute");
     end
+
+    if (rand_delay_en) do_rand_delay(1, step_delay);
+
+    // Check for any non-fatal mailbox protocol or sram errors that occurred during the test
+    reg_model.soc_ifc_reg_rm.CPTRA_HW_ERROR_NON_FATAL.read(reg_sts, err, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(500)));
+    // don't use report_reg_sts since this isn't a mbox reg and doesn't have pauser requirements
+    if (reg_sts != UVM_IS_OK) begin
+        `uvm_error("MBOX_SEQ", "Unexpected error on read from CPTRA_HW_ERROR_NON_FATAL")
+    end
+    if (|err) begin
+        `uvm_info("MBOX_SEQ", "Detected non-fatal errors at end of mailbox flow. Clearing.", UVM_LOW)
+        reg_model.soc_ifc_reg_rm.CPTRA_HW_ERROR_NON_FATAL.write(reg_sts, err, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(500)));
+        if (reg_sts != UVM_IS_OK) begin
+            `uvm_error("MBOX_SEQ", "Unexpected error on write to CPTRA_HW_ERROR_NON_FATAL")
+        end
+    end
 endtask
 
 //==========================================
@@ -507,6 +625,33 @@ task soc_ifc_env_mbox_sequence_base::mbox_teardown();
     `uvm_info("MBOX_SEQ", $sformatf("Count of mailbox accesses performed with invalid PAUSER: %0d", hit_invalid_pauser_count), UVM_MEDIUM)
 endtask
 
+//==========================================
+// Function:    do_rand_delay
+// Description: Use the class variable "rand_delay"
+//              to inject random stalls between various stages
+//              of the sequence.
+//              If do_delay_randomize is set to 1, the value
+//              of rand_delay is re-randomized (according to
+//              class constraints), otherwise the previous value
+//              is used.
+//==========================================
+task soc_ifc_env_mbox_sequence_base::do_rand_delay(input bit do_delay_randomize=1, input delay_scale_e scale=DLY_SMALL);
+    if (do_delay_randomize) begin
+        // Update delay constraint based on delay mode
+        this.zero_delay_c  .constraint_mode(scale == DLY_ZERO);
+        this.small_delay_c .constraint_mode(scale == DLY_SMALL);
+        this.medium_delay_c.constraint_mode(scale == DLY_MEDIUM);
+        this.large_delay_c .constraint_mode(scale == DLY_LARGE);
+        this.custom_delay_c.constraint_mode(scale == DLY_CUSTOM);
+        if (!this.randomize(rand_delay))
+            `uvm_error("MBOX_SEQ", $sformatf("Failed to randomize rand_delay with scale %p", scale))
+        else
+            `uvm_info("MBOX_SEQ", $sformatf("Generated rand delay value: [%0d] cycles from constraint scale %p", rand_delay, scale), UVM_DEBUG)
+    end
+    if (rand_delay != 0)
+        configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(rand_delay);
+endtask
+
 //==========================================
 // Function:    set_pauser_prob_vals
 // Description: Assign values to class variables
@@ -563,11 +708,14 @@ endfunction
 // Description: Assess whether the most recent APB
 //              transfer used a valid PAUSER or not
 //==========================================
-function bit soc_ifc_env_mbox_sequence_base::pauser_used_is_valid();
+function bit soc_ifc_env_mbox_sequence_base::pauser_used_is_valid(caliptra_apb_user user_handle = null);
+    caliptra_apb_user user;
+    if (user_handle == null) user = this.apb_user_obj;
+    else                     user = user_handle;
     if (this.pauser_locked.locked)
-        return this.apb_user_obj.get_addr_user() == this.pauser_locked.pauser;
+        return user.get_addr_user() == this.pauser_locked.pauser;
     else 
-        return this.apb_user_obj.get_addr_user() inside mbox_valid_users;
+        return user.get_addr_user() inside mbox_valid_users;
 endfunction
 
 //==========================================
@@ -576,20 +724,29 @@ endfunction
 //              of the most recent APB transfer, accounting for
 //              the PAUSER value that was used.
 //==========================================
-function void soc_ifc_env_mbox_sequence_base::report_reg_sts(uvm_status_e reg_sts, string name);
+task soc_ifc_env_mbox_sequence_base::report_reg_sts(uvm_status_e reg_sts, string name, caliptra_apb_user user_handle = null);
+    caliptra_apb_user user;
+    int waiters = in_report_reg_sts.get_num_waiters();
+    in_report_reg_sts.trigger();
+    if (user_handle == null) user = this.apb_user_obj;
+    else                     user = user_handle;
     // APB error is flagged only for PAUSER that doesn't match the registered
     // values, it does not check that PAUSER matches the exact value in
     // mbox_user that was stored when lock was acquired (this results in a
     // silent error but a successful reg read).
     // Ergo, check against mbox_valid_users instead of pauser_locked.
-    if (reg_sts != UVM_IS_OK && this.apb_user_obj.get_addr_user() inside mbox_valid_users)
+    if (reg_sts != UVM_IS_OK && user.get_addr_user() inside mbox_valid_users)
         `uvm_error("MBOX_SEQ",
-                   $sformatf("Register access failed unexpectedly with valid PAUSER! 0x%x (%s)", this.apb_user_obj.get_addr_user(), name))
-    else if (reg_sts == UVM_IS_OK && !(this.apb_user_obj.get_addr_user() inside mbox_valid_users))
+                   $sformatf("Register access failed unexpectedly with valid PAUSER! 0x%x (%s)", user.get_addr_user(), name))
+    else if (reg_sts == UVM_IS_OK && !(user.get_addr_user() inside mbox_valid_users))
         `uvm_error("MBOX_SEQ",
-                   $sformatf("Register access passed unexpectedly with invalid PAUSER! 0x%x (%s)", this.apb_user_obj.get_addr_user(), name))
+                   $sformatf("Register access passed unexpectedly with invalid PAUSER! 0x%x (%s)", user.get_addr_user(), name))
     else
         `uvm_info("MBOX_SEQ",
-                  $sformatf("Register access to (%s) with pauser_used_is_valid: %b and reg_sts: %p", name, this.pauser_used_is_valid(), reg_sts),
+                  $sformatf("Register access to (%s) with pauser_used_is_valid: %b and reg_sts: %p", name, this.pauser_used_is_valid(user), reg_sts),
                   UVM_HIGH)
-endfunction
+    if (waiters)
+        in_report_reg_sts.wait_off();
+    else
+        in_report_reg_sts.reset();
+endtask
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sha_accel_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sha_accel_sequence.svh
index f86d996f6..aa6f609cf 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sha_accel_sequence.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sha_accel_sequence.svh
@@ -67,6 +67,15 @@ class soc_ifc_env_mbox_sha_accel_sequence extends soc_ifc_env_mbox_sequence_base
     constraint start_addr_c {start_addr inside { [4:131068] }; 
                              start_addr[1:0] == '0; }
 
+    //==========================================
+    // Function:    new
+    // Description: Constructor
+    //==========================================
+    function new(string name = "" );
+        super.new(name);
+        this.mbox_dlen_min_c.constraint_mode(0);
+    endfunction
+
 endclass
 
 task soc_ifc_env_mbox_sha_accel_sequence::mbox_setup();
@@ -127,15 +136,24 @@ task soc_ifc_env_mbox_sha_accel_sequence::mbox_setup();
     byte_shift = 'd4 - this.dlen[1:0];
     sha_block_data = sha_block_data << (byte_shift * 8);
 
-    // Restrict the start addr so that we don't overflow the mailbox
-    if ( (this.start_addr + this.dlen) > MBOX_SIZE_BYTES ) begin
-        //if we would have overflowed, just lower start address so the data fits in the mailbox at the end
-        this.start_addr = MBOX_SIZE_BYTES - (this.dlen);
-        //round it down to match the alignment of the data
-        this.start_addr[1:0] = '0;
+    // Override dlen to reflect the size of the SHA data + the start address dword
+    this.mbox_op_rand.dlen = 4 + this.dlen;
+
+    // Ensure that the start address is after the data
+    if ( (this.start_addr <= this.mbox_op_rand.dlen) || ( (this.start_addr + this.dlen) > MBOX_SIZE_BYTES )) begin
+        // Re-randomize start address to ensure it is after the valid data
+        // and still meets alignment requirements.
+        // Restrict the start addr so that we don't overflow the mailbox
+        this.randomize(this.start_addr) with { this.start_addr >= this.mbox_op_rand.dlen + 4;
+                                               this.start_addr + this.dlen <= MBOX_SIZE_BYTES;
+                                               this.start_addr[1:0] == 2'b00; };
+    end
+    // This shouldn't happen - if it does we bail out
+    // Check that re-randomizing start_addr for overlow didn't cause us to
+    // overlap. Key would have to be like half the mailbox in length which is impossible
+    if ( (this.start_addr < this.mbox_op_rand.dlen)) begin
+        `uvm_error("SHA_ACCEL_SEQ",$sformatf("Can't place the key in the mailbox properly Start_Addr: %x Dlen: %x", this.start_addr, this.mbox_op_rand.dlen))
     end
-    // Override dlen to reflect the size of the SHA data
-    this.mbox_op_rand.dlen = this.start_addr + this.dlen;
 endtask
 
 // This should be overridden with real data to write
@@ -143,20 +161,20 @@ task soc_ifc_env_mbox_sha_accel_sequence::mbox_push_datain();
     int ii;
     reg [31:0] data;
     int most_sig_dword;
-    int sha_block_start_dw;
+    //int sha_block_start_dw;
 
     //write 0's until the start address
-    sha_block_start_dw = this.start_addr >> 2;
+    //sha_block_start_dw = this.start_addr >> 2;
 
     //write the start address into the first dword
     reg_model.mbox_csr_rm.mbox_datain.write(reg_sts, uvm_reg_data_t'(this.start_addr), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(PAUSER_PROB_DATAIN)));
     report_reg_sts(reg_sts, "mbox_datain");
 
     //pad the data until start address
-    for (ii=1; ii < sha_block_start_dw; ii++) begin
-        reg_model.mbox_csr_rm.mbox_datain.write(reg_sts, uvm_reg_data_t'('0), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(PAUSER_PROB_DATAIN)));
-        report_reg_sts(reg_sts, "mbox_datain");
-    end
+    //for (ii=1; ii < sha_block_start_dw; ii++) begin
+    //    reg_model.mbox_csr_rm.mbox_datain.write(reg_sts, uvm_reg_data_t'('0), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(PAUSER_PROB_DATAIN)));
+    //    report_reg_sts(reg_sts, "mbox_datain");
+    //end
 
     //write the sha block
     most_sig_dword = (this.dlen[1:0] == 2'b00) ? (this.dlen >> 2) - 1 : (this.dlen >> 2);
@@ -190,4 +208,4 @@ task soc_ifc_env_mbox_sha_accel_sequence::mbox_read_resp_data();
             `uvm_error("SHA_ACCEL_SEQ",$sformatf("SHA512 Digest Mismatch - Digest[%x] Expected: %x Actual: %x", ii, sha_digest[digest_dwords-1-ii], data))
         end
     end
-endtask
\ No newline at end of file
+endtask
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_large_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_large_sequence.svh
new file mode 100644
index 000000000..b26f72ab5
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_large_sequence.svh
@@ -0,0 +1,44 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Extended from Mailbox SRAM double bit flip injection
+//              sequence for the special 'large' test case
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_mbox_sram_double_bit_flip_large_sequence extends soc_ifc_env_mbox_sram_double_bit_flip_sequence;
+
+  `uvm_object_utils( soc_ifc_env_mbox_sram_double_bit_flip_large_sequence )
+
+  // Constrain size to a large command
+  // Min. size: 16KiB
+  constraint mbox_dlen_min_large_c { mbox_op_rand.dlen > 32'h0000_4000; }
+  // Constrain response data size to also be large
+  // Min. size: 16KiB
+  constraint mbox_resp_dlen_min_large_c { mbox_op_rand.cmd.cmd_s.resp_reqd -> mbox_resp_expected_dlen >= 32'h0000_4000; }
+  // Valid solution for the custom delay ruleset, to control random delays while
+  // waiting to inject random error accesses
+  constraint custom_delay_c { rand_delay > 0;
+                              rand_delay dist {[1                   :mbox_op_rand.dlen*2 -1] :/ 250,
+                                               [mbox_op_rand.dlen*2 :mbox_op_rand.dlen*5 -1] :/ 100,
+                                               [mbox_op_rand.dlen*5 :mbox_op_rand.dlen*15-1] :/ 25}; }
+
+endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_medium_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_medium_sequence.svh
new file mode 100644
index 000000000..35c7e14ca
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_medium_sequence.svh
@@ -0,0 +1,48 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Extended from Mailbox SRAM double bit flip injection
+//              sequence for the special 'medium' test case
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_mbox_sram_double_bit_flip_medium_sequence extends soc_ifc_env_mbox_sram_double_bit_flip_sequence;
+
+  `uvm_object_utils( soc_ifc_env_mbox_sram_double_bit_flip_medium_sequence )
+
+  // Constrain dlen to be a medium command
+  // Max. size: 4096B
+  constraint mbox_dlen_max_medium_c { mbox_op_rand.dlen <= 32'h0000_1000; }
+  // Minimum 512B
+  constraint mbox_dlen_min_medium_c { mbox_op_rand.dlen >= 32'h0000_0200; }
+  // Constrain response data size to also be medium
+  // Max. size: 4096B
+  // Min. size: 512B
+  constraint mbox_resp_dlen_max_medium_c { mbox_resp_expected_dlen <= 32'h0000_1000; }
+  constraint mbox_resp_dlen_min_medium_c { mbox_op_rand.cmd.cmd_s.resp_reqd -> mbox_resp_expected_dlen >= 32'h0000_0200; }
+  // Valid solution for the custom delay ruleset, to control random delays while
+  // waiting to inject random error accesses
+  constraint custom_delay_c { rand_delay > 0;
+                              rand_delay dist {[1                   :mbox_op_rand.dlen*2 -1] :/ 250,
+                                               [mbox_op_rand.dlen*2 :mbox_op_rand.dlen*5 -1] :/ 100,
+                                               [mbox_op_rand.dlen*5 :mbox_op_rand.dlen*15-1] :/ 25}; }
+
+endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_sequence.svh
new file mode 100644
index 000000000..22f0a3134
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_sequence.svh
@@ -0,0 +1,105 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Extended from mbox sequence base to exercise double-bit flips
+//              on the mailbox SRAM.
+//              Desired result is to observe the internal error interrupt and
+//              assertion of the cptra_error_non_fatal pin.
+//              After responding to the error by clearing the interrupts, the
+//              mailbox flow will be terminated.
+// NOTES:
+//   - SOC may respond with any of:
+//     1. Wait for uC to clear the internal interrupt / reset the mbox
+//        FSM (or proceed with the cmd as normal), then proceed to
+//        clear the cptra_error_non_fatal pin
+//     2. Clear the cptra_error_non_fatal pin immediately, issue a new command
+//        (still requires waiting for LOCK)
+//     3. Reset Caliptra
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_mbox_sram_double_bit_flip_sequence extends soc_ifc_env_mbox_sequence_base;
+
+  `uvm_object_utils( soc_ifc_env_mbox_sram_double_bit_flip_sequence )
+
+  // Constrain command to undefined opcode
+  constraint mbox_cmd_undef_c { !(mbox_op_rand.cmd.cmd_s inside {defined_cmds}); }
+
+  function new(string name = "" );
+    super.new(name);
+  endfunction
+
+  //==========================================
+  // Task:        body
+  // Description: Implement main functionality for
+  //              SOC-side transmission of mailbox request.
+  //              Override default body to inject double
+  //              bit flips into the Mailbox SRAM at random
+  //              throughout a normal test flow.
+  //==========================================
+  virtual task body();
+
+    op_sts_e op_sts;
+    process mbox_flow_proc;
+    process err_proc;
+
+    sts_rsp_count = 0;
+
+    fork
+        forever begin
+            @(soc_ifc_status_agent_rsp_seq.new_rsp) sts_rsp_count++;
+        end
+    join_none
+
+    `uvm_info("MBOX_SEQ", $sformatf("Initiating command sequence to mailbox with cmd: [%p] dlen: [%p] resp_dlen: [%p]", mbox_op_rand.cmd.cmd_e, mbox_op_rand.dlen, mbox_resp_expected_dlen), UVM_MEDIUM)
+
+    fork
+        begin: MBOX_FLOW
+            mbox_setup();               if (rand_delay_en) do_rand_delay(1, step_delay);
+            mbox_acquire_lock(op_sts);  if (rand_delay_en) do_rand_delay(1, step_delay);
+            mbox_flow_proc = process::self();
+            mbox_set_cmd(mbox_op_rand); if (rand_delay_en) do_rand_delay(1, step_delay);
+            mbox_push_datain();         if (rand_delay_en) do_rand_delay(1, step_delay);
+            mbox_execute();             if (rand_delay_en) do_rand_delay(1, step_delay);
+            mbox_poll_status();         if (rand_delay_en) do_rand_delay(1, step_delay);
+            if (err_proc.status() == process::WAITING) begin
+                `uvm_info("MBOX_SEQ", "Ending SRAM bit flip injection thread before it has completed!", UVM_LOW)
+                disable ERR_INJECT_FLOW;
+            end
+            else if (err_proc.status() != process::FINISHED) begin
+                `uvm_error("MBOX_SEQ", $sformatf("Error process is in unexpected state %s!", err_proc.status().name()))
+            end
+        end
+        begin: ERR_INJECT_FLOW
+            err_proc = process::self();
+            wait(mbox_flow_proc != null);
+            // Wait and do the SRAM error injection at some random point in the sequence
+            do_rand_delay(1, DLY_CUSTOM);
+            `uvm_info("MBOX_SEQ", "Triggering Mailbox SRAM double-bit flip injection", UVM_LOW)
+            set_mbox_sram_ecc_double_error_injection();
+        end
+    join
+    mbox_clr_execute();         if (rand_delay_en) do_rand_delay(1, step_delay);
+    mbox_teardown();
+
+  endtask
+
+endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_small_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_small_sequence.svh
new file mode 100644
index 000000000..37e77b4b1
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_small_sequence.svh
@@ -0,0 +1,44 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Extended from Mailbox SRAM double bit flip injection
+//              sequence for the special 'small' test case
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_mbox_sram_double_bit_flip_small_sequence extends soc_ifc_env_mbox_sram_double_bit_flip_sequence;
+
+  `uvm_object_utils( soc_ifc_env_mbox_sram_double_bit_flip_small_sequence )
+
+  // Constrain dlen to be a small command
+  // Max. size: 512B
+  constraint mbox_dlen_max_small_c { mbox_op_rand.dlen <= 32'h0000_0200; }
+  // Constrain response data size to also be small
+  // Max. size: 512B
+  constraint mbox_resp_dlen_max_small_c { mbox_resp_expected_dlen < 32'h0000_0200; }
+  // Valid solution for the custom delay ruleset, to control random delays while
+  // waiting to inject random error accesses
+  constraint custom_delay_c { rand_delay > 0;
+                              rand_delay dist {[1                   :mbox_op_rand.dlen*2 -1] :/ 250,
+                                               [mbox_op_rand.dlen*2 :mbox_op_rand.dlen*5 -1] :/ 100,
+                                               [mbox_op_rand.dlen*5 :mbox_op_rand.dlen*15-1] :/ 25}; }
+
+endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_uc_reg_access_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_uc_reg_access_sequence.svh
index 6a04950c9..6b46cd035 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_uc_reg_access_sequence.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_uc_reg_access_sequence.svh
@@ -63,6 +63,9 @@ class soc_ifc_env_mbox_uc_reg_access_sequence extends soc_ifc_env_mbox_sequence_
                            out_of_bounds == 1 -> mbox_op_rand.dlen == 32'h8; //min dlen for "resp req" command
                            solve out_of_bounds before mbox_op_rand;
                            solve num_reg before mbox_op_rand; }
+                           
+  // Response dlen should be the same as the dlen since we read once for each reg access
+  constraint mbox_resp_dlen_c {mbox_resp_expected_dlen == mbox_op_rand.dlen;}
 
   // pick a slave to select an address in a valid range
   constraint slave_sel_c { slave_sel.size() == num_reg;
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_soc_mbox_handler_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_soc_mbox_handler_sequence.svh
index 4941d69a1..028e280af 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_soc_mbox_handler_sequence.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_soc_mbox_handler_sequence.svh
@@ -36,6 +36,7 @@ class soc_ifc_env_soc_mbox_handler_sequence extends soc_ifc_env_sequence_base #(
   mbox_op_s op;
   uvm_status_e reg_sts;
   int sts_rsp_count = 0;
+  uvm_event in_report_reg_sts;
 
   // PAUSER tracking/override
   bit [apb5_master_0_params::PAUSER_WIDTH-1:0] mbox_valid_users [6];
@@ -48,9 +49,10 @@ class soc_ifc_env_soc_mbox_handler_sequence extends soc_ifc_env_sequence_base #(
   extern virtual task mbox_pop_dataout();
   extern virtual task mbox_set_status();
   extern virtual task mbox_check_fsm();
+  extern virtual task mbox_wait_done();
   extern virtual task mbox_teardown();
 
-  extern virtual function void report_reg_sts(uvm_status_e sts, string name);
+  extern virtual task report_reg_sts(uvm_status_e sts, string name, caliptra_apb_user user_handle = null);
 
 
   //==========================================
@@ -63,6 +65,9 @@ class soc_ifc_env_soc_mbox_handler_sequence extends soc_ifc_env_sequence_base #(
     // Setup a User object to override PAUSER
     apb_user_obj = new();
 
+    // Event
+    in_report_reg_sts = new();
+
   endfunction
 
   //==========================================
@@ -106,16 +111,13 @@ class soc_ifc_env_soc_mbox_handler_sequence extends soc_ifc_env_sequence_base #(
 
     // Get COMMAND
     mbox_get_command();
-
-    // Get DATAOUT
     mbox_pop_dataout();
 
-    // Set STATUS
+    // Return control to uC
     mbox_set_status();
-
-    // Check FSM status
     configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(2); // Takes a few cycles for FSM update to propagate into register
     mbox_check_fsm();
+    mbox_wait_done();
 
     // End of Sequence
     mbox_teardown();
@@ -272,11 +274,48 @@ task soc_ifc_env_soc_mbox_handler_sequence::mbox_check_fsm();
     report_reg_sts(reg_sts,"mbox_status");
 
     fsm_state = mbox_fsm_state_e'(data >> reg_model.mbox_csr_rm.mbox_status.mbox_fsm_ps.get_lsb_pos());
-    if (fsm_state != MBOX_EXECUTE_UC) begin
+    if (fsm_state inside {MBOX_IDLE, MBOX_ERROR} && (sts_rsp_count > 0) && soc_ifc_status_agent_rsp_seq.rsp.cptra_error_non_fatal_intr_pending) begin
+        `uvm_info("SOC_MBOX_HANDLER", $sformatf("Observed mailbox FSM state: %p, which is not a failure since it corresponds with non_fatal HW interrupt", fsm_state), UVM_MEDIUM)
+    end
+    else if (fsm_state != MBOX_EXECUTE_UC) begin
         `uvm_error("SOC_MBOX_HANDLER", $sformatf("Unexpected mailbox FSM state: %p", fsm_state))
     end
 endtask
 
+//==========================================
+// Task:        mbox_wait_done
+// Description: Wait for uC to end the mailbox flow as indicated
+//              by mbox_lock being relinquished.
+//              If necessary, service any cptra HW error (fatal or
+//              non_fatal) that occurred.
+//==========================================
+task soc_ifc_env_soc_mbox_handler_sequence::mbox_wait_done();
+    uvm_reg_data_t non_fatal, fatal;
+
+    // Wait for lock to clear
+    while(reg_model.mbox_csr_rm.mbox_lock.get_mirrored_value())
+        configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(1);
+
+    // Check for interrupts
+    if (sts_rsp_count && (soc_ifc_status_agent_rsp_seq.rsp.cptra_error_non_fatal_intr_pending ||
+                          soc_ifc_status_agent_rsp_seq.rsp.cptra_error_fatal_intr_pending)) begin
+        // Read status
+        reg_model.soc_ifc_reg_rm.CPTRA_HW_ERROR_NON_FATAL.read(reg_sts, non_fatal, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(apb_user_obj));
+        report_reg_sts(reg_sts, "CPTRA_HW_ERROR_NON_FATAL");
+        reg_model.soc_ifc_reg_rm.CPTRA_HW_ERROR_FATAL.read(reg_sts, fatal, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(apb_user_obj));
+        report_reg_sts(reg_sts, "CPTRA_HW_ERROR_FATAL");
+
+        if (~|fatal && ~|non_fatal)
+            `uvm_error("SOC_MBOX_HANDLER", $sformatf("Received status response transaction with cptra error asserted [%s] but both fatal and non_fatal registers are 0!", soc_ifc_status_agent_rsp_seq.rsp.convert2string()))
+
+        // Write 1 to clear
+        reg_model.soc_ifc_reg_rm.CPTRA_HW_ERROR_NON_FATAL.write(reg_sts, non_fatal, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(apb_user_obj));
+        report_reg_sts(reg_sts, "CPTRA_HW_ERROR_NON_FATAL");
+        reg_model.soc_ifc_reg_rm.CPTRA_HW_ERROR_FATAL.write(reg_sts, fatal, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(apb_user_obj));
+        report_reg_sts(reg_sts, "CPTRA_HW_ERROR_FATAL");
+    end
+endtask
+
 //==========================================
 // Task:        mbox_teardown
 // Description: Placeholder task to allow derived classes
@@ -293,20 +332,29 @@ endtask
 //              of the most recent APB transfer, accounting for
 //              the PAUSER value that was used.
 //==========================================
-function void soc_ifc_env_soc_mbox_handler_sequence::report_reg_sts(uvm_status_e sts, string name);
+task soc_ifc_env_soc_mbox_handler_sequence::report_reg_sts(uvm_status_e sts, string name, caliptra_apb_user user_handle = null);
+    caliptra_apb_user user;
+    int waiters = in_report_reg_sts.get_num_waiters();
+    in_report_reg_sts.trigger();
+    if (user_handle == null) user = this.apb_user_obj;
+    else                     user = user_handle;
     // APB error is flagged only for PAUSER that doesn't match the registered
     // values, it does not check that PAUSER matches the exact value in
     // mbox_user that was stored when lock was acquired (this results in a
     // silent error but a successful reg read).
     // Ergo, check against mbox_valid_users instead of pauser_locked.
-    if (sts != UVM_IS_OK && this.apb_user_obj.get_addr_user() inside mbox_valid_users)
+    if (sts != UVM_IS_OK && user.get_addr_user() inside mbox_valid_users)
         `uvm_error("SOC_MBOX_HANDLER",
-                   $sformatf("Register access failed unexpectedly with valid PAUSER! 0x%x (%s)", this.apb_user_obj.get_addr_user(), name))
-    else if (sts == UVM_IS_OK && !(this.apb_user_obj.get_addr_user() inside mbox_valid_users))
+                   $sformatf("Register access failed unexpectedly with valid PAUSER! 0x%x (%s)", user.get_addr_user(), name))
+    else if (sts == UVM_IS_OK && !(user.get_addr_user() inside mbox_valid_users))
         `uvm_error("SOC_MBOX_HANDLER",
-                   $sformatf("Register access passed unexpectedly with invalid PAUSER! 0x%x (%s)", this.apb_user_obj.get_addr_user(), name))
+                   $sformatf("Register access passed unexpectedly with invalid PAUSER! 0x%x (%s)", user.get_addr_user(), name))
     else
         `uvm_info("SOC_MBOX_HANDLER",
                   $sformatf("Register access to (%s) with pauser_used_is_valid: %b and sts: %p", name, 1/* this.pauser_used_is_valid()*/, sts),
                   UVM_HIGH)
-endfunction
+    if (waiters)
+        in_report_reg_sts.wait_off();
+    else
+        in_report_reg_sts.reset();
+endtask
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_soc_mbox_reg_axs_invalid_handler_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_soc_mbox_reg_axs_invalid_handler_sequence.svh
new file mode 100644
index 000000000..9c5b1a209
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_soc_mbox_reg_axs_invalid_handler_sequence.svh
@@ -0,0 +1,207 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Sequence to wait for Mailbox commands (from uC) and
+//              respond/handle the command.
+//              This sequence also injects protocol errors into the mailbox
+//              by performing out-of-order register accesses.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_soc_mbox_reg_axs_invalid_handler_sequence extends soc_ifc_env_soc_mbox_handler_sequence;
+
+
+  `uvm_object_utils( soc_ifc_env_soc_mbox_reg_axs_invalid_handler_sequence )
+
+  extern virtual task                    mbox_do_random_reg_write(process mainline);
+  extern virtual function uvm_reg_data_t get_rand_wr_data(uvm_reg axs_reg);
+
+  //==========================================
+  // Task:        body
+  // Description: Implement main functionality for
+  //              Caliptra-side handling of received
+  //              mailbox request.
+  //==========================================
+  virtual task body();
+
+    op_sts_e op_sts;
+    bit do_fsm_chk = 1;
+    process mbox_flow_proc;
+    reg_model = configuration.soc_ifc_rm;
+
+    if (soc_ifc_status_agent_rsp_seq == null)
+        `uvm_fatal("SOC_MBOX_HANDLER", "SOC_IFC ENV SOC mailbox handler sequence expected a handle to the soc_ifc status agent responder sequence (from bench-level sequence) but got null!")
+    fork
+        forever begin
+            @(soc_ifc_status_agent_rsp_seq.new_rsp) sts_rsp_count++;
+        end
+    join_none
+
+    // Setup
+    mbox_setup();
+
+    fork
+        begin: HANDLER_FLOW
+            mbox_flow_proc = process::self();
+            // Wait for a mailbox command to be received
+            mbox_wait_for_command(op_sts);
+            if (op_sts != CPTRA_SUCCESS) begin
+                `uvm_error("SOC_MBOX_HANDLER", "Unsuccessful return code from wait_for_command_avail()")
+            end
+
+            // Get COMMAND
+            mbox_get_command();
+            mbox_pop_dataout();
+
+            // Return control to uC
+            if (sts_rsp_count && !soc_ifc_status_agent_rsp_seq.rsp.mailbox_data_avail) begin
+                // Our random_reg_write may write to mbox_status and cause us to exit EXECUTE_SOC early...
+                do_fsm_chk = 0;
+            end
+            mbox_set_status();
+            configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(2); // Takes a few cycles for FSM update to propagate into register
+            if (do_fsm_chk)
+                mbox_check_fsm();
+        end
+        begin: ERR_INJECT_FLOW
+            wait(mbox_flow_proc != null);
+            mbox_do_random_reg_write(mbox_flow_proc);
+        end
+    join
+    mbox_wait_done();
+
+    // End of Sequence
+    mbox_teardown();
+
+  endtask
+
+endclass
+
+//==========================================
+// Task:        mbox_do_random_reg_write
+// Description: Do some random reg write that will
+//              (most likely) be invalid and trigger
+//              the protocol error violation.
+//==========================================
+task soc_ifc_env_soc_mbox_reg_axs_invalid_handler_sequence::mbox_do_random_reg_write(process mainline);
+    uvm_reg mbox_regs[$];
+    int unsigned rand_idx;
+    int unsigned rand_delay;
+    uvm_reg_data_t rand_wr_data;
+    caliptra_apb_user local_apb_user_obj;
+
+    mbox_regs.push_back(reg_model.mbox_csr_rm.mbox_cmd    );
+    mbox_regs.push_back(reg_model.mbox_csr_rm.mbox_dlen   );
+    mbox_regs.push_back(reg_model.mbox_csr_rm.mbox_datain );
+    mbox_regs.push_back(reg_model.mbox_csr_rm.mbox_dataout);
+    mbox_regs.push_back(reg_model.mbox_csr_rm.mbox_execute);
+    mbox_regs.push_back(reg_model.mbox_csr_rm.mbox_status );
+
+    if (!std::randomize(rand_idx) with {rand_idx < mbox_regs.size(); })
+        `uvm_fatal("SOC_MBOX_HANDLER", "Failed to randomize reg idx")
+
+    // Wait to do the reg write at some random point in the sequence
+    std::randomize(rand_delay) with {rand_delay dist {[1:255] :/ 5, [256:1023] :/ 3, [1024:65535] :/ 1};};
+    configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(rand_delay);
+ 
+    // Data used depends on which reg is being accessed to force invalid contents
+    rand_wr_data = get_rand_wr_data(mbox_regs[rand_idx]);
+
+    // Get a randomized PAUSER for this transaction - 50% chance of being valid
+    local_apb_user_obj = new();
+    if (!local_apb_user_obj.randomize() with {(addr_user inside {mbox_valid_users}) dist
+                                              {1 :/ 1,
+                                               0 :/ 1}; })
+        `uvm_error("SOC_MBOX_HANDLER", "Failed to randomize APB PAUSER override value")
+    else
+        `uvm_info("SOC_MBOX_HANDLER", $sformatf("Randomized APB PAUSER override value to 0x%x", local_apb_user_obj.addr_user), UVM_HIGH)
+
+    // Pause the main mailbox responder flow to prevent race conditions (on accesses to the same register, triggering is_busy UVM_WARNING)
+    if (mainline.status() inside {process::RUNNING,process::WAITING}) begin
+        in_report_reg_sts.wait_on();
+        `uvm_info("SOC_MBOX_HANDLER", $sformatf("Pausing main mailbox flow to allow random reg access injection"), UVM_HIGH)
+        mainline.suspend();
+        in_report_reg_sts.reset();
+    end
+    else begin
+        `uvm_info("SOC_MBOX_HANDLER", $sformatf("Main mailbox flow is in state [%s], so it will not be suspended for random reg access injection", mainline.status().name()), UVM_HIGH)
+    end
+
+    // Do the access
+    `uvm_info("SOC_MBOX_HANDLER", {"Performing random register access to ", mbox_regs[rand_idx].get_name()}, UVM_LOW)
+    if (mbox_regs[rand_idx].get_name() == "mbox_dataout") begin
+        mbox_regs[rand_idx].read(reg_sts, rand_wr_data, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(local_apb_user_obj));
+        report_reg_sts(reg_sts, mbox_regs[rand_idx].get_name(), local_apb_user_obj);
+    end
+    else if (mbox_regs[rand_idx].get_name() == "mbox_datain") begin
+        wait(reg_model.mbox_csr_rm.mbox_fn_state_sigs.uc_receive_stage == 1'b0);
+        mbox_regs[rand_idx].write(reg_sts, rand_wr_data, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(local_apb_user_obj));
+        report_reg_sts(reg_sts, mbox_regs[rand_idx].get_name(), local_apb_user_obj);
+    end
+    else begin
+        mbox_regs[rand_idx].write(reg_sts, rand_wr_data, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(local_apb_user_obj));
+        report_reg_sts(reg_sts, mbox_regs[rand_idx].get_name(), local_apb_user_obj);
+    end
+    if (mainline.status() == process::SUSPENDED) begin
+        `uvm_info("SOC_MBOX_HANDLER", $sformatf("Resuming main mailbox flow after random reg access injection"), UVM_HIGH)
+        mainline.resume();
+    end
+endtask
+
+//==========================================
+// Task:        get_rand_wr_data
+// Description: Generate random data according
+//              to a set of rules related to which register
+//              is being accessed, with intent to cause
+//              a protocol violation.
+//==========================================
+function uvm_reg_data_t soc_ifc_env_soc_mbox_reg_axs_invalid_handler_sequence::get_rand_wr_data(uvm_reg axs_reg);
+    uvm_reg_data_t tmp_data;
+    case (axs_reg.get_name()) inside
+        "mbox_cmd": begin
+            tmp_data = op.cmd;
+        end
+        "mbox_dlen": begin
+            tmp_data = op.dlen; 
+        end
+        "mbox_datain",
+        "mbox_dataout": begin
+            std::randomize(tmp_data);
+        end
+        "mbox_execute": begin
+            uvm_reg_data_t msk;
+            msk = ~(uvm_reg_data_t'(1) << reg_model.mbox_csr_rm.mbox_execute.execute.get_lsb_pos());
+            std::randomize(tmp_data) with {(tmp_data & msk) == 0;};
+        end
+        "mbox_status": begin
+            uvm_reg_data_t msk;
+            msk = (uvm_reg_data_t'(1) << reg_model.mbox_csr_rm.mbox_status.status.get_n_bits()) - 1;
+            msk = ~msk;
+            std::randomize(tmp_data) with {(tmp_data & msk) == 0;};
+        end
+        default: begin
+            `uvm_fatal("SOC_MBOX_HANDLER", "Bad reg")
+        end
+    endcase
+    return tmp_data;
+endfunction
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_cptra_mbox_reg_axs_invalid_small_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_cptra_mbox_reg_axs_invalid_small_sequence.svh
new file mode 100644
index 000000000..e97196520
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_cptra_mbox_reg_axs_invalid_small_sequence.svh
@@ -0,0 +1,44 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Sequence to initiate (and respond) to mailbox command
+//              "TOP" sequence because it invokes lower level env sequences
+//              to facilitate the uC/SoC sides of mailbox command handling
+//              and this sequence defines the whole mailbox flow.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_top_cptra_mbox_reg_axs_invalid_small_sequence extends soc_ifc_env_top_cptra_mbox_sequence_base;
+
+
+  `uvm_object_utils( soc_ifc_env_top_cptra_mbox_reg_axs_invalid_small_sequence )
+
+  extern virtual function create_seqs();
+
+endclass
+
+function soc_ifc_env_top_cptra_mbox_reg_axs_invalid_small_sequence::create_seqs();
+    uvm_object obj;
+    obj = soc_ifc_env_cptra_mbox_req_rand_small_sequence_t::get_type().create_object("soc_ifc_env_cptra_mbox_seq");
+    if(!$cast(soc_ifc_env_cptra_mbox_seq,obj)) `uvm_fatal("SOC_IFC_TOP_MBOX_REG_AXS_INVALID_SMALL", "soc_ifc_env_top_cptra_mbox_reg_axs_invalid_small_sequence::create_seqs() - <seq_type>.create_object() failed")
+    obj = soc_ifc_env_soc_mbox_reg_axs_invalid_handler_sequence_t::get_type().create_object("soc_ifc_env_soc_handler_seq");
+    if(!$cast(soc_ifc_env_soc_handler_seq,obj)) `uvm_fatal("SOC_IFC_TOP_MBOX_REG_AXS_INVALID_SMALL", "soc_ifc_env_top_cptra_mbox_reg_axs_invalid_small_sequence::create_seqs() - <seq_type>.create_object() failed")
+endfunction
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_mbox_dlen_violation_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_mbox_dlen_violation_sequence.svh
index 0ef5560b3..4d754b25e 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_mbox_dlen_violation_sequence.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_mbox_dlen_violation_sequence.svh
@@ -39,27 +39,38 @@ function soc_ifc_env_top_mbox_dlen_violation_sequence::create_seqs();
     uvm_object obj;
 
     enum {
+        MBOX_MIN,
+        MBOX_MAX,
         MBOX_UNDERFLOW_SMALL,
         MBOX_UNDERFLOW_MEDIUM,
         MBOX_UNDERFLOW_LARGE,
         MBOX_OVERFLOW_SMALL,
         MBOX_OVERFLOW_MEDIUM,
-        MBOX_OVERFLOW_LARGE
+        MBOX_OVERFLOW_LARGE,
+        MBOX_INVALID
     } mbox_sel;
     enum {
+        CPTRA_STANDARD,
         CPTRA_UNDERREAD,
         CPTRA_OVERREAD
     } cptra_sel;
 
-    if (!std::randomize(mbox_sel,cptra_sel) with {mbox_sel dist {MBOX_UNDERFLOW_SMALL  :/ 100,
+    if (!std::randomize(mbox_sel,cptra_sel) with {mbox_sel dist {MBOX_MIN              :/ 100,
+                                                                 MBOX_MAX              :/ 100,
+                                                                 MBOX_UNDERFLOW_SMALL  :/ 100,
                                                                  MBOX_UNDERFLOW_MEDIUM :/ 100,
-                                                                 MBOX_UNDERFLOW_LARGE  :/ 1,
+                                                                 MBOX_UNDERFLOW_LARGE  :/ 10,
                                                                  MBOX_OVERFLOW_SMALL   :/ 100,
                                                                  MBOX_OVERFLOW_MEDIUM  :/ 100,
-                                                                 MBOX_OVERFLOW_LARGE   :/ 1};})
+                                                                 MBOX_OVERFLOW_LARGE   :/ 10,
+                                                                 MBOX_INVALID          :/ 10};})
         `uvm_fatal("SOC_IFC_MBOX_TOP", "Failed to randomize sub-sequence types")
 
     case (mbox_sel) inside
+        MBOX_MIN:
+            obj = soc_ifc_env_mbox_min_sequence_t::get_type().create_object("soc_ifc_env_mbox_seq");
+        MBOX_MAX:
+            obj = soc_ifc_env_mbox_max_sequence_t::get_type().create_object("soc_ifc_env_mbox_seq");
         MBOX_UNDERFLOW_SMALL:
             obj = soc_ifc_env_mbox_dlen_underflow_small_sequence_t::get_type().create_object("soc_ifc_env_mbox_seq");
         MBOX_UNDERFLOW_MEDIUM:
@@ -72,11 +83,15 @@ function soc_ifc_env_top_mbox_dlen_violation_sequence::create_seqs();
             obj = soc_ifc_env_mbox_dlen_overflow_medium_sequence_t::get_type().create_object("soc_ifc_env_mbox_seq");
         MBOX_OVERFLOW_LARGE:
             obj = soc_ifc_env_mbox_dlen_overflow_large_sequence_t::get_type().create_object("soc_ifc_env_mbox_seq");
+        MBOX_INVALID:
+            obj = soc_ifc_env_mbox_dlen_invalid_sequence_t::get_type().create_object("soc_ifc_env_mbox_seq");
         default: `uvm_fatal("SOC_IFC_MBOX_TOP","Bad mbox_sel")
     endcase
     if(!$cast(soc_ifc_env_mbox_seq,obj)) `uvm_fatal("SOC_IFC_TOP_MBOX", "soc_ifc_env_top_mbox_dlen_violation::create_seqs() - <seq_type>.create_object() failed")
 
     case (cptra_sel) inside
+        CPTRA_STANDARD:
+            obj = soc_ifc_env_cptra_mbox_handler_sequence_t::get_type().create_object("soc_ifc_env_cptra_handler_seq");
         CPTRA_UNDERREAD:
             obj = soc_ifc_env_cptra_mbox_dlen_underread_handler_sequence_t::get_type().create_object("soc_ifc_env_cptra_handler_seq");
         CPTRA_OVERREAD:
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_mbox_max_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_mbox_max_sequence.svh
new file mode 100644
index 000000000..0203322de
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_mbox_max_sequence.svh
@@ -0,0 +1,43 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Sequence to initiate (and respond) to mailbox command
+//              "TOP" sequence because it invokes lower level env sequences
+//              to facilitate the uC/SoC sides of mailbox command handling
+//              and this sequence defines the whole mailbox flow.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_top_mbox_max_sequence extends soc_ifc_env_top_mbox_sequence_base;
+
+
+  `uvm_object_utils( soc_ifc_env_top_mbox_max_sequence )
+
+  extern virtual function create_seqs();
+
+endclass
+
+function soc_ifc_env_top_mbox_max_sequence::create_seqs();
+    uvm_object obj;
+    obj = soc_ifc_env_mbox_max_sequence_t::get_type().create_object("soc_ifc_env_mbox_seq");
+    if(!$cast(soc_ifc_env_mbox_seq,obj)) `uvm_fatal("SOC_IFC_TOP_MBOX_RAND_SMALL", "soc_ifc_env_top_mbox_max_sequence::create_seqs() - <seq_type>.create_object() failed")
+    soc_ifc_env_cptra_handler_seq = soc_ifc_env_cptra_mbox_dlen_overread_handler_sequence_t::type_id::create("soc_ifc_env_cptra_handler_seq");
+endfunction
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_mbox_min_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_mbox_min_sequence.svh
new file mode 100644
index 000000000..2e9b3d567
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_mbox_min_sequence.svh
@@ -0,0 +1,43 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Sequence to initiate (and respond) to mailbox command
+//              "TOP" sequence because it invokes lower level env sequences
+//              to facilitate the uC/SoC sides of mailbox command handling
+//              and this sequence defines the whole mailbox flow.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_top_mbox_min_sequence extends soc_ifc_env_top_mbox_sequence_base;
+
+
+  `uvm_object_utils( soc_ifc_env_top_mbox_min_sequence )
+
+  extern virtual function create_seqs();
+
+endclass
+
+function soc_ifc_env_top_mbox_min_sequence::create_seqs();
+    uvm_object obj;
+    obj = soc_ifc_env_mbox_min_sequence_t::get_type().create_object("soc_ifc_env_mbox_seq");
+    if(!$cast(soc_ifc_env_mbox_seq,obj)) `uvm_fatal("SOC_IFC_TOP_MBOX_RAND_SMALL", "soc_ifc_env_top_mbox_min_sequence::create_seqs() - <seq_type>.create_object() failed")
+    soc_ifc_env_cptra_handler_seq = soc_ifc_env_cptra_mbox_dlen_overread_handler_sequence_t::type_id::create("soc_ifc_env_cptra_handler_seq");
+endfunction
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_mbox_rand_delay_large_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_mbox_rand_delay_large_sequence.svh
new file mode 100644
index 000000000..d0e10e8f8
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_mbox_rand_delay_large_sequence.svh
@@ -0,0 +1,43 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Sequence to initiate (and respond) to mailbox command
+//              "TOP" sequence because it invokes lower level env sequences
+//              to facilitate the uC/SoC sides of mailbox command handling
+//              and this sequence defines the whole mailbox flow.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_top_mbox_rand_delay_large_sequence extends soc_ifc_env_top_mbox_sequence_base;
+
+
+  `uvm_object_utils( soc_ifc_env_top_mbox_rand_delay_large_sequence )
+
+  extern virtual function      create_seqs();
+
+endclass
+
+function soc_ifc_env_top_mbox_rand_delay_large_sequence::create_seqs();
+    uvm_object obj;
+    obj = soc_ifc_env_mbox_rand_delay_large_sequence_t::get_type().create_object("soc_ifc_env_mbox_seq");
+    if(!$cast(soc_ifc_env_mbox_seq,obj)) `uvm_fatal("SOC_IFC_TOP_MBOX_RAND_DELAY", "soc_ifc_env_top_mbox_rand_delay_large_sequence::create_seqs() - <seq_type>.create_object() failed")
+    soc_ifc_env_cptra_handler_seq = soc_ifc_env_cptra_mbox_handler_sequence_t::type_id::create("soc_ifc_env_cptra_handler_seq");
+endfunction
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_mbox_rand_delay_medium_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_mbox_rand_delay_medium_sequence.svh
new file mode 100644
index 000000000..1efff8dd4
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_mbox_rand_delay_medium_sequence.svh
@@ -0,0 +1,43 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Sequence to initiate (and respond) to mailbox command
+//              "TOP" sequence because it invokes lower level env sequences
+//              to facilitate the uC/SoC sides of mailbox command handling
+//              and this sequence defines the whole mailbox flow.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_top_mbox_rand_delay_medium_sequence extends soc_ifc_env_top_mbox_sequence_base;
+
+
+  `uvm_object_utils( soc_ifc_env_top_mbox_rand_delay_medium_sequence )
+
+  extern virtual function      create_seqs();
+
+endclass
+
+function soc_ifc_env_top_mbox_rand_delay_medium_sequence::create_seqs();
+    uvm_object obj;
+    obj = soc_ifc_env_mbox_rand_delay_medium_sequence_t::get_type().create_object("soc_ifc_env_mbox_seq");
+    if(!$cast(soc_ifc_env_mbox_seq,obj)) `uvm_fatal("SOC_IFC_TOP_MBOX_RAND_DELAY", "soc_ifc_env_top_mbox_rand_delay_medium_sequence::create_seqs() - <seq_type>.create_object() failed")
+    soc_ifc_env_cptra_handler_seq = soc_ifc_env_cptra_mbox_handler_sequence_t::type_id::create("soc_ifc_env_cptra_handler_seq");
+endfunction
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_mbox_rand_delay_small_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_mbox_rand_delay_small_sequence.svh
new file mode 100644
index 000000000..3e036c9e4
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_mbox_rand_delay_small_sequence.svh
@@ -0,0 +1,43 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Sequence to initiate (and respond) to mailbox command
+//              "TOP" sequence because it invokes lower level env sequences
+//              to facilitate the uC/SoC sides of mailbox command handling
+//              and this sequence defines the whole mailbox flow.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_top_mbox_rand_delay_small_sequence extends soc_ifc_env_top_mbox_sequence_base;
+
+
+  `uvm_object_utils( soc_ifc_env_top_mbox_rand_delay_small_sequence )
+
+  extern virtual function      create_seqs();
+
+endclass
+
+function soc_ifc_env_top_mbox_rand_delay_small_sequence::create_seqs();
+    uvm_object obj;
+    obj = soc_ifc_env_mbox_rand_delay_small_sequence_t::get_type().create_object("soc_ifc_env_mbox_seq");
+    if(!$cast(soc_ifc_env_mbox_seq,obj)) `uvm_fatal("SOC_IFC_TOP_MBOX_RAND_DELAY", "soc_ifc_env_top_mbox_rand_delay_small_sequence::create_seqs() - <seq_type>.create_object() failed")
+    soc_ifc_env_cptra_handler_seq = soc_ifc_env_cptra_mbox_handler_sequence_t::type_id::create("soc_ifc_env_cptra_handler_seq");
+endfunction
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_mbox_rand_large_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_mbox_rand_large_sequence.svh
new file mode 100644
index 000000000..c9b5f5629
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_mbox_rand_large_sequence.svh
@@ -0,0 +1,43 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Sequence to initiate (and respond) to mailbox command
+//              "TOP" sequence because it invokes lower level env sequences
+//              to facilitate the uC/SoC sides of mailbox command handling
+//              and this sequence defines the whole mailbox flow.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_top_mbox_rand_large_sequence extends soc_ifc_env_top_mbox_sequence_base;
+
+
+  `uvm_object_utils( soc_ifc_env_top_mbox_rand_large_sequence )
+
+  extern virtual function create_seqs();
+
+endclass
+
+function soc_ifc_env_top_mbox_rand_large_sequence::create_seqs();
+    uvm_object obj;
+    obj = soc_ifc_env_mbox_rand_large_sequence_t::get_type().create_object("soc_ifc_env_mbox_seq");
+    if(!$cast(soc_ifc_env_mbox_seq,obj)) `uvm_fatal("SOC_IFC_TOP_MBOX_RAND_LARGE", "soc_ifc_env_top_mbox_rand_large_sequence::create_seqs() - <seq_type>.create_object() failed")
+    soc_ifc_env_cptra_handler_seq = soc_ifc_env_cptra_mbox_handler_sequence_t::type_id::create("soc_ifc_env_cptra_handler_seq");
+endfunction
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_mbox_rand_large_unlock_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_mbox_rand_large_unlock_sequence.svh
new file mode 100644
index 000000000..db69abf2a
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_mbox_rand_large_unlock_sequence.svh
@@ -0,0 +1,51 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Sequence to initiate (and respond) to mailbox command
+//              "TOP" sequence because it invokes lower level env sequences
+//              to facilitate the uC/SoC sides of mailbox command handling
+//              and this sequence defines the whole mailbox flow.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_top_mbox_rand_large_unlock_sequence extends soc_ifc_env_top_mbox_sequence_base;
+
+
+  `uvm_object_utils( soc_ifc_env_top_mbox_rand_large_unlock_sequence )
+
+  extern virtual function create_seqs();
+  extern virtual function randomize_seqs();
+
+endclass
+
+function soc_ifc_env_top_mbox_rand_large_unlock_sequence::create_seqs();
+    uvm_object obj;
+    obj = soc_ifc_env_mbox_rand_large_sequence_t::get_type().create_object("soc_ifc_env_mbox_seq");
+    if(!$cast(soc_ifc_env_mbox_seq,obj)) `uvm_fatal("SOC_IFC_TOP_MBOX_RAND_LARGE", "soc_ifc_env_top_mbox_rand_large_unlock_sequence::create_seqs() - <seq_type>.create_object() failed")
+    soc_ifc_env_cptra_handler_seq = soc_ifc_env_cptra_mbox_handler_sequence_t::type_id::create("soc_ifc_env_cptra_handler_seq");
+endfunction
+
+function soc_ifc_env_top_mbox_rand_large_unlock_sequence::randomize_seqs();
+    if(!soc_ifc_env_mbox_seq.randomize())
+        `uvm_fatal("SOC_IFC_MBOX_TOP", $sformatf("soc_ifc_env_top_mbox_rand_large_unlock_sequence::body() - %s randomization failed", soc_ifc_env_mbox_seq.get_type_name()));
+    if(!soc_ifc_env_cptra_handler_seq.randomize() with { inject_force_unlock == 1'b1; })
+        `uvm_fatal("SOC_IFC_MBOX_TOP", $sformatf("soc_ifc_env_top_mbox_rand_large_unlock_sequence::body() - %s randomization failed", soc_ifc_env_cptra_handler_seq.get_type_name()));
+endfunction
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_mbox_reg_axs_invalid_large_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_mbox_reg_axs_invalid_large_sequence.svh
new file mode 100644
index 000000000..5576ddb0c
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_mbox_reg_axs_invalid_large_sequence.svh
@@ -0,0 +1,53 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Sequence to initiate (and respond) to mailbox command
+//              "TOP" sequence because it invokes lower level env sequences
+//              to facilitate the uC/SoC sides of mailbox command handling
+//              and this sequence defines the whole mailbox flow.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_top_mbox_reg_axs_invalid_large_sequence extends soc_ifc_env_top_mbox_sequence_base;
+
+
+  `uvm_object_utils( soc_ifc_env_top_mbox_reg_axs_invalid_large_sequence )
+
+  extern virtual function      create_seqs();
+
+endclass
+
+function soc_ifc_env_top_mbox_reg_axs_invalid_large_sequence::create_seqs();
+    uvm_object obj;
+    enum {
+        BASE,
+        INTRFR
+    } handler_type;
+    obj = soc_ifc_env_mbox_reg_axs_invalid_large_sequence_t::get_type().create_object("soc_ifc_env_mbox_seq");
+    if(!$cast(soc_ifc_env_mbox_seq,obj)) `uvm_fatal("SOC_IFC_TOP_MBOX_REG_AXS_INVALID", "soc_ifc_env_top_mbox_reg_axs_invalid_large_sequence::create_seqs() - <seq_type>.create_object() failed")
+    void'(std::randomize(handler_type));
+    case (handler_type) inside
+        BASE:    obj = soc_ifc_env_cptra_mbox_handler_sequence_t::get_type().create_object("soc_ifc_env_cptra_handler_seq");
+        INTRFR:  obj = soc_ifc_env_cptra_mbox_interference_handler_sequence_t::get_type().create_object("soc_ifc_env_cptra_handler_seq");
+        default: `uvm_fatal("SOC_IFC_TOP_MBOX_REG_AXS_INVALID", $sformatf("Bad handler type - %p", handler_type))
+    endcase
+    if(!$cast(soc_ifc_env_cptra_handler_seq,obj)) `uvm_fatal("SOC_IFC_TOP_MBOX_REG_AXS_INVALID", "soc_ifc_env_top_mbox_reg_axs_invalid_large_sequence::create_seqs() - <seq_type>.create_object() failed")
+endfunction
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_mbox_reg_axs_invalid_medium_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_mbox_reg_axs_invalid_medium_sequence.svh
new file mode 100644
index 000000000..bf207b577
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_mbox_reg_axs_invalid_medium_sequence.svh
@@ -0,0 +1,53 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Sequence to initiate (and respond) to mailbox command
+//              "TOP" sequence because it invokes lower level env sequences
+//              to facilitate the uC/SoC sides of mailbox command handling
+//              and this sequence defines the whole mailbox flow.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_top_mbox_reg_axs_invalid_medium_sequence extends soc_ifc_env_top_mbox_sequence_base;
+
+
+  `uvm_object_utils( soc_ifc_env_top_mbox_reg_axs_invalid_medium_sequence )
+
+  extern virtual function      create_seqs();
+
+endclass
+
+function soc_ifc_env_top_mbox_reg_axs_invalid_medium_sequence::create_seqs();
+    uvm_object obj;
+    enum {
+        BASE,
+        INTRFR
+    } handler_type;
+    obj = soc_ifc_env_mbox_reg_axs_invalid_medium_sequence_t::get_type().create_object("soc_ifc_env_mbox_seq");
+    if(!$cast(soc_ifc_env_mbox_seq,obj)) `uvm_fatal("SOC_IFC_TOP_MBOX_REG_AXS_INVALID", "soc_ifc_env_top_mbox_reg_axs_invalid_medium_sequence::create_seqs() - <seq_type>.create_object() failed")
+    void'(std::randomize(handler_type));
+    case (handler_type) inside
+        BASE:    obj = soc_ifc_env_cptra_mbox_handler_sequence_t::get_type().create_object("soc_ifc_env_cptra_handler_seq");
+        INTRFR:  obj = soc_ifc_env_cptra_mbox_interference_handler_sequence_t::get_type().create_object("soc_ifc_env_cptra_handler_seq");
+        default: `uvm_fatal("SOC_IFC_TOP_MBOX_REG_AXS_INVALID", $sformatf("Bad handler type - %p", handler_type))
+    endcase
+    if(!$cast(soc_ifc_env_cptra_handler_seq,obj)) `uvm_fatal("SOC_IFC_TOP_MBOX_REG_AXS_INVALID", "soc_ifc_env_top_mbox_reg_axs_invalid_large_sequence::create_seqs() - <seq_type>.create_object() failed")
+endfunction
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_mbox_reg_axs_invalid_small_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_mbox_reg_axs_invalid_small_sequence.svh
new file mode 100644
index 000000000..fbe6034ec
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc_env_top_mbox_reg_axs_invalid_small_sequence.svh
@@ -0,0 +1,53 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Sequence to initiate (and respond) to mailbox command
+//              "TOP" sequence because it invokes lower level env sequences
+//              to facilitate the uC/SoC sides of mailbox command handling
+//              and this sequence defines the whole mailbox flow.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_top_mbox_reg_axs_invalid_small_sequence extends soc_ifc_env_top_mbox_sequence_base;
+
+
+  `uvm_object_utils( soc_ifc_env_top_mbox_reg_axs_invalid_small_sequence )
+
+  extern virtual function      create_seqs();
+
+endclass
+
+function soc_ifc_env_top_mbox_reg_axs_invalid_small_sequence::create_seqs();
+    uvm_object obj;
+    enum {
+        BASE,
+        INTRFR
+    } handler_type;
+    obj = soc_ifc_env_mbox_reg_axs_invalid_small_sequence_t::get_type().create_object("soc_ifc_env_mbox_seq");
+    if(!$cast(soc_ifc_env_mbox_seq,obj)) `uvm_fatal("SOC_IFC_TOP_MBOX_REG_AXS_INVALID", "soc_ifc_env_top_mbox_reg_axs_invalid_small_sequence::create_seqs() - <seq_type>.create_object() failed")
+    void'(std::randomize(handler_type));
+    case (handler_type) inside
+        BASE:    obj = soc_ifc_env_cptra_mbox_handler_sequence_t::get_type().create_object("soc_ifc_env_cptra_handler_seq");
+        INTRFR:  obj = soc_ifc_env_cptra_mbox_interference_handler_sequence_t::get_type().create_object("soc_ifc_env_cptra_handler_seq");
+        default: `uvm_fatal("SOC_IFC_TOP_MBOX_REG_AXS_INVALID", $sformatf("Bad handler type - %p", handler_type))
+    endcase
+    if(!$cast(soc_ifc_env_cptra_handler_seq,obj)) `uvm_fatal("SOC_IFC_TOP_MBOX_REG_AXS_INVALID", "soc_ifc_env_top_mbox_reg_axs_invalid_large_sequence::create_seqs() - <seq_type>.create_object() failed")
+endfunction
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/sha_accel/soc_ifc_env_sha_accel_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/sha_accel/soc_ifc_env_sha_accel_sequence.svh
index 74290e01b..5ac1f3a6d 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/sha_accel/soc_ifc_env_sha_accel_sequence.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/sha_accel/soc_ifc_env_sha_accel_sequence.svh
@@ -181,6 +181,10 @@ task soc_ifc_env_sha_accel_sequence::sha_accel_acquire_lock(output op_sts_e op_s
         reg_model.sha512_acc_csr_rm.LOCK.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(apb_user_obj));
         report_reg_sts(reg_sts, "LOCK");
     end
+    //Read the lock again to test predictor
+    configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(200); // FIXME add more randomization on delay
+    reg_model.sha512_acc_csr_rm.LOCK.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(apb_user_obj));
+    report_reg_sts(reg_sts, "LOCK");
     op_sts = CPTRA_SUCCESS;
 endtask
 
@@ -197,6 +201,14 @@ task soc_ifc_env_sha_accel_sequence::sha_accel_set_cmd(input sha_accel_op_s op);
 
     reg_model.sha512_acc_csr_rm.DLEN.write(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(apb_user_obj));
     report_reg_sts(reg_sts, "DLEN");
+
+    //read back some fields to test predictor
+    reg_model.sha512_acc_csr_rm.USER.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(apb_user_obj));
+    report_reg_sts(reg_sts, "USER");
+    reg_model.sha512_acc_csr_rm.MODE.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(apb_user_obj));
+    report_reg_sts(reg_sts, "MODE");
+    reg_model.sha512_acc_csr_rm.DLEN.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(apb_user_obj));
+    report_reg_sts(reg_sts, "DLEN");  
 endtask
 
 task soc_ifc_env_sha_accel_sequence::sha_accel_push_datain(reg [3199:0][31:0] sha_block_data);
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/trng/cptra/soc_ifc_env_cptra_trng_data_req_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/trng/cptra/soc_ifc_env_cptra_trng_data_req_sequence.svh
index 7f86f5e15..bcfebf76f 100755
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/trng/cptra/soc_ifc_env_cptra_trng_data_req_sequence.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/trng/cptra/soc_ifc_env_cptra_trng_data_req_sequence.svh
@@ -114,4 +114,11 @@ task soc_ifc_env_cptra_trng_data_req_sequence::soc_ifc_ext_trng_clear_req();
     reg_model.soc_ifc_reg_rm.CPTRA_TRNG_STATUS.write(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
     if (reg_sts != UVM_IS_OK)
         `uvm_error("TRNG_REQ_SEQ", "Register access failed to write TRNG_STATUS register")
+
+    //Set TRNG CTRL clear bit to clear data regs
+    reg_model.soc_ifc_reg_rm.CPTRA_TRNG_CTRL.write(reg_sts, uvm_reg_data_t'(1), UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this);
+    
+    if (reg_sts != UVM_IS_OK)
+        `uvm_error("TRNG_REQ_SEQ", "Register access failed to write TRNG_CTRL register")
+    
 endtask
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/trng/soc_ifc/soc_ifc_env_trng_write_data_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/trng/soc_ifc/soc_ifc_env_trng_write_data_sequence.svh
index d2acca98a..5f4a8b35e 100755
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/trng/soc_ifc/soc_ifc_env_trng_write_data_sequence.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/trng/soc_ifc/soc_ifc_env_trng_write_data_sequence.svh
@@ -31,6 +31,7 @@ class soc_ifc_env_trng_write_data_sequence extends soc_ifc_env_sequence_base #(.
   rand bit trng_write_done;
   rand bit [3:0] trng_num_dwords;
 
+  int sts_rsp_count;
   bit trng_data_req;
 
   bit [apb5_master_0_params::PAUSER_WIDTH-1:0] trng_valid_user;
@@ -69,15 +70,24 @@ class soc_ifc_env_trng_write_data_sequence extends soc_ifc_env_sequence_base #(.
 
   virtual task body();
 
+    sts_rsp_count = 0;
+
+    fork
+        forever begin
+            @(soc_ifc_status_agent_rsp_seq.new_rsp) sts_rsp_count++;
+        end
+    join_none
+
     soc_ifc_env_trng_setup();
-    `uvm_info("TRNG_REQ_SEQ", $sformatf("Responding to TRNG_DATA_REQ with %0d dwords", trng_num_dwords), UVM_DEBUG)
     if (this.trng_data_req == 1'b0) 
       soc_ifc_env_trng_poll_data_req();
     if (this.trng_data_req) begin
+      `uvm_info("TRNG_REQ_SEQ", $sformatf("Responding to TRNG_DATA_REQ with %0d dwords", trng_num_dwords), UVM_FULL)
       soc_ifc_env_trng_write_data();
       soc_ifc_env_trng_write_done();
       soc_ifc_env_trng_wait_idle();
     end
+    `uvm_info("TRNG_REQ_SEQ", "TRNG write data sequence completed", UVM_HIGH)
 
   endtask
 
@@ -108,6 +118,7 @@ task soc_ifc_env_trng_write_data_sequence::soc_ifc_env_trng_setup();
 
     // Assign user and use throughout sequence
     apb_user_obj.set_addr_user(trng_valid_user);
+    `uvm_info("TRNG_REQ_SEQ", $sformatf("trng_valid_user initialized to value 0x%x", trng_valid_user), UVM_HIGH)
 
 endtask
 
@@ -120,10 +131,15 @@ task soc_ifc_env_trng_write_data_sequence::soc_ifc_env_trng_poll_data_req();
 
   soc_ifc_env_trng_check_data_req(data_req);
   while (data_req == 1'b0) begin
-    configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(200);
-    soc_ifc_env_trng_check_data_req(data_req);
+    wait (sts_rsp_count != 0);
+    data_req = soc_ifc_status_agent_rsp_seq.rsp.trng_req_pending;
+    sts_rsp_count = 0;
   end
+  soc_ifc_env_trng_check_data_req(data_req);
+  if (!data_req)
+    `uvm_error("TRNG_REQ_SEQ", "Got status transaction with trng_req_pending, but read from CPTRA_TRNG_STATUS.DATA_REQ returned 0!")
   this.trng_data_req = data_req;
+  `uvm_info("TRNG_REQ_SEQ", $sformatf("Got status transaction with trng_req_pending, read from CPTRA_TRNG_STATUS.DATA_REQ returned %d", data_req), UVM_MEDIUM)
 endtask
 
 //==========================================
@@ -152,7 +168,7 @@ task soc_ifc_env_trng_write_data_sequence::soc_ifc_env_trng_write_data();
   uvm_reg_data_t data;
   for (ii = 0; ii < this.trng_num_dwords; ii++) begin
     if (!std::randomize(data)) `uvm_error("TRNG_REQ_SEQ", "Failed to randomize data")
-    `uvm_info("TRNG_REQ_SEQ", $sformatf("Sending TRNG_DATA[%0d]: 0x%0x", ii, data), UVM_DEBUG)
+    `uvm_info("TRNG_REQ_SEQ", $sformatf("Sending TRNG_DATA[%0d]: 0x%0x", ii, data), UVM_HIGH)
     reg_model.soc_ifc_reg_rm.CPTRA_TRNG_DATA[ii].write(reg_sts, uvm_reg_data_t'(data), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(apb_user_obj));
     if (reg_sts != UVM_IS_OK) 
       `uvm_error("TRNG_REQ_SEQ", "Register access failed (TRNG_DATA)")
@@ -165,7 +181,7 @@ endtask
 //==========================================
 task soc_ifc_env_trng_write_data_sequence::soc_ifc_env_trng_write_done();
   uvm_status_e reg_sts;
-  `uvm_info("TRNG_REQ_SEQ", "Sending TRNG_DONE", UVM_DEBUG)
+  `uvm_info("TRNG_REQ_SEQ", "Sending TRNG_DONE", UVM_MEDIUM)
   reg_model.soc_ifc_reg_rm.CPTRA_TRNG_STATUS.write(reg_sts, uvm_reg_data_t'(trng_write_done) << reg_model.soc_ifc_reg_rm.CPTRA_TRNG_STATUS.DATA_WR_DONE.get_lsb_pos(), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(apb_user_obj));
   if (reg_sts != UVM_IS_OK) 
     `uvm_error("TRNG_REQ_SEQ", "Register access failed (TRNG_DONE)")
@@ -191,4 +207,5 @@ task soc_ifc_env_trng_write_data_sequence::soc_ifc_env_trng_wait_idle();
       if (reg_sts != UVM_IS_OK) 
         `uvm_error("TRNG_REQ_SEQ", "Register access failed (CPTRA_TRNG_STATUS)")
   end
+  `uvm_info("TRNG_REQ_SEQ", "Observed TRNG_DONE cleared to 0", UVM_HIGH)
 endtask
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/wdt/cptra/soc_ifc_env_cptra_wdt_cascade_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/wdt/cptra/soc_ifc_env_cptra_wdt_cascade_sequence.svh
new file mode 100644
index 000000000..58822372a
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/wdt/cptra/soc_ifc_env_cptra_wdt_cascade_sequence.svh
@@ -0,0 +1,49 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Bringup sequence for the SOC_IFC environment
+//              (essentially just a cold-reset sequence)
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_cptra_wdt_cascade_sequence extends soc_ifc_env_wdt_sequence_base;
+
+
+    `uvm_object_utils( soc_ifc_env_cptra_wdt_cascade_sequence )
+
+    // typedef soc_ifc_ctrl_sequence_base soc_ifc_ctrl_sequence_t;
+    // soc_ifc_ctrl_sequence_t soc_ifc_ctrl_seq;
+  
+    typedef soc_ifc_ctrl_wdt_cascade_sequence soc_ifc_ctrl_wdt_cascade_sequence_t;
+  
+    function new(string name = "" );
+      uvm_object obj;
+      super.new(name);
+    //   soc_ifc_ctrl_seq = soc_ifc_ctrl_sequence_t::type_id::create("soc_ifc_ctrl_seq");
+      obj = soc_ifc_ctrl_wdt_cascade_sequence_t::get_type().create_object("soc_ifc_ctrl_wdt_cascade_seq");
+      if (!$cast(soc_ifc_ctrl_seq,obj))
+          `uvm_fatal("SOC_IFC_WDT", "Failed to cast object as WDT sequence!")
+    endfunction
+  
+  endclass
+  
\ No newline at end of file
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/wdt/cptra/soc_ifc_env_cptra_wdt_independent_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/wdt/cptra/soc_ifc_env_cptra_wdt_independent_sequence.svh
new file mode 100644
index 000000000..9334e1004
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/wdt/cptra/soc_ifc_env_cptra_wdt_independent_sequence.svh
@@ -0,0 +1,49 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Bringup sequence for the SOC_IFC environment
+//              (essentially just a cold-reset sequence)
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_cptra_wdt_independent_sequence extends soc_ifc_env_wdt_sequence_base;
+
+
+    `uvm_object_utils( soc_ifc_env_cptra_wdt_independent_sequence )
+
+    // typedef soc_ifc_ctrl_sequence_base soc_ifc_ctrl_sequence_t;
+    // soc_ifc_ctrl_sequence_t soc_ifc_ctrl_seq;
+  
+    typedef soc_ifc_ctrl_wdt_independent_sequence soc_ifc_ctrl_wdt_independent_sequence_t;
+  
+    function new(string name = "" );
+      uvm_object obj;
+      super.new(name);
+    //   soc_ifc_ctrl_seq = soc_ifc_ctrl_sequence_t::type_id::create("soc_ifc_ctrl_seq");
+      obj = soc_ifc_ctrl_wdt_independent_sequence_t::get_type().create_object("soc_ifc_ctrl_wdt_independent_seq");
+      if (!$cast(soc_ifc_ctrl_seq,obj))
+          `uvm_fatal("SOC_IFC_WDT", "Failed to cast object as WDT sequence!")
+    endfunction
+  
+  endclass
+  
\ No newline at end of file
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/wdt/cptra/soc_ifc_env_wdt_sequence_base.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/wdt/cptra/soc_ifc_env_wdt_sequence_base.svh
new file mode 100644
index 000000000..940209c2f
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/wdt/cptra/soc_ifc_env_wdt_sequence_base.svh
@@ -0,0 +1,120 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Issue a reset in the soc_ifc environment
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_env_wdt_sequence_base extends soc_ifc_env_sequence_base #(.CONFIG_T(soc_ifc_env_configuration_t));
+
+
+    `uvm_object_utils( soc_ifc_env_wdt_sequence_base )
+  
+      typedef soc_ifc_ctrl_sequence_base soc_ifc_ctrl_sequence_t;
+      soc_ifc_ctrl_sequence_t soc_ifc_ctrl_seq;
+  
+    // caliptra_apb_user apb_user_obj;
+  
+    // typedef struct packed {
+    //     bit              set_bootfsm_breakpoint;
+    //     security_state_t security_state;
+    // } ctrl_reset_seq_context_t;
+  
+    // rand uvm_reg_data_t uds_seed_rand      [12];
+    // rand uvm_reg_data_t field_entropy_rand [32];
+    // rand uvm_reg_data_t owner_pk_hash_rand [12];
+    // rand uvm_reg_data_t key_manifest_pk_hash_rand [12];
+    // rand uvm_reg_data_t idevid_cert_attr_rand [24];
+    // rand uvm_reg_data_t soc_stepping_id_rand;
+    // rand struct packed {
+    //   bit uds;
+    //   bit field_entropy;
+    //   bit [0:11] key_manifest_pk_hash;
+    //   bit [0:11] owner_pk_hash;
+    //   bit soc_stepping_id;
+    //   bit [0:23] idevid_cert_attr;
+    //   bit lms_verify;
+    // } fuses_to_set;
+  
+  
+    //==========================================
+    // Name:        new
+    // Description: Constructor
+    //==========================================
+    function new(string name = "" );
+      super.new(name);
+      soc_ifc_ctrl_seq = soc_ifc_ctrl_sequence_t::type_id::create("soc_ifc_ctrl_seq");
+        
+      // Setup a User object to override PAUSER
+    //   apb_user_obj = new();
+  
+    endfunction
+  
+  
+    //==========================================
+    // Name:        run_ctrl_seq
+    // Description: Run low-level soc_ifc_ctrl sequence to wiggle gen input wires to let RT fw know which mode of WDT to enable
+    //==========================================
+    virtual task run_ctrl_seq();
+      if ( configuration.soc_ifc_ctrl_agent_config.sequencer != null )
+          soc_ifc_ctrl_seq.start(configuration.soc_ifc_ctrl_agent_config.sequencer);
+      else
+          `uvm_error("SOC_IFC_WDT", "soc_ifc_ctrl_agent_config.sequencer is null!")
+  
+    endtask
+  
+  
+    
+  
+    //==========================================
+    // Name:        pre_body
+    // Description: Setup tasks to:
+    //               - get a reg model handle
+    //               - check for a valid responder handle
+    //==========================================
+    virtual task pre_body();
+      super.pre_body();
+      reg_model = configuration.soc_ifc_rm;
+      if (soc_ifc_status_agent_rsp_seq == null)
+          `uvm_fatal("SOC_IFC_WDT", "SOC_IFC ENV wdt sequence expected a handle to the soc_ifc status agent responder sequence (from bench-level sequence) but got null!")
+    //   apb_user_obj.set_addr_user(reg_model.soc_ifc_reg_rm.CPTRA_MBOX_VALID_PAUSER[0].PAUSER.get_reset("HARD"));
+    endtask
+  
+  
+    //==========================================
+    // Name:        body
+    // Description: Run the main functionality
+    //==========================================
+    virtual task body();
+
+  
+      // Run ctrl seq
+      run_ctrl_seq();
+  
+      
+  
+    endtask
+  
+  endclass
+  
+  
\ No newline at end of file
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/soc_ifc_env_pkg.compile b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/soc_ifc_env_pkg.compile
index 8f6852326..57aedbdc2 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/soc_ifc_env_pkg.compile
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/soc_ifc_env_pkg.compile
@@ -4,6 +4,7 @@ needs:
   - ../../../verification_ip/interface_packages/cptra_ctrl_pkg/cptra_ctrl_hvl.compile
   - ../../../verification_ip/interface_packages/soc_ifc_status_pkg/soc_ifc_status_hvl.compile
   - ../../../verification_ip/interface_packages/cptra_status_pkg/cptra_status_hvl.compile
+  - ../../../verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_hvl.compile
 
 src:
   - registers/soc_ifc_reg_model_top_pkg.sv
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/soc_ifc_env_pkg.sv b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/soc_ifc_env_pkg.sv
index 9e93f03ff..38fae2c2f 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/soc_ifc_env_pkg.sv
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/soc_ifc_env_pkg.sv
@@ -50,6 +50,8 @@ package soc_ifc_env_pkg;
   import soc_ifc_status_pkg_hdl::*;
   import cptra_status_pkg::*;
   import cptra_status_pkg_hdl::*;
+  import mbox_sram_pkg::*;
+  import mbox_sram_pkg_hdl::*;
   import soc_ifc_reg_model_top_pkg::*;
   import qvip_ahb_lite_slave_pkg::*;
   import qvip_ahb_lite_slave_params_pkg::*;
@@ -58,6 +60,7 @@ package soc_ifc_env_pkg;
  
   `uvm_analysis_imp_decl(_soc_ifc_ctrl_agent_ae)
   `uvm_analysis_imp_decl(_cptra_ctrl_agent_ae)
+  `uvm_analysis_imp_decl(_mbox_sram_agent_ae)
   `uvm_analysis_imp_decl(_ahb_slave_0_ae)
   `uvm_analysis_imp_decl(_apb5_slave_0_ae)
   `uvm_analysis_imp_decl(_expected_analysis_export)
@@ -68,6 +71,14 @@ package soc_ifc_env_pkg;
   `uvm_analysis_imp_decl(_expected_apb_analysis_export)
   `uvm_analysis_imp_decl(_actual_ahb_analysis_export)
   `uvm_analysis_imp_decl(_actual_apb_analysis_export)
+ 
+  `uvm_analysis_imp_decl(_cov_soc_ifc_ctrl_ae)
+  `uvm_analysis_imp_decl(_cov_soc_ifc_status_ae)
+  `uvm_analysis_imp_decl(_cov_apb_ae)
+  `uvm_analysis_imp_decl(_cov_cptra_ctrl_ae)
+  `uvm_analysis_imp_decl(_cov_cptra_status_ae)
+  `uvm_analysis_imp_decl(_cov_ahb_ae)
+  `uvm_analysis_imp_decl(_cov_mbox_sram_ae)
 
   // pragma uvmf custom package_imports_additional begin
   import soc_ifc_pkg::*;
@@ -80,6 +91,8 @@ package soc_ifc_env_pkg;
   `include "src/soc_ifc_env_configuration.svh"
   `include "src/soc_ifc_predictor.svh"
   `include "src/soc_ifc_scoreboard.svh"
+  `include "src/soc_ifc_reg_cov_subscriber.svh"
+  `include "src/soc_ifc_env_cov_subscriber.svh"
   `include "src/soc_ifc_environment.svh"
   `include "src/soc_ifc_env_sequence_base.svh"
 
@@ -100,6 +113,8 @@ package soc_ifc_env_pkg;
   typedef soc_ifc_env_reset_sequence_base soc_ifc_env_reset_sequence_base_t;
   `include "sequences/bringup/soc_ifc/soc_ifc_env_bringup_sequence.svh"
   typedef soc_ifc_env_bringup_sequence soc_ifc_env_bringup_sequence_t;
+  `include "sequences/bringup/soc_ifc/soc_ifc_env_rom_bringup_sequence.svh"
+  typedef soc_ifc_env_rom_bringup_sequence soc_ifc_env_rom_bringup_sequence_t;
   `include "sequences/bringup/soc_ifc/soc_ifc_env_pauser_init_sequence.svh"
   typedef soc_ifc_env_pauser_init_sequence soc_ifc_env_pauser_init_sequence_t;
   `include "sequences/bringup/soc_ifc/soc_ifc_env_reset_warm_sequence.svh"
@@ -112,8 +127,16 @@ package soc_ifc_env_pkg;
   typedef soc_ifc_env_mbox_rand_fw_sequence soc_ifc_env_mbox_rand_fw_sequence_t;
   `include "sequences/mbox/soc_ifc/soc_ifc_env_mbox_real_fw_sequence.svh"
   typedef soc_ifc_env_mbox_real_fw_sequence soc_ifc_env_mbox_real_fw_sequence_t;
+  `include "sequences/mbox/soc_ifc/soc_ifc_env_mbox_fw_upd_sequence.svh"
+  typedef soc_ifc_env_mbox_fw_upd_sequence soc_ifc_env_mbox_fw_upd_sequence_t;
+  `include "sequences/mbox/soc_ifc/soc_ifc_env_mbox_rom_fw_sequence.svh"
+  typedef soc_ifc_env_mbox_rom_fw_sequence soc_ifc_env_mbox_rom_fw_sequence_t;
   `include "sequences/mbox/soc_ifc/soc_ifc_env_mbox_rand_small_sequence.svh"
   typedef soc_ifc_env_mbox_rand_small_sequence soc_ifc_env_mbox_rand_small_sequence_t;
+  `include "sequences/mbox/soc_ifc/soc_ifc_env_mbox_min_sequence.svh"
+  typedef soc_ifc_env_mbox_min_sequence soc_ifc_env_mbox_min_sequence_t;
+  `include "sequences/mbox/soc_ifc/soc_ifc_env_mbox_max_sequence.svh"
+  typedef soc_ifc_env_mbox_max_sequence soc_ifc_env_mbox_max_sequence_t;
   `include "sequences/mbox/soc_ifc/soc_ifc_env_mbox_rand_medium_sequence.svh"
   typedef soc_ifc_env_mbox_rand_medium_sequence soc_ifc_env_mbox_rand_medium_sequence_t;
   `include "sequences/mbox/soc_ifc/soc_ifc_env_mbox_rand_large_sequence.svh"
@@ -128,8 +151,26 @@ package soc_ifc_env_pkg;
   typedef soc_ifc_env_mbox_rand_pauser_medium_sequence soc_ifc_env_mbox_rand_pauser_medium_sequence_t;
   `include "sequences/mbox/soc_ifc/soc_ifc_env_mbox_rand_pauser_large_sequence.svh"
   typedef soc_ifc_env_mbox_rand_pauser_large_sequence soc_ifc_env_mbox_rand_pauser_large_sequence_t;
-  `include "sequences/mbox/soc_ifc/soc_ifc_env_mbox_rand_multi_agent_sequence.svh"
-  typedef soc_ifc_env_mbox_rand_multi_agent_sequence soc_ifc_env_mbox_rand_multi_agent_sequence_t;
+  `include "sequences/mbox/soc_ifc/soc_ifc_env_mbox_rand_delay_sequence.svh"
+  typedef soc_ifc_env_mbox_rand_delay_sequence soc_ifc_env_mbox_rand_delay_sequence_t;
+  `include "sequences/mbox/soc_ifc/soc_ifc_env_mbox_rand_delay_small_sequence.svh"
+  typedef soc_ifc_env_mbox_rand_delay_small_sequence soc_ifc_env_mbox_rand_delay_small_sequence_t;
+  `include "sequences/mbox/soc_ifc/soc_ifc_env_mbox_rand_delay_medium_sequence.svh"
+  typedef soc_ifc_env_mbox_rand_delay_medium_sequence soc_ifc_env_mbox_rand_delay_medium_sequence_t;
+  `include "sequences/mbox/soc_ifc/soc_ifc_env_mbox_rand_delay_large_sequence.svh"
+  typedef soc_ifc_env_mbox_rand_delay_large_sequence soc_ifc_env_mbox_rand_delay_large_sequence_t;
+  `include "sequences/mbox/soc_ifc/soc_ifc_env_mbox_reg_axs_invalid_sequence.svh"
+  typedef soc_ifc_env_mbox_reg_axs_invalid_sequence soc_ifc_env_mbox_reg_axs_invalid_sequence_t;
+  `include "sequences/mbox/soc_ifc/soc_ifc_env_mbox_reg_axs_invalid_small_sequence.svh"
+  typedef soc_ifc_env_mbox_reg_axs_invalid_small_sequence soc_ifc_env_mbox_reg_axs_invalid_small_sequence_t;
+  `include "sequences/mbox/soc_ifc/soc_ifc_env_mbox_reg_axs_invalid_medium_sequence.svh"
+  typedef soc_ifc_env_mbox_reg_axs_invalid_medium_sequence soc_ifc_env_mbox_reg_axs_invalid_medium_sequence_t;
+  `include "sequences/mbox/soc_ifc/soc_ifc_env_mbox_reg_axs_invalid_large_sequence.svh"
+  typedef soc_ifc_env_mbox_reg_axs_invalid_large_sequence soc_ifc_env_mbox_reg_axs_invalid_large_sequence_t;
+  `include "sequences/mbox/soc_ifc/soc_ifc_env_mbox_dlen_invalid_sequence.svh"
+  typedef soc_ifc_env_mbox_dlen_invalid_sequence soc_ifc_env_mbox_dlen_invalid_sequence_t;
+  `include "sequences/mbox/soc_ifc/soc_ifc_env_mbox_dir_read_sequence.svh"
+  typedef soc_ifc_env_mbox_dir_read_sequence soc_ifc_env_mbox_dir_read_sequence_t;
   `include "sequences/mbox/soc_ifc/soc_ifc_env_mbox_dlen_overflow_sequence.svh"
   typedef soc_ifc_env_mbox_dlen_overflow_sequence soc_ifc_env_mbox_dlen_overflow_sequence_t;
   `include "sequences/mbox/soc_ifc/soc_ifc_env_mbox_dlen_overflow_small_sequence.svh"
@@ -146,6 +187,16 @@ package soc_ifc_env_pkg;
   typedef soc_ifc_env_mbox_dlen_underflow_medium_sequence soc_ifc_env_mbox_dlen_underflow_medium_sequence_t;
   `include "sequences/mbox/soc_ifc/soc_ifc_env_mbox_dlen_underflow_large_sequence.svh"
   typedef soc_ifc_env_mbox_dlen_underflow_large_sequence soc_ifc_env_mbox_dlen_underflow_large_sequence_t;
+  `include "sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_sequence.svh"
+  typedef soc_ifc_env_mbox_sram_double_bit_flip_sequence soc_ifc_env_mbox_sram_double_bit_flip_sequence_t;
+  `include "sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_small_sequence.svh"
+  typedef soc_ifc_env_mbox_sram_double_bit_flip_small_sequence soc_ifc_env_mbox_sram_double_bit_flip_small_sequence_t;
+  `include "sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_medium_sequence.svh"
+  typedef soc_ifc_env_mbox_sram_double_bit_flip_medium_sequence soc_ifc_env_mbox_sram_double_bit_flip_medium_sequence_t;
+  `include "sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_large_sequence.svh"
+  typedef soc_ifc_env_mbox_sram_double_bit_flip_large_sequence soc_ifc_env_mbox_sram_double_bit_flip_large_sequence_t;
+  `include "sequences/mbox/soc_ifc/soc_ifc_env_mbox_rand_multi_agent_sequence.svh"
+  typedef soc_ifc_env_mbox_rand_multi_agent_sequence soc_ifc_env_mbox_rand_multi_agent_sequence_t;
   `include "sequences/mbox/soc_ifc/soc_ifc_env_mbox_rst_sequence.svh"
   typedef soc_ifc_env_mbox_rst_sequence soc_ifc_env_mbox_rst_sequence_t;
   `include "sequences/mbox/soc_ifc/soc_ifc_env_mbox_rst_warm_rand_medium_sequence.svh"
@@ -162,6 +213,14 @@ package soc_ifc_env_pkg;
   typedef soc_ifc_env_trng_write_data_sequence soc_ifc_env_trng_write_data_sequence_t;
   `include "sequences/mbox/soc_ifc/soc_ifc_env_soc_mbox_handler_sequence.svh"
   typedef soc_ifc_env_soc_mbox_handler_sequence soc_ifc_env_soc_mbox_handler_sequence_t;
+  `include "sequences/mbox/soc_ifc/soc_ifc_env_soc_mbox_reg_axs_invalid_handler_sequence.svh"
+  typedef soc_ifc_env_soc_mbox_reg_axs_invalid_handler_sequence soc_ifc_env_soc_mbox_reg_axs_invalid_handler_sequence_t;
+  `include "sequences/wdt/cptra/soc_ifc_env_wdt_sequence_base.svh"
+  typedef soc_ifc_env_wdt_sequence_base soc_ifc_env_wdt_sequence_base_t;
+  `include "sequences/wdt/cptra/soc_ifc_env_cptra_wdt_independent_sequence.svh"
+  typedef soc_ifc_env_cptra_wdt_independent_sequence soc_ifc_env_cptra_wdt_independent_sequence_t;
+  `include "sequences/wdt/cptra/soc_ifc_env_cptra_wdt_cascade_sequence.svh"
+  typedef soc_ifc_env_cptra_wdt_cascade_sequence soc_ifc_env_cptra_wdt_cascade_sequence_t;
 
   ///////////////////// Sequences usable from soc_ifc bench only /////////////////////
   // These sequences include stimulus for the internal/caliptra-side of the
@@ -169,6 +228,8 @@ package soc_ifc_env_pkg;
   /* TODO: If desired in top-level rand sequence, add this to the rand_seq_idx enum/avail_env_seqs_c constraint */
   `include "sequences/bringup/cptra/soc_ifc_env_cptra_rst_wait_sequence.svh"
   typedef soc_ifc_env_cptra_rst_wait_sequence soc_ifc_env_cptra_rst_wait_sequence_t;
+  `include "sequences/bringup/cptra/soc_ifc_env_cptra_init_interrupts_sequence.svh"
+  typedef soc_ifc_env_cptra_init_interrupts_sequence soc_ifc_env_cptra_init_interrupts_sequence_t;
   `include "sequences/bringup/soc_ifc_env_top_reset_warm_sequence.svh"
   typedef soc_ifc_env_top_reset_warm_sequence soc_ifc_env_top_reset_warm_sequence_t;
   `include "sequences/bringup/soc_ifc_env_top_reset_cold_sequence.svh"
@@ -187,14 +248,22 @@ package soc_ifc_env_pkg;
   typedef soc_ifc_env_cptra_mbox_req_rand_small_sequence soc_ifc_env_cptra_mbox_req_rand_small_sequence_t;
   `include "sequences/mbox/soc_ifc_env_top_mbox_sequence_base.svh"
   typedef soc_ifc_env_top_mbox_sequence_base soc_ifc_env_top_mbox_sequence_base_t;
+  `include "sequences/mbox/soc_ifc_env_top_mbox_min_sequence.svh"
+  typedef soc_ifc_env_top_mbox_min_sequence soc_ifc_env_top_mbox_min_sequence_t;
+  `include "sequences/mbox/soc_ifc_env_top_mbox_max_sequence.svh"
+  typedef soc_ifc_env_top_mbox_max_sequence soc_ifc_env_top_mbox_max_sequence_t;
   `include "sequences/mbox/soc_ifc_env_top_mbox_rand_small_sequence.svh"
   typedef soc_ifc_env_top_mbox_rand_small_sequence soc_ifc_env_top_mbox_rand_small_sequence_t;
   `include "sequences/mbox/soc_ifc_env_top_mbox_rand_medium_sequence.svh"
   typedef soc_ifc_env_top_mbox_rand_medium_sequence soc_ifc_env_top_mbox_rand_medium_sequence_t;
+  `include "sequences/mbox/soc_ifc_env_top_mbox_rand_large_sequence.svh"
+  typedef soc_ifc_env_top_mbox_rand_large_sequence soc_ifc_env_top_mbox_rand_large_sequence_t;
   `include "sequences/mbox/soc_ifc_env_top_mbox_rand_small_unlock_sequence.svh"
   typedef soc_ifc_env_top_mbox_rand_small_unlock_sequence soc_ifc_env_top_mbox_rand_small_unlock_sequence_t;
   `include "sequences/mbox/soc_ifc_env_top_mbox_rand_medium_unlock_sequence.svh"
   typedef soc_ifc_env_top_mbox_rand_medium_unlock_sequence soc_ifc_env_top_mbox_rand_medium_unlock_sequence_t;
+  `include "sequences/mbox/soc_ifc_env_top_mbox_rand_large_unlock_sequence.svh"
+  typedef soc_ifc_env_top_mbox_rand_large_unlock_sequence soc_ifc_env_top_mbox_rand_large_unlock_sequence_t;
   `include "sequences/mbox/soc_ifc_env_top_mbox_contention_sequence.svh"
   typedef soc_ifc_env_top_mbox_contention_sequence soc_ifc_env_top_mbox_contention_sequence_t;
   `include "sequences/mbox/soc_ifc_env_top_mbox_rand_pauser_sequence.svh"
@@ -217,6 +286,18 @@ package soc_ifc_env_pkg;
   typedef soc_ifc_env_top_mbox_rand_pauser_medium_unlock_sequence soc_ifc_env_top_mbox_rand_pauser_medium_unlock_sequence_t;
   `include "sequences/mbox/soc_ifc_env_top_mbox_rand_pauser_large_unlock_sequence.svh"
   typedef soc_ifc_env_top_mbox_rand_pauser_large_unlock_sequence soc_ifc_env_top_mbox_rand_pauser_large_unlock_sequence_t;
+  `include "sequences/mbox/soc_ifc_env_top_mbox_rand_delay_small_sequence.svh"
+  typedef soc_ifc_env_top_mbox_rand_delay_small_sequence soc_ifc_env_top_mbox_rand_delay_small_sequence_t;
+  `include "sequences/mbox/soc_ifc_env_top_mbox_rand_delay_medium_sequence.svh"
+  typedef soc_ifc_env_top_mbox_rand_delay_medium_sequence soc_ifc_env_top_mbox_rand_delay_medium_sequence_t;
+  `include "sequences/mbox/soc_ifc_env_top_mbox_rand_delay_large_sequence.svh"
+  typedef soc_ifc_env_top_mbox_rand_delay_large_sequence soc_ifc_env_top_mbox_rand_delay_large_sequence_t;
+  `include "sequences/mbox/soc_ifc_env_top_mbox_reg_axs_invalid_small_sequence.svh"
+  typedef soc_ifc_env_top_mbox_reg_axs_invalid_small_sequence soc_ifc_env_top_mbox_reg_axs_invalid_small_sequence_t;
+  `include "sequences/mbox/soc_ifc_env_top_mbox_reg_axs_invalid_medium_sequence.svh"
+  typedef soc_ifc_env_top_mbox_reg_axs_invalid_medium_sequence soc_ifc_env_top_mbox_reg_axs_invalid_medium_sequence_t;
+  `include "sequences/mbox/soc_ifc_env_top_mbox_reg_axs_invalid_large_sequence.svh"
+  typedef soc_ifc_env_top_mbox_reg_axs_invalid_large_sequence soc_ifc_env_top_mbox_reg_axs_invalid_large_sequence_t;
   `include "sequences/mbox/soc_ifc_env_top_mbox_multi_agent_sequence.svh"
   typedef soc_ifc_env_top_mbox_multi_agent_sequence soc_ifc_env_top_mbox_multi_agent_sequence_t;
   `include "sequences/mbox/soc_ifc_env_top_mbox_dlen_violation_sequence.svh"
@@ -231,6 +312,8 @@ package soc_ifc_env_pkg;
   typedef soc_ifc_env_top_cptra_mbox_sequence_base soc_ifc_env_top_cptra_mbox_sequence_base_t;
   `include "sequences/mbox/soc_ifc_env_top_cptra_mbox_rand_small_sequence.svh"
   typedef soc_ifc_env_top_cptra_mbox_rand_small_sequence soc_ifc_env_top_cptra_mbox_rand_small_sequence_t;
+  `include "sequences/mbox/soc_ifc_env_top_cptra_mbox_reg_axs_invalid_small_sequence.svh"
+  typedef soc_ifc_env_top_cptra_mbox_reg_axs_invalid_small_sequence soc_ifc_env_top_cptra_mbox_reg_axs_invalid_small_sequence_t;
 
   // pragma uvmf custom package_item_additional end
 endpackage
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/soc_ifc_env_pkg.vinfo b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/soc_ifc_env_pkg.vinfo
index e54e883b1..ae707c7ab 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/soc_ifc_env_pkg.vinfo
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/soc_ifc_env_pkg.vinfo
@@ -3,6 +3,7 @@
 @use $UVMF_VIP_LIBRARY_HOME/interface_packages/cptra_ctrl_pkg/cptra_ctrl_pkg.vinfo
 @use $UVMF_VIP_LIBRARY_HOME/interface_packages/soc_ifc_status_pkg/soc_ifc_status_pkg.vinfo
 @use $UVMF_VIP_LIBRARY_HOME/interface_packages/cptra_status_pkg/cptra_status_pkg.vinfo
+@use $UVMF_VIP_LIBRARY_HOME/interface_packages/mbox_sram_pkg/mbox_sram_pkg.vinfo
 registers/soc_ifc_reg_model_top_pkg.sv
 +incdir+@vinfodir
 soc_ifc_env_pkg.sv
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_env_configuration.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_env_configuration.svh
index ce2ce0eb6..fbf7ef959 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_env_configuration.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_env_configuration.svh
@@ -57,6 +57,9 @@ extends uvmf_environment_configuration_base;
     typedef cptra_status_configuration cptra_status_agent_config_t;
     rand cptra_status_agent_config_t cptra_status_agent_config;
 
+    typedef mbox_sram_configuration mbox_sram_agent_config_t;
+    rand mbox_sram_agent_config_t mbox_sram_agent_config;
+
 
 
     qvip_ahb_lite_slave_env_configuration     qvip_ahb_lite_slave_subenv_config;
@@ -90,6 +93,7 @@ extends uvmf_environment_configuration_base;
     cptra_ctrl_agent_config = cptra_ctrl_agent_config_t::type_id::create("cptra_ctrl_agent_config");
     soc_ifc_status_agent_config = soc_ifc_status_agent_config_t::type_id::create("soc_ifc_status_agent_config");
     cptra_status_agent_config = cptra_status_agent_config_t::type_id::create("cptra_status_agent_config");
+    mbox_sram_agent_config = mbox_sram_agent_config_t::type_id::create("mbox_sram_agent_config");
 
     qvip_ahb_lite_slave_subenv_config = qvip_ahb_lite_slave_env_configuration::type_id::create("qvip_ahb_lite_slave_subenv_config");
     qvip_apb5_slave_subenv_config = qvip_apb5_slave_env_configuration::type_id::create("qvip_apb5_slave_subenv_config");
@@ -133,6 +137,7 @@ extends uvmf_environment_configuration_base;
      "\n", cptra_ctrl_agent_config.convert2string,
      "\n", soc_ifc_status_agent_config.convert2string,
      "\n", cptra_status_agent_config.convert2string,
+     "\n", mbox_sram_agent_config.convert2string,
 
      "\n", qvip_ahb_lite_slave_subenv_config.convert2string,
      "\n", qvip_apb5_slave_subenv_config.convert2string
@@ -176,20 +181,24 @@ extends uvmf_environment_configuration_base;
   // Interface initialization for local agents
      soc_ifc_ctrl_agent_config.initialize( interface_activity[2], {environment_path,".soc_ifc_ctrl_agent"}, interface_names[2]);
      soc_ifc_ctrl_agent_config.initiator_responder = INITIATOR;
-     // soc_ifc_ctrl_agent_config.has_coverage = 1;
+     soc_ifc_ctrl_agent_config.has_coverage = 1;
      cptra_ctrl_agent_config.initialize( interface_activity[3], {environment_path,".cptra_ctrl_agent"}, interface_names[3]);
      cptra_ctrl_agent_config.initiator_responder = INITIATOR;
-     // cptra_ctrl_agent_config.has_coverage = 1;
+     cptra_ctrl_agent_config.has_coverage = 1;
      soc_ifc_status_agent_config.initialize( interface_activity[4], {environment_path,".soc_ifc_status_agent"}, interface_names[4]);
      soc_ifc_status_agent_config.initiator_responder = RESPONDER;
-     // soc_ifc_status_agent_config.has_coverage = 1;
+     soc_ifc_status_agent_config.has_coverage = 1;
      cptra_status_agent_config.initialize( interface_activity[5], {environment_path,".cptra_status_agent"}, interface_names[5]);
      cptra_status_agent_config.initiator_responder = RESPONDER;
-     // cptra_status_agent_config.has_coverage = 1;
+     cptra_status_agent_config.has_coverage = 1;
+     mbox_sram_agent_config.initialize( interface_activity[6], {environment_path,".mbox_sram_agent"}, interface_names[6]);
+     mbox_sram_agent_config.initiator_responder = RESPONDER;
+     mbox_sram_agent_config.has_coverage = 1;
 
     // pragma uvmf custom reg_model_config_initialize begin
     // Register model creation and configuation
     if (register_model == null) begin
+      uvm_reg::include_coverage("*", UVM_CVR_ALL); // Register coverage config with resource DB, used later by build_coverage()
       soc_ifc_rm = soc_ifc_reg_model_top::type_id::create("soc_ifc_rm");
       soc_ifc_rm.build();
       soc_ifc_rm.lock_model();
@@ -208,7 +217,12 @@ extends uvmf_environment_configuration_base;
 
 
   // pragma uvmf custom initialize begin
+     qvip_ahb_lite_slave_subenv_config.ahb_lite_slave_0_cfg.agent_cfg.en_cvg.slave = 1'b1;
+     qvip_ahb_lite_slave_subenv_config.ahb_lite_slave_0_cfg.agent_cfg.en_cvg.master = 1'b1;
+     qvip_ahb_lite_slave_subenv_config.ahb_lite_slave_0_cfg.agent_cfg.en_cvg.response = 1'b1;
+
      qvip_apb5_slave_subenv_config.apb5_master_0_cfg.agent_cfg.en_sb = 1'b0; /* FIXME -- apb scoreboard flags ERRORs when read_data != write_data to a given address, which happens frequently (non-erroneously) in this environment */
+     qvip_apb5_slave_subenv_config.apb5_master_0_cfg.agent_cfg.en_cvg = 1'b1;
     // Add analysis ports to send Bus traffic to the scoreboard, so that the predictor/scoreboard can check read transfer data
     void'(qvip_ahb_lite_slave_subenv_config.ahb_lite_slave_0_cfg.set_monitor_item( "burst_transfer_sb" , ahb_master_burst_transfer #(ahb_lite_slave_0_params::AHB_NUM_MASTERS,
                                                                                                                                      ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS,
@@ -220,6 +234,17 @@ extends uvmf_environment_configuration_base;
                                                                                                                          apb5_master_0_params::APB3_PADDR_BIT_WIDTH,
                                                                                                                          apb5_master_0_params::APB3_PWDATA_BIT_WIDTH,
                                                                                                                          apb5_master_0_params::APB3_PRDATA_BIT_WIDTH)::type_id::get() ));
+    // Add analysis ports to send Bus traffic to the coverage subscriber
+    void'(qvip_ahb_lite_slave_subenv_config.ahb_lite_slave_0_cfg.set_monitor_item( "burst_transfer_cov" , ahb_master_burst_transfer #(ahb_lite_slave_0_params::AHB_NUM_MASTERS,
+                                                                                                                                      ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS,
+                                                                                                                                      ahb_lite_slave_0_params::AHB_NUM_SLAVES,
+                                                                                                                                      ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH,
+                                                                                                                                      ahb_lite_slave_0_params::AHB_WDATA_WIDTH,
+                                                                                                                                      ahb_lite_slave_0_params::AHB_RDATA_WIDTH)::type_id::get() ));
+    void'(qvip_apb5_slave_subenv_config.apb5_master_0_cfg.set_monitor_item( "trans_ap_cov" , apb3_host_apb3_transaction #(apb5_master_0_params::APB3_SLAVE_COUNT,
+                                                                                                                          apb5_master_0_params::APB3_PADDR_BIT_WIDTH,
+                                                                                                                          apb5_master_0_params::APB3_PWDATA_BIT_WIDTH,
+                                                                                                                          apb5_master_0_params::APB3_PRDATA_BIT_WIDTH)::type_id::get() ));
   // pragma uvmf custom initialize end
 
   endfunction
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_env_cov_subscriber.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_env_cov_subscriber.svh
new file mode 100644
index 000000000..b77ae11d4
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_env_cov_subscriber.svh
@@ -0,0 +1,614 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//------------------------------------------------------------------------------
+//
+// CLASS: soc_ifc_env_cov_subscriber
+//
+// This class provides an analysis export for receiving transactions from a
+// connected analysis export. Making such a connection "subscribes" this
+// component to any transactions emitted by the connected analysis port.
+//
+// This extended class provides a coverage subscriber that receives uvm_reg_item
+// objects exported from the uvm_reg_predictor and calls the sample_values 
+// function for the associated register.
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+//
+// CLASS: soc_ifc_env_cov_subscriber
+//
+// This class instantiates externally defined analysis exports for receiving
+// transactions from connected monitors.
+//
+// This extended class provides a coverage subscriber that receives transaction
+// items from all interfaces and leverages the reg-model and predictor state
+// to calculate functional coverage for UVM stimulus.
+//
+// In the environment build flow, connections are made from monitors to the
+// analysis exports from this subscriber _last_, so that any prediction tasks
+// will complete prior to the coverage model being called. This allows coverage
+// to be computed on the updated current state of the system, with reference
+// to expected changes.
+//
+//------------------------------------------------------------------------------
+
+class soc_ifc_env_cov_subscriber #(
+  type PRED_T = soc_ifc_predictor,
+  type CONFIG_T,
+  type BASE_T = uvm_component
+  )
+ extends BASE_T;
+
+  typedef soc_ifc_env_cov_subscriber #( PRED_T, CONFIG_T, BASE_T) this_type;
+
+  // Factory registration of this class
+  `uvm_component_param_utils( this_type )
+
+  PRED_T pred;
+  CONFIG_T configuration;
+  soc_ifc_reg_model_top c_soc_ifc_rm;
+
+
+  //------------------------------------------------------------------------------------------
+  //                                   Coverage Signals
+  //------------------------------------------------------------------------------------------
+  mbox_steps_by_if_s prev_step_sampled = '{is_ahb: NOT_AHB_REQ, step:{null_action: 1'b1, default: 1'b0}};
+
+
+  //------------------------------------------------------------------------------------------
+  //                                   Covergroups
+  //------------------------------------------------------------------------------------------
+  covergroup soc_ifc_env_mbox_steps_cg with function sample (input bit is_ahb, input mbox_steps_s next_step);
+    option.per_instance = 1;
+    step_lock_acquire   : coverpoint (next_step.lock_acquire);
+    step_cmd_wr         : coverpoint (next_step.cmd_wr);
+    step_dlen_wr        : coverpoint (next_step.dlen_wr);
+    step_datain_wr      : coverpoint (next_step.datain_wr);
+    step_exec_set       : coverpoint (next_step.exec_set);
+    step_cmd_rd         : coverpoint (next_step.cmd_rd);
+    step_dlen_rd        : coverpoint (next_step.dlen_rd);
+    step_dataout_rd     : coverpoint (next_step.dataout_rd);
+    step_resp_datain_wr : coverpoint (next_step.resp_datain_wr);
+    step_resp_dlen_wr   : coverpoint (next_step.resp_dlen_wr);
+    step_resp_dlen_rd   : coverpoint (next_step.resp_dlen_rd);
+    step_resp_dataout_rd: coverpoint (next_step.resp_dataout_rd);
+    step_status_wr      : coverpoint (next_step.status_wr);
+    step_status_rd      : coverpoint (next_step.status_rd);
+    step_exec_clr       : coverpoint (next_step.exec_clr);
+    step_force_unlock   : coverpoint (next_step.force_unlock);
+    step_reset          : coverpoint (next_step.reset);
+    /*
+    *steps_all_mbox_flow : coverpoint (next_step) {
+    *    bins mbox_flow = (MBOX_STEP_LOCK_ACQUIRE            =>
+    *                      MBOX_STEP_CMD_WR         [=1]     =>
+    *                      MBOX_STEP_DLEN_WR        [=1]     =>
+    *                      MBOX_STEP_DATAIN_WR      [=1:511] =>
+    *                      MBOX_STEP_EXEC_SET       [=1]     =>
+    *                      MBOX_STEP_CMD_RD         [=1]     =>
+    *                      MBOX_STEP_DLEN_RD        [=1]     =>
+    *                      MBOX_STEP_DATAOUT_RD     [=1:511] =>
+    *                      MBOX_STEP_STATUS_WR      [=1]     =>
+    *                      MBOX_STEP_STATUS_RD      [=1:511] =>
+    *                      MBOX_STEP_EXEC_CLR);
+    *    bins mbox_resp_flow = (MBOX_STEP_LOCK_ACQUIRE                                                       =>
+    *                           MBOX_STEP_CMD_WR                                                    [=1]     =>
+    *                           MBOX_STEP_DLEN_WR                                                   [=1]     =>
+    *                           MBOX_STEP_DATAIN_WR                                                 [=1:511] =>
+    *                           MBOX_STEP_EXEC_SET                                                  [=1]     =>
+    *                           MBOX_STEP_CMD_RD                                                    [=1]     =>
+    *                           MBOX_STEP_DLEN_RD                                                   [=1]     =>
+    *                           MBOX_STEP_DATAOUT_RD                                                [=1:511] =>
+    *                           MBOX_STEP_RESP_DATAIN_WR,MBOX_STEP_RESP_DLEN_WR                     [=2:511] =>
+    *                           MBOX_STEP_STATUS_WR                                                 [=1]     =>
+    *                           MBOX_STEP_RESP_DLEN_RD,MBOX_STEP_RESP_DATAOUT_RD,MBOX_STEP_STATUS_RD[=3:511] =>
+    *                           MBOX_STEP_EXEC_CLR);
+    *}
+    */
+    which_lock_acquire   : cross step_lock_acquire   , is_ahb;
+    which_cmd_wr         : cross step_cmd_wr         , is_ahb;
+    which_dlen_wr        : cross step_dlen_wr        , is_ahb;
+    which_datain_wr      : cross step_datain_wr      , is_ahb;
+    which_exec_set       : cross step_exec_set       , is_ahb;
+    which_cmd_rd         : cross step_cmd_rd         , is_ahb;
+    which_dlen_rd        : cross step_dlen_rd        , is_ahb;
+    which_dataout_rd     : cross step_dataout_rd     , is_ahb;
+    which_resp_datain_wr : cross step_resp_datain_wr , is_ahb { ignore_bins ignore_apb = binsof(is_ahb) intersect {1'b0}; }
+    which_resp_dlen_wr   : cross step_resp_dlen_wr   , is_ahb { ignore_bins ignore_apb = binsof(is_ahb) intersect {1'b0}; }
+    which_resp_dlen_rd   : cross step_resp_dlen_rd   , is_ahb { ignore_bins ignore_ahb = binsof(is_ahb) intersect {1'b1}; }
+    which_resp_dataout_rd: cross step_resp_dataout_rd, is_ahb { ignore_bins ignore_ahb = binsof(is_ahb) intersect {1'b1}; }
+    which_status_wr      : cross step_status_wr      , is_ahb;
+    which_status_rd      : cross step_status_rd      , is_ahb;
+    which_exec_clr       : cross step_exec_clr       , is_ahb;
+    which_force_unlock   : cross step_force_unlock   , is_ahb { ignore_bins ignore_apb = binsof(is_ahb) intersect {1'b0}; }
+  endgroup
+
+  covergroup soc_ifc_env_mbox_scenarios_cg with function sample (mbox_steps_by_if_s step_by_if);
+    option.per_instance = 1;
+    mbox_steps_by_if : coverpoint (step_by_if) {
+        bins step_lock_acquire_ahb    = {{    AHB_REQ,MBOX_STEP_LOCK_ACQUIRE}};
+        bins step_cmd_wr_ahb          = {{    AHB_REQ,MBOX_STEP_CMD_WR}};
+        bins step_dlen_wr_ahb         = {{    AHB_REQ,MBOX_STEP_DLEN_WR}};
+        bins step_datain_wr_ahb       = {{    AHB_REQ,MBOX_STEP_DATAIN_WR}};
+        bins step_exec_set_ahb        = {{    AHB_REQ,MBOX_STEP_EXEC_SET}};
+        bins step_cmd_rd_ahb          = {{    AHB_REQ,MBOX_STEP_CMD_RD}};
+        bins step_dlen_rd_ahb         = {{    AHB_REQ,MBOX_STEP_DLEN_RD}};
+        bins step_dataout_rd_ahb      = {{    AHB_REQ,MBOX_STEP_DATAOUT_RD}};
+        bins step_resp_datain_wr_ahb  = {{    AHB_REQ,MBOX_STEP_RESP_DATAIN_WR}};
+        bins step_resp_dlen_wr_ahb    = {{    AHB_REQ,MBOX_STEP_RESP_DLEN_WR}};
+        bins step_status_wr_ahb       = {{    AHB_REQ,MBOX_STEP_STATUS_WR}};
+        bins step_status_rd_ahb       = {{    AHB_REQ,MBOX_STEP_STATUS_RD}};
+        bins step_exec_clr_ahb        = {{    AHB_REQ,MBOX_STEP_EXEC_CLR}};
+        bins step_force_unlock_ahb    = {{    AHB_REQ,MBOX_STEP_FORCE_UNLOCK}};
+        bins step_lock_acquire_apb    = {{NOT_AHB_REQ,MBOX_STEP_LOCK_ACQUIRE}};
+        bins step_cmd_wr_apb          = {{NOT_AHB_REQ,MBOX_STEP_CMD_WR}};
+        bins step_dlen_wr_apb         = {{NOT_AHB_REQ,MBOX_STEP_DLEN_WR}};
+        bins step_datain_wr_apb       = {{NOT_AHB_REQ,MBOX_STEP_DATAIN_WR}};
+        bins step_exec_set_apb        = {{NOT_AHB_REQ,MBOX_STEP_EXEC_SET}};
+        bins step_cmd_rd_apb          = {{NOT_AHB_REQ,MBOX_STEP_CMD_RD}};
+        bins step_dlen_rd_apb         = {{NOT_AHB_REQ,MBOX_STEP_DLEN_RD}};
+        bins step_dataout_rd_apb      = {{NOT_AHB_REQ,MBOX_STEP_DATAOUT_RD}};
+        bins step_resp_dlen_rd_apb    = {{NOT_AHB_REQ,MBOX_STEP_RESP_DLEN_RD}};
+        bins step_resp_dataout_rd_apb = {{NOT_AHB_REQ,MBOX_STEP_RESP_DATAOUT_RD}};
+        bins step_status_wr_apb       = {{NOT_AHB_REQ,MBOX_STEP_STATUS_WR}};
+        bins step_status_rd_apb       = {{NOT_AHB_REQ,MBOX_STEP_STATUS_RD}};
+        bins step_exec_clr_apb        = {{NOT_AHB_REQ,MBOX_STEP_EXEC_CLR}};
+        bins step_reset               = {{NOT_AHB_REQ,MBOX_STEP_RESET}};
+    }
+    /*
+    *mbox_flow_by_if : coverpoint (step_by_if) {
+    *    bins uc_to_soc_flow = (
+    *        {    AHB_REQ,MBOX_STEP_LOCK_ACQUIRE}          =>
+    *        {    AHB_REQ,MBOX_STEP_CMD_WR      } [=1]     =>
+    *        {    AHB_REQ,MBOX_STEP_DLEN_WR     } [=1]     =>
+    *        {    AHB_REQ,MBOX_STEP_DATAIN_WR   } [=1:511] =>
+    *        {    AHB_REQ,MBOX_STEP_EXEC_SET    } [=1]     =>
+    *        {NOT_AHB_REQ,MBOX_STEP_CMD_RD      } [=1]     =>
+    *        {NOT_AHB_REQ,MBOX_STEP_DLEN_RD     } [=1]     =>
+    *        {NOT_AHB_REQ,MBOX_STEP_DATAOUT_RD  } [=1:511] =>
+    *        {NOT_AHB_REQ,MBOX_STEP_STATUS_WR   } [=1]     =>
+    *        {    AHB_REQ,MBOX_STEP_STATUS_RD   } [=1:511] =>
+    *        {    AHB_REQ,MBOX_STEP_EXEC_CLR    });
+    *    bins soc_to_uc_flow = (
+    *        {NOT_AHB_REQ,MBOX_STEP_LOCK_ACQUIRE}                                                                                    =>
+    *        {NOT_AHB_REQ,MBOX_STEP_CMD_WR      }                                                                           [=1]     =>
+    *        {NOT_AHB_REQ,MBOX_STEP_DLEN_WR     }                                                                           [=1]     =>
+    *        {NOT_AHB_REQ,MBOX_STEP_DATAIN_WR   }                                                                           [=1:511] =>
+    *        {NOT_AHB_REQ,MBOX_STEP_EXEC_SET    }                                                                           [=1]     =>
+    *        {    AHB_REQ,MBOX_STEP_CMD_RD      }                                                                           [=1]     =>
+    *        {    AHB_REQ,MBOX_STEP_DLEN_RD     }                                                                           [=1]     =>
+    *        {    AHB_REQ,MBOX_STEP_DATAOUT_RD  }                                                                           [=1:511] =>
+    *        {    AHB_REQ,MBOX_STEP_RESP_DATAIN_WR},{AHB_REQ,MBOX_STEP_RESP_DLEN_WR}                                        [=2:511] =>
+    *        {    AHB_REQ,MBOX_STEP_STATUS_WR   }                                                                           [=1]     =>
+    *        {NOT_AHB_REQ,MBOX_STEP_RESP_DLEN_RD},{NOT_AHB_REQ,MBOX_STEP_RESP_DATAOUT_RD},{NOT_AHB_REQ,MBOX_STEP_STATUS_RD} [=3:511] =>
+    *        {NOT_AHB_REQ,MBOX_STEP_EXEC_CLR    });
+    *}
+    *mbox_flow_uc_to_soc_with_rst_by_if : coverpoint (step_by_if) {
+    *    bins uc_to_soc_rst_after_lock  = (
+    *        {    AHB_REQ,MBOX_STEP_LOCK_ACQUIRE}          =>
+    *        {NOT_AHB_REQ,MBOX_STEP_RESET       });
+    *    bins uc_to_soc_rst_after_cmd = (
+    *        {    AHB_REQ,MBOX_STEP_LOCK_ACQUIRE}          =>
+    *        {    AHB_REQ,MBOX_STEP_CMD_WR      } [->1]    =>
+    *        {NOT_AHB_REQ,MBOX_STEP_RESET       });
+    *    bins uc_to_soc_rst_after_dlen = (
+    *        {    AHB_REQ,MBOX_STEP_LOCK_ACQUIRE}          =>
+    *        {    AHB_REQ,MBOX_STEP_CMD_WR      } [=1]     =>
+    *        {    AHB_REQ,MBOX_STEP_DLEN_WR     } [->1]    =>
+    *        {NOT_AHB_REQ,MBOX_STEP_RESET       });
+    *    bins uc_to_soc_rst_after_datain = (
+    *        {    AHB_REQ,MBOX_STEP_LOCK_ACQUIRE}           =>
+    *        {    AHB_REQ,MBOX_STEP_CMD_WR      } [=1]      =>
+    *        {    AHB_REQ,MBOX_STEP_DLEN_WR     } [=1]      =>
+    *        {    AHB_REQ,MBOX_STEP_DATAIN_WR   } [->1:511] =>
+    *        {NOT_AHB_REQ,MBOX_STEP_RESET       });
+    *    bins uc_to_soc_rst_after_exec_set = (
+    *        {    AHB_REQ,MBOX_STEP_LOCK_ACQUIRE}          =>
+    *        {    AHB_REQ,MBOX_STEP_CMD_WR      } [=1]     =>
+    *        {    AHB_REQ,MBOX_STEP_DLEN_WR     } [=1]     =>
+    *        {    AHB_REQ,MBOX_STEP_DATAIN_WR   } [=1:511] =>
+    *        {    AHB_REQ,MBOX_STEP_EXEC_SET    } [->1]    =>
+    *        {NOT_AHB_REQ,MBOX_STEP_RESET       });
+    *    bins uc_to_soc_rst_after_cmd_rd = (
+    *        {    AHB_REQ,MBOX_STEP_LOCK_ACQUIRE}          =>
+    *        {    AHB_REQ,MBOX_STEP_CMD_WR      } [=1]     =>
+    *        {    AHB_REQ,MBOX_STEP_DLEN_WR     } [=1]     =>
+    *        {    AHB_REQ,MBOX_STEP_DATAIN_WR   } [=1:511] =>
+    *        {    AHB_REQ,MBOX_STEP_EXEC_SET    } [=1]     =>
+    *        {NOT_AHB_REQ,MBOX_STEP_CMD_RD      } [->1]    =>
+    *        {NOT_AHB_REQ,MBOX_STEP_RESET       });
+    *    bins uc_to_soc_rst_after_dlen_rd = (
+    *        {    AHB_REQ,MBOX_STEP_LOCK_ACQUIRE}          =>
+    *        {    AHB_REQ,MBOX_STEP_CMD_WR      } [=1]     =>
+    *        {    AHB_REQ,MBOX_STEP_DLEN_WR     } [=1]     =>
+    *        {    AHB_REQ,MBOX_STEP_DATAIN_WR   } [=1:511] =>
+    *        {    AHB_REQ,MBOX_STEP_EXEC_SET    } [=1]     =>
+    *        {NOT_AHB_REQ,MBOX_STEP_CMD_RD      } [=1]     =>
+    *        {NOT_AHB_REQ,MBOX_STEP_DLEN_RD     } [->1]    =>
+    *        {NOT_AHB_REQ,MBOX_STEP_RESET       });
+    *    bins uc_to_soc_rst_after_dataout_rd = (
+    *        {    AHB_REQ,MBOX_STEP_LOCK_ACQUIRE}           =>
+    *        {    AHB_REQ,MBOX_STEP_CMD_WR      } [=1]      =>
+    *        {    AHB_REQ,MBOX_STEP_DLEN_WR     } [=1]      =>
+    *        {    AHB_REQ,MBOX_STEP_DATAIN_WR   } [=1:511]  =>
+    *        {    AHB_REQ,MBOX_STEP_EXEC_SET    } [=1]      =>
+    *        {NOT_AHB_REQ,MBOX_STEP_CMD_RD      } [=1]      =>
+    *        {NOT_AHB_REQ,MBOX_STEP_DLEN_RD     } [=1]      =>
+    *        {NOT_AHB_REQ,MBOX_STEP_DATAOUT_RD  } [->1:511] =>
+    *        {NOT_AHB_REQ,MBOX_STEP_RESET       });
+    *    bins uc_to_soc_rst_after_status_wr = (
+    *        {    AHB_REQ,MBOX_STEP_LOCK_ACQUIRE}          =>
+    *        {    AHB_REQ,MBOX_STEP_CMD_WR      } [=1]     =>
+    *        {    AHB_REQ,MBOX_STEP_DLEN_WR     } [=1]     =>
+    *        {    AHB_REQ,MBOX_STEP_DATAIN_WR   } [=1:511] =>
+    *        {    AHB_REQ,MBOX_STEP_EXEC_SET    } [=1]     =>
+    *        {NOT_AHB_REQ,MBOX_STEP_CMD_RD      } [=1]     =>
+    *        {NOT_AHB_REQ,MBOX_STEP_DLEN_RD     } [=1]     =>
+    *        {NOT_AHB_REQ,MBOX_STEP_DATAOUT_RD  } [=1:511] =>
+    *        {NOT_AHB_REQ,MBOX_STEP_STATUS_WR   } [->1]    =>
+    *        {NOT_AHB_REQ,MBOX_STEP_RESET       });
+    *    bins uc_to_soc_rst_after_status_rd = (
+    *        {    AHB_REQ,MBOX_STEP_LOCK_ACQUIRE}           =>
+    *        {    AHB_REQ,MBOX_STEP_CMD_WR      } [=1]      =>
+    *        {    AHB_REQ,MBOX_STEP_DLEN_WR     } [=1]      =>
+    *        {    AHB_REQ,MBOX_STEP_DATAIN_WR   } [=1:511]  =>
+    *        {    AHB_REQ,MBOX_STEP_EXEC_SET    } [=1]      =>
+    *        {NOT_AHB_REQ,MBOX_STEP_CMD_RD      } [=1]      =>
+    *        {NOT_AHB_REQ,MBOX_STEP_DLEN_RD     } [=1]      =>
+    *        {NOT_AHB_REQ,MBOX_STEP_DATAOUT_RD  } [=1:511]  =>
+    *        {NOT_AHB_REQ,MBOX_STEP_STATUS_WR   } [=1]      =>
+    *        {    AHB_REQ,MBOX_STEP_STATUS_RD   } [->1:511] =>
+    *        {NOT_AHB_REQ,MBOX_STEP_RESET       });
+    *    bins uc_to_soc_rst_after_exec_clr = (
+    *        {    AHB_REQ,MBOX_STEP_LOCK_ACQUIRE}          =>
+    *        {    AHB_REQ,MBOX_STEP_CMD_WR      } [=1]     =>
+    *        {    AHB_REQ,MBOX_STEP_DLEN_WR     } [=1]     =>
+    *        {    AHB_REQ,MBOX_STEP_DATAIN_WR   } [=1:511] =>
+    *        {    AHB_REQ,MBOX_STEP_EXEC_SET    } [=1]     =>
+    *        {NOT_AHB_REQ,MBOX_STEP_CMD_RD      } [=1]     =>
+    *        {NOT_AHB_REQ,MBOX_STEP_DLEN_RD     } [=1]     =>
+    *        {NOT_AHB_REQ,MBOX_STEP_DATAOUT_RD  } [=1:511] =>
+    *        {NOT_AHB_REQ,MBOX_STEP_STATUS_WR   } [=1]     =>
+    *        {    AHB_REQ,MBOX_STEP_STATUS_RD   } [=1:511] =>
+    *        {    AHB_REQ,MBOX_STEP_EXEC_CLR    } [->1]    =>
+    *        {NOT_AHB_REQ,MBOX_STEP_RESET       });
+    *}
+    *mbox_flow_soc_to_uc_with_rst_by_if : coverpoint (step_by_if) {
+    *    bins soc_to_uc_rst_after_lock = (
+    *        {NOT_AHB_REQ,MBOX_STEP_LOCK_ACQUIRE}                                                                                    =>
+    *        {NOT_AHB_REQ,MBOX_STEP_RESET       });
+    *    bins soc_to_uc_rst_after_cmd_wr = (
+    *        {NOT_AHB_REQ,MBOX_STEP_LOCK_ACQUIRE}                                                                                    =>
+    *        {NOT_AHB_REQ,MBOX_STEP_CMD_WR      }                                                                           [->1]    =>
+    *        {NOT_AHB_REQ,MBOX_STEP_RESET       });
+    *    bins soc_to_uc_rst_after_dlen_wr = (
+    *        {NOT_AHB_REQ,MBOX_STEP_LOCK_ACQUIRE}                                                                                    =>
+    *        {NOT_AHB_REQ,MBOX_STEP_CMD_WR      }                                                                           [=1]     =>
+    *        {NOT_AHB_REQ,MBOX_STEP_DLEN_WR     }                                                                           [->1]    =>
+    *        {NOT_AHB_REQ,MBOX_STEP_RESET       });
+    *    bins soc_to_uc_rst_after_datain_wr = (
+    *        {NOT_AHB_REQ,MBOX_STEP_LOCK_ACQUIRE}                                                                                     =>
+    *        {NOT_AHB_REQ,MBOX_STEP_CMD_WR      }                                                                           [=1]      =>
+    *        {NOT_AHB_REQ,MBOX_STEP_DLEN_WR     }                                                                           [=1]      =>
+    *        {NOT_AHB_REQ,MBOX_STEP_DATAIN_WR   }                                                                           [->1:511] =>
+    *        {NOT_AHB_REQ,MBOX_STEP_RESET       });
+    *    bins soc_to_uc_rst_after_exec_set = (
+    *        {NOT_AHB_REQ,MBOX_STEP_LOCK_ACQUIRE}                                                                                    =>
+    *        {NOT_AHB_REQ,MBOX_STEP_CMD_WR      }                                                                           [=1]     =>
+    *        {NOT_AHB_REQ,MBOX_STEP_DLEN_WR     }                                                                           [=1]     =>
+    *        {NOT_AHB_REQ,MBOX_STEP_DATAIN_WR   }                                                                           [=1:511] =>
+    *        {NOT_AHB_REQ,MBOX_STEP_EXEC_SET    }                                                                           [->1]    =>
+    *        {NOT_AHB_REQ,MBOX_STEP_RESET       });
+    *    bins soc_to_uc_rst_after_cmd_rd = (
+    *        {NOT_AHB_REQ,MBOX_STEP_LOCK_ACQUIRE}                                                                                    =>
+    *        {NOT_AHB_REQ,MBOX_STEP_CMD_WR      }                                                                           [=1]     =>
+    *        {NOT_AHB_REQ,MBOX_STEP_DLEN_WR     }                                                                           [=1]     =>
+    *        {NOT_AHB_REQ,MBOX_STEP_DATAIN_WR   }                                                                           [=1:511] =>
+    *        {NOT_AHB_REQ,MBOX_STEP_EXEC_SET    }                                                                           [=1]     =>
+    *        {    AHB_REQ,MBOX_STEP_CMD_RD      }                                                                           [->1]    =>
+    *        {NOT_AHB_REQ,MBOX_STEP_RESET       });
+    *    bins soc_to_uc_rst_after_dlen_rd = (
+    *        {NOT_AHB_REQ,MBOX_STEP_LOCK_ACQUIRE}                                                                                    =>
+    *        {NOT_AHB_REQ,MBOX_STEP_CMD_WR      }                                                                           [=1]     =>
+    *        {NOT_AHB_REQ,MBOX_STEP_DLEN_WR     }                                                                           [=1]     =>
+    *        {NOT_AHB_REQ,MBOX_STEP_DATAIN_WR   }                                                                           [=1:511] =>
+    *        {NOT_AHB_REQ,MBOX_STEP_EXEC_SET    }                                                                           [=1]     =>
+    *        {    AHB_REQ,MBOX_STEP_CMD_RD      }                                                                           [=1]     =>
+    *        {    AHB_REQ,MBOX_STEP_DLEN_RD     }                                                                           [->1]    =>
+    *        {NOT_AHB_REQ,MBOX_STEP_RESET       });
+    *    bins soc_to_uc_rst_after_dataout_rd = (
+    *        {NOT_AHB_REQ,MBOX_STEP_LOCK_ACQUIRE}                                                                                     =>
+    *        {NOT_AHB_REQ,MBOX_STEP_CMD_WR      }                                                                           [=1]      =>
+    *        {NOT_AHB_REQ,MBOX_STEP_DLEN_WR     }                                                                           [=1]      =>
+    *        {NOT_AHB_REQ,MBOX_STEP_DATAIN_WR   }                                                                           [=1:511]  =>
+    *        {NOT_AHB_REQ,MBOX_STEP_EXEC_SET    }                                                                           [=1]      =>
+    *        {    AHB_REQ,MBOX_STEP_CMD_RD      }                                                                           [=1]      =>
+    *        {    AHB_REQ,MBOX_STEP_DLEN_RD     }                                                                           [=1]      =>
+    *        {    AHB_REQ,MBOX_STEP_DATAOUT_RD  }                                                                           [->1:511] =>
+    *        {NOT_AHB_REQ,MBOX_STEP_RESET       });
+    *    bins soc_to_uc_rst_after_resp_dlen_wr = (
+    *        {NOT_AHB_REQ,MBOX_STEP_LOCK_ACQUIRE}                                                                                     =>
+    *        {NOT_AHB_REQ,MBOX_STEP_CMD_WR      }                                                                           [=1]      =>
+    *        {NOT_AHB_REQ,MBOX_STEP_DLEN_WR     }                                                                           [=1]      =>
+    *        {NOT_AHB_REQ,MBOX_STEP_DATAIN_WR   }                                                                           [=1:511]  =>
+    *        {NOT_AHB_REQ,MBOX_STEP_EXEC_SET    }                                                                           [=1]      =>
+    *        {    AHB_REQ,MBOX_STEP_CMD_RD      }                                                                           [=1]      =>
+    *        {    AHB_REQ,MBOX_STEP_DLEN_RD     }                                                                           [=1]      =>
+    *        {    AHB_REQ,MBOX_STEP_DATAOUT_RD  }                                                                           [=1:511]  =>
+    *        {    AHB_REQ,MBOX_STEP_RESP_DATAIN_WR},{AHB_REQ,MBOX_STEP_RESP_DLEN_WR}                                        [->2:511] =>
+    *        {NOT_AHB_REQ,MBOX_STEP_RESET       });
+    *    bins soc_to_uc_rst_after_status_wr = (
+    *        {NOT_AHB_REQ,MBOX_STEP_LOCK_ACQUIRE}                                                                                     =>
+    *        {NOT_AHB_REQ,MBOX_STEP_CMD_WR      }                                                                           [=1]      =>
+    *        {NOT_AHB_REQ,MBOX_STEP_DLEN_WR     }                                                                           [=1]      =>
+    *        {NOT_AHB_REQ,MBOX_STEP_DATAIN_WR   }                                                                           [=1:511]  =>
+    *        {NOT_AHB_REQ,MBOX_STEP_EXEC_SET    }                                                                           [=1]      =>
+    *        {    AHB_REQ,MBOX_STEP_CMD_RD      }                                                                           [=1]      =>
+    *        {    AHB_REQ,MBOX_STEP_DLEN_RD     }                                                                           [=1]      =>
+    *        {    AHB_REQ,MBOX_STEP_DATAOUT_RD  }                                                                           [=1:511]  =>
+    *        {    AHB_REQ,MBOX_STEP_RESP_DATAIN_WR},{AHB_REQ,MBOX_STEP_RESP_DLEN_WR}                                        [=2:511]  =>
+    *        {    AHB_REQ,MBOX_STEP_STATUS_WR   }                                                                           [->1]     =>
+    *        {NOT_AHB_REQ,MBOX_STEP_RESET       });
+    *    bins soc_to_uc_rst_after_status_rd = (
+    *        {NOT_AHB_REQ,MBOX_STEP_LOCK_ACQUIRE}                                                                                     =>
+    *        {NOT_AHB_REQ,MBOX_STEP_CMD_WR      }                                                                           [=1]      =>
+    *        {NOT_AHB_REQ,MBOX_STEP_DLEN_WR     }                                                                           [=1]      =>
+    *        {NOT_AHB_REQ,MBOX_STEP_DATAIN_WR   }                                                                           [=1:511]  =>
+    *        {NOT_AHB_REQ,MBOX_STEP_EXEC_SET    }                                                                           [=1]      =>
+    *        {    AHB_REQ,MBOX_STEP_CMD_RD      }                                                                           [=1]      =>
+    *        {    AHB_REQ,MBOX_STEP_DLEN_RD     }                                                                           [=1]      =>
+    *        {    AHB_REQ,MBOX_STEP_DATAOUT_RD  }                                                                           [=1:511]  =>
+    *        {    AHB_REQ,MBOX_STEP_RESP_DATAIN_WR},{AHB_REQ,MBOX_STEP_RESP_DLEN_WR}                                        [=2:511]  =>
+    *        {    AHB_REQ,MBOX_STEP_STATUS_WR   }                                                                           [=1]      =>
+    *        {NOT_AHB_REQ,MBOX_STEP_RESP_DLEN_RD},{NOT_AHB_REQ,MBOX_STEP_RESP_DATAOUT_RD},{NOT_AHB_REQ,MBOX_STEP_STATUS_RD} [->3:511] =>
+    *        {NOT_AHB_REQ,MBOX_STEP_RESET       });
+    *    bins soc_to_uc_rst_after_exec_clr = (
+    *        {NOT_AHB_REQ,MBOX_STEP_LOCK_ACQUIRE}                                                                                    =>
+    *        {NOT_AHB_REQ,MBOX_STEP_CMD_WR      }                                                                           [=1]     =>
+    *        {NOT_AHB_REQ,MBOX_STEP_DLEN_WR     }                                                                           [=1]     =>
+    *        {NOT_AHB_REQ,MBOX_STEP_DATAIN_WR   }                                                                           [=1:511] =>
+    *        {NOT_AHB_REQ,MBOX_STEP_EXEC_SET    }                                                                           [=1]     =>
+    *        {    AHB_REQ,MBOX_STEP_CMD_RD      }                                                                           [=1]     =>
+    *        {    AHB_REQ,MBOX_STEP_DLEN_RD     }                                                                           [=1]     =>
+    *        {    AHB_REQ,MBOX_STEP_DATAOUT_RD  }                                                                           [=1:511] =>
+    *        {    AHB_REQ,MBOX_STEP_RESP_DATAIN_WR},{AHB_REQ,MBOX_STEP_RESP_DLEN_WR}                                        [=2:511] =>
+    *        {    AHB_REQ,MBOX_STEP_STATUS_WR   }                                                                           [=1]     =>
+    *        {NOT_AHB_REQ,MBOX_STEP_RESP_DLEN_RD},{NOT_AHB_REQ,MBOX_STEP_RESP_DATAOUT_RD},{NOT_AHB_REQ,MBOX_STEP_STATUS_RD} [=3:511] =>
+    *        {NOT_AHB_REQ,MBOX_STEP_EXEC_CLR    }                                                                           [->1]    =>
+    *        {NOT_AHB_REQ,MBOX_STEP_RESET       });
+    *}
+    */
+  endgroup
+  /* TODO:
+  * covergroup soc_ifc_env_resets;
+  * covergroup soc_ifc_env_trng; // Incl. TRNG PAUSER cases
+  * covergroup soc_ifc_env_pauser;
+  * covergroup soc_ifc_env_iccm_lock;
+  * covergroup soc_ifc_env_wdt;
+  * covergroup soc_ifc_env_mtime;
+  * covergroup soc_ifc_env_fuses; // Writes, resets, blocked writes
+  * covergroup soc_ifc_env_errors; // E.g. NMI, MBOX PROT, ECC
+  * covergroup soc_ifc_env_interrupts;
+  * covergroup soc_ifc_env_boot;
+  * covergroup soc_ifc_env_security_state;
+  * covergroup soc_ifc_env_clk_gate;
+  * covergroup soc_ifc_env_sha_accel;
+  * covergroup soc_ifc_env_ahb_apb_arb; // Cover access contention
+  */
+
+
+  //------------------------------------------------------------------------------------------
+  //                                   Member Variables
+  //------------------------------------------------------------------------------------------
+  typedef ahb_master_burst_transfer #(ahb_lite_slave_0_params::AHB_NUM_MASTERS,
+                                      ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS,
+                                      ahb_lite_slave_0_params::AHB_NUM_SLAVES,
+                                      ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH,
+                                      ahb_lite_slave_0_params::AHB_WDATA_WIDTH,
+                                      ahb_lite_slave_0_params::AHB_RDATA_WIDTH) ahb_transaction_t;
+  typedef apb3_host_apb3_transaction #(apb5_master_0_params::APB3_SLAVE_COUNT,
+                                       apb5_master_0_params::APB3_PADDR_BIT_WIDTH,
+                                       apb5_master_0_params::APB3_PWDATA_BIT_WIDTH,
+                                       apb5_master_0_params::APB3_PRDATA_BIT_WIDTH) apb_transaction_t;
+
+  // Instantiate the analysis exports
+  uvm_analysis_imp_cov_soc_ifc_ctrl_ae   #(soc_ifc_ctrl_transaction,   this_type) soc_ifc_ctrl_ae;
+  uvm_analysis_imp_cov_soc_ifc_status_ae #(soc_ifc_status_transaction, this_type) soc_ifc_status_ae;
+  uvm_analysis_imp_cov_apb_ae            #(mvc_sequence_item_base,     this_type) apb_ae;
+  uvm_analysis_imp_cov_cptra_ctrl_ae     #(cptra_ctrl_transaction,     this_type) cptra_ctrl_ae;
+  uvm_analysis_imp_cov_cptra_status_ae   #(cptra_status_transaction,   this_type) cptra_status_ae;
+  uvm_analysis_imp_cov_ahb_ae            #(mvc_sequence_item_base,     this_type) ahb_ae;
+  uvm_analysis_imp_cov_mbox_sram_ae      #(mbox_sram_transaction,      this_type) mbox_sram_ae;
+
+  //------------------------------------------------------------------------------------------
+  //                                   Constructor
+  //------------------------------------------------------------------------------------------
+  function new (string name, uvm_component parent);
+    super.new(name, parent);
+    soc_ifc_env_mbox_steps_cg = new;
+    soc_ifc_env_mbox_scenarios_cg = new;
+  endfunction
+
+  //------------------------------------------------------------------------------------------
+  //                                   build_phase
+  //------------------------------------------------------------------------------------------
+  virtual function void build_phase (uvm_phase phase);
+    soc_ifc_ctrl_ae   = new("soc_ifc_ctrl_ae"  , this);
+    soc_ifc_status_ae = new("soc_ifc_status_ae", this);
+    apb_ae            = new("apb_ae"           , this);
+    cptra_ctrl_ae     = new("cptra_ctrl_ae"    , this);
+    cptra_status_ae   = new("cptra_status_ae"  , this);
+    ahb_ae            = new("ahb_ae"           , this);
+    mbox_sram_ae      = new("mbox_sram_ae"     , this);
+
+    c_soc_ifc_rm = configuration.soc_ifc_rm;
+    soc_ifc_env_mbox_steps_cg.set_inst_name($sformatf("soc_ifc_env_mbox_steps_cg_%s",get_full_name()));
+    soc_ifc_env_mbox_scenarios_cg.set_inst_name($sformatf("soc_ifc_env_mbox_scenarios_cg_%s",get_full_name()));
+  endfunction
+
+  //------------------------------------------------------------------------------------------
+  //                                   CPTRA CTRL - write
+  //------------------------------------------------------------------------------------------
+  virtual function void write_cov_cptra_ctrl_ae(cptra_ctrl_transaction txn);
+//    `uvm_fatal("FIXME", "FIXME")
+  endfunction
+
+  //------------------------------------------------------------------------------------------
+  //                                   CPTRA STATUS - write
+  //------------------------------------------------------------------------------------------
+  virtual function void write_cov_cptra_status_ae(cptra_status_transaction txn);
+//    `uvm_fatal("FIXME", "FIXME")
+  endfunction
+
+  //------------------------------------------------------------------------------------------
+  //                                   SOC_IFC CTRL - write
+  //------------------------------------------------------------------------------------------
+  virtual function void write_cov_soc_ifc_ctrl_ae(soc_ifc_ctrl_transaction txn);
+    `uvm_info("SOC_IFC_COV_SOC_IFC_CTRL", {"Collecting coverage on transaction: ", txn.convert2string()}, UVM_HIGH)
+    if (!txn.set_pwrgood || txn.assert_rst) begin
+        `uvm_info("SOC_IFC_COV_SOC_IFC_CTRL", $sformatf("Got next_step [%p]", pred.next_step), UVM_FULL)
+        soc_ifc_env_mbox_steps_cg.sample(.is_ahb(NOT_AHB_REQ), .next_step(pred.next_step));
+        soc_ifc_env_mbox_scenarios_cg.sample({NOT_AHB_REQ,pred.next_step});
+        prev_step_sampled = {is_ahb:NOT_AHB_REQ,step:pred.next_step};
+    end
+  endfunction
+
+  //------------------------------------------------------------------------------------------
+  //                                   SOC_IFC STATUS - write
+  //------------------------------------------------------------------------------------------
+  virtual function void write_cov_soc_ifc_status_ae(soc_ifc_status_transaction txn);
+//    `uvm_fatal("FIXME", "FIXME")
+  endfunction
+
+  //------------------------------------------------------------------------------------------
+  //                                   MBOX SRAM - write
+  //------------------------------------------------------------------------------------------
+  virtual function void write_cov_mbox_sram_ae(mbox_sram_transaction txn);
+//    `uvm_fatal("FIXME", "FIXME")
+  endfunction
+
+  //------------------------------------------------------------------------------------------
+  //                                   AHB - write
+  //------------------------------------------------------------------------------------------
+  virtual function void write_cov_ahb_ae(mvc_sequence_item_base txn);
+    ahb_transaction_t ahb_txn;
+    uvm_reg axs_reg;
+    uvm_mem axs_mem;
+
+    // Decode argument to access type
+    if (!$cast(ahb_txn,txn))
+        `uvm_fatal("SOC_IFC_ENV_COV", "AHB coverage analysis import received invalid transaction")
+    if (c_soc_ifc_rm.soc_ifc_AHB_map.get_mem_by_offset(ahb_txn.address) != null) begin: MEM_HANDLE
+        `uvm_info("SOC_IFC_COV_AHB", $sformatf("Detected access to mailbox at address: 0x%x", ahb_txn.address), UVM_HIGH)
+        axs_mem = c_soc_ifc_rm.soc_ifc_AHB_map.get_mem_by_offset(ahb_txn.address);
+    end: MEM_HANDLE
+    else begin: REG_HANDLE
+        axs_reg = c_soc_ifc_rm.soc_ifc_AHB_map.get_reg_by_offset(ahb_txn.address);
+        if (axs_reg == null) begin
+            `uvm_error("SOC_IFC_COV_AHB", $sformatf("AHB transaction to address: 0x%x decodes to null from soc_ifc_AHB_map", ahb_txn.address))
+        end
+    end: REG_HANDLE
+
+    // Calculate coverage impact from register access
+    if (axs_mem != null) begin: MEM_AXS
+        `uvm_info("SOC_IFC_COV_AHB", $sformatf("Not calculating any system coverage for access to mailbox at address: 0x%x", ahb_txn.address), UVM_FULL)
+    end// MEM_AXS
+    else if (axs_reg == null) begin
+        `uvm_error("SOC_IFC_COV_AHB", $sformatf("AHB transaction to address: 0x%x decodes to null from soc_ifc_AHB_map", ahb_txn.address))
+    end
+    else begin: REG_AXS
+        `uvm_info("SOC_IFC_COV_AHB", {"Collecting coverage on access to register: ", axs_reg.get_full_name()}, UVM_HIGH)
+        // Non-interrupt registers have 2-levels of ancestry back to reg_model top
+        if (axs_reg.get_parent().get_parent().get_name() == "soc_ifc_rm") begin
+            case (axs_reg.get_name()) inside
+                "mbox_lock",
+                "mbox_user",
+                "mbox_cmd",
+                "mbox_dlen",
+                "mbox_datain",
+                "mbox_dataout",
+                "mbox_execute",
+                "mbox_status",
+                "mbox_unlock": begin
+                    `uvm_info("SOC_IFC_COV_AHB", $sformatf("Got next_step [%p]", pred.next_step), UVM_FULL)
+                    // Skip coverage on repeated steps, as a memory optimization (large rep. operators are onerous)
+                    if (pred.next_step inside {MBOX_STEP_DATAIN_WR,
+                                               MBOX_STEP_DATAOUT_RD,
+                                               MBOX_STEP_STATUS_RD,
+                                               MBOX_STEP_RESP_DATAIN_WR,
+                                               MBOX_STEP_RESP_DATAOUT_RD/*shouldn't happen*/} &&
+                        pred.next_step == prev_step_sampled.step &&
+                        prev_step_sampled.is_ahb) begin
+                        `uvm_info("SOC_IFC_COV_AHB", "Skipping sample for step [%p] as it is a repetition", UVM_DEBUG)
+                    end
+                    else begin
+                        soc_ifc_env_mbox_steps_cg.sample(.is_ahb(AHB_REQ), .next_step(pred.next_step));
+                        soc_ifc_env_mbox_scenarios_cg.sample({AHB_REQ,pred.next_step});
+                        prev_step_sampled = '{is_ahb:AHB_REQ, step:pred.next_step};
+                    end
+                end
+            endcase
+        end
+    end
+  endfunction
+
+  //------------------------------------------------------------------------------------------
+  //                                   APB - write
+  //------------------------------------------------------------------------------------------
+  virtual function void write_cov_apb_ae(mvc_sequence_item_base txn);
+    apb_transaction_t apb_txn;
+    uvm_reg           axs_reg;
+
+    // Extract info
+    if (!$cast(apb_txn,txn)) `uvm_fatal("SOC_IFC_COV_APB", "APB coverage analysis import received invalid transaction")
+    axs_reg = c_soc_ifc_rm.soc_ifc_APB_map.get_reg_by_offset(apb_txn.addr);
+
+    // Calculate coverage impact from register access
+    if (axs_reg == null) begin
+        `uvm_error("SOC_IFC_COV_APB", $sformatf("APB transaction to address: 0x%x decodes to null from soc_ifc_APB_map", apb_txn.addr))
+    end
+    else begin: REG_AXS
+        `uvm_info("SOC_IFC_COV_APB", {"Collecting coverage on access to register: ", axs_reg.get_full_name()}, UVM_HIGH)
+        case (axs_reg.get_name()) inside
+            "mbox_lock",
+            "mbox_user",
+            "mbox_cmd",
+            "mbox_dlen",
+            "mbox_datain",
+            "mbox_dataout",
+            "mbox_execute",
+            "mbox_status",
+            "mbox_unlock": begin
+                `uvm_info("SOC_IFC_COV_APB", $sformatf("Got next_step [%p]", pred.next_step), UVM_FULL)
+                // Skip coverage on repeated steps, as a memory optimization (large rep. operators are onerous)
+                if (pred.next_step inside {MBOX_STEP_DATAIN_WR,
+                                           MBOX_STEP_DATAOUT_RD,
+                                           MBOX_STEP_STATUS_RD,
+                                           MBOX_STEP_RESP_DATAIN_WR/*shouldn't happen*/,
+                                           MBOX_STEP_RESP_DATAOUT_RD} &&
+                    pred.next_step == prev_step_sampled.step &&
+                    !prev_step_sampled.is_ahb) begin
+                    `uvm_info("SOC_IFC_COV_APB", "Skipping sample for step [%p] as it is a repetition", UVM_DEBUG)
+                end
+                else begin
+                    soc_ifc_env_mbox_steps_cg.sample(.is_ahb(NOT_AHB_REQ), .next_step(pred.next_step));
+                    soc_ifc_env_mbox_scenarios_cg.sample({NOT_AHB_REQ,pred.next_step});
+                    prev_step_sampled = '{is_ahb: NOT_AHB_REQ, step:pred.next_step};
+                end
+            end
+        endcase
+    end
+  endfunction
+  
+endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_env_sequence_base.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_env_sequence_base.svh
index 3a7ba5eb4..1cb88c7da 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_env_sequence_base.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_env_sequence_base.svh
@@ -55,6 +55,7 @@ class soc_ifc_env_sequence_base #(
   // Responder agent sequencers in soc_ifc_environment:
     // configuration.soc_ifc_status_agent_config.sequencer
     // configuration.cptra_status_agent_config.sequencer
+    // configuration.mbox_sram_agent_config.sequencer
 
 
     typedef soc_ifc_ctrl_random_sequence soc_ifc_ctrl_agent_random_sequence_t;
@@ -76,6 +77,18 @@ class soc_ifc_env_sequence_base #(
     `uvm_info(this.get_type_name(), "In: pre_start() for sequence", UVM_NONE)
   endtask
 
+  virtual function get_mbox_sram_ecc_error_injection();
+    return this.configuration.mbox_sram_agent_config.inject_ecc_error;
+  endfunction
+  virtual function set_mbox_sram_ecc_single_error_injection();
+    this.configuration.mbox_sram_agent_config.inject_ecc_error |= 2'b01;
+  endfunction
+  virtual function set_mbox_sram_ecc_double_error_injection();
+    this.configuration.mbox_sram_agent_config.inject_ecc_error |= 2'b10;
+  endfunction
+  virtual function clr_mbox_sram_ecc_error_injection();
+    this.configuration.mbox_sram_agent_config.inject_ecc_error = 2'b00;
+  endfunction
   // pragma uvmf custom class_item_additional end
   
   function new(string name = "" );
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_env_typedefs.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_env_typedefs.svh
index 3fb908c12..bcc8dd5d8 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_env_typedefs.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_env_typedefs.svh
@@ -45,14 +45,17 @@
    *   [29]: uC->SoC command
    */
   typedef enum logic [31:0] {
+      MBOX_CMD_DIR_RD     = 32'h01000000,
       MBOX_CMD_UC_BASIC   = 32'h20000000,
+      MBOX_CMD_UC_OVERRUN = 32'h20000001,
       MBOX_CMD_RESP_BASIC = 32'h40000000,
       MBOX_CMD_REG_ACCESS = 32'h40000001,
       MBOX_CMD_OOB_ACCESS = 32'h40000002,
       MBOX_CMD_FMC_UPDATE = 32'hba5eba11,
       MBOX_CMD_RT_UPDATE  = 32'hbabecafe,
       MBOX_CMD_SHA384_REQ = 32'h40C0FFEE,
-      MBOX_CMD_SHA512_REQ = 32'h41C0FFEE
+      MBOX_CMD_SHA512_REQ = 32'h41C0FFEE,
+      MBOX_CMD_ROM_FW_UPD = 32'h46574C44
   } mbox_cmd_e;
   
   typedef union packed {
@@ -75,5 +78,50 @@
     logic sha512_mode;
   } sha_accel_op_s;
 
+  typedef struct packed {
+      bit null_action; /* no-effect reads or writes to mbox regs, or resets when mbox is idle */
+      bit lock_acquire;
+      bit cmd_wr;
+      bit dlen_wr;
+      bit datain_wr;
+      bit exec_set;
+      bit cmd_rd;
+      bit dlen_rd;
+      bit dataout_rd;
+      bit resp_datain_wr;
+      bit resp_dlen_wr;
+      bit resp_dlen_rd;
+      bit resp_dataout_rd;
+      bit status_wr;
+      bit status_rd;
+      bit exec_clr;
+      bit force_unlock;
+      bit reset; /* should be triggered by a soc_ifc_ctrl transaction to indicate that an _active_ mailbox flow was interrupted by reset */
+  } mbox_steps_s;
+  localparam mbox_steps_s MBOX_STEP_NULL_ACTION     = '{null_action    : 1'b1, default: 1'b0};
+  localparam mbox_steps_s MBOX_STEP_LOCK_ACQUIRE    = '{lock_acquire   : 1'b1, default: 1'b0};
+  localparam mbox_steps_s MBOX_STEP_CMD_WR          = '{cmd_wr         : 1'b1, default: 1'b0};
+  localparam mbox_steps_s MBOX_STEP_DLEN_WR         = '{dlen_wr        : 1'b1, default: 1'b0};
+  localparam mbox_steps_s MBOX_STEP_DATAIN_WR       = '{datain_wr      : 1'b1, default: 1'b0};
+  localparam mbox_steps_s MBOX_STEP_EXEC_SET        = '{exec_set       : 1'b1, default: 1'b0};
+  localparam mbox_steps_s MBOX_STEP_CMD_RD          = '{cmd_rd         : 1'b1, default: 1'b0};
+  localparam mbox_steps_s MBOX_STEP_DLEN_RD         = '{dlen_rd        : 1'b1, default: 1'b0};
+  localparam mbox_steps_s MBOX_STEP_DATAOUT_RD      = '{dataout_rd     : 1'b1, default: 1'b0};
+  localparam mbox_steps_s MBOX_STEP_RESP_DATAIN_WR  = '{resp_datain_wr : 1'b1, default: 1'b0};
+  localparam mbox_steps_s MBOX_STEP_RESP_DLEN_WR    = '{resp_dlen_wr   : 1'b1, default: 1'b0};
+  localparam mbox_steps_s MBOX_STEP_RESP_DLEN_RD    = '{resp_dlen_rd   : 1'b1, default: 1'b0};
+  localparam mbox_steps_s MBOX_STEP_RESP_DATAOUT_RD = '{resp_dataout_rd: 1'b1, default: 1'b0};
+  localparam mbox_steps_s MBOX_STEP_STATUS_WR       = '{status_wr      : 1'b1, default: 1'b0};
+  localparam mbox_steps_s MBOX_STEP_STATUS_RD       = '{status_rd      : 1'b1, default: 1'b0};
+  localparam mbox_steps_s MBOX_STEP_EXEC_CLR        = '{exec_clr       : 1'b1, default: 1'b0};
+  localparam mbox_steps_s MBOX_STEP_FORCE_UNLOCK    = '{force_unlock   : 1'b1, default: 1'b0};
+  localparam mbox_steps_s MBOX_STEP_RESET           = '{reset          : 1'b1, default: 1'b0};
+
+  localparam bit     AHB_REQ = 1'b1;
+  localparam bit NOT_AHB_REQ = 1'b0;
+  typedef struct packed {
+    bit          is_ahb;
+    mbox_steps_s step;
+  } mbox_steps_by_if_s;
   // pragma uvmf custom additional end
 
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_environment.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_environment.svh
index ea05dda33..0b2c30b66 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_environment.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_environment.svh
@@ -54,6 +54,9 @@ class soc_ifc_environment  extends uvmf_environment_base #(
   typedef cptra_status_agent  cptra_status_agent_t;
   cptra_status_agent_t cptra_status_agent;
 
+  typedef mbox_sram_agent  mbox_sram_agent_t;
+  mbox_sram_agent_t mbox_sram_agent;
+
 
 
 
@@ -67,6 +70,17 @@ class soc_ifc_environment  extends uvmf_environment_base #(
                 )
  soc_ifc_sb_t;
   soc_ifc_sb_t soc_ifc_sb;
+  typedef soc_ifc_env_cov_subscriber #(
+                .PRED_T(soc_ifc_pred_t),
+                .CONFIG_T(CONFIG_T)
+  )
+  soc_ifc_env_cov_sub_t;
+ soc_ifc_env_cov_sub_t soc_ifc_env_cov_sub;
+  typedef soc_ifc_reg_cov_subscriber #(
+                .CONFIG_T(CONFIG_T)
+                )
+ soc_ifc_reg_cov_sub_t;
+  soc_ifc_reg_cov_sub_t soc_ifc_reg_cov_sub;
 
 
 // UVMF_CHANGE_ME: QVIP_AGENT_USED_FOR_REG_MAP: 
@@ -161,11 +175,18 @@ class soc_ifc_environment  extends uvmf_environment_base #(
     soc_ifc_status_agent.set_config(configuration.soc_ifc_status_agent_config);
     cptra_status_agent = cptra_status_agent_t::type_id::create("cptra_status_agent",this);
     cptra_status_agent.set_config(configuration.cptra_status_agent_config);
+    mbox_sram_agent = mbox_sram_agent_t::type_id::create("mbox_sram_agent",this);
+    mbox_sram_agent.set_config(configuration.mbox_sram_agent_config);
     soc_ifc_pred = soc_ifc_pred_t::type_id::create("soc_ifc_pred",this);
     soc_ifc_pred.configuration = configuration;
     soc_ifc_sb = soc_ifc_sb_t::type_id::create("soc_ifc_sb",this);
     soc_ifc_sb.configuration = configuration;
     soc_ifc_sb.enable_wait_for_scoreboard_empty();
+    soc_ifc_env_cov_sub = soc_ifc_env_cov_sub_t::type_id::create("soc_ifc_env_cov_sub",this);
+    soc_ifc_env_cov_sub.configuration = configuration;
+    soc_ifc_env_cov_sub.pred = soc_ifc_pred;
+    soc_ifc_reg_cov_sub = soc_ifc_reg_cov_sub_t::type_id::create("soc_ifc_reg_cov_sub",this);
+    soc_ifc_reg_cov_sub.configuration = configuration;
 // pragma uvmf custom reg_model_build_phase begin
   // Build register model predictor if prediction is enabled
   if (configuration.enable_reg_prediction) begin
@@ -185,7 +206,7 @@ class soc_ifc_environment  extends uvmf_environment_base #(
 // ****************************************************************************
 // FUNCTION: connect_phase()
 // This function makes all connections within this environment.  Connections
-// typically inclue agent to predictor, predictor to scoreboard and scoreboard
+// typically include agent to predictor, predictor to scoreboard and scoreboard
 // to agent.
 //
   virtual function void connect_phase(uvm_phase phase);
@@ -194,6 +215,7 @@ class soc_ifc_environment  extends uvmf_environment_base #(
     super.connect_phase(phase);
     soc_ifc_ctrl_agent.monitored_ap.connect(soc_ifc_pred.soc_ifc_ctrl_agent_ae);
     cptra_ctrl_agent.monitored_ap.connect(soc_ifc_pred.cptra_ctrl_agent_ae);
+    mbox_sram_agent.monitored_ap.connect(soc_ifc_pred.mbox_sram_agent_ae);
     soc_ifc_pred.soc_ifc_sb_ap.connect(soc_ifc_sb.expected_analysis_export);
     soc_ifc_pred.cptra_sb_ap.connect(soc_ifc_sb.expected_cptra_analysis_export);
     soc_ifc_pred.soc_ifc_sb_ahb_ap.connect(soc_ifc_sb.expected_ahb_analysis_export);
@@ -211,6 +233,15 @@ class soc_ifc_environment  extends uvmf_environment_base #(
     if ( configuration.qvip_apb5_slave_subenv_interface_activity[0] == ACTIVE )
        uvm_config_db #(mvc_sequencer)::set(null,UVMF_SEQUENCERS,configuration.qvip_apb5_slave_subenv_interface_names[0],qvip_apb5_slave_subenv.apb5_master_0.m_sequencer  );
     // pragma uvmf custom reg_model_connect_phase begin
+    /*if (TODO) */begin:connect_coverage
+        soc_ifc_pred.soc_ifc_cov_ap      .connect                                   (soc_ifc_env_cov_sub.soc_ifc_ctrl_ae  );
+        soc_ifc_pred.cptra_cov_ap        .connect                                   (soc_ifc_env_cov_sub.cptra_ctrl_ae    );
+        soc_ifc_status_agent.monitored_ap.connect                                   (soc_ifc_env_cov_sub.soc_ifc_status_ae);
+        cptra_status_agent  .monitored_ap.connect                                   (soc_ifc_env_cov_sub.cptra_status_ae  );
+        mbox_sram_agent     .monitored_ap.connect                                   (soc_ifc_env_cov_sub.mbox_sram_ae     );
+        qvip_ahb_lite_slave_subenv_ahb_lite_slave_0_ap["burst_transfer_cov"].connect(soc_ifc_env_cov_sub.ahb_ae           );
+        qvip_apb5_slave_subenv_apb5_master_0_ap       ["trans_ap_cov"]      .connect(soc_ifc_env_cov_sub.apb_ae           );
+    end:connect_coverage
     // Create register model adapter if required
     if (configuration.enable_reg_prediction ||
         configuration.enable_reg_adaptation) begin
@@ -246,6 +277,8 @@ class soc_ifc_environment  extends uvmf_environment_base #(
       // of the sub-maps must be done manually.
       soc_ifc_pred.soc_ifc_ahb_reg_ap.connect(ahb_reg_predictor.bus_item_export);
       soc_ifc_pred.soc_ifc_apb_reg_ap.connect(apb_reg_predictor.bus_item_export);
+      ahb_reg_predictor.reg_ap.connect(soc_ifc_reg_cov_sub.analysis_export);
+      apb_reg_predictor.reg_ap.connect(soc_ifc_reg_cov_sub.analysis_export);
 //      qvip_ahb_lite_slave_subenv_ahb_lite_slave_0_ap["burst_transfer"].connect(ahb_reg_predictor.bus_item_export);
 //      qvip_apb5_slave_subenv_apb5_master_0_ap["trans_ap"].connect(apb_reg_predictor.bus_item_export);
     end
@@ -286,15 +319,47 @@ function void soc_ifc_environment::set_can_handle_reset(bit en = 1'b1);
 endfunction
 
 task soc_ifc_environment::handle_reset(string kind = "HARD");
+    uvm_object obj;
+    uvm_event reset_synchro;
+    reset_flag rst_sync_flag;
+
     // Reset status agents (needed to reset monitor transaction keys)
     this.cptra_status_agent.handle_reset(kind);
     this.soc_ifc_status_agent.handle_reset(kind);
 
+    // Reset mbox_sram agent (needed to reset the ECC error injection)
+    this.mbox_sram_agent.handle_reset(kind);
+
     // Reset scoreboard according to kind
     this.soc_ifc_sb.handle_reset(kind);
 
     // Reset predictor according to kind
-    this.soc_ifc_pred.handle_reset(kind);
+    this.soc_ifc_pred.handle_reset(kind, reset_synchro);
+
+    // A "SOFT" reset (cptra_rst_b) is followed by noncore reset assertion; we
+    // need to time the assertion of the reset to all the soc_ifc_env components
+    // based on the predictor
+    if (kind == "SOFT") begin
+        `uvm_info("SOC_IFC_ENV_HANDLE_RESET", "After receiving SOFT reset, waiting for predictor to signal the NONCORE reset so environment can be reset", UVM_LOW)
+
+        reset_synchro.wait_trigger_data(obj);
+        $cast(rst_sync_flag, obj);
+        if (rst_sync_flag.get_name() != "noncore_reset_flag")
+            `uvm_error("SOC_IFC_ENV_HANDLE_RESET", {"Reset synchronization event returned a reset event of unexpected type! ", rst_sync_flag.get_name()})
+
+        // Reset status agents (needed to reset monitor transaction keys)
+        this.cptra_status_agent.handle_reset("NONCORE");
+        this.soc_ifc_status_agent.handle_reset("NONCORE");
+
+        // Reset mbox_sram agent (needed to reset the ECC error injection)
+        this.mbox_sram_agent.handle_reset("NONCORE");
+
+        // Reset scoreboard according to kind
+        this.soc_ifc_sb.handle_reset("NONCORE");
+
+        `uvm_info("SOC_IFC_ENV_HANDLE_RESET", "After receiving NONCORE reset signal from soc_ifc_predictor, completed environment-level NONCORE reset prerequisites and continuing with reset prediction", UVM_LOW)
+        reset_synchro.reset();
+    end
 
     // TODO does this happen naturally from hdl_top driving reset?
     // Reset APB
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_predictor.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_predictor.svh
index 58008bdee..9e1465f0f 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_predictor.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_predictor.svh
@@ -29,6 +29,7 @@
 //
 //   soc_ifc_ctrl_agent_ae receives transactions of type  soc_ifc_ctrl_transaction
 //   cptra_ctrl_agent_ae receives transactions of type  cptra_ctrl_transaction
+//   mbox_sram_agent_ae receives transactions of type  mbox_sram_transaction
 //   ahb_slave_0_ae receives transactions of type  mvc_sequence_item_base
 //   apb5_slave_0_ae receives transactions of type  mvc_sequence_item_base
 //
@@ -81,6 +82,11 @@ class soc_ifc_predictor #(
                               .BASE_T(BASE_T)
                               )
 ) cptra_ctrl_agent_ae;
+  uvm_analysis_imp_mbox_sram_agent_ae #(mbox_sram_transaction, soc_ifc_predictor #(
+                              .CONFIG_T(CONFIG_T),
+                              .BASE_T(BASE_T)
+                              )
+) mbox_sram_agent_ae;
   uvm_analysis_imp_ahb_slave_0_ae #(mvc_sequence_item_base, soc_ifc_predictor #(
                               .CONFIG_T(CONFIG_T),
                               .BASE_T(BASE_T)
@@ -99,6 +105,9 @@ class soc_ifc_predictor #(
   uvm_analysis_port #(mvc_sequence_item_base) soc_ifc_sb_ahb_ap;
   uvm_analysis_port #(mvc_sequence_item_base) soc_ifc_sb_apb_ap;
 
+  uvm_analysis_port #(soc_ifc_ctrl_transaction) soc_ifc_cov_ap;
+  uvm_analysis_port #(cptra_ctrl_transaction  ) cptra_cov_ap;
+
 
   // Transaction variable for predicted values to be sent out soc_ifc_sb_ap
   // Once a transaction is sent through an analysis_port, another transaction should
@@ -143,6 +152,7 @@ class soc_ifc_predictor #(
   // Define transaction handles for debug visibility
   soc_ifc_ctrl_transaction soc_ifc_ctrl_agent_ae_debug;
   cptra_ctrl_transaction cptra_ctrl_agent_ae_debug;
+  mbox_sram_transaction mbox_sram_agent_ae_debug;
   mvc_sequence_item_base ahb_slave_0_ae_debug;
   mvc_sequence_item_base apb5_slave_0_ae_debug;
 
@@ -151,28 +161,43 @@ class soc_ifc_predictor #(
   uvm_analysis_port #(mvc_sequence_item_base) soc_ifc_ahb_reg_ap;
   uvm_analysis_port #(mvc_sequence_item_base) soc_ifc_apb_reg_ap;
 
+  process running_dly_jobs[$];
+  int unsigned job_end_count[time];
+  bit cptra_pwrgood_asserted = 1'b0;
   bit soc_ifc_rst_in_asserted = 1'b1;
   bit noncore_rst_out_asserted = 1'b1;
   bit uc_rst_out_asserted = 1'b1;
+  bit fw_update_rst_window = 1'b0;
   bit soc_ifc_error_intr_pending = 1'b0;
   bit soc_ifc_notif_intr_pending = 1'b0;
   bit sha_err_intr_pending = 1'b0; // TODO
   bit sha_notif_intr_pending = 1'b0; // TODO
+  bit timer_intr_pending = 1'b1;
+  bit nmi_intr_pending = 1'b0;
+  bit cptra_error_fatal = 1'b0;
+  bit cptra_error_non_fatal = 1'b0;
   bit fuse_update_enabled = 1'b1;
   bit ready_for_fw_push = 1'b0; // TODO
-  bit ready_for_runtime = 1'b0; // TODO
+  bit ready_for_runtime = 1'b0;
   bit mailbox_flow_done = 1'b0;
+  bit clk_gate_active         = 1'b1; // TODO
+  bit rdc_clk_gate_active     = 1'b1;
+  bit soc_ifc_clk_gate_active = 1'b1; // TODO
 
   bit mailbox_data_avail = 1'b0;
 
   int datain_count = 0;
   int dataout_count = 0;
 
+  bit dataout_mismatch_expected = 1'b0;
+
   bit [31:0] nmi_vector = 32'h0;
-  bit iccm_locked = 1'b0; // TODO
+  bit iccm_locked = 1'b0;
   bit [`CLP_OBF_KEY_DWORDS-1:0] [31:0] cptra_obf_key_reg = '{default:32'h0}; // FIXME use reg-model value?
-  security_state_t security_state = '{debug_locked: 1'b1, device_lifecycle: DEVICE_UNPROVISIONED};
+  security_state_t security_state = '{debug_locked: 1'b1, device_lifecycle: DEVICE_UNPROVISIONED}; // FIXME unused
   bit bootfsm_breakpoint = 1'b0;
+  bit cptra_in_dbg_or_manuf_mode = 1'b0;
+  int unsigned fw_update_wait_count = 0;
 
   bit [63:0] generic_output_wires = 64'h0;
 
@@ -182,6 +207,10 @@ class soc_ifc_predictor #(
   bit trng_data_req = 1'b0;
   bit [apb5_master_0_params::APB3_PWDATA_BIT_WIDTH-1:0] trng_data [12]       = '{default: '0}; // FIXME what is this used for? Can we just use the reg-model mirrors instead?
 
+  // For collecting coverage
+  mbox_steps_s prev_step = '{null_action: 1'b1, default: 1'b0};
+  mbox_steps_s next_step = '{null_action: 1'b1, default: 1'b0};
+
   soc_ifc_reg_model_top  p_soc_ifc_rm;
   uvm_reg_map p_soc_ifc_APB_map; // Block map
   uvm_reg_map p_soc_ifc_AHB_map; // Block map
@@ -194,12 +223,34 @@ class soc_ifc_predictor #(
 
   reset_flag hard_reset_flag;
   reset_flag soft_reset_flag;
+  reset_flag noncore_reset_flag;
+
+  //WDT vars:
+  bit [63:0] t1_count, t2_count;
+  bit wdt_error_intr_sent;
+  bit wdt_t2_error_intr_sent;
+  bit wdt_nmi_intr_sent;
+  bit reset_wdt_count;
+  bit wdt_t1_restart;
+  bit wdt_t2_restart;
 
   extern task          poll_and_run_delay_jobs();
+  extern function void send_delayed_expected_transactions();
+  extern function bit  check_mbox_no_lock_error(soc_ifc_sb_apb_ap_output_transaction_t txn, uvm_reg axs_reg);
+  extern function bit  check_mbox_ooo_error(soc_ifc_sb_apb_ap_output_transaction_t txn, uvm_reg axs_reg);
+  extern function bit  check_mbox_inv_user_error(soc_ifc_sb_apb_ap_output_transaction_t txn, uvm_reg axs_reg);
+  extern task          update_mtime_mirrors();
+  extern task          mtime_counter_task();
+  extern function bit  mtime_lt_mtimecmp();
+  extern task          wdt_counter_task();
   extern function bit  valid_requester(input uvm_transaction txn);
   extern function bit  valid_receiver(input uvm_transaction txn);
-  extern task          handle_reset(input string kind = "HARD");
+  extern function bit  sha_valid_user(input uvm_transaction txn);
+  extern function void predict_boot_wait_boot_done();
+  extern task          handle_reset(input string kind = "HARD", output uvm_event reset_synchro);
   extern function void predict_reset(input string kind = "HARD");
+  extern function bit  soc_ifc_status_txn_expected_after_noncore_reset();
+  extern function bit  cptra_status_txn_expected_after_noncore_reset();
   extern function bit  soc_ifc_status_txn_expected_after_warm_reset();
   extern function bit  cptra_status_txn_expected_after_warm_reset();
   extern function bit  soc_ifc_status_txn_expected_after_cold_reset();
@@ -213,7 +264,6 @@ class soc_ifc_predictor #(
   // FUNCTION: new
   function new(string name, uvm_component parent);
      super.new(name,parent);
-    `uvm_info("PREDICTOR_REVIEW", "This predictor has been created either through generation or re-generation with merging.  Remove this message after the predictor has been reviewed. (manually downgraded to uvm_info)", UVM_LOW)
   // pragma uvmf custom new begin
   // pragma uvmf custom new end
   endfunction
@@ -224,6 +274,7 @@ class soc_ifc_predictor #(
 
     soc_ifc_ctrl_agent_ae = new("soc_ifc_ctrl_agent_ae", this);
     cptra_ctrl_agent_ae = new("cptra_ctrl_agent_ae", this);
+    mbox_sram_agent_ae = new("mbox_sram_agent_ae", this);
     ahb_slave_0_ae = new("ahb_slave_0_ae", this);
     apb5_slave_0_ae = new("apb5_slave_0_ae", this);
     soc_ifc_sb_ap = new("soc_ifc_sb_ap", this );
@@ -232,6 +283,8 @@ class soc_ifc_predictor #(
     soc_ifc_sb_apb_ap = new("soc_ifc_sb_apb_ap", this );
     soc_ifc_ahb_reg_ap = new("soc_ifc_ahb_reg_ap", this);
     soc_ifc_apb_reg_ap = new("soc_ifc_apb_reg_ap", this);
+    soc_ifc_cov_ap = new("soc_ifc_cov_ap", this );
+    cptra_cov_ap = new("cptra_cov_ap", this );
   // pragma uvmf custom build_phase begin
     p_soc_ifc_rm = configuration.soc_ifc_rm;
     p_soc_ifc_AHB_map = p_soc_ifc_rm.get_map_by_name("soc_ifc_AHB_map");
@@ -240,12 +293,15 @@ class soc_ifc_predictor #(
     reset_handled = new("reset_handled");
     hard_reset_flag = new("hard_reset_flag"); // Used as trigger data for reset events. In UVM 1.2, data changes from a uvm_object to a string
     soft_reset_flag = new("soft_reset_flag"); // Used as trigger data for reset events. In UVM 1.2, data changes from a uvm_object to a string
+    noncore_reset_flag = new("noncore_reset_flag"); // Used as trigger data for reset events. In UVM 1.2, data changes from a uvm_object to a string
   // pragma uvmf custom build_phase end
   endfunction
 
   task run_phase(uvm_phase phase);
     fork
         poll_and_run_delay_jobs();
+        mtime_counter_task();
+        wdt_counter_task();
     join_none
     super.run_phase(phase);
   endtask
@@ -263,7 +319,7 @@ class soc_ifc_predictor #(
 
     soc_ifc_ctrl_agent_ae_debug = t;
     `uvm_info("PRED_SOC_IFC_CTRL", "Transaction Received through soc_ifc_ctrl_agent_ae", UVM_MEDIUM)
-    `uvm_info("PRED_SOC_IFC_CTRL", {"            Data: ",t.convert2string()}, UVM_FULL)
+    `uvm_info("PRED_SOC_IFC_CTRL", {"            Data: ",t.convert2string()}, UVM_HIGH)
     // Construct one of each output transaction type.
     soc_ifc_sb_ap_output_transaction = soc_ifc_sb_ap_output_transaction_t::type_id::create("soc_ifc_sb_ap_output_transaction");
     cptra_sb_ap_output_transaction = cptra_sb_ap_output_transaction_t::type_id::create("cptra_sb_ap_output_transaction");
@@ -273,6 +329,8 @@ class soc_ifc_predictor #(
 
     // FIXME account for security_state/scan_mode below
 
+    cptra_pwrgood_asserted = t.set_pwrgood;
+
     // Initial boot
     if (!t.set_pwrgood && soc_ifc_rst_in_asserted) begin
         cptra_obf_key_reg = t.cptra_obf_key_rand;
@@ -282,16 +340,20 @@ class soc_ifc_predictor #(
         end
         if (!t.assert_rst)
             `uvm_fatal("PRED_SOC_IFC_CTRL", "Bad initial boot with cptra_rst_b deasserted")
+        if (!p_soc_ifc_rm.soc_ifc_reg_rm.boot_fn_state_sigs.boot_idle)
+            `uvm_fatal("PRED_SOC_IFC_CTRL", $sformatf("Bad initial boot FSM prediction: %p", p_soc_ifc_rm.soc_ifc_reg_rm.boot_fn_state_sigs))
         if (reset_handled.is_on()) begin
             `uvm_error("PRED_SOC_IFC_CTRL", "reset_handled event unexpectedly set on receiving soc_ifc_ctrl_transaction for initial boot reset")
             reset_handled.reset();
         end
         predict_reset("HARD");
+        reset_predicted.trigger(hard_reset_flag/*"HARD"*/);
     end
     // Cold reset assertion
     else if (!t.set_pwrgood) begin
         // FIXME
         // Catch obf_key, uds_seed, field_entropy reset on cold-reset
+
         if (!t.assert_rst) begin
             `uvm_fatal("PRED_SOC_IFC_CTRL", "Bad cold rst")
         end
@@ -332,6 +394,12 @@ class soc_ifc_predictor #(
             send_cptra_sts_txn |= (t.cptra_obf_key_rand[ii] != cptra_obf_key_reg[ii]);
         end
         cptra_obf_key_reg = t.cptra_obf_key_rand;
+        reset_predicted.reset();
+        // No new signal predictions since it was all done on Cold reset assertion.
+        // But trigger the soft reset event to indicate to the predict_reset delay spinoff task
+        // that the soft reset is done (once cptra_rst_b deasserts)
+        reset_predicted.trigger(soft_reset_flag/*"SOFT"*/);
+        `uvm_info("PRED_SOC_IFC_CTRL", $sformatf("In response to cold_reset deassertion, send_cptra_sts_txn: %d", send_cptra_sts_txn), UVM_NONE)
     end
     // Warm reset assertion
     else if (t.assert_rst && !soc_ifc_rst_in_asserted) begin
@@ -351,19 +419,24 @@ class soc_ifc_predictor #(
         if (soc_ifc_rst_in_asserted) begin
             // Todo check for breakpoint assertion and flag an expected AHB write to clear it
             soc_ifc_rst_in_asserted = 1'b0;
-            p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_FLOW_STATUS.ready_for_fuses.predict(1'b1);
-            noncore_rst_out_asserted = 1'b1;
-            uc_rst_out_asserted = 1'b1;
-            bootfsm_breakpoint = t.set_bootfsm_breakpoint;
-            send_soc_ifc_sts_txn = 1;
+            cptra_in_dbg_or_manuf_mode = ~t.security_state.debug_locked || t.security_state.device_lifecycle == DEVICE_MANUFACTURING;
+            bootfsm_breakpoint = t.set_bootfsm_breakpoint && cptra_in_dbg_or_manuf_mode;
+            reset_predicted.reset();
+            send_soc_ifc_sts_txn = 0; // prediction for ready_for_fuses done in predict_reset after noncore reset deassertion
             send_cptra_sts_txn = 0; // cptra sts transaction not expected until after CPTRA_FUSE_WR_DONE
+            reset_wdt_count = 1'b0;
+            `uvm_info("PRED_SOC_IFC_CTRL", $sformatf("In response to warm_reset deassertion, send_soc_ifc_sts_txn: %d", send_soc_ifc_sts_txn), UVM_NONE)
         end
         // Normal operation
         else begin
-            //TODO beyond detecting uc_rst_asserted, this block needs more logic
-            noncore_rst_out_asserted = 1'b0; // <-- all status transactions after the first one should reflect Caliptra reset deasserted
-            uc_rst_out_asserted = 1'b1; // FIXME
-            send_cptra_sts_txn = 1;
+            //TODO this block needs more logic
+            if (t.generic_input_val ^ {SOC_IFC_DATA_W'(p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_GENERIC_INPUT_WIRES[1].generic_wires.get_mirrored_value()), SOC_IFC_DATA_W'(p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_GENERIC_INPUT_WIRES[0].generic_wires.get_mirrored_value())}) begin
+                `uvm_info("PRED_SOC_IFC_CTRL", "Detected toggle in generic_input_wires", UVM_HIGH)
+                p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.notif_internal_intr_r.notif_gen_in_toggle_sts.predict(1'b1, -1, UVM_PREDICT_READ, UVM_PREDICT, p_soc_ifc_AHB_map); /* AHB-access only, use AHB map*/
+                //Update reg model with the generic_input_val 
+                p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_GENERIC_INPUT_WIRES[0].generic_wires.predict(t.generic_input_val[31:0], -1, UVM_PREDICT_READ, UVM_PREDICT, p_soc_ifc_AHB_map);
+                p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_GENERIC_INPUT_WIRES[1].generic_wires.predict(t.generic_input_val[63:32], -1, UVM_PREDICT_READ, UVM_PREDICT, p_soc_ifc_AHB_map);
+            end
         end
     end
 
@@ -377,7 +450,6 @@ class soc_ifc_predictor #(
         soc_ifc_sb_ap.write(soc_ifc_sb_ap_output_transaction);
         `uvm_info("PRED_SOC_IFC_CTRL", "Transaction submitted through soc_ifc_sb_ap", UVM_MEDIUM)
     end
-    // TODO
     // Code for sending output transaction out through cptra_sb_ap
     // Please note that each broadcasted transaction should be a different object than previously 
     // broadcasted transactions.  Creation of a different object is done by constructing the transaction 
@@ -406,6 +478,12 @@ class soc_ifc_predictor #(
         soc_ifc_sb_apb_ap.write(soc_ifc_sb_apb_ap_output_transaction);
         `uvm_error("PRED_SOC_IFC_CTRL", "NULL Transaction submitted through soc_ifc_sb_apb_ap")
     end
+
+    if (1/*FIXME*/) begin
+        // Forward the received transaction on to the coverage subscriber
+        soc_ifc_cov_ap.write(t);
+        `uvm_info("PRED_SOC_IFC_CTRL", "Transaction submitted through soc_ifc_cov_ap", UVM_MEDIUM)
+    end
     // pragma uvmf custom soc_ifc_ctrl_agent_ae_predictor end
   endfunction
 
@@ -422,7 +500,7 @@ class soc_ifc_predictor #(
 
     cptra_ctrl_agent_ae_debug = t;
     `uvm_info("PRED_CPTRA_CTRL", "Transaction Received through cptra_ctrl_agent_ae", UVM_MEDIUM)
-    `uvm_info("PRED_CPTRA_CTRL", {"            Data: ",t.convert2string()}, UVM_FULL)
+    `uvm_info("PRED_CPTRA_CTRL", {"            Data: ",t.convert2string()}, UVM_HIGH)
     // Construct one of each output transaction type.
     soc_ifc_sb_ap_output_transaction = soc_ifc_sb_ap_output_transaction_t::type_id::create("soc_ifc_sb_ap_output_transaction");
     cptra_sb_ap_output_transaction = cptra_sb_ap_output_transaction_t::type_id::create("cptra_sb_ap_output_transaction");
@@ -437,13 +515,17 @@ class soc_ifc_predictor #(
         //    "do_predict" bypasses the access-check and does not enforce W1C
         //    behavior on this attempt to set interrupt status to 1
         p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.error_internal_intr_r.error_iccm_blocked_sts.predict(1'b1, -1, UVM_PREDICT_READ, UVM_PREDICT, p_soc_ifc_AHB_map); /* AHB-access only, use AHB map*/
-        if (!soc_ifc_error_intr_pending && p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.error_global_intr_r.agg_sts.get_mirrored_value()) begin
-            soc_ifc_error_intr_pending = 1'b1;
-            send_cptra_sts_txn = 1'b1;
-        end
     end
     if (t.assert_clear_secrets) begin
-        `uvm_error("PRED_CPTRA_CTRL", "Unimplemented predictor for clearing secrets")
+        foreach (p_soc_ifc_rm.soc_ifc_reg_rm.internal_obf_key[ii]) p_soc_ifc_rm.soc_ifc_reg_rm.internal_obf_key[ii].key.reset();
+        foreach (p_soc_ifc_rm.soc_ifc_reg_rm.fuse_field_entropy[ii]) p_soc_ifc_rm.soc_ifc_reg_rm.fuse_field_entropy[ii].seed.reset();
+        foreach (p_soc_ifc_rm.soc_ifc_reg_rm.fuse_uds_seed[ii]) p_soc_ifc_rm.soc_ifc_reg_rm.fuse_uds_seed[ii].seed.reset;
+        this.cptra_obf_key_reg = '{default:32'h0};
+        send_cptra_sts_txn = 1'b1;
+        `uvm_info("PRED_CPTRA_CTRL", "Received transaction with clear secrets set! Resetting Caliptra model secrets", UVM_MEDIUM)
+    end
+    if (t.pulse_rv_ecc_error) begin
+        `uvm_error("PRED_CPTRA_CTRL", "Unimplemented predictor for signaling RISCV SRAM ECC Errors")
     end
 
     // Code for sending output transaction out through soc_ifc_sb_ap
@@ -484,9 +566,95 @@ class soc_ifc_predictor #(
         soc_ifc_sb_apb_ap.write(soc_ifc_sb_apb_ap_output_transaction);
         `uvm_error("PRED_CPTRA_CTRL", "NULL Transaction submitted through soc_ifc_sb_apb_ap")
     end
+
+    if (1/*FIXME*/) begin
+        // Forward the received transaction on to the coverage subscriber
+        cptra_cov_ap.write(t);
+        `uvm_info("PRED_CPTRA_CTRL", "Transaction submitted through cptra_cov_ap", UVM_MEDIUM)
+    end
     // pragma uvmf custom cptra_ctrl_agent_ae_predictor end
   endfunction
 
+  // FUNCTION: write_mbox_sram_agent_ae
+  // Transactions received through mbox_sram_agent_ae initiate the execution of this function.
+  // This function performs prediction of DUT output values based on DUT input, configuration and state
+  virtual function void write_mbox_sram_agent_ae(mbox_sram_transaction t);
+    // pragma uvmf custom mbox_sram_agent_ae_predictor begin
+    // Flags control whether each transaction is sent to scoreboard
+    bit send_soc_ifc_sts_txn = 0;
+    bit send_cptra_sts_txn = 0;
+    bit send_ahb_txn = 0;
+    bit send_apb_txn = 0;
+
+    mbox_sram_agent_ae_debug = t;
+    `uvm_info("PRED_MBOX_SRAM", "Transaction Received through mbox_sram_agent_ae", UVM_MEDIUM)
+    `uvm_info("PRED_MBOX_SRAM", {"            Data: ",t.convert2string()}, UVM_HIGH)
+    // Construct one of each output transaction type.
+    soc_ifc_sb_ap_output_transaction = soc_ifc_sb_ap_output_transaction_t::type_id::create("soc_ifc_sb_ap_output_transaction");
+    cptra_sb_ap_output_transaction = cptra_sb_ap_output_transaction_t::type_id::create("cptra_sb_ap_output_transaction");
+    soc_ifc_sb_ahb_ap_output_transaction = soc_ifc_sb_ahb_ap_output_transaction_t::type_id::create("soc_ifc_sb_ahb_ap_output_transaction");
+    soc_ifc_sb_apb_ap_output_transaction = soc_ifc_sb_apb_ap_output_transaction_t::type_id::create("soc_ifc_sb_apb_ap_output_transaction");
+
+    if (rdc_clk_gate_active || noncore_rst_out_asserted) begin
+        `uvm_info("PRED_MBOX_SRAM", "Received transaction while RDC clock gate is active, no system prediction to do since interrupt bits cannot be set", UVM_MEDIUM)
+    end
+    else if (t.is_read && t.ecc_double_bit_error) begin
+        p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.error_internal_intr_r.error_mbox_ecc_unc_sts.predict(1'b1, -1, UVM_PREDICT_READ, UVM_PREDICT, p_soc_ifc_AHB_map); /* AHB-access only, use AHB map*/
+        p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc.predict(1'b1, -1, UVM_PREDICT_READ, UVM_PREDICT, p_soc_ifc_AHB_map);
+        dataout_mismatch_expected = 1'b1;
+        cptra_error_non_fatal = 1'b1;
+        send_soc_ifc_sts_txn = 1'b1;
+        `uvm_info("PRED_MBOX_SRAM", "Received read transaction with Double bit ECC corruption, triggering the err interrupt", UVM_MEDIUM)
+    end
+    else if (t.is_read && t.ecc_single_bit_error) begin
+        p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.notif_internal_intr_r.notif_mbox_ecc_cor_sts.predict(1'b1, -1, UVM_PREDICT_READ, UVM_PREDICT, p_soc_ifc_AHB_map); /* AHB-access only, use AHB map*/
+        `uvm_info("PRED_MBOX_SRAM", "Received read transaction with Single bit ECC corruption, triggering the notification interrupt", UVM_MEDIUM)
+    end
+    else begin
+        `uvm_info("PRED_MBOX_SRAM", "Received mailbox SRAM transaction does not cause a system state change prediction", UVM_FULL)
+    end
+
+    // Code for sending output transaction out through soc_ifc_sb_ap
+    // Please note that each broadcasted transaction should be a different object than previously 
+    // broadcasted transactions.  Creation of a different object is done by constructing the transaction 
+    // using either new() or create().  Broadcasting a transaction object more than once to either the 
+    // same subscriber or multiple subscribers will result in unexpected and incorrect behavior.
+    if (send_soc_ifc_sts_txn) begin
+        populate_expected_soc_ifc_status_txn(soc_ifc_sb_ap_output_transaction);
+        soc_ifc_sb_ap.write(soc_ifc_sb_ap_output_transaction);
+        `uvm_info("PRED_MBOX_SRAM", "Transaction submitted through soc_ifc_sb_ap", UVM_MEDIUM)
+    end
+    // Code for sending output transaction out through cptra_sb_ap
+    // Please note that each broadcasted transaction should be a different object than previously 
+    // broadcasted transactions.  Creation of a different object is done by constructing the transaction 
+    // using either new() or create().  Broadcasting a transaction object more than once to either the 
+    // same subscriber or multiple subscribers will result in unexpected and incorrect behavior.
+    if (send_cptra_sts_txn) begin
+        populate_expected_cptra_status_txn(cptra_sb_ap_output_transaction);
+        cptra_sb_ap.write(cptra_sb_ap_output_transaction);
+        `uvm_error("PRED_MBOX_SRAM", "NULL Transaction submitted through cptra_sb_ap")
+    end
+    // Code for sending output transaction out through soc_ifc_sb_ahb_ap
+    // Please note that each broadcasted transaction should be a different object than previously 
+    // broadcasted transactions.  Creation of a different object is done by constructing the transaction 
+    // using either new() or create().  Broadcasting a transaction object more than once to either the 
+    // same subscriber or multiple subscribers will result in unexpected and incorrect behavior.
+    if (send_ahb_txn) begin
+        soc_ifc_sb_ahb_ap.write(soc_ifc_sb_ahb_ap_output_transaction);
+        `uvm_error("PRED_MBOX_SRAM", "NULL Transaction submitted through soc_ifc_sb_ahb_ap")
+    end
+    // Code for sending output transaction out through soc_ifc_sb_apb_ap
+    // Please note that each broadcasted transaction should be a different object than previously 
+    // broadcasted transactions.  Creation of a different object is done by constructing the transaction 
+    // using either new() or create().  Broadcasting a transaction object more than once to either the 
+    // same subscriber or multiple subscribers will result in unexpected and incorrect behavior.
+    if (send_apb_txn) begin
+        soc_ifc_sb_apb_ap.write(soc_ifc_sb_apb_ap_output_transaction);
+        `uvm_error("PRED_MBOX_SRAM", "NULL Transaction submitted through soc_ifc_sb_apb_ap")
+    end
+    // pragma uvmf custom mbox_sram_agent_ae_predictor end
+  endfunction
+
   // FUNCTION: write_ahb_slave_0_ae
   // Transactions received through ahb_slave_0_ae initiate the execution of this function.
   // This function performs prediction of DUT output values based on DUT input, configuration and state
@@ -503,10 +671,14 @@ class soc_ifc_predictor #(
     bit send_cptra_sts_txn = 0;
     bit send_ahb_txn = 1;
     bit send_apb_txn = 0;
+    bit wdt_cascade = 0;
+    bit wdt_independent = 0;
+    bit wdt_t1_timeout = 0;
+    bit wdt_t2_timeout = 0;
     ahb_slave_0_ae_debug = t;
 
     `uvm_info("PRED_AHB", "Transaction Received through ahb_slave_0_ae", UVM_MEDIUM)
-    `uvm_info("PRED_AHB", {"            Data: ",t.convert2string()}, UVM_FULL)
+    `uvm_info("PRED_AHB", {"            Data: ",t.convert2string()}, UVM_HIGH)
 
     // Construct one of each output transaction type.
     soc_ifc_sb_ap_output_transaction = soc_ifc_sb_ap_output_transaction_t::type_id::create("soc_ifc_sb_ap_output_transaction");
@@ -539,13 +711,30 @@ class soc_ifc_predictor #(
     if (!configuration.enable_reg_prediction) begin
         do_reg_prediction = 1'b0;
     end
+    else if (rdc_clk_gate_active || noncore_rst_out_asserted) begin
+        do_reg_prediction = 1'b0;
+        if (ahb_txn.RnW == AHB_READ)
+            soc_ifc_sb_ahb_ap_output_transaction.data[0] = 0;
+    end
     else if (axs_mem != null) begin
         do_reg_prediction = 1'b0;
     end
     else if (axs_reg != null) begin
         // Mailbox accesses are discarded based on valid_requester/valid_receiver
         case (axs_reg.get_name()) inside
-            "mbox_lock",
+            "mbox_lock": begin
+                if (ahb_txn.RnW == AHB_READ && ahb_txn.resp[0] != AHB_OKAY) begin
+                    do_reg_prediction = 1'b0;
+                    // "Expected" read data is 0
+                    soc_ifc_sb_ahb_ap_output_transaction.data[0] = 0;
+                    // Complete any scheduled predictions to 0 (due to other delay jobs)
+                    if (p_soc_ifc_rm.mbox_csr_rm.mbox_lock_clr_miss.is_on()) begin
+                        p_soc_ifc_rm.mbox_csr_rm.mbox_lock.lock.predict(0);
+                        `uvm_info("PRED_AHB", "Completed mbox_lock deassert prediction (scheduled by mbox_execute) since mbox_lock reg prediction is disabled, due to failed AHB transfer", UVM_MEDIUM)
+                        p_soc_ifc_rm.mbox_csr_rm.mbox_lock_clr_miss.reset(0);
+                    end
+                end
+            end
             "mbox_user": begin
                 if (ahb_txn.RnW == AHB_READ && ahb_txn.resp[0] != AHB_OKAY) begin
                     do_reg_prediction = 1'b0;
@@ -599,6 +788,14 @@ class soc_ifc_predictor #(
                         // "Expected" read data for scoreboard is current
                         // mirrored value prior to running do_predict
                         soc_ifc_sb_ahb_ap_output_transaction.data[0] = axs_reg.get_mirrored_value() << 8*(address_aligned % (ahb_lite_slave_0_params::AHB_WDATA_WIDTH/8));
+                        // ... unless it's an ECC double bit error, just use the
+                        // observed data to avoid a scoreboard error (since the
+                        // mismatch is anticipated)
+                        if (dataout_mismatch_expected) begin
+                            `uvm_info("PRED_AHB", "Ignoring mbox_dataout predicted contents and using observed AHB data due to prior ECC double bit flip", UVM_HIGH)
+                            dataout_mismatch_expected = 1'b0;
+                            soc_ifc_sb_ahb_ap_output_transaction.data[0] = ahb_txn.data[0];
+                        end
                         dataout_count++;
                     end
                     else begin
@@ -614,13 +811,58 @@ class soc_ifc_predictor #(
                 if (ahb_txn.RnW == AHB_WRITE) begin
                     if (!valid_receiver(ahb_txn) || ahb_txn.resp[0] != AHB_OKAY) begin
                         do_reg_prediction = 1'b0;
-                        `uvm_warning("PRED_AHB", $sformatf("Write to mbox_status in state [%p] is unexpected! mbox_lock.lock: %0d, soc_has_lock: %0d, valid_receiver: %0d",
-                                                           p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs,
-                                                           p_soc_ifc_rm.mbox_csr_rm.mbox_lock.lock.get_mirrored_value(),
-                                                           p_soc_ifc_rm.mbox_csr_rm.mbox_status.soc_has_lock.get_mirrored_value(),
-                                                           valid_receiver(ahb_txn)))
+                        // NOTE: This might happen if a force-unlock is in progress when the mbox_status write is initiated
+                        `uvm_info("PRED_AHB",
+                                  $sformatf("Write to mbox_status in state [%p] is unexpected! mbox_lock.lock: %0d, soc_has_lock: %0d, valid_receiver: %0d",
+                                            p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs,
+                                            p_soc_ifc_rm.mbox_csr_rm.mbox_lock.lock.get_mirrored_value(),
+                                            p_soc_ifc_rm.mbox_csr_rm.mbox_status.soc_has_lock.get_mirrored_value(),
+                                            valid_receiver(ahb_txn)),
+                                  UVM_LOW)
+                    end
+                end
+                else begin
+                    if (ahb_txn.resp[0] != AHB_OKAY) begin
+                        do_reg_prediction = 1'b0;
+                        // "Expected" read data is 0
+                        soc_ifc_sb_ahb_ap_output_transaction.data[0] = 0;
+                    end
+                end
+            end
+            //SHA Accelerator Functions
+            "LOCK",
+            "USER": begin
+                if (ahb_txn.RnW == AHB_READ && ahb_txn.resp[0] != AHB_OKAY) begin
+                    do_reg_prediction = 1'b0;
+                    // "Expected" read data is 0
+                    soc_ifc_sb_ahb_ap_output_transaction.data[0] = 0;
+                end
+            end
+            "MODE",
+            "START_ADDRESS",
+            "DLEN": begin
+                if (ahb_txn.RnW == AHB_WRITE) begin
+                    do_reg_prediction = sha_valid_user(ahb_txn) && (ahb_txn.resp[0] == AHB_OKAY);
+                end
+                else begin
+                    if (ahb_txn.resp[0] != AHB_OKAY) begin
+                        do_reg_prediction = 1'b0;
+                        // "Expected" read data is 0
+                        soc_ifc_sb_ahb_ap_output_transaction.data[0] = 0;
                     end
                 end
+            end
+            "DATAIN": begin
+                if (ahb_txn.resp[0] != AHB_OKAY) begin
+                    do_reg_prediction = 1'b0;
+                    // "Expected" read data is 0
+                    soc_ifc_sb_ahb_ap_output_transaction.data[0] = 0;
+                end
+            end
+            "EXECUTE": begin
+                if (ahb_txn.RnW == AHB_WRITE) begin
+                    do_reg_prediction = sha_valid_user(ahb_txn) && (ahb_txn.resp[0] == AHB_OKAY);
+                end
                 else begin
                     if (ahb_txn.resp[0] != AHB_OKAY) begin
                         do_reg_prediction = 1'b0;
@@ -629,6 +871,17 @@ class soc_ifc_predictor #(
                     end
                 end
             end
+            "STATUS",
+            ["DIGEST[0]":"DIGEST[9]"],
+            ["DIGEST[10]":"DIGEST[15]"]: begin
+                if (ahb_txn.resp[0] != AHB_OKAY) begin
+                    do_reg_prediction = 1'b0;
+                    // "Expected" read data is 0
+                    soc_ifc_sb_ahb_ap_output_transaction.data[0] = 0;
+                end
+            end
+            "CONTROL": begin
+            end
             default: begin
                 `uvm_info("PRED_AHB", {"Enable reg prediction on access to ", axs_reg.get_name()}, UVM_FULL)
             end
@@ -642,7 +895,10 @@ class soc_ifc_predictor #(
     end
 
     // Calculate any other system effects from the register access
-    if (axs_mem != null) begin: MEM_AXS
+    if (rdc_clk_gate_active || noncore_rst_out_asserted) begin
+        `uvm_info("PRED_AHB", {"On access to register: ", axs_reg.get_full_name(), " reset is asserted, skipping system prediction"}, UVM_MEDIUM)
+    end
+    else if (axs_mem != null) begin: MEM_AXS
         `uvm_info("PRED_AHB", $sformatf("Not performing any system prediction for access to mailbox at address: 0x%x", ahb_txn.address), UVM_FULL)
     end// MEM_AXS
     else if (axs_reg != null) begin: REG_AXS
@@ -666,9 +922,15 @@ class soc_ifc_predictor #(
                         // Reset counters at beginning of command
                         datain_count = 0;
                         dataout_count = 0;
+                        // Log the step for coverage
+                        next_step = '{lock_acquire: 1'b1, default: 1'b0};
+                        `uvm_info("PRED_AHB", $sformatf("Logged mailbox step [%p]", next_step), UVM_HIGH)
                     end
                     else begin
                         `uvm_info("PRED_AHB", $sformatf("Access to mbox_lock of type %p has no effect", ahb_txn.RnW), UVM_MEDIUM)
+                        // Log the step for coverage
+                        next_step = '{null_action: 1'b1, default: 1'b0};
+                        `uvm_info("PRED_AHB", $sformatf("Logged mailbox step [%p]", next_step), UVM_HIGH)
                     end
                 end
                 "mbox_user": begin
@@ -678,67 +940,194 @@ class soc_ifc_predictor #(
                     else begin
                         `uvm_info("PRED_AHB", {"Read to ", axs_reg.get_name(), " has no effect on system"}, UVM_MEDIUM)
                     end
+                    // Log the step for coverage
+                    next_step = '{null_action: 1'b1, default: 1'b0};
+                    `uvm_info("PRED_AHB", $sformatf("Logged mailbox step [%p]", next_step), UVM_HIGH)
+                end
+                "mbox_cmd": begin
+                    if (ahb_txn.RnW == AHB_WRITE && do_reg_prediction) begin
+                        // Log the step for coverage
+                        next_step = '{cmd_wr: 1'b1, default: 1'b0};
+                        `uvm_info("PRED_AHB", $sformatf("Logged mailbox step [%p]", next_step), UVM_HIGH)
+                    end
+                    else if (ahb_txn.RnW == AHB_READ && p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.uc_receive_stage) begin
+                        // Log the step for coverage
+                        next_step = '{cmd_rd: 1'b1, default: 1'b0};
+                        `uvm_info("PRED_AHB", $sformatf("Logged mailbox step [%p]", next_step), UVM_HIGH)
+                    end
+                    else begin
+                        // Log the step for coverage
+                        next_step = '{null_action: 1'b1, default: 1'b0};
+                        `uvm_info("PRED_AHB", $sformatf("Logged mailbox step [%p]", next_step), UVM_HIGH)
+                    end
                 end
-                "mbox_cmd",
                 "mbox_dlen": begin
-                    `uvm_info("PRED_AHB", "Nothing to do", UVM_DEBUG)
+                    if (ahb_txn.RnW == AHB_WRITE && do_reg_prediction) begin
+                        // Log the step for coverage
+                        if (p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.uc_dlen_stage)
+                            next_step = '{dlen_wr: 1'b1, default: 1'b0};
+                        else if (p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.uc_receive_stage)
+                            next_step = '{resp_dlen_wr: 1'b1, default: 1'b0};
+                        `uvm_info("PRED_AHB", $sformatf("Logged mailbox step [%p]", next_step), UVM_HIGH)
+                    end
+                    else if (ahb_txn.RnW == AHB_READ && p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.uc_receive_stage) begin
+                        // Log the step for coverage
+                        next_step = '{dlen_rd: 1'b1, default: 1'b0};
+                        `uvm_info("PRED_AHB", $sformatf("Logged mailbox step [%p]", next_step), UVM_HIGH)
+                    end
+                    else begin
+                        // Log the step for coverage
+                        next_step = '{null_action: 1'b1, default: 1'b0};
+                        `uvm_info("PRED_AHB", $sformatf("Logged mailbox step [%p]", next_step), UVM_HIGH)
+                    end
                 end
                 "mbox_datain": begin
                     `uvm_info("PRED_AHB", $sformatf("Access to mailbox datain, write count: %d", datain_count), UVM_FULL)
+                    if (ahb_txn.RnW == AHB_WRITE && do_reg_prediction) begin
+                        // Log the step for coverage
+                        if (p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.uc_data_stage)
+                            next_step = '{datain_wr: 1'b1, default: 1'b0};
+                        else if (p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.uc_receive_stage)
+                            next_step = '{resp_datain_wr: 1'b1, default: 1'b0};
+                        else
+                            next_step = '{null_action: 1'b1, default: 1'b0};
+                        `uvm_info("PRED_AHB", $sformatf("Logged mailbox step [%p]", next_step), UVM_HIGH)
+                    end
+                    else begin
+                        // Log the step for coverage
+                        next_step = '{null_action: 1'b1, default: 1'b0};
+                        `uvm_info("PRED_AHB", $sformatf("Logged mailbox step [%p]", next_step), UVM_HIGH)
+                    end
                 end
                 "mbox_dataout": begin
                     `uvm_info("PRED_AHB", $sformatf("Access to mailbox dataout, read count: %d", dataout_count), UVM_FULL)
+                    // Log the step for coverage
+                    next_step = '{null_action: 1'b1, default: 1'b0};
+                    if (ahb_txn.RnW == AHB_READ && do_reg_prediction) begin
+                        // Log the step for coverage
+                        if (p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.uc_receive_stage) begin
+                            next_step = '{dataout_rd: 1'b1, default: 1'b0};
+                        end
+                    end
+                    `uvm_info("PRED_AHB", $sformatf("Logged mailbox step [%p]", next_step), UVM_HIGH)
                 end
                 "mbox_execute": begin
-                    // Expect a status transition on mailbox_data_avail
-                    // whenever an AHB write changes the value of mbox_execute
-                    if (mailbox_data_avail ^ p_soc_ifc_rm.mbox_csr_rm.mbox_execute.execute.get_mirrored_value()) begin
-                        `uvm_info("PRED_AHB", "Write to mbox_execute triggers mailbox_data_avail transition", UVM_LOW)
-                        send_soc_ifc_sts_txn = 1'b1;
-                        mailbox_data_avail = p_soc_ifc_rm.mbox_csr_rm.mbox_execute.execute.get_mirrored_value();
+                    // Log the step for coverage
+                    next_step = '{null_action: 1'b1, default: 1'b0};
+                    if (ahb_txn.RnW == AHB_WRITE && do_reg_prediction) begin
+                        // Log the step for coverage
+                        if (p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.uc_data_stage && p_soc_ifc_rm.mbox_csr_rm.mbox_execute.execute.get_mirrored_value()) begin
+                            next_step = '{exec_set: 1'b1, default: 1'b0};
+                        end
+                        else if (p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.uc_done_stage && !p_soc_ifc_rm.mbox_csr_rm.mbox_execute.execute.get_mirrored_value()) begin
+                            next_step = '{exec_clr: 1'b1, default: 1'b0};
+                        end
                     end
+                    `uvm_info("PRED_AHB", $sformatf("Logged mailbox step [%p]", next_step), UVM_HIGH)
                 end
                 "mbox_status": begin
-                    // Write to mbox_status hands control back to SOC
-                    if (ahb_txn.RnW == AHB_WRITE && !mailbox_data_avail && p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.soc_done_stage) begin
-                        mailbox_data_avail = 1'b1;
-                        send_soc_ifc_sts_txn = 1'b1;
+                    if (ahb_txn.RnW == AHB_WRITE && do_reg_prediction) begin
+                        // Log the step for coverage
+                        next_step = '{status_wr: 1'b1, default: 1'b0};
+                        `uvm_info("PRED_AHB", $sformatf("Logged mailbox step [%p]", next_step), UVM_HIGH)
+                    end
+                    else if (ahb_txn.RnW == AHB_READ && do_reg_prediction) begin
+                        // Log the step for coverage
+                        next_step = '{status_rd: 1'b1, default: 1'b0};
+                        `uvm_info("PRED_AHB", $sformatf("Logged mailbox step [%p]", next_step), UVM_HIGH)
+                    end
+                    else begin
+                        // Log the step for coverage
+                        next_step = '{null_action: 1'b1, default: 1'b0};
+                        `uvm_info("PRED_AHB", $sformatf("Logged mailbox step [%p]", next_step), UVM_HIGH)
                     end
                 end
                 "mbox_unlock": begin
-                    // Reg prediction handled in callback
-                    `uvm_info("PRED_AHB", $sformatf("Handling access to %s.", axs_reg.get_name()), UVM_HIGH)
-                    if (data_active[p_soc_ifc_rm.mbox_csr_rm.mbox_unlock.unlock.get_lsb_pos()]) begin
-// NOTE: This is all delayed now...
-//                        if (p_soc_ifc_rm.mbox_csr_rm.mbox_lock.lock.get_mirrored_value()) begin
-//                            `uvm_error("PRED_AHB", "Write to mbox_unlock with value 1 failed to update the predicted value on mbox_lock of 0!")
-//                        end
-//                        if (p_soc_ifc_rm.mbox_csr_rm.mbox_execute.execute.get_mirrored_value()) begin
-//                            `uvm_error("PRED_AHB", "Write to mbox_unlock with value 1 failed to update the predicted value on mbox_execute of 0!")
-//                        end
-//                        if (!p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.mbox_idle) begin
-//                            `uvm_error("PRED_AHB", "Write to mbox_unlock with value 1 failed to update the predicted value on state signals back to mbox_idle!")
-//                        end
-                        // Force unlock will reset mailbox_data_avail, if set, but
-                        // will not reset any pending interrupts to uC because those
-                        // are sticky
-                        if (mailbox_data_avail) begin
-                            `uvm_info("PRED_AHB", $sformatf("Resetting mailbox_data_avail"), UVM_MEDIUM)
-                            mailbox_data_avail = 1'b0;
-                            send_soc_ifc_sts_txn = 1'b1;
-                        end
+                    if (ahb_txn.RnW == AHB_WRITE && do_reg_prediction && p_soc_ifc_rm.mbox_csr_rm.mbox_unlock.unlock.get_mirrored_value()) begin
+                        // Log the step for coverage
+                        next_step = '{force_unlock: 1'b1, default: 1'b0};
+                        `uvm_info("PRED_AHB", $sformatf("Logged mailbox step [%p]", next_step), UVM_HIGH)
+                    end
+                    else begin
+                        // Log the step for coverage
+                        next_step = '{null_action: 1'b1, default: 1'b0};
+                        `uvm_info("PRED_AHB", $sformatf("Logged mailbox step [%p]", next_step), UVM_HIGH)
                     end
                 end
                 //SHA Accelerator Functions
-                "EXECUTE": begin
-                    // Expect a status transition on sha_notif_intr_pending
-                    // whenever an AHB write changes the value of SHA Accelerator Execute
-                    if (sha_notif_intr_pending ^ p_soc_ifc_rm.sha512_acc_csr_rm.EXECUTE.EXECUTE.get_mirrored_value()) begin
-                        `uvm_info("PRED_AHB", "Write to SHA512 Accel Execute triggers soc_ifc_notif_intr_pending transition", UVM_LOW)
-                        send_cptra_sts_txn = 1'b1;
-                        sha_notif_intr_pending = p_soc_ifc_rm.sha512_acc_csr_rm.EXECUTE.EXECUTE.get_mirrored_value();
+                "LOCK": begin
+                    // Reading sha_lock when it is already locked has no effect, so
+                    // only calculate predictions on acquiring lock (rdata == 0)
+                    // which requires that the AHB transfer was successful in
+                    // performing the access
+                    if (~data_active[p_soc_ifc_rm.sha512_acc_csr_rm.LOCK.LOCK.get_lsb_pos()] &&
+                        p_soc_ifc_rm.sha512_acc_csr_rm.LOCK.LOCK.get_mirrored_value() &&
+                        do_reg_prediction)
+                    begin
+                        // Cannot put this inside the reg callback because the post_predict
+                        // method has no way to access the addr_user value
+                        `uvm_info("PRED_AHB", $sformatf("Predicting new value [0x%x] for sha_user as AHB agent acquires lock",p_soc_ifc_rm.sha512_acc_csr_rm.USER.get_reset("HARD")), UVM_HIGH)
+                        p_soc_ifc_rm.sha512_acc_csr_rm.USER.predict(p_soc_ifc_rm.sha512_acc_csr_rm.USER.get_reset("HARD"));
+                    end
+                    else begin
+                        `uvm_info("PRED_AHB", $sformatf("Access to sha_lock of type %p has no effect", ahb_txn.RnW), UVM_MEDIUM)
+                    end
+                end
+                "USER": begin
+                    if (ahb_txn.RnW == AHB_WRITE) begin
+                        `uvm_warning("PRED_AHB", {"Write to RO register: ", axs_reg.get_name(), " has no effect on system"})
+                    end
+                    else begin
+                        `uvm_info("PRED_AHB", {"Read to ", axs_reg.get_name(), " has no effect on system"}, UVM_MEDIUM)
+                    end
+                end
+                "MODE",
+                "START_ADDRESS",
+                "DLEN",
+                "DATAIN",
+                "EXECUTE",
+                "STATUS",
+                ["DIGEST[0]":"DIGEST[9]"],
+                ["DIGEST[10]":"DIGEST[15]"],
+                "CONTROL": begin
+                    `uvm_info("PRED_AHB", $sformatf("Handling access to %s. Nothing to do.", axs_reg.get_name()), UVM_FULL)
+                end
+                "CPTRA_HW_ERROR_FATAL": begin
+                    if (ahb_txn.RnW == AHB_WRITE && |data_active && (p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_HW_ERROR_FATAL.get_mirrored_value() == 0)) begin
+                        `uvm_info("PRED_AHB", $sformatf("Write to %s results in all bits cleared, but has no effect on cptra_error_fatal (requires reset)", axs_reg.get_name()), UVM_MEDIUM)
+                    end
+                end
+                "CPTRA_HW_ERROR_NON_FATAL": begin
+                    if (p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_HW_ERROR_NON_FATAL.get_mirrored_value() == 0) begin
+                        cptra_error_non_fatal = 1'b0;
+                    end
+                end
+                "CPTRA_FW_ERROR_FATAL": begin
+                    if (ahb_txn.RnW == AHB_WRITE && |(data_active && ~p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_FW_ERROR_FATAL.get_mirrored_value())) begin
+                        `uvm_info("PRED_AHB", $sformatf("Write to %s set a new bit, trigger cptra_error_fatal interrupt", axs_reg.get_name()), UVM_MEDIUM)
+                        cptra_error_fatal = 1'b1;
+                        send_soc_ifc_sts_txn = 1'b1;
+                    end
+                    if (ahb_txn.RnW == AHB_WRITE && |data_active && (p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_FW_ERROR_FATAL.get_mirrored_value() == 0)) begin
+                        `uvm_info("PRED_AHB", $sformatf("Write to %s results in all bits cleared, but has no effect on cptra_error_fatal (requires reset)", axs_reg.get_name()), UVM_MEDIUM)
+                    end
+                end
+                "CPTRA_FW_ERROR_NON_FATAL": begin
+                    if (p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_FW_ERROR_NON_FATAL.get_mirrored_value() == 0) begin
+                        cptra_error_non_fatal = 1'b0;
+                    end
+                end
+                "CPTRA_HW_ERROR_ENC",
+                "CPTRA_FW_ERROR_ENC",
+                ["CPTRA_FW_EXTENDED_ERROR_INFO[0]":"CPTRA_FW_EXTENDED_ERROR_INFO[7]"]: begin
+                    if (ahb_txn.RnW == AHB_WRITE) begin
+                        `uvm_error("PRED_AHB", {"Add prediction for write to ",axs_reg.get_name()," register on AHB interface"}) // TODO
                     end
                 end
+                "CPTRA_BOOT_STATUS": begin
+                    // Handled in callbacks via reg predictor
+                    `uvm_info("PRED_AHB", $sformatf("Handling access to %s. Nothing to do.", axs_reg.get_name()), UVM_DEBUG)
+                end
                 "CPTRA_FLOW_STATUS": begin
                     if (ahb_txn.RnW == AHB_WRITE &&
                         ((p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_FLOW_STATUS.ready_for_fw.get_mirrored_value()      != this.ready_for_fw_push) ||
@@ -753,14 +1142,41 @@ class soc_ifc_predictor #(
                         send_soc_ifc_sts_txn = 1'b0;
                     end
                 end
-                "CPTRA_RESET_REASON": begin
+                "CPTRA_RESET_REASON",
+                "CPTRA_SECURITY_STATE": begin
                     if (ahb_txn.RnW == AHB_WRITE)
                         `uvm_info("PRED_AHB", {"Write to ", axs_reg.get_name(), " has no effect"}, UVM_DEBUG)
                 end
+                ["CPTRA_MBOX_VALID_PAUSER[0]":"CPTRA_MBOX_VALID_PAUSER[4]"]: begin
+                    int idx = axs_reg.get_offset(p_soc_ifc_AHB_map) - p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_MBOX_VALID_PAUSER[0].get_offset(p_soc_ifc_AHB_map);
+                    idx /= 4;
+                    if (mbox_valid_users_locked[idx] && ahb_txn.RnW == AHB_WRITE) begin
+                        `uvm_error("PRED_AHB", {"Write attempted to locked register: ", axs_reg.get_name()})
+                    end
+                    else if (ahb_txn.RnW == AHB_WRITE) begin
+                        `uvm_info("PRED_AHB", {"Write to ", axs_reg.get_name(), " has no effect on system until locked"}, UVM_MEDIUM)
+                    end
+                end
+                ["CPTRA_MBOX_PAUSER_LOCK[0]":"CPTRA_MBOX_PAUSER_LOCK[4]"]: begin
+                    int idx = axs_reg.get_offset(p_soc_ifc_AHB_map) - p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_MBOX_PAUSER_LOCK[0].get_offset(p_soc_ifc_AHB_map);
+                    idx /= 4;
+                    if (mbox_valid_users_locked[idx] && ahb_txn.RnW == AHB_WRITE) begin
+                        `uvm_error("PRED_AHB", {"Write attempted to locked register: ", axs_reg.get_name()})
+                    end
+                    else if (ahb_txn.RnW == AHB_WRITE) begin
+                        mbox_valid_users[idx] = p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_MBOX_VALID_PAUSER[idx].get_mirrored_value(); // VALID_PAUSER field is only applied when locked
+                        mbox_valid_users_locked[idx] |= data_active[p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_MBOX_PAUSER_LOCK[idx].LOCK.get_lsb_pos()];
+                        `uvm_info("PRED_AHB", $sformatf("mbox_valid_users_locked[%d] set to 0x%x, mbox_valid_users[%d] has value: 0x%x", idx, mbox_valid_users_locked[idx], idx, mbox_valid_users[idx]), UVM_MEDIUM)
+                    end
+                    else begin
+                        `uvm_info("PRED_AHB", $sformatf("mbox_valid_users_locked[%d] read value 0x%x, mbox_valid_users[%d] has value: 0x%x", idx, mbox_valid_users_locked[idx], idx, mbox_valid_users[idx]), UVM_HIGH)
+                    end
+                end
                 "CPTRA_TRNG_VALID_PAUSER",
                 "CPTRA_TRNG_PAUSER_LOCK",
                 ["CPTRA_TRNG_DATA[0]" : "CPTRA_TRNG_DATA[9]"],
-                ["CPTRA_TRNG_DATA[10]" : "CPTRA_TRNG_DATA[11]"]: begin
+                ["CPTRA_TRNG_DATA[10]" : "CPTRA_TRNG_DATA[11]"],
+		        "CPTRA_TRNG_CTRL": begin
                     // Handled in callbacks via reg predictor
                     `uvm_info("PRED_AHB", $sformatf("Handling access to %s. Nothing to do.", axs_reg.get_name()), UVM_DEBUG)
                 end
@@ -775,8 +1191,26 @@ class soc_ifc_predictor #(
                         send_soc_ifc_sts_txn = 1'b0;
                     end
                 end
-                "CPTRA_FUSE_WR_DONE": begin
-                    `uvm_error("PRED_AHB", "Unexpected write to CPTRA_FUSE_WR_DONE register on AHB interface")
+                "CPTRA_FUSE_WR_DONE",
+                "CPTRA_TIMER_CONFIG",
+                "CPTRA_BOOTFSM_GO": begin
+                    if (ahb_txn.RnW == AHB_WRITE) begin
+                        `uvm_error("PRED_AHB", $sformatf("Unexpected write to %s register on AHB interface", axs_reg.get_name()))
+                    end
+                end
+                "CPTRA_DBG_MANUF_SERVICE_REG": begin
+                    `uvm_info("PRED_AHB", $sformatf("Handling access to %s. Nothing to do.", axs_reg.get_name()), UVM_DEBUG)
+                end
+                "CPTRA_CLK_GATING_EN": begin
+                    if (ahb_txn.RnW == AHB_WRITE) begin
+                        `uvm_error("PRED_AHB", $sformatf("Unexpected write to %s register on AHB interface", axs_reg.get_name()))
+                    end
+                end
+                "CPTRA_GENERIC_INPUT_WIRES[0]",
+                "CPTRA_GENERIC_INPUT_WIRES[1]": begin
+                    if (ahb_txn.RnW == AHB_WRITE) begin
+                        `uvm_info("PRED_AHB", $sformatf("Write to %s register on AHB interface has no effect", axs_reg.get_name()), UVM_LOW)
+                    end
                 end
                 "CPTRA_GENERIC_OUTPUT_WIRES[0]": begin
                     if (ahb_txn.RnW == AHB_WRITE) begin
@@ -798,9 +1232,9 @@ class soc_ifc_predictor #(
                             32'hfc:
                                 `uvm_info("PRED_AHB", "Observed write to CPTRA_GENERIC_OUTPUT_WIRES [Clear the isr_active bit]", UVM_MEDIUM)
                             32'hfd:
-                                `uvm_info("PRED_AHB", "Observed write to CPTRA_GENERIC_OUTPUT_WIRES [Toggle random SRAM single bit error injection]", UVM_MEDIUM)
+                                `uvm_info("PRED_AHB", "Observed write to CPTRA_GENERIC_OUTPUT_WIRES [Toggle random SRAM single bit flip injection]", UVM_MEDIUM)
                             32'hfe:
-                                `uvm_info("PRED_AHB", "Observed write to CPTRA_GENERIC_OUTPUT_WIRES [Toggle random SRAM double bit error injection]", UVM_MEDIUM)
+                                `uvm_info("PRED_AHB", "Observed write to CPTRA_GENERIC_OUTPUT_WIRES [Toggle random SRAM double bit flip injection]", UVM_MEDIUM)
                             32'hff:
                                 `uvm_info("PRED_AHB", "Observed write to CPTRA_GENERIC_OUTPUT_WIRES to End the simulation with a Success status", UVM_LOW)
                         endcase
@@ -808,15 +1242,143 @@ class soc_ifc_predictor #(
                         generic_output_wires = {generic_output_wires[63:32],data_active}; // FIXME for data width?
                     end
                 end
+                "CPTRA_GENERIC_OUTPUT_WIRES[1]": begin
+                    if (ahb_txn.RnW == AHB_WRITE) begin
+                        send_soc_ifc_sts_txn = data_active != generic_output_wires[63:32];
+                        generic_output_wires = {data_active,generic_output_wires[31:0]}; // FIXME for data width?
+                    end
+                end
+                "CPTRA_HW_REV_ID": begin
+                    if (ahb_txn.RnW == AHB_WRITE) begin
+                        `uvm_warning("PRED_AHB", {"Write to RO register: ", axs_reg.get_name(), " has no effect on system"})
+                    end
+                    else begin
+                        `uvm_info("PRED_AHB", {"Read to ", axs_reg.get_name(), " has no effect on system"}, UVM_MEDIUM)
+                    end
+                end
+                "CPTRA_FW_REV_ID[0]",
+                "CPTRA_FW_REV_ID[1]": begin
+                    `uvm_info("PRED_AHB", {"Access to ", axs_reg.get_name(), " has no effect on system"}, UVM_MEDIUM)
+                end
+                "CPTRA_HW_CONFIG": begin
+                    if (ahb_txn.RnW == AHB_WRITE) begin
+                        `uvm_warning("PRED_AHB", {"Write to RO register: ", axs_reg.get_name(), " has no effect on system"})
+                    end
+                    else begin
+                        `uvm_info("PRED_AHB", {"Read to ", axs_reg.get_name(), " has no effect on system"}, UVM_MEDIUM)
+                    end
+                end
+                "CPTRA_WDT_TIMER1_EN": begin
+                    if (ahb_txn.RnW == AHB_WRITE) begin
+                        `uvm_info("PRED_AHB", {"Detected write to ", axs_reg.get_name()," register on AHB interface, starting WDT timer1"}, UVM_MEDIUM);
+                    end
+                end
+                "CPTRA_WDT_TIMER1_CTRL": begin
+                    if (ahb_txn.RnW == AHB_WRITE && data_active[p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_TIMER1_CTRL.timer1_restart.get_lsb_pos()]) begin
+                        `uvm_info("PRED_AHB", $sformatf("Handling access to %s. This will restart WDT timer1 after 1 clock cycle", axs_reg.get_name()), UVM_MEDIUM);
+                        fork
+                            begin
+                            configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(1);
+                            //Capture restart bit so the counters can be updated
+                            wdt_t1_restart = 1;
+                            `uvm_info("PRED_AHB", $sformatf("After delay from access to %s - restart WDT timer1", axs_reg.get_name()), UVM_MEDIUM);
+                            end
+                        join_none
+                    end
+                end
+                "CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[0]",
+                "CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[1]": begin
+                    if (ahb_txn.RnW == AHB_WRITE) begin
+                        `uvm_info("PRED_AHB", {"Write to ",axs_reg.get_name()," register on AHB interface has no side-effect"}, UVM_HIGH) // TODO
+                    end
+                end
+                "CPTRA_WDT_TIMER2_EN": begin
+                    if (ahb_txn.RnW == AHB_WRITE) begin
+                        `uvm_info("PRED_AHB", {"Detected write to ", axs_reg.get_name(), " register on AHB interface, starting WDT timer2"}, UVM_MEDIUM);
+                    end
+                end
+                "CPTRA_WDT_TIMER2_CTRL": begin
+                    if (ahb_txn.RnW == AHB_WRITE && data_active[p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_TIMER2_CTRL.timer2_restart.get_lsb_pos()]) begin
+                        `uvm_info("PRED_AHB", $sformatf("Handling access to %s. This will restart WDT timer2 after 1 clock cycle", axs_reg.get_name()), UVM_MEDIUM);
+                        fork
+                            begin
+                            configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(1);
+                            //Capture restart bit so the counters can be updated
+                            wdt_t2_restart = 1;
+                            `uvm_info("PRED_AHB", $sformatf("After delay from access to %s - restart WDT timer2", axs_reg.get_name()), UVM_MEDIUM);
+                            end
+                        join_none
+                    end
+                end
+                "CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[0]",
+                "CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[1]": begin
+                    if (ahb_txn.RnW == AHB_WRITE) begin
+                        `uvm_info("PRED_AHB", {"Write to ",axs_reg.get_name()," register on AHB interface has no side-effect"}, UVM_HIGH) // TODO
+                    end
+                end
+                "CPTRA_WDT_STATUS": begin
+                    `uvm_info("PRED_AHB", "AHB access of WDT status", UVM_MEDIUM);
+                end
+                "CPTRA_FUSE_VALID_PAUSER",
+                "CPTRA_FUSE_PAUSER_LOCK": begin
+                    if (ahb_txn.RnW == AHB_WRITE) begin
+                        `uvm_error("PRED_AHB", {"Add prediction for write to ",axs_reg.get_name()," register on AHB interface"}) // TODO
+                    end
+                end
+                ["CPTRA_WDT_CFG[0]":"CPTRA_WDT_CFG[1]"],
+                "CPTRA_iTRNG_ENTROPY_CONFIG_0",
+                "CPTRA_iTRNG_ENTROPY_CONFIG_1",
+                ["CPTRA_RSVD_REG[0]":"CPTRA_RSVD_REG[1]"]: begin
+                    `uvm_info("PRED_AHB", {"Access to ", axs_reg.get_name(), " has no effect on system"}, UVM_MEDIUM)
+                end
+                ["fuse_uds_seed[0]" :"fuse_uds_seed[9]" ],
+                ["fuse_uds_seed[10]":"fuse_uds_seed[11]"]: begin
+                    if (fuse_update_enabled) begin
+                        `uvm_error("PRED_AHB", {"Unexpected write to ", axs_reg.get_name(), " should not occur when fuse_update_enabled == 1!"})
+                        send_cptra_sts_txn       = 1'b1;
+                    end
+                end
+                ["fuse_field_entropy[0]" :"fuse_field_entropy[7]" ]: begin
+                    if (fuse_update_enabled) begin
+                        `uvm_error("PRED_AHB", {"Unexpected write to ", axs_reg.get_name(), " should not occur when fuse_update_enabled == 1!"})
+                        send_cptra_sts_txn       = 1'b1;
+                    end
+                end
+                ["fuse_key_manifest_pk_hash[0]" :"fuse_key_manifest_pk_hash[9]"],
+                ["fuse_key_manifest_pk_hash[10]":"fuse_key_manifest_pk_hash[11]"],
+                "fuse_key_manifest_pk_hash_mask",
+                ["fuse_owner_pk_hash[0]" :"fuse_owner_pk_hash[9]"],
+                ["fuse_owner_pk_hash[10]":"fuse_owner_pk_hash[11]"],
+                "fuse_fmc_key_manifest_svn",
+                ["fuse_runtime_svn[0]":"fuse_runtime_svn[3]"],
+                "fuse_anti_rollback_disable",
+                ["fuse_idevid_cert_attr[0]" :"fuse_idevid_cert_attr[9]"],
+                ["fuse_idevid_cert_attr[10]":"fuse_idevid_cert_attr[19]"],
+                ["fuse_idevid_cert_attr[20]":"fuse_idevid_cert_attr[23]"],
+                ["fuse_idevid_manuf_hsm_id[0]":"fuse_idevid_manuf_hsm_id[3]"],
+                "fuse_life_cycle",
+                "fuse_lms_verify",
+                "fuse_lms_revocation",
+                "fuse_soc_stepping_id",
+                ["internal_obf_key[0]":"internal_obf_key[7]"]: begin
+                    // Handled in callbacks via reg predictor
+                    `uvm_info("PRED_AHB", $sformatf("Handling access to fuse/key/secret register %s. Nothing to do.", axs_reg.get_name()), UVM_DEBUG)
+                end
                 "internal_iccm_lock": begin
                     if (ahb_txn.RnW == AHB_WRITE && !iccm_locked) begin
                         iccm_locked = 1'b1;
+                        `uvm_info("FW_RST_DEBUG", $sformatf("Write to set iccm lock, value is 0x%x", p_soc_ifc_rm.soc_ifc_reg_rm.internal_iccm_lock.lock.get_mirrored_value()), UVM_LOW)
                         send_cptra_sts_txn = 1;
                     end
                     else if (ahb_txn.RnW == AHB_WRITE) begin
                         `uvm_error("PRED_AHB", {"Unexpected write to ",axs_reg.get_name()," register on AHB interface"})
                     end
                 end
+                "internal_fw_update_reset",
+                "internal_fw_update_reset_wait_cycles": begin
+                    // Handled in callbacks via reg predictor
+                    `uvm_info("PRED_AHB", $sformatf("Handling access to register %s. Nothing to do.", axs_reg.get_name()), UVM_DEBUG)
+                end
                 "internal_nmi_vector": begin
                     if (ahb_txn.RnW == AHB_WRITE) begin
                         if (nmi_vector != data_active) begin
@@ -825,26 +1387,65 @@ class soc_ifc_predictor #(
                         end
                     end
                 end
-                default: begin
-                    `uvm_warning("PRED_AHB", $sformatf("Prediction for accesses to register '%s' unimplemented! Fix soc_ifc_predictor", axs_reg.get_name()))
+                "internal_hw_error_fatal_mask",
+                "internal_hw_error_non_fatal_mask",
+                "internal_fw_error_fatal_mask",
+                "internal_fw_error_non_fatal_mask": begin
+                    if (ahb_txn.RnW == AHB_WRITE) begin
+                        `uvm_error("PRED_AHB", $sformatf("FIXME - need to add logic for error mask register %s", axs_reg.get_name())) // TODO
+                    end
+                    else begin
+                        `uvm_info("PRED_AHB", {"Read from ", axs_reg.get_name(), " has no effect"}, UVM_DEBUG)
+                    end
                 end
-            endcase
-        end
+                "internal_rv_mtime_l",
+                "internal_rv_mtime_h",
+                "internal_rv_mtimecmp_l",
+                "internal_rv_mtimecmp_h": begin
+                    if (ahb_txn.RnW == AHB_WRITE) begin
+                        if (timer_intr_pending && mtime_lt_mtimecmp()) begin
+                            `uvm_info("PRED_AHB", $sformatf("Write to %s causes immediate deassertion of timer interrupt", axs_reg.get_name()), UVM_HIGH)
+                            timer_intr_pending = 0;
+//                            send_cptra_sts_txn = 1; // No transaction captured on deassertion
+                        end
+                        else if (timer_intr_pending) begin
+                            `uvm_info("PRED_AHB", $sformatf("Write to %s does not change the status of timer interrupt", axs_reg.get_name()), UVM_HIGH)
+                        end
+                        else if (!timer_intr_pending && mtime_lt_mtimecmp()) begin
+                            `uvm_info("PRED_AHB", $sformatf("Write to %s does not change the status of timer interrupt", axs_reg.get_name()), UVM_HIGH)
+                        end
+                        else if (!timer_intr_pending && !mtime_lt_mtimecmp()) begin
+                            `uvm_info("PRED_AHB", $sformatf("Write to %s causes immediate assertion of timer interrupt", axs_reg.get_name()), UVM_HIGH)
+                            timer_intr_pending = 1;
+                            send_cptra_sts_txn = 1;
+                        end
+                    end
+                    else begin
+                        `uvm_info("PRED_AHB", $sformatf("Read from %s does not change the status of timer interrupt", axs_reg.get_name()), UVM_FULL)
+                    end
+                end
+                default: begin
+                    `uvm_warning("PRED_AHB", $sformatf("Prediction for accesses to register '%s' unimplemented! Fix soc_ifc_predictor", axs_reg.get_name()))
+                end
+            endcase
+        end
         // Interrupt registers have 3-levels of ancestry back to reg_model top
         //                          2-levels of ancestry back to unique parent
         else if (axs_reg.get_parent().get_parent().get_name() == "soc_ifc_reg_rm") begin
             case (axs_reg.get_name()) inside
-                "global_intr_en_r",
+                "global_intr_en_r": begin
+                    if (ahb_txn.RnW == AHB_WRITE) begin
+                        send_cptra_sts_txn = (!this.soc_ifc_error_intr_pending && p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.error_global_intr_r.agg_sts.get_mirrored_value() && p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.global_intr_en_r.error_en.get_mirrored_value()) ||
+                                             (!this.soc_ifc_notif_intr_pending && p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.notif_global_intr_r.agg_sts.get_mirrored_value() && p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.global_intr_en_r.notif_en.get_mirrored_value());
+                        this.soc_ifc_error_intr_pending = p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.error_global_intr_r.agg_sts.get_mirrored_value() && p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.global_intr_en_r.error_en.get_mirrored_value();
+                        this.soc_ifc_notif_intr_pending = p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.notif_global_intr_r.agg_sts.get_mirrored_value() && p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.global_intr_en_r.notif_en.get_mirrored_value();
+                    end
+                end
                 "error_intr_en_r",
                 "notif_intr_en_r",
                 "error_intr_trig_r",
                 "notif_intr_trig_r": begin
-                    if (ahb_txn.RnW == AHB_WRITE) begin
-                        send_cptra_sts_txn = (!this.soc_ifc_error_intr_pending && p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.error_global_intr_r.agg_sts.get_mirrored_value()) ||
-                                             (!this.soc_ifc_notif_intr_pending && p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.notif_global_intr_r.agg_sts.get_mirrored_value());
-                        this.soc_ifc_error_intr_pending = p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.error_global_intr_r.agg_sts.get_mirrored_value();
-                        this.soc_ifc_notif_intr_pending = p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.notif_global_intr_r.agg_sts.get_mirrored_value();
-                    end
+                    `uvm_info("PRED_AHB", $sformatf("Write to %s handled in callback", axs_reg.get_name()), UVM_DEBUG)
                 end
                 "error_global_intr_r",
                 "notif_global_intr_r": begin
@@ -859,8 +1460,32 @@ class soc_ifc_predictor #(
                         // but this does not result in a cptra status transaction because we only
                         // capture rising edges as a transaction
                         `uvm_info("PRED_AHB", {"Write to ", axs_reg.get_name(), " attempts to clear an interrupt"}, UVM_HIGH)
-                        this.soc_ifc_error_intr_pending = p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.error_global_intr_r.agg_sts.get_mirrored_value();
-                        this.soc_ifc_notif_intr_pending = p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.notif_global_intr_r.agg_sts.get_mirrored_value();
+                        
+                        //If the WDT timeout interrupt bits are being cleared, also reset the t1/t2 count values and the corresponding
+                        //interrupt flags (used in wdt_counter_task)
+                        wdt_cascade = (p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_TIMER1_EN.timer1_en.get_mirrored_value() && !(p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_TIMER2_EN.timer2_en.get_mirrored_value()));
+                        wdt_independent = p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_TIMER2_EN.timer2_en.get_mirrored_value();
+                        wdt_t1_timeout = (this.t1_count == {p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[1].timer1_timeout_period.get_mirrored_value(), p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[0].timer1_timeout_period.get_mirrored_value()});
+                        wdt_t2_timeout = (this.t2_count == {p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[1].timer2_timeout_period.get_mirrored_value(), p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[0].timer2_timeout_period.get_mirrored_value()});
+
+                        if (wdt_cascade && wdt_t1_timeout && data_active[`SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_LOW]) begin
+                            this.t1_count = 'h0;
+                            this.t2_count = 'h0;
+                            this.wdt_error_intr_sent = 1'b0;
+                        end
+                        else if (wdt_independent) begin
+                            if (data_active[`SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_LOW]) begin
+                                if (wdt_t1_timeout)
+                                    this.t1_count = 'h0;
+                                this.wdt_error_intr_sent = 1'b0;
+                            end
+                            if (data_active[`SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_LOW]) begin
+                                if (wdt_t2_timeout)
+                                    this.t2_count = 'h0;
+                                this.wdt_t2_error_intr_sent = 1'b0;
+                            end
+                        end
+
                     end
                 end
                 "error_internal_intr_count_r",
@@ -873,7 +1498,10 @@ class soc_ifc_predictor #(
                 "error_wdt_timer2_timeout_intr_count_r",
                 "notif_cmd_avail_intr_count_r",
                 "notif_mbox_ecc_cor_intr_count_r",
-                "notif_debug_locked_intr_count_r": begin
+                "notif_debug_locked_intr_count_r",
+                "notif_scan_mode_intr_count_r",
+                "notif_soc_req_lock_intr_count_r",
+                "notif_gen_in_toggle_intr_count_r": begin
                     if (ahb_txn.RnW == AHB_WRITE) begin
                         `uvm_info("PRED_AHB", {"Write to ", axs_reg.get_name(), " modifies interrupt statistics count"}, UVM_HIGH)
                     end
@@ -891,7 +1519,10 @@ class soc_ifc_predictor #(
                 "error_wdt_timer2_timeout_intr_count_incr_r",
                 "notif_cmd_avail_intr_count_incr_r",
                 "notif_mbox_ecc_cor_intr_count_incr_r",
-                "notif_debug_locked_intr_count_incr_r": begin
+                "notif_debug_locked_intr_count_incr_r",
+                "notif_scan_mode_intr_count_incr_r",
+                "notif_soc_req_lock_intr_count_incr_r",
+                "notif_gen_in_toggle_intr_count_incr_r": begin
                     `uvm_info("PRED_AHB", {"Access to register ", axs_reg.get_name(), " will have no effect on system"}, UVM_HIGH)
                 end
                 default: begin
@@ -903,17 +1534,19 @@ class soc_ifc_predictor #(
         //                          2-levels of ancestry back to unique parent
         else if (axs_reg.get_parent().get_parent().get_name() == "sha512_acc_csr_rm") begin
             case (axs_reg.get_name()) inside
-                "global_intr_en_r",
+                "global_intr_en_r": begin
+                    if (ahb_txn.RnW == AHB_WRITE) begin
+                        send_cptra_sts_txn = (!this.sha_err_intr_pending   && p_soc_ifc_rm.sha512_acc_csr_rm.intr_block_rf_ext.error_global_intr_r.agg_sts.get_mirrored_value() && p_soc_ifc_rm.sha512_acc_csr_rm.intr_block_rf_ext.global_intr_en_r.error_en.get_mirrored_value()) ||
+                                             (!this.sha_notif_intr_pending && p_soc_ifc_rm.sha512_acc_csr_rm.intr_block_rf_ext.notif_global_intr_r.agg_sts.get_mirrored_value() && p_soc_ifc_rm.sha512_acc_csr_rm.intr_block_rf_ext.global_intr_en_r.notif_en.get_mirrored_value());
+                        this.sha_err_intr_pending   = p_soc_ifc_rm.sha512_acc_csr_rm.intr_block_rf_ext.error_global_intr_r.agg_sts.get_mirrored_value() && p_soc_ifc_rm.sha512_acc_csr_rm.intr_block_rf_ext.global_intr_en_r.error_en.get_mirrored_value();
+                        this.sha_notif_intr_pending = p_soc_ifc_rm.sha512_acc_csr_rm.intr_block_rf_ext.notif_global_intr_r.agg_sts.get_mirrored_value() && p_soc_ifc_rm.sha512_acc_csr_rm.intr_block_rf_ext.global_intr_en_r.notif_en.get_mirrored_value();
+                    end
+                end
                 "error_intr_en_r",
                 "notif_intr_en_r",
                 "error_intr_trig_r",
                 "notif_intr_trig_r": begin
-                    if (ahb_txn.RnW == AHB_WRITE) begin
-                        send_cptra_sts_txn = (!this.sha_err_intr_pending   && p_soc_ifc_rm.sha512_acc_csr_rm.intr_block_rf_ext.error_global_intr_r.agg_sts.get_mirrored_value()) ||
-                                             (!this.sha_notif_intr_pending && p_soc_ifc_rm.sha512_acc_csr_rm.intr_block_rf_ext.notif_global_intr_r.agg_sts.get_mirrored_value());
-                        this.sha_err_intr_pending   = p_soc_ifc_rm.sha512_acc_csr_rm.intr_block_rf_ext.error_global_intr_r.agg_sts.get_mirrored_value();
-                        this.sha_notif_intr_pending = p_soc_ifc_rm.sha512_acc_csr_rm.intr_block_rf_ext.notif_global_intr_r.agg_sts.get_mirrored_value();
-                    end
+                    `uvm_info("PRED_AHB", $sformatf("Write to %s handled in callback", axs_reg.get_name()), UVM_DEBUG)
                 end
                 "error_global_intr_r",
                 "notif_global_intr_r": begin
@@ -928,10 +1561,27 @@ class soc_ifc_predictor #(
                         // but this does not result in a cptra status transaction because we only
                         // capture rising edges as a transaction
                         `uvm_info("PRED_AHB", {"Write to ", axs_reg.get_name(), " attempts to clear an interrupt"}, UVM_HIGH)
-                        this.sha_err_intr_pending   = p_soc_ifc_rm.sha512_acc_csr_rm.intr_block_rf_ext.error_global_intr_r.agg_sts.get_mirrored_value();
-                        this.sha_notif_intr_pending = p_soc_ifc_rm.sha512_acc_csr_rm.intr_block_rf_ext.notif_global_intr_r.agg_sts.get_mirrored_value();
                     end
                 end
+                "error0_intr_count_r",
+                "error1_intr_count_r",
+                "error2_intr_count_r",
+                "error3_intr_count_r",
+                "notif_cmd_done_intr_count_r": begin
+                    if (ahb_txn.RnW == AHB_WRITE) begin
+                        `uvm_info("PRED_AHB", {"Write to ", axs_reg.get_name(), " modifies interrupt statistics count"}, UVM_HIGH)
+                    end
+                    else begin
+                        `uvm_info("PRED_AHB", {"Access to register ", axs_reg.get_name(), " will have no effect on system"}, UVM_HIGH)
+                    end
+                end
+                "error0_intr_count_incr_r",
+                "error1_intr_count_incr_r",
+                "error2_intr_count_incr_r",
+                "error3_intr_count_incr_r",
+                "notif_cmd_done_intr_count_incr_r": begin
+                    `uvm_info("PRED_AHB", {"Access to register ", axs_reg.get_name(), " will have no effect on system"}, UVM_HIGH)
+                end
                 default: begin
                     `uvm_warning("PRED_AHB", $sformatf("Prediction for accesses to register '%s' unimplemented! Fix soc_ifc_predictor", axs_reg.get_name()))
                 end
@@ -939,6 +1589,14 @@ class soc_ifc_predictor #(
         end
     end// REG_AXS
 
+    fork
+        begin
+        // This allows coverage subscriber to observe both prev_step and next_step before the transition
+        uvm_wait_for_nba_region();
+        prev_step = next_step;
+        end
+    join_none
+
     // Code for sending output transaction out through soc_ifc_sb_ap
     // Please note that each broadcasted transaction should be a different object than previously
     // broadcasted transactions.  Creation of a different object is done by constructing the transaction
@@ -998,7 +1656,7 @@ class soc_ifc_predictor #(
     apb5_slave_0_ae_debug = t;
 
     `uvm_info("PRED_APB", "Transaction Received through apb5_slave_0_ae", UVM_MEDIUM)
-    `uvm_info("PRED_APB", {"            Data: ",t.convert2string()}, UVM_FULL)
+    `uvm_info("PRED_APB", {"            Data: ",t.convert2string()}, UVM_HIGH)
 
     // Construct one of each output transaction type.
     soc_ifc_sb_ap_output_transaction = soc_ifc_sb_ap_output_transaction_t::type_id::create("soc_ifc_sb_ap_output_transaction");
@@ -1015,15 +1673,34 @@ class soc_ifc_predictor #(
     if (!configuration.enable_reg_prediction) begin
         do_reg_prediction = 1'b0;
     end
+    // This is because of the RDC CLK GATE disablement...
+    else if (rdc_clk_gate_active || noncore_rst_out_asserted) begin
+        do_reg_prediction = 1'b0;
+        soc_ifc_sb_apb_ap_output_transaction.rd_data = 0;
+    end
     else begin
         // Mailbox accesses are discarded based on valid_requester/valid_receiver
         // (i.e. PAUSER + state info)
+        // SHA Accelerator Functions also screened based on PAUSER
         case (axs_reg.get_name()) inside
-            "mbox_lock",
-            "mbox_user",
-            "mbox_unlock": begin
+            "mbox_lock": begin
                 // RS access policy wants to update lock to 1 on a read, but if the PAUSER value is invalid
                 // lock will not be set. It will hold the previous value.
+                if (!(apb_txn.addr_user inside mbox_valid_users) || apb_txn.slave_err) begin
+                    // Access to mbox_lock is dropped if PAUSER is not valid
+                    do_reg_prediction = 1'b0;
+                    // "Expected" read data is 0
+                    soc_ifc_sb_apb_ap_output_transaction.rd_data = 0;
+                    // Complete any scheduled predictions to 0 (due to other delay jobs)
+                    if (p_soc_ifc_rm.mbox_csr_rm.mbox_lock_clr_miss.is_on()) begin
+                        p_soc_ifc_rm.mbox_csr_rm.mbox_lock.lock.predict(0);
+                        `uvm_info("PRED_APB", "Completed mbox_lock deassert prediction (scheduled by mbox_execute) since mbox_lock reg prediction is disabled, due to failed APB transfer", UVM_MEDIUM)
+                        p_soc_ifc_rm.mbox_csr_rm.mbox_lock_clr_miss.reset(0);
+                    end
+                end
+            end
+            "mbox_user",
+            "mbox_unlock": begin
                 if (!(apb_txn.addr_user inside mbox_valid_users) || apb_txn.slave_err) begin
                     // Access to mbox_lock is dropped if PAUSER is not valid
                     do_reg_prediction = 1'b0;
@@ -1077,6 +1754,14 @@ class soc_ifc_predictor #(
                         // "Expected" read data for scoreboard is current
                         // mirrored value prior to running do_predict
                         soc_ifc_sb_apb_ap_output_transaction.rd_data = axs_reg.get_mirrored_value();
+                        // ... unless it's an ECC double bit error, just use the
+                        // observed data to avoid a scoreboard error (since the
+                        // mismatch is anticipated)
+                        if (dataout_mismatch_expected) begin
+                            `uvm_info("PRED_APB", "Ignoring mbox_dataout predicted contents and using observed APB data due to prior ECC double bit flip", UVM_HIGH)
+                            dataout_mismatch_expected = 1'b0;
+                            soc_ifc_sb_apb_ap_output_transaction.rd_data = apb_txn.rd_data;
+                        end
                         dataout_count++;
                     end
                     else begin
@@ -1099,6 +1784,59 @@ class soc_ifc_predictor #(
                     end
                 end
             end
+            //SHA Accelerator Functions
+            "LOCK",
+            "USER": begin
+                if (apb_txn.read_or_write == APB3_TRANS_READ && apb_txn.slave_err) begin
+                    do_reg_prediction = 1'b0;
+                    // "Expected" read data is 0
+                    soc_ifc_sb_apb_ap_output_transaction.rd_data = 0;
+                end
+            end
+            "MODE",
+            "START_ADDRESS",
+            "DLEN": begin
+                if (apb_txn.read_or_write == APB3_TRANS_WRITE) begin
+                    do_reg_prediction = sha_valid_user(apb_txn) && (!apb_txn.slave_err);
+                end
+                else begin
+                    if (apb_txn.slave_err) begin
+                        do_reg_prediction = 1'b0;
+                        // "Expected" read data is 0
+                        soc_ifc_sb_apb_ap_output_transaction.rd_data = 0;
+                    end
+                end
+            end
+            "DATAIN": begin
+                if (apb_txn.slave_err) begin
+                    do_reg_prediction = 1'b0;
+                    // "Expected" read data is 0
+                    soc_ifc_sb_apb_ap_output_transaction.rd_data = 0;
+                end
+            end
+            "EXECUTE": begin
+                if (apb_txn.read_or_write == APB3_TRANS_WRITE) begin
+                    do_reg_prediction = sha_valid_user(apb_txn) && (!apb_txn.slave_err);
+                end
+                else begin
+                    if (apb_txn.slave_err) begin
+                        do_reg_prediction = 1'b0;
+                        // "Expected" read data is 0
+                        soc_ifc_sb_apb_ap_output_transaction.rd_data = 0;
+                    end
+                end
+            end
+            "STATUS",
+            ["DIGEST[0]":"DIGEST[9]"],
+            ["DIGEST[10]":"DIGEST[15]"]:begin
+                if (apb_txn.slave_err) begin
+                    do_reg_prediction = 1'b0;
+                    // "Expected" read data is 0
+                    soc_ifc_sb_apb_ap_output_transaction.rd_data = 0;
+                end
+            end
+            "CONTROL": begin
+            end
             default: begin
                 `uvm_info("PRED_APB", {"Enable reg prediction on access to ", axs_reg.get_name()}, UVM_FULL)
             end
@@ -1117,7 +1855,10 @@ class soc_ifc_predictor #(
     end
 
     // Calculate any other system effects from the register access
-    if (axs_reg == null) begin
+    if (rdc_clk_gate_active || noncore_rst_out_asserted) begin
+        `uvm_info("PRED_APB", {"On access to register: ", axs_reg.get_full_name(), " reset is asserted, skipping system prediction"}, UVM_MEDIUM)
+    end
+    else if (axs_reg == null) begin
         `uvm_error("PRED_APB", $sformatf("APB transaction to address: 0x%x decodes to null from soc_ifc_APB_map", apb_txn.addr))
     end
     else begin
@@ -1139,62 +1880,255 @@ class soc_ifc_predictor #(
                     // Reset counters at beginning of command
                     datain_count = 0;
                     dataout_count = 0;
+                    // Log the step for coverage
+                    next_step = '{lock_acquire: 1'b1, default: 1'b0};
+                    `uvm_info("PRED_APB", $sformatf("Logged mailbox step [%p]", next_step), UVM_HIGH)
                 end
                 else begin
                     `uvm_info("PRED_APB", $sformatf("Access to mbox_lock of type %p has no effect", apb_txn.read_or_write), UVM_MEDIUM)
+                    // Log the step for coverage
+                    next_step = '{null_action: 1'b1, default: 1'b0};
+                    `uvm_info("PRED_APB", $sformatf("Logged mailbox step [%p]", next_step), UVM_HIGH)
+                end
+                void'(check_mbox_no_lock_error(apb_txn, axs_reg));
+                void'(check_mbox_ooo_error(apb_txn, axs_reg));
+                void'(check_mbox_inv_user_error(apb_txn, axs_reg));
+                if (mailbox_data_avail && p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.mbox_error) begin
+                    mailbox_data_avail = 1'b0;
+                    send_soc_ifc_sts_txn = 1'b1;
                 end
             end
             "mbox_user": begin
-                if (apb_txn.read_or_write == APB3_TRANS_WRITE) begin
-                    `uvm_warning("PRED_APB", {"Write to RO register: ", axs_reg.get_name(), " has no effect on system"})
+                if (check_mbox_no_lock_error(apb_txn, axs_reg) || check_mbox_ooo_error(apb_txn, axs_reg)) begin
+                    `uvm_warning("PRED_APB", {"Access to RO register: ", axs_reg.get_name(), " triggers mailbox protocol violation"})
+                end
+                else if (mailbox_data_avail && p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.mbox_error) begin
+                    mailbox_data_avail = 1'b0;
+                    send_soc_ifc_sts_txn = 1'b1;
                 end
                 else begin
                     `uvm_info("PRED_APB", {"Read to ", axs_reg.get_name(), " has no effect on system"}, UVM_MEDIUM)
                 end
+                void'(check_mbox_inv_user_error(apb_txn, axs_reg));
+                // Log the step for coverage
+                next_step = '{null_action: 1'b1, default: 1'b0};
+                `uvm_info("PRED_APB", $sformatf("Logged mailbox step [%p]", next_step), UVM_HIGH)
             end
-            "mbox_execute": begin
-                // Clearing 'execute' - Expect sts pin change
-                if (mailbox_data_avail && !p_soc_ifc_rm.mbox_csr_rm.mbox_execute.execute.get_mirrored_value()) begin
-                    send_soc_ifc_sts_txn = 1;
+            "mbox_cmd": begin
+                void'(check_mbox_no_lock_error(apb_txn, axs_reg));
+                void'(check_mbox_ooo_error(apb_txn, axs_reg));
+                void'(check_mbox_inv_user_error(apb_txn, axs_reg));
+                if (mailbox_data_avail && p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.mbox_error) begin
                     mailbox_data_avail = 1'b0;
+                    send_soc_ifc_sts_txn = 1'b1;
                 end
-                // Setting 'execute' - Expect a uC interrupt if enabled
-                if (!soc_ifc_notif_intr_pending && p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.notif_global_intr_r.agg_sts.get_mirrored_value()) begin
-                    `uvm_info("PRED_APB", "Write to mbox_execute triggers interrupt output", UVM_LOW)
-                    soc_ifc_notif_intr_pending = 1'b1;
-                    send_cptra_sts_txn = 1;
+                if (apb_txn.read_or_write == APB3_TRANS_WRITE &&
+                    do_reg_prediction &&
+                    p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.soc_cmd_stage) begin
+                    // Log the step for coverage
+                    next_step = '{cmd_wr: 1'b1, default: 1'b0};
+                    `uvm_info("PRED_APB", $sformatf("Logged mailbox step [%p]", next_step), UVM_HIGH)
+                end
+                else if (apb_txn.read_or_write == APB3_TRANS_READ && p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.soc_receive_stage) begin
+                    // Log the step for coverage
+                    next_step = '{cmd_rd: 1'b1, default: 1'b0};
+                    `uvm_info("PRED_APB", $sformatf("Logged mailbox step [%p]", next_step), UVM_HIGH)
                 end
                 else begin
-                    if (apb_txn.read_or_write == APB3_TRANS_WRITE) begin
-                        `uvm_info("PRED_APB",
-                                  $sformatf("Write to mbox_execute does not trigger interrupt output due to global_intr_en: [%x] notif_cmd_avail_en: [%x] soc_ifc_notif_intr_pending: [%x]",
-                                            p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.global_intr_en_r.notif_en.get_mirrored_value(),
-                                            p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.notif_intr_en_r.notif_cmd_avail_en.get_mirrored_value(),
-                                            soc_ifc_notif_intr_pending),
-                                  UVM_HIGH)
-                    end
+                    // Log the step for coverage
+                    next_step = '{null_action: 1'b1, default: 1'b0};
+                    `uvm_info("PRED_APB", $sformatf("Logged mailbox step [%p]", next_step), UVM_HIGH)
+                end
+            end
+            "mbox_dlen": begin
+                void'(check_mbox_no_lock_error(apb_txn, axs_reg));
+                void'(check_mbox_ooo_error(apb_txn, axs_reg));
+                void'(check_mbox_inv_user_error(apb_txn, axs_reg));
+                if (p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.mbox_error && mailbox_data_avail) begin
+                    mailbox_data_avail = 1'b0;
+                    send_soc_ifc_sts_txn = 1'b1;
+                end
+                if (apb_txn.read_or_write == APB3_TRANS_WRITE && do_reg_prediction) begin
+                    // Log the step for coverage
+                    if (p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.soc_dlen_stage)
+                        next_step = '{dlen_wr: 1'b1, default: 1'b0};
+                    else if (p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.soc_receive_stage)
+                        next_step = '{resp_dlen_wr: 1'b1, default: 1'b0};
+                    `uvm_info("PRED_APB", $sformatf("Logged mailbox step [%p]", next_step), UVM_HIGH)
+                end
+                else if (apb_txn.read_or_write == APB3_TRANS_READ) begin
+                    // Log the step for coverage
+                    if (p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.soc_receive_stage)
+                        next_step = '{dlen_rd: 1'b1, default: 1'b0};
+                    else if (p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.soc_done_stage)
+                        next_step = '{resp_dlen_rd: 1'b1, default: 1'b0};
+                    `uvm_info("PRED_APB", $sformatf("Logged mailbox step [%p]", next_step), UVM_HIGH)
+                end
+                else begin
+                    // Log the step for coverage
+                    next_step = '{null_action: 1'b1, default: 1'b0};
+                    `uvm_info("PRED_APB", $sformatf("Logged mailbox step [%p]", next_step), UVM_HIGH)
                 end
             end
             "mbox_datain": begin
                 `uvm_info("PRED_APB", $sformatf("Access to mailbox datain, write count: %d", datain_count), UVM_FULL)
+                void'(check_mbox_no_lock_error(apb_txn, axs_reg));
+                void'(check_mbox_ooo_error(apb_txn, axs_reg));
+                void'(check_mbox_inv_user_error(apb_txn, axs_reg));
+                if (mailbox_data_avail && p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.mbox_error) begin
+                    mailbox_data_avail = 1'b0;
+                    send_soc_ifc_sts_txn = 1'b1;
+                end
+                if (apb_txn.read_or_write == APB3_TRANS_WRITE && do_reg_prediction) begin
+                    // Log the step for coverage
+                    if (p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.soc_data_stage)
+                        next_step = '{datain_wr: 1'b1, default: 1'b0};
+                    else
+                        next_step = '{null_action: 1'b1, default: 1'b0};
+                    `uvm_info("PRED_APB", $sformatf("Logged mailbox step [%p]", next_step), UVM_HIGH)
+                end
+                else begin
+                    // Log the step for coverage
+                    next_step = '{null_action: 1'b1, default: 1'b0};
+                    `uvm_info("PRED_APB", $sformatf("Logged mailbox step [%p]", next_step), UVM_HIGH)
+                end
             end
             "mbox_dataout": begin
                 `uvm_info("PRED_APB", $sformatf("Access to mailbox dataout, read count: %d", dataout_count), UVM_FULL)
+                void'(check_mbox_no_lock_error(apb_txn, axs_reg));
+                void'(check_mbox_ooo_error(apb_txn, axs_reg));
+                void'(check_mbox_inv_user_error(apb_txn, axs_reg));
+                if (mailbox_data_avail && p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.mbox_error) begin
+                    mailbox_data_avail = 1'b0;
+                    send_soc_ifc_sts_txn = 1'b1;
+                end
+                // Log the step for coverage
+                next_step = '{null_action: 1'b1, default: 1'b0};
+                if (apb_txn.read_or_write == APB3_TRANS_READ && do_reg_prediction) begin
+                    if (p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.soc_receive_stage) begin
+                        next_step = '{dataout_rd: 1'b1, default: 1'b0};
+                    end
+                    else if (p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.soc_done_stage) begin
+                        next_step = '{resp_dataout_rd: 1'b1, default: 1'b0};
+                    end
+                end
+                `uvm_info("PRED_APB", $sformatf("Logged mailbox step [%p]", next_step), UVM_HIGH)
+            end
+            "mbox_execute": begin
+                void'(check_mbox_no_lock_error(apb_txn, axs_reg));
+                void'(check_mbox_ooo_error(apb_txn, axs_reg));
+                void'(check_mbox_inv_user_error(apb_txn, axs_reg));
+                if (mailbox_data_avail && p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.mbox_error) begin
+                    mailbox_data_avail = 1'b0;
+                    send_soc_ifc_sts_txn = 1'b1;
+                end
+                // Log the step for coverage
+                next_step = '{null_action: 1'b1, default: 1'b0};
+                if (apb_txn.read_or_write == APB3_TRANS_WRITE && do_reg_prediction) begin
+                    // Log the step for coverage
+                    if (p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.soc_data_stage && p_soc_ifc_rm.mbox_csr_rm.mbox_execute.execute.get_mirrored_value()) begin
+                        next_step = '{exec_set: 1'b1, default: 1'b0};
+                    end
+                    else if (p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.soc_done_stage && !p_soc_ifc_rm.mbox_csr_rm.mbox_execute.execute.get_mirrored_value()) begin
+                        next_step = '{exec_clr: 1'b1, default: 1'b0};
+                    end
+                end
+                `uvm_info("PRED_APB", $sformatf("Logged mailbox step [%p]", next_step), UVM_HIGH)
             end
-            "mbox_cmd",
-            "mbox_dlen",
             "mbox_status": begin
-                // Write to mbox_status hands control back to uC
-                if (apb_txn.read_or_write == APB3_TRANS_WRITE && mailbox_data_avail && p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.uc_done_stage) begin
+                void'(check_mbox_no_lock_error(apb_txn, axs_reg));
+                void'(check_mbox_ooo_error(apb_txn, axs_reg));
+                void'(check_mbox_inv_user_error(apb_txn, axs_reg));
+                if (mailbox_data_avail && p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.mbox_error) begin
                     mailbox_data_avail = 1'b0;
                     send_soc_ifc_sts_txn = 1'b1;
                 end
+                if (apb_txn.read_or_write == APB3_TRANS_WRITE && do_reg_prediction) begin
+                    // Log the step for coverage
+                    next_step = '{status_wr: 1'b1, default: 1'b0};
+                    `uvm_info("PRED_APB", $sformatf("Logged mailbox step [%p]", next_step), UVM_HIGH)
+                end
+                else if (apb_txn.read_or_write == APB3_TRANS_READ && do_reg_prediction) begin
+                    // Log the step for coverage
+                    next_step = '{status_rd: 1'b1, default: 1'b0};
+                    `uvm_info("PRED_APB", $sformatf("Logged mailbox step [%p]", next_step), UVM_HIGH)
+                end
+                else begin
+                    // Log the step for coverage
+                    next_step = '{null_action: 1'b1, default: 1'b0};
+                    `uvm_info("PRED_APB", $sformatf("Logged mailbox step [%p]", next_step), UVM_HIGH)
+                end
             end
             "mbox_unlock": begin
-                // Handled in callback
+                void'(check_mbox_no_lock_error(apb_txn, axs_reg));
+                void'(check_mbox_ooo_error(apb_txn, axs_reg));
+                void'(check_mbox_inv_user_error(apb_txn, axs_reg));
+                // Log the step for coverage
+                next_step = '{null_action: 1'b1, default: 1'b0};
+                `uvm_info("PRED_APB", $sformatf("Logged mailbox step [%p]", next_step), UVM_HIGH)
+            end
+            //SHA Accelerator Functions
+            "LOCK": begin 
+                // Reading sha_lock when it is already locked has no effect, so
+                // only calculate predictions on acquiring lock (rdata == 0)
+                // which requires that the AHB transfer was successful in
+                // performing the access
+                if (do_reg_prediction &&
+                    ~apb_txn.rd_data[p_soc_ifc_rm.sha512_acc_csr_rm.LOCK.LOCK.get_lsb_pos()] &&
+                    p_soc_ifc_rm.sha512_acc_csr_rm.LOCK.LOCK.get_mirrored_value())
+                begin
+                    // Cannot put this inside the reg callback because the post_predict
+                    // method has no way to access the addr_user value
+                    `uvm_info("PRED_APB", $sformatf("Predicting new value [0x%x] for sha_user as AHB agent acquires lock",apb_txn.addr_user), UVM_HIGH)
+                    p_soc_ifc_rm.sha512_acc_csr_rm.USER.predict(uvm_reg_data_t'(apb_txn.addr_user));
+                end
+                else begin
+                    `uvm_info("PRED_APB", $sformatf("Access to sha_lock of type %p has no effect", apb_txn.read_or_write), UVM_MEDIUM)
+                end
+            end
+            "USER": begin
+                if (apb_txn.read_or_write == APB3_TRANS_WRITE) begin
+                    `uvm_warning("PRED_APB", {"Write to RO register: ", axs_reg.get_name(), " has no effect on system"})
+                end
+                else begin
+                    `uvm_info("PRED_APB", {"Read to ", axs_reg.get_name(), " has no effect on system"}, UVM_MEDIUM)
+                end
+            end
+            "MODE",
+            "START_ADDRESS",
+            "DLEN",
+            "DATAIN",
+            "EXECUTE",
+            "STATUS",
+            ["DIGEST[0]":"DIGEST[9]"],
+            ["DIGEST[10]":"DIGEST[15]"],
+            "CONTROL": begin
                 `uvm_info("PRED_APB", $sformatf("Handling access to %s. Nothing to do.", axs_reg.get_name()), UVM_FULL)
             end
-            "CPTRA_RESET_REASON": begin
+            "CPTRA_HW_ERROR_FATAL": begin
+                if (apb_txn.read_or_write == APB3_TRANS_WRITE && |apb_txn.wr_data && (p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_HW_ERROR_FATAL.get_mirrored_value() == 0)) begin
+                    `uvm_info("PRED_APB", $sformatf("Write to %s results in all bits cleared, but has no effect on cptra_error_fatal (requires reset)", axs_reg.get_name()), UVM_MEDIUM)
+                end
+            end
+            "CPTRA_HW_ERROR_NON_FATAL": begin
+                if (p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_HW_ERROR_NON_FATAL.get_mirrored_value() == 0) begin
+                    cptra_error_non_fatal = 1'b0;
+                end
+            end
+            "CPTRA_FW_ERROR_FATAL": begin
+                if (apb_txn.read_or_write == APB3_TRANS_WRITE && |apb_txn.wr_data && (p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_FW_ERROR_FATAL.get_mirrored_value() == 0)) begin
+                    `uvm_info("PRED_APB", $sformatf("Write to %s results in all bits cleared, but has no effect on cptra_error_fatal (requires reset)", axs_reg.get_name()), UVM_MEDIUM)
+                end
+            end
+            "CPTRA_FW_ERROR_NON_FATAL": begin
+                if (p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_FW_ERROR_NON_FATAL.get_mirrored_value() == 0) begin
+                    cptra_error_non_fatal = 1'b0;
+                end
+            end
+            "CPTRA_BOOT_STATUS",
+            "CPTRA_FLOW_STATUS",
+            "CPTRA_RESET_REASON",
+            "CPTRA_SECURITY_STATE": begin
                 if (apb_txn.read_or_write == APB3_TRANS_WRITE)
                     `uvm_info("PRED_APB", {"Write to ", axs_reg.get_name(), " has no effect"}, UVM_DEBUG)
             end
@@ -1237,6 +2171,7 @@ class soc_ifc_predictor #(
             end
             "CPTRA_TRNG_VALID_PAUSER",
             "CPTRA_TRNG_PAUSER_LOCK",
+            "CPTRA_TRNG_CTRL",
             "CPTRA_TRNG_STATUS": begin
                 // Handled in callbacks via reg predictor
                 `uvm_info("PRED_APB", $sformatf("Handling access to %s. Nothing to do.", axs_reg.get_name()), UVM_DEBUG)
@@ -1248,54 +2183,129 @@ class soc_ifc_predictor #(
 //                end
             end
             "CPTRA_FUSE_WR_DONE": begin
-                if (apb_txn.wr_data != axs_reg.get() && apb_txn.read_or_write == APB3_TRANS_WRITE)
-                    `uvm_error("PRED_APB", $sformatf("APB transaction with data: 0x%x, write: %p, may not match reg model value: %x", apb_txn.wr_data, apb_txn.read_or_write, axs_reg.get()))
                 // Only expect a status transaction if this fuse download is occuring during boot sequence // FIXME
                 // Even after a warm reset, we expect a write to this register (although the write is dropped)
-                if (noncore_rst_out_asserted && (apb_txn.wr_data == 1/*FIXME hardcoded*/) && apb_txn.read_or_write == APB3_TRANS_WRITE) begin
-                    noncore_rst_out_asserted =  bootfsm_breakpoint;
-                    uc_rst_out_asserted      =  bootfsm_breakpoint;
-                    send_cptra_sts_txn       = !bootfsm_breakpoint;
+                // When writing fuse done, if breakpoint is set we're going to wait state where noncore reset will be de-asserted
+                // SoC or JTAG would check for boot fsm to be in wait state before setting GO when ready to advance and bring uc out of reset
+                if (p_soc_ifc_rm.soc_ifc_reg_rm.boot_fn_state_sigs.boot_fuse &&
+                    apb_txn.wr_data[p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_FUSE_WR_DONE.done.get_lsb_pos()] &&
+                    apb_txn.read_or_write == APB3_TRANS_WRITE)
+                begin
+                    //predict ready for fuses de-assertion
                     p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_FLOW_STATUS.ready_for_fuses.predict(1'b0);
-                    send_soc_ifc_sts_txn = 1'b1;
-                    fuse_update_enabled = 1'b0;
+                    if (bootfsm_breakpoint) begin
+                        // Similar logic should be tied to the fw_update_reset reg callback
+                        p_soc_ifc_rm.soc_ifc_reg_rm.boot_fn_state_sigs = '{boot_wait: 1'b1, default: 1'b0};
+//                        uc_rst_out_asserted = 1; // No transition - this is already asserted on entry to boot_wait by merit of predict_reset("NONCORE")
+                        fw_update_rst_window = 1'b1;
+                        send_cptra_sts_txn = 1'b1;
+                        `uvm_info("PRED_APB", $sformatf("Write to %s results in uc reset assertion and boot FSM state transition to %p", axs_reg.get_name(), p_soc_ifc_rm.soc_ifc_reg_rm.boot_fn_state_sigs), UVM_HIGH)
+                        fork
+                            begin
+                                fw_update_wait_count = p_soc_ifc_rm.soc_ifc_reg_rm.internal_fw_update_reset_wait_cycles.wait_cycles.get_mirrored_value();
+                                repeat(32'(p_soc_ifc_rm.soc_ifc_reg_rm.internal_fw_update_reset_wait_cycles.wait_cycles.get_mirrored_value())) begin
+                                    configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(1);
+                                    if (fw_update_wait_count == 0)
+                                        `uvm_fatal("PRED_APB", "Decrement will underflow!")
+                                    fw_update_wait_count--;
+                                end
+                                if (!bootfsm_breakpoint) begin
+                                    cptra_sb_ap_output_transaction_t local_cptra_sb_ap_txn;
+                                    `uvm_info("PRED_APB", $sformatf("After expiration of fw_update reset counter, bootfsm_breakpoint is already cleared. Submitting transaction prediction immediately for state change."), UVM_HIGH)
+                                    predict_boot_wait_boot_done();
+                                    local_cptra_sb_ap_txn = cptra_sb_ap_output_transaction_t::type_id::create("local_cptra_sb_ap_txn");
+                                    populate_expected_cptra_status_txn(local_cptra_sb_ap_txn); // fw_update_rst_window
+                                    cptra_sb_ap.write(local_cptra_sb_ap_txn);
+                                    `uvm_info("PRED_APB", "Transaction submitted through cptra_sb_ap", UVM_MEDIUM)
+                                end
+                                else begin
+                                    `uvm_info("PRED_APB", $sformatf("After expiration of fw_update reset counter, bootfsm_breakpoint is still set. Predicted state change and reset signal updates will be handled on BOOTFSM_GO."), UVM_HIGH)
+                                end
+                            end
+                        join_none
+                    end
+                    else begin
+                        predict_boot_wait_boot_done();
+//                        send_cptra_sts_txn = 1'b1; // fw_update_rst_window was never asserted
+                        `uvm_info("PRED_APB", $sformatf("Write to %s results in uc reset deassertion and boot FSM state transition to %p", axs_reg.get_name(), p_soc_ifc_rm.soc_ifc_reg_rm.boot_fn_state_sigs), UVM_HIGH)
+                    end
+                    fuse_update_enabled      = 1'b0;
+                    send_soc_ifc_sts_txn     = 1'b1; // for ready_for_fuses
+                end
+                else begin
+                    `uvm_info("PRED_APB", $sformatf("Write to %s has no effect on boot FSM due to state [%p] breakpoint [%d] and txn type [%p]", axs_reg.get_name(), p_soc_ifc_rm.soc_ifc_reg_rm.boot_fn_state_sigs, bootfsm_breakpoint, apb_txn.read_or_write), UVM_FULL)
                 end
             end
             "CPTRA_BOOTFSM_GO": begin
                 // FIXME -- use reg predictor somehow?
-                uvm_reg_data_t fuse_wr_done = p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_FUSE_WR_DONE.get();
+                //When uc reset is still asserted and we're writing to bootfsm go, expect uc to be brough out of reset
+                bit setting_go = apb_txn.read_or_write == APB3_TRANS_WRITE &&
+                                 apb_txn.wr_data[p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_BOOTFSM_GO.GO.get_lsb_pos()];
 
-                if (noncore_rst_out_asserted &&
+                if (p_soc_ifc_rm.soc_ifc_reg_rm.boot_fn_state_sigs.boot_wait &&
                     bootfsm_breakpoint &&
-                    apb_txn.read_or_write == APB3_TRANS_WRITE &&
-                    (apb_txn.wr_data[p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_BOOTFSM_GO.GO.get_lsb_pos()])) begin
+                    setting_go) begin
 
-                    bootfsm_breakpoint = 1'b0;
-                    if (fuse_wr_done[p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_FUSE_WR_DONE.done.get_lsb_pos()]) begin
-                        noncore_rst_out_asserted = 1'b0;
-                        uc_rst_out_asserted      = 1'b0;
-                        send_cptra_sts_txn       = 1'b1;
+                    if (fw_update_wait_count == 0) begin
+                        `uvm_info("PRED_APB", $sformatf("Write to %s results in boot FSM state transition and uC reset deassertion", axs_reg.get_name()), UVM_MEDIUM)
+                        predict_boot_wait_boot_done();
+                        send_cptra_sts_txn = 1'b1; // fw_update_rst_window
+                    end
+                    else begin
+                        // State transition will be triggered in the thread spawned by CPTRA_FUSE_WR_DONE write instead
+                        `uvm_info("PRED_APB", $sformatf("Write to %s clears bootfsm_breakpoint, but state transition is delayed by %d cycles", axs_reg.get_name(), fw_update_wait_count), UVM_HIGH)
                     end
 
                 end
+                else begin
+                    `uvm_info("PRED_APB", $sformatf("Write to %s has no effect on boot FSM due to state [%p] breakpoint [%d] and 'setting_go' [%d]", axs_reg.get_name(), p_soc_ifc_rm.soc_ifc_reg_rm.boot_fn_state_sigs, bootfsm_breakpoint, setting_go), UVM_DEBUG)
+                end
+                bootfsm_breakpoint &= ~setting_go;
+            end
+            "CPTRA_DBG_MANUF_SERVICE_REG": begin
+                `uvm_info("PRED_APB", $sformatf("Handling access to %s. Nothing to do.", axs_reg.get_name()), UVM_DEBUG)
+            end
+            ["CPTRA_WDT_CFG[0]":"CPTRA_WDT_CFG[1]"],
+            "CPTRA_iTRNG_ENTROPY_CONFIG_0",
+            "CPTRA_iTRNG_ENTROPY_CONFIG_1",
+            ["CPTRA_RSVD_REG[0]":"CPTRA_RSVD_REG[1]"]: begin
+                `uvm_info("PRED_APB", {"Access to ", axs_reg.get_name(), " has no effect on system"}, UVM_MEDIUM)
             end
             ["fuse_uds_seed[0]" :"fuse_uds_seed[9]" ],
             ["fuse_uds_seed[10]":"fuse_uds_seed[11]"]: begin
-//                // FIXME -- use reg predictor somehow?
-//                uvm_reg_data_t data = p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_FUSE_WR_DONE.get();
-//                if (!data[p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_FUSE_WR_DONE.done.get_lsb_pos()]) begin
                 if (fuse_update_enabled) begin
                     send_cptra_sts_txn       = 1'b1;
                 end
             end
             ["fuse_field_entropy[0]" :"fuse_field_entropy[7]" ]: begin
-//                // FIXME -- use reg predictor somehow?
-//                uvm_reg_data_t data = p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_FUSE_WR_DONE.get();
-//                if (!data[p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_FUSE_WR_DONE.done.get_lsb_pos()]) begin
                 if (fuse_update_enabled) begin
                     send_cptra_sts_txn       = 1'b1;
                 end
             end
+            ["fuse_key_manifest_pk_hash[0]" :"fuse_key_manifest_pk_hash[9]"],
+            ["fuse_key_manifest_pk_hash[10]":"fuse_key_manifest_pk_hash[11]"],
+            "fuse_key_manifest_pk_hash_mask",
+            ["fuse_owner_pk_hash[0]" :"fuse_owner_pk_hash[9]"],
+            ["fuse_owner_pk_hash[10]":"fuse_owner_pk_hash[11]"],
+            "fuse_fmc_key_manifest_svn",
+            ["fuse_runtime_svn[0]":"fuse_runtime_svn[3]"],
+            "fuse_anti_rollback_disable",
+            ["fuse_idevid_cert_attr[0]" :"fuse_idevid_cert_attr[9]"],
+            ["fuse_idevid_cert_attr[10]":"fuse_idevid_cert_attr[19]"],
+            ["fuse_idevid_cert_attr[20]":"fuse_idevid_cert_attr[23]"],
+            ["fuse_idevid_manuf_hsm_id[0]":"fuse_idevid_manuf_hsm_id[3]"],
+            "fuse_life_cycle",
+            "fuse_lms_verify",
+            "fuse_lms_revocation",
+            "fuse_soc_stepping_id",
+            ["internal_obf_key[0]":"internal_obf_key[7]"]: begin
+                // Handled in callbacks via reg predictor
+                `uvm_info("PRED_APB", $sformatf("Handling access to fuse/key/secret register %s. Nothing to do.", axs_reg.get_name()), UVM_DEBUG)
+            end
+            "internal_iccm_lock": begin
+                // Handled in callbacks via reg predictor
+                `uvm_info("PRED_APB", $sformatf("Handling access to register %s. Nothing to do.", axs_reg.get_name()), UVM_DEBUG)
+            end
             "global_intr_en_r",
             "error_intr_en_r",
             "notif_intr_en_r",
@@ -1311,18 +2321,28 @@ class soc_ifc_predictor #(
             "error_bad_fuse_intr_count_r",
             "error_iccm_blocked_intr_count_r",
             "error_mbox_ecc_unc_intr_count_r",
+            "error_wdt_timer1_timeout_intr_count_r",
+            "error_wdt_timer2_timeout_intr_count_r",
             "notif_cmd_avail_intr_count_r",
             "notif_mbox_ecc_cor_intr_count_r",
             "notif_debug_locked_intr_count_r",
+            "notif_scan_mode_intr_count_r",
+            "notif_soc_req_lock_intr_count_r",
+            "notif_gen_in_toggle_intr_count_r",
             "error_internal_intr_count_incr_r",
             "error_inv_dev_intr_count_incr_r",
             "error_cmd_fail_intr_count_incr_r",
             "error_bad_fuse_intr_count_incr_r",
             "error_iccm_blocked_intr_count_incr_r",
             "error_mbox_ecc_unc_intr_count_incr_r",
+            "error_wdt_timer1_timeout_intr_count_incr_r",
+            "error_wdt_timer2_timeout_intr_count_incr_r",
             "notif_cmd_avail_intr_count_incr_r",
             "notif_mbox_ecc_cor_intr_count_incr_r",
             "notif_debug_locked_intr_count_incr_r",
+            "notif_scan_mode_intr_count_incr_r",
+            "notif_soc_req_lock_intr_count_incr_r",
+            "notif_gen_in_toggle_intr_count_incr_r",
             "error0_intr_count_r",
             "error1_intr_count_r",
             "error2_intr_count_r",
@@ -1351,6 +2371,14 @@ class soc_ifc_predictor #(
         endcase
     end
 
+    fork
+        begin
+        // This allows coverage subscriber to observe both prev_step and next_step before the transition
+        uvm_wait_for_nba_region();
+        prev_step = next_step;
+        end
+    join_none
+
     // Code for sending output transaction out through soc_ifc_sb_ap
     // Please note that each broadcasted transaction should be a different object than previously
     // broadcasted transactions.  Creation of a different object is done by constructing the transaction
@@ -1397,6 +2425,177 @@ endclass
 
 // pragma uvmf custom external begin
 
+// After delay jobs run and update the mailbox model state, calculate
+// any transactions that are newly expected and send to the scoreboard.
+function void soc_ifc_predictor::send_delayed_expected_transactions();
+    bit send_soc_ifc_sts_txn = 0;
+    bit send_cptra_sts_txn = 0;
+
+    //////////////////////////////////////////////////
+    // Construct one of each output transaction type.
+    //
+    soc_ifc_sb_ap_output_transaction = soc_ifc_sb_ap_output_transaction_t::type_id::create("soc_ifc_sb_ap_output_transaction");
+    cptra_sb_ap_output_transaction = cptra_sb_ap_output_transaction_t::type_id::create("cptra_sb_ap_output_transaction");
+
+    //////////////////////////////////////////////////
+    // Check for any updates that may occur as a result of delayed jobs
+    // from the mailbox model
+    //
+    // === mailbox_data_avail ===
+    if (!mailbox_data_avail && p_soc_ifc_rm.mbox_csr_rm.mbox_execute.execute.get_mirrored_value() && p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.soc_receive_stage) begin
+        `uvm_info("PRED_DLY", "Observed mbox_execute being set after delay job, triggering mailbox_data_avail transition", UVM_HIGH)
+        send_soc_ifc_sts_txn = 1'b1;
+        mailbox_data_avail = p_soc_ifc_rm.mbox_csr_rm.mbox_execute.execute.get_mirrored_value();
+    end
+    // Clearing 'execute' - Expect sts pin change
+    // Force unlock will also reset mailbox_data_avail, if set, but
+    // will not reset any pending interrupts to uC because those
+    // are sticky
+    else if (mailbox_data_avail && !p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.soc_receive_stage && !p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.soc_done_stage) begin
+        `uvm_info("PRED_DLY", $sformatf("Resetting mailbox_data_avail"), UVM_HIGH)
+        send_soc_ifc_sts_txn = 1'b1;
+        mailbox_data_avail = 1'b0;
+    end
+    // Write to mbox_status hands control back to SOC
+    // if the status field is updated, the mbox flow has not been
+    // interrupted by an unlock, and system is in
+    // the expected state
+    else if (!mailbox_data_avail && p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.soc_done_stage &&
+        p_soc_ifc_rm.mbox_csr_rm.mbox_status.status.get_mirrored_value() != CMD_BUSY &&
+        !p_soc_ifc_rm.mbox_csr_rm.mbox_unlock.unlock.get_mirrored_value() && p_soc_ifc_rm.mbox_csr_rm.mbox_lock.lock.get_mirrored_value()) begin
+        `uvm_info("PRED_DLY", "Observed transition to soc_done_stage after delay job, triggering mailbox_data_avail transition", UVM_HIGH)
+        mailbox_data_avail = 1'b1;
+        send_soc_ifc_sts_txn = 1'b1;
+    end
+    // Write to mbox_status hands control back to uC
+    else if (mailbox_data_avail && p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.uc_done_stage &&
+             p_soc_ifc_rm.mbox_csr_rm.mbox_status.status.get_mirrored_value() != CMD_BUSY &&
+             !p_soc_ifc_rm.mbox_csr_rm.mbox_unlock.unlock.get_mirrored_value() && p_soc_ifc_rm.mbox_csr_rm.mbox_lock.lock.get_mirrored_value()) begin
+        `uvm_info("PRED_DLY", "Observed transition to uc_done_stage after delay job, triggering mailbox_data_avail deassertion", UVM_HIGH)
+        mailbox_data_avail = 1'b0;
+        send_soc_ifc_sts_txn = 1'b1;
+    end
+    // === soc_ifc_notif_intr_pending ===
+    // Setting 'execute' - Expect a uC interrupt if enabled
+    if (!soc_ifc_notif_intr_pending && p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.notif_global_intr_r.agg_sts.get_mirrored_value() && p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.global_intr_en_r.notif_en.get_mirrored_value()) begin
+        `uvm_info("PRED_DLY", "Delay job triggers soc_ifc notification interrupt output", UVM_HIGH)
+        soc_ifc_notif_intr_pending = 1'b1;
+        send_cptra_sts_txn = 1'b1;
+    end
+    else if (soc_ifc_notif_intr_pending && !(p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.notif_global_intr_r.agg_sts.get_mirrored_value() && p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.global_intr_en_r.notif_en.get_mirrored_value())) begin
+        `uvm_info("PRED_DLY", "Delay job causes soc_ifc notification interrupt deassertion", UVM_HIGH)
+        soc_ifc_notif_intr_pending = 1'b0;
+    end
+
+//    if (!cptra_error_fatal && |p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_HW_ERROR_FATAL.get_mirrored_value()) begin
+//        `uvm_info("PRED_DLY", "Delay job triggers cptra_error_fatal output", UVM_HIGH)
+//        cptra_error_fatal = 1;
+//        send_soc_ifc_sts_txn = 1'b1;
+//    end
+    // mbox protocol violations
+    // TODO The interrupt is cleared by warm reset even though reg values are not - the assertion
+    // should be tied directly to the event detection instead of comparing the interrupt value with the reg mirror value
+    if (!cptra_error_non_fatal && |p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_HW_ERROR_NON_FATAL.get_mirrored_value()) begin
+        `uvm_info("PRED_DLY", "Delay job triggers cptra_error_non_fatal output", UVM_HIGH)
+        cptra_error_non_fatal = 1;
+        send_soc_ifc_sts_txn = 1'b1;
+    end
+
+    // Check for any Error Interrupt
+    if (!soc_ifc_error_intr_pending && p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.error_global_intr_r.agg_sts.get_mirrored_value() && p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.global_intr_en_r.error_en.get_mirrored_value()) begin
+        `uvm_info("PRED_DLY", "Delay job triggers soc_ifc error_intr output", UVM_HIGH)
+        soc_ifc_error_intr_pending = 1'b1;
+        send_cptra_sts_txn = 1'b1;
+    end
+    else if (soc_ifc_error_intr_pending && !(p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.error_global_intr_r.agg_sts.get_mirrored_value() && p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.global_intr_en_r.error_en.get_mirrored_value())) begin
+        `uvm_info("PRED_DLY", "Delay job causes soc_ifc error_intr deassertion", UVM_HIGH)
+        soc_ifc_error_intr_pending = 1'b0;
+        if (p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_STATUS.t1_timeout.get_mirrored_value())
+            p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_STATUS.t1_timeout.predict(1'b0, -1, UVM_PREDICT_READ, UVM_PREDICT, p_soc_ifc_AHB_map);
+        if (p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_STATUS.t2_timeout.get_mirrored_value())
+            p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_STATUS.t2_timeout.predict(1'b0, -1, UVM_PREDICT_READ, UVM_PREDICT, p_soc_ifc_AHB_map);
+    end
+
+    // Check for Timer Interrupt
+    if (timer_intr_pending && mtime_lt_mtimecmp()) begin
+        `uvm_info("PRED_DLY", $sformatf("Detected deassertion of timer interrupt"), UVM_HIGH)
+        timer_intr_pending = 0;
+//        send_cptra_sts_txn = 1; // No transaction captured on deassertion
+    end
+    else if (!timer_intr_pending && !mtime_lt_mtimecmp()) begin
+        `uvm_info("PRED_DLY", $sformatf("Detected assertion of timer interrupt"), UVM_HIGH)
+        timer_intr_pending = 1;
+        send_cptra_sts_txn = 1;
+    end
+
+    // // Check for NMI Interrupt
+    // if (!nmi_intr_pending && p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_HW_ERROR_FATAL.nmi_pin.get_mirrored_value()) begin
+    //     `uvm_info("PRED_DLY", "Delay job triggers nmi interrupt output", UVM_MEDIUM)
+    //     nmi_intr_pending = 1'b1;
+    //     send_cptra_sts_txn = 1'b1;
+    // end
+
+    // SHA Accel Notification Interrupt
+    // Expect a status transition on sha_notif_intr_pending
+    // whenever a write changes the value of SHA Accelerator Execute
+    // and triggers a delayed prediction job resulting in interrupt firing
+    if (!sha_notif_intr_pending && p_soc_ifc_rm.sha512_acc_csr_rm.intr_block_rf_ext.notif_global_intr_r.agg_sts.get_mirrored_value() && p_soc_ifc_rm.sha512_acc_csr_rm.intr_block_rf_ext.global_intr_en_r.notif_en.get_mirrored_value()) begin
+        sha_notif_intr_pending = 1;
+        if (sha_notif_intr_pending) begin
+            `uvm_info("PRED_DLY", "Delay job triggers sha_notif_intr_pending transition", UVM_HIGH)
+            send_cptra_sts_txn = 1'b1;
+        end
+    end
+    else if (sha_notif_intr_pending && !(p_soc_ifc_rm.sha512_acc_csr_rm.intr_block_rf_ext.notif_global_intr_r.agg_sts.get_mirrored_value() && p_soc_ifc_rm.sha512_acc_csr_rm.intr_block_rf_ext.global_intr_en_r.notif_en.get_mirrored_value())) begin
+        `uvm_info("PRED_DLY", "Delay job causes sha512_acc notification interrupt deassertion", UVM_HIGH)
+        sha_notif_intr_pending = 1'b0;
+    end
+
+    ///////////////// ORDERING MUST BE PRESERVED FOR THESE ASSIGNMENTS /////////////////
+    // Check for uC reset changes (both transitions due to delay job
+    // scheduled from internal_fw_update_reset callback)
+    if (p_soc_ifc_rm.soc_ifc_reg_rm.boot_fn_state_sigs.boot_wait && !uc_rst_out_asserted) begin
+        uc_rst_out_asserted = 1;
+        send_cptra_sts_txn = 1;
+    end
+    // uC reset deassertion is delayed from iccm_lock and fw_update_rst_window transitions
+    else if (p_soc_ifc_rm.soc_ifc_reg_rm.boot_fn_state_sigs.boot_done && !iccm_locked && !fw_update_rst_window && uc_rst_out_asserted) begin
+        uc_rst_out_asserted = 0;
+        send_cptra_sts_txn = 1;
+    end
+
+    if ((p_soc_ifc_rm.soc_ifc_reg_rm.boot_fn_state_sigs.boot_fw_rst || p_soc_ifc_rm.soc_ifc_reg_rm.boot_fn_state_sigs.boot_wait) && !fw_update_rst_window) begin
+        fw_update_rst_window = 1;
+        send_cptra_sts_txn = 1;
+    end
+    else if (p_soc_ifc_rm.soc_ifc_reg_rm.boot_fn_state_sigs.boot_done && fw_update_rst_window) begin
+        fw_update_rst_window = 0;
+        send_cptra_sts_txn = 1;
+    end
+
+    // Check for iccm unlock change
+    if (iccm_locked && ~|p_soc_ifc_rm.soc_ifc_reg_rm.internal_iccm_lock.lock.get_mirrored_value()) begin
+        `uvm_info("PRED_DLY", $sformatf("Detected de-assertion of ICCM LOCK"), UVM_LOW)
+        iccm_locked = 0;
+        send_cptra_sts_txn = 1;
+    end
+    /////////////////            END ORDERED ASSIGNMENTS            /////////////////
+
+    //////////////////////////////////////////////////
+    // Send expected transactions to Scoreboard
+    //
+    if (send_soc_ifc_sts_txn) begin
+        populate_expected_soc_ifc_status_txn(soc_ifc_sb_ap_output_transaction);
+        soc_ifc_sb_ap.write(soc_ifc_sb_ap_output_transaction);
+        `uvm_info("PRED_DLY", "Transaction submitted through soc_ifc_sb_ap", UVM_MEDIUM)
+    end
+    if (send_cptra_sts_txn) begin
+        populate_expected_cptra_status_txn(cptra_sb_ap_output_transaction);
+        cptra_sb_ap.write(cptra_sb_ap_output_transaction);
+        `uvm_info("PRED_DLY", "Transaction submitted through cptra_sb_ap", UVM_MEDIUM)
+    end
+endfunction
+
 // Time-delay jobs may be scheduled in the register model by a callback if
 // it requires some time to elapse before e.g. updating mirror values.
 // This task detects those scheduled jobs and runs them after waiting for
@@ -1406,9 +2605,28 @@ task soc_ifc_predictor::poll_and_run_delay_jobs();
         while (p_soc_ifc_rm.delay_jobs.size() > 0) begin
             fork
                 soc_ifc_reg_delay_job job = p_soc_ifc_rm.delay_jobs.pop_front();
-                begin
-                    configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(job.get_delay_cycles());
+                if (!noncore_rst_out_asserted) begin
+                    int idx[$];
+                    time end_time;
+                    running_dly_jobs.push_back(process::self()); // This tracks all the delay_jobs that are pending so they can be clobbered on rst
+                    `uvm_info("PRED_DLY", $sformatf("Doing delay of %0d cycles before running delay job with signature: %s", job.get_delay_cycles(), job.get_name()), UVM_HIGH/*UVM_FULL*/)
+                    end_time = $time + 10*job.get_delay_cycles();
+                    job_end_count[end_time] += 1;
+                    // delay cycles reported as 0's based value, since 1-cycle delay
+                    // is inherent to this forever loop
+                    if (job.get_delay_cycles()) configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(job.get_delay_cycles());
+                    uvm_wait_for_nba_region();
+                    idx = running_dly_jobs.find_first_index(pr) with (pr == process::self());
+                    running_dly_jobs.delete(idx.pop_front());
                     job.do_job();
+                    job_end_count[end_time] -= 1;
+//                    p_soc_ifc_rm.sample_values(); /* Sample coverage after completing any delayed prediction/mirror updates */ // NOTE: Added sample post_predict callback to reg fields instead
+                    // Aggregate the results of all delay jobs that end on the same clock cycle into a
+                    // single method call that sends all the predited transactions
+                    if (job_end_count[end_time] == 0) begin
+                        job_end_count.delete(end_time);
+                        send_delayed_expected_transactions();
+                    end
                 end
             join_none
         end
@@ -1416,23 +2634,461 @@ task soc_ifc_predictor::poll_and_run_delay_jobs();
     end
 endtask
 
-function bit soc_ifc_predictor::soc_ifc_status_txn_expected_after_warm_reset();
-    /* FIXME calculate this from the reg-model somehow? */
-    return p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_FLOW_STATUS.ready_for_fuses.get_mirrored_value() || ready_for_fw_push || ready_for_runtime || mailbox_data_avail || |generic_output_wires /*|| trng_req_pending*/; /* only expect a soc_ifc_status_transaction if some signal will transition */
+function bit soc_ifc_predictor::check_mbox_no_lock_error(soc_ifc_sb_apb_ap_output_transaction_t txn, uvm_reg axs_reg);
+    soc_ifc_reg_delay_job_mbox_csr_mbox_prot_error error_job;
+    uvm_reg_field fld;
+    bit is_error = 0;
+    if (!p_soc_ifc_rm.mbox_csr_rm.mbox_lock.lock.get_mirrored_value() && txn.addr_user inside mbox_valid_users) begin
+        case (axs_reg.get_name()) inside
+            "mbox_lock": begin
+                fld = axs_reg.get_field_by_name("lock");
+                is_error = txn.read_or_write == APB3_TRANS_WRITE;
+            end
+            "mbox_user": begin
+                fld = axs_reg.get_field_by_name("user");
+                is_error = txn.read_or_write == APB3_TRANS_WRITE;
+            end
+            "mbox_cmd": begin
+                fld = axs_reg.get_field_by_name("command");
+                is_error = txn.read_or_write == APB3_TRANS_WRITE;
+            end
+            "mbox_dlen": begin
+                fld = axs_reg.get_field_by_name("length");
+                is_error = txn.read_or_write == APB3_TRANS_WRITE;
+            end
+            "mbox_datain": begin
+                fld = axs_reg.get_field_by_name("datain");
+                is_error = txn.read_or_write == APB3_TRANS_WRITE;
+            end
+            "mbox_dataout": begin
+                fld = axs_reg.get_field_by_name("dataout");
+                is_error = 1;
+            end
+            "mbox_execute": begin
+                fld = axs_reg.get_field_by_name("execute");
+                is_error = txn.read_or_write == APB3_TRANS_WRITE;
+            end
+            "mbox_status": begin
+                fld = axs_reg.get_field_by_name("status");
+                is_error = txn.read_or_write == APB3_TRANS_WRITE;
+            end
+            "mbox_unlock": begin
+                fld = axs_reg.get_field_by_name("unlock");
+                is_error = txn.read_or_write == APB3_TRANS_WRITE;
+            end
+            default: begin
+                `uvm_error("MBOX_NO_LOCK_CHK", "This function should not be called for access to non-mailbox regs")
+            end
+        endcase
+    end
+    if (is_error) begin
+        error_job = soc_ifc_reg_delay_job_mbox_csr_mbox_prot_error::type_id::create("error_job");
+        error_job.rm = p_soc_ifc_rm.mbox_csr_rm;
+        error_job.map = p_soc_ifc_APB_map;
+        error_job.fld = fld;
+        error_job.set_delay_cycles(0);
+        error_job.state_nxt = MBOX_IDLE;
+        error_job.error = '{axs_without_lock: 1'b1, default: 1'b0};
+        p_soc_ifc_rm.delay_jobs.push_back(error_job);
+        `uvm_info("MBOX_NO_LOCK_CHK",
+                  $sformatf("%s to %s on map [%s] with value [%x] causes a mbox no_lock protocol violation. Delay job is queued to update DUT model.",
+                            txn.read_or_write.name(),
+                            fld.get_name(),
+                            p_soc_ifc_APB_map.get_name(),
+                            txn.read_or_write == APB3_TRANS_WRITE ? txn.wr_data : txn.rd_data),
+                  UVM_LOW)
+    end
+    return is_error;
 endfunction
 
-function bit soc_ifc_predictor::cptra_status_txn_expected_after_warm_reset();
+function bit soc_ifc_predictor::check_mbox_ooo_error(soc_ifc_sb_apb_ap_output_transaction_t txn, uvm_reg axs_reg);
+    soc_ifc_reg_delay_job_mbox_csr_mbox_prot_error error_job;
+    uvm_reg_field fld;
+    bit is_error = 0;
+    // Only check for access-out-of-order errors here that will not be caught
+    // by reg prediction callbacks.
+    // That means that register accesses where valid_requester/valid_receiver is false
+    // (as applicable to the register in question) might trigger an error if the inverse
+    // is true (valid_receiver/valid_requester).
+    // When !soc_has_lock, valid_receiver must be true for any writes made,
+    // but not necessarily valid_requester.
+    // Since valid_requester may be false, the reg_prediction is not done, and
+    // thus the callback can't catch this scenario.
+    if (txn.addr_user inside mbox_valid_users) begin
+        case (axs_reg.get_name()) inside
+            "mbox_lock": begin
+                fld = axs_reg.get_field_by_name("lock");
+                is_error = txn.read_or_write == APB3_TRANS_WRITE && !p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.mbox_idle;
+            end
+            "mbox_user": begin
+                fld = axs_reg.get_field_by_name("user");
+                is_error = txn.read_or_write == APB3_TRANS_WRITE && !p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.mbox_idle;
+            end
+            "mbox_cmd": begin
+                fld = axs_reg.get_field_by_name("command");
+                is_error = txn.read_or_write == APB3_TRANS_WRITE &&  valid_receiver(txn) && !valid_requester(txn);
+            end
+            "mbox_dlen": begin
+                fld = axs_reg.get_field_by_name("length");
+                is_error = txn.read_or_write == APB3_TRANS_WRITE &&  valid_receiver(txn) && !valid_requester(txn);
+            end
+            "mbox_datain": begin
+                fld = axs_reg.get_field_by_name("datain");
+                is_error = txn.read_or_write == APB3_TRANS_WRITE &&  valid_receiver(txn) && !valid_requester(txn);
+            end
+            "mbox_dataout": begin
+                fld = axs_reg.get_field_by_name("dataout");
+                is_error =                                          !valid_receiver(txn) &&  valid_requester(txn);
+            end
+            "mbox_execute": begin
+                fld = axs_reg.get_field_by_name("execute");
+                is_error = txn.read_or_write == APB3_TRANS_WRITE &&  valid_receiver(txn) && !valid_requester(txn);
+            end
+            "mbox_status": begin
+                fld = axs_reg.get_field_by_name("status");
+                is_error = txn.read_or_write == APB3_TRANS_WRITE && !valid_receiver(txn) &&  valid_requester(txn);
+            end
+            "mbox_unlock": begin
+                fld = axs_reg.get_field_by_name("unlock");
+                is_error = txn.read_or_write == APB3_TRANS_WRITE && !p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.mbox_idle;
+            end
+            default: begin
+                `uvm_error("MBOX_OOO_CHK", "This function should not be called for access to non-mailbox regs")
+            end
+        endcase
+    end
+    if (is_error && p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.mbox_error) begin
+        `uvm_info("MBOX_OOO_CHK",
+                  $sformatf("%s to %s on map [%s] with value [%x] calculates as a mbox out_of_order protocol violation, but no delay job is scheduled since predictor is already in state [%p].",
+                            txn.read_or_write.name(),
+                            fld.get_name(),
+                            p_soc_ifc_APB_map.get_name(),
+                            txn.read_or_write == APB3_TRANS_WRITE ? txn.wr_data : txn.rd_data,
+                            p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs),
+                  UVM_LOW)
+    end
+    else if (is_error) begin
+        error_job = soc_ifc_reg_delay_job_mbox_csr_mbox_prot_error::type_id::create("error_job");
+        error_job.rm = p_soc_ifc_rm.mbox_csr_rm;
+        error_job.map = p_soc_ifc_APB_map;
+        error_job.fld = fld;
+        error_job.set_delay_cycles(0);
+        error_job.state_nxt = MBOX_ERROR;
+        error_job.error = '{axs_incorrect_order: 1'b1, default: 1'b0};
+        p_soc_ifc_rm.delay_jobs.push_back(error_job);
+        `uvm_info("MBOX_OOO_CHK", $sformatf("%s to %s on map [%s] with value [%x] causes a mbox out_of_order protocol violation. Delay job is queued to update DUT model.", txn.read_or_write.name(), fld.get_name(), p_soc_ifc_APB_map.get_name(), txn.read_or_write == APB3_TRANS_WRITE ? txn.wr_data : txn.rd_data), UVM_LOW)
+        p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs = '{mbox_error: 1'b1, default: 1'b0};
+    end
+    return is_error;
+endfunction
+
+function bit soc_ifc_predictor::check_mbox_inv_user_error(soc_ifc_sb_apb_ap_output_transaction_t txn, uvm_reg axs_reg);
+    bit is_error = 0;
+    // The invalid PAUSER error is only flagged for write attempts by an agent
+    // that is considered 'valid', but which currently doesn't have lock
+    // (exception: reads to mbox_dataout while not holding lock also flagged)
+    if (txn.addr_user inside mbox_valid_users) begin
+        case (axs_reg.get_name()) inside
+            "mbox_lock":    is_error = txn.read_or_write == APB3_TRANS_WRITE && !(valid_requester(txn)                       );
+            "mbox_user":    is_error = txn.read_or_write == APB3_TRANS_WRITE && !(valid_requester(txn)                       );
+            "mbox_cmd":     is_error = txn.read_or_write == APB3_TRANS_WRITE && !(valid_requester(txn)                       );
+            "mbox_dlen":    is_error = txn.read_or_write == APB3_TRANS_WRITE && !(valid_requester(txn) || valid_receiver(txn));
+            "mbox_datain":  is_error = txn.read_or_write == APB3_TRANS_WRITE && !(valid_requester(txn)                       );
+            "mbox_dataout": is_error =                                          !(valid_requester(txn) || valid_receiver(txn));
+            "mbox_execute": is_error = txn.read_or_write == APB3_TRANS_WRITE && !(valid_requester(txn)                       );
+            "mbox_status":  is_error = txn.read_or_write == APB3_TRANS_WRITE && !(valid_requester(txn) || valid_receiver(txn));
+            // Unwriteable via APB, but writes still don't flag a PAUSER invalid error
+            "mbox_unlock":  is_error = txn.read_or_write == APB3_TRANS_WRITE && !(valid_requester(txn)                       );
+            default: `uvm_error("MBOX_INV_USER_CHK", "This function should not be called for access to non-mailbox regs")
+        endcase
+    end
+    if (is_error) begin
+        p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.error_internal_intr_r.error_inv_dev_sts.predict(1'b1, -1, UVM_PREDICT_READ, UVM_PREDICT, p_soc_ifc_AHB_map); /* AHB-access only, use AHB map*/
+        `uvm_info("MBOX_INV_USER_CHK", $sformatf("%s to %s on map [%s] with user [0x%x] causes a mbox invalid PAUSER detection.", txn.read_or_write.name(), axs_reg.get_name(), p_soc_ifc_APB_map.get_name(), txn.addr_user), UVM_LOW)
+    end
+    return is_error;
+endfunction
+
+task soc_ifc_predictor::update_mtime_mirrors();
+    typedef longint unsigned mtime_type;
+    mtime_type mtime;
+    mtime_type new_mtime;
+
+    mtime = p_soc_ifc_rm.soc_ifc_reg_rm.internal_rv_mtime_l.count_l.get_mirrored_value() |
+            p_soc_ifc_rm.soc_ifc_reg_rm.internal_rv_mtime_h.count_h.get_mirrored_value() << 32;
+    new_mtime = mtime + 1; // In clock cycles
+
+    fork
+        if (p_soc_ifc_rm.soc_ifc_reg_rm.internal_rv_mtime_l.is_busy()) begin
+            uvm_wait_for_nba_region();
+            // If mtime_l transitions from busy to not busy on the current clock edge, leave the mirror at the value it just acquired instead of overwriting
+            // (unless the value was not updated by the recent transfer, e.g. because it was an APB transfer)
+            // Else, predict a new value (which will be overwritten later when the active transfer completes)
+            if (p_soc_ifc_rm.soc_ifc_reg_rm.internal_rv_mtime_l.is_busy() || (mtime[31:00] == p_soc_ifc_rm.soc_ifc_reg_rm.internal_rv_mtime_l.count_l.get_mirrored_value())) begin
+                p_soc_ifc_rm.soc_ifc_reg_rm.internal_rv_mtime_l.count_l.predict(new_mtime[31:00], .kind(UVM_PREDICT_WRITE), .path(UVM_PREDICT), .map(p_soc_ifc_AHB_map));
+            end
+            new_mtime[31:00] = p_soc_ifc_rm.soc_ifc_reg_rm.internal_rv_mtime_l.count_l.get_mirrored_value();
+        end
+        else begin
+            p_soc_ifc_rm.soc_ifc_reg_rm.internal_rv_mtime_l.count_l.predict(new_mtime[31:00]);
+        end
+        if (p_soc_ifc_rm.soc_ifc_reg_rm.internal_rv_mtime_h.is_busy()) begin
+            uvm_wait_for_nba_region();
+            // If mtime_h transitions from busy to not busy on the current clock edge, leave the mirror at the value it just acquired instead of overwriting
+            // (unless the value was not updated by the recent transfer, e.g. because it was an APB transfer)
+            // Else, predict a new value (which will be overwritten later when the active transfer completes)
+            if (p_soc_ifc_rm.soc_ifc_reg_rm.internal_rv_mtime_h.is_busy() || (mtime[63:32] == p_soc_ifc_rm.soc_ifc_reg_rm.internal_rv_mtime_h.count_h.get_mirrored_value())) begin
+                p_soc_ifc_rm.soc_ifc_reg_rm.internal_rv_mtime_h.count_h.predict(new_mtime[63:32], .kind(UVM_PREDICT_WRITE), .path(UVM_PREDICT), .map(p_soc_ifc_AHB_map));
+            end
+            new_mtime[63:32] = p_soc_ifc_rm.soc_ifc_reg_rm.internal_rv_mtime_h.count_h.get_mirrored_value();
+        end
+        else begin
+            p_soc_ifc_rm.soc_ifc_reg_rm.internal_rv_mtime_h.count_h.predict(new_mtime[63:32]);
+        end
+    join
+
+    `uvm_info("PRED", $sformatf("Updated mtime register mirrors to 0x%x", new_mtime), UVM_DEBUG)
+endtask
+
+// Increment mtime every clock cycle
+task soc_ifc_predictor::mtime_counter_task();
+    forever begin
+        configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(1);
+        if (cptra_pwrgood_asserted) begin
+            update_mtime_mirrors();
+            send_delayed_expected_transactions();
+        end
+    end
+endtask
+
+function bit soc_ifc_predictor::mtime_lt_mtimecmp();
+    longint unsigned mtime;
+    longint unsigned mtimecmp;
+
+    mtime = p_soc_ifc_rm.soc_ifc_reg_rm.internal_rv_mtime_l.count_l.get_mirrored_value() |
+            p_soc_ifc_rm.soc_ifc_reg_rm.internal_rv_mtime_h.count_h.get_mirrored_value() << 32;
+    mtimecmp = p_soc_ifc_rm.soc_ifc_reg_rm.internal_rv_mtimecmp_l.compare_l.get_mirrored_value() |
+               p_soc_ifc_rm.soc_ifc_reg_rm.internal_rv_mtimecmp_h.compare_h.get_mirrored_value() << 32;
+
+    return mtime < mtimecmp;
+endfunction
+
+//If WDT is enabled via reg write, emulate behavior here
+task soc_ifc_predictor::wdt_counter_task();
+    bit timer1_debug_flag, timer2_debug_flag;
+    forever begin
+        uvm_reg_data_t wdt_reg_data;
+        logic wdt_t1_en;
+        logic wdt_t2_en;
+        logic cascade, independent;
+        logic [63:0] wdt_t1_period, wdt_t2_period;
+        bit wdt_t1_restart_temp;
+
+        cptra_sb_ap_output_transaction_t local_cptra_sb_ap_txn;
+        soc_ifc_sb_ap_output_transaction_t local_soc_ifc_sb_ap_txn;
+        local_cptra_sb_ap_txn = cptra_sb_ap_output_transaction_t::type_id::create("local_cptra_sb_ap_txn");
+        local_soc_ifc_sb_ap_txn = soc_ifc_sb_ap_output_transaction_t::type_id::create("local_soc_ifc_sb_ap_txn");
+
+        //Poll for WDT enable bits
+        wdt_reg_data = p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_TIMER1_EN.timer1_en.get(); //_mirrored_value();
+        wdt_t1_en = wdt_reg_data[0];
+
+        wdt_reg_data = p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_TIMER2_EN.timer2_en.get(); //_mirrored_value();
+        wdt_t2_en = wdt_reg_data[0];
+    
+        cascade = (wdt_t1_en && !wdt_t2_en);
+        independent = wdt_t2_en;
+
+        wdt_reg_data = p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[0].timer1_timeout_period.get_mirrored_value();
+        wdt_t1_period[31:0] = wdt_reg_data[31:0];
+        wdt_reg_data = p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[1].timer1_timeout_period.get_mirrored_value();
+        wdt_t1_period[63:32] = wdt_reg_data[31:0];
+
+        wdt_reg_data = p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[0].timer2_timeout_period.get_mirrored_value();
+        wdt_t2_period[31:0] = wdt_reg_data[31:0];
+        wdt_reg_data = p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[1].timer2_timeout_period.get_mirrored_value();
+        wdt_t2_period[63:32] = wdt_reg_data[31:0];
+
+        //Reset event
+        if (this.reset_wdt_count) begin
+            `uvm_info("PRED_WDT", "Resetting WDT t1 and t2 counts due to a reset event", UVM_HIGH)
+            this.t1_count = 'h0;
+            this.t2_count = 'h0;
+            this.wdt_error_intr_sent = 1'b0;
+            this.wdt_t2_error_intr_sent = 1'b0;
+            this.wdt_nmi_intr_sent = 1'b0;
+            p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_STATUS.t1_timeout.predict(1'b0, -1, UVM_PREDICT_READ, UVM_PREDICT, p_soc_ifc_AHB_map);
+            p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_STATUS.t2_timeout.predict(1'b0, -1, UVM_PREDICT_READ, UVM_PREDICT, p_soc_ifc_AHB_map);
+        end
+
+        //Cascade mode
+        if (cascade) begin
+            if (this.wdt_t1_restart && !p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_STATUS.t1_timeout.get_mirrored_value()) begin
+                this.t1_count = 'h0;
+                `uvm_info("PRED_WDT", "Cascade mode, received t1 pet - restarting t1 count", UVM_MEDIUM)
+                this.wdt_t1_restart = 1'b0; //Reset flag so we can capture another restart event
+            end
+            else if (this.t1_count != wdt_t1_period) begin
+                this.t1_count++;
+                if (!($time % 500))
+                    `uvm_info("PRED_WDT", $sformatf("In cascade mode. t1_count increments to 0x%x, wdt_to_period is 0x%x", this.t1_count, wdt_t1_period), UVM_DEBUG)
+            end
+            else begin
+                //T1 expired, so send out soc error intr, and start t2 counter
+                if (!this.wdt_error_intr_sent) begin
+                    `uvm_info("PRED_WDT", "Timer1 expired in cascade mode. Starting timer2", UVM_MEDIUM)
+                    p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.error_internal_intr_r.error_wdt_timer1_timeout_sts.predict(1'b1, -1, UVM_PREDICT_READ, UVM_PREDICT, p_soc_ifc_AHB_map);
+                    p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_STATUS.t1_timeout.predict(1'b1, -1, UVM_PREDICT_READ, UVM_PREDICT, p_soc_ifc_AHB_map);
+                    //Set a flag so we don't keep sending transactions while the timer holds value until interrupt
+                    //is serviced or reset
+                    this.wdt_error_intr_sent = 1'b1;
+                end
+
+                if (this.wdt_t2_restart) begin
+                    `uvm_error("PRED_WDT", "Cascade mode, received t2 pet - unexpected t2 pet!")
+                end
+                else if (this.t2_count != wdt_t2_period) begin
+                    this.t2_count++;
+                    if (!($time % 500))
+                        `uvm_info("PRED_WDT", $sformatf("In cascade mode. t2_count increments to 0x%x, wdt_to_period is 0x%x", this.t2_count, wdt_t2_period), UVM_DEBUG)
+                end
+                else begin
+                    if (!this.wdt_nmi_intr_sent) begin
+                        `uvm_info("PRED_WDT", "Timer2 expired in cascade mode. Expecting NMI to be handled", UVM_MEDIUM);
+                        p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_HW_ERROR_FATAL.nmi_pin.predict(1'b1, -1, UVM_PREDICT_READ, UVM_PREDICT, p_soc_ifc_AHB_map); //TODO: use default map?
+                        p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_STATUS.t2_timeout.predict(1'b1, -1, UVM_PREDICT_READ, UVM_PREDICT, p_soc_ifc_AHB_map);
+                        
+                        //Sending cptra_status_txn in the same clock as NMI
+                        nmi_intr_pending = 1'b1;
+                        populate_expected_cptra_status_txn(local_cptra_sb_ap_txn);
+                        cptra_sb_ap.write(local_cptra_sb_ap_txn);
+                        `uvm_info("PRED_WDT", "Transaction submitted through cptra_sb_ap", UVM_MEDIUM)
+
+                        // Fatal error interrupt is delayed by 1 cycle due to reg state
+                        fork
+                            configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(1);
+                            if (!noncore_rst_out_asserted) begin
+                                `uvm_info("PRED_WDT", "Watchdog timeout triggers cptra_error_fatal output", UVM_HIGH)
+                                cptra_error_fatal = 1;
+                                populate_expected_soc_ifc_status_txn(local_soc_ifc_sb_ap_txn);
+                                soc_ifc_sb_ap.write(local_soc_ifc_sb_ap_txn);
+                                `uvm_info("PRED_WDT", "Transaction submitted through soc_ifc_sb_ap", UVM_MEDIUM)
+                            end
+                        join_none
+
+                        //Set a flag so we don't keep sending transactions while the timer holds value until interrupt
+                        //is serviced or reset
+                        this.wdt_nmi_intr_sent = 1'b1;
+                    end
+                end
+            end
+        end //Cascade mode
+        else if (independent) begin
+            if (this.wdt_t1_restart && !p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_STATUS.t1_timeout.get_mirrored_value()) begin
+                this.t1_count = 'h0;
+                `uvm_info("PRED_WDT", "Independent mode, received t1 pet - restarting t1 count", UVM_MEDIUM)
+                this.wdt_t1_restart = 1'b0; //Reset flag so we can capture another restart event
+            end
+            else if (this.t1_count != wdt_t1_period) begin
+                this.t1_count++;
+                if (!($time % 500))
+                    `uvm_info("PRED_WDT", $sformatf("In independent mode. t1_count increments to 0x%x, wdt_to_period is 0x%x", this.t1_count, wdt_t1_period), UVM_DEBUG)
+            end
+            else begin
+                //T1 expired, so send out soc error intr
+                if (!this.wdt_error_intr_sent) begin
+                    `uvm_info("PRED_WDT", "Independent mode, T1 expired", UVM_MEDIUM)
+                    p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.error_internal_intr_r.error_wdt_timer1_timeout_sts.predict(1'b1, -1, UVM_PREDICT_READ, UVM_PREDICT, p_soc_ifc_AHB_map);
+                    p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_STATUS.t1_timeout.predict(1'b1, -1, UVM_PREDICT_READ, UVM_PREDICT, p_soc_ifc_AHB_map);
+                    
+                    //Set a flag so we don't keep sending transactions while the timer holds value until interrupt
+                    //is serviced or reset
+                    this.wdt_error_intr_sent = 1'b1;
+                    timer1_debug_flag = 0;
+                end
+                else if (!timer1_debug_flag) begin
+                    `uvm_info("PRED_WDT", "Independent mode, T1 expired, but wdt_error_intr_sent is already set!", UVM_DEBUG)
+                    timer1_debug_flag = 1;
+                end
+            end
+            //-------------------------------------------------
+            //Timer 2
+            //-------------------------------------------------
+            if (this.wdt_t2_restart && !p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_STATUS.t2_timeout.get_mirrored_value()) begin
+                this.t2_count = 'h0;
+                `uvm_info("PRED_WDT", "Independent mode, received t2 pet - restarting t2 count", UVM_MEDIUM)
+                this.wdt_t2_restart = 1'b0; //Reset flag so we can capture another restart event
+            end
+            else if (this.t2_count != wdt_t2_period) begin
+                this.t2_count++;
+                if (!($time % 500))
+                    `uvm_info("PRED_WDT", $sformatf("In independent mode. t2_count increments to 0x%x, wdt_to_period is 0x%x", this.t2_count, wdt_t2_period), UVM_DEBUG)
+            end
+            else begin
+                //T2 expired, so send out soc error intr
+                if (!this.wdt_t2_error_intr_sent) begin
+                    `uvm_info("PRED_WDT", "Independent mode, T2 expired", UVM_MEDIUM)
+                    p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.error_internal_intr_r.error_wdt_timer2_timeout_sts.predict(1'b1, -1, UVM_PREDICT_READ, UVM_PREDICT, p_soc_ifc_AHB_map);
+                    p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_STATUS.t2_timeout.predict(1'b1, -1, UVM_PREDICT_READ, UVM_PREDICT, p_soc_ifc_AHB_map);
+                    
+                    //Set a flag so we don't keep sending transactions while the timer holds value until interrupt
+                    //is serviced or reset
+                    this.wdt_t2_error_intr_sent = 1'b1;
+                    timer2_debug_flag = 0;
+                end
+                else if (!timer2_debug_flag) begin
+                    `uvm_info("PRED_WDT", "Independent mode, T2 expired, but wdt_t2_error_intr_sent is already set!", UVM_DEBUG)
+                    timer2_debug_flag = 1;
+                end
+            end
+
+        end //Independent mode
+
+        configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(1);
+        // Hit an issue where this task would make predictions and schedule delay jobs before poll_and_run_delay_jobs() had
+        // kicked off the current cycle's jobs - so delay jobs (to intr pins) were not being delayed.
+        // Stall until after the task poll_and_run_delay_jobs has already forked delay jobs before reentering wdt loop and predicting new updates
+        uvm_wait_for_nba_region();
+
+    end //forever
+endtask
+
+
+function bit soc_ifc_predictor::soc_ifc_status_txn_expected_after_noncore_reset();
+    /* FIXME calculate all of these from the reg-model somehow? */
+    return ready_for_fw_push || ready_for_runtime || mailbox_data_avail || |generic_output_wires /*|| trng_req_pending*/; /* only expect a soc_ifc_status_transaction if some signal will transition */
+endfunction
+
+function bit soc_ifc_predictor::cptra_status_txn_expected_after_noncore_reset();
     /* FIXME calculate this from the reg-model somehow? */
-    return !noncore_rst_out_asserted                                                                      ||
-           !uc_rst_out_asserted                                                                           ||
-           p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.error_global_intr_r.agg_sts.get_mirrored_value() ||
-           p_soc_ifc_rm.soc_ifc_reg_rm.intr_block_rf_ext.notif_global_intr_r.agg_sts.get_mirrored_value() ||
-           sha_err_intr_pending                                                                           ||
-           sha_notif_intr_pending                                                                         ||
-           iccm_locked                                                                                    ||
+    // NOTE: Interrupt signals deasserting (due to reset) will not result in a
+    //       status transaction, because only interrupt rising edges are detected
+    return !noncore_rst_out_asserted ||
+           !uc_rst_out_asserted      ||
+           iccm_locked               ||
            |nmi_vector;
 endfunction
 
+function bit soc_ifc_predictor::soc_ifc_status_txn_expected_after_warm_reset();
+    // Most soc_ifc_status signals are actually reset by the noncore reset assertion (later)
+    // instead of the cptra_rst_b
+    return p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_FLOW_STATUS.ready_for_fuses.get_mirrored_value();
+endfunction
+
+function bit soc_ifc_predictor::cptra_status_txn_expected_after_warm_reset();
+    // NOTE: Almost all (maybe all?) cptra_status signals persists across warm reset
+    //       until it cascades into the assertion of noncore reset.
+    return 0;
+endfunction
+
+function bit soc_ifc_predictor::soc_ifc_status_txn_expected_after_cold_reset();
+    return soc_ifc_status_txn_expected_after_warm_reset() || soc_ifc_status_txn_expected_after_noncore_reset(); /* all resets are expected in conjunction with cold */
+endfunction
+
+function bit soc_ifc_predictor::cptra_status_txn_expected_after_cold_reset();
+    return cptra_status_txn_expected_after_warm_reset() || cptra_status_txn_expected_after_noncore_reset(); /* all resets are expected in conjunction with cold */
+endfunction
+
 function bit soc_ifc_predictor::valid_requester(input uvm_transaction txn);
     soc_ifc_sb_ahb_ap_output_transaction_t ahb_txn;
     soc_ifc_sb_apb_ap_output_transaction_t apb_txn;
@@ -1470,7 +3126,7 @@ function bit soc_ifc_predictor::valid_requester(input uvm_transaction txn);
         return valid_requester;
     end
     else begin
-        `uvm_error("PRED", "valid_requester received invalid transaction - cannot cast as AHB or APB!")
+        `uvm_error("PRED_VALID_REQ", "valid_requester received invalid transaction - cannot cast as AHB or APB!")
         valid_requester = 0;
         return valid_requester;
     end
@@ -1519,13 +3175,75 @@ function bit soc_ifc_predictor::valid_receiver(input uvm_transaction txn);
         return valid_receiver;
     end
     else begin
-        `uvm_error("PRED", "valid_receiver received invalid transaction - cannot cast as AHB or APB!")
+        `uvm_error("PRED_VALID_RCV", "valid_receiver received invalid transaction - cannot cast as AHB or APB!")
         valid_receiver = 0;
         return valid_receiver;
     end
 endfunction
 
-task soc_ifc_predictor::handle_reset(input string kind = "HARD");
+function bit soc_ifc_predictor::sha_valid_user(input uvm_transaction txn);
+    soc_ifc_sb_ahb_ap_output_transaction_t ahb_txn;
+    soc_ifc_sb_apb_ap_output_transaction_t apb_txn;
+    if ($cast(ahb_txn,txn)) begin
+        sha_valid_user = p_soc_ifc_rm.sha512_acc_csr_rm.LOCK.LOCK.get_mirrored_value() &&
+                        !p_soc_ifc_rm.sha512_acc_csr_rm.STATUS.SOC_HAS_LOCK.get_mirrored_value();
+        if (!sha_valid_user) begin
+            string msg = $sformatf("sha_valid_user is false!\nsha_lock: %d\nsha_accel_status.soc_has_lock: %d",
+                                   p_soc_ifc_rm.sha512_acc_csr_rm.LOCK.LOCK.get_mirrored_value(),
+                                   p_soc_ifc_rm.sha512_acc_csr_rm.STATUS.SOC_HAS_LOCK.get_mirrored_value());
+            `uvm_info("PRED_VALID_SHA", msg, UVM_HIGH)
+        end
+        else begin
+            `uvm_info("PRED_VALID_SHA", "sha_valid_user is true", UVM_DEBUG)
+        end
+        return sha_valid_user;
+    end
+    else if ($cast(apb_txn,txn)) begin
+        sha_valid_user = p_soc_ifc_rm.sha512_acc_csr_rm.LOCK.LOCK.get_mirrored_value() &&
+                         p_soc_ifc_rm.sha512_acc_csr_rm.STATUS.SOC_HAS_LOCK.get_mirrored_value() &&
+                         p_soc_ifc_rm.sha512_acc_csr_rm.USER.get_mirrored_value() == apb_txn.addr_user;
+        if (!sha_valid_user) begin
+            string msg = $sformatf("sha_valid_user is false!\nsha_lock: %d\nsha_status.soc_has_lock: %d\naddr_user: 0x%x\nsha_user: 0x%x",
+                                   p_soc_ifc_rm.sha512_acc_csr_rm.LOCK.LOCK.get_mirrored_value(),
+                                   p_soc_ifc_rm.sha512_acc_csr_rm.STATUS.SOC_HAS_LOCK.get_mirrored_value(),
+                                   apb_txn.addr_user,
+                                   p_soc_ifc_rm.sha512_acc_csr_rm.USER.get_mirrored_value());
+            `uvm_info("PRED_VALID_SHA", msg, UVM_HIGH)
+        end
+        else begin
+            `uvm_info("PRED_VALID_SHA", "sha_valid_user is true", UVM_DEBUG)
+        end
+        return sha_valid_user;
+    end
+    else begin
+        `uvm_error("PRED_VALID_SHA", "sha_valid_user received invalid transaction - cannot cast as AHB or APB!")
+        sha_valid_user = 0;
+        return sha_valid_user;
+    end
+endfunction
+
+function void soc_ifc_predictor::predict_boot_wait_boot_done();
+    cptra_sb_ap_output_transaction_t local_cptra_sb_ap_txn;
+
+    p_soc_ifc_rm.soc_ifc_reg_rm.boot_fn_state_sigs = '{boot_done: 1'b1, default: 1'b0};
+    fw_update_rst_window                           = 1'b0;
+
+    fork
+        begin
+            configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(1);
+            if (uc_rst_out_asserted) begin
+                uc_rst_out_asserted   = 1'b0;
+                local_cptra_sb_ap_txn = cptra_sb_ap_output_transaction_t::type_id::create("local_cptra_sb_ap_txn");
+                populate_expected_cptra_status_txn(local_cptra_sb_ap_txn);
+                cptra_sb_ap.write(local_cptra_sb_ap_txn);
+                `uvm_info("PRED_BOOT", "Transaction submitted through cptra_sb_ap", UVM_MEDIUM)
+            end
+        end
+    join_none
+
+endfunction
+
+task soc_ifc_predictor::handle_reset(input string kind = "HARD", output uvm_event reset_synchro);
     uvm_object obj_triggered;
     reset_flag kind_predicted;
     reset_flag kind_handled;
@@ -1534,84 +3252,250 @@ task soc_ifc_predictor::handle_reset(input string kind = "HARD");
                    kind == "SOFT" ? soft_reset_flag :
                                     null;
     reset_handled.trigger(kind_handled);
+    `uvm_info("PRED_HANDLE_RESET", "On call to handle_reset, waiting to receive the ctrl reset transaction", UVM_HIGH)
     reset_predicted.wait_trigger_data(obj_triggered);
+    `uvm_info("PRED_HANDLE_RESET", "In call to handle_reset, received the ctrl reset transaction", UVM_HIGH)
     if (!$cast(kind_predicted, obj_triggered))
-        `uvm_fatal("SOC_IFC_PRED", "Failed to retrieve triggered reset_flag")
+        `uvm_fatal("PRED_HANDLE_RESET", "Failed to retrieve triggered reset_flag")
     if (kind_handled != kind_predicted)
-        `uvm_error("SOC_IFC_PRED", $sformatf("handle_reset called with different reset type [%s] than was processed in predictor [%s]!", kind_handled.get_name(), kind_predicted.get_name()))
-    reset_predicted.reset();
+        `uvm_error("PRED_HANDLE_RESET", $sformatf("handle_reset called with different reset type [%s] than was processed in predictor [%s]!", kind_handled.get_name(), kind_predicted.get_name()))
+    // Used to synchronize the noncore reset in the reset of the environment with
+    // the predictor (all other components must be reset before predictor)
+    reset_synchro = reset_handled;
 endtask
 
 function void soc_ifc_predictor::predict_reset(input string kind = "HARD");
     uvm_reg all_regs[$];
+    reset_flag last_predicted_kind = null;
 
-    `uvm_info("SOC_IFC_PRED", $sformatf("Predicting reset of kind: %p", kind), UVM_LOW)
+    `uvm_info("PRED_RESET", $sformatf("Predicting reset of kind: %p", kind), UVM_LOW)
+
+    // Monitor the assertion of internal resets, which assert instantly for HARD reset
+    // but are delayed slightly from SOFT resets
+    if (kind == "HARD") begin: IMMEDIATE_INTERNAL_RESET_ASSERTION
+        `uvm_info("PRED_RESET", $sformatf("Reset prediction of kind: %p results in immediate assertion of internal resets", kind), UVM_MEDIUM)
+        noncore_rst_out_asserted = 1'b1;
+        uc_rst_out_asserted = 1'b1;
+        rdc_clk_gate_active = 1'b1;
+    end
+    else if (kind == "SOFT") begin
+        fork
+            begin: DELAY_INTERNAL_RESET_ASSERTION
+            cptra_sb_ap_output_transaction_t local_cptra_sb_ap_txn;
+            soc_ifc_sb_ap_output_transaction_t local_soc_ifc_sb_ap_txn;
+            bit send_soc_ifc_sts_txn = soc_ifc_status_txn_expected_after_noncore_reset();
+
+            // Do the noncore reset
+            `uvm_info("PRED_RESET", $sformatf("Reset prediction of kind: %p results in assertion of internal resets after a delay", kind), UVM_MEDIUM)
+            fork
+                begin
+                    // FIXME need to implement clk gating features in uvmf_soc_ifc
+                    if (configuration.cptra_ctrl_agent_config.active_passive == PASSIVE) begin
+                        configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(2);
+                        uvm_wait_for_nba_region();
+                        rdc_clk_gate_active = 1'b1;
+                        `uvm_info("PRED_RESET", $sformatf("Reset prediction of kind: %p results in assertion of RDC clk gate", kind), UVM_MEDIUM)
+                    end
+                end
+                configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(SOC_IFC_CPTRA_RST_NONCORE_RST_DELAY);
+            join
+            // Synchronize the noncore reset with the reset of the environment and allow other
+            // components to reset before proceeding with predicted activity
+            reset_handled.trigger(noncore_reset_flag);
+            reset_handled.wait_off();
+            predict_reset("NONCORE");
+
+            // Send predicted transactions
+            if (1) begin
+                local_cptra_sb_ap_txn = cptra_sb_ap_output_transaction_t::type_id::create("local_cptra_sb_ap_txn");
+                populate_expected_cptra_status_txn(local_cptra_sb_ap_txn);
+                cptra_sb_ap.write(local_cptra_sb_ap_txn);
+                `uvm_info("PRED_RESET", "Transaction submitted through cptra_sb_ap", UVM_MEDIUM)
+            end
+            if (send_soc_ifc_sts_txn) begin
+                local_soc_ifc_sb_ap_txn = soc_ifc_sb_ap_output_transaction_t::type_id::create("local_soc_ifc_sb_ap_txn");
+                populate_expected_soc_ifc_status_txn(local_soc_ifc_sb_ap_txn);
+                soc_ifc_sb_ap.write(local_soc_ifc_sb_ap_txn);
+                `uvm_info("PRED_RESET", "Transaction submitted through soc_ifc_sb_ap", UVM_MEDIUM)
+            end
+            end: DELAY_INTERNAL_RESET_ASSERTION
+        join_none
+    end
+    else if (kind == "NONCORE") begin: NONCORE_INTERNAL_RESET_ASSERTION
+        `uvm_info("PRED_RESET", $sformatf("Reset prediction of kind: %p results in assertion of internal resets", kind), UVM_MEDIUM)
+        noncore_rst_out_asserted = 1'b1;
+        uc_rst_out_asserted = 1'b1;
+    end
+
+    // Track the BOOT FSM internally
+    if (kind inside {"HARD", "SOFT"}) begin: BOOT_FSM_THREAD
+        p_soc_ifc_rm.soc_ifc_reg_rm.boot_fn_state_sigs = '{boot_idle: 1'b1, default: 1'b0};
+        // schedule the delayed transition to next state
+        // Wait for the reset deassertion transactions to be detected, indicating
+        // BOOT FSM can progress and subsequent
+        fork
+            begin
+                cptra_sb_ap_output_transaction_t local_cptra_sb_ap_txn;
+                soc_ifc_sb_ap_output_transaction_t local_soc_ifc_sb_ap_txn;
+
+                // Wait for cptra_rst_b deassertion
+                `uvm_info("PRED_RESET", $sformatf("Reset prediction of kind: %p will result in state change after reset deasserts. Wait for cptra_rst_b==1...", kind), UVM_MEDIUM)
+                while (last_predicted_kind != soft_reset_flag) begin
+                    uvm_object obj_predicted;
+                    reset_predicted.wait_ptrigger_data(obj_predicted);
+                    reset_predicted.wait_off();
+                    $cast(last_predicted_kind,obj_predicted);
+                    `uvm_info("PRED_RESET", $sformatf("After reset_predicted was cleared, last predicted kind was: %s", last_predicted_kind.get_name()), UVM_MEDIUM)
+                end
+
+                // Additional delay until RDC clock comes back alive
+                // NOTE: Not implemented in uvmf_soc_ifc, only occurs in caliptra_top. TODO
+                if (configuration.cptra_ctrl_agent_config.active_passive == PASSIVE)
+                    configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(4); // FIXME, correct delay value?
+                rdc_clk_gate_active = 1'b0;
+
+                p_soc_ifc_rm.soc_ifc_reg_rm.boot_fn_state_sigs = '{boot_fuse: 1'b1, default: 1'b0};
+                `uvm_info("PRED_RESET", $sformatf("After detecting warm reset deassertion, boot FSM state change predicted: [%p]", p_soc_ifc_rm.soc_ifc_reg_rm.boot_fn_state_sigs), UVM_MEDIUM)
+                // NOTE: Next state progression is triggered by write to CPTRA_FUSE_WR_DONE
+
+                // Now, deassertion of noncore reset is delayed from state transition by 2 cycles
+                configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(2); // FIXME, correct delay value?
+                noncore_rst_out_asserted = 1'b0;
+                reset_wdt_count = 1'b0;
+                p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_FLOW_STATUS.ready_for_fuses.predict(1'b1);
+
+                // Send predicted transactions
+                if (1) begin
+                    // cptra status is for noncore reset deassertion
+                    local_cptra_sb_ap_txn = cptra_sb_ap_output_transaction_t::type_id::create("local_cptra_sb_ap_txn");
+                    populate_expected_cptra_status_txn(local_cptra_sb_ap_txn);
+                    cptra_sb_ap.write(local_cptra_sb_ap_txn);
+                    `uvm_info("PRED_RESET", "Transaction submitted through cptra_sb_ap", UVM_MEDIUM)
+                end
+                if (1) begin
+                    // soc_ifc status is for ready_for_fuses
+                    local_soc_ifc_sb_ap_txn = soc_ifc_sb_ap_output_transaction_t::type_id::create("local_soc_ifc_sb_ap_txn");
+                    populate_expected_soc_ifc_status_txn(local_soc_ifc_sb_ap_txn);
+                    soc_ifc_sb_ap.write(local_soc_ifc_sb_ap_txn);
+                    `uvm_info("PRED_RESET", "Transaction submitted through soc_ifc_sb_ap", UVM_MEDIUM)
+                end
+            end
+        join_none
+    end
 
     // Predict value changes due to reset
-    soc_ifc_rst_in_asserted = 1'b1;
-    noncore_rst_out_asserted = 1'b1;
-    uc_rst_out_asserted = 1'b1;
-    p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_FLOW_STATUS.ready_for_fuses.predict(1'b0);
+    fw_update_wait_count = 0;
+
+    if (kind inside {"HARD", "SOFT"}) begin: RESET_VAL_CHANGES_HARD_SOFT
+        soc_ifc_rst_in_asserted = 1'b1;
+        p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_FLOW_STATUS.ready_for_fuses.predict(1'b0);
+    end: RESET_VAL_CHANGES_HARD_SOFT
+
+    // Signals that are tied to reg values are not reset by warm reset until it
+    // propagates to the internal resets
     // FIXME: Do a reg-model reset and then extract these from the reg_model???
-    ready_for_fw_push = 1'b0;
-    ready_for_runtime = 1'b0;
-    nmi_vector = '0;
-    iccm_locked = 1'b0;
-    mailbox_data_avail = 1'b0;
-    soc_ifc_error_intr_pending = 1'b0;
-    soc_ifc_notif_intr_pending = 1'b0;
-    sha_err_intr_pending = 1'b0;
-    sha_notif_intr_pending = 1'b0;
-    generic_output_wires = '0;
-
-    // FIXME get rid of this variable?
-    mbox_valid_users        = '{p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_MBOX_VALID_PAUSER[0].PAUSER.get_reset(kind),
-                                p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_MBOX_VALID_PAUSER[1].PAUSER.get_reset(kind),
-                                p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_MBOX_VALID_PAUSER[2].PAUSER.get_reset(kind),
-                                p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_MBOX_VALID_PAUSER[3].PAUSER.get_reset(kind),
-                                p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_MBOX_VALID_PAUSER[4].PAUSER.get_reset(kind),
-                                p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_MBOX_VALID_PAUSER[0].PAUSER.get_reset(kind)/*This entry is for the non-programmable default value */};
-    mbox_valid_users_locked =  {p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_MBOX_PAUSER_LOCK[0].LOCK.get_reset(kind),
-                                p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_MBOX_PAUSER_LOCK[1].LOCK.get_reset(kind),
-                                p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_MBOX_PAUSER_LOCK[2].LOCK.get_reset(kind),
-                                p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_MBOX_PAUSER_LOCK[3].LOCK.get_reset(kind),
-                                p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_MBOX_PAUSER_LOCK[4].LOCK.get_reset(kind)};
-
-    trng_data_req = 1'b0;
-
-    if (kind == "HARD") begin
-        fuse_update_enabled = 1'b1; // Fuses only latch new values from APB write after a cold-reset (which clears CPTRA_FUSE_WR_DONE)
-    end
+    if (kind inside {"HARD", "NONCORE"}) begin: RESET_VAL_CHANGES_HARD_NONCORE
+        ready_for_fw_push = 1'b0;
+        ready_for_runtime = 1'b0;
+        nmi_vector = '0;
+        iccm_locked = 1'b0;
+        mailbox_data_avail = 1'b0;
+        soc_ifc_error_intr_pending = 1'b0;
+        soc_ifc_notif_intr_pending = 1'b0;
+        sha_err_intr_pending = 1'b0;
+        sha_notif_intr_pending = 1'b0;
+
+        generic_output_wires = '0;
+
+        cptra_error_fatal = 1'b0;
+        cptra_error_non_fatal = 1'b0;
+
+        //WDT
+        nmi_intr_pending = 1'b0; //Reset nmi_intr on reset assertion
+        reset_wdt_count = 1'b1;
+
+        // FIXME get rid of this variable?
+        mbox_valid_users        = '{p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_MBOX_VALID_PAUSER[0].PAUSER.get_reset(kind),
+                                    p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_MBOX_VALID_PAUSER[1].PAUSER.get_reset(kind),
+                                    p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_MBOX_VALID_PAUSER[2].PAUSER.get_reset(kind),
+                                    p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_MBOX_VALID_PAUSER[3].PAUSER.get_reset(kind),
+                                    p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_MBOX_VALID_PAUSER[4].PAUSER.get_reset(kind),
+                                    p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_MBOX_VALID_PAUSER[0].PAUSER.get_reset(kind)/*This entry is for the non-programmable default value */};
+        mbox_valid_users_locked =  {p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_MBOX_PAUSER_LOCK[0].LOCK.get_reset(kind),
+                                    p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_MBOX_PAUSER_LOCK[1].LOCK.get_reset(kind),
+                                    p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_MBOX_PAUSER_LOCK[2].LOCK.get_reset(kind),
+                                    p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_MBOX_PAUSER_LOCK[3].LOCK.get_reset(kind),
+                                    p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_MBOX_PAUSER_LOCK[4].LOCK.get_reset(kind)};
+
+        trng_data_req = 1'b0;
+
+        // Mailbox 'step' represents how the current transaction affects the mailbox
+        // flow, and is used for coverage.
+        if (p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.mbox_idle)
+            next_step = '{null_action: 1'b1, default: 1'b0};
+        else
+            next_step = '{reset: 1'b1, default: 1'b0};
+        fork
+            begin
+            // This allows coverage subscriber to observe both prev_step and next_step before the transition
+            uvm_wait_for_nba_region();
+            prev_step = next_step;
+            end
+        join_none
+
+        datain_count = 0;
+        dataout_count = 0;
+
+        dataout_mismatch_expected = 1'b0;
 
-    datain_count = 0;
-    dataout_count = 0;
+    end: RESET_VAL_CHANGES_HARD_NONCORE
+
+    if (kind == "HARD") begin: RESET_VAL_CHANGES_HARD
+        cptra_pwrgood_asserted = 1'b0;
+        timer_intr_pending = 1'b1;
+        fuse_update_enabled = 1'b1; // Fuses only latch new values from APB write after a cold-reset (which clears CPTRA_FUSE_WR_DONE)
+    end: RESET_VAL_CHANGES_HARD
 
     // HARD reset is the default for a reg-model
-    // FIXME SOFT reset is not fully defined for our reg-model yet
     // FIXME move this to env?
     p_soc_ifc_rm.reset(kind);
-    // If any reg access was in progress when reset occurred, clear the busy
-    // flag (since the APB/AHB sequencers and any mailbox sequences were killed)
-    p_soc_ifc_rm.get_registers(all_regs, UVM_HIER);
-    foreach (all_regs[ii]) begin
-        if (all_regs[ii].is_busy()) begin
-            `uvm_info("SOC_IFC_PRED", $sformatf("After resetting the reg-model, found a busy reg: [%s]. Resetting the busy bit.", all_regs[ii].get_full_name()), UVM_FULL)
-            // TODO: This is not in the official API, and the 'reset' function doesn't
-            //       automatically clear busy. Not sure how to do this properly
-            all_regs[ii].Xset_busyX(0);
+    // Kill any delay_jobs that have been initiated but not completed yet
+    if (kind inside {"HARD","NONCORE"}) begin: KILL_DLY_JOBS_HARD_NONCORE
+        if (running_dly_jobs.size() > 0)
+            `uvm_info("PRED_RESET", $sformatf("Terminating %0d active delayed jobs.", running_dly_jobs.size()), UVM_HIGH)
+        while (running_dly_jobs.size() > 0) begin
+            process job_to_kill = running_dly_jobs.pop_front();
+            if (job_to_kill.status() inside {process::KILLED,process::SUSPENDED,process::FINISHED}) begin
+                `uvm_fatal("PRED_RESET", $sformatf("Found delay job in the running jobs queue with unexpected status %s", job_to_kill.status().name()))
+            end
+            else begin
+                job_to_kill.kill();
+            end
         end
+        job_end_count.delete();
     end
 
-    soc_ifc_status_txn_key = 0;
-    cptra_status_txn_key = 0;
-endfunction
-
-function bit soc_ifc_predictor::soc_ifc_status_txn_expected_after_cold_reset();
-    return soc_ifc_status_txn_expected_after_warm_reset(); /* warm reset is expected in conjunction with cold */
-endfunction
+    if (kind inside {"HARD","NONCORE"}) begin: RESET_REG_BUSY_HARD_NONCORE
+        // If any reg access was in progress when reset occurred, clear the busy
+        // flag (since the APB/AHB sequencers and any mailbox sequences were killed).
+        // We don't run this for warm/soft resets because cptra_rst_b doesn't immediately
+        // reset the AHB interface, so pending transactions might still complete.
+        p_soc_ifc_rm.get_registers(all_regs, UVM_HIER);
+        foreach (all_regs[ii]) begin
+            if (all_regs[ii].is_busy()) begin
+                `uvm_info("PRED_RESET", $sformatf("After resetting the reg-model, found a busy reg: [%s]. Resetting the busy bit.", all_regs[ii].get_full_name()), UVM_FULL)
+                // TODO: This is not in the official API, and the 'reset' function doesn't
+                //       automatically clear busy. Not sure how to do this properly
+                all_regs[ii].Xset_busyX(0);
+            end
+        end
+    end: RESET_REG_BUSY_HARD_NONCORE
 
-function bit soc_ifc_predictor::cptra_status_txn_expected_after_cold_reset();
-    return cptra_status_txn_expected_after_warm_reset(); /* warm reset is expected in conjunction with cold */
+    // Key keeps on rolling after a SOFT reset because activity continues until NONCORE reset asserts
+    if (kind inside {"HARD","NONCORE"}) begin: RESET_TXN_KEY_HARD_NONCORE
+        soc_ifc_status_txn_key = 0;
+        cptra_status_txn_key = 0;
+    end: RESET_TXN_KEY_HARD_NONCORE
 endfunction
 
 function bit [`CLP_OBF_FE_DWORDS-1:0] [31:0] soc_ifc_predictor::get_expected_obf_field_entropy();
@@ -1638,8 +3522,8 @@ function void soc_ifc_predictor::populate_expected_soc_ifc_status_txn(ref soc_if
     txn.ready_for_runtime                  = this.ready_for_runtime;
     txn.mailbox_data_avail                 = this.mailbox_data_avail;
     txn.mailbox_flow_done                  = this.mailbox_flow_done; // FIXME
-    txn.cptra_error_fatal_intr_pending     = 1'b0; // FIXME
-    txn.cptra_error_non_fatal_intr_pending = 1'b0; // FIXME
+    txn.cptra_error_fatal_intr_pending     = this.cptra_error_fatal;
+    txn.cptra_error_non_fatal_intr_pending = this.cptra_error_non_fatal;
     txn.trng_req_pending                   = this.trng_data_req;
     txn.generic_output_val                 = this.generic_output_wires;
     txn.set_key(soc_ifc_status_txn_key++);
@@ -1648,17 +3532,19 @@ endfunction
 function void soc_ifc_predictor::populate_expected_cptra_status_txn(ref cptra_sb_ap_output_transaction_t txn);
     txn.noncore_rst_asserted       = this.noncore_rst_out_asserted;
     txn.uc_rst_asserted            = this.uc_rst_out_asserted;
+    txn.fw_update_rst_window       = this.fw_update_rst_window;
     txn.soc_ifc_err_intr_pending   = this.soc_ifc_error_intr_pending;
     txn.soc_ifc_notif_intr_pending = this.soc_ifc_notif_intr_pending;
     txn.sha_err_intr_pending       = this.sha_err_intr_pending;
     txn.sha_notif_intr_pending     = this.sha_notif_intr_pending;
+    txn.timer_intr_pending         = this.timer_intr_pending;
     txn.cptra_obf_key_reg          = this.cptra_obf_key_reg;
     txn.obf_field_entropy          = this.get_expected_obf_field_entropy();
     txn.obf_uds_seed               = this.get_expected_obf_uds_seed();
     txn.nmi_vector                 = this.nmi_vector;
+    txn.nmi_intr_pending           = this.nmi_intr_pending;
     txn.iccm_locked                = this.iccm_locked;
     txn.set_key(cptra_status_txn_key++);
 endfunction
 
 // pragma uvmf custom external end
-
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_reg_cov_subscriber.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_reg_cov_subscriber.svh
new file mode 100644
index 000000000..c14aff7d5
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_reg_cov_subscriber.svh
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//------------------------------------------------------------------------------
+//
+// CLASS: soc_ifc_reg_cov_subscriber
+//
+// This class provides an analysis export for receiving transactions from a
+// connected analysis export. Making such a connection "subscribes" this
+// component to any transactions emitted by the connected analysis port.
+//
+// This extended class provides a coverage subscriber that receives uvm_reg_item
+// objects exported from the uvm_reg_predictor and calls the sample_values 
+// function for the associated register.
+//------------------------------------------------------------------------------
+
+class soc_ifc_reg_cov_subscriber #(
+  type CONFIG_T,
+  type T=uvm_reg_item,
+  type BASE_T = uvm_subscriber #(T)
+  )
+ extends BASE_T;
+
+  typedef soc_ifc_reg_cov_subscriber #( CONFIG_T, T, BASE_T) this_type;
+
+  // Factory registration of this class
+  `uvm_component_param_utils( this_type )
+
+  CONFIG_T configuration;
+
+  function new (string name, uvm_component parent);
+    super.new(name, parent);
+  endfunction
+  
+ virtual function void write(T t);
+    uvm_object obj;
+    uvm_reg axs_reg;
+    obj = t.element;
+    if (t.element_kind == UVM_REG)
+        $cast(axs_reg,obj);
+    else
+        `uvm_fatal("SOC_IFC_REG_COV_SUB", "Bad object type in received item")
+    `uvm_info("SOC_IFC_REG_COV_SUB", $sformatf("Received reg item accessing reg %s for coverage sampling", axs_reg.get_full_name()), UVM_FULL)
+    axs_reg.sample_values();
+ endfunction
+
+endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_scoreboard.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_scoreboard.svh
index 761ffb179..ca05dce58 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_scoreboard.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_scoreboard.svh
@@ -143,9 +143,10 @@ class soc_ifc_scoreboard #(
   bit [1:0] soc_ifc_status_monitor_toggle_count [$bits(soc_ifc_status_monitor_s)-1:0] = '{default: 0};
 
   // Variables used to report transaction matches and mismatches
-  int match_count; // FIXME report this
-  int mismatch_count; // FIXME report this
-  int nothing_to_compare_against_count; // FIXME check this and report
+  int match_count = 0;
+  int mismatch_count = 0;
+  int nothing_to_compare_against_count = 0;
+  int multiple_missed_txn_count = 0;
   bit testcase_passed = 1'b0;
 
   // Variables used for report_phase summary output formatting using report_message()
@@ -154,7 +155,7 @@ class soc_ifc_scoreboard #(
 
   // Variable used to enable end of test scoreboard empty check
   bit end_of_test_empty_check=1; // FIXME
-  int transaction_count; // FIXME check this
+  int transaction_count = 0;
 
   // Variable used to delay run phase completion until scoreboard empty
   bit wait_for_scoreboard_empty; // FIXME
@@ -164,6 +165,7 @@ class soc_ifc_scoreboard #(
   uvm_event reset_handled;
   reset_flag hard_reset_flag;
   reset_flag soft_reset_flag;
+  reset_flag noncore_reset_flag;
 
   extern function void handle_reset(string kind = "HARD");
   extern function void disable_wait_for_scoreboard_empty();
@@ -195,6 +197,7 @@ class soc_ifc_scoreboard #(
     reset_handled = new("reset_handled");
     hard_reset_flag = new("hard_reset_flag"); // Used as trigger data for reset events. In UVM 1.2, data changes from a uvm_object to a string
     soft_reset_flag = new("soft_reset_flag"); // Used as trigger data for reset events. In UVM 1.2, data changes from a uvm_object to a string
+    noncore_reset_flag = new("noncore_reset_flag"); // Used as trigger data for reset events. In UVM 1.2, data changes from a uvm_object to a string
   // pragma uvmf custom build_phase end
   endfunction
 
@@ -207,7 +210,7 @@ class soc_ifc_scoreboard #(
     soc_ifc_status_monitor_s soc_ifc_status_monitor_struct_rpt = '{default:0};
 
     `uvm_info("SCBD_SOC_IFC_STS", $sformatf("Transaction Received through expected_analysis_export with key: [%0d]", t.get_key()), UVM_MEDIUM)
-    `uvm_info("SCBD_SOC_IFC_STS", {"            Data: ",t.convert2string()}, UVM_FULL)
+    `uvm_info("SCBD_SOC_IFC_STS", {"            Data: ",t.convert2string()}, UVM_HIGH)
 
     soc_ifc_expected_hash[t.get_key()] = t;
     soc_ifc_status_monitor_struct_prev = soc_ifc_status_monitor_struct;
@@ -223,8 +226,10 @@ class soc_ifc_scoreboard #(
             soc_ifc_status_monitor_struct_rpt[sts_bit] = 1'b1;
         end
     end
-    if (multiple_missed_txn_error)
+    if (multiple_missed_txn_error) begin
+        multiple_missed_txn_count++;
         `uvm_error("SCBD_SOC_IFC_STS",$sformatf("Received multiple expected transactions without corresponding actual transaction. Problem fields: %p", soc_ifc_status_monitor_struct_rpt))
+    end
     transaction_count++;
     -> entry_received;
  
@@ -237,7 +242,7 @@ class soc_ifc_scoreboard #(
   virtual function void write_expected_cptra_analysis_export(cptra_status_transaction t);
     // pragma uvmf custom expected_cptra_analysis_export_scoreboard begin
     `uvm_info("SCBD_CPTRA_STS", $sformatf("Transaction Received through expected_cptra_analysis_export with key: [%0d]", t.get_key()), UVM_MEDIUM)
-    `uvm_info("SCBD_CPTRA_STS", {"            Data: ",t.convert2string()}, UVM_FULL)
+    `uvm_info("SCBD_CPTRA_STS", {"            Data: ",t.convert2string()}, UVM_HIGH)
 
     cptra_expected_hash[t.get_key()] = t;
     if (reset_handled.is_on()) begin
@@ -260,7 +265,7 @@ class soc_ifc_scoreboard #(
     bit txn_eq;
 
     `uvm_info("SCBD_SOC_IFC_STS", $sformatf("Transaction Received through actual_analysis_export with key: [%0d]", t.get_key()), UVM_MEDIUM)
-    `uvm_info("SCBD_SOC_IFC_STS", {"            Data: ",t.convert2string()}, UVM_FULL)
+    `uvm_info("SCBD_SOC_IFC_STS", {"            Data: ",t.convert2string()}, UVM_HIGH)
 
     // Check for expected analysis port to receive first transaction after a reset before proceeding with the actual check
     // This indicates the environment level reset is finished and the predictor had time to forward an expected
@@ -358,9 +363,7 @@ class soc_ifc_scoreboard #(
         soc_ifc_status_monitor_toggle_count = '{default:2'b00};
     end
     else begin
-        `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_LOW)
-        `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The soc_ifc_scoreboard::write_actual_analysis_export function needs to be completed with custom scoreboard functionality",UVM_LOW)
-        `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_LOW)
+        `uvm_info("FIXME_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The soc_ifc_scoreboard::write_actual_analysis_export function needs to be completed with custom scoreboard functionality for unexpected actual transactions",UVM_LOW)
         `uvm_error("SCBD_SOC_IFC_STS",$sformatf("NO PREDICTED ENTRY WITH KEY [%0d] TO COMPARE AGAINST:%s", t.get_key(), t.convert2string()))
         nothing_to_compare_against_count++;
     end
@@ -378,7 +381,7 @@ class soc_ifc_scoreboard #(
     bit txn_eq;
 
     `uvm_info("SCBD_CPTRA_STS", $sformatf("Transaction Received through actual_cptra_analysis_export with key: [%0d]", t.get_key()), UVM_MEDIUM)
-    `uvm_info("SCBD_CPTRA_STS", {"            Data: ",t.convert2string()}, UVM_FULL)
+    `uvm_info("SCBD_CPTRA_STS", {"            Data: ",t.convert2string()}, UVM_HIGH)
 
     // Check for expected analysis port to receive first transaction after a reset before proceeding with the actual check
     if (reset_handled.is_on())
@@ -397,9 +400,7 @@ class soc_ifc_scoreboard #(
         cptra_expected_hash.delete(t.get_key());
     end
     else begin
-        `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_LOW)
-        `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The soc_ifc_scoreboard::write_actual_cptra_analysis_export function needs to be completed with custom scoreboard functionality",UVM_LOW)
-        `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_LOW)
+        `uvm_info("FIXME_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The soc_ifc_scoreboard::write_actual_cptra_analysis_export function needs to be completed with custom scoreboard functionality for unexpected actual transactions",UVM_LOW)
         `uvm_error("SCBD_CPTRA_STS",$sformatf("NO PREDICTED ENTRY WITH KEY [%0d] TO COMPARE AGAINST:%s", t.get_key(), t.convert2string()))
         nothing_to_compare_against_count++;
     end
@@ -420,7 +421,7 @@ class soc_ifc_scoreboard #(
       `uvm_fatal("SCBD_AHB","Cast from mvc_sequence_item_base to ahb_master_burst_transfer #(ahb_lite_slave_0_params::AHB_NUM_MASTERS, ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS, ahb_lite_slave_0_params::AHB_NUM_SLAVES, ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH, ahb_lite_slave_0_params::AHB_WDATA_WIDTH, ahb_lite_slave_0_params::AHB_RDATA_WIDTH) in write_expected_ahb_analysis_export failed!")
     end
     `uvm_info("SCBD_AHB", "Transaction Received through expected_ahb_analysis_export", UVM_MEDIUM)
-    `uvm_info("SCBD_AHB",{"            Data: ",t.convert2string()}, UVM_FULL)
+    `uvm_info("SCBD_AHB",{"            Data: ",t.convert2string()}, UVM_HIGH)
 
     ahb_expected_q.push_back(t);
 
@@ -441,7 +442,7 @@ class soc_ifc_scoreboard #(
       `uvm_fatal("SCBD_APB","Cast from mvc_sequence_item_base to apb3_host_apb3_transaction #(apb5_master_0_params::APB3_SLAVE_COUNT, apb5_master_0_params::APB3_PADDR_BIT_WIDTH, apb5_master_0_params::APB3_PWDATA_BIT_WIDTH, apb5_master_0_params::APB3_PRDATA_BIT_WIDTH) in write_expected_apb_analysis_export failed!")
     end
     `uvm_info("SCBD_APB", "Transaction Received through expected_apb_analysis_export", UVM_MEDIUM)
-    `uvm_info("SCBD_APB",{"            Data: ",t.convert2string()}, UVM_FULL)
+    `uvm_info("SCBD_APB",{"            Data: ",t.convert2string()}, UVM_HIGH)
 
     apb_expected_q.push_back(t);
 
@@ -464,7 +465,7 @@ class soc_ifc_scoreboard #(
       `uvm_fatal("SCBD_AHB","Cast from mvc_sequence_item_base to ahb_master_burst_transfer #(ahb_lite_slave_0_params::AHB_NUM_MASTERS, ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS, ahb_lite_slave_0_params::AHB_NUM_SLAVES, ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH, ahb_lite_slave_0_params::AHB_WDATA_WIDTH, ahb_lite_slave_0_params::AHB_RDATA_WIDTH) in write_actual_ahb_analysis_export failed!")
     end
     `uvm_info("SCBD_AHB", "Transaction Received through actual_ahb_analysis_export", UVM_MEDIUM)
-    `uvm_info("SCBD_AHB",{"            Data: ",t.convert2string()}, UVM_FULL)
+    `uvm_info("SCBD_AHB",{"            Data: ",t.convert2string()}, UVM_HIGH)
 
     if (ahb_expected_q.size() > 0) begin
         t_exp = ahb_expected_q.pop_front();
@@ -479,9 +480,7 @@ class soc_ifc_scoreboard #(
         end
     end
     else begin
-        `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_LOW)
-        `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The soc_ifc_scoreboard::write_actual_ahb_analysis_export function needs to be completed with custom scoreboard functionality",UVM_LOW)
-        `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_LOW)
+        `uvm_info("FIXME_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The soc_ifc_scoreboard::write_actual_ahb_analysis_export function needs to be completed with custom scoreboard functionality for unexpected actual transactions",UVM_LOW)
         `uvm_error("SCBD_AHB",$sformatf("NO PREDICTED ENTRY TO COMPARE AGAINST:%s",t.convert2string()))
         nothing_to_compare_against_count++;
     end
@@ -503,7 +502,7 @@ class soc_ifc_scoreboard #(
       `uvm_fatal("SCBD_APB","Cast from mvc_sequence_item_base to apb3_host_apb3_transaction #(apb5_master_0_params::APB3_SLAVE_COUNT, apb5_master_0_params::APB3_PADDR_BIT_WIDTH, apb5_master_0_params::APB3_PWDATA_BIT_WIDTH, apb5_master_0_params::APB3_PRDATA_BIT_WIDTH) in write_actual_apb_analysis_export failed!")
     end
     `uvm_info("SCBD_APB", "Transaction Received through actual_apb_analysis_export", UVM_MEDIUM)
-    `uvm_info("SCBD_APB",{"            Data: ",t.convert2string()}, UVM_FULL)
+    `uvm_info("SCBD_APB",{"            Data: ",t.convert2string()}, UVM_HIGH)
 
     if (apb_expected_q.size() > 0) begin
         t_exp = apb_expected_q.pop_front();
@@ -518,9 +517,7 @@ class soc_ifc_scoreboard #(
         end
     end
     else begin
-        `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_LOW)
-        `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The soc_ifc_scoreboard::write_actual_apb_analysis_export function needs to be completed with custom scoreboard functionality",UVM_LOW)
-        `uvm_info("UNIMPLEMENTED_CUSTOM_SCOREBOARD", "******************************************************************************************************",UVM_LOW)
+        `uvm_info("FIXME_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The soc_ifc_scoreboard::write_actual_apb_analysis_export function needs to be completed with custom scoreboard functionality for unexpected actual transactions",UVM_LOW)
         `uvm_error("SCBD_APB",$sformatf("NO PREDICTED ENTRY TO COMPARE AGAINST:%s",t.convert2string()))
         nothing_to_compare_against_count++;
     end
@@ -534,7 +531,7 @@ class soc_ifc_scoreboard #(
   virtual function void extract_phase(uvm_phase phase);
 // pragma uvmf custom extract_phase begin
      super.extract_phase(phase);
-     report_variables = {transaction_count, match_count, mismatch_count, nothing_to_compare_against_count};
+     report_variables = {transaction_count, match_count, mismatch_count, nothing_to_compare_against_count, multiple_missed_txn_count};
 // pragma uvmf custom extract_phase end
   endfunction
 
@@ -543,7 +540,7 @@ class soc_ifc_scoreboard #(
 // pragma uvmf custom check_phase begin
      super.check_phase(phase);
      if (transaction_count == 0) `uvm_error("SCBD","No Transactions Scoreboarded")
-     if ((match_count > 0) && (mismatch_count == 0) && (nothing_to_compare_against_count == 0))
+     if ((match_count > 0) && (mismatch_count == 0) && (nothing_to_compare_against_count == 0) && (multiple_missed_txn_count == 0))
         testcase_passed = 1'b1;
 // pragma uvmf custom check_phase end
   endfunction
@@ -552,7 +549,7 @@ class soc_ifc_scoreboard #(
   // Builds the report_phase message printed for scoreboards derived from this base 
   // Provides for customization of output formatting
   virtual function string report_message(string header, int variables [] );
-        return {$sformatf("%s PREDICTED_TRANSACTIONS=%0d MATCHES=%0d MISMATCHES=%0d NO_COMPARISON_TXN=%0d", header, variables[0], variables[1], variables[2], variables[3])}; 
+        return {$sformatf("%s PREDICTED_TRANSACTIONS=%0d MATCHES=%0d MISMATCHES=%0d NO_COMPARISON_TXN=%0d MULTIPLE_MISSED_TXN=%0d", header, variables[0], variables[1], variables[2], variables[3], variables[4])}; 
   endfunction
 
   // FUNCTION: report_phase
@@ -575,30 +572,39 @@ endclass
   // Used to facilitate reset handling for different kinds of reset
   // that may occur in soc_ifc environment.
   // "SOFT" reset (aka cptra_rst_b=0)
-  //   * Causes flush of all expected and actual transactions
+  //   * Causes flush of all expected and actual transactions after a delay
+  //     representing the eventual assertion of noncore reset
   //   * Initiates an event trigger to indicate reset was called
   // "HARD" reset (aka cptra_pwrgood=0)
   //   * Causes flush of all expected and actual transactions
   //   * Initiates an event trigger to indicate reset was called
+  // This function is called in the soc_ifc_environment prior to handle_reset
+  // in the soc_ifc_predictor.
   function void soc_ifc_scoreboard::handle_reset(string kind = "HARD");
       reset_flag kind_handled;
-      kind_handled = kind == "HARD" ? hard_reset_flag :
-                     kind == "SOFT" ? soft_reset_flag :
-                                      null;
-
-      // Flush transactions
-      soc_ifc_expected_hash.delete();
-      cptra_expected_hash  .delete();
-      ahb_expected_q.delete();
-      apb_expected_q.delete();
-
-      // Clear toggle counter
-      soc_ifc_status_monitor_struct      = '{default:0};
-      soc_ifc_status_monitor_struct_prev = '{default:0};
-      soc_ifc_status_monitor_toggle_count = '{default:2'b00};
-
-      // Event trigger
-      reset_handled.trigger(kind_handled);
+      kind_handled = kind == "HARD"    ? hard_reset_flag :
+                     kind == "SOFT"    ? soft_reset_flag :
+                     kind == "NONCORE" ? noncore_reset_flag :
+                                         null;
+
+      if (kind inside {"HARD","NONCORE"}) begin
+          `uvm_info("SCBD_HANDLE_RESET", {"On call to handle_reset of kind [", kind , "] executing scoreboard reset"}, UVM_HIGH)
+
+          // Flush transactions
+          soc_ifc_expected_hash.delete();
+          cptra_expected_hash  .delete();
+          ahb_expected_q.delete();
+          apb_expected_q.delete();
+
+          // Clear toggle counter
+          soc_ifc_status_monitor_struct      = '{default:0};
+          soc_ifc_status_monitor_struct_prev = '{default:0};
+          soc_ifc_status_monitor_toggle_count = '{default:2'b00};
+
+          // Event trigger
+          reset_handled.trigger(kind_handled);
+          `uvm_info("SCBD_HANDLE_RESET", "On call to handle_reset, triggered the event indicating an expected status transaction for internal resets", UVM_HIGH)
+      end
   endfunction
 
   // FUNCTION: disable_wait_for_scoreboard_empty
@@ -625,6 +631,12 @@ endclass
       if (apb_expected_q.size() != 0)        entries_remaining |= 1;
       while (entries_remaining) begin : while_entries_remaining
           `uvm_info("SOC_IFC_SCBD_DRAIN",$sformatf("Waiting for entries to drain. Remaining: soc_ifc_exp[%d] cptra_exp[%d] ahb_exp[%d] apb_exp[%d]", soc_ifc_expected_hash.size(), cptra_expected_hash.size(), ahb_expected_q.size(), apb_expected_q.size()),UVM_NONE)
+          begin: VERBOSE_TXN_DUMP
+              foreach (soc_ifc_expected_hash[ii]) begin `uvm_info("SOC_IFC_SCBD_DRAIN",$sformatf("soc_ifc_expected[%0d]: %s",ii,soc_ifc_expected_hash[ii].convert2string()), UVM_FULL) end
+              foreach (cptra_expected_hash  [ii]) begin `uvm_info("SOC_IFC_SCBD_DRAIN",$sformatf("cptra_expected[%0d]:   %s",ii,cptra_expected_hash  [ii].convert2string()), UVM_FULL) end
+              foreach (ahb_expected_q       [ii]) begin `uvm_info("SOC_IFC_SCBD_DRAIN",$sformatf("ahb_expected[%0d]:     %s",ii,ahb_expected_q       [ii].convert2string()), UVM_FULL) end
+              foreach (apb_expected_q       [ii]) begin `uvm_info("SOC_IFC_SCBD_DRAIN",$sformatf("apb_expected[%0d]:     %s",ii,apb_expected_q       [ii].convert2string()), UVM_FULL) end
+          end
           @entry_received;
           entries_remaining=0;
           if (soc_ifc_expected_hash.size() != 0) entries_remaining |= 1;
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/yaml/soc_ifc_environment.yaml b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/yaml/soc_ifc_environment.yaml
index a8ba2df23..111d254aa 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/yaml/soc_ifc_environment.yaml
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/yaml/soc_ifc_environment.yaml
@@ -14,6 +14,9 @@ uvmf:
       - initiator_responder: RESPONDER
         name: cptra_status_agent
         type: cptra_status
+      - initiator_responder: RESPONDER
+        name: mbox_sram_agent
+        type: mbox_sram
       analysis_components:
       - name: soc_ifc_pred
         parameters: []
@@ -67,6 +70,9 @@ uvmf:
       - driver: cptra_ctrl_agent.monitored_ap
         receiver: soc_ifc_pred.cptra_ctrl_agent_ae
         validate: 'True'
+      - driver: mbox_sram_agent.monitored_ap
+        receiver: soc_ifc_pred.mbox_sram_agent_ae
+        validate: 'True'
       - driver: soc_ifc_pred.soc_ifc_sb_ap
         receiver: soc_ifc_sb.expected_analysis_export
         validate: 'True'
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/yaml/soc_ifc_util_comp_soc_ifc_predictor.yaml b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/yaml/soc_ifc_util_comp_soc_ifc_predictor.yaml
index ed86e0948..9b07c8789 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/yaml/soc_ifc_util_comp_soc_ifc_predictor.yaml
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/yaml/soc_ifc_util_comp_soc_ifc_predictor.yaml
@@ -6,6 +6,8 @@ uvmf:
         type: soc_ifc_ctrl_transaction
       - name: cptra_ctrl_agent_ae
         type: cptra_ctrl_transaction
+      - name: mbox_sram_agent_ae
+        type: mbox_sram_transaction
       - name: ahb_slave_0_ae
         type: mvc_sequence_item_base
       - name: apb5_slave_0_ae
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/cptra_ctrl_pkg.sv b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/cptra_ctrl_pkg.sv
index 722aa9db4..196f0b473 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/cptra_ctrl_pkg.sv
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/cptra_ctrl_pkg.sv
@@ -52,6 +52,7 @@ package cptra_ctrl_pkg;
    `include "uvm_macros.svh"
 
    // pragma uvmf custom package_imports_additional begin 
+   import soc_ifc_pkg::*;
    // pragma uvmf custom package_imports_additional end
    `include "src/cptra_ctrl_macros.svh"
 
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_driver_bfm.sv b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_driver_bfm.sv
index da509ea8c..e0609dcf0 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_driver_bfm.sv
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_driver_bfm.sv
@@ -110,6 +110,8 @@ end
   reg  clear_obf_secrets_o = 'b0;
   tri  iccm_axs_blocked_i;
   reg  iccm_axs_blocked_o = 'b0;
+  tri [3:0] rv_ecc_sts_i;
+  reg [3:0] rv_ecc_sts_o = 'b0;
 
   // Bi-directional signals
   
@@ -127,6 +129,8 @@ end
   assign clear_obf_secrets_i = bus.clear_obf_secrets;
   assign bus.iccm_axs_blocked = (initiator_responder == INITIATOR) ? iccm_axs_blocked_o : 'bz;
   assign iccm_axs_blocked_i = bus.iccm_axs_blocked;
+  assign bus.rv_ecc_sts = (initiator_responder == INITIATOR) ? rv_ecc_sts_o : 'bz;
+  assign rv_ecc_sts_i = bus.rv_ecc_sts;
 
   // Proxy handle to UVM driver
   cptra_ctrl_pkg::cptra_ctrl_driver   proxy;
@@ -160,6 +164,7 @@ end
        // INITIATOR mode output signals
        clear_obf_secrets_o <= 'b0;
        iccm_axs_blocked_o <= 'b0;
+       rv_ecc_sts_o <= 'b0;
        // Bi-directional signals
 
      end
@@ -201,9 +206,11 @@ end
        // Members within the cptra_ctrl_initiator_struct:
        //   bit assert_clear_secrets ;
        //   bit iccm_axs_blocked ;
+       //   rv_ecc_sts_t pulse_rv_ecc_error ;
        // Members within the cptra_ctrl_responder_struct:
        //   bit assert_clear_secrets ;
        //   bit iccm_axs_blocked ;
+       //   rv_ecc_sts_t pulse_rv_ecc_error ;
        initiator_struct = cptra_ctrl_initiator_struct;
        //
        // Reference code;
@@ -220,15 +227,18 @@ end
        //    Initiator output signals
        //      clear_obf_secrets_o <= cptra_ctrl_initiator_struct.xyz;  //     
        //      iccm_axs_blocked_o <= cptra_ctrl_initiator_struct.xyz;  //     
+       //      rv_ecc_sts_o <= cptra_ctrl_initiator_struct.xyz;  //    [3:0] 
        //    Initiator inout signals
     // Initiate a transfer using the data received.
     @(posedge clk_i);
     clear_obf_secrets_o <= cptra_ctrl_initiator_struct.assert_clear_secrets;
     iccm_axs_blocked_o  <= cptra_ctrl_initiator_struct.iccm_axs_blocked;
+    rv_ecc_sts_o        <= cptra_ctrl_initiator_struct.pulse_rv_ecc_error;
     // Wait for the responder to complete the transfer then place the responder data into 
     // cptra_ctrl_responder_struct.
     @(posedge clk_i);
     iccm_axs_blocked_o  <= 1'b0;
+    rv_ecc_sts_o        <= '0;
     cptra_ctrl_responder_struct.assert_clear_secrets <= clear_obf_secrets_i;
     cptra_ctrl_responder_struct.iccm_axs_blocked     <= iccm_axs_blocked_i;
     responder_struct = cptra_ctrl_responder_struct;
@@ -256,9 +266,11 @@ bit first_transfer=1;
   // Variables within the cptra_ctrl_initiator_struct:
   //   bit assert_clear_secrets ;
   //   bit iccm_axs_blocked ;
+  //   rv_ecc_sts_t pulse_rv_ecc_error ;
   // Variables within the cptra_ctrl_responder_struct:
   //   bit assert_clear_secrets ;
   //   bit iccm_axs_blocked ;
+  //   rv_ecc_sts_t pulse_rv_ecc_error ;
        // Reference code;
        //    How to wait for signal value
        //      while (control_signal == 1'b1) @(posedge clk_i);
@@ -268,6 +280,7 @@ bit first_transfer=1;
        //    Responder input signals
        //      cptra_ctrl_responder_struct.xyz = clear_obf_secrets_i;  //     
        //      cptra_ctrl_responder_struct.xyz = iccm_axs_blocked_i;  //     
+       //      cptra_ctrl_responder_struct.xyz = rv_ecc_sts_i;  //    [3:0] 
        //    Responder inout signals
        //    How to assign a signal, named xyz, from an initiator struct member.   
        //    All available responder output and inout signals listed.
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_if.sv b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_if.sv
index 7f72e3111..a19c7fe26 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_if.sv
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_if.sv
@@ -35,6 +35,7 @@
 //
 // .dut_signal_port(cptra_ctrl_bus.clear_obf_secrets), // Agent output 
 // .dut_signal_port(cptra_ctrl_bus.iccm_axs_blocked), // Agent output 
+// .dut_signal_port(cptra_ctrl_bus.rv_ecc_sts), // Agent output 
 
 import uvmf_base_pkg_hdl::*;
 import cptra_ctrl_pkg_hdl::*;
@@ -45,7 +46,8 @@ interface  cptra_ctrl_if
   input tri clk, 
   input tri dummy,
   inout tri  clear_obf_secrets,
-  inout tri  iccm_axs_blocked
+  inout tri  iccm_axs_blocked,
+  inout tri [3:0] rv_ecc_sts
   );
 
 modport monitor_port 
@@ -53,7 +55,8 @@ modport monitor_port
   input clk,
   input dummy,
   input clear_obf_secrets,
-  input iccm_axs_blocked
+  input iccm_axs_blocked,
+  input rv_ecc_sts
   );
 
 modport initiator_port 
@@ -61,7 +64,8 @@ modport initiator_port
   input clk,
   input dummy,
   output clear_obf_secrets,
-  output iccm_axs_blocked
+  output iccm_axs_blocked,
+  output rv_ecc_sts
   );
 
 modport responder_port 
@@ -69,7 +73,8 @@ modport responder_port
   input clk,
   input dummy,  
   input clear_obf_secrets,
-  input iccm_axs_blocked
+  input iccm_axs_blocked,
+  input rv_ecc_sts
   );
   
 
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_macros.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_macros.svh
index bfd061c78..ba6c985f7 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_macros.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_macros.svh
@@ -65,6 +65,7 @@ typedef struct packed  { \
   `define cptra_ctrl_MONITOR_STRUCT typedef struct packed  { \
   bit assert_clear_secrets ; \
   bit iccm_axs_blocked ; \
+  rv_ecc_sts_t pulse_rv_ecc_error ; \
      } cptra_ctrl_monitor_s;
 
   `define cptra_ctrl_TO_MONITOR_STRUCT_FUNCTION \
@@ -72,7 +73,8 @@ typedef struct packed  { \
     cptra_ctrl_monitor_struct = \
             { \
             this.assert_clear_secrets , \
-            this.iccm_axs_blocked  \
+            this.iccm_axs_blocked , \
+            this.pulse_rv_ecc_error  \
             };\
     return ( cptra_ctrl_monitor_struct);\
   endfunction\
@@ -81,7 +83,8 @@ typedef struct packed  { \
   virtual function void from_monitor_struct(cptra_ctrl_monitor_s cptra_ctrl_monitor_struct);\
             {\
             this.assert_clear_secrets , \
-            this.iccm_axs_blocked  \
+            this.iccm_axs_blocked , \
+            this.pulse_rv_ecc_error  \
             } = cptra_ctrl_monitor_struct;\
   endfunction
 
@@ -93,6 +96,7 @@ typedef struct packed  { \
   `define cptra_ctrl_INITIATOR_STRUCT typedef struct packed  { \
   bit assert_clear_secrets ; \
   bit iccm_axs_blocked ; \
+  rv_ecc_sts_t pulse_rv_ecc_error ; \
      } cptra_ctrl_initiator_s;
 
   `define cptra_ctrl_TO_INITIATOR_STRUCT_FUNCTION \
@@ -100,7 +104,8 @@ typedef struct packed  { \
     cptra_ctrl_initiator_struct = \
            {\
            this.assert_clear_secrets , \
-           this.iccm_axs_blocked  \
+           this.iccm_axs_blocked , \
+           this.pulse_rv_ecc_error  \
            };\
     return ( cptra_ctrl_initiator_struct);\
   endfunction
@@ -109,7 +114,8 @@ typedef struct packed  { \
   virtual function void from_initiator_struct(cptra_ctrl_initiator_s cptra_ctrl_initiator_struct);\
            {\
            this.assert_clear_secrets , \
-           this.iccm_axs_blocked  \
+           this.iccm_axs_blocked , \
+           this.pulse_rv_ecc_error  \
            } = cptra_ctrl_initiator_struct;\
   endfunction
 
@@ -121,6 +127,7 @@ typedef struct packed  { \
   `define cptra_ctrl_RESPONDER_STRUCT typedef struct packed  { \
   bit assert_clear_secrets ; \
   bit iccm_axs_blocked ; \
+  rv_ecc_sts_t pulse_rv_ecc_error ; \
      } cptra_ctrl_responder_s;
 
   `define cptra_ctrl_TO_RESPONDER_STRUCT_FUNCTION \
@@ -128,7 +135,8 @@ typedef struct packed  { \
     cptra_ctrl_responder_struct = \
            {\
            this.assert_clear_secrets , \
-           this.iccm_axs_blocked  \
+           this.iccm_axs_blocked , \
+           this.pulse_rv_ecc_error  \
            };\
     return ( cptra_ctrl_responder_struct);\
   endfunction
@@ -137,7 +145,8 @@ typedef struct packed  { \
   virtual function void from_responder_struct(cptra_ctrl_responder_s cptra_ctrl_responder_struct);\
            {\
            this.assert_clear_secrets , \
-           this.iccm_axs_blocked  \
+           this.iccm_axs_blocked , \
+           this.pulse_rv_ecc_error  \
            } = cptra_ctrl_responder_struct;\
   endfunction
 // pragma uvmf custom additional begin
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_monitor_bfm.sv b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_monitor_bfm.sv
index 167bae11b..32506aba6 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_monitor_bfm.sv
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_monitor_bfm.sv
@@ -85,21 +85,24 @@ end
   tri dummy_i;
   tri  clear_obf_secrets_i;
   tri  iccm_axs_blocked_i;
+  tri [3:0] rv_ecc_sts_i;
   assign clk_i = bus.clk;
   assign dummy_i = bus.dummy;
   assign clear_obf_secrets_i = bus.clear_obf_secrets;
   assign iccm_axs_blocked_i = bus.iccm_axs_blocked;
+  assign rv_ecc_sts_i = bus.rv_ecc_sts;
 
   // Proxy handle to UVM monitor
   cptra_ctrl_pkg::cptra_ctrl_monitor  proxy;
   // pragma tbx oneway proxy.notify_transaction                 
 
   // pragma uvmf custom interface_item_additional begin
-  logic clear_obf_secrets_r;
-  logic iccm_axs_blocked_r;
+  logic clear_obf_secrets_r = 1'b0;
+  logic iccm_axs_blocked_r = 1'b0;
   function bit any_signal_changed();
       return |(clear_obf_secrets_i   ^  clear_obf_secrets_r  ) ||
-             |(iccm_axs_blocked_i    ^  iccm_axs_blocked_r   );
+             |(iccm_axs_blocked_i    ^  iccm_axs_blocked_r   ) ||
+             |(rv_ecc_sts_i          /* pulse no reg-stage */);
   endfunction
   // pragma uvmf custom interface_item_additional end
 
@@ -117,13 +120,17 @@ end
   // pragma uvmf custom reset_condition end
   endtask
 
-  //******************************************************************
-
-  task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf
+  // pragma uvmf custom wait_for_num_clocks begin
+  //****************************************************************************                         
+  // Inject pragmas's here to throw a warning on regeneration.
+  // Task must have automatic lifetime so that it can be concurrently invoked
+  // by multiple entities with a different wait value.
+  task automatic wait_for_num_clocks(input int unsigned count); // pragma tbx xtf
+    if (count == 0) `uvm_fatal("CFG", "wait_for_num_clocks called with count of 0 - this will lead to a hang");
     @(posedge clk_i);
-
     repeat (count-1) @(posedge clk_i);
   endtask
+  // pragma uvmf custom wait_for_num_clocks end                                                                
 
   //******************************************************************
   event go;
@@ -166,6 +173,7 @@ end
     // Available struct members:
     //     //    cptra_ctrl_monitor_struct.assert_clear_secrets
     //     //    cptra_ctrl_monitor_struct.iccm_axs_blocked
+    //     //    cptra_ctrl_monitor_struct.pulse_rv_ecc_error
     //     //
     // Reference code;
     //    How to wait for signal value
@@ -175,6 +183,7 @@ end
     //    All available input signals listed.
     //      cptra_ctrl_monitor_struct.xyz = clear_obf_secrets_i;  //     
     //      cptra_ctrl_monitor_struct.xyz = iccm_axs_blocked_i;  //
+    //      cptra_ctrl_monitor_struct.xyz = rv_ecc_sts_i;  //    [3:0]
     // pragma uvmf custom do_monitor begin
     // UVMF_CHANGE_ME : Implement protocol monitoring.  The commented reference code
     // below are examples of how to capture signal values and assign them to
@@ -193,6 +202,7 @@ end
   // Variables within the cptra_ctrl_monitor_struct:
          cptra_ctrl_monitor_struct.iccm_axs_blocked     = iccm_axs_blocked_i;
          cptra_ctrl_monitor_struct.assert_clear_secrets = clear_obf_secrets_i;
+         cptra_ctrl_monitor_struct.pulse_rv_ecc_error   = rv_ecc_sts_i;
     end
     // pragma uvmf custom do_monitor end
   endtask
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_transaction.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_transaction.svh
index fcbe42427..e756d447f 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_transaction.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_transaction.svh
@@ -34,6 +34,7 @@ class cptra_ctrl_transaction  extends uvmf_transaction_base;
 
   bit assert_clear_secrets ;
   bit iccm_axs_blocked ;
+  rv_ecc_sts_t pulse_rv_ecc_error ;
 
   //Constraints for the transaction variables:
 
@@ -116,7 +117,7 @@ class cptra_ctrl_transaction  extends uvmf_transaction_base;
   virtual function string convert2string();
     // pragma uvmf custom convert2string begin
     // UVMF_CHANGE_ME : Customize format if desired.
-    return $sformatf("assert_clear_secrets:0x%x iccm_axs_blocked:0x%x ",assert_clear_secrets,iccm_axs_blocked);
+    return $sformatf("assert_clear_secrets:0x%x iccm_axs_blocked:0x%x pulse_rv_ecc_error:0x%x %s",assert_clear_secrets,iccm_axs_blocked,pulse_rv_ecc_error,super.convert2string);
     // pragma uvmf custom convert2string end
   endfunction
 
@@ -160,6 +161,7 @@ class cptra_ctrl_transaction  extends uvmf_transaction_base;
     super.do_copy(rhs);
     this.assert_clear_secrets = RHS.assert_clear_secrets;
     this.iccm_axs_blocked = RHS.iccm_axs_blocked;
+    this.pulse_rv_ecc_error = RHS.pulse_rv_ecc_error;
     // pragma uvmf custom do_copy end
   endfunction
 
@@ -185,6 +187,7 @@ class cptra_ctrl_transaction  extends uvmf_transaction_base;
     // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer
     $add_attribute(transaction_view_h,assert_clear_secrets,"assert_clear_secrets");
     $add_attribute(transaction_view_h,iccm_axs_blocked,"iccm_axs_blocked");
+    $add_attribute(transaction_view_h,pulse_rv_ecc_error,"pulse_rv_ecc_error");
     // pragma uvmf custom add_to_wave end
     $end_transaction(transaction_view_h,end_time);
     $free_transaction(transaction_view_h);
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_transaction_coverage.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_transaction_coverage.svh
index 35a0ecff1..8a1d6e013 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_transaction_coverage.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/src/cptra_ctrl_transaction_coverage.svh
@@ -45,6 +45,7 @@ class cptra_ctrl_transaction_coverage  extends uvm_subscriber #(.T(cptra_ctrl_tr
     option.per_instance=1;
     assert_clear_secrets: coverpoint coverage_trans.assert_clear_secrets;
     iccm_axs_blocked: coverpoint coverage_trans.iccm_axs_blocked;
+    pulse_rv_ecc_error: coverpoint coverage_trans.pulse_rv_ecc_error;
     // pragma uvmf custom covergroup end
   endgroup
 
@@ -55,7 +56,6 @@ class cptra_ctrl_transaction_coverage  extends uvm_subscriber #(.T(cptra_ctrl_tr
   function new(string name="", uvm_component parent=null);
     super.new(name,parent);
     cptra_ctrl_transaction_cg=new;
-    `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging.  Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup.  Remove this warning after the covergroup has been reviewed.")
   endfunction
 
   // ****************************************************************************
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/yaml/cptra_ctrl_interface.yaml b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/yaml/cptra_ctrl_interface.yaml
index c379666ea..a8e49df4c 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/yaml/cptra_ctrl_interface.yaml
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_ctrl_pkg/yaml/cptra_ctrl_interface.yaml
@@ -20,6 +20,10 @@ uvmf:
         name: iccm_axs_blocked
         reset_value: '''bz'
         width: '1'
+      - dir: output
+        name: rv_ecc_sts
+        reset_value: '''bz'
+        width: '4'
       reset: dummy
       reset_assertion_level: 'False'
       transaction_constraints: []
@@ -36,4 +40,10 @@ uvmf:
         name: iccm_axs_blocked
         type: bit
         unpacked_dimension: ''
+      - comment: ''
+        iscompare: 'False'
+        isrand: 'False'
+        name: pulse_rv_ecc_error
+        type: rv_ecc_sts_t
+        unpacked_dimension: ''
       use_dpi_link: 'False'
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_driver_bfm.sv b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_driver_bfm.sv
index 1e899bb4f..fb0d7ec78 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_driver_bfm.sv
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_driver_bfm.sv
@@ -110,6 +110,8 @@ end
   reg  cptra_noncore_rst_b_o = 'b0;
   tri  cptra_uc_rst_b_i;
   reg  cptra_uc_rst_b_o = 'b0;
+  tri  fw_update_rst_window_i;
+  reg  fw_update_rst_window_o = 'bz;
   tri [`CLP_OBF_KEY_DWORDS-1:0][31:0] cptra_obf_key_reg_i;
   reg [`CLP_OBF_KEY_DWORDS-1:0][31:0] cptra_obf_key_reg_o = 'bz;
   tri [`CLP_OBF_FE_DWORDS-1:0][31:0] obf_field_entropy_i;
@@ -124,8 +126,12 @@ end
   reg  sha_error_intr_o = 'bz;
   tri  sha_notif_intr_i;
   reg  sha_notif_intr_o = 'bz;
+  tri  timer_intr_i;
+  reg  timer_intr_o = 'bz;
   tri [31:0] nmi_vector_i;
   reg [31:0] nmi_vector_o = 'bz;
+  tri  nmi_intr_i;
+  reg  nmi_intr_o = 'bz;
   tri  iccm_lock_i;
   reg  iccm_lock_o = 'bz;
 
@@ -145,6 +151,8 @@ end
   assign cptra_noncore_rst_b_i = bus.cptra_noncore_rst_b;
   assign bus.cptra_uc_rst_b = (initiator_responder == INITIATOR) ? cptra_uc_rst_b_o : 'bz;
   assign cptra_uc_rst_b_i = bus.cptra_uc_rst_b;
+  assign bus.fw_update_rst_window = (initiator_responder == INITIATOR) ? fw_update_rst_window_o : 'bz;
+  assign fw_update_rst_window_i = bus.fw_update_rst_window;
   assign bus.cptra_obf_key_reg = (initiator_responder == INITIATOR) ? cptra_obf_key_reg_o : 'bz;
   assign cptra_obf_key_reg_i = bus.cptra_obf_key_reg;
   assign bus.obf_field_entropy = (initiator_responder == INITIATOR) ? obf_field_entropy_o : 'bz;
@@ -159,8 +167,12 @@ end
   assign sha_error_intr_i = bus.sha_error_intr;
   assign bus.sha_notif_intr = (initiator_responder == INITIATOR) ? sha_notif_intr_o : 'bz;
   assign sha_notif_intr_i = bus.sha_notif_intr;
+  assign bus.timer_intr = (initiator_responder == INITIATOR) ? timer_intr_o : 'bz;
+  assign timer_intr_i = bus.timer_intr;
   assign bus.nmi_vector = (initiator_responder == INITIATOR) ? nmi_vector_o : 'bz;
   assign nmi_vector_i = bus.nmi_vector;
+  assign bus.nmi_intr = (initiator_responder == INITIATOR) ? nmi_intr_o : 'bz;
+  assign nmi_intr_i = bus.nmi_intr;
   assign bus.iccm_lock = (initiator_responder == INITIATOR) ? iccm_lock_o : 'bz;
   assign iccm_lock_i = bus.iccm_lock;
 
@@ -196,6 +208,7 @@ end
        // INITIATOR mode output signals
        cptra_noncore_rst_b_o <= 'b0;
        cptra_uc_rst_b_o <= 'b0;
+       fw_update_rst_window_o <= 'bz;
        cptra_obf_key_reg_o <= 'bz;
        obf_field_entropy_o <= 'bz;
        obf_uds_seed_o <= 'bz;
@@ -203,7 +216,9 @@ end
        soc_ifc_notif_intr_o <= 'bz;
        sha_error_intr_o <= 'bz;
        sha_notif_intr_o <= 'bz;
+       timer_intr_o <= 'bz;
        nmi_vector_o <= 'bz;
+       nmi_intr_o <= 'bz;
        iccm_lock_o <= 'bz;
        // Bi-directional signals
  
@@ -220,6 +235,7 @@ end
       else
           return |(cptra_noncore_rst_b_i  ^  cptra_noncore_rst_b_o      ) ||
                  |(cptra_uc_rst_b_i       ^  cptra_uc_rst_b_o           ) ||
+                 |(fw_update_rst_window_i ^  fw_update_rst_window_o     ) ||
                  |(cptra_obf_key_reg_i    ^  cptra_obf_key_reg_o        ) ||
                  |(obf_field_entropy_i    ^  obf_field_entropy_o        ) ||
                  |(obf_uds_seed_i         ^  obf_uds_seed_o             ) ||
@@ -227,7 +243,9 @@ end
                  |(soc_ifc_notif_intr_i   & !soc_ifc_notif_intr_o       ) ||
                  |(sha_error_intr_i       & !sha_error_intr_o           ) ||
                  |(sha_notif_intr_i       & !sha_notif_intr_o           ) ||
+                 |(timer_intr_i           & !timer_intr_o               ) ||
                  |(nmi_vector_i           ^  nmi_vector_o               ) ||
+                 |(nmi_intr_i             & !nmi_intr_o                 ) ||
                  |(iccm_lock_i            ^  iccm_lock_o                );
   endfunction
   // pragma uvmf custom interface_item_additional end
@@ -267,24 +285,30 @@ end
        //   bit soc_ifc_notif_intr_pending ;
        //   bit sha_err_intr_pending ;
        //   bit sha_notif_intr_pending ;
+       //   bit timer_intr_pending ;
        //   bit noncore_rst_asserted ;
        //   bit uc_rst_asserted ;
+       //   bit fw_update_rst_window ;
        //   bit [`CLP_OBF_KEY_DWORDS-1:0] [31:0] cptra_obf_key_reg ;
        //   bit [`CLP_OBF_FE_DWORDS-1:0] [31:0] obf_field_entropy ;
        //   bit [`CLP_OBF_UDS_DWORDS-1:0] [31:0] obf_uds_seed ;
        //   bit [31:0] nmi_vector ;
+       //   bit nmi_intr_pending ;
        //   bit iccm_locked ;
        // Members within the cptra_status_responder_struct:
        //   bit soc_ifc_err_intr_pending ;
        //   bit soc_ifc_notif_intr_pending ;
        //   bit sha_err_intr_pending ;
        //   bit sha_notif_intr_pending ;
+       //   bit timer_intr_pending ;
        //   bit noncore_rst_asserted ;
        //   bit uc_rst_asserted ;
+       //   bit fw_update_rst_window ;
        //   bit [`CLP_OBF_KEY_DWORDS-1:0] [31:0] cptra_obf_key_reg ;
        //   bit [`CLP_OBF_FE_DWORDS-1:0] [31:0] obf_field_entropy ;
        //   bit [`CLP_OBF_UDS_DWORDS-1:0] [31:0] obf_uds_seed ;
        //   bit [31:0] nmi_vector ;
+       //   bit nmi_intr_pending ;
        //   bit iccm_locked ;
        initiator_struct = cptra_status_initiator_struct;
        //
@@ -302,6 +326,7 @@ end
        //    Initiator output signals
        //      cptra_noncore_rst_b_o <= cptra_status_initiator_struct.xyz;  //     
        //      cptra_uc_rst_b_o <= cptra_status_initiator_struct.xyz;  //
+       //      fw_update_rst_window_o <= cptra_status_initiator_struct.xyz;  //
        //      cptra_obf_key_reg_o <= cptra_status_initiator_struct.xyz;  //    [`CLP_OBF_KEY_DWORDS-1:0][31:0] 
        //      obf_field_entropy_o <= cptra_status_initiator_struct.xyz;  //    [`CLP_OBF_FE_DWORDS-1:0][31:0] 
        //      obf_uds_seed_o <= cptra_status_initiator_struct.xyz;  //    [`CLP_OBF_UDS_DWORDS-1:0][31:0] 
@@ -309,7 +334,9 @@ end
        //      soc_ifc_notif_intr_o <= cptra_status_initiator_struct.xyz;  //    
        //      sha_error_intr_o <= cptra_status_initiator_struct.xyz;  //     
        //      sha_notif_intr_o <= cptra_status_initiator_struct.xyz;  //     
+       //      timer_intr_o <= cptra_status_initiator_struct.xyz;  //     
        //      nmi_vector_o <= cptra_status_initiator_struct.xyz;  //    [31:0]
+       //      nmi_intr_o <= cptra_status_initiator_struct.xyz;  //     
        //      iccm_lock_o <= cptra_status_initiator_struct.xyz;  //     
        //    Initiator inout signals
     // Initiate a transfer using the data received.
@@ -346,24 +373,30 @@ bit first_transfer=1;
   //   bit soc_ifc_notif_intr_pending ;
   //   bit sha_err_intr_pending ;
   //   bit sha_notif_intr_pending ;
+  //   bit timer_intr_pending ;
   //   bit noncore_rst_asserted ;
   //   bit uc_rst_asserted ;
+  //   bit fw_update_rst_window ;
   //   bit [`CLP_OBF_KEY_DWORDS-1:0] [31:0] cptra_obf_key_reg ;
   //   bit [`CLP_OBF_FE_DWORDS-1:0] [31:0] obf_field_entropy ;
   //   bit [`CLP_OBF_UDS_DWORDS-1:0] [31:0] obf_uds_seed ;
   //   bit [31:0] nmi_vector ;
+  //   bit nmi_intr_pending ;
   //   bit iccm_locked ;
   // Variables within the cptra_status_responder_struct:
   //   bit soc_ifc_err_intr_pending ;
   //   bit soc_ifc_notif_intr_pending ;
   //   bit sha_err_intr_pending ;
   //   bit sha_notif_intr_pending ;
+  //   bit timer_intr_pending ;
   //   bit noncore_rst_asserted ;
   //   bit uc_rst_asserted ;
+  //   bit fw_update_rst_window ;
   //   bit [`CLP_OBF_KEY_DWORDS-1:0] [31:0] cptra_obf_key_reg ;
   //   bit [`CLP_OBF_FE_DWORDS-1:0] [31:0] obf_field_entropy ;
   //   bit [`CLP_OBF_UDS_DWORDS-1:0] [31:0] obf_uds_seed ;
   //   bit [31:0] nmi_vector ;
+  //   bit nmi_intr_pending ;
   //   bit iccm_locked ;
        // Reference code;
        //    How to wait for signal value
@@ -374,6 +407,7 @@ bit first_transfer=1;
        //    Responder input signals
        //      cptra_status_responder_struct.xyz = cptra_noncore_rst_b_i;  //     
        //      cptra_status_responder_struct.xyz = cptra_uc_rst_b_i;  //     
+       //      cptra_status_responder_struct.xyz = fw_update_rst_window_i;  //     
        //      cptra_status_responder_struct.xyz = cptra_obf_key_reg_i;  //    [`CLP_OBF_KEY_DWORDS-1:0][31:0] 
        //      cptra_status_responder_struct.xyz = obf_field_entropy_i;  //    [`CLP_OBF_FE_DWORDS-1:0][31:0] 
        //      cptra_status_responder_struct.xyz = obf_uds_seed_i;  //    [`CLP_OBF_UDS_DWORDS-1:0][31:0] 
@@ -381,7 +415,9 @@ bit first_transfer=1;
        //      cptra_status_responder_struct.xyz = soc_ifc_notif_intr_i;  //   
        //      cptra_status_responder_struct.xyz = sha_error_intr_i;  //     
        //      cptra_status_responder_struct.xyz = sha_notif_intr_i;  //     
+       //      cptra_status_responder_struct.xyz = timer_intr_i;  //     
        //      cptra_status_responder_struct.xyz = nmi_vector_i;  //    [31:0] 
+       //      cptra_status_responder_struct.xyz = nmi_intr_i;  //     
        //      cptra_status_responder_struct.xyz = iccm_lock_i;  //     
        //    Responder inout signals
        //    How to assign a signal, named xyz, from an initiator struct member.   
@@ -400,16 +436,19 @@ bit first_transfer=1;
 //  end
     // Wait for next transfer then gather info from intiator about the transfer.
     // Place the data into the cptra_status_initiator_struct.
-    do begin
+    @(posedge clk_i);
+    while (!any_signal_changed()) begin
         soc_ifc_error_intr_o           <= soc_ifc_error_intr_i;
         soc_ifc_notif_intr_o           <= soc_ifc_notif_intr_i;
         sha_error_intr_o               <= sha_error_intr_i    ;
         sha_notif_intr_o               <= sha_notif_intr_i    ;
+        timer_intr_o                   <= timer_intr_i        ;
+        nmi_intr_o                     <= nmi_intr_i          ;
         @(posedge clk_i);
     end
-    while (!any_signal_changed());
     cptra_noncore_rst_b_o          <= cptra_noncore_rst_b_i ;
     cptra_uc_rst_b_o               <= cptra_uc_rst_b_i      ;
+    fw_update_rst_window_o         <= fw_update_rst_window_i;
     cptra_obf_key_reg_o            <= cptra_obf_key_reg_i   ;
     obf_field_entropy_o            <= obf_field_entropy_i   ;
     obf_uds_seed_o                 <= obf_uds_seed_i        ;
@@ -417,7 +456,9 @@ bit first_transfer=1;
     soc_ifc_notif_intr_o           <= soc_ifc_notif_intr_i  ;
     sha_error_intr_o               <= sha_error_intr_i      ;
     sha_notif_intr_o               <= sha_notif_intr_i      ;
+    timer_intr_o                   <= timer_intr_i          ;
     nmi_vector_o                   <= nmi_vector_i          ;
+    nmi_intr_o                     <= nmi_intr_i            ;
     iccm_lock_o                    <= iccm_lock_i           ;
 //    @(posedge clk_i);
     first_transfer = 0;
@@ -427,12 +468,15 @@ bit first_transfer=1;
          cptra_status_initiator_struct.soc_ifc_notif_intr_pending = soc_ifc_notif_intr_i;
          cptra_status_initiator_struct.sha_err_intr_pending       = sha_error_intr_i;
          cptra_status_initiator_struct.sha_notif_intr_pending     = sha_notif_intr_i;
+         cptra_status_initiator_struct.timer_intr_pending         = timer_intr_i;
          cptra_status_initiator_struct.noncore_rst_asserted       = !cptra_noncore_rst_b_i;
          cptra_status_initiator_struct.uc_rst_asserted            = !cptra_uc_rst_b_i;
+         cptra_status_initiator_struct.fw_update_rst_window       = fw_update_rst_window_i;
          cptra_status_initiator_struct.cptra_obf_key_reg          = cptra_obf_key_reg_i;
          cptra_status_initiator_struct.obf_field_entropy          = obf_field_entropy_i;
          cptra_status_initiator_struct.obf_uds_seed               = obf_uds_seed_i;
          cptra_status_initiator_struct.nmi_vector                 = nmi_vector_i;
+         cptra_status_initiator_struct.nmi_intr_pending           = nmi_intr_i;
          cptra_status_initiator_struct.iccm_locked                = iccm_lock_i;
     end
   endtask
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_if.sv b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_if.sv
index 3835f69b7..15468ad29 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_if.sv
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_if.sv
@@ -35,6 +35,7 @@
 //
 // .dut_signal_port(cptra_status_bus.cptra_noncore_rst_b), // Agent output 
 // .dut_signal_port(cptra_status_bus.cptra_uc_rst_b), // Agent output 
+// .dut_signal_port(cptra_status_bus.fw_update_rst_window), // Agent output 
 // .dut_signal_port(cptra_status_bus.cptra_obf_key_reg), // Agent output 
 // .dut_signal_port(cptra_status_bus.obf_field_entropy), // Agent output 
 // .dut_signal_port(cptra_status_bus.obf_uds_seed), // Agent output 
@@ -42,7 +43,9 @@
 // .dut_signal_port(cptra_status_bus.soc_ifc_notif_intr), // Agent output 
 // .dut_signal_port(cptra_status_bus.sha_error_intr), // Agent output 
 // .dut_signal_port(cptra_status_bus.sha_notif_intr), // Agent output 
+// .dut_signal_port(cptra_status_bus.timer_intr), // Agent output 
 // .dut_signal_port(cptra_status_bus.nmi_vector), // Agent output 
+// .dut_signal_port(cptra_status_bus.nmi_intr), // Agent output 
 // .dut_signal_port(cptra_status_bus.iccm_lock), // Agent output 
 
 import uvmf_base_pkg_hdl::*;
@@ -55,6 +58,7 @@ interface  cptra_status_if
   input tri dummy,
   inout tri  cptra_noncore_rst_b,
   inout tri  cptra_uc_rst_b,
+  inout tri  fw_update_rst_window,
   inout tri [`CLP_OBF_KEY_DWORDS-1:0][31:0] cptra_obf_key_reg,
   inout tri [`CLP_OBF_FE_DWORDS-1:0][31:0] obf_field_entropy,
   inout tri [`CLP_OBF_UDS_DWORDS-1:0][31:0] obf_uds_seed,
@@ -62,7 +66,9 @@ interface  cptra_status_if
   inout tri  soc_ifc_notif_intr,
   inout tri  sha_error_intr,
   inout tri  sha_notif_intr,
+  inout tri  timer_intr,
   inout tri [31:0] nmi_vector,
+  inout tri  nmi_intr,
   inout tri  iccm_lock
   );
 
@@ -72,6 +78,7 @@ modport monitor_port
   input dummy,
   input cptra_noncore_rst_b,
   input cptra_uc_rst_b,
+  input fw_update_rst_window,
   input cptra_obf_key_reg,
   input obf_field_entropy,
   input obf_uds_seed,
@@ -79,7 +86,9 @@ modport monitor_port
   input soc_ifc_notif_intr,
   input sha_error_intr,
   input sha_notif_intr,
+  input timer_intr,
   input nmi_vector,
+  input nmi_intr,
   input iccm_lock
   );
 
@@ -89,6 +98,7 @@ modport initiator_port
   input dummy,
   output cptra_noncore_rst_b,
   output cptra_uc_rst_b,
+  output fw_update_rst_window,
   output cptra_obf_key_reg,
   output obf_field_entropy,
   output obf_uds_seed,
@@ -96,7 +106,9 @@ modport initiator_port
   output soc_ifc_notif_intr,
   output sha_error_intr,
   output sha_notif_intr,
+  output timer_intr,
   output nmi_vector,
+  output nmi_intr,
   output iccm_lock
   );
 
@@ -106,6 +118,7 @@ modport responder_port
   input dummy,  
   input cptra_noncore_rst_b,
   input cptra_uc_rst_b,
+  input fw_update_rst_window,
   input cptra_obf_key_reg,
   input obf_field_entropy,
   input obf_uds_seed,
@@ -113,7 +126,9 @@ modport responder_port
   input soc_ifc_notif_intr,
   input sha_error_intr,
   input sha_notif_intr,
+  input timer_intr,
   input nmi_vector,
+  input nmi_intr,
   input iccm_lock
   );
   
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_macros.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_macros.svh
index 7afa64a0a..c17f0bbe4 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_macros.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_macros.svh
@@ -67,12 +67,15 @@ typedef struct packed  { \
   bit soc_ifc_notif_intr_pending ; \
   bit sha_err_intr_pending ; \
   bit sha_notif_intr_pending ; \
+  bit timer_intr_pending ; \
   bit noncore_rst_asserted ; \
   bit uc_rst_asserted ; \
+  bit fw_update_rst_window ; \
   bit [`CLP_OBF_KEY_DWORDS-1:0] [31:0] cptra_obf_key_reg ; \
   bit [`CLP_OBF_FE_DWORDS-1:0] [31:0] obf_field_entropy ; \
   bit [`CLP_OBF_UDS_DWORDS-1:0] [31:0] obf_uds_seed ; \
   bit [31:0] nmi_vector ; \
+  bit nmi_intr_pending ; \
   bit iccm_locked ; \
      } cptra_status_monitor_s;
 
@@ -84,12 +87,15 @@ typedef struct packed  { \
             this.soc_ifc_notif_intr_pending , \
             this.sha_err_intr_pending , \
             this.sha_notif_intr_pending , \
+            this.timer_intr_pending , \
             this.noncore_rst_asserted , \
             this.uc_rst_asserted , \
+            this.fw_update_rst_window , \
             this.cptra_obf_key_reg , \
             this.obf_field_entropy , \
             this.obf_uds_seed , \
             this.nmi_vector , \
+            this.nmi_intr_pending , \
             this.iccm_locked  \
             };\
     return ( cptra_status_monitor_struct);\
@@ -102,12 +108,15 @@ typedef struct packed  { \
             this.soc_ifc_notif_intr_pending , \
             this.sha_err_intr_pending , \
             this.sha_notif_intr_pending , \
+            this.timer_intr_pending , \
             this.noncore_rst_asserted , \
             this.uc_rst_asserted , \
+            this.fw_update_rst_window , \
             this.cptra_obf_key_reg , \
             this.obf_field_entropy , \
             this.obf_uds_seed , \
             this.nmi_vector , \
+            this.nmi_intr_pending , \
             this.iccm_locked  \
             } = cptra_status_monitor_struct;\
   endfunction
@@ -122,12 +131,15 @@ typedef struct packed  { \
   bit soc_ifc_notif_intr_pending ; \
   bit sha_err_intr_pending ; \
   bit sha_notif_intr_pending ; \
+  bit timer_intr_pending ; \
   bit noncore_rst_asserted ; \
   bit uc_rst_asserted ; \
+  bit fw_update_rst_window ; \
   bit [`CLP_OBF_KEY_DWORDS-1:0] [31:0] cptra_obf_key_reg ; \
   bit [`CLP_OBF_FE_DWORDS-1:0] [31:0] obf_field_entropy ; \
   bit [`CLP_OBF_UDS_DWORDS-1:0] [31:0] obf_uds_seed ; \
   bit [31:0] nmi_vector ; \
+  bit nmi_intr_pending ; \
   bit iccm_locked ; \
      } cptra_status_initiator_s;
 
@@ -139,12 +151,15 @@ typedef struct packed  { \
            this.soc_ifc_notif_intr_pending , \
            this.sha_err_intr_pending , \
            this.sha_notif_intr_pending , \
+           this.timer_intr_pending , \
            this.noncore_rst_asserted , \
            this.uc_rst_asserted , \
+           this.fw_update_rst_window , \
            this.cptra_obf_key_reg , \
            this.obf_field_entropy , \
            this.obf_uds_seed , \
            this.nmi_vector , \
+           this.nmi_intr_pending , \
            this.iccm_locked  \
            };\
     return ( cptra_status_initiator_struct);\
@@ -157,12 +172,15 @@ typedef struct packed  { \
            this.soc_ifc_notif_intr_pending , \
            this.sha_err_intr_pending , \
            this.sha_notif_intr_pending , \
+           this.timer_intr_pending , \
            this.noncore_rst_asserted , \
            this.uc_rst_asserted , \
+           this.fw_update_rst_window , \
            this.cptra_obf_key_reg , \
            this.obf_field_entropy , \
            this.obf_uds_seed , \
            this.nmi_vector , \
+           this.nmi_intr_pending , \
            this.iccm_locked  \
            } = cptra_status_initiator_struct;\
   endfunction
@@ -177,12 +195,15 @@ typedef struct packed  { \
   bit soc_ifc_notif_intr_pending ; \
   bit sha_err_intr_pending ; \
   bit sha_notif_intr_pending ; \
+  bit timer_intr_pending ; \
   bit noncore_rst_asserted ; \
   bit uc_rst_asserted ; \
+  bit fw_update_rst_window ; \
   bit [`CLP_OBF_KEY_DWORDS-1:0] [31:0] cptra_obf_key_reg ; \
   bit [`CLP_OBF_FE_DWORDS-1:0] [31:0] obf_field_entropy ; \
   bit [`CLP_OBF_UDS_DWORDS-1:0] [31:0] obf_uds_seed ; \
   bit [31:0] nmi_vector ; \
+  bit nmi_intr_pending ; \
   bit iccm_locked ; \
      } cptra_status_responder_s;
 
@@ -194,12 +215,15 @@ typedef struct packed  { \
            this.soc_ifc_notif_intr_pending , \
            this.sha_err_intr_pending , \
            this.sha_notif_intr_pending , \
+           this.timer_intr_pending , \
            this.noncore_rst_asserted , \
            this.uc_rst_asserted , \
+           this.fw_update_rst_window , \
            this.cptra_obf_key_reg , \
            this.obf_field_entropy , \
            this.obf_uds_seed , \
            this.nmi_vector , \
+           this.nmi_intr_pending , \
            this.iccm_locked  \
            };\
     return ( cptra_status_responder_struct);\
@@ -212,12 +236,15 @@ typedef struct packed  { \
            this.soc_ifc_notif_intr_pending , \
            this.sha_err_intr_pending , \
            this.sha_notif_intr_pending , \
+           this.timer_intr_pending , \
            this.noncore_rst_asserted , \
            this.uc_rst_asserted , \
+           this.fw_update_rst_window , \
            this.cptra_obf_key_reg , \
            this.obf_field_entropy , \
            this.obf_uds_seed , \
            this.nmi_vector , \
+           this.nmi_intr_pending , \
            this.iccm_locked  \
            } = cptra_status_responder_struct;\
   endfunction
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_monitor.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_monitor.svh
index ce2b62266..50d6612ba 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_monitor.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_monitor.svh
@@ -103,7 +103,8 @@ endclass
 
 // pragma uvmf custom external begin
 task cptra_status_monitor::handle_reset(string kind = "HARD");
-    txn_key = 0;
+    if (kind inside {"HARD", "NONCORE"})
+        txn_key = 0;
 endtask
 // pragma uvmf custom external end
 
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_monitor_bfm.sv b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_monitor_bfm.sv
index 62ecb025a..9932169ff 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_monitor_bfm.sv
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_monitor_bfm.sv
@@ -85,6 +85,7 @@ end
   tri dummy_i;
   tri  cptra_noncore_rst_b_i;
   tri  cptra_uc_rst_b_i;
+  tri  fw_update_rst_window_i;
   tri [`CLP_OBF_KEY_DWORDS-1:0][31:0] cptra_obf_key_reg_i;
   tri [`CLP_OBF_FE_DWORDS-1:0][31:0] obf_field_entropy_i;
   tri [`CLP_OBF_UDS_DWORDS-1:0][31:0] obf_uds_seed_i;
@@ -92,12 +93,15 @@ end
   tri  soc_ifc_notif_intr_i;
   tri  sha_error_intr_i;
   tri  sha_notif_intr_i;
+  tri  timer_intr_i;
   tri [31:0] nmi_vector_i;
+  tri  nmi_intr_i;
   tri  iccm_lock_i;
   assign clk_i = bus.clk;
   assign dummy_i = bus.dummy;
   assign cptra_noncore_rst_b_i = bus.cptra_noncore_rst_b;
   assign cptra_uc_rst_b_i = bus.cptra_uc_rst_b;
+  assign fw_update_rst_window_i = bus.fw_update_rst_window;
   assign cptra_obf_key_reg_i = bus.cptra_obf_key_reg;
   assign obf_field_entropy_i = bus.obf_field_entropy;
   assign obf_uds_seed_i = bus.obf_uds_seed;
@@ -105,7 +109,9 @@ end
   assign soc_ifc_notif_intr_i = bus.soc_ifc_notif_intr;
   assign sha_error_intr_i = bus.sha_error_intr;
   assign sha_notif_intr_i = bus.sha_notif_intr;
+  assign timer_intr_i = bus.timer_intr;
   assign nmi_vector_i = bus.nmi_vector;
+  assign nmi_intr_i = bus.nmi_intr;
   assign iccm_lock_i = bus.iccm_lock;
 
   // Proxy handle to UVM monitor
@@ -115,6 +121,7 @@ end
   // pragma uvmf custom interface_item_additional begin
   reg  cptra_noncore_rst_b_o = 'b0;
   reg  cptra_uc_rst_b_o = 'b0;
+  reg  fw_update_rst_window_o = 'b0;
   reg [`CLP_OBF_KEY_DWORDS-1:0][31:0] cptra_obf_key_reg_o = 'b0;
   reg [`CLP_OBF_FE_DWORDS-1:0][31:0] obf_field_entropy_o = 'b0;
   reg [`CLP_OBF_UDS_DWORDS-1:0][31:0] obf_uds_seed_o = 'b0;
@@ -122,7 +129,9 @@ end
   reg  soc_ifc_notif_intr_o = 'b0;
   reg  sha_error_intr_o = 'b0;
   reg  sha_notif_intr_o = 'b0;
+  reg  timer_intr_o = 'b0;
   reg [31:0] nmi_vector_o = 'b0;
+  reg  nmi_intr_o = 'b0;
   reg  iccm_lock_o = 'b0;
   function bit any_signal_changed();
       if (!cptra_noncore_rst_b_o)
@@ -133,6 +142,7 @@ end
       else
           return |(cptra_noncore_rst_b_i  ^  cptra_noncore_rst_b_o      ) ||
                  |(cptra_uc_rst_b_i       ^  cptra_uc_rst_b_o           ) ||
+                 |(fw_update_rst_window_i ^  fw_update_rst_window_o     ) ||
                  |(cptra_obf_key_reg_i    ^  cptra_obf_key_reg_o        ) ||
                  |(obf_field_entropy_i    ^  obf_field_entropy_o        ) ||
                  |(obf_uds_seed_i         ^  obf_uds_seed_o             ) ||
@@ -140,7 +150,9 @@ end
                  |(soc_ifc_notif_intr_i   & !soc_ifc_notif_intr_o       ) ||
                  |(sha_error_intr_i       & !sha_error_intr_o           ) ||
                  |(sha_notif_intr_i       & !sha_notif_intr_o           ) ||
+                 |(timer_intr_i           & !timer_intr_o               ) ||
                  |(nmi_vector_i           ^  nmi_vector_o               ) ||
+                 |(nmi_intr_i             & !nmi_intr_o                 ) ||
                  |(iccm_lock_i            ^  iccm_lock_o                );
   endfunction
   // pragma uvmf custom interface_item_additional end
@@ -159,13 +171,17 @@ end
   // pragma uvmf custom reset_condition end
   endtask
 
-  //******************************************************************
-
-  task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf
+  // pragma uvmf custom wait_for_num_clocks begin
+  //****************************************************************************                         
+  // Inject pragmas's here to throw a warning on regeneration.
+  // Task must have automatic lifetime so that it can be concurrently invoked
+  // by multiple entities with a different wait value.
+  task automatic wait_for_num_clocks(input int unsigned count); // pragma tbx xtf
+    if (count == 0) `uvm_fatal("CFG", "wait_for_num_clocks called with count of 0 - this will lead to a hang");
     @(posedge clk_i);
-
     repeat (count-1) @(posedge clk_i);
   endtask
+  // pragma uvmf custom wait_for_num_clocks end                                                                
 
   //******************************************************************
   event go;
@@ -210,12 +226,15 @@ end
     //     //    cptra_status_monitor_struct.soc_ifc_notif_intr_pending
     //     //    cptra_status_monitor_struct.sha_err_intr_pending
     //     //    cptra_status_monitor_struct.sha_notif_intr_pending
+    //     //    cptra_status_monitor_struct.timer_intr_pending
     //     //    cptra_status_monitor_struct.noncore_rst_asserted
     //     //    cptra_status_monitor_struct.uc_rst_asserted
+    //     //    cptra_status_monitor_struct.fw_update_rst_window
     //     //    cptra_status_monitor_struct.cptra_obf_key_reg
     //     //    cptra_status_monitor_struct.obf_field_entropy
     //     //    cptra_status_monitor_struct.obf_uds_seed
     //     //    cptra_status_monitor_struct.nmi_vector
+    //     //    cptra_status_monitor_struct.nmi_intr_pending
     //     //    cptra_status_monitor_struct.iccm_locked
     //     //
     // Reference code;
@@ -226,6 +245,7 @@ end
     //    All available input signals listed.
     //      cptra_status_monitor_struct.xyz = cptra_noncore_rst_b_i;  //     
     //      cptra_status_monitor_struct.xyz = cptra_uc_rst_b_i;  //     
+    //      cptra_status_monitor_struct.xyz = fw_update_rst_window_i;  //     
     //      cptra_status_monitor_struct.xyz = cptra_obf_key_reg_i;  //    [`CLP_OBF_KEY_DWORDS-1:0][31:0] 
     //      cptra_status_monitor_struct.xyz = obf_field_entropy_i;  //    [`CLP_OBF_FE_DWORDS-1:0][31:0] 
     //      cptra_status_monitor_struct.xyz = obf_uds_seed_i;  //    [`CLP_OBF_UDS_DWORDS-1:0][31:0] 
@@ -233,7 +253,9 @@ end
     //      cptra_status_monitor_struct.xyz = soc_ifc_notif_intr_i;  //     
     //      cptra_status_monitor_struct.xyz = sha_error_intr_i;  //     
     //      cptra_status_monitor_struct.xyz = sha_notif_intr_i;  //     
+    //      cptra_status_monitor_struct.xyz = timer_intr_i;  //     
     //      cptra_status_monitor_struct.xyz = nmi_vector_i;  //    [31:0] 
+    //      cptra_status_monitor_struct.xyz = nmi_intr_i;  //     
     //      cptra_status_monitor_struct.xyz = iccm_lock_i;  //     
     // pragma uvmf custom do_monitor begin
     // UVMF_CHANGE_ME : Implement protocol monitoring.  The commented reference code
@@ -253,10 +275,13 @@ end
         soc_ifc_notif_intr_o           <= soc_ifc_notif_intr_i  ;
         sha_error_intr_o               <= sha_error_intr_i      ;
         sha_notif_intr_o               <= sha_notif_intr_i      ;
+        timer_intr_o                   <= timer_intr_i          ;
+        nmi_intr_o                     <= nmi_intr_i            ;
         @(posedge clk_i);
     end
     cptra_noncore_rst_b_o          <= cptra_noncore_rst_b_i ;
     cptra_uc_rst_b_o               <= cptra_uc_rst_b_i      ;
+    fw_update_rst_window_o         <= fw_update_rst_window_i;
     cptra_obf_key_reg_o            <= cptra_obf_key_reg_i   ;
     obf_field_entropy_o            <= obf_field_entropy_i   ;
     obf_uds_seed_o                 <= obf_uds_seed_i        ;
@@ -264,21 +289,26 @@ end
     soc_ifc_notif_intr_o           <= soc_ifc_notif_intr_i  ;
     sha_error_intr_o               <= sha_error_intr_i      ;
     sha_notif_intr_o               <= sha_notif_intr_i      ;
+    timer_intr_o                   <= timer_intr_i          ;
     nmi_vector_o                   <= nmi_vector_i          ;
+    nmi_intr_o                     <= nmi_intr_i            ;
     iccm_lock_o                    <= iccm_lock_i           ;
 //    @(posedge clk_i);
     begin: build_return_struct
   // Variables within the cptra_status_initiator_struct:
          cptra_status_monitor_struct.noncore_rst_asserted       = !cptra_noncore_rst_b_i;
          cptra_status_monitor_struct.uc_rst_asserted            = !cptra_uc_rst_b_i;
+         cptra_status_monitor_struct.fw_update_rst_window       =  fw_update_rst_window_i;
          cptra_status_monitor_struct.soc_ifc_err_intr_pending   =  soc_ifc_error_intr_i;
          cptra_status_monitor_struct.soc_ifc_notif_intr_pending =  soc_ifc_notif_intr_i;
          cptra_status_monitor_struct.sha_err_intr_pending       =  sha_error_intr_i;
          cptra_status_monitor_struct.sha_notif_intr_pending     =  sha_notif_intr_i;
+         cptra_status_monitor_struct.timer_intr_pending         =  timer_intr_i;
          cptra_status_monitor_struct.cptra_obf_key_reg          =  cptra_obf_key_reg_i;
          cptra_status_monitor_struct.obf_field_entropy          =  obf_field_entropy_i;
          cptra_status_monitor_struct.obf_uds_seed               =  obf_uds_seed_i;
          cptra_status_monitor_struct.nmi_vector                 =  nmi_vector_i;
+         cptra_status_monitor_struct.nmi_intr_pending           =  nmi_intr_i;
          cptra_status_monitor_struct.iccm_locked                =  iccm_lock_i;
     end
     // pragma uvmf custom do_monitor end
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_transaction.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_transaction.svh
index 106311533..5e8e7edb3 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_transaction.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_transaction.svh
@@ -36,12 +36,15 @@ class cptra_status_transaction  extends uvmf_transaction_base;
   bit soc_ifc_notif_intr_pending ;
   bit sha_err_intr_pending ;
   bit sha_notif_intr_pending ;
+  bit timer_intr_pending ;
   bit noncore_rst_asserted ;
   bit uc_rst_asserted ;
+  bit fw_update_rst_window ;
   bit [`CLP_OBF_KEY_DWORDS-1:0] [31:0] cptra_obf_key_reg ;
   bit [`CLP_OBF_FE_DWORDS-1:0] [31:0] obf_field_entropy ;
   bit [`CLP_OBF_UDS_DWORDS-1:0] [31:0] obf_uds_seed ;
   bit [31:0] nmi_vector ;
+  bit nmi_intr_pending ;
   bit iccm_locked ;
 
   //Constraints for the transaction variables:
@@ -125,7 +128,7 @@ class cptra_status_transaction  extends uvmf_transaction_base;
   virtual function string convert2string();
     // pragma uvmf custom convert2string begin
     // UVMF_CHANGE_ME : Customize format if desired.
-    return $sformatf("soc_ifc_err_intr_pending:0x%x soc_ifc_notif_intr_pending:0x%x sha_err_intr_pending:0x%x sha_notif_intr_pending:0x%x noncore_rst_asserted:0x%x uc_rst_asserted:0x%x cptra_obf_key_reg:0x%x obf_field_entropy:0x%x obf_uds_seed:0x%x nmi_vector:0x%x iccm_locked:0x%x ",soc_ifc_err_intr_pending,soc_ifc_notif_intr_pending,sha_err_intr_pending,sha_notif_intr_pending,noncore_rst_asserted,uc_rst_asserted,cptra_obf_key_reg,obf_field_entropy,obf_uds_seed,nmi_vector,iccm_locked);
+    return $sformatf("soc_ifc_err_intr_pending:0x%x soc_ifc_notif_intr_pending:0x%x sha_err_intr_pending:0x%x sha_notif_intr_pending:0x%x timer_intr_pending:0x%x noncore_rst_asserted:0x%x uc_rst_asserted:0x%x fw_update_rst_window:0x%x cptra_obf_key_reg:0x%x obf_field_entropy:0x%x obf_uds_seed:0x%x nmi_vector:0x%x nmi_intr_pending:0x%x iccm_locked:0x%x %s",soc_ifc_err_intr_pending,soc_ifc_notif_intr_pending,sha_err_intr_pending,sha_notif_intr_pending,timer_intr_pending,noncore_rst_asserted,uc_rst_asserted,fw_update_rst_window,cptra_obf_key_reg,obf_field_entropy,obf_uds_seed,nmi_vector,nmi_intr_pending,iccm_locked,super.convert2string());
     // pragma uvmf custom convert2string end
   endfunction
 
@@ -157,12 +160,15 @@ class cptra_status_transaction  extends uvmf_transaction_base;
             &&(this.soc_ifc_notif_intr_pending == RHS.soc_ifc_notif_intr_pending)
             &&(this.sha_err_intr_pending == RHS.sha_err_intr_pending)
             &&(this.sha_notif_intr_pending == RHS.sha_notif_intr_pending)
+            &&(this.timer_intr_pending == RHS.timer_intr_pending)
             &&(this.noncore_rst_asserted == RHS.noncore_rst_asserted)
             &&(this.uc_rst_asserted == RHS.uc_rst_asserted)
+            &&(this.fw_update_rst_window == RHS.fw_update_rst_window)
             &&(this.cptra_obf_key_reg == RHS.cptra_obf_key_reg)
             &&(this.obf_field_entropy == RHS.obf_field_entropy)
             &&(this.obf_uds_seed == RHS.obf_uds_seed)
             &&(this.nmi_vector == RHS.nmi_vector)
+            &&(this.nmi_intr_pending == RHS.nmi_intr_pending)
             &&(this.iccm_locked == RHS.iccm_locked)
             );
     // pragma uvmf custom do_compare end
@@ -182,12 +188,15 @@ class cptra_status_transaction  extends uvmf_transaction_base;
     this.soc_ifc_notif_intr_pending = RHS.soc_ifc_notif_intr_pending;
     this.sha_err_intr_pending = RHS.sha_err_intr_pending;
     this.sha_notif_intr_pending = RHS.sha_notif_intr_pending;
+    this.timer_intr_pending = RHS.timer_intr_pending;
     this.noncore_rst_asserted = RHS.noncore_rst_asserted;
     this.uc_rst_asserted = RHS.uc_rst_asserted;
+    this.fw_update_rst_window = RHS.fw_update_rst_window;
     this.cptra_obf_key_reg = RHS.cptra_obf_key_reg;
     this.obf_field_entropy = RHS.obf_field_entropy;
     this.obf_uds_seed = RHS.obf_uds_seed;
     this.nmi_vector = RHS.nmi_vector;
+    this.nmi_intr_pending = RHS.nmi_intr_pending;
     this.iccm_locked = RHS.iccm_locked;
     // pragma uvmf custom do_copy end
   endfunction
@@ -216,12 +225,15 @@ class cptra_status_transaction  extends uvmf_transaction_base;
     $add_attribute(transaction_view_h,soc_ifc_notif_intr_pending,"soc_ifc_notif_intr_pending");
     $add_attribute(transaction_view_h,sha_err_intr_pending,"sha_err_intr_pending");
     $add_attribute(transaction_view_h,sha_notif_intr_pending,"sha_notif_intr_pending");
+    $add_attribute(transaction_view_h,timer_intr_pending,"timer_intr_pending");
     $add_attribute(transaction_view_h,noncore_rst_asserted,"noncore_rst_asserted");
     $add_attribute(transaction_view_h,uc_rst_asserted,"uc_rst_asserted");
+    $add_attribute(transaction_view_h,fw_update_rst_window,"fw_update_rst_window");
     $add_attribute(transaction_view_h,cptra_obf_key_reg,"cptra_obf_key_reg");
     $add_attribute(transaction_view_h,obf_field_entropy,"obf_field_entropy");
     $add_attribute(transaction_view_h,obf_uds_seed,"obf_uds_seed");
     $add_attribute(transaction_view_h,nmi_vector,"nmi_vector");
+    $add_attribute(transaction_view_h,nmi_intr_pending,"nmi_intr_pending");
     $add_attribute(transaction_view_h,iccm_locked,"iccm_locked");
     // pragma uvmf custom add_to_wave end
     $end_transaction(transaction_view_h,end_time);
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_transaction_coverage.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_transaction_coverage.svh
index f5ab21302..e2b53b1f5 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_transaction_coverage.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/src/cptra_status_transaction_coverage.svh
@@ -28,6 +28,11 @@
 //----------------------------------------------------------------------
 //----------------------------------------------------------------------
 //
+covergroup cptra_status_transaction_bit_cg with function sample(input bit val);
+  option.per_instance = 1;
+  ea_bit: coverpoint val;
+endgroup
+
 class cptra_status_transaction_coverage  extends uvm_subscriber #(.T(cptra_status_transaction ));
 
   `uvm_component_utils( cptra_status_transaction_coverage )
@@ -35,6 +40,9 @@ class cptra_status_transaction_coverage  extends uvm_subscriber #(.T(cptra_statu
   T coverage_trans;
 
   // pragma uvmf custom class_item_additional begin
+  cptra_status_transaction_bit_cg cptra_obf_key_reg_bit_cg[`CLP_OBF_KEY_DWORDS-1:0] [31:0];
+  cptra_status_transaction_bit_cg obf_field_entropy_bit_cg[`CLP_OBF_FE_DWORDS -1:0] [31:0];
+  cptra_status_transaction_bit_cg obf_uds_seed_bit_cg     [`CLP_OBF_UDS_DWORDS-1:0] [31:0];
   // pragma uvmf custom class_item_additional end
   
   // ****************************************************************************
@@ -44,16 +52,77 @@ class cptra_status_transaction_coverage  extends uvm_subscriber #(.T(cptra_statu
     option.auto_bin_max=1024;
     option.per_instance=1;
     soc_ifc_err_intr_pending: coverpoint coverage_trans.soc_ifc_err_intr_pending;
+    soc_ifc_err_intr_transition: coverpoint coverage_trans.soc_ifc_err_intr_pending {
+        bins rise = (0 => 1);
+        bins fall = (1 => 0);
+    }
     soc_ifc_notif_intr_pending: coverpoint coverage_trans.soc_ifc_notif_intr_pending;
+    soc_ifc_notif_intr_transition: coverpoint coverage_trans.soc_ifc_notif_intr_pending {
+        bins rise = (0 => 1);
+        bins fall = (1 => 0);
+    }
     sha_err_intr_pending: coverpoint coverage_trans.sha_err_intr_pending;
+    sha_err_intr_transition: coverpoint coverage_trans.sha_err_intr_pending {
+        bins rise = (0 => 1);
+        bins fall = (1 => 0);
+    }
     sha_notif_intr_pending: coverpoint coverage_trans.sha_notif_intr_pending;
+    sha_notif_intr_transition: coverpoint coverage_trans.sha_notif_intr_pending {
+        bins rise = (0 => 1);
+        bins fall = (1 => 0);
+    }
+    timer_intr_pending: coverpoint coverage_trans.timer_intr_pending;
+    timer_intr_transition: coverpoint coverage_trans.timer_intr_pending {
+        bins rise = (0 => 1);
+        bins fall = (1 => 0);
+    }
     noncore_rst_asserted: coverpoint coverage_trans.noncore_rst_asserted;
+    noncore_rst_transition: coverpoint coverage_trans.noncore_rst_asserted {
+        bins rise = (0 => 1);
+        bins fall = (1 => 0);
+    }
     uc_rst_asserted: coverpoint coverage_trans.uc_rst_asserted;
-    cptra_obf_key_reg: coverpoint coverage_trans.cptra_obf_key_reg;
-    obf_field_entropy: coverpoint coverage_trans.obf_field_entropy;
-    obf_uds_seed: coverpoint coverage_trans.obf_uds_seed;
-    nmi_vector: coverpoint coverage_trans.nmi_vector;
+    uc_rst_transition: coverpoint coverage_trans.uc_rst_asserted {
+        bins rise = (0 => 1);
+        bins fall = (1 => 0);
+    }
+    fw_update_rst_window: coverpoint coverage_trans.fw_update_rst_window;
+    fw_update_rst_window_transition: coverpoint coverage_trans.fw_update_rst_window {
+        bins rise = (0 => 1);
+        bins fall = (1 => 0);
+    }
+    cptra_obf_key_reg: coverpoint coverage_trans.cptra_obf_key_reg {
+        bins zero_key  = {0};
+        bins rand_key  = {[1:{`CLP_OBF_KEY_DWORDS{32'hFFFF_FFFF}}-1]};
+        bins ones_key  = {{`CLP_OBF_KEY_DWORDS{32'hFFFF_FFFF}}};
+    }
+    obf_field_entropy: coverpoint coverage_trans.obf_field_entropy {
+        bins zero_fe  = {0};
+        bins rand_fe  = {[1:{`CLP_OBF_FE_DWORDS{32'hFFFF_FFFF}}-1]};
+        bins ones_fe  = {{`CLP_OBF_FE_DWORDS{32'hFFFF_FFFF}}};
+    }
+    obf_uds_seed: coverpoint coverage_trans.obf_uds_seed {
+        bins zero_uds  = {0};
+        bins rand_uds  = {[1:{`CLP_OBF_UDS_DWORDS{32'hFFFF_FFFF}}-1]};
+        bins ones_uds  = {{`CLP_OBF_UDS_DWORDS{32'hFFFF_FFFF}}};
+    }
+    nmi_vector: coverpoint coverage_trans.nmi_vector {
+                 bins zero = {32'h0};
+        wildcard bins rom  = {32'h0000_????};
+        wildcard bins iccm = {32'h400?_????};
+        wildcard bins set  = (32'h0000_0000 => 32'h400?_????);
+        wildcard bins clr  = (32'h400?_???? => 32'h0000_0000);
+    }
+    nmi_intr_pending: coverpoint coverage_trans.nmi_intr_pending;
+    nmi_intr_transition: coverpoint coverage_trans.nmi_intr_pending {
+        bins rise = (0 => 1);
+        bins fall = (1 => 0);
+    }
     iccm_locked: coverpoint coverage_trans.iccm_locked;
+    iccm_locked_transition: coverpoint coverage_trans.iccm_locked {
+        bins rise = (0 => 1);
+        bins fall = (1 => 0);
+    }
     // pragma uvmf custom covergroup end
   endgroup
 
@@ -64,7 +133,9 @@ class cptra_status_transaction_coverage  extends uvm_subscriber #(.T(cptra_statu
   function new(string name="", uvm_component parent=null);
     super.new(name,parent);
     cptra_status_transaction_cg=new;
-    `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging.  Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup.  Remove this warning after the covergroup has been reviewed.")
+    foreach (coverage_trans.cptra_obf_key_reg[dw,bt]) cptra_obf_key_reg_bit_cg[dw][bt] = new;
+    foreach (coverage_trans.obf_field_entropy[dw,bt]) obf_field_entropy_bit_cg[dw][bt] = new;
+    foreach (coverage_trans.obf_uds_seed     [dw,bt]) obf_uds_seed_bit_cg     [dw][bt] = new;
   endfunction
 
   // ****************************************************************************
@@ -73,6 +144,9 @@ class cptra_status_transaction_coverage  extends uvm_subscriber #(.T(cptra_statu
   //
   function void build_phase(uvm_phase phase);
     cptra_status_transaction_cg.set_inst_name($sformatf("cptra_status_transaction_cg_%s",get_full_name()));
+    foreach (coverage_trans.cptra_obf_key_reg[dw,bt]) cptra_obf_key_reg_bit_cg[dw][bt].set_inst_name($sformatf("cptra_obf_key_reg_bit_cg_%d_%d_%s",dw, bt, get_full_name()));
+    foreach (coverage_trans.obf_field_entropy[dw,bt]) obf_field_entropy_bit_cg[dw][bt].set_inst_name($sformatf("obf_field_entropy_bit_cg_%d_%d_%s",dw, bt, get_full_name()));
+    foreach (coverage_trans.obf_uds_seed     [dw,bt]) obf_uds_seed_bit_cg     [dw][bt].set_inst_name($sformatf("obf_uds_seed_bit_cg_%d_%d_%s",dw, bt, get_full_name()));
   endfunction
 
   // ****************************************************************************
@@ -85,6 +159,9 @@ class cptra_status_transaction_coverage  extends uvm_subscriber #(.T(cptra_statu
     `uvm_info("COV","Received transaction",UVM_HIGH);
     coverage_trans = t;
     cptra_status_transaction_cg.sample();
+    foreach (coverage_trans.cptra_obf_key_reg[dw,bt]) cptra_obf_key_reg_bit_cg[dw][bt].sample(coverage_trans.cptra_obf_key_reg[dw][bt]);
+    foreach (coverage_trans.obf_field_entropy[dw,bt]) obf_field_entropy_bit_cg[dw][bt].sample(coverage_trans.obf_field_entropy[dw][bt]);
+    foreach (coverage_trans.obf_uds_seed     [dw,bt]) obf_uds_seed_bit_cg     [dw][bt].sample(coverage_trans.obf_uds_seed     [dw][bt]);
   endfunction
 
 endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/yaml/cptra_status_interface.yaml b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/yaml/cptra_status_interface.yaml
index f1c95429b..9622bc4dd 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/yaml/cptra_status_interface.yaml
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/cptra_status_pkg/yaml/cptra_status_interface.yaml
@@ -20,6 +20,10 @@ uvmf:
         name: cptra_uc_rst_b
         reset_value: '''bz'
         width: '1'
+      - dir: output
+        name: fw_update_rst_window
+        reset_value: '''bz'
+        width: '1'
       - dir: output
         name: cptra_obf_key_reg
         reset_value: '''bz'
@@ -48,10 +52,18 @@ uvmf:
         name: sha_notif_intr
         reset_value: '''bz'
         width: '1'
+      - dir: output
+        name: timer_intr
+        reset_value: '''bz'
+        width: '1'
       - dir: output
         name: nmi_vector
         reset_value: '''bz'
         width: '32'
+      - dir: output
+        name: nmi_intr
+        reset_value: '''bz'
+        width: '1'
       - dir: output
         name: iccm_lock
         reset_value: '''bz'
@@ -84,6 +96,12 @@ uvmf:
         name: sha_notif_intr_pending
         type: bit
         unpacked_dimension: ''
+      - comment: ''
+        iscompare: 'True'
+        isrand: 'False'
+        name: timer_intr_pending
+        type: bit
+        unpacked_dimension: ''
       - comment: ''
         iscompare: 'True'
         isrand: 'False'
@@ -96,6 +114,12 @@ uvmf:
         name: uc_rst_asserted
         type: bit
         unpacked_dimension: ''
+      - comment: ''
+        iscompare: 'True'
+        isrand: 'False'
+        name: fw_update_rst_window
+        type: bit
+        unpacked_dimension: ''
       - comment: ''
         iscompare: 'True'
         isrand: 'False'
@@ -120,6 +144,12 @@ uvmf:
         name: nmi_vector
         type: bit [31:0]
         unpacked_dimension: ''
+      - comment: ''
+        iscompare: 'True'
+        isrand: 'False'
+        name: nmi_intr_pending
+        type: bit
+        unpacked_dimension: ''
       - comment: ''
         iscompare: 'True'
         isrand: 'False'
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/.project b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/.project
new file mode 100644
index 000000000..25262dcd1
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/.project
@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>mbox_sram_pkg</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.python.pydev.PyDevBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>net.sf.sveditor.core.SVProjectBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>net.sf.sveditor.core.SVNature</nature>
+		<nature>org.python.pydev.pythonNature</nature>
+	</natures>
+	<variableList>
+		<variable>
+			<name>UVMF_VIP_LIBRARY_HOME</name>
+			<value>$%7BPARENT-2-PROJECT_LOC%7D</value>
+		</variable>
+	</variableList>
+</projectDescription>
+
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/.svproject b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/.svproject
new file mode 100644
index 000000000..82ebbab03
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/.svproject
@@ -0,0 +1,16 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<svproject>
+  <defines/>
+  <includePaths/>
+  <buildPaths/>
+  <pluginPaths>
+    <pluginPath path="net.sf.sveditor.sv_builtin"/>
+  </pluginPaths>
+  <libraryPaths/>
+  <argFilePaths>
+    <argFilePath path="${project_loc}/mbox_sram_pkg_sve.F"/>
+  </argFilePaths>
+  <sourceCollections/>
+  <projectRefs/>
+  <templatePaths/>
+</svproject>
\ No newline at end of file
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/Makefile b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/Makefile
new file mode 100644
index 000000000..60c82949b
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/Makefile
@@ -0,0 +1,66 @@
+# mbox_sram interface packages source
+# pragma uvmf custom additional begin
+# pragma uvmf custom additional end
+
+mbox_sram_PKG         = \
+	+incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/mbox_sram_pkg \
+	-F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/mbox_sram_pkg/mbox_sram_filelist_hvl.f 
+
+mbox_sram_PKG_HDL         = \
+	+incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/mbox_sram_pkg \
+	-F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/mbox_sram_pkg/mbox_sram_filelist_hdl.f 
+
+mbox_sram_PKG_XRTL         = \
+	+incdir+$(UVMF_VIP_LIBRARY_HOME)/interface_packages/mbox_sram_pkg \
+	-F $(UVMF_VIP_LIBRARY_HOME)/interface_packages/mbox_sram_pkg/mbox_sram_filelist_xrtl.f 
+
+COMP_mbox_sram_PKG_TGT_0 = q_comp_mbox_sram_pkg
+COMP_mbox_sram_PKG_TGT_1 = v_comp_mbox_sram_pkg
+COMP_mbox_sram_PKG_TGT = $(COMP_mbox_sram_PKG_TGT_$(USE_VELOCE))
+
+comp_mbox_sram_pkg: $(COMP_mbox_sram_PKG_TGT) 
+
+q_comp_mbox_sram_pkg:
+	$(HDL_COMP_CMD) $(mbox_sram_PKG_HDL)
+	$(HVL_COMP_CMD) $(mbox_sram_PKG)
+	$(HDL_COMP_CMD) $(mbox_sram_PKG_XRTL) 
+
+v_comp_mbox_sram_pkg:
+	$(HVL_COMP_CMD) $(mbox_sram_PKG_HDL)
+	$(HVL_COMP_CMD) $(mbox_sram_PKG)
+	$(VELANALYZE_CMD) $(mbox_sram_PKG_HDL) 
+	$(VELANALYZE_HVL_CMD) $(mbox_sram_PKG) 
+	$(HDL_COMP_CMD) $(mbox_sram_PKG_XRTL)
+
+ifeq ($(MTI_VCO_MODE),64)
+  GCC_COMP_ARCH = -m64
+else
+  GCC_COMP_ARCH = -m32
+endif
+
+export mbox_sram_IF_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/interface_packages/mbox_sram_pkg/dpi
+
+C_FILE_COMPILE_LIST_mbox_sram_pkg	= \
+
+O_FILE_COMPILE_LIST_mbox_sram_pkg = $(notdir $(C_FILE_COMPILE_LIST_mbox_sram_pkg:.c=.o))
+
+GCC_COMP_ARGS_mbox_sram_pkg	+= -I$(mbox_sram_IF_DPI_SRC) \
+	-fPIC 
+
+GCC_COMP_ARGS_mbox_sram_pkg	+= $(mbox_sram_IF_GCC_COMP_ARGUMENTS)
+
+GCC_LINK_ARGS_mbox_sram_pkg	+= \
+	 \
+ 	-o .so
+
+comp_mbox_sram_pkg_c_files:
+	@echo "--------------------------------"
+	@echo "Compiling Interface C source"
+	@echo "--------------------------------"
+	gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_mbox_sram_pkg) $(C_FILE_COMPILE_LIST_mbox_sram_pkg)
+	@echo "--------------------------------"
+	@echo "Linking Interface C objects into a shared object"
+	@echo "--------------------------------"
+	gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_mbox_sram_pkg) $(O_FILE_COMPILE_LIST_mbox_sram_pkg)
+	@echo "--------------------------------"
+
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/compile.do b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/compile.do
new file mode 100644
index 000000000..e20bed409
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/compile.do
@@ -0,0 +1,14 @@
+# Tcl do file for compile of mbox_sram interface
+
+# pragma uvmf custom additional begin
+# pragma uvmf custom additional end
+
+
+vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/mbox_sram_pkg \
+  -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/mbox_sram_pkg/mbox_sram_filelist_hdl.f
+
+vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/mbox_sram_pkg \
+  -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/mbox_sram_pkg/mbox_sram_filelist_hvl.f
+
+vlog -sv -timescale 1ps/1ps -suppress 2223,2286 +incdir+$env(UVMF_VIP_LIBRARY_HOME)/interface_packages/mbox_sram_pkg \
+  -F $env(UVMF_VIP_LIBRARY_HOME)/interface_packages/mbox_sram_pkg/mbox_sram_filelist_xrtl.f
\ No newline at end of file
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram.compile b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram.compile
new file mode 100644
index 000000000..b0b806055
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram.compile
@@ -0,0 +1,3 @@
+needs:
+  - mbox_sram_hvl.compile
+  - mbox_sram_hdl.compile
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_bfm.vinfo b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_bfm.vinfo
new file mode 100644
index 000000000..a738c1152
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_bfm.vinfo
@@ -0,0 +1,6 @@
+@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo
+@use mbox_sram_pkg_hdl.vinfo
++incdir+@vinfodir
+src/mbox_sram_if.sv
+src/mbox_sram_driver_bfm.sv
+src/mbox_sram_monitor_bfm.sv
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_common.compile b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_common.compile
new file mode 100644
index 000000000..f701a7be2
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_common.compile
@@ -0,0 +1,7 @@
+needs:
+  - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile
+incdir:
+  - .
+  - ${uvm_path}/src
+src:
+  - mbox_sram_pkg_hdl.sv
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_filelist_hdl.f b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_filelist_hdl.f
new file mode 100644
index 000000000..91803d05e
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_filelist_hdl.f
@@ -0,0 +1 @@
+$UVMF_VIP_LIBRARY_HOME/interface_packages/mbox_sram_pkg/mbox_sram_pkg_hdl.sv
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_filelist_hvl.f b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_filelist_hvl.f
new file mode 100644
index 000000000..f4fb8adc1
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_filelist_hvl.f
@@ -0,0 +1 @@
+$UVMF_VIP_LIBRARY_HOME/interface_packages/mbox_sram_pkg/mbox_sram_pkg.sv
\ No newline at end of file
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_filelist_xrtl.f b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_filelist_xrtl.f
new file mode 100644
index 000000000..85b63fa2f
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_filelist_xrtl.f
@@ -0,0 +1,3 @@
+$UVMF_VIP_LIBRARY_HOME/interface_packages/mbox_sram_pkg/src/mbox_sram_if.sv
+$UVMF_VIP_LIBRARY_HOME/interface_packages/mbox_sram_pkg/src/mbox_sram_monitor_bfm.sv
+$UVMF_VIP_LIBRARY_HOME/interface_packages/mbox_sram_pkg/src/mbox_sram_driver_bfm.sv
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_hdl.compile b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_hdl.compile
new file mode 100644
index 000000000..032a5e03c
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_hdl.compile
@@ -0,0 +1,9 @@
+needs:
+  - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile
+  - ./mbox_sram_common.compile
+incdir:
+  - .
+src:
+  - src/mbox_sram_if.sv
+  - src/mbox_sram_monitor_bfm.sv
+  - src/mbox_sram_driver_bfm.sv
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_hvl.compile b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_hvl.compile
new file mode 100644
index 000000000..da9f7fe81
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_hvl.compile
@@ -0,0 +1,7 @@
+needs:
+  - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile
+  - ./mbox_sram_common.compile
+incdir:
+  - .
+src:
+  - mbox_sram_pkg.sv
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_pkg.sv b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_pkg.sv
new file mode 100644
index 000000000..3d9b7ecf4
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_pkg.sv
@@ -0,0 +1,93 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//     
+// PACKAGE: This file defines all of the files contained in the
+//    interface package that will run on the host simulator.
+//
+// CONTAINS:
+//    - <mbox_sram_typedefs_hdl>
+//    - <mbox_sram_typedefs.svh>
+//    - <mbox_sram_transaction.svh>
+
+//    - <mbox_sram_configuration.svh>
+//    - <mbox_sram_driver.svh>
+//    - <mbox_sram_monitor.svh>
+
+//    - <mbox_sram_transaction_coverage.svh>
+//    - <mbox_sram_sequence_base.svh>
+//    - <mbox_sram_random_sequence.svh>
+
+//    - <mbox_sram_responder_sequence.svh>
+//    - <mbox_sram2reg_adapter.svh>
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+package mbox_sram_pkg;
+  
+   import uvm_pkg::*;
+   import uvmf_base_pkg_hdl::*;
+   import uvmf_base_pkg::*;
+   import mbox_sram_pkg_hdl::*;
+
+   `include "uvm_macros.svh"
+
+   // pragma uvmf custom package_imports_additional begin 
+   import soc_ifc_pkg::*;
+   // pragma uvmf custom package_imports_additional end
+   `include "src/mbox_sram_macros.svh"
+
+   export mbox_sram_pkg_hdl::*;
+   
+ 
+
+   // Parameters defined as HVL parameters
+
+   `include "src/mbox_sram_typedefs.svh"
+   `include "src/mbox_sram_transaction.svh"
+
+   `include "src/mbox_sram_configuration.svh"
+   `include "src/mbox_sram_driver.svh"
+   `include "src/mbox_sram_monitor.svh"
+
+   `include "src/mbox_sram_transaction_coverage.svh"
+   `include "src/mbox_sram_sequence_base.svh"
+   `include "src/mbox_sram_random_sequence.svh"
+
+   `include "src/mbox_sram_responder_sequence.svh"
+   `include "src/mbox_sram2reg_adapter.svh"
+
+   `include "src/mbox_sram_agent.svh"
+
+   // pragma uvmf custom package_item_additional begin
+   // UVMF_CHANGE_ME : When adding new interface sequences to the src directory
+   //    be sure to add the sequence file here so that it will be
+   //    compiled as part of the interface package.  Be sure to place
+   //    the new sequence after any base sequences of the new sequence.
+   typedef mbox_sram_responder_sequence mbox_sram_agent_responder_seq_t;
+   // pragma uvmf custom package_item_additional end
+
+endpackage
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_pkg.vinfo b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_pkg.vinfo
new file mode 100644
index 000000000..2d5289a09
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_pkg.vinfo
@@ -0,0 +1,4 @@
+@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo
+@use mbox_sram_pkg_hdl.vinfo
++incdir+@vinfodir
+mbox_sram_pkg.sv
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_pkg_hdl.sv b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_pkg_hdl.sv
new file mode 100644
index 000000000..82e9bb46a
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_pkg_hdl.sv
@@ -0,0 +1,52 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//     
+// PACKAGE: This file defines all of the files contained in the
+//    interface package that needs to be compiled and synthesized
+//    for running on Veloce.
+//
+// CONTAINS:
+//    - <mbox_sram_typedefs_hdl>
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+package mbox_sram_pkg_hdl;
+  
+  import uvmf_base_pkg_hdl::*;
+
+  // pragma uvmf custom package_imports_additional begin 
+  // pragma uvmf custom package_imports_additional end
+
+  // Parameters defined as HDL parameters
+
+  `include "src/mbox_sram_typedefs_hdl.svh"
+  `include "src/mbox_sram_macros.svh"
+
+  // pragma uvmf custom package_item_additional begin
+  // pragma uvmf custom package_item_additional end
+
+endpackage
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_pkg_hdl.vinfo b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_pkg_hdl.vinfo
new file mode 100644
index 000000000..b490cd934
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_pkg_hdl.vinfo
@@ -0,0 +1,2 @@
+@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo
+mbox_sram_pkg_hdl.sv
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_pkg_sve.F b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_pkg_sve.F
new file mode 100644
index 000000000..690a04c08
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/mbox_sram_pkg_sve.F
@@ -0,0 +1,10 @@
+// UVM
++incdir+${UVM_HOME}/src
+${UVM_HOME}/src/uvm_pkg.sv
+
+// Common UVMF files
+-f ${UVMF_HOME}/common/common_sve.f
+
++incdir+.
+-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/mbox_sram_pkg/mbox_sram_filelist_hdl.f
+-f ${UVMF_VIP_LIBRARY_HOME}/interface_packages/mbox_sram_pkg/mbox_sram_filelist_hvl.f
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram2reg_adapter.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram2reg_adapter.svh
new file mode 100644
index 000000000..deba1e67c
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram2reg_adapter.svh
@@ -0,0 +1,112 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//     
+// DESCRIPTION: 
+// This file contains the UVM register adapter for the mbox_sram interface.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class mbox_sram2reg_adapter  extends uvm_reg_adapter;
+
+  `uvm_object_utils( mbox_sram2reg_adapter )
+  
+  // pragma uvmf custom class_item_additional begin
+  // pragma uvmf custom class_item_additional end
+
+  //--------------------------------------------------------------------
+  // new
+  //--------------------------------------------------------------------
+  function new (string name = "mbox_sram2reg_adapter" );
+    super.new(name);
+    // pragma uvmf custom new begin
+    // UVMF_CHANGE_ME : Configure the adapter regarding byte enables and provides response.
+
+    // Does the protocol the Agent is modeling support byte enables?
+    // 0 = NO
+    // 1 = YES
+    supports_byte_enable = 0;
+
+    // Does the Agent's Driver provide separate response sequence items?
+    // i.e. Does the driver call seq_item_port.put() 
+    // and do the sequences call get_response()?
+    // 0 = NO
+    // 1 = YES
+    provides_responses = 0;
+    // pragma uvmf custom new end
+
+  endfunction: new
+
+  //--------------------------------------------------------------------
+  // reg2bus
+  //--------------------------------------------------------------------
+  virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw);
+
+    mbox_sram_transaction  trans_h = mbox_sram_transaction ::type_id::create("trans_h");
+    
+    // pragma uvmf custom reg2bus begin
+    // UVMF_CHANGE_ME : Fill in the reg2bus adapter mapping registe fields to protocol fields.
+
+    //Adapt the following for your sequence item type
+    // trans_h.op = (rw.kind == UVM_READ) ? WB_READ : WB_WRITE;
+    //Copy over address
+    // trans_h.addr = rw.addr;
+    //Copy over write data
+    // trans_h.data = rw.data;
+
+    // pragma uvmf custom reg2bus end
+    
+    // Return the adapted transaction
+    return trans_h;
+
+  endfunction: reg2bus
+
+  //--------------------------------------------------------------------
+  // bus2reg
+  //--------------------------------------------------------------------
+  virtual function void bus2reg(uvm_sequence_item bus_item,
+                                ref uvm_reg_bus_op rw);
+    mbox_sram_transaction  trans_h;
+    if (!$cast(trans_h, bus_item)) begin
+      `uvm_fatal("ADAPT","Provided bus_item is not of the correct type")
+      return;
+    end
+    // pragma uvmf custom bus2reg begin
+    // UVMF_CHANGE_ME : Fill in the bus2reg adapter mapping protocol fields to register fields.
+    //Adapt the following for your sequence item type
+    //Copy over instruction type 
+    // rw.kind = (trans_h.op == WB_WRITE) ? UVM_WRITE : UVM_READ;
+    //Copy over address
+    // rw.addr = trans_h.addr;
+    //Copy over read data
+    // rw.data = trans_h.data;
+    //Check for errors on the bus and return UVM_NOT_OK if there is an error
+    // rw.status = UVM_IS_OK;
+    // pragma uvmf custom bus2reg end
+
+  endfunction: bus2reg
+
+endclass : mbox_sram2reg_adapter
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_agent.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_agent.svh
new file mode 100644
index 000000000..ba0eb1e33
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_agent.svh
@@ -0,0 +1,71 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: Protocol specific agent class definition
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class mbox_sram_agent  extends uvmf_parameterized_agent #(
+                    .CONFIG_T(mbox_sram_configuration ),
+                    .DRIVER_T(mbox_sram_driver ),
+                    .MONITOR_T(mbox_sram_monitor ),
+                    .COVERAGE_T(mbox_sram_transaction_coverage ),
+                    .TRANS_T(mbox_sram_transaction )
+                    );
+
+  `uvm_component_utils( mbox_sram_agent )
+
+// pragma uvmf custom class_item_additional begin
+  extern task handle_reset(string kind = "HARD");
+// pragma uvmf custom class_item_additional end
+
+// ****************************************************************************
+// FUNCTION : new()
+// This function is the standard SystemVerilog constructor.
+//
+  function new( string name = "", uvm_component parent = null );
+    super.new( name, parent );
+  endfunction
+
+// ****************************************************************************
+  // FUNCTION: build_phase
+  virtual function void build_phase(uvm_phase phase);
+// pragma uvmf custom build_phase_pre_super begin
+// pragma uvmf custom build_phase_pre_super end
+    super.build_phase(phase);
+    if (configuration.active_passive == ACTIVE) begin
+      // Place sequencer handle into configuration object
+      // so that it may be retrieved from configuration 
+      // rather than using uvm_config_db
+      configuration.sequencer = this.sequencer;
+    end
+  endfunction
+  
+endclass
+
+// pragma uvmf custom external begin
+task mbox_sram_agent::handle_reset(string kind = "HARD");
+    configuration.handle_reset(kind);
+endtask
+// pragma uvmf custom external end
+
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_configuration.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_configuration.svh
new file mode 100644
index 000000000..4b3c2e2c3
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_configuration.svh
@@ -0,0 +1,203 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//                                          
+// DESCRIPTION: This class contains all variables and functions used
+//      to configure the mbox_sram agent and its bfm's.  It gets the
+//      bfm's from the uvm_config_db for use by the agent.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class mbox_sram_configuration  extends uvmf_parameterized_agent_configuration_base #(
+      .DRIVER_BFM_BIND_T(virtual mbox_sram_driver_bfm ),
+      .MONITOR_BFM_BIND_T( virtual mbox_sram_monitor_bfm ));
+
+  `uvm_object_utils( mbox_sram_configuration )
+
+  // Controls injection of ECC errors for write transactions. Bit[0]: Single Bit Error. Bit[1]: Double Bit Error
+  bit [1:0] inject_ecc_error = 2'b00;
+  // When set, causes the mbox_sram_responder_sequence to clear the variable 'inject_ecc_error' after a single ECC error is injected
+  bit auto_clear_ecc_error_injection = 1'b1;
+
+  // Sequencer handle populated by agent
+  uvm_sequencer #(mbox_sram_transaction  ) sequencer;
+
+  //Constraints for the configuration variables:
+
+  // pragma uvmf custom class_item_additional begin
+  extern task handle_reset(string kind = "HARD");
+  // pragma uvmf custom class_item_additional end
+  
+  covergroup mbox_sram_configuration_cg;
+    // pragma uvmf custom covergroup begin
+    option.auto_bin_max=1024;
+    coverpoint inject_ecc_error;
+    coverpoint auto_clear_ecc_error_injection;
+    // pragma uvmf custom covergroup end
+  endgroup
+
+  //*******************************************************************
+  //*******************************************************************
+  // Structure used to pass configuration variables to monitor and driver BFM's.
+  // Use to_struct function to pack variables into structure.
+  // Use from_struct function to unpack variables from structure.
+  // This structure is defined in mbox_sram_macros.svh
+  `mbox_sram_CONFIGURATION_STRUCT
+  mbox_sram_configuration_s mbox_sram_configuration_struct;
+  //*******************************************************************
+  // FUNCTION: to_struct()
+  // This function packs variables into a mbox_sram_configuration_s
+  // structure.  The function returns the handle to the mbox_sram_configuration_struct.
+  // This function is defined in mbox_sram_macros.svh
+  `mbox_sram_CONFIGURATION_TO_STRUCT_FUNCTION
+  //*******************************************************************
+  // FUNCTION: from_struct()
+  // This function unpacks the struct provided as an argument into 
+  // variables of this class.
+  // This function is defined in mbox_sram_macros.svh
+  `mbox_sram_CONFIGURATION_FROM_STRUCT_FUNCTION
+
+  // ****************************************************************************
+  // FUNCTION : new()
+  // This function is the standard SystemVerilog constructor.
+  //
+  function new( string name = "" );
+    super.new( name );
+    // Construct the covergroup for this configuration class 
+    mbox_sram_configuration_cg = new;
+  endfunction
+
+  // ****************************************************************************
+  // FUNCTION: post_randomize()
+  // This function is automatically called after the randomize() function 
+  // is executed.
+  //
+  function void post_randomize();
+    super.post_randomize();
+    mbox_sram_configuration_cg.sample();
+  endfunction
+
+  // ****************************************************************************
+  // FUNCTION: initialize
+  //                   This function causes the configuration to retrieve
+  //                   its virtual interface handle from the uvm_config_db.
+  //                   This function also makes itself available to its
+  //                   agent through the uvm_config_db.
+  //
+  //                ARGUMENTS:
+  //                   uvmf_active_passive_t activity:
+  //                        This argument identifies the simulation level
+  //                        as either BLOCK, CHIP, SIMULATION, etc.
+  //
+  //                   AGENT_PATH:
+  //                        This argument identifies the path to this
+  //                        configurations agent.  This configuration
+  //                        makes itself available to the agent specified
+  //                        by agent_path by placing itself into the
+  //                        uvm_config_db.
+  //
+  //                   INTERFACE_NAME:
+  //                        This argument identifies the string name of
+  //                        this configurations BFM's.  This string
+  //                        name is used to retrieve the driver and 
+  //                        monitor BFM from the uvm_config_db.
+  //
+  virtual function void initialize(uvmf_active_passive_t activity,
+                                            string agent_path,
+                                            string interface_name);
+
+    super.initialize( activity, agent_path, interface_name);
+    // The covergroup is given the same name as the interface
+    mbox_sram_configuration_cg.set_inst_name(interface_name);
+
+    // This configuration places itself into the uvm_config_db for the agent, identified by the agent_path variable, to retrieve.  
+    uvm_config_db #( mbox_sram_configuration  
+                    )::set( null ,agent_path,UVMF_AGENT_CONFIG, this );
+
+    // This configuration also places itself in the config db using the same identifier used by the interface.  This allows users to access
+    // configuration variables and the interface through the bfm api class rather than directly accessing the BFM.  This is useful for 
+    // accessingthe BFM when using Veloce
+    uvm_config_db #( mbox_sram_configuration  
+                    )::set( null ,UVMF_CONFIGURATIONS, interface_name, this );
+
+    mbox_sram_configuration_cg.set_inst_name($sformatf("mbox_sram_configuration_cg_%s",get_full_name()));
+
+// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent.
+// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG
+// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings.
+// All of the messages from this feature have a UVM messaging id value of "CFG"
+// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings.
+    `uvm_info("CFG", 
+              $psprintf("The agent at '%s' is using interface named %s has the following parameters: ", agent_path, interface_name, ),
+              UVM_DEBUG)
+
+    // pragma uvmf custom initialize begin
+    // This controls whether or not the agent returns a transaction handle in the driver when calling 
+    // item_done() back into the sequencer or not. If set to 1, a transaction is sent back which means
+    // the sequence on the other end must use the get_response() part of the driver/sequence API. If 
+    // this doesn't occur, there will eventually be response_queue overflow errors during the test.
+    return_transaction_response = 1'b1;
+
+    // pragma uvmf custom initialize end
+
+  endfunction
+
+  // ****************************************************************************
+  // TASK: wait_for_reset
+  // *[Required]*  Blocks until reset is released.  The wait_for_reset operation is performed
+  // by a task in the monitor bfm.
+  virtual task wait_for_reset();
+    monitor_bfm.wait_for_reset();
+  endtask
+
+  // ****************************************************************************
+  // TASK: wait_for_num_clocks
+  // *[Required]* Blocks until specified number of clocks have elapsed. The wait_for_num_clocks
+  // operation is performed by a task in the monitor bfm.
+  virtual task wait_for_num_clocks(int clocks);
+    monitor_bfm.wait_for_num_clocks(clocks);
+  endtask
+
+  // ****************************************************************************
+  // FUNCTION : convert2string()
+  // This function is used to convert variables in this class into a string for log messaging.
+  // 
+  virtual function string convert2string ();
+    // pragma uvmf custom convert2string begin
+    return $sformatf("inject_ecc_error:0x%x  auto_clear_ecc_error_injection:0x%x  ",inject_ecc_error,auto_clear_ecc_error_injection);
+    // pragma uvmf custom convert2string end
+  endfunction
+
+  // ****************************************************************************
+  // FUNCTION: get_sequencer
+  function uvm_sequencer #(mbox_sram_transaction) get_sequencer();
+    return sequencer;
+  endfunction
+
+endclass
+
+// pragma uvmf custom external begin
+task mbox_sram_configuration::handle_reset(string kind = "HARD");
+    inject_ecc_error = 0;
+endtask
+// pragma uvmf custom external end
+
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_driver.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_driver.svh
new file mode 100644
index 000000000..c083be2b0
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_driver.svh
@@ -0,0 +1,105 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//     
+// DESCRIPTION: This class passes transactions between the sequencer
+//        and the BFM driver interface.  It accesses the driver BFM 
+//        through the bfm handle. This driver
+//        passes transactions to the driver BFM through the access
+//        task.  
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class mbox_sram_driver   extends uvmf_driver_base #(
+                   .CONFIG_T(mbox_sram_configuration   ),
+                   .BFM_BIND_T(virtual mbox_sram_driver_bfm   ),
+                   .REQ(mbox_sram_transaction   ),
+                   .RSP(mbox_sram_transaction   ));
+
+  `uvm_component_utils( mbox_sram_driver )
+//*******************************************************************
+// Macros that define structs located in mbox_sram_macros.svh
+//*******************************************************************
+// Initiator macro used by mbox_sram_driver and mbox_sram_driver_bfm
+// to communicate initiator driven data to mbox_sram_driver_bfm.           
+`mbox_sram_INITIATOR_STRUCT
+  mbox_sram_initiator_s mbox_sram_initiator_struct;
+//*******************************************************************
+// Responder macro used by mbox_sram_driver and mbox_sram_driver_bfm
+// to communicate Responder driven data to mbox_sram_driver_bfm.
+`mbox_sram_RESPONDER_STRUCT
+  mbox_sram_responder_s mbox_sram_responder_struct;
+
+// pragma uvmf custom class_item_additional begin
+// pragma uvmf custom class_item_additional end
+
+// ****************************************************************************
+// This function is the standard SystemVerilog constructor.
+//
+  function new( string name = "", uvm_component parent=null );
+    super.new( name, parent );
+  endfunction
+
+// ****************************************************************************
+// This function sends configuration object variables to the driver BFM 
+// using the configuration struct.
+//
+  virtual function void configure(input CONFIG_T cfg);
+      bfm.configure( cfg.to_struct() );
+  endfunction
+
+// ****************************************************************************
+// This function places a handle to this class in the proxy variable in the
+// driver BFM.  This allows the driver BFM to call tasks and function within this class.
+//
+  virtual function void set_bfm_proxy_handle();
+    bfm.proxy = this;  endfunction
+
+// **************************************************************************** 
+// This task is called by the run_phase in uvmf_driver_base.              
+  virtual task access( inout REQ txn );
+// pragma uvmf custom access begin
+    if (configuration.initiator_responder==RESPONDER) begin
+      // Complete current transfer and wait for next transfer
+      bfm.respond_and_wait_for_next_transfer( 
+          mbox_sram_initiator_struct, 
+          txn.to_responder_struct() 
+          );
+      // Unpack information about initiated transfer received by this responder
+      txn.from_initiator_struct(mbox_sram_initiator_struct);
+    end else begin    
+      // Initiate a transfer and get response
+      bfm.initiate_and_get_response( 
+          txn.to_initiator_struct(), 
+          mbox_sram_responder_struct 
+          );
+      // Unpack transfer response information received by this initiator
+      txn.from_responder_struct(mbox_sram_responder_struct);
+    end
+// pragma uvmf custom access end
+  endtask
+
+endclass
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_driver_bfm.sv b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_driver_bfm.sv
new file mode 100644
index 000000000..6c9359089
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_driver_bfm.sv
@@ -0,0 +1,334 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// pragma uvmf custom header begin
+import soc_ifc_pkg::*;
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//     
+// DESCRIPTION: 
+//    This interface performs the mbox_sram signal driving.  It is
+//     accessed by the uvm mbox_sram driver through a virtual interface
+//     handle in the mbox_sram configuration.  It drives the singals passed
+//     in through the port connection named bus of type mbox_sram_if.
+//
+//     Input signals from the mbox_sram_if are assigned to an internal input
+//     signal with a _i suffix.  The _i signal should be used for sampling.
+//
+//     The input signal connections are as follows:
+//       bus.signal -> signal_i 
+//
+//     This bfm drives signals with a _o suffix.  These signals
+//     are driven onto signals within mbox_sram_if based on INITIATOR/RESPONDER and/or
+//     ARBITRATION/GRANT status.  
+//
+//     The output signal connections are as follows:
+//        signal_o -> bus.signal
+//
+//                                                                                           
+//      Interface functions and tasks used by UVM components:
+//
+//             configure:
+//                   This function gets configuration attributes from the
+//                   UVM driver to set any required BFM configuration
+//                   variables such as 'initiator_responder'.                                       
+//                                                                                           
+//             initiate_and_get_response:
+//                   This task is used to perform signaling activity for initiating
+//                   a protocol transfer.  The task initiates the transfer, using
+//                   input data from the initiator struct.  Then the task captures
+//                   response data, placing the data into the response struct.
+//                   The response struct is returned to the driver class.
+//
+//             respond_and_wait_for_next_transfer:
+//                   This task is used to complete a current transfer as a responder
+//                   and then wait for the initiator to start the next transfer.
+//                   The task uses data in the responder struct to drive protocol
+//                   signals to complete the transfer.  The task then waits for 
+//                   the next transfer.  Once the next transfer begins, data from
+//                   the initiator is placed into the initiator struct and sent
+//                   to the responder sequence for processing to determine 
+//                   what data to respond with.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+import uvmf_base_pkg_hdl::*;
+import mbox_sram_pkg_hdl::*;
+`include "src/mbox_sram_macros.svh"
+
+interface mbox_sram_driver_bfm 
+  (mbox_sram_if bus);
+  // The following pragma and additional ones in-lined further below are for running this BFM on Veloce
+  // pragma attribute mbox_sram_driver_bfm partition_interface_xif
+
+`ifndef XRTL
+// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent.
+// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG
+// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings.
+// All of the messages from this feature have a UVM messaging id value of "CFG"
+// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings.
+import uvm_pkg::*;
+`include "uvm_macros.svh"
+initial begin : bfm_vs_agent_parameter_debug
+  `uvm_info("CFG", 
+      $psprintf("The BFM at '%m' has the following parameters: ", ),
+      UVM_DEBUG)
+end
+`endif
+
+  // Config value to determine if this is an initiator or a responder 
+  uvmf_initiator_responder_t initiator_responder;
+  // Custom configuration variables.  
+  // These are set using the configure function which is called during the UVM connect_phase
+  bit [1:0] inject_ecc_error ;
+  bit auto_clear_ecc_error_injection ;
+
+  tri clk_i;
+  tri dummy_i;
+
+  // Signal list (all signals are capable of being inputs and outputs for the sake
+  // of supporting both INITIATOR and RESPONDER mode operation. Expectation is that 
+  // directionality in the config file was from the point-of-view of the INITIATOR
+
+  // INITIATOR mode input signals
+  tri [$bits(mbox_sram_resp_t)-1:0] mbox_sram_resp_i;
+//  reg [$bits(mbox_sram_resp_t)-1:0] mbox_sram_resp_o = 'bz;
+  mbox_sram_resp_t mbox_sram_resp_o = 'bz;
+
+  // INITIATOR mode output signals
+//  tri [$bits(mbox_sram_req_t)-1:0] mbox_sram_req_i;
+  mbox_sram_req_t mbox_sram_req_i;
+  reg [$bits(mbox_sram_req_t)-1:0] mbox_sram_req_o = 'bz;
+
+  // Bi-directional signals
+  
+
+  assign clk_i = bus.clk;
+  assign dummy_i = bus.dummy;
+
+  // These are signals marked as 'input' by the config file, but the signals will be
+  // driven by this BFM if put into RESPONDER mode (flipping all signal directions around)
+  assign mbox_sram_resp_i = bus.mbox_sram_resp;
+  assign bus.mbox_sram_resp = (initiator_responder == RESPONDER) ? mbox_sram_resp_o : 'bz;
+
+
+  // These are signals marked as 'output' by the config file, but the outputs will
+  // not be driven by this BFM unless placed in INITIATOR mode.
+  assign bus.mbox_sram_req = (initiator_responder == INITIATOR) ? mbox_sram_req_o : 'bz;
+  assign mbox_sram_req_i = bus.mbox_sram_req;
+
+  // Proxy handle to UVM driver
+  mbox_sram_pkg::mbox_sram_driver   proxy;
+  // pragma tbx oneway proxy.my_function_name_in_uvm_driver                 
+
+  // ****************************************************************************
+  // **************************************************************************** 
+  // Macros that define structs located in mbox_sram_macros.svh
+  // ****************************************************************************
+  // Struct for passing configuration data from mbox_sram_driver to this BFM
+  // ****************************************************************************
+  `mbox_sram_CONFIGURATION_STRUCT
+  // ****************************************************************************
+  // Structs for INITIATOR and RESPONDER data flow
+  //*******************************************************************
+  // Initiator macro used by mbox_sram_driver and mbox_sram_driver_bfm
+  // to communicate initiator driven data to mbox_sram_driver_bfm.           
+  `mbox_sram_INITIATOR_STRUCT
+    mbox_sram_initiator_s initiator_struct;
+  // Responder macro used by mbox_sram_driver and mbox_sram_driver_bfm
+  // to communicate Responder driven data to mbox_sram_driver_bfm.
+  `mbox_sram_RESPONDER_STRUCT
+    mbox_sram_responder_s responder_struct;
+
+  // ****************************************************************************
+// pragma uvmf custom reset_condition_and_response begin
+  // Always block used to return signals to reset value upon assertion of reset
+  always @( negedge dummy_i )
+     begin
+       // RESPONDER mode output signals
+       mbox_sram_resp_o <= 'bz;
+       // INITIATOR mode output signals
+       mbox_sram_req_o <= 'bz;
+       // Bi-directional signals
+ 
+     end    
+// pragma uvmf custom reset_condition_and_response end
+
+  // pragma uvmf custom interface_item_additional begin
+  // pragma uvmf custom interface_item_additional end
+
+  //******************************************************************
+  // The configure() function is used to pass agent configuration
+  // variables to the driver BFM.  It is called by the driver within
+  // the agent at the beginning of the simulation.  It may be called 
+  // during the simulation if agent configuration variables are updated
+  // and the driver BFM needs to be aware of the new configuration 
+  // variables.
+  //
+
+  function void configure(mbox_sram_configuration_s mbox_sram_configuration_arg); // pragma tbx xtf  
+    initiator_responder = mbox_sram_configuration_arg.initiator_responder;
+    inject_ecc_error = mbox_sram_configuration_arg.inject_ecc_error;
+    auto_clear_ecc_error_injection = mbox_sram_configuration_arg.auto_clear_ecc_error_injection;
+  // pragma uvmf custom configure begin
+  // pragma uvmf custom configure end
+  endfunction                                                                             
+
+// pragma uvmf custom initiate_and_get_response begin
+// ****************************************************************************
+// UVMF_CHANGE_ME
+// This task is used by an initator.  The task first initiates a transfer then
+// waits for the responder to complete the transfer.
+    task initiate_and_get_response( 
+       // This argument passes transaction variables used by an initiator
+       // to perform the initial part of a protocol transfer.  The values
+       // come from a sequence item created in a sequence.
+       input mbox_sram_initiator_s mbox_sram_initiator_struct, 
+       // This argument is used to send data received from the responder
+       // back to the sequence item.  The sequence item is returned to the sequence.
+       output mbox_sram_responder_s mbox_sram_responder_struct 
+       );// pragma tbx xtf  
+       // 
+       // Members within the mbox_sram_initiator_struct:
+       //   bit is_read ;
+       //   bit [MBOX_ADDR_W-1:0] address ;
+       //   bit [MBOX_DATA_W-1:0] data ;
+       //   bit [MBOX_ECC_DATA_W-1:0] data_ecc ;
+       //   bit ecc_single_bit_error ;
+       //   bit ecc_double_bit_error ;
+       // Members within the mbox_sram_responder_struct:
+       //   bit is_read ;
+       //   bit [MBOX_ADDR_W-1:0] address ;
+       //   bit [MBOX_DATA_W-1:0] data ;
+       //   bit [MBOX_ECC_DATA_W-1:0] data_ecc ;
+       //   bit ecc_single_bit_error ;
+       //   bit ecc_double_bit_error ;
+       initiator_struct = mbox_sram_initiator_struct;
+       //
+       // Reference code;
+       //    How to wait for signal value
+       //      while (control_signal == 1'b1) @(posedge clk_i);
+       //    
+       //    How to assign a responder struct member, named xyz, from a signal.   
+       //    All available initiator input and inout signals listed.
+       //    Initiator input signals
+       //      mbox_sram_responder_struct.xyz = mbox_sram_resp_i;  //    [$bits(mbox_sram_resp_t)-1:0] 
+       //    Initiator inout signals
+       //    How to assign a signal from an initiator struct member named xyz.   
+       //    All available initiator output and inout signals listed.
+       //    Notice the _o.  Those are storage variables that allow for procedural assignment.
+       //    Initiator output signals
+       //      mbox_sram_req_o <= mbox_sram_initiator_struct.xyz;  //    [$bits(mbox_sram_req_t)-1:0] 
+       //    Initiator inout signals
+    // Initiate a transfer using the data received.
+    @(posedge clk_i);
+    @(posedge clk_i);
+    // Wait for the responder to complete the transfer then place the responder data into 
+    // mbox_sram_responder_struct.
+    @(posedge clk_i);
+    @(posedge clk_i);
+    `uvm_fatal("MBOX_SRAM_DRIVER_BFM", "Unimplemented initiate_and_get_response")
+    responder_struct = mbox_sram_responder_struct;
+  endtask        
+// pragma uvmf custom initiate_and_get_response end
+
+// pragma uvmf custom respond_and_wait_for_next_transfer begin
+// ****************************************************************************
+// The first_transfer variable is used to prevent completing a transfer in the 
+// first call to this task.  For the first call to this task, there is not
+// current transfer to complete.
+bit first_transfer=1;
+
+// UVMF_CHANGE_ME
+// This task is used by a responder.  The task first completes the current 
+// transfer in progress then waits for the initiator to start the next transfer.
+  task respond_and_wait_for_next_transfer( 
+       // This argument is used to send data received from the initiator
+       // back to the sequence item.  The sequence determines how to respond.
+       output mbox_sram_initiator_s mbox_sram_initiator_struct, 
+       // This argument passes transaction variables used by a responder
+       // to complete a protocol transfer.  The values come from a sequence item.       
+       input mbox_sram_responder_s mbox_sram_responder_struct 
+       );// pragma tbx xtf   
+  // Variables within the mbox_sram_initiator_struct:
+  //   bit is_read ;
+  //   bit [MBOX_ADDR_W-1:0] address ;
+  //   bit [MBOX_DATA_W-1:0] data ;
+  //   bit [MBOX_ECC_DATA_W-1:0] data_ecc ;
+  //   bit ecc_single_bit_error ;
+  //   bit ecc_double_bit_error ;
+  // Variables within the mbox_sram_responder_struct:
+  //   bit is_read ;
+  //   bit [MBOX_ADDR_W-1:0] address ;
+  //   bit [MBOX_DATA_W-1:0] data ;
+  //   bit [MBOX_ECC_DATA_W-1:0] data_ecc ;
+  //   bit ecc_single_bit_error ;
+  //   bit ecc_double_bit_error ;
+       // Reference code;
+       //    How to wait for signal value
+       //      while (control_signal == 1'b1) @(posedge clk_i);
+       //    
+       //    How to assign a responder struct member, named xyz, from a signal.   
+       //    All available responder input and inout signals listed.
+       //    Responder input signals
+       //      mbox_sram_responder_struct.xyz = mbox_sram_req_i;  //    [$bits(mbox_sram_req_t)-1:0] 
+       //    Responder inout signals
+       //    How to assign a signal, named xyz, from an initiator struct member.   
+       //    All available responder output and inout signals listed.
+       //    Notice the _o.  Those are storage variables that allow for procedural assignment.
+       //    Responder output signals
+       //      mbox_sram_resp_o <= mbox_sram_initiator_struct.xyz;  //    [$bits(mbox_sram_resp_t)-1:0] 
+       //    Responder inout signals
+    
+  responder_struct <= mbox_sram_responder_struct;
+  if (!first_transfer) begin
+    // Perform transfer response here.   
+    // Reply using data recieved in the mbox_sram_responder_struct.
+    if (mbox_sram_responder_struct.is_read) begin
+        mbox_sram_resp_o.rdata.data <= mbox_sram_responder_struct.data;
+        mbox_sram_resp_o.rdata.ecc  <= mbox_sram_responder_struct.data_ecc;
+    end
+    @(posedge clk_i);
+  end
+  while (mbox_sram_req_i.cs !== 1'b1) @(posedge clk_i);
+  // Wait for next transfer then gather info from intiator about the transfer.
+  // Place the data into the mbox_sram_initiator_struct.
+  mbox_sram_initiator_struct.is_read              = ~mbox_sram_req_i.we;
+  mbox_sram_initiator_struct.address              =  mbox_sram_req_i.addr;
+  mbox_sram_initiator_struct.data                 =  mbox_sram_req_i.wdata.data;
+  mbox_sram_initiator_struct.data_ecc             =  mbox_sram_req_i.wdata.ecc;
+  mbox_sram_initiator_struct.ecc_single_bit_error = mbox_sram_req_i.we && proxy.configuration.inject_ecc_error[0];
+  mbox_sram_initiator_struct.ecc_double_bit_error = mbox_sram_req_i.we && proxy.configuration.inject_ecc_error[1];
+  if (mbox_sram_initiator_struct.ecc_single_bit_error || mbox_sram_initiator_struct.ecc_double_bit_error) `uvm_info("MBOX_SRAM_DRIVER_BFM", "Injecting ECC bit flip", UVM_DEBUG)
+  else if (mbox_sram_req_i.we)                                                                            `uvm_info("MBOX_SRAM_DRIVER_BFM", "Receiving SRAM write without ECC bit flip", UVM_DEBUG)
+  if (proxy.configuration.auto_clear_ecc_error_injection && |proxy.configuration.inject_ecc_error) begin
+      proxy.configuration.inject_ecc_error = 2'b00;
+      `uvm_info("MBOX_SRAM_DRIVER_BFM", "Resetting inject_ecc_error value to 0", UVM_DEBUG)
+  end
+  first_transfer = 0;
+  initiator_struct = mbox_sram_initiator_struct;
+  endtask
+// pragma uvmf custom respond_and_wait_for_next_transfer end
+
+ 
+endinterface
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_if.sv b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_if.sv
new file mode 100644
index 000000000..d84655f20
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_if.sv
@@ -0,0 +1,83 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//     
+// DESCRIPTION: This interface contains the mbox_sram interface signals.
+//      It is instantiated once per mbox_sram bus.  Bus Functional Models, 
+//      BFM's named mbox_sram_driver_bfm, are used to drive signals on the bus.
+//      BFM's named mbox_sram_monitor_bfm are used to monitor signals on the 
+//      bus. This interface signal bundle is passed in the port list of
+//      the BFM in order to give the BFM access to the signals in this
+//      interface.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// This template can be used to connect a DUT to these signals
+//
+// .dut_signal_port(mbox_sram_bus.mbox_sram_req), // Agent output 
+// .dut_signal_port(mbox_sram_bus.mbox_sram_resp), // Agent input 
+
+import uvmf_base_pkg_hdl::*;
+import mbox_sram_pkg_hdl::*;
+
+interface  mbox_sram_if 
+
+  (
+  input tri clk, 
+  input tri dummy,
+  inout tri [$bits(mbox_sram_req_t)-1:0] mbox_sram_req,
+  inout tri [$bits(mbox_sram_resp_t)-1:0] mbox_sram_resp
+  );
+
+modport monitor_port 
+  (
+  input clk,
+  input dummy,
+  input mbox_sram_req,
+  input mbox_sram_resp
+  );
+
+modport initiator_port 
+  (
+  input clk,
+  input dummy,
+  output mbox_sram_req,
+  input mbox_sram_resp
+  );
+
+modport responder_port 
+  (
+  input clk,
+  input dummy,  
+  input mbox_sram_req,
+  output mbox_sram_resp
+  );
+  
+
+// pragma uvmf custom interface_item_additional begin
+// pragma uvmf custom interface_item_additional end
+
+endinterface
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_infact_coverage_strategy.csv b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_infact_coverage_strategy.csv
new file mode 100644
index 000000000..1c218e146
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_infact_coverage_strategy.csv
@@ -0,0 +1,6 @@
+Global
+auto_bin_max, 64
+
+Name,Type,Include
+rand_fields,coverpoint,=rand *.**
+
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_macros.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_macros.svh
new file mode 100644
index 000000000..19d629026
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_macros.svh
@@ -0,0 +1,186 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//     
+// DESCRIPTION: This file contains macros used with the mbox_sram package.
+//   These macros include packed struct definitions.  These structs are
+//   used to pass data between classes, hvl, and BFM's, hdl.  Use of 
+//   structs are more efficient and simpler to modify.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+// ****************************************************************************
+// When changing the contents of this struct, be sure to update the to_struct
+//      and from_struct methods defined in the macros below that are used in  
+//      the mbox_sram_configuration class.
+//
+  `define mbox_sram_CONFIGURATION_STRUCT \
+typedef struct packed  { \
+     bit [1:0] inject_ecc_error;\
+     bit auto_clear_ecc_error_injection;\
+     uvmf_active_passive_t active_passive; \
+     uvmf_initiator_responder_t initiator_responder; \
+     } mbox_sram_configuration_s;
+
+  `define mbox_sram_CONFIGURATION_TO_STRUCT_FUNCTION \
+  virtual function mbox_sram_configuration_s to_struct();\
+    mbox_sram_configuration_struct = \
+       {\
+       this.inject_ecc_error,\
+       this.auto_clear_ecc_error_injection,\
+       this.active_passive,\
+       this.initiator_responder\
+       };\
+    return ( mbox_sram_configuration_struct );\
+  endfunction
+
+  `define mbox_sram_CONFIGURATION_FROM_STRUCT_FUNCTION \
+  virtual function void from_struct(mbox_sram_configuration_s mbox_sram_configuration_struct);\
+      {\
+      this.inject_ecc_error,\
+      this.auto_clear_ecc_error_injection,\
+      this.active_passive,\
+      this.initiator_responder  \
+      } = mbox_sram_configuration_struct;\
+  endfunction
+
+// ****************************************************************************
+// When changing the contents of this struct, be sure to update the to_monitor_struct
+//      and from_monitor_struct methods of the mbox_sram_transaction class.
+//
+  `define mbox_sram_MONITOR_STRUCT typedef struct packed  { \
+  bit is_read ; \
+  bit [MBOX_ADDR_W-1:0] address ; \
+  bit [MBOX_DATA_W-1:0] data ; \
+  bit [MBOX_ECC_DATA_W-1:0] data_ecc ; \
+  bit ecc_single_bit_error ; \
+  bit ecc_double_bit_error ; \
+     } mbox_sram_monitor_s;
+
+  `define mbox_sram_TO_MONITOR_STRUCT_FUNCTION \
+  virtual function mbox_sram_monitor_s to_monitor_struct();\
+    mbox_sram_monitor_struct = \
+            { \
+            this.is_read , \
+            this.address , \
+            this.data , \
+            this.data_ecc , \
+            this.ecc_single_bit_error , \
+            this.ecc_double_bit_error  \
+            };\
+    return ( mbox_sram_monitor_struct);\
+  endfunction\
+
+  `define mbox_sram_FROM_MONITOR_STRUCT_FUNCTION \
+  virtual function void from_monitor_struct(mbox_sram_monitor_s mbox_sram_monitor_struct);\
+            {\
+            this.is_read , \
+            this.address , \
+            this.data , \
+            this.data_ecc , \
+            this.ecc_single_bit_error , \
+            this.ecc_double_bit_error  \
+            } = mbox_sram_monitor_struct;\
+  endfunction
+
+// ****************************************************************************
+// When changing the contents of this struct, be sure to update the to_initiator_struct
+//      and from_initiator_struct methods of the mbox_sram_transaction class.
+//      Also update the comments in the driver BFM.
+//
+  `define mbox_sram_INITIATOR_STRUCT typedef struct packed  { \
+  bit is_read ; \
+  bit [MBOX_ADDR_W-1:0] address ; \
+  bit [MBOX_DATA_W-1:0] data ; \
+  bit [MBOX_ECC_DATA_W-1:0] data_ecc ; \
+  bit ecc_single_bit_error ; \
+  bit ecc_double_bit_error ; \
+     } mbox_sram_initiator_s;
+
+  `define mbox_sram_TO_INITIATOR_STRUCT_FUNCTION \
+  virtual function mbox_sram_initiator_s to_initiator_struct();\
+    mbox_sram_initiator_struct = \
+           {\
+           this.is_read , \
+           this.address , \
+           this.data , \
+           this.data_ecc , \
+           this.ecc_single_bit_error , \
+           this.ecc_double_bit_error  \
+           };\
+    return ( mbox_sram_initiator_struct);\
+  endfunction
+
+  `define mbox_sram_FROM_INITIATOR_STRUCT_FUNCTION \
+  virtual function void from_initiator_struct(mbox_sram_initiator_s mbox_sram_initiator_struct);\
+           {\
+           this.is_read , \
+           this.address , \
+           this.data , \
+           this.data_ecc , \
+           this.ecc_single_bit_error , \
+           this.ecc_double_bit_error  \
+           } = mbox_sram_initiator_struct;\
+  endfunction
+
+// ****************************************************************************
+// When changing the contents of this struct, be sure to update the to_responder_struct
+//      and from_responder_struct methods of the mbox_sram_transaction class.
+//      Also update the comments in the driver BFM.
+//
+  `define mbox_sram_RESPONDER_STRUCT typedef struct packed  { \
+  bit is_read ; \
+  bit [MBOX_ADDR_W-1:0] address ; \
+  bit [MBOX_DATA_W-1:0] data ; \
+  bit [MBOX_ECC_DATA_W-1:0] data_ecc ; \
+  bit ecc_single_bit_error ; \
+  bit ecc_double_bit_error ; \
+     } mbox_sram_responder_s;
+
+  `define mbox_sram_TO_RESPONDER_STRUCT_FUNCTION \
+  virtual function mbox_sram_responder_s to_responder_struct();\
+    mbox_sram_responder_struct = \
+           {\
+           this.is_read , \
+           this.address , \
+           this.data , \
+           this.data_ecc , \
+           this.ecc_single_bit_error , \
+           this.ecc_double_bit_error  \
+           };\
+    return ( mbox_sram_responder_struct);\
+  endfunction
+
+  `define mbox_sram_FROM_RESPONDER_STRUCT_FUNCTION \
+  virtual function void from_responder_struct(mbox_sram_responder_s mbox_sram_responder_struct);\
+           {\
+           this.is_read , \
+           this.address , \
+           this.data , \
+           this.data_ecc , \
+           this.ecc_single_bit_error , \
+           this.ecc_double_bit_error  \
+           } = mbox_sram_responder_struct;\
+  endfunction
+// pragma uvmf custom additional begin
+// pragma uvmf custom additional end
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_monitor.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_monitor.svh
new file mode 100644
index 000000000..701ca2ef4
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_monitor.svh
@@ -0,0 +1,101 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//     
+// DESCRIPTION: This class receives mbox_sram transactions observed by the
+//     mbox_sram monitor BFM and broadcasts them through the analysis port
+//     on the agent. It accesses the monitor BFM through the monitor
+//     task. This UVM component captures transactions
+//     for viewing in the waveform viewer if the
+//     enable_transaction_viewing flag is set in the configuration.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class mbox_sram_monitor  extends uvmf_monitor_base #(
+                    .CONFIG_T(mbox_sram_configuration  ),
+                    .BFM_BIND_T(virtual mbox_sram_monitor_bfm  ),
+                    .TRANS_T(mbox_sram_transaction  ));
+
+  `uvm_component_utils( mbox_sram_monitor )
+
+// Structure used to pass data from monitor BFM to monitor class in agent.
+// Use to_monitor_struct function to pack transaction variables into structure.
+// Use from_monitor_struct function to unpack transaction variables from structure.
+`mbox_sram_MONITOR_STRUCT
+
+  // pragma uvmf custom class_item_additional begin
+  // pragma uvmf custom class_item_additional end
+  
+// ****************************************************************************
+// This function is the standard SystemVerilog constructor.
+//
+  function new( string name = "", uvm_component parent = null );
+    super.new( name, parent );
+  endfunction
+
+// ****************************************************************************
+// This function sends configuration object variables to the monitor BFM 
+// using the configuration struct.
+//
+   virtual function void configure(input CONFIG_T cfg);
+      bfm.configure( cfg.to_struct() );
+
+   endfunction
+
+// ****************************************************************************
+// This function places a handle to this class in the proxy variable in the
+// monitor BFM.  This allows the monitor BFM to call the notify_transaction
+// function within this class.
+//
+   virtual function void set_bfm_proxy_handle();
+      bfm.proxy = this;   endfunction
+
+// ***************************************************************************              
+  virtual task run_phase(uvm_phase phase);                                                   
+  // Start monitor BFM thread and don't call super.run() in order to                       
+  // override the default monitor proxy 'pull' behavior with the more                      
+  // emulation-friendly BFM 'push' approach using the notify_transaction                   
+  // function below                                                                        
+  bfm.start_monitoring();                                                   
+  endtask                                                                                    
+  
+// **************************************************************************  
+  
+// This function is called by the monitor BFM.  It receives data observed by the
+// monitor BFM.  Data is passed using the mbox_sram_monitor_struct.          
+ virtual function void notify_transaction(input mbox_sram_monitor_s mbox_sram_monitor_struct);
+ 
+ 
+    trans = new("trans");
+    trans.from_monitor_struct(mbox_sram_monitor_struct);
+    trans.start_time = time_stamp;                                                          
+    trans.end_time = $time;                                                                 
+    time_stamp = trans.end_time;
+ 
+    analyze(trans);                                                                         
+  endfunction  
+
+endclass
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_monitor_bfm.sv b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_monitor_bfm.sv
new file mode 100644
index 000000000..191287ca8
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_monitor_bfm.sv
@@ -0,0 +1,238 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// pragma uvmf custom header begin
+import soc_ifc_pkg::*;
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION: This interface performs the mbox_sram signal monitoring.
+//      It is accessed by the uvm mbox_sram monitor through a virtual
+//      interface handle in the mbox_sram configuration.  It monitors the
+//      signals passed in through the port connection named bus of
+//      type mbox_sram_if.
+//
+//     Input signals from the mbox_sram_if are assigned to an internal input
+//     signal with a _i suffix.  The _i signal should be used for sampling.
+//
+//     The input signal connections are as follows:
+//       bus.signal -> signal_i
+//
+//      Interface functions and tasks used by UVM components:
+//             monitor(inout TRANS_T txn);
+//                   This task receives the transaction, txn, from the
+//                   UVM monitor and then populates variables in txn
+//                   from values observed on bus activity.  This task
+//                   blocks until an operation on the mbox_sram bus is complete.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+import uvmf_base_pkg_hdl::*;
+import mbox_sram_pkg_hdl::*;
+`include "src/mbox_sram_macros.svh"
+
+
+interface mbox_sram_monitor_bfm
+  ( mbox_sram_if  bus );
+  // The pragma below and additional ones in-lined further down are for running this BFM on Veloce
+  // pragma attribute mbox_sram_monitor_bfm partition_interface_xif
+
+`ifndef XRTL
+// This code is to aid in debugging parameter mismatches between the BFM and its corresponding agent.
+// Enable this debug by setting UVM_VERBOSITY to UVM_DEBUG
+// Setting UVM_VERBOSITY to UVM_DEBUG causes all BFM's and all agents to display their parameter settings.
+// All of the messages from this feature have a UVM messaging id value of "CFG"
+// The transcript or run.log can be parsed to ensure BFM parameter settings match its corresponding agents parameter settings.
+import uvm_pkg::*;
+`include "uvm_macros.svh"
+initial begin : bfm_vs_agent_parameter_debug
+  `uvm_info("CFG",
+      $psprintf("The BFM at '%m' has the following parameters: ", ),
+      UVM_DEBUG)
+end
+`endif
+
+
+  // Structure used to pass transaction data from monitor BFM to monitor class in agent.
+`mbox_sram_MONITOR_STRUCT
+  mbox_sram_monitor_s mbox_sram_monitor_struct;
+
+  // Structure used to pass configuration data from monitor class to monitor BFM.
+ `mbox_sram_CONFIGURATION_STRUCT
+
+
+  // Config value to determine if this is an initiator or a responder
+  uvmf_initiator_responder_t initiator_responder;
+  // Custom configuration variables.
+  // These are set using the configure function which is called during the UVM connect_phase
+  bit [1:0] inject_ecc_error ;
+  bit auto_clear_ecc_error_injection ;
+
+  tri clk_i;
+  tri dummy_i;
+  tri mbox_sram_req_t  mbox_sram_req_i;
+  tri mbox_sram_resp_t mbox_sram_resp_i;
+  assign clk_i = bus.clk;
+  assign dummy_i = bus.dummy;
+  assign mbox_sram_req_i = bus.mbox_sram_req;
+  assign mbox_sram_resp_i = bus.mbox_sram_resp;
+
+  // Proxy handle to UVM monitor
+  mbox_sram_pkg::mbox_sram_monitor  proxy;
+  // pragma tbx oneway proxy.notify_transaction
+
+  // pragma uvmf custom interface_item_additional begin
+  function bit [1:0] rvecc_decode  ( input [31:0]  din, input [6:0]   ecc_in);
+    bit [6:0]  ecc_check;
+
+    // Generate the ecc bits
+    ecc_check[0] = ecc_in[0]^din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30];
+    ecc_check[1] = ecc_in[1]^din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31];
+    ecc_check[2] = ecc_in[2]^din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31];
+    ecc_check[3] = ecc_in[3]^din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25];
+    ecc_check[4] = ecc_in[4]^din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25];
+    ecc_check[5] = ecc_in[5]^din[26]^din[27]^din[28]^din[29]^din[30]^din[31];
+
+    // This is the parity bit
+    ecc_check[6] = ((^din[31:0])^(^ecc_in[6:0]));
+
+    rvecc_decode[0] = (ecc_check[6:0] != 0) &  ecc_check[6]; // Single-bit error
+    rvecc_decode[1] = (ecc_check[6:0] != 0) & ~ecc_check[6]; // Double-bit error
+
+  endfunction: rvecc_decode
+  // pragma uvmf custom interface_item_additional end
+
+  //******************************************************************
+  task wait_for_reset();// pragma tbx xtf
+//    @(posedge clk_i) ;
+//    do_wait_for_reset();
+  endtask
+
+  // ****************************************************************************
+  task do_wait_for_reset();
+  // pragma uvmf custom reset_condition begin
+    wait ( dummy_i === 1 ) ;
+    @(posedge clk_i) ;
+  // pragma uvmf custom reset_condition end
+  endtask
+
+  // pragma uvmf custom wait_for_num_clocks begin
+  //****************************************************************************                         
+  // Inject pragmas's here to throw a warning on regeneration.
+  // Task must have automatic lifetime so that it can be concurrently invoked
+  // by multiple entities with a different wait value.
+  task automatic wait_for_num_clocks(input int unsigned count); // pragma tbx xtf
+    if (count == 0) `uvm_fatal("CFG", "wait_for_num_clocks called with count of 0 - this will lead to a hang");
+    @(posedge clk_i);
+    repeat (count-1) @(posedge clk_i);
+  endtask
+  // pragma uvmf custom wait_for_num_clocks end                                                                
+
+  //******************************************************************
+  event go;
+  function void start_monitoring();// pragma tbx xtf
+    -> go;
+  endfunction
+
+  // ****************************************************************************
+  initial begin
+    @go;
+    forever begin
+      do_monitor( mbox_sram_monitor_struct );
+      proxy.notify_transaction( mbox_sram_monitor_struct );
+      // Back-to-back writes require a clock in between to avoid a 0-time forever loop.
+      // Reads already inject the extra clock cycle, so we can check cs again immediately.
+      if (!mbox_sram_monitor_struct.is_read) @(posedge clk_i);
+
+    end
+  end
+
+  //******************************************************************
+  // The configure() function is used to pass agent configuration
+  // variables to the monitor BFM.  It is called by the monitor within
+  // the agent at the beginning of the simulation.  It may be called
+  // during the simulation if agent configuration variables are updated
+  // and the monitor BFM needs to be aware of the new configuration
+  // variables.
+  //
+    function void configure(mbox_sram_configuration_s mbox_sram_configuration_arg); // pragma tbx xtf
+    initiator_responder = mbox_sram_configuration_arg.initiator_responder;
+    inject_ecc_error = mbox_sram_configuration_arg.inject_ecc_error;
+    auto_clear_ecc_error_injection = mbox_sram_configuration_arg.auto_clear_ecc_error_injection;
+  // pragma uvmf custom configure begin
+  // pragma uvmf custom configure end
+  endfunction
+
+
+  // ****************************************************************************
+
+  task do_monitor(output mbox_sram_monitor_s mbox_sram_monitor_struct);
+    //
+    // Available struct members:
+    //     //    mbox_sram_monitor_struct.is_read
+    //     //    mbox_sram_monitor_struct.address
+    //     //    mbox_sram_monitor_struct.data
+    //     //    mbox_sram_monitor_struct.data_ecc
+    //     //    mbox_sram_monitor_struct.ecc_single_bit_error
+    //     //    mbox_sram_monitor_struct.ecc_double_bit_error
+    //     //
+    // Reference code;
+    //    How to wait for signal value
+    //      while (control_signal === 1'b1) @(posedge clk_i);
+    //
+    //    How to assign a struct member, named xyz, from a signal.
+    //    All available input signals listed.
+    //      mbox_sram_monitor_struct.xyz = mbox_sram_req_i;  //    [$bits(mbox_sram_req_t)-1:0]
+    //      mbox_sram_monitor_struct.xyz = mbox_sram_resp_i;  //    [$bits(mbox_sram_resp_t)-1:0]
+    // pragma uvmf custom do_monitor begin
+    // UVMF_CHANGE_ME : Implement protocol monitoring.  The commented reference code
+    // below are examples of how to capture signal values and assign them to
+    // structure members.  All available input signals are listed.  The 'while'
+    // code example shows how to wait for a synchronous flow control signal.  This
+    // task should return when a complete transfer has been observed.  Once this task is
+    // exited with captured values, it is then called again to wait for and observe
+    // the next transfer. One clock cycle is consumed between calls to do_monitor.
+    while (mbox_sram_req_i.cs !== 1'b1) @(posedge clk_i);
+    mbox_sram_monitor_struct.is_read              = ~mbox_sram_req_i.we;
+    mbox_sram_monitor_struct.address              =  mbox_sram_req_i.addr;
+    mbox_sram_monitor_struct.data                 =  mbox_sram_req_i.wdata.data;
+    mbox_sram_monitor_struct.data_ecc             =  mbox_sram_req_i.wdata.ecc;
+    // For writes, the monitored transaction signals the _intent_ to inject an ECC error
+    // at the responder sequence
+    mbox_sram_monitor_struct.ecc_single_bit_error =  proxy.configuration.inject_ecc_error[0];
+    mbox_sram_monitor_struct.ecc_double_bit_error =  proxy.configuration.inject_ecc_error[1];
+    // If a write is detected, return immediately (that's the whole transaction)
+    if (mbox_sram_req_i.we) return;
+    // If a read, continue another clock cycle to capture return data
+    @(posedge clk_i);
+    mbox_sram_monitor_struct.data     = mbox_sram_resp_i.rdata.data;
+    mbox_sram_monitor_struct.data_ecc = mbox_sram_resp_i.rdata.ecc;
+    // For reads, the monitored transaction signals the calculation of actual ECC errors
+    // observed on the data returned from the responder sequence
+    {mbox_sram_monitor_struct.ecc_double_bit_error,
+     mbox_sram_monitor_struct.ecc_single_bit_error} = rvecc_decode(mbox_sram_monitor_struct.data, mbox_sram_monitor_struct.data_ecc);
+    // pragma uvmf custom do_monitor end
+  endtask
+
+
+endinterface
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_random_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_random_sequence.svh
new file mode 100644
index 000000000..90ce2cdb4
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_random_sequence.svh
@@ -0,0 +1,67 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//     
+// DESCRIPTION: 
+// This sequences randomizes the mbox_sram transaction and sends it 
+// to the UVM driver.
+//
+// This sequence constructs and randomizes a mbox_sram_transaction.
+// 
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class mbox_sram_random_sequence 
+  extends mbox_sram_sequence_base ;
+
+  `uvm_object_utils( mbox_sram_random_sequence )
+
+  // pragma uvmf custom class_item_additional begin
+  // pragma uvmf custom class_item_additional end
+  
+  //*****************************************************************
+  function new(string name = "");
+    super.new(name);
+  endfunction: new
+
+  // ****************************************************************************
+  // TASK : body()
+  // This task is automatically executed when this sequence is started using the 
+  // start(sequencerHandle) task.
+  //
+  task body();
+  
+      // Construct the transaction
+      req=mbox_sram_transaction::type_id::create("req");
+      start_item(req);
+      // Randomize the transaction
+      if(!req.randomize()) `uvm_fatal("SEQ", "mbox_sram_random_sequence::body()-mbox_sram_transaction randomization failed")
+      // Send the transaction to the mbox_sram_driver_bfm via the sequencer and mbox_sram_driver.
+      finish_item(req);
+      `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM)
+
+  endtask
+
+endclass: mbox_sram_random_sequence
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_responder_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_responder_sequence.svh
new file mode 100644
index 000000000..97e8efc3c
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_responder_sequence.svh
@@ -0,0 +1,122 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//     
+// DESCRIPTION: This class can be used to provide stimulus when an interface
+//              has been configured to run in a responder mode. It
+//              will never finish by default, always going back to the driver
+//              and driver BFM for the next transaction with which to respond.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class mbox_sram_responder_sequence 
+  extends mbox_sram_sequence_base ;
+
+  `uvm_object_utils( mbox_sram_responder_sequence )
+
+  // pragma uvmf custom class_item_additional begin
+  // Implement a model of the Mailbox SRAM
+  localparam NUM_BYTES = MBOX_DATA_AND_ECC_W/8 + ((MBOX_DATA_AND_ECC_W % 8) ? 1 : 0);
+  // TODO support initialization from mailbox.hex
+  logic [7:0] ram [MBOX_DEPTH][NUM_BYTES-1:0] = '{default: 8'h00};
+
+  function bit [1:0] rvecc_decode  ( input [31:0]  din, input [6:0]   ecc_in);
+    bit [6:0]  ecc_check;
+
+    // Generate the ecc bits
+    ecc_check[0] = ecc_in[0]^din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30];
+    ecc_check[1] = ecc_in[1]^din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31];
+    ecc_check[2] = ecc_in[2]^din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31];
+    ecc_check[3] = ecc_in[3]^din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25];
+    ecc_check[4] = ecc_in[4]^din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25];
+    ecc_check[5] = ecc_in[5]^din[26]^din[27]^din[28]^din[29]^din[30]^din[31];
+
+    // This is the parity bit
+    ecc_check[6] = ((^din[31:0])^(^ecc_in[6:0]));
+
+    rvecc_decode[0] = (ecc_check[6:0] != 0) &  ecc_check[6]; // Single-bit error
+    rvecc_decode[1] = (ecc_check[6:0] != 0) & ~ecc_check[6]; // Double-bit error
+
+  endfunction: rvecc_decode
+  // pragma uvmf custom class_item_additional end
+
+  function new(string name = "mbox_sram_responder_sequence");
+    super.new(name);
+  endfunction
+
+  task body();
+    req=mbox_sram_transaction::type_id::create("req");
+    forever begin
+      start_item(req);
+      finish_item(req);
+      // pragma uvmf custom body begin
+      // Do something here with the resulting req item.  The
+      // finish_item() call above will block until the req transaction is ready
+      // to be handled by the responder sequence.
+      // If this was an item that required a response, the expectation is
+      // that the response should be populated within this transaction now.
+      wait(new_rsp.triggered);
+      if (req.compare(rsp)) `uvm_info("MBOX_SRAM_SEQ", "req and rsp are the same after finish_item", UVM_DEBUG)
+      else                  `uvm_error("MBOX_SRAM_SEQ", $sformatf("NOTE: req and rsp are different after finish_item.\nreq: %s\nrsp: %s", req.convert2string(), rsp.convert2string()))
+      // The 'rsp' is actually a request from the DUT, we need to create a response
+      if (rsp.is_read) begin
+        byte unsigned ii;
+        for (ii=0;ii<MBOX_DATA_W/8;ii++) begin
+            req.data[ii*8+:8] = ram[rsp.address][ii];
+        end
+        req.data_ecc = ram[rsp.address][NUM_BYTES-1][MBOX_ECC_DATA_W-1:0];
+        {req.ecc_double_bit_error,
+         req.ecc_single_bit_error} = rvecc_decode(req.data, req.data_ecc);
+      end
+      else begin
+        byte unsigned ii;
+        mbox_sram_data_t wdata;
+        mbox_sram_data_t wdata_mask;
+        wdata.data = rsp.data;
+        wdata.ecc  = rsp.data_ecc;
+        if (rsp.ecc_double_bit_error) begin
+            if (!std::randomize(wdata_mask) with {$countones(wdata_mask) == 2;})
+                `uvm_error("MBOX_SRAM_SEQ", "Failed to generate a random mask to inject ECC double bit error!")
+            wdata ^= wdata_mask;
+            `uvm_info("MBOX_SRAM_SEQ", $sformatf("Injecting ECC double bit flip to write data. Modified data: 0x%x [%p]", wdata, wdata), UVM_HIGH)
+        end
+        else if (rsp.ecc_single_bit_error) begin
+            if (!std::randomize(wdata_mask) with {$countones(wdata_mask) == 1;})
+                `uvm_error("MBOX_SRAM_SEQ", "Failed to generate a random mask to inject ECC single bit error!")
+            wdata ^= wdata_mask;
+            `uvm_info("MBOX_SRAM_SEQ", $sformatf("Injecting ECC single bit flip to write data. Modified data: 0x%x [%p]", wdata, wdata), UVM_HIGH)
+        end
+        for (ii=0;ii<MBOX_DATA_W/8;ii++) begin
+            ram[rsp.address][ii] = wdata.data[ii*8+:8];
+        end
+        ram[rsp.address][NUM_BYTES-1][MBOX_ECC_DATA_W-1:0] = wdata.ecc;
+      end
+      `uvm_info("MBOX_SRAM_SEQ",$sformatf("Processed txn: %s",req.convert2string()),UVM_HIGH)
+      // pragma uvmf custom body end
+    end
+  endtask
+
+endclass
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_sequence_base.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_sequence_base.svh
new file mode 100644
index 000000000..f1908da4c
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_sequence_base.svh
@@ -0,0 +1,110 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//     
+// DESCRIPTION: 
+// This file contains the class used as the base class for all sequences
+// for this interface.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class mbox_sram_sequence_base    extends uvmf_sequence_base #(
+                             .REQ(mbox_sram_transaction  ),
+                             .RSP(mbox_sram_transaction  ));
+
+  `uvm_object_utils( mbox_sram_sequence_base )
+
+  // variables
+  typedef mbox_sram_transaction  mbox_sram_transaction_req_t;
+  mbox_sram_transaction_req_t req;
+  typedef mbox_sram_transaction  mbox_sram_transaction_rsp_t;
+  mbox_sram_transaction_rsp_t rsp;
+
+  // Event for identifying when a response was received from the sequencer
+  event new_rsp;
+
+
+  // pragma uvmf custom class_item_additional begin
+  // pragma uvmf custom class_item_additional end
+
+  // ****************************************************************************
+  // TASK : get_responses()
+  // This task recursively gets sequence item responses from the sequencer.
+  //
+  virtual task get_responses();
+    fork
+      forever begin
+        // Block until new rsp available
+        get_response(rsp);
+        // New rsp received.  Indicate to sequence using event.
+        ->new_rsp;
+        // Display the received response transaction
+        `uvm_info("SEQ", {"New response transaction:",rsp.convert2string()}, UVM_MEDIUM)
+      end
+    join_none
+  endtask
+
+  // ****************************************************************************
+  // TASK : pre_body()
+  // This task is called automatically when start is called with call_pre_post set to 1 (default).
+  // By calling get_responses() within pre_body() any derived sequences are automatically 
+  // processing response transactions. Only un-comment this call to get_responses() if you
+  // have configured the interface driver to utilize the response transaction path by setting
+  // the configuration variable "return_transaction_response" to 1. Otherwise it is possible
+  // to impact runtime performance and memory utilization.
+  //
+  virtual task pre_body();
+    // pragma uvmf custom pre_body begin
+    get_responses();
+    // pragma uvmf custom pre_body end
+  endtask
+
+  // ****************************************************************************
+  // TASK : body()
+  // This task is called automatically when start is called.  This sequence sends
+  // a req sequence item to the sequencer identified as an argument in the call
+  // to start.
+  //
+  virtual task body();
+    // pragma uvmf custom body begin
+  	start_item(req);
+  	finish_item(req);
+    // pragma uvmf custom body end
+  endtask
+
+  // ****************************************************************************
+  // FUNCTION : new()
+  // This function is the standard SystemVerilog constructor.
+  //
+  function new( string name ="");
+    super.new( name );
+    // pragma uvmf custom new begin
+    req = mbox_sram_transaction_req_t::type_id::create("req");
+    rsp = mbox_sram_transaction_rsp_t::type_id::create("rsp");
+    // pragma uvmf custom new end
+  endfunction
+
+endclass
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_transaction.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_transaction.svh
new file mode 100644
index 000000000..dd3049af0
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_transaction.svh
@@ -0,0 +1,216 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//     
+// DESCRIPTION: This class defines the variables required for an mbox_sram
+//    transaction.  Class variables to be displayed in waveform transaction
+//    viewing are added to the transaction viewing stream in the add_to_wave
+//    function.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class mbox_sram_transaction  extends uvmf_transaction_base;
+
+  `uvm_object_utils( mbox_sram_transaction )
+
+  rand bit is_read ;
+  rand bit [MBOX_ADDR_W-1:0] address ;
+  rand bit [MBOX_DATA_W-1:0] data ;
+  bit [MBOX_ECC_DATA_W-1:0] data_ecc ;
+  rand bit ecc_single_bit_error ;
+  rand bit ecc_double_bit_error ;
+
+  //Constraints for the transaction variables:
+
+  // pragma uvmf custom class_item_additional begin
+  // pragma uvmf custom class_item_additional end
+
+  //*******************************************************************
+  //*******************************************************************
+  // Macros that define structs and associated functions are
+  // located in mbox_sram_macros.svh
+
+  //*******************************************************************
+  // Monitor macro used by mbox_sram_monitor and mbox_sram_monitor_bfm
+  // This struct is defined in mbox_sram_macros.svh
+  `mbox_sram_MONITOR_STRUCT
+    mbox_sram_monitor_s mbox_sram_monitor_struct;
+  //*******************************************************************
+  // FUNCTION: to_monitor_struct()
+  // This function packs transaction variables into a mbox_sram_monitor_s
+  // structure.  The function returns the handle to the mbox_sram_monitor_struct.
+  // This function is defined in mbox_sram_macros.svh
+  `mbox_sram_TO_MONITOR_STRUCT_FUNCTION 
+  //*******************************************************************
+  // FUNCTION: from_monitor_struct()
+  // This function unpacks the struct provided as an argument into transaction 
+  // variables of this class.
+  // This function is defined in mbox_sram_macros.svh
+  `mbox_sram_FROM_MONITOR_STRUCT_FUNCTION 
+
+  //*******************************************************************
+  // Initiator macro used by mbox_sram_driver and mbox_sram_driver_bfm
+  // to communicate initiator driven data to mbox_sram_driver_bfm.
+  // This struct is defined in mbox_sram_macros.svh
+  `mbox_sram_INITIATOR_STRUCT
+    mbox_sram_initiator_s mbox_sram_initiator_struct;
+  //*******************************************************************
+  // FUNCTION: to_initiator_struct()
+  // This function packs transaction variables into a mbox_sram_initiator_s
+  // structure.  The function returns the handle to the mbox_sram_initiator_struct.
+  // This function is defined in mbox_sram_macros.svh
+  `mbox_sram_TO_INITIATOR_STRUCT_FUNCTION  
+  //*******************************************************************
+  // FUNCTION: from_initiator_struct()
+  // This function unpacks the struct provided as an argument into transaction 
+  // variables of this class.
+  // This function is defined in mbox_sram_macros.svh
+  `mbox_sram_FROM_INITIATOR_STRUCT_FUNCTION 
+
+  //*******************************************************************
+  // Responder macro used by mbox_sram_driver and mbox_sram_driver_bfm
+  // to communicate Responder driven data to mbox_sram_driver_bfm.
+  // This struct is defined in mbox_sram_macros.svh
+  `mbox_sram_RESPONDER_STRUCT
+    mbox_sram_responder_s mbox_sram_responder_struct;
+  //*******************************************************************
+  // FUNCTION: to_responder_struct()
+  // This function packs transaction variables into a mbox_sram_responder_s
+  // structure.  The function returns the handle to the mbox_sram_responder_struct.
+  // This function is defined in mbox_sram_macros.svh
+  `mbox_sram_TO_RESPONDER_STRUCT_FUNCTION 
+  //*******************************************************************
+  // FUNCTION: from_responder_struct()
+  // This function unpacks the struct provided as an argument into transaction 
+  // variables of this class.
+  // This function is defined in mbox_sram_macros.svh
+  `mbox_sram_FROM_RESPONDER_STRUCT_FUNCTION 
+  // ****************************************************************************
+  // FUNCTION : new()
+  // This function is the standard SystemVerilog constructor.
+  //
+  function new( string name = "" );
+    super.new( name );
+  endfunction
+
+  // ****************************************************************************
+  // FUNCTION: convert2string()
+  // This function converts all variables in this class to a single string for 
+  // logfile reporting.
+  //
+  virtual function string convert2string();
+    // pragma uvmf custom convert2string begin
+    // UVMF_CHANGE_ME : Customize format if desired.
+    return $sformatf("is_read:0x%x address:0x%x data:0x%x data_ecc:0x%x ecc_single_bit_error:0x%x ecc_double_bit_error:0x%x ",is_read,address,data,data_ecc,ecc_single_bit_error,ecc_double_bit_error);
+    // pragma uvmf custom convert2string end
+  endfunction
+
+  //*******************************************************************
+  // FUNCTION: do_print()
+  // This function is automatically called when the .print() function
+  // is called on this class.
+  //
+  virtual function void do_print(uvm_printer printer);
+    // pragma uvmf custom do_print begin
+    // UVMF_CHANGE_ME : Current contents of do_print allows for the use of UVM 1.1d, 1.2 or P1800.2.
+    // Update based on your own printing preference according to your preferred UVM version
+    $display(convert2string());
+    // pragma uvmf custom do_print end
+  endfunction
+
+  //*******************************************************************
+  // FUNCTION: do_compare()
+  // This function is automatically called when the .compare() function
+  // is called on this class.
+  //
+  virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer);
+    mbox_sram_transaction  RHS;
+    if (!$cast(RHS,rhs)) return 0;
+    // pragma uvmf custom do_compare begin
+    // UVMF_CHANGE_ME : Eliminate comparison of variables not to be used for compare
+    return (super.do_compare(rhs,comparer)
+            &&(this.is_read == RHS.is_read)
+            &&(this.address == RHS.address)
+            &&(this.data == RHS.data)
+            &&(this.data_ecc == RHS.data_ecc)
+            &&(this.ecc_single_bit_error == RHS.ecc_single_bit_error)
+            &&(this.ecc_double_bit_error == RHS.ecc_double_bit_error)
+            );
+    // pragma uvmf custom do_compare end
+  endfunction
+
+  //*******************************************************************
+  // FUNCTION: do_copy()
+  // This function is automatically called when the .copy() function
+  // is called on this class.
+  //
+  virtual function void do_copy (uvm_object rhs);
+    mbox_sram_transaction  RHS;
+    assert($cast(RHS,rhs));
+    // pragma uvmf custom do_copy begin
+    super.do_copy(rhs);
+    this.is_read = RHS.is_read;
+    this.address = RHS.address;
+    this.data = RHS.data;
+    this.data_ecc = RHS.data_ecc;
+    this.ecc_single_bit_error = RHS.ecc_single_bit_error;
+    this.ecc_double_bit_error = RHS.ecc_double_bit_error;
+    // pragma uvmf custom do_copy end
+  endfunction
+
+  // ****************************************************************************
+  // FUNCTION: add_to_wave()
+  // This function is used to display variables in this class in the waveform 
+  // viewer.  The start_time and end_time variables must be set before this 
+  // function is called.  If the start_time and end_time variables are not set
+  // the transaction will be hidden at 0ns on the waveform display.
+  // 
+  virtual function void add_to_wave(int transaction_viewing_stream_h);
+    `ifdef QUESTA
+    if (transaction_view_h == 0) begin
+      transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"mbox_sram_transaction",start_time);
+    end
+    super.add_to_wave(transaction_view_h);
+    // pragma uvmf custom add_to_wave begin
+    // UVMF_CHANGE_ME : Color can be applied to transaction entries based on content, example below
+    // case()
+    //   1 : $add_color(transaction_view_h,"red");
+    //   default : $add_color(transaction_view_h,"grey");
+    // endcase
+    // UVMF_CHANGE_ME : Eliminate transaction variables not wanted in transaction viewing in the waveform viewer
+    $add_attribute(transaction_view_h,is_read,"is_read");
+    $add_attribute(transaction_view_h,address,"address");
+    $add_attribute(transaction_view_h,data,"data");
+    $add_attribute(transaction_view_h,data_ecc,"data_ecc");
+    $add_attribute(transaction_view_h,ecc_single_bit_error,"ecc_single_bit_error");
+    $add_attribute(transaction_view_h,ecc_double_bit_error,"ecc_double_bit_error");
+    // pragma uvmf custom add_to_wave end
+    $end_transaction(transaction_view_h,end_time);
+    $free_transaction(transaction_view_h);
+    `endif // QUESTA
+  endfunction
+
+endclass
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_transaction_coverage.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_transaction_coverage.svh
new file mode 100644
index 000000000..9c935c889
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_transaction_coverage.svh
@@ -0,0 +1,107 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//     
+// DESCRIPTION: This class records mbox_sram transaction information using
+//       a covergroup named mbox_sram_transaction_cg.  An instance of this
+//       coverage component is instantiated in the uvmf_parameterized_agent
+//       if the has_coverage flag is set.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+covergroup mbox_sram_transaction_bit_cg with function sample(input bit val);
+  option.per_instance = 1;
+  ea_bit: coverpoint val;
+endgroup
+
+class mbox_sram_transaction_coverage  extends uvm_subscriber #(.T(mbox_sram_transaction ));
+
+  `uvm_component_utils( mbox_sram_transaction_coverage )
+
+  T coverage_trans;
+
+  // pragma uvmf custom class_item_additional begin
+  mbox_sram_transaction_bit_cg address_bit_cg[MBOX_ADDR_W];
+  mbox_sram_transaction_bit_cg data_bit_cg[MBOX_DATA_W];
+  mbox_sram_transaction_bit_cg data_ecc_bit_cg[MBOX_ECC_DATA_W];
+  // pragma uvmf custom class_item_additional end
+  
+  // ****************************************************************************
+  covergroup mbox_sram_transaction_cg;
+    // pragma uvmf custom covergroup begin
+    // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs.
+    option.auto_bin_max=1024;
+    option.per_instance=1;
+    is_read: coverpoint coverage_trans.is_read;
+    address: coverpoint coverage_trans.address;
+    data: coverpoint coverage_trans.data;
+    data_ecc: coverpoint coverage_trans.data_ecc;
+    ecc_single_bit_error: coverpoint coverage_trans.ecc_single_bit_error;
+    ecc_double_bit_error: coverpoint coverage_trans.ecc_double_bit_error;
+    // TODO add checks for ecc single/double errors, address='0, address='1, address alignment cases
+    // TODO add cross for read transaction, write transaction
+    // pragma uvmf custom covergroup end
+  endgroup
+
+  // ****************************************************************************
+  // FUNCTION : new()
+  // This function is the standard SystemVerilog constructor.
+  //
+  function new(string name="", uvm_component parent=null);
+    super.new(name,parent);
+    mbox_sram_transaction_cg=new;
+    foreach (coverage_trans.address[bt]) address_bit_cg[bt] = new;
+    foreach (coverage_trans.data[bt]) data_bit_cg[bt] = new;
+    foreach (coverage_trans.data_ecc[bt]) data_ecc_bit_cg[bt] = new;
+  endfunction
+
+  // ****************************************************************************
+  // FUNCTION : build_phase()
+  // This function is the standard UVM build_phase.
+  //
+  function void build_phase(uvm_phase phase);
+    mbox_sram_transaction_cg.set_inst_name($sformatf("mbox_sram_transaction_cg_%s",get_full_name()));
+    foreach (coverage_trans.address[bt])  address_bit_cg[bt].set_inst_name($sformatf("address_bit_cg_%d_%s", bt, get_full_name()));
+    foreach (coverage_trans.data[bt])     data_bit_cg[bt].set_inst_name($sformatf("data_bit_cg_%d_%s", bt, get_full_name()));
+    foreach (coverage_trans.data_ecc[bt]) data_ecc_bit_cg[bt].set_inst_name($sformatf("data_ecc_bit_cg_%d_%s", bt, get_full_name()));
+  endfunction
+
+  // ****************************************************************************
+  // FUNCTION: write (T t)
+  // This function is automatically executed when a transaction arrives on the
+  // analysis_export.  It copies values from the variables in the transaction 
+  // to local variables used to collect functional coverage.  
+  //
+  virtual function void write (T t);
+    `uvm_info("COV","Received transaction",UVM_HIGH);
+    coverage_trans = t;
+    mbox_sram_transaction_cg.sample();
+    foreach (coverage_trans.address [bt]) address_bit_cg [bt].sample(coverage_trans.address [bt]);
+    foreach (coverage_trans.data    [bt]) data_bit_cg    [bt].sample(coverage_trans.data    [bt]);
+    foreach (coverage_trans.data_ecc[bt]) data_ecc_bit_cg[bt].sample(coverage_trans.data_ecc[bt]);
+  endfunction
+
+endclass
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_typedefs.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_typedefs.svh
new file mode 100644
index 000000000..f2a7bdb94
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_typedefs.svh
@@ -0,0 +1,34 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//     
+// DESCRIPTION: 
+// This file contains defines and typedefs to be compiled for use in
+// the simulation running on the host server when using Veloce.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+
+
+// pragma uvmf custom additional begin
+// pragma uvmf custom additional end
+
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_typedefs_hdl.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_typedefs_hdl.svh
new file mode 100644
index 000000000..0d58518e2
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/src/mbox_sram_typedefs_hdl.svh
@@ -0,0 +1,35 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//     
+// DESCRIPTION: 
+// This file contains defines and typedefs to be compiled for use in
+// the simulation running on the emulator when using Veloce.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+                                                                               
+
+
+// pragma uvmf custom additional begin
+// pragma uvmf custom additional end
+
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/yaml/mbox_sram_interface.yaml b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/yaml/mbox_sram_interface.yaml
new file mode 100644
index 000000000..903678275
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/mbox_sram_pkg/yaml/mbox_sram_interface.yaml
@@ -0,0 +1,73 @@
+uvmf:
+  interfaces:
+    mbox_sram:
+      clock: clk
+      config_constraints: []
+      config_vars:
+      - comment: 'Controls injection of ECC errors for write transactions. Bit[0]: Single Bit Error. Bit[1]: Double Bit Error'
+        isrand: 'False'
+        name: inject_ecc_error
+        type: bit [1:0]
+        value: 1'b0
+      - comment: When set, causes the mbox_sram_responder_sequence to clear the variable 'inject_ecc_error' after a single ECC error is injected
+        isrand: 'False'
+        name: auto_clear_ecc_error_injection
+        type: bit
+        value: 1'b1
+      existing_library_component: 'True'
+      gen_inbound_streaming_driver: 'False'
+      hdl_pkg_parameters: []
+      hdl_typedefs: []
+      hvl_pkg_parameters: []
+      hvl_typedefs: []
+      parameters: []
+      ports:
+      - dir: output
+        name: mbox_sram_req
+        reset_value: '''bz'
+        width: $bits(mbox_sram_req_t)
+      - dir: input
+        name: mbox_sram_resp
+        reset_value: '''bz'
+        width: $bits(mbox_sram_resp_t)
+      reset: dummy
+      reset_assertion_level: 'False'
+      transaction_constraints: []
+      transaction_vars:
+      - comment: ''
+        iscompare: 'True'
+        isrand: 'True'
+        name: is_read
+        type: bit
+        unpacked_dimension: ''
+      - comment: ''
+        iscompare: 'True'
+        isrand: 'True'
+        name: address
+        type: bit [MBOX_ADDR_W-1:0]
+        unpacked_dimension: ''
+      - comment: ''
+        iscompare: 'True'
+        isrand: 'True'
+        name: data
+        type: bit [MBOX_DATA_W-1:0]
+        unpacked_dimension: ''
+      - comment: ''
+        iscompare: 'True'
+        isrand: 'False'
+        name: data_ecc
+        type: bit [MBOX_ECC_DATA_W-1:0]
+        unpacked_dimension: ''
+      - comment: ''
+        iscompare: 'True'
+        isrand: 'True'
+        name: ecc_single_bit_error
+        type: bit
+        unpacked_dimension: ''
+      - comment: ''
+        iscompare: 'True'
+        isrand: 'True'
+        name: ecc_double_bit_error
+        type: bit
+        unpacked_dimension: ''
+      use_dpi_link: 'False'
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/soc_ifc_ctrl_pkg.sv b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/soc_ifc_ctrl_pkg.sv
index 85624b2e8..32a87187f 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/soc_ifc_ctrl_pkg.sv
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/soc_ifc_ctrl_pkg.sv
@@ -85,8 +85,11 @@ package soc_ifc_ctrl_pkg;
    //    the new sequence after any base sequences of the new sequence.
    `include "src/soc_ifc_ctrl_reset_sequence_base.svh"
    `include "src/soc_ifc_ctrl_poweron_sequence.svh"
+   `include "src/soc_ifc_ctrl_rom_poweron_sequence.svh"
    `include "src/soc_ifc_ctrl_reset_warm_sequence.svh"
    `include "src/soc_ifc_ctrl_reset_cold_sequence.svh"
+   `include "src/soc_ifc_ctrl_wdt_cascade_sequence.svh"
+   `include "src/soc_ifc_ctrl_wdt_independent_sequence.svh"
    // pragma uvmf custom package_item_additional end
 
 endpackage
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_monitor_bfm.sv b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_monitor_bfm.sv
index 6e6c1e325..171da784b 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_monitor_bfm.sv
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_monitor_bfm.sv
@@ -184,8 +184,8 @@ end
   // Task must have automatic lifetime so that it can be concurrently invoked
   // by multiple entities with a different wait value.
   task automatic wait_for_num_clocks(input int unsigned count); // pragma tbx xtf 
-    @(posedge clk_i);  
-                                                                   
+    if (count == 0) `uvm_fatal("CFG", "wait_for_num_clocks called with count of 0 - this will lead to a hang");
+    @(posedge clk_i);
     repeat (count-1) @(posedge clk_i);                                                    
   endtask      
   // pragma uvmf custom wait_for_num_clocks end                                                                
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_reset_sequence_base.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_reset_sequence_base.svh
index e93a29ef3..715992a1a 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_reset_sequence_base.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_reset_sequence_base.svh
@@ -37,7 +37,7 @@ class soc_ifc_ctrl_reset_sequence_base
   // pragma uvmf custom class_item_additional begin
   bit warm_reset_only = 1'b0;
   bit set_bootfsm_breakpoint;
-  bit debug_locked = 1'b1; // Can randomize this with another sequence...
+  security_state_t security_state;
   bit [7:0] [31:0] cptra_obf_key ;
   // pragma uvmf custom class_item_additional end
 
@@ -58,7 +58,6 @@ class soc_ifc_ctrl_reset_sequence_base
       if(!req.randomize()) `uvm_fatal("SOC_IFC_CTRL_RST", "soc_ifc_ctrl_reset_sequence_base::body()-soc_ifc_ctrl_transaction randomization failed")
       req.set_pwrgood = 1'b0;
       req.assert_rst = 1'b1; // active-low assertion
-      req.security_state.debug_locked = this.debug_locked;
       // Send the transaction to the soc_ifc_ctrl_driver_bfm via the sequencer and soc_ifc_ctrl_driver.
       finish_item(req);
       `uvm_info("SOC_IFC_CTRL_RST", {"Response:",req.convert2string()},UVM_MEDIUM)
@@ -78,7 +77,6 @@ class soc_ifc_ctrl_reset_sequence_base
       if(!req.randomize()) `uvm_fatal("SOC_IFC_CTRL_RST", "soc_ifc_ctrl_reset_sequence_base::body()-soc_ifc_ctrl_transaction randomization failed")
       req.set_pwrgood = 1'b1;
       req.assert_rst = 1'b1; // active-low assertion
-      req.security_state.debug_locked = this.debug_locked;
       if (warm_reset_only) begin
           this.cptra_obf_key     = req.cptra_obf_key_rand;
           this.set_bootfsm_breakpoint = req.set_bootfsm_breakpoint;
@@ -104,12 +102,12 @@ class soc_ifc_ctrl_reset_sequence_base
       if(!req.randomize()) `uvm_fatal("SOC_IFC_CTRL_RST", "soc_ifc_ctrl_reset_sequence_base::body()-soc_ifc_ctrl_transaction randomization failed")
       req.set_pwrgood = 1'b1;
       req.assert_rst = 1'b0;
-      req.security_state.debug_locked = this.debug_locked;
       req.cptra_obf_key_rand          = this.cptra_obf_key;
       req.set_bootfsm_breakpoint      = this.set_bootfsm_breakpoint;
       req.wait_cycles = 0;
       // Send the transaction to the soc_ifc_ctrl_driver_bfm via the sequencer and soc_ifc_ctrl_driver.
       finish_item(req);
+      this.security_state = req.security_state;
       `uvm_info("SOC_IFC_CTRL_RST", {"Response:",req.convert2string()},UVM_MEDIUM)
 
   endtask
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_rom_poweron_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_rom_poweron_sequence.svh
new file mode 100644
index 000000000..841c92a7b
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_rom_poweron_sequence.svh
@@ -0,0 +1,62 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+// DESCRIPTION:
+// This sequences randomizes the soc_ifc_ctrl transaction and sends it
+// to the UVM driver.
+//
+// This sequence constructs and randomizes a soc_ifc_ctrl_transaction.
+//
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_ctrl_rom_poweron_sequence
+  extends soc_ifc_ctrl_reset_sequence_base ;
+
+  `uvm_object_utils( soc_ifc_ctrl_rom_poweron_sequence )
+
+  //*****************************************************************
+  function new(string name = "");
+    super.new(name);
+  endfunction: new
+
+  // ****************************************************************************
+  // TASK : assert_cold_rst()
+  // Invoked by body()
+  //
+  virtual task assert_cold_rst();
+      // Initialize first transaction with pwrgood = 0, cptra_rst_b = 0 (asserted)
+      req=soc_ifc_ctrl_transaction::type_id::create("pwr_req");
+      start_item(req);
+      // Randomize the transaction (must be DEVICE_UNPROVISIONED for ROM bringup)
+      if(!req.randomize() with {security_state.device_lifecycle != DEVICE_UNPROVISIONED;})
+        `uvm_fatal("SOC_IFC_CTRL_RST", "soc_ifc_ctrl_reset_sequence_base::body()-soc_ifc_ctrl_transaction randomization failed")
+      req.set_pwrgood = 1'b0;
+      req.assert_rst = 1'b1; // active-low assertion
+      // Send the transaction to the soc_ifc_ctrl_driver_bfm via the sequencer and soc_ifc_ctrl_driver.
+      finish_item(req);
+      `uvm_info("SOC_IFC_CTRL_RST", {"Response:",req.convert2string()},UVM_MEDIUM)
+      this.cptra_obf_key          = req.cptra_obf_key_rand;
+      this.set_bootfsm_breakpoint = req.set_bootfsm_breakpoint;
+  endtask
+
+endclass: soc_ifc_ctrl_rom_poweron_sequence
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_transaction.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_transaction.svh
index aa0afde7c..4266453ce 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_transaction.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_transaction.svh
@@ -43,8 +43,15 @@ class soc_ifc_ctrl_transaction  extends uvmf_transaction_base;
   //Constraints for the transaction variables:
   constraint wait_cycles_c { wait_cycles dist {[1:25] := 80, [25:100] := 15, [100:500] := 5}; }
   constraint generic_tie_zero_c { generic_input_val == 64'h0; }
+  constraint debug_locked_c {security_state.debug_locked == 1'b1;} //reset sequence tied this off, doing it here instead
   constraint device_lifecycle_const_c { if (device_lifecycle_set_static) {security_state.device_lifecycle == device_lifecycle_static; } }
   
+  //Match RTL constraint for latching bootfsm breakpoint
+  //we'll never set bootfsm breakpoint unless we are in the appropriate debug/device lifecycle state to latch it in RTL
+  constraint set_bootfsm_breakpoint_c { if ((security_state.debug_locked) & 
+                                            ~((security_state.debug_locked) & (security_state.device_lifecycle == DEVICE_MANUFACTURING)))
+                                            {set_bootfsm_breakpoint == 0;} 
+                                          solve security_state before set_bootfsm_breakpoint; }
 
   // pragma uvmf custom class_item_additional begin
   static device_lifecycle_e device_lifecycle_static = 'X;
@@ -128,7 +135,7 @@ class soc_ifc_ctrl_transaction  extends uvmf_transaction_base;
   virtual function string convert2string();
     // pragma uvmf custom convert2string begin
     // UVMF_CHANGE_ME : Customize format if desired.
-    return $sformatf("cptra_obf_key_rand:0x%x set_pwrgood:0x%x assert_rst:0x%x wait_cycles:0x%x security_state:%p set_bootfsm_breakpoint:0x%x generic_input_val:0x%x ",cptra_obf_key_rand,set_pwrgood,assert_rst,wait_cycles,security_state,set_bootfsm_breakpoint,generic_input_val);
+    return $sformatf("cptra_obf_key_rand:0x%x set_pwrgood:0x%x assert_rst:0x%x wait_cycles:0x%x security_state:%p set_bootfsm_breakpoint:0x%x generic_input_val:0x%x %s",cptra_obf_key_rand,set_pwrgood,assert_rst,wait_cycles,security_state,set_bootfsm_breakpoint,generic_input_val,super.convert2string());
     // pragma uvmf custom convert2string end
   endfunction
 
@@ -219,6 +226,7 @@ endclass
 // pragma uvmf custom external begin
 function void soc_ifc_ctrl_transaction::post_randomize();
     super.post_randomize();
+
     if (!device_lifecycle_set_static || (device_lifecycle_static == 'hX)) begin
         device_lifecycle_static = this.security_state.device_lifecycle;
         device_lifecycle_set_static = 1'b1;
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_transaction_coverage.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_transaction_coverage.svh
index d4d918af5..c245cbb33 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_transaction_coverage.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_transaction_coverage.svh
@@ -28,6 +28,11 @@
 //----------------------------------------------------------------------
 //----------------------------------------------------------------------
 //
+covergroup soc_ifc_ctrl_transaction_bit_cg with function sample(input bit val);
+  option.per_instance = 1;
+  ea_bit: coverpoint val;
+endgroup
+
 class soc_ifc_ctrl_transaction_coverage  extends uvm_subscriber #(.T(soc_ifc_ctrl_transaction ));
 
   `uvm_component_utils( soc_ifc_ctrl_transaction_coverage )
@@ -35,6 +40,8 @@ class soc_ifc_ctrl_transaction_coverage  extends uvm_subscriber #(.T(soc_ifc_ctr
   T coverage_trans;
 
   // pragma uvmf custom class_item_additional begin
+  soc_ifc_ctrl_transaction_bit_cg cptra_obf_key_rand_bit_cg[`CLP_OBF_KEY_DWORDS-1:0] [31:0];
+  soc_ifc_ctrl_transaction_bit_cg  generic_input_val_bit_cg[63:0]                          ;
   // pragma uvmf custom class_item_additional end
   
   // ****************************************************************************
@@ -43,13 +50,39 @@ class soc_ifc_ctrl_transaction_coverage  extends uvm_subscriber #(.T(soc_ifc_ctr
     // UVMF_CHANGE_ME : Add coverage bins, crosses, exclusions, etc. according to coverage needs.
     option.auto_bin_max=1024;
     option.per_instance=1;
-    cptra_obf_key_rand: coverpoint coverage_trans.cptra_obf_key_rand;
+    cptra_obf_key_rand: coverpoint coverage_trans.cptra_obf_key_rand {
+        bins zero_key  = {0};
+        bins rand_key  = {[1:{`CLP_OBF_KEY_DWORDS{32'hFFFF_FFFF}}-1]};
+        bins ones_key  = {{`CLP_OBF_KEY_DWORDS{32'hFFFF_FFFF}}};
+    }
     set_pwrgood: coverpoint coverage_trans.set_pwrgood;
     assert_rst: coverpoint coverage_trans.assert_rst;
-    wait_cycles: coverpoint coverage_trans.wait_cycles;
+    wait_cycles: coverpoint coverage_trans.wait_cycles {
+        bins zero_wait  = {0};
+        bins one_wait   = {1};
+        bins small_wait = {[2:255]};
+        bins med_wait   = {[256:1023]};
+        bins large_wait = {[1024:65535]};
+        bins max_wait   = {[65536:$]};
+    }
     security_state: coverpoint coverage_trans.security_state;
     set_bootfsm_breakpoint: coverpoint coverage_trans.set_bootfsm_breakpoint;
-    generic_input_val: coverpoint coverage_trans.generic_input_val;
+    generic_input_val: coverpoint coverage_trans.generic_input_val {
+        bins byte_none = {64'h0000_0000_0000_0000};
+        bins byte_0    = {[0:$]} with ($countones(item[ 7: 0] > 0));
+        bins byte_1    = {[0:$]} with ($countones(item[15: 8] > 0));
+        bins byte_2    = {[0:$]} with ($countones(item[23:16] > 0));
+        bins byte_3    = {[0:$]} with ($countones(item[31:24] > 0));
+        bins byte_4    = {[0:$]} with ($countones(item[39:32] > 0));
+        bins byte_5    = {[0:$]} with ($countones(item[47:40] > 0));
+        bins byte_6    = {[0:$]} with ($countones(item[55:48] > 0));
+        bins byte_7    = {[0:$]} with ($countones(item[63:56] > 0));
+    }
+
+    cross_rst : cross set_pwrgood, assert_rst;
+    cross_brk : cross assert_rst, set_bootfsm_breakpoint {
+        bins brkpoint_while_rst = binsof (set_bootfsm_breakpoint) with (assert_rst == 1);
+    }
     // pragma uvmf custom covergroup end
   endgroup
 
@@ -60,7 +93,8 @@ class soc_ifc_ctrl_transaction_coverage  extends uvm_subscriber #(.T(soc_ifc_ctr
   function new(string name="", uvm_component parent=null);
     super.new(name,parent);
     soc_ifc_ctrl_transaction_cg=new;
-    `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging.  Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup.  Remove this warning after the covergroup has been reviewed.")
+    foreach (coverage_trans.cptra_obf_key_rand[dw,bt]) cptra_obf_key_rand_bit_cg[dw][bt] = new;
+    foreach (coverage_trans.generic_input_val[bt]     ) generic_input_val_bit_cg[bt]     = new;
   endfunction
 
   // ****************************************************************************
@@ -69,6 +103,8 @@ class soc_ifc_ctrl_transaction_coverage  extends uvm_subscriber #(.T(soc_ifc_ctr
   //
   function void build_phase(uvm_phase phase);
     soc_ifc_ctrl_transaction_cg.set_inst_name($sformatf("soc_ifc_ctrl_transaction_cg_%s",get_full_name()));
+    foreach (coverage_trans.cptra_obf_key_rand[dw,bt]) cptra_obf_key_rand_bit_cg[dw][bt].set_inst_name($sformatf("cptra_obf_key_rand_bit_cg_%d_%d_%s",dw, bt, get_full_name()));
+    foreach (coverage_trans. generic_input_val[bt])     generic_input_val_bit_cg[bt]    .set_inst_name($sformatf( "generic_input_val_bit_cg_%d_%s",       bt, get_full_name()));
   endfunction
 
   // ****************************************************************************
@@ -81,6 +117,8 @@ class soc_ifc_ctrl_transaction_coverage  extends uvm_subscriber #(.T(soc_ifc_ctr
     `uvm_info("COV","Received transaction",UVM_HIGH);
     coverage_trans = t;
     soc_ifc_ctrl_transaction_cg.sample();
+    foreach (coverage_trans.cptra_obf_key_rand[dw,bt]) cptra_obf_key_rand_bit_cg[dw][bt].sample(coverage_trans.cptra_obf_key_rand[dw][bt]);
+    foreach (coverage_trans. generic_input_val[bt])     generic_input_val_bit_cg[bt]    .sample(coverage_trans.generic_input_val[bt]);
   endfunction
 
 endclass
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_wdt_cascade_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_wdt_cascade_sequence.svh
new file mode 100644
index 000000000..bd100d1dd
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_wdt_cascade_sequence.svh
@@ -0,0 +1,70 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//     
+// DESCRIPTION: 
+// This sequences randomizes the soc_ifc_ctrl transaction and sends it 
+// to the UVM driver.
+//
+// This sequence constructs and randomizes a soc_ifc_ctrl_transaction.
+// 
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_ctrl_wdt_cascade_sequence 
+  extends soc_ifc_ctrl_sequence_base ;
+
+  `uvm_object_utils( soc_ifc_ctrl_wdt_cascade_sequence )
+
+  // pragma uvmf custom class_item_additional begin
+  // pragma uvmf custom class_item_additional end
+  
+  //*****************************************************************
+  function new(string name = "");
+    super.new(name);
+  endfunction: new
+
+  // ****************************************************************************
+  // TASK : body()
+  // This task is automatically executed when this sequence is started using the 
+  // start(sequencerHandle) task.
+  //
+  task body();
+  
+      // Construct the transaction
+      req=soc_ifc_ctrl_transaction::type_id::create("req");
+      start_item(req);
+      // Randomize the transaction
+      if(!req.randomize()) `uvm_fatal("SEQ", "soc_ifc_ctrl_wdt_cascade_sequence::body()-soc_ifc_ctrl_transaction randomization failed")
+      req.generic_input_val = 64'hABAB;
+      req.set_pwrgood = 'b1;
+      req.assert_rst = 'b0;
+      // Send the transaction to the soc_ifc_ctrl_driver_bfm via the sequencer and soc_ifc_ctrl_driver.
+      finish_item(req);
+      `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM)
+
+  endtask
+
+endclass: soc_ifc_ctrl_wdt_cascade_sequence
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_wdt_independent_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_wdt_independent_sequence.svh
new file mode 100644
index 000000000..ff420478f
--- /dev/null
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_ctrl_pkg/src/soc_ifc_ctrl_wdt_independent_sequence.svh
@@ -0,0 +1,84 @@
+//----------------------------------------------------------------------
+// Created with uvmf_gen version 2022.3
+//----------------------------------------------------------------------
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// pragma uvmf custom header begin
+// pragma uvmf custom header end
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//     
+// DESCRIPTION: 
+// This sequences randomizes the soc_ifc_ctrl transaction and sends it 
+// to the UVM driver.
+//
+// This sequence constructs and randomizes a soc_ifc_ctrl_transaction.
+// 
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+//
+class soc_ifc_ctrl_wdt_independent_sequence 
+  extends soc_ifc_ctrl_sequence_base ;
+
+  `uvm_object_utils( soc_ifc_ctrl_wdt_independent_sequence )
+
+  // pragma uvmf custom class_item_additional begin
+  // pragma uvmf custom class_item_additional end
+  
+  //*****************************************************************
+  function new(string name = "");
+    super.new(name);
+  endfunction: new
+
+  // ****************************************************************************
+  // TASK : body()
+  // This task is automatically executed when this sequence is started using the 
+  // start(sequencerHandle) task.
+  //
+  task body();
+
+      // Construct the transaction
+    req=soc_ifc_ctrl_transaction::type_id::create("req");
+    start_item(req);
+    // Randomize the transaction
+    if(!req.randomize()) `uvm_fatal("SEQ", "soc_ifc_ctrl_wdt_independent_sequence::body()-soc_ifc_ctrl_transaction randomization failed")
+    // req.wait_cycles = 'd1000;
+    req.generic_input_val = 64'h1234_5678_90AB_CDEF;
+    req.set_pwrgood = 'b1;
+    req.assert_rst = 'b0;
+    // Send the transaction to the soc_ifc_ctrl_driver_bfm via the sequencer and soc_ifc_ctrl_driver.
+    finish_item(req);
+    `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM)
+
+      // Construct the transaction
+      req=soc_ifc_ctrl_transaction::type_id::create("req");
+      start_item(req);
+      // Randomize the transaction
+      if(!req.randomize()) `uvm_fatal("SEQ", "soc_ifc_ctrl_wdt_independent_sequence::body()-soc_ifc_ctrl_transaction randomization failed")
+      // req.wait_cycles = 'd1000;
+      req.generic_input_val = 64'hEFEF;
+      req.set_pwrgood = 'b1;
+      req.assert_rst = 'b0;
+      // Send the transaction to the soc_ifc_ctrl_driver_bfm via the sequencer and soc_ifc_ctrl_driver.
+      finish_item(req);
+      `uvm_info("SEQ", {"Response:",req.convert2string()},UVM_MEDIUM)
+
+  endtask
+
+endclass: soc_ifc_ctrl_wdt_independent_sequence
+
+// pragma uvmf custom external begin
+// pragma uvmf custom external end
+
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src/soc_ifc_status_driver_bfm.sv b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src/soc_ifc_status_driver_bfm.sv
index 308e98511..54133ce34 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src/soc_ifc_status_driver_bfm.sv
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src/soc_ifc_status_driver_bfm.sv
@@ -370,12 +370,12 @@ bit first_transfer=1;
 //  end
     // Wait for next transfer then gather info from intiator about the transfer.
     // Place the data into the soc_ifc_status_initiator_struct.
-    do begin
+    @(posedge clk_i);
+    while (!any_signal_changed()) begin
         cptra_error_fatal_o            <= cptra_error_fatal_i    ;
         cptra_error_non_fatal_o        <= cptra_error_non_fatal_i;
         @(posedge clk_i);
     end
-    while (!any_signal_changed());
     ready_for_fuses_o              <= ready_for_fuses_i      ;
     ready_for_fw_push_o            <= ready_for_fw_push_i    ;
     ready_for_runtime_o            <= ready_for_runtime_i    ;
@@ -394,9 +394,9 @@ bit first_transfer=1;
          soc_ifc_status_initiator_struct.ready_for_runtime                  = ready_for_runtime_i;
          soc_ifc_status_initiator_struct.mailbox_data_avail                 = mailbox_data_avail_i;
          soc_ifc_status_initiator_struct.mailbox_flow_done                  = mailbox_flow_done_i;
-         soc_ifc_status_responder_struct.cptra_error_fatal_intr_pending     = cptra_error_fatal_i;  //     
-         soc_ifc_status_responder_struct.cptra_error_non_fatal_intr_pending = cptra_error_non_fatal_i;  //     
-         soc_ifc_status_responder_struct.trng_req_pending                   = trng_req_i;  //     
+         soc_ifc_status_initiator_struct.cptra_error_fatal_intr_pending     = cptra_error_fatal_i;
+         soc_ifc_status_initiator_struct.cptra_error_non_fatal_intr_pending = cptra_error_non_fatal_i;
+         soc_ifc_status_initiator_struct.trng_req_pending                   = trng_req_i;
          soc_ifc_status_initiator_struct.generic_output_val                 = generic_output_wires_i;
     end
   endtask
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src/soc_ifc_status_monitor.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src/soc_ifc_status_monitor.svh
index 07a530944..ef48ed8cf 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src/soc_ifc_status_monitor.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src/soc_ifc_status_monitor.svh
@@ -111,7 +111,7 @@ function void soc_ifc_status_monitor::force_advance_txn_key(int unsigned incr);
 endfunction
 
 task soc_ifc_status_monitor::handle_reset(string kind = "HARD");
-    txn_key = 0;
+    if (kind inside {"HARD","NONCORE"})
+        txn_key = 0;
 endtask
 // pragma uvmf custom external end
-
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src/soc_ifc_status_monitor_bfm.sv b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src/soc_ifc_status_monitor_bfm.sv
index d4feb990a..f4ed4b30a 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src/soc_ifc_status_monitor_bfm.sv
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src/soc_ifc_status_monitor_bfm.sv
@@ -145,13 +145,17 @@ end
   // pragma uvmf custom reset_condition end
   endtask
 
-  //******************************************************************
-
-  task wait_for_num_clocks(input int unsigned count); // pragma tbx xtf
+  // pragma uvmf custom wait_for_num_clocks begin
+  //****************************************************************************                         
+  // Inject pragmas's here to throw a warning on regeneration.
+  // Task must have automatic lifetime so that it can be concurrently invoked
+  // by multiple entities with a different wait value.
+  task automatic wait_for_num_clocks(input int unsigned count); // pragma tbx xtf
+    if (count == 0) `uvm_fatal("CFG", "wait_for_num_clocks called with count of 0 - this will lead to a hang");
     @(posedge clk_i);
-
     repeat (count-1) @(posedge clk_i);
   endtask
+  // pragma uvmf custom wait_for_num_clocks end                                                                
 
   //******************************************************************
   event go;
@@ -254,6 +258,7 @@ end
          soc_ifc_status_monitor_struct.trng_req_pending                   = trng_req_i;
          soc_ifc_status_monitor_struct.generic_output_val                 =  generic_output_wires_i;
     end
+
     // pragma uvmf custom do_monitor end
   endtask
 
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src/soc_ifc_status_transaction.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src/soc_ifc_status_transaction.svh
index 8ef5a775d..69bcd9df8 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src/soc_ifc_status_transaction.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src/soc_ifc_status_transaction.svh
@@ -123,7 +123,7 @@ class soc_ifc_status_transaction  extends uvmf_transaction_base;
   virtual function string convert2string();
     // pragma uvmf custom convert2string begin
     // UVMF_CHANGE_ME : Customize format if desired.
-    return $sformatf("ready_for_fuses:0x%x ready_for_fw_push:0x%x ready_for_runtime:0x%x mailbox_data_avail:0x%x mailbox_flow_done:0x%x cptra_error_fatal_intr_pending:0x%x cptra_error_non_fatal_intr_pending:0x%x trng_req_pending:0x%x generic_output_val:0x%x ",ready_for_fuses,ready_for_fw_push,ready_for_runtime,mailbox_data_avail,mailbox_flow_done,cptra_error_fatal_intr_pending,cptra_error_non_fatal_intr_pending,trng_req_pending,generic_output_val);
+    return $sformatf("ready_for_fuses:0x%x ready_for_fw_push:0x%x ready_for_runtime:0x%x mailbox_data_avail:0x%x mailbox_flow_done:0x%x cptra_error_fatal_intr_pending:0x%x cptra_error_non_fatal_intr_pending:0x%x trng_req_pending:0x%x generic_output_val:0x%x %s",ready_for_fuses,ready_for_fw_push,ready_for_runtime,mailbox_data_avail,mailbox_flow_done,cptra_error_fatal_intr_pending,cptra_error_non_fatal_intr_pending,trng_req_pending,generic_output_val,super.convert2string());
     // pragma uvmf custom convert2string end
   endfunction
 
diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src/soc_ifc_status_transaction_coverage.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src/soc_ifc_status_transaction_coverage.svh
index 3489d565a..bcb3e8445 100644
--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src/soc_ifc_status_transaction_coverage.svh
+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/interface_packages/soc_ifc_status_pkg/src/soc_ifc_status_transaction_coverage.svh
@@ -28,6 +28,11 @@
 //----------------------------------------------------------------------
 //----------------------------------------------------------------------
 //
+covergroup soc_ifc_status_transaction_bit_cg with function sample(input bit val);
+  option.per_instance = 1;
+  ea_bit: coverpoint val;
+endgroup
+
 class soc_ifc_status_transaction_coverage  extends uvm_subscriber #(.T(soc_ifc_status_transaction ));
 
   `uvm_component_utils( soc_ifc_status_transaction_coverage )
@@ -35,6 +40,7 @@ class soc_ifc_status_transaction_coverage  extends uvm_subscriber #(.T(soc_ifc_s
   T coverage_trans;
 
   // pragma uvmf custom class_item_additional begin
+  soc_ifc_status_transaction_bit_cg  generic_output_val_bit_cg[63:0]                          ;
   // pragma uvmf custom class_item_additional end
   
   // ****************************************************************************
@@ -51,7 +57,20 @@ class soc_ifc_status_transaction_coverage  extends uvm_subscriber #(.T(soc_ifc_s
     cptra_error_fatal_intr_pending: coverpoint coverage_trans.cptra_error_fatal_intr_pending;
     cptra_error_non_fatal_intr_pending: coverpoint coverage_trans.cptra_error_non_fatal_intr_pending;
     trng_req_pending: coverpoint coverage_trans.trng_req_pending;
-    generic_output_val: coverpoint coverage_trans.generic_output_val;
+    generic_output_val: coverpoint coverage_trans.generic_output_val {
+        bins byte_none = {64'h0000_0000_0000_0000};
+        bins byte_0    = {[0:$]} with ($countones(item[ 7: 0] > 0));
+        bins byte_1    = {[0:$]} with ($countones(item[15: 8] > 0));
+        bins byte_2    = {[0:$]} with ($countones(item[23:16] > 0));
+        bins byte_3    = {[0:$]} with ($countones(item[31:24] > 0));
+        bins byte_4    = {[0:$]} with ($countones(item[39:32] > 0));
+        bins byte_5    = {[0:$]} with ($countones(item[47:40] > 0));
+        bins byte_6    = {[0:$]} with ($countones(item[55:48] > 0));
+        bins byte_7    = {[0:$]} with ($countones(item[63:56] > 0));
+    }
+
+    cross_err : cross cptra_error_fatal_intr_pending, cptra_error_non_fatal_intr_pending;
+    cross_req : cross mailbox_data_avail, trng_req_pending;
     // pragma uvmf custom covergroup end
   endgroup
 
@@ -62,7 +81,7 @@ class soc_ifc_status_transaction_coverage  extends uvm_subscriber #(.T(soc_ifc_s
   function new(string name="", uvm_component parent=null);
     super.new(name,parent);
     soc_ifc_status_transaction_cg=new;
-    `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging.  Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup.  Remove this warning after the covergroup has been reviewed.")
+    foreach (coverage_trans.generic_output_val[bt]) generic_output_val_bit_cg[bt] = new;
   endfunction
 
   // ****************************************************************************
@@ -71,6 +90,7 @@ class soc_ifc_status_transaction_coverage  extends uvm_subscriber #(.T(soc_ifc_s
   //
   function void build_phase(uvm_phase phase);
     soc_ifc_status_transaction_cg.set_inst_name($sformatf("soc_ifc_status_transaction_cg_%s",get_full_name()));
+    foreach (coverage_trans.generic_output_val[bt]) generic_output_val_bit_cg[bt].set_inst_name($sformatf("generic_output_val_bit_cg_%d_%s", bt, get_full_name()));
   endfunction
 
   // ****************************************************************************
@@ -83,6 +103,7 @@ class soc_ifc_status_transaction_coverage  extends uvm_subscriber #(.T(soc_ifc_s
     `uvm_info("COV","Received transaction",UVM_HIGH);
     coverage_trans = t;
     soc_ifc_status_transaction_cg.sample();
+    foreach (coverage_trans.generic_output_val[bt]) generic_output_val_bit_cg[bt].sample(coverage_trans.generic_output_val[bt]);
   endfunction
 
 endclass
diff --git a/src/spi_host/config/compile.yml b/src/spi_host/config/compile.yml
index 5f7914b0e..f9ed579c7 100644
--- a/src/spi_host/config/compile.yml
+++ b/src/spi_host/config/compile.yml
@@ -3,7 +3,7 @@ provides: [spi_host]
 schema_version: 2.4.0
 requires:
   - libs
-  - prim
+  - caliptra_prim
 targets:
   rtl:
     directories: [$COMPILE_ROOT/rtl]
@@ -20,7 +20,39 @@ targets:
       - $COMPILE_ROOT/rtl/spi_host_reg_top.sv
       - $COMPILE_ROOT/rtl/spi_host_shift_register.sv
     tops: [spi_host]
+  tb:
+    directories: [$COMPILE_ROOT/rtl]
+    files:
+      - $COMPILE_ROOT/rtl/spi_host_reg_pkg.sv
+      - $COMPILE_ROOT/rtl/spi_host_cmd_pkg.sv
+---
+provides: [spiflash]
+schema_version: 2.4.0
+requires:
+  - spi_host
+targets:
+  tb:
+    directories: [$COMPILE_ROOT/tb]
+    files:
+      - $COMPILE_ROOT/tb/spi_device_pkg.sv
+      - $COMPILE_ROOT/tb/spiflash.sv
+    tops: [spiflash]
+---
+provides: [spi_host_tb]
+schema_version: 2.4.0
+requires:
+  - spi_host
+  - spiflash
+targets:
   tb:
     directories: [$COMPILE_ROOT/tb]
     files:
       - $COMPILE_ROOT/tb/spi_host_tb.sv
+    tops: [spi_host_tb]
+global:
+  tool:
+    vcs:
+      default:
+        - '-assert svaext'
+        - +define+CLP_ASSERT_ON
+        - '-noinherit_timescale=1ns/1ps'
diff --git a/src/spi_host/config/spi_host.vf b/src/spi_host/config/spi_host.vf
index 246a36c47..1b0661420 100644
--- a/src/spi_host/config/spi_host.vf
+++ b/src/spi_host/config/spi_host.vf
@@ -1,48 +1,68 @@
++incdir+${CALIPTRA_ROOT}/src/integration/rtl
 +incdir+${CALIPTRA_ROOT}/src/libs/rtl
-+incdir+${CALIPTRA_ROOT}/src/prim/rtl
++incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl
++incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl
++incdir+${CALIPTRA_ROOT}/src/spi_host/rtl
++incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl
+${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh
+${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sva.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_macros.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sram.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_defines_pkg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_ahb_srom.sv
+${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
-${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_util_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_alert_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_mubi_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_cipher_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_pkg.sv
-${CALIPTRA_ROOT}/src/prim_generic/rtl/prim_generic_buf.sv
-${CALIPTRA_ROOT}/src/prim_generic/rtl/prim_generic_flop.sv
-${CALIPTRA_ROOT}/src/prim_generic/rtl/prim_generic_flop_en.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_flop_en.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_flop_2sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_lfsr.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_mubi4_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_diff_decode.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sec_anchor_buf.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_slicer.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_count.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sparse_fsm_flop.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_dom_and_2share.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sec_anchor_flop.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_reg_we_check.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_packer_fifo.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_max_tree.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg_arb.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_intr_hw.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_onehot_check.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_mubi8_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_fifo_sync_cnt.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_buf.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_alert_receiver.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_flop.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_alert_sender.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_fifo_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_arbiter_ppc.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sum_tree.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg_ext.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_edge_detector.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv
+${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv
+${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv
+${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv
 ${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_cmd_pkg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_en.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cdc_rand_delay.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lfsr.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi4_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_diff_decode.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_slicer.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_count.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_dom_and_2share.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_reg_we_check.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_max_tree.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_arb.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_intr_hw.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_onehot_check.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi8_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync_cnt.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lc_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_receiver.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_sender.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv
 ${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host.sv
 ${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_byte_merge.sv
 ${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_byte_select.sv
@@ -52,7 +72,3 @@ ${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_data_fifos.sv
 ${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_fsm.sv
 ${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_reg_top.sv
 ${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_shift_register.sv
-${CALIPTRA_ROOT}/src/spi_host/tb/spi_device_pkg.sv
-${CALIPTRA_ROOT}/src/spi_host/tb/spiflash.sv
-${CALIPTRA_ROOT}/src/spi_host/tb/spi_host_tb.sv
-
diff --git a/src/spi_host/config/spi_host.vlt b/src/spi_host/config/spi_host.vlt
index 9f196f260..5e03da9c1 100644
--- a/src/spi_host/config/spi_host.vlt
+++ b/src/spi_host/config/spi_host.vlt
@@ -1,3 +1,6 @@
-${CALIPTRA_ROOT}/src/prim/lint/prim_max_tree.vlt
-${CALIPTRA_ROOT}/src/prim/lint/prim_sum_tree.vlt
-${CALIPTRA_ROOT}/src/prim/lint/prim_onehot_check.vlt
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+${CALIPTRA_ROOT}/src/caliptra_prim/lint/caliptra_prim_max_tree.vlt
+${CALIPTRA_ROOT}/src/caliptra_prim/lint/caliptra_prim_sum_tree.vlt
+${CALIPTRA_ROOT}/src/caliptra_prim/lint/caliptra_prim_onehot_check.vlt
diff --git a/src/spi_host/config/spi_host_tb.vf b/src/spi_host/config/spi_host_tb.vf
new file mode 100644
index 000000000..687e76aca
--- /dev/null
+++ b/src/spi_host/config/spi_host_tb.vf
@@ -0,0 +1,78 @@
++incdir+${CALIPTRA_ROOT}/src/integration/rtl
++incdir+${CALIPTRA_ROOT}/src/libs/rtl
++incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl
++incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl
++incdir+${CALIPTRA_ROOT}/src/spi_host/rtl
++incdir+${CALIPTRA_ROOT}/src/spi_host/tb
++incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl
+${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh
+${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sva.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_macros.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sram.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_defines_pkg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_ahb_srom.sv
+${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv
+${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv
+${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv
+${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_reg_pkg.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_cmd_pkg.sv
+${CALIPTRA_ROOT}/src/spi_host/tb/spi_device_pkg.sv
+${CALIPTRA_ROOT}/src/spi_host/tb/spiflash.sv
+${CALIPTRA_ROOT}/src/spi_host/tb/spi_host_tb.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_en.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cdc_rand_delay.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lfsr.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi4_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_diff_decode.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_slicer.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_count.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_dom_and_2share.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_reg_we_check.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_max_tree.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_arb.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_intr_hw.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_onehot_check.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi8_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync_cnt.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lc_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_receiver.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_sender.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_byte_merge.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_byte_select.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_command_queue.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_core.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_data_fifos.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_fsm.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_reg_top.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_shift_register.sv
\ No newline at end of file
diff --git a/src/spi_host/config/spiflash.vf b/src/spi_host/config/spiflash.vf
new file mode 100644
index 000000000..6821ad3d0
--- /dev/null
+++ b/src/spi_host/config/spiflash.vf
@@ -0,0 +1,77 @@
++incdir+${CALIPTRA_ROOT}/src/integration/rtl
++incdir+${CALIPTRA_ROOT}/src/libs/rtl
++incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl
++incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl
++incdir+${CALIPTRA_ROOT}/src/spi_host/rtl
++incdir+${CALIPTRA_ROOT}/src/spi_host/tb
++incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl
+${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh
+${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sva.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_macros.svh
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sram.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_defines_pkg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_ahb_srom.sv
+${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv
+${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv
+${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv
+${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_reg_pkg.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_cmd_pkg.sv
+${CALIPTRA_ROOT}/src/spi_host/tb/spi_device_pkg.sv
+${CALIPTRA_ROOT}/src/spi_host/tb/spiflash.sv
+${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_en.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cdc_rand_delay.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lfsr.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi4_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_diff_decode.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_slicer.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_count.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_dom_and_2share.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_reg_we_check.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_max_tree.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_arb.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_intr_hw.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_onehot_check.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi8_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync_cnt.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lc_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_receiver.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_sender.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_byte_merge.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_byte_select.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_command_queue.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_core.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_data_fifos.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_fsm.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_reg_top.sv
+${CALIPTRA_ROOT}/src/spi_host/rtl/spi_host_shift_register.sv
\ No newline at end of file
diff --git a/src/spi_host/rtl/spi_host.sv b/src/spi_host/rtl/spi_host.sv
index 6fc6fc796..efe85108b 100644
--- a/src/spi_host/rtl/spi_host.sv
+++ b/src/spi_host/rtl/spi_host.sv
@@ -6,7 +6,7 @@
 //
 //
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
 module spi_host
   import spi_host_reg_pkg::*;
@@ -32,8 +32,8 @@ module spi_host
   output logic [AHBDataWidth-1:0] hrdata_o,
 
   // Alerts
-  input  prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i,
-  output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o,
+  input  caliptra_prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i,
+  output caliptra_prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o,
 
   // SPI Interface
   output logic             cio_sck_o,
@@ -88,10 +88,10 @@ module spi_host
   };
 
   for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx
-    prim_alert_sender #(
+    caliptra_prim_alert_sender #(
       .AsyncOn(AlertAsyncOn[i]),
       .IsFatal(1'b1)
-    ) u_prim_alert_sender (
+    ) u_caliptra_prim_alert_sender (
       .clk_i,
       .rst_ni,
       .alert_test_i  (alert_test[i] ),
@@ -343,7 +343,7 @@ module spi_host
 
   // Note on ByteOrder and ByteSwapping.
   // ByteOrder == 1 is for Little-Endian transmission (i.e. LSB first), which is acheived by
-  // default with the prim_packer_fifo implementation.  Thus we have to swap if Big-Endian
+  // default with the caliptra_prim_packer_fifo implementation.  Thus we have to swap if Big-Endian
   // transmission is required (i.e. if ByteOrder == 0).
   spi_host_data_fifos #(
     .TxDepth(TxDepth),
@@ -476,7 +476,7 @@ module spi_host
   assign event_error   = |(error_vec & error_mask);
   assign enb_error     = |sw_error_status;
 
-  prim_intr_hw #(.Width(1)) intr_hw_error (
+  caliptra_prim_intr_hw #(.Width(1)) intr_hw_error (
     .clk_i,
     .rst_ni,
     .event_intr_i           (event_error),
@@ -548,7 +548,7 @@ module spi_host
     end
   end
 
-  prim_intr_hw #(.Width(1)) intr_hw_spi_event (
+  caliptra_prim_intr_hw #(.Width(1)) intr_hw_spi_event (
     .clk_i,
     .rst_ni,
     .event_intr_i           (event_spi_event),
diff --git a/src/spi_host/rtl/spi_host_byte_merge.sv b/src/spi_host/rtl/spi_host_byte_merge.sv
index faa425bdd..a4a8e17cb 100644
--- a/src/spi_host/rtl/spi_host_byte_merge.sv
+++ b/src/spi_host/rtl/spi_host_byte_merge.sv
@@ -47,7 +47,7 @@ module spi_host_byte_merge (
     end
   end
 
-  prim_packer_fifo #(
+  caliptra_prim_packer_fifo #(
     .InW(8),
     .OutW(32)
   ) u_packer (
diff --git a/src/spi_host/rtl/spi_host_byte_select.sv b/src/spi_host/rtl/spi_host_byte_select.sv
index 78f288ed0..775d45fae 100644
--- a/src/spi_host/rtl/spi_host_byte_select.sv
+++ b/src/spi_host/rtl/spi_host_byte_select.sv
@@ -34,7 +34,7 @@ module spi_host_byte_select (
     assign wdata_be[9*ii +: 9] = { word_be_i[ii], word_i[8*ii +: 8] };
   end : gen_map_data_be
 
-  prim_packer_fifo #(
+  caliptra_prim_packer_fifo #(
     .InW(36),
     .OutW(9)
   ) u_packer (
diff --git a/src/spi_host/rtl/spi_host_cmd_pkg.sv b/src/spi_host/rtl/spi_host_cmd_pkg.sv
index 45abc0223..e8c06d14d 100644
--- a/src/spi_host/rtl/spi_host_cmd_pkg.sv
+++ b/src/spi_host/rtl/spi_host_cmd_pkg.sv
@@ -7,7 +7,7 @@
 
 package spi_host_cmd_pkg;
 
-  parameter int CSW = prim_util_pkg::vbits(spi_host_reg_pkg::NumCS);
+  parameter int CSW = caliptra_prim_util_pkg::vbits(spi_host_reg_pkg::NumCS);
   parameter int CmdSize = CSW + 45;
 
   // For decoding the direction register
diff --git a/src/spi_host/rtl/spi_host_command_queue.sv b/src/spi_host/rtl/spi_host_command_queue.sv
index fbca9e490..66e438722 100644
--- a/src/spi_host/rtl/spi_host_command_queue.sv
+++ b/src/spi_host/rtl/spi_host_command_queue.sv
@@ -26,7 +26,7 @@ module spi_host_command_queue #(
   input                              sw_rst_i
 );
 
-  localparam int CmdDepthW = prim_util_pkg::vbits(CmdDepth+1);
+  localparam int CmdDepthW = caliptra_prim_util_pkg::vbits(CmdDepth+1);
 
   logic command_ready;
 
@@ -35,7 +35,7 @@ module spi_host_command_queue #(
 
   logic [CmdDepthW-1:0] cmd_depth;
 
-  prim_fifo_sync #(
+  caliptra_prim_fifo_sync #(
     .Width(spi_host_cmd_pkg::CmdSize),
     .Pass(1),
     .Depth(CmdDepth)
diff --git a/src/spi_host/rtl/spi_host_data_fifos.sv b/src/spi_host/rtl/spi_host_data_fifos.sv
index 0f1e36ee5..0fbadda37 100644
--- a/src/spi_host/rtl/spi_host_data_fifos.sv
+++ b/src/spi_host/rtl/spi_host_data_fifos.sv
@@ -45,8 +45,8 @@ module spi_host_data_fifos #(
   output logic        rx_wm_o
 );
 
-  localparam int RxDepthW = prim_util_pkg::vbits(RxDepth+1);
-  localparam int TxDepthW = prim_util_pkg::vbits(TxDepth+1);
+  localparam int RxDepthW = caliptra_prim_util_pkg::vbits(RxDepth+1);
+  localparam int TxDepthW = caliptra_prim_util_pkg::vbits(TxDepth+1);
 
   logic [31:0] tx_data_ordered;
   logic [3:0]  tx_be_ordered;
@@ -72,7 +72,7 @@ module spi_host_data_fifos #(
   assign tx_data_be = { tx_data_ordered, tx_be_ordered };
   assign { core_tx_data_o, core_tx_be_o } = core_tx_data_be;
 
-  prim_fifo_sync #(
+  caliptra_prim_fifo_sync #(
     .Width(36),
     .Pass(1),
     .Depth(TxDepth)
@@ -95,7 +95,7 @@ module spi_host_data_fifos #(
 
   assign rx_qd_o = 8'(rx_depth);
 
-  prim_fifo_sync #(
+  caliptra_prim_fifo_sync #(
     .Width(32),
     .Pass(1),
     .Depth(RxDepth)
diff --git a/src/spi_host/rtl/spi_host_fsm.sv b/src/spi_host/rtl/spi_host_fsm.sv
index 4f7996042..50f63c040 100644
--- a/src/spi_host/rtl/spi_host_fsm.sv
+++ b/src/spi_host/rtl/spi_host_fsm.sv
@@ -536,7 +536,7 @@ module spi_host_fsm
 
   assign sck_o = sck_q;
 
-  prim_flop_en u_sck_flop (
+  caliptra_prim_flop_en u_sck_flop (
     .clk_i,
     .rst_ni,
     .en_i(~stall),
diff --git a/src/spi_host/rtl/spi_host_reg_top.sv b/src/spi_host/rtl/spi_host_reg_top.sv
index 4774308ea..33f986b2f 100644
--- a/src/spi_host/rtl/spi_host_reg_top.sv
+++ b/src/spi_host/rtl/spi_host_reg_top.sv
@@ -4,7 +4,7 @@
 //
 // Register Top module auto-generated by `reggen`
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
 module spi_host_reg_top #(
     parameter AHBDataWidth = 64,
@@ -70,9 +70,9 @@ module spi_host_reg_top #(
   // also check for spurious write enables
   logic reg_we_err;
   logic [14:0] reg_we_check;
-  prim_reg_we_check #(
+  caliptra_prim_reg_we_check #(
     .OneHotWidth(15)
-  ) u_prim_reg_we_check (
+  ) u_caliptra_prim_reg_we_check (
     .clk_i(clk_i),
     .rst_ni(rst_ni),
     .oh_i  (reg_we_check),
@@ -275,9 +275,9 @@ module spi_host_reg_top #(
   // Register instances
   // R[intr_state]: V(False)
   //   F[error]: 0:0
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW1C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_intr_state_error (
     .clk_i   (clk_i),
@@ -301,9 +301,9 @@ module spi_host_reg_top #(
   );
 
   //   F[spi_event]: 1:1
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW1C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_intr_state_spi_event (
     .clk_i   (clk_i),
@@ -329,9 +329,9 @@ module spi_host_reg_top #(
 
   // R[intr_enable]: V(False)
   //   F[error]: 0:0
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_intr_enable_error (
     .clk_i   (clk_i),
@@ -355,9 +355,9 @@ module spi_host_reg_top #(
   );
 
   //   F[spi_event]: 1:1
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_intr_enable_spi_event (
     .clk_i   (clk_i),
@@ -386,7 +386,7 @@ module spi_host_reg_top #(
   logic [1:0] intr_test_flds_we;
   assign intr_test_qe = &intr_test_flds_we;
   //   F[error]: 0:0
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (1)
   ) u_intr_test_error (
     .re     (1'b0),
@@ -402,7 +402,7 @@ module spi_host_reg_top #(
   assign reg2hw.intr_test.error.qe = intr_test_qe;
 
   //   F[spi_event]: 1:1
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (1)
   ) u_intr_test_spi_event (
     .re     (1'b0),
@@ -422,7 +422,7 @@ module spi_host_reg_top #(
   logic alert_test_qe;
   logic [0:0] alert_test_flds_we;
   assign alert_test_qe = &alert_test_flds_we;
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (1)
   ) u_alert_test (
     .re     (1'b0),
@@ -440,9 +440,9 @@ module spi_host_reg_top #(
 
   // R[control]: V(False)
   //   F[rx_watermark]: 7:0
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (8),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (8'h7f)
   ) u_control_rx_watermark (
     .clk_i   (clk_i),
@@ -466,9 +466,9 @@ module spi_host_reg_top #(
   );
 
   //   F[tx_watermark]: 15:8
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (8),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (8'h0)
   ) u_control_tx_watermark (
     .clk_i   (clk_i),
@@ -492,9 +492,9 @@ module spi_host_reg_top #(
   );
 
   //   F[output_en]: 29:29
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_control_output_en (
     .clk_i   (clk_i),
@@ -518,9 +518,9 @@ module spi_host_reg_top #(
   );
 
   //   F[sw_rst]: 30:30
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_control_sw_rst (
     .clk_i   (clk_i),
@@ -544,9 +544,9 @@ module spi_host_reg_top #(
   );
 
   //   F[spien]: 31:31
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_control_spien (
     .clk_i   (clk_i),
@@ -572,9 +572,9 @@ module spi_host_reg_top #(
 
   // R[status]: V(False)
   //   F[txqd]: 7:0
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (8),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (8'h0)
   ) u_status_txqd (
     .clk_i   (clk_i),
@@ -598,9 +598,9 @@ module spi_host_reg_top #(
   );
 
   //   F[rxqd]: 15:8
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (8),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (8'h0)
   ) u_status_rxqd (
     .clk_i   (clk_i),
@@ -624,9 +624,9 @@ module spi_host_reg_top #(
   );
 
   //   F[cmdqd]: 19:16
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (4),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (4'h0)
   ) u_status_cmdqd (
     .clk_i   (clk_i),
@@ -650,9 +650,9 @@ module spi_host_reg_top #(
   );
 
   //   F[rxwm]: 20:20
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_status_rxwm (
     .clk_i   (clk_i),
@@ -676,9 +676,9 @@ module spi_host_reg_top #(
   );
 
   //   F[byteorder]: 22:22
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_status_byteorder (
     .clk_i   (clk_i),
@@ -702,9 +702,9 @@ module spi_host_reg_top #(
   );
 
   //   F[rxstall]: 23:23
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_status_rxstall (
     .clk_i   (clk_i),
@@ -728,9 +728,9 @@ module spi_host_reg_top #(
   );
 
   //   F[rxempty]: 24:24
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_status_rxempty (
     .clk_i   (clk_i),
@@ -754,9 +754,9 @@ module spi_host_reg_top #(
   );
 
   //   F[rxfull]: 25:25
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_status_rxfull (
     .clk_i   (clk_i),
@@ -780,9 +780,9 @@ module spi_host_reg_top #(
   );
 
   //   F[txwm]: 26:26
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_status_txwm (
     .clk_i   (clk_i),
@@ -806,9 +806,9 @@ module spi_host_reg_top #(
   );
 
   //   F[txstall]: 27:27
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_status_txstall (
     .clk_i   (clk_i),
@@ -832,9 +832,9 @@ module spi_host_reg_top #(
   );
 
   //   F[txempty]: 28:28
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_status_txempty (
     .clk_i   (clk_i),
@@ -858,9 +858,9 @@ module spi_host_reg_top #(
   );
 
   //   F[txfull]: 29:29
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_status_txfull (
     .clk_i   (clk_i),
@@ -884,9 +884,9 @@ module spi_host_reg_top #(
   );
 
   //   F[active]: 30:30
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_status_active (
     .clk_i   (clk_i),
@@ -910,9 +910,9 @@ module spi_host_reg_top #(
   );
 
   //   F[ready]: 31:31
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_status_ready (
     .clk_i   (clk_i),
@@ -939,9 +939,9 @@ module spi_host_reg_top #(
   // Subregister 0 of Multireg configopts
   // R[configopts_0]: V(False)
   //   F[clkdiv_0]: 15:0
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (16),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (16'h0)
   ) u_configopts_0_clkdiv_0 (
     .clk_i   (clk_i),
@@ -965,9 +965,9 @@ module spi_host_reg_top #(
   );
 
   //   F[csnidle_0]: 19:16
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (4),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (4'h0)
   ) u_configopts_0_csnidle_0 (
     .clk_i   (clk_i),
@@ -991,9 +991,9 @@ module spi_host_reg_top #(
   );
 
   //   F[csntrail_0]: 23:20
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (4),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (4'h0)
   ) u_configopts_0_csntrail_0 (
     .clk_i   (clk_i),
@@ -1017,9 +1017,9 @@ module spi_host_reg_top #(
   );
 
   //   F[csnlead_0]: 27:24
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (4),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (4'h0)
   ) u_configopts_0_csnlead_0 (
     .clk_i   (clk_i),
@@ -1043,9 +1043,9 @@ module spi_host_reg_top #(
   );
 
   //   F[fullcyc_0]: 29:29
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_configopts_0_fullcyc_0 (
     .clk_i   (clk_i),
@@ -1069,9 +1069,9 @@ module spi_host_reg_top #(
   );
 
   //   F[cpha_0]: 30:30
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_configopts_0_cpha_0 (
     .clk_i   (clk_i),
@@ -1095,9 +1095,9 @@ module spi_host_reg_top #(
   );
 
   //   F[cpol_0]: 31:31
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_configopts_0_cpol_0 (
     .clk_i   (clk_i),
@@ -1124,9 +1124,9 @@ module spi_host_reg_top #(
   // Subregister 1 of Multireg configopts
   // R[configopts_1]: V(False)
   //   F[clkdiv_1]: 15:0
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (16),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (16'h0)
   ) u_configopts_1_clkdiv_1 (
     .clk_i   (clk_i),
@@ -1150,9 +1150,9 @@ module spi_host_reg_top #(
   );
 
   //   F[csnidle_1]: 19:16
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (4),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (4'h0)
   ) u_configopts_1_csnidle_1 (
     .clk_i   (clk_i),
@@ -1176,9 +1176,9 @@ module spi_host_reg_top #(
   );
 
   //   F[csntrail_1]: 23:20
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (4),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (4'h0)
   ) u_configopts_1_csntrail_1 (
     .clk_i   (clk_i),
@@ -1202,9 +1202,9 @@ module spi_host_reg_top #(
   );
 
   //   F[csnlead_1]: 27:24
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (4),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (4'h0)
   ) u_configopts_1_csnlead_1 (
     .clk_i   (clk_i),
@@ -1228,9 +1228,9 @@ module spi_host_reg_top #(
   );
 
   //   F[fullcyc_1]: 29:29
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_configopts_1_fullcyc_1 (
     .clk_i   (clk_i),
@@ -1254,9 +1254,9 @@ module spi_host_reg_top #(
   );
 
   //   F[cpha_1]: 30:30
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_configopts_1_cpha_1 (
     .clk_i   (clk_i),
@@ -1280,9 +1280,9 @@ module spi_host_reg_top #(
   );
 
   //   F[cpol_1]: 31:31
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_configopts_1_cpol_1 (
     .clk_i   (clk_i),
@@ -1307,9 +1307,9 @@ module spi_host_reg_top #(
 
 
   // R[csid]: V(False)
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (32),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (32'h0)
   ) u_csid (
     .clk_i   (clk_i),
@@ -1338,7 +1338,7 @@ module spi_host_reg_top #(
   logic [3:0] command_flds_we;
   assign command_qe = &command_flds_we;
   //   F[len]: 8:0
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (9)
   ) u_command_len (
     .re     (1'b0),
@@ -1354,7 +1354,7 @@ module spi_host_reg_top #(
   assign reg2hw.command.len.qe = command_qe;
 
   //   F[csaat]: 9:9
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (1)
   ) u_command_csaat (
     .re     (1'b0),
@@ -1370,7 +1370,7 @@ module spi_host_reg_top #(
   assign reg2hw.command.csaat.qe = command_qe;
 
   //   F[speed]: 11:10
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (2)
   ) u_command_speed (
     .re     (1'b0),
@@ -1386,7 +1386,7 @@ module spi_host_reg_top #(
   assign reg2hw.command.speed.qe = command_qe;
 
   //   F[direction]: 13:12
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (2)
   ) u_command_direction (
     .re     (1'b0),
@@ -1403,9 +1403,9 @@ module spi_host_reg_top #(
 
 
   // R[rxdata]: V(False)
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (32),
-    .SwAccess(prim_subreg_pkg::SwAccessRO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO),
     .RESVAL  (32'h0)
   ) u_rxdata (
     .clk_i   (clk_i),
@@ -1433,7 +1433,7 @@ module spi_host_reg_top #(
   logic txdata_qe;
   logic [0:0] txdata_flds_we;
   assign txdata_qe = &txdata_flds_we;
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (32)
   ) u_txdata (
     .re     (1'b0),
@@ -1451,9 +1451,9 @@ module spi_host_reg_top #(
 
   // R[error_enable]: V(False)
   //   F[cmdbusy]: 0:0
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h1)
   ) u_error_enable_cmdbusy (
     .clk_i   (clk_i),
@@ -1477,9 +1477,9 @@ module spi_host_reg_top #(
   );
 
   //   F[overflow]: 1:1
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h1)
   ) u_error_enable_overflow (
     .clk_i   (clk_i),
@@ -1503,9 +1503,9 @@ module spi_host_reg_top #(
   );
 
   //   F[underflow]: 2:2
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h1)
   ) u_error_enable_underflow (
     .clk_i   (clk_i),
@@ -1529,9 +1529,9 @@ module spi_host_reg_top #(
   );
 
   //   F[cmdinval]: 3:3
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h1)
   ) u_error_enable_cmdinval (
     .clk_i   (clk_i),
@@ -1555,9 +1555,9 @@ module spi_host_reg_top #(
   );
 
   //   F[csidinval]: 4:4
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h1)
   ) u_error_enable_csidinval (
     .clk_i   (clk_i),
@@ -1583,9 +1583,9 @@ module spi_host_reg_top #(
 
   // R[error_status]: V(False)
   //   F[cmdbusy]: 0:0
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW1C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_error_status_cmdbusy (
     .clk_i   (clk_i),
@@ -1609,9 +1609,9 @@ module spi_host_reg_top #(
   );
 
   //   F[overflow]: 1:1
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW1C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_error_status_overflow (
     .clk_i   (clk_i),
@@ -1635,9 +1635,9 @@ module spi_host_reg_top #(
   );
 
   //   F[underflow]: 2:2
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW1C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_error_status_underflow (
     .clk_i   (clk_i),
@@ -1661,9 +1661,9 @@ module spi_host_reg_top #(
   );
 
   //   F[cmdinval]: 3:3
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW1C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_error_status_cmdinval (
     .clk_i   (clk_i),
@@ -1687,9 +1687,9 @@ module spi_host_reg_top #(
   );
 
   //   F[csidinval]: 4:4
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW1C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_error_status_csidinval (
     .clk_i   (clk_i),
@@ -1713,9 +1713,9 @@ module spi_host_reg_top #(
   );
 
   //   F[accessinval]: 5:5
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW1C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_error_status_accessinval (
     .clk_i   (clk_i),
@@ -1741,9 +1741,9 @@ module spi_host_reg_top #(
 
   // R[event_enable]: V(False)
   //   F[rxfull]: 0:0
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_event_enable_rxfull (
     .clk_i   (clk_i),
@@ -1767,9 +1767,9 @@ module spi_host_reg_top #(
   );
 
   //   F[txempty]: 1:1
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_event_enable_txempty (
     .clk_i   (clk_i),
@@ -1793,9 +1793,9 @@ module spi_host_reg_top #(
   );
 
   //   F[rxwm]: 2:2
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_event_enable_rxwm (
     .clk_i   (clk_i),
@@ -1819,9 +1819,9 @@ module spi_host_reg_top #(
   );
 
   //   F[txwm]: 3:3
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_event_enable_txwm (
     .clk_i   (clk_i),
@@ -1845,9 +1845,9 @@ module spi_host_reg_top #(
   );
 
   //   F[ready]: 4:4
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_event_enable_ready (
     .clk_i   (clk_i),
@@ -1871,9 +1871,9 @@ module spi_host_reg_top #(
   );
 
   //   F[idle]: 5:5
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_event_enable_idle (
     .clk_i   (clk_i),
diff --git a/src/spi_host/tb/Makefile b/src/spi_host/tb/Makefile
index e65bb88cb..cbec3d6b4 100644
--- a/src/spi_host/tb/Makefile
+++ b/src/spi_host/tb/Makefile
@@ -1,3 +1,18 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
 VERILATOR = verilator
 
 IPNAME = spi_host
diff --git a/src/spi_host/tb/spi_host_tb.sv b/src/spi_host/tb/spi_host_tb.sv
index 677285648..766a748dc 100644
--- a/src/spi_host/tb/spi_host_tb.sv
+++ b/src/spi_host/tb/spi_host_tb.sv
@@ -24,7 +24,7 @@
 module spi_host_tb
   import spi_host_reg_pkg::*;
   import spi_device_pkg::*;
-  import prim_mubi_pkg::mubi8_t;
+  import caliptra_prim_mubi_pkg::mubi8_t;
 (
 `ifdef VERILATOR
   input bit clk_tb
@@ -140,7 +140,7 @@ module spi_host_tb
     .hrdata_o    (hrdata_o_tb),
 
     // Alerts
-    .alert_rx_i(prim_alert_pkg::ALERT_RX_DEFAULT),
+    .alert_rx_i(caliptra_prim_alert_pkg::ALERT_RX_DEFAULT),
     .alert_tx_o(),
 
     // SPI Interface
@@ -195,7 +195,7 @@ module spi_host_tb
   // the dut as needed.
   //----------------------------------------------------------------
   always_ff @(posedge clk_tb) begin : sys_monitor
-      cycle_ctr = cycle_ctr + 1;
+      cycle_ctr = (~reset_n_tb) ? 0 : cycle_ctr + 1;
     end
 
 
@@ -228,7 +228,6 @@ module spi_host_tb
   task init_sim;
     begin
       generate_rng = '0;
-      cycle_ctr    = '0;
       error_ctr    = '0;
       tc_ctr       = '0;
 `ifndef VERILATOR
@@ -492,9 +491,9 @@ module spi_host_tb
   // Configures the spi_host to request data from the spi flash
   // The spiflash device will return data at the requested addresses
   //----------------------------------------------------------------
-  task run_read_test(input int host);
+  task automatic run_read_test(input int host);
     logic [31:0] rx_data;
-    logic [7:0]  rx_bytes[$] = {};
+    automatic logic [7:0]  rx_bytes[$] = {};
     spi_host_status_t status;
     logic [7:0]  spi_data;
     logic [19:0] spi_offset;
diff --git a/src/uart/config/compile.yml b/src/uart/config/compile.yml
index 7a7dd3f5e..b4836131d 100644
--- a/src/uart/config/compile.yml
+++ b/src/uart/config/compile.yml
@@ -2,8 +2,8 @@
 provides: [uart]
 schema_version: 2.4.0
 requires:
-  - prim_generic
-  - prim
+  - caliptra_prim_generic
+  - caliptra_prim
   - libs
 targets:
   rtl:
diff --git a/src/uart/config/uart.vf b/src/uart/config/uart.vf
index 5f5cfae6b..469205a79 100644
--- a/src/uart/config/uart.vf
+++ b/src/uart/config/uart.vf
@@ -1,9 +1,9 @@
 +incdir+${CALIPTRA_ROOT}/src/integration/rtl
 +incdir+${CALIPTRA_ROOT}/src/libs/rtl
-+incdir+${CALIPTRA_ROOT}/src/prim/rtl
++incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl
 +incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl
 +incdir+${CALIPTRA_ROOT}/src/uart/rtl
-+incdir+${CALIPTRA_ROOT}/src/prim_generic/rtl
++incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl
 ${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh
 ${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh
 ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sva.svh
@@ -15,47 +15,53 @@ ${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_util_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_alert_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_mubi_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_cipher_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_pkg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv
 ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv
 ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv
-${CALIPTRA_ROOT}/src/prim_generic/rtl/prim_generic_flop.sv
-${CALIPTRA_ROOT}/src/prim_generic/rtl/prim_generic_buf.sv
+${CALIPTRA_ROOT}/src/uart/rtl/uart_reg_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_flop_2sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_lfsr.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_mubi4_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_diff_decode.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sec_anchor_buf.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_slicer.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_count.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sparse_fsm_flop.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_dom_and_2share.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sec_anchor_flop.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_reg_we_check.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_packer_fifo.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_max_tree.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg_arb.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_intr_hw.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_onehot_check.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_mubi8_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_fifo_sync_cnt.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_buf.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_lc_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_alert_receiver.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_flop.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_alert_sender.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_fifo_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_arbiter_ppc.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sum_tree.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg_ext.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_edge_detector.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_en.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cdc_rand_delay.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lfsr.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi4_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_diff_decode.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_slicer.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_count.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_dom_and_2share.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_reg_we_check.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_max_tree.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_arb.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_intr_hw.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_onehot_check.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi8_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync_cnt.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lc_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_receiver.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_sender.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv
 ${CALIPTRA_ROOT}/src/uart/rtl/uart_tx.sv
 ${CALIPTRA_ROOT}/src/uart/rtl/uart_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/uart/rtl/uart_reg_top.sv
diff --git a/src/uart/config/uart.vlt b/src/uart/config/uart.vlt
index 21794084e..5e03da9c1 100644
--- a/src/uart/config/uart.vlt
+++ b/src/uart/config/uart.vlt
@@ -1,6 +1,6 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
-${CALIPTRA_ROOT}/src/prim/lint/prim_max_tree.vlt
-${CALIPTRA_ROOT}/src/prim/lint/prim_sum_tree.vlt
-${CALIPTRA_ROOT}/src/prim/lint/prim_onehot_check.vlt
+${CALIPTRA_ROOT}/src/caliptra_prim/lint/caliptra_prim_max_tree.vlt
+${CALIPTRA_ROOT}/src/caliptra_prim/lint/caliptra_prim_sum_tree.vlt
+${CALIPTRA_ROOT}/src/caliptra_prim/lint/caliptra_prim_onehot_check.vlt
diff --git a/src/uart/config/uart_tb.vf b/src/uart/config/uart_tb.vf
index c0cf4c1cc..4332da0e6 100644
--- a/src/uart/config/uart_tb.vf
+++ b/src/uart/config/uart_tb.vf
@@ -1,10 +1,10 @@
 +incdir+${CALIPTRA_ROOT}/src/integration/rtl
 +incdir+${CALIPTRA_ROOT}/src/libs/rtl
-+incdir+${CALIPTRA_ROOT}/src/prim/rtl
++incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl
 +incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl
 +incdir+${CALIPTRA_ROOT}/src/uart/rtl
 +incdir+${CALIPTRA_ROOT}/src/uart/tb
-+incdir+${CALIPTRA_ROOT}/src/prim_generic/rtl
++incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl
 ${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh
 ${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh
 ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_sva.svh
@@ -16,51 +16,56 @@ ${CALIPTRA_ROOT}/src/libs/rtl/apb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/caliptra_icg.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/clk_gate.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_util_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_alert_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_mubi_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_cipher_pkg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_pkg.sv
+${CALIPTRA_ROOT}/src/libs/rtl/caliptra_2ff_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cipher_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_pkg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_pkg.sv
 ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_state_pkg.sv
 ${CALIPTRA_ROOT}/src/lc_ctrl/rtl/lc_ctrl_pkg.sv
 ${CALIPTRA_ROOT}/src/uart/rtl/uart_reg_pkg.sv
 ${CALIPTRA_ROOT}/src/uart/tb/uart_tb.sv
-${CALIPTRA_ROOT}/src/prim_generic/rtl/prim_generic_flop.sv
-${CALIPTRA_ROOT}/src/prim_generic/rtl/prim_generic_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_buf.sv
 ${CALIPTRA_ROOT}/src/libs/rtl/ahb_to_reg_adapter.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_flop_2sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_lfsr.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_mubi4_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_diff_decode.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sec_anchor_buf.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_slicer.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_count.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sparse_fsm_flop.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_dom_and_2share.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sec_anchor_flop.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_reg_we_check.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_packer_fifo.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_max_tree.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg_arb.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_intr_hw.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_onehot_check.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_mubi8_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_fifo_sync_cnt.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_buf.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_lc_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_alert_receiver.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_flop.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_alert_sender.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_fifo_sync.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_arbiter_ppc.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_sum_tree.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_subreg_ext.sv
-${CALIPTRA_ROOT}/src/prim/rtl/prim_edge_detector.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_en.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_cdc_rand_delay.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lfsr.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi4_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_diff_decode.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_slicer.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_count.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sparse_fsm_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_dom_and_2share.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sec_anchor_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_reg_we_check.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_max_tree.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_arb.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_intr_hw.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_onehot_check.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_mubi8_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync_cnt.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_buf.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_lc_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_receiver.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_flop.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_sender.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_fifo_sync.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv
+${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv
 ${CALIPTRA_ROOT}/src/uart/rtl/uart_tx.sv
 ${CALIPTRA_ROOT}/src/uart/rtl/uart_reg_top.sv
 ${CALIPTRA_ROOT}/src/uart/rtl/uart_rx.sv
 ${CALIPTRA_ROOT}/src/uart/rtl/uart.sv
-${CALIPTRA_ROOT}/src/uart/rtl/uart_core.sv
\ No newline at end of file
+${CALIPTRA_ROOT}/src/uart/rtl/uart_core.sv
diff --git a/src/uart/doc/_index.md b/src/uart/doc/_index.md
index f59e7c3c7..f9e152306 100644
--- a/src/uart/doc/_index.md
+++ b/src/uart/doc/_index.md
@@ -1,3 +1,18 @@
+_*SPDX-License-Identifier: Apache-2.0<BR>
+<BR>
+<BR>
+Licensed under the Apache License, Version 2.0 (the "License");<BR>
+you may not use this file except in compliance with the License.<BR>
+You may obtain a copy of the License at<BR>
+<BR>
+http://www.apache.org/licenses/LICENSE-2.0 <BR>
+<BR>
+Unless required by applicable law or agreed to in writing, software<BR>
+distributed under the License is distributed on an "AS IS" BASIS,<BR>
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.<BR>
+See the License for the specific language governing permissions and<BR>
+limitations under the License.*_<BR>
+
 ---
 title: "UART HWIP Technical Specification"
 ---
diff --git a/src/uart/doc/checklist.md b/src/uart/doc/checklist.md
index d6d67aa94..3a7b4abad 100644
--- a/src/uart/doc/checklist.md
+++ b/src/uart/doc/checklist.md
@@ -1,3 +1,18 @@
+_*SPDX-License-Identifier: Apache-2.0<BR>
+<BR>
+<BR>
+Licensed under the Apache License, Version 2.0 (the "License");<BR>
+you may not use this file except in compliance with the License.<BR>
+You may obtain a copy of the License at<BR>
+<BR>
+http://www.apache.org/licenses/LICENSE-2.0 <BR>
+<BR>
+Unless required by applicable law or agreed to in writing, software<BR>
+distributed under the License is distributed on an "AS IS" BASIS,<BR>
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.<BR>
+See the License for the specific language governing permissions and<BR>
+limitations under the License.*_<BR>
+
 ---
 title: "UART Checklist"
 ---
diff --git a/src/uart/doc/dv/index.md b/src/uart/doc/dv/index.md
index e9f9d1b48..9fa501640 100644
--- a/src/uart/doc/dv/index.md
+++ b/src/uart/doc/dv/index.md
@@ -1,3 +1,18 @@
+_*SPDX-License-Identifier: Apache-2.0<BR>
+<BR>
+<BR>
+Licensed under the Apache License, Version 2.0 (the "License");<BR>
+you may not use this file except in compliance with the License.<BR>
+You may obtain a copy of the License at<BR>
+<BR>
+http://www.apache.org/licenses/LICENSE-2.0 <BR>
+<BR>
+Unless required by applicable law or agreed to in writing, software<BR>
+distributed under the License is distributed on an "AS IS" BASIS,<BR>
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.<BR>
+See the License for the specific language governing permissions and<BR>
+limitations under the License.*_<BR>
+
 ---
 title: "UART DV document"
 ---
diff --git a/src/uart/rtl/uart.sv b/src/uart/rtl/uart.sv
index 002f016b0..c5d8806f3 100644
--- a/src/uart/rtl/uart.sv
+++ b/src/uart/rtl/uart.sv
@@ -4,7 +4,7 @@
 //
 // Description: UART top level wrapper file
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
 module uart
     import uart_reg_pkg::*;
@@ -30,8 +30,8 @@ module uart
   output logic [AHBDataWidth-1:0] hrdata_o,
 
   // Alerts
-  input  prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i,
-  output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o,
+  input  caliptra_prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i,
+  output caliptra_prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o,
 
   // Generic IO
   input           cio_rx_i,
@@ -102,10 +102,10 @@ module uart
   };
 
   for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx
-    prim_alert_sender #(
+    caliptra_prim_alert_sender #(
       .AsyncOn(AlertAsyncOn[i]),
       .IsFatal(1'b1)
-    ) u_prim_alert_sender (
+    ) u_caliptra_prim_alert_sender (
       .clk_i,
       .rst_ni,
       .alert_test_i  ( alert_test[i] ),
diff --git a/src/uart/rtl/uart_core.sv b/src/uart/rtl/uart_core.sv
index c0f775fd2..aed925c70 100644
--- a/src/uart/rtl/uart_core.sv
+++ b/src/uart/rtl/uart_core.sv
@@ -169,7 +169,7 @@ module uart_core (
 
   assign tx_fifo_rready = tx_uart_idle & tx_fifo_rvalid & tx_enable;
 
-  prim_fifo_sync #(
+  caliptra_prim_fifo_sync #(
     .Width   (8),
     .Pass    (1'b0),
     .Depth   (32)
@@ -219,7 +219,7 @@ module uart_core (
   //////////////
 
   //      sync the incoming data
-  prim_flop_2sync #(
+  caliptra_prim_flop_2sync #(
     .Width(1),
     .ResetValue(1'b1)
   ) sync_rx (
@@ -270,7 +270,7 @@ module uart_core (
 
   assign rx_fifo_wvalid = rx_valid & ~event_rx_frame_err & ~event_rx_parity_err;
 
-  prim_fifo_sync #(
+  caliptra_prim_fifo_sync #(
     .Width   (8),
     .Pass    (1'b0),
     .Depth   (32)
@@ -387,7 +387,7 @@ module uart_core (
 
   // instantiate interrupt hardware primitives
 
-  prim_intr_hw #(.Width(1)) intr_hw_tx_watermark (
+  caliptra_prim_intr_hw #(.Width(1)) intr_hw_tx_watermark (
     .clk_i,
     .rst_ni,
     .event_intr_i           (event_tx_watermark),
@@ -400,7 +400,7 @@ module uart_core (
     .intr_o                 (intr_tx_watermark_o)
   );
 
-  prim_intr_hw #(.Width(1)) intr_hw_rx_watermark (
+  caliptra_prim_intr_hw #(.Width(1)) intr_hw_rx_watermark (
     .clk_i,
     .rst_ni,
     .event_intr_i           (event_rx_watermark),
@@ -413,7 +413,7 @@ module uart_core (
     .intr_o                 (intr_rx_watermark_o)
   );
 
-  prim_intr_hw #(.Width(1)) intr_hw_tx_empty (
+  caliptra_prim_intr_hw #(.Width(1)) intr_hw_tx_empty (
     .clk_i,
     .rst_ni,
     .event_intr_i           (event_tx_empty),
@@ -426,7 +426,7 @@ module uart_core (
     .intr_o                 (intr_tx_empty_o)
   );
 
-  prim_intr_hw #(.Width(1)) intr_hw_rx_overflow (
+  caliptra_prim_intr_hw #(.Width(1)) intr_hw_rx_overflow (
     .clk_i,
     .rst_ni,
     .event_intr_i           (event_rx_overflow),
@@ -439,7 +439,7 @@ module uart_core (
     .intr_o                 (intr_rx_overflow_o)
   );
 
-  prim_intr_hw #(.Width(1)) intr_hw_rx_frame_err (
+  caliptra_prim_intr_hw #(.Width(1)) intr_hw_rx_frame_err (
     .clk_i,
     .rst_ni,
     .event_intr_i           (event_rx_frame_err),
@@ -452,7 +452,7 @@ module uart_core (
     .intr_o                 (intr_rx_frame_err_o)
   );
 
-  prim_intr_hw #(.Width(1)) intr_hw_rx_break_err (
+  caliptra_prim_intr_hw #(.Width(1)) intr_hw_rx_break_err (
     .clk_i,
     .rst_ni,
     .event_intr_i           (event_rx_break_err),
@@ -465,7 +465,7 @@ module uart_core (
     .intr_o                 (intr_rx_break_err_o)
   );
 
-  prim_intr_hw #(.Width(1)) intr_hw_rx_timeout (
+  caliptra_prim_intr_hw #(.Width(1)) intr_hw_rx_timeout (
     .clk_i,
     .rst_ni,
     .event_intr_i           (event_rx_timeout),
@@ -478,7 +478,7 @@ module uart_core (
     .intr_o                 (intr_rx_timeout_o)
   );
 
-  prim_intr_hw #(.Width(1)) intr_hw_rx_parity_err (
+  caliptra_prim_intr_hw #(.Width(1)) intr_hw_rx_parity_err (
     .clk_i,
     .rst_ni,
     .event_intr_i           (event_rx_parity_err),
diff --git a/src/uart/rtl/uart_reg_top.sv b/src/uart/rtl/uart_reg_top.sv
index 66a61359a..b66a9efef 100644
--- a/src/uart/rtl/uart_reg_top.sv
+++ b/src/uart/rtl/uart_reg_top.sv
@@ -4,7 +4,7 @@
 //
 // Register Top module auto-generated by `reggen`
 
-`include "prim_assert.sv"
+`include "caliptra_prim_assert.sv"
 
 module uart_reg_top #(
     parameter AHBDataWidth = 64,
@@ -67,9 +67,9 @@ module uart_reg_top #(
   // also check for spurious write enables
   logic reg_we_err;
   logic [12:0] reg_we_check;
-  prim_reg_we_check #(
+  caliptra_prim_reg_we_check #(
     .OneHotWidth(13)
-  ) u_prim_reg_we_check (
+  ) u_caliptra_prim_reg_we_check (
     .clk_i(clk_i),
     .rst_ni(rst_ni),
     .oh_i  (reg_we_check),
@@ -250,9 +250,9 @@ module uart_reg_top #(
   // Register instances
   // R[intr_state]: V(False)
   //   F[tx_watermark]: 0:0
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW1C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_intr_state_tx_watermark (
     .clk_i   (clk_i),
@@ -276,9 +276,9 @@ module uart_reg_top #(
   );
 
   //   F[rx_watermark]: 1:1
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW1C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_intr_state_rx_watermark (
     .clk_i   (clk_i),
@@ -302,9 +302,9 @@ module uart_reg_top #(
   );
 
   //   F[tx_empty]: 2:2
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW1C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_intr_state_tx_empty (
     .clk_i   (clk_i),
@@ -328,9 +328,9 @@ module uart_reg_top #(
   );
 
   //   F[rx_overflow]: 3:3
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW1C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_intr_state_rx_overflow (
     .clk_i   (clk_i),
@@ -354,9 +354,9 @@ module uart_reg_top #(
   );
 
   //   F[rx_frame_err]: 4:4
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW1C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_intr_state_rx_frame_err (
     .clk_i   (clk_i),
@@ -380,9 +380,9 @@ module uart_reg_top #(
   );
 
   //   F[rx_break_err]: 5:5
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW1C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_intr_state_rx_break_err (
     .clk_i   (clk_i),
@@ -406,9 +406,9 @@ module uart_reg_top #(
   );
 
   //   F[rx_timeout]: 6:6
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW1C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_intr_state_rx_timeout (
     .clk_i   (clk_i),
@@ -432,9 +432,9 @@ module uart_reg_top #(
   );
 
   //   F[rx_parity_err]: 7:7
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessW1C),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_intr_state_rx_parity_err (
     .clk_i   (clk_i),
@@ -460,9 +460,9 @@ module uart_reg_top #(
 
   // R[intr_enable]: V(False)
   //   F[tx_watermark]: 0:0
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_intr_enable_tx_watermark (
     .clk_i   (clk_i),
@@ -486,9 +486,9 @@ module uart_reg_top #(
   );
 
   //   F[rx_watermark]: 1:1
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_intr_enable_rx_watermark (
     .clk_i   (clk_i),
@@ -512,9 +512,9 @@ module uart_reg_top #(
   );
 
   //   F[tx_empty]: 2:2
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_intr_enable_tx_empty (
     .clk_i   (clk_i),
@@ -538,9 +538,9 @@ module uart_reg_top #(
   );
 
   //   F[rx_overflow]: 3:3
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_intr_enable_rx_overflow (
     .clk_i   (clk_i),
@@ -564,9 +564,9 @@ module uart_reg_top #(
   );
 
   //   F[rx_frame_err]: 4:4
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_intr_enable_rx_frame_err (
     .clk_i   (clk_i),
@@ -590,9 +590,9 @@ module uart_reg_top #(
   );
 
   //   F[rx_break_err]: 5:5
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_intr_enable_rx_break_err (
     .clk_i   (clk_i),
@@ -616,9 +616,9 @@ module uart_reg_top #(
   );
 
   //   F[rx_timeout]: 6:6
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_intr_enable_rx_timeout (
     .clk_i   (clk_i),
@@ -642,9 +642,9 @@ module uart_reg_top #(
   );
 
   //   F[rx_parity_err]: 7:7
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_intr_enable_rx_parity_err (
     .clk_i   (clk_i),
@@ -673,7 +673,7 @@ module uart_reg_top #(
   logic [7:0] intr_test_flds_we;
   assign intr_test_qe = &intr_test_flds_we;
   //   F[tx_watermark]: 0:0
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (1)
   ) u_intr_test_tx_watermark (
     .re     (1'b0),
@@ -689,7 +689,7 @@ module uart_reg_top #(
   assign reg2hw.intr_test.tx_watermark.qe = intr_test_qe;
 
   //   F[rx_watermark]: 1:1
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (1)
   ) u_intr_test_rx_watermark (
     .re     (1'b0),
@@ -705,7 +705,7 @@ module uart_reg_top #(
   assign reg2hw.intr_test.rx_watermark.qe = intr_test_qe;
 
   //   F[tx_empty]: 2:2
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (1)
   ) u_intr_test_tx_empty (
     .re     (1'b0),
@@ -721,7 +721,7 @@ module uart_reg_top #(
   assign reg2hw.intr_test.tx_empty.qe = intr_test_qe;
 
   //   F[rx_overflow]: 3:3
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (1)
   ) u_intr_test_rx_overflow (
     .re     (1'b0),
@@ -737,7 +737,7 @@ module uart_reg_top #(
   assign reg2hw.intr_test.rx_overflow.qe = intr_test_qe;
 
   //   F[rx_frame_err]: 4:4
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (1)
   ) u_intr_test_rx_frame_err (
     .re     (1'b0),
@@ -753,7 +753,7 @@ module uart_reg_top #(
   assign reg2hw.intr_test.rx_frame_err.qe = intr_test_qe;
 
   //   F[rx_break_err]: 5:5
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (1)
   ) u_intr_test_rx_break_err (
     .re     (1'b0),
@@ -769,7 +769,7 @@ module uart_reg_top #(
   assign reg2hw.intr_test.rx_break_err.qe = intr_test_qe;
 
   //   F[rx_timeout]: 6:6
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (1)
   ) u_intr_test_rx_timeout (
     .re     (1'b0),
@@ -785,7 +785,7 @@ module uart_reg_top #(
   assign reg2hw.intr_test.rx_timeout.qe = intr_test_qe;
 
   //   F[rx_parity_err]: 7:7
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (1)
   ) u_intr_test_rx_parity_err (
     .re     (1'b0),
@@ -805,7 +805,7 @@ module uart_reg_top #(
   logic alert_test_qe;
   logic [0:0] alert_test_flds_we;
   assign alert_test_qe = &alert_test_flds_we;
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (1)
   ) u_alert_test (
     .re     (1'b0),
@@ -823,9 +823,9 @@ module uart_reg_top #(
 
   // R[ctrl]: V(False)
   //   F[tx]: 0:0
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_ctrl_tx (
     .clk_i   (clk_i),
@@ -849,9 +849,9 @@ module uart_reg_top #(
   );
 
   //   F[rx]: 1:1
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_ctrl_rx (
     .clk_i   (clk_i),
@@ -875,9 +875,9 @@ module uart_reg_top #(
   );
 
   //   F[nf]: 2:2
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_ctrl_nf (
     .clk_i   (clk_i),
@@ -901,9 +901,9 @@ module uart_reg_top #(
   );
 
   //   F[slpbk]: 4:4
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_ctrl_slpbk (
     .clk_i   (clk_i),
@@ -927,9 +927,9 @@ module uart_reg_top #(
   );
 
   //   F[llpbk]: 5:5
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_ctrl_llpbk (
     .clk_i   (clk_i),
@@ -953,9 +953,9 @@ module uart_reg_top #(
   );
 
   //   F[parity_en]: 6:6
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_ctrl_parity_en (
     .clk_i   (clk_i),
@@ -979,9 +979,9 @@ module uart_reg_top #(
   );
 
   //   F[parity_odd]: 7:7
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_ctrl_parity_odd (
     .clk_i   (clk_i),
@@ -1005,9 +1005,9 @@ module uart_reg_top #(
   );
 
   //   F[rxblvl]: 9:8
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (2),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (2'h0)
   ) u_ctrl_rxblvl (
     .clk_i   (clk_i),
@@ -1031,9 +1031,9 @@ module uart_reg_top #(
   );
 
   //   F[nco]: 31:16
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (16),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (16'h0)
   ) u_ctrl_nco (
     .clk_i   (clk_i),
@@ -1059,7 +1059,7 @@ module uart_reg_top #(
 
   // R[status]: V(True)
   //   F[txfull]: 0:0
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (1)
   ) u_status_txfull (
     .re     (status_re),
@@ -1074,7 +1074,7 @@ module uart_reg_top #(
   );
 
   //   F[rxfull]: 1:1
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (1)
   ) u_status_rxfull (
     .re     (status_re),
@@ -1089,7 +1089,7 @@ module uart_reg_top #(
   );
 
   //   F[txempty]: 2:2
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (1)
   ) u_status_txempty (
     .re     (status_re),
@@ -1104,7 +1104,7 @@ module uart_reg_top #(
   );
 
   //   F[txidle]: 3:3
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (1)
   ) u_status_txidle (
     .re     (status_re),
@@ -1119,7 +1119,7 @@ module uart_reg_top #(
   );
 
   //   F[rxidle]: 4:4
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (1)
   ) u_status_rxidle (
     .re     (status_re),
@@ -1134,7 +1134,7 @@ module uart_reg_top #(
   );
 
   //   F[rxempty]: 5:5
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (1)
   ) u_status_rxempty (
     .re     (status_re),
@@ -1150,7 +1150,7 @@ module uart_reg_top #(
 
 
   // R[rdata]: V(True)
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (8)
   ) u_rdata (
     .re     (rdata_re),
@@ -1168,7 +1168,7 @@ module uart_reg_top #(
   // R[wdata]: V(False)
   logic wdata_qe;
   logic [0:0] wdata_flds_we;
-  prim_flop #(
+  caliptra_prim_flop #(
     .Width(1),
     .ResetValue(0)
   ) u_wdata0_qe (
@@ -1177,9 +1177,9 @@ module uart_reg_top #(
     .d_i(&wdata_flds_we),
     .q_o(wdata_qe)
   );
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (8),
-    .SwAccess(prim_subreg_pkg::SwAccessWO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessWO),
     .RESVAL  (8'h0)
   ) u_wdata (
     .clk_i   (clk_i),
@@ -1207,7 +1207,7 @@ module uart_reg_top #(
   // R[fifo_ctrl]: V(False)
   logic fifo_ctrl_qe;
   logic [3:0] fifo_ctrl_flds_we;
-  prim_flop #(
+  caliptra_prim_flop #(
     .Width(1),
     .ResetValue(0)
   ) u_fifo_ctrl0_qe (
@@ -1217,9 +1217,9 @@ module uart_reg_top #(
     .q_o(fifo_ctrl_qe)
   );
   //   F[rxrst]: 0:0
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessWO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessWO),
     .RESVAL  (1'h0)
   ) u_fifo_ctrl_rxrst (
     .clk_i   (clk_i),
@@ -1244,9 +1244,9 @@ module uart_reg_top #(
   assign reg2hw.fifo_ctrl.rxrst.qe = fifo_ctrl_qe;
 
   //   F[txrst]: 1:1
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessWO),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessWO),
     .RESVAL  (1'h0)
   ) u_fifo_ctrl_txrst (
     .clk_i   (clk_i),
@@ -1271,9 +1271,9 @@ module uart_reg_top #(
   assign reg2hw.fifo_ctrl.txrst.qe = fifo_ctrl_qe;
 
   //   F[rxilvl]: 4:2
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (3),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (3'h0)
   ) u_fifo_ctrl_rxilvl (
     .clk_i   (clk_i),
@@ -1298,9 +1298,9 @@ module uart_reg_top #(
   assign reg2hw.fifo_ctrl.rxilvl.qe = fifo_ctrl_qe;
 
   //   F[txilvl]: 6:5
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (2),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (2'h0)
   ) u_fifo_ctrl_txilvl (
     .clk_i   (clk_i),
@@ -1327,7 +1327,7 @@ module uart_reg_top #(
 
   // R[fifo_status]: V(True)
   //   F[txlvl]: 5:0
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (6)
   ) u_fifo_status_txlvl (
     .re     (fifo_status_re),
@@ -1342,7 +1342,7 @@ module uart_reg_top #(
   );
 
   //   F[rxlvl]: 21:16
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (6)
   ) u_fifo_status_rxlvl (
     .re     (fifo_status_re),
@@ -1359,9 +1359,9 @@ module uart_reg_top #(
 
   // R[ovrd]: V(False)
   //   F[txen]: 0:0
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_ovrd_txen (
     .clk_i   (clk_i),
@@ -1385,9 +1385,9 @@ module uart_reg_top #(
   );
 
   //   F[txval]: 1:1
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_ovrd_txval (
     .clk_i   (clk_i),
@@ -1412,7 +1412,7 @@ module uart_reg_top #(
 
 
   // R[val]: V(True)
-  prim_subreg_ext #(
+  caliptra_prim_subreg_ext #(
     .DW    (16)
   ) u_val (
     .re     (val_re),
@@ -1429,9 +1429,9 @@ module uart_reg_top #(
 
   // R[timeout_ctrl]: V(False)
   //   F[val]: 23:0
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (24),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (24'h0)
   ) u_timeout_ctrl_val (
     .clk_i   (clk_i),
@@ -1455,9 +1455,9 @@ module uart_reg_top #(
   );
 
   //   F[en]: 31:31
-  prim_subreg #(
+  caliptra_prim_subreg #(
     .DW      (1),
-    .SwAccess(prim_subreg_pkg::SwAccessRW),
+    .SwAccess(caliptra_prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_timeout_ctrl_en (
     .clk_i   (clk_i),
diff --git a/src/uart/tb/uart_tb.sv b/src/uart/tb/uart_tb.sv
index 5ba89aacb..e854891c1 100644
--- a/src/uart/tb/uart_tb.sv
+++ b/src/uart/tb/uart_tb.sv
@@ -23,7 +23,7 @@
 
 module uart_tb
   import uart_reg_pkg::*;
-  import prim_mubi_pkg::mubi8_t;
+  import caliptra_prim_mubi_pkg::mubi8_t;
 (
 `ifdef VERILATOR
   input bit clk_tb
@@ -321,10 +321,10 @@ module uart_tb
   localparam logic [63:0] baud_rate = 115_200;
   logic [7:0] exp_data_q[$];  // queue of random input
 
-  task run_test;
+  task automatic run_test;
     logic [31:0] random_data;
     logic [7:0]  exp_data, act_data;
-    logic [31:0] ctrl = '0;
+    logic [31:0] ctrl;
     logic [63:0] nco;
 
     repeat (1000) @(posedge clk_tb);
@@ -347,6 +347,7 @@ module uart_tb
     nco = nco / 64'd100_000_000;
 
     $display("nco = %d", nco);
+    ctrl = '0;
     ctrl[31:16] = nco[15:0];
     ctrl[1:0] = 2'b11;
     write_single_word(ADDR_CTRL, ctrl);  // Enable RX/TX
diff --git a/tools/scripts/Makefile b/tools/scripts/Makefile
index 593f204ef..6a7efb724 100755
--- a/tools/scripts/Makefile
+++ b/tools/scripts/Makefile
@@ -1,5 +1,4 @@
 # SPDX-License-Identifier: Apache-2.0
-# Copyright 2020 Western Digital Corporation or its affiliates.
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
@@ -15,7 +14,8 @@
 #
 
 PLAYBOOK_RANDOM_SEED ?= $(shell date +%s)
-TEST_CFLAGS = -g -O3 -DMY_RANDOM_SEED=$(PLAYBOOK_RANDOM_SEED)
+BUILD_CFLAGS ?= 
+TEST_CFLAGS = -g -O3 -DMY_RANDOM_SEED=$(PLAYBOOK_RANDOM_SEED) $(BUILD_CFLAGS)
 
 ABI = -mabi=ilp32 -march=rv32imc
 
@@ -23,6 +23,14 @@ VERILATOR = verilator
 GCC_PREFIX = riscv64-unknown-elf
 BUILD_DIR = $(CURDIR)
 
+rv_gcc_version = $(strip $(shell $(GCC_PREFIX)-gcc --version | head -1 | sed "s/$(GCC_PREFIX)-gcc (\w\+) //"))
+$(info rv_gcc_version is $(rv_gcc_version))
+ifeq (12.2.0, $(rv_gcc_version))
+ABI = -mabi=ilp32 -march=rv32imc_zicsr_zifencei
+else
+ABI = -mabi=ilp32 -march=rv32imc
+endif
+
 # Define test name
 TESTNAME ?= iccm_lock
 TEST_DIR = $(CALIPTRA_ROOT)/src/integration/test_suites/$(TESTNAME)
@@ -47,7 +55,8 @@ COMP_LIB_NAMES := aes \
 		  datavault \
 		  sha256 \
 		  sha512 \
-		  soc_ifc
+		  soc_ifc \
+		  clk_gate
 COMP_LIBS := $(foreach name, $(COMP_LIB_NAMES), $(CALIPTRA_ROOT)/src/integration/test_suites/libs/$(name))
 HEADER_FILES := $(INCLUDES_DIR)/caliptra_defines.h \
 		$(INCLUDES_DIR)/defines.h \
@@ -74,12 +83,21 @@ OFILES += printf.o
 # Always compile the lib files - for every target
 OFILES += $(foreach comp_lib_name, $(COMP_LIB_NAMES), $(comp_lib_name).o)
 
+# Verilator trace format
+VERILATOR_TRACE=vcd
+
 ifdef debug
  DEBUG_PLUS = +dumpon
  IRUN_DEBUG = -access +rc
  IRUN_DEBUG_RUN = -input $(RV_ROOT)/testbench/input.tcl
  VCS_DEBUG = -debug_access
- VERILATOR_DEBUG = --trace --trace-structs
+ ifeq ($(VERILATOR_TRACE), vcd)
+  VERILATOR_DEBUG = --trace --trace-structs
+ else ifeq ($(VERILATOR_TRACE), fst)
+  VERILATOR_DEBUG = --trace-fst --trace-structs --trace-threads 2
+ else
+  $(error Unsupported Verilator trace format '$(VERILATOR_TRACE)')
+ endif
  RIVIERA_DEBUG = +access +r
 endif
 
@@ -138,15 +156,43 @@ includes = -I$(BUILD_DIR)
 #               v            v                v            v               v            v
 suppress = -Wno-WIDTH -Wno-UNOPTFLAT -Wno-LITENDIAN -Wno-CMPCONST -Wno-MULTIDRIVEN -Wno-UNPACKED
 
-# CFLAGS for verilator generated Makefiles. Without -std=c++11 it
+# CFLAGS for verilator generated Makefiles. Without -std=c++17 it
 # complains for `auto` variables
-CFLAGS += "-std=c++11"
+CFLAGS += -std=c++17
 
 # Optimization for better performance; alternative is nothing for
 # slower runtime (faster compiles) -O2 for faster runtime (slower
 # compiles), or -O for balance.
 VERILATOR_MAKE_FLAGS = OPT_FAST="-Os"
 
+# Testbench libs
+VERILATOR_TB_LIBS = jtagdpi/jtagdpi.c \
+                    tcp_server/tcp_server.c
+
+# Testbench sources
+VERILATOR_TB_SRCS = $(TBDIR)/test_caliptra_top_tb.cpp \
+                    $(addprefix $(CALIPTRA_ROOT)/src/integration/test_suites/libs/,$(VERILATOR_TB_LIBS))
+
+# Testbench defs
+VERILATOR_TB_DEFS = +define+CALIPTRA_INTERNAL_QSPI+CALIPTRA_INTERNAL_TRNG+CALIPTRA_INTERNAL_UART
+
+# By default debugging (JTAG) is locked in Caliptra. Add "DEBUG_UNLOCKED=1" to
+# enable it.
+ifdef DEBUG_UNLOCKED
+    VERILATOR_TB_DEFS += +define+CALIPTRA_DEBUG_UNLOCKED
+endif
+
+# To enforce holding the RISC-V core in reset add "FORCE_CPU_RESET=1".
+ifdef FORCE_CPU_RESET
+    VERILATOR_TB_DEFS += +define+CALIPTRA_FORCE_CPU_RESET
+endif
+
+# Run time arguments from command line
+VERILATOR_RUN_ARGS ?= ""
+
+# Add testbench lib include paths
+CFLAGS += $(addprefix -I$(CALIPTRA_ROOT)/src/integration/test_suites/libs/,$(dir $(VERILATOR_TB_LIBS)))
+
 # Targets
 all: clean verilator
 
@@ -156,10 +202,13 @@ clean:
 	dataset.asdb  library.cfg vsimsa.cfg  riviera-build wave.asdb sim.vcd \
 	*.h
 
+clean_fw:
+	rm -rf *.o *.h
+
 ############ Model Builds ###############################
 
-verilator-build: $(TBFILES) $(INCLUDES_DIR)/defines.h test_caliptra_top_tb.cpp
-	$(VERILATOR)  --cc -CFLAGS $(CFLAGS) \
+verilator-build: $(TBFILES) $(INCLUDES_DIR)/defines.h $(VERILATOR_TB_SRCS)
+	$(VERILATOR) $(VERILATOR_TB_SRCS) --cc -CFLAGS "$(CFLAGS)" \
 	  +libext+.v+.sv +define+RV_OPENSOURCE \
 	  --timescale 1ns/1ps \
 		--timing \
@@ -168,9 +217,8 @@ verilator-build: $(TBFILES) $(INCLUDES_DIR)/defines.h test_caliptra_top_tb.cpp
 	  -f $(TBDIR)/../config/caliptra_top_tb.vf --top-module caliptra_top_tb \
 	  -f $(TBDIR)/../config/caliptra_top_tb.vlt \
 	  -exe test_caliptra_top_tb.cpp --autoflush $(VERILATOR_DEBUG) \
-		+define+CALIPTRA_INTERNAL_QSPI+CALIPTRA_INTERNAL_TRNG+CALIPTRA_INTERNAL_UART
-	cp $(TBDIR)/test_caliptra_top_tb.cpp obj_dir/
-	$(MAKE) -j -e -C obj_dir/ -f Vcaliptra_top_tb.mk $(VERILATOR_MAKE_FLAGS) VM_PARALLEL_BUILDS=1
+	  $(VERILATOR_TB_DEFS)
+	$(MAKE) -j`nproc` -e -C obj_dir/ -f Vcaliptra_top_tb.mk $(VERILATOR_MAKE_FLAGS) VM_PARALLEL_BUILDS=1
 	touch verilator-build
 
 vcs-build: $(TBFILES) $(INCLUDES_DIR)/defines.h
@@ -183,7 +231,7 @@ vcs-build: $(TBFILES) $(INCLUDES_DIR)/defines.h
 ############ TEST Simulation ###############################
 
 verilator: program.hex verilator-build
-	./obj_dir/Vcaliptra_top_tb
+	./obj_dir/Vcaliptra_top_tb $(VERILATOR_RUN_ARGS)
 
 vcs: program.hex vcs-build
 	./simv.caliptra_top_tb
@@ -202,7 +250,7 @@ else ifneq (,$(wildcard $(TEST_DIR)/$(TESTNAME)))
 # Build program.hex from RUST executable
 program.hex:
 	@echo "Building program.hex from $(TESTNAME) using Crypto Test rules for pre-compiled RUST executables"
-	-$(GCC_PREFIX)-objcopy -O verilog -R .data -R .rodata -R .bss -R .sbss -R .iccm -R .dccm -R .eh_frame --pad-to 0x8000 --gap-fill 0xFF --no-change-warnings $(TEST_DIR)/$(TESTNAME) program.hex
+	-$(GCC_PREFIX)-objcopy -O verilog -R .data -R .rodata -R .bss -R .sbss -R .iccm -R .dccm -R .eh_frame --pad-to 0xC000 --gap-fill 0xFF --no-change-warnings $(TEST_DIR)/$(TESTNAME) program.hex
 	-$(GCC_PREFIX)-objcopy -O verilog -j .data -j .rodata -j .bss -j .sbss -j .dccm \
 			      --change-section-lma       .data-0x50000000 \
 			      --change-section-lma     .rodata-0x50000000 \
@@ -222,7 +270,7 @@ else
 program.hex: $(OFILE_CRT) $(OFILES) $(LINK)
 	@echo Building $(TESTNAME)
 	$(GCC_PREFIX)-gcc $(ABI) -Wl,-Map=$(TESTNAME).map -lgcc -T$(LINK) -o $(TESTNAME).exe $(OFILE_CRT) $(OFILES) -nostartfiles  $(TEST_LIBS)
-	-$(GCC_PREFIX)-objcopy -O verilog -R .data_iccm0 -R .data_iccm1 -R .data_iccm2 -R .iccm -R .dccm -R .eh_frame --pad-to 0x8000 --no-change-warnings $(TESTNAME).exe program.hex
+	-$(GCC_PREFIX)-objcopy -O verilog -R .data_iccm0 -R .data_iccm1 -R .data_iccm2 -R .iccm -R .dccm -R .eh_frame --pad-to 0xC000 --no-change-warnings $(TESTNAME).exe program.hex
 	-$(GCC_PREFIX)-objcopy -O verilog -j .data_iccm0 -j .data_iccm1 -j .data_iccm2 -j .dccm \
 			      --change-section-lma .data_iccm0-0x50000000 \
 			      --change-section-lma .data_iccm1-0x50000000 \
@@ -262,5 +310,5 @@ help:
 	@echo Make sure the environment variable RV_ROOT is set.
 	@echo Possible targets: verilator vcs irun vlog riviera help clean all verilator-build irun-build vcs-build riviera-build program.hex
 
-.PHONY: help clean verilator vcs irun vlog riviera
+.PHONY: help clean clean_fw verilator vcs irun vlog riviera
 
diff --git a/tools/scripts/openocd/board/caliptra-verilator-rst.cfg b/tools/scripts/openocd/board/caliptra-verilator-rst.cfg
new file mode 100644
index 000000000..630df5369
--- /dev/null
+++ b/tools/scripts/openocd/board/caliptra-verilator-rst.cfg
@@ -0,0 +1,5 @@
+source [find interface/sim-jtagdpi.cfg]
+source [find target/veer-el2-rst.cfg]
+
+# Increase timeouts in simulation
+riscv set_command_timeout_sec 300
diff --git a/tools/scripts/openocd/board/caliptra-verilator.cfg b/tools/scripts/openocd/board/caliptra-verilator.cfg
new file mode 100644
index 000000000..c91718677
--- /dev/null
+++ b/tools/scripts/openocd/board/caliptra-verilator.cfg
@@ -0,0 +1,5 @@
+source [find interface/sim-jtagdpi.cfg]
+source [find target/veer-el2.cfg]
+
+# Increase timeouts in simulation
+riscv set_command_timeout_sec 300
diff --git a/tools/scripts/openocd/interface/sim-jtagdpi.cfg b/tools/scripts/openocd/interface/sim-jtagdpi.cfg
new file mode 100644
index 000000000..7d43a4ad5
--- /dev/null
+++ b/tools/scripts/openocd/interface/sim-jtagdpi.cfg
@@ -0,0 +1,11 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+# "JTAG adapter" for simulation, exposed to OpenOCD through a TCP socket
+# speaking the remote_bitbang protocol. The adapter is implemented as
+# SystemVerilog DPI module.
+
+adapter driver remote_bitbang
+remote_bitbang port 5000
+remote_bitbang host localhost
diff --git a/tools/scripts/openocd/target/veer-el2-rst.cfg b/tools/scripts/openocd/target/veer-el2-rst.cfg
new file mode 100644
index 000000000..0f4c86fde
--- /dev/null
+++ b/tools/scripts/openocd/target/veer-el2-rst.cfg
@@ -0,0 +1,35 @@
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME riscv
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x1000008b
+}
+
+jtag newtap $_CHIPNAME tap -irlen 5 -expected-id $_CPUTAPID
+set _TARGETNAME $_CHIPNAME.tap
+target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -rtos hwthread
+
+# Configure work area in on-chip SRAM
+$_TARGETNAME.0 configure -work-area-phys 0x50001000 -work-area-size 0x1000 -work-area-backup 0
+
+# Mem access mode
+riscv set_mem_access sysbus
+
+# The following commands disable target examination and set explicitly the
+# core parameters read from CSRs. These required a modified version of
+# OpenOCD from https://github.com/antmicro/openocd/tree/riscv-nohalt
+riscv set_nohalt on
+riscv set_xlen 32
+riscv set_misa 0x40001104
+
+# Be verbose about GDB errors
+gdb_report_data_abort enable
+gdb_report_register_access_error enable
+
+# Always use hardware breakpoints.
+gdb_breakpoint_override hard
diff --git a/tools/scripts/openocd/target/veer-el2.cfg b/tools/scripts/openocd/target/veer-el2.cfg
new file mode 100644
index 000000000..45374886d
--- /dev/null
+++ b/tools/scripts/openocd/target/veer-el2.cfg
@@ -0,0 +1,28 @@
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME riscv
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x1000008b
+}
+
+jtag newtap $_CHIPNAME tap -irlen 5 -expected-id $_CPUTAPID
+set _TARGETNAME $_CHIPNAME.tap
+target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -rtos hwthread
+
+# Configure work area in on-chip SRAM
+$_TARGETNAME.0 configure -work-area-phys 0x50001000 -work-area-size 0x1000 -work-area-backup 0
+
+# Mem access mode
+riscv set_mem_access abstract
+
+# Be verbose about GDB errors
+gdb_report_data_abort enable
+gdb_report_register_access_error enable
+
+# Always use hardware breakpoints.
+gdb_breakpoint_override hard
diff --git a/tools/scripts/rdl_post_process.py b/tools/scripts/rdl_post_process.py
index 4690f7e2f..4c86f1091 100644
--- a/tools/scripts/rdl_post_process.py
+++ b/tools/scripts/rdl_post_process.py
@@ -32,9 +32,12 @@ def scrub_line_by_line(fname):
     #       and dimensions are on separate lines
     for line in rhandle:
         has_assign = re.search(r'\bassign\b', line)
+        has_reg_strb = re.search(r'\bdecoded_reg_strb\b', line)
         has_unpacked = re.search(r'\[\d+\]', line)
         has_struct = re.search(r'\bstruct\b\s*(?:unpacked)?', line)
-        if (has_assign is not None):
+        # Skip lines with logic assignments or references to signals; we
+        # only want to scrub signal definitions for unpacked arrays
+        if (has_assign is not None or has_reg_strb is not None):
             mod_lines+=line
         elif (has_struct is not None):
             line = re.sub(r'(\bstruct\b)\s*(?:unpacked)?', r'\1 packed', line)
diff --git a/tools/scripts/reg_doc_gen.sh b/tools/scripts/reg_doc_gen.sh
index 3a222c621..367c77598 100755
--- a/tools/scripts/reg_doc_gen.sh
+++ b/tools/scripts/reg_doc_gen.sh
@@ -14,7 +14,7 @@
 # limitations under the License.
 #
 
-python tools/scripts/reg_doc_gen.py \
+python3 tools/scripts/reg_doc_gen.py \
 src/integration/rtl/caliptra_reg.rdl \
 src/keyvault/rtl/kv_reg.rdl \
 src/pcrvault/rtl/pv_reg.rdl \
@@ -33,7 +33,7 @@ src/csrng/data/csrng.rdl \
 src/spi_host/data/spi_host.rdl \
 src/uart/data/uart.rdl
 
-python tools/scripts/reg_doc_gen.py \
+python3 tools/scripts/reg_doc_gen.py \
 src/soc_ifc/rtl/caliptra_top_reg.rdl \
 src/soc_ifc/rtl/soc_ifc_doc.rdl \
 src/soc_ifc/rtl/mbox_csr.rdl \
diff --git a/tools/scripts/reg_gen.py b/tools/scripts/reg_gen.py
index 9d48a4e39..eed084da1 100644
--- a/tools/scripts/reg_gen.py
+++ b/tools/scripts/reg_gen.py
@@ -98,8 +98,15 @@ def get_regfile_name(self):
     )
 
     # Export a UVM register model
-    exporter = UVMExporter()
+    exporter = UVMExporter(user_template_dir=os.path.join(repo_root, "tools/templates/rdl/uvm"))
     exporter.export(root, os.path.join(rtl_output_dir, os.path.splitext(os.path.basename(sys.argv[1]))[0]) + "_uvm.sv")
+    # The below lines are used to generate a baseline/starting point for the include files "<reg_name>_covergroups.svh" and "<reg_name>_sample.svh"
+    # The generated files will need to be hand-edited to provide the desired functionality.
+    # Uncomment these lines and run this script directly on the target RDL file to generate the files.
+#    exporter = UVMExporter(user_template_dir=os.path.join(repo_root, "tools/templates/rdl/cov"))
+#    exporter.export(root, os.path.join(rtl_output_dir, os.path.splitext(os.path.basename(sys.argv[1]))[0]) + "_covergroups.svh")
+#    exporter = UVMExporter(user_template_dir=os.path.join(repo_root, "tools/templates/rdl/smp"))
+#    exporter.export(root, os.path.join(rtl_output_dir, os.path.splitext(os.path.basename(sys.argv[1]))[0]) + "_sample.svh")
 
     # Traverse the register model!
     walker = RDLWalker(unroll=True)
@@ -108,6 +115,7 @@ def get_regfile_name(self):
 
     # Scrub the output SystemVerilog files to modify the coding style
     #  - Change unpacked arrays to packed, unpacked structs to packed
+    # TODO just make a new exporter template instead of scrubbing?
     rdl_post_process.scrub_line_by_line(str(pkglistener.get_regfile_name() + ".sv"))
     rdl_post_process.scrub_line_by_line(str(pkglistener.get_regfile_name() + "_pkg.sv"))
 
diff --git a/tools/scripts/run_verilator_l0_regression.py b/tools/scripts/run_verilator_l0_regression.py
index acce0bd85..a4cbbd2ee 100644
--- a/tools/scripts/run_verilator_l0_regression.py
+++ b/tools/scripts/run_verilator_l0_regression.py
@@ -22,6 +22,7 @@
 import subprocess
 import logging
 import datetime
+from multiprocessing import Pool
 
 logger = logging.getLogger()
 logger.setLevel(logging.INFO)
@@ -119,11 +120,19 @@ def getTestNames():
 
     for testYml in testPaths:
         x = re.search(r'../test_suites/(\S+)/\S+.yml', testYml)
+        # Skip clk gating tests in Verilator until PC issue is resolved
+        # https://github.com/chipsalliance/Cores-VeeR-EL2/issues/88
+        # https://github.com/chipsalliance/caliptra-rtl/issues/126
+        if (re.search(r'(smoke_test_clk_gating|smoke_test_cg_wdt)',x.groups()[0])) :
+            continue
         integrationTestSuiteList.append(x.groups()[0])
 
     return integrationTestSuiteList
 
-def runTest(test, scratch, verilated):
+def runTest(args):
+
+    (test, scratch, verilated) = args;
+
     testdir = os.path.join(scratch, test)
     # Reuse pristine verilator-build output for each test
     shutil.copytree(verilated, testdir)
@@ -146,7 +155,7 @@ def runTest(test, scratch, verilated):
     # Invoke makefile for the current test
     mfile = os.path.join(os.environ.get('CALIPTRA_ROOT'),"tools/scripts/Makefile")
     testname = "TESTNAME=" + test
-    cmd = " ".join(["make", "-C", testdir, "-f", mfile, testname, "verilator"])
+    cmd = " ".join(["make", "-C", testdir, "-f", mfile, testname, "verilator", "VERILATOR_RUN_ARGS=+CLP_REGRESSION"])
     exitcode, resultout, resulterr = runBashScript(cmd)
 
     # Parse and log the results
@@ -200,20 +209,22 @@ def main():
     verilated = verilateTB(scratch)
     # Parse yaml file for test list
     testnames=getTestNames()
-    exitcode = 0
-    # Run all tests and accumulate error status codes
-    for test in testnames:
-        exitcode += runTest(test, scratch, verilated)
+    # Run all tests in parallel and accumulate error status codes to the global failcount
+    failcount=0
+    run_args = [(testname, scratch, verilated) for testname in testnames]
+    test_status_list = Pool(len(testnames)).map(runTest, run_args)
+    for sts in test_status_list:
+        failcount += sts
     # Ending summary
     infoMsg = f"############################################## SUMMARY ##############################################"
     logger.info(infoMsg)
-    if exitcode == 0:
+    if failcount == 0:
         infoMsg = f"All tests passed!"
         logger.info(infoMsg)
     else:
-        errorMsg = f"Regression failed! Total number of failing tests: {exitcode}"
+        errorMsg = f"Regression failed! Total number of failing tests: {failcount}"
         logger.error(errorMsg)
-    return exitcode
+    return failcount
 
 if __name__ == "__main__":
     sys.exit(main())
diff --git a/tools/templates/rdl/cov/main.sv b/tools/templates/rdl/cov/main.sv
new file mode 100644
index 000000000..10c531d0c
--- /dev/null
+++ b/tools/templates/rdl/cov/main.sv
@@ -0,0 +1,14 @@
+{% import 'uvm_reg.sv' as uvm_reg with context %}
+{%- macro top() %}
+{%- for node in top_node.descendants(in_post_order=True) -%}
+    {{child_cg(node)}}
+{%- endfor -%}
+{% endmacro -%}
+
+{% macro child_cg(node) -%}
+    {%- if isinstance(node, RegNode) -%}
+        {%- if not node.is_virtual -%}
+            {{uvm_reg.cg_definition(node)}}
+        {%- endif -%}
+    {%- endif -%}
+{%- endmacro %}
diff --git a/tools/templates/rdl/cov/top_pkg.sv b/tools/templates/rdl/cov/top_pkg.sv
new file mode 100644
index 000000000..4502c01c3
--- /dev/null
+++ b/tools/templates/rdl/cov/top_pkg.sv
@@ -0,0 +1,20 @@
+{%- import 'main.sv' as main with context -%}
+{%- raw -%}
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+{% endraw %}
+{{ "`ifndef" }} {{top_node.get_path()|upper}}_COVERGROUPS
+    {{ "`define" }} {{top_node.get_path()|upper}}_COVERGROUPS
+    {{main.top()|indent}}
+{{ "`endif" }}
diff --git a/tools/templates/rdl/cov/uvm_reg.sv b/tools/templates/rdl/cov/uvm_reg.sv
new file mode 120000
index 000000000..0d29126df
--- /dev/null
+++ b/tools/templates/rdl/cov/uvm_reg.sv
@@ -0,0 +1 @@
+../uvm/uvm_reg.sv
\ No newline at end of file
diff --git a/tools/templates/rdl/smp/main.sv b/tools/templates/rdl/smp/main.sv
new file mode 100644
index 000000000..f6dc1c077
--- /dev/null
+++ b/tools/templates/rdl/smp/main.sv
@@ -0,0 +1,16 @@
+{%- import 'uvm_reg.sv' as uvm_reg with context -%}
+{%- macro top() -%}
+{%- for node in top_node.descendants(in_post_order=True) -%}
+    {{child_smp(node)}}
+{%- endfor -%}
+{%- endmacro -%}
+
+{%- macro child_smp(node) -%}
+    {%- if isinstance(node, RegNode) -%}
+        {% if not node.is_virtual %}
+{{"/*-----------------------"}} {{get_class_name(node)|upper}} {{"SAMPLE FUNCTIONS -----------------------*/"}}
+{{uvm_reg.function_sample_def(node)}}
+{{uvm_reg.function_sample_values_def(node)}}
+        {%- endif %}
+    {%- endif -%}
+{%- endmacro %}
diff --git a/tools/templates/rdl/smp/top_pkg.sv b/tools/templates/rdl/smp/top_pkg.sv
new file mode 100644
index 000000000..429fcd633
--- /dev/null
+++ b/tools/templates/rdl/smp/top_pkg.sv
@@ -0,0 +1,20 @@
+{%- import 'main.sv' as main with context -%}
+{%- raw -%}
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+{% endraw %}
+{{ "`ifndef" }} {{top_node.get_path()|upper}}_SAMPLE
+    {{ "`define" }} {{top_node.get_path()|upper}}_SAMPLE
+    {{main.top()|indent}}
+{{ "`endif" }}
diff --git a/tools/templates/rdl/smp/uvm_reg.sv b/tools/templates/rdl/smp/uvm_reg.sv
new file mode 120000
index 000000000..0d29126df
--- /dev/null
+++ b/tools/templates/rdl/smp/uvm_reg.sv
@@ -0,0 +1 @@
+../uvm/uvm_reg.sv
\ No newline at end of file
diff --git a/tools/templates/rdl/uvm/main.sv b/tools/templates/rdl/uvm/main.sv
new file mode 100644
index 000000000..e3bdff560
--- /dev/null
+++ b/tools/templates/rdl/uvm/main.sv
@@ -0,0 +1,37 @@
+{% import 'uvm_reg.sv' as uvm_reg with context %}
+{% import 'uvm_vreg.sv' as uvm_vreg with context %}
+{% import 'uvm_reg_block-mem.sv' as uvm_reg_block_mem with context %}
+{% import 'uvm_reg_block.sv' as uvm_reg_block with context %}
+
+
+{% macro top() -%}
+{{include_covergroups(top_node)}}
+    {%- for node in top_node.descendants(in_post_order=True) -%}
+        {{child_def(node)}}
+    {%- endfor -%}
+    {{child_def(top_node)}}
+{{include_sample(top_node)}}
+{%- endmacro %}
+
+
+{% macro child_def(node) -%}
+    {%- if isinstance(node, RegNode) -%}
+        {%- if node.is_virtual -%}
+            {{uvm_vreg.class_definition(node)}}
+        {%- else -%}
+            {{uvm_reg.class_definition(node)}}
+        {%- endif -%}
+    {%- elif isinstance(node, (RegfileNode, AddrmapNode)) -%}
+        {{uvm_reg_block.class_definition(node)}}
+    {%- elif isinstance(node, MemNode) -%}
+        {{uvm_reg_block_mem.class_definition(node)}}
+    {%- endif -%}
+{%- endmacro %}
+
+{% macro include_covergroups(node) -%}
+`include "{{get_class_name(node)}}_covergroups.svh"
+{%- endmacro %}
+
+{% macro include_sample(node) -%}
+`include "{{get_class_name(node)}}_sample.svh"
+{%- endmacro %}
diff --git a/tools/templates/rdl/uvm/uvm_reg.sv b/tools/templates/rdl/uvm/uvm_reg.sv
new file mode 100644
index 000000000..bf30f1187
--- /dev/null
+++ b/tools/templates/rdl/uvm/uvm_reg.sv
@@ -0,0 +1,288 @@
+{% import 'utils.sv' as utils with context %}
+
+//------------------------------------------------------------------------------
+// uvm_reg definition
+//------------------------------------------------------------------------------
+{% macro class_definition(node) -%}
+{%- if class_needs_definition(node) %}
+// {{get_class_friendly_name(node)}}
+class {{get_class_name(node)}} extends uvm_reg;
+{%- if use_uvm_factory %}
+    `uvm_object_utils({{get_class_name(node)}})
+{%- endif %}
+    protected uvm_reg_data_t m_current;
+    protected uvm_reg_data_t m_data;
+    protected bit            m_is_read;
+{% for field in node.fields() %}
+    {{bit_covergroup_name(node)|indent}} {{bit_covergroup_inst(field)}}[{{field.width}}];
+{%- endfor %}
+    {{fld_covergroup_name(node)|indent}} fld_cg;
+    {{child_insts(node)|indent}}
+    {{function_new(node)|indent}}
+    {{function_sample_values(node)|indent}}
+    {{function_sample(node)|indent}}
+
+    {{function_build(node)|indent}}
+endclass : {{get_class_name(node)}}
+{% endif -%}
+{%- endmacro %}
+
+
+//------------------------------------------------------------------------------
+// Covergroup Definitions
+//------------------------------------------------------------------------------
+{% macro cg_definition(node) %}
+{{"/*-----------------------"}} {{get_class_name(node)|upper}} {{"COVERGROUPS -----------------------*/"}}
+covergroup {{bit_covergroup_name(node)}} with function sample(input bit reg_bit);
+    option.per_instance = 1;
+    {{bit_coverpoint()|indent}}
+endgroup
+covergroup {{fld_covergroup_name(node)}} with function sample({{covergroup_inputs(node)}});
+    option.per_instance = 1;
+    {{fld_coverpoints(node)|indent}}
+endgroup
+{% endmacro %}
+
+
+//------------------------------------------------------------------------------
+// Covergroup Inputs
+//------------------------------------------------------------------------------
+{% macro covergroup_inputs(node) %}
+{% for field in node.fields() -%}
+input bit [{{field.width}}-1:0] {{get_inst_name(field)}}{% if not loop.last %}{{","}}{% endif %}
+{% endfor %}
+{%- endmacro %}
+
+
+//------------------------------------------------------------------------------
+// Coverpoint Definitions
+//------------------------------------------------------------------------------
+{%- macro fld_coverpoints(node) -%}
+{%- for field in node.fields() -%}
+{{field_coverpoint(field)}}
+{%- endfor -%}
+{%- endmacro -%}
+
+
+//------------------------------------------------------------------------------
+// Singular Coverpoint Definition
+//------------------------------------------------------------------------------
+{%- macro bit_coverpoint() -%}
+reg_bit_cp : coverpoint reg_bit {
+    bins value[2] = {0,1};
+}
+reg_bit_edge_cp : coverpoint reg_bit {
+    bins rise = (0 => 1);
+    bins fall = (1 => 0);
+}
+{% endmacro %}
+{%- macro field_coverpoint(field) -%}
+{{get_inst_name(field)}}_cp : coverpoint {{get_inst_name(field)}};
+{% endmacro %}
+
+
+//------------------------------------------------------------------------------
+// Child instances
+//------------------------------------------------------------------------------
+{% macro child_insts(node) -%}
+{%- for field in node.fields() -%}
+rand uvm_reg_field {{get_inst_name(field)}};
+{% endfor -%}
+{%- endmacro %}
+
+
+//------------------------------------------------------------------------------
+// new() function
+//------------------------------------------------------------------------------
+{% macro function_new(node) -%}
+function new(string name = "{{get_class_name(node)}}");
+    super.new(name, {{node.get_property('regwidth')}}, build_coverage(UVM_CVR_ALL));
+endfunction : new
+{%- endmacro %}
+
+
+//------------------------------------------------------------------------------
+// sample() function declaration
+//------------------------------------------------------------------------------
+{% macro function_sample(node) -%}
+extern protected virtual function void sample(uvm_reg_data_t  data,
+                                              uvm_reg_data_t  byte_en,
+                                              bit             is_read,
+                                              uvm_reg_map     map);
+{%- endmacro %}
+
+
+//------------------------------------------------------------------------------
+// sample_values() function declaration
+//------------------------------------------------------------------------------
+{% macro function_sample_values(node) -%}
+extern virtual function void sample_values();
+{%- endmacro %}
+
+
+//------------------------------------------------------------------------------
+// sample() function definition
+//------------------------------------------------------------------------------
+{%- macro function_sample_def(node) -%}
+function void {{get_class_name(node)}}::sample(uvm_reg_data_t  data,
+                                               uvm_reg_data_t  byte_en,
+                                               bit             is_read,
+                                               uvm_reg_map     map);
+    m_current = get();
+    m_data    = data;
+    m_is_read = is_read;
+    if (get_coverage(UVM_CVR_REG_BITS)) begin
+{%- for field in node.fields() %}
+        foreach({{bit_covergroup_inst(field)}}[bt]) this.{{bit_covergroup_inst(field)}}[bt].sample(data[{{field.lsb}} + bt]);
+{%- endfor %}
+    end
+    if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+        this.fld_cg.sample({{covergroup_sample_args(node)}});
+    end
+endfunction
+{% endmacro -%}
+
+
+//------------------------------------------------------------------------------
+// sample_values() function definition
+//------------------------------------------------------------------------------
+{%- macro function_sample_values_def(node) -%}
+function void {{get_class_name(node)}}::sample_values();
+    if (get_coverage(UVM_CVR_REG_BITS)) begin
+{%- for field in node.fields() %}
+        foreach({{bit_covergroup_inst(field)}}[bt]) this.{{bit_covergroup_inst(field)}}[bt].sample({{get_inst_name(field)}}.get_mirrored_value() >> bt);
+{%- endfor %}
+    end
+    if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+        this.fld_cg.sample({{covergroup_sample_values_args(node)}});
+    end
+endfunction
+{% endmacro %}
+
+
+//------------------------------------------------------------------------------
+// build() function
+//------------------------------------------------------------------------------
+{% macro function_build(node) -%}
+virtual function void build();
+    {%- for field in node.fields() %}
+    {%- if use_uvm_factory %}
+    this.{{get_inst_name(field)}} = uvm_reg_field::type_id::create("{{get_inst_name(field)}}");
+    {%- else %}
+    this.{{get_inst_name(field)}} = new("{{get_inst_name(field)}}");
+    {%- endif %}
+    this.{{get_inst_name(field)}}.configure(this, {{field.width}}, {{field.lsb}}, "{{get_field_access(field)}}", {{field.is_volatile|int}}, {{"'h%x" % field.get_property('reset', default=0)}}, {{field.get_property('reset') is not none|int}}, 1, 0);
+    {%- endfor %}
+    if (has_coverage(UVM_CVR_REG_BITS)) begin
+{%- for field in node.fields() %}
+        foreach({{bit_covergroup_inst(field)}}[bt]) {{bit_covergroup_inst(field)}}[bt] = new();
+{%- endfor %}
+    end
+    if (has_coverage(UVM_CVR_FIELD_VALS))
+        fld_cg = new();
+endfunction : build
+{%- endmacro %}
+
+
+//------------------------------------------------------------------------------
+// Covergroup Name
+//------------------------------------------------------------------------------
+{% macro bit_covergroup_name(node)  -%} {{get_class_name(node)}}_bit_cg {%- endmacro %}
+{% macro bit_covergroup_inst(field) -%} {{"%s_bit_cg"|format(get_inst_name(field))}} {%- endmacro %}
+{% macro fld_covergroup_name(node)  -%} {{get_class_name(node)}}_fld_cg {%- endmacro %}
+
+
+//------------------------------------------------------------------------------
+// Covergroup Constructor Arguments
+//------------------------------------------------------------------------------
+{% macro covergroup_new_args(node) -%}
+    {%- for field in node.fields() %} {{covergroup_new_arg(field)}} {% if loop.last %} {{''}} {% else %} {{","}} {% endif %} {%- endfor %}
+{%- endmacro %}
+{% macro covergroup_new_arg(field) -%}
+    {{get_inst_name(field)}}.get_reset()
+{%- endmacro %}
+{% macro covergroup_sample_args(node) -%}
+    {%- for field in node.fields() %} {{covergroup_sample_arg(field)}} {% if loop.last %} {{''}} {% else %} {{","}} {% endif %} {%- endfor %}
+{%- endmacro %}
+{% macro covergroup_sample_arg(field) -%}
+    data[{{field.msb}}:{{field.lsb}}]{{"/*%s*/"|format(get_inst_name(field))}}
+{%- endmacro %}
+{% macro covergroup_sample_values_args(node) -%}
+    {%- for field in node.fields() %} {{covergroup_sample_values_arg(field)}} {% if loop.last %} {{''}} {% else %} {{","}} {% endif %} {%- endfor %}
+{%- endmacro %}
+{% macro covergroup_sample_values_arg(field) -%}
+    {{get_inst_name(field)}}.get_mirrored_value()
+{%- endmacro %}
+
+
+//------------------------------------------------------------------------------
+// build() actions for uvm_reg instance (called by parent)
+//------------------------------------------------------------------------------
+{% macro build_instance(node) -%}
+{%- if node.is_array %}
+foreach(this.{{get_inst_name(node)}}[{{utils.array_iterator_list(node)}}]) begin
+    {%- if use_uvm_factory %}
+    this.{{get_inst_name(node)}}{{utils.array_iterator_suffix(node)}} = {{get_class_name(node)}}::type_id::create($sformatf("{{get_inst_name(node)}}{{utils.array_suffix_format(node)}}", {{utils.array_iterator_list(node)}}));
+    {%- else %}
+    this.{{get_inst_name(node)}}{{utils.array_iterator_suffix(node)}} = new($sformatf("{{get_inst_name(node)}}{{utils.array_suffix_format(node)}}", {{utils.array_iterator_list(node)}}));
+    {%- endif %}
+    this.{{get_inst_name(node)}}{{utils.array_iterator_suffix(node)}}.configure(this);
+    {{add_hdl_path_slices(node, get_inst_name(node) + utils.array_iterator_suffix(node))|trim|indent}}
+    this.{{get_inst_name(node)}}{{utils.array_iterator_suffix(node)}}.build();
+    this.default_map.add_reg(this.{{get_inst_name(node)}}{{utils.array_iterator_suffix(node)}}, {{get_array_address_offset_expr(node)}});
+end
+{%- else %}
+{%- if use_uvm_factory %}
+this.{{get_inst_name(node)}} = {{get_class_name(node)}}::type_id::create("{{get_inst_name(node)}}");
+{%- else %}
+this.{{get_inst_name(node)}} = new("{{get_inst_name(node)}}");
+{%- endif %}
+this.{{get_inst_name(node)}}.configure(this);
+{{add_hdl_path_slices(node, get_inst_name(node))|trim}}
+this.{{get_inst_name(node)}}.build();
+this.default_map.add_reg(this.{{get_inst_name(node)}}, {{"'h%x" % node.raw_address_offset}});
+{%- endif %}
+{%- endmacro %}
+
+//------------------------------------------------------------------------------
+// Load HDL path slices for this reg instance
+//------------------------------------------------------------------------------
+{% macro add_hdl_path_slices(node, inst_ref) -%}
+{%- if node.get_property('hdl_path') %}
+{{inst_ref}}.add_hdl_path_slice("{{node.get_property('hdl_path')}}", -1, -1);
+{%- endif -%}
+
+{%- if node.get_property('hdl_path_gate') %}
+{{inst_ref}}.add_hdl_path_slice("{{node.get_property('hdl_path_gate')}}", -1, -1, 0, "GATE");
+{%- endif -%}
+
+{%- for field in node.fields() %}
+{%- if field.get_property('hdl_path_slice') is none -%}
+{%- elif field.get_property('hdl_path_slice')|length == 1 %}
+{{inst_ref}}.add_hdl_path_slice("{{field.get_property('hdl_path_slice')[0]}}", {{field.lsb}}, {{field.width}});
+{%- elif field.get_property('hdl_path_slice')|length == field.width %}
+{%- for slice in field.get_property('hdl_path_slice') %}
+{%- if field.msb > field.lsb %}
+{{inst_ref}}.add_hdl_path_slice("{{slice}}", {{field.msb - loop.index0}}, 1);
+{%- else %}
+{{inst_ref}}.add_hdl_path_slice("{{slice}}", {{field.msb + loop.index0}}, 1);
+{%- endif %}
+{%- endfor %}
+{%- endif %}
+{%- endfor -%}
+
+{%- for field in node.fields() %}
+{%- if field.get_property('hdl_path_gate_slice') is none -%}
+{%- elif field.get_property('hdl_path_gate_slice')|length == 1 %}
+{{inst_ref}}.add_hdl_path_slice("{{field.get_property('hdl_path_gate_slice')[0]}}", {{field.lsb}}, {{field.width}}, 0, "GATE");
+{%- elif field.get_property('hdl_path_gate_slice')|length == field.width %}
+{%- for slice in field.get_property('hdl_path_gate_slice') %}
+{%- if field.msb > field.lsb %}
+{{inst_ref}}.add_hdl_path_slice("{{slice}}", {{field.msb - loop.index0}}, 1, 0, "GATE");
+{%- else %}
+{{inst_ref}}.add_hdl_path_slice("{{slice}}", {{field.msb + loop.index0}}, 1, 0, "GATE");
+{%- endif %}
+{%- endfor %}
+{%- endif %}
+{%- endfor %}
+{%- endmacro %}