From 5b2a0b266957216fcefafe9c773f9ee50f5d677c Mon Sep 17 00:00:00 2001 From: Kiran Upadhyayula Date: Fri, 15 Sep 2023 23:39:59 +0000 Subject: [PATCH 01/11] Merged PR 124577: Fix WDT NMI prediction Fixes the case where timers restart and then t2 times out in cascade mode and NMI is triggered. Expected txn needs to occur in the same clk as NMI interrupt Related work items: #545794 --- .../soc_ifc_env_pkg/src/soc_ifc_predictor.svh | 56 ++++++++++--------- 1 file changed, 29 insertions(+), 27 deletions(-) diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_predictor.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_predictor.svh index 9e1465f0f..7a9a43cd0 100644 --- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_predictor.svh +++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_predictor.svh @@ -2951,34 +2951,36 @@ task soc_ifc_predictor::wdt_counter_task(); this.t2_count++; if (!($time % 500)) `uvm_info("PRED_WDT", $sformatf("In cascade mode. t2_count increments to 0x%x, wdt_to_period is 0x%x", this.t2_count, wdt_t2_period), UVM_DEBUG) - end - else begin - if (!this.wdt_nmi_intr_sent) begin - `uvm_info("PRED_WDT", "Timer2 expired in cascade mode. Expecting NMI to be handled", UVM_MEDIUM); - p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_HW_ERROR_FATAL.nmi_pin.predict(1'b1, -1, UVM_PREDICT_READ, UVM_PREDICT, p_soc_ifc_AHB_map); //TODO: use default map? - p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_STATUS.t2_timeout.predict(1'b1, -1, UVM_PREDICT_READ, UVM_PREDICT, p_soc_ifc_AHB_map); - - //Sending cptra_status_txn in the same clock as NMI - nmi_intr_pending = 1'b1; - populate_expected_cptra_status_txn(local_cptra_sb_ap_txn); - cptra_sb_ap.write(local_cptra_sb_ap_txn); - `uvm_info("PRED_WDT", "Transaction submitted through cptra_sb_ap", UVM_MEDIUM) - - // Fatal error interrupt is delayed by 1 cycle due to reg state - fork - configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(1); - if (!noncore_rst_out_asserted) begin - `uvm_info("PRED_WDT", "Watchdog timeout triggers cptra_error_fatal output", UVM_HIGH) - cptra_error_fatal = 1; - populate_expected_soc_ifc_status_txn(local_soc_ifc_sb_ap_txn); - soc_ifc_sb_ap.write(local_soc_ifc_sb_ap_txn); - `uvm_info("PRED_WDT", "Transaction submitted through soc_ifc_sb_ap", UVM_MEDIUM) - end - join_none - //Set a flag so we don't keep sending transactions while the timer holds value until interrupt - //is serviced or reset - this.wdt_nmi_intr_sent = 1'b1; + //If t2 count expires, send cptra_status_txn in the same clk + if (this.t2_count == wdt_t2_period) begin + if (!this.wdt_nmi_intr_sent) begin + `uvm_info("PRED_WDT", "Timer2 expired in cascade mode. Expecting NMI to be handled", UVM_MEDIUM); + p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_HW_ERROR_FATAL.nmi_pin.predict(1'b1, -1, UVM_PREDICT_READ, UVM_PREDICT, p_soc_ifc_AHB_map); //TODO: use default map? + p_soc_ifc_rm.soc_ifc_reg_rm.CPTRA_WDT_STATUS.t2_timeout.predict(1'b1, -1, UVM_PREDICT_READ, UVM_PREDICT, p_soc_ifc_AHB_map); + + //Sending cptra_status_txn in the same clock as NMI + nmi_intr_pending = 1'b1; + populate_expected_cptra_status_txn(local_cptra_sb_ap_txn); + cptra_sb_ap.write(local_cptra_sb_ap_txn); + `uvm_info("PRED_WDT", "Transaction submitted through cptra_sb_ap", UVM_MEDIUM) + + // Fatal error interrupt is delayed by 1 cycle due to reg state + fork + configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(1); + if (!noncore_rst_out_asserted) begin + `uvm_info("PRED_WDT", "Watchdog timeout triggers cptra_error_fatal output", UVM_HIGH) + cptra_error_fatal = 1; + populate_expected_soc_ifc_status_txn(local_soc_ifc_sb_ap_txn); + soc_ifc_sb_ap.write(local_soc_ifc_sb_ap_txn); + `uvm_info("PRED_WDT", "Transaction submitted through soc_ifc_sb_ap", UVM_MEDIUM) + end + join_none + + //Set a flag so we don't keep sending transactions while the timer holds value until interrupt + //is serviced or reset + this.wdt_nmi_intr_sent = 1'b1; + end end end end From ecd5319a5ff2299fd66dd8a9b6bb9644123728b9 Mon Sep 17 00:00:00 2001 From: Mojtaba Bisheh Niasar Date: Wed, 20 Sep 2023 23:05:18 +0000 Subject: [PATCH 02/11] Merged PR 125379: added message reduction added message reduction Related work items: #554637 --- src/ecc/rtl/ecc_dsa_ctrl.sv | 20 ++++++++++++++++++-- src/ecc/tb/test_vectors/ecc_drbg_mbedtls.hex | 18 +++++++++--------- 2 files changed, 27 insertions(+), 11 deletions(-) diff --git a/src/ecc/rtl/ecc_dsa_ctrl.sv b/src/ecc/rtl/ecc_dsa_ctrl.sv index 48eb05af2..fd4c98c81 100644 --- a/src/ecc/rtl/ecc_dsa_ctrl.sv +++ b/src/ecc/rtl/ecc_dsa_ctrl.sv @@ -129,6 +129,7 @@ module ecc_dsa_ctrl logic [1 : 0] cmd_reg; logic [2 : 0] pm_cmd_reg; logic [REG_NUM_DWORDS-1 : 0][RADIX-1:0] msg_reg; + logic [REG_NUM_DWORDS-1 : 0][RADIX-1:0] msg_reduced_reg; logic [REG_NUM_DWORDS-1 : 0][RADIX-1:0] privkey_reg; logic [REG_NUM_DWORDS-1 : 0][RADIX-1:0] kv_reg; logic [REG_NUM_DWORDS-1 : 0][RADIX-1:0] pubkeyx_reg; @@ -263,7 +264,7 @@ module ecc_dsa_ctrl .keygen_seed(seed_reg), .keygen_nonce(nonce_reg), .privKey(privkey_reg), - .hashed_msg(msg_reg), + .hashed_msg(msg_reduced_reg), .IV(IV_reg), .lambda(lambda), .scalar_rnd(scalar_rnd_reg), @@ -435,6 +436,21 @@ module ecc_dsa_ctrl hwif_in.ECC_IV[dword].IV.hwclr = zeroize_reg; end end + + //transformed msg into modulo q + always_ff @(posedge clk or negedge reset_n) + begin : reduced_msg + if (!reset_n) + msg_reduced_reg <= '0; + else if (zeroize_reg) + msg_reduced_reg <= '0; + else begin + if (msg_reg >= GROUP_ORDER) + msg_reduced_reg <= msg_reg - GROUP_ORDER; + else + msg_reduced_reg <= msg_reg; + end + end always_comb hwif_in.ECC_CTRL.CTRL.hwclr = |hwif_out.ECC_CTRL.CTRL.value; @@ -564,7 +580,7 @@ module ecc_dsa_ctrl CONST_G_Y_MONT_ID : write_reg = {zero_pad, G_Y_MONT}; CONST_R2_q_MONT_ID : write_reg = {zero_pad, R2_q_MONT}; CONST_ONE_q_MONT_ID : write_reg = {zero_pad, ONE_q_MONT}; - MSG_ID : write_reg = {zero_pad, msg_reg}; + MSG_ID : write_reg = {zero_pad, msg_reduced_reg}; PRIVKEY_ID : write_reg = {zero_pad, privkey_reg}; PUBKEYX_ID : write_reg = {zero_pad, pubkeyx_reg}; PUBKEYY_ID : write_reg = {zero_pad, pubkeyy_reg}; diff --git a/src/ecc/tb/test_vectors/ecc_drbg_mbedtls.hex b/src/ecc/tb/test_vectors/ecc_drbg_mbedtls.hex index 03bb042c5..e2a501f0a 100644 --- a/src/ecc/tb/test_vectors/ecc_drbg_mbedtls.hex +++ b/src/ecc/tb/test_vectors/ecc_drbg_mbedtls.hex @@ -8,15 +8,15 @@ BB9C3A2F061E8D7014278DD51E66A918A6B6F9F1C1937312D4E7A921B18EF0F41FDD401D9E771850 E548E535A1CC600E133B5591AEBAAD78054006D752D0E1DF94FBFA95D78F0B3F8E81B9119C2BE008BF6D6F4E4185F87D 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 0 -C8F518D4F3AA1BD46ED56C1C3C9E16FB800AF504DB98843548C5F623EE115F73D4C62ABC06D303B5D90D9A175087290D -F274F69D163B0C9F1FC3EBF4292AD1C4EB3CEC1C5A7DDE6F80C14292934C2055E087748D0A169C772483ADEE5EE70E17 -D79C6D972B34A1DFC916A7B6E0A99B6B5387B34DA2187607C1AD0A4D1A8C2E4172AB5FA5D9AB58FE45E43F56BBB66BA4 -5A7363932B06B4F223BEF0B60A6390265112DBBD0AAE67FEF26B465BE935B48E451E68D16F1118F2B32B4C28608749ED -8FA8541C82A392CA74F23ED1DBFD73541C5966391B97EA73D744B0E34B9DF59ED0158063E39C09A5A055371EDF7A5441 -1B7EC5E548E8AAA92EC77097CA9551C9783CE682CA18FB1EDBD9F1E50BC382DB8AB39496C8EE423F8CA105CBBA7B6588 -871E6EA4DDC5432CDDAA60FD7F055472D3C4DD41A5BFB26709E88C311A97093599A7C8F55B3974C19E4F5A7BFC1DD2AC -3E5552DE6403350EE70AD74E4B854D2DC4126BBF9C153A5D7A07BD4B85D06E45F850920E898FB7D34F80796DAE29365C -3401CEFAE20A737649073AC1A351E32926DB9ED0DB6B1CFFAB0493DAAFB93DDDD83EDEA28A803D0D003B2633B9D0F1BF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +30802CFC9EACEA478B8511604CC9B0734281CE9C65B6D3DA1B07D6D71E9AA58E5B03509F3F1D09A39F693E376CD0EF69 +0341F64BAB8B41B7D11486CBD84EF8A9B00F5C0112CC9093B0166B9D93D571B4C1EE38C477CCEE73C651596F2F4AAFED +6E39A8A85D42EDA0442B3C3B9C6B5E16E21392EDBA702C2530808C9D975FD9FD9E345710884A031EA542D351192C60C7 +EB7A88B7A05EF13B3F3582438B8C7B8C0D5DCB8E972EF2D40C22059E95129FCDE7F75D35210C1DB6A619747E3BCC3FB1 +F36220929C3BABAF12008CB1DDF360CE533AF62368567E47187CFBC69D8BBEA8EB05ACF32752FE0B4077D1B76EE22155 +D11935F6710CF706500AE86DD1953017949984CABFC1C1D113FCC340D6C0CA4023659D54F774B18EA50D310297FFE1C2 +E1AF7B6C1012EE82575B883CC41BBBD4F052892DD3455B3D9B4B3F6A35A2C1637CFD623E3AB73949B74A61A75AE85B19 +F287851824D8C8DE17291A89F053A60D33DC29600E2D1654B58085A8AA8969E3195B9EAF649C069A28295260497B2521 1 5F1C0F632D10524D84F4BD20C9ADDAD795CDF5DAA60EA1217A00DD7B1ECAD268C23CC6D7F258E3747A5E4299893F8C37 C9DA896F656439AE83BCA037496DC001CB1F8F0FC9AB9C3C1723768352399E4BF5F44A60E84C2567B88C32569342B706 From 86a41e688359cb5206a3b201a1157b0d70757e17 Mon Sep 17 00:00:00 2001 From: Kiran Upadhyayula Date: Fri, 22 Sep 2023 00:17:42 +0000 Subject: [PATCH 03/11] Merged PR 125576: Increase WDT timer timeout value Enforce a minimum of 5 clks on timer timeout values for WDT tests to avoid transaction mismatches Related work items: #555119 --- src/integration/test_suites/caliptra_rt/caliptra_rt.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/integration/test_suites/caliptra_rt/caliptra_rt.c b/src/integration/test_suites/caliptra_rt/caliptra_rt.c index 5474d3032..b8968fc00 100644 --- a/src/integration/test_suites/caliptra_rt/caliptra_rt.c +++ b/src/integration/test_suites/caliptra_rt/caliptra_rt.c @@ -173,8 +173,9 @@ void caliptra_rt() { lsu_write_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R, SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK); //Program timer1 and 2 periods to <= 0x100 to test NMI generation - wdt_rand_t1_val = rand() % 0x100; - wdt_rand_t2_val = rand() % 0x100; + wdt_rand_t1_val = (rand() % 0x100) + 0x5; + wdt_rand_t2_val = (rand() % 0x100) + 0x5; + //WDT cascade mode with t2 timeout lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_EN, !SOC_IFC_REG_CPTRA_WDT_TIMER2_EN_TIMER2_EN_MASK); lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0, wdt_rand_t1_val); From 3c503cc82a63561c73a7ea7223b8e9caaf7d6b1a Mon Sep 17 00:00:00 2001 From: Kiran Upadhyayula Date: Fri, 22 Sep 2023 19:30:27 +0000 Subject: [PATCH 04/11] Merged PR 125587: KV clear prediction fix, debug x AHB sequence, convert rst cross cps to cover props 1. Emulate the 1 cycle delay in clear function 2. Add more scenarios to debug sequence 3. Rst cross coverpoints never get hit, converting to cover properties for better coverage Related work items: #532848 --- src/keyvault/coverage/keyvault_cov_if.sv | 19 +-- src/keyvault/coverage/keyvault_cov_props.sv | 67 ++++++++ .../src/kv_rand_debug_test_sequence.svh | 28 +++- .../src/kv_rand_wr_rd_test_sequence.svh | 3 + .../kv_env_pkg/kv_env_pkg.sv | 3 +- .../registers/kv_reg_model_top_pkg.sv | 28 ++++ .../kv_env_pkg/src/kv_ahb_sequence.svh | 15 +- .../src/kv_env_debug_on_sequence.svh | 148 ++++++++++++++++++ .../kv_env_pkg/src/kv_predictor.svh | 144 ++++++++++++++--- .../kv_env_pkg/src/kv_reg_predictor.svh | 6 +- .../src/kv_wr_rd_debug_sequence.svh | 23 ++- .../kv_env_pkg/src/kv_wr_rd_lock_sequence.svh | 62 +++----- .../kv_rst_pkg/kv_rst_pkg.sv | 2 + .../src/kv_rst_debug_off_sequence.svh | 68 ++++++++ .../src/kv_rst_debug_on_sequence.svh | 69 ++++++++ 15 files changed, 596 insertions(+), 89 deletions(-) create mode 100644 src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_env_debug_on_sequence.svh create mode 100644 src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_debug_off_sequence.svh create mode 100644 src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_debug_on_sequence.svh diff --git a/src/keyvault/coverage/keyvault_cov_if.sv b/src/keyvault/coverage/keyvault_cov_if.sv index f896c3d02..bf0979c4a 100644 --- a/src/keyvault/coverage/keyvault_cov_if.sv +++ b/src/keyvault/coverage/keyvault_cov_if.sv @@ -101,21 +101,22 @@ interface keyvault_cov_if debugXclear: cross debug, clear; debugXlock_wrXlock_useXclear: cross debug, lock_wr, lock_use, clear; debugXclear_secrets: cross debug, cp_clear_secrets_wr, cp_clear_secrets_sel; + debugXkv_write: cross debug, kv_write_en; //Cover warm reset assertion while regs are locked/cleared - lock_wrXwarm_rst: cross lock_wr, rst_b; - lock_useXwarm_rst: cross lock_use, rst_b; - clearXwarm_rst: cross clear, rst_b; + // lock_wrXwarm_rst: cross lock_wr, rst_b; + // lock_useXwarm_rst: cross lock_use, rst_b; + // clearXwarm_rst: cross clear, rst_b; //Cover cold reset while regs are locked/cleared - lock_wrXcold_rst: cross lock_wr, cptra_pwrgood; - lock_useXcold_rst: cross lock_use, cptra_pwrgood; - clearXcold_rst: cross clear, cptra_pwrgood; + // lock_wrXcold_rst: cross lock_wr, cptra_pwrgood; + // lock_useXcold_rst: cross lock_use, cptra_pwrgood; + // clearXcold_rst: cross clear, cptra_pwrgood; //Cover core reset while regs are locked/cleared - lock_wrXcore_rst: cross lock_wr, core_only_rst_b; - lock_useXcore_rst: cross lock_use, core_only_rst_b; - clearXcore_rst: cross clear, core_only_rst_b; + // lock_wrXcore_rst: cross lock_wr, core_only_rst_b; + // lock_useXcore_rst: cross lock_use, core_only_rst_b; + // clearXcore_rst: cross clear, core_only_rst_b; //Cover simultaneous locks/clear settings lock_wrXlock_useXclearXclear_secrets: cross lock_wr, lock_use, clear, cp_clear_secrets_wr, cp_clear_secrets_sel; diff --git a/src/keyvault/coverage/keyvault_cov_props.sv b/src/keyvault/coverage/keyvault_cov_props.sv index f1ea9b9b7..4ee35a38d 100644 --- a/src/keyvault/coverage/keyvault_cov_props.sv +++ b/src/keyvault/coverage/keyvault_cov_props.sv @@ -33,21 +33,88 @@ module keyvault_cov_props generate for(genvar i = 0; i < KV_NUM_KEYS; i++) begin + //------------------------------------------------------------------------------ //lock write => clear secrets => warm reset in next clk //Expectation: Keys will be flushed since reset is not seen until next clk, locks are reset + //------------------------------------------------------------------------------ property cover_prop_locks_clear_secr_warm_rst; @(posedge dut.clk) (dut.kv_reg_hwif_out.KEY_CTRL[i].lock_wr && dut.kv_reg_hwif_out.CLEAR_SECRETS.wr_debug_values |-> ##[1:$] !dut.rst_b); endproperty covprop_lock_clear_secr_warmrst: cover property(cover_prop_locks_clear_secr_warm_rst); + //------------------------------------------------------------------------------ //lock write => clear secrets => cold reset in next clk //Expectation: Keys will be flushed since reset is not seen until next clk, locks and keys are reset once cold reset happens + //------------------------------------------------------------------------------ property cover_prop_locks_clear_secr_cold_rst; @(posedge dut.clk) (dut.kv_reg_hwif_out.KEY_CTRL[i].lock_wr && dut.kv_reg_hwif_out.CLEAR_SECRETS.wr_debug_values |-> ##[1:$] !dut.cptra_pwrgood); endproperty covprop_lock_clear_secr_coldrst: cover property(cover_prop_locks_clear_secr_cold_rst); + + //------------------------------------------------------------------------------ + //Check that locks/clear were set before issuing warm reset + //------------------------------------------------------------------------------ + property cover_prop_lock_wr_warmrst; + @(posedge dut.clk) + (dut.kv_reg_hwif_out.KEY_CTRL[i].lock_wr |-> ##[0:$] !dut.rst_b); + endproperty + covprop_lock_wr_warmrst: cover property(cover_prop_lock_wr_warmrst); + + property cover_prop_lock_use_warmrst; + @(posedge dut.clk) + (dut.kv_reg_hwif_out.KEY_CTRL[i].lock_use |-> ##[0:$] !dut.rst_b); + endproperty + covprop_lock_use_warmrst: cover property(cover_prop_lock_use_warmrst); + + property cover_prop_clear_warmrst; + @(posedge dut.clk) + (dut.kv_reg_hwif_out.KEY_CTRL[i].clear |-> ##[0:$] !dut.rst_b); + endproperty + covprop_clear_warmrst: cover property(cover_prop_clear_warmrst); + + //------------------------------------------------------------------------------ + //Check that locks/clear were set before issuing cold reset + //------------------------------------------------------------------------------ + property cover_prop_lock_wr_coldrst; + @(posedge dut.clk) + (dut.kv_reg_hwif_out.KEY_CTRL[i].lock_wr |-> ##[0:$] !dut.cptra_pwrgood); + endproperty + covprop_lock_wr_coldrst: cover property(cover_prop_lock_wr_coldrst); + + property cover_prop_lock_use_coldrst; + @(posedge dut.clk) + (dut.kv_reg_hwif_out.KEY_CTRL[i].lock_use |-> ##[0:$] !dut.cptra_pwrgood); + endproperty + covprop_lock_use_coldrst: cover property(cover_prop_lock_use_coldrst); + + property cover_prop_clear_coldrst; + @(posedge dut.clk) + (dut.kv_reg_hwif_out.KEY_CTRL[i].clear |-> ##[0:$] !dut.cptra_pwrgood); + endproperty + covprop_clear_coldrst: cover property(cover_prop_clear_coldrst); + + //------------------------------------------------------------------------------ + //Check that locks/clear were set before issuing core reset + //------------------------------------------------------------------------------ + property cover_prop_lock_wr_corerst; + @(posedge dut.clk) + (dut.kv_reg_hwif_out.KEY_CTRL[i].lock_wr |-> ##[0:$] !dut.core_only_rst_b); + endproperty + covprop_lock_wr_corerst: cover property(cover_prop_lock_wr_corerst); + + property cover_prop_lock_use_corerst; + @(posedge dut.clk) + (dut.kv_reg_hwif_out.KEY_CTRL[i].lock_use |-> ##[0:$] !dut.core_only_rst_b); + endproperty + covprop_lock_use_corerst: cover property(cover_prop_lock_use_corerst); + + property cover_prop_clear_corerst; + @(posedge dut.clk) + (dut.kv_reg_hwif_out.KEY_CTRL[i].clear |-> ##[0:$] !dut.core_only_rst_b); + endproperty + covprop_clear_corerst: cover property(cover_prop_clear_corerst); end endgenerate diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/sequences/src/kv_rand_debug_test_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/sequences/src/kv_rand_debug_test_sequence.svh index 15d6b3fbf..2735d0063 100644 --- a/src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/sequences/src/kv_rand_debug_test_sequence.svh +++ b/src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/sequences/src/kv_rand_debug_test_sequence.svh @@ -65,6 +65,9 @@ class kv_rand_debug_test_sequence extends kv_bench_sequence_base; typedef kv_wr_rd_debug_sequence #(.CONFIG_T(kv_env_configuration_t)) kv_wr_rd_debug_sequence_t; rand kv_wr_rd_debug_sequence_t kv_wr_rd_debug_seq; + typedef kv_env_debug_on_sequence #(.CONFIG_T(kv_env_configuration_t)) kv_env_debug_on_sequence_t; + rand kv_env_debug_on_sequence_t kv_env_debug_on_seq; + typedef kv_wr_rd_debug_lock_sequence #(.CONFIG_T(kv_env_configuration_t)) kv_wr_rd_debug_lock_sequence_t; rand kv_wr_rd_debug_lock_sequence_t kv_wr_rd_debug_lock_seq; @@ -80,6 +83,9 @@ class kv_rand_debug_test_sequence extends kv_bench_sequence_base; typedef kv_wr_rd_debug_core_rst_sequence #(.CONFIG_T(kv_env_configuration_t)) kv_wr_rd_debug_core_rst_sequence_t; rand kv_wr_rd_debug_core_rst_sequence_t kv_wr_rd_debug_core_rst_seq; + typedef kv_ahb_sequence #(.CONFIG_T(kv_env_configuration_t)) kv_ahb_sequence_t; + rand kv_ahb_sequence_t kv_ahb_seq; + //Responder sequences: typedef kv_read_responder_sequence kv_hmac_key_read_agent_responder_seq_t; kv_hmac_key_read_agent_responder_seq_t kv_hmac_key_read_agent_responder_seq; @@ -90,6 +96,7 @@ class kv_rand_debug_test_sequence extends kv_bench_sequence_base; virtual task body(); + kv_rst_poweron_seq = kv_rst_poweron_sequence_t::type_id::create("kv_rst_poweron_seq"); kv_wr_rd_seq = kv_wr_rd_sequence_t::type_id::create("kv_wr_rd_seq"); kv_wr_rd_rst_seq = kv_wr_rd_rst_sequence_t::type_id::create("kv_wr_rd_rst_seq"); kv_wr_rd_cold_rst_seq = kv_wr_rd_cold_rst_sequence_t::type_id::create("kv_wr_rd_cold_rst_seq"); @@ -99,12 +106,16 @@ class kv_rand_debug_test_sequence extends kv_bench_sequence_base; kv_wr_rd_lock_cold_rst_seq = kv_wr_rd_lock_cold_rst_sequence_t::type_id::create("kv_wr_rd_lock_cold_rst_seq"); kv_wr_rd_lock_core_rst_seq = kv_wr_rd_lock_core_rst_sequence_t::type_id::create("kv_wr_rd_lock_core_rst_seq"); kv_wr_rd_debug_seq = kv_wr_rd_debug_sequence_t::type_id::create("kv_wr_rd_debug_seq"); + kv_env_debug_on_seq = kv_env_debug_on_sequence_t::type_id::create("kv_env_debug_on_seq"); kv_wr_rd_debug_lock_seq = kv_wr_rd_debug_lock_sequence_t::type_id::create("kv_wr_rd_debug_lock_seq"); kv_wr_rd_debug_lock_clear_rst_seq = kv_wr_rd_debug_lock_clear_rst_sequence_t::type_id::create("kv_wr_rd_debug_lock_clear_rst_seq"); kv_wr_rd_debug_warm_rst_seq = kv_wr_rd_debug_warm_rst_sequence_t::type_id::create("kv_wr_rd_debug_warm_rst_seq"); kv_wr_rd_debug_cold_rst_seq = kv_wr_rd_debug_cold_rst_sequence_t::type_id::create("kv_wr_rd_debug_cold_rst_seq"); kv_wr_rd_debug_core_rst_seq = kv_wr_rd_debug_core_rst_sequence_t::type_id::create("kv_wr_rd_debug_core_rst_seq"); + kv_ahb_seq = kv_ahb_sequence_t::type_id::create("kv_ahb_seq"); + if(!kv_rst_poweron_seq.randomize()) + `uvm_fatal("KV POWERON SEQ", "Failed to randomize KV RST poweron seq"); if(!kv_wr_rd_seq.randomize()) `uvm_fatal("KV WR RD SEQ", "kv_rand_debug_test_sequence::body() - kv_wr_rd_seq randomization failed"); if(!kv_key_wr_rd_basic_seq.randomize()) @@ -115,11 +126,24 @@ class kv_rand_debug_test_sequence extends kv_bench_sequence_base; `uvm_fatal("KV WR RD COLD RST SEQ", "kv_rand_debug_test_sequence::body() - kv_wr_rd_cold_rst_seq randomization failed"); if(!kv_wr_rd_lock_seq.randomize()) `uvm_fatal("KV_WR_RD_LOCK_SEQ", "kv_rand_debug_test_sequence::body() - kv_wr_rd_lock_seq randomization failed"); + if(!kv_ahb_seq.randomize()) + `uvm_fatal("KV_AHB_SEQ", "kv_ahb_sequence::body() - kv_ahb_seq randomization failed"); + if(!kv_env_debug_on_seq.randomize()) + `uvm_fatal("KV_ENV_DEBUG_ON SEQ", "kv_rand_debug_test_sequence::body() - kv_env_debug_on_seq randomization failed"); reg_model.reset(); + `uvm_info("TOP", "AHB stop sequences", UVM_MEDIUM) + reg_model.kv_AHB_map.get_sequencer().stop_sequences(); + `uvm_info("TOP", "HMAC key read stop sequences", UVM_MEDIUM) + reg_model.kv_hmac_key_read_map.get_sequencer().stop_sequences(); + `uvm_info("TOP", "Poweron Sequence", UVM_MEDIUM) + kv_rst_poweron_seq.start(top_configuration.kv_rst_agent_config.sequencer); + - `uvm_info("TOP", "DEBUG sequence",UVM_MEDIUM); - kv_wr_rd_debug_seq.start(top_configuration.vsqr); + `uvm_info("TOP", "DEBUG on sequence", UVM_MEDIUM) + kv_env_debug_on_seq.start(top_configuration.vsqr); + `uvm_info("TOP", "AHB sequence", UVM_MEDIUM) + kv_ahb_seq.start(top_configuration.vsqr); `uvm_info("TOP", "DEBUG lock sequence",UVM_MEDIUM); kv_wr_rd_debug_lock_seq.start(top_configuration.vsqr); `uvm_info("TOP", "DEBUG warm rst sequence",UVM_MEDIUM); diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/sequences/src/kv_rand_wr_rd_test_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/sequences/src/kv_rand_wr_rd_test_sequence.svh index 897bce4e1..a95571f87 100644 --- a/src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/sequences/src/kv_rand_wr_rd_test_sequence.svh +++ b/src/keyvault/uvmf_kv/uvmf_template_output/project_benches/kv/tb/sequences/src/kv_rand_wr_rd_test_sequence.svh @@ -44,6 +44,9 @@ class kv_rand_wr_rd_test_sequence extends kv_bench_sequence_base; typedef kv_key_wr_rd_basic_sequence #(.CONFIG_T(kv_env_configuration_t))kv_key_wr_rd_basic_sequence_t; rand kv_key_wr_rd_basic_sequence_t kv_key_wr_rd_basic_seq; + // typedef kv_key_wr_rd_single_sequence #(.CONFIG_T(kv_env_configuration_t))kv_key_wr_rd_single_sequence_t; + // rand kv_key_wr_rd_single_sequence_t kv_key_wr_rd_single_seq; + typedef kv_wr_rd_rst_sequence #(.CONFIG_T(kv_env_configuration_t))kv_wr_rd_rst_sequence_t; rand kv_wr_rd_rst_sequence_t kv_wr_rd_rst_seq; diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/kv_env_pkg.sv b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/kv_env_pkg.sv index afa6d0c14..5d8d7558e 100644 --- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/kv_env_pkg.sv +++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/kv_env_pkg.sv @@ -107,6 +107,7 @@ package kv_env_pkg; `include "src/kv_scoreboard.svh" `include "src/kv_environment.svh" `include "src/kv_env_sequence_base.svh" + `include "src/kv_ahb_sequence.svh" `include "src/kv_wr_rd_sequence.svh" `include "src/kv_wr_rd_rst_sequence.svh" `include "src/kv_wr_rd_cold_rst_sequence.svh" @@ -116,12 +117,12 @@ package kv_env_pkg; `include "src/kv_wr_rd_lock_cold_rst_sequence.svh" `include "src/kv_wr_rd_lock_core_rst_sequence.svh" `include "src/kv_wr_rd_debug_sequence.svh" + `include "src/kv_env_debug_on_sequence.svh" `include "src/kv_wr_rd_debug_lock_sequence.svh" `include "src/kv_wr_rd_debug_lock_clear_rst_sequence.svh" `include "src/kv_wr_rd_debug_warm_rst_sequence.svh" `include "src/kv_wr_rd_debug_cold_rst_sequence.svh" `include "src/kv_wr_rd_debug_core_rst_sequence.svh" - `include "src/kv_ahb_sequence.svh" // pragma uvmf custom package_item_additional begin // UVMF_CHANGE_ME : When adding new environment level sequences to the src directory diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/registers/kv_reg_model_top_pkg.sv b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/registers/kv_reg_model_top_pkg.sv index 0132574a6..79c3706ef 100644 --- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/registers/kv_reg_model_top_pkg.sv +++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/registers/kv_reg_model_top_pkg.sv @@ -110,6 +110,11 @@ package kv_reg_model_top_pkg; endclass : kv_reg_ext + // //Callbacks + // `include "kv_reg_delay_job.svh" + // `include "kv_reg_cbs_kv_reg_KEY_ENTRY_data.svh" + + //-------------------------------------------------------------------- // Class: kv_example_reg0 // @@ -316,6 +321,11 @@ package kv_reg_model_top_pkg; uvm_reg_map kv_ecc_privkey_read_map; uvm_reg_map kv_ecc_seed_read_map; + int ii, jj; + + // //Callbacks + // kv_reg_cbs_kv_reg_KEY_ENTRY_data KEY_ENTRY_data_cb; + // uvm_queue #(kv_reg_delay_job) delay_jobs; //TODO add coverage for the other maps // kv_ahb_map_coverage ahb_map_cg; @@ -325,6 +335,16 @@ package kv_reg_model_top_pkg; super.new(name, build_coverage(UVM_CVR_ALL)); endfunction + // Function: reset + // + // function void reset(string kind = "HARD"); + // super.reset(kind); + // if (kind == "HARD") begin + // `uvm_info("KV_REG_MODEL_TOP", {"Reset of kind ", kind, " results in delay_jobs being cleared"}, UVM_HIGH) + // delay_jobs.delete(); + // end + // endfunction + // Function: build // virtual function void build(); @@ -344,6 +364,9 @@ package kv_reg_model_top_pkg; // example_reg1.configure(this, null, "example_reg1"); // example_reg1.build(); + // delay_jobs = new("delay_jobs"); + // uvm_config_db#(uvm_queue#(kv_reg_delay_job))::set(null, "kv_reg_model_top", "delay_jobs", delay_jobs); + val_reg = kv_val_reg::type_id::create("val_reg"); val_reg.configure(this,null,"val_reg"); val_reg.build(); @@ -366,6 +389,11 @@ package kv_reg_model_top_pkg; this.kv_reg_rm.configure(this); this.kv_reg_rm.build(); + // //Add callbacks + // KEY_ENTRY_data_cb = kv_reg_cbs_kv_reg_KEY_ENTRY_data::type_id::create("KEY_ENTRY_data_cb"); + + // foreach (kv_reg_rm.KEY_ENTRY[ii][jj]) uvm_reg_field_cb::add(kv_reg_rm.KEY_ENTRY[ii][jj].data, KEY_ENTRY_data_cb); + this.default_map = create_map("kv_default_map", 0, 4, UVM_LITTLE_ENDIAN); this.default_map.add_submap(this.kv_reg_rm.default_map, 0); diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_ahb_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_ahb_sequence.svh index 3867b3b62..5e4a5dcc3 100644 --- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_ahb_sequence.svh +++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_ahb_sequence.svh @@ -52,20 +52,15 @@ class kv_ahb_sequence #( // 1 <= iter <= 5; // }; iter = 1; - //Issue reset - if(configuration.kv_rst_agent_config.sequencer != null) - kv_rst_agent_poweron_seq.start(configuration.kv_rst_agent_config.sequencer); - else - `uvm_error("KV AHB", "kv_rst_agent_config.sequencer is null!") //KEY ENTRY reg writes for (i = 0; i < iter; i++) begin for(entry = 0; entry < KV_NUM_KEYS; entry++) begin - for (offset = 0; offset < KV_NUM_DWORDS; offset++) begin - std::randomize(wr_data); - reg_model.kv_reg_rm.KEY_ENTRY[entry][offset].write(sts, wr_data, UVM_FRONTDOOR, reg_model.kv_AHB_map, this); - assert(sts == UVM_IS_OK) else `uvm_error("KV AHB", $sformatf("Failed when writing to KEY[%d][%d] entry",entry, offset)) - end + // for (offset = 0; offset < KV_NUM_DWORDS; offset++) begin + std::randomize(wr_data) with {wr_data <= 'h7;}; + reg_model.kv_reg_rm.KEY_CTRL[entry].write(sts, wr_data, UVM_FRONTDOOR, reg_model.kv_AHB_map, this); + assert(sts == UVM_IS_OK) else `uvm_error("KV AHB", $sformatf("Failed when writing to KEY[%d] entry",entry)) + // end end end diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_env_debug_on_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_env_debug_on_sequence.svh new file mode 100644 index 000000000..08e441629 --- /dev/null +++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_env_debug_on_sequence.svh @@ -0,0 +1,148 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: Performs KV writes and reads while randomly issuing debug unlock +// via input pin or CLEAR_SECRETS reg. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class kv_env_debug_on_sequence #( + type CONFIG_T +) extends kv_env_sequence_base #(.CONFIG_T(CONFIG_T)); + + `uvm_object_param_utils(kv_env_debug_on_sequence #(CONFIG_T)); + + typedef kv_rst_poweron_sequence kv_rst_agent_poweron_sequence_t; + kv_rst_agent_poweron_sequence_t kv_rst_agent_poweron_seq; + kv_rst_agent_poweron_sequence_t kv_rst_agent_poweron_seq_2; + + typedef kv_rst_debug_sequence kv_rst_agent_debug_sequence_t; + kv_rst_agent_debug_sequence_t kv_rst_agent_debug_seq; + typedef kv_rst_debug_on_sequence kv_rst_agent_debug_on_sequence_t; + kv_rst_agent_debug_on_sequence_t kv_rst_agent_debug_on_seq; + typedef kv_rst_debug_off_sequence kv_rst_agent_debug_off_sequence_t; + kv_rst_agent_debug_off_sequence_t kv_rst_agent_debug_off_seq; + + typedef kv_write_key_entry_sequence kv_write_agent_key_entry_sequence_t; + kv_write_agent_key_entry_sequence_t hmac_write_seq; + kv_write_agent_key_entry_sequence_t sha512_write_seq; + kv_write_agent_key_entry_sequence_t ecc_write_seq; + kv_write_agent_key_entry_sequence_t doe_write_seq; + + typedef kv_read_key_entry_sequence kv_read_agent_key_entry_sequence_t; + kv_read_agent_key_entry_sequence_t hmac_key_read_seq; + kv_read_agent_key_entry_sequence_t hmac_block_read_seq; + kv_read_agent_key_entry_sequence_t sha512_block_read_seq; + kv_read_agent_key_entry_sequence_t ecc_privkey_read_seq; + kv_read_agent_key_entry_sequence_t ecc_seed_read_seq; + + rand reg [KV_ENTRY_ADDR_W-1:0] hmac_write_entry, sha512_write_entry, ecc_write_entry, doe_write_entry; + rand int unsigned wait_cycles_from_seq; + rand bit debug_type; + rand reg [1:0] clear_secrets_data; + + typedef enum {SECURITY_STATE, CLEAR_SECRETS} debug_inputs; + + function new(string name = ""); + super.new(name); + kv_rst_agent_poweron_seq = kv_rst_agent_poweron_sequence_t::type_id::create("kv_rst_agent_poweron_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_DEBUG_ON", "Failed to randomize KV RST poweron seq"); + kv_rst_agent_poweron_seq_2 = kv_rst_agent_poweron_sequence_t::type_id::create("kv_rst_agent_poweron_seq_2"); + if(!this.randomize()) `uvm_error("KV_ENV_DEBUG_ON", "Failed to randomize KV RST poweron seq"); + + kv_rst_agent_debug_seq = kv_rst_agent_debug_sequence_t::type_id::create("kv_rst_agent_debug_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_DEBUG_ON", "Failed to randomize KV RST debug seq"); + kv_rst_agent_debug_on_seq = kv_rst_agent_debug_on_sequence_t::type_id::create("kv_rst_agent_debug_on_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_DEBUG_ON", "Failed to randomize KV RST debug on seq"); + kv_rst_agent_debug_off_seq = kv_rst_agent_debug_off_sequence_t::type_id::create("kv_rst_agent_debug_off_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_DEBUG_ON", "Failed to randomize KV RST debug off seq"); + + hmac_write_seq = kv_write_agent_key_entry_sequence_t::type_id::create("hmac_write_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_DEBUG_ON", "Failed to randomize KV WRITE seq"); + sha512_write_seq = kv_write_agent_key_entry_sequence_t::type_id::create("sha512_write_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_DEBUG_ON", "Failed to randomize KV WRITE seq"); + ecc_write_seq = kv_write_agent_key_entry_sequence_t::type_id::create("ecc_write_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_DEBUG_ON", "Failed to randomize KV WRITE seq"); + doe_write_seq = kv_write_agent_key_entry_sequence_t::type_id::create("doe_write_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_DEBUG_ON", "Failed to randomize KV WRITE seq"); + + hmac_key_read_seq = kv_read_agent_key_entry_sequence_t::type_id::create("hmac_key_read_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_DEBUG_ON", "Failed to randomize KV READ seq"); + hmac_block_read_seq = kv_read_agent_key_entry_sequence_t::type_id::create("hmac_block_read_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_DEBUG_ON", "Failed to randomize KV READ seq"); + sha512_block_read_seq = kv_read_agent_key_entry_sequence_t::type_id::create("sha512_block_read_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_DEBUG_ON", "Failed to randomize KV READ seq"); + ecc_privkey_read_seq = kv_read_agent_key_entry_sequence_t::type_id::create("ecc_privkey_read_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_DEBUG_ON", "Failed to randomize KV READ seq"); + ecc_seed_read_seq = kv_read_agent_key_entry_sequence_t::type_id::create("ecc_seed_read_seq"); + if(!this.randomize()) `uvm_error("KV_ENV_DEBUG_ON", "Failed to randomize KV READ seq"); + //kv_rst_agent_poweron_seq_2 = kv_rst_agent_poweron_sequence_t::type_id::create("kv_rst_agent_poweron_seq_2"); + endfunction + + virtual task body(); + uvm_status_e sts; + //uvm_reg_data_t rd_data; + int write_entry = 0; + int write_offset = 0; + int read_entry = 0; + int read_offset = 0; + reg [31:0] wr_data, rd_data; + reg_model = configuration.kv_rm; + + + //Issue and wait for reset + // if(configuration.kv_rst_agent_config.sequencer != null) + // kv_rst_agent_poweron_seq.start(configuration.kv_rst_agent_config.sequencer); + // else + // `uvm_error("KV_ENV_DEBUG_ON", "kv_rst_agent_config.sequencer is null!") + + + //Unlock debug mode or clear secrets randomly + + // std::randomize(debug_type); //0 - security state, 1 - clear secrets + debug_type = 0; + + std::randomize(wait_cycles_from_seq) with { + wait_cycles_from_seq >= 5; + wait_cycles_from_seq <= 100; + }; + + std::randomize(clear_secrets_data); //wren, debug_value0/1 + + //Wait for random delay before starting debug txn + configuration.kv_rst_agent_config.wait_for_num_clocks(wait_cycles_from_seq); + + case(debug_type) + SECURITY_STATE: begin + //start debug seq on rst agent + // kv_rst_agent_debug_seq.start(configuration.kv_rst_agent_config.sequencer); + kv_rst_agent_debug_on_seq.start(configuration.kv_rst_agent_config.sequencer); + end + CLEAR_SECRETS: begin + reg_model.kv_reg_rm.CLEAR_SECRETS.write(sts, clear_secrets_data, UVM_FRONTDOOR, reg_model.kv_AHB_map, this); + assert(sts == UVM_IS_OK) else `uvm_error("AHB_CLEAR_SECRETS_SET", "Failed when writing to CLEAR_SECRETS reg!") + end + endcase + endtask +endclass \ No newline at end of file diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_predictor.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_predictor.svh index 7b9db72bf..4f787c534 100644 --- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_predictor.svh +++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_predictor.svh @@ -206,8 +206,20 @@ class kv_predictor #( string client; logic [KV_ENTRY_SIZE_W-1:0]last_dword_written[0:KV_NUM_KEYS-1]; + // process running_dly_jobs[$]; + // int unsigned job_end_count[time]; + // bit write_entry_pending = 0; + // bit send_hmac_write_txn = 0; + bit set_val_ctrl_derived = 0; + logic [KV_NUM_KEYS-1:0] val_ctrl_derived_data = 0; + extern function void populate_expected_kv_read_txn(ref kv_sb_ap_output_transaction_t t_expected, kv_read_transaction t_received, string client); extern function void populate_expected_kv_write_txn(ref kv_sb_ap_output_transaction_write_t t_expected, kv_write_transaction t_received); + extern task poll_and_run_delay_jobs(); + // extern function send_delayed_expected_transactions_hmac_write(kv_write_transaction t); + // extern function send_delayed_expected_transactions_sha512_write(kv_write_transaction t); + // extern function send_delayed_expected_transactions_ecc_write(kv_write_transaction t); + // extern function send_delayed_expected_transactions_doe_write(kv_write_transaction t); // pragma uvmf custom class_item_additional end // FUNCTION: new @@ -272,6 +284,13 @@ class kv_predictor #( // pragma uvmf custom build_phase end endfunction + task run_phase (uvm_phase phase); + fork + poll_and_run_delay_jobs(); + join_none + super.run_phase(phase); + endtask + // FUNCTION: write_kv_rst_agent_ae // Transactions received through kv_rst_agent_ae initiate the execution of this function. // This function performs prediction of DUT output values based on DUT input, configuration and state @@ -382,6 +401,8 @@ class kv_predictor #( // Construct one of each output transaction type. kv_sb_ap_output_transaction_write = kv_sb_ap_output_transaction_write_t::type_id::create("kv_sb_ap_output_transaction_write"); populate_expected_kv_write_txn(kv_sb_ap_output_transaction_write, t); + // this.write_entry_pending = 1'b1; + // send_hmac_write_txn = 1'b1; // Code for sending output transaction out through kv_sb_ap // Please note that each broadcasted transaction should be a different object than previously @@ -593,8 +614,9 @@ class kv_predictor #( reg [KV_DATA_W-1:0] data_active; reg [ahb_lite_slave_0_params::AHB_WDATA_WIDTH-1:0] address_aligned; uvm_reg val_ctrl, val_reg, val_ctrl_derived; - uvm_reg_data_t val_ctrl_data, val_reg_data, val_ctrl_derived_data; + uvm_reg_data_t val_ctrl_data, val_reg_data; + this.set_val_ctrl_derived = 'b0; ahb_slave_0_ae_debug = t; `uvm_info("PRED", "Transaction Received through ahb_slave_0_ae", UVM_MEDIUM) `uvm_info("PRED", {" Data: ",t.convert2string()}, UVM_FULL) @@ -605,15 +627,15 @@ class kv_predictor #( //Convert data from AHB to txn address_aligned = ahb_txn.address & ~(KV_DATA_W/8 - 1); data_active = KV_DATA_W'(ahb_txn.data[0] >> (8*(address_aligned % (ahb_lite_slave_0_params::AHB_WDATA_WIDTH/8)))); + + //Read val reg to determine if we're in debug mode + val_reg = p_kv_rm.get_reg_by_name("val_reg"); + val_reg_data = val_reg.get(); if(ahb_txn.RnW == AHB_WRITE) begin //Copy txn and modify required fields later kv_sb_ahb_ap_output_transaction.copy(ahb_txn); - //Read val reg to determine if we're in debug mode - val_reg = p_kv_rm.get_reg_by_name("val_reg"); - val_reg_data = val_reg.get(); - //Only allow clear_secrets during debug mode if ((ahb_txn.address == `KV_REG_CLEAR_SECRETS) ) begin //Update val register with CLEAR_SECRETS wr_debug_values field @@ -621,7 +643,8 @@ class kv_predictor #( if (val_reg_data[p_kv_rm.val_reg.cptra_in_debug_scan_mode.get_lsb_pos()]) begin //[2]) begin //Only allow clear operation if in debug mode - if (data_active[1:0] == 'h1) begin + //if (data_active[1:0] == 'h1) begin + if (data_active [p_kv_rm.kv_reg_rm.CLEAR_SECRETS.wr_debug_values.get_lsb_pos()] && !data_active[p_kv_rm.kv_reg_rm.CLEAR_SECRETS.sel_debug_value.get_lsb_pos()]) begin for(entry = 0; entry < KV_NUM_KEYS; entry++) begin //Read locks before clearing - do not clear if locked kv_reg = p_kv_rm.get_reg_by_name($sformatf("KEY_CTRL[%0d]",entry)); @@ -634,7 +657,8 @@ class kv_predictor #( end end end - else if(data_active[1:0] == 'h3) begin + //else if(data_active[1:0] == 'h3) begin + else if (data_active [p_kv_rm.kv_reg_rm.CLEAR_SECRETS.wr_debug_values.get_lsb_pos()] && data_active[p_kv_rm.kv_reg_rm.CLEAR_SECRETS.sel_debug_value.get_lsb_pos()]) begin for(entry = 0; entry < KV_NUM_KEYS; entry++) begin //Read locks before clearing kv_reg = p_kv_rm.get_reg_by_name($sformatf("KEY_CTRL[%0d]",entry)); @@ -660,21 +684,32 @@ class kv_predictor #( val_ctrl = p_kv_rm.get_reg_by_name("val_ctrl"); val_ctrl_data = val_ctrl.get(); - if(data_active[2] && !kv_reg_data[0] && !kv_reg_data[1]) begin + if(data_active[p_kv_rm.kv_reg_rm.KEY_CTRL[entry].clear.get_lsb_pos()] && !kv_reg_data[p_kv_rm.kv_reg_rm.KEY_CTRL[entry].lock_wr.get_lsb_pos()] && !kv_reg_data[p_kv_rm.kv_reg_rm.KEY_CTRL[entry].lock_use.get_lsb_pos()] && !val_reg_data[p_kv_rm.val_reg.cptra_in_debug_scan_mode.get_lsb_pos()]) begin val_ctrl_data[entry] = 'b1; //In design, clear is a single pulse reg. This val_ctrl[*] will be reset in kv_reg_predictor - val_ctrl_derived_data[entry] = 'b1; + // for (int i = 0; i < KV_NUM_KEYS; i++) begin + this.val_ctrl_derived_data[entry] = 'b1; + // this.val_ctrl_derived_data[i] = (i == entry); + // end + // this.set_val_ctrl_derived = 'b1; //p_kv_rm.kv_reg_rm.kv_val_ctrl.predict(val_ctrl_data); `uvm_info("PRED", "Setting clear field of val_ctrl register", UVM_MEDIUM) p_kv_rm.val_ctrl.set(val_ctrl_data); - `uvm_info("PRED", "Setting clear field of val_ctrl_derived register", UVM_MEDIUM) - p_kv_rm.val_ctrl_derived.set(val_ctrl_derived_data); + //`uvm_info("PRED", "Setting clear field of val_ctrl_derived register", UVM_MEDIUM) + // //configuration.kv_hmac_write_agent_config.wait_for_num_clocks(1); + //p_kv_rm.val_ctrl_derived.set(val_ctrl_derived_data); //Clear the entry that is being accessed for(offset = 0; offset < KV_NUM_DWORDS; offset++) begin p_kv_rm.kv_reg_rm.KEY_ENTRY[entry][offset].predict('h0); p_kv_rm.kv_reg_rm.KEY_ENTRY[entry][offset].set('h0); end end + //Reset all bits of val_ctrl_derived except current entry irrespective of locks + this.set_val_ctrl_derived = 'b1; + for (int i = 0; i < KV_NUM_KEYS; i++) begin + if (i != entry) + this.val_ctrl_derived_data[i] = 0; + end end end else begin @@ -708,8 +743,8 @@ endclass uvm_reg kv_reg; uvm_reg_data_t kv_reg_data; - uvm_reg val_ctrl; - uvm_reg_data_t val_ctrl_data; + uvm_reg val_ctrl, val_ctrl_derived; + uvm_reg_data_t val_ctrl_data, val_ctrl_derived_data; logic lock_use; logic [KV_NUM_READ-1:0] dest_valid; logic client_dest_valid; @@ -717,12 +752,16 @@ endclass val_ctrl = p_kv_rm.get_reg_by_name("val_ctrl"); val_ctrl_data = val_ctrl.get(); + val_ctrl_derived = p_kv_rm.get_reg_by_name("val_ctrl_derived"); + val_ctrl_derived_data = val_ctrl_derived.get(); + kv_reg = p_kv_rm.get_reg_by_name($sformatf("KEY_CTRL[%0d]",t_received.read_entry)); kv_reg_data = kv_reg.get_mirrored_value(); kv_reg = p_kv_rm.get_reg_by_name($sformatf("KEY_ENTRY[%0d][%0d]",t_received.read_entry,t_received.read_offset)); - lock_use = kv_reg_data[1]; + lock_use = kv_reg_data[p_kv_rm.kv_reg_rm.KEY_CTRL[t_received.read_entry].lock_use.get_lsb_pos()]; dest_valid = kv_reg_data[13:9]; //[16:14] are rsvd + // dest_valid = kv_reg_data[p_kv_rm.kv_reg_rm.KEY_CTRL[entry].dest_valid.get_lsb_pos()]; case(client) inside @@ -744,13 +783,13 @@ endclass //kv_predictor takes care of #1. #2 and #3 should be done is custom AHB reg predictor which we don't have //As a workaround, setting a val_ctrl reg when clear happens. Until a write occurs on that entry, this bit will remain set //During every read, we check val_ctrl[entry] bit. If 1, return 0s, resp.err = 1 and last dword = 0 to mimic design - if (lock_use || !client_dest_valid || val_ctrl_data[t_received.read_entry]) begin + if (lock_use || !client_dest_valid || val_ctrl_data[t_received.read_entry] || val_ctrl_derived_data[t_received.read_entry]) begin t_expected.read_data = 'h0; t_expected.error = 'b1; end else begin kv_reg_data = kv_reg.get_mirrored_value(); - t_expected.read_data = kv_reg_data[31:0]; //Data from KEY entry + t_expected.read_data = KV_DATA_W'(kv_reg_data); //kv_reg_data[31:0]; //Data from KEY entry t_expected.error = 'b0; end @@ -776,8 +815,8 @@ endclass kv_reg = p_kv_rm.get_reg_by_name($sformatf("KEY_CTRL[%0d]",t_received.write_entry)); kv_reg_data = kv_reg.get_mirrored_value(); - lock_wr = kv_reg_data[0]; - lock_use = kv_reg_data[1]; + lock_wr = kv_reg_data[p_kv_rm.kv_reg_rm.KEY_CTRL[t_received.write_entry].lock_wr.get_lsb_pos()]; + lock_use = kv_reg_data[p_kv_rm.kv_reg_rm.KEY_CTRL[t_received.write_entry].lock_use.get_lsb_pos()]; val_ctrl_derived = p_kv_rm.get_reg_by_name("val_ctrl_derived"); val_ctrl_derived_data = val_ctrl_derived.get(); @@ -798,7 +837,7 @@ endclass end else if (/*this.write_in_progress[t_received.write_entry] &&*/ val_ctrl_derived_data[t_received.write_entry]) begin t_expected.error = 1'b1; - `uvm_info("PRED","Attempts to clear a reg while write is in progress results in an error", UVM_MEDIUM) + `uvm_info("PRED","Attempts to clear a reg while write is in progress results in an err", UVM_MEDIUM) `uvm_info("PRED", $sformatf("Write entry = %0d, val_ctrl_derived_data = %b", t_received.write_entry, val_ctrl_derived_data), UVM_MEDIUM) end else begin @@ -813,5 +852,72 @@ endclass endfunction + + // function void kv_predictor::send_delayed_expected_transactions_hmac_write(kv_write_transaction t); + // bit send_hmac_write_txn = 0; + + // kv_sb_ap_output_transaction_write = kv_sb_ap_output_transaction_write_t::type_id::create("kv_sb_ap_output_transaction_write"); + + // if (this.write_entry_pending) begin + // `uvm_info("PRED_DLY", "Delay job to update KEY_ENTRY value", UVM_HIGH) + // this.write_entry_pending = 1'b0; + // end + + // //------------------------------------- + // //Send expected txns to SCBD + // //------------------------------------- + // if (send_hmac_write_txn) begin + // populate_expected_kv_write_txn(kv_sb_ap_output_transaction_write, t); + // kv_hmac_write_sb_ap.write(kv_sb_ap_output_transaction_write); + // `uvm_info("PRED_DLY", "Transaction submitted through kv_hmac_write_sb_ap", UVM_MEDIUM) + // send_hmac_write_txn = 1'b0; + // end + + // endfunction + + // task kv_predictor::poll_and_run_delay_jobs(); + // forever begin + // while (p_kv_rm.delay_jobs.size() > 0) begin + // fork + // kv_reg_delay_job job = p_kv_rm.delay_jobs.pop_front(); + // //TODO: add reset check + // int idx[$]; + // time end_time; + // this.running_dly_jobs.push_back(process::self()); // This tracks all the delay_jobs that are pending so they can be clobbered on rst + // `uvm_info("PRED_DLY", $sformatf("Doing delay of %0d cycles before running delay job with signature: %s", job.get_delay_cycles(), job.get_name()), UVM_HIGH) + // end_time = $time + 10*job.get_delay_cycles(); + // job_end_count[end_time] += 1; + // //Delay jobs have 1 cycle inherent delay + // if (job.get_delay_cycles()) configuration.kv_hmac_write_agent_config.wait_for_num_clocks(job.get_delay_cycles()); + // uvm_wait_for_nba_region(); + // idx = this.running_dly_jobs.find_first_index(pr) with (pr == process::self()); + // this.running_dly_jobs.delete(idx.pop_front()); + // job.do_job(); + // job_end_count[end_time] -= 1; + + // if (job_end_count[end_time] == 0) begin + // job_end_count.delete(end_time); + // // send_delayed_expected_transactions_hmac_write(t); + // end + // //end TODO: add reset check + // join_none + // end + // configuration.kv_hmac_write_agent_config.wait_for_num_clocks(1); + // end + // endtask + + task kv_predictor::poll_and_run_delay_jobs(); + forever begin + while (this.set_val_ctrl_derived) begin + // fork + configuration.kv_hmac_write_agent_config.wait_for_num_clocks(2); + `uvm_info("PRED", "Setting clear field of val_ctrl_derived register", UVM_MEDIUM) + p_kv_rm.val_ctrl_derived.set(this.val_ctrl_derived_data); + this.set_val_ctrl_derived = 'b0; + // join_none + end + configuration.kv_hmac_write_agent_config.wait_for_num_clocks(1); + end + endtask // pragma uvmf custom external end diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_reg_predictor.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_reg_predictor.svh index de58e86f4..fb5e0fc14 100644 --- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_reg_predictor.svh +++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_reg_predictor.svh @@ -152,7 +152,7 @@ class kv_reg_predictor#(type BUSTYPE=int) extends uvm_reg_predictor #(.BUSTYPE(B //This will be used to hold the clear until writes are finished to current entry //----------------------------------------------- for (int i = 0; i < KV_NUM_KEYS; i++) begin - val_ctrl_derived_data[i] /*[entry_offset[4:0]]*/ = (val_ctrl_derived_data[i] & (i == entry_offset[4:0])); //'b0; //Reset clear bit of current entry + val_ctrl_derived_data[i] = (val_ctrl_derived_data[i] & (i == entry_offset[4:0])); //'b0; //Reset clear bit of everything except current entry end val_ctrl_item = new; @@ -182,10 +182,11 @@ class kv_reg_predictor#(type BUSTYPE=int) extends uvm_reg_predictor #(.BUSTYPE(B //TODO: Revisit lock and clear condition //TODO: Can write to regs during debug mode. Remove check after updating sequences `uvm_info("KV_REG_PRED", $sformatf("OUTSIDE, lock_wr = %0d, lock_use = %0d, clear_secrets_wren = %0d, val_reg_data = %b", lock_wr, lock_use, clear_secrets_data[0], val_reg_data), UVM_FULL) - if (!lock_wr && !lock_use && !(clear_secrets_data[0] && val_reg_data[2]) && !val_reg_data[0]) begin + if (!lock_wr && !lock_use && !(clear_secrets_data[0] && val_reg_data[2]) /*&& !val_reg_data[0]*/) begin `uvm_info("KV_REG_PRED", "Writing to KEY_ENTRY", UVM_FULL) super.write(tr); + if ((rw.addr >= `KV_REG_KEY_ENTRY_0_0) && (rw.addr <= `KV_REG_KEY_ENTRY_31_11)) begin //Only update KEY_CTRL if it's a KEY_ENTRY write `uvm_info("KV_REG_PRED", "Updating KEY_CTRL", UVM_FULL) //----------------------------------------------- @@ -201,6 +202,7 @@ class kv_reg_predictor#(type BUSTYPE=int) extends uvm_reg_predictor #(.BUSTYPE(B //Update CTRL reg kv_reg_ctrl.do_predict(kv_reg_ctrl_item, UVM_PREDICT_DIRECT); + end end else begin `uvm_info("KV_REG_PRED", "Skipping write to KEY_ENTRY", UVM_FULL) diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_sequence.svh index 08233fef5..dcadcfcf1 100644 --- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_sequence.svh +++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_sequence.svh @@ -39,6 +39,10 @@ class kv_wr_rd_debug_sequence #( typedef kv_rst_debug_sequence kv_rst_agent_debug_sequence_t; kv_rst_agent_debug_sequence_t kv_rst_agent_debug_seq; + typedef kv_rst_debug_on_sequence kv_rst_agent_debug_on_sequence_t; + kv_rst_agent_debug_on_sequence_t kv_rst_agent_debug_on_seq; + typedef kv_rst_debug_off_sequence kv_rst_agent_debug_off_sequence_t; + kv_rst_agent_debug_off_sequence_t kv_rst_agent_debug_off_seq; typedef kv_write_key_entry_sequence kv_write_agent_key_entry_sequence_t; kv_write_agent_key_entry_sequence_t hmac_write_seq; @@ -69,6 +73,10 @@ class kv_wr_rd_debug_sequence #( kv_rst_agent_debug_seq = kv_rst_agent_debug_sequence_t::type_id::create("kv_rst_agent_debug_seq"); if(!this.randomize()) `uvm_error("KV WR RD", "Failed to randomize KV RST debug seq"); + kv_rst_agent_debug_on_seq = kv_rst_agent_debug_on_sequence_t::type_id::create("kv_rst_agent_debug_on_seq"); + if(!this.randomize()) `uvm_error("KV WR RD", "Failed to randomize KV RST debug on seq"); + kv_rst_agent_debug_off_seq = kv_rst_agent_debug_off_sequence_t::type_id::create("kv_rst_agent_debug_off_seq"); + if(!this.randomize()) `uvm_error("KV WR RD", "Failed to randomize KV RST debug off seq"); hmac_write_seq = kv_write_agent_key_entry_sequence_t::type_id::create("hmac_write_seq"); if(!this.randomize()) `uvm_error("KV WR RD", "Failed to randomize KV WRITE seq"); @@ -90,7 +98,6 @@ class kv_wr_rd_debug_sequence #( ecc_seed_read_seq = kv_read_agent_key_entry_sequence_t::type_id::create("ecc_seed_read_seq"); if(!this.randomize()) `uvm_error("KV WR RD", "Failed to randomize KV READ seq"); //kv_rst_agent_poweron_seq_2 = kv_rst_agent_poweron_sequence_t::type_id::create("kv_rst_agent_poweron_seq_2"); - endfunction virtual task body(); @@ -105,15 +112,16 @@ class kv_wr_rd_debug_sequence #( //Issue and wait for reset - if(configuration.kv_rst_agent_config.sequencer != null) - kv_rst_agent_poweron_seq.start(configuration.kv_rst_agent_config.sequencer); - else - `uvm_error("KV WR RD", "kv_rst_agent_config.sequencer is null!") + // if(configuration.kv_rst_agent_config.sequencer != null) + // kv_rst_agent_poweron_seq.start(configuration.kv_rst_agent_config.sequencer); + // else + // `uvm_error("KV WR RD", "kv_rst_agent_config.sequencer is null!") //Unlock debug mode or clear secrets randomly - std::randomize(debug_type); //0 - security state, 1 - clear secrets + // std::randomize(debug_type); //0 - security state, 1 - clear secrets + debug_type = 0; std::randomize(wait_cycles_from_seq) with { wait_cycles_from_seq >= 5; @@ -128,7 +136,8 @@ class kv_wr_rd_debug_sequence #( case(debug_type) SECURITY_STATE: begin //start debug seq on rst agent - kv_rst_agent_debug_seq.start(configuration.kv_rst_agent_config.sequencer); + // kv_rst_agent_debug_seq.start(configuration.kv_rst_agent_config.sequencer); + kv_rst_agent_debug_on_seq.start(configuration.kv_rst_agent_config.sequencer); end CLEAR_SECRETS: begin reg_model.kv_reg_rm.CLEAR_SECRETS.write(sts, clear_secrets_data, UVM_FRONTDOOR, reg_model.kv_AHB_map, this); diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_lock_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_lock_sequence.svh index 37b51bb32..630079dc5 100644 --- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_lock_sequence.svh +++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_lock_sequence.svh @@ -198,46 +198,30 @@ class kv_wr_rd_lock_sequence #( end end - //TODO: this needs env clean up! (Emulate 1 clk delay between key_entry_clear and wr_resp_error) - // //clear x write - // // fork - - // //Issue and wait for reset - // if(configuration.kv_rst_agent_config.sequencer != null) - // kv_rst_agent_poweron_seq.start(configuration.kv_rst_agent_config.sequencer); - // else - // `uvm_error("KV_WR_RD_LOCK", "kv_rst_agent_config.sequencer is null!") + + //clear x write + // fork + + //Issue and wait for reset + if(configuration.kv_rst_agent_config.sequencer != null) + kv_rst_agent_poweron_seq.start(configuration.kv_rst_agent_config.sequencer); + else + `uvm_error("KV_WR_RD_LOCK", "kv_rst_agent_config.sequencer is null!") - // // begin - // //Set each CTRL reg with random lock data - // for(int write_entry_temp = 0; write_entry_temp < KV_NUM_KEYS; write_entry_temp++) begin - // // if (write_entry_temp < KV_NUM_KEYS-1) begin - // // lock_data = $urandom_range(1,7); //Can set one of lock_wr, lock_use, clear or all together - // reg_model.kv_reg_rm.KEY_CTRL[write_entry_temp].write(sts, 'h4, UVM_FRONTDOOR, reg_model.kv_AHB_map, this); - // `uvm_info("KNU_LOCK", $sformatf("Setting KEY CTRL: %d", write_entry_temp), UVM_MEDIUM) - // assert(sts == UVM_IS_OK) else `uvm_error("AHB_LOCK_SET", $sformatf("Failed when writing to KEY_CTRL[%d]",write_entry_temp)) - // // end - - // for (int write_offset_temp = 0; write_offset_temp < KV_NUM_DWORDS; write_offset_temp++) begin - // // Construct the transaction - // uvm_config_db#(reg [KV_ENTRY_ADDR_W-1:0])::set(null, "uvm_test_top.environment.kv_hmac_write_agent.sequencer.hmac_write_seq", "local_write_entry",write_entry_temp); - // uvm_config_db#(reg [KV_ENTRY_SIZE_W-1:0])::set(null, "uvm_test_top.environment.kv_hmac_write_agent.sequencer.hmac_write_seq", "local_write_offset",write_offset_temp); - // `uvm_info("KNU_WRITE", $sformatf("Writing to entry: %0d, offset: %0d", write_entry_temp, write_offset_temp), UVM_MEDIUM) - // hmac_write_seq.start(configuration.kv_hmac_write_agent_config.sequencer); - // end - - - // end - // // end - - // // begin - // //Write to all entries, random offsets - // // for (int write_entry_temp = 0; write_entry_temp < KV_NUM_KEYS; write_entry_temp++) begin - - // // end - - // // end - // // join + //Set each CTRL reg with random lock data + for(int write_entry_temp = 0; write_entry_temp < KV_NUM_KEYS; write_entry_temp++) begin + lock_data = $urandom_range(1,7); //Can set one of lock_wr, lock_use, clear or all together + reg_model.kv_reg_rm.KEY_CTRL[write_entry_temp].write(sts, lock_data, UVM_FRONTDOOR, reg_model.kv_AHB_map, this); + assert(sts == UVM_IS_OK) else `uvm_error("AHB_LOCK_SET", $sformatf("Failed when writing to KEY_CTRL[%d]",write_entry_temp)) + + for (int write_offset_temp = 0; write_offset_temp < KV_NUM_DWORDS; write_offset_temp++) begin + // Construct the transaction + uvm_config_db#(reg [KV_ENTRY_ADDR_W-1:0])::set(null, "uvm_test_top.environment.kv_hmac_write_agent.sequencer.hmac_write_seq", "local_write_entry",write_entry_temp); + uvm_config_db#(reg [KV_ENTRY_SIZE_W-1:0])::set(null, "uvm_test_top.environment.kv_hmac_write_agent.sequencer.hmac_write_seq", "local_write_offset",write_offset_temp); + hmac_write_seq.start(configuration.kv_hmac_write_agent_config.sequencer); + end + + end endtask diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/kv_rst_pkg.sv b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/kv_rst_pkg.sv index aa593334e..87a6a8f8b 100644 --- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/kv_rst_pkg.sv +++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/kv_rst_pkg.sv @@ -79,6 +79,8 @@ package kv_rst_pkg; `include "src/kv_rst_cold_rst_sequence.svh" `include "src/kv_rst_core_rst_sequence.svh" `include "src/kv_rst_debug_sequence.svh" + `include "src/kv_rst_debug_on_sequence.svh" + `include "src/kv_rst_debug_off_sequence.svh" `include "src/kv_rst_agent.svh" diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_debug_off_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_debug_off_sequence.svh new file mode 100644 index 000000000..069cb5f6c --- /dev/null +++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_debug_off_sequence.svh @@ -0,0 +1,68 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the soc_ifc_ctrl transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a soc_ifc_ctrl_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class kv_rst_debug_off_sequence extends kv_rst_sequence_base; + + `uvm_object_utils( kv_rst_debug_off_sequence ) + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + + task body(); + + // Deassert debug mode + req=kv_rst_transaction::type_id::create("rst_req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("KV_RST_DEBUG", "kv_rst_debug_off_sequence::body()-kv_rst_transaction randomization failed") + `uvm_info("KV_RST_DEBUG", "Asserting reset, pwrgood high", UVM_MEDIUM) + req.set_pwrgood = 1'b1; + req.assert_rst = 1'b0; + req.assert_core_rst = 1'b0; + req.debug_mode = 1'b0; + req.scan_mode = 1'b0; + + finish_item(req); + `uvm_info("KV_RST_DEBUG", {"Response:",req.convert2string()},UVM_MEDIUM) + + + +endtask + +endclass \ No newline at end of file diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_debug_on_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_debug_on_sequence.svh new file mode 100644 index 000000000..7daaf9ea2 --- /dev/null +++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_rst_pkg/src/kv_rst_debug_on_sequence.svh @@ -0,0 +1,69 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This sequences randomizes the soc_ifc_ctrl transaction and sends it +// to the UVM driver. +// +// This sequence constructs and randomizes a soc_ifc_ctrl_transaction. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class kv_rst_debug_on_sequence extends kv_rst_sequence_base; + + `uvm_object_utils( kv_rst_debug_on_sequence ) + + //***************************************************************** + function new(string name = ""); + super.new(name); + endfunction: new + + // **************************************************************************** + // TASK : body() + // This task is automatically executed when this sequence is started using the + // start(sequencerHandle) task. + // + + task body(); + + // Assert debug mode + req=kv_rst_transaction::type_id::create("pwr_req"); + start_item(req); + // Randomize the transaction + if(!req.randomize()) `uvm_fatal("KV_RST_DEBUG", "kv_rst_debug_on_sequence::body()-kv_rst_transaction randomization failed") + `uvm_info("KV_RST_DEBUG", "Asserting reset, pwrgood low", UVM_MEDIUM) + req.set_pwrgood = 1'b1; + req.assert_rst = 1'b0; + req.assert_core_rst = 1'b0; + req.debug_mode = 1'b1; + req.scan_mode = 1'b0; + + finish_item(req); + `uvm_info("KV_RST_DEBUG", {"Response:",req.convert2string()},UVM_MEDIUM) + + + + +endtask + +endclass \ No newline at end of file From 47b4ceb83d8ba34f918dac4dc52eb73ea3fdaf28 Mon Sep 17 00:00:00 2001 From: Mojtaba Bisheh Niasar Date: Tue, 26 Sep 2023 17:46:46 +0000 Subject: [PATCH 05/11] Merged PR 126129: added failure in signing if generated signature has s=0 added s_out_of_range failure for signing output added ecc test vector for seed/nonce/iv full range Related work items: #561868 --- src/ecc/coverage/ecc_top_cov_if.sv | 3 + src/ecc/rtl/ecc_dsa_ctrl.sv | 4 +- src/ecc/tb/test_vectors/ecc_drbg_mbedtls.hex | 16 ++-- .../tb/caliptra_top_tb_services.sv | 17 ++++ .../smoke_test_ecc_errortrigger.c | 91 ++++++++++++++++++- 5 files changed, 121 insertions(+), 10 deletions(-) diff --git a/src/ecc/coverage/ecc_top_cov_if.sv b/src/ecc/coverage/ecc_top_cov_if.sv index 97f1a8cac..345964c64 100644 --- a/src/ecc/coverage/ecc_top_cov_if.sv +++ b/src/ecc/coverage/ecc_top_cov_if.sv @@ -34,6 +34,7 @@ interface ecc_top_cov_if logic error_flag; logic privkey_input_outofrange; logic r_output_outofrange; + logic s_output_outofrange; logic r_input_outofrange; logic s_input_outofrange; logic pubkeyx_input_outofrange; @@ -93,6 +94,7 @@ interface ecc_top_cov_if assign error_flag = ecc_top.ecc_dsa_ctrl_i.error_flag; assign privkey_input_outofrange = ecc_top.ecc_dsa_ctrl_i.privkey_input_outofrange; assign r_output_outofrange = ecc_top.ecc_dsa_ctrl_i.r_output_outofrange; + assign s_output_outofrange = ecc_top.ecc_dsa_ctrl_i.s_output_outofrange; assign r_input_outofrange = ecc_top.ecc_dsa_ctrl_i.r_input_outofrange; assign s_input_outofrange = ecc_top.ecc_dsa_ctrl_i.s_input_outofrange; assign pubkeyx_input_outofrange = ecc_top.ecc_dsa_ctrl_i.pubkeyx_input_outofrange; @@ -118,6 +120,7 @@ interface ecc_top_cov_if error_flag_cp: coverpoint error_flag; privkey_input_outofrange_cp: coverpoint privkey_input_outofrange; r_output_outofrange_cp: coverpoint r_output_outofrange; + s_output_outofrange_cp: coverpoint s_output_outofrange; r_input_outofrange_cp: coverpoint r_input_outofrange; s_input_outofrange_cp: coverpoint s_input_outofrange; pubkeyx_input_outofrange_cp: coverpoint pubkeyx_input_outofrange; diff --git a/src/ecc/rtl/ecc_dsa_ctrl.sv b/src/ecc/rtl/ecc_dsa_ctrl.sv index fd4c98c81..405c7fa4e 100644 --- a/src/ecc/rtl/ecc_dsa_ctrl.sv +++ b/src/ecc/rtl/ecc_dsa_ctrl.sv @@ -197,6 +197,7 @@ module ecc_dsa_ctrl logic privkey_input_outofrange; logic r_output_outofrange; + logic s_output_outofrange; logic r_input_outofrange; logic s_input_outofrange; logic pubkeyx_input_outofrange; @@ -659,6 +660,7 @@ module ecc_dsa_ctrl assign privkey_input_outofrange = signing_process & ((privkey_reg == 0) | (privkey_reg >= GROUP_ORDER)); assign r_output_outofrange = signing_process & (hw_r_we & (read_reg == 0)); + assign s_output_outofrange = signing_process & (hw_s_we & (read_reg == 0)); assign r_input_outofrange = verifying_process & ((r_reg == 0) | (r_reg >= GROUP_ORDER)); assign s_input_outofrange = verifying_process & ((s_reg == 0) | (s_reg >= GROUP_ORDER)); @@ -668,7 +670,7 @@ module ecc_dsa_ctrl assign pcr_sign_input_invalid = ((cmd_reg == KEYGEN) | (cmd_reg == VERIFY)) & pcr_sign_mode; - assign error_flag = privkey_input_outofrange | r_output_outofrange | r_input_outofrange | s_input_outofrange | pubkeyx_input_outofrange | pubkeyy_input_outofrange | pubkey_input_invalid | pcr_sign_input_invalid; + assign error_flag = privkey_input_outofrange | r_output_outofrange | s_output_outofrange | r_input_outofrange | s_input_outofrange | pubkeyx_input_outofrange | pubkeyy_input_outofrange | pubkey_input_invalid | pcr_sign_input_invalid; //---------------------------------------------------------------- // ECDSA_FSM_flow diff --git a/src/ecc/tb/test_vectors/ecc_drbg_mbedtls.hex b/src/ecc/tb/test_vectors/ecc_drbg_mbedtls.hex index e2a501f0a..03e50bb56 100644 --- a/src/ecc/tb/test_vectors/ecc_drbg_mbedtls.hex +++ b/src/ecc/tb/test_vectors/ecc_drbg_mbedtls.hex @@ -9,14 +9,14 @@ E548E535A1CC600E133B5591AEBAAD78054006D752D0E1DF94FBFA95D78F0B3F8E81B9119C2BE008 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 0 FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF -30802CFC9EACEA478B8511604CC9B0734281CE9C65B6D3DA1B07D6D71E9AA58E5B03509F3F1D09A39F693E376CD0EF69 -0341F64BAB8B41B7D11486CBD84EF8A9B00F5C0112CC9093B0166B9D93D571B4C1EE38C477CCEE73C651596F2F4AAFED -6E39A8A85D42EDA0442B3C3B9C6B5E16E21392EDBA702C2530808C9D975FD9FD9E345710884A031EA542D351192C60C7 -EB7A88B7A05EF13B3F3582438B8C7B8C0D5DCB8E972EF2D40C22059E95129FCDE7F75D35210C1DB6A619747E3BCC3FB1 -F36220929C3BABAF12008CB1DDF360CE533AF62368567E47187CFBC69D8BBEA8EB05ACF32752FE0B4077D1B76EE22155 -D11935F6710CF706500AE86DD1953017949984CABFC1C1D113FCC340D6C0CA4023659D54F774B18EA50D310297FFE1C2 -E1AF7B6C1012EE82575B883CC41BBBD4F052892DD3455B3D9B4B3F6A35A2C1637CFD623E3AB73949B74A61A75AE85B19 -F287851824D8C8DE17291A89F053A60D33DC29600E2D1654B58085A8AA8969E3195B9EAF649C069A28295260497B2521 +7F68A6D896EA5DA62E78DEDB46F6662BC141F2F0B9E641ACC7342663FD51444E380FEA1DABBCA55F18987C0CFC10DF77 +787D82654607CD1D5A1B11F25C7DF90541380E497CB0560E1489BF7F71B6596300CC9D19335C4827A9BC6148B342F5EC +A321B7C112EEE7227631066CDB556F0D6C66CA87AE912EB4DC412F2F108B27E2BECCBA94F0D844BD7872106EF25C9F25 +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +F3132CF17D965F02E7BF2FDA8755BF54B31B72053D3C35031AA28AB7689C046AF863DB63D04D4810CD042F3B07A860FC +01A6FDB4EFC82CC544B06FE7741CF9C6E8D8189C14A250FBAFCB3FDC5290F30E5E7092FCD1B1A54E60E4F37750BBFE7D +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF 1 5F1C0F632D10524D84F4BD20C9ADDAD795CDF5DAA60EA1217A00DD7B1ECAD268C23CC6D7F258E3747A5E4299893F8C37 C9DA896F656439AE83BCA037496DC001CB1F8F0FC9AB9C3C1723768352399E4BF5F44A60E84C2567B88C32569342B706 diff --git a/src/integration/tb/caliptra_top_tb_services.sv b/src/integration/tb/caliptra_top_tb_services.sv index e274b6565..c55f07969 100644 --- a/src/integration/tb/caliptra_top_tb_services.sv +++ b/src/integration/tb/caliptra_top_tb_services.sv @@ -169,6 +169,8 @@ module caliptra_top_tb_services logic inject_zero_sign_r; logic inject_zero_sign_r_needs_release; + logic inject_zero_sign_s; + logic inject_zero_sign_s_needs_release; logic en_jtag_access; @@ -235,6 +237,7 @@ module caliptra_top_tb_services // 8'h92 - Check PCR singing with randomized vector // 8'h98 - Inject invalid zero sign_r into ECC // 8'h99 - Inject zeroize into HMAC + // 8'h9a - Inject invalid zero sign_s into ECC // 8'ha0: 8'ha7 - Inject HMAC_KEY to kv_key register // 8'hc0: 8'hc7 - Inject SHA_BLOCK to kv_key register // 8'he0 - Set random ICCM SRAM single bit error injection @@ -450,10 +453,15 @@ module caliptra_top_tb_services if (~cptra_rst_b) begin inject_zero_sign_r <= 1'b0; inject_zero_sign_r_needs_release <= 1'b0; + inject_zero_sign_s <= 1'b0; + inject_zero_sign_s_needs_release <= 1'b0; end else if((WriteData[7:0] == 8'h98) && mailbox_write) begin inject_zero_sign_r <= 1'b1; end + else if((WriteData[7:0] == 8'h9a) && mailbox_write) begin + inject_zero_sign_s <= 1'b1; + end else if(inject_zero_sign_r) begin if (caliptra_top_dut.ecc_top1.ecc_dsa_ctrl_i.prog_instr.reg_id == 6'd21) begin //R_ID force caliptra_top_dut.ecc_top1.ecc_dsa_ctrl_i.ecc_arith_unit_i.d_o = '0; @@ -463,6 +471,15 @@ module caliptra_top_tb_services inject_zero_sign_r <= 1'b0; end end + else if(inject_zero_sign_s) begin + if (caliptra_top_dut.ecc_top1.ecc_dsa_ctrl_i.prog_instr.reg_id == 6'd22) begin //S_ID + force caliptra_top_dut.ecc_top1.ecc_dsa_ctrl_i.ecc_arith_unit_i.d_o = '0; + inject_zero_sign_s_needs_release <= 1'b1; + end + else if (inject_zero_sign_s_needs_release) begin + inject_zero_sign_s <= 1'b0; + end + end else begin release caliptra_top_dut.ecc_top1.ecc_dsa_ctrl_i.ecc_arith_unit_i.d_o; end diff --git a/src/integration/test_suites/smoke_test_ecc_errortrigger/smoke_test_ecc_errortrigger.c b/src/integration/test_suites/smoke_test_ecc_errortrigger/smoke_test_ecc_errortrigger.c index d6d358ca7..5233f778c 100644 --- a/src/integration/test_suites/smoke_test_ecc_errortrigger/smoke_test_ecc_errortrigger.c +++ b/src/integration/test_suites/smoke_test_ecc_errortrigger/smoke_test_ecc_errortrigger.c @@ -563,7 +563,96 @@ void main() { } ecc_zeroize(); - } + //Issue warm reset + rst_count++; + printf("%c",0xf6); + } + else if(rst_count == 9) { + // wait for ECC to be ready + while((lsu_read_32(CLP_ECC_REG_ECC_STATUS) & ECC_REG_ECC_STATUS_READY_MASK) == 0); + + printf("\n TEST INVALID OUTPUT SIGN_S\n"); + // Program ECC PRIVKEY + reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_PRIVKEY_IN_0; + offset = 0; + while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_PRIVKEY_IN_11) { + *reg_ptr++ = ecc_privkey[offset++]; + } + + // Program ECC MSG + reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_MSG_0; + offset = 0; + while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_MSG_11) { + *reg_ptr++ = ecc_msg[offset++]; + } + + // Program ECC IV + reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_IV_0; + offset = 0; + while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_IV_11) { + *reg_ptr++ = ecc_iv[offset++]; + } + + //Inject invalid zero sign_s + printf("%c",0x9a); + + // Enable ECC SIGNING core + printf("\nECC SIGNING\n"); + lsu_write_32(CLP_ECC_REG_ECC_CTRL, ECC_CMD_SIGNING); + + // wait for ECC SIGNING process to be done + wait_for_ecc_intr(); + if ((cptra_intr_rcv.ecc_error == 0)){ + printf("\nECC s_output_outofrange error is not detected.\n"); + printf("%c", 0x1); + while(1); + } + + ecc_zeroize(); + //Issue warm reset + rst_count++; + printf("%c",0xf6); + } + else if(rst_count == 10) { + // wait for ECC to be ready + while((lsu_read_32(CLP_ECC_REG_ECC_STATUS) & ECC_REG_ECC_STATUS_READY_MASK) == 0); + + printf("\n TEST PCR WITH INVALID OUTPUT SIGN_S\n"); + + // Program ECC IV + reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_IV_0; + offset = 0; + while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_IV_11) { + *reg_ptr++ = ecc_iv[offset++]; + } + + //Inject invalid zero sign_s + printf("%c",0x9a); + + //inject seed to kv key reg (in RTL) + printf("Inject PRIVKEY into KV slot 7\n"); + privkey_inject_cmd = 0x88 + 0x7; + printf("%c", privkey_inject_cmd); + + printf("Inject MSG into SHA512 digest\n"); + printf("%c", 0x90); + + // Enable ECC PCR SIGNING core + printf("\nECC PCR SIGNING\n"); + lsu_write_32(CLP_ECC_REG_ECC_CTRL, ECC_CMD_SIGNING | + ((1 << ECC_REG_ECC_CTRL_PCR_SIGN_LOW) & ECC_REG_ECC_CTRL_PCR_SIGN_MASK)); + + + // wait for ECC PCR SIGNING process to be done + wait_for_ecc_intr(); + if ((cptra_intr_rcv.ecc_error == 0)){ + printf("\nECC PCR s_output_outofrange error is not detected.\n"); + printf("%c", 0x1); + while(1); + } + + ecc_zeroize(); + } printf("%c",0xff); //End the test From 121689d752588636f147de21c1515e650278db3e Mon Sep 17 00:00:00 2001 From: Michael Norris Date: Tue, 26 Sep 2023 20:08:39 +0000 Subject: [PATCH 06/11] Merged PR 125683: Scan mode dft override and synchronizer removal - fix for scan coverage Removing synchronizer from scan mode signal on reset override. Adding warm reset pin to drive reset during scan mode for max coverage. Related work items: #555293 --- src/ahb_lite_bus/rtl/ahb_lite_bus.sv | 2 +- src/integration/rtl/caliptra_top.sv | 6 +++--- src/soc_ifc/rtl/soc_ifc_boot_fsm.sv | 6 +++--- src/soc_ifc/rtl/soc_ifc_top.sv | 14 +++++++------- src/soc_ifc/tb/soc_ifc_tb.sv | 8 ++++---- .../soc_ifc/tb/testbench/hdl_top.sv | 2 +- 6 files changed, 19 insertions(+), 19 deletions(-) diff --git a/src/ahb_lite_bus/rtl/ahb_lite_bus.sv b/src/ahb_lite_bus/rtl/ahb_lite_bus.sv index 4cc2cc372..b6a088d9e 100644 --- a/src/ahb_lite_bus/rtl/ahb_lite_bus.sv +++ b/src/ahb_lite_bus/rtl/ahb_lite_bus.sv @@ -36,7 +36,7 @@ module ahb_lite_bus #( // -------------------------------------- // Responder Interface Port // -------------------------------------- - CALIPTRA_AHB_LITE_BUS_INF.Responder_Interface_Ports ahb_lite_responders[NUM_RESPONDERS-1:0], + CALIPTRA_AHB_LITE_BUS_INF.Responder_Interface_Ports ahb_lite_responders[0:NUM_RESPONDERS-1], // ---------------------------------------------- // Respnder Disable diff --git a/src/integration/rtl/caliptra_top.sv b/src/integration/rtl/caliptra_top.sv index 3937626d9..94bffc153 100755 --- a/src/integration/rtl/caliptra_top.sv +++ b/src/integration/rtl/caliptra_top.sv @@ -285,7 +285,7 @@ end .AHB_LITE_ADDR_WIDTH(`CALIPTRA_AHB_HADDR_SIZE), .AHB_LITE_DATA_WIDTH(`CALIPTRA_AHB_HDATA_SIZE) ) - responder_inst[`CALIPTRA_AHB_SLAVES_NUM-1:0](); + responder_inst[0:`CALIPTRA_AHB_SLAVES_NUM-1](); //======================================================================== // AHB Master ports @@ -540,7 +540,7 @@ el2_veer_wrapper rvtop ( .soft_int (soft_int), .core_id ('0), - .scan_mode ( cptra_scan_mode_Latched ), // To enable scan mode + .scan_mode ( scan_mode ), // To enable scan mode .mbist_mode ( 1'b0 ) // to enable mbist ); @@ -1236,7 +1236,7 @@ soc_ifc_top1 .timer_intr(timer_int), //Obfuscated UDS and FE .clear_obf_secrets(clear_obf_secrets_debugScanQ), //input - includes debug & scan modes to do the register clearing - .scan_mode_f(cptra_scan_mode_Latched), + .scan_mode(scan_mode), .cptra_obf_key(cptra_obf_key), .cptra_obf_key_reg(cptra_obf_key_reg), .obf_field_entropy(obf_field_entropy), diff --git a/src/soc_ifc/rtl/soc_ifc_boot_fsm.sv b/src/soc_ifc/rtl/soc_ifc_boot_fsm.sv index e5b522184..a04e3678e 100644 --- a/src/soc_ifc/rtl/soc_ifc_boot_fsm.sv +++ b/src/soc_ifc/rtl/soc_ifc_boot_fsm.sv @@ -230,9 +230,9 @@ always_ff @(posedge clk or negedge cptra_pwrgood) begin end //protect resets during scan mode -//TODO dft override for reset? -assign cptra_noncore_rst_b = cptra_noncore_rst_b_nq | scan_mode; -assign cptra_uc_rst_b = cptra_uc_rst_b_nq | scan_mode; +//utilize warm reset pin to drive reset during scan mode +assign cptra_noncore_rst_b = scan_mode ? cptra_rst_b : cptra_noncore_rst_b_nq; +assign cptra_uc_rst_b = scan_mode ? cptra_rst_b : cptra_uc_rst_b_nq; //uC reset generation always_ff @(posedge clk or negedge cptra_rst_b) begin diff --git a/src/soc_ifc/rtl/soc_ifc_top.sv b/src/soc_ifc/rtl/soc_ifc_top.sv index 5629dd4b5..618c2eea5 100644 --- a/src/soc_ifc/rtl/soc_ifc_top.sv +++ b/src/soc_ifc/rtl/soc_ifc_top.sv @@ -94,7 +94,7 @@ module soc_ifc_top //Obfuscated UDS and FE input logic clear_obf_secrets, - input logic scan_mode_f, + input logic scan_mode, input logic [`CLP_OBF_KEY_DWORDS-1:0][31:0] cptra_obf_key, output logic [`CLP_OBF_KEY_DWORDS-1:0][31:0] cptra_obf_key_reg, output logic [`CLP_OBF_FE_DWORDS-1 :0][31:0] obf_field_entropy, @@ -174,7 +174,7 @@ logic uc_mbox_data_avail_d; logic uc_cmd_avail_p; logic security_state_debug_locked_d; logic security_state_debug_locked_p; -logic scan_mode_d; +logic scan_mode_f; logic scan_mode_p; logic sram_single_ecc_error; logic sram_double_ecc_error; @@ -235,7 +235,7 @@ soc_ifc_boot_fsm i_soc_ifc_boot_fsm ( .clk(clk), .cptra_pwrgood(cptra_pwrgood), .cptra_rst_b (cptra_rst_b), - .scan_mode(scan_mode_f), + .scan_mode(scan_mode), .fw_update_rst (soc_ifc_reg_hwif_out.internal_fw_update_reset.core_rst.value), .fw_update_rst_wait_cycles (soc_ifc_reg_hwif_out.internal_fw_update_reset_wait_cycles.wait_cycles.value), .ready_for_fuses(ready_for_fuses), @@ -442,7 +442,7 @@ always_comb begin soc_ifc_reg_hwif_in.CPTRA_FLOW_STATUS.boot_fsm_ps.next = boot_fsm_ps; soc_ifc_reg_hwif_in.CPTRA_SECURITY_STATE.device_lifecycle.next = security_state.device_lifecycle; soc_ifc_reg_hwif_in.CPTRA_SECURITY_STATE.debug_locked.next = security_state.debug_locked; - soc_ifc_reg_hwif_in.CPTRA_SECURITY_STATE.scan_mode.next = scan_mode_f; + soc_ifc_reg_hwif_in.CPTRA_SECURITY_STATE.scan_mode.next = scan_mode; //generic wires for (int i = 0; i < 2; i++) begin generic_output_wires[i] = soc_ifc_reg_hwif_out.CPTRA_GENERIC_OUTPUT_WIRES[i].generic_wires.value; @@ -531,14 +531,14 @@ always_comb security_state_debug_locked_p = security_state.debug_locked ^ securi // Generate a pulse to set the interrupt bit always_ff @(posedge clk or negedge cptra_noncore_rst_b) begin if (~cptra_noncore_rst_b) begin - scan_mode_d <= '0; + scan_mode_f <= '0; end else begin - scan_mode_d <= scan_mode_f; + scan_mode_f <= scan_mode; end end -always_comb scan_mode_p = scan_mode_f & ~scan_mode_d; +always_comb scan_mode_p = scan_mode & ~scan_mode_f; //Filtering by PAUSER always_comb begin diff --git a/src/soc_ifc/tb/soc_ifc_tb.sv b/src/soc_ifc/tb/soc_ifc_tb.sv index 7a50704d0..46cd5641a 100644 --- a/src/soc_ifc/tb/soc_ifc_tb.sv +++ b/src/soc_ifc/tb/soc_ifc_tb.sv @@ -137,7 +137,7 @@ module soc_ifc_tb logic [31:0] generic_input_wires1; logic clear_obf_secrets; - logic scan_mode_f; + logic scan_mode; // obfuscation, uds and field entropy for observation logic [`CLP_OBF_KEY_DWORDS-1:0][31:0] cptra_obf_key_reg; @@ -265,7 +265,7 @@ module soc_ifc_tb .rv_ecc_sts(rv_ecc_sts_t'{default:1'b0}), .clear_obf_secrets(clear_obf_secrets), - .scan_mode_f(scan_mode_f), + .scan_mode(scan_mode), .cptra_obf_key('0), .cptra_obf_key_reg(cptra_obf_key_reg), .obf_field_entropy(obf_field_entropy), @@ -327,7 +327,7 @@ module soc_ifc_tb // Tie-offs - assign scan_mode_f = 1'b0; + assign scan_mode = 1'b0; assign clear_obf_secrets = 1'b0; @@ -422,7 +422,7 @@ module soc_ifc_tb // CPTRA SECUIRTY_STATE, FLOW_STATUS, GENERIC_INPUT_WIRES //---------------------------------------------------------------- - always_comb update_CPTRA_SECURITY_STATE(scan_mode_f, security_state.debug_locked, security_state.device_lifecycle); + always_comb update_CPTRA_SECURITY_STATE(scan_mode, security_state.debug_locked, security_state.device_lifecycle); always_comb update_CPTRA_FLOW_STATUS(ready_for_fuses, `REG_HIER_BOOT_FSM_PS); always_comb update_CPTRA_GENERIC_INPUT_WIRES(generic_input_wires1_q, 1'b1); always_comb update_CPTRA_GENERIC_INPUT_WIRES(generic_input_wires0_q, 1'b0); diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/testbench/hdl_top.sv b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/testbench/hdl_top.sv index 621ee5af9..38ef2b1da 100644 --- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/testbench/hdl_top.sv +++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/testbench/hdl_top.sv @@ -201,7 +201,7 @@ import uvmf_base_pkg_hdl::*; .rv_ecc_sts(cptra_ctrl_agent_bus.rv_ecc_sts), //Obfuscated UDS and FE .clear_obf_secrets(cptra_ctrl_agent_bus.clear_obf_secrets), - .scan_mode_f (1'b0), + .scan_mode (1'b0), .cptra_obf_key(soc_ifc_ctrl_agent_bus.cptra_obf_key), .cptra_obf_key_reg(cptra_status_agent_bus.cptra_obf_key_reg), .obf_field_entropy(cptra_status_agent_bus.obf_field_entropy), From e39cc0b3c526a65b9a60ab90ea1e6a19446a3a0e Mon Sep 17 00:00:00 2001 From: Kiran Upadhyayula Date: Tue, 26 Sep 2023 22:56:22 +0000 Subject: [PATCH 07/11] Merged PR 126213: Check for pending t1 interrupt before changing timeout values in RT fw Related work items: #562658 --- src/integration/test_suites/caliptra_rt/caliptra_rt.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/integration/test_suites/caliptra_rt/caliptra_rt.c b/src/integration/test_suites/caliptra_rt/caliptra_rt.c index b8968fc00..59adf843c 100644 --- a/src/integration/test_suites/caliptra_rt/caliptra_rt.c +++ b/src/integration/test_suites/caliptra_rt/caliptra_rt.c @@ -172,10 +172,14 @@ void caliptra_rt() { //Clear timer1 intr lsu_write_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R, SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK); - //Program timer1 and 2 periods to <= 0x100 to test NMI generation + //Program timer1 and 2 periods to <= 0x100 to test NMI generation. First check if there is any pending timer1 interrupt. In a corner case scenario, timer1 can timeout a second time (if the period is small enough) + //before its timeout value is changed in prep for NMI testing. In that case, the subsequent timer1 interrupt will not be serviced resulting in a hang wdt_rand_t1_val = (rand() % 0x100) + 0x5; wdt_rand_t2_val = (rand() % 0x100) + 0x5; + if (lsu_read_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R) & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK) + lsu_write_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R, SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK); + //WDT cascade mode with t2 timeout lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_EN, !SOC_IFC_REG_CPTRA_WDT_TIMER2_EN_TIMER2_EN_MASK); lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0, wdt_rand_t1_val); From a3c29b84b7cb82cb1ca351ebb25826a0e89b10e0 Mon Sep 17 00:00:00 2001 From: Michael Norris Date: Fri, 29 Sep 2023 02:05:09 +0000 Subject: [PATCH 08/11] Merged PR 126577: Coverage merge all duts Pipeline to merge all duts coverage into one database Related work items: #563789 --- coverage/config/clp_mapfile | 36 +++++++++++++++++++ coverage/config/uvmf_soc_ifc_caliptra_tb.yml | 13 +++++++ src/aes/config/aes.vf | 1 + src/aes/config/aes_pkg.vf | 1 + src/ahb_lite_bus/config/ahb_lite_bus.vf | 1 + src/caliptra_prim/config/caliptra_prim.vf | 1 + src/caliptra_prim/config/caliptra_prim_pkg.vf | 1 + .../config/caliptra_prim_generic.vf | 1 + src/csrng/config/csrng.vf | 1 + src/csrng/config/csrng_pkg.vf | 1 + src/csrng/config/csrng_tb.vf | 1 + src/datavault/config/datavault.vf | 1 + src/datavault/config/dv_defines_pkg.vf | 1 + src/datavault/config/dv_uvm_pkg.vf | 1 + src/doe/config/doe_cbc_tb.vf | 1 + src/doe/config/doe_core_cbc_tb.vf | 1 + src/doe/config/doe_ctrl.vf | 1 + src/doe/config/doe_defines_pkg.vf | 1 + src/ecc/config/ecc_montgomerymultiplier_tb.vf | 1 + src/ecc/config/ecc_top.vf | 1 + src/ecc/config/ecc_top_tb.vf | 1 + .../ECC/tb/testbench/hdl_top.sv | 1 + src/edn/config/edn_pkg.vf | 1 + src/entropy_src/config/entropy_src.vf | 1 + src/entropy_src/config/entropy_src_pkg.vf | 1 + src/entropy_src/config/entropy_src_tb.vf | 1 + src/hmac/config/hmac_ctrl.vf | 1 + src/hmac/config/hmac_ctrl_tb.vf | 1 + .../HMAC/tb/testbench/hdl_top.sv | 1 + src/hmac_drbg/config/hmac_drbg.vf | 1 + src/hmac_drbg/config/hmac_drbg_tb.vf | 1 + src/integration/asserts/config/asserts.vf | 1 + src/integration/config/caliptra_top.vf | 1 + .../config/caliptra_top_defines.vf | 1 + src/integration/config/caliptra_top_tb.vf | 9 +++++ .../config/caliptra_top_trng_tb.vf | 9 +++++ src/integration/config/compile.yml | 2 ++ .../tb/caliptra_top_tb_services.sv | 2 ++ .../uvmf_caliptra_top/config/compile.yml | 2 ++ src/keyvault/config/keyvault.vf | 1 + src/keyvault/config/keyvault_cov.vf | 1 + src/keyvault/config/kv_defines_pkg.vf | 1 + src/keyvault/config/kv_uvm_pkg.vf | 1 + src/keyvault/coverage/keyvault_cov_bind.sv | 8 ++--- src/kmac/config/kmac.vf | 1 + src/kmac/config/kmac_pkg.vf | 1 + src/lc_ctrl/config/lc_ctrl_pkg.vf | 1 + src/libs/config/libs.vf | 1 + src/pcrvault/config/pcrvault.vf | 1 + src/pcrvault/config/pcrvault_cov.vf | 1 + src/pcrvault/config/pv_defines_pkg.vf | 1 + src/pcrvault/config/pv_uvm_pkg.vf | 1 + src/pcrvault/coverage/pcrvault_cov_bind.sv | 8 ++--- .../veer_el2/config/el2_veer_pkg.vf | 1 + .../veer_el2/config/el2_veer_wrapper.vf | 1 + .../veer_el2/config/el2_veer_wrapper_tb.vf | 1 + src/sha256/config/sha256_ctrl.vf | 1 + src/sha256/config/sha256_ctrl_tb.vf | 1 + src/sha256/config/sha256_random_test.vf | 1 + src/sha512/config/sha512_ctrl.vf | 1 + src/sha512/config/sha512_ctrl_32bit_tb.vf | 1 + .../SHA512/tb/testbench/hdl_top.sv | 2 ++ .../config/sha512_masked_core.vf | 1 + .../config/sha512_masked_core_tb.vf | 1 + src/soc_ifc/config/soc_ifc_pkg.vf | 1 + src/soc_ifc/config/soc_ifc_tb.vf | 1 + src/soc_ifc/config/soc_ifc_top.vf | 1 + src/soc_ifc/config/soc_ifc_uvm_pkg.vf | 1 + src/soc_ifc/uvmf_soc_ifc/config/compile.yml | 1 + .../soc_ifc/tb/testbench/hdl_top.sv | 3 ++ src/spi_host/config/spi_host.vf | 1 + src/spi_host/config/spi_host_tb.vf | 1 + src/spi_host/config/spiflash.vf | 1 + src/uart/config/uart.vf | 1 + src/uart/config/uart_tb.vf | 1 + 75 files changed, 150 insertions(+), 8 deletions(-) create mode 100644 coverage/config/clp_mapfile create mode 100644 coverage/config/uvmf_soc_ifc_caliptra_tb.yml diff --git a/coverage/config/clp_mapfile b/coverage/config/clp_mapfile new file mode 100644 index 000000000..c2c9c1336 --- /dev/null +++ b/coverage/config/clp_mapfile @@ -0,0 +1,36 @@ +MODULE: caliptra_top +INSTANCE: +SRC: caliptra_top_tb.caliptra_top_dut +DST: hdl_top.caliptra_top_dut + +MODULE: soc_ifc_top +INSTANCE: +SRC: hdl_top.dut +DST: hdl_top.caliptra_top_dut.soc_ifc_top1 +SRC: soc_ifc_tb.dut +DST: hdl_top.caliptra_top_dut.soc_ifc_top1 + +MODULE: ecc_top +INSTANCE: +SRC: hdl_top.dut +DST: hdl_top.caliptra_top_dut.ecc_top1 + +MODULE: hmac_ctrl +INSTANCE: +SRC: hdl_top.dut +DST: hdl_top.caliptra_top_dut.hmac + +MODULE: kv +INSTANCE: +SRC: hdl_top.dut +DST: hdl_top.caliptra_top_dut.key_vault1 + +MODULE: pv +INSTANCE: +SRC: hdl_top.pv +DST: hdl_top.caliptra_top_dut.pcr_vault1 + +MODULE: sha512_ctrl +INSTANCE: +SRC: hdl_top.dut +DST: hdl_top.caliptra_top_dut.sha512 \ No newline at end of file diff --git a/coverage/config/uvmf_soc_ifc_caliptra_tb.yml b/coverage/config/uvmf_soc_ifc_caliptra_tb.yml new file mode 100644 index 000000000..de768258e --- /dev/null +++ b/coverage/config/uvmf_soc_ifc_caliptra_tb.yml @@ -0,0 +1,13 @@ +# Copyright (C) Microsoft Corporation. All rights reserved. + +# Repo/Bench config specific settings +# For repo-specific file, common settings like retention policy, additional merge options etc can be specified + +# +# https://dev.azure.com/ms-tsd/Base_Verification/_wiki/wikis/Base_Verification.wiki/34333/Coverage-merge-YAML +# + +variables: + BENCH_CONFIG: uvmf_soc_ifc + +template: caliptra_cov_cfg.yml diff --git a/src/aes/config/aes.vf b/src/aes/config/aes.vf index 9592049a5..97ae18b1e 100644 --- a/src/aes/config/aes.vf +++ b/src/aes/config/aes.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl diff --git a/src/aes/config/aes_pkg.vf b/src/aes/config/aes_pkg.vf index 5c75eb1af..4ae176a70 100644 --- a/src/aes/config/aes_pkg.vf +++ b/src/aes/config/aes_pkg.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl diff --git a/src/ahb_lite_bus/config/ahb_lite_bus.vf b/src/ahb_lite_bus/config/ahb_lite_bus.vf index 86fbbb2e2..77806285c 100644 --- a/src/ahb_lite_bus/config/ahb_lite_bus.vf +++ b/src/ahb_lite_bus/config/ahb_lite_bus.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl diff --git a/src/caliptra_prim/config/caliptra_prim.vf b/src/caliptra_prim/config/caliptra_prim.vf index 59740aec8..49501fa5e 100644 --- a/src/caliptra_prim/config/caliptra_prim.vf +++ b/src/caliptra_prim/config/caliptra_prim.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl diff --git a/src/caliptra_prim/config/caliptra_prim_pkg.vf b/src/caliptra_prim/config/caliptra_prim_pkg.vf index dfed9ddd5..4d5c4720b 100644 --- a/src/caliptra_prim/config/caliptra_prim_pkg.vf +++ b/src/caliptra_prim/config/caliptra_prim_pkg.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_alert_pkg.sv diff --git a/src/caliptra_prim_generic/config/caliptra_prim_generic.vf b/src/caliptra_prim_generic/config/caliptra_prim_generic.vf index 38af67734..29d0649a4 100644 --- a/src/caliptra_prim_generic/config/caliptra_prim_generic.vf +++ b/src/caliptra_prim_generic/config/caliptra_prim_generic.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl ${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop_en.sv ${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv diff --git a/src/csrng/config/csrng.vf b/src/csrng/config/csrng.vf index ef06dd886..06245ddcc 100644 --- a/src/csrng/config/csrng.vf +++ b/src/csrng/config/csrng.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl diff --git a/src/csrng/config/csrng_pkg.vf b/src/csrng/config/csrng_pkg.vf index 6badfdba1..6d0386cb0 100644 --- a/src/csrng/config/csrng_pkg.vf +++ b/src/csrng/config/csrng_pkg.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl +incdir+${CALIPTRA_ROOT}/src/csrng/rtl ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm_pkg.sv diff --git a/src/csrng/config/csrng_tb.vf b/src/csrng/config/csrng_tb.vf index 4793e52ec..b54328edb 100644 --- a/src/csrng/config/csrng_tb.vf +++ b/src/csrng/config/csrng_tb.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl diff --git a/src/datavault/config/datavault.vf b/src/datavault/config/datavault.vf index 829d888e8..ef7c7d194 100644 --- a/src/datavault/config/datavault.vf +++ b/src/datavault/config/datavault.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/datavault/rtl diff --git a/src/datavault/config/dv_defines_pkg.vf b/src/datavault/config/dv_defines_pkg.vf index e0f236757..5caf89c26 100644 --- a/src/datavault/config/dv_defines_pkg.vf +++ b/src/datavault/config/dv_defines_pkg.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/datavault/rtl ${CALIPTRA_ROOT}/src/datavault/rtl/dv_defines_pkg.sv ${CALIPTRA_ROOT}/src/datavault/rtl/dv_defines_pkg.sv \ No newline at end of file diff --git a/src/datavault/config/dv_uvm_pkg.vf b/src/datavault/config/dv_uvm_pkg.vf index 16b523f56..d49e18a4d 100644 --- a/src/datavault/config/dv_uvm_pkg.vf +++ b/src/datavault/config/dv_uvm_pkg.vf @@ -1,2 +1,3 @@ + +incdir+${CALIPTRA_ROOT}/src/datavault/rtl ${CALIPTRA_ROOT}/src/datavault/rtl/dv_reg_uvm.sv \ No newline at end of file diff --git a/src/doe/config/doe_cbc_tb.vf b/src/doe/config/doe_cbc_tb.vf index 343b1bc45..57c5ab16d 100644 --- a/src/doe/config/doe_cbc_tb.vf +++ b/src/doe/config/doe_cbc_tb.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl diff --git a/src/doe/config/doe_core_cbc_tb.vf b/src/doe/config/doe_core_cbc_tb.vf index be61bb115..4f252f2ab 100644 --- a/src/doe/config/doe_core_cbc_tb.vf +++ b/src/doe/config/doe_core_cbc_tb.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl diff --git a/src/doe/config/doe_ctrl.vf b/src/doe/config/doe_ctrl.vf index 09ff0b298..0b25365b2 100644 --- a/src/doe/config/doe_ctrl.vf +++ b/src/doe/config/doe_ctrl.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl diff --git a/src/doe/config/doe_defines_pkg.vf b/src/doe/config/doe_defines_pkg.vf index 2bd3dd260..a2f3e9ab8 100644 --- a/src/doe/config/doe_defines_pkg.vf +++ b/src/doe/config/doe_defines_pkg.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/doe/rtl ${CALIPTRA_ROOT}/src/doe/rtl/doe_defines_pkg.sv ${CALIPTRA_ROOT}/src/doe/rtl/doe_defines_pkg.sv \ No newline at end of file diff --git a/src/ecc/config/ecc_montgomerymultiplier_tb.vf b/src/ecc/config/ecc_montgomerymultiplier_tb.vf index 0754d8f22..03ff15a97 100644 --- a/src/ecc/config/ecc_montgomerymultiplier_tb.vf +++ b/src/ecc/config/ecc_montgomerymultiplier_tb.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl diff --git a/src/ecc/config/ecc_top.vf b/src/ecc/config/ecc_top.vf index 51e02138b..2af9e7727 100644 --- a/src/ecc/config/ecc_top.vf +++ b/src/ecc/config/ecc_top.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl diff --git a/src/ecc/config/ecc_top_tb.vf b/src/ecc/config/ecc_top_tb.vf index ea081512c..7c34bdeb3 100644 --- a/src/ecc/config/ecc_top_tb.vf +++ b/src/ecc/config/ecc_top_tb.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl diff --git a/src/ecc/uvmf_ecc/uvmf_template_output/project_benches/ECC/tb/testbench/hdl_top.sv b/src/ecc/uvmf_ecc/uvmf_template_output/project_benches/ECC/tb/testbench/hdl_top.sv index d9d9209bb..01fffdedb 100644 --- a/src/ecc/uvmf_ecc/uvmf_template_output/project_benches/ECC/tb/testbench/hdl_top.sv +++ b/src/ecc/uvmf_ecc/uvmf_template_output/project_benches/ECC/tb/testbench/hdl_top.sv @@ -120,6 +120,7 @@ import uvmf_base_pkg_hdl::*; .debugUnlock_or_scan_mode_switch('0) ); + ecc_top_cov_bind i_ecc_top_cov_bind(); // pragma uvmf custom dut_instantiation end initial begin // tbx vif_binding_block diff --git a/src/edn/config/edn_pkg.vf b/src/edn/config/edn_pkg.vf index cc750fdb6..3da7239ed 100644 --- a/src/edn/config/edn_pkg.vf +++ b/src/edn/config/edn_pkg.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl +incdir+${CALIPTRA_ROOT}/src/edn/rtl ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm_pkg.sv diff --git a/src/entropy_src/config/entropy_src.vf b/src/entropy_src/config/entropy_src.vf index f8a916e71..d27b6f989 100644 --- a/src/entropy_src/config/entropy_src.vf +++ b/src/entropy_src/config/entropy_src.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl diff --git a/src/entropy_src/config/entropy_src_pkg.vf b/src/entropy_src/config/entropy_src_pkg.vf index 8d4b48b40..21d2f59ff 100644 --- a/src/entropy_src/config/entropy_src_pkg.vf +++ b/src/entropy_src/config/entropy_src_pkg.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_main_sm_pkg.sv ${CALIPTRA_ROOT}/src/entropy_src/rtl/entropy_src_ack_sm_pkg.sv diff --git a/src/entropy_src/config/entropy_src_tb.vf b/src/entropy_src/config/entropy_src_tb.vf index f0f720b91..895ea5b5d 100644 --- a/src/entropy_src/config/entropy_src_tb.vf +++ b/src/entropy_src/config/entropy_src_tb.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/entropy_src/rtl +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl diff --git a/src/hmac/config/hmac_ctrl.vf b/src/hmac/config/hmac_ctrl.vf index 666c3371f..f4b3c6952 100644 --- a/src/hmac/config/hmac_ctrl.vf +++ b/src/hmac/config/hmac_ctrl.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl diff --git a/src/hmac/config/hmac_ctrl_tb.vf b/src/hmac/config/hmac_ctrl_tb.vf index 1ca5eaa69..ac588c35c 100644 --- a/src/hmac/config/hmac_ctrl_tb.vf +++ b/src/hmac/config/hmac_ctrl_tb.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl diff --git a/src/hmac/uvmf_2022/uvmf_template_output/project_benches/HMAC/tb/testbench/hdl_top.sv b/src/hmac/uvmf_2022/uvmf_template_output/project_benches/HMAC/tb/testbench/hdl_top.sv index feeda3abe..24bbe0a1c 100644 --- a/src/hmac/uvmf_2022/uvmf_template_output/project_benches/HMAC/tb/testbench/hdl_top.sv +++ b/src/hmac/uvmf_2022/uvmf_template_output/project_benches/HMAC/tb/testbench/hdl_top.sv @@ -108,6 +108,7 @@ hmac_ctrl #( .debugUnlock_or_scan_mode_switch('0) ); +hmac_ctrl_cov_bind i_hmac_ctrl_cov_bind(); // pragma uvmf custom dut_instantiation end initial begin // tbx vif_binding_block diff --git a/src/hmac_drbg/config/hmac_drbg.vf b/src/hmac_drbg/config/hmac_drbg.vf index 2e7367213..1c00130ee 100644 --- a/src/hmac_drbg/config/hmac_drbg.vf +++ b/src/hmac_drbg/config/hmac_drbg.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl diff --git a/src/hmac_drbg/config/hmac_drbg_tb.vf b/src/hmac_drbg/config/hmac_drbg_tb.vf index 9754c6784..96d3675d1 100644 --- a/src/hmac_drbg/config/hmac_drbg_tb.vf +++ b/src/hmac_drbg/config/hmac_drbg_tb.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl diff --git a/src/integration/asserts/config/asserts.vf b/src/integration/asserts/config/asserts.vf index 9e5fd10c5..af9a0394b 100644 --- a/src/integration/asserts/config/asserts.vf +++ b/src/integration/asserts/config/asserts.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl +incdir+${CALIPTRA_ROOT}/src/doe/rtl +incdir+${CALIPTRA_ROOT}/src/integration/asserts diff --git a/src/integration/config/caliptra_top.vf b/src/integration/config/caliptra_top.vf index 44074db29..c25142575 100644 --- a/src/integration/config/caliptra_top.vf +++ b/src/integration/config/caliptra_top.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl diff --git a/src/integration/config/caliptra_top_defines.vf b/src/integration/config/caliptra_top_defines.vf index 32aaeaef2..c60a9363b 100644 --- a/src/integration/config/caliptra_top_defines.vf +++ b/src/integration/config/caliptra_top_defines.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/integration/rtl ${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh ${CALIPTRA_ROOT}/src/integration/rtl/caliptra_reg_defines.svh diff --git a/src/integration/config/caliptra_top_tb.vf b/src/integration/config/caliptra_top_tb.vf index 836578fd2..477862615 100644 --- a/src/integration/config/caliptra_top_tb.vf +++ b/src/integration/config/caliptra_top_tb.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl +incdir+${CALIPTRA_ROOT}/src/doe/rtl +incdir+${CALIPTRA_ROOT}/src/integration/asserts @@ -20,6 +21,8 @@ +incdir+${CALIPTRA_ROOT}/src/hmac/coverage +incdir+${CALIPTRA_ROOT}/src/ecc/coverage +incdir+${CALIPTRA_ROOT}/src/soc_ifc/coverage ++incdir+${CALIPTRA_ROOT}/src/pcrvault/coverage ++incdir+${CALIPTRA_ROOT}/src/keyvault/coverage +incdir+${CALIPTRA_ROOT}/src/integration/tb +incdir+${CALIPTRA_ROOT}/src/integration/coverage +incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl @@ -90,6 +93,12 @@ ${CALIPTRA_ROOT}/src/ecc/coverage/ecc_top_cov_if.sv ${CALIPTRA_ROOT}/src/ecc/coverage/ecc_top_cov_bind.sv ${CALIPTRA_ROOT}/src/soc_ifc/coverage/soc_ifc_cov_if.sv ${CALIPTRA_ROOT}/src/soc_ifc/coverage/soc_ifc_cov_bind.sv +${CALIPTRA_ROOT}/src/pcrvault/coverage/pcrvault_cov_if.sv +${CALIPTRA_ROOT}/src/pcrvault/coverage/pcrvault_cov_props.sv +${CALIPTRA_ROOT}/src/pcrvault/coverage/pcrvault_cov_bind.sv +${CALIPTRA_ROOT}/src/keyvault/coverage/keyvault_cov_if.sv +${CALIPTRA_ROOT}/src/keyvault/coverage/keyvault_cov_props.sv +${CALIPTRA_ROOT}/src/keyvault/coverage/keyvault_cov_bind.sv ${CALIPTRA_ROOT}/src/integration/tb/caliptra_top_tb_pkg.sv ${CALIPTRA_ROOT}/src/integration/tb/caliptra_veer_sram_export.sv ${CALIPTRA_ROOT}/src/integration/tb/caliptra_top_tb_services.sv diff --git a/src/integration/config/caliptra_top_trng_tb.vf b/src/integration/config/caliptra_top_trng_tb.vf index 6e8b39584..b770d4870 100644 --- a/src/integration/config/caliptra_top_trng_tb.vf +++ b/src/integration/config/caliptra_top_trng_tb.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl +incdir+${CALIPTRA_ROOT}/src/doe/rtl +incdir+${CALIPTRA_ROOT}/src/integration/asserts @@ -20,6 +21,8 @@ +incdir+${CALIPTRA_ROOT}/src/hmac/coverage +incdir+${CALIPTRA_ROOT}/src/ecc/coverage +incdir+${CALIPTRA_ROOT}/src/soc_ifc/coverage ++incdir+${CALIPTRA_ROOT}/src/pcrvault/coverage ++incdir+${CALIPTRA_ROOT}/src/keyvault/coverage +incdir+${CALIPTRA_ROOT}/src/integration/tb +incdir+${CALIPTRA_ROOT}/src/integration/coverage +incdir+${CALIPTRA_ROOT}/src/caliptra_prim_generic/rtl @@ -90,6 +93,12 @@ ${CALIPTRA_ROOT}/src/ecc/coverage/ecc_top_cov_if.sv ${CALIPTRA_ROOT}/src/ecc/coverage/ecc_top_cov_bind.sv ${CALIPTRA_ROOT}/src/soc_ifc/coverage/soc_ifc_cov_if.sv ${CALIPTRA_ROOT}/src/soc_ifc/coverage/soc_ifc_cov_bind.sv +${CALIPTRA_ROOT}/src/pcrvault/coverage/pcrvault_cov_if.sv +${CALIPTRA_ROOT}/src/pcrvault/coverage/pcrvault_cov_props.sv +${CALIPTRA_ROOT}/src/pcrvault/coverage/pcrvault_cov_bind.sv +${CALIPTRA_ROOT}/src/keyvault/coverage/keyvault_cov_if.sv +${CALIPTRA_ROOT}/src/keyvault/coverage/keyvault_cov_props.sv +${CALIPTRA_ROOT}/src/keyvault/coverage/keyvault_cov_bind.sv ${CALIPTRA_ROOT}/src/integration/tb/caliptra_top_tb_pkg.sv ${CALIPTRA_ROOT}/src/integration/tb/caliptra_veer_sram_export.sv ${CALIPTRA_ROOT}/src/integration/tb/caliptra_top_tb_services.sv diff --git a/src/integration/config/compile.yml b/src/integration/config/compile.yml index 564ce173c..607940696 100644 --- a/src/integration/config/compile.yml +++ b/src/integration/config/compile.yml @@ -74,6 +74,8 @@ requires: - hmac_coverage - ecc_coverage - soc_ifc_coverage + - pcrvault_cov + - keyvault_cov targets: dpi_compile: directories: diff --git a/src/integration/tb/caliptra_top_tb_services.sv b/src/integration/tb/caliptra_top_tb_services.sv index c55f07969..817ae3129 100644 --- a/src/integration/tb/caliptra_top_tb_services.sv +++ b/src/integration/tb/caliptra_top_tb_services.sv @@ -1677,6 +1677,8 @@ sha512_ctrl_cov_bind i_sha512_ctrl_cov_bind(); sha256_ctrl_cov_bind i_sha256_ctrl_cov_bind(); hmac_ctrl_cov_bind i_hmac_ctrl_cov_bind(); ecc_top_cov_bind i_ecc_top_cov_bind(); +keyvault_cov_bind i_keyvault_cov_bind(); +pcrvault_cov_bind i_pcrvault_cov_bind(); `endif /* verilator lint_off CASEINCOMPLETE */ diff --git a/src/integration/uvmf_caliptra_top/config/compile.yml b/src/integration/uvmf_caliptra_top/config/compile.yml index a6eaa74e2..b20a2c8fd 100644 --- a/src/integration/uvmf_caliptra_top/config/compile.yml +++ b/src/integration/uvmf_caliptra_top/config/compile.yml @@ -21,6 +21,8 @@ requires: - hmac_coverage - ecc_coverage - soc_ifc_coverage + - pcrvault_cov + - keyvault_cov targets: tb: directories: diff --git a/src/keyvault/config/keyvault.vf b/src/keyvault/config/keyvault.vf index 40ef426e3..bbda10b87 100644 --- a/src/keyvault/config/keyvault.vf +++ b/src/keyvault/config/keyvault.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl diff --git a/src/keyvault/config/keyvault_cov.vf b/src/keyvault/config/keyvault_cov.vf index b5d6ed794..b3eaabf81 100644 --- a/src/keyvault/config/keyvault_cov.vf +++ b/src/keyvault/config/keyvault_cov.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/keyvault/coverage ${CALIPTRA_ROOT}/src/keyvault/coverage/keyvault_cov_if.sv ${CALIPTRA_ROOT}/src/keyvault/coverage/keyvault_cov_props.sv diff --git a/src/keyvault/config/kv_defines_pkg.vf b/src/keyvault/config/kv_defines_pkg.vf index a43072fdf..baa074186 100644 --- a/src/keyvault/config/kv_defines_pkg.vf +++ b/src/keyvault/config/kv_defines_pkg.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_defines_pkg.sv ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_macros.svh diff --git a/src/keyvault/config/kv_uvm_pkg.vf b/src/keyvault/config/kv_uvm_pkg.vf index 994d2f5a3..4dfee8f5c 100644 --- a/src/keyvault/config/kv_uvm_pkg.vf +++ b/src/keyvault/config/kv_uvm_pkg.vf @@ -1,2 +1,3 @@ + +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl ${CALIPTRA_ROOT}/src/keyvault/rtl/kv_reg_uvm.sv \ No newline at end of file diff --git a/src/keyvault/coverage/keyvault_cov_bind.sv b/src/keyvault/coverage/keyvault_cov_bind.sv index 7e2311508..0a6af3188 100644 --- a/src/keyvault/coverage/keyvault_cov_bind.sv +++ b/src/keyvault/coverage/keyvault_cov_bind.sv @@ -14,8 +14,8 @@ module keyvault_cov_bind; - //`ifdef FCOV - bind dut keyvault_cov_if i_keyvault_cov_if(.*); - bind dut keyvault_cov_props i_keyvault_cov_props(.*); - //`endif + `ifdef FCOV + bind kv keyvault_cov_if i_keyvault_cov_if(.*); + bind kv keyvault_cov_props i_keyvault_cov_props(.*); + `endif endmodule diff --git a/src/kmac/config/kmac.vf b/src/kmac/config/kmac.vf index 21bfb92e0..b0da634ae 100644 --- a/src/kmac/config/kmac.vf +++ b/src/kmac/config/kmac.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl +incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl +incdir+${CALIPTRA_ROOT}/src/kmac/rtl diff --git a/src/kmac/config/kmac_pkg.vf b/src/kmac/config/kmac_pkg.vf index acf975fa5..00f6c16cf 100644 --- a/src/kmac/config/kmac_pkg.vf +++ b/src/kmac/config/kmac_pkg.vf @@ -1,2 +1,3 @@ + +incdir+${CALIPTRA_ROOT}/src/kmac/rtl ${CALIPTRA_ROOT}/src/kmac/rtl/sha3_pkg.sv \ No newline at end of file diff --git a/src/lc_ctrl/config/lc_ctrl_pkg.vf b/src/lc_ctrl/config/lc_ctrl_pkg.vf index e41a7f442..e7120d98c 100644 --- a/src/lc_ctrl/config/lc_ctrl_pkg.vf +++ b/src/lc_ctrl/config/lc_ctrl_pkg.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl +incdir+${CALIPTRA_ROOT}/src/lc_ctrl/rtl ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv diff --git a/src/libs/config/libs.vf b/src/libs/config/libs.vf index 7c0d4c77b..90d291bb7 100644 --- a/src/libs/config/libs.vf +++ b/src/libs/config/libs.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl ${CALIPTRA_ROOT}/src/integration/rtl/config_defines.svh diff --git a/src/pcrvault/config/pcrvault.vf b/src/pcrvault/config/pcrvault.vf index 5e59b1772..673bab586 100644 --- a/src/pcrvault/config/pcrvault.vf +++ b/src/pcrvault/config/pcrvault.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/pcrvault/rtl diff --git a/src/pcrvault/config/pcrvault_cov.vf b/src/pcrvault/config/pcrvault_cov.vf index e8172adeb..4cf22e5dc 100644 --- a/src/pcrvault/config/pcrvault_cov.vf +++ b/src/pcrvault/config/pcrvault_cov.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/pcrvault/coverage ${CALIPTRA_ROOT}/src/pcrvault/coverage/pcrvault_cov_if.sv ${CALIPTRA_ROOT}/src/pcrvault/coverage/pcrvault_cov_props.sv diff --git a/src/pcrvault/config/pv_defines_pkg.vf b/src/pcrvault/config/pv_defines_pkg.vf index ab7aa0fd0..7e4f67eea 100644 --- a/src/pcrvault/config/pv_defines_pkg.vf +++ b/src/pcrvault/config/pv_defines_pkg.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/pcrvault/rtl diff --git a/src/pcrvault/config/pv_uvm_pkg.vf b/src/pcrvault/config/pv_uvm_pkg.vf index 8fb32e123..cb4b5df57 100644 --- a/src/pcrvault/config/pv_uvm_pkg.vf +++ b/src/pcrvault/config/pv_uvm_pkg.vf @@ -1,2 +1,3 @@ + +incdir+${CALIPTRA_ROOT}/src/pcrvault/rtl ${CALIPTRA_ROOT}/src/pcrvault/rtl/pv_reg_uvm.sv \ No newline at end of file diff --git a/src/pcrvault/coverage/pcrvault_cov_bind.sv b/src/pcrvault/coverage/pcrvault_cov_bind.sv index 09251cf44..c54f3fc3d 100644 --- a/src/pcrvault/coverage/pcrvault_cov_bind.sv +++ b/src/pcrvault/coverage/pcrvault_cov_bind.sv @@ -14,8 +14,8 @@ module pcrvault_cov_bind; - //`ifdef FCOV - bind dut pcrvault_cov_if i_pcrvault_cov_if(.*); - bind dut pcrvault_cov_props i_pcrvault_cov_props(.*); - //`endif + `ifdef FCOV + bind pv pcrvault_cov_if i_pcrvault_cov_if(.*); + bind pv pcrvault_cov_props i_pcrvault_cov_props(.*); + `endif endmodule diff --git a/src/riscv_core/veer_el2/config/el2_veer_pkg.vf b/src/riscv_core/veer_el2/config/el2_veer_pkg.vf index 3e3824be2..95f06cacf 100644 --- a/src/riscv_core/veer_el2/config/el2_veer_pkg.vf +++ b/src/riscv_core/veer_el2/config/el2_veer_pkg.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl +incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv diff --git a/src/riscv_core/veer_el2/config/el2_veer_wrapper.vf b/src/riscv_core/veer_el2/config/el2_veer_wrapper.vf index da326a7e7..7bcf4091e 100644 --- a/src/riscv_core/veer_el2/config/el2_veer_wrapper.vf +++ b/src/riscv_core/veer_el2/config/el2_veer_wrapper.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl +incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv diff --git a/src/riscv_core/veer_el2/config/el2_veer_wrapper_tb.vf b/src/riscv_core/veer_el2/config/el2_veer_wrapper_tb.vf index 146b42520..594ea3a70 100644 --- a/src/riscv_core/veer_el2/config/el2_veer_wrapper_tb.vf +++ b/src/riscv_core/veer_el2/config/el2_veer_wrapper_tb.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl +incdir+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl diff --git a/src/sha256/config/sha256_ctrl.vf b/src/sha256/config/sha256_ctrl.vf index 1a53cf1eb..f8413b0e9 100644 --- a/src/sha256/config/sha256_ctrl.vf +++ b/src/sha256/config/sha256_ctrl.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/sha256/rtl diff --git a/src/sha256/config/sha256_ctrl_tb.vf b/src/sha256/config/sha256_ctrl_tb.vf index 7889eaad5..9bc3eb6fd 100644 --- a/src/sha256/config/sha256_ctrl_tb.vf +++ b/src/sha256/config/sha256_ctrl_tb.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/sha256/coverage diff --git a/src/sha256/config/sha256_random_test.vf b/src/sha256/config/sha256_random_test.vf index 1d5ed66c8..0820eeec7 100644 --- a/src/sha256/config/sha256_random_test.vf +++ b/src/sha256/config/sha256_random_test.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/sha256/coverage diff --git a/src/sha512/config/sha512_ctrl.vf b/src/sha512/config/sha512_ctrl.vf index 71a30643d..0f4ae2e2c 100644 --- a/src/sha512/config/sha512_ctrl.vf +++ b/src/sha512/config/sha512_ctrl.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl diff --git a/src/sha512/config/sha512_ctrl_32bit_tb.vf b/src/sha512/config/sha512_ctrl_32bit_tb.vf index 621c83d2e..9e274b18d 100644 --- a/src/sha512/config/sha512_ctrl_32bit_tb.vf +++ b/src/sha512/config/sha512_ctrl_32bit_tb.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl diff --git a/src/sha512/uvmf_sha512/uvmf_template_output/project_benches/SHA512/tb/testbench/hdl_top.sv b/src/sha512/uvmf_sha512/uvmf_template_output/project_benches/SHA512/tb/testbench/hdl_top.sv index bf5448523..ff20cae1d 100644 --- a/src/sha512/uvmf_sha512/uvmf_template_output/project_benches/SHA512/tb/testbench/hdl_top.sv +++ b/src/sha512/uvmf_sha512/uvmf_template_output/project_benches/SHA512/tb/testbench/hdl_top.sv @@ -110,6 +110,8 @@ import uvmf_base_pkg_hdl::*; .notif_intr(), .debugUnlock_or_scan_mode_switch('0) ); + +sha512_ctrl_cov_bind i_sha512_ctrl_cov_bind(); // pragma uvmf custom dut_instantiation end initial begin // tbx vif_binding_block diff --git a/src/sha512_masked/config/sha512_masked_core.vf b/src/sha512_masked/config/sha512_masked_core.vf index e9d04af99..9816a2017 100644 --- a/src/sha512_masked/config/sha512_masked_core.vf +++ b/src/sha512_masked/config/sha512_masked_core.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl diff --git a/src/sha512_masked/config/sha512_masked_core_tb.vf b/src/sha512_masked/config/sha512_masked_core_tb.vf index b9fa2a419..10d6ce690 100644 --- a/src/sha512_masked/config/sha512_masked_core_tb.vf +++ b/src/sha512_masked/config/sha512_masked_core_tb.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/keyvault/rtl diff --git a/src/soc_ifc/config/soc_ifc_pkg.vf b/src/soc_ifc/config/soc_ifc_pkg.vf index 0ba5a33ba..c8c03c8da 100644 --- a/src/soc_ifc/config/soc_ifc_pkg.vf +++ b/src/soc_ifc/config/soc_ifc_pkg.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv diff --git a/src/soc_ifc/config/soc_ifc_tb.vf b/src/soc_ifc/config/soc_ifc_tb.vf index 55dbfb700..0f6d2c09c 100644 --- a/src/soc_ifc/config/soc_ifc_tb.vf +++ b/src/soc_ifc/config/soc_ifc_tb.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl diff --git a/src/soc_ifc/config/soc_ifc_top.vf b/src/soc_ifc/config/soc_ifc_top.vf index 4e1965ce5..2367cc6f8 100644 --- a/src/soc_ifc/config/soc_ifc_top.vf +++ b/src/soc_ifc/config/soc_ifc_top.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl diff --git a/src/soc_ifc/config/soc_ifc_uvm_pkg.vf b/src/soc_ifc/config/soc_ifc_uvm_pkg.vf index ef4ec886b..ca9cf8b7e 100644 --- a/src/soc_ifc/config/soc_ifc_uvm_pkg.vf +++ b/src/soc_ifc/config/soc_ifc_uvm_pkg.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/soc_ifc/rtl ${CALIPTRA_ROOT}/src/soc_ifc/rtl/soc_ifc_pkg.sv ${CALIPTRA_ROOT}/src/soc_ifc/rtl/mbox_csr_uvm.sv diff --git a/src/soc_ifc/uvmf_soc_ifc/config/compile.yml b/src/soc_ifc/uvmf_soc_ifc/config/compile.yml index 1f9cf8295..ebf9d8986 100644 --- a/src/soc_ifc/uvmf_soc_ifc/config/compile.yml +++ b/src/soc_ifc/uvmf_soc_ifc/config/compile.yml @@ -53,6 +53,7 @@ provides: [uvmf_soc_ifc] schema_version: 2.4.0 requires: - uvmf_soc_ifc_vip + - soc_ifc_coverage targets: tb: directories: diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/testbench/hdl_top.sv b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/testbench/hdl_top.sv index 38ef2b1da..dbc11dfbd 100644 --- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/testbench/hdl_top.sv +++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/project_benches/soc_ifc/tb/testbench/hdl_top.sv @@ -253,6 +253,9 @@ import uvmf_base_pkg_hdl::*; assign uvm_test_top_environment_qvip_apb5_slave_subenv_qvip_hdl.apb5_master_0_PSLVERRCHK = 0; assign uvm_test_top_environment_qvip_apb5_slave_subenv_qvip_hdl.apb5_master_0_PRUSERCHK = 0; assign uvm_test_top_environment_qvip_apb5_slave_subenv_qvip_hdl.apb5_master_0_PBUSERCHK = 0; + + + soc_ifc_cov_bind i_soc_ifc_cov_bind(); // pragma uvmf custom dut_instantiation end initial begin // tbx vif_binding_block diff --git a/src/spi_host/config/spi_host.vf b/src/spi_host/config/spi_host.vf index 1b0661420..6d7b740ad 100644 --- a/src/spi_host/config/spi_host.vf +++ b/src/spi_host/config/spi_host.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl diff --git a/src/spi_host/config/spi_host_tb.vf b/src/spi_host/config/spi_host_tb.vf index 687e76aca..9e426f787 100644 --- a/src/spi_host/config/spi_host_tb.vf +++ b/src/spi_host/config/spi_host_tb.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl diff --git a/src/spi_host/config/spiflash.vf b/src/spi_host/config/spiflash.vf index 6821ad3d0..d08a0f326 100644 --- a/src/spi_host/config/spiflash.vf +++ b/src/spi_host/config/spiflash.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl diff --git a/src/uart/config/uart.vf b/src/uart/config/uart.vf index 469205a79..e352155c7 100644 --- a/src/uart/config/uart.vf +++ b/src/uart/config/uart.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl diff --git a/src/uart/config/uart_tb.vf b/src/uart/config/uart_tb.vf index 4332da0e6..78eb779e6 100644 --- a/src/uart/config/uart_tb.vf +++ b/src/uart/config/uart_tb.vf @@ -1,3 +1,4 @@ + +incdir+${CALIPTRA_ROOT}/src/integration/rtl +incdir+${CALIPTRA_ROOT}/src/libs/rtl +incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl From 2c300e095607ab3a36c89dc3632fb5c112bb8880 Mon Sep 17 00:00:00 2001 From: Michael Norris Date: Fri, 29 Sep 2023 19:49:57 +0000 Subject: [PATCH 09/11] Merged PR 126835: Fixing +COVERAGE compiles that broke after coverage bind additions Addition of coverage binds to top level caliptra benches broke compilation when +COVERAGE was added. Missed this due to pipeline and manual testing not includingt he option. Related work items: #563789 --- src/keyvault/coverage/keyvault_cov_if.sv | 16 +++---- src/keyvault/coverage/keyvault_cov_props.sv | 48 ++++++++++----------- src/pcrvault/coverage/pcrvault_cov_if.sv | 8 ++-- src/pcrvault/coverage/pcrvault_cov_props.sv | 12 +++--- 4 files changed, 42 insertions(+), 42 deletions(-) diff --git a/src/keyvault/coverage/keyvault_cov_if.sv b/src/keyvault/coverage/keyvault_cov_if.sv index bf0979c4a..6d5020250 100644 --- a/src/keyvault/coverage/keyvault_cov_if.sv +++ b/src/keyvault/coverage/keyvault_cov_if.sv @@ -41,26 +41,26 @@ interface keyvault_cov_if //Assign clear and locks of each KEY_CTRL reg to corresponding bit in the intermediate bus generate for(genvar i = 0; i < KV_NUM_KEYS; i++) begin - assign key_ctrl_lock_wr[i] = dut.kv_reg_hwif_out.KEY_CTRL[i].lock_wr; - assign key_ctrl_lock_use[i] = dut.kv_reg_hwif_out.KEY_CTRL[i].lock_use; - assign key_ctrl_clear[i] = dut.kv_reg_hwif_out.KEY_CTRL[i].clear; + assign key_ctrl_lock_wr[i] = kv.kv_reg_hwif_out.KEY_CTRL[i].lock_wr; + assign key_ctrl_lock_use[i] = kv.kv_reg_hwif_out.KEY_CTRL[i].lock_use; + assign key_ctrl_clear[i] = kv.kv_reg_hwif_out.KEY_CTRL[i].clear; end endgenerate //CLEAR_SECRETS - assign clear_secrets_wr = dut.kv_reg_hwif_out.CLEAR_SECRETS.wr_debug_values; - assign clear_secrets_sel = dut.kv_reg_hwif_out.CLEAR_SECRETS.sel_debug_value; + assign clear_secrets_wr = kv.kv_reg_hwif_out.CLEAR_SECRETS.wr_debug_values; + assign clear_secrets_sel = kv.kv_reg_hwif_out.CLEAR_SECRETS.sel_debug_value; //Crypto interface write_en generate for(genvar client = 0; client < KV_NUM_WRITE; client++) begin - assign kv_write_en[client] = dut.kv_write[client].write_en; + assign kv_write_en[client] = kv.kv_write[client].write_en; end endgenerate //AHB signals - assign ahb_write = dut.kv_ahb_slv1.dv & dut.kv_ahb_slv1.write; - assign ahb_read = dut.kv_ahb_slv1.dv & ~dut.kv_ahb_slv1.write; + assign ahb_write = kv.kv_ahb_slv1.dv & kv.kv_ahb_slv1.write; + assign ahb_read = kv.kv_ahb_slv1.dv & ~kv.kv_ahb_slv1.write; covergroup keyvault_top_cov_grp @(posedge clk); option.per_instance = 1; diff --git a/src/keyvault/coverage/keyvault_cov_props.sv b/src/keyvault/coverage/keyvault_cov_props.sv index 4ee35a38d..ce8d437e9 100644 --- a/src/keyvault/coverage/keyvault_cov_props.sv +++ b/src/keyvault/coverage/keyvault_cov_props.sv @@ -25,8 +25,8 @@ module keyvault_cov_props //clear_secrets followed by warm reset in the next clk //Expectation: Keys cleared before warm reset property cover_prop_clear_secr_warm_rst; - @(posedge dut.clk) - (dut.kv_reg_hwif_out.CLEAR_SECRETS.wr_debug_values |-> ##[1:$] !dut.rst_b); + @(posedge kv.clk) + (kv.kv_reg_hwif_out.CLEAR_SECRETS.wr_debug_values |-> ##[1:$] !kv.rst_b); endproperty covprop_clear_secr_warmrst: cover property(cover_prop_clear_secr_warm_rst); @@ -38,8 +38,8 @@ module keyvault_cov_props //Expectation: Keys will be flushed since reset is not seen until next clk, locks are reset //------------------------------------------------------------------------------ property cover_prop_locks_clear_secr_warm_rst; - @(posedge dut.clk) - (dut.kv_reg_hwif_out.KEY_CTRL[i].lock_wr && dut.kv_reg_hwif_out.CLEAR_SECRETS.wr_debug_values |-> ##[1:$] !dut.rst_b); + @(posedge kv.clk) + (kv.kv_reg_hwif_out.KEY_CTRL[i].lock_wr && kv.kv_reg_hwif_out.CLEAR_SECRETS.wr_debug_values |-> ##[1:$] !kv.rst_b); endproperty covprop_lock_clear_secr_warmrst: cover property(cover_prop_locks_clear_secr_warm_rst); @@ -48,8 +48,8 @@ module keyvault_cov_props //Expectation: Keys will be flushed since reset is not seen until next clk, locks and keys are reset once cold reset happens //------------------------------------------------------------------------------ property cover_prop_locks_clear_secr_cold_rst; - @(posedge dut.clk) - (dut.kv_reg_hwif_out.KEY_CTRL[i].lock_wr && dut.kv_reg_hwif_out.CLEAR_SECRETS.wr_debug_values |-> ##[1:$] !dut.cptra_pwrgood); + @(posedge kv.clk) + (kv.kv_reg_hwif_out.KEY_CTRL[i].lock_wr && kv.kv_reg_hwif_out.CLEAR_SECRETS.wr_debug_values |-> ##[1:$] !kv.cptra_pwrgood); endproperty covprop_lock_clear_secr_coldrst: cover property(cover_prop_locks_clear_secr_cold_rst); @@ -57,20 +57,20 @@ module keyvault_cov_props //Check that locks/clear were set before issuing warm reset //------------------------------------------------------------------------------ property cover_prop_lock_wr_warmrst; - @(posedge dut.clk) - (dut.kv_reg_hwif_out.KEY_CTRL[i].lock_wr |-> ##[0:$] !dut.rst_b); + @(posedge kv.clk) + (kv.kv_reg_hwif_out.KEY_CTRL[i].lock_wr |-> ##[0:$] !kv.rst_b); endproperty covprop_lock_wr_warmrst: cover property(cover_prop_lock_wr_warmrst); property cover_prop_lock_use_warmrst; - @(posedge dut.clk) - (dut.kv_reg_hwif_out.KEY_CTRL[i].lock_use |-> ##[0:$] !dut.rst_b); + @(posedge kv.clk) + (kv.kv_reg_hwif_out.KEY_CTRL[i].lock_use |-> ##[0:$] !kv.rst_b); endproperty covprop_lock_use_warmrst: cover property(cover_prop_lock_use_warmrst); property cover_prop_clear_warmrst; - @(posedge dut.clk) - (dut.kv_reg_hwif_out.KEY_CTRL[i].clear |-> ##[0:$] !dut.rst_b); + @(posedge kv.clk) + (kv.kv_reg_hwif_out.KEY_CTRL[i].clear |-> ##[0:$] !kv.rst_b); endproperty covprop_clear_warmrst: cover property(cover_prop_clear_warmrst); @@ -78,20 +78,20 @@ module keyvault_cov_props //Check that locks/clear were set before issuing cold reset //------------------------------------------------------------------------------ property cover_prop_lock_wr_coldrst; - @(posedge dut.clk) - (dut.kv_reg_hwif_out.KEY_CTRL[i].lock_wr |-> ##[0:$] !dut.cptra_pwrgood); + @(posedge kv.clk) + (kv.kv_reg_hwif_out.KEY_CTRL[i].lock_wr |-> ##[0:$] !kv.cptra_pwrgood); endproperty covprop_lock_wr_coldrst: cover property(cover_prop_lock_wr_coldrst); property cover_prop_lock_use_coldrst; - @(posedge dut.clk) - (dut.kv_reg_hwif_out.KEY_CTRL[i].lock_use |-> ##[0:$] !dut.cptra_pwrgood); + @(posedge kv.clk) + (kv.kv_reg_hwif_out.KEY_CTRL[i].lock_use |-> ##[0:$] !kv.cptra_pwrgood); endproperty covprop_lock_use_coldrst: cover property(cover_prop_lock_use_coldrst); property cover_prop_clear_coldrst; - @(posedge dut.clk) - (dut.kv_reg_hwif_out.KEY_CTRL[i].clear |-> ##[0:$] !dut.cptra_pwrgood); + @(posedge kv.clk) + (kv.kv_reg_hwif_out.KEY_CTRL[i].clear |-> ##[0:$] !kv.cptra_pwrgood); endproperty covprop_clear_coldrst: cover property(cover_prop_clear_coldrst); @@ -99,20 +99,20 @@ module keyvault_cov_props //Check that locks/clear were set before issuing core reset //------------------------------------------------------------------------------ property cover_prop_lock_wr_corerst; - @(posedge dut.clk) - (dut.kv_reg_hwif_out.KEY_CTRL[i].lock_wr |-> ##[0:$] !dut.core_only_rst_b); + @(posedge kv.clk) + (kv.kv_reg_hwif_out.KEY_CTRL[i].lock_wr |-> ##[0:$] !kv.core_only_rst_b); endproperty covprop_lock_wr_corerst: cover property(cover_prop_lock_wr_corerst); property cover_prop_lock_use_corerst; - @(posedge dut.clk) - (dut.kv_reg_hwif_out.KEY_CTRL[i].lock_use |-> ##[0:$] !dut.core_only_rst_b); + @(posedge kv.clk) + (kv.kv_reg_hwif_out.KEY_CTRL[i].lock_use |-> ##[0:$] !kv.core_only_rst_b); endproperty covprop_lock_use_corerst: cover property(cover_prop_lock_use_corerst); property cover_prop_clear_corerst; - @(posedge dut.clk) - (dut.kv_reg_hwif_out.KEY_CTRL[i].clear |-> ##[0:$] !dut.core_only_rst_b); + @(posedge kv.clk) + (kv.kv_reg_hwif_out.KEY_CTRL[i].clear |-> ##[0:$] !kv.core_only_rst_b); endproperty covprop_clear_corerst: cover property(cover_prop_clear_corerst); end diff --git a/src/pcrvault/coverage/pcrvault_cov_if.sv b/src/pcrvault/coverage/pcrvault_cov_if.sv index c14ec311a..45ae4d94c 100644 --- a/src/pcrvault/coverage/pcrvault_cov_if.sv +++ b/src/pcrvault/coverage/pcrvault_cov_if.sv @@ -31,19 +31,19 @@ interface pcrvault_cov_if //Assign clear and locks of each PCR_CTRL reg to corresponding bit in the intermediate bus generate for(genvar i = 0; i < PV_NUM_PCR; i++) begin - assign pcr_ctrl_lock[i] = dut.pv_reg_hwif_out.PCR_CTRL[i].lock; + assign pcr_ctrl_lock[i] = pv.pv_reg_hwif_out.PCR_CTRL[i].lock; end endgenerate generate for(genvar client = 0; client < PV_NUM_WRITE; client++) begin - assign pv_write_en[client] = dut.pv_write[client].write_en; + assign pv_write_en[client] = pv.pv_write[client].write_en; end endgenerate //AHB signals - assign ahb_write = dut.pv_ahb_slv1.dv & dut.pv_ahb_slv1.write; - assign ahb_read = dut.pv_ahb_slv1.dv & ~dut.pv_ahb_slv1.write; + assign ahb_write = pv.pv_ahb_slv1.dv & pv.pv_ahb_slv1.write; + assign ahb_read = pv.pv_ahb_slv1.dv & ~pv.pv_ahb_slv1.write; covergroup pcrvault_top_cov_grp @(posedge clk); option.per_instance = 1; diff --git a/src/pcrvault/coverage/pcrvault_cov_props.sv b/src/pcrvault/coverage/pcrvault_cov_props.sv index ba63232e7..3df578a6f 100644 --- a/src/pcrvault/coverage/pcrvault_cov_props.sv +++ b/src/pcrvault/coverage/pcrvault_cov_props.sv @@ -26,24 +26,24 @@ module pcrvault_cov_props //clear followed by warm reset in the next clk //Expectation: PCRs cleared before warm reset property cover_prop_clear_warm_rst; - @(posedge dut.clk) - (dut.pv_reg_hwif_out.PCR_CTRL[i].clear |-> ##[1:$] !dut.rst_b); + @(posedge pv.clk) + (pv.pv_reg_hwif_out.PCR_CTRL[i].clear |-> ##[1:$] !pv.rst_b); endproperty covprop_clear_warmrst: cover property(cover_prop_clear_warm_rst); //locks, followed by clear, followed by warm reset in the next clk //Expectation: Unlocked PCRs cleared before warm reset, locks cleared on warm reset property cover_prop_lock_clear_warm_rst; - @(posedge dut.clk) - (dut.pv_reg_hwif_out.PCR_CTRL[i].lock |-> ##[0:$] dut.pv_reg_hwif_out.PCR_CTRL[i].clear |-> ##[1:$] !dut.rst_b); + @(posedge pv.clk) + (pv.pv_reg_hwif_out.PCR_CTRL[i].lock |-> ##[0:$] pv.pv_reg_hwif_out.PCR_CTRL[i].clear |-> ##[1:$] !pv.rst_b); endproperty covprop_lock_clear_warmrst: cover property(cover_prop_lock_clear_warm_rst); //locks, followed by clear, followed by cold reset in the next clk //Expectation: Unlocked PCRs cleared before cold reset, everything cleared on cold reset property cover_prop_lock_clear_cold_rst; - @(posedge dut.clk) - (dut.pv_reg_hwif_out.PCR_CTRL[i].lock |-> ##[0:$] dut.pv_reg_hwif_out.PCR_CTRL[i].clear |-> ##[1:$] !dut.cptra_pwrgood); + @(posedge pv.clk) + (pv.pv_reg_hwif_out.PCR_CTRL[i].lock |-> ##[0:$] pv.pv_reg_hwif_out.PCR_CTRL[i].clear |-> ##[1:$] !pv.cptra_pwrgood); endproperty covprop_lock_clear_coldrst: cover property(cover_prop_lock_clear_cold_rst); end From e90baa949024dadccd0cfd763dde86c343f08bbe Mon Sep 17 00:00:00 2001 From: Mojtaba Bisheh Niasar Date: Mon, 2 Oct 2023 22:03:33 +0000 Subject: [PATCH 10/11] Merged PR 127057: added a missing default case to hmac_drbg_interface added a missing default case to hmac_drbg_interface Related work items: #565291 --- src/ecc/rtl/ecc_hmac_drbg_interface.sv | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/ecc/rtl/ecc_hmac_drbg_interface.sv b/src/ecc/rtl/ecc_hmac_drbg_interface.sv index 4df95d7a3..aff0288f6 100644 --- a/src/ecc/rtl/ecc_hmac_drbg_interface.sv +++ b/src/ecc/rtl/ecc_hmac_drbg_interface.sv @@ -209,7 +209,6 @@ module ecc_hmac_drbg_interface#( end else if (hmac_done_edge) begin - /* verilator lint_off CASEINCOMPLETE */ unique case (state_reg) inside LFSR_ST: lfsr_seed_reg <= hmac_drbg_result[147 : 0]; LAMBDA_ST: lambda_reg <= hmac_drbg_result; @@ -217,8 +216,14 @@ module ecc_hmac_drbg_interface#( MASKING_RND_ST: masking_rnd_reg <= hmac_drbg_result; KEYGEN_ST: drbg_reg <= hmac_drbg_result; SIGN_ST: drbg_reg <= hmac_drbg_result; + default: begin + lambda_reg <= '0; + scalar_rnd_reg <= '0; + masking_rnd_reg <= '0; + drbg_reg <= '0; + lfsr_seed_reg <= LFSR_INIT_SEED; + end endcase - /* verilator lint_on CASEINCOMPLETE */ end end //reg_update From 62cf3cea5a9fe3d9f41b9bc7ad28a7562f95595d Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Mon, 2 Oct 2023 15:54:22 -0700 Subject: [PATCH 11/11] Remove MSFT internal collateral files --- coverage/config/clp_mapfile | 36 -------------------- coverage/config/uvmf_soc_ifc_caliptra_tb.yml | 13 ------- 2 files changed, 49 deletions(-) delete mode 100644 coverage/config/clp_mapfile delete mode 100644 coverage/config/uvmf_soc_ifc_caliptra_tb.yml diff --git a/coverage/config/clp_mapfile b/coverage/config/clp_mapfile deleted file mode 100644 index c2c9c1336..000000000 --- a/coverage/config/clp_mapfile +++ /dev/null @@ -1,36 +0,0 @@ -MODULE: caliptra_top -INSTANCE: -SRC: caliptra_top_tb.caliptra_top_dut -DST: hdl_top.caliptra_top_dut - -MODULE: soc_ifc_top -INSTANCE: -SRC: hdl_top.dut -DST: hdl_top.caliptra_top_dut.soc_ifc_top1 -SRC: soc_ifc_tb.dut -DST: hdl_top.caliptra_top_dut.soc_ifc_top1 - -MODULE: ecc_top -INSTANCE: -SRC: hdl_top.dut -DST: hdl_top.caliptra_top_dut.ecc_top1 - -MODULE: hmac_ctrl -INSTANCE: -SRC: hdl_top.dut -DST: hdl_top.caliptra_top_dut.hmac - -MODULE: kv -INSTANCE: -SRC: hdl_top.dut -DST: hdl_top.caliptra_top_dut.key_vault1 - -MODULE: pv -INSTANCE: -SRC: hdl_top.pv -DST: hdl_top.caliptra_top_dut.pcr_vault1 - -MODULE: sha512_ctrl -INSTANCE: -SRC: hdl_top.dut -DST: hdl_top.caliptra_top_dut.sha512 \ No newline at end of file diff --git a/coverage/config/uvmf_soc_ifc_caliptra_tb.yml b/coverage/config/uvmf_soc_ifc_caliptra_tb.yml deleted file mode 100644 index de768258e..000000000 --- a/coverage/config/uvmf_soc_ifc_caliptra_tb.yml +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (C) Microsoft Corporation. All rights reserved. - -# Repo/Bench config specific settings -# For repo-specific file, common settings like retention policy, additional merge options etc can be specified - -# -# https://dev.azure.com/ms-tsd/Base_Verification/_wiki/wikis/Base_Verification.wiki/34333/Coverage-merge-YAML -# - -variables: - BENCH_CONFIG: uvmf_soc_ifc - -template: caliptra_cov_cfg.yml