From 896ae4473af333c0f549d46fd8ca24363780414b Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Tue, 12 Sep 2023 12:30:32 -0700 Subject: [PATCH] Updated Release Notes for 1p0 --- Release_Notes.md | 116 ++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 104 insertions(+), 12 deletions(-) diff --git a/Release_Notes.md b/Release_Notes.md index f2af94086..4f15a6e40 100644 --- a/Release_Notes.md +++ b/Release_Notes.md @@ -14,13 +14,112 @@ See the License for the specific language governing permissions and
limitations under the License.*_
# **Release Notes** # -_*Last Update: 2023/08/25*_ +_*Last Update: 2023/09/11*_ -## Rev 0p8 ## +## Rev 1p0 ## -### DISCALIMER: This is NOT A BUG-FREE MODEL YET. This is a 0p8 release model. Please see testplan document in docs folder to know the status of validation. ### -#### This model is released mainly for interface, floorplan planning purposes for consumers. #### -#### Rev 0p8 release date: 03-31-2023 #### +### Rev 1p0 release date: (pending ROM release for official declaration) ### +- Caliptra IP Specification: see docs/ folder +- Caliptra Integration Specification: see docs/ folder +- Caliptra testplan: see docs/ folder +- Data Vault +- RISC-V Timers + - mtime + mtimecmp implementation + - Watchdog timer configuration by SOC; escalate interrupts to error +- Reliability, Availability, Serviceability Features + - Connectivity for cptra_error_fatal/cptra_error_non_fatal interrupts + - Mailbox protocol violation detection and Error state + - SRAM ECC error detection and reporting for ICCM, DCCM, Mailbox + - Key clearing and system reset on fatal errors +- SOC Interface + - QSPI inout changed to input+output+enable + - FUSE PAUSER config registers and enforcement +- Reset Domain Crossing (RDC) fixes + - Reset-triggered clock gating on cross-domain registers + - Reset timing changes for noncore reset assertion + - Migrate most internal logic to the noncore reset domain + - Migrate APB interface to noncore reset domain +- FIPS compliance updates + - SHA Accelerator LOCK default to Caliptra-owned + - LMS Fuse + - SOC Stepping ID field in HW Revision + - Extended pcr_nonce from 32-bit to 256-bit + - TRNG Data Clear +- RISC-V Core + - Increase ROM size to 48KiB + - Added 2:1 AHB lite mux on LSU and SB buses to allow debug access to + peripherals +- Timing Optimizations + - Remove PSEL loopback path in APB slave + - Remove unnecessary Mailbox SRAM ECC writeback path +- Validation enhancements + - SOC_IFC/Mailbox randomized regressions via UVM testbench + - SOC Interface Register validation via directed + random tests + - Coverage reporting and analysis for all interfaces, registers, FSM + - Automated GitHub action using OpenOCD for interactive JTAG debugging + - SHA Formal Verification + +### Bug Fixes ### +[CLK GATING] Fatal error should wake up clks
+[CLK GATING] JTAG accesses need to wake up clocks
+[DOE] add zeroize to clear all internal regs
+[DOE] DOE IV reg needs hwclr input
+[DOE] doe_fsm incr_dest_sel logic can be removed since FE now only takes up 12 dwords
+[DOE] doe_fsm write_offset increments to 0xC
+[DOE] Simplify kv_write dest_valid hardcoded value in doe_fsm
+[ECC] ECC input register bound check
+[ECC] ECC output register bound check
+[ECC] ECC Public key validation check
+[ECC] mismatch of final reduction in Mont. mult in the case of prime<= p_internal
+[ECC] mismatch of modular addition result in the case of p<= a+b < 2^384
+[ECC] remove FW read access to kv/privkey reg
+[ECC} error trigger when pcr_sign ctrl input is set in keygen/verifying mode
+[KV] Debug Mode and Scan Mode switch doesn't flush locked registers
+[KV] Debug mode should flush KV even if core is asleep
+[KV] Dest_valid and last_dword should check lock_use to clear along with lock_wr
+[KV] KV may still contain secrets during scan mode
+[KV] kv_reg.rdl still has 6 bits for dest_valid while we have 5 valid clients
+[KV] KV->SHA ->FW read path and KV->HMAC->FW read path should NOT exist in the design
+[KV] last dword of secret values stays in KV/crypto interface
+[KV] Suppress writes to an entry altogether when it's being cleared
+[MBOX] ECC error decode may detect error on mbox_sram when a write is in progress
+[MBOX] First resp read data is zero after handling a command with DLEN > MBOX SIZE
+[MBOX] HWCLR triggered by force-unlock has lower precedence than SW writes
+[MBOX] Mailbox data length limiting reads is calculated incorrectly
+[MBOX] Mailbox does not flag protocol error for attempted writes to DLEN
+[MBOX] mailbox returns non-zero data in an overread case
+[MBOX] New RAS feature to detect protocol violation incorrectly decodes certain reg accesses as errors
+[MBOX] SOC can read mbox_dataout with stale data
+[MBOX] Writes beyond the mailbox size overwrite the last data dword in mailbox memory
+[MBOX] Writes to (a) unaligned addresses (b) size < AHB_DATA_WIDTH may corrupt memory
+[MBOX] error_cmd_fail_sts.hwset is continuously set when mailbox protocol error occurs
+[PCR] Extend PCR Nonce from 32-bit to 256-bit to protect replay attack
+[PCR] PCR dword mismatch
+[PCR] Update the reset of the 'lock' PCR control to the core reset domain (so that a FW update reset or warm reset can also unlock the PCR)
+[PCR] zeroize doesn't take effect if is set with pcr at the same cycle
+[SHA ACCEL] SoC requester can use mailbox mode
+[SOC_IFC] Arbiter lets direct request dv through at the same time as soc ifc mailbox request causing deadlock
+[SOC_IFC] Breakpoint is unreachable
+[SOC_IFC] Fuse Registers can never be written using non-default values programmed in FUSE_VALID_PAUSER
+[SOC_IFC] Generic Input Wires toggle (any bit) should trigger notification interrupt to uC
+[SOC_IFC] INTERNAL_HW_ERROR_FATAL_MASK and INTERNAL_HW_ERROR_NON_FATAL_MASK allow writes to (and non-zero reads from) reserved fields.
+[SOC_IFC] Mailbox ECC errors detected during SHA Accel direct accesses are not detected/corrected
+[SOC_IFC] mbox_execute can be cleared by SOC at any point after acquiring lock
+[SOC_IFC] uC can't write to CPTRA_FW_ERROR regs (Github issue #64)
+[SOC_IFC] WDT may not correctly detect when uC services the timer expiration interrupt
+[WDT] CPTRA_WDT_STATUS reg should be FW writeable so it can clear the flags
+[WDT] First stage interrupt output should be "error_intr" instead of "notif_intr"
+[WDT] WDT registers need to be on ungated clk
+[AHB] AHB 2:1 Mux hangs with back to back transactions after a stall
+[RST] scan_mode should not corrupt resets
+ +## Previous Releases ## + +### Rev 0p8 ### + +#### DISCALIMER: This is NOT A BUG-FREE MODEL YET. This is a 0p8 release model. Please see testplan document in docs folder to know the status of validation. #### +##### This model is released mainly for interface, floorplan planning purposes for consumers. ##### +##### Rev 0p8 release date: 03-31-2023 ##### - Caliptra IP Specification: see docs/ folder - Caliptra Integration Specification: see docs/ folder @@ -59,13 +158,6 @@ _*Last Update: 2023/08/25*_ - UVMF for multiple DUT blocks and SOC interface - DV complete for first cut of the boot & reset flows, Fuses, SOC registers, Crypto blocks, Key vault, PCR Vault, PCR extend, PCR signing, Mailbox -## Pending for RTL 1p0: ## -- Timers, integrated-TRNG integration w/ Caliptra, Error domain logic -- Lots of bug fixes :-) -- Data Vault, TRNG REQ protocol, SHA384 acceleration, More mailbox val, PCR val, cross product flows - -## Previous Releases ## - ### Rev Pre0p8: ### #### DISCLAIMER: This is NOT A BUG-FREE MODEL. This is a pre-0p8 development model that will be sync’d every week. #### #### This model is released mainly for interface, floorplan planning purposes for consumers. ####