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Global hdlin variable hazard: hdlin_interface_port_downto true #220

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nstewart-amd opened this issue Sep 18, 2023 · 1 comment · Fixed by #240

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nstewart-amd commented Sep 18, 2023

Source: ahb_lite_bus.sv

https://spdocs.synopsys.com/dow_retrieve/qsc-t/dg/dcolh/T-2022.03/dcolh/Default.htm#manpages/synn/ELAB.htm#ELAB-123
https://solvnetplus.synopsys.com/s/article/How-Does-Elaboration-Represent-Arrays-of-Interfaces-1576165809529

Two options:

Configuring our synth environment with: hdlin_interface_port_downto true
Global impact to all RTL file read.
Not acceptable.
Change the port ordering in ahb_lite_bus.sv.
See modified RTL here. Trial in progress:
ahb_lite_bus.sv.tar.gz

Contributor Author

nstewart-amd commented Sep 19, 2023

Code change provided resolved the ELAB-123 Error.

bharatpillilli assigned Nitsirks

bharatpillilli added enhancement Approved labels

Nitsirks linked a pull request

that will close this issue

Merge dev-integrate --> main #240

Merged

Nitsirks closed this as completed

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