diff --git a/README.md b/README.md index 7070e2e35..5b5ade8f8 100644 --- a/README.md +++ b/README.md @@ -14,7 +14,7 @@ See the License for the specific language governing permissions and
limitations under the License.*_
# **Caliptra Hands-On Guide** # -_*Last Update: 2023/09/06*_ +_*Last Update: 2023/10/17*_ ## **Tools Used** ## @@ -37,6 +37,8 @@ Simulation: - `Version 2021.2.1` of AHB/APB models - UVM installation - `Version 1.1d` + - Mentor Graphics UVM-Frameworks + - `2022.3` Synthesis: - Synopsys DC @@ -121,6 +123,9 @@ VF files provide absolute filepaths (prefixed by the `CALIPTRA_ROOT` environment The "Integration" sub-component contains the top-level fileset for Caliptra. `src/integration/config/compile.yml` defines the required filesets and sub-component dependencies for this build target. All of the files/dependencies are explicitly listed in `src/integration/config/caliptra_top_tb.vf`. Users may compile the entire design using only this VF filelist.
+## **Verilog File Lists** ## +Verilog file lists are generated via VCS and included in the config directory for each unit. New files added to the design should be included in the vf list. They can be included manually or by using VCS to regenerate the vf file. File lists define the compilation sources (including all dependencies) required to build and simulate a given module or testbench, and should be used for simulation, lint, and synthesis. + ## **Scripts Description** ## `demo.rdl`:Sample RDL file
@@ -142,10 +147,12 @@ The "Integration" sub-component contains the top-level fileset for Caliptra. `sr 1. Setup tools, add to PATH (ensure riscv64-unknown-elf-gcc is also available) 2. Define all environment variables above - For the initial test run after downloading repository, `iccm_lock` is recommended for TESTNAME + - See [Regression Tests](#Regression-Tests) for information about available tests. 3. Create a run folder for build outputs (and cd to it) 4. [OPTIONAL] By default, this run flow will use the riscv64 toolchain to compile test firmware (according to TESTNAME) into program.hex, iccm.hex, dccm.hex, and mailbox.hex. As a first pass, integrators may alternatively use the pre-built hexfiles for convenience (available for `iccm_lock` test). To do this, copy `iccm_lock.hex` to the run directory and rename to `program.hex`. `dccm.hex` should also be copied to the run directory, as-is. Use `touch iccm.hex mailbox.hex` to create empty hex files, as these are unnecessary for `iccm_lock` test. 5. Invoke `${CALIPTRA_ROOT}/tools/scripts/Makefile` with target 'program.hex' to produce SRAM initialization files from the firmware found in `src/integration/test_suites/${TESTNAME}` - E.g.: `make -f ${CALIPTRA_ROOT}/tools/scripts/Makefile program.hex` + - NOTE: TESTNAME may also be overridden in the makefile command line invocation, e.g. `make -f ${CALIPTRA_ROOT}/tools/scripts/Makefile TESTNAME=iccm_lock program.hex` 6. Compile complete project using `src/integration/config/caliptra_top_tb.vf` as a compilation target in VCS. When running the `vcs` command to generate simv, users should ensure that `caliptra_top_tb` is explicitly specified as the top-level component in their command to ensure this is the sole "top" that gets simulated. 7. Simulate project with `caliptra_top_tb` as the top target @@ -153,6 +160,7 @@ The "Integration" sub-component contains the top-level fileset for Caliptra. `sr 1. Setup tools, add to PATH (ensure Verilator, GCC, and riscv64-unknown-elf-gcc are available) 2. Define all environment variables above - For the initial test run after downloading repository, `iccm_lock` is recommended for TESTNAME + - See [Regression Tests](#Regression-Tests) for information about available tests. 3. Create a run folder for build outputs - Recommended to place run folder under `${CALIPTRA_WORKSPACE}/scratch/$USER/verilator/` 4. [OPTIONAL] By default, this run flow will use the riscv64 toolchain to compile test firmware (according to TESTNAME) into program.hex, iccm.hex, dccm.hex, and mailbox.hex. As a first pass, integrators may alternatively use the pre-built hexfiles for convenience (available for `iccm_lock` test). To do this, copy `iccm_lock.hex` to the run directory and rename to `program.hex`. `dccm.hex` should also be copied to the run directory, as-is. Use `touch iccm.hex mailbox.hex` to create empty hex files, as these are unnecessary for `iccm_lock` test. @@ -178,20 +186,38 @@ The UVM Framework generation tool was used to create the baseline UVM testbench **Prerequisites**:
- QVIP 2021.2.1 for Mentor Graphics (provides the AHB/APB VIP) - UVM 1.1d installation +- Mentor Graphics UVM-Framework installation Steps:
1. Compile UVM 1.1d library -2. Compile the AHB/APB QVIP source -3. Compile the UVMF wrapper for APB/AHB in Caliptra/src/libs/uvmf -4. Compile the `verification_ip` provided for `soc_ifc` found in `Caliptra/src/soc_ifc/uvmf_soc_ifc` -5. Compile the `caliptra_top` testbench found in `Caliptra/src/integration/uvmf_caliptra_top` -6. `Caliptra/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/testbench/hdl_top.sv` is the top-level TB wrapper for the system -7. Select a test to run from the set of tests in `Caliptra/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src` -8. Provide `+UVM_TESTNAME=` argument to simulation +1. Compile the AHB/APB QVIP source +1. Compile the Mentor Graphics UVM-Frameworks base library +1. Compile the UVMF wrapper for APB/AHB in Caliptra/src/libs/uvmf +1. Compile the `verification_ip` provided for `soc_ifc` found in `Caliptra/src/soc_ifc/uvmf_soc_ifc` +1. Compile the `caliptra_top` testbench found in `Caliptra/src/integration/uvmf_caliptra_top` +1. `Caliptra/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/testbench/hdl_top.sv` is the top-level TB wrapper for the system +1. Compile the validation firmware (as described in [Regression Tests](#Regression-Tests)) that will run on Caliptra's embedded RISC-V core + - The expected output products are `program.hex`, `caliptra_fmc.hex`, `caliptra_rt.hex` and must be placed in the simulation run directory + - `make -f ${CALIPTRA_ROOT}/tools/scripts/Makefile TESTNAME=caliptra_top program.hex` + - `make -f ${CALIPTRA_ROOT}/tools/scripts/Makefile TESTNAME=caliptra_fmc caliptra_fmc.hex` + - `make -f ${CALIPTRA_ROOT}/tools/scripts/Makefile TESTNAME=caliptra_rt caliptra_rt.hex` +1. Select a test to run from the set of tests in `Caliptra/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src` +1. Provide `+UVM_TESTNAME=` argument to simulation ## **Regression Tests** ## -Only tests from the L0 Regression List should be run. +### Standalone SystemVerilog Testbench Regression ### +Only tests from the L0 Regression List should be run. +The list is defined in the file [L0_regression.yml](https://github.com/chipsalliance/caliptra-rtl/blob/main/src/integration/stimulus/L0_regression.yml) + +### UVM Regression ### +The UVM simulation environment for `caliptra_top` uses a special set of validation firmware to generate stimulus as required for the test plan. This firmware suite is found in `src/integration/test_suites` and includes: + - `caliptra_top`: A C-based program that emulates a minimal set of bringup functions similar to the function of the ROM. This C file transitions very early to either a the FMC image or Runtime image based on bringup (reset reason) conditions. + - `caliptra_fmc`: A C-based program that emulates the functionality of the First Mutable Code. In this reduced-functionality validation implementation, the FMC code is a simple intermediary that runs from ICCM and serves to boot the Runtime Firmware. + - `caliptra_rt`: A C-based program that emulates the functionality of the production Runtime code. This program receives and services interrupts, defines a minimal Non-Maskable Interrupt handler, generates FW resets as needed, processes mailbox commands (generated through the UVM validation test plan), and runs some baseline Watchdog Timer testing. + +These three programs are designed to be run within the context of a UVM simulation, and will fail to generate meaningful stimulus in the standalone `caliptra_top_tb` test. + ## **NOTES** ## * The internal registers are auto rendered at the [GitHub page](https://chipsalliance.github.io/caliptra-rtl/main/internal-regs) diff --git a/docs/Caliptra_Integration_Specification.pdf b/docs/Caliptra_Integration_Specification.pdf deleted file mode 100755 index 0cc3f9ebe..000000000 Binary files a/docs/Caliptra_Integration_Specification.pdf and /dev/null differ diff --git a/src/caliptra_prim/rtl/caliptra_prim_assert.sv b/src/caliptra_prim/rtl/caliptra_prim_assert.sv index 7a91601a9..7ab0e3bc7 100644 --- a/src/caliptra_prim/rtl/caliptra_prim_assert.sv +++ b/src/caliptra_prim/rtl/caliptra_prim_assert.sv @@ -49,8 +49,8 @@ // Static assertions for checks inside SV packages. If the conditions is not true, this will // trigger an error during elaboration. `define CALIPTRA_ASSERT_STATIC_IN_PACKAGE(__name, __prop) \ - function automatic bit assert_static_in_package_``__name(); \ - bit unused_bit [((__prop) ? 1 : -1)]; \ + function automatic logic assert_static_in_package_``__name(); \ + logic unused_bit [((__prop) ? 1 : -1)]; \ unused_bit = '{default: 1'b0}; \ return unused_bit[0]; \ endfunction diff --git a/src/csrng/rtl/csrng_reg_top.sv b/src/csrng/rtl/csrng_reg_top.sv index 70a8d0056..45086aee3 100644 --- a/src/csrng/rtl/csrng_reg_top.sv +++ b/src/csrng/rtl/csrng_reg_top.sv @@ -1947,74 +1947,74 @@ module csrng_reg_top #( // Read data return always_comb begin reg_rdata_next = '0; - unique case (1'b1) - addr_hit[0]: begin + unique case (addr_hit) + 17'h00001: begin reg_rdata_next[0] = intr_state_cs_cmd_req_done_qs; reg_rdata_next[1] = intr_state_cs_entropy_req_qs; reg_rdata_next[2] = intr_state_cs_hw_inst_exc_qs; reg_rdata_next[3] = intr_state_cs_fatal_err_qs; end - addr_hit[1]: begin + 17'h00002: begin reg_rdata_next[0] = intr_enable_cs_cmd_req_done_qs; reg_rdata_next[1] = intr_enable_cs_entropy_req_qs; reg_rdata_next[2] = intr_enable_cs_hw_inst_exc_qs; reg_rdata_next[3] = intr_enable_cs_fatal_err_qs; end - addr_hit[2]: begin + 17'h00004: begin reg_rdata_next[0] = '0; reg_rdata_next[1] = '0; reg_rdata_next[2] = '0; reg_rdata_next[3] = '0; end - addr_hit[3]: begin + 17'h00008: begin reg_rdata_next[0] = '0; reg_rdata_next[1] = '0; end - addr_hit[4]: begin + 17'h00010: begin reg_rdata_next[0] = regwen_qs; end - addr_hit[5]: begin + 17'h00020: begin reg_rdata_next[3:0] = ctrl_enable_qs; reg_rdata_next[7:4] = ctrl_sw_app_enable_qs; reg_rdata_next[11:8] = ctrl_read_int_state_qs; end - addr_hit[6]: begin + 17'h00040: begin reg_rdata_next[31:0] = '0; end - addr_hit[7]: begin + 17'h00080: begin reg_rdata_next[0] = sw_cmd_sts_cmd_rdy_qs; reg_rdata_next[1] = sw_cmd_sts_cmd_sts_qs; end - addr_hit[8]: begin + 17'h00100: begin reg_rdata_next[0] = genbits_vld_genbits_vld_qs; reg_rdata_next[1] = genbits_vld_genbits_fips_qs; end - addr_hit[9]: begin + 17'h00200: begin reg_rdata_next[31:0] = genbits_qs; end - addr_hit[10]: begin + 17'h00400: begin reg_rdata_next[3:0] = int_state_num_qs; end - addr_hit[11]: begin + 17'h00800: begin reg_rdata_next[31:0] = int_state_val_qs; end - addr_hit[12]: begin + 17'h01000: begin reg_rdata_next[15:0] = hw_exc_sts_qs; end - addr_hit[13]: begin + 17'h02000: begin reg_rdata_next[0] = recov_alert_sts_enable_field_alert_qs; reg_rdata_next[1] = recov_alert_sts_sw_app_enable_field_alert_qs; reg_rdata_next[2] = recov_alert_sts_read_int_state_field_alert_qs; @@ -2023,7 +2023,7 @@ module csrng_reg_top #( reg_rdata_next[13] = recov_alert_sts_cs_main_sm_alert_qs; end - addr_hit[14]: begin + 17'h04000: begin reg_rdata_next[0] = err_code_sfifo_cmd_err_qs; reg_rdata_next[1] = err_code_sfifo_genbits_err_qs; reg_rdata_next[2] = err_code_sfifo_cmdreq_err_qs; @@ -2052,11 +2052,11 @@ module csrng_reg_top #( reg_rdata_next[30] = err_code_fifo_state_err_qs; end - addr_hit[15]: begin + 17'h08000: begin reg_rdata_next[4:0] = err_code_test_qs; end - addr_hit[16]: begin + 17'h10000: begin reg_rdata_next[7:0] = main_sm_state_qs; end endcase diff --git a/src/entropy_src/rtl/entropy_src_reg_top.sv b/src/entropy_src/rtl/entropy_src_reg_top.sv index e443608a4..de571706a 100644 --- a/src/entropy_src/rtl/entropy_src_reg_top.sv +++ b/src/entropy_src/rtl/entropy_src_reg_top.sv @@ -3588,56 +3588,56 @@ module entropy_src_reg_top #( // Read data return always_comb begin reg_rdata_next = '0; - unique case (1'b1) - addr_hit[0]: begin + unique case (addr_hit) + 57'h000000000000001: begin reg_rdata_next[0] = intr_state_es_entropy_valid_qs; reg_rdata_next[1] = intr_state_es_health_test_failed_qs; reg_rdata_next[2] = intr_state_es_observe_fifo_ready_qs; reg_rdata_next[3] = intr_state_es_fatal_err_qs; end - addr_hit[1]: begin + 57'h000000000000002: begin reg_rdata_next[0] = intr_enable_es_entropy_valid_qs; reg_rdata_next[1] = intr_enable_es_health_test_failed_qs; reg_rdata_next[2] = intr_enable_es_observe_fifo_ready_qs; reg_rdata_next[3] = intr_enable_es_fatal_err_qs; end - addr_hit[2]: begin + 57'h000000000000004: begin reg_rdata_next[0] = '0; reg_rdata_next[1] = '0; reg_rdata_next[2] = '0; reg_rdata_next[3] = '0; end - addr_hit[3]: begin + 57'h000000000000008: begin reg_rdata_next[0] = '0; reg_rdata_next[1] = '0; end - addr_hit[4]: begin + 57'h000000000000010: begin reg_rdata_next[0] = me_regwen_qs; end - addr_hit[5]: begin + 57'h000000000000020: begin reg_rdata_next[0] = sw_regupd_qs; end - addr_hit[6]: begin + 57'h000000000000040: begin reg_rdata_next[0] = regwen_qs; end - addr_hit[7]: begin + 57'h000000000000080: begin reg_rdata_next[7:0] = rev_abi_revision_qs; reg_rdata_next[15:8] = rev_hw_revision_qs; reg_rdata_next[23:16] = rev_chip_type_qs; end - addr_hit[8]: begin + 57'h000000000000100: begin reg_rdata_next[3:0] = module_enable_qs; end - addr_hit[9]: begin + 57'h000000000000200: begin reg_rdata_next[3:0] = conf_fips_enable_qs; reg_rdata_next[7:4] = conf_entropy_data_reg_enable_qs; reg_rdata_next[15:12] = conf_threshold_scope_qs; @@ -3645,156 +3645,156 @@ module entropy_src_reg_top #( reg_rdata_next[25:24] = conf_rng_bit_sel_qs; end - addr_hit[10]: begin + 57'h000000000000400: begin reg_rdata_next[3:0] = entropy_control_es_route_qs; reg_rdata_next[7:4] = entropy_control_es_type_qs; end - addr_hit[11]: begin + 57'h000000000000800: begin reg_rdata_next[31:0] = entropy_data_qs; end - addr_hit[12]: begin + 57'h000000000001000: begin reg_rdata_next[15:0] = health_test_windows_fips_window_qs; reg_rdata_next[31:16] = health_test_windows_bypass_window_qs; end - addr_hit[13]: begin + 57'h000000000002000: begin reg_rdata_next[15:0] = repcnt_thresholds_fips_thresh_qs; reg_rdata_next[31:16] = repcnt_thresholds_bypass_thresh_qs; end - addr_hit[14]: begin + 57'h000000000004000: begin reg_rdata_next[15:0] = repcnts_thresholds_fips_thresh_qs; reg_rdata_next[31:16] = repcnts_thresholds_bypass_thresh_qs; end - addr_hit[15]: begin + 57'h000000000008000: begin reg_rdata_next[15:0] = adaptp_hi_thresholds_fips_thresh_qs; reg_rdata_next[31:16] = adaptp_hi_thresholds_bypass_thresh_qs; end - addr_hit[16]: begin + 57'h000000000010000: begin reg_rdata_next[15:0] = adaptp_lo_thresholds_fips_thresh_qs; reg_rdata_next[31:16] = adaptp_lo_thresholds_bypass_thresh_qs; end - addr_hit[17]: begin + 57'h000000000020000: begin reg_rdata_next[15:0] = bucket_thresholds_fips_thresh_qs; reg_rdata_next[31:16] = bucket_thresholds_bypass_thresh_qs; end - addr_hit[18]: begin + 57'h000000000040000: begin reg_rdata_next[15:0] = markov_hi_thresholds_fips_thresh_qs; reg_rdata_next[31:16] = markov_hi_thresholds_bypass_thresh_qs; end - addr_hit[19]: begin + 57'h000000000080000: begin reg_rdata_next[15:0] = markov_lo_thresholds_fips_thresh_qs; reg_rdata_next[31:16] = markov_lo_thresholds_bypass_thresh_qs; end - addr_hit[20]: begin + 57'h000000000100000: begin reg_rdata_next[15:0] = extht_hi_thresholds_fips_thresh_qs; reg_rdata_next[31:16] = extht_hi_thresholds_bypass_thresh_qs; end - addr_hit[21]: begin + 57'h000000000200000: begin reg_rdata_next[15:0] = extht_lo_thresholds_fips_thresh_qs; reg_rdata_next[31:16] = extht_lo_thresholds_bypass_thresh_qs; end - addr_hit[22]: begin + 57'h000000000400000: begin reg_rdata_next[15:0] = repcnt_hi_watermarks_fips_watermark_qs; reg_rdata_next[31:16] = repcnt_hi_watermarks_bypass_watermark_qs; end - addr_hit[23]: begin + 57'h000000000800000: begin reg_rdata_next[15:0] = repcnts_hi_watermarks_fips_watermark_qs; reg_rdata_next[31:16] = repcnts_hi_watermarks_bypass_watermark_qs; end - addr_hit[24]: begin + 57'h000000001000000: begin reg_rdata_next[15:0] = adaptp_hi_watermarks_fips_watermark_qs; reg_rdata_next[31:16] = adaptp_hi_watermarks_bypass_watermark_qs; end - addr_hit[25]: begin + 57'h000000002000000: begin reg_rdata_next[15:0] = adaptp_lo_watermarks_fips_watermark_qs; reg_rdata_next[31:16] = adaptp_lo_watermarks_bypass_watermark_qs; end - addr_hit[26]: begin + 57'h000000004000000: begin reg_rdata_next[15:0] = extht_hi_watermarks_fips_watermark_qs; reg_rdata_next[31:16] = extht_hi_watermarks_bypass_watermark_qs; end - addr_hit[27]: begin + 57'h000000008000000: begin reg_rdata_next[15:0] = extht_lo_watermarks_fips_watermark_qs; reg_rdata_next[31:16] = extht_lo_watermarks_bypass_watermark_qs; end - addr_hit[28]: begin + 57'h000000010000000: begin reg_rdata_next[15:0] = bucket_hi_watermarks_fips_watermark_qs; reg_rdata_next[31:16] = bucket_hi_watermarks_bypass_watermark_qs; end - addr_hit[29]: begin + 57'h000000020000000: begin reg_rdata_next[15:0] = markov_hi_watermarks_fips_watermark_qs; reg_rdata_next[31:16] = markov_hi_watermarks_bypass_watermark_qs; end - addr_hit[30]: begin + 57'h000000040000000: begin reg_rdata_next[15:0] = markov_lo_watermarks_fips_watermark_qs; reg_rdata_next[31:16] = markov_lo_watermarks_bypass_watermark_qs; end - addr_hit[31]: begin + 57'h000000080000000: begin reg_rdata_next[31:0] = repcnt_total_fails_qs; end - addr_hit[32]: begin + 57'h000000100000000: begin reg_rdata_next[31:0] = repcnts_total_fails_qs; end - addr_hit[33]: begin + 57'h000000200000000: begin reg_rdata_next[31:0] = adaptp_hi_total_fails_qs; end - addr_hit[34]: begin + 57'h000000400000000: begin reg_rdata_next[31:0] = adaptp_lo_total_fails_qs; end - addr_hit[35]: begin + 57'h000000800000000: begin reg_rdata_next[31:0] = bucket_total_fails_qs; end - addr_hit[36]: begin + 57'h000001000000000: begin reg_rdata_next[31:0] = markov_hi_total_fails_qs; end - addr_hit[37]: begin + 57'h000002000000000: begin reg_rdata_next[31:0] = markov_lo_total_fails_qs; end - addr_hit[38]: begin + 57'h000004000000000: begin reg_rdata_next[31:0] = extht_hi_total_fails_qs; end - addr_hit[39]: begin + 57'h000008000000000: begin reg_rdata_next[31:0] = extht_lo_total_fails_qs; end - addr_hit[40]: begin + 57'h000010000000000: begin reg_rdata_next[15:0] = alert_threshold_alert_threshold_qs; reg_rdata_next[31:16] = alert_threshold_alert_threshold_inv_qs; end - addr_hit[41]: begin + 57'h000020000000000: begin reg_rdata_next[15:0] = alert_summary_fail_counts_qs; end - addr_hit[42]: begin + 57'h000040000000000: begin reg_rdata_next[7:4] = alert_fail_counts_repcnt_fail_count_qs; reg_rdata_next[11:8] = alert_fail_counts_adaptp_hi_fail_count_qs; reg_rdata_next[15:12] = alert_fail_counts_adaptp_lo_fail_count_qs; @@ -3804,45 +3804,45 @@ module entropy_src_reg_top #( reg_rdata_next[31:28] = alert_fail_counts_repcnts_fail_count_qs; end - addr_hit[43]: begin + 57'h000080000000000: begin reg_rdata_next[3:0] = extht_fail_counts_extht_hi_fail_count_qs; reg_rdata_next[7:4] = extht_fail_counts_extht_lo_fail_count_qs; end - addr_hit[44]: begin + 57'h000100000000000: begin reg_rdata_next[3:0] = fw_ov_control_fw_ov_mode_qs; reg_rdata_next[7:4] = fw_ov_control_fw_ov_entropy_insert_qs; end - addr_hit[45]: begin + 57'h000200000000000: begin reg_rdata_next[3:0] = fw_ov_sha3_start_qs; end - addr_hit[46]: begin + 57'h000400000000000: begin reg_rdata_next[0] = fw_ov_wr_fifo_full_qs; end - addr_hit[47]: begin + 57'h000800000000000: begin reg_rdata_next[0] = fw_ov_rd_fifo_overflow_qs; end - addr_hit[48]: begin + 57'h001000000000000: begin reg_rdata_next[31:0] = fw_ov_rd_data_qs; end - addr_hit[49]: begin + 57'h002000000000000: begin reg_rdata_next[31:0] = '0; end - addr_hit[50]: begin + 57'h004000000000000: begin reg_rdata_next[6:0] = observe_fifo_thresh_qs; end - addr_hit[51]: begin + 57'h008000000000000: begin reg_rdata_next[6:0] = observe_fifo_depth_qs; end - addr_hit[52]: begin + 57'h010000000000000: begin reg_rdata_next[2:0] = debug_status_entropy_fifo_depth_qs; reg_rdata_next[5:3] = debug_status_sha3_fsm_qs; reg_rdata_next[6] = debug_status_sha3_block_pr_qs; @@ -3853,7 +3853,7 @@ module entropy_src_reg_top #( reg_rdata_next[17] = debug_status_main_sm_boot_done_qs; end - addr_hit[53]: begin + 57'h020000000000000: begin reg_rdata_next[0] = recov_alert_sts_fips_enable_field_alert_qs; reg_rdata_next[1] = recov_alert_sts_entropy_data_reg_en_field_alert_qs; reg_rdata_next[2] = recov_alert_sts_module_enable_field_alert_qs; @@ -3871,7 +3871,7 @@ module entropy_src_reg_top #( reg_rdata_next[16] = recov_alert_sts_es_fw_ov_disable_alert_qs; end - addr_hit[54]: begin + 57'h040000000000000: begin reg_rdata_next[0] = err_code_sfifo_esrng_err_qs; reg_rdata_next[1] = err_code_sfifo_observe_err_qs; reg_rdata_next[2] = err_code_sfifo_esfinal_err_qs; @@ -3885,11 +3885,11 @@ module entropy_src_reg_top #( reg_rdata_next[30] = err_code_fifo_state_err_qs; end - addr_hit[55]: begin + 57'h080000000000000: begin reg_rdata_next[4:0] = err_code_test_qs; end - addr_hit[56]: begin + 57'h100000000000000: begin reg_rdata_next[8:0] = main_sm_state_qs; end endcase diff --git a/src/integration/coverage/config/caliptra_top_tb_cm_hier.cfg b/src/integration/coverage/config/caliptra_top_tb_cm_hier.cfg index f0543f488..56a129afb 100644 --- a/src/integration/coverage/config/caliptra_top_tb_cm_hier.cfg +++ b/src/integration/coverage/config/caliptra_top_tb_cm_hier.cfg @@ -1,3 +1,3 @@ -begin line+tgl+fsm+cond - +tree caliptra_top_tb.caliptra_top 0 +begin line+tgl+fsm+cond+branch + +tree caliptra_top_tb.caliptra_top_dut 0 end diff --git a/src/integration/stimulus/testsuites/caliptra_top_nightly_directed_regression.yml b/src/integration/stimulus/testsuites/caliptra_top_nightly_directed_regression.yml index e726e2ba5..2105ac57d 100644 --- a/src/integration/stimulus/testsuites/caliptra_top_nightly_directed_regression.yml +++ b/src/integration/stimulus/testsuites/caliptra_top_nightly_directed_regression.yml @@ -11,3 +11,43 @@ contents: - ${CALIPTRA_ROOT}/src/integration/test_suites/fw_test_sha256/fw_test_sha256.yml - ${CALIPTRA_ROOT}/src/integration/test_suites/fw_test_sha384/fw_test_sha384.yml - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_datavault_mini/smoke_test_datavault_mini.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_veer/smoke_test_veer.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_mbox/smoke_test_mbox.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_sha512/smoke_test_sha512.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_sha256/smoke_test_sha256.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_sha_accel/smoke_test_sha_accel.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/memCpy_ROM_to_dccm/memCpy_ROM_to_dccm.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/memCpy_dccm_to_iccm/memCpy_dccm_to_iccm.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/hello_world_iccm/hello_world_iccm.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/iccm_lock/iccm_lock.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/c_intr_handler/c_intr_handler.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_ecc/smoke_test_ecc.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_hmac/smoke_test_hmac.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_kv/smoke_test_kv.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_sram_ecc/smoke_test_sram_ecc.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_ras/smoke_test_ras.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_trng/smoke_test_trng.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_qspi/smoke_test_qspi.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_uart/smoke_test_uart.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_kv_uds_reset/smoke_test_kv_uds_reset.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_kv_securitystate/smoke_test_kv_securitystate.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_kv_ecc_flow/smoke_test_kv_ecc_flow.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_kv_hmac_flow/smoke_test_kv_hmac_flow.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_kv_sha512_flow/smoke_test_kv_sha512_flow.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_kv_crypto_flow/smoke_test_kv_crypto_flow.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/pv_hash_and_sign/pv_hash_and_sign.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_pcr_signing/smoke_test_pcr_signing.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_fw_kv_backtoback_hmac/smoke_test_fw_kv_backtoback_hmac.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_ecc_errortrigger/smoke_test_ecc_errortrigger.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_pcr_zeroize/smoke_test_pcr_zeroize.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_ahb_mux/smoke_test_ahb_mux.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_doe_rand/smoke_test_doe_rand.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_doe_scan/smoke_test_doe_scan.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_zeroize_crypto/smoke_test_zeroize_crypto.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_datavault_basic/smoke_test_datavault_basic.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_datavault_reset/smoke_test_datavault_reset.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_datavault_lock/smoke_test_datavault_lock.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_wdt/smoke_test_wdt.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_cg_wdt/smoke_test_cg_wdt.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_clk_gating/smoke_test_clk_gating.yml + - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_iccm_reset/smoke_test_iccm_reset.yml diff --git a/src/integration/stimulus/testsuites/caliptra_top_nightly_random_regression.yml b/src/integration/stimulus/testsuites/caliptra_top_nightly_random_regression.yml index 70c33e93e..0a2c3c918 100644 --- a/src/integration/stimulus/testsuites/caliptra_top_nightly_random_regression.yml +++ b/src/integration/stimulus/testsuites/caliptra_top_nightly_random_regression.yml @@ -16,5 +16,5 @@ contents: path: "{template_basename}__{seed}.yml" templates: $CALIPTRA_ROOT/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_rand_test : { weight 100 } - $CALIPTRA_ROOT/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_wdt_test : { weight 100 } - $CALIPTRA_ROOT/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_wdt_independent_test : { weight 100 } + $CALIPTRA_ROOT/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_wdt_test : { weight 10 } + $CALIPTRA_ROOT/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_wdt_independent_test : { weight 10 } diff --git a/src/integration/test_suites/caliptra_rt/caliptra_rt.c b/src/integration/test_suites/caliptra_rt/caliptra_rt.c index 59adf843c..70f8e6373 100644 --- a/src/integration/test_suites/caliptra_rt/caliptra_rt.c +++ b/src/integration/test_suites/caliptra_rt/caliptra_rt.c @@ -36,6 +36,7 @@ #include #include #include "printf.h" +#include "wdt.h" /* --------------- Global symbols/typedefs --------------- */ extern uintptr_t STACK; @@ -142,7 +143,7 @@ void caliptra_rt() { lsu_write_32((uintptr_t) (CLP_SOC_IFC_REG_INTERNAL_NMI_VECTOR), (uint32_t) (nmi_handler)); // Initialize rand num generator - VPRINTF(LOW,"\nUsing random seed = %d\n\n", MY_RANDOM_SEED); + VPRINTF(LOW,"\nUsing random seed = %u\n\n", (uint32_t) MY_RANDOM_SEED); srand((uint32_t) MY_RANDOM_SEED); // Runtime flow -- set ready for RT @@ -160,17 +161,13 @@ void caliptra_rt() { while (!(lsu_read_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R) & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK)); if (lsu_read_32(CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0) == WDT_CASCADE) { //rand() % 2; //0 - independent mode, 1 - cascade mode VPRINTF(LOW, "Restarting WDT in cascade mode\n"); - //Enable timer1 to start cascade mode - lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_EN, SOC_IFC_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_MASK); - //Set timer1 period to a small random value, so core can see timer1 timing out - lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0, wdt_rand_t1_val); - lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1, 0x00000000); - //Restart timer1 - lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL, SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART_MASK); - - while (!(lsu_read_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R) & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK)); - //Clear timer1 intr - lsu_write_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R, SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK); + // //Enable timer1 to start cascade mode + configure_wdt_cascade(wdt_rand_t1_val, 0x00000000, 0xffffffff, 0xffffffff); + service_t1_intr(); + + //Disable timers before next testing + lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_EN, 0); + lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_EN, 0); //Program timer1 and 2 periods to <= 0x100 to test NMI generation. First check if there is any pending timer1 interrupt. In a corner case scenario, timer1 can timeout a second time (if the period is small enough) //before its timeout value is changed in prep for NMI testing. In that case, the subsequent timer1 interrupt will not be serviced resulting in a hang @@ -180,50 +177,42 @@ void caliptra_rt() { if (lsu_read_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R) & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK) lsu_write_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R, SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK); - //WDT cascade mode with t2 timeout - lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_EN, !SOC_IFC_REG_CPTRA_WDT_TIMER2_EN_TIMER2_EN_MASK); - lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0, wdt_rand_t1_val); - lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1, 0x00000000); - lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0, wdt_rand_t2_val); - lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1, 0x00000000); - lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL, SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART_MASK); - // lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL, SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART_MASK); - + // //WDT cascade mode with t2 timeout + configure_wdt_cascade(wdt_rand_t1_val, 0x00000000, wdt_rand_t2_val, 0x00000000); //Don't service interrupts so it can timeout and cause NMI } else if (lsu_read_32(CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0) == WDT_INDEPENDENT){ - VPRINTF(LOW, "Restarting WDT in independent mode\n"); - lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_EN, SOC_IFC_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_MASK); - lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0, wdt_rand_t1_val); - lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1, 0x00000000); - - lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_EN, SOC_IFC_REG_CPTRA_WDT_TIMER2_EN_TIMER2_EN_MASK); - lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0, wdt_rand_t2_val); - lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1, 0x00000000); - - lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL, SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART_MASK); - lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL, SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART_MASK); + + //------------------------------------------- + //Test independent mode - both timers enabled + //------------------------------------------- + configure_wdt_independent(BOTH_TIMERS_EN, wdt_rand_t1_val, 0x00000000, wdt_rand_t2_val, 0x00000000); while (!(lsu_read_32(CLP_SOC_IFC_REG_CPTRA_WDT_STATUS) & SOC_IFC_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_MASK)); //Reset timer1 period to avoid hangs in test - lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0, 0xffffffff); - lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1, 0xffffffff); + set_default_t1_period(); - while (!(lsu_read_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R) & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK)); - //Clear timer1 intr - lsu_write_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R, SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK); + service_t1_intr(); cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK; //Reset timer2 period to avoid hangs in test while (!(lsu_read_32(CLP_SOC_IFC_REG_CPTRA_WDT_STATUS) & SOC_IFC_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_MASK)); - lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0, 0xffffffff); - lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1, 0xffffffff); + set_default_t2_period(); - while (!(lsu_read_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R) & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK)); - //Clear timer2 intr - lsu_write_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R, SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK); + service_t2_intr(); cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK; + //------------------------------------------- + //Test independent mode - only timer2 enabled + //------------------------------------------- + configure_wdt_independent(T1_DIS_T2_EN, wdt_rand_t1_val, 0x00000000, wdt_rand_t2_val, 0x00000000); + + //Reset timer2 period to avoid hangs in test + while (!(lsu_read_32(CLP_SOC_IFC_REG_CPTRA_WDT_STATUS) & SOC_IFC_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_MASK)); + set_default_t2_period(); + + service_t2_intr(); + cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK; } #endif // Initialization @@ -347,9 +336,34 @@ void caliptra_rt() { SEND_STDOUT_CTRL(0x1); while(1); } + // This oftens occurs alongside the cmd_fail bit in error injection tests... + if (cptra_intr_rcv.soc_ifc_error & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) { + CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) + VPRINTF(LOW, "Clearing FW soc_ifc_error intr bit (inv dev) after servicing\n"); + } } continue; } + // Clear any uncorrectable ECC error interrupts that may have held over from the previous operation + // This can happen after the command flow is transferred back to SOC + // if the ECC error occurred at address 0, since ending the flow triggers + // rst_mbox_rdptr and a final read from 0. This might be missed by the above + // soc_ifc_error handler. + // There might also be vestigial cmd_fail/inv_dev failures held over from a previous + // invalid reg_axs sequence... clear those too + if (cptra_intr_rcv.soc_ifc_error & (SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK | + SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK | + SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK )) { + CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK & + ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK & + ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK) + } + // Any other errors that are flagged at this point are unexpected and should cause a test failure + if (cptra_intr_rcv.soc_ifc_error) { + VPRINTF(ERROR, "Unexpected err intr 0x%x\n", cptra_intr_rcv.soc_ifc_error); + SEND_STDOUT_CTRL(0x1); + while(1); + } //read the mbox command op = soc_ifc_read_mbox_cmd(); if (op.cmd & MBOX_CMD_FIELD_FW_MASK) { @@ -425,8 +439,15 @@ void caliptra_rt() { lsu_write_32((uintptr_t) (CLP_MBOX_CSR_MBOX_DLEN), temp); // Write response data - for (loop_iter = 0; loop_iter #include #include "printf.h" +#include "riscv_hw_if.h" +#include "wdt.h" volatile char* stdout = (char *)STDOUT; volatile uint32_t intr_count = 0; @@ -83,21 +85,21 @@ void main() { VPRINTF(LOW, "Cascaded mode\n"); //Enable WDT timer1 *wdt_timer1_en = SOC_IFC_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_MASK; - *wdt_timer1_period_0 = 0x00000040; - *wdt_timer1_period_1 = 0x00000000; + set_t1_period(0x00000040, 0x00000000); + VPRINTF(LOW, "Stall until timer1 times out\n"); + while (!(lsu_read_32(SOC_IFC_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_MASK))); + VPRINTF(LOW, "WDT T1 timed out as expected\n"); *wdt_timer1_ctrl = SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART_MASK; - //Set timer1 period to something else to avoid immediate time out - *wdt_timer1_period_0 = 0x0000FFFF; - *wdt_timer1_period_1 = 0x00000000; + //Set timer1 period to default to avoid immediate time out + set_default_t1_period(); - VPRINTF(LOW, "Independent mode\n"); + VPRINTF(LOW, "Independent mode - both timers enabled\n"); //Enable WDT timer1 *wdt_timer2_en = SOC_IFC_REG_CPTRA_WDT_TIMER2_EN_TIMER2_EN_MASK; - *wdt_timer2_period_0 = 0x00000040; - *wdt_timer2_period_1 = 0x00000000; + set_t2_period(0x00000040, 0x00000000); VPRINTF(LOW, "Stall until timer2 times out\n"); //Release forced timer periods from tb so test can set them @@ -108,21 +110,31 @@ void main() { *wdt_timer1_ctrl = 0x1; //restart counter so timer1 can start counting rst_count++; //Increment count so when NMI is processed we advance in the test - *wdt_timer1_period_0 = 0x00000040; - *wdt_timer1_period_1 = 0x00000000; + set_t1_period(0x00000040, 0x00000000); - VPRINTF(LOW, "Stall until timer1 times out"); - VPRINTF(LOW, "Stall until timer2 times out"); + VPRINTF(LOW, "Stall until timer1 times out\n"); + VPRINTF(LOW, "Stall until timer2 times out\n"); } else if(rst_count == 1) { //Issue warm reset after NMI as per spec + VPRINTF(LOW, "Issuing reset in response to NMI (t2 timeout)\n"); rst_count++; SEND_STDOUT_CTRL(0xf6); } else { + VPRINTF(LOW, "Independent mode - timer2 enabled, timer1 disabled\n"); + *wdt_timer2_en = SOC_IFC_REG_CPTRA_WDT_TIMER2_EN_TIMER2_EN_MASK; + set_t2_period(0x00000040, 0x00000000); + + VPRINTF(LOW, "Stall until timer2 times out\n"); + while (!(lsu_read_32(SOC_IFC_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_MASK))); + VPRINTF(LOW, "WDT T2 timed out as expected\n") + //Release forced timer periods from tb so test can set them + // SEND_STDOUT_CTRL(0xf1); + //Write 1 to clear HW fatal error register if ((*hw_error_fatal && SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_NMI_PIN_MASK) == 1) { *hw_error_fatal = SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_NMI_PIN_MASK; diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_cold_rst_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_cold_rst_sequence.svh index 90d0a06a9..7e32d9da8 100644 --- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_cold_rst_sequence.svh +++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_cold_rst_sequence.svh @@ -252,6 +252,16 @@ class kv_wr_rd_cold_rst_sequence #( join active_phase.reset; + configuration.kv_rst_agent_config.wait_for_num_clocks(1000); + configuration.kv_hmac_write_agent_config.wait_for_num_clocks(1000); + configuration.kv_sha512_write_agent_config.wait_for_num_clocks(1000); + configuration.kv_ecc_write_agent_config.wait_for_num_clocks(1000); + configuration.kv_doe_write_agent_config.wait_for_num_clocks(1000); + configuration.kv_hmac_key_read_agent_config.wait_for_num_clocks(1000); + configuration.kv_hmac_block_read_agent_config.wait_for_num_clocks(1000); + configuration.kv_sha512_block_read_agent_config.wait_for_num_clocks(1000); + configuration.kv_ecc_privkey_read_agent_config.wait_for_num_clocks(1000); + configuration.kv_ecc_seed_read_agent_config.wait_for_num_clocks(1000); endtask endclass \ No newline at end of file diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_lock_clear_rst_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_lock_clear_rst_sequence.svh index 48cfbaf03..114d7a2c0 100644 --- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_lock_clear_rst_sequence.svh +++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_lock_clear_rst_sequence.svh @@ -204,7 +204,7 @@ class kv_wr_rd_debug_lock_clear_rst_sequence #( endcase kv_warm_rst_seq.start(configuration.kv_rst_agent_config.sequencer); - fork + // fork // begin // //Write to all entries // for (write_entry = 0; write_entry < KV_NUM_KEYS; write_entry++) begin @@ -215,7 +215,7 @@ class kv_wr_rd_debug_lock_clear_rst_sequence #( // end // end // end - begin + // begin //Read all entries for (read_entry = 0; read_entry < KV_NUM_KEYS; read_entry++) begin for (read_offset = 0; read_offset < KV_NUM_DWORDS; read_offset++) begin @@ -224,7 +224,7 @@ class kv_wr_rd_debug_lock_clear_rst_sequence #( sha512_block_read_seq.start(configuration.kv_sha512_block_read_agent_config.sequencer); end end - end - join + // end + // join endtask endclass \ No newline at end of file diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_lock_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_lock_sequence.svh index 12ce1eab2..00e97ce95 100644 --- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_lock_sequence.svh +++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_lock_sequence.svh @@ -157,7 +157,7 @@ class kv_wr_rd_debug_lock_sequence #( endcase - fork + // fork // begin // //Write to all entries // for (write_entry = 0; write_entry < KV_NUM_KEYS; write_entry++) begin @@ -168,7 +168,7 @@ class kv_wr_rd_debug_lock_sequence #( // end // end // end - begin + // begin //Read all entries for (read_entry = 0; read_entry < KV_NUM_KEYS; read_entry++) begin for (read_offset = 0; read_offset < KV_NUM_DWORDS; read_offset++) begin @@ -177,7 +177,7 @@ class kv_wr_rd_debug_lock_sequence #( sha512_block_read_seq.start(configuration.kv_sha512_block_read_agent_config.sequencer); end end - end - join + // end + // join endtask endclass \ No newline at end of file diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_sequence.svh index dcadcfcf1..1e7bb375a 100644 --- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_sequence.svh +++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_debug_sequence.svh @@ -167,5 +167,15 @@ class kv_wr_rd_debug_sequence #( end end join + configuration.kv_rst_agent_config.wait_for_num_clocks(1000); + configuration.kv_hmac_write_agent_config.wait_for_num_clocks(1000); + configuration.kv_sha512_write_agent_config.wait_for_num_clocks(1000); + configuration.kv_ecc_write_agent_config.wait_for_num_clocks(1000); + configuration.kv_doe_write_agent_config.wait_for_num_clocks(1000); + configuration.kv_hmac_key_read_agent_config.wait_for_num_clocks(1000); + configuration.kv_hmac_block_read_agent_config.wait_for_num_clocks(1000); + configuration.kv_sha512_block_read_agent_config.wait_for_num_clocks(1000); + configuration.kv_ecc_privkey_read_agent_config.wait_for_num_clocks(1000); + configuration.kv_ecc_seed_read_agent_config.wait_for_num_clocks(1000); endtask endclass \ No newline at end of file diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_rst_sequence.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_rst_sequence.svh index 9bf46403f..173f61e47 100644 --- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_rst_sequence.svh +++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/environment_packages/kv_env_pkg/src/kv_wr_rd_rst_sequence.svh @@ -192,6 +192,17 @@ class kv_wr_rd_rst_sequence #( join active_phase.reset; + configuration.kv_rst_agent_config.wait_for_num_clocks(1000); + configuration.kv_hmac_write_agent_config.wait_for_num_clocks(1000); + configuration.kv_sha512_write_agent_config.wait_for_num_clocks(1000); + configuration.kv_ecc_write_agent_config.wait_for_num_clocks(1000); + configuration.kv_doe_write_agent_config.wait_for_num_clocks(1000); + configuration.kv_hmac_key_read_agent_config.wait_for_num_clocks(1000); + configuration.kv_hmac_block_read_agent_config.wait_for_num_clocks(1000); + configuration.kv_sha512_block_read_agent_config.wait_for_num_clocks(1000); + configuration.kv_ecc_privkey_read_agent_config.wait_for_num_clocks(1000); + configuration.kv_ecc_seed_read_agent_config.wait_for_num_clocks(1000); + endtask endclass \ No newline at end of file diff --git a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_read_pkg/src/kv_read_transaction_coverage.svh b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_read_pkg/src/kv_read_transaction_coverage.svh index 83a9258f0..1e05201f3 100644 --- a/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_read_pkg/src/kv_read_transaction_coverage.svh +++ b/src/keyvault/uvmf_kv/uvmf_template_output/verification_ip/interface_packages/kv_read_pkg/src/kv_read_transaction_coverage.svh @@ -30,7 +30,7 @@ // // -covergroup rd_data(input logic rd_data_bit); +covergroup rd_data with function sample(input logic rd_data_bit); option.per_instance = 1; value: coverpoint rd_data_bit; transition: coverpoint rd_data_bit { @@ -55,7 +55,7 @@ class kv_read_transaction_coverage #( T coverage_trans; // pragma uvmf custom class_item_additional begin - rd_data rd_data_bus[KV_DATA_W]; + rd_data rd_data_bus[KV_DATA_W-1:0]; // pragma uvmf custom class_item_additional end // **************************************************************************** @@ -83,6 +83,7 @@ class kv_read_transaction_coverage #( function new(string name="", uvm_component parent=null); super.new(name,parent); kv_read_transaction_cg=new; + foreach(coverage_trans.read_data[i]) rd_data_bus[i] = new; //`uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that transaction variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") endfunction @@ -92,6 +93,7 @@ class kv_read_transaction_coverage #( // function void build_phase(uvm_phase phase); kv_read_transaction_cg.set_inst_name($sformatf("kv_read_transaction_cg_%s",get_full_name())); + foreach(coverage_trans.read_data[i]) rd_data_bus[i].set_inst_name($sformatf("rd_data_bus[%0d]_%s",i,get_full_name())); endfunction // **************************************************************************** @@ -104,11 +106,8 @@ class kv_read_transaction_coverage #( `uvm_info("COV","Received transaction",UVM_HIGH); coverage_trans = t; - foreach(rd_data_bus[i]) rd_data_bus[i] = new(coverage_trans.read_data[i]); - foreach(rd_data_bus[i]) rd_data_bus[i].set_inst_name($sformatf("rd_data_bus[%0d]_%s",i,get_full_name())); - kv_read_transaction_cg.sample(); - foreach(rd_data_bus[i]) rd_data_bus[i].sample(); + foreach(rd_data_bus[i]) rd_data_bus[i].sample(coverage_trans.read_data[i]); endfunction endclass diff --git a/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv b/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv index d8850eaf4..42823c762 100644 --- a/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv +++ b/src/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv @@ -268,7 +268,7 @@ package lc_ctrl_reg_pkg; parameter logic [31:0] LC_CTRL_MANUF_STATE_7_RESVAL = 32'h 0; // Register index - typedef enum int { + typedef enum logic [31:0] { LC_CTRL_ALERT_TEST, LC_CTRL_STATUS, LC_CTRL_CLAIM_TRANSITION_IF, diff --git a/src/soc_ifc/rtl/mbox.sv b/src/soc_ifc/rtl/mbox.sv index 2413f6954..a70ea6890 100644 --- a/src/soc_ifc/rtl/mbox.sv +++ b/src/soc_ifc/rtl/mbox.sv @@ -269,14 +269,13 @@ always_comb begin : mbox_fsm_combo end if (arc_FORCE_MBOX_UNLOCK) begin mbox_fsm_ns = MBOX_IDLE; - rst_mbox_wrptr = 1; - rst_mbox_rdptr = 1; mbox_protocol_error_nxt = '{default: 0}; end end MBOX_RDY_FOR_DLEN: begin if (arc_MBOX_RDY_FOR_DLEN_MBOX_RDY_FOR_DATA) begin mbox_fsm_ns = MBOX_RDY_FOR_DATA; + rst_mbox_wrptr = 1; end else if (arc_MBOX_RDY_FOR_DLEN_MBOX_ERROR) begin mbox_fsm_ns = MBOX_ERROR; @@ -284,8 +283,6 @@ always_comb begin : mbox_fsm_combo end if (arc_FORCE_MBOX_UNLOCK) begin mbox_fsm_ns = MBOX_IDLE; - rst_mbox_wrptr = 1; - rst_mbox_rdptr = 1; mbox_protocol_error_nxt = '{default: 0}; end end @@ -312,8 +309,6 @@ always_comb begin : mbox_fsm_combo mbox_fsm_ns = MBOX_IDLE; inc_wrptr = 0; inc_rdptr = 0; - rst_mbox_wrptr = 1; - rst_mbox_rdptr = 1; mbox_protocol_error_nxt = '{default: 0}; end end @@ -326,8 +321,6 @@ always_comb begin : mbox_fsm_combo inc_wrptr = hwif_out.mbox_datain.datain.swmod & ~req_data.soc_req; if (arc_MBOX_EXECUTE_UC_MBOX_IDLE) begin mbox_fsm_ns = MBOX_IDLE; - rst_mbox_wrptr = 1; - rst_mbox_rdptr = 1; end else if (arc_MBOX_EXECUTE_UC_MBOX_EXECUTE_SOC) begin mbox_fsm_ns = MBOX_EXECUTE_SOC; @@ -342,8 +335,6 @@ always_comb begin : mbox_fsm_combo mbox_fsm_ns = MBOX_IDLE; inc_wrptr = 0; inc_rdptr = 0; - rst_mbox_wrptr = 1; - rst_mbox_rdptr = 1; mbox_protocol_error_nxt = '{default: 0}; end end @@ -356,8 +347,6 @@ always_comb begin : mbox_fsm_combo inc_rdptr = (dmi_inc_rdptr | (hwif_out.mbox_dataout.dataout.swacc & req_data.soc_req & valid_receiver)); if (arc_MBOX_EXECUTE_SOC_MBOX_IDLE) begin mbox_fsm_ns = MBOX_IDLE; - rst_mbox_wrptr = 1; - rst_mbox_rdptr = 1; end else if (arc_MBOX_EXECUTE_SOC_MBOX_EXECUTE_UC) begin mbox_fsm_ns = MBOX_EXECUTE_UC; @@ -372,8 +361,6 @@ always_comb begin : mbox_fsm_combo mbox_fsm_ns = MBOX_IDLE; inc_wrptr = 0; inc_rdptr = 0; - rst_mbox_wrptr = 1; - rst_mbox_rdptr = 1; mbox_protocol_error_nxt = '{default: 0}; end end @@ -381,8 +368,6 @@ always_comb begin : mbox_fsm_combo mbox_protocol_error_nxt = '{default: 0}; if (arc_FORCE_MBOX_UNLOCK) begin mbox_fsm_ns = MBOX_IDLE; - rst_mbox_wrptr = 1; - rst_mbox_rdptr = 1; mbox_protocol_error_nxt = '{default: 0}; end end @@ -415,6 +400,7 @@ always_ff @(posedge clk or negedge rst_b) begin mbox_wr_full <= '0; mbox_rdptr <= '0; mbox_rd_full <= '0; + mbox_rd_valid_f <= '0; mbox_protocol_sram_rd_f <= '0; dlen_in_dws <= '0; mbox_protocol_error <= '0; diff --git a/src/soc_ifc/rtl/soc_ifc_top.sv b/src/soc_ifc/rtl/soc_ifc_top.sv index 618c2eea5..02ac2942d 100644 --- a/src/soc_ifc/rtl/soc_ifc_top.sv +++ b/src/soc_ifc/rtl/soc_ifc_top.sv @@ -376,13 +376,15 @@ soc_ifc_arb #( .sha_error(sha_error), //FUNC reg inf .soc_ifc_reg_req_dv(soc_ifc_reg_req_dv), - .soc_ifc_reg_req_hold(1'b0), + .soc_ifc_reg_req_hold(soc_ifc_reg_req_hold), .soc_ifc_reg_req_data(soc_ifc_reg_req_data), .soc_ifc_reg_rdata(soc_ifc_reg_rdata), .soc_ifc_reg_error(soc_ifc_reg_error) ); +always_comb soc_ifc_reg_req_hold = 1'b0; + //Functional Registers and Fuses //This module contains the functional registers maintained by the Caliptra Mailbox diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_status_status.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_status_status.svh index 0e27ee264..e5e19fe41 100644 --- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_status_status.svh +++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_status_status.svh @@ -32,7 +32,15 @@ class soc_ifc_reg_delay_job_mbox_csr_mbox_status_status extends soc_ifc_reg_dela return; end end - if (rm.mbox_lock.lock.get_mirrored_value()) begin + if (rm.mbox_fn_state_sigs.mbox_error) begin + // NOTE: This is due to a logic bug in mbox.sv. Regular state transitions + // take priority over error state transitions, so if an arc_..._ERROR state + // goes high at the same time as that state's normal arc_ signal, + // RTL won't go to the ERROR state as predicted. + // Flag this as an error here, that will cause regression failures until fixed. + `uvm_error("SOC_IFC_REG_DELAY_JOB", $sformatf("While running [%s] (scheduled due to access against mbox_status on map [%p]), functional state value detected as: %p. Skipping delay job state transitions. This is a known RTL bug in mbox.sv", this.get_type_name(), map.get_name(), rm.mbox_fn_state_sigs)) + end + else if (rm.mbox_lock.lock.get_mirrored_value()) begin rm.mbox_status.mbox_fsm_ps.predict(state_nxt, .kind(UVM_PREDICT_READ), .path(UVM_PREDICT), .map(map)); if (state_nxt == MBOX_EXECUTE_SOC) begin rm.mbox_fn_state_sigs = '{soc_done_stage: 1'b1, default: 1'b0}; diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_delay_job_intr_block_rf_ext.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_delay_job_intr_block_rf_ext.svh index bc8f55aaf..c5b982007 100644 --- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_delay_job_intr_block_rf_ext.svh +++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_delay_job_intr_block_rf_ext.svh @@ -36,6 +36,10 @@ class soc_ifc_reg_delay_job_intr_block_rf_ext extends soc_ifc_reg_delay_job; // Wait for all predictor callbacks to run for every intr bit accessed // during the current clock cycle, so mirrors are up to date uvm_wait_for_nba_region(); + // There might be delay_jobs running additional bit updates + // at this point, so wait again + // FIXME -- find a better way to capture field updates at each clock edge + uvm_wait_for_nba_region(); // Snapshot of current value, since next cycle may see value changes again val_sts_reg = sts_reg.get_mirrored_value(); val_en_reg = en_reg .get_mirrored_value(); @@ -47,7 +51,7 @@ class soc_ifc_reg_delay_job_intr_block_rf_ext extends soc_ifc_reg_delay_job; virtual task do_job(); `uvm_info("SOC_IFC_REG_DELAY_JOB", $sformatf("Running delayed job for %s", req_fld.get_full_name()), UVM_MEDIUM) - if (!/*val_sts_glb*/sts_glb.get_mirrored_value() && |(val_sts_reg/*sts_reg.get_mirrored_value()*/ & val_en_reg/*en_reg.get_mirrored_value()*/) /*&& val_en_glb / * en_glb.get_mirrored_value()*/) begin + if (!sts_glb.get_mirrored_value() && |(val_sts_reg & val_en_reg)) begin sts_glb.predict(1'b1); `uvm_info("SOC_IFC_REG_DELAY_JOB", $sformatf("post_predict called through map [%p] on %s results in interrupt status bit being set to 0x%0x. Values: en_reg(latched) [0x%0x(0x%0x)] sts_reg [0x%0x(0x%0x)] en_glb [0x%0x(0x%0x)] sts_glb [0x%0x(0x%0x)]", @@ -58,7 +62,7 @@ class soc_ifc_reg_delay_job_intr_block_rf_ext extends soc_ifc_reg_delay_job; sts_glb.get_mirrored_value(), val_sts_glb), UVM_MEDIUM) end - else if (/*val_sts_glb*/sts_glb.get_mirrored_value() && !(|(val_sts_reg/*sts_reg.get_mirrored_value()*/ & val_en_reg/*en_reg.get_mirrored_value()*/) /*&& val_en_glb / * en_glb.get_mirrored_value()*/)) begin + else if (sts_glb.get_mirrored_value() && !(|(val_sts_reg & val_en_reg))) begin sts_glb.predict(1'b0); `uvm_info("SOC_IFC_REG_DELAY_JOB", $sformatf("post_predict called through map [%p] on %s results in interrupt status bit being cleared to 0x%0x. Values: en_reg(latched) [0x%0x(0x%0x)] sts_reg [0x%0x(0x%0x)] en_glb [0x%0x(0x%0x)] sts_glb [0x%0x(0x%0x)]", diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_model_top_pkg.sv b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_model_top_pkg.sv index ed868206a..34e7253b4 100644 --- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_model_top_pkg.sv +++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_model_top_pkg.sv @@ -386,6 +386,13 @@ package soc_ifc_reg_model_top_pkg; uvm_event mbox_lock_clr_miss; uvm_event mbox_datain_to_dataout_predict; + // This semaphore is a necessary workaround for a known bug in the UVM + // library uvm_reg class, as described here: + // https://forums.accellera.org/topic/7037-register-write-clobbers-simultaneous-access-in-multi-threaded-testbench/ + // Essentially, the uvm_reg native atomic fails to correctly arbitrate + // between multiple contending accessors in separate threads. + semaphore mbox_datain_sem; + // This tracks expected functionality of the mailbox in a way that is // agnostic to the internal state machine implementation and strictly // observes the mailbox specification. This is what a more rigorous @@ -403,6 +410,7 @@ package soc_ifc_reg_model_top_pkg; mbox_fn_state_sigs = '{mbox_idle: 1'b1, default: 1'b0}; mbox_lock_clr_miss = new("mbox_lock_clr_miss"); mbox_datain_to_dataout_predict = new("mbox_datain_to_dataout_predict"); + mbox_datain_sem = new(1); endfunction : new // FIXME Manually maintaining a list here of registers that are configured @@ -459,6 +467,9 @@ package soc_ifc_reg_model_top_pkg; mbox_resp_q.delete(); mbox_lock_clr_miss.reset(); mbox_datain_to_dataout_predict.reset(); + // In case any active sequences claimed the semaphore but didn't relinquish it. + void'(mbox_datain_sem.try_get()); + mbox_datain_sem.put(); // Mailbox State Changes // TODO what to do for FW update? diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_handler_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_handler_sequence.svh index 608f241e2..87fad7657 100644 --- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_handler_sequence.svh +++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_handler_sequence.svh @@ -219,7 +219,7 @@ task soc_ifc_env_cptra_mbox_handler_sequence::handler_setup(); report_reg_sts(reg_sts, "notif_internal_intr_r"); // Clear errors if (err_rsp_count) begin - `uvm_warning("CPTRA_MBOX_HANDLER", "Did not expect to receive any new cptra_status err interrupt transactions at sequence entry!") + `uvm_info("CPTRA_MBOX_HANDLER", "Received new cptra_status err interrupt transactions at sequence entry! Is this run in a multi-agent context?", UVM_LOW) err_rsp_count = 0; end reg_model.soc_ifc_reg_rm.intr_block_rf_ext.error_internal_intr_r.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this); diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_interference_handler_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_interference_handler_sequence.svh index 755c60628..76a06bec8 100644 --- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_interference_handler_sequence.svh +++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_interference_handler_sequence.svh @@ -33,7 +33,7 @@ class soc_ifc_env_cptra_mbox_interference_handler_sequence extends soc_ifc_env_c extern virtual task mbox_wait_for_command(output op_sts_e op_sts); extern virtual task mbox_wait_and_force_unlock(); - extern virtual task burst_random_reg_accesses(uvm_event stop); + extern virtual task burst_random_reg_accesses(uvm_event stop, ref process this_proc); rand uvm_reg_data_t data; rand uvm_reg_addr_t mem_offset; @@ -120,29 +120,39 @@ endtask task soc_ifc_env_cptra_mbox_interference_handler_sequence::mbox_wait_and_force_unlock(); uvm_reg_data_t data; mbox_fsm_state_e state; - uvm_event force_unlock_delay_complete = new("force_unlock_delay_complete"); + process rand_reg_axs_proc; + uvm_event halt_rand_reg_accesses = new("halt_rand_reg_accesses"); // Start the unlock proc prior to burst accesses so that the parent // sequence knows to wait for AHB traffic to complete before ending the // sequence unlock_proc_active = 1'b1; + `uvm_info("CPTRA_MBOX_HANDLER", $sformatf("Starting mbox_wait_and_force_unlock with inject_force_unlock [%d] force_unlock_delay_cycles [%0d]", inject_force_unlock, force_unlock_delay_cycles), UVM_MEDIUM) // Wait... // If force unlock is disabled, this task will only exit upon detecting // an ERROR that requires servicing, whereupon force_unlock will still // be set to recover. In either case, only an event resulting in force // unlock causes this routine to break - force_unlock_delay_complete.reset(); + halt_rand_reg_accesses.reset(); fork begin + wait(rand_reg_axs_proc != null); if (inject_force_unlock) begin configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(force_unlock_delay_cycles); + halt_rand_reg_accesses.trigger(); + while(rand_reg_axs_proc.status() != process::WAITING) + configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(1); end else begin `uvm_info("CPTRA_MBOX_HANDLER", "Not injecting force unlock - burst random reg accesses until any err interrupt is observed", UVM_HIGH) forever begin if (err_rsp_count > 0 && cptra_status_agent_rsp_seq.rsp.soc_ifc_err_intr_pending) begin `uvm_info("CPTRA_MBOX_HANDLER", "Received soc_ifc_err_intr, clearing and (if needed) proceeding to mbox_unlock", UVM_MEDIUM) + // Pause rand reg accesses while servicing interrupt + halt_rand_reg_accesses.trigger(); + while(rand_reg_axs_proc.status() != process::WAITING) + configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(1); // Read and clear any error interrupts reg_model.soc_ifc_reg_rm.intr_block_rf_ext.error_internal_intr_r.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this); report_reg_sts(reg_sts, "error_internal_intr_r"); @@ -152,6 +162,7 @@ task soc_ifc_env_cptra_mbox_interference_handler_sequence::mbox_wait_and_force_u err_rsp_count = 0; // Next, check if we need to proceed to mbox_unlock step if (!data[reg_model.soc_ifc_reg_rm.intr_block_rf_ext.error_internal_intr_r.error_cmd_fail_sts.get_lsb_pos()]) begin + halt_rand_reg_accesses.reset(); continue; end reg_model.mbox_csr_rm.mbox_status.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this); @@ -168,9 +179,9 @@ task soc_ifc_env_cptra_mbox_interference_handler_sequence::mbox_wait_and_force_u end end end - force_unlock_delay_complete.trigger(); + rand_reg_axs_proc.kill(); end - burst_random_reg_accesses(force_unlock_delay_complete); + burst_random_reg_accesses(halt_rand_reg_accesses, rand_reg_axs_proc); join // After waiting the requisite number of cycles, check mbox_status. @@ -211,7 +222,7 @@ endtask // intermixed with random delays, until the input event // is triggered. //========================================== -task soc_ifc_env_cptra_mbox_interference_handler_sequence::burst_random_reg_accesses(uvm_event stop); +task soc_ifc_env_cptra_mbox_interference_handler_sequence::burst_random_reg_accesses(uvm_event stop, ref process this_proc); int unsigned burst_length; int unsigned delay_cycles; @@ -225,6 +236,7 @@ task soc_ifc_env_cptra_mbox_interference_handler_sequence::burst_random_reg_acce uvm_reg_data_t rand_data; uvm_status_e rand_sts; + this_proc = process::self(); reg_model.soc_ifc_AHB_map.get_registers(regs, UVM_HIER); // Registers we won't randomly access due to side-effects @@ -249,6 +261,7 @@ task soc_ifc_env_cptra_mbox_interference_handler_sequence::burst_random_reg_acce delay_cycles inside {[1:500]};}) `uvm_error("CPTRA_MBOX_HANDLER", "Failed to randomize burst_length and delay_cycles") else begin + `uvm_info("CPTRA_MBOX_HANDLER", $sformatf("Beginning random AHB burst with delay_cycles [%d] burst_length [%d]", delay_cycles, burst_length), UVM_HIGH) for (ii=0; ii 0; ii--) begin configuration.soc_ifc_ctrl_agent_config.wait_for_num_clocks(1); - if (stop.is_on()) return; + if (stop.is_on()) stop.wait_off(); end end endtask diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_dlen_overflow_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_dlen_overflow_sequence.svh index 9f06602ab..f30a64077 100644 --- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_dlen_overflow_sequence.svh +++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_dlen_overflow_sequence.svh @@ -63,11 +63,15 @@ task soc_ifc_env_mbox_dlen_overflow_sequence::mbox_push_datain(); if (!std::randomize(data)) `uvm_error("MBOX_SEQ", "Failed to randomize data") end `uvm_info("MBOX_SEQ", $sformatf("[Iteration: %0d] Sending datain: 0x%x", ii/4, data), UVM_DEBUG) + reg_model.mbox_csr_rm.mbox_datain_sem.get(); reg_model.mbox_csr_rm.mbox_datain.write(reg_sts, uvm_reg_data_t'(data), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(PAUSER_PROB_DATAIN))); + reg_model.mbox_csr_rm.mbox_datain_sem.put(); report_reg_sts(reg_sts, "mbox_datain"); if (!pauser_used_is_valid() && retry_failed_reg_axs) begin `uvm_info("MBOX_SEQ", "Re-do datain write with valid PAUSER", UVM_HIGH) + reg_model.mbox_csr_rm.mbox_datain_sem.get(); reg_model.mbox_csr_rm.mbox_datain.write(reg_sts, uvm_reg_data_t'(data), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(FORCE_VALID_PAUSER))); + reg_model.mbox_csr_rm.mbox_datain_sem.put(); report_reg_sts(reg_sts, "mbox_datain"); end end diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_dlen_underflow_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_dlen_underflow_sequence.svh index 1777a7d57..70c1aed9e 100644 --- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_dlen_underflow_sequence.svh +++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_dlen_underflow_sequence.svh @@ -61,11 +61,15 @@ task soc_ifc_env_mbox_dlen_underflow_sequence::mbox_push_datain(); if (!std::randomize(data)) `uvm_error("MBOX_SEQ", "Failed to randomize data") end `uvm_info("MBOX_SEQ", $sformatf("[Iteration: %0d] Sending datain: 0x%x", ii/4, data), UVM_DEBUG) + reg_model.mbox_csr_rm.mbox_datain_sem.get(); reg_model.mbox_csr_rm.mbox_datain.write(reg_sts, uvm_reg_data_t'(data), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(PAUSER_PROB_DATAIN))); + reg_model.mbox_csr_rm.mbox_datain_sem.put(); report_reg_sts(reg_sts, "mbox_datain"); if (!pauser_used_is_valid() && retry_failed_reg_axs) begin `uvm_info("MBOX_SEQ", "Re-do datain write with valid PAUSER", UVM_HIGH) + reg_model.mbox_csr_rm.mbox_datain_sem.get(); reg_model.mbox_csr_rm.mbox_datain.write(reg_sts, uvm_reg_data_t'(data), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(FORCE_VALID_PAUSER))); + reg_model.mbox_csr_rm.mbox_datain_sem.put(); report_reg_sts(reg_sts, "mbox_datain"); end end diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_max_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_max_sequence.svh index a57976374..f53828d64 100644 --- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_max_sequence.svh +++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_max_sequence.svh @@ -52,12 +52,16 @@ task soc_ifc_env_mbox_max_sequence::mbox_push_datain(); if (!std::randomize(data)) `uvm_error("MBOX_SEQ", "Failed to randomize data") `uvm_info("MBOX_SEQ", $sformatf("[Iteration: %0d] Sending datain: 0x%x", ii/4, data), UVM_DEBUG) + reg_model.mbox_csr_rm.mbox_datain_sem.get(); reg_model.mbox_csr_rm.mbox_datain.write(reg_sts, uvm_reg_data_t'(data), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(PAUSER_PROB_DATAIN))); + reg_model.mbox_csr_rm.mbox_datain_sem.put(); report_reg_sts(reg_sts, "mbox_datain"); if (!pauser_used_is_valid() && retry_failed_reg_axs) begin `uvm_info("MBOX_SEQ", "Re-do datain write with valid PAUSER", UVM_HIGH) + reg_model.mbox_csr_rm.mbox_datain_sem.get(); reg_model.mbox_csr_rm.mbox_datain.write(reg_sts, uvm_reg_data_t'(data), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(FORCE_VALID_PAUSER))); + reg_model.mbox_csr_rm.mbox_datain_sem.put(); report_reg_sts(reg_sts, "mbox_datain"); end end -endtask \ No newline at end of file +endtask diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_min_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_min_sequence.svh index 1cb78434c..3f74c7fe3 100644 --- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_min_sequence.svh +++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_min_sequence.svh @@ -51,12 +51,16 @@ task soc_ifc_env_mbox_min_sequence::mbox_push_datain(); if (!std::randomize(data)) `uvm_error("MBOX_SEQ", "Failed to randomize data") `uvm_info("MBOX_SEQ", $sformatf("[Iteration: %0d] Sending datain: 0x%x", ii/4, data), UVM_DEBUG) + reg_model.mbox_csr_rm.mbox_datain_sem.get(); reg_model.mbox_csr_rm.mbox_datain.write(reg_sts, uvm_reg_data_t'(data), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(PAUSER_PROB_DATAIN))); + reg_model.mbox_csr_rm.mbox_datain_sem.put(); report_reg_sts(reg_sts, "mbox_datain"); if (!pauser_used_is_valid() && retry_failed_reg_axs) begin `uvm_info("MBOX_SEQ", "Re-do datain write with valid PAUSER", UVM_HIGH) + reg_model.mbox_csr_rm.mbox_datain_sem.get(); reg_model.mbox_csr_rm.mbox_datain.write(reg_sts, uvm_reg_data_t'(data), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(FORCE_VALID_PAUSER))); + reg_model.mbox_csr_rm.mbox_datain_sem.put(); report_reg_sts(reg_sts, "mbox_datain"); end end -endtask \ No newline at end of file +endtask diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_real_fw_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_real_fw_sequence.svh index 3b8134b3f..45d4bd280 100644 --- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_real_fw_sequence.svh +++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_real_fw_sequence.svh @@ -77,7 +77,9 @@ task soc_ifc_env_mbox_real_fw_sequence::mbox_push_datain(); for (ii=0; ii < firmware_end_dw; ii++) begin data = uvm_reg_data_t'({fw_img[ii][3],fw_img[ii][2],fw_img[ii][1],fw_img[ii][0]}); `uvm_info("MBOX_SEQ", $sformatf("[Iteration: %0d] Sending datain: 0x%x", ii, data), UVM_DEBUG) + reg_model.mbox_csr_rm.mbox_datain_sem.get(); reg_model.mbox_csr_rm.mbox_datain.write(reg_sts, uvm_reg_data_t'(data), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(PAUSER_PROB_DATAIN))); + reg_model.mbox_csr_rm.mbox_datain_sem.put(); report_reg_sts(reg_sts, "mbox_datain"); end endtask diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_rom_fw_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_rom_fw_sequence.svh index 5e265b325..d269ac052 100644 --- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_rom_fw_sequence.svh +++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_rom_fw_sequence.svh @@ -67,7 +67,9 @@ task soc_ifc_env_mbox_rom_fw_sequence::mbox_push_datain(); `uvm_info("MBOX_SEQ", $sformatf("[Iteration: %0d] Sending datain: 0x%x", ii, data), UVM_LOW) else `uvm_info("MBOX_SEQ", $sformatf("[Iteration: %0d] Sending datain: 0x%x", ii, data), UVM_DEBUG) + reg_model.mbox_csr_rm.mbox_datain_sem.get(); reg_model.mbox_csr_rm.mbox_datain.write(reg_sts, uvm_reg_data_t'(data), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(PAUSER_PROB_DATAIN))); + reg_model.mbox_csr_rm.mbox_datain_sem.put(); report_reg_sts(reg_sts, "mbox_datain"); end endtask diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sequence_base.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sequence_base.svh index 166e40bc7..2e7d04680 100644 --- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sequence_base.svh +++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sequence_base.svh @@ -439,12 +439,16 @@ task soc_ifc_env_mbox_sequence_base::mbox_push_datain(); if (!std::randomize(data)) `uvm_error("MBOX_SEQ", "Failed to randomize data") end `uvm_info("MBOX_SEQ", $sformatf("[Iteration: %0d] Sending datain: 0x%x", ii/4, data), UVM_DEBUG) + reg_model.mbox_csr_rm.mbox_datain_sem.get(); reg_model.mbox_csr_rm.mbox_datain.write(reg_sts, uvm_reg_data_t'(data), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(PAUSER_PROB_DATAIN))); + reg_model.mbox_csr_rm.mbox_datain_sem.put(); report_reg_sts(reg_sts, "mbox_datain"); if (!pauser_used_is_valid() && retry_failed_reg_axs) begin if (rand_delay_en) do_rand_delay(1, data_delay); `uvm_info("MBOX_SEQ", "Re-do datain write with valid PAUSER", UVM_HIGH) + reg_model.mbox_csr_rm.mbox_datain_sem.get(); reg_model.mbox_csr_rm.mbox_datain.write(reg_sts, uvm_reg_data_t'(data), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(FORCE_VALID_PAUSER))); + reg_model.mbox_csr_rm.mbox_datain_sem.put(); report_reg_sts(reg_sts, "mbox_datain"); end if (rand_delay_en) do_rand_delay(1, data_delay); diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sha_accel_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sha_accel_sequence.svh index aa6f609cf..724ab6d49 100644 --- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sha_accel_sequence.svh +++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sha_accel_sequence.svh @@ -167,7 +167,9 @@ task soc_ifc_env_mbox_sha_accel_sequence::mbox_push_datain(); //sha_block_start_dw = this.start_addr >> 2; //write the start address into the first dword + reg_model.mbox_csr_rm.mbox_datain_sem.get(); reg_model.mbox_csr_rm.mbox_datain.write(reg_sts, uvm_reg_data_t'(this.start_addr), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(PAUSER_PROB_DATAIN))); + reg_model.mbox_csr_rm.mbox_datain_sem.put(); report_reg_sts(reg_sts, "mbox_datain"); //pad the data until start address @@ -183,7 +185,9 @@ task soc_ifc_env_mbox_sha_accel_sequence::mbox_push_datain(); for (ii=most_sig_dword; ii >= 0 ; ii--) begin data = sha_block_data[ii]; `uvm_info("SHA_ACCEL_SEQ", $sformatf("[Iteration: %0d] Sending datain: 0x%x", ii, data), UVM_DEBUG) + reg_model.mbox_csr_rm.mbox_datain_sem.get(); reg_model.mbox_csr_rm.mbox_datain.write(reg_sts, uvm_reg_data_t'(data), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(PAUSER_PROB_DATAIN))); + reg_model.mbox_csr_rm.mbox_datain_sem.put(); report_reg_sts(reg_sts, "mbox_datain"); end end diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_uc_reg_access_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_uc_reg_access_sequence.svh index 6b46cd035..49b827b0c 100644 --- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_uc_reg_access_sequence.svh +++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_uc_reg_access_sequence.svh @@ -109,7 +109,9 @@ task soc_ifc_env_mbox_uc_reg_access_sequence::mbox_push_datain(); uvm_reg_data_t data; for (int i = 0; i < num_reg; i++) begin data = uvm_reg_data_t'(reg_addr[i]); + reg_model.mbox_csr_rm.mbox_datain_sem.get(); reg_model.mbox_csr_rm.mbox_datain.write(reg_sts, uvm_reg_data_t'(data), UVM_FRONTDOOR, reg_model.soc_ifc_APB_map, this, .extension(get_rand_user(PAUSER_PROB_DATAIN))); + reg_model.mbox_csr_rm.mbox_datain_sem.put(); report_reg_sts(reg_sts, "mbox_datain"); end diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_predictor.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_predictor.svh index 7a9a43cd0..543a5e7e6 100644 --- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_predictor.svh +++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_predictor.svh @@ -1954,6 +1954,10 @@ class soc_ifc_predictor #( next_step = '{dlen_wr: 1'b1, default: 1'b0}; else if (p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.soc_receive_stage) next_step = '{resp_dlen_wr: 1'b1, default: 1'b0}; + else begin + next_step = '{null_action: 1'b1, default: 1'b0}; + `uvm_info("PRED_APB", $sformatf("Logging unexpected step %p; access to %s while in state %p", next_step, axs_reg.get_name(), p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs), UVM_LOW) + end `uvm_info("PRED_APB", $sformatf("Logged mailbox step [%p]", next_step), UVM_HIGH) end else if (apb_txn.read_or_write == APB3_TRANS_READ) begin @@ -2609,7 +2613,7 @@ task soc_ifc_predictor::poll_and_run_delay_jobs(); int idx[$]; time end_time; running_dly_jobs.push_back(process::self()); // This tracks all the delay_jobs that are pending so they can be clobbered on rst - `uvm_info("PRED_DLY", $sformatf("Doing delay of %0d cycles before running delay job with signature: %s", job.get_delay_cycles(), job.get_name()), UVM_HIGH/*UVM_FULL*/) + `uvm_info("PRED_DLY", $sformatf("Doing delay of %0d cycles before running delay job with signature: %s", job.get_delay_cycles(), job.get_type_name()), UVM_HIGH/*UVM_FULL*/) end_time = $time + 10*job.get_delay_cycles(); job_end_count[end_time] += 1; // delay cycles reported as 0's based value, since 1-cycle delay diff --git a/tools/scripts/Makefile b/tools/scripts/Makefile index 6a7efb724..3a629eb77 100755 --- a/tools/scripts/Makefile +++ b/tools/scripts/Makefile @@ -56,7 +56,8 @@ COMP_LIB_NAMES := aes \ sha256 \ sha512 \ soc_ifc \ - clk_gate + clk_gate \ + wdt COMP_LIBS := $(foreach name, $(COMP_LIB_NAMES), $(CALIPTRA_ROOT)/src/integration/test_suites/libs/$(name)) HEADER_FILES := $(INCLUDES_DIR)/caliptra_defines.h \ $(INCLUDES_DIR)/defines.h \