From a2b2f525687ee336f4d504f30353ab3b4aba4b71 Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Fri, 5 Jan 2024 18:22:06 -0800 Subject: [PATCH 01/12] Add table to describe integrator/vendor module overrides --- docs/CaliptraIntegrationSpecification.md | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/docs/CaliptraIntegrationSpecification.md b/docs/CaliptraIntegrationSpecification.md index 3c77bd611..da371638d 100644 --- a/docs/CaliptraIntegrationSpecification.md +++ b/docs/CaliptraIntegrationSpecification.md @@ -653,6 +653,22 @@ The following table describes SoC integration requirements. | ecc_montgomerymultiplier | Netlist for always_ff block does not contain flip flop | 274, 326 |Output width is smaller than internal signals, synthesis optimizes away the extra internal flops with no loads| | Multiple modules | Signed to unsigned conversion occurs | || +## Integrator RTL replacement requirements + +The following files implement functionality that may be process specific, and should be replaced by integrators using components from their fabrication vendor library. + +*Table 19: Caliptra integrator custom RTL file list* + +| Module | Description | +| :---------------------------------------- | :----------------------------------------------------------------------------------------- | +| [caliptra_icg](src/libs/rtl/caliptra_icg.sv) | Replace with technology specific clock gater. | +| [beh_lib](src/riscv_core/veer_el2/rtl/lib/beh_lib.sv) | Replace with technology specific clock gater. | +| [config_defines](src/integration/rtl/config_defines.svh) | Enable Caliptra internal TRNG (if applicable) | +| [caliptra_prim_flop_2sync](src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv) | Replace with technology specific sync cell. | +| [dmi_jtag_to_core_sync](src/riscv_core/veer_el2/rtl/dmi/dmi_jtag_to_core_sync.v) | Replace with technology specific sync cell. | +| [caliptra_2ff_sync](src/libs/rtl/caliptra_2ff_sync.sv) | Replace with technology specific sync cell. | + + # CDC analysis and constraints Clock Domain Crossing (CDC) analysis is performed on the Caliptra core IP. The following are the results and recommended constraints for Caliptra integrators using standard CDC analysis EDA tools. @@ -707,7 +723,7 @@ The area is expressed in units of square microns. The target foundry technology node is an industry standard, moderately advanced technology node as of 2023 September. -*Table 19: Netlist synthesis data* +*Table 20: Netlist synthesis data* | **IP Name** | **Date** | **Path Group** | **Target Freq** | **QoR WNS** | **QoR Achieveable Freq** | | :--------- | :--------- | :--------- | :--------- | :--------- | :--------- | @@ -870,7 +886,7 @@ Fatal: The 'default' or 'others' must be last case in a case statement The following terminology is used in this document. -*Table 20: Terminology* +*Table 21: Terminology* | Abbreviation | Description | From e5607887e07b6c9883f67f1bb3bde7984124cee8 Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Fri, 5 Jan 2024 18:38:11 -0800 Subject: [PATCH 02/12] relative path fix --- docs/CaliptraIntegrationSpecification.md | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/docs/CaliptraIntegrationSpecification.md b/docs/CaliptraIntegrationSpecification.md index da371638d..4a1d53038 100644 --- a/docs/CaliptraIntegrationSpecification.md +++ b/docs/CaliptraIntegrationSpecification.md @@ -655,18 +655,18 @@ The following table describes SoC integration requirements. ## Integrator RTL replacement requirements -The following files implement functionality that may be process specific, and should be replaced by integrators using components from their fabrication vendor library. +The following files implement functionality that may be process specific, and should be replaced by integrators using components from the cell library of their fabrication vendor. *Table 19: Caliptra integrator custom RTL file list* | Module | Description | | :---------------------------------------- | :----------------------------------------------------------------------------------------- | -| [caliptra_icg](src/libs/rtl/caliptra_icg.sv) | Replace with technology specific clock gater. | -| [beh_lib](src/riscv_core/veer_el2/rtl/lib/beh_lib.sv) | Replace with technology specific clock gater. | -| [config_defines](src/integration/rtl/config_defines.svh) | Enable Caliptra internal TRNG (if applicable) | -| [caliptra_prim_flop_2sync](src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv) | Replace with technology specific sync cell. | -| [dmi_jtag_to_core_sync](src/riscv_core/veer_el2/rtl/dmi/dmi_jtag_to_core_sync.v) | Replace with technology specific sync cell. | -| [caliptra_2ff_sync](src/libs/rtl/caliptra_2ff_sync.sv) | Replace with technology specific sync cell. | +| [caliptra_icg](../src/libs/rtl/caliptra_icg.sv) | Replace with technology specific clock gater. | +| [beh_lib](../src/riscv_core/veer_el2/rtl/lib/beh_lib.sv) | Replace with technology specific clock gater. | +| [config_defines](../src/integration/rtl/config_defines.svh) | Enable Caliptra internal TRNG (if applicable) | +| [caliptra_prim_flop_2sync](../src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv) | Replace with technology specific sync cell. | +| [dmi_jtag_to_core_sync](../src/riscv_core/veer_el2/rtl/dmi/dmi_jtag_to_core_sync.v) | Replace with technology specific sync cell. | +| [caliptra_2ff_sync](../src/libs/rtl/caliptra_2ff_sync.sv) | Replace with technology specific sync cell. | # CDC analysis and constraints From d663bb21637cc0c99c4b87215aafa5e933a3c552 Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Fri, 5 Jan 2024 19:07:15 -0800 Subject: [PATCH 03/12] Add soc_ifc_pkg as file to modify --- docs/CaliptraIntegrationSpecification.md | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/docs/CaliptraIntegrationSpecification.md b/docs/CaliptraIntegrationSpecification.md index 4a1d53038..e4010a9a9 100644 --- a/docs/CaliptraIntegrationSpecification.md +++ b/docs/CaliptraIntegrationSpecification.md @@ -659,14 +659,15 @@ The following files implement functionality that may be process specific, and sh *Table 19: Caliptra integrator custom RTL file list* -| Module | Description | -| :---------------------------------------- | :----------------------------------------------------------------------------------------- | -| [caliptra_icg](../src/libs/rtl/caliptra_icg.sv) | Replace with technology specific clock gater. | -| [beh_lib](../src/riscv_core/veer_el2/rtl/lib/beh_lib.sv) | Replace with technology specific clock gater. | -| [config_defines](../src/integration/rtl/config_defines.svh) | Enable Caliptra internal TRNG (if applicable) | -| [caliptra_prim_flop_2sync](../src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv) | Replace with technology specific sync cell. | -| [dmi_jtag_to_core_sync](../src/riscv_core/veer_el2/rtl/dmi/dmi_jtag_to_core_sync.v) | Replace with technology specific sync cell. | -| [caliptra_2ff_sync](../src/libs/rtl/caliptra_2ff_sync.sv) | Replace with technology specific sync cell. | +| Module | Description | +| :------------------------------------------------------------------------------------- | :--------------------------------------------------------------------- | +| [caliptra_icg.sv](../src/libs/rtl/caliptra_icg.sv) | Replace with technology specific clock gater. | +| [beh_lib.sv](../src/riscv_core/veer_el2/rtl/lib/beh_lib.sv) | Replace rvclkhdr/rvoclkhdr with technology specific clock gater. | +| [config_defines.svh](../src/integration/rtl/config_defines.svh) | Enable Caliptra internal TRNG (if applicable) | +| [caliptra_prim_flop_2sync.sv](../src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv) | Replace with technology specific sync cell. | +| [dmi_jtag_to_core_sync.v](../src/riscv_core/veer_el2/rtl/dmi/dmi_jtag_to_core_sync.v) | Replace with technology specific sync cell. | +| [caliptra_2ff_sync.sv](../src/libs/rtl/caliptra_2ff_sync.sv) | Replace with technology specific sync cell. | +| [soc_ifc_pkg.sv](../src/soc_ifc/rtl/soc_ifc_pkg.sv) | Define PAUSER default behavior and (if applicable) override values. See [Integration Parameters](#integration-parameters) | # CDC analysis and constraints From a2a4ca19836e85508bcbbb8371c02c8874b7807d Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Fri, 5 Jan 2024 19:17:17 -0800 Subject: [PATCH 04/12] Clarification on procedure for overriding native clock gate module --- docs/CaliptraIntegrationSpecification.md | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/docs/CaliptraIntegrationSpecification.md b/docs/CaliptraIntegrationSpecification.md index e4010a9a9..ce1f3f6ef 100644 --- a/docs/CaliptraIntegrationSpecification.md +++ b/docs/CaliptraIntegrationSpecification.md @@ -65,6 +65,8 @@ The following table describes integration parameters. | CALIPTRA_INTERNAL_TRNG | config_defines.svh | Defining this enables the internal TRNG source. | | CALIPTRA_INTERNAL_UART | config_defines.svh | Defining this enables the internal UART. | | CALIPTRA_INTERNAL_QSPI | config_defines.svh | Defining this enables the internal QSPI. | +| USER_ICG | config_defines.svh | If added by an integrator, provides the name of the custom clock gating module that will be used in [clk_gate.sv](../src/libs/rtl/clk_gate.sv). This substitution is only performed if integrators also define TECH_SPECIFIC_ICG | +| TECH_SPECIFIC_ICG | config_defines.svh | Defining this causes the custom, integrator-defined clock gate module (indicated by the macro USER_ICG) to be used in place of the native Caliptra clock gate module | ## Interface @@ -661,13 +663,16 @@ The following files implement functionality that may be process specific, and sh | Module | Description | | :------------------------------------------------------------------------------------- | :--------------------------------------------------------------------- | -| [caliptra_icg.sv](../src/libs/rtl/caliptra_icg.sv) | Replace with technology specific clock gater. | +| [config_defines.svh](../src/integration/rtl/config_defines.svh) | Enable Caliptra internal TRNG (if applicable)
+ Declare name of custom clock gate module by defining USER_ICG
+ Enable custom clock gate by defining TECH_SPECIFIC_ICG | +| [soc_ifc_pkg.sv](../src/soc_ifc/rtl/soc_ifc_pkg.sv) | Define PAUSER default behavior and (if applicable) override values. See [Integration Parameters](#integration-parameters) | +| [caliptra_icg.sv](../src/libs/rtl/caliptra_icg.sv) | Replace with technology specific clock gater.
+ Modifying this file is not necessary if integrators override the clock gate module that is used by setting TECH_SPECIFIC_ICG | | [beh_lib.sv](../src/riscv_core/veer_el2/rtl/lib/beh_lib.sv) | Replace rvclkhdr/rvoclkhdr with technology specific clock gater. | -| [config_defines.svh](../src/integration/rtl/config_defines.svh) | Enable Caliptra internal TRNG (if applicable) | | [caliptra_prim_flop_2sync.sv](../src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv) | Replace with technology specific sync cell. | -| [dmi_jtag_to_core_sync.v](../src/riscv_core/veer_el2/rtl/dmi/dmi_jtag_to_core_sync.v) | Replace with technology specific sync cell. | | [caliptra_2ff_sync.sv](../src/libs/rtl/caliptra_2ff_sync.sv) | Replace with technology specific sync cell. | -| [soc_ifc_pkg.sv](../src/soc_ifc/rtl/soc_ifc_pkg.sv) | Define PAUSER default behavior and (if applicable) override values. See [Integration Parameters](#integration-parameters) | +| [dmi_jtag_to_core_sync.v](../src/riscv_core/veer_el2/rtl/dmi/dmi_jtag_to_core_sync.v) | Replace with technology specific sync cell. | # CDC analysis and constraints From e30969039555340396a454780c695073198d2b3a Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Fri, 5 Jan 2024 19:19:28 -0800 Subject: [PATCH 05/12] Punctuation --- docs/CaliptraIntegrationSpecification.md | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/docs/CaliptraIntegrationSpecification.md b/docs/CaliptraIntegrationSpecification.md index ce1f3f6ef..bdaa904cc 100644 --- a/docs/CaliptraIntegrationSpecification.md +++ b/docs/CaliptraIntegrationSpecification.md @@ -65,8 +65,8 @@ The following table describes integration parameters. | CALIPTRA_INTERNAL_TRNG | config_defines.svh | Defining this enables the internal TRNG source. | | CALIPTRA_INTERNAL_UART | config_defines.svh | Defining this enables the internal UART. | | CALIPTRA_INTERNAL_QSPI | config_defines.svh | Defining this enables the internal QSPI. | -| USER_ICG | config_defines.svh | If added by an integrator, provides the name of the custom clock gating module that will be used in [clk_gate.sv](../src/libs/rtl/clk_gate.sv). This substitution is only performed if integrators also define TECH_SPECIFIC_ICG | -| TECH_SPECIFIC_ICG | config_defines.svh | Defining this causes the custom, integrator-defined clock gate module (indicated by the macro USER_ICG) to be used in place of the native Caliptra clock gate module | +| USER_ICG | config_defines.svh | If added by an integrator, provides the name of the custom clock gating module that will be used in [clk_gate.sv](../src/libs/rtl/clk_gate.sv). This substitution is only performed if integrators also define TECH_SPECIFIC_ICG. | +| TECH_SPECIFIC_ICG | config_defines.svh | Defining this causes the custom, integrator-defined clock gate module (indicated by the macro USER_ICG) to be used in place of the native Caliptra clock gate module. | ## Interface @@ -663,12 +663,12 @@ The following files implement functionality that may be process specific, and sh | Module | Description | | :------------------------------------------------------------------------------------- | :--------------------------------------------------------------------- | -| [config_defines.svh](../src/integration/rtl/config_defines.svh) | Enable Caliptra internal TRNG (if applicable)
- Declare name of custom clock gate module by defining USER_ICG
- Enable custom clock gate by defining TECH_SPECIFIC_ICG | -| [soc_ifc_pkg.sv](../src/soc_ifc/rtl/soc_ifc_pkg.sv) | Define PAUSER default behavior and (if applicable) override values. See [Integration Parameters](#integration-parameters) | +| [config_defines.svh](../src/integration/rtl/config_defines.svh) | Enable Caliptra internal TRNG (if applicable).
+ Declare name of custom clock gate module by defining USER_ICG.
+ Enable custom clock gate by defining TECH_SPECIFIC_ICG. | +| [soc_ifc_pkg.sv](../src/soc_ifc/rtl/soc_ifc_pkg.sv) | Define PAUSER default behavior and (if applicable) override values. See [Integration Parameters](#integration-parameters). | | [caliptra_icg.sv](../src/libs/rtl/caliptra_icg.sv) | Replace with technology specific clock gater.
- Modifying this file is not necessary if integrators override the clock gate module that is used by setting TECH_SPECIFIC_ICG | + Modifying this file is not necessary if integrators override the clock gate module that is used by setting TECH_SPECIFIC_ICG. | | [beh_lib.sv](../src/riscv_core/veer_el2/rtl/lib/beh_lib.sv) | Replace rvclkhdr/rvoclkhdr with technology specific clock gater. | | [caliptra_prim_flop_2sync.sv](../src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv) | Replace with technology specific sync cell. | | [caliptra_2ff_sync.sv](../src/libs/rtl/caliptra_2ff_sync.sv) | Replace with technology specific sync cell. | From 20928f496ad632a499ece7f838bc8829684b453f Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Fri, 5 Jan 2024 19:20:24 -0800 Subject: [PATCH 06/12] Change a word --- docs/CaliptraIntegrationSpecification.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/CaliptraIntegrationSpecification.md b/docs/CaliptraIntegrationSpecification.md index bdaa904cc..1a1bb2450 100644 --- a/docs/CaliptraIntegrationSpecification.md +++ b/docs/CaliptraIntegrationSpecification.md @@ -655,7 +655,7 @@ The following table describes SoC integration requirements. | ecc_montgomerymultiplier | Netlist for always_ff block does not contain flip flop | 274, 326 |Output width is smaller than internal signals, synthesis optimizes away the extra internal flops with no loads| | Multiple modules | Signed to unsigned conversion occurs | || -## Integrator RTL replacement requirements +## Integrator RTL modification requirements The following files implement functionality that may be process specific, and should be replaced by integrators using components from the cell library of their fabrication vendor. From 817c35e8532b21398305323562a157fc3aa73b9a Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Fri, 5 Jan 2024 19:22:54 -0800 Subject: [PATCH 07/12] Formatting --- docs/CaliptraIntegrationSpecification.md | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/docs/CaliptraIntegrationSpecification.md b/docs/CaliptraIntegrationSpecification.md index 1a1bb2450..9388e5802 100644 --- a/docs/CaliptraIntegrationSpecification.md +++ b/docs/CaliptraIntegrationSpecification.md @@ -663,12 +663,9 @@ The following files implement functionality that may be process specific, and sh | Module | Description | | :------------------------------------------------------------------------------------- | :--------------------------------------------------------------------- | -| [config_defines.svh](../src/integration/rtl/config_defines.svh) | Enable Caliptra internal TRNG (if applicable).
- Declare name of custom clock gate module by defining USER_ICG.
- Enable custom clock gate by defining TECH_SPECIFIC_ICG. | +| [config_defines.svh](../src/integration/rtl/config_defines.svh) | Enable Caliptra internal TRNG (if applicable).
Declare name of custom clock gate module by defining USER_ICG.
Enable custom clock gate by defining TECH_SPECIFIC_ICG. | | [soc_ifc_pkg.sv](../src/soc_ifc/rtl/soc_ifc_pkg.sv) | Define PAUSER default behavior and (if applicable) override values. See [Integration Parameters](#integration-parameters). | -| [caliptra_icg.sv](../src/libs/rtl/caliptra_icg.sv) | Replace with technology specific clock gater.
- Modifying this file is not necessary if integrators override the clock gate module that is used by setting TECH_SPECIFIC_ICG. | +| [caliptra_icg.sv](../src/libs/rtl/caliptra_icg.sv) | Replace with technology specific clock gater.
Modifying this file is not necessary if integrators override the clock gate module that is used by setting TECH_SPECIFIC_ICG. | | [beh_lib.sv](../src/riscv_core/veer_el2/rtl/lib/beh_lib.sv) | Replace rvclkhdr/rvoclkhdr with technology specific clock gater. | | [caliptra_prim_flop_2sync.sv](../src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv) | Replace with technology specific sync cell. | | [caliptra_2ff_sync.sv](../src/libs/rtl/caliptra_2ff_sync.sv) | Replace with technology specific sync cell. | From abdbcb90f661df6cf20c8e6551ae63a302d1fac7 Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Tue, 9 Jan 2024 16:41:11 -0800 Subject: [PATCH 08/12] Clarified description of file modifications to be done by integrators --- docs/CaliptraIntegrationSpecification.md | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/docs/CaliptraIntegrationSpecification.md b/docs/CaliptraIntegrationSpecification.md index 9388e5802..ed01868b6 100644 --- a/docs/CaliptraIntegrationSpecification.md +++ b/docs/CaliptraIntegrationSpecification.md @@ -657,19 +657,19 @@ The following table describes SoC integration requirements. ## Integrator RTL modification requirements -The following files implement functionality that may be process specific, and should be replaced by integrators using components from the cell library of their fabrication vendor. +Several files contain code that may be specific to an integrator's implementation and should be overridden. This overridable code is either configuration parameters with integrator-specific values or modules that implement process specific functionality. Code in these files should be modified or replaced by integrators using components from the cell library of their fabrication vendor. The following table describes recommended modifications for each file. *Table 19: Caliptra integrator custom RTL file list* -| Module | Description | +| File | Description | | :------------------------------------------------------------------------------------- | :--------------------------------------------------------------------- | | [config_defines.svh](../src/integration/rtl/config_defines.svh) | Enable Caliptra internal TRNG (if applicable).
Declare name of custom clock gate module by defining USER_ICG.
Enable custom clock gate by defining TECH_SPECIFIC_ICG. | | [soc_ifc_pkg.sv](../src/soc_ifc/rtl/soc_ifc_pkg.sv) | Define PAUSER default behavior and (if applicable) override values. See [Integration Parameters](#integration-parameters). | -| [caliptra_icg.sv](../src/libs/rtl/caliptra_icg.sv) | Replace with technology specific clock gater.
Modifying this file is not necessary if integrators override the clock gate module that is used by setting TECH_SPECIFIC_ICG. | -| [beh_lib.sv](../src/riscv_core/veer_el2/rtl/lib/beh_lib.sv) | Replace rvclkhdr/rvoclkhdr with technology specific clock gater. | -| [caliptra_prim_flop_2sync.sv](../src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv) | Replace with technology specific sync cell. | -| [caliptra_2ff_sync.sv](../src/libs/rtl/caliptra_2ff_sync.sv) | Replace with technology specific sync cell. | -| [dmi_jtag_to_core_sync.v](../src/riscv_core/veer_el2/rtl/dmi/dmi_jtag_to_core_sync.v) | Replace with technology specific sync cell. | +| [caliptra_icg.sv](../src/libs/rtl/caliptra_icg.sv) | Replace with technology-specific clock gater.
Modifying this file is not necessary if integrators override the clock gate module that is used by setting TECH_SPECIFIC_ICG. | +| [beh_lib.sv](../src/riscv_core/veer_el2/rtl/lib/beh_lib.sv) | Replace rvclkhdr/rvoclkhdr with technology-specific clock gater. | +| [caliptra_prim_flop_2sync.sv](../src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv) | Replace with technology-specific sync cell. | +| [caliptra_2ff_sync.sv](../src/libs/rtl/caliptra_2ff_sync.sv) | Replace with technology-specific sync cell. | +| [dmi_jtag_to_core_sync.v](../src/riscv_core/veer_el2/rtl/dmi/dmi_jtag_to_core_sync.v) | Replace with technology-specific sync cell. | # CDC analysis and constraints From 80e906675963b7569890d0e3b1dbe39af6ccc07a Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Wed, 10 Jan 2024 11:36:46 -0800 Subject: [PATCH 09/12] hyphenate process-specific --- docs/CaliptraIntegrationSpecification.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/CaliptraIntegrationSpecification.md b/docs/CaliptraIntegrationSpecification.md index ed01868b6..b98415702 100644 --- a/docs/CaliptraIntegrationSpecification.md +++ b/docs/CaliptraIntegrationSpecification.md @@ -657,7 +657,7 @@ The following table describes SoC integration requirements. ## Integrator RTL modification requirements -Several files contain code that may be specific to an integrator's implementation and should be overridden. This overridable code is either configuration parameters with integrator-specific values or modules that implement process specific functionality. Code in these files should be modified or replaced by integrators using components from the cell library of their fabrication vendor. The following table describes recommended modifications for each file. +Several files contain code that may be specific to an integrator's implementation and should be overridden. This overridable code is either configuration parameters with integrator-specific values or modules that implement process-specific functionality. Code in these files should be modified or replaced by integrators using components from the cell library of their fabrication vendor. The following table describes recommended modifications for each file. *Table 19: Caliptra integrator custom RTL file list* From a580a9613a0faf58b07ddefa4702696f359a9d13 Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Fri, 12 Jan 2024 13:44:44 -0800 Subject: [PATCH 10/12] Add macro for RV core custom clock gating module --- docs/CaliptraIntegrationSpecification.md | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/docs/CaliptraIntegrationSpecification.md b/docs/CaliptraIntegrationSpecification.md index b98415702..760d0472e 100644 --- a/docs/CaliptraIntegrationSpecification.md +++ b/docs/CaliptraIntegrationSpecification.md @@ -67,6 +67,8 @@ The following table describes integration parameters. | CALIPTRA_INTERNAL_QSPI | config_defines.svh | Defining this enables the internal QSPI. | | USER_ICG | config_defines.svh | If added by an integrator, provides the name of the custom clock gating module that will be used in [clk_gate.sv](../src/libs/rtl/clk_gate.sv). This substitution is only performed if integrators also define TECH_SPECIFIC_ICG. | | TECH_SPECIFIC_ICG | config_defines.svh | Defining this causes the custom, integrator-defined clock gate module (indicated by the macro USER_ICG) to be used in place of the native Caliptra clock gate module. | +| USER_EC_RV_ICG | config_defines.svh | If added by an integrator, provides the name of the custom clock gating module that will be used in the RISC-V core. This replaces the clock gating module TEC_RV_ICG defined in [beh_lib.sv](../src/riscv_core/veer_el2/rtl/lib/beh_lib.sv). This substitution is only performed if integrators also define TECH_SPECIFIC_EC_RV_ICG. | +| TECH_SPECIFIC_EC_RV_ICG | config_defines.svh | Defining this causes the custom, integrator-defined clock gate module (indicated by the macro USER_EC_RV_ICG) to be used in place of the native RISC-V core clock gate module. | ## Interface @@ -666,7 +668,7 @@ Several files contain code that may be specific to an integrator's implementatio | [config_defines.svh](../src/integration/rtl/config_defines.svh) | Enable Caliptra internal TRNG (if applicable).
Declare name of custom clock gate module by defining USER_ICG.
Enable custom clock gate by defining TECH_SPECIFIC_ICG. | | [soc_ifc_pkg.sv](../src/soc_ifc/rtl/soc_ifc_pkg.sv) | Define PAUSER default behavior and (if applicable) override values. See [Integration Parameters](#integration-parameters). | | [caliptra_icg.sv](../src/libs/rtl/caliptra_icg.sv) | Replace with technology-specific clock gater.
Modifying this file is not necessary if integrators override the clock gate module that is used by setting TECH_SPECIFIC_ICG. | -| [beh_lib.sv](../src/riscv_core/veer_el2/rtl/lib/beh_lib.sv) | Replace rvclkhdr/rvoclkhdr with technology-specific clock gater. | +| [beh_lib.sv](../src/riscv_core/veer_el2/rtl/lib/beh_lib.sv) | Replace rvclkhdr/rvoclkhdr with technology-specific clock gater.
Modifying this file may not be necessary if integrators override the clock gate module that is used by setting TECH_SPECIFIC_EC_RV_ICG. | | [caliptra_prim_flop_2sync.sv](../src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv) | Replace with technology-specific sync cell. | | [caliptra_2ff_sync.sv](../src/libs/rtl/caliptra_2ff_sync.sv) | Replace with technology-specific sync cell. | | [dmi_jtag_to_core_sync.v](../src/riscv_core/veer_el2/rtl/dmi/dmi_jtag_to_core_sync.v) | Replace with technology-specific sync cell. | From 3d7120b1dd3fc72f2cfd03f24ccbc5ba9c37aaf5 Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Fri, 12 Jan 2024 14:34:18 -0800 Subject: [PATCH 11/12] Grammar updates from review --- docs/CaliptraIntegrationSpecification.md | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/docs/CaliptraIntegrationSpecification.md b/docs/CaliptraIntegrationSpecification.md index 760d0472e..3539e249a 100644 --- a/docs/CaliptraIntegrationSpecification.md +++ b/docs/CaliptraIntegrationSpecification.md @@ -65,10 +65,10 @@ The following table describes integration parameters. | CALIPTRA_INTERNAL_TRNG | config_defines.svh | Defining this enables the internal TRNG source. | | CALIPTRA_INTERNAL_UART | config_defines.svh | Defining this enables the internal UART. | | CALIPTRA_INTERNAL_QSPI | config_defines.svh | Defining this enables the internal QSPI. | -| USER_ICG | config_defines.svh | If added by an integrator, provides the name of the custom clock gating module that will be used in [clk_gate.sv](../src/libs/rtl/clk_gate.sv). This substitution is only performed if integrators also define TECH_SPECIFIC_ICG. | -| TECH_SPECIFIC_ICG | config_defines.svh | Defining this causes the custom, integrator-defined clock gate module (indicated by the macro USER_ICG) to be used in place of the native Caliptra clock gate module. | -| USER_EC_RV_ICG | config_defines.svh | If added by an integrator, provides the name of the custom clock gating module that will be used in the RISC-V core. This replaces the clock gating module TEC_RV_ICG defined in [beh_lib.sv](../src/riscv_core/veer_el2/rtl/lib/beh_lib.sv). This substitution is only performed if integrators also define TECH_SPECIFIC_EC_RV_ICG. | -| TECH_SPECIFIC_EC_RV_ICG | config_defines.svh | Defining this causes the custom, integrator-defined clock gate module (indicated by the macro USER_EC_RV_ICG) to be used in place of the native RISC-V core clock gate module. | +| USER_ICG | config_defines.svh | If added by an integrator, provides the name of the custom clock gating module that is used in [clk_gate.sv](../src/libs/rtl/clk_gate.sv). USER_ICG replaces the clock gating module CALIPTRA_ICG defined in [caliptra_icg.sv](../src/libs/rtl/caliptra_icg.sv). This substitution is only performed if integrators also define TECH_SPECIFIC_ICG. | +| TECH_SPECIFIC_ICG | config_defines.svh | Defining this causes the custom, integrator-defined clock gate module (indicated by the USER_ICG macro) to be used in place of the native Caliptra clock gate module. | +| USER_EC_RV_ICG | config_defines.svh | If added by an integrator, provides the name of the custom clock gating module that is used in the RISC-V core. USER_EC_RV_ICG replaces the clock gating module TEC_RV_ICG defined in [beh_lib.sv](../src/riscv_core/veer_el2/rtl/lib/beh_lib.sv). This substitution is only performed if integrators also define TECH_SPECIFIC_EC_RV_ICG. | +| TECH_SPECIFIC_EC_RV_ICG | config_defines.svh | Defining this causes the custom, integrator-defined clock gate module (indicated by the USER_EC_RV_ICG macro) to be used in place of the native RISC-V core clock gate module. | ## Interface From 6708d9f54ec4ba0f293a57268a9e755ba93c1f6f Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Fri, 12 Jan 2024 14:35:56 -0800 Subject: [PATCH 12/12] Commas --- docs/CaliptraIntegrationSpecification.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/CaliptraIntegrationSpecification.md b/docs/CaliptraIntegrationSpecification.md index 3539e249a..b7e603f38 100644 --- a/docs/CaliptraIntegrationSpecification.md +++ b/docs/CaliptraIntegrationSpecification.md @@ -65,9 +65,9 @@ The following table describes integration parameters. | CALIPTRA_INTERNAL_TRNG | config_defines.svh | Defining this enables the internal TRNG source. | | CALIPTRA_INTERNAL_UART | config_defines.svh | Defining this enables the internal UART. | | CALIPTRA_INTERNAL_QSPI | config_defines.svh | Defining this enables the internal QSPI. | -| USER_ICG | config_defines.svh | If added by an integrator, provides the name of the custom clock gating module that is used in [clk_gate.sv](../src/libs/rtl/clk_gate.sv). USER_ICG replaces the clock gating module CALIPTRA_ICG defined in [caliptra_icg.sv](../src/libs/rtl/caliptra_icg.sv). This substitution is only performed if integrators also define TECH_SPECIFIC_ICG. | +| USER_ICG | config_defines.svh | If added by an integrator, provides the name of the custom clock gating module that is used in [clk_gate.sv](../src/libs/rtl/clk_gate.sv). USER_ICG replaces the clock gating module, CALIPTRA_ICG, defined in [caliptra_icg.sv](../src/libs/rtl/caliptra_icg.sv). This substitution is only performed if integrators also define TECH_SPECIFIC_ICG. | | TECH_SPECIFIC_ICG | config_defines.svh | Defining this causes the custom, integrator-defined clock gate module (indicated by the USER_ICG macro) to be used in place of the native Caliptra clock gate module. | -| USER_EC_RV_ICG | config_defines.svh | If added by an integrator, provides the name of the custom clock gating module that is used in the RISC-V core. USER_EC_RV_ICG replaces the clock gating module TEC_RV_ICG defined in [beh_lib.sv](../src/riscv_core/veer_el2/rtl/lib/beh_lib.sv). This substitution is only performed if integrators also define TECH_SPECIFIC_EC_RV_ICG. | +| USER_EC_RV_ICG | config_defines.svh | If added by an integrator, provides the name of the custom clock gating module that is used in the RISC-V core. USER_EC_RV_ICG replaces the clock gating module, TEC_RV_ICG, defined in [beh_lib.sv](../src/riscv_core/veer_el2/rtl/lib/beh_lib.sv). This substitution is only performed if integrators also define TECH_SPECIFIC_EC_RV_ICG. | | TECH_SPECIFIC_EC_RV_ICG | config_defines.svh | Defining this causes the custom, integrator-defined clock gate module (indicated by the USER_EC_RV_ICG macro) to be used in place of the native RISC-V core clock gate module. | ## Interface