From df2a881a7c0aea425317a194f286bd7333d50381 Mon Sep 17 00:00:00 2001
From: Karol Gugala <kgugala@antmicro.com>
Date: Wed, 27 Nov 2024 11:29:34 +0100
Subject: [PATCH] projects: veer: add logo

Signed-off-by: Karol Gugala <kgugala@antmicro.com>
---
 projects/logos/veer.svg              | 9 +++++++++
 projects/project-data-files/veer.yml | 2 +-
 2 files changed, 10 insertions(+), 1 deletion(-)
 create mode 100644 projects/logos/veer.svg

diff --git a/projects/logos/veer.svg b/projects/logos/veer.svg
new file mode 100644
index 0000000..025c850
--- /dev/null
+++ b/projects/logos/veer.svg
@@ -0,0 +1,9 @@
+<svg width="4096" height="744" viewBox="0 0 4096 744" fill="none" xmlns="http://www.w3.org/2000/svg">
+<path d="M2116.55 85.9419L1799.49 624.829H1684.77L1367.72 85.9419H1483.21L1617.32 316.884L1742.12 537.849L1866.92 316.884L2001.02 85.9419H2116.52H2116.55Z" fill="black"/>
+<path d="M3433.97 85.9419H3864.2C3980.47 85.9419 4073.51 129.834 4073.51 259.165C4073.51 388.497 3978.92 429.308 3864.97 429.308H3844.85L4096 624.862H3940.96L3703.77 432.388H3533.99V624.862H3434V85.9419H3433.97ZM3866.52 339.215C3927 339.215 3971.17 319.194 3971.17 259.132C3971.17 199.069 3927.75 178.312 3867.3 178.312H3533.96V339.215H3866.52Z" fill="black"/>
+<path d="M2112.34 403.128V380.027C2112.34 209.147 2172.82 158.292 2398.38 158.292C2623.95 158.292 2679.77 209.114 2680.55 380.027C2681.32 395.428 2680.55 409.288 2680.55 420.839H2214.65C2219.31 514.749 2253.42 540.93 2403.81 540.93C2561.95 540.93 2582.11 516.289 2582.11 463.96L2680.55 467.04C2680.55 580.201 2634.84 624.863 2403.03 624.863C2171.23 624.863 2112.34 574.041 2112.34 403.128V403.128ZM2214.65 349.226H2575.91C2573.58 262.212 2544.89 235.295 2399.16 235.295C2253.42 235.295 2220.86 259.166 2214.65 349.226Z" fill="black"/>
+<path d="M2753.47 403.128V380.027C2753.47 209.147 2813.94 158.292 3039.51 158.292C3265.07 158.292 3320.9 209.114 3321.68 380.027C3322.45 395.428 3321.68 409.288 3321.68 420.839H2855.78C2860.43 514.749 2894.55 540.93 3044.94 540.93C3203.08 540.93 3223.24 516.289 3223.24 463.96L3321.68 467.04C3321.68 580.201 3275.96 624.863 3044.16 624.863C2812.36 624.863 2753.47 574.041 2753.47 403.128V403.128ZM2855.78 349.226H3217.04C3214.71 262.212 3186.02 235.295 3040.28 235.295C2894.55 235.295 2861.98 259.166 2855.78 349.226Z" fill="black"/>
+<path d="M542.623 743.681L0 428.806V314.875L542.623 0V114.701L310.08 247.883L87.5829 371.824L310.08 495.765L542.623 628.947V743.648V743.681Z" fill="black"/>
+<path d="M688.021 0L1230.64 314.875V428.806L688.021 743.681V628.98L920.564 495.799L1143.06 371.857L920.564 247.916L688.021 114.734V0V0Z" fill="black"/>
+<path d="M498.157 510.06L845.421 297.03L733.734 233.62L385.257 445.88L498.157 510.06Z" fill="#10CFC9"/>
+</svg>
diff --git a/projects/project-data-files/veer.yml b/projects/project-data-files/veer.yml
index 0a68731..0c592dd 100644
--- a/projects/project-data-files/veer.yml
+++ b/projects/project-data-files/veer.yml
@@ -13,7 +13,7 @@ mission_statement_link:
   - https://github.com/chipsalliance/Cores-VeeR-EL2/blob/main/README.md
   - https://github.com/chipsalliance/Cores-VeeR-EH2/blob/main/README.md
   - https://github.com/chipsalliance/Cores-VeeR-EH1/blob/main/README.md
-svg_logo_link: N/A
+svg_logo_link: logos/veer.svg
 # The primary contact person for the project, will become TSC representative once admitted
 primary_contact:
   name: Tomasz Michalak