From adc978830e6a8fc7965a1cb1646b39294d6ad2a0 Mon Sep 17 00:00:00 2001 From: Tim Paine Date: Sun, 5 Mar 2023 13:52:09 -0500 Subject: [PATCH] working on mac compatibility changes rename synth_quicklogic to synth_quicklogic_f4pga to not conflict with yosys internal update gha to just use vendored surelog deps build and install flatbuffers install orderedmultidict for surelog fix surelog build on mac Add test assets to gitignore add specific version of surelog --- .github/workflows/build-and-test.sh | 17 +- .github/workflows/ci.yml | 75 +++++-- .github/workflows/common.sh | 7 + .github/workflows/format-check.sh | 2 +- .github/workflows/licensing.yml | 4 +- .github/workflows/setup.sh | 69 ------ .gitignore | 11 + .gitmodules | 6 - Makefile | 14 +- Makefile_plugin.common | 11 +- Makefile_test.common | 13 +- README.md | 48 +++- common/bank_tiles.h | 27 ++- dsp-ff-plugin/Makefile | 4 +- environment.yml | 23 -- ql-qlf-plugin/Makefile | 3 +- ql-qlf-plugin/synth_quicklogic.cc | 49 ++-- ql-qlf-plugin/tests/Makefile | 1 - ql-qlf-plugin/tests/consts/consts.tcl | 2 +- ql-qlf-plugin/tests/dffs/dffs.tcl | 210 +++++++++--------- ql-qlf-plugin/tests/fsm/fsm.tcl | 2 +- ql-qlf-plugin/tests/full_adder/full_adder.tcl | 24 +- .../tests/iob_no_flatten/iob_no_flatten.tcl | 4 +- .../tests/iob_no_flatten/iob_no_flatten.ys | 2 +- ql-qlf-plugin/tests/latches/latches.tcl | 18 +- ql-qlf-plugin/tests/logic/logic.tcl | 6 +- ql-qlf-plugin/tests/logic/logic.ys | 2 +- ql-qlf-plugin/tests/mac_unit/mac_unit.tcl | 4 +- ql-qlf-plugin/tests/multiplier/multiplier.tcl | 4 +- ql-qlf-plugin/tests/mux/mux.tcl | 8 +- ql-qlf-plugin/tests/pp3_bram/pp3_bram.tcl | 8 +- ql-qlf-plugin/tests/qlf_k6n10_bram/bram.tcl | 8 +- ql-qlf-plugin/tests/qlf_k6n10_bram/bram.ys | 8 +- .../asymmetric_bram18k_sdp.tcl | 4 +- .../asymmetric_bram36k_afifo.tcl | 8 +- .../asymmetric_bram36k_sdp.tcl | 8 +- .../asymmetric_bram36k_sfifo.tcl | 8 +- .../bram18k_afifo/bram18k_afifo.tcl | 8 +- .../qlf_k6n10f/bram18k_sdp/bram18k_sdp.tcl | 6 +- .../bram18k_sfifo/bram18k_sfifo.tcl | 8 +- .../qlf_k6n10f/bram18k_tdp/bram18k_tdp.tcl | 6 +- .../bram36k_afifo/bram36k_afifo.tcl | 6 +- .../qlf_k6n10f/bram36k_sdp/bram36k_sdp.tcl | 12 +- .../bram36k_sfifo/bram36k_sfifo.tcl | 6 +- .../qlf_k6n10f/bram36k_tdp/bram36k_tdp.tcl | 6 +- .../bram_asymmetric_wider_read.tcl | 8 +- .../bram_asymmetric_wider_write.tcl | 8 +- .../tests/qlf_k6n10f/bram_sdp/bram_sdp.tcl | 18 +- .../bram_sdp_split/bram_sdp_split.tcl | 14 +- .../tests/qlf_k6n10f/bram_tdp/bram_tdp.tcl | 18 +- .../bram_tdp_split/bram_tdp_split.tcl | 14 +- .../tests/qlf_k6n10f/dsp_macc/dsp_macc.tcl | 8 +- .../tests/qlf_k6n10f/dsp_madd/dsp_madd.tcl | 8 +- .../tests/qlf_k6n10f/dsp_mult/dsp_mult.tcl | 8 +- .../dsp_mult_post_synth_sim.tcl | 4 +- .../tests/qlf_k6n10f/dsp_simd/dsp_simd.tcl | 8 +- .../dsp_simd_post_synth_sim.tcl | 6 +- ql-qlf-plugin/tests/shreg/shreg.tcl | 4 +- ql-qlf-plugin/tests/tribuf/tribuf.tcl | 2 +- requirements.txt | 0 third_party/googletest | 1 - third_party/make-env | 1 - xdc-plugin/Makefile | 3 +- .../minilitex_ddr_arty/minilitex_ddr_arty.tcl | 1 + xdc-plugin/xdc.cc | 1 - 65 files changed, 457 insertions(+), 458 deletions(-) delete mode 100644 .github/workflows/setup.sh delete mode 100644 .gitmodules delete mode 100644 environment.yml delete mode 100644 requirements.txt delete mode 160000 third_party/googletest delete mode 160000 third_party/make-env diff --git a/.github/workflows/build-and-test.sh b/.github/workflows/build-and-test.sh index efab5db15..86b5c0745 100755 --- a/.github/workflows/build-and-test.sh +++ b/.github/workflows/build-and-test.sh @@ -28,13 +28,14 @@ fi start_section Building -if [ "$PLUGIN_NAME" == "xdc" ] || [ "$PLUGIN_NAME" == "sdc" ]; then - make design_introspection.so -j`nproc` - make install_design_introspection -j`nproc` -fi +if [ "$PLUGIN_NAME" == "xdc" ] || [ "$PLUGIN_NAME" == "sdc" ]; then + make design_introspection.so -j$NPROC + sudo make install_design_introspection -j$NPROC +fi export CXXFLAGS=-Werror -make ${PLUGIN_NAME}.so -j`nproc` +make ${PLUGIN_NAME}.so -j$NPROC + unset CXXFLAGS end_section @@ -42,19 +43,19 @@ end_section ########################################################################## start_section Installing -make install_${PLUGIN_NAME} -j`nproc` +sudo make install_${PLUGIN_NAME} -j$NPROC end_section ########################################################################## start_section Testing -make test_${PLUGIN_NAME} -j`nproc` +make test_${PLUGIN_NAME} -j$NPROC end_section ########################################################################## start_section Cleanup -make clean_${PLUGIN_NAME} -j`nproc` +make clean_${PLUGIN_NAME} -j$NPROC end_section ########################################################################## diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index f2fae724a..c1976beca 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -21,11 +21,11 @@ on: [push, pull_request] jobs: Run-tests: - runs-on: ubuntu-20.04 - + runs-on: ${{ matrix.os }} strategy: fail-fast: false matrix: + os: [ubuntu-20.04, macos-11] plugin: - fasm - xdc @@ -39,40 +39,87 @@ jobs: steps: - - uses: actions/checkout@v2 + - uses: actions/checkout@v4 with: submodules: recursive - - uses: actions/setup-python@v2 + - uses: actions/setup-python@v4 + with: + python-version: '3.9' - - name: Install + - name: Install Ubuntu Dependencies run: | sudo apt-get update sudo apt-get install git g++-9 build-essential bison flex \ libreadline-dev gawk tcl-dev libffi-dev git graphviz xdot \ pkg-config libboost-system-dev libboost-python-dev \ - libboost-filesystem-dev zlib1g-dev clang-format-8 cmake + libboost-filesystem-dev zlib1g-dev clang-format-8 cmake \ + nlohmann-json3-dev iverilog + if: ${{ runner.os != 'macOS'}} + + - name: Setup homebrew cache + uses: actions/cache@v3 + with: + path: | + ~/Library/Caches/Homebrew/boost--* + ~/Library/Caches/Homebrew/downloads/*--boost-* + key: brew-${{ hashFiles('cpp/perspective/CMakeLists.txt') }} + restore-keys: brew- + if: ${{ runner.os == 'macOS' }} + + - name: Install Mac Dependencies + run: | + brew install bison boost ccache cmake flex graphviz icarus-verilog make nlohmann-json + sudo ln -s /usr/local/bin/gmake /usr/local/bin/make + env: + HOMEBREW_NO_AUTO_UPDATE: "1" + if: ${{ runner.os == 'macOS'}} - name: Format run: source .github/workflows/format-check.sh env: OS: ${{ runner.os }} + if: ${{ runner.os != 'macOS'}} - name: ccache uses: hendrikmuhs/ccache-action@v1 + with: + key: ccache-${{ matrix.os }}-${{ matrix.plugin }} - - name: Install Yosys + - name: Install yosys run: | - export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH" - source .github/workflows/setup.sh - env: - OS: ${{ runner.os }} + export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH" + set -ex + + git clone https://github.com/YosysHQ/yosys.git --branch yosys-0.17 + pushd yosys + make CONFIG=gcc -j`nproc` && sudo make CONFIG=gcc install + if: ${{ runner.os != 'macOS' }} + + - name: Install yosys + run: | + export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH" + set -ex + + git clone https://github.com/YosysHQ/yosys.git --branch yosys-0.17 + pushd yosys + make -j`nproc` && sudo make install + if: ${{ runner.os == 'macOS' }} + + - name: Install Googletest + run: | + export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH" + set -ex + + git clone --branch release-1.8.1 https://github.com/google/googletest.git + pushd googletest + cmake -B build -DCMAKE_BUILD_TYPE=Release -DCMAKE_CXX_STANDARD=17 . && cmake --build build && sudo cmake --install build + popd - name: Build and test plugins run: | export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH" - source env/conda/bin/activate yosys-plugins - source .github/workflows/build-and-test.sh + .github/workflows/build-and-test.sh env: OS: ${{ runner.os }} PLUGIN_NAME: ${{ matrix.plugin }} @@ -85,7 +132,7 @@ jobs: contents: write steps: - - uses: actions/checkout@v2 + - uses: actions/checkout@v4 with: fetch-depth: 0 token: ${{ secrets.GITHUB_TOKEN }} diff --git a/.github/workflows/common.sh b/.github/workflows/common.sh index 9d5157075..c2455150c 100644 --- a/.github/workflows/common.sh +++ b/.github/workflows/common.sh @@ -26,6 +26,13 @@ fi # Parallel builds! MAKEFLAGS="-j 2" +export UNAME=`uname` +if [ "$UNAME" == "Darwin" ]; then + export NPROC=`sysctl -n hw.physicalcpu` +else + export NPROC=`nproc` +fi + function action_fold() { if [ "$1" = "start" ]; then echo "::group::$2" diff --git a/.github/workflows/format-check.sh b/.github/workflows/format-check.sh index 930ff57cf..cd7f34f1a 100644 --- a/.github/workflows/format-check.sh +++ b/.github/workflows/format-check.sh @@ -22,7 +22,7 @@ source .github/workflows/common.sh ########################################################################## start_section Formatting -make format -j`nproc` +make format -j$NPROC test $(git status --porcelain | wc -l) -eq 0 || { git diff; false; } end_section diff --git a/.github/workflows/licensing.yml b/.github/workflows/licensing.yml index 60e54f613..fd46e6c8d 100644 --- a/.github/workflows/licensing.yml +++ b/.github/workflows/licensing.yml @@ -25,7 +25,7 @@ jobs: Checks: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v2 + - uses: actions/checkout@v4 - uses: SymbiFlow/actions/checks@main with: @@ -33,5 +33,3 @@ jobs: ./design_introspection-plugin/tests/selection_to_tcl_list/selection_to_tcl_list.v ./third_party/minilitex_ddr_arty/minilitex_ddr_arty.v ./third_party/VexRiscv_Lite/VexRiscv_Lite.v - third_party: | - ./third_party/googletest/ diff --git a/.github/workflows/setup.sh b/.github/workflows/setup.sh deleted file mode 100644 index 1111aa3a9..000000000 --- a/.github/workflows/setup.sh +++ /dev/null @@ -1,69 +0,0 @@ -#! /bin/bash -# Copyright 2020-2022 F4PGA Authors -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier: Apache-2.0 - -set -e - -source .github/workflows/common.sh - -########################################################################## - -# Output status information. -start_section Status -( - set +e - set -x - git status - git branch -v - git log -n 5 --graph - git log --format=oneline -n 20 --graph -) -end_section - -########################################################################## - -# Update submodules -start_section Submodules -( - git submodule update --init --recursive -) -end_section - -########################################################################## - -#Install yosys -start_section Install-Yosys -( - echo '=====================' - echo 'Making env with Yosys' - echo '=====================' - make env - source env/conda/bin/activate yosys-plugins - conda list -) -end_section - -########################################################################## - -start_section Yosys-Version -( - source env/conda/bin/activate yosys-plugins - echo $(which yosys) - echo $(which yosys-config) - echo $(yosys --version) - echo $(yosys-config --datdir) -) -end_section diff --git a/.gitignore b/.gitignore index a299974b4..1a97c8f4d 100644 --- a/.gitignore +++ b/.gitignore @@ -4,3 +4,14 @@ *.swp *.log /*/build +pmgen.py + + +# Test assets +*/tests/*/ok +*/tests/*/*.eblif +*/tests/*/*.json +*/tests/*/*.sdc +*/tests/*/*.test +*/tests/*/tmp +*/tests/*/*.txt diff --git a/.gitmodules b/.gitmodules deleted file mode 100644 index 918b2bfde..000000000 --- a/.gitmodules +++ /dev/null @@ -1,6 +0,0 @@ -[submodule "third_party/googletest"] - path = third_party/googletest - url = https://github.com/google/googletest -[submodule "third_party/make-env"] - path = third_party/make-env - url = https://github.com/SymbiFlow/make-env.git diff --git a/Makefile b/Makefile index 11721f978..b39a1303f 100644 --- a/Makefile +++ b/Makefile @@ -34,10 +34,14 @@ PLUGINS_TEST := $(foreach plugin,$(PLUGIN_LIST),test_$(plugin)) all: plugins TOP_DIR := $(realpath $(dir $(lastword $(MAKEFILE_LIST)))) -REQUIREMENTS_FILE ?= requirements.txt -ENVIRONMENT_FILE ?= environment.yml --include third_party/make-env/conda.mk +UNAME := $(shell uname) +ifeq ($(UNAME), Linux) +NPROC = $(shell nproc) +endif +ifeq ($(UNAME), Darwin) +NPROC = $(shell sysctl -n hw.physicalcpu) +endif define install_plugin = .PHONY: $(1).so @@ -60,7 +64,7 @@ endef $(foreach plugin,$(PLUGIN_LIST),$(eval $(call install_plugin,$(plugin)))) pmgen.py: - wget -nc -O $@ https://raw.githubusercontent.com/YosysHQ/yosys/master/passes/pmgen/pmgen.py + wget -nc -O $@ https://raw.githubusercontent.com/YosysHQ/yosys/yosys-0.17/passes/pmgen/pmgen.py .PHONY: plugins plugins: $(PLUGINS) @@ -81,7 +85,7 @@ clean:: plugins_clean CLANG_FORMAT ?= clang-format-8 .PHONY: format format: - find . \( -name "*.h" -o -name "*.cc" \) -and -not -path '*/third_party/*' -print0 | xargs -0 -P $$(nproc) ${CLANG_FORMAT} -style=file -i + find . \( -name "*.h" -o -name "*.cc" \) -and -not -path '*/third_party/*' -print0 | xargs -0 -P ${NPROC} ${CLANG_FORMAT} -style=file -i VERIBLE_FORMAT ?= verible-verilog-format .PHONY: format-verilog diff --git a/Makefile_plugin.common b/Makefile_plugin.common index bfa980994..8d549ed19 100644 --- a/Makefile_plugin.common +++ b/Makefile_plugin.common @@ -46,6 +46,8 @@ TOP_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) _MAKEFILES := $(abspath $(filter-out %.d,$(MAKEFILE_LIST))) +UNAME := $(shell uname) + # Either find yosys in system and use its path or use the given path YOSYS_PATH ?= $(realpath $(dir $(shell command -v yosys))/..) @@ -61,6 +63,10 @@ LDFLAGS := $(shell $(YOSYS_CONFIG) --ldflags) $(LDFLAGS) LDLIBS := $(shell $(YOSYS_CONFIG) --ldlibs) $(LDLIBS) EXTRA_FLAGS ?= +ifeq ($(shell uname), Linux) +EXTRA_FLAGS := $(EXTRA_FLAGS) -MMD +endif + YOSYS_DATA_DIR = $(DESTDIR)$(shell $(YOSYS_CONFIG) --datdir) YOSYS_PLUGINS_DIR = $(YOSYS_DATA_DIR)/plugins @@ -93,7 +99,7 @@ endef $(foreach source,$(SOURCES),$(eval $(value _process-single-source-file))) $(_ALL_OBJECTS): $(_MAKEFILES) - $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(EXTRA_FLAGS) -MMD -c -o $@ $(TARGET_SOURCES) + $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(EXTRA_FLAGS) -c -o $@ $(TARGET_SOURCES) # Objects list for the purpose of adding extra dependencies after inclusion. # Example use: `$(OBJECTS): $(BUILD_DIR)/some-file.h` @@ -126,7 +132,8 @@ endif # Installation $(YOSYS_PLUGINS_DIR)/$(NAME).so: $(SO_LIB) | $(YOSYS_PLUGINS_DIR) - install -D $(SO_LIB) $@ + mkdir -p $(YOSYS_PLUGINS_DIR) + install $(SO_LIB) $@ .PHONY: install_plugin install_plugin: $(YOSYS_PLUGINS_DIR)/$(NAME).so diff --git a/Makefile_test.common b/Makefile_test.common index 5d72327c2..a7bd10174 100644 --- a/Makefile_test.common +++ b/Makefile_test.common @@ -25,9 +25,8 @@ ifeq (,$(wildcard $(YOSYS_CONFIG))) $(error "Didn't find 'yosys-config' under '$(YOSYS_PATH)'") endif -GTEST_DIR ?= $(abspath ../../third_party/googletest) CXX ?= $(shell $(YOSYS_CONFIG) --cxx) -CXXFLAGS ?= $(shell $(YOSYS_CONFIG) --cxxflags) -I.. -I$(GTEST_DIR)/googletest/include +CXXFLAGS ?= $(shell $(YOSYS_CONFIG) --cxxflags) -I.. LDLIBS ?= $(shell $(YOSYS_CONFIG) --ldlibs) -L$(GTEST_DIR)/build/lib -lgtest -lgtest_main -lpthread LDFLAGS ?= $(shell $(YOSYS_CONFIG) --ldflags) TEST_UTILS ?= $(abspath ../../test-utils/test-utils.tcl) @@ -79,7 +78,7 @@ $(1): $(1)/ok @printf "Test %-18s \e[32mPASSED\e[0m @ %s\n" $(1) $(CURDIR); $(1)/$$(notdir $(1).vvp): $(1)/$$(notdir $(1).v) - @iverilog -vvvv -g2005 -o $$@ $$< $(SIM_LIBS) -I../ -DVCD_FILE=\"$(1)/$$(notdir $(1).vcd)\" >$(1)/$$(notdir $(1).vvp.log) 2>&1; \ + @iverilog -vvvv -g2005 -grelative-include -I../ -DVCD_FILE=\"$(1)/$$(notdir $(1).vcd)\" -o $$@ $$< $(SIM_LIBS) >$(1)/$$(notdir $(1).vvp.log) 2>&1; \ if [ $$$$? -ne 0 ]; then \ printf "Test %-18s \e[31;1mFAILED\e[0m @ %s\n" $(1) $(CURDIR); \ false; \ @@ -142,7 +141,7 @@ define unit_test_tpl = $(1): $(1)/$(1).test @$$< -$(1)/$(1).test: $(1)/$(1).test.o $$(GTEST_DIR)/build/lib/libgtest.a +$(1)/$(1).test: $(1)/$(1).test.o @$(CXX) $(LDFLAGS) -o $$@ $$< $(LDLIBS) $(1)/$(1).test.o: $(1)/$(1).test.cc @@ -154,12 +153,6 @@ diff_test = diff $(1)/$(1).golden.$(2) $(1)/$(1).$(2) all: $(TESTS) $(SIM_TESTS) $(POST_SYNTH_SIM_TESTS) $(UNIT_TESTS) -$(GTEST_DIR)/build/lib/libgtest.a $(GTEST_DIR)/build/lib/libgtest_main.a: - @mkdir -p $(GTEST_DIR)/build - @cd $(GTEST_DIR)/build; \ - cmake ..; \ - make - .PHONY: all clean $(TESTS) $(SIM_TESTS) $(UNIT_TESTS) $(foreach test,$(TESTS),$(eval $(call test_tpl,$(test)))) diff --git a/README.md b/README.md index d440eae6d..1d47e3d65 100644 --- a/README.md +++ b/README.md @@ -2,7 +2,32 @@ This repository contains plugins for [Yosys](https://github.com/YosysHQ/yosys.git) developed as [part of the F4PGA project](https://f4pga.org). -## Design introspection plugin + +## Installation +The plugin build is tested on Ubuntu 22.04 and MacOS 11. + +On Ubuntu: +```bash +sudo apt-get install git g++-9 build-essential bison flex \ + libreadline-dev gawk tcl-dev libffi-dev git graphviz xdot \ + pkg-config libboost-system-dev libboost-python-dev \ + libboost-filesystem-dev zlib1g-dev clang-format-8 cmake \ + nlohmann-json3-dev iverilog \ +make plugins +make install +``` + +On macOS (note that macs vendor a very old version of GNU Make, so a newer one is required). + +```bash +brew install make cmake graphviz bison flex boost nlohmann-json yosys icarus-verilog +gmake plugins +gmake install +``` + +## Plugins + +### Design introspection plugin Adds several commands that allow for collecting information about cells, nets, pins and ports in the design or a selection of objects. @@ -17,7 +42,7 @@ Following commands are added with the plugin: * get_count * selection_to_tcl_list -## FASM plugin +### FASM plugin Writes out the design's [fasm features](https://fasm.readthedocs.io/en/latest/) based on the parameter annotations on a design cell. @@ -26,7 +51,7 @@ The plugin adds the following command: * write_fasm -## Integrate inverters plugin +### Integrate inverters plugin Implements a pass that integrates inverters into cells that have ports with the 'invertible_pin' attribute set. @@ -34,7 +59,7 @@ The plugin adds the following command: * integrateinv -## Parameters plugin +### Parameters plugin Reads the specified parameter on a selected object. @@ -42,7 +67,7 @@ The plugin adds the following command: * getparam -## QuickLogic IOB plugin +### QuickLogic IOB plugin [QuickLogic IOB plugin](./ql-iob-plugin/) annotates IO buffer cells with information from IO placement constraints. Used during synthesis for QuickLogic EOS-S3 architecture. @@ -51,18 +76,18 @@ The plugin adds the following command: * quicklogic_iob -## QuickLogic QLF FPGAs plugin +### QuickLogic QLF FPGAs plugin [QuickLogic QLF plugin](./ql-qlf-plugin) extends Yosys with synthesis support for `qlf_k4n8` and `qlf_k6n10` architectures. The plugin adds the following command: -* synth_quicklogic +* synth_quicklogic_f4pga * ql_dsp Detailed help on the supported command(s) can be obtained by running `help ` in Yosys. -## SDC plugin +### SDC plugin Reads Standard Delay Format (SDC) constraints, propagates these constraints across the design and writes out the complete SDC information. @@ -78,7 +103,7 @@ The plugin adds the following commands: * set_max_delay * set_clock_groups -## XDC plugin +### XDC plugin Reads Xilinx Design Constraints (XDC) files and annotates the specified cells parameters with properties such as: @@ -97,11 +122,11 @@ The plugin adds the following commands: * set_property * get_bank_tiles -## SystemVerilog plugin +### SystemVerilog plugin The SystemVerilog plugin has been moved to [chipsalliance/systemverilog-plugin](https://github.com/chipsalliance/systemverilog-plugin). -## Clock Gating plugin +### Clock Gating plugin Performs dynamic power optimization by automatically clock gating registers in design. @@ -112,3 +137,4 @@ The plugin adds the following command: * reg_clock_gating Detailed help on the supported command(s) can be obtained by running `help ` in Yosys. + diff --git a/common/bank_tiles.h b/common/bank_tiles.h index e15753bb4..c0d06dea1 100644 --- a/common/bank_tiles.h +++ b/common/bank_tiles.h @@ -17,7 +17,10 @@ * */ #include "kernel/log.h" -#include "libs/json11/json11.hpp" +#include +#include + +using json = nlohmann::json; USING_YOSYS_NAMESPACE // Coordinates of HCLK_IOI tiles associated with a specified bank @@ -32,20 +35,22 @@ inline BankTilesMap get_bank_tiles(const std::string json_file_name) if (!json_file.good()) { log_cmd_error("Can't open JSON file %s", json_file_name.c_str()); } - std::string json_str((std::istreambuf_iterator(json_file)), std::istreambuf_iterator()); - std::string error; - auto json = json11::Json::parse(json_str, error); - if (!error.empty()) { - log_cmd_error("%s\n", error.c_str()); + + json data; + try { + data = json::parse(json_file); + } catch (json::parse_error &ex) { + log_cmd_error("json parsing error: %s\n", ex.what()); + return bank_tiles; } - auto json_objects = json.object_items(); - auto iobanks = json_objects.find("iobanks"); - if (iobanks == json_objects.end()) { + + auto iobanks = data.find("iobanks"); + if (iobanks == data.end()) { log_cmd_error("IO Bank information missing in the part's json: %s\n", json_file_name.c_str()); } - for (auto iobank : iobanks->second.object_items()) { - bank_tiles.emplace(std::atoi(iobank.first.c_str()), iobank.second.string_value()); + for (auto &el : iobanks->items()) { + bank_tiles.emplace(std::atoi(el.key().c_str()), to_string(el.value())); } return bank_tiles; diff --git a/dsp-ff-plugin/Makefile b/dsp-ff-plugin/Makefile index 0466d853f..cb9994200 100644 --- a/dsp-ff-plugin/Makefile +++ b/dsp-ff-plugin/Makefile @@ -22,5 +22,5 @@ SOURCES = dsp_ff.cc include ../Makefile_plugin.common install: - install -D nexus-dsp_rules.txt $(YOSYS_DATA_DIR)/nexus/dsp_rules.txt - + mkdir -p $(YOSYS_DATA_DIR)/nexus/ + install nexus-dsp_rules.txt $(YOSYS_DATA_DIR)/nexus/dsp_rules.txt diff --git a/environment.yml b/environment.yml deleted file mode 100644 index 5e5062b3d..000000000 --- a/environment.yml +++ /dev/null @@ -1,23 +0,0 @@ -# Copyright 2020-2022 F4PGA Authors -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier: Apache-2.0 - -name: yosys-plugins -channels: - - defaults - - litex-hub -dependencies: - - litex-hub::yosys=0.17_7_g990c9b8e1=20220512_085338_py37 - - litex-hub::iverilog diff --git a/ql-qlf-plugin/Makefile b/ql-qlf-plugin/Makefile index d546b164e..5f37b3a1e 100644 --- a/ql-qlf-plugin/Makefile +++ b/ql-qlf-plugin/Makefile @@ -108,6 +108,7 @@ $(PMGEN_OUT_DIR)/ql-bram-asymmetric-wider-read.h: ql-bram-asymmetric-wider-read. python3 $(PMGEN_PY) -o $@ -p ql_bram_asymmetric_wider_read ql-bram-asymmetric-wider-read.pmg install_modules: $(VERILOG_MODULES) - $(foreach f,$^,install -D $(f) $(YOSYS_DATA_DIR)/quicklogic/$(f);) + mkdir -p $(YOSYS_DATA_DIR)/quicklogic_f4pga/$(COMMON) $(YOSYS_DATA_DIR)/quicklogic_f4pga/$(QLF_K4N8_DIR) $(YOSYS_DATA_DIR)/quicklogic_f4pga/$(QLF_K6N10_DIR) $(YOSYS_DATA_DIR)/quicklogic_f4pga/$(QLF_K6N10F_DIR) $(YOSYS_DATA_DIR)/quicklogic_f4pga/$(PP3_DIR) + $(foreach f,$^,install $(f) $(YOSYS_DATA_DIR)/quicklogic_f4pga/$(f);) install: install_modules diff --git a/ql-qlf-plugin/synth_quicklogic.cc b/ql-qlf-plugin/synth_quicklogic.cc index b6b475e6f..f0fe71987 100644 --- a/ql-qlf-plugin/synth_quicklogic.cc +++ b/ql-qlf-plugin/synth_quicklogic.cc @@ -28,7 +28,7 @@ PRIVATE_NAMESPACE_BEGIN #define STR(val) XSTR(val) #ifndef PASS_NAME -#define PASS_NAME synth_quicklogic +#define PASS_NAME synth_quicklogic_f4pga #endif struct SynthQuickLogicPass : public ScriptPass { @@ -135,7 +135,6 @@ struct SynthQuickLogicPass : public ScriptPass { { string run_from, run_to; clear_flags(); - size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { if (args[argidx] == "-run" && argidx + 1 < args.size()) { @@ -230,7 +229,7 @@ struct SynthQuickLogicPass : public ScriptPass { design->scratchpad_set_int("abc9.D", 41667); // 12MHz = 83.33.. ns; divided by two to allow for interconnect delay. } - log_header(design, "Executing SYNTH_QUICKLOGIC pass.\n"); + log_header(design, "Executing synth_quicklogic_f4pga pass.\n"); log_push(); run_script(design, run_from, run_to); @@ -241,7 +240,7 @@ struct SynthQuickLogicPass : public ScriptPass { void script() override { if (check_label("begin")) { - std::string family_path = " +/quicklogic/" + family; + std::string family_path = " +/quicklogic_f4pga/" + family; std::string readVelArgs; // Read simulation library @@ -254,7 +253,7 @@ struct SynthQuickLogicPass : public ScriptPass { // Use -nomem2reg here to prevent Yosys from complaining about // some block ram cell models. After all the only part of the cells // library required here is cell port definitions plus specify blocks. - run("read_verilog -lib -specify -nomem2reg +/quicklogic/common/cells_sim.v" + readVelArgs); + run("read_verilog -lib -specify -nomem2reg +/quicklogic_f4pga/common/cells_sim.v" + readVelArgs); run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); } @@ -291,7 +290,7 @@ struct SynthQuickLogicPass : public ScriptPass { if (help_mode || !nodsp) { run("memory_dff"); run("wreduce t:$mul"); - run("techmap -map +/mul2dsp.v -map +/quicklogic/" + family + + run("techmap -map +/mul2dsp.v -map +/quicklogic_f4pga/" + family + "/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 " "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 " "-D DSP_NAME=$__MUL16X16", @@ -324,13 +323,13 @@ struct SynthQuickLogicPass : public ScriptPass { run("ql_dsp_macc" + use_dsp_cfg_params, "(for qlf_k6n10f if not -no_dsp)"); run("techmap -map +/mul2dsp.v [...]", " (for qlf_k6n10f if not -no_dsp)"); run("chtype -set $mul t:$__soft_mul", " (for qlf_k6n10f if not -no_dsp)"); - run("techmap -map +/quicklogic/" + family + "/dsp_map.v", "(for qlf_k6n10f if not -no_dsp)"); + run("techmap -map +/quicklogic_f4pga/" + family + "/dsp_map.v", "(for qlf_k6n10f if not -no_dsp)"); if (use_dsp_cfg_params.empty()) - run("techmap -map +/quicklogic/" + family + "/dsp_map.v -D USE_DSP_CFG_PARAMS=0", "(for qlf_k6n10f if not -no_dsp)"); + run("techmap -map +/quicklogic_f4pga/" + family + "/dsp_map.v -D USE_DSP_CFG_PARAMS=0", "(for qlf_k6n10f if not -no_dsp)"); else - run("techmap -map +/quicklogic/" + family + "/dsp_map.v -D USE_DSP_CFG_PARAMS=1", "(for qlf_k6n10f if not -no_dsp)"); + run("techmap -map +/quicklogic_f4pga/" + family + "/dsp_map.v -D USE_DSP_CFG_PARAMS=1", "(for qlf_k6n10f if not -no_dsp)"); run("ql_dsp_simd ", "(for qlf_k6n10f if not -no_dsp)"); - run("techmap -map +/quicklogic/" + family + "/dsp_final_map.v", "(for qlf_k6n10f if not -no_dsp)"); + run("techmap -map +/quicklogic_f4pga/" + family + "/dsp_final_map.v", "(for qlf_k6n10f if not -no_dsp)"); run("ql_dsp_io_regs"); } else if (!nodsp) { @@ -346,11 +345,11 @@ struct SynthQuickLogicPass : public ScriptPass { run("chtype -set $mul t:$__soft_mul"); } if (use_dsp_cfg_params.empty()) - run("techmap -map +/quicklogic/" + family + "/dsp_map.v -D USE_DSP_CFG_PARAMS=0"); + run("techmap -map +/quicklogic_f4pga/" + family + "/dsp_map.v -D USE_DSP_CFG_PARAMS=0"); else - run("techmap -map +/quicklogic/" + family + "/dsp_map.v -D USE_DSP_CFG_PARAMS=1"); + run("techmap -map +/quicklogic_f4pga/" + family + "/dsp_map.v -D USE_DSP_CFG_PARAMS=1"); run("ql_dsp_simd"); - run("techmap -map +/quicklogic/" + family + "/dsp_final_map.v"); + run("techmap -map +/quicklogic_f4pga/" + family + "/dsp_final_map.v"); run("ql_dsp_io_regs"); } } @@ -370,14 +369,14 @@ struct SynthQuickLogicPass : public ScriptPass { } if (check_label("map_bram", "(skip if -no_bram)") && (family == "qlf_k6n10" || family == "qlf_k6n10f" || family == "pp3") && inferBram) { - run("memory_bram -rules +/quicklogic/" + family + "/brams.txt"); + run("memory_bram -rules +/quicklogic_f4pga/" + family + "/brams.txt"); if (family == "pp3") { run("pp3_braminit"); } run("ql_bram_split ", "(for qlf_k6n10f if not -no_bram)"); - run("techmap -autoproc -map +/quicklogic/" + family + "/brams_map.v"); + run("techmap -autoproc -map +/quicklogic_f4pga/" + family + "/brams_map.v"); if (family == "qlf_k6n10f") { - run("techmap -map +/quicklogic/" + family + "/brams_final_map.v"); + run("techmap -map +/quicklogic_f4pga/" + family + "/brams_final_map.v"); } // Data width to specialized cell type width map @@ -439,7 +438,7 @@ struct SynthQuickLogicPass : public ScriptPass { if (check_label("map_gates")) { if (inferAdder && (family == "qlf_k4n8" || family == "qlf_k6n10" || family == "qlf_k6n10f")) { - run("techmap -map +/techmap.v -map +/quicklogic/" + family + "/arith_map.v"); + run("techmap -map +/techmap.v -map +/quicklogic_f4pga/" + family + "/arith_map.v"); } else { run("techmap"); } @@ -476,9 +475,9 @@ struct SynthQuickLogicPass : public ScriptPass { run("dfflegalize" + legalizeArgs); } else if (family == "pp3") { run("dfflegalize -cell $_DFFSRE_PPPP_ 0 -cell $_DLATCH_?_ x"); - run("techmap -map +/quicklogic/" + family + "/cells_map.v"); + run("techmap -map +/quicklogic_f4pga/" + family + "/cells_map.v"); } - std::string techMapArgs = " -map +/techmap.v -map +/quicklogic/" + family + "/ffs_map.v"; + std::string techMapArgs = " -map +/techmap.v -map +/quicklogic_f4pga/" + family + "/ffs_map.v"; if (!noffmap) { run("techmap " + techMapArgs); } @@ -497,14 +496,14 @@ struct SynthQuickLogicPass : public ScriptPass { } else if (family == "qlf_k4n8") { run("abc -lut 4 "); } else if (family == "pp3") { - run("techmap -map +/quicklogic/" + family + "/latches_map.v"); + run("techmap -map +/quicklogic_f4pga/" + family + "/latches_map.v"); if (abc9) { - run("read_verilog -lib -specify -icells +/quicklogic/" + family + "/abc9_model.v"); - run("techmap -map +/quicklogic/" + family + "/abc9_map.v"); + run("read_verilog -lib -specify -icells +/quicklogic_f4pga/" + family + "/abc9_model.v"); + run("techmap -map +/quicklogic_f4pga/" + family + "/abc9_map.v"); run("abc9 -maxlut 4 -dff"); - run("techmap -map +/quicklogic/" + family + "/abc9_unmap.v"); + run("techmap -map +/quicklogic_f4pga/" + family + "/abc9_unmap.v"); } else { - std::string lutDefs = "+/quicklogic/" + family + "/lutdefs.txt"; + std::string lutDefs = "+/quicklogic_f4pga/" + family + "/lutdefs.txt"; rewrite_filename(lutDefs); std::string abcArgs = "+read_lut," + lutDefs + @@ -523,7 +522,7 @@ struct SynthQuickLogicPass : public ScriptPass { if (check_label("map_cells") && (family == "qlf_k6n10" || family == "pp3")) { std::string techMapArgs; - techMapArgs = "-map +/quicklogic/" + family + "/lut_map.v"; + techMapArgs = "-map +/quicklogic_f4pga/" + family + "/lut_map.v"; run("techmap " + techMapArgs); run("clean"); } diff --git a/ql-qlf-plugin/tests/Makefile b/ql-qlf-plugin/tests/Makefile index cd1c7e1e5..2993a5600 100644 --- a/ql-qlf-plugin/tests/Makefile +++ b/ql-qlf-plugin/tests/Makefile @@ -37,7 +37,6 @@ TESTS = \ # qlf_k6n10_bram \ SIM_TESTS = \ - qlf_k6n10f/sim_dsp_mult_cfg_ports \ qlf_k6n10f/sim_dsp_mult_cfg_ports \ qlf_k6n10f/sim_dsp_mult_cfg_params \ qlf_k6n10f/sim_dsp_mult_r_cfg_ports \ diff --git a/ql-qlf-plugin/tests/consts/consts.tcl b/ql-qlf-plugin/tests/consts/consts.tcl index 270f6790c..44e9ef0ee 100644 --- a/ql-qlf-plugin/tests/consts/consts.tcl +++ b/ql-qlf-plugin/tests/consts/consts.tcl @@ -4,7 +4,7 @@ yosys -import ;# ingest plugin commands read_verilog $::env(DESIGN_TOP).v -synth_quicklogic -top my_top -family pp3 +synth_quicklogic_f4pga -top my_top -family pp3 stat yosys cd my_top select -assert-count 1 t:my_lut diff --git a/ql-qlf-plugin/tests/dffs/dffs.tcl b/ql-qlf-plugin/tests/dffs/dffs.tcl index 4e8792eab..9d348094c 100644 --- a/ql-qlf-plugin/tests/dffs/dffs.tcl +++ b/ql-qlf-plugin/tests/dffs/dffs.tcl @@ -11,8 +11,8 @@ design -save read # DFF hierarchy -top my_dff yosys proc -equiv_opt -assert -async2sync -map +/quicklogic/qlf_k4n8/cells_sim.v synth_quicklogic -family qlf_k4n8 -top my_dff -synth_quicklogic -family qlf_k4n8 -top my_dff +equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k4n8/cells_sim.v synth_quicklogic_f4pga -family qlf_k4n8 -top my_dff +synth_quicklogic_f4pga -family qlf_k4n8 -top my_dff design -load postopt yosys cd my_dff stat @@ -20,7 +20,7 @@ select -assert-count 1 t:dffsr # DFFR (posedge RST) design -load read -synth_quicklogic -family qlf_k4n8 -top my_dffr_p +synth_quicklogic_f4pga -family qlf_k4n8 -top my_dffr_p yosys cd my_dffr_p stat select -assert-count 1 t:dffsr @@ -28,7 +28,7 @@ select -assert-count 1 t:\$lut # DFFR (posedge RST) design -load read -synth_quicklogic -family qlf_k4n8 -top my_dffr_p_2 +synth_quicklogic_f4pga -family qlf_k4n8 -top my_dffr_p_2 yosys cd my_dffr_p_2 stat select -assert-count 2 t:dffsr @@ -36,14 +36,14 @@ select -assert-count 1 t:\$lut # DFFR (negedge RST) design -load read -synth_quicklogic -family qlf_k4n8 -top my_dffr_n +synth_quicklogic_f4pga -family qlf_k4n8 -top my_dffr_n yosys cd my_dffr_n stat select -assert-count 1 t:dffsr # DFFS (posedge SET) design -load read -synth_quicklogic -family qlf_k4n8 -top my_dffs_p +synth_quicklogic_f4pga -family qlf_k4n8 -top my_dffs_p yosys cd my_dffs_p stat select -assert-count 1 t:dffsr @@ -51,14 +51,14 @@ select -assert-count 1 t:\$lut # DFFS (negedge SET) design -load read -synth_quicklogic -family qlf_k4n8 -top my_dffs_n +synth_quicklogic_f4pga -family qlf_k4n8 -top my_dffs_n yosys cd my_dffs_n stat select -assert-count 1 t:dffsr # DFFN design -load read -synth_quicklogic -family qlf_k4n8 -top my_dffn +synth_quicklogic_f4pga -family qlf_k4n8 -top my_dffn yosys cd my_dffn stat select -assert-count 1 t:dffnsr @@ -66,7 +66,7 @@ select -assert-count 1 t:dffnsr # DFFNR (negedge CLK posedge RST) design -load read -synth_quicklogic -family qlf_k4n8 -top my_dffnr_p +synth_quicklogic_f4pga -family qlf_k4n8 -top my_dffnr_p yosys cd my_dffnr_p stat select -assert-count 1 t:dffnsr @@ -74,14 +74,14 @@ select -assert-count 1 t:\$lut # DFFNR (negedge CLK negedge RST) design -load read -synth_quicklogic -family qlf_k4n8 -top my_dffnr_n +synth_quicklogic_f4pga -family qlf_k4n8 -top my_dffnr_n yosys cd my_dffnr_n stat select -assert-count 1 t:dffnsr # DFFNS (negedge CLK posedge SET) design -load read -synth_quicklogic -family qlf_k4n8 -top my_dffns_p +synth_quicklogic_f4pga -family qlf_k4n8 -top my_dffns_p yosys cd my_dffns_p stat select -assert-count 1 t:dffnsr @@ -89,14 +89,14 @@ select -assert-count 1 t:\$lut # DFFS (negedge CLK negedge SET) design -load read -synth_quicklogic -family qlf_k4n8 -top my_dffns_n +synth_quicklogic_f4pga -family qlf_k4n8 -top my_dffns_n yosys cd my_dffns_n stat select -assert-count 1 t:dffnsr # DFFSR (posedge CLK posedge SET posedge RST) design -load read -synth_quicklogic -family qlf_k4n8 -top my_dffsr_ppp +synth_quicklogic_f4pga -family qlf_k4n8 -top my_dffsr_ppp yosys cd my_dffsr_ppp stat select -assert-count 1 t:dffsr @@ -104,7 +104,7 @@ select -assert-count 2 t:\$lut # DFFSR (posedge CLK negedge SET posedge RST) design -load read -synth_quicklogic -family qlf_k4n8 -top my_dffsr_pnp +synth_quicklogic_f4pga -family qlf_k4n8 -top my_dffsr_pnp yosys cd my_dffsr_pnp stat select -assert-count 1 t:dffsr @@ -112,7 +112,7 @@ select -assert-count 2 t:\$lut # DFFSR (posedge CLK posedge SET negedge RST) design -load read -synth_quicklogic -family qlf_k4n8 -top my_dffsr_ppn +synth_quicklogic_f4pga -family qlf_k4n8 -top my_dffsr_ppn yosys cd my_dffsr_ppn stat select -assert-count 1 t:dffsr @@ -120,7 +120,7 @@ select -assert-count 1 t:\$lut # DFFSR (posedge CLK negedge SET negedge RST) design -load read -synth_quicklogic -family qlf_k4n8 -top my_dffsr_pnn +synth_quicklogic_f4pga -family qlf_k4n8 -top my_dffsr_pnn yosys cd my_dffsr_pnn stat select -assert-count 1 t:dffsr @@ -128,7 +128,7 @@ select -assert-count 1 t:\$lut # DFFSR (negedge CLK posedge SET posedge RST) design -load read -synth_quicklogic -family qlf_k4n8 -top my_dffsr_npp +synth_quicklogic_f4pga -family qlf_k4n8 -top my_dffsr_npp yosys cd my_dffsr_npp stat select -assert-count 1 t:dffnsr @@ -136,7 +136,7 @@ select -assert-count 2 t:\$lut # DFFSR (negedge CLK negedge SET posedge RST) design -load read -synth_quicklogic -family qlf_k4n8 -top my_dffsr_nnp +synth_quicklogic_f4pga -family qlf_k4n8 -top my_dffsr_nnp yosys cd my_dffsr_nnp stat select -assert-count 1 t:dffnsr @@ -144,7 +144,7 @@ select -assert-count 2 t:\$lut # DFFSR (negedge CLK posedge SET negedge RST) design -load read -synth_quicklogic -family qlf_k4n8 -top my_dffsr_npn +synth_quicklogic_f4pga -family qlf_k4n8 -top my_dffsr_npn yosys cd my_dffsr_npn stat select -assert-count 1 t:dffnsr @@ -152,7 +152,7 @@ select -assert-count 1 t:\$lut # DFFSR (negedge CLK negedge SET negedge RST) design -load read -synth_quicklogic -family qlf_k4n8 -top my_dffsr_nnn +synth_quicklogic_f4pga -family qlf_k4n8 -top my_dffsr_nnn yosys cd my_dffsr_nnn stat select -assert-count 1 t:dffnsr @@ -169,7 +169,7 @@ design -save read # DFF hierarchy -top my_dff yosys proc -equiv_opt -assert -map +/quicklogic/qlf_k6n10/cells_sim.v synth_quicklogic -family qlf_k6n10 -top my_dff +equiv_opt -assert -map +/quicklogic_f4pga/qlf_k6n10/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10 -top my_dff design -load postopt yosys cd my_dff stat @@ -177,21 +177,21 @@ select -assert-count 1 t:dff # DFFR (posedge RST) design -load read -synth_quicklogic -family qlf_k6n10 -top my_dffr_p +synth_quicklogic_f4pga -family qlf_k6n10 -top my_dffr_p yosys cd my_dffr_p stat select -assert-count 1 t:dffr # DFFR (posedge RST) design -load read -synth_quicklogic -family qlf_k6n10 -top my_dffr_p_2 +synth_quicklogic_f4pga -family qlf_k6n10 -top my_dffr_p_2 yosys cd my_dffr_p_2 stat select -assert-count 2 t:dffr # DFFR (negedge RST) design -load read -synth_quicklogic -family qlf_k6n10 -top my_dffr_n +synth_quicklogic_f4pga -family qlf_k6n10 -top my_dffr_n yosys cd my_dffr_n stat select -assert-count 1 t:dffr @@ -199,14 +199,14 @@ select -assert-count 1 t:\$lut #DFFRE (posedge RST) design -load read -synth_quicklogic -family qlf_k6n10 -top my_dffre_p +synth_quicklogic_f4pga -family qlf_k6n10 -top my_dffre_p yosys cd my_dffre_p stat select -assert-count 1 t:dffre #DFFRE (negedge RST) design -load read -synth_quicklogic -family qlf_k6n10 -top my_dffre_n +synth_quicklogic_f4pga -family qlf_k6n10 -top my_dffre_n yosys cd my_dffre_n stat select -assert-count 1 t:dffre @@ -214,14 +214,14 @@ select -assert-count 1 t:\$lut # DFFS (posedge SET) design -load read -synth_quicklogic -family qlf_k6n10 -top my_dffs_p +synth_quicklogic_f4pga -family qlf_k6n10 -top my_dffs_p yosys cd my_dffs_p stat select -assert-count 1 t:dffs # DFFS (negedge SET) design -load read -synth_quicklogic -family qlf_k6n10 -top my_dffs_n +synth_quicklogic_f4pga -family qlf_k6n10 -top my_dffs_n yosys cd my_dffs_n stat select -assert-count 1 t:dffs @@ -229,21 +229,21 @@ select -assert-count 1 t:\$lut # DFFSE (posedge SET) design -load read -synth_quicklogic -family qlf_k6n10 -top my_dffse_p +synth_quicklogic_f4pga -family qlf_k6n10 -top my_dffse_p yosys cd my_dffse_p stat select -assert-count 1 t:dffse # DFFSE (negedge SET) design -load read -synth_quicklogic -family qlf_k6n10 -top my_dffse_n +synth_quicklogic_f4pga -family qlf_k6n10 -top my_dffse_n yosys cd my_dffse_n stat select -assert-count 1 t:dffse # DFFN design -load read -synth_quicklogic -family qlf_k6n10 -top my_dffn +synth_quicklogic_f4pga -family qlf_k6n10 -top my_dffn yosys cd my_dffn stat select -assert-count 1 t:dff @@ -251,7 +251,7 @@ select -assert-count 1 t:\$lut # DFFNR (negedge CLK posedge RST) design -load read -synth_quicklogic -family qlf_k6n10 -top my_dffnr_p +synth_quicklogic_f4pga -family qlf_k6n10 -top my_dffnr_p yosys cd my_dffnr_p stat select -assert-count 1 t:dffr @@ -259,7 +259,7 @@ select -assert-count 1 t:\$lut # DFFNR (negedge CLK negedge RST) design -load read -synth_quicklogic -family qlf_k6n10 -top my_dffnr_n +synth_quicklogic_f4pga -family qlf_k6n10 -top my_dffnr_n yosys cd my_dffnr_n stat select -assert-count 1 t:dffr @@ -267,7 +267,7 @@ select -assert-count 2 t:\$lut # DFFNS (negedge CLK posedge SET) design -load read -synth_quicklogic -family qlf_k6n10 -top my_dffns_p +synth_quicklogic_f4pga -family qlf_k6n10 -top my_dffns_p yosys cd my_dffns_p stat select -assert-count 1 t:dffs @@ -275,7 +275,7 @@ select -assert-count 1 t:\$lut # DFFS (negedge CLK negedge SET) design -load read -synth_quicklogic -family qlf_k6n10 -top my_dffns_n +synth_quicklogic_f4pga -family qlf_k6n10 -top my_dffns_n yosys cd my_dffns_n stat select -assert-count 1 t:dffs @@ -283,7 +283,7 @@ select -assert-count 2 t:\$lut # DFFSR (posedge CLK posedge SET posedge RST) design -load read -synth_quicklogic -family qlf_k6n10 -top my_dffsr_ppp +synth_quicklogic_f4pga -family qlf_k6n10 -top my_dffsr_ppp yosys cd my_dffsr_ppp stat select -assert-count 1 t:dffsr @@ -291,7 +291,7 @@ select -assert-count 1 t:\$lut # DFFSR (posedge CLK negedge SET posedge RST) design -load read -synth_quicklogic -family qlf_k6n10 -top my_dffsr_pnp +synth_quicklogic_f4pga -family qlf_k6n10 -top my_dffsr_pnp yosys cd my_dffsr_pnp stat select -assert-count 1 t:dffsr @@ -299,7 +299,7 @@ select -assert-count 1 t:\$lut # DFFSR (posedge CLK posedge SET negedge RST) design -load read -synth_quicklogic -family qlf_k6n10 -top my_dffsr_ppn +synth_quicklogic_f4pga -family qlf_k6n10 -top my_dffsr_ppn yosys cd my_dffsr_ppn stat select -assert-count 1 t:dffsr @@ -307,7 +307,7 @@ select -assert-count 2 t:\$lut # DFFSR (posedge CLK negedge SET negedge RST) design -load read -synth_quicklogic -family qlf_k6n10 -top my_dffsr_pnn +synth_quicklogic_f4pga -family qlf_k6n10 -top my_dffsr_pnn yosys cd my_dffsr_pnn stat select -assert-count 1 t:dffsr @@ -315,7 +315,7 @@ select -assert-count 2 t:\$lut # DFFSR (negedge CLK posedge SET posedge RST) design -load read -synth_quicklogic -family qlf_k6n10 -top my_dffsr_npp +synth_quicklogic_f4pga -family qlf_k6n10 -top my_dffsr_npp yosys cd my_dffsr_npp stat select -assert-count 1 t:dffsr @@ -323,7 +323,7 @@ select -assert-count 2 t:\$lut # DFFSR (negedge CLK negedge SET posedge RST) design -load read -synth_quicklogic -family qlf_k6n10 -top my_dffsr_nnp +synth_quicklogic_f4pga -family qlf_k6n10 -top my_dffsr_nnp yosys cd my_dffsr_nnp stat select -assert-count 1 t:dffsr @@ -331,7 +331,7 @@ select -assert-count 2 t:\$lut # DFFSR (negedge CLK posedge SET negedge RST) design -load read -synth_quicklogic -family qlf_k6n10 -top my_dffsr_npn +synth_quicklogic_f4pga -family qlf_k6n10 -top my_dffsr_npn yosys cd my_dffsr_npn stat select -assert-count 1 t:dffsr @@ -339,7 +339,7 @@ select -assert-count 3 t:\$lut # DFFSR (negedge CLK negedge SET negedge RST) design -load read -synth_quicklogic -family qlf_k6n10 -top my_dffsr_nnn +synth_quicklogic_f4pga -family qlf_k6n10 -top my_dffsr_nnn yosys cd my_dffsr_nnn stat select -assert-count 1 t:dffsr @@ -347,7 +347,7 @@ select -assert-count 3 t:\$lut # DFFSRE (posedge CLK posedge SET posedge RST) design -load read -synth_quicklogic -family qlf_k6n10 -top my_dffsre_ppp +synth_quicklogic_f4pga -family qlf_k6n10 -top my_dffsre_ppp yosys cd my_dffsre_ppp stat select -assert-count 1 t:dffsre @@ -355,7 +355,7 @@ select -assert-count 1 t:\$lut # DFFSRE (posedge CLK negedge SET posedge RST) design -load read -synth_quicklogic -family qlf_k6n10 -top my_dffsre_pnp +synth_quicklogic_f4pga -family qlf_k6n10 -top my_dffsre_pnp yosys cd my_dffsre_pnp stat select -assert-count 1 t:dffsre @@ -363,7 +363,7 @@ select -assert-count 1 t:\$lut # DFFSRE (posedge CLK posedge SET negedge RST) design -load read -synth_quicklogic -family qlf_k6n10 -top my_dffsre_ppn +synth_quicklogic_f4pga -family qlf_k6n10 -top my_dffsre_ppn yosys cd my_dffsre_ppn stat select -assert-count 1 t:dffsre @@ -371,7 +371,7 @@ select -assert-count 2 t:\$lut # DFFSRE (posedge CLK negedge SET negedge RST) design -load read -synth_quicklogic -family qlf_k6n10 -top my_dffsre_pnn +synth_quicklogic_f4pga -family qlf_k6n10 -top my_dffsre_pnn yosys cd my_dffsre_pnn stat select -assert-count 1 t:dffsre @@ -379,7 +379,7 @@ select -assert-count 2 t:\$lut # DFFSRE (negedge CLK posedge SET posedge RST) design -load read -synth_quicklogic -family qlf_k6n10 -top my_dffsre_npp +synth_quicklogic_f4pga -family qlf_k6n10 -top my_dffsre_npp yosys cd my_dffsre_npp stat select -assert-count 1 t:dffsre @@ -387,7 +387,7 @@ select -assert-count 2 t:\$lut # DFFSRE (negedge CLK negedge SET posedge RST) design -load read -synth_quicklogic -family qlf_k6n10 -top my_dffsre_nnp +synth_quicklogic_f4pga -family qlf_k6n10 -top my_dffsre_nnp yosys cd my_dffsre_nnp stat select -assert-count 1 t:dffsre @@ -395,7 +395,7 @@ select -assert-count 2 t:\$lut # DFFSRE (negedge CLK posedge SET negedge RST) design -load read -synth_quicklogic -family qlf_k6n10 -top my_dffsre_npn +synth_quicklogic_f4pga -family qlf_k6n10 -top my_dffsre_npn yosys cd my_dffsre_npn stat select -assert-count 1 t:dffsre @@ -403,7 +403,7 @@ select -assert-count 3 t:\$lut # DFFSRE (negedge CLK negedge SET negedge RST) design -load read -synth_quicklogic -family qlf_k6n10 -top my_dffsre_nnn +synth_quicklogic_f4pga -family qlf_k6n10 -top my_dffsre_nnn yosys cd my_dffsre_nnn stat select -assert-count 1 t:dffsre @@ -420,7 +420,7 @@ design -save read # DFF hierarchy -top my_dff yosys proc -equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_dff +equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_dff design -load postopt yosys cd my_dff stat @@ -430,7 +430,7 @@ select -assert-count 1 t:sdffsre design -load read hierarchy -top my_dffn yosys proc -equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_dffn +equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_dffn design -load postopt yosys cd my_dffn stat @@ -441,7 +441,7 @@ select -assert-count 1 t:sdffnsre design -load read hierarchy -top my_dffr_n yosys proc -equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_dffr_n +equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_dffr_n design -load postopt yosys cd my_dffr_n stat @@ -451,7 +451,7 @@ select -assert-count 1 t:dffsre design -load read hierarchy -top my_dffr_p yosys proc -equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_dffr_p +equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_dffr_p design -load postopt yosys cd my_dffr_p stat @@ -462,7 +462,7 @@ select -assert-count 1 t:\$lut design -load read hierarchy -top my_dffre_n yosys proc -equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_dffre_n +equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_dffre_n design -load postopt yosys cd my_dffre_n stat @@ -472,7 +472,7 @@ select -assert-count 1 t:dffsre design -load read hierarchy -top my_dffre_p yosys proc -equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_dffre_p +equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_dffre_p design -load postopt yosys cd my_dffre_p stat @@ -484,7 +484,7 @@ select -assert-count 1 t:\$lut design -load read hierarchy -top my_dffs_n yosys proc -equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_dffs_n +equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_dffs_n design -load postopt yosys cd my_dffs_n stat @@ -494,7 +494,7 @@ select -assert-count 1 t:dffsre design -load read hierarchy -top my_dffs_p yosys proc -equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_dffs_p +equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_dffs_p design -load postopt yosys cd my_dffs_p stat @@ -505,7 +505,7 @@ select -assert-count 1 t:\$lut design -load read hierarchy -top my_dffse_n yosys proc -equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_dffse_n +equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_dffse_n design -load postopt yosys cd my_dffse_n stat @@ -515,7 +515,7 @@ select -assert-count 1 t:dffsre design -load read hierarchy -top my_dffse_p yosys proc -equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_dffse_p +equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_dffse_p design -load postopt yosys cd my_dffse_p stat @@ -527,7 +527,7 @@ select -assert-count 1 t:\$lut design -load read hierarchy -top my_sdffr_n yosys proc -equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_sdffr_n +equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_sdffr_n design -load postopt yosys cd my_sdffr_n stat @@ -537,7 +537,7 @@ select -assert-count 1 t:sdffsre design -load read hierarchy -top my_sdffr_p yosys proc -equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_sdffr_p +equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_sdffr_p design -load postopt yosys cd my_sdffr_p stat @@ -548,7 +548,7 @@ select -assert-count 1 t:\$lut design -load read hierarchy -top my_sdffs_n yosys proc -equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_sdffs_n +equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_sdffs_n design -load postopt yosys cd my_sdffs_n stat @@ -558,7 +558,7 @@ select -assert-count 1 t:sdffsre design -load read hierarchy -top my_sdffs_p yosys proc -equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_sdffs_p +equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_sdffs_p design -load postopt yosys cd my_sdffs_p stat @@ -570,7 +570,7 @@ select -assert-count 1 t:\$lut design -load read hierarchy -top my_sdffnr_n yosys proc -equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_sdffnr_n +equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_sdffnr_n design -load postopt yosys cd my_sdffnr_n stat @@ -580,7 +580,7 @@ select -assert-count 1 t:sdffnsre design -load read hierarchy -top my_sdffnr_p yosys proc -equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_sdffnr_p +equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_sdffnr_p design -load postopt yosys cd my_sdffnr_p stat @@ -591,7 +591,7 @@ select -assert-count 1 t:\$lut design -load read hierarchy -top my_sdffns_n yosys proc -equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_sdffns_n +equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_sdffns_n design -load postopt yosys cd my_sdffns_n stat @@ -601,7 +601,7 @@ select -assert-count 1 t:sdffnsre design -load read hierarchy -top my_sdffns_p yosys proc -equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_sdffns_p +equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_sdffns_p design -load postopt yosys cd my_sdffns_p stat @@ -613,7 +613,7 @@ select -assert-count 1 t:\$lut design -load read hierarchy -top my_latch yosys proc -equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_latch +equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_latch design -load postopt yosys cd my_latch stat @@ -623,7 +623,7 @@ select -assert-count 1 t:latchsre design -load read hierarchy -top my_latchn yosys proc -equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_latchn +equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_latchn design -load postopt yosys cd my_latchn stat @@ -634,7 +634,7 @@ select -assert-count 1 t:latchnsre #design -load read #hierarchy -top my_latchr_n #yosys proc -#equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_latchr_n +#equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_latchr_n #design -load postopt #yosys cd my_latchr_n #stat @@ -644,7 +644,7 @@ select -assert-count 1 t:latchnsre #design -load read #hierarchy -top my_latchr_p #yosys proc -#equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_latchr_p +#equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_latchr_p #design -load postopt #yosys cd my_latchr_p #stat @@ -655,7 +655,7 @@ select -assert-count 1 t:latchnsre #design -load read #hierarchy -top my_latchs_n #yosys proc -#equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_latchs_n +#equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_latchs_n #design -load postopt #yosys cd my_latchs_n #stat @@ -665,7 +665,7 @@ select -assert-count 1 t:latchnsre #design -load read #hierarchy -top my_latchs_p #yosys proc -#equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_latchs_p +#equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_latchs_p #design -load postopt #yosys cd my_latchs_p #stat @@ -677,7 +677,7 @@ select -assert-count 1 t:latchnsre #design -load read #hierarchy -top my_latchnr_n #yosys proc -#equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_latchnr_n +#equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_latchnr_n #design -load postopt #yosys cd my_latchnr_n #stat @@ -687,7 +687,7 @@ select -assert-count 1 t:latchnsre #design -load read #hierarchy -top my_latchnr_p #yosys proc -#equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_latchnr_p +#equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_latchnr_p #design -load postopt #yosys cd my_latchnr_p #stat @@ -698,7 +698,7 @@ select -assert-count 1 t:latchnsre #design -load read #hierarchy -top my_latchns_n #yosys proc -#equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_latchns_n +#equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_latchns_n #design -load postopt #yosys cd my_latchns_n #stat @@ -708,7 +708,7 @@ select -assert-count 1 t:latchnsre #design -load read #hierarchy -top my_latchns_p #yosys proc -#equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_latchns_p +#equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_latchns_p #design -load postopt #yosys cd my_latchns_p #stat @@ -727,7 +727,7 @@ design -save read # DFF hierarchy -top my_dff yosys proc -equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_dff -nosdff +equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_dff -nosdff design -load postopt yosys cd my_dff stat @@ -737,7 +737,7 @@ select -assert-count 1 t:dffsre design -load read hierarchy -top my_dffn yosys proc -equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_dffn -nosdff +equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_dffn -nosdff design -load postopt yosys cd my_dffn stat @@ -748,7 +748,7 @@ select -assert-count 1 t:dffnsre design -load read hierarchy -top my_dffr_n yosys proc -equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_dffr_n -nosdff +equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_dffr_n -nosdff design -load postopt yosys cd my_dffr_n stat @@ -758,7 +758,7 @@ select -assert-count 1 t:dffsre design -load read hierarchy -top my_dffr_p yosys proc -equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_dffr_p -nosdff +equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_dffr_p -nosdff design -load postopt yosys cd my_dffr_p stat @@ -769,7 +769,7 @@ select -assert-count 1 t:\$lut design -load read hierarchy -top my_dffre_n yosys proc -equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_dffre_n -nosdff +equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_dffre_n -nosdff design -load postopt yosys cd my_dffre_n stat @@ -779,7 +779,7 @@ select -assert-count 1 t:dffsre design -load read hierarchy -top my_dffre_p yosys proc -equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_dffre_p -nosdff +equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_dffre_p -nosdff design -load postopt yosys cd my_dffre_p stat @@ -791,7 +791,7 @@ select -assert-count 1 t:\$lut design -load read hierarchy -top my_dffs_n yosys proc -equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_dffs_n -nosdff +equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_dffs_n -nosdff design -load postopt yosys cd my_dffs_n stat @@ -801,7 +801,7 @@ select -assert-count 1 t:dffsre design -load read hierarchy -top my_dffs_p yosys proc -equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_dffs_p -nosdff +equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_dffs_p -nosdff design -load postopt yosys cd my_dffs_p stat @@ -812,7 +812,7 @@ select -assert-count 1 t:\$lut design -load read hierarchy -top my_dffse_n yosys proc -equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_dffse_n -nosdff +equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_dffse_n -nosdff design -load postopt yosys cd my_dffse_n stat @@ -822,7 +822,7 @@ select -assert-count 1 t:dffsre design -load read hierarchy -top my_dffse_p yosys proc -equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_dffse_p -nosdff +equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_dffse_p -nosdff design -load postopt yosys cd my_dffse_p stat @@ -834,7 +834,7 @@ select -assert-count 1 t:\$lut design -load read hierarchy -top my_latch yosys proc -equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_latch -nosdff +equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_latch -nosdff design -load postopt yosys cd my_latch stat @@ -844,7 +844,7 @@ select -assert-count 1 t:latchsre design -load read hierarchy -top my_latchn yosys proc -equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_latchn -nosdff +equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_latchn -nosdff design -load postopt yosys cd my_latchn stat @@ -855,7 +855,7 @@ select -assert-count 1 t:latchnsre #design -load read #hierarchy -top my_latchr_n #yosys proc -#equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_latchr_n -nosdff +#equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_latchr_n -nosdff #design -load postopt #yosys cd my_latchr_n #stat @@ -865,7 +865,7 @@ select -assert-count 1 t:latchnsre #design -load read #hierarchy -top my_latchr_p #yosys proc -#equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_latchr_p -nosdff +#equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_latchr_p -nosdff #design -load postopt #yosys cd my_latchr_p #stat @@ -876,7 +876,7 @@ select -assert-count 1 t:latchnsre #design -load read #hierarchy -top my_latchs_n #yosys proc -#equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_latchs_n -nosdff +#equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_latchs_n -nosdff #design -load postopt #yosys cd my_latchs_n #stat @@ -886,7 +886,7 @@ select -assert-count 1 t:latchnsre #design -load read #hierarchy -top my_latchs_p #yosys proc -#equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_latchs_p -nosdff +#equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_latchs_p -nosdff #design -load postopt #yosys cd my_latchs_p #stat @@ -898,7 +898,7 @@ select -assert-count 1 t:latchnsre #design -load read #hierarchy -top my_latchnr_n #yosys proc -#equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_latchnr_n -nosdff +#equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_latchnr_n -nosdff #design -load postopt #yosys cd my_latchnr_n #stat @@ -908,7 +908,7 @@ select -assert-count 1 t:latchnsre #design -load read #hierarchy -top my_latchnr_p #yosys proc -#equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_latchnr_p -nosdff +#equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_latchnr_p -nosdff #design -load postopt #yosys cd my_latchnr_p #stat @@ -919,7 +919,7 @@ select -assert-count 1 t:latchnsre #design -load read #hierarchy -top my_latchns_n #yosys proc -#equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_latchns_n -nosdff +#equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_latchns_n -nosdff #design -load postopt #yosys cd my_latchns_n #stat @@ -929,7 +929,7 @@ select -assert-count 1 t:latchnsre #design -load read #hierarchy -top my_latchns_p #yosys proc -#equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f -top my_latchns_p -nosdff +#equiv_opt -assert -async2sync -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f -top my_latchns_p -nosdff #design -load postopt #yosys cd my_latchns_p #stat @@ -950,7 +950,7 @@ design -save read # DFF hierarchy -top my_dff yosys proc -equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3 -top my_dff +equiv_opt -async2sync -assert -map +/quicklogic_f4pga/pp3/cells_sim.v synth_quicklogic_f4pga -family pp3 -top my_dff design -load postopt yosys cd my_dff stat @@ -965,7 +965,7 @@ select -assert-count 1 t:logic_1 design -load read hierarchy -top my_dffe yosys proc -equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3 -top my_dffe +equiv_opt -async2sync -assert -map +/quicklogic_f4pga/pp3/cells_sim.v synth_quicklogic_f4pga -family pp3 -top my_dffe design -load postopt yosys cd my_dffe stat @@ -979,7 +979,7 @@ select -assert-count 1 t:logic_0 design -load read hierarchy -top my_dffr_p yosys proc -equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3 -top my_dffr_p +equiv_opt -async2sync -assert -map +/quicklogic_f4pga/pp3/cells_sim.v synth_quicklogic_f4pga -family pp3 -top my_dffr_p design -load postopt yosys cd my_dffr_p stat @@ -996,7 +996,7 @@ select -assert-none t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad %% t:* design -load read hierarchy -top my_dffr_n yosys proc -equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3 -top my_dffr_n +equiv_opt -async2sync -assert -map +/quicklogic_f4pga/pp3/cells_sim.v synth_quicklogic_f4pga -family pp3 -top my_dffr_n design -load postopt yosys cd my_dffr_n stat @@ -1014,7 +1014,7 @@ select -assert-none t:LUT1 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad design -load read hierarchy -top my_sdffs_p yosys proc -equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3 -top my_sdffs_p +equiv_opt -async2sync -assert -map +/quicklogic_f4pga/pp3/cells_sim.v synth_quicklogic_f4pga -family pp3 -top my_sdffs_p design -load postopt yosys cd my_sdffs_p stat @@ -1032,7 +1032,7 @@ select -assert-none t:LUT2 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad design -load read hierarchy -top my_sdffns_p yosys proc -equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3 -top my_sdffns_p +equiv_opt -async2sync -assert -map +/quicklogic_f4pga/pp3/cells_sim.v synth_quicklogic_f4pga -family pp3 -top my_sdffns_p design -load postopt yosys cd my_sdffns_p stat diff --git a/ql-qlf-plugin/tests/fsm/fsm.tcl b/ql-qlf-plugin/tests/fsm/fsm.tcl index 61a1e108e..b41ce255d 100644 --- a/ql-qlf-plugin/tests/fsm/fsm.tcl +++ b/ql-qlf-plugin/tests/fsm/fsm.tcl @@ -9,7 +9,7 @@ hierarchy -top fsm yosys proc flatten -equiv_opt -run :prove -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3 +equiv_opt -run :prove -map +/quicklogic_f4pga/pp3/cells_sim.v synth_quicklogic_f4pga -family pp3 async2sync miter -equiv -make_assert -flatten gold gate miter sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter diff --git a/ql-qlf-plugin/tests/full_adder/full_adder.tcl b/ql-qlf-plugin/tests/full_adder/full_adder.tcl index 83b68cb8c..52b165f8b 100644 --- a/ql-qlf-plugin/tests/full_adder/full_adder.tcl +++ b/ql-qlf-plugin/tests/full_adder/full_adder.tcl @@ -6,7 +6,7 @@ yosys -import ;# ingest plugin commands read_verilog -icells -DWIDTH=4 $::env(DESIGN_TOP).v hierarchy -check -top full_adder yosys proc -equiv_opt -assert -map +/quicklogic/qlf_k4n8/cells_sim.v synth_quicklogic -family qlf_k4n8 +equiv_opt -assert -map +/quicklogic_f4pga/qlf_k4n8/cells_sim.v synth_quicklogic_f4pga -family qlf_k4n8 design -reset @@ -14,21 +14,21 @@ design -reset read_verilog -icells -DWIDTH=4 $::env(DESIGN_TOP).v hierarchy -check -top subtractor yosys proc -equiv_opt -assert -map +/quicklogic/qlf_k4n8/cells_sim.v synth_quicklogic -family qlf_k4n8 +equiv_opt -assert -map +/quicklogic_f4pga/qlf_k4n8/cells_sim.v synth_quicklogic_f4pga -family qlf_k4n8 design -reset # Equivalence check for comparator synthesis read_verilog -icells -DWIDTH=4 $::env(DESIGN_TOP).v hierarchy -check -top comparator yosys proc -equiv_opt -assert -map +/quicklogic/qlf_k4n8/cells_sim.v synth_quicklogic -family qlf_k4n8 +equiv_opt -assert -map +/quicklogic_f4pga/qlf_k4n8/cells_sim.v synth_quicklogic_f4pga -family qlf_k4n8 design -reset # Equivalence check for adder synthesis for qlf-k6n10 read_verilog -icells -DWIDTH=4 $::env(DESIGN_TOP).v hierarchy -check -top full_adder yosys proc -equiv_opt -assert -map +/quicklogic/qlf_k6n10/cells_sim.v synth_quicklogic -family qlf_k6n10 +equiv_opt -assert -map +/quicklogic_f4pga/qlf_k6n10/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10 design -load postopt yosys cd full_adder stat @@ -40,7 +40,7 @@ design -reset read_verilog -icells -DWIDTH=4 $::env(DESIGN_TOP).v hierarchy -check -top subtractor yosys proc -equiv_opt -assert -map +/quicklogic/qlf_k6n10/cells_sim.v synth_quicklogic -family qlf_k6n10 +equiv_opt -assert -map +/quicklogic_f4pga/qlf_k6n10/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10 design -load postopt yosys cd subtractor stat @@ -52,7 +52,7 @@ design -reset read_verilog -icells -DWIDTH=4 $::env(DESIGN_TOP).v hierarchy -check -top comparator yosys proc -equiv_opt -assert -map +/quicklogic/qlf_k6n10/cells_sim.v synth_quicklogic -family qlf_k6n10 +equiv_opt -assert -map +/quicklogic_f4pga/qlf_k6n10/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10 design -load postopt yosys cd comparator stat @@ -64,7 +64,7 @@ design -reset read_verilog -icells -DWIDTH=4 $::env(DESIGN_TOP).v hierarchy -check -top full_adder yosys proc -equiv_opt -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f +equiv_opt -assert -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f design -load postopt yosys cd full_adder stat @@ -76,7 +76,7 @@ design -reset read_verilog -icells -DWIDTH=4 $::env(DESIGN_TOP).v hierarchy -check -top subtractor yosys proc -equiv_opt -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f +equiv_opt -assert -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f design -load postopt yosys cd subtractor stat @@ -88,7 +88,7 @@ design -reset read_verilog -icells -DWIDTH=4 $::env(DESIGN_TOP).v hierarchy -check -top comparator yosys proc -equiv_opt -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f +equiv_opt -assert -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10f design -load postopt yosys cd comparator stat @@ -100,7 +100,7 @@ design -reset read_verilog -icells -DWIDTH=4 $::env(DESIGN_TOP).v hierarchy -check -top full_adder yosys proc -equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3 +equiv_opt -assert -map +/quicklogic_f4pga/pp3/cells_sim.v synth_quicklogic_f4pga -family pp3 design -load postopt yosys cd full_adder @@ -119,7 +119,7 @@ design -reset read_verilog -icells -DWIDTH=4 $::env(DESIGN_TOP).v hierarchy -check -top subtractor yosys proc -equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3 +equiv_opt -assert -map +/quicklogic_f4pga/pp3/cells_sim.v synth_quicklogic_f4pga -family pp3 design -load postopt yosys cd subtractor @@ -137,7 +137,7 @@ design -reset read_verilog -icells -DWIDTH=4 $::env(DESIGN_TOP).v hierarchy -check -top comparator yosys proc -equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3 +equiv_opt -assert -map +/quicklogic_f4pga/pp3/cells_sim.v synth_quicklogic_f4pga -family pp3 design -load postopt yosys cd comparator diff --git a/ql-qlf-plugin/tests/iob_no_flatten/iob_no_flatten.tcl b/ql-qlf-plugin/tests/iob_no_flatten/iob_no_flatten.tcl index 6e6ccb5bd..575cfb23e 100644 --- a/ql-qlf-plugin/tests/iob_no_flatten/iob_no_flatten.tcl +++ b/ql-qlf-plugin/tests/iob_no_flatten/iob_no_flatten.tcl @@ -4,7 +4,7 @@ yosys -import ;# ingest plugin commands read_verilog $::env(DESIGN_TOP).v -synth_quicklogic -family qlf_k4n8 -top my_top +synth_quicklogic_f4pga -family qlf_k4n8 -top my_top yosys stat yosys cd my_top select -assert-count 2 t:dffsr @@ -13,7 +13,7 @@ design -reset read_verilog $::env(DESIGN_TOP).v -synth_quicklogic -family qlf_k6n10 -top my_top +synth_quicklogic_f4pga -family qlf_k6n10 -top my_top yosys stat yosys cd my_top select -assert-count 2 t:dff diff --git a/ql-qlf-plugin/tests/iob_no_flatten/iob_no_flatten.ys b/ql-qlf-plugin/tests/iob_no_flatten/iob_no_flatten.ys index 1dfc87c27..34f6e9623 100644 --- a/ql-qlf-plugin/tests/iob_no_flatten/iob_no_flatten.ys +++ b/ql-qlf-plugin/tests/iob_no_flatten/iob_no_flatten.ys @@ -1,7 +1,7 @@ plugin -i ql-qlf read_verilog ./iob_no_flatten.v -synth_quicklogic -family qlf_k4n8 -top my_top +synth_quicklogic_f4pga -family qlf_k4n8 -top my_top stat cd my_top select -assert-count 2 t:$_DFF_P_ diff --git a/ql-qlf-plugin/tests/latches/latches.tcl b/ql-qlf-plugin/tests/latches/latches.tcl index 72b31d831..242d2416d 100644 --- a/ql-qlf-plugin/tests/latches/latches.tcl +++ b/ql-qlf-plugin/tests/latches/latches.tcl @@ -8,14 +8,14 @@ design -save read # Tests for qlf_k6n10 family # LATCHP design -load read -synth_quicklogic -family qlf_k6n10 -top latchp +synth_quicklogic_f4pga -family qlf_k6n10 -top latchp yosys cd latchp stat select -assert-count 1 t:latchsre # LATCHN design -load read -synth_quicklogic -family qlf_k6n10 -top latchn +synth_quicklogic_f4pga -family qlf_k6n10 -top latchn yosys cd latchn stat select -assert-count 1 t:\$lut @@ -23,7 +23,7 @@ select -assert-count 1 t:latchsre # LATCHSRE design -load read -synth_quicklogic -family qlf_k6n10 -top my_latchsre +synth_quicklogic_f4pga -family qlf_k6n10 -top my_latchsre yosys cd my_latchsre stat select -assert-count 2 t:\$lut @@ -31,16 +31,16 @@ select -assert-count 1 t:latchsre ## Tests for qlf_k4n8 family ## Currently disabled cause latch aren't supported -## in synth_quicklogic for that family +## in synth_quicklogic_f4pga for that family ## LATCHP -#synth_quicklogic -family qlf_k4n8 -top latchp +#synth_quicklogic_f4pga -family qlf_k4n8 -top latchp #yosys cd latchp #stat #select -assert-count 1 t:\$_DLATCH_P_ # ## LATCHP no init #design -load read -#synth_quicklogic -family qlf_k4n8 -top latchp_noinit +#synth_quicklogic_f4pga -family qlf_k4n8 -top latchp_noinit #yosys cd latchp_noinit #stat #select -assert-count 1 t:\$_DLATCH_P_ @@ -52,7 +52,7 @@ design -load read hierarchy -top latchp_noinit yosys proc # Can't run any sort of equivalence check because latches are blown to LUTs -synth_quicklogic -family pp3 -top latchp_noinit +synth_quicklogic_f4pga -family pp3 -top latchp_noinit yosys cd latchp_noinit select -assert-count 1 t:LUT3 select -assert-count 3 t:inpad @@ -65,7 +65,7 @@ design -load read hierarchy -top latchn yosys proc # Can't run any sort of equivalence check because latches are blown to LUTs -synth_quicklogic -family pp3 -top latchn +synth_quicklogic_f4pga -family pp3 -top latchn yosys cd latchn select -assert-count 1 t:LUT3 select -assert-count 3 t:inpad @@ -78,7 +78,7 @@ design -load read hierarchy -top my_latchsre yosys proc # Can't run any sort of equivalence check because latches are blown to LUTs -synth_quicklogic -family pp3 -top my_latchsre +synth_quicklogic_f4pga -family pp3 -top my_latchsre yosys cd my_latchsre select -assert-count 1 t:LUT2 select -assert-count 1 t:LUT4 diff --git a/ql-qlf-plugin/tests/logic/logic.tcl b/ql-qlf-plugin/tests/logic/logic.tcl index b1de9f73c..cdfc5cc64 100644 --- a/ql-qlf-plugin/tests/logic/logic.tcl +++ b/ql-qlf-plugin/tests/logic/logic.tcl @@ -6,7 +6,7 @@ yosys -import ;# ingest plugin commands read_verilog $::env(DESIGN_TOP).v hierarchy -top top yosys proc -equiv_opt -assert -map +/quicklogic/qlf_k4n8/cells_sim.v synth_quicklogic -family qlf_k4n8 +equiv_opt -assert -map +/quicklogic_f4pga/qlf_k4n8/cells_sim.v synth_quicklogic_f4pga -family qlf_k4n8 design -load postopt yosys cd top @@ -19,7 +19,7 @@ design -reset read_verilog $::env(DESIGN_TOP).v hierarchy -top top yosys proc -equiv_opt -assert -map +/quicklogic/qlf_k6n10/cells_sim.v synth_quicklogic -family qlf_k6n10 +equiv_opt -assert -map +/quicklogic_f4pga/qlf_k6n10/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10 design -load postopt yosys cd top @@ -32,7 +32,7 @@ design -reset read_verilog $::env(DESIGN_TOP).v hierarchy -top top yosys proc -equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3 +equiv_opt -assert -map +/quicklogic_f4pga/pp3/cells_sim.v synth_quicklogic_f4pga -family pp3 design -load postopt yosys cd top diff --git a/ql-qlf-plugin/tests/logic/logic.ys b/ql-qlf-plugin/tests/logic/logic.ys index 037896c37..9c906c17f 100644 --- a/ql-qlf-plugin/tests/logic/logic.ys +++ b/ql-qlf-plugin/tests/logic/logic.ys @@ -2,7 +2,7 @@ plugin -i ql-qlf read_verilog ./logic.v hierarchy -top top proc -equiv_opt -assert -map +/quicklogic/qlf_k4n8/cells_sim.v synth_quicklogic -family qlf_k4n8 +equiv_opt -assert -map +/quicklogic_f4pga/qlf_k4n8/cells_sim.v synth_quicklogic_f4pga -family qlf_k4n8 design -load postopt cd top diff --git a/ql-qlf-plugin/tests/mac_unit/mac_unit.tcl b/ql-qlf-plugin/tests/mac_unit/mac_unit.tcl index 0db32a985..41b4ebdd6 100644 --- a/ql-qlf-plugin/tests/mac_unit/mac_unit.tcl +++ b/ql-qlf-plugin/tests/mac_unit/mac_unit.tcl @@ -8,7 +8,7 @@ design -save read #Infer QL_DSP hierarchy -top $TOP -synth_quicklogic -family qlf_k6n10 -top $TOP +synth_quicklogic_f4pga -family qlf_k6n10 -top $TOP yosys cd $TOP stat select -assert-count 1 t:QL_DSP @@ -16,7 +16,7 @@ select -assert-count 1 t:QL_DSP #Test no_dsp arg design -load read hierarchy -top $TOP -synth_quicklogic -family qlf_k6n10 -top $TOP -no_dsp +synth_quicklogic_f4pga -family qlf_k6n10 -top $TOP -no_dsp yosys cd $TOP stat select -assert-count 0 t:QL_DSP diff --git a/ql-qlf-plugin/tests/multiplier/multiplier.tcl b/ql-qlf-plugin/tests/multiplier/multiplier.tcl index 5c783c258..8eb8fc37c 100644 --- a/ql-qlf-plugin/tests/multiplier/multiplier.tcl +++ b/ql-qlf-plugin/tests/multiplier/multiplier.tcl @@ -8,7 +8,7 @@ design -save read #Infer QL_DSP hierarchy -top $TOP -synth_quicklogic -family qlf_k6n10 -top $TOP +synth_quicklogic_f4pga -family qlf_k6n10 -top $TOP yosys cd $TOP stat select -assert-count 1 t:QL_DSP @@ -16,7 +16,7 @@ select -assert-count 1 t:QL_DSP #Test no_dsp arg design -load read hierarchy -top $TOP -synth_quicklogic -family qlf_k6n10 -top $TOP -no_dsp +synth_quicklogic_f4pga -family qlf_k6n10 -top $TOP -no_dsp yosys cd $TOP stat select -assert-count 0 t:QL_DSP diff --git a/ql-qlf-plugin/tests/mux/mux.tcl b/ql-qlf-plugin/tests/mux/mux.tcl index 3d0f94981..b36f82802 100644 --- a/ql-qlf-plugin/tests/mux/mux.tcl +++ b/ql-qlf-plugin/tests/mux/mux.tcl @@ -7,7 +7,7 @@ design -save read hierarchy -top mux2 yosys proc -equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3 +equiv_opt -assert -map +/quicklogic_f4pga/pp3/cells_sim.v synth_quicklogic_f4pga -family pp3 design -load postopt yosys cd mux2 select -assert-count 1 t:LUT3 @@ -19,7 +19,7 @@ select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D design -load read hierarchy -top mux4 yosys proc -equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3 +equiv_opt -assert -map +/quicklogic_f4pga/pp3/cells_sim.v synth_quicklogic_f4pga -family pp3 design -load postopt yosys cd mux4 select -assert-count 3 t:LUT3 @@ -31,7 +31,7 @@ select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D design -load read hierarchy -top mux8 yosys proc -equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3 +equiv_opt -assert -map +/quicklogic_f4pga/pp3/cells_sim.v synth_quicklogic_f4pga -family pp3 design -load postopt yosys cd mux8 select -assert-count 1 t:LUT1 @@ -45,7 +45,7 @@ select -assert-none t:LUT1 t:LUT3 t:mux4x0 t:inpad t:outpad %% t:* %D design -load read hierarchy -top mux16 yosys proc -equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3 +equiv_opt -assert -map +/quicklogic_f4pga/pp3/cells_sim.v synth_quicklogic_f4pga -family pp3 design -load postopt yosys cd mux16 select -assert-count 1 t:LUT3 diff --git a/ql-qlf-plugin/tests/pp3_bram/pp3_bram.tcl b/ql-qlf-plugin/tests/pp3_bram/pp3_bram.tcl index eadfda3cd..598a1d067 100644 --- a/ql-qlf-plugin/tests/pp3_bram/pp3_bram.tcl +++ b/ql-qlf-plugin/tests/pp3_bram/pp3_bram.tcl @@ -6,7 +6,7 @@ read_verilog $::env(DESIGN_TOP).v design -save read design -load read -synth_quicklogic -family pp3 -top top_bram_9_16 +synth_quicklogic_f4pga -family pp3 -top top_bram_9_16 yosys cd top_bram_9_16 stat select -assert-count 1 t:ckpad @@ -15,7 +15,7 @@ select -assert-count 16 t:outpad select -assert-count 1 t:ram8k_2x1_cell_macro design -load read -synth_quicklogic -family pp3 -top top_bram_9_32 +synth_quicklogic_f4pga -family pp3 -top top_bram_9_32 yosys cd top_bram_9_32 stat select -assert-count 1 t:ckpad @@ -24,7 +24,7 @@ select -assert-count 32 t:outpad select -assert-count 1 t:ram8k_2x1_cell_macro design -load read -synth_quicklogic -family pp3 -top top_bram_10_16 +synth_quicklogic_f4pga -family pp3 -top top_bram_10_16 yosys cd top_bram_10_16 stat select -assert-count 1 t:ckpad @@ -34,7 +34,7 @@ select -assert-count 1 t:ram8k_2x1_cell_macro # BRAM initialization from file using pp3_braminig pass test design -load read -synth_quicklogic -family pp3 -top top_bram_init +synth_quicklogic_f4pga -family pp3 -top top_bram_init yosys cd top_bram_init stat select -assert-count 1 t:ckpad diff --git a/ql-qlf-plugin/tests/qlf_k6n10_bram/bram.tcl b/ql-qlf-plugin/tests/qlf_k6n10_bram/bram.tcl index 5275fa53f..0c74746bc 100644 --- a/ql-qlf-plugin/tests/qlf_k6n10_bram/bram.tcl +++ b/ql-qlf-plugin/tests/qlf_k6n10_bram/bram.tcl @@ -6,22 +6,22 @@ read_verilog $::env(DESIGN_TOP).v hierarchy -top BRAM_32x512 yosys proc yosys memory -equiv_opt -assert -map +/quicklogic/qlf_k6n10_cells_sim.v synth_quicklogic -family qlf_k6n10 -top BRAM_32x512 +equiv_opt -assert -map +/quicklogic_f4pga/qlf_k6n10_cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10 -top BRAM_32x512 design -load read -synth_quicklogic -family qlf_k6n10 -top BRAM_16x1024 +synth_quicklogic_f4pga -family qlf_k6n10 -top BRAM_16x1024 yosys cd BRAM_16x1024 stat select -assert-count 1 t:DP_RAM16K design -load read -synth_quicklogic -family qlf_k6n10 -top BRAM_8x2048 +synth_quicklogic_f4pga -family qlf_k6n10 -top BRAM_8x2048 yosys cd BRAM_16x1024 stat select -assert-count 1 t:DP_RAM16K design -load read -synth_quicklogic -family qlf_k6n10 -top BRAM_4x4096 +synth_quicklogic_f4pga -family qlf_k6n10 -top BRAM_4x4096 yosys cd BRAM_16x1024 stat select -assert-count 1 t:DP_RAM16K diff --git a/ql-qlf-plugin/tests/qlf_k6n10_bram/bram.ys b/ql-qlf-plugin/tests/qlf_k6n10_bram/bram.ys index 20228ca6f..72ebee600 100644 --- a/ql-qlf-plugin/tests/qlf_k6n10_bram/bram.ys +++ b/ql-qlf-plugin/tests/qlf_k6n10_bram/bram.ys @@ -8,7 +8,7 @@ design -save read hierarchy -top BRAM_32x512 proc memory -equiv_opt -assert -map +/quicklogic/qlf_k6n10/cells_sim.v synth_quicklogic -family qlf_k6n10 -top BRAM_32x512 +equiv_opt -assert -map +/quicklogic_f4pga/qlf_k6n10/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10 -top BRAM_32x512 design -load postopt cd BRAM_32x512 stat @@ -19,7 +19,7 @@ select -assert-count 1 t:DP_RAM16K hierarchy -top BRAM_32x512 proc memory -equiv_opt -assert -map +/quicklogic/qlf_k6n10/cells_sim.v synth_quicklogic -family qlf_k6n10 -top BRAM_16x1024 +equiv_opt -assert -map +/quicklogic_f4pga/qlf_k6n10/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10 -top BRAM_16x1024 design -load postopt cd BRAM_16x1024 stat @@ -30,7 +30,7 @@ select -assert-count 1 t:DP_RAM16K hierarchy -top BRAM_8x2048 proc memory -equiv_opt -assert -map +/quicklogic/qlf_k6n10/cells_sim.v synth_quicklogic -family qlf_k6n10 -top BRAM_8x2048 +equiv_opt -assert -map +/quicklogic_f4pga/qlf_k6n10/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10 -top BRAM_8x2048 design -load postopt cd BRAM_8x2048 stat @@ -41,7 +41,7 @@ select -assert-count 1 t:DP_RAM16K hierarchy -top BRAM_4x4096 proc memory -equiv_opt -assert -map +/quicklogic/qlf_k6n10/cells_sim.v synth_quicklogic -family qlf_k6n10 -top BRAM_4x4096 +equiv_opt -assert -map +/quicklogic_f4pga/qlf_k6n10/cells_sim.v synth_quicklogic_f4pga -family qlf_k6n10 -top BRAM_4x4096 design -load postopt cd BRAM_4x4096 stat diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram18k_sdp/asymmetric_bram18k_sdp.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram18k_sdp/asymmetric_bram18k_sdp.tcl index 05794628e..ef217bfb3 100644 --- a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram18k_sdp/asymmetric_bram18k_sdp.tcl +++ b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram18k_sdp/asymmetric_bram18k_sdp.tcl @@ -8,7 +8,7 @@ design -save asymmetric_bram18k_sdp select spram_9x2048_18x1024 select * -synth_quicklogic -family qlf_k6n10f -top spram_9x2048_18x1024 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top spram_9x2048_18x1024 -bram_types opt_expr -undriven opt_clean stat @@ -19,7 +19,7 @@ select -clear design -load asymmetric_bram18k_sdp select spram_18x1024_9x2048 select * -synth_quicklogic -family qlf_k6n10f -top spram_18x1024_9x2048 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top spram_18x1024_9x2048 -bram_types opt_expr -undriven opt_clean stat diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_afifo/asymmetric_bram36k_afifo.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_afifo/asymmetric_bram36k_afifo.tcl index 66e26863c..88086fc85 100644 --- a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_afifo/asymmetric_bram36k_afifo.tcl +++ b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_afifo/asymmetric_bram36k_afifo.tcl @@ -8,7 +8,7 @@ design -save asymmetric_bram36k_afifo select af4096x9_1024x36 select * -synth_quicklogic -family qlf_k6n10f -top af4096x9_1024x36 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top af4096x9_1024x36 -bram_types opt_expr -undriven opt_clean stat @@ -19,7 +19,7 @@ select -clear design -load asymmetric_bram36k_afifo select af2048x18_1024x36 select * -synth_quicklogic -family qlf_k6n10f -top af2048x18_1024x36 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top af2048x18_1024x36 -bram_types opt_expr -undriven opt_clean stat @@ -30,7 +30,7 @@ select -clear design -load asymmetric_bram36k_afifo select af2048x18_4098x9 select * -synth_quicklogic -family qlf_k6n10f -top af2048x18_4098x9 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top af2048x18_4098x9 -bram_types opt_expr -undriven opt_clean stat @@ -41,7 +41,7 @@ select -clear design -load asymmetric_bram36k_afifo select af1024x36_4098x9 select * -synth_quicklogic -family qlf_k6n10f -top af1024x36_4098x9 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top af1024x36_4098x9 -bram_types opt_expr -undriven opt_clean stat diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sdp/asymmetric_bram36k_sdp.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sdp/asymmetric_bram36k_sdp.tcl index 827914a45..db0818442 100644 --- a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sdp/asymmetric_bram36k_sdp.tcl +++ b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sdp/asymmetric_bram36k_sdp.tcl @@ -8,7 +8,7 @@ design -save asymmetric_bram36k_sdp select spram_9x4096_36x1024 select * -synth_quicklogic -family qlf_k6n10f -top spram_9x4096_36x1024 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top spram_9x4096_36x1024 -bram_types opt_expr -undriven opt_clean stat @@ -19,7 +19,7 @@ select -clear design -load asymmetric_bram36k_sdp select spram_18x2048_36x1024 select * -synth_quicklogic -family qlf_k6n10f -top spram_18x2048_36x1024 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top spram_18x2048_36x1024 -bram_types opt_expr -undriven opt_clean stat @@ -30,7 +30,7 @@ select -clear design -load asymmetric_bram36k_sdp select spram_18x2048_9x4096 select * -synth_quicklogic -family qlf_k6n10f -top spram_18x2048_9x4096 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top spram_18x2048_9x4096 -bram_types opt_expr -undriven opt_clean stat @@ -41,7 +41,7 @@ select -clear design -load asymmetric_bram36k_sdp select spram_36x1024_18x2048 select * -synth_quicklogic -family qlf_k6n10f -top spram_36x1024_18x2048 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top spram_36x1024_18x2048 -bram_types opt_expr -undriven opt_clean stat diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sfifo/asymmetric_bram36k_sfifo.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sfifo/asymmetric_bram36k_sfifo.tcl index 4b2447089..a940597f1 100644 --- a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sfifo/asymmetric_bram36k_sfifo.tcl +++ b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sfifo/asymmetric_bram36k_sfifo.tcl @@ -8,7 +8,7 @@ design -save asymmetric_bram36k_sfifo select f4096x9_1024x36 select * -synth_quicklogic -family qlf_k6n10f -top f4096x9_1024x36 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top f4096x9_1024x36 -bram_types opt_expr -undriven opt_clean stat @@ -19,7 +19,7 @@ select -clear design -load asymmetric_bram36k_sfifo select f2048x18_1024x36 select * -synth_quicklogic -family qlf_k6n10f -top f2048x18_1024x36 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top f2048x18_1024x36 -bram_types opt_expr -undriven opt_clean stat @@ -30,7 +30,7 @@ select -clear design -load asymmetric_bram36k_sfifo select f2048x18_4098x9 select * -synth_quicklogic -family qlf_k6n10f -top f2048x18_4098x9 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top f2048x18_4098x9 -bram_types opt_expr -undriven opt_clean stat @@ -41,7 +41,7 @@ select -clear design -load asymmetric_bram36k_sfifo select f1024x36_2048x18 select * -synth_quicklogic -family qlf_k6n10f -top f1024x36_2048x18 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top f1024x36_2048x18 -bram_types opt_expr -undriven opt_clean stat diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_afifo/bram18k_afifo.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_afifo/bram18k_afifo.tcl index 99c7405b6..a9c0f9d14 100644 --- a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_afifo/bram18k_afifo.tcl +++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_afifo/bram18k_afifo.tcl @@ -8,7 +8,7 @@ design -save bram18k_afifo select af1024x18_1024x18 select * -synth_quicklogic -family qlf_k6n10f -top af1024x18_1024x18 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top af1024x18_1024x18 -bram_types opt_expr -undriven opt_clean stat @@ -19,7 +19,7 @@ select -clear design -load bram18k_afifo select af1024x16_1024x16 select * -synth_quicklogic -family qlf_k6n10f -top af1024x16_1024x16 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top af1024x16_1024x16 -bram_types opt_expr -undriven opt_clean stat @@ -30,7 +30,7 @@ select -clear design -load bram18k_afifo select af2048x9_2048x9 select * -synth_quicklogic -family qlf_k6n10f -top af2048x9_2048x9 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top af2048x9_2048x9 -bram_types opt_expr -undriven opt_clean stat @@ -41,7 +41,7 @@ select -clear design -load bram18k_afifo select af2048x8_2048x8 select * -synth_quicklogic -family qlf_k6n10f -top af2048x8_2048x8 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top af2048x8_2048x8 -bram_types opt_expr -undriven opt_clean stat diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sdp/bram18k_sdp.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sdp/bram18k_sdp.tcl index 092d4c226..29db408c2 100644 --- a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sdp/bram18k_sdp.tcl +++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sdp/bram18k_sdp.tcl @@ -8,7 +8,7 @@ design -save bram18k_sdp select spram_18x1024_2x select * -synth_quicklogic -family qlf_k6n10f -top spram_18x1024_2x -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top spram_18x1024_2x -bram_types opt_expr -undriven opt_clean stat @@ -19,7 +19,7 @@ select -clear design -load bram18k_sdp select spram_9x2048_x2 select * -synth_quicklogic -family qlf_k6n10f -top spram_9x2048_x2 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top spram_9x2048_x2 -bram_types opt_expr -undriven opt_clean stat @@ -30,7 +30,7 @@ select -clear design -load bram18k_sdp select spram_9x2048_18x1024 select * -synth_quicklogic -family qlf_k6n10f -top spram_9x2048_18x1024 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top spram_9x2048_18x1024 -bram_types opt_expr -undriven opt_clean stat diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sfifo/bram18k_sfifo.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sfifo/bram18k_sfifo.tcl index a5ff2765d..b08dc3e00 100644 --- a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sfifo/bram18k_sfifo.tcl +++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sfifo/bram18k_sfifo.tcl @@ -8,7 +8,7 @@ design -save bram18k_sfifo select f1024x18_1024x18 select * -synth_quicklogic -family qlf_k6n10f -top f1024x18_1024x18 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top f1024x18_1024x18 -bram_types opt_expr -undriven opt_clean stat @@ -19,7 +19,7 @@ select -clear design -load bram18k_sfifo select f1024x16_1024x16 select * -synth_quicklogic -family qlf_k6n10f -top f1024x16_1024x16 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top f1024x16_1024x16 -bram_types opt_expr -undriven opt_clean stat @@ -30,7 +30,7 @@ select -clear design -load bram18k_sfifo select f2048x9_2048x9 select * -synth_quicklogic -family qlf_k6n10f -top f2048x9_2048x9 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top f2048x9_2048x9 -bram_types opt_expr -undriven opt_clean stat @@ -41,7 +41,7 @@ select -clear design -load bram18k_sfifo select f2048x8_2048x8 select * -synth_quicklogic -family qlf_k6n10f -top f2048x8_2048x8 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top f2048x8_2048x8 -bram_types opt_expr -undriven opt_clean stat diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_tdp/bram18k_tdp.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_tdp/bram18k_tdp.tcl index e42cd1621..5929f532a 100644 --- a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_tdp/bram18k_tdp.tcl +++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_tdp/bram18k_tdp.tcl @@ -8,7 +8,7 @@ design -save bram18k_tdp select dpram_18x1024_x2 select * -synth_quicklogic -family qlf_k6n10f -top dpram_18x1024_x2 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top dpram_18x1024_x2 -bram_types opt_expr -undriven opt_clean stat @@ -19,7 +19,7 @@ select -clear design -load bram18k_tdp select dpram_9x2048_x2 select * -synth_quicklogic -family qlf_k6n10f -top dpram_9x2048_x2 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top dpram_9x2048_x2 -bram_types opt_expr -undriven opt_clean stat @@ -30,7 +30,7 @@ select -clear design -load bram18k_tdp select dpram_18x1024_9x2048 select * -synth_quicklogic -family qlf_k6n10f -top dpram_18x1024_9x2048 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top dpram_18x1024_9x2048 -bram_types opt_expr -undriven opt_clean stat diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_afifo/bram36k_afifo.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_afifo/bram36k_afifo.tcl index dacbe7707..d14ef2d86 100644 --- a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_afifo/bram36k_afifo.tcl +++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_afifo/bram36k_afifo.tcl @@ -8,7 +8,7 @@ design -save bram36k_afifo select af1024x36_1024x36 select * -synth_quicklogic -family qlf_k6n10f -top af1024x36_1024x36 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top af1024x36_1024x36 -bram_types opt_expr -undriven opt_clean stat @@ -19,7 +19,7 @@ select -clear design -load bram36k_afifo select af2048x18_2048x18 select * -synth_quicklogic -family qlf_k6n10f -top af2048x18_2048x18 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top af2048x18_2048x18 -bram_types opt_expr -undriven opt_clean stat @@ -30,7 +30,7 @@ select -clear design -load bram36k_afifo select af4096x9_4096x9 select * -synth_quicklogic -family qlf_k6n10f -top af4096x9_4096x9 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top af4096x9_4096x9 -bram_types opt_expr -undriven opt_clean stat diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sdp/bram36k_sdp.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sdp/bram36k_sdp.tcl index b5d38b017..6b96d9f72 100644 --- a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sdp/bram36k_sdp.tcl +++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sdp/bram36k_sdp.tcl @@ -8,7 +8,7 @@ design -save bram36_sdp select spram_36x1024 select * -synth_quicklogic -family qlf_k6n10f -top spram_36x1024 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top spram_36x1024 -bram_types opt_expr -undriven opt_clean stat @@ -19,7 +19,7 @@ select -clear design -load bram36_sdp select spram_32x1024 select * -synth_quicklogic -family qlf_k6n10f -top spram_32x1024 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top spram_32x1024 -bram_types opt_expr -undriven opt_clean stat @@ -30,7 +30,7 @@ select -clear design -load bram36_sdp select spram_18x2048 select * -synth_quicklogic -family qlf_k6n10f -top spram_18x2048 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top spram_18x2048 -bram_types opt_expr -undriven opt_clean stat @@ -41,7 +41,7 @@ select -clear design -load bram36_sdp select spram_16x2048 select * -synth_quicklogic -family qlf_k6n10f -top spram_16x2048 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top spram_16x2048 -bram_types opt_expr -undriven opt_clean stat @@ -52,7 +52,7 @@ select -clear design -load bram36_sdp select spram_9x4096 select * -synth_quicklogic -family qlf_k6n10f -top spram_9x4096 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top spram_9x4096 -bram_types opt_expr -undriven opt_clean stat @@ -63,7 +63,7 @@ select -clear design -load bram36_sdp select spram_8x4096 select * -synth_quicklogic -family qlf_k6n10f -top spram_8x4096 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top spram_8x4096 -bram_types opt_expr -undriven opt_clean stat diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sfifo/bram36k_sfifo.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sfifo/bram36k_sfifo.tcl index 8ffd95fef..38297f48b 100644 --- a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sfifo/bram36k_sfifo.tcl +++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sfifo/bram36k_sfifo.tcl @@ -8,7 +8,7 @@ design -save bram36k_sfifo select f1024x36_1024x36 select * -synth_quicklogic -family qlf_k6n10f -top f1024x36_1024x36 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top f1024x36_1024x36 -bram_types opt_expr -undriven opt_clean stat @@ -19,7 +19,7 @@ select -clear design -load bram36k_sfifo select f2048x18_2048x18 select * -synth_quicklogic -family qlf_k6n10f -top f2048x18_2048x18 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top f2048x18_2048x18 -bram_types opt_expr -undriven opt_clean stat @@ -30,7 +30,7 @@ select -clear design -load bram36k_sfifo select f4096x9_4096x9 select * -synth_quicklogic -family qlf_k6n10f -top f4096x9_4096x9 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top f4096x9_4096x9 -bram_types opt_expr -undriven opt_clean stat diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_tdp/bram36k_tdp.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_tdp/bram36k_tdp.tcl index df4591e2d..e3d7f2893 100644 --- a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_tdp/bram36k_tdp.tcl +++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_tdp/bram36k_tdp.tcl @@ -8,7 +8,7 @@ design -save bram36k_tdp select dpram_36x1024 select * -synth_quicklogic -family qlf_k6n10f -top dpram_36x1024 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top dpram_36x1024 -bram_types opt_expr -undriven opt_clean stat @@ -19,7 +19,7 @@ select -clear design -load bram36k_tdp select dpram_18x2048 select * -synth_quicklogic -family qlf_k6n10f -top dpram_18x2048 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top dpram_18x2048 -bram_types opt_expr -undriven opt_clean stat @@ -30,7 +30,7 @@ select -clear design -load bram36k_tdp select dpram_9x4096 select * -synth_quicklogic -family qlf_k6n10f -top dpram_9x4096 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top dpram_9x4096 -bram_types opt_expr -undriven opt_clean stat diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram_asymmetric_wider_read/bram_asymmetric_wider_read.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/bram_asymmetric_wider_read/bram_asymmetric_wider_read.tcl index 1ae531aae..29a699310 100644 --- a/ql-qlf-plugin/tests/qlf_k6n10f/bram_asymmetric_wider_read/bram_asymmetric_wider_read.tcl +++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram_asymmetric_wider_read/bram_asymmetric_wider_read.tcl @@ -8,7 +8,7 @@ design -save bram_tdp select spram_16x2048_32x1024 select * -synth_quicklogic -family qlf_k6n10f -top spram_16x2048_32x1024 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top spram_16x2048_32x1024 -bram_types opt_expr -undriven opt_clean stat @@ -20,7 +20,7 @@ select -clear design -load bram_tdp select spram_8x4096_16x2048 select * -synth_quicklogic -family qlf_k6n10f -top spram_8x4096_16x2048 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top spram_8x4096_16x2048 -bram_types opt_expr -undriven opt_clean stat @@ -32,7 +32,7 @@ select -clear design -load bram_tdp select spram_8x2048_16x1024 select * -synth_quicklogic -family qlf_k6n10f -top spram_8x2048_16x1024 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top spram_8x2048_16x1024 -bram_types opt_expr -undriven opt_clean stat @@ -44,7 +44,7 @@ select -clear design -load bram_tdp select spram_8x4096_32x1024 select * -synth_quicklogic -family qlf_k6n10f -top spram_8x4096_32x1024 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top spram_8x4096_32x1024 -bram_types opt_expr -undriven opt_clean stat diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram_asymmetric_wider_write/bram_asymmetric_wider_write.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/bram_asymmetric_wider_write/bram_asymmetric_wider_write.tcl index 254c2ea9c..bf21591c6 100644 --- a/ql-qlf-plugin/tests/qlf_k6n10f/bram_asymmetric_wider_write/bram_asymmetric_wider_write.tcl +++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram_asymmetric_wider_write/bram_asymmetric_wider_write.tcl @@ -8,7 +8,7 @@ design -save bram_tdp select spram_16x1024_8x2048 select * -synth_quicklogic -family qlf_k6n10f -top spram_16x1024_8x2048 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top spram_16x1024_8x2048 -bram_types opt_expr -undriven opt_clean stat @@ -20,7 +20,7 @@ select -clear design -load bram_tdp select spram_16x2048_8x4096 select * -synth_quicklogic -family qlf_k6n10f -top spram_16x2048_8x4096 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top spram_16x2048_8x4096 -bram_types opt_expr -undriven opt_clean stat @@ -32,7 +32,7 @@ select -clear design -load bram_tdp select spram_32x1024_16x2048 select * -synth_quicklogic -family qlf_k6n10f -top spram_32x1024_16x2048 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top spram_32x1024_16x2048 -bram_types opt_expr -undriven opt_clean stat @@ -44,7 +44,7 @@ select -clear design -load bram_tdp select spram_32x1024_8x4096 select * -synth_quicklogic -family qlf_k6n10f -top spram_32x1024_8x4096 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top spram_32x1024_8x4096 -bram_types opt_expr -undriven opt_clean stat diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp/bram_sdp.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp/bram_sdp.tcl index 4e985854f..f5f3d16e7 100644 --- a/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp/bram_sdp.tcl +++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp/bram_sdp.tcl @@ -8,7 +8,7 @@ design -save bram_sdp select BRAM_SDP_36x1024 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_36x1024 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top BRAM_SDP_36x1024 -bram_types opt_expr -undriven opt_clean stat @@ -19,7 +19,7 @@ select -clear design -load bram_sdp select BRAM_SDP_32x1024 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_32x1024 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top BRAM_SDP_32x1024 -bram_types opt_expr -undriven opt_clean stat @@ -30,7 +30,7 @@ select -clear design -load bram_sdp select BRAM_SDP_18x2048 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_18x2048 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top BRAM_SDP_18x2048 -bram_types opt_expr -undriven opt_clean stat @@ -41,7 +41,7 @@ select -clear design -load bram_sdp select BRAM_SDP_16x2048 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_16x2048 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top BRAM_SDP_16x2048 -bram_types opt_expr -undriven opt_clean stat @@ -52,7 +52,7 @@ select -clear design -load bram_sdp select BRAM_SDP_9x4096 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_9x4096 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top BRAM_SDP_9x4096 -bram_types opt_expr -undriven opt_clean stat @@ -63,7 +63,7 @@ select -clear design -load bram_sdp select BRAM_SDP_8x4096 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_8x4096 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top BRAM_SDP_8x4096 -bram_types opt_expr -undriven opt_clean stat @@ -74,7 +74,7 @@ select -clear design -load bram_sdp select BRAM_SDP_4x8192 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_4x8192 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top BRAM_SDP_4x8192 -bram_types opt_expr -undriven opt_clean stat @@ -85,7 +85,7 @@ select -clear design -load bram_sdp select BRAM_SDP_2x16384 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_2x16384 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top BRAM_SDP_2x16384 -bram_types opt_expr -undriven opt_clean stat @@ -96,7 +96,7 @@ select -clear design -load bram_sdp select BRAM_SDP_1x32768 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_1x32768 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top BRAM_SDP_1x32768 -bram_types opt_expr -undriven opt_clean stat diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp_split/bram_sdp_split.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp_split/bram_sdp_split.tcl index fcf9acdff..bf9d0da6b 100644 --- a/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp_split/bram_sdp_split.tcl +++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp_split/bram_sdp_split.tcl @@ -8,7 +8,7 @@ design -save bram_sdp_split select BRAM_SDP_SPLIT_2x18x1024 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x18x1024 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x18x1024 -bram_types opt_expr -undriven opt_clean stat @@ -19,7 +19,7 @@ select -clear design -load bram_sdp_split select BRAM_SDP_SPLIT_2x16x1024 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x16x1024 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x16x1024 -bram_types opt_expr -undriven opt_clean stat @@ -30,7 +30,7 @@ select -clear design -load bram_sdp_split select BRAM_SDP_SPLIT_2x9x2048 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x9x2048 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x9x2048 -bram_types opt_expr -undriven opt_clean stat @@ -41,7 +41,7 @@ select -clear design -load bram_sdp_split select BRAM_SDP_SPLIT_2x8x2048 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x8x2048 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x8x2048 -bram_types opt_expr -undriven opt_clean stat @@ -52,7 +52,7 @@ select -clear design -load bram_sdp_split select BRAM_SDP_SPLIT_2x4x4096 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x4x4096 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x4x4096 -bram_types opt_expr -undriven opt_clean stat @@ -63,7 +63,7 @@ select -clear design -load bram_sdp_split select BRAM_SDP_SPLIT_2x2x8192 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x2x8192 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x2x8192 -bram_types opt_expr -undriven opt_clean stat @@ -74,7 +74,7 @@ select -clear design -load bram_sdp_split select BRAM_SDP_SPLIT_2x1x16384 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x1x16384 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top BRAM_SDP_SPLIT_2x1x16384 -bram_types opt_expr -undriven opt_clean stat diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram_tdp/bram_tdp.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/bram_tdp/bram_tdp.tcl index ea5ae8e21..28d4e692d 100644 --- a/ql-qlf-plugin/tests/qlf_k6n10f/bram_tdp/bram_tdp.tcl +++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram_tdp/bram_tdp.tcl @@ -8,7 +8,7 @@ design -save bram_tdp select BRAM_TDP_36x1024 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_36x1024 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top BRAM_TDP_36x1024 -bram_types opt_expr -undriven opt_clean stat @@ -19,7 +19,7 @@ select -clear design -load bram_tdp select BRAM_TDP_32x1024 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_32x1024 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top BRAM_TDP_32x1024 -bram_types opt_expr -undriven opt_clean stat @@ -30,7 +30,7 @@ select -clear design -load bram_tdp select BRAM_TDP_18x2048 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_18x2048 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top BRAM_TDP_18x2048 -bram_types opt_expr -undriven opt_clean stat @@ -41,7 +41,7 @@ select -clear design -load bram_tdp select BRAM_TDP_16x2048 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_16x2048 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top BRAM_TDP_16x2048 -bram_types opt_expr -undriven opt_clean stat @@ -52,7 +52,7 @@ select -clear design -load bram_tdp select BRAM_TDP_9x4096 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_9x4096 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top BRAM_TDP_9x4096 -bram_types opt_expr -undriven opt_clean stat @@ -63,7 +63,7 @@ select -clear design -load bram_tdp select BRAM_TDP_8x4096 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_8x4096 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top BRAM_TDP_8x4096 -bram_types opt_expr -undriven opt_clean stat @@ -74,7 +74,7 @@ select -clear design -load bram_tdp select BRAM_TDP_4x8192 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_4x8192 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top BRAM_TDP_4x8192 -bram_types opt_expr -undriven opt_clean stat @@ -85,7 +85,7 @@ select -clear design -load bram_tdp select BRAM_TDP_2x16384 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_2x16384 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top BRAM_TDP_2x16384 -bram_types opt_expr -undriven opt_clean stat @@ -96,7 +96,7 @@ select -clear design -load bram_tdp select BRAM_TDP_1x32768 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_1x32768 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top BRAM_TDP_1x32768 -bram_types opt_expr -undriven opt_clean stat diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram_tdp_split/bram_tdp_split.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/bram_tdp_split/bram_tdp_split.tcl index 7b56e8dc9..442c7d8b3 100644 --- a/ql-qlf-plugin/tests/qlf_k6n10f/bram_tdp_split/bram_tdp_split.tcl +++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram_tdp_split/bram_tdp_split.tcl @@ -8,7 +8,7 @@ design -save bram_tdp_split select BRAM_TDP_SPLIT_2x18x1024 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x18x1024 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x18x1024 -bram_types opt_expr -undriven opt_clean stat @@ -19,7 +19,7 @@ select -clear design -load bram_tdp_split select BRAM_TDP_SPLIT_2x16x1024 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x16x1024 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x16x1024 -bram_types opt_expr -undriven opt_clean stat @@ -30,7 +30,7 @@ select -clear design -load bram_tdp_split select BRAM_TDP_SPLIT_2x9x2048 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x9x2048 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x9x2048 -bram_types opt_expr -undriven opt_clean stat @@ -41,7 +41,7 @@ select -clear design -load bram_tdp_split select BRAM_TDP_SPLIT_2x8x2048 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x8x2048 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x8x2048 -bram_types opt_expr -undriven opt_clean stat @@ -52,7 +52,7 @@ select -clear design -load bram_tdp_split select BRAM_TDP_SPLIT_2x4x4096 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x4x4096 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x4x4096 -bram_types opt_expr -undriven opt_clean stat @@ -63,7 +63,7 @@ select -clear design -load bram_tdp_split select BRAM_TDP_SPLIT_2x2x8192 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x2x8192 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x2x8192 -bram_types opt_expr -undriven opt_clean stat @@ -74,7 +74,7 @@ select -clear design -load bram_tdp_split select BRAM_TDP_SPLIT_2x1x16384 select * -synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x1x16384 -bram_types +synth_quicklogic_f4pga -family qlf_k6n10f -top BRAM_TDP_SPLIT_2x1x16384 -bram_types opt_expr -undriven opt_clean stat diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/dsp_macc/dsp_macc.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/dsp_macc/dsp_macc.tcl index 377689af2..c5adda028 100644 --- a/ql-qlf-plugin/tests/qlf_k6n10f/dsp_macc/dsp_macc.tcl +++ b/ql-qlf-plugin/tests/qlf_k6n10f/dsp_macc/dsp_macc.tcl @@ -7,10 +7,10 @@ proc check_equiv {top use_cfg_params} { design -save preopt if {${use_cfg_params} == 1} { - synth_quicklogic -family qlf_k6n10f -top ${top} -use_dsp_cfg_params + synth_quicklogic_f4pga -family qlf_k6n10f -top ${top} -use_dsp_cfg_params } else { stat - synth_quicklogic -family qlf_k6n10f -top ${top} + synth_quicklogic_f4pga -family qlf_k6n10f -top ${top} } design -stash postopt @@ -18,8 +18,8 @@ proc check_equiv {top use_cfg_params} { design -copy-from preopt -as gold A:top design -copy-from postopt -as gate A:top - techmap -wb -autoproc -map +/quicklogic/qlf_k6n10f/cells_sim.v - techmap -wb -autoproc -map +/quicklogic/qlf_k6n10f/dsp_sim.v + techmap -wb -autoproc -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v + techmap -wb -autoproc -map +/quicklogic_f4pga/qlf_k6n10f/dsp_sim.v yosys proc opt_expr opt_clean -purge diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/dsp_madd/dsp_madd.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/dsp_madd/dsp_madd.tcl index eeefa6061..c910dfb33 100644 --- a/ql-qlf-plugin/tests/qlf_k6n10f/dsp_madd/dsp_madd.tcl +++ b/ql-qlf-plugin/tests/qlf_k6n10f/dsp_madd/dsp_madd.tcl @@ -7,10 +7,10 @@ proc check_equiv {top use_cfg_params} { design -save preopt if {${use_cfg_params} == 1} { - synth_quicklogic -family qlf_k6n10f -top ${top} -use_dsp_cfg_params + synth_quicklogic_f4pga -family qlf_k6n10f -top ${top} -use_dsp_cfg_params } else { stat - synth_quicklogic -family qlf_k6n10f -top ${top} + synth_quicklogic_f4pga -family qlf_k6n10f -top ${top} } design -stash postopt @@ -18,8 +18,8 @@ proc check_equiv {top use_cfg_params} { design -copy-from preopt -as gold A:top design -copy-from postopt -as gate A:top - techmap -wb -autoproc -map +/quicklogic/qlf_k6n10f/cells_sim.v - techmap -wb -autoproc -map +/quicklogic/qlf_k6n10f/dsp_sim.v + techmap -wb -autoproc -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v + techmap -wb -autoproc -map +/quicklogic_f4pga/qlf_k6n10f/dsp_sim.v yosys proc opt_expr opt_clean -purge diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/dsp_mult/dsp_mult.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/dsp_mult/dsp_mult.tcl index aea70766f..29829fddb 100644 --- a/ql-qlf-plugin/tests/qlf_k6n10f/dsp_mult/dsp_mult.tcl +++ b/ql-qlf-plugin/tests/qlf_k6n10f/dsp_mult/dsp_mult.tcl @@ -7,10 +7,10 @@ proc check_equiv {top use_cfg_params} { design -save preopt if {${use_cfg_params} == 1} { - synth_quicklogic -family qlf_k6n10f -top ${top} -use_dsp_cfg_params + synth_quicklogic_f4pga -family qlf_k6n10f -top ${top} -use_dsp_cfg_params } else { stat - synth_quicklogic -family qlf_k6n10f -top ${top} + synth_quicklogic_f4pga -family qlf_k6n10f -top ${top} } design -stash postopt @@ -18,8 +18,8 @@ proc check_equiv {top use_cfg_params} { design -copy-from preopt -as gold A:top design -copy-from postopt -as gate A:top - techmap -wb -autoproc -map +/quicklogic/qlf_k6n10f/cells_sim.v - techmap -wb -autoproc -map +/quicklogic/qlf_k6n10f/dsp_sim.v + techmap -wb -autoproc -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v + techmap -wb -autoproc -map +/quicklogic_f4pga/qlf_k6n10f/dsp_sim.v yosys proc opt_expr opt_clean -purge diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/dsp_mult_post_synth_sim/dsp_mult_post_synth_sim.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/dsp_mult_post_synth_sim/dsp_mult_post_synth_sim.tcl index 8ef551f17..3845be225 100644 --- a/ql-qlf-plugin/tests/qlf_k6n10f/dsp_mult_post_synth_sim/dsp_mult_post_synth_sim.tcl +++ b/ql-qlf-plugin/tests/qlf_k6n10f/dsp_mult_post_synth_sim/dsp_mult_post_synth_sim.tcl @@ -8,7 +8,7 @@ design -save dsp_mult_post_synth_sim select dsp_mult select * -synth_quicklogic -family qlf_k6n10f -top dsp_mult +synth_quicklogic_f4pga -family qlf_k6n10f -top dsp_mult opt_expr -undriven opt_clean stat @@ -19,7 +19,7 @@ select -clear design -load dsp_mult_post_synth_sim select dsp_mult select * -synth_quicklogic -family qlf_k6n10f -top dsp_mult -use_dsp_cfg_params +synth_quicklogic_f4pga -family qlf_k6n10f -top dsp_mult -use_dsp_cfg_params opt_expr -undriven opt_clean stat diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd/dsp_simd.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd/dsp_simd.tcl index 5f65729fc..5afbe16c4 100644 --- a/ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd/dsp_simd.tcl +++ b/ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd/dsp_simd.tcl @@ -7,10 +7,10 @@ proc check_equiv {top use_cfg_params} { design -save preopt if {${use_cfg_params} == 1} { - synth_quicklogic -family qlf_k6n10f -top ${top} -use_dsp_cfg_params + synth_quicklogic_f4pga -family qlf_k6n10f -top ${top} -use_dsp_cfg_params } else { stat - synth_quicklogic -family qlf_k6n10f -top ${top} + synth_quicklogic_f4pga -family qlf_k6n10f -top ${top} } design -stash postopt @@ -18,8 +18,8 @@ proc check_equiv {top use_cfg_params} { design -copy-from preopt -as gold A:top design -copy-from postopt -as gate A:top - techmap -wb -autoproc -map +/quicklogic/qlf_k6n10f/cells_sim.v - techmap -wb -autoproc -map +/quicklogic/qlf_k6n10f/dsp_sim.v + techmap -wb -autoproc -map +/quicklogic_f4pga/qlf_k6n10f/cells_sim.v + techmap -wb -autoproc -map +/quicklogic_f4pga/qlf_k6n10f/dsp_sim.v yosys proc opt_expr opt_clean diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd_post_synth_sim/dsp_simd_post_synth_sim.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd_post_synth_sim/dsp_simd_post_synth_sim.tcl index 5fbc441b5..0af977861 100644 --- a/ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd_post_synth_sim/dsp_simd_post_synth_sim.tcl +++ b/ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd_post_synth_sim/dsp_simd_post_synth_sim.tcl @@ -8,7 +8,7 @@ design -save dsp_simd select simd_mult select * -synth_quicklogic -family qlf_k6n10f -top simd_mult +synth_quicklogic_f4pga -family qlf_k6n10f -top simd_mult opt_expr -undriven opt_clean stat @@ -19,7 +19,7 @@ select -clear design -load dsp_simd select simd_mult_explicit_ports select * -synth_quicklogic -family qlf_k6n10f -top simd_mult_explicit_ports +synth_quicklogic_f4pga -family qlf_k6n10f -top simd_mult_explicit_ports opt_expr -undriven opt_clean stat @@ -30,7 +30,7 @@ select -clear design -load dsp_simd select simd_mult_explicit_params select * -synth_quicklogic -family qlf_k6n10f -top simd_mult_explicit_params -use_dsp_cfg_params +synth_quicklogic_f4pga -family qlf_k6n10f -top simd_mult_explicit_params -use_dsp_cfg_params opt_expr -undriven opt_clean stat diff --git a/ql-qlf-plugin/tests/shreg/shreg.tcl b/ql-qlf-plugin/tests/shreg/shreg.tcl index fe4b6333d..8830d2b5b 100644 --- a/ql-qlf-plugin/tests/shreg/shreg.tcl +++ b/ql-qlf-plugin/tests/shreg/shreg.tcl @@ -3,14 +3,14 @@ if { [info procs quicklogic_eqn] == {} } { plugin -i ql-qlf } yosys -import ;# ingest plugin commands read_verilog $::env(DESIGN_TOP).v -synth_quicklogic -family qlf_k4n8 -top top +synth_quicklogic_f4pga -family qlf_k4n8 -top top stat select -assert-count 8 t:sh_dff design -reset read_verilog $::env(DESIGN_TOP).v -synth_quicklogic -family qlf_k6n10f -top top +synth_quicklogic_f4pga -family qlf_k6n10f -top top stat select -assert-count 8 t:sh_dff diff --git a/ql-qlf-plugin/tests/tribuf/tribuf.tcl b/ql-qlf-plugin/tests/tribuf/tribuf.tcl index 0d759b5c0..278b258e8 100644 --- a/ql-qlf-plugin/tests/tribuf/tribuf.tcl +++ b/ql-qlf-plugin/tests/tribuf/tribuf.tcl @@ -9,7 +9,7 @@ yosys proc tribuf flatten synth -equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/simcells.v synth_quicklogic -family pp3 +equiv_opt -assert -map +/quicklogic_f4pga/pp3/cells_sim.v -map +/simcells.v synth_quicklogic_f4pga -family pp3 design -load postopt yosys cd tristate select -assert-count 2 t:inpad diff --git a/requirements.txt b/requirements.txt deleted file mode 100644 index e69de29bb..000000000 diff --git a/third_party/googletest b/third_party/googletest deleted file mode 160000 index e2239ee60..000000000 --- a/third_party/googletest +++ /dev/null @@ -1 +0,0 @@ -Subproject commit e2239ee6043f73722e7aa812a459f54a28552929 diff --git a/third_party/make-env b/third_party/make-env deleted file mode 160000 index 33b80bd32..000000000 --- a/third_party/make-env +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 33b80bd32c30fb8affd0fd5cda544d1bca075593 diff --git a/xdc-plugin/Makefile b/xdc-plugin/Makefile index b2ebd883b..25635efc0 100644 --- a/xdc-plugin/Makefile +++ b/xdc-plugin/Makefile @@ -22,6 +22,7 @@ include ../Makefile_plugin.common VERILOG_MODULES = BANK.v install_modules: $(VERILOG_MODULES) - install -D $< $(YOSYS_PLUGINS_DIR)/fasm_extra_modules/$< + mkdir -p $(YOSYS_PLUGINS_DIR)/fasm_extra_modules/ + install $< $(YOSYS_PLUGINS_DIR)/fasm_extra_modules/$< install: install_modules diff --git a/xdc-plugin/tests/minilitex_ddr_arty/minilitex_ddr_arty.tcl b/xdc-plugin/tests/minilitex_ddr_arty/minilitex_ddr_arty.tcl index df2555c13..046b34ece 100644 --- a/xdc-plugin/tests/minilitex_ddr_arty/minilitex_ddr_arty.tcl +++ b/xdc-plugin/tests/minilitex_ddr_arty/minilitex_ddr_arty.tcl @@ -7,6 +7,7 @@ read_verilog $::env(DESIGN_TOP).v read_verilog [file dirname [info script]]/VexRiscv_Lite.v # -flatten is used to ensure that the output eblif has only one module. # Some of F4PGA expects eblifs with only one module. + synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp #Read the design constraints diff --git a/xdc-plugin/xdc.cc b/xdc-plugin/xdc.cc index 9a6602956..ee6b140ac 100644 --- a/xdc-plugin/xdc.cc +++ b/xdc-plugin/xdc.cc @@ -30,7 +30,6 @@ #include "kernel/log.h" #include "kernel/register.h" #include "kernel/rtlil.h" -#include "libs/json11/json11.hpp" #include USING_YOSYS_NAMESPACE