Synplify Flow Integration #553
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memory libmap support
added wire definition in cell_sim.v file to avoid compilation errors
…from cells_sim.v file
modified lipmap brams txt to fix the ram inferring due to initialization
RAM inferring fix - reduced cost
rectified the model for FFs with set
…es the abc9 examples failures
ram initialization support and split libmap_brams_map.v file to tdp and sdp versions.
temporary fix for assertion failure with DSP packing
… timing annotation
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This branch changed the synth_ql pass in order to support the Synplify Post-map Flow.