Code

Synplify Flow Integration#553

Code

Closed

navidjafarof wants to merge 39 commits intochipsalliance:mainchipsalliance/yosys-f4pga-plugins:mainfrom QuickLogic-Corp:synplify-integrationQuickLogic-Corp/yosys-f4pga-plugins:synplify-integrationCopy head branch name to clipboard

+93,357-23,892

Commits

Commits on Feb 18, 2023

• enable abc9 for k6n10

  tpagarani

  committed
  408d7af

Commits on May 8, 2023

• qlf_k6n10f/cells_sim.v

  

  Tarachand Pagarani

  committed
  c72a4fc

• add correct delays

  

  Tarachand Pagarani

  committed
  c87c6f3

Commits on May 16, 2023

• fix carry chain issue

  

  Tarachand Pagarani

  committed
  bcaf51a

Commits on May 18, 2023

• add carry attribute to keep carry chain

  

  Tarachand Pagarani

  committed
  f7bd1e6

Commits on Jun 1, 2023

• fix crash issues

  

  Tarachand Pagarani

  committed
  5669bd7

Commits on Jun 10, 2023

• Merge branch 'main' into abc9

  coolbreeze413

  committed
  b411f22

Commits on Jun 14, 2023

• memory libmap support, modified instantiation macros

  rakeshm75

  committed
  74dd252

Commits on Jun 19, 2023

• modified bram map, bram final map amd synth_quicklogic files

  rakeshm75

  committed
  955074d

• Merge pull request #3 from QuickLogic-Corp/memory_libmap

  Show description for a5c00a3
  rakeshm75

  authored
  a5c00a3

Commits on Jun 29, 2023

• added wire definition in cell_sim.v file to avoid compilation errors

  rakeshm75

  committed
  57b26d8

• Merge pull request #4 from QuickLogic-Corp/cell_sim

  Show description for 98ea3c2
  coolbreeze413

  authored
  98ea3c2

Commits on Jul 17, 2023

• modified lipmap brams txt to change the init & removed the frac_lut6 from cells_sim.v file

  rakeshm75

  committed
  a8914e1

Commits on Jul 19, 2023

• Add generated files(pmgen.py, bram_types_sim.v) to gitignore

  coolbreeze413

  committed
  7482ed9

Commits on Jul 20, 2023

• Merge pull request #5 from QuickLogic-Corp/bram_init

  Show description for e97f8b3
  rakeshm75

  authored
  e97f8b3

• ram cost reduced to 65 from 257 in libmap_brams.txt

  rakeshm75

  committed
  93bfca7

• Merge pull request #6 from QuickLogic-Corp/memory_libmap_fix

  Show description for 18aba5f
  rakeshm75

  authored
  18aba5f

Commits on Sep 12, 2023

• add no_opt support

  

  Tarachand Pagarani

  committed
  774485b

• Minor formatting changes in synth_quicklogic.cc

  coolbreeze413

  committed
  5548780

Commits on Feb 12, 2024

• added support for multiple architectures

  rakeshm75

  committed
  befbcd1

Commits on Feb 19, 2024

• added the updated cell_sim.v file

  rakeshm75

  committed
  bc017e7

Commits on Feb 20, 2024

• updated the DSP map file to avoid x on the inputs reset and clock

  rakeshm75

  committed
  7efcbcf

Commits on Feb 28, 2024

• reverted the cells_sim.v, lipmap_brams_map.v to the default tsmc device target

  rakeshm75

  committed
  d731711

Commits on Mar 22, 2024

• rectified the model for FFs with set

  rakeshm75

  committed
  df029b0

• Merge pull request #13 from QuickLogic-Corp/rakesh_dev

  Show description for 2b9146c
  rakeshm75

  authored
  2b9146c

Commits on Mar 28, 2024

• added lut6 behavior into cells_sim to pass synth stage

  saaramahmoudi

  committed
  5977bbd

Commits on May 10, 2024

• Merge branch 'main' into support_blackbox_lut

  coolbreeze413

  committed
  362539d

Commits on May 14, 2024

• delays for abc9_box was missing for LUT6 blackbox modules, which causes the abc9 examples failures

  saaramahmoudi

  committed
  9fdedd2

Commits on May 22, 2024

• ram initialization support

  rakeshm75

  committed
  92865b1

Commits on May 23, 2024

• Merge pull request #16 from QuickLogic-Corp/ram_init

  Show description for f612a08
  coolbreeze413

  authored
  f612a08

• rectified sram1024x18.v construct

  rakeshm75

  committed
  74b9d75

Commits on May 31, 2024

• changed the shifter register primitive name

  rakeshm75

  committed
  bd1d16e

Commits on Aug 13, 2024

• temporary fix for assertion failure with DSP packing

  rakeshm75

  committed
  ed85bca

• Merge pull request #19 from QuickLogic-Corp/dsp_packing_fix

  Show description for a49ba3e
  rakeshm75

  authored
  a49ba3e

Commits on Aug 27, 2024

• modified the RAM Map with respect to addr2, wen2, ren2 for the proper timing annotation

  rakeshm75

  committed
  ddefc65

• fix the brams_sim.v file compilation issue

  rakeshm75

  committed
  823d3ef

Commits on Oct 7, 2024

• Changed pass, added the synplify map file, and edited makefile

  

  Navid Jafarof

  committed
  fd3faa4

Commits on Oct 18, 2024

• Removed the Synplify flag foor DSP

  

  Navid Jafarof

  committed
  65ce689

Commits on Oct 19, 2024

• formatting issue resolved

  

  Navid Jafarof

  committed
  c4a8e65