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i8080.cpp
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i8080.cpp
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/**
i8080.cpp - Intel 8080 (KR580VM80A) microprocessor core model
Copyright (C) 2012 Alexander Demin <[email protected]>
Credits
Viacheslav Slavinsky, Vector-06C FPGA Replica
http://code.google.com/p/vector06cc/
Dmitry Tselikov, Bashrikia-2M and Radio-86RK on Altera DE1
http://bashkiria-2m.narod.ru/fpga.html
Ian Bartholomew, 8080/8085 CPU Exerciser
http://www.idb.me.uk/sunhillow/8080.html
Frank Cringle, The origianal exerciser for the Z80.
Thanks to zx.pk.ru and nedopc.org/forum communities.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include "i8080.h"
#define RD_BYTE(addr) read_byte(addr)
#define RD_WORD(addr) read_word(addr)
#define WR_BYTE(addr, value) write_byte(addr, value)
#define WR_WORD(addr, value) write_word(addr, value)
#define FLAGS regs.f
#define AF regs.af.w
#define BC regs.bc.w
#define DE regs.de.w
#define HL regs.hl.w
#define SP regs.sp.w
#define PC regs.pc.w
#define A regs.af.b.h
#define F regs.af.b.l
#define B regs.bc.b.h
#define C regs.bc.b.l
#define D regs.de.b.h
#define E regs.de.b.l
#define H regs.hl.b.h
#define L regs.hl.b.l
#define HSP regs.sp.b.h
#define LSP regs.sp.b.l
#define HPC regs.pc.b.h
#define LPC regs.pc.b.l
#define IFF regs.iff
#define F_CARRY 0x01
#define F_UN1 0x02
#define F_PARITY 0x04
#define F_UN3 0x08
#define F_HCARRY 0x10
#define F_UN5 0x20
#define F_ZERO 0x40
#define F_NEG 0x80
#define C_FLAG FLAGS.carry_flag
#define P_FLAG FLAGS.parity_flag
#define H_FLAG FLAGS.half_carry_flag
#define Z_FLAG FLAGS.zero_flag
#define S_FLAG FLAGS.sign_flag
#define UN1_FLAG FLAGS.unused1
#define UN3_FLAG FLAGS.unused3
#define UN5_FLAG FLAGS.unused5
#define SET(flag) (flag = 1)
#define CLR(flag) (flag = 0)
#define TST(flag) (flag)
#define CPL(flag) (flag = !flag)
#define POP(reg) { (reg) = RD_WORD(SP); SP += 2; }
#define PUSH(reg) { SP -= 2; WR_WORD(SP, (reg)); }
#define RET() { POP(PC); }
#define STC() { SET(C_FLAG); }
#define CMC() { CPL(C_FLAG); }
#define INR(reg) { \
++(reg); \
S_FLAG = (((reg) & 0x80) != 0); \
Z_FLAG = ((reg) == 0); \
H_FLAG = (((reg) & 0x0f) == 0); \
P_FLAG = PARITY(reg); \
}
#define DCR(reg) { \
--(reg); \
S_FLAG = (((reg) & 0x80) != 0); \
Z_FLAG = ((reg) == 0); \
H_FLAG = !(((reg) & 0x0f) == 0x0f); \
P_FLAG = PARITY(reg); \
}
#define ADD(val) { \
work16 = (uns16)A + (val); \
index = ((A & 0x88) >> 1) | \
(((val) & 0x88) >> 2) | \
((work16 & 0x88) >> 3); \
A = work16 & 0xff; \
S_FLAG = ((A & 0x80) != 0); \
Z_FLAG = (A == 0); \
H_FLAG = half_carry_table[index & 0x7]; \
P_FLAG = PARITY(A); \
C_FLAG = ((work16 & 0x0100) != 0); \
}
#define ADC(val) { \
work16 = (uns16)A + (val) + C_FLAG; \
index = ((A & 0x88) >> 1) | \
(((val) & 0x88) >> 2) | \
((work16 & 0x88) >> 3); \
A = work16 & 0xff; \
S_FLAG = ((A & 0x80) != 0); \
Z_FLAG = (A == 0); \
H_FLAG = half_carry_table[index & 0x7]; \
P_FLAG = PARITY(A); \
C_FLAG = ((work16 & 0x0100) != 0); \
}
#define SUB(val) { \
work16 = (uns16)A - (val); \
index = ((A & 0x88) >> 1) | \
(((val) & 0x88) >> 2) | \
((work16 & 0x88) >> 3); \
A = work16 & 0xff; \
S_FLAG = ((A & 0x80) != 0); \
Z_FLAG = (A == 0); \
H_FLAG = !sub_half_carry_table[index & 0x7]; \
P_FLAG = PARITY(A); \
C_FLAG = ((work16 & 0x0100) != 0); \
}
#define SBB(val) { \
work16 = (uns16)A - (val) - C_FLAG; \
index = ((A & 0x88) >> 1) | \
(((val) & 0x88) >> 2) | \
((work16 & 0x88) >> 3); \
A = work16 & 0xff; \
S_FLAG = ((A & 0x80) != 0); \
Z_FLAG = (A == 0); \
H_FLAG = !sub_half_carry_table[index & 0x7]; \
P_FLAG = PARITY(A); \
C_FLAG = ((work16 & 0x0100) != 0); \
}
#define CMP(val) { \
work16 = (uns16)A - (val); \
index = ((A & 0x88) >> 1) | \
(((val) & 0x88) >> 2) | \
((work16 & 0x88) >> 3); \
S_FLAG = ((work16 & 0x80) != 0); \
Z_FLAG = ((work16 & 0xff) == 0); \
H_FLAG = !sub_half_carry_table[index & 0x7]; \
C_FLAG = ((work16 & 0x0100) != 0); \
P_FLAG = PARITY(work16 & 0xff); \
}
#define ANA(val) { \
H_FLAG = ((A | val) & 0x08) != 0; \
A &= (val); \
S_FLAG = ((A & 0x80) != 0); \
Z_FLAG = (A == 0); \
P_FLAG = PARITY(A); \
CLR(C_FLAG); \
}
#define XRA(val) { \
A ^= (val); \
S_FLAG = ((A & 0x80) != 0); \
Z_FLAG = (A == 0); \
CLR(H_FLAG); \
P_FLAG = PARITY(A); \
CLR(C_FLAG); \
}
#define ORA(val) { \
A |= (val); \
S_FLAG = ((A & 0x80) != 0); \
Z_FLAG = (A == 0); \
CLR(H_FLAG); \
P_FLAG = PARITY(A); \
CLR(C_FLAG); \
}
#define DAD(reg) { \
work32 = (uns32)HL + (reg); \
HL = work32 & 0xffff; \
C_FLAG = ((work32 & 0x10000L) != 0); \
}
#define CALL { \
PUSH(PC + 2); \
PC = RD_WORD(PC); \
}
#define RST(addr) { \
PUSH(PC); \
PC = (addr); \
}
#define PARITY(reg) getParity(reg)
//int parity_table[] = {
// 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
// 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
// 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
// 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
// 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
// 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
// 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
// 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
// 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
// 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
// 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
// 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
// 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
// 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
// 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
// 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
//};
int getParity(int val) {
val ^= val >> 4;
val &= 0xf;
return !((0x6996 >> val) & 1);
}
int half_carry_table[] = { 0, 0, 1, 0, 1, 0, 1, 1 };
int sub_half_carry_table[] = { 0, 1, 1, 1, 0, 0, 0, 1 };
I8080::I8080() {
}
I8080::~I8080() {
}
void I8080::init(void) {
C_FLAG = 0;
S_FLAG = 0;
Z_FLAG = 0;
H_FLAG = 0;
P_FLAG = 0;
UN1_FLAG = 1;
UN3_FLAG = 0;
UN5_FLAG = 0;
PC = 0xF800;
}
void I8080::store_flags(void) {
if (S_FLAG) F |= F_NEG; else F &= ~F_NEG;
if (Z_FLAG) F |= F_ZERO; else F &= ~F_ZERO;
if (H_FLAG) F |= F_HCARRY; else F &= ~F_HCARRY;
if (P_FLAG) F |= F_PARITY; else F &= ~F_PARITY;
if (C_FLAG) F |= F_CARRY; else F &= ~F_CARRY;
F |= F_UN1; // UN1_FLAG is always 1.
F &= ~F_UN3; // UN3_FLAG is always 0.
F &= ~F_UN5; // UN5_FLAG is always 0.
}
void I8080::retrieve_flags(void) {
S_FLAG = F & F_NEG ? 1 : 0;
Z_FLAG = F & F_ZERO ? 1 : 0;
H_FLAG = F & F_HCARRY ? 1 : 0;
P_FLAG = F & F_PARITY ? 1 : 0;
C_FLAG = F & F_CARRY ? 1 : 0;
}
int I8080::execute(int opcode) {
int cycles;
this->opcode = opcode;
switch (opcode) {
case 0x00: /* nop */
// Undocumented NOP.
case 0x08: /* nop */
case 0x10: /* nop */
case 0x18: /* nop */
case 0x20: /* nop */
case 0x28: /* nop */
case 0x30: /* nop */
case 0x38: /* nop */
cycles = 4;
break;
case 0x01: /* lxi b, data16 */
cycles = 10;
BC = RD_WORD(PC);
PC += 2;
break;
case 0x02: /* stax b */
cycles = 7;
WR_BYTE(BC, A);
break;
case 0x03: /* inx b */
cycles = 5;
BC++;
break;
case 0x04: /* inr b */
cycles = 5;
INR(B);
break;
case 0x05: /* dcr b */
cycles = 5;
DCR(B);
break;
case 0x06: /* mvi b, data8 */
cycles = 7;
B = RD_BYTE(PC++);
break;
case 0x07: /* rlc */
cycles = 4;
C_FLAG = ((A & 0x80) != 0);
A = (A << 1) | C_FLAG;
break;
case 0x09: /* dad b */
cycles = 10;
DAD(BC);
break;
case 0x0A: /* ldax b */
cycles = 7;
A = RD_BYTE(BC);
break;
case 0x0B: /* dcx b */
cycles = 5;
BC--;
break;
case 0x0C: /* inr c */
cycles = 5;
INR(C);
break;
case 0x0D: /* dcr c */
cycles = 5;
DCR(C);
break;
case 0x0E: /* mvi c, data8 */
cycles = 7;
C = RD_BYTE(PC++);
break;
case 0x0F: /* rrc */
cycles = 4;
C_FLAG = A & 0x01;
A = (A >> 1) | (C_FLAG << 7);
break;
case 0x11: /* lxi d, data16 */
cycles = 10;
DE = RD_WORD(PC);
PC += 2;
break;
case 0x12: /* stax d */
cycles = 7;
WR_BYTE(DE, A);
break;
case 0x13: /* inx d */
cycles = 5;
DE++;
break;
case 0x14: /* inr d */
cycles = 5;
INR(D);
break;
case 0x15: /* dcr d */
cycles = 5;
DCR(D);
break;
case 0x16: /* mvi d, data8 */
cycles = 7;
D = RD_BYTE(PC++);
break;
case 0x17: /* ral */
cycles = 4;
work8 = (uns8)C_FLAG;
C_FLAG = ((A & 0x80) != 0);
A = (A << 1) | work8;
break;
case 0x19: /* dad d */
cycles = 10;
DAD(DE);
break;
case 0x1A: /* ldax d */
cycles = 7;
A = RD_BYTE(DE);
break;
case 0x1B: /* dcx d */
cycles = 5;
DE--;
break;
case 0x1C: /* inr e */
cycles = 5;
INR(E);
break;
case 0x1D: /* dcr e */
cycles = 5;
DCR(E);
break;
case 0x1E: /* mvi e, data8 */
cycles = 7;
E = RD_BYTE(PC++);
break;
case 0x1F: /* rar */
cycles = 4;
work8 = (uns8)C_FLAG;
C_FLAG = A & 0x01;
A = (A >> 1) | (work8 << 7);
break;
case 0x21: /* lxi h, data16 */
cycles = 10;
HL = RD_WORD(PC);
PC += 2;
break;
case 0x22: /* shld addr */
cycles = 16;
WR_WORD(RD_WORD(PC), HL);
PC += 2;
break;
case 0x23: /* inx h */
cycles = 5;
HL++;
break;
case 0x24: /* inr h */
cycles = 5;
INR(H);
break;
case 0x25: /* dcr h */
cycles = 5;
DCR(H);
break;
case 0x26: /* mvi h, data8 */
cycles = 7;
H = RD_BYTE(PC++);
break;
case 0x27: /* daa */
cycles = 4;
carry = (uns8)C_FLAG;
add = 0;
if (H_FLAG || (A & 0x0f) > 9) {
add = 0x06;
}
if (C_FLAG || (A >> 4) > 9 || ((A >> 4) >= 9 && (A & 0x0f) > 9)) {
add |= 0x60;
carry = 1;
}
ADD(add);
P_FLAG = PARITY(A);
C_FLAG = carry;
break;
case 0x29: /* dad hl */
cycles = 10;
DAD(HL);
break;
case 0x2A: /* ldhl addr */
cycles = 16;
HL = RD_WORD(RD_WORD(PC));
PC += 2;
break;
case 0x2B: /* dcx h */
cycles = 5;
HL--;
break;
case 0x2C: /* inr l */
cycles = 5;
INR(L);
break;
case 0x2D: /* dcr l */
cycles = 5;
DCR(L);
break;
case 0x2E: /* mvi l, data8 */
cycles = 7;
L = RD_BYTE(PC++);
break;
case 0x2F: /* cma */
cycles = 4;
A ^= 0xff;
break;
case 0x31: /* lxi sp, data16 */
cycles = 10;
SP = RD_WORD(PC);
PC += 2;
break;
case 0x32: /* sta addr */
cycles = 13;
WR_BYTE(RD_WORD(PC), A);
PC += 2;
break;
case 0x33: /* inx sp */
cycles = 5;
SP++;
break;
case 0x34: /* inr m */
cycles = 10;
work8 = RD_BYTE(HL);
INR(work8);
WR_BYTE(HL, work8);
break;
case 0x35: /* dcr m */
cycles = 10;
work8 = RD_BYTE(HL);
DCR(work8);
WR_BYTE(HL, work8);
break;
case 0x36: /* mvi m, data8 */
cycles = 10;
WR_BYTE(HL, RD_BYTE(PC++));
break;
case 0x37: /* stc */
cycles = 4;
SET(C_FLAG);
break;
case 0x39: /* dad sp */
cycles = 10;
DAD(SP);
break;
case 0x3A: /* lda addr */
cycles = 13;
A = RD_BYTE(RD_WORD(PC));
PC += 2;
break;
case 0x3B: /* dcx sp */
cycles = 5;
SP--;
break;
case 0x3C: /* inr a */
cycles = 5;
INR(A);
break;
case 0x3D: /* dcr a */
cycles = 5;
DCR(A);
break;
case 0x3E: /* mvi a, data8 */
cycles = 7;
A = RD_BYTE(PC++);
break;
case 0x3F: /* cmc */
cycles = 4;
CPL(C_FLAG);
break;
case 0x40: /* mov b, b */
cycles = 4;
break;
case 0x41: /* mov b, c */
cycles = 5;
B = C;
break;
case 0x42: /* mov b, d */
cycles = 5;
B = D;
break;
case 0x43: /* mov b, e */
cycles = 5;
B = E;
break;
case 0x44: /* mov b, h */
cycles = 5;
B = H;
break;
case 0x45: /* mov b, l */
cycles = 5;
B = L;
break;
case 0x46: /* mov b, m */
cycles = 7;
B = RD_BYTE(HL);
break;
case 0x47: /* mov b, a */
cycles = 5;
B = A;
break;
case 0x48: /* mov c, b */
cycles = 5;
C = B;
break;
case 0x49: /* mov c, c */
cycles = 5;
break;
case 0x4A: /* mov c, d */
cycles = 5;
C = D;
break;
case 0x4B: /* mov c, e */
cycles = 5;
C = E;
break;
case 0x4C: /* mov c, h */
cycles = 5;
C = H;
break;
case 0x4D: /* mov c, l */
cycles = 5;
C = L;
break;
case 0x4E: /* mov c, m */
cycles = 7;
C = RD_BYTE(HL);
break;
case 0x4F: /* mov c, a */
cycles = 5;
C = A;
break;
case 0x50: /* mov d, b */
cycles = 5;
D = B;
break;
case 0x51: /* mov d, c */
cycles = 5;
D = C;
break;
case 0x52: /* mov d, d */
cycles = 5;
break;
case 0x53: /* mov d, e */
cycles = 5;
D = E;
break;
case 0x54: /* mov d, h */
cycles = 5;
D = H;
break;
case 0x55: /* mov d, l */
cycles = 5;
D = L;
break;
case 0x56: /* mov d, m */
cycles = 7;
D = RD_BYTE(HL);
break;
case 0x57: /* mov d, a */
cycles = 5;
D = A;
break;
case 0x58: /* mov e, b */
cycles = 5;
E = B;
break;
case 0x59: /* mov e, c */
cycles = 5;
E = C;
break;
case 0x5A: /* mov e, d */
cycles = 5;
E = D;
break;
case 0x5B: /* mov e, e */
cycles = 5;
break;
case 0x5C: /* mov c, h */
cycles = 5;
E = H;
break;
case 0x5D: /* mov c, l */
cycles = 5;
E = L;
break;
case 0x5E: /* mov c, m */
cycles = 7;
E = RD_BYTE(HL);
break;
case 0x5F: /* mov c, a */
cycles = 5;
E = A;
break;
case 0x60: /* mov h, b */
cycles = 5;
H = B;
break;
case 0x61: /* mov h, c */
cycles = 5;
H = C;
break;
case 0x62: /* mov h, d */
cycles = 5;
H = D;
break;
case 0x63: /* mov h, e */
cycles = 5;
H = E;
break;
case 0x64: /* mov h, h */
cycles = 5;
break;
case 0x65: /* mov h, l */
cycles = 5;
H = L;
break;
case 0x66: /* mov h, m */
cycles = 7;
H = RD_BYTE(HL);
break;
case 0x67: /* mov h, a */
cycles = 5;
H = A;
break;
case 0x68: /* mov l, b */
cycles = 5;
L = B;
break;
case 0x69: /* mov l, c */
cycles = 5;
L = C;
break;
case 0x6A: /* mov l, d */
cycles = 5;
L = D;
break;
case 0x6B: /* mov l, e */
cycles = 5;
L = E;
break;
case 0x6C: /* mov l, h */
cycles = 5;
L = H;
break;
case 0x6D: /* mov l, l */
cycles = 5;
break;
case 0x6E: /* mov l, m */
cycles = 7;
L = RD_BYTE(HL);
break;
case 0x6F: /* mov l, a */
cycles = 5;
L = A;
break;
case 0x70: /* mov m, b */
cycles = 7;
WR_BYTE(HL, B);
break;
case 0x71: /* mov m, c */
cycles = 7;
WR_BYTE(HL, C);
break;
case 0x72: /* mov m, d */
cycles = 7;
WR_BYTE(HL, D);
break;
case 0x73: /* mov m, e */
cycles = 7;
WR_BYTE(HL, E);
break;
case 0x74: /* mov m, h */
cycles = 7;
WR_BYTE(HL, H);
break;
case 0x75: /* mov m, l */
cycles = 7;
WR_BYTE(HL, L);
break;
case 0x76: /* hlt */
cycles = 4;
PC--;
break;
case 0x77: /* mov m, a */
cycles = 7;
WR_BYTE(HL, A);
break;
case 0x78: /* mov a, b */
cycles = 5;
A = B;
break;
case 0x79: /* mov a, c */
cycles = 5;
A = C;
break;
case 0x7A: /* mov a, d */
cycles = 5;
A = D;
break;
case 0x7B: /* mov a, e */
cycles = 5;
A = E;
break;
case 0x7C: /* mov a, h */
cycles = 5;
A = H;
break;
case 0x7D: /* mov a, l */
cycles = 5;
A = L;
break;
case 0x7E: /* mov a, m */
cycles = 7;
A = RD_BYTE(HL);
break;
case 0x7F: /* mov a, a */
cycles = 5;
break;
case 0x80: /* add b */
cycles = 4;
ADD(B);
break;
case 0x81: /* add c */
cycles = 4;
ADD(C);
break;
case 0x82: /* add d */
cycles = 4;
ADD(D);
break;
case 0x83: /* add e */
cycles = 4;
ADD(E);
break;
case 0x84: /* add h */
cycles = 4;
ADD(H);
break;
case 0x85: /* add l */
cycles = 4;
ADD(L);
break;
case 0x86: /* add m */
cycles = 7;
work8 = RD_BYTE(HL);
ADD(work8);
break;
case 0x87: /* add a */
cycles = 4;
ADD(A);
break;
case 0x88: /* adc b */
cycles = 4;
ADC(B);
break;
case 0x89: /* adc c */
cycles = 4;
ADC(C);
break;
case 0x8A: /* adc d */
cycles = 4;
ADC(D);
break;
case 0x8B: /* adc e */
cycles = 4;
ADC(E);
break;
case 0x8C: /* adc h */
cycles = 4;
ADC(H);
break;
case 0x8D: /* adc l */
cycles = 4;
ADC(L);
break;
case 0x8E: /* adc m */
cycles = 7;
work8 = RD_BYTE(HL);
ADC(work8);
break;