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AMD Ryzen 7 9800X3D #517

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notpentadactyl opened this issue Nov 19, 2024 · 19 comments
Open

AMD Ryzen 7 9800X3D #517

notpentadactyl opened this issue Nov 19, 2024 · 19 comments

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@notpentadactyl
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notpentadactyl commented Nov 19, 2024 •
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corefreq-cli -s

Processor                                 [AMD Ryzen 7 9800X3D 8-Core Processor]
|- Architecture                                             [Zen5/Granite Ridge]
|- Vendor ID                                                      [AuthenticAMD]
|- Microcode                                                        [0x0b404023]
|- Signature                                                           [  BF_44]
|- Stepping                                                            [      0]
|- Online CPU                                                          [ 16/ 16]
|- Base Clock                                                          [100.003]
|- Frequency            (MHz)                      Ratio
                 Min   3000.09                    <  30 >
                 Max   4700.14                    <  47 >
|- Factory                                                             [100.000]
                       4700                       [  47 ]
|- Performance
                 TGT   4700.14                    <  47 >
   |- CPPC
                 Min   3400.10                    <  34 >
                 Max   2200.09                    <  22 >
                 TGT      AUTO                    <   0 >
   |- Boost                                                            [ UNLOCK]
                 XFR   5200.16                    [  52 ]
                 CPB   5200.16                    [  52 ]
   |- P-State
                 P1    3000.09                    <  30 >
|- Uncore                                                              [   LOCK]

Instruction Set Extensions
|- 3DNow!/Ext [N/N]          ADX [Y]          AES [Y]  AVX/AVX2 [Y/Y]
|- AVX512-F     [Y]    AVX512-DQ [Y]  AVX512-IFMA [Y]   AVX512-PF [N]
|- AVX512-ER    [N]    AVX512-CD [Y]    AVX512-BW [Y]   AVX512-VL [Y]
|- AVX512-VBMI  [Y] AVX512-VBMI2 [Y]  AVX512-VNNI [Y]  AVX512-ALG [Y]
|- AVX512-VPOP  [Y] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [Y]
|- AVX512-BF16  [Y] AVX-VNNI-VEX [Y]    AVX-FP128 [N]   AVX-FP256 [N]
|- BMI1/BMI2  [Y/Y]         CLWB [Y]      CLFLUSH [Y] CLFLUSH-OPT [Y]
|- CLAC-STAC    [Y]         CMOV [Y]    CMPXCHG8B [Y]  CMPXCHG16B [Y]
|- F16C         [Y]          FPU [Y]         FXSR [Y]   LAHF-SAHF [Y]
|- MMX/Ext    [Y/Y] MON/MWAITX [Y/Y]        MOVBE [Y]   PCLMULQDQ [Y]
|- POPCNT       [Y]       RDRAND [Y]       RDSEED [Y]      RDTSCP [Y]
|- SEP          [Y]          SHA [Y]          SSE [Y]        SSE2 [Y]
|- SSE3         [Y]        SSSE3 [Y]  SSE4.1/4A [Y/Y]      SSE4.2 [Y]
|- SERIALIZE    [N]      SYSCALL [Y]        RDPID [Y]        UMIP [Y]
|- VAES         [Y]   VPCLMULQDQ [Y]   PREFETCH/W [Y]       LZCNT [Y]

Features
|- 1 GB Pages Support                                      1GB-PAGES   [Capable]
|- 100 MHz multiplier Control                            100MHzSteps   [Missing]
|- Advanced Configuration & Power Interface                     ACPI   [Capable]
|- Advanced Programmable Interrupt Controller                   APIC   [Capable]
|- Advanced Virtual Interrupt Controller                        AVIC   [Capable]
|- APIC Timer Invariance                                        ARAT   [Capable]
|- LOCK prefix to read CR8                                    AltMov   [Capable]
|- Clear Zero Instruction                                     CLZERO   [Capable]
|- Core Multi-Processing                                  CMP Legacy   [Capable]
|- L1 Data Cache Context ID                                  CNXT-ID   [Missing]
|- Collaborative Processor Performance Control                  CPPC   [Capable]
|- Direct Cache Access                                           DCA   [Missing]
|- Debugging Extension                                            DE   [Capable]
|- Debug Store & Precise Event Based Sampling               DS, PEBS   [Missing]
|- CPL Qualified Debug Store                                  DS-CPL   [Missing]
|- 64-Bit Debug Store                                         DTES64   [Missing]
|- Fast Short REP CMPSB|SCASB                                   FSRC   [Capable]
|- Fast Short REP MOVSB                                         FSRM   [Capable]
|- Fast Short REP STOSB                                         FSRS   [Capable]
|- Fast-String Operation                                        ERMS   [Capable]
|- Fused Multiply Add                                           FMA4   [Missing]
|- Fused Multiply Add                                            FMA   [Capable]
|- Hardware Lock Elision                                         HLE   [Missing]
|- Hyper-Threading Technology                                    HTT   [Capable]
|- Hardware P-state control                                      HwP   [Capable]
|- Instruction Based Sampling                                    IBS   [Capable]
|- Instruction INVLPGB                                       INVLPGB   [Missing]
|- Instruction INVPCID                                       INVPCID   [Capable]
|- Long Mode 64 bits                                       IA64 | LM   [Capable]
|- LightWeight Profiling                                         LWP   [Missing]
|- Memory Bandwidth Enforcement                                  MBE   [Capable]
|- Machine-Check Architecture                                    MCA   [Capable]
|- Instruction MCOMMIT                                       MCOMMIT   [Missing]
|- Model Specific Registers                                      MSR   [Capable]
|- Memory Type Range Registers                                  MTRR   [Capable]
|- No-Execute Page Protection                                     NX   [Capable]
|- OS-Enabled Ext. State Management                          OSXSAVE   [Capable]
|- OS Visible Work-around                                       OSVW   [Capable]
|- Physical Address Extension                                    PAE   [Capable]
|- Page Attribute Table                                          PAT   [Capable]
|- Pending Break Enable                                          PBE   [Missing]
|- Process Context Identifiers                                  PCID   [Missing]
|- Perfmon and Debug Capability                                 PDCM   [Missing]
|- Page Global Enable                                            PGE   [Capable]
|- Page Size Extension                                           PSE   [Capable]
|- 36-bit Page Size Extension                                  PSE36   [Capable]
|- Processor Serial Number                                       PSN   [Missing]
|- PREFETCHIT0/1 Instructions                              PREFETCHI   [Capable]
|- Resource Director Technology/PQE                            RDT-A   [Capable]
|- Resource Director Technology/PQM                            RDT-M   [Capable]
|- Read Processor Register at User level                       RDPRU   [Capable]
|- Restricted Transactional Memory                               RTM   [Missing]
|- Safer Mode Extensions                                         SMX   [Missing]
|- Self-Snoop                                                     SS   [Missing]
|- Supervisor-Mode Access Prevention                            SMAP   [Capable]
|- Supervisor-Mode Execution Prevention                         SMEP   [Capable]
|- Trailing Bit Manipulation                                     TBM   [Missing]
|- Translation Cache Extension                                   TCE   [Capable]
|- Time Stamp Counter                                            TSC [Invariant]
|- Time Stamp Counter Deadline                          TSC-DEADLINE   [Missing]
|- TSX Force Abort MSR Register                            TSX-ABORT   [Missing]
|- TSX Suspend Load Address Tracking                       TSX-LDTRK   [Missing]
|- User-Mode Instruction Prevention                             UMIP   [Capable]
|- Virtual Mode Extension                                        VME   [Capable]
|- Virtual Machine Extensions                                    VMX   [Missing]
|- Write Back & Do Not Invalidate Cache                     WBNOINVD   [Capable]
|- Extended xAPIC Support                                     x2APIC   [  xAPIC]
|- AVIC controller for x2APIC                                 x2AVIC   [Capable]
|- XSAVE/XSTOR States                                          XSAVE   [Capable]
|- xTPR Update Control                                          xTPR   [Missing]
|- Extended Operation Support                                    XOP   [Missing]
Mitigation mechanisms
|- Indirect Branch Restricted Speculation                       IBRS   [Capable]
   |- IBRS Always-On preferred by processor                            [ Unable]
   |- IBRS preferred over software solution                            [Capable]
   |- IBRS provides same speculation limits                            [Capable]
|- Indirect Branch Prediction Barrier                           IBPB   [Capable]
|- Selective Branch Predictor Barrier                           SBPB   [Capable]
|- Single Thread Indirect Branch Predictor                     STIBP   [ Enable]
|- Speculative Store Bypass Disable                             SSBD   [Capable]
   |- SSBD use VIRT_SPEC_CTRL register                                 [ Unable]
   |- SSBD not needed on this processor                                [ Unable]
|- No Speculative Return Stack Overflow                      SRSO_NO   [ Unable]
   |- No SRSO at the User-Kernel boundary                              [Capable]
|- No Branch Type Confusion                                   BTC_NO   [Capable]
|- BTC on Non-Branch instruction                            BTC-NOBR   [Capable]
|- Limited Early Redirect Window                            AGENPICK   [ Unable]
|- Arch - No Fast Predictive Store Forwarding                   PSFD   [Capable]
|- Arch - Enhanced Predictive Store Forwarding                  EPSF   [Capable]
|- Arch - Cross Processor Information Leak                XPROC_LEAK   [ Unable]
Security Features
|- CET Shadow Stack features                                  CET-SS   [Capable]
|- Secure Init and Jump with Attestation                      SKINIT   [Capable]
|- Secure Encrypted Virtualization                               SEV   [Missing]
|- SEV - Encrypted State                                      SEV-ES   [Missing]
|- SEV - Secure Nested Paging                                SEV-SNP   [Missing]
|- Guest Mode Execute Trap                                      GMET   [Capable]
|- Supervisor Shadow Stack                                       SSS   [Capable]
|- VM Permission Levels                                         VMPL   [Missing]
|- VMPL Supervisor Shadow Stack                             VMPL-SSS   [Missing]
|- Secure Memory Encryption                                      SME   [Capable]
|- Transparent SME                                              TSME   [ Unable]
|- Secure Multi-Key Memory Encryption                         SME-MK   [Missing]
|- DRAM Data Scrambling                                    Scrambler   [ Unable]

Technologies
|- Instruction Cache Unit
   |- L1 IP Prefetcher                                          L1 HW IP   < ON>
|- Data Cache Unit
   |- L1 Prefetcher                                                L1 HW   < ON>
|- Cache Prefetchers
   |- L2 Prefetcher                                                L2 HW   < ON>
   |- L1 Stride Prefetcher                                     L1 Stride   < ON>
   |- L1 Region Prefetcher                                     L1 Region   < ON>
   |- L1 Burst Prefetch Mode                                    L1 Burst   < ON>
   |- L2 Stream HW Prefetcher                                  L2 Stream   < ON>
   |- L2 Up/Down Prefetcher                                   L2 Up/Down   < ON>
|- System Management Mode                                       SMM-Lock   [ ON]
|- Simultaneous Multithreading                                       SMT   [ ON]
|- PowerNow!                                                         CnQ   [ ON]
|- Core C-States                                                     CCx   [ ON]
|- Core Performance Boost                                            CPB   < ON>
|- Watchdog Timer                                                    WDT   < ON>
|- Virtualization                                                    SVM   [ ON]
   |- I/O MMU                                                      AMD-V   [OFF]
   |- Version                                                     [         N/A]
   |- Hypervisor                                                           [OFF]
   |- Vendor ID                                                   [         N/A]

Performance Monitoring
|- Version                                                        PM       [  2]
|- Counters:          General                   Fixed
|           {  6,  6, 16 } x 48 bits            3 x 64 bits
|- Enhanced Halt State                                           C1E       <OFF>
|- C2 UnDemotion                                                 C2U       < ON>
|- C3 UnDemotion                                                 C3U       < ON>
|- Core C6 State                                                 CC6       < ON>
|- Package C6 State                                              PC6       < ON>
|- Legacy Frequency ID control                                   FID       [OFF]
|- Legacy Voltage ID control                                     VID       [OFF]
|- P-State Hardware Coordination Feedback                MPERF/APERF       [ ON]
|- Core C-States
   |- C-States Base Address                                      BAR   [ 0x413 ]
|- ACPI Processor C-States                                      _CST   [      3]
|- MONITOR/MWAIT
   |- State index:    #0    #1    #2    #3    #4    #5    #6    #7
   |- Sub C-State:     1     2     0     0     0     0     0     0
   |- Monitor-Mwait Extensions                                   EMX   [Capable]
   |- Interrupt Break-Event                                      IBE   [Capable]
|- Core Cycles                                                         [Capable]
|- Instructions Retired                                                [Capable]
|- Reference Cycles                                                    [Capable]
|- Last Level Cache References                                         [Capable]
|- Global Time Stamp Counter                                           [Missing]
|- Data Fabric Performance Counter                                     [Capable]
|- Core Performance Counter                                            [Capable]
|- Processor Performance Control                                _PCT   [ Enable]
|- Performance Supported States                                 _PSS   [      2]
|- Performance Present Capabilities                             _PPC   [      0]
|- Continuous Performance Control                               _CPC   [Missing]

Power, Current & Thermal
|- Temperature Offset:Junction                                 TjMax [ 49: 95 C]
|- CPPC Energy Preference                                        EPP   <    128>
|- Digital Thermal Sensor                                        DTS   [Capable]
|- Power Limit Notification                                      PLN   [Missing]
|- Package Thermal Management                                    PTM   [Missing]
|- Thermal Monitor 1                                             TTP   [ Enable]
|- Thermal Monitor 2                                             HTC   [ Enable]
|- Thermal Design Power                                          TDP   [Missing]
   |- Minimum Power                                              Min   [Missing]
   |- Maximum Power                                              Max   [Missing]
|- Thermal Design Power                                      Package   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
   |- Power Limit                                                PL2   [    0 W]
   |- Time Window                                                TW2   [   0 ns]
|- Thermal Design Power                                         Core   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
|- Thermal Design Power                                       Uncore   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
|- Thermal Design Power                                         DRAM   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
|- Thermal Design Power                                     Platform   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
   |- Power Limit                                                PL2   [    0 W]
   |- Time Window                                                TW2   [   0 ns]
|- Package Power Tracking                                        PPT   [Missing]
|- Electrical Design Current                                     EDC   [Missing]
|- Thermal Design Current                                        TDC   [Missing]
|- Core Thermal Point
|- Package Thermal Point
   |- Thermal Monitor Trip                                     Limit   [  115 C]
   |- HTC Temperature Limit                                    Limit   [  127 C]
   |- HTC Temperature Hysteresis                           Threshold   [    2 C]
|- Units
   |- Power                                               watt   [      Missing]
   |- Energy                                             joule   [  0.000015259]
   |- Window                                            second   [  0.000976562]

corefreq-cli -k -n -B -n -M

Linux:
|- Release                                        [6.12.0-rc7-1-cachyos-autofdo]
|- Version              [#1 SMP PREEMPT_DYNAMIC Mon, 11 Nov 2024 12:35:24 +0000]
|- Machine                                                              [x86_64]
Memory:
|- Total RAM                                                         65412008 KB
|- Shared RAM                                                          525884 KB
|- Free RAM                                                          48305028 KB
|- Buffer RAM                                                          291080 KB
|- Total High                                                               0 KB
|- Free High                                                                0 KB
Clock Source                                                  <             tsc>
CPU-Freq driver                                               [  amd-pstate-epp]
Governor                                                      [         Missing]
CPU-Idle driver                                               [       acpi_idle]
|- Idle Limit                                                 [              C3]
   |- State        POLL      C1      C2      C3
   |-           CPUIDLE ACPI FF ACPI IO ACPI IO
   |- Power          -1       0       0       0
   |- Latency         0       1      18     350
   |- Residency       0       2      36     700

[ 0] American Megatrends International, LLC.
[ 1] 3.10
[ 2] 10/24/2024
[ 3] ASRock
[ 4] X870E Taichi Lite
[ 5] Default string
[ 6] D---u---s---n-
[ 7] Default string
[ 8] Default string
[ 9] ASRock
[10] X870E Taichi Lite
[11] Default string
[12] M---H---8---7--
[13] Number Of Devices:4\Maximum Capacity:134217728 kilobytes
[14]
[15] DIMM 1\P0 CHANNEL A
[16]
[17] DIMM 1\P0 CHANNEL B
[18]
[19] Unknown
[20]
[21] Unknown
[22]
[23] F5-6000J3040G32G
[24]
[25] F5-6000J3040G32G

                            AuthenticAMD  [   0]

corefreq-cli -m -n -z

CPU Pkg  Apic  Core/Thread  Caches      (w)rite-Back (i)nclusive
 #   ID   ID CCD CCX ID/ID L1-Inst Way  L1-Data Way      L2  Way      L3  Way
000:BSP    0   0  0   0  0      32  8        48 12      1024 16 i   98304 16w
001:  0    2   0  0   1  0      32  8        48 12      1024 16 i   98304 16w
002:  0    4   0  0   2  0      32  8        48 12      1024 16 i   98304 16w
003:  0    6   0  0   3  0      32  8        48 12      1024 16 i   98304 16w
004:  0    8   0  1   4  0      32  8        48 12      1024 16 i   98304 16w
005:  0   10   0  1   5  0      32  8        48 12      1024 16 i   98304 16w
006:  0   12   0  1   6  0      32  8        48 12      1024 16 i   98304 16w
007:  0   14   0  1   7  0      32  8        48 12      1024 16 i   98304 16w
008:  0    1   0  0   0  1      32  8        48 12      1024 16 i   98304 16w
009:  0    3   0  0   1  1      32  8        48 12      1024 16 i   98304 16w
010:  0    5   0  0   2  1      32  8        48 12      1024 16 i   98304 16w
011:  0    7   0  0   3  1      32  8        48 12      1024 16 i   98304 16w
012:  0    9   0  1   4  1      32  8        48 12      1024 16 i   98304 16w
013:  0   11   0  1   5  1      32  8        48 12      1024 16 i   98304 16w
014:  0   13   0  1   6  1      32  8        48 12      1024 16 i   98304 16w
015:  0   15   0  1   7  1      32  8        48 12      1024 16 i   98304 16w

|- Collaborative Processor Performance Control                  CPPC       < ON>
   |- Capabilities     Lowest      Efficient     Guaranteed        Highest
   |- CPU #0     400.01 (  4)  1900.03 ( 19)  3000.04 ( 30)  4000.06 ( 40)
   |- CPU #1     400.00 (  4)  1900.01 ( 19)  3000.01 ( 30)  4000.02 ( 40)
   |- CPU #2     400.00 (  4)  1900.00 ( 19)  2999.99 ( 30)  3599.99 ( 36)
   |- CPU #3     400.00 (  4)  1900.00 ( 19)  3000.00 ( 30)  3700.01 ( 37)
   |- CPU #4     400.00 (  4)  1899.99 ( 19)  2999.99 ( 30)  3799.99 ( 38)
   |- CPU #5     400.00 (  4)  1900.01 ( 19)  3000.01 ( 30)  3900.02 ( 39)
   |- CPU #6     400.00 (  4)  1899.99 ( 19)  2999.99 ( 30)  3499.99 ( 35)
   |- CPU #7     400.01 (  4)  1900.03 ( 19)  3000.04 ( 30)  3400.05 ( 34)
   |- CPU #8     400.00 (  4)  1900.01 ( 19)  3000.01 ( 30)  4000.02 ( 40)
   |- CPU #9     400.00 (  4)  1900.01 ( 19)  3000.02 ( 30)  4000.02 ( 40)
   |- CPU #10    400.00 (  4)  1900.01 ( 19)  3000.01 ( 30)  3600.01 ( 36)
   |- CPU #11    400.00 (  4)  1899.99 ( 19)  2999.99 ( 30)  3699.98 ( 37)
   |- CPU #12    400.00 (  4)  1900.01 ( 19)  3000.02 ( 30)  3800.02 ( 38)
   |- CPU #13    400.00 (  4)  1900.01 ( 19)  3000.01 ( 30)  3900.02 ( 39)
   |- CPU #14    400.00 (  4)  1899.99 ( 19)  2999.99 ( 30)  3499.99 ( 35)
   |- CPU #15    400.00 (  4)  1900.00 ( 19)  3000.01 ( 30)  3400.01 ( 34)

corefreq-cli -u
corefreq-cli-u.txt

Idle:

image

Atomic:

image
@cyring
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cyring commented Nov 19, 2024

@notpentadactyl Thank you very much for this first 9800X3D report.

  • Unfortunately, no Power Limit shown because no HSMP protocol on this model
  • Memory Controller and IOMMU are not printed
    1- Can you try from the develop branch in which I have recently pushed a PCI list change
    2- Rebuild, reload module and post corefreq-cli -s -n -M
    3- In case, there is still no output from Memory Controller, please post the PCI identifiers from command lspci -nn

@notpentadactyl
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notpentadactyl commented Nov 19, 2024 •
edited
Loading

@cyring no problem!

https://github.com/cyring/CoreFreq/tree/develop doesn't seem to like my kernel linux-cachyos-autofdo 6.12.rc7-1:
make.log

I need 6.12 for ethernet on this mainboard.

That being said: I could build it on kernel linux-cachyos 6.11.9-2:
corefreq-cli -s -n -M

Processor                                 [AMD Ryzen 7 9800X3D 8-Core Processor]
|- Architecture                                             [Zen5/Granite Ridge]
|- Vendor ID                                                      [AuthenticAMD]
|- Microcode                                                        [0x0b404023]
|- Signature                                                           [  BF_44]
|- Stepping                                                            [      0]
|- Online CPU                                                          [ 16/ 16]
|- Base Clock                                                          [ 41.229]
|- Frequency            (MHz)                      Ratio
                 Min   3628.17                    <  88 >
                 Max   4700.13                    < 114 >
|- Factory                                                             [100.000]
                      11400                       [ 114 ]
|- Performance
                 TGT   4700.13                    < 114 >
   |- CPPC
                 Min   3504.49                    <  85 >
                 Max   2020.25                    <  49 >
                 TGT      AUTO                    <   0 >
   |- Boost                                                            [   LOCK]
                 XFR   4700.13                    [ 114 ]
                 CPB   4700.13                    [ 114 ]
   |- P-State
                 P1    3628.17                    <  88 >
|- Uncore                                                              [   LOCK]
                 CLK    618.44                    [  15 ]
                 MEM   1236.88                    [  30 ]

Instruction Set Extensions
|- 3DNow!/Ext [N/N]          ADX [Y]          AES [Y]  AVX/AVX2 [Y/Y]
|- AVX512-F     [Y]    AVX512-DQ [Y]  AVX512-IFMA [Y]   AVX512-PF [N]
|- AVX512-ER    [N]    AVX512-CD [Y]    AVX512-BW [Y]   AVX512-VL [Y]
|- AVX512-VBMI  [Y] AVX512-VBMI2 [Y]  AVX512-VNNI [Y]  AVX512-ALG [Y]
|- AVX512-VPOP  [Y] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [Y]
|- AVX512-BF16  [Y] AVX-VNNI-VEX [Y]    AVX-FP128 [N]   AVX-FP256 [N]
|- BMI1/BMI2  [Y/Y]         CLWB [Y]      CLFLUSH [Y] CLFLUSH-OPT [Y]
|- CLAC-STAC    [Y]         CMOV [Y]    CMPXCHG8B [Y]  CMPXCHG16B [Y]
|- F16C         [Y]          FPU [Y]         FXSR [Y]   LAHF-SAHF [Y]
|- MMX/Ext    [Y/Y] MON/MWAITX [Y/Y]        MOVBE [Y]   PCLMULQDQ [Y]
|- POPCNT       [Y]       RDRAND [Y]       RDSEED [Y]      RDTSCP [Y]
|- SEP          [Y]          SHA [Y]          SSE [Y]        SSE2 [Y]
|- SSE3         [Y]        SSSE3 [Y]  SSE4.1/4A [Y/Y]      SSE4.2 [Y]
|- SERIALIZE    [N]      SYSCALL [Y]        RDPID [Y]        UMIP [Y]
|- VAES         [Y]   VPCLMULQDQ [Y]   PREFETCH/W [Y]       LZCNT [Y]

Features
|- 1 GB Pages Support                                      1GB-PAGES   [Capable]
|- 100 MHz multiplier Control                            100MHzSteps   [Missing]
|- Advanced Configuration & Power Interface                     ACPI   [Capable]
|- Advanced Programmable Interrupt Controller                   APIC   [Capable]
|- Advanced Virtual Interrupt Controller                        AVIC   [Capable]
|- APIC Timer Invariance                                        ARAT   [Capable]
|- LOCK prefix to read CR8                                    AltMov   [Capable]
|- Clear Zero Instruction                                     CLZERO   [Capable]
|- Core Multi-Processing                                  CMP Legacy   [Capable]
|- L1 Data Cache Context ID                                  CNXT-ID   [Missing]
|- Collaborative Processor Performance Control                  CPPC   [Capable]
|- Direct Cache Access                                           DCA   [Missing]
|- Debugging Extension                                            DE   [Capable]
|- Debug Store & Precise Event Based Sampling               DS, PEBS   [Missing]
|- CPL Qualified Debug Store                                  DS-CPL   [Missing]
|- 64-Bit Debug Store                                         DTES64   [Missing]
|- Fast Short REP MOVSB                                         FSRM   [Capable]
|- Fast-String Operation                                        ERMS   [Capable]
|- Fused Multiply Add                                           FMA4   [Missing]
|- Fused Multiply Add                                            FMA   [Capable]
|- Hardware Lock Elision                                         HLE   [Missing]
|- Hyper-Threading Technology                                    HTT   [Capable]
|- Hardware P-state control                                      HwP   [Capable]
|- Instruction Based Sampling                                    IBS   [Capable]
|- Instruction INVLPGB                                       INVLPGB   [Missing]
|- Instruction INVPCID                                       INVPCID   [Capable]
|- Long Mode 64 bits                                       IA64 | LM   [Capable]
|- LightWeight Profiling                                         LWP   [Missing]
|- Memory Bandwidth Enforcement                                  MBE   [Capable]
|- Machine-Check Architecture                                    MCA   [Capable]
|- Instruction MCOMMIT                                       MCOMMIT   [Missing]
|- Model Specific Registers                                      MSR   [Capable]
|- Memory Type Range Registers                                  MTRR   [Capable]
|- No-Execute Page Protection                                     NX   [Capable]
|- OS-Enabled Ext. State Management                          OSXSAVE   [Capable]
|- OS Visible Work-around                                       OSVW   [Capable]
|- Physical Address Extension                                    PAE   [Capable]
|- Page Attribute Table                                          PAT   [Capable]
|- Pending Break Enable                                          PBE   [Missing]
|- Process Context Identifiers                                  PCID   [Missing]
|- Perfmon and Debug Capability                                 PDCM   [Missing]
|- Page Global Enable                                            PGE   [Capable]
|- Page Size Extension                                           PSE   [Capable]
|- 36-bit Page Size Extension                                  PSE36   [Capable]
|- Processor Serial Number                                       PSN   [Missing]
|- Resource Director Technology/PQE                            RDT-A   [Capable]
|- Resource Director Technology/PQM                            RDT-M   [Capable]
|- Read Processor Register at User level                       RDPRU   [Capable]
|- Restricted Transactional Memory                               RTM   [Missing]
|- Safer Mode Extensions                                         SMX   [Missing]
|- Self-Snoop                                                     SS   [Missing]
|- Supervisor-Mode Access Prevention                            SMAP   [Capable]
|- Supervisor-Mode Execution Prevention                         SMEP   [Capable]
|- Trailing Bit Manipulation                                     TBM   [Missing]
|- Translation Cache Extension                                   TCE   [Capable]
|- Time Stamp Counter                                            TSC [Invariant]
|- Time Stamp Counter Deadline                          TSC-DEADLINE   [Missing]
|- TSX Force Abort MSR Register                            TSX-ABORT   [Missing]
|- TSX Suspend Load Address Tracking                       TSX-LDTRK   [Missing]
|- User-Mode Instruction Prevention                             UMIP   [Capable]
|- Virtual Mode Extension                                        VME   [Capable]
|- Virtual Machine Extensions                                    VMX   [Missing]
|- Write Back & Do Not Invalidate Cache                     WBNOINVD   [Capable]
|- Extended xAPIC Support                                     x2APIC   [  xAPIC]
|- AVIC controller for x2APIC                                 x2AVIC   [Capable]
|- XSAVE/XSTOR States                                          XSAVE   [Capable]
|- xTPR Update Control                                          xTPR   [Missing]
|- Extended Operation Support                                    XOP   [Missing]
Mitigation mechanisms
|- Indirect Branch Restricted Speculation                       IBRS   [Capable]
   |- IBRS Always-On preferred by processor                            [ Unable]
   |- IBRS preferred over software solution                            [Capable]
   |- IBRS provides same speculation limits                            [Capable]
|- Indirect Branch Prediction Barrier                           IBPB   [Capable]
|- Single Thread Indirect Branch Predictor                     STIBP   [ Enable]
|- Speculative Store Bypass Disable                             SSBD   [Capable]
   |- SSBD use VIRT_SPEC_CTRL register                                 [ Unable]
   |- SSBD not needed on this processor                                [ Unable]
|- No Branch Type Confusion                                   BTC_NO   [Capable]
|- BTC on Non-Branch instruction                            BTC-NOBR   [Capable]
|- Limited Early Redirect Window                            AGENPICK   [ Unable]
|- Arch - No Fast Predictive Store Forwarding                   PSFD   [Capable]
|- Arch - Enhanced Predictive Store Forwarding                  EPSF   [Capable]
|- Arch - Cross Processor Information Leak                XPROC_LEAK   [ Unable]
Security Features
|- CET Shadow Stack features                                  CET-SS   [Capable]
|- Secure Init and Jump with Attestation                      SKINIT   [Capable]
|- Secure Encrypted Virtualization                               SEV   [Missing]
|- SEV - Encrypted State                                      SEV-ES   [Missing]
|- SEV - Secure Nested Paging                                SEV-SNP   [Missing]
|- Guest Mode Execute Trap                                      GMET   [Capable]
|- Supervisor Shadow Stack                                       SSS   [Capable]
|- VM Permission Levels                                         VMPL   [Missing]
|- VMPL Supervisor Shadow Stack                             VMPL-SSS   [Missing]
|- Secure Memory Encryption                                      SME   [Capable]
|- Transparent SME                                              TSME   [ Enable]
|- Secure Multi-Key Memory Encryption                         SME-MK   [Missing]
|- DRAM Data Scrambling                                    Scrambler   [ Enable]

Technologies
|- Instruction Cache Unit
   |- L1 IP Prefetcher                                          L1 HW IP   < ON>
|- Data Cache Unit
   |- L1 Prefetcher                                                L1 HW   < ON>
|- Cache Prefetchers
   |- L2 Prefetcher                                                L2 HW   < ON>
   |- L1 Stride Prefetcher                                     L1 Stride   < ON>
   |- L1 Region Prefetcher                                     L1 Region   < ON>
   |- L1 Burst Prefetch Mode                                    L1 Burst   < ON>
   |- L2 Stream HW Prefetcher                                  L2 Stream   < ON>
   |- L2 Up/Down Prefetcher                                   L2 Up/Down   < ON>
|- System Management Mode                                       SMM-Lock   [ ON]
|- Simultaneous Multithreading                                       SMT   [ ON]
|- PowerNow!                                                         CnQ   [ ON]
|- Core C-States                                                     CCx   [ ON]
|- Core Performance Boost                                            CPB   < ON>
|- Watchdog Timer                                                    WDT   < ON>
|- Virtualization                                                    SVM   [ ON]
   |- I/O MMU                                                      AMD-V   [ ON]
   |- Version                                                     [         0.1]
   |- Hypervisor                                                           [OFF]
   |- Vendor ID                                                   [         N/A]

Performance Monitoring
|- Version                                                        PM       [  2]
|- Counters:          General                   Fixed
|           {  6,  4, 16 } x 48 bits            3 x 64 bits
|- Enhanced Halt State                                           C1E       <OFF>
|- C2 UnDemotion                                                 C2U       < ON>
|- C3 UnDemotion                                                 C3U       < ON>
|- Core C6 State                                                 CC6       < ON>
|- Package C6 State                                              PC6       < ON>
|- Legacy Frequency ID control                                   FID       [OFF]
|- Legacy Voltage ID control                                     VID       [OFF]
|- P-State Hardware Coordination Feedback                MPERF/APERF       [ ON]
|- Core C-States
   |- C-States Base Address                                      BAR   [ 0x413 ]
|- ACPI Processor C-States                                      _CST   [      3]
|- MONITOR/MWAIT
   |- State index:    #0    #1    #2    #3    #4    #5    #6    #7
   |- Sub C-State:     1     2     0     0     0     0     0     0
   |- Monitor-Mwait Extensions                                   EMX   [Capable]
   |- Interrupt Break-Event                                      IBE   [Capable]
|- Core Cycles                                                         [Capable]
|- Instructions Retired                                                [Capable]
|- Reference Cycles                                                    [Capable]
|- Last Level Cache References                                         [Capable]
|- Global Time Stamp Counter                                           [Missing]
|- Data Fabric Performance Counter                                     [Capable]
|- Core Performance Counter                                            [Capable]
|- Processor Performance Control                                _PCT   [ Enable]
|- Performance Supported States                                 _PSS   [      2]
|- Performance Present Capabilities                             _PPC   [      0]
|- Continuous Performance Control                               _CPC   [Missing]

Power, Current & Thermal
|- Temperature Offset:Junction                                 TjMax [ 49:  0 C]
|- CPPC Energy Preference                                        EPP   <    128>
|- Digital Thermal Sensor                                        DTS   [Capable]
|- Power Limit Notification                                      PLN   [Missing]
|- Package Thermal Management                                    PTM   [Missing]
|- Thermal Monitor 1                                             TTP   [ Enable]
|- Thermal Monitor 2                                             HTC   [ Enable]
|- Thermal Design Power                                          TDP   [Missing]
   |- Minimum Power                                              Min   [Missing]
   |- Maximum Power                                              Max   [Missing]
|- Thermal Design Power                                      Package   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
   |- Power Limit                                                PL2   [    0 W]
   |- Time Window                                                TW2   [   0 ns]
|- Thermal Design Power                                         Core   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
|- Thermal Design Power                                       Uncore   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
|- Thermal Design Power                                         DRAM   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
|- Thermal Design Power                                     Platform   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
   |- Power Limit                                                PL2   [    0 W]
   |- Time Window                                                TW2   [   0 ns]
|- Package Power Tracking                                        PPT   [Missing]
|- Electrical Design Current                                     EDC   [Missing]
|- Thermal Design Current                                        TDC   [Missing]
|- Core Thermal Point
|- Package Thermal Point
   |- Thermal Monitor Trip                                     Limit   [  115 C]
   |- HTC Temperature Limit                                    Limit   [  127 C]
   |- HTC Temperature Hysteresis                           Threshold   [    2 C]
|- Units
   |- Power                                               watt   [      Missing]
   |- Energy                                             joule   [  0.000015259]
   |- Window                                            second   [  0.000976562]

                              Zen UMC  [14E0]
Controller #0                                                Dual Channel
 Bus Rate  3000 MHz       Bus Speed 1236 MHz           DDR5 Speed 2472 MT/s

 Cha   CL  RCDr RCDw  RP  RAS   RC  RRDs RRDl FAW  WTRs WTRl  WR  clRR clWW
  #0   30   40   40   40   96  137    8   15   32    8   30   96    8   23
  #1   30   40   40   40   96  137    8   15   32    8   30   96    8   23
      CWL  RTP RdWr WrRd scWW sdWW ddWW scRR sdRR ddRR drRR drWW drWR drRRD
  #0   28   23   22    8    1   11   11    1   11   11    0    0    0    0
  #1   28   23   23    8    1   11   11    1   11   11    0    0    0    0
      REFI RFC1 RFC2 RFCsb RCPB RPPB BGS:Alt  Ban  Page  CKE  CMD  GDM  ECC
  #0 11677  312  192  391   0    0    ON OFF  R0W0   0    0   1T    ON   0
  #1 11677  312  192  391   0    0    ON OFF  R0W0   0    0   1T    ON   0
      MRD:PDA   MOD:PDA  WRMPR STAG PDM RDDATA WRD  WRL  RDL  XS   XP CPDED
  #0   42  32    42  32    24    7 0:F:0   18   6   16   36  914   23   15
  #1   42  32    42  32    24    7 0:F:0   18   6   16   36  914   23   15

 DIMM Geometry for channel #0
      Slot Bank Rank     Rows   Columns    Memory Size (MB)
       #0
       #1    32    1     65536      1024          16384    F5-6000J3040G32G
 DIMM Geometry for channel #1
      Slot Bank Rank     Rows   Columns    Memory Size (MB)
       #0
       #1    32    1     65536      1024          16384    F5-6000J3040G32G

edit: the reported DDR5 Speed 2472 MT/s looks wrong (see dmidecode):

sudo dmidecode --type 17 | grep Speed

    Speed: 4800 MT/s
    Configured Memory Speed: 6000 MT/s
    Speed: 4800 MT/s
    Configured Memory Speed: 6000 MT/s

@cyring
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cyring commented Nov 19, 2024

https://github.com/cyring/CoreFreq/tree/develop doesn't seem to like my kernel linux-cachyos-autofdo 6.12.rc7-1: make.log

The make log shows '/usr/src/corefreq-1.98.1.r0.ge8fe368'
But the develop branch is currently 1.98.6
However I will try some non-regression tests with latest Cachy

I can see that your last build is now showing the UMC, some Uncore ratios, the IOMMU.

Remaining issues

  • The DIMM size is wrong (compared to kernel reported size)

  • The estimated baseclock has suddenly fall down to 41 Mhz
    This is something I had fixed for 9950X in this issue

    Since Zen5, specification of coefficient of frequency CpuFid has been expand to 12 bits and it is handled by function AMD_Zen_CoreCOF()

    But for some reasons your Processor has not follow the switch() case of Family 0xB as I have programmed it for 9950X

    Can you dump the first three P-State registers ?

rdmsr -ax 0xC0010064
rdmsr -ax 0xC0010065
rdmsr -ax 0xC0010066

@notpentadactyl
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  But for some reasons your Processor has not follow the `switch()` case of Family `0xB` as I have programmed it for 9950X
  Can you dump the first three P-State registers ?

rdmsr -ax 0xC0010064
800000004bf243ac
800000004bf243ac
800000004bf243ac
800000004bf243ac
800000004bf243ac
800000004bf243ac
800000004bf243ac
800000004bf243ac
800000004bf243ac
800000004bf243ac
800000004bf243ac
800000004bf243ac
800000004bf243ac
800000004bf243ac
800000004bf243ac
800000004bf243ac

rdmsr -ax 0xC0010065
80000000479e4258
80000000479e4258
80000000479e4258
80000000479e4258
80000000479e4258
80000000479e4258
80000000479e4258
80000000479e4258
80000000479e4258
80000000479e4258
80000000479e4258
80000000479e4258
80000000479e4258
80000000479e4258
80000000479e4258
80000000479e4258

rdmsr -ax 0xC0010066
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

@cyring
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cyring commented Nov 19, 2024 •
edited
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@notpentadactyl

Found the issue in 0x800000004bf243ac

1000000000000000000000000000000001001011111100100100001110101100

where I was expecting bits [14-8] to be greater than 0b111 but 9800X3D is 0b000011
I will submit a fix soon.

@cyring
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cyring commented Nov 19, 2024

edit: the reported DDR5 Speed 2472 MT/s

Yes, it is linked with the COF function whom fix is in progress.

@cyring
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cyring commented Nov 19, 2024

@notpentadactyl Hello,

For your testings, a fix is available in commit c574ab1 of develop branch
It provides both reading and programming the frequency ratio within Zen5 P-State.

Save you files before this test. Processor may freeze.

To modify a P-State:

1- Disable Core Performance Boost in the Technologies window
2024-11-19-213104_646x356_scrot

2- In Processor window, go to the P-State and press [Enter]
2024-11-19-213216_623x321_scrot

3- In the opened window, keep the top row 1C selected for whole processor (aka all cores)
2024-11-19-213436_381x485_scrot

4- At this time of the test, just add carefully one bin to the ratio.
(My case for example, I'm going from 28 to 29)
Press [Enter] to submit ratio.
2024-11-19-213631_242x948_scrot

5- Window is refreshed with new ratio. Press [Escape]
2024-11-19-213826_375x486_scrot

6- P-State is also updated in Processor window
2024-11-19-213940_624x319_scrot

7- CPB can now be restored to enabled
2024-11-19-214039_494x351_scrot

If things are OK, P-state have been programmed; Base Clock should still be evaluated to 100 Mhz

@cyring cyring mentioned this issue Nov 20, 2024
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@cyring
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cyring commented Nov 20, 2024

https://github.com/cyring/CoreFreq/tree/develop doesn't seem to like my kernel linux-cachyos-autofdo 6.12.rc7-1:
make.log

About CachyOS; here is how I have built and run CoreFreq with.

  1. CachyOS on top of ArchLinux
git clone [email protected]:CachyOS/linux-cachyos.git

cd linux-cachyos/linux-cachyos-autofdo/

makepkg -cCsfir

ls /boot/
initramfs-linux-cachyos-autofdo-fallback.img
initramfs-linux-cachyos-autofdo.img
vmlinuz-linux-cachyos-autofdo
  1. Install CachyOS in EFI
cd /efi/loader/entries/

cat cachyos.conf
title   Arch Linux [CachyOS]
linux   /EFI/Linux/vmlinuz-linux-cachyos-autofdo
initrd  /EFI/Linux/amd-ucode.img
initrd  /EFI/Linux/initramfs-linux-cachyos-autofdo.img
options root=/dev/disk/by-label/root rw quiet break=n add_efi_memmap loglevel=3 rd.systemd.show_status=auto rd.udev.log-priority=3 consoleblank=0 vt.color=0x03 modprobe.blacklist=pcspkr,joydev,mousedev audit=0 amdgpu.ppfeaturemask=0xffffffff initcall_blacklist=acpi_cpufreq_init amd_pstate.shared_mem=1 idle=halt amd_pstate=guided
  • Boot CachyOS kernel
  1. Build CoreFreq
git clone -b develop [email protected]:cyring/CoreFreq.git

cd CoreFreq
make clean
make -j CC=clang LD=ld.lld
  1. Run CoreFreq
## as root
insmod build/corefreqk.ko
./build/corefreqd -d

## as User
./build/corefreq-cli

2024-11-20-133937_644x940_scrot

@notpentadactyl
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notpentadactyl commented Nov 20, 2024 •
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@cyring thanks, seem to work, in this example I went from 30 to 31.

image

Memory controller also looks better:

image

Anything else I should check?

edit: I guess the individual core temps are wrong, they all show the same, hwinfo on windows looks more accurate.

@cyring
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cyring commented Nov 20, 2024

@cyring thanks, seem to work, in this example I went from 30 to 31.

image

Memory controller also looks better:

image

Anything else I should check?

edit: I guess the individual core temps are wrong, they all show the same, hwinfo on windows looks more accurate.

Happy to see the change worked fine.
I'm gonna merge it into master branch

DIMM size is still something I have to fix.

About temperature sensors, at most CoreFreq can provide values per CCX or CCD cluster.
Could you stress various single CPU and check if high temp is the same for the same cluster group ?

@notpentadactyl
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DIMM size is still something I have to fix.

About temperature sensors, at most CoreFreq can provide values per CCX or CCD cluster. Could you stress various single CPU and check if high temp is the same for the same cluster group ?

image

I guess it kinda works.

Bus Rate on Memory Controller is empty, unsure what it even is, but probably should show 3000 MHz?

@cyring
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cyring commented Nov 20, 2024 •
edited
Loading

DIMM size is still something I have to fix.
About temperature sensors, at most CoreFreq can provide values per CCX or CCD cluster. Could you stress various single CPU and check if high temp is the same for the same cluster group ?

image

I guess it kinda works.

Bus Rate on Memory Controller is empty, unsure what it even is, but probably should show 3000 MHz?

  • Unfortunately we are only getting the same temperature for all cores. They belong to a single CCD.
    About accuracy, I wonder if your temperature reading with CoreFreq differs a lot or not from your Windows tools ?

  • Bus rate: indeed it has to show 3000 MHz like your previous output.

    • Is it also missing in corefreq-cli -M ?
    • Can it be a UI bug only ?
  • Edit: was my above CachyOS procedure helpful to solve your build issue ?

@notpentadactyl
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DIMM size is still something I have to fix.
About temperature sensors, at most CoreFreq can provide values per CCX or CCD cluster. Could you stress various single CPU and check if high temp is the same for the same cluster group ?

image
I guess it kinda works.
Bus Rate on Memory Controller is empty, unsure what it even is, but probably should show 3000 MHz?

* Unfortunately we are only getting the same temperature for all cores. They belong to a single CCD.
  About accuracy, I wonder if your temperature reading with _CoreFreq_ differs a lot or not from your Windows tools ?

No, temps are close, I was just talking about per core temps, which is something hwinfo can do, but not too important. 👍

* Bus rate: indeed it has to show `3000 MHz` like your previous [output](https://github.com/cyring/CoreFreq/issues/517#issuecomment-2485866099).
  
  * Is it also missing in `corefreq-cli -M` ?
  * Can it be a UI bug only ?

You are correct!

./build/corefreq-cli -M

                              Zen UMC  [14E0]
Controller #0                                                Dual Channel
 Bus Rate  3000 MHz       Bus Speed 3000 MHz           DDR5 Speed 6000 MT/s

 Cha   CL  RCDr RCDw  RP  RAS   RC  RRDs RRDl FAW  WTRs WTRl  WR  clRR clWW
  #0   30   40   40   40   96  137    8   15   32    8   30   96    8   23
  #1   30   40   40   40   96  137    8   15   32    8   30   96    8   23
      CWL  RTP RdWr WrRd scWW sdWW ddWW scRR sdRR ddRR drRR drWW drWR drRRD
  #0   28   23   22    8    1   11   11    1   11   11    0    0    0    0
  #1   28   23   23    8    1   11   11    1   11   11    0    0    0    0
      REFI RFC1 RFC2 RFCsb RCPB RPPB BGS:Alt  Ban  Page  CKE  CMD  GDM  ECC
  #0 11677  312  192  391   0    0    ON OFF  R0W0   0    0   1T    ON   0
  #1 11677  312  192  391   0    0    ON OFF  R0W0   0    0   1T    ON   0
      MRD:PDA   MOD:PDA  WRMPR STAG PDM RDDATA WRD  WRL  RDL  XS   XP CPDED
  #0   42  32    42  32    24    7 0:F:0   18   6   16   36  914   23   15
  #1   42  32    42  32    24    7 0:F:0   18   6   16   36  914   23   15

 DIMM Geometry for channel #0
      Slot Bank Rank     Rows   Columns    Memory Size (MB)
       #0
       #1    32    1     65536      1024          16384    F5-6000J3040G32G
 DIMM Geometry for channel #1
      Slot Bank Rank     Rows   Columns    Memory Size (MB)
       #0
       #1    32    1     65536      1024          16384    F5-6000J3040G32G

* Edit: was my above CachyOS procedure helpful to solve your build issue ?

Yeah, I was tying to use the aur git package but failed. I think it is mostly the make patch that is broken with current develop branch.

@cyring
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cyring commented Nov 20, 2024

@notpentadactyl
I don't how to reproduce the UI issue with missing Bus Rate

Can you tell a bit more about which Terminal, which Desktop Environment or Window Manager ?

Is moving selection cursor to missing cell makes value appeared ?

Can try corefreq-cli in a plain XTerm and see if issue happens ?

@notpentadactyl
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@notpentadactyl I don't how to reproduce the UI issue with missing Bus Rate

Can you tell a bit more about which Terminal, which Desktop Environment or Window Manager ?

alacritty 0.14.0 (22a44757)
KDE Plasma 6.2.3 (kwin 6.2.3)

Happens in Konsole 24.08.3 too.

Is moving selection cursor to missing cell makes value appeared ?

No.

Can try corefreq-cli in a plain XTerm and see if issue happens ?

corefreq-cli_xterm.mp4

Also unsure why it is no longer reporting 3000 MHz/6000 MT/s (corefreq-cli -M does the same).

~/git/CoreFreq develop ❯ ./build/corefreq-cli -M | grep Bus
 Bus Rate  3000 MHz       Bus Speed 2997 MHz           DDR5 Speed 5994 MT/s

Here is dmidecode:

	Speed: 4800 MT/s
	Configured Memory Speed: 6000 MT/s
	Speed: 4800 MT/s
	Configured Memory Speed: 6000 MT/s

@cyring
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cyring commented Nov 20, 2024 •
edited
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@notpentadactyl I don't how to reproduce the UI issue with missing Bus Rate
Can you tell a bit more about which Terminal, which Desktop Environment or Window Manager ?

alacritty 0.14.0 (22a44757) KDE Plasma 6.2.3 (kwin 6.2.3)

Happens in Konsole 24.08.3 too.

Is moving selection cursor to missing cell makes value appeared ?

No.

Can try corefreq-cli in a plain XTerm and see if issue happens ?

corefreq-cli_xterm.mp4
Also unsure why it is no longer reporting 3000 MHz/6000 MT/s (corefreq-cli -M does the same).

~/git/CoreFreq develop ❯ ./build/corefreq-cli -M | grep Bus
 Bus Rate  3000 MHz       Bus Speed 2997 MHz           DDR5 Speed 5994 MT/s

Here is dmidecode:

	Speed: 4800 MT/s
	Configured Memory Speed: 6000 MT/s
	Speed: 4800 MT/s
	Configured Memory Speed: 6000 MT/s

Thanks, it helps a lot.

I think UI is rendering an empty cell where freq is the word behind the window and it has been fused in foreground.
I have to find a way to reproduce this issue.

Bus speed and DDR speed are based on Bus rate, normalized with the Processor base clock. That's why you're getting respectively 2997 and 5994

@cyring
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cyring commented Nov 21, 2024 •
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@notpentadactyl Hi,

Looking at the video:
Had the monitoring been stopped and started while Memory Controller window being displayed ?
For example, using shortkeys } and {

@cyring
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cyring commented Nov 21, 2024

Edit: is the cell also emptied if you run the UI into the physical console ?
I mean the console you access with combination keys Alt + Shift + digit

@notpentadactyl
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@notpentadactyl Hi,

Looking at the video: Had the monitoring been stopped and started while Memory Controller window being displayed ? For example, using shortkeys } and {

No.

Edit: is the cell also emptied if you run the UI into the physical console ? I mean the console you access with combination keys Alt + Shift + digit

I switched to tty3 with Alt + Ctrl + F3 (I assume this is what you meant?). Same issue there.

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