added netgen pull request efabless#33

d-m-bailey · Oct 15, 2021 · efc7759 · efc7759
1 parent 74325dc
commit efc7759
Showing 1 changed file with 6 additions and 3 deletions.
diff --git a/docs/source/lvs.rst b/docs/source/lvs.rst
@@ -135,6 +135,9 @@ storage
     $PDK_ROOT/sky130A/libs.ref/sky130_sram_macros/spice/sram_1rw1r_32_256_8_sky130.spice
 
 2. Disconnected substrate connections yield mismatches. 
+
+   NB: Merging netgen pull request #33 will remedy the problem without having to explicity flatten the suggested cells.
+
    The ``pmos_m1_w0_550_sli_dli`` is automatically flattened in to ``precharge_1``, but the ``VSUBS`` connection is not recognized as a disconnected node. 
    Maybe recalculate connectivity after flattening in netgen?::
 
@@ -259,9 +262,9 @@ storage
         unmatched pins = 0
         property failures = 0
 
-   NB: Merging netgen pull request #33 will remedy the problem without having to explicity flatten the above cells.
-
-3. ``control_logic_r`` has been flattened in the layout, but not in the netlist::
+3. ``control_logic_r`` has been flattened in the layout, but not in the netlist.
+   
+   NB: Merging netgen pull request #33 will remedy the problem without having to explicity flatten the suggested cells::
 
     Subcircuit summary:
     Circuit 1: control_logic_r                 |Circuit 2: control_logic_r