From b2085370561b68c67343afb42649fc9434227b9d Mon Sep 17 00:00:00 2001 From: manarabdelaty Date: Mon, 25 Oct 2021 20:47:00 +0200 Subject: [PATCH 1/2] Update rcx target --- Makefile | 9 +++-- utils/rcx.sh | 103 +++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 108 insertions(+), 4 deletions(-) create mode 100644 utils/rcx.sh diff --git a/Makefile b/Makefile index f5b7702cd..fec7010eb 100644 --- a/Makefile +++ b/Makefile @@ -60,7 +60,7 @@ SPECIAL_VOLTAGE_LIBRARY ?= sky130_fd_sc_hvl IO_LIBRARY ?= sky130_fd_io PRIMITIVES_LIBRARY ?= sky130_fd_pr SKYWATER_COMMIT ?= c094b6e83a4f9298e47f696ec5a7fd53535ec5eb -OPEN_PDKS_COMMIT ?= 6c05bc48dc88784f9d98b89d6791cdfd91526676 +OPEN_PDKS_COMMIT ?= 14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad INSTALL_SRAM ?= disabled .DEFAULT_GOAL := ship @@ -483,13 +483,14 @@ $(RCX_BLOCKS): rcx-% : ./def/%.def }\ };\ set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um;\ - read_liberty -min ${PDK_ROOT}/sky130A/libs.ref/${STD_CELL_LIBRARY}/lib/${STD_CELL_LIBRARY}__ff_n40C_1v95.lib;\ - read_liberty -max ${PDK_ROOT}/sky130A/libs.ref/${STD_CELL_LIBRARY}/lib/${STD_CELL_LIBRARY}__ss_100C_1v60.lib;\ + read_liberty $(PDK_ROOT)/sky130A/libs.ref/$(STD_CELL_LIBRARY)/lib/$(STD_CELL_LIBRARY)__tt_025C_1v80.lib;\ read_verilog ./verilog/gl/$*.v;\ link_design $*;\ read_spef ./def/tmp/$*.spef;\ read_sdc -echo ./openlane/$*/base.sdc;\ - report_checks -fields {capacitance slew input_pins nets fanout} -path_delay min_max;\ + write_sdf $*.sdf;\ + report_checks -fields {capacitance slew input_pins nets fanout} -path_delay min_max -group_count 1000;\ + report_check_types -max_slew -max_capacitance -max_fanout -violators;\ " > ./def/tmp/or_sta_$*.tcl docker run -it -v $(OPENLANE_ROOT):/openLANE_flow -v $(PDK_ROOT):$(PDK_ROOT) -v $(PWD):/caravel -e PDK_ROOT=$(PDK_ROOT) -u $(shell id -u $(USER)):$(shell id -g $(USER)) $(OPENLANE_IMAGE_NAME) \ sh -c "cd /caravel; openroad -exit ./def/tmp/or_sta_$*.tcl |& tee ./def/tmp/or_sta_$*.log" diff --git a/utils/rcx.sh b/utils/rcx.sh new file mode 100644 index 000000000..a5249e9f7 --- /dev/null +++ b/utils/rcx.sh @@ -0,0 +1,103 @@ +# RCX Extraction +# ./rcx.sh --input_def spm.def --input_sdc spm.sdc --input_gl spm.v --top_module spm +while [ "$1" != "" ]; do + case $1 in + -d | --input_def ) + shift + input_def=$1 + ;; + -d | --input_sdc ) + shift + input_sdc=$1 + ;; + -v | --input_gl ) + shift + input_gl=$1 + ;; + -t | --top_module ) + shift + top_module=$1 + ;; + -l | --input_lefs ) + shift + input_lefs=$1 + ;; + * ) + exit 1 + esac + shift +done +​ +output_directory=$PWD/$top_module +OPENLANE_IMAGE_NAME=efabless/openlane:2021.09.16_03.28.21 +​ +echo "Running RC Extraction on $input_def" +mkdir -p $output_directory +# merge techlef and standard cell lef files +python3 $OPENLANE_ROOT/scripts/mergeLef.py -i $PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd.tlef $PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hd/lef/*.lef -o $output_directory/merged.lef +echo "\ + read_liberty $PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib;\ + set std_cell_lef $output_directory/merged.lef;\ + if {[catch {read_lef \$std_cell_lef} errmsg]} {\ + puts stderr \$errmsg;\ + exit 1;\ + };\ + if { \"$input_lefs\" eq \"\"} {\ + } else {\ + foreach lef_file [list $input_lefs] {\ + if {[catch {read_lef \$lef_file} errmsg]} {\ + puts stderr \$errmsg;\ + exit 1;\ + }\ + };\ + };\ + if {[catch {read_def -order_wires $input_def} errmsg]} {\ + puts stderr \$errmsg;\ + exit 1;\ + };\ + read_sdc $input_sdc;\ + set_propagated_clock [all_clocks];\ + set rc_values \"mcon 9.249146E-3,via 4.5E-3,via2 3.368786E-3,via3 0.376635E-3,via4 0.00580E-3\";\ + set vias_rc [split \$rc_values ","];\ + foreach via_rc \$vias_rc {\ + set layer_name [lindex \$via_rc 0];\ + set resistance [lindex \$via_rc 1];\ + set_layer_rc -via \$layer_name -resistance \$resistance;\ + };\ + set_wire_rc -signal -layer met2;\ + set_wire_rc -clock -layer met5;\ + define_process_corner -ext_model_index 0 X;\ + extract_parasitics -ext_model_file $PDK_ROOT/sky130A/libs.tech/openlane/rcx_rules.info -corner_cnt 1 -max_res 50 -coupling_threshold 0.1 -cc_model 10 -context_depth 5;\ + write_spef $output_directory/$top_module.spef" > $output_directory/or_rcx_$top_module.tcl +## Generate Spef file +docker run -it -v $OPENLANE_ROOT:/openLANE_flow -v $PDK_ROOT:$PDK_ROOT -v $PWD:/project -v $output_directory:$output_directory -e PDK_ROOT=$PDK_ROOT $OPENLANE_IMAGE_NAME \ +sh -c " cd /project ; openroad -exit $output_directory/or_rcx_$top_module.tcl |& tee $output_directory/or_rcx_$top_module.log" +## Run OpenSTA +echo "\ + set std_cell_lef $output_directory/merged.lef;\ + if {[catch {read_lef \$std_cell_lef} errmsg]} {\ + puts stderr \$errmsg;\ + exit 1;\ + };\ + if { \"$input_lefs\" eq \"\"} {\ + } else {\ + foreach lef_file [list $input_lefs] {\ + if {[catch {read_lef \$lef_file} errmsg]} {\ + puts stderr \$errmsg;\ + exit 1;\ + }\ + };\ + };\ + set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um;\ + read_liberty $PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib;\ + read_verilog $input_gl;\ + link_design $top_module;\ + read_spef $output_directory/$top_module.spef;\ + read_sdc -echo $input_sdc;\ + write_sdf $top_module.sdf;\ + report_checks -fields {capacitance slew input_pins nets fanout} -path_delay min_max -group_count 1000;\ + report_check_types -max_slew -max_capacitance -max_fanout -violators;\ + " > $output_directory/or_sta_$top_module.tcl +​ +docker run -it -v $OPENLANE_ROOT:/openLANE_flow -v $PDK_ROOT:$PDK_ROOT -v $PWD:/project -v $output_directory:$output_directory -e PDK_ROOT=$PDK_ROOT $OPENLANE_IMAGE_NAME \ +sh -c "cd /project; openroad -exit $output_directory/or_sta_$top_module.tcl |& tee $output_directory/or_sta_$top_module.log" \ No newline at end of file From adf8a044e19d726f0679029c99b51c2ad44b8b29 Mon Sep 17 00:00:00 2001 From: manarabdelaty Date: Mon, 25 Oct 2021 21:06:23 +0200 Subject: [PATCH 2/2] Update OL tag --- openlane/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openlane/Makefile b/openlane/Makefile index 93988410a..d1ac633fa 100644 --- a/openlane/Makefile +++ b/openlane/Makefile @@ -18,7 +18,7 @@ BLOCKS = $(shell find * -maxdepth 0 -type d) CONFIG = $(foreach block,$(BLOCKS), ./$(block)/config.tcl) CLEAN = $(foreach block,$(BLOCKS), clean-$(block)) -OPENLANE_TAG ?= 2021.09.19_20.25.16 +OPENLANE_TAG ?= mpw-3a OPENLANE_IMAGE_NAME ?= efabless/openlane:$(OPENLANE_TAG) OPENLANE_BASIC_COMMAND = "cd /project/openlane && flow.tcl -design ./$* -save_path .. -save -tag $* -overwrite" OPENLANE_INTERACTIVE_COMMAND = "cd /project/openlane && flow.tcl -it -file ./$*/interactive.tcl" @@ -71,7 +71,7 @@ ifeq ($(OPENLANE_ROOT),) @echo "Please export OPENLANE_ROOT" @exit 1 endif - git clone https://github.com/The-OpenROAD-Project/OpenLane --branch=$(OPENLANE_TAG) --depth=1 $(OPENLANE_ROOT) && \ + git clone https://github.com/efabless/OpenLane --branch=$(OPENLANE_TAG) --depth=1 $(OPENLANE_ROOT) && \ cd $(OPENLANE_ROOT) && \ export IMAGE_NAME=efabless/openlane:$(OPENLANE_TAG) && \ make openlane