Skip to content

Commit

Permalink
Merge pull request #29 from efabless/develop
Browse files Browse the repository at this point in the history
mpw-one-b
  • Loading branch information
agorararmard authored Dec 15, 2020
2 parents 9ed16cc + 4d78284 commit f48448d
Show file tree
Hide file tree
Showing 314 changed files with 5,161,833 additions and 5,429,204 deletions.
3 changes: 2 additions & 1 deletion .travis.yml
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
# Copyright 2020 Efabless Corporation
# SPDX-FileCopyrightText: 2020 Efabless Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
Expand All @@ -11,6 +11,7 @@
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# SPDX-License-Identifier: Apache-2.0

language: minimal

Expand Down
3 changes: 2 additions & 1 deletion .travisCI/runPrecheck.sh
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
#!/bin/bash
# Copyright 2020 Efabless Corporation
# SPDX-FileCopyrightText: 2020 Efabless Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
Expand All @@ -12,6 +12,7 @@
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# SPDX-License-Identifier: Apache-2.0
export TARGET_PATH=$(pwd)
cd ..
export PDK_ROOT=$(pwd)/pdks
Expand Down
3 changes: 2 additions & 1 deletion .travisCI/travisBuild.sh
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
#!/bin/bash
# Copyright 2020 Efabless Corporation
# SPDX-FileCopyrightText: 2020 Efabless Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
Expand All @@ -12,6 +12,7 @@
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# SPDX-License-Identifier: Apache-2.0

export TARGET_PATH=$(pwd)
git clone https://github.com/efabless/open_mpw_precheck.git
Expand Down
33 changes: 30 additions & 3 deletions Makefile
Original file line number Diff line number Diff line change
@@ -1,4 +1,20 @@
# cannot commit files larger than 100 MB to GitHub
# SPDX-FileCopyrightText: 2020 Efabless Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# SPDX-License-Identifier: Apache-2.0

# cannot commit files larger than 100 MB to GitHub
FILE_SIZE_LIMIT_MB = 100
LARGE_FILES := $(shell find ./gds -type f -name "*.gds")
LARGE_FILES += $(shell find . -type f -size +$(FILE_SIZE_LIMIT_MB)M -not -path "./.git/*" -not -path "./gds/*" -not -path "./openlane/*")
Expand All @@ -8,14 +24,13 @@ LARGE_FILES_GZ := $(addsuffix .gz, $(LARGE_FILES))
ARCHIVES := $(shell find . -type f -name "*.gz")
ARCHIVE_SOURCES := $(basename $(ARCHIVES))


# PDK setup configs
THREADS ?= $(shell nproc)
STD_CELL_LIBRARY ?= sky130_fd_sc_hd
SPECIAL_VOLTAGE_LIBRARY ?= sky130_fd_sc_hvl
IO_LIBRARY ?= sky130_fd_io
SKYWATER_COMMIT ?= 3d7617a1acb92ea883539bcf22a632d6361a5de4
OPEN_PDKS_COMMIT ?= b184e85de7629b8c87087a46b79eb45e7f7cd383
OPEN_PDKS_COMMIT ?= 32cdb2097fd9a629c91e8ea33e1f6de08ab25946

.DEFAULT_GOAL := ship
# We need portable GDS_FILE pointers...
Expand Down Expand Up @@ -101,6 +116,7 @@ $(PDK_ROOT)/skywater-pdk:
.PHONY: skywater-pdk
skywater-pdk: check-env $(PDK_ROOT)/skywater-pdk
cd $(PDK_ROOT)/skywater-pdk && \
git checkout master && git pull && \
git checkout -qf $(SKYWATER_COMMIT)

.PHONY: skywater-library
Expand All @@ -118,6 +134,7 @@ $(PDK_ROOT)/open_pdks:
.PHONY: open_pdks
open_pdks: check-env $(PDK_ROOT)/open_pdks
cd $(PDK_ROOT)/open_pdks && \
git checkout master && git pull && \
git checkout -qf $(OPEN_PDKS_COMMIT)

.PHONY: build-pdk
Expand All @@ -134,6 +151,16 @@ build-pdk: check-env $(PDK_ROOT)/open_pdks $(PDK_ROOT)/skywater-pdk
$(MAKE) && \
$(MAKE) install-local

.RECIPE: manifest
manifest:
cd verilog/rtl/ && \
find * -type f ! -name "user_*.v" ! -name "manifest" ! -name "README" ! -name "defines.v" -exec shasum {} \; > manifest && \
cd ../../maglef/ && \
shasum *.mag > manifest && \
cd ../mag/ && \
shasum caravel.mag .magicrc > manifest


check-env:
ifndef PDK_ROOT
$(error PDK_ROOT is undefined, please export it before running make)
Expand Down
42 changes: 34 additions & 8 deletions README.md
Original file line number Diff line number Diff line change
@@ -1,8 +1,25 @@
<!---
# SPDX-FileCopyrightText: 2020 Efabless Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# SPDX-License-Identifier: Apache-2.0
-->
# CIIC Harness

A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.

<p align=center>
<p align="center">
<img src="/doc/ciic_harness.png" width="75%" height="75%">
</p>

Expand All @@ -21,7 +38,7 @@ make uncompress
Then you need to install the open_pdks prerequisite:
- [Magic VLSI Layout Tool](http://opencircuitdesign.com/magic/index.html) is needed to run open_pdks -- version >= 8.3.60*

> \* Note: You can avoid the need for the magic prerequisite by using the openlane docker to do the installation step in open_pdks. This [file](https://github.com/efabless/openlane/blob/develop/travisCI/travisBuild.sh) shows how.
> \* Note: You can avoid the need for the magic prerequisite by using the openlane docker to do the installation step in open_pdks. This could be done by cloning [openlane](https://github.com/efabless/openlane/tree/master) and following the instructions given there to use the Makefile.
Install the required version of the PDK by running the following commands:

Expand All @@ -34,14 +51,18 @@ Then, you can learn more about the caravel chip by watching these video:
- Caravel User Project Features -- https://youtu.be/zJhnmilXGPo
- Aboard Caravel -- How to put your design on Caravel? -- https://youtu.be/9QV8SDelURk
- Things to Clarify About Caravel -- What versions to use with Caravel? -- https://youtu.be/-LZ522mxXMw
- You could only use openlane:rc5
- You could only use openlane:rc6
- Make sure you have the commit hashes provided here inside the [Makefile](./Makefile)
## Aboard Caravel:

Your area is the full user_project_wrapper, so feel free to add your project there or create a differnt macro and harden it seperately then insert it into the user_project_wrapper. For example, if your design is analog or you're using a different tool other than OpenLANE.

If you will use OpenLANE to harden your design, go through the instructions in this [README.md][0].

You must copy your synthesized gate-level-netlist for `user_project_wrapper` to `verilog/gl/` and overwrite `user_project_wrapper.v`. Otherwise, you can point to it in [info.yaml](info.yaml).

> Note: If you're using openlane to harden your design, this should happen automatically.
Then, you will need to put your design aboard the Caravel chip. Make sure you have the following:

- [Magic VLSI Layout Tool](http://opencircuitdesign.com/magic/index.html) installed on your machine. We may provide a Dockerized version later.\*
Expand All @@ -56,7 +77,7 @@ export PDK_ROOT=<The place where the installed pdk resides. The same PDK_ROOT us
make
```

This should merge the GDSes using magic and you'll end up with your version of `./gds/caravel.gds`. You should expect hundred of thousands of magic DRC violations with the current "development" state of caravel.
This should merge the GDSes using magic and you'll end up with your version of `./gds/caravel.gds`. You should expect ~90 magic DRC violations with the current "development" state of caravel.

## Running Make using OpenLANE Magic

Expand All @@ -65,7 +86,7 @@ To use the magic installed inside Openlane to complete the final GDS streaming o
```bash
export PDK_ROOT=<The location where the pdk is installed>
export OPENLANE_ROOT=<the absolute path to the openlane directory cloned or to be cloned>
export IMAGE_NAME=<the openlane image name installed on your machine. Preferably openlane:rc5>
export IMAGE_NAME=<the openlane image name installed on your machine. Preferably openlane:rc6>
export CARAVEL_PATH=$(pwd)
```

Expand All @@ -82,7 +103,12 @@ make
exit
```

This should merge the GDSes using magic and you'll end up with your version of `./gds/caravel.gds`. You should expect hundred of thousands of magic DRC violations with the current "development" state of caravel.
This should merge the GDSes using magic and you'll end up with your version of `./gds/caravel.gds`. You should expect ~90 magic DRC violations with the current "development" state of caravel.


## IMPORTANT:

Please make sure to run `make compress` before commiting anything to your repository. Avoid having 2 versions of the gds/user_project_wrapper.gds or gds/caravel.gds one compressed and the other not compressed.

## Required Directory Structure

Expand Down Expand Up @@ -110,7 +136,7 @@ The memory map of the management SoC can be found [here](verilog/rtl/README)
This is the user space. It has limited silicon area (TBD, about 3.1mm x 3.8mm) as well as a fixed number of I/O pads (37) and power pads (10). See [the Caravel premliminary datasheet](doc/caravel_datasheet.pdf) for details.
The repository contains a [sample user project](/verilog/rtl/user_proj_example.v) that contains a binary 32-bit up counter. </br>

<p align=center>
<p align="center">
<img src="/doc/counter_32.png" width="50%" height="50%">
</p>

Expand All @@ -120,4 +146,4 @@ The firmware running on the Management Area SoC, configures the I/O pads used by
3. Configure the User Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles: [LA_Test2](verilog/dv/caravel/user_proj_example/la_test2).

[0]: openlane/README.md
[1]: mpw-one-a.md
[1]: mpw-one-b.md
Loading

0 comments on commit f48448d

Please sign in to comment.