From 3ac55a62d8c1656c7a5c1970166eaaf1789691d2 Mon Sep 17 00:00:00 2001 From: Matt Venn Date: Wed, 18 Nov 2020 16:07:47 +0100 Subject: [PATCH 01/32] add multi project --- verilog/dv/caravel/mgmt_soc/gpio/Makefile | 8 +- .../seven-segment-counter/Makefile | 42 +++ .../seven-segment-counter/seven_segment.c | 70 +++++ .../seven-segment-counter/seven_segment.gtkw | 287 +++++++++++++++++ .../seven-segment-counter/seven_segment_tb.v | 149 +++++++++ .../user_proj_example/vga-clock/Makefile | 42 +++ .../user_proj_example/vga-clock/vga_clock.c | 75 +++++ .../vga-clock/vga_clock.gtkw | 180 +++++++++++ .../vga-clock/vga_clock_tb.v | 133 ++++++++ .../caravel/user_proj_example/ws2812/Makefile | 42 +++ .../caravel/user_proj_example/ws2812/ws2812.c | 68 ++++ .../user_proj_example/ws2812/ws2812.gtkw | 294 ++++++++++++++++++ .../user_proj_example/ws2812/ws2812_tb.v | 149 +++++++++ verilog/rtl/caravel.v | 2 +- verilog/rtl/user_project_wrapper.v | 2 +- 15 files changed, 1537 insertions(+), 6 deletions(-) create mode 100644 verilog/dv/caravel/user_proj_example/seven-segment-counter/Makefile create mode 100644 verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment.c create mode 100644 verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment.gtkw create mode 100644 verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment_tb.v create mode 100644 verilog/dv/caravel/user_proj_example/vga-clock/Makefile create mode 100644 verilog/dv/caravel/user_proj_example/vga-clock/vga_clock.c create mode 100644 verilog/dv/caravel/user_proj_example/vga-clock/vga_clock.gtkw create mode 100644 verilog/dv/caravel/user_proj_example/vga-clock/vga_clock_tb.v create mode 100644 verilog/dv/caravel/user_proj_example/ws2812/Makefile create mode 100644 verilog/dv/caravel/user_proj_example/ws2812/ws2812.c create mode 100644 verilog/dv/caravel/user_proj_example/ws2812/ws2812.gtkw create mode 100644 verilog/dv/caravel/user_proj_example/ws2812/ws2812_tb.v diff --git a/verilog/dv/caravel/mgmt_soc/gpio/Makefile b/verilog/dv/caravel/mgmt_soc/gpio/Makefile index 49bbb0cc..c711aac3 100644 --- a/verilog/dv/caravel/mgmt_soc/gpio/Makefile +++ b/verilog/dv/caravel/mgmt_soc/gpio/Makefile @@ -3,7 +3,7 @@ RTL_PATH = ../../../../rtl IP_PATH = ../../../../ip BEHAVIOURAL_MODELS = ../../ -GCC_PATH?=/ef/apps/bin +TOOLCHAIN_PREFIX?=/ef/apps/bin/riscv32-unknown-elf- PDK_PATH?=/ef/tech/SW/sky130A .SUFFIXES: @@ -23,15 +23,15 @@ hex: ${PATTERN:=.hex} vvp $< %.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s - ${GCC_PATH}/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< + $(TOOLCHAIN_PREFIX)gcc -mabi=ilp32 -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< %.hex: %.elf - ${GCC_PATH}/riscv32-unknown-elf-objcopy -O verilog $< $@ + $(TOOLCHAIN_PREFIX)objcopy -O verilog $< $@ # to fix flash base address sed -i 's/@10000000/@00000000/g' $@ %.bin: %.elf - ${GCC_PATH}/riscv32-unknown-elf-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ + $(TOOLCHAIN_PREFIX)objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ # ---- Clean ---- diff --git a/verilog/dv/caravel/user_proj_example/seven-segment-counter/Makefile b/verilog/dv/caravel/user_proj_example/seven-segment-counter/Makefile new file mode 100644 index 00000000..359c89cf --- /dev/null +++ b/verilog/dv/caravel/user_proj_example/seven-segment-counter/Makefile @@ -0,0 +1,42 @@ +FIRMWARE_PATH = ../.. +RTL_PATH = ../../../../rtl +IP_PATH = ../../../../ip +#MP_PATH = ../../../../rtl/multi_project_harness +BEHAVIOURAL_MODELS = ../../ + +TOOLCHAIN_PREFIX?=/opt/riscv64-unknown-elf-gcc-8.3.0-2020.04.1-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf- +PDK_PATH?=~/work/asic-workshop/pdks/sky130A + +.SUFFIXES: + +PATTERN = seven_segment + +all: ${PATTERN:=.vcd} + +hex: ${PATTERN:=.hex} + +%.vvp: %_tb.v %.hex + iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \ + -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \ + $< -o $@ + +%.vcd: %.vvp + vvp $< + +%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s + $(TOOLCHAIN_PREFIX)gcc -mabi=ilp32 -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< + +%.hex: %.elf + $(TOOLCHAIN_PREFIX)objcopy -O verilog $< $@ + # to fix flash base address + sed -i 's/@10000000/@00000000/g' $@ + +%.bin: %.elf + $(TOOLCHAIN_PREFIX)objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ + +# ---- Clean ---- + +clean: + rm -f *.elf *.hex *.bin *.vvp *.vcd *.log + +.PHONY: clean hex all diff --git a/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment.c b/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment.c new file mode 100644 index 00000000..b5df6e3e --- /dev/null +++ b/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment.c @@ -0,0 +1,70 @@ +#include "../../defs.h" + +/* + IO Test: + - Configures MPRJ pins + - Observes counter value through the LED digits +*/ + +#define reg_mprj_7seg (*(volatile uint32_t*)0x30000200) + +void main() +{ + /* + IO Control Registers + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | + + Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | + + Output: 0000_0110_0000_1111 (0x1809) = GPIO_MODE_MGNT_STD_OUTPUT + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | + + + Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | + + */ + + /* + Inputs + + 0 clock + 1 reset + + + Outputs + + 8:2 seven segment LEDs + */ + + reg_mprj_io_0 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_1 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_6 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT; + + /* Apply configuration */ + reg_mprj_xfer = 1; + while (reg_mprj_xfer == 1); + + // change to project 0 + reg_mprj_slave = 0; + + // use logic analyser to reset the counter + reg_la0_ena = 0x00000000; // bits 31:0 outputs + reg_la0_data = 0x00000001; // reset high is on bit 0 + reg_la0_data = 0x00000000; // low + + // update 7seg compare reg to 10 + reg_mprj_7seg = 10; +} + diff --git a/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment.gtkw b/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment.gtkw new file mode 100644 index 00000000..91e9a67b --- /dev/null +++ b/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment.gtkw @@ -0,0 +1,287 @@ +[*] +[*] GTKWave Analyzer v3.3.108 (w)1999-2020 BSI +[*] Wed Nov 18 13:22:40 2020 +[*] +[dumpfile] "/home/matt/work/asic-workshop/caravel/verilog/dv/caravel/user_proj_example/seven-segment-counter/io_ports.vcd" +[dumpfile_mtime] "Wed Nov 18 13:21:30 2020" +[dumpfile_size] 107734924 +[savefile] "/home/matt/work/asic-workshop/caravel/verilog/dv/caravel/user_proj_example/seven-segment-counter/gpio.gtkw" +[timestart] 187492000 +[size] 2434 1411 +[pos] -1 -1 +*-20.000000 192189000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] seven_segment_tb. +[treeopen] seven_segment_tb.uut. +[treeopen] seven_segment_tb.uut.gpio_control_bidir[0].gpio_in_buf. +[treeopen] seven_segment_tb.uut.gpio_control_in[4].gpio_in_buf. +[treeopen] seven_segment_tb.uut.gpio_control_in[4].gpio_logic_high. +[treeopen] seven_segment_tb.uut.mprj. +[treeopen] seven_segment_tb.uut.mprj.mprj. +[treeopen] seven_segment_tb.uut.mprj.mprj.proj_0. +[treeopen] seven_segment_tb.uut.soc. +[treeopen] seven_segment_tb.uut.soc.housekeeping. +[treeopen] seven_segment_tb.uut.soc.soc. +[treeopen] seven_segment_tb.uut.soc.soc.cpu. +[treeopen] seven_segment_tb.uut.soc.soc.cpu.picorv32_core. +[treeopen] seven_segment_tb.uut.soc.soc.gpio_wb. +[treeopen] seven_segment_tb.uut.soc.soc.mprj_ctrl. +[sst_width] 719 +[signals_width] 682 +[sst_expanded] 1 +[sst_vpaned_height] 862 +@28 +seven_segment_tb.clock +seven_segment_tb.RSTB +@200 +- +@800200 +-wbs +@28 +seven_segment_tb.uut.mprj.mprj.wb_rst_i +seven_segment_tb.uut.mprj.mprj.wb_clk_i +seven_segment_tb.uut.mprj.mprj.wbs_ack_o +@22 +seven_segment_tb.uut.mprj.mprj.wbs_adr_i[31:0] +@28 +seven_segment_tb.uut.mprj.mprj.wbs_cyc_i +@24 +seven_segment_tb.uut.mprj.mprj.wbs_dat_i[31:0] +@22 +seven_segment_tb.uut.mprj.mprj.wbs_dat_o[31:0] +seven_segment_tb.uut.mprj.mprj.wbs_sel_i[3:0] +@28 +seven_segment_tb.uut.mprj.mprj.wbs_stb_i +seven_segment_tb.uut.mprj.mprj.wbs_we_i +seven_segment_tb.uut.mprj.mprj.valid +@24 +seven_segment_tb.uut.mprj.mprj.wstrb[3:0] +@1000200 +-wbs +@800200 +-multi proj control +@28 +seven_segment_tb.uut.soc.soc.mprj_ctrl.mprj_ctrl.xfer_ctrl +@1000200 +-multi proj control +@800200 +-la +@22 +seven_segment_tb.uut.mprj.mprj.la_data_in[127:0] +seven_segment_tb.uut.mprj.mprj.la_data_out[127:0] +seven_segment_tb.uut.mprj.mprj.la_oen[127:0] +@1000200 +-la +@22 +seven_segment_tb.uut.soc.soc.cpu.picorv32_core.next_insn_opcode[31:0] +@200 +- +@800200 +-multi project +@22 +seven_segment_tb.uut.mprj.mprj.active_project[7:0] +@28 +seven_segment_tb.uut.mprj.mprj.wb_rst_i +@c00022 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a/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment_tb.v b/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment_tb.v new file mode 100644 index 00000000..fa59edfd --- /dev/null +++ b/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment_tb.v @@ -0,0 +1,149 @@ +`default_nettype none + +`timescale 1 ns / 1 ps + +`include "caravel.v" +`include "spiflash.v" + +module seven_segment_tb; + reg clock; + reg ext_clock; + reg RSTB; + reg power1, power2; + reg power3, power4; + + wire gpio; + wire [37:0] mprj_io; + wire [6:0] segments; + + assign segments = mprj_io[8:2]; + + // External clock is used by default. Make this artificially fast for the + // simulation. Normally this would be a slow clock and the digital PLL + // would be the fast clock. + + always #12.5 clock <= (clock === 1'b0); + always #6.25 ext_clock <= (ext_clock === 1'b0); + + initial begin + clock = 0; + ext_clock = 0; + end + + // seven seg wants ext clock on gpio0 and reset on gpio1 + assign mprj_io[0] = ext_clock; + assign mprj_io[1] = !RSTB; + + initial begin + $dumpfile("seven_segment.vcd"); + $dumpvars(0, seven_segment_tb); + + // Repeat cycles of 1000 clock edges as needed to complete testbench + repeat (15) begin + repeat (1000) @(posedge clock); + // $display("+1000 cycles"); + end + $display("%c[1;31m",27); + $display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed"); + $display("%c[0m",27); + $finish; + end + + initial begin + // Observe segments counting from 0 to 9 + + wait(segments == 7'b0111111); + wait(segments == 7'b0000110); + wait(segments == 7'b1011011); + wait(segments == 7'b1001111); + wait(segments == 7'b1100110); + wait(segments == 7'b1101101); + wait(segments == 7'b1111100); + wait(segments == 7'b0000111); + wait(segments == 7'b1111111); + wait(segments == 7'b1111111); + wait(segments == 7'b1100111); + + $display("Monitor: Test 1 Mega-Project IO (RTL) Passed"); + $finish; + end + + initial begin + RSTB <= 1'b0; + #2000; + RSTB <= 1'b1; // Release reset + end + + initial begin // Power-up sequence + power1 <= 1'b0; + power2 <= 1'b0; + power3 <= 1'b0; + power4 <= 1'b0; + #200; + power1 <= 1'b1; + #200; + power2 <= 1'b1; + #200; + power3 <= 1'b1; + #200; + power4 <= 1'b1; + end + + /* + always @(mprj_io) begin + #1 $display("MPRJ-IO state = %b ", mprj_io[7:0]); + end + */ + + wire flash_csb; + wire flash_clk; + wire flash_io0; + wire flash_io1; + + wire VDD1V8; + wire VDD3V3; + wire VSS; + + assign VDD3V3 = power1; + assign VDD1V8 = power2; + assign USER_VDD3V3 = power3; + assign USER_VDD1V8 = power4; + assign VSS = 1'b0; + + caravel uut ( + .vddio (VDD3V3), + .vssio (VSS), + .vdda (VDD3V3), + .vssa (VSS), + .vccd (VDD1V8), + .vssd (VSS), + .vdda1 (USER_VDD3V3), + .vdda2 (USER_VDD3V3), + .vssa1 (VSS), + .vssa2 (VSS), + .vccd1 (USER_VDD1V8), + .vccd2 (USER_VDD1V8), + .vssd1 (VSS), + .vssd2 (VSS), + .clock (clock), + .gpio (gpio), + .mprj_io (mprj_io), + .flash_csb(flash_csb), + .flash_clk(flash_clk), + .flash_io0(flash_io0), + .flash_io1(flash_io1), + .resetb (RSTB) + ); + + spiflash #( + .FILENAME("seven_segment.hex") + ) spiflash ( + .csb(flash_csb), + .clk(flash_clk), + .io0(flash_io0), + .io1(flash_io1), + .io2(), // not used + .io3() // not used + ); + +endmodule diff --git a/verilog/dv/caravel/user_proj_example/vga-clock/Makefile b/verilog/dv/caravel/user_proj_example/vga-clock/Makefile new file mode 100644 index 00000000..b53df602 --- /dev/null +++ b/verilog/dv/caravel/user_proj_example/vga-clock/Makefile @@ -0,0 +1,42 @@ +FIRMWARE_PATH = ../.. +RTL_PATH = ../../../../rtl +IP_PATH = ../../../../ip +#MP_PATH = ../../../../rtl/multi_project_harness +BEHAVIOURAL_MODELS = ../../ + +TOOLCHAIN_PREFIX?=/opt/riscv64-unknown-elf-gcc-8.3.0-2020.04.1-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf- +PDK_PATH?=~/work/asic-workshop/pdks/sky130A + +.SUFFIXES: + +PATTERN = vga_clock + +all: ${PATTERN:=.vcd} + +hex: ${PATTERN:=.hex} + +%.vvp: %_tb.v %.hex + iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \ + -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \ + $< -o $@ + +%.vcd: %.vvp + vvp $< + +%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s + $(TOOLCHAIN_PREFIX)gcc -mabi=ilp32 -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< + +%.hex: %.elf + $(TOOLCHAIN_PREFIX)objcopy -O verilog $< $@ + # to fix flash base address + sed -i 's/@10000000/@00000000/g' $@ + +%.bin: %.elf + $(TOOLCHAIN_PREFIX)objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ + +# ---- Clean ---- + +clean: + rm -f *.elf *.hex *.bin *.vvp *.vcd *.log + +.PHONY: clean hex all diff --git a/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock.c b/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock.c new file mode 100644 index 00000000..ac50ba30 --- /dev/null +++ b/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock.c @@ -0,0 +1,75 @@ +#include "../../defs.h" + +/* + IO Test: + - Configures MPRJ pins + - Observes counter value through the LED digits +*/ + +void main() +{ + /* + IO Control Registers + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | + + Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | + + Output: 0000_0110_0000_1111 (0x1809) = GPIO_MODE_MGNT_STD_OUTPUT + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | + + + Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | + + */ + + /* + Inputs + + 0 clock + 1 reset + 2 adj hours + 3 adj min + 4 adj sec + + + Outputs + + 5 hsync + 6 vsync + 7-12 rrggbb + */ + + reg_mprj_io_0 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_1 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_2 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_3 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_4 = GPIO_MODE_USER_STD_INPUT_NOPULL; + + reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_6 = GPIO_MODE_USER_STD_OUTPUT; + + reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_9 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT; + + /* Apply configuration */ + reg_mprj_xfer = 1; + while (reg_mprj_xfer == 1); + + // change to project 2 + reg_mprj_slave = 2; + + // use logic analyser to reset the design + reg_la0_ena = 0x00000000; // bits 31:0 outputs + reg_la0_data = 0x00000001; // reset high is on bit 0 + reg_la0_data = 0x00000000; // low +} diff --git a/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock.gtkw b/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock.gtkw new file mode 100644 index 00000000..819c5385 --- /dev/null +++ b/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock.gtkw @@ -0,0 +1,180 @@ +[*] +[*] GTKWave Analyzer v3.3.108 (w)1999-2020 BSI +[*] Wed Nov 18 15:01:40 2020 +[*] +[dumpfile] "/home/matt/work/asic-workshop/caravel/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock.vcd" +[dumpfile_mtime] "Wed Nov 18 14:58:01 2020" +[dumpfile_size] 201011801 +[savefile] "/home/matt/work/asic-workshop/caravel/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock.gtkw" +[timestart] 0 +[size] 2488 1529 +[pos] -1 -1 +*-27.000000 224331250 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] vga_clock_tb. +[treeopen] vga_clock_tb.uut. +[treeopen] vga_clock_tb.uut.gpio_control_bidir[0].gpio_in_buf. +[treeopen] vga_clock_tb.uut.gpio_control_in[4].gpio_in_buf. +[treeopen] vga_clock_tb.uut.gpio_control_in[4].gpio_logic_high. +[treeopen] vga_clock_tb.uut.mprj. +[treeopen] vga_clock_tb.uut.mprj.mprj. +[treeopen] vga_clock_tb.uut.mprj.mprj.proj_0. +[treeopen] vga_clock_tb.uut.mprj.mprj.proj_2. +[treeopen] vga_clock_tb.uut.soc. +[treeopen] vga_clock_tb.uut.soc.housekeeping. +[treeopen] vga_clock_tb.uut.soc.soc. +[treeopen] vga_clock_tb.uut.soc.soc.cpu. +[treeopen] vga_clock_tb.uut.soc.soc.cpu.picorv32_core. +[treeopen] vga_clock_tb.uut.soc.soc.gpio_wb. +[treeopen] vga_clock_tb.uut.soc.soc.mprj_ctrl. +[sst_width] 719 +[signals_width] 682 +[sst_expanded] 1 +[sst_vpaned_height] 862 +@28 +vga_clock_tb.clock +vga_clock_tb.RSTB +@200 +- +@800200 +-wbs +@28 +vga_clock_tb.uut.mprj.mprj.wb_rst_i +vga_clock_tb.uut.mprj.mprj.wb_clk_i +vga_clock_tb.uut.mprj.mprj.wbs_ack_o +@22 +vga_clock_tb.uut.mprj.mprj.wbs_adr_i[31:0] +@28 +vga_clock_tb.uut.mprj.mprj.wbs_cyc_i +@24 +vga_clock_tb.uut.mprj.mprj.wbs_dat_i[31:0] +@22 +vga_clock_tb.uut.mprj.mprj.wbs_dat_o[31:0] +vga_clock_tb.uut.mprj.mprj.wbs_sel_i[3:0] +@28 +vga_clock_tb.uut.mprj.mprj.wbs_stb_i +vga_clock_tb.uut.mprj.mprj.wbs_we_i +vga_clock_tb.uut.mprj.mprj.valid +@24 +vga_clock_tb.uut.mprj.mprj.wstrb[3:0] +@1000200 +-wbs +@800200 +-multi proj control +@28 +vga_clock_tb.uut.soc.soc.mprj_ctrl.mprj_ctrl.xfer_ctrl +@1000200 +-multi proj control +@800200 +-la +@22 +vga_clock_tb.uut.mprj.mprj.la_data_in[127:0] +vga_clock_tb.uut.mprj.mprj.la_data_out[127:0] +vga_clock_tb.uut.mprj.mprj.la_oen[127:0] +@1000200 +-la +@22 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b/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock_tb.v @@ -0,0 +1,133 @@ +`default_nettype none + +`timescale 1 ns / 1 ps + +`include "caravel.v" +`include "spiflash.v" + +module vga_clock_tb; + reg clock; + reg ext_clock; + reg RSTB; + reg power1, power2; + reg power3, power4; + + wire gpio; + wire [37:0] mprj_io; + wire [5:0] rrggbb; + wire hsync, vsync; + + assign hsync = mprj_io[5]; + assign vsync = mprj_io[6]; + assign rrggbb = mprj_io[12:7]; + + // External clock is used by default. Make this artificially fast for the + // simulation. Normally this would be a slow clock and the digital PLL + // would be the fast clock. + + always #12.5 clock <= (clock === 1'b0); + always #6.25 ext_clock <= (ext_clock === 1'b0); + + initial begin + clock = 0; + ext_clock = 0; + end + + // vga_clock wants ext clock on gpio0 and reset on gpio1 + assign mprj_io[0] = ext_clock; + assign mprj_io[1] = !RSTB; + + initial begin + $dumpfile("vga_clock.vcd"); + $dumpvars(0, vga_clock_tb); + + // Repeat cycles of 1000 clock edges as needed to complete testbench + repeat (15) begin + repeat (1000) @(posedge clock); + // $display("+1000 cycles"); + end + $display("%c[1;31m",27); + $display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed"); + $display("%c[0m",27); + $finish; + end + + initial begin + RSTB <= 1'b0; + #2000; + RSTB <= 1'b1; // Release reset + end + + initial begin // Power-up sequence + power1 <= 1'b0; + power2 <= 1'b0; + power3 <= 1'b0; + power4 <= 1'b0; + #200; + power1 <= 1'b1; + #200; + power2 <= 1'b1; + #200; + power3 <= 1'b1; + #200; + power4 <= 1'b1; + end + + /* + always @(mprj_io) begin + #1 $display("MPRJ-IO state = %b ", mprj_io[7:0]); + end + */ + + wire flash_csb; + wire flash_clk; + wire flash_io0; + wire flash_io1; + + wire VDD1V8; + wire VDD3V3; + wire VSS; + + assign VDD3V3 = power1; + assign VDD1V8 = power2; + assign USER_VDD3V3 = power3; + assign USER_VDD1V8 = power4; + assign VSS = 1'b0; + + caravel uut ( + .vddio (VDD3V3), + .vssio (VSS), + .vdda (VDD3V3), + .vssa (VSS), + .vccd (VDD1V8), + .vssd (VSS), + .vdda1 (USER_VDD3V3), + .vdda2 (USER_VDD3V3), + .vssa1 (VSS), + .vssa2 (VSS), + .vccd1 (USER_VDD1V8), + .vccd2 (USER_VDD1V8), + .vssd1 (VSS), + .vssd2 (VSS), + .clock (clock), + .gpio (gpio), + .mprj_io (mprj_io), + .flash_csb(flash_csb), + .flash_clk(flash_clk), + .flash_io0(flash_io0), + .flash_io1(flash_io1), + .resetb (RSTB) + ); + + spiflash #( + .FILENAME("vga_clock.hex") + ) spiflash ( + .csb(flash_csb), + .clk(flash_clk), + .io0(flash_io0), + .io1(flash_io1), + .io2(), // not used + .io3() // not used + ); + +endmodule diff --git a/verilog/dv/caravel/user_proj_example/ws2812/Makefile b/verilog/dv/caravel/user_proj_example/ws2812/Makefile new file mode 100644 index 00000000..3a007484 --- /dev/null +++ b/verilog/dv/caravel/user_proj_example/ws2812/Makefile @@ -0,0 +1,42 @@ +FIRMWARE_PATH = ../.. +RTL_PATH = ../../../../rtl +IP_PATH = ../../../../ip +#MP_PATH = ../../../../rtl/multi_project_harness +BEHAVIOURAL_MODELS = ../../ + +TOOLCHAIN_PREFIX?=/opt/riscv64-unknown-elf-gcc-8.3.0-2020.04.1-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf- +PDK_PATH?=~/work/asic-workshop/pdks/sky130A + +.SUFFIXES: + +PATTERN = ws2812 + +all: ${PATTERN:=.vcd} + +hex: ${PATTERN:=.hex} + +%.vvp: %_tb.v %.hex + iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \ + -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \ + $< -o $@ + +%.vcd: %.vvp + vvp $< + +%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s + $(TOOLCHAIN_PREFIX)gcc -mabi=ilp32 -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< + +%.hex: %.elf + $(TOOLCHAIN_PREFIX)objcopy -O verilog $< $@ + # to fix flash base address + sed -i 's/@10000000/@00000000/g' $@ + +%.bin: %.elf + $(TOOLCHAIN_PREFIX)objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ + +# ---- Clean ---- + +clean: + rm -f *.elf *.hex *.bin *.vvp *.vcd *.log + +.PHONY: clean hex all diff --git a/verilog/dv/caravel/user_proj_example/ws2812/ws2812.c b/verilog/dv/caravel/user_proj_example/ws2812/ws2812.c new file mode 100644 index 00000000..3529da1d --- /dev/null +++ b/verilog/dv/caravel/user_proj_example/ws2812/ws2812.c @@ -0,0 +1,68 @@ +#include "../../defs.h" + +/* + IO Test: + - Configures MPRJ pins + - Observes counter value through the LED digits +*/ + +#define reg_mprj_ws2812 (*(volatile uint32_t*)0x30000100) + +void main() +{ + /* + IO Control Registers + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | + + Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | + + Output: 0000_0110_0000_1111 (0x1809) = GPIO_MODE_MGNT_STD_OUTPUT + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | + + + Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | + + */ + + /* + Inputs + + 0 clock + 1 reset + + + Outputs + + 2 data for ws2812 + */ + + reg_mprj_io_0 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_1 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT; + + /* Apply configuration */ + reg_mprj_xfer = 1; + while (reg_mprj_xfer == 1); + + // change to project 1 + reg_mprj_slave = 1; + + // use logic analyser to reset the design + reg_la0_ena = 0x00000000; // bits 31:0 outputs + reg_la0_data = 0x00000001; // reset high is on bit 0 + reg_la0_data = 0x00000000; // low + + // update led 7 + uint8_t led_num = 7; + uint8_t r = 255; + uint8_t g = 10; + uint8_t b = 100; + reg_mprj_ws2812 = (led_num << 24) + (r << 16) + (g << 8) + b; +} + diff --git a/verilog/dv/caravel/user_proj_example/ws2812/ws2812.gtkw b/verilog/dv/caravel/user_proj_example/ws2812/ws2812.gtkw new file mode 100644 index 00000000..76a98792 --- /dev/null +++ b/verilog/dv/caravel/user_proj_example/ws2812/ws2812.gtkw @@ -0,0 +1,294 @@ +[*] +[*] GTKWave Analyzer v3.3.108 (w)1999-2020 BSI +[*] Wed Nov 18 14:45:52 2020 +[*] +[dumpfile] "/home/matt/work/asic-workshop/caravel/verilog/dv/caravel/user_proj_example/ws2812/ws2812.vcd" +[dumpfile_mtime] "Wed Nov 18 14:43:49 2020" +[dumpfile_size] 197685076 +[savefile] "/home/matt/work/asic-workshop/caravel/verilog/dv/caravel/user_proj_example/ws2812/ws2812.gtkw" +[timestart] 26300000 +[size] 2488 1529 +[pos] -1 -1 +*-26.000000 224331250 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] ws2812_tb. +[treeopen] ws2812_tb.uut. +[treeopen] ws2812_tb.uut.gpio_control_bidir[0].gpio_in_buf. +[treeopen] ws2812_tb.uut.gpio_control_in[4].gpio_in_buf. +[treeopen] ws2812_tb.uut.gpio_control_in[4].gpio_logic_high. +[treeopen] ws2812_tb.uut.mprj. +[treeopen] ws2812_tb.uut.mprj.mprj. +[treeopen] ws2812_tb.uut.mprj.mprj.proj_0. +[treeopen] ws2812_tb.uut.soc. +[treeopen] ws2812_tb.uut.soc.housekeeping. +[treeopen] ws2812_tb.uut.soc.soc. +[treeopen] ws2812_tb.uut.soc.soc.cpu. +[treeopen] ws2812_tb.uut.soc.soc.cpu.picorv32_core. +[treeopen] ws2812_tb.uut.soc.soc.gpio_wb. +[treeopen] ws2812_tb.uut.soc.soc.mprj_ctrl. +[sst_width] 719 +[signals_width] 682 +[sst_expanded] 1 +[sst_vpaned_height] 862 +@28 +ws2812_tb.clock +ws2812_tb.RSTB +@200 +- +@800200 +-wbs +@28 +ws2812_tb.uut.mprj.mprj.wb_rst_i +ws2812_tb.uut.mprj.mprj.wb_clk_i +ws2812_tb.uut.mprj.mprj.wbs_ack_o +@22 +ws2812_tb.uut.mprj.mprj.wbs_adr_i[31:0] +@28 +ws2812_tb.uut.mprj.mprj.wbs_cyc_i +@24 +ws2812_tb.uut.mprj.mprj.wbs_dat_i[31:0] +@22 +ws2812_tb.uut.mprj.mprj.wbs_dat_o[31:0] +ws2812_tb.uut.mprj.mprj.wbs_sel_i[3:0] +@28 +ws2812_tb.uut.mprj.mprj.wbs_stb_i +ws2812_tb.uut.mprj.mprj.wbs_we_i +ws2812_tb.uut.mprj.mprj.valid +@24 +ws2812_tb.uut.mprj.mprj.wstrb[3:0] +@1000200 +-wbs +@800200 +-multi proj control +@28 +ws2812_tb.uut.soc.soc.mprj_ctrl.mprj_ctrl.xfer_ctrl +@1000200 +-multi proj control +@800200 +-la +@22 +ws2812_tb.uut.mprj.mprj.la_data_in[127:0] +ws2812_tb.uut.mprj.mprj.la_data_out[127:0] +ws2812_tb.uut.mprj.mprj.la_oen[127:0] +@1000200 +-la +@22 +ws2812_tb.uut.soc.soc.cpu.picorv32_core.next_insn_opcode[31:0] +@200 +- +@800200 +-multi project +@22 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+(36)ws2812_tb.uut.mprj.mprj.io_out[37:0] +(37)ws2812_tb.uut.mprj.mprj.io_out[37:0] +@1401200 +-group_end +@22 +ws2812_tb.uut.mprj.mprj.io_oeb[37:0] +ws2812_tb.uut.mprj.mprj.io_in[37:0] +@1001200 +-group_end +@c00200 +-seven seg +@28 +ws2812_tb.uut.mprj.mprj.proj_0.clk +@22 +ws2812_tb.uut.mprj.mprj.proj_0.second_counter[23:0] +@24 +ws2812_tb.uut.mprj.mprj.proj_0.compare[23:0] +@28 +ws2812_tb.uut.mprj.mprj.proj_0.reset +@800022 +ws2812_tb.uut.mprj.mprj.proj_0.digit[3:0] +@28 +(0)ws2812_tb.uut.mprj.mprj.proj_0.digit[3:0] +(1)ws2812_tb.uut.mprj.mprj.proj_0.digit[3:0] +(2)ws2812_tb.uut.mprj.mprj.proj_0.digit[3:0] +(3)ws2812_tb.uut.mprj.mprj.proj_0.digit[3:0] +@22 +ws2812_tb.uut.mprj.mprj.proj_0.led_out[6:0] +@1001200 +-group_end +@1401200 +-seven seg +@800200 +-ws2812 +@25 +ws2812_tb.uut.mprj.mprj.proj_1.bit_counter[11:0] +@24 +ws2812_tb.uut.mprj.mprj.proj_1.rgb_counter[4:0] +ws2812_tb.uut.mprj.mprj.proj_1.led_counter[2:0] +@1000200 +-ws2812 +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/verilog/dv/caravel/user_proj_example/ws2812/ws2812_tb.v b/verilog/dv/caravel/user_proj_example/ws2812/ws2812_tb.v new file mode 100644 index 00000000..5869fcfe --- /dev/null +++ b/verilog/dv/caravel/user_proj_example/ws2812/ws2812_tb.v @@ -0,0 +1,149 @@ +`default_nettype none + +`timescale 1 ns / 1 ps + +`include "caravel.v" +`include "spiflash.v" + +module ws2812_tb; + reg clock; + reg ext_clock; + reg RSTB; + reg power1, power2; + reg power3, power4; + + wire gpio; + wire [37:0] mprj_io; + wire [6:0] segments; + + assign segments = mprj_io[8:2]; + + // External clock is used by default. Make this artificially fast for the + // simulation. Normally this would be a slow clock and the digital PLL + // would be the fast clock. + + always #12.5 clock <= (clock === 1'b0); + always #6.25 ext_clock <= (ext_clock === 1'b0); + + initial begin + clock = 0; + ext_clock = 0; + end + + // ws2812 wants ext clock on gpio0 and reset on gpio1 + assign mprj_io[0] = ext_clock; + assign mprj_io[1] = !RSTB; + + initial begin + $dumpfile("ws2812.vcd"); + $dumpvars(0, ws2812_tb); + + // Repeat cycles of 1000 clock edges as needed to complete testbench + repeat (15) begin + repeat (1000) @(posedge clock); + // $display("+1000 cycles"); + end + $display("%c[1;31m",27); + $display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed"); + $display("%c[0m",27); + $finish; + end + + initial begin + // Observe segments counting from 0 to 9 + + wait(segments == 7'b0111111); + wait(segments == 7'b0000110); + wait(segments == 7'b1011011); + wait(segments == 7'b1001111); + wait(segments == 7'b1100110); + wait(segments == 7'b1101101); + wait(segments == 7'b1111100); + wait(segments == 7'b0000111); + wait(segments == 7'b1111111); + wait(segments == 7'b1111111); + wait(segments == 7'b1100111); + + $display("Monitor: Test 1 Mega-Project IO (RTL) Passed"); + $finish; + end + + initial begin + RSTB <= 1'b0; + #2000; + RSTB <= 1'b1; // Release reset + end + + initial begin // Power-up sequence + power1 <= 1'b0; + power2 <= 1'b0; + power3 <= 1'b0; + power4 <= 1'b0; + #200; + power1 <= 1'b1; + #200; + power2 <= 1'b1; + #200; + power3 <= 1'b1; + #200; + power4 <= 1'b1; + end + + /* + always @(mprj_io) begin + #1 $display("MPRJ-IO state = %b ", mprj_io[7:0]); + end + */ + + wire flash_csb; + wire flash_clk; + wire flash_io0; + wire flash_io1; + + wire VDD1V8; + wire VDD3V3; + wire VSS; + + assign VDD3V3 = power1; + assign VDD1V8 = power2; + assign USER_VDD3V3 = power3; + assign USER_VDD1V8 = power4; + assign VSS = 1'b0; + + caravel uut ( + .vddio (VDD3V3), + .vssio (VSS), + .vdda (VDD3V3), + .vssa (VSS), + .vccd (VDD1V8), + .vssd (VSS), + .vdda1 (USER_VDD3V3), + .vdda2 (USER_VDD3V3), + .vssa1 (VSS), + .vssa2 (VSS), + .vccd1 (USER_VDD1V8), + .vccd2 (USER_VDD1V8), + .vssd1 (VSS), + .vssd2 (VSS), + .clock (clock), + .gpio (gpio), + .mprj_io (mprj_io), + .flash_csb(flash_csb), + .flash_clk(flash_clk), + .flash_io0(flash_io0), + .flash_io1(flash_io1), + .resetb (RSTB) + ); + + spiflash #( + .FILENAME("ws2812.hex") + ) spiflash ( + .csb(flash_csb), + .clk(flash_clk), + .io0(flash_io0), + .io1(flash_io1), + .io2(), // not used + .io3() // not used + ); + +endmodule diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v index 24a2f3fc..57ebf3a0 100644 --- a/verilog/rtl/caravel.v +++ b/verilog/rtl/caravel.v @@ -50,7 +50,7 @@ /*------------------------------*/ /* Include user project here */ /*------------------------------*/ -`include "user_proj_example.v" +`include "multi_project_harness/includes.v" // `ifdef USE_OPENRAM // `include "sram_1rw1r_32_256_8_sky130.v" diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index 488e4cc5..275cdd9f 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v @@ -55,7 +55,7 @@ module user_project_wrapper #( /* User project is instantiated here */ /*--------------------------------------*/ - user_proj_example mprj ( + multi_project_harness mprj ( .vdda1(vdda1), // User area 1 3.3V power .vdda2(vdda2), // User area 2 3.3V power .vssa1(vssa1), // User area 1 analog ground From 14bfbfda8e813be6e2e3a0c6aa629b4734999b83 Mon Sep 17 00:00:00 2001 From: Matt Venn Date: Wed, 18 Nov 2020 16:09:38 +0100 Subject: [PATCH 02/32] add multi project as gitmodule --- .gitmodules | 3 +++ verilog/rtl/multi-project-harness | 1 + 2 files changed, 4 insertions(+) create mode 100644 .gitmodules create mode 160000 verilog/rtl/multi-project-harness diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 00000000..260b81bc --- /dev/null +++ b/.gitmodules @@ -0,0 +1,3 @@ +[submodule "verilog/rtl/multi-project-harness"] + path = verilog/rtl/multi-project-harness + url = https://github.com/mattvenn/multi-project-harness.git diff --git a/verilog/rtl/multi-project-harness b/verilog/rtl/multi-project-harness new file mode 160000 index 00000000..ce2fe911 --- /dev/null +++ b/verilog/rtl/multi-project-harness @@ -0,0 +1 @@ +Subproject commit ce2fe911421c7c76ebe5cee0c60fd3a8df56506d From 06ad481836649dc48e5b01de8e6047fe4b2272f2 Mon Sep 17 00:00:00 2001 From: Matt Venn Date: Wed, 18 Nov 2020 16:19:55 +0100 Subject: [PATCH 03/32] switch to wishbone branch --- verilog/rtl/multi-project-harness | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/verilog/rtl/multi-project-harness b/verilog/rtl/multi-project-harness index ce2fe911..8f682e4d 160000 --- a/verilog/rtl/multi-project-harness +++ b/verilog/rtl/multi-project-harness @@ -1 +1 @@ -Subproject commit ce2fe911421c7c76ebe5cee0c60fd3a8df56506d +Subproject commit 8f682e4d7d3cb2036e3f17f62e588ff8ca57b19b From f2aeef52fd7a1f0e33a98ccdaf66c0ff50c6b38d Mon Sep 17 00:00:00 2001 From: Matt Venn Date: Wed, 18 Nov 2020 16:24:20 +0100 Subject: [PATCH 04/32] fix path --- .gitmodules | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitmodules b/.gitmodules index 260b81bc..9c6b613e 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,3 @@ [submodule "verilog/rtl/multi-project-harness"] - path = verilog/rtl/multi-project-harness + path = verilog/rtl/multi_project_harness url = https://github.com/mattvenn/multi-project-harness.git From 60adb0a7caa7c07840e7776b41d517a80e53db31 Mon Sep 17 00:00:00 2001 From: Matt Venn Date: Wed, 18 Nov 2020 16:41:53 +0100 Subject: [PATCH 05/32] renamed --- verilog/rtl/{multi-project-harness => multi_project_harness} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename verilog/rtl/{multi-project-harness => multi_project_harness} (100%) diff --git a/verilog/rtl/multi-project-harness b/verilog/rtl/multi_project_harness similarity index 100% rename from verilog/rtl/multi-project-harness rename to verilog/rtl/multi_project_harness From e92bf8952f7935c32fb20bf3b70e3414844f046a Mon Sep 17 00:00:00 2001 From: Matt Venn Date: Wed, 18 Nov 2020 17:49:00 +0100 Subject: [PATCH 06/32] add spinet --- verilog/rtl/multi_project_harness | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/verilog/rtl/multi_project_harness b/verilog/rtl/multi_project_harness index 8f682e4d..bd6eaefc 160000 --- a/verilog/rtl/multi_project_harness +++ b/verilog/rtl/multi_project_harness @@ -1 +1 @@ -Subproject commit 8f682e4d7d3cb2036e3f17f62e588ff8ca57b19b +Subproject commit bd6eaefcdd7263992ff2854c37dda923275152af From 104e80657f3ff7eac006346f23fd7a41881183cb Mon Sep 17 00:00:00 2001 From: Matt Venn Date: Fri, 20 Nov 2020 11:42:55 +0100 Subject: [PATCH 07/32] update with new clock/reset strategy --- .../seven-segment-counter/seven_segment.c | 8 +- .../seven-segment-counter/seven_segment_tb.v | 235 +++++++++-------- .../user_proj_example/vga-clock/vga_clock.c | 6 +- .../vga-clock/vga_clock.gtkw | 17 +- .../vga-clock/vga_clock_tb.v | 223 ++++++++-------- .../caravel/user_proj_example/ws2812/ws2812.c | 6 +- .../user_proj_example/ws2812/ws2812.gtkw | 62 +---- .../user_proj_example/ws2812/ws2812_tb.v | 240 ++++++++---------- 8 files changed, 351 insertions(+), 446 deletions(-) diff --git a/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment.c b/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment.c index b5df6e3e..2d068f3c 100644 --- a/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment.c +++ b/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment.c @@ -33,8 +33,8 @@ void main() /* Inputs - 0 clock - 1 reset + system clock + system reset Outputs @@ -42,8 +42,8 @@ void main() 8:2 seven segment LEDs */ - reg_mprj_io_0 = GPIO_MODE_USER_STD_INPUT_NOPULL; - reg_mprj_io_1 = GPIO_MODE_USER_STD_INPUT_NOPULL; + //reg_mprj_io_0 = GPIO_MODE_USER_STD_INPUT_NOPULL; + //reg_mprj_io_1 = GPIO_MODE_USER_STD_INPUT_NOPULL; reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT; reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT; reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT; diff --git a/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment_tb.v b/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment_tb.v index fa59edfd..48a5a971 100644 --- a/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment_tb.v +++ b/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment_tb.v @@ -6,53 +6,46 @@ `include "spiflash.v" module seven_segment_tb; - reg clock; - reg ext_clock; - reg RSTB; - reg power1, power2; - reg power3, power4; - - wire gpio; - wire [37:0] mprj_io; - wire [6:0] segments; - - assign segments = mprj_io[8:2]; - - // External clock is used by default. Make this artificially fast for the - // simulation. Normally this would be a slow clock and the digital PLL - // would be the fast clock. - - always #12.5 clock <= (clock === 1'b0); - always #6.25 ext_clock <= (ext_clock === 1'b0); - - initial begin - clock = 0; - ext_clock = 0; - end - - // seven seg wants ext clock on gpio0 and reset on gpio1 - assign mprj_io[0] = ext_clock; - assign mprj_io[1] = !RSTB; - - initial begin - $dumpfile("seven_segment.vcd"); - $dumpvars(0, seven_segment_tb); - - // Repeat cycles of 1000 clock edges as needed to complete testbench - repeat (15) begin - repeat (1000) @(posedge clock); - // $display("+1000 cycles"); - end - $display("%c[1;31m",27); - $display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed"); - $display("%c[0m",27); - $finish; - end - - initial begin - // Observe segments counting from 0 to 9 - - wait(segments == 7'b0111111); + reg clock; + reg RSTB; + reg power1, power2; + reg power3, power4; + + wire gpio; + wire [37:0] mprj_io; + wire [6:0] segments; + + assign segments = mprj_io[8:2]; + + // External clock is used by default. Make this artificially fast for the + // simulation. Normally this would be a slow clock and the digital PLL + // would be the fast clock. + + always #12.5 clock <= (clock === 1'b0); + + initial begin + clock = 0; + end + + initial begin + $dumpfile("seven_segment.vcd"); + $dumpvars(0, seven_segment_tb); + + // Repeat cycles of 1000 clock edges as needed to complete testbench + repeat (15) begin + repeat (1000) @(posedge clock); + // $display("+1000 cycles"); + end + $display("%c[1;31m",27); + $display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed"); + $display("%c[0m",27); + $finish; + end + + initial begin + // Observe segments counting from 0 to 9 + + wait(segments == 7'b0111111); wait(segments == 7'b0000110); wait(segments == 7'b1011011); wait(segments == 7'b1001111); @@ -64,86 +57,86 @@ module seven_segment_tb; wait(segments == 7'b1111111); wait(segments == 7'b1100111); - $display("Monitor: Test 1 Mega-Project IO (RTL) Passed"); + $display("Monitor: Test 1 Mega-Project IO (RTL) Passed"); $finish; - end - - initial begin - RSTB <= 1'b0; - #2000; - RSTB <= 1'b1; // Release reset - end - - initial begin // Power-up sequence - power1 <= 1'b0; - power2 <= 1'b0; - power3 <= 1'b0; - power4 <= 1'b0; - #200; - power1 <= 1'b1; - #200; - power2 <= 1'b1; - #200; - power3 <= 1'b1; - #200; - power4 <= 1'b1; - end + end + + initial begin + RSTB <= 1'b0; + #2000; + RSTB <= 1'b1; // Release reset + end + + initial begin // Power-up sequence + power1 <= 1'b0; + power2 <= 1'b0; + power3 <= 1'b0; + power4 <= 1'b0; + #200; + power1 <= 1'b1; + #200; + power2 <= 1'b1; + #200; + power3 <= 1'b1; + #200; + power4 <= 1'b1; + end /* - always @(mprj_io) begin - #1 $display("MPRJ-IO state = %b ", mprj_io[7:0]); - end + always @(mprj_io) begin + #1 $display("MPRJ-IO state = %b ", mprj_io[7:0]); + end */ - wire flash_csb; - wire flash_clk; - wire flash_io0; - wire flash_io1; + wire flash_csb; + wire flash_clk; + wire flash_io0; + wire flash_io1; - wire VDD1V8; - wire VDD3V3; - wire VSS; + wire VDD1V8; + wire VDD3V3; + wire VSS; - assign VDD3V3 = power1; - assign VDD1V8 = power2; - assign USER_VDD3V3 = power3; - assign USER_VDD1V8 = power4; - assign VSS = 1'b0; - - caravel uut ( - .vddio (VDD3V3), - .vssio (VSS), - .vdda (VDD3V3), - .vssa (VSS), - .vccd (VDD1V8), - .vssd (VSS), - .vdda1 (USER_VDD3V3), - .vdda2 (USER_VDD3V3), - .vssa1 (VSS), - .vssa2 (VSS), - .vccd1 (USER_VDD1V8), - .vccd2 (USER_VDD1V8), - .vssd1 (VSS), - .vssd2 (VSS), - .clock (clock), - .gpio (gpio), - .mprj_io (mprj_io), - .flash_csb(flash_csb), - .flash_clk(flash_clk), - .flash_io0(flash_io0), - .flash_io1(flash_io1), - .resetb (RSTB) - ); - - spiflash #( - .FILENAME("seven_segment.hex") - ) spiflash ( - .csb(flash_csb), - .clk(flash_clk), - .io0(flash_io0), - .io1(flash_io1), - .io2(), // not used - .io3() // not used - ); + assign VDD3V3 = power1; + assign VDD1V8 = power2; + assign USER_VDD3V3 = power3; + assign USER_VDD1V8 = power4; + assign VSS = 1'b0; + + caravel uut ( + .vddio (VDD3V3), + .vssio (VSS), + .vdda (VDD3V3), + .vssa (VSS), + .vccd (VDD1V8), + .vssd (VSS), + .vdda1 (USER_VDD3V3), + .vdda2 (USER_VDD3V3), + .vssa1 (VSS), + .vssa2 (VSS), + .vccd1 (USER_VDD1V8), + .vccd2 (USER_VDD1V8), + .vssd1 (VSS), + .vssd2 (VSS), + .clock (clock), + .gpio (gpio), + .mprj_io (mprj_io), + .flash_csb(flash_csb), + .flash_clk(flash_clk), + .flash_io0(flash_io0), + .flash_io1(flash_io1), + .resetb (RSTB) + ); + + spiflash #( + .FILENAME("seven_segment.hex") + ) spiflash ( + .csb(flash_csb), + .clk(flash_clk), + .io0(flash_io0), + .io1(flash_io1), + .io2(), // not used + .io3() // not used + ); endmodule diff --git a/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock.c b/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock.c index ac50ba30..210e0cfe 100644 --- a/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock.c +++ b/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock.c @@ -31,8 +31,8 @@ void main() /* Inputs - 0 clock - 1 reset + system clock + system reset 2 adj hours 3 adj min 4 adj sec @@ -45,8 +45,6 @@ void main() 7-12 rrggbb */ - reg_mprj_io_0 = GPIO_MODE_USER_STD_INPUT_NOPULL; - reg_mprj_io_1 = GPIO_MODE_USER_STD_INPUT_NOPULL; reg_mprj_io_2 = GPIO_MODE_USER_STD_INPUT_NOPULL; reg_mprj_io_3 = GPIO_MODE_USER_STD_INPUT_NOPULL; reg_mprj_io_4 = GPIO_MODE_USER_STD_INPUT_NOPULL; diff --git a/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock.gtkw b/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock.gtkw index 819c5385..22f2bef5 100644 --- a/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock.gtkw +++ b/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock.gtkw @@ -1,15 +1,15 @@ [*] [*] GTKWave Analyzer v3.3.108 (w)1999-2020 BSI -[*] Wed Nov 18 15:01:40 2020 +[*] Fri Nov 20 10:42:39 2020 [*] [dumpfile] "/home/matt/work/asic-workshop/caravel/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock.vcd" -[dumpfile_mtime] "Wed Nov 18 14:58:01 2020" -[dumpfile_size] 201011801 +[dumpfile_mtime] "Fri Nov 20 10:36:44 2020" +[dumpfile_size] 192004694 [savefile] "/home/matt/work/asic-workshop/caravel/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock.gtkw" -[timestart] 0 +[timestart] 136100000 [size] 2488 1529 [pos] -1 -1 -*-27.000000 224331250 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +*-25.000000 266612500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] vga_clock_tb. [treeopen] vga_clock_tb.uut. [treeopen] vga_clock_tb.uut.gpio_control_bidir[0].gpio_in_buf. @@ -171,6 +171,13 @@ vga_clock_tb.uut.mprj.mprj.io_out[37:0] @1000200 -multi project @28 +vga_clock_tb.uut.mprj.mprj.proj_2.reset +@29 +vga_clock_tb.uut.mprj.mprj.proj_2.px_clk +@24 +vga_clock_tb.uut.mprj.mprj.proj_2.y_px[9:0] +vga_clock_tb.uut.mprj.mprj.proj_2.x_px[9:0] +@28 vga_clock_tb.uut.mprj.mprj.proj_2.activevideo vga_clock_tb.uut.mprj.mprj.proj_2.vsync vga_clock_tb.hsync diff --git a/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock_tb.v b/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock_tb.v index 37b1007c..5b13c0dc 100644 --- a/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock_tb.v +++ b/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock_tb.v @@ -6,128 +6,115 @@ `include "spiflash.v" module vga_clock_tb; - reg clock; - reg ext_clock; - reg RSTB; - reg power1, power2; - reg power3, power4; - - wire gpio; - wire [37:0] mprj_io; - wire [5:0] rrggbb; + reg clock; + reg RSTB; + reg power1, power2; + reg power3, power4; + + wire gpio; + wire [37:0] mprj_io; + wire [5:0] rrggbb; wire hsync, vsync; assign hsync = mprj_io[5]; assign vsync = mprj_io[6]; - assign rrggbb = mprj_io[12:7]; - - // External clock is used by default. Make this artificially fast for the - // simulation. Normally this would be a slow clock and the digital PLL - // would be the fast clock. - - always #12.5 clock <= (clock === 1'b0); - always #6.25 ext_clock <= (ext_clock === 1'b0); - - initial begin - clock = 0; - ext_clock = 0; - end - - // vga_clock wants ext clock on gpio0 and reset on gpio1 - assign mprj_io[0] = ext_clock; - assign mprj_io[1] = !RSTB; - - initial begin - $dumpfile("vga_clock.vcd"); - $dumpvars(0, vga_clock_tb); - - // Repeat cycles of 1000 clock edges as needed to complete testbench - repeat (15) begin - repeat (1000) @(posedge clock); - // $display("+1000 cycles"); - end - $display("%c[1;31m",27); - $display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed"); - $display("%c[0m",27); - $finish; - end - - initial begin - RSTB <= 1'b0; - #2000; - RSTB <= 1'b1; // Release reset - end - - initial begin // Power-up sequence - power1 <= 1'b0; - power2 <= 1'b0; - power3 <= 1'b0; - power4 <= 1'b0; - #200; - power1 <= 1'b1; - #200; - power2 <= 1'b1; - #200; - power3 <= 1'b1; - #200; - power4 <= 1'b1; - end - - /* - always @(mprj_io) begin - #1 $display("MPRJ-IO state = %b ", mprj_io[7:0]); - end - */ - - wire flash_csb; - wire flash_clk; - wire flash_io0; - wire flash_io1; - - wire VDD1V8; - wire VDD3V3; - wire VSS; + assign rrggbb = mprj_io[12:7]; + + // External clock is used by default. Make this artificially fast for the + // simulation. Normally this would be a slow clock and the digital PLL + // would be the fast clock. + + always #12.5 clock <= (clock === 1'b0); + + initial begin + clock = 0; + end + + initial begin + $dumpfile("vga_clock.vcd"); + $dumpvars(0, vga_clock_tb); + + // Repeat cycles of 1000 clock edges as needed to complete testbench + repeat (15) begin + repeat (1000) @(posedge clock); + // $display("+1000 cycles"); + end + $display("%c[1;31m",27); + $display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed"); + $display("%c[0m",27); + $finish; + end + + initial begin + RSTB <= 1'b0; + #2000; + RSTB <= 1'b1; // Release reset + end + + initial begin // Power-up sequence + power1 <= 1'b0; + power2 <= 1'b0; + power3 <= 1'b0; + power4 <= 1'b0; + #200; + power1 <= 1'b1; + #200; + power2 <= 1'b1; + #200; + power3 <= 1'b1; + #200; + power4 <= 1'b1; + end + + wire flash_csb; + wire flash_clk; + wire flash_io0; + wire flash_io1; + + wire VDD1V8; + wire VDD3V3; + wire VSS; - assign VDD3V3 = power1; - assign VDD1V8 = power2; - assign USER_VDD3V3 = power3; - assign USER_VDD1V8 = power4; - assign VSS = 1'b0; - - caravel uut ( - .vddio (VDD3V3), - .vssio (VSS), - .vdda (VDD3V3), - .vssa (VSS), - .vccd (VDD1V8), - .vssd (VSS), - .vdda1 (USER_VDD3V3), - .vdda2 (USER_VDD3V3), - .vssa1 (VSS), - .vssa2 (VSS), - .vccd1 (USER_VDD1V8), - .vccd2 (USER_VDD1V8), - .vssd1 (VSS), - .vssd2 (VSS), - .clock (clock), - .gpio (gpio), - .mprj_io (mprj_io), - .flash_csb(flash_csb), - .flash_clk(flash_clk), - .flash_io0(flash_io0), - .flash_io1(flash_io1), - .resetb (RSTB) - ); - - spiflash #( - .FILENAME("vga_clock.hex") - ) spiflash ( - .csb(flash_csb), - .clk(flash_clk), - .io0(flash_io0), - .io1(flash_io1), - .io2(), // not used - .io3() // not used - ); + assign VDD3V3 = power1; + assign VDD1V8 = power2; + assign USER_VDD3V3 = power3; + assign USER_VDD1V8 = power4; + assign VSS = 1'b0; + + caravel uut ( + .vddio (VDD3V3), + .vssio (VSS), + .vdda (VDD3V3), + .vssa (VSS), + .vccd (VDD1V8), + .vssd (VSS), + .vdda1 (USER_VDD3V3), + .vdda2 (USER_VDD3V3), + .vssa1 (VSS), + .vssa2 (VSS), + .vccd1 (USER_VDD1V8), + .vccd2 (USER_VDD1V8), + .vssd1 (VSS), + .vssd2 (VSS), + .clock (clock), + .gpio (gpio), + .mprj_io (mprj_io), + .flash_csb(flash_csb), + .flash_clk(flash_clk), + .flash_io0(flash_io0), + .flash_io1(flash_io1), + .resetb (RSTB) + ); + + spiflash #( + .FILENAME("vga_clock.hex") + ) spiflash ( + .csb(flash_csb), + .clk(flash_clk), + .io0(flash_io0), + .io1(flash_io1), + .io2(), // not used + .io3() // not used + ); endmodule diff --git a/verilog/dv/caravel/user_proj_example/ws2812/ws2812.c b/verilog/dv/caravel/user_proj_example/ws2812/ws2812.c index 3529da1d..c077b2e2 100644 --- a/verilog/dv/caravel/user_proj_example/ws2812/ws2812.c +++ b/verilog/dv/caravel/user_proj_example/ws2812/ws2812.c @@ -33,8 +33,8 @@ void main() /* Inputs - 0 clock - 1 reset + system clock + system reset Outputs @@ -42,8 +42,6 @@ void main() 2 data for ws2812 */ - reg_mprj_io_0 = GPIO_MODE_USER_STD_INPUT_NOPULL; - reg_mprj_io_1 = GPIO_MODE_USER_STD_INPUT_NOPULL; reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT; /* Apply configuration */ diff --git a/verilog/dv/caravel/user_proj_example/ws2812/ws2812.gtkw b/verilog/dv/caravel/user_proj_example/ws2812/ws2812.gtkw index 76a98792..65cbad90 100644 --- a/verilog/dv/caravel/user_proj_example/ws2812/ws2812.gtkw +++ b/verilog/dv/caravel/user_proj_example/ws2812/ws2812.gtkw @@ -1,15 +1,15 @@ [*] [*] GTKWave Analyzer v3.3.108 (w)1999-2020 BSI -[*] Wed Nov 18 14:45:52 2020 +[*] Fri Nov 20 10:34:36 2020 [*] [dumpfile] "/home/matt/work/asic-workshop/caravel/verilog/dv/caravel/user_proj_example/ws2812/ws2812.vcd" -[dumpfile_mtime] "Wed Nov 18 14:43:49 2020" -[dumpfile_size] 197685076 +[dumpfile_mtime] "Fri Nov 20 10:32:17 2020" +[dumpfile_size] 192131563 [savefile] "/home/matt/work/asic-workshop/caravel/verilog/dv/caravel/user_proj_example/ws2812/ws2812.gtkw" -[timestart] 26300000 +[timestart] 0 [size] 2488 1529 [pos] -1 -1 -*-26.000000 224331250 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +*-26.000000 138637500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] ws2812_tb. [treeopen] ws2812_tb.uut. [treeopen] ws2812_tb.uut.gpio_control_bidir[0].gpio_in_buf. @@ -18,6 +18,7 @@ [treeopen] ws2812_tb.uut.mprj. [treeopen] ws2812_tb.uut.mprj.mprj. [treeopen] ws2812_tb.uut.mprj.mprj.proj_0. +[treeopen] ws2812_tb.uut.mprj.mprj.proj_2. [treeopen] ws2812_tb.uut.soc. [treeopen] ws2812_tb.uut.soc.housekeeping. [treeopen] ws2812_tb.uut.soc.soc. @@ -210,52 +211,6 @@ ws2812_tb.mprj_io[37:0] (35)ws2812_tb.mprj_io[37:0] (36)ws2812_tb.mprj_io[37:0] (37)ws2812_tb.mprj_io[37:0] -@c00022 -ws2812_tb.uut.mprj.mprj.io_out[37:0] -@28 -(0)ws2812_tb.uut.mprj.mprj.io_out[37:0] -(1)ws2812_tb.uut.mprj.mprj.io_out[37:0] -(2)ws2812_tb.uut.mprj.mprj.io_out[37:0] -(3)ws2812_tb.uut.mprj.mprj.io_out[37:0] -(4)ws2812_tb.uut.mprj.mprj.io_out[37:0] -(5)ws2812_tb.uut.mprj.mprj.io_out[37:0] -(6)ws2812_tb.uut.mprj.mprj.io_out[37:0] -(7)ws2812_tb.uut.mprj.mprj.io_out[37:0] -(8)ws2812_tb.uut.mprj.mprj.io_out[37:0] -(9)ws2812_tb.uut.mprj.mprj.io_out[37:0] -(10)ws2812_tb.uut.mprj.mprj.io_out[37:0] -(11)ws2812_tb.uut.mprj.mprj.io_out[37:0] -(12)ws2812_tb.uut.mprj.mprj.io_out[37:0] -(13)ws2812_tb.uut.mprj.mprj.io_out[37:0] -(14)ws2812_tb.uut.mprj.mprj.io_out[37:0] -(15)ws2812_tb.uut.mprj.mprj.io_out[37:0] -(16)ws2812_tb.uut.mprj.mprj.io_out[37:0] -(17)ws2812_tb.uut.mprj.mprj.io_out[37:0] -(18)ws2812_tb.uut.mprj.mprj.io_out[37:0] -(19)ws2812_tb.uut.mprj.mprj.io_out[37:0] -(20)ws2812_tb.uut.mprj.mprj.io_out[37:0] -(21)ws2812_tb.uut.mprj.mprj.io_out[37:0] -(22)ws2812_tb.uut.mprj.mprj.io_out[37:0] -(23)ws2812_tb.uut.mprj.mprj.io_out[37:0] -(24)ws2812_tb.uut.mprj.mprj.io_out[37:0] -(25)ws2812_tb.uut.mprj.mprj.io_out[37:0] -(26)ws2812_tb.uut.mprj.mprj.io_out[37:0] -(27)ws2812_tb.uut.mprj.mprj.io_out[37:0] -(28)ws2812_tb.uut.mprj.mprj.io_out[37:0] -(29)ws2812_tb.uut.mprj.mprj.io_out[37:0] -(30)ws2812_tb.uut.mprj.mprj.io_out[37:0] -(31)ws2812_tb.uut.mprj.mprj.io_out[37:0] -(32)ws2812_tb.uut.mprj.mprj.io_out[37:0] -(33)ws2812_tb.uut.mprj.mprj.io_out[37:0] -(34)ws2812_tb.uut.mprj.mprj.io_out[37:0] -(35)ws2812_tb.uut.mprj.mprj.io_out[37:0] -(36)ws2812_tb.uut.mprj.mprj.io_out[37:0] -(37)ws2812_tb.uut.mprj.mprj.io_out[37:0] -@1401200 --group_end -@22 -ws2812_tb.uut.mprj.mprj.io_oeb[37:0] -ws2812_tb.uut.mprj.mprj.io_in[37:0] @1001200 -group_end @c00200 @@ -281,11 +236,12 @@ ws2812_tb.uut.mprj.mprj.proj_0.led_out[6:0] -group_end @1401200 -seven seg +@29 +ws2812_tb.uut.mprj.mprj.proj_1.reset @800200 -ws2812 -@25 -ws2812_tb.uut.mprj.mprj.proj_1.bit_counter[11:0] @24 +ws2812_tb.uut.mprj.mprj.proj_1.bit_counter[11:0] ws2812_tb.uut.mprj.mprj.proj_1.rgb_counter[4:0] ws2812_tb.uut.mprj.mprj.proj_1.led_counter[2:0] @1000200 diff --git a/verilog/dv/caravel/user_proj_example/ws2812/ws2812_tb.v b/verilog/dv/caravel/user_proj_example/ws2812/ws2812_tb.v index 5869fcfe..94f9c902 100644 --- a/verilog/dv/caravel/user_proj_example/ws2812/ws2812_tb.v +++ b/verilog/dv/caravel/user_proj_example/ws2812/ws2812_tb.v @@ -6,144 +6,110 @@ `include "spiflash.v" module ws2812_tb; - reg clock; - reg ext_clock; - reg RSTB; - reg power1, power2; - reg power3, power4; - - wire gpio; - wire [37:0] mprj_io; - wire [6:0] segments; - - assign segments = mprj_io[8:2]; - - // External clock is used by default. Make this artificially fast for the - // simulation. Normally this would be a slow clock and the digital PLL - // would be the fast clock. - - always #12.5 clock <= (clock === 1'b0); - always #6.25 ext_clock <= (ext_clock === 1'b0); - - initial begin - clock = 0; - ext_clock = 0; - end - - // ws2812 wants ext clock on gpio0 and reset on gpio1 - assign mprj_io[0] = ext_clock; - assign mprj_io[1] = !RSTB; - - initial begin - $dumpfile("ws2812.vcd"); - $dumpvars(0, ws2812_tb); - - // Repeat cycles of 1000 clock edges as needed to complete testbench - repeat (15) begin - repeat (1000) @(posedge clock); - // $display("+1000 cycles"); - end - $display("%c[1;31m",27); - $display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed"); - $display("%c[0m",27); - $finish; - end - - initial begin - // Observe segments counting from 0 to 9 - - wait(segments == 7'b0111111); - wait(segments == 7'b0000110); - wait(segments == 7'b1011011); - wait(segments == 7'b1001111); - wait(segments == 7'b1100110); - wait(segments == 7'b1101101); - wait(segments == 7'b1111100); - wait(segments == 7'b0000111); - wait(segments == 7'b1111111); - wait(segments == 7'b1111111); - wait(segments == 7'b1100111); - - $display("Monitor: Test 1 Mega-Project IO (RTL) Passed"); + reg clock; + reg RSTB; + reg power1, power2; + reg power3, power4; + + wire gpio; + wire [37:0] mprj_io; + + // External clock is used by default. Make this artificially fast for the + // simulation. Normally this would be a slow clock and the digital PLL + // would be the fast clock. + + always #12.5 clock <= (clock === 1'b0); + + initial begin + clock = 0; + end + + + initial begin + $dumpfile("ws2812.vcd"); + $dumpvars(0, ws2812_tb); + + // Repeat cycles of 1000 clock edges as needed to complete testbench + repeat (15) begin + repeat (1000) @(posedge clock); + // $display("+1000 cycles"); + end + $display("%c[1;31m",27); + $display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed"); + $display("%c[0m",27); $finish; - end - - initial begin - RSTB <= 1'b0; - #2000; - RSTB <= 1'b1; // Release reset - end - - initial begin // Power-up sequence - power1 <= 1'b0; - power2 <= 1'b0; - power3 <= 1'b0; - power4 <= 1'b0; - #200; - power1 <= 1'b1; - #200; - power2 <= 1'b1; - #200; - power3 <= 1'b1; - #200; - power4 <= 1'b1; - end - - /* - always @(mprj_io) begin - #1 $display("MPRJ-IO state = %b ", mprj_io[7:0]); - end - */ - - wire flash_csb; - wire flash_clk; - wire flash_io0; - wire flash_io1; - - wire VDD1V8; - wire VDD3V3; - wire VSS; + end + + initial begin + RSTB <= 1'b0; + #2000; + RSTB <= 1'b1; // Release reset + end + + initial begin // Power-up sequence + power1 <= 1'b0; + power2 <= 1'b0; + power3 <= 1'b0; + power4 <= 1'b0; + #200; + power1 <= 1'b1; + #200; + power2 <= 1'b1; + #200; + power3 <= 1'b1; + #200; + power4 <= 1'b1; + end + + wire flash_csb; + wire flash_clk; + wire flash_io0; + wire flash_io1; + + wire VDD1V8; + wire VDD3V3; + wire VSS; - assign VDD3V3 = power1; - assign VDD1V8 = power2; - assign USER_VDD3V3 = power3; - assign USER_VDD1V8 = power4; - assign VSS = 1'b0; - - caravel uut ( - .vddio (VDD3V3), - .vssio (VSS), - .vdda (VDD3V3), - .vssa (VSS), - .vccd (VDD1V8), - .vssd (VSS), - .vdda1 (USER_VDD3V3), - .vdda2 (USER_VDD3V3), - .vssa1 (VSS), - .vssa2 (VSS), - .vccd1 (USER_VDD1V8), - .vccd2 (USER_VDD1V8), - .vssd1 (VSS), - .vssd2 (VSS), - .clock (clock), - .gpio (gpio), - .mprj_io (mprj_io), - .flash_csb(flash_csb), - .flash_clk(flash_clk), - .flash_io0(flash_io0), - .flash_io1(flash_io1), - .resetb (RSTB) - ); - - spiflash #( - .FILENAME("ws2812.hex") - ) spiflash ( - .csb(flash_csb), - .clk(flash_clk), - .io0(flash_io0), - .io1(flash_io1), - .io2(), // not used - .io3() // not used - ); + assign VDD3V3 = power1; + assign VDD1V8 = power2; + assign USER_VDD3V3 = power3; + assign USER_VDD1V8 = power4; + assign VSS = 1'b0; + + caravel uut ( + .vddio (VDD3V3), + .vssio (VSS), + .vdda (VDD3V3), + .vssa (VSS), + .vccd (VDD1V8), + .vssd (VSS), + .vdda1 (USER_VDD3V3), + .vdda2 (USER_VDD3V3), + .vssa1 (VSS), + .vssa2 (VSS), + .vccd1 (USER_VDD1V8), + .vccd2 (USER_VDD1V8), + .vssd1 (VSS), + .vssd2 (VSS), + .clock (clock), + .gpio (gpio), + .mprj_io (mprj_io), + .flash_csb(flash_csb), + .flash_clk(flash_clk), + .flash_io0(flash_io0), + .flash_io1(flash_io1), + .resetb (RSTB) + ); + + spiflash #( + .FILENAME("ws2812.hex") + ) spiflash ( + .csb(flash_csb), + .clk(flash_clk), + .io0(flash_io0), + .io1(flash_io1), + .io2(), // not used + .io3() // not used + ); endmodule From e2fff35b7d5170eb3be8431748c5afef7584e7f0 Mon Sep 17 00:00:00 2001 From: Matt Venn Date: Fri, 20 Nov 2020 12:09:10 +0100 Subject: [PATCH 08/32] sync --- verilog/rtl/multi_project_harness | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/verilog/rtl/multi_project_harness b/verilog/rtl/multi_project_harness index bd6eaefc..4afc63cc 160000 --- a/verilog/rtl/multi_project_harness +++ b/verilog/rtl/multi_project_harness @@ -1 +1 @@ -Subproject commit bd6eaefcdd7263992ff2854c37dda923275152af +Subproject commit 4afc63cc87f7c30163066918c31d6106bf3b46f2 From faf6fadccb362a574a3f57bc7deaacfeff9bd0db Mon Sep 17 00:00:00 2001 From: Matt Venn Date: Fri, 20 Nov 2020 13:53:53 +0100 Subject: [PATCH 09/32] reset multi project harness --- .gitmodules | 2 +- verilog/rtl/multi_project_harness | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitmodules b/.gitmodules index 9c6b613e..5e8cd70c 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,3 @@ -[submodule "verilog/rtl/multi-project-harness"] +[submodule "verilog/rtl/multi_project_harness"] path = verilog/rtl/multi_project_harness url = https://github.com/mattvenn/multi-project-harness.git diff --git a/verilog/rtl/multi_project_harness b/verilog/rtl/multi_project_harness index 4afc63cc..af81d55a 160000 --- a/verilog/rtl/multi_project_harness +++ b/verilog/rtl/multi_project_harness @@ -1 +1 @@ -Subproject commit 4afc63cc87f7c30163066918c31d6106bf3b46f2 +Subproject commit af81d55a07de9fbdebf5c7adda3e653dd9855f8d From 27f16a1d22c6f28a8accb15e9cd58a9fbf53ba69 Mon Sep 17 00:00:00 2001 From: Richard Miller Date: Fri, 20 Nov 2020 17:05:52 +0000 Subject: [PATCH 10/32] Add spinet test --- .../caravel/user_proj_example/spinet/Makefile | 42 +++++ .../caravel/user_proj_example/spinet/spinet.c | 65 +++++++ .../user_proj_example/spinet/spinet_tb.v | 175 ++++++++++++++++++ 3 files changed, 282 insertions(+) create mode 100644 verilog/dv/caravel/user_proj_example/spinet/Makefile create mode 100644 verilog/dv/caravel/user_proj_example/spinet/spinet.c create mode 100644 verilog/dv/caravel/user_proj_example/spinet/spinet_tb.v diff --git a/verilog/dv/caravel/user_proj_example/spinet/Makefile b/verilog/dv/caravel/user_proj_example/spinet/Makefile new file mode 100644 index 00000000..5f9cc7a1 --- /dev/null +++ b/verilog/dv/caravel/user_proj_example/spinet/Makefile @@ -0,0 +1,42 @@ +FIRMWARE_PATH = ../.. +RTL_PATH = ../../../../rtl +IP_PATH = ../../../../ip +#MP_PATH = ../../../../rtl/multi_project_harness +BEHAVIOURAL_MODELS = ../../ + +TOOLCHAIN_PREFIX?=/opt/gcc-riscv/bin/riscv32-unknown-elf- +PDK_PATH?=/mnt/extra/vlsi/sky130A + +.SUFFIXES: + +PATTERN = spinet + +all: ${PATTERN:=.vcd} + +hex: ${PATTERN:=.hex} + +%.vvp: %_tb.v %.hex + iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \ + -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \ + $< -o $@ + +%.vcd: %.vvp + vvp $< + +%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s + $(TOOLCHAIN_PREFIX)gcc -mabi=ilp32 -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< + +%.hex: %.elf + $(TOOLCHAIN_PREFIX)objcopy -O verilog $< $@ + # to fix flash base address + sed -i 's/@10000000/@00000000/g' $@ + +%.bin: %.elf + $(TOOLCHAIN_PREFIX)objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ + +# ---- Clean ---- + +clean: + rm -f *.elf *.hex *.bin *.vvp *.vcd *.log + +.PHONY: clean hex all diff --git a/verilog/dv/caravel/user_proj_example/spinet/spinet.c b/verilog/dv/caravel/user_proj_example/spinet/spinet.c new file mode 100644 index 00000000..c8e6caef --- /dev/null +++ b/verilog/dv/caravel/user_proj_example/spinet/spinet.c @@ -0,0 +1,65 @@ +#include "../../defs.h" + +/* + IO Test: + - Configures MPRJ pins + - Nothing else to do: spinet is autonomous +*/ + +#define PROJECT 3 +#define NUMNODES 6 + +void main() +{ + /* + IO Control Registers + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | + + Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | + + Output: 0000_0110_0000_1111 (0x1809) = GPIO_MODE_MGNT_STD_OUTPUT + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | + + + Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | + + */ + + /* + Inputs | Outputs + Node MOSI SCK SS MISO TXRDY RXRDY + 0 0 6 12 18 24 30 + 1 1 7 13 19 25 31 + 2 2 8 14 20 26 32 + 3 3 9 15 21 27 33 + 4 4 10 16 22 28 34 + 5 5 11 17 23 29 35 + + */ + + volatile uint32_t *io = ®_mprj_io_0; + for (int i = 0; i < NUMNODES; i++) { + for (int j = 0; j <= 12; j += 6) + io[i + j] = GPIO_MODE_USER_STD_INPUT_NOPULL; + for (int j = 18; j <= 30; j += 6) + io[i + j] = GPIO_MODE_USER_STD_OUTPUT; + } + + /* Apply configuration */ + reg_mprj_xfer = 1; + while (reg_mprj_xfer == 1); + + // change to project + reg_mprj_slave = PROJECT; + + // use logic analyser bit 0 as reset + reg_la0_ena = 0x00000000; // bits 31:0 outputs + reg_la0_data = 0x00000001; // reset high is on bit 0 + reg_la0_data = 0x00000000; // low +} diff --git a/verilog/dv/caravel/user_proj_example/spinet/spinet_tb.v b/verilog/dv/caravel/user_proj_example/spinet/spinet_tb.v new file mode 100644 index 00000000..bde2222d --- /dev/null +++ b/verilog/dv/caravel/user_proj_example/spinet/spinet_tb.v @@ -0,0 +1,175 @@ +`default_nettype none + +`timescale 1 ns / 1 ps + +`include "caravel.v" +`include "spiflash.v" + +module spinet_tb; + reg clock; + reg ext_clock; + reg RSTB; + reg power1, power2; + reg power3, power4; + + wire gpio; + wire [37:0] mprj_io; + + localparam N = 6; + + // SPI signals for each node + reg [N-1:0] mosi, sck, ss; + wire [N-1:0]miso, txrdy, rxrdy; + assign mprj_io[5:0] = mosi; + assign mprj_io[11:6] = sck; + assign mprj_io[17:12] = ss; + assign miso = mprj_io[23:18]; + assign txrdy = mprj_io[29:24]; + assign rxrdy = mprj_io[35:30]; + + initial begin + sck = 0; + ss = ~0; + mosi = 0; + end + + // External clock is used by default. Make this artificially fast for the + // simulation. Normally this would be a slow clock and the digital PLL + // would be the fast clock. + + always #12.5 clock <= (clock === 1'b0); + always #6.25 ext_clock <= (ext_clock === 1'b0); + + initial begin + clock = 0; + ext_clock = 0; + end + + initial begin + $dumpfile("spinet.vcd"); + $dumpvars(0, spinet_tb); + + // Repeat cycles of 1000 clock edges as needed to complete testbench + repeat (30) begin + repeat (1000) @(posedge clock); + end + $display("%c[1;31m",27); + $display ("Monitor: Timeout, Test Failed"); + $display("%c[0m",27); + $finish; + end + + reg [15:0] snd, rcv; + initial begin + // Wait for initial reset (not clear what signal to wait for?) + #1000; + // Node 2 sends one packet to node 4 + snd <= {2'b10,3'h4,3'h2,8'h42}; + #100 ss[2] <= 0; + #50; + repeat (16) begin + mosi[2] <= snd[15]; + #50 sck[2] <= 1; + rcv <= {rcv[15:0],miso[2]}; + #50 sck[2] <= 0; + snd <= snd << 1; + end + #100 ss[2] <= 1; + // Wait for node 4 to see RXRDY + wait (rxrdy[4] != 0) + // Node 4 reads the packet + snd <= 0; + ss[4] <= 0; + #50 + repeat (16) begin + mosi[4] <= snd[15]; + #50 sck[4] <= 1; + rcv <= {rcv[15:0],miso[4]}; + #50 sck[4] <= 0; + snd <= snd << 1; + end + #100 ss[4] <= 1; + $display("received: %x", rcv); + $display("Monitor: Test Passed"); + $finish; + end + + initial begin + RSTB <= 1'b0; + #2000; + RSTB <= 1'b1; // Release reset + end + + initial begin // Power-up sequence + power1 <= 1'b0; + power2 <= 1'b0; + power3 <= 1'b0; + power4 <= 1'b0; + #200; + power1 <= 1'b1; + #200; + power2 <= 1'b1; + #200; + power3 <= 1'b1; + #200; + power4 <= 1'b1; + end + + /* + always @(mprj_io) begin + #1 $display("MPRJ-IO state = %b ", mprj_io[7:0]); + end + */ + + wire flash_csb; + wire flash_clk; + wire flash_io0; + wire flash_io1; + + wire VDD1V8; + wire VDD3V3; + wire VSS; + + assign VDD3V3 = power1; + assign VDD1V8 = power2; + assign USER_VDD3V3 = power3; + assign USER_VDD1V8 = power4; + assign VSS = 1'b0; + + caravel uut ( + .vddio (VDD3V3), + .vssio (VSS), + .vdda (VDD3V3), + .vssa (VSS), + .vccd (VDD1V8), + .vssd (VSS), + .vdda1 (USER_VDD3V3), + .vdda2 (USER_VDD3V3), + .vssa1 (VSS), + .vssa2 (VSS), + .vccd1 (USER_VDD1V8), + .vccd2 (USER_VDD1V8), + .vssd1 (VSS), + .vssd2 (VSS), + .clock (clock), + .gpio (gpio), + .mprj_io (mprj_io), + .flash_csb(flash_csb), + .flash_clk(flash_clk), + .flash_io0(flash_io0), + .flash_io1(flash_io1), + .resetb (RSTB) + ); + + spiflash #( + .FILENAME("spinet.hex") + ) spiflash ( + .csb(flash_csb), + .clk(flash_clk), + .io0(flash_io0), + .io1(flash_io1), + .io2(), // not used + .io3() // not used + ); + +endmodule From f7492b86f51a72cfcd54d11ba64ef3a4bb4433ca Mon Sep 17 00:00:00 2001 From: Richard Miller Date: Sat, 21 Nov 2020 08:52:46 +0000 Subject: [PATCH 11/32] spinet test: add -O2 to gcc compilation and reduce number of activated nodes Test was timing out because the configuration in the firmware was taking too many cycles. Make it quicker by compiling with optimisation and configuring the signals for only two nodes. --- .../caravel/user_proj_example/spinet/Makefile | 2 +- .../caravel/user_proj_example/spinet/spinet.c | 18 ++++++- .../user_proj_example/spinet/spinet_tb.v | 48 ++++++++++--------- 3 files changed, 44 insertions(+), 24 deletions(-) diff --git a/verilog/dv/caravel/user_proj_example/spinet/Makefile b/verilog/dv/caravel/user_proj_example/spinet/Makefile index 5f9cc7a1..cee341c5 100644 --- a/verilog/dv/caravel/user_proj_example/spinet/Makefile +++ b/verilog/dv/caravel/user_proj_example/spinet/Makefile @@ -24,7 +24,7 @@ hex: ${PATTERN:=.hex} vvp $< %.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s - $(TOOLCHAIN_PREFIX)gcc -mabi=ilp32 -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< + $(TOOLCHAIN_PREFIX)gcc -O2 -mabi=ilp32 -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< %.hex: %.elf $(TOOLCHAIN_PREFIX)objcopy -O verilog $< $@ diff --git a/verilog/dv/caravel/user_proj_example/spinet/spinet.c b/verilog/dv/caravel/user_proj_example/spinet/spinet.c index c8e6caef..0938c018 100644 --- a/verilog/dv/caravel/user_proj_example/spinet/spinet.c +++ b/verilog/dv/caravel/user_proj_example/spinet/spinet.c @@ -7,7 +7,7 @@ */ #define PROJECT 3 -#define NUMNODES 6 +#define NUMNODES 2 void main() { @@ -44,12 +44,27 @@ void main() */ volatile uint32_t *io = ®_mprj_io_0; +#ifndef notdef for (int i = 0; i < NUMNODES; i++) { for (int j = 0; j <= 12; j += 6) io[i + j] = GPIO_MODE_USER_STD_INPUT_NOPULL; for (int j = 18; j <= 30; j += 6) io[i + j] = GPIO_MODE_USER_STD_OUTPUT; } +#else + reg_mprj_io_0 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_1 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_6 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_7 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_12 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_13 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_18 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_19 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_24 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_25 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_30 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_31 = GPIO_MODE_USER_STD_OUTPUT; +#endif /* Apply configuration */ reg_mprj_xfer = 1; @@ -62,4 +77,5 @@ void main() reg_la0_ena = 0x00000000; // bits 31:0 outputs reg_la0_data = 0x00000001; // reset high is on bit 0 reg_la0_data = 0x00000000; // low + } diff --git a/verilog/dv/caravel/user_proj_example/spinet/spinet_tb.v b/verilog/dv/caravel/user_proj_example/spinet/spinet_tb.v index bde2222d..9671d569 100644 --- a/verilog/dv/caravel/user_proj_example/spinet/spinet_tb.v +++ b/verilog/dv/caravel/user_proj_example/spinet/spinet_tb.v @@ -50,7 +50,7 @@ module spinet_tb; $dumpvars(0, spinet_tb); // Repeat cycles of 1000 clock edges as needed to complete testbench - repeat (30) begin + repeat (15) begin repeat (1000) @(posedge clock); end $display("%c[1;31m",27); @@ -61,36 +61,40 @@ module spinet_tb; reg [15:0] snd, rcv; initial begin - // Wait for initial reset (not clear what signal to wait for?) - #1000; - // Node 2 sends one packet to node 4 - snd <= {2'b10,3'h4,3'h2,8'h42}; - #100 ss[2] <= 0; + // Wait for initial reset + wait (uut.la_data_in_mprj[0] === 1'b1); + wait (uut.la_data_in_mprj[0] === 1'b0); + // Node 0 sends one packet to node 1 + snd <= {2'b10,3'h1,3'h0,8'h42}; + #100 ss[0] <= 0; #50; repeat (16) begin - mosi[2] <= snd[15]; - #50 sck[2] <= 1; - rcv <= {rcv[15:0],miso[2]}; - #50 sck[2] <= 0; + #50 mosi[0] <= snd[15]; + sck[0] <= 1; + #50 rcv <= {rcv[14:0],miso[0]}; + sck[0] <= 0; snd <= snd << 1; end - #100 ss[2] <= 1; - // Wait for node 4 to see RXRDY - wait (rxrdy[4] != 0) - // Node 4 reads the packet + #100 ss[0] <= 1; + // Wait for node 1 to see RXRDY + wait (rxrdy[1] != 0) + // Node 1 reads the packet snd <= 0; - ss[4] <= 0; + ss[1] <= 0; #50 repeat (16) begin - mosi[4] <= snd[15]; - #50 sck[4] <= 1; - rcv <= {rcv[15:0],miso[4]}; - #50 sck[4] <= 0; + #50 mosi[1] <= snd[15]; + sck[1] <= 1; + #50 rcv <= {rcv[14:0],miso[1]}; + sck[1] <= 0; snd <= snd << 1; end - #100 ss[4] <= 1; - $display("received: %x", rcv); - $display("Monitor: Test Passed"); + #100 ss[1] <= 1; + $display("received: %h", rcv); + if (rcv == {2'b10,3'h1,3'h0,8'h42}) + $display("Monitor: Test Passed"); + else + $display("Monitor: Test Failed"); $finish; end From f773d1fa06af65d8c2aafb9bced72ffe4518ba04 Mon Sep 17 00:00:00 2001 From: Richard Miller Date: Sat, 21 Nov 2020 10:18:24 +0000 Subject: [PATCH 12/32] spinet test: configure signals for 4 nodes --- .../caravel/user_proj_example/spinet/spinet.c | 17 +---------------- 1 file changed, 1 insertion(+), 16 deletions(-) diff --git a/verilog/dv/caravel/user_proj_example/spinet/spinet.c b/verilog/dv/caravel/user_proj_example/spinet/spinet.c index 0938c018..4759a524 100644 --- a/verilog/dv/caravel/user_proj_example/spinet/spinet.c +++ b/verilog/dv/caravel/user_proj_example/spinet/spinet.c @@ -7,7 +7,7 @@ */ #define PROJECT 3 -#define NUMNODES 2 +#define NUMNODES 4 void main() { @@ -44,27 +44,12 @@ void main() */ volatile uint32_t *io = ®_mprj_io_0; -#ifndef notdef for (int i = 0; i < NUMNODES; i++) { for (int j = 0; j <= 12; j += 6) io[i + j] = GPIO_MODE_USER_STD_INPUT_NOPULL; for (int j = 18; j <= 30; j += 6) io[i + j] = GPIO_MODE_USER_STD_OUTPUT; } -#else - reg_mprj_io_0 = GPIO_MODE_USER_STD_INPUT_NOPULL; - reg_mprj_io_1 = GPIO_MODE_USER_STD_INPUT_NOPULL; - reg_mprj_io_6 = GPIO_MODE_USER_STD_INPUT_NOPULL; - reg_mprj_io_7 = GPIO_MODE_USER_STD_INPUT_NOPULL; - reg_mprj_io_12 = GPIO_MODE_USER_STD_INPUT_NOPULL; - reg_mprj_io_13 = GPIO_MODE_USER_STD_INPUT_NOPULL; - reg_mprj_io_18 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_19 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_24 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_25 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_30 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_31 = GPIO_MODE_USER_STD_OUTPUT; -#endif /* Apply configuration */ reg_mprj_xfer = 1; From 5ae1c1b6064073aea69641a9c0d925568a0a5bff Mon Sep 17 00:00:00 2001 From: Richard Miller Date: Sun, 22 Nov 2020 19:18:15 +0000 Subject: [PATCH 13/32] spinet: expand test to exchange packets with all 6 nodes --- .../caravel/user_proj_example/spinet/spinet.c | 2 +- .../user_proj_example/spinet/spinet_tb.v | 139 +++++++++++++----- 2 files changed, 101 insertions(+), 40 deletions(-) diff --git a/verilog/dv/caravel/user_proj_example/spinet/spinet.c b/verilog/dv/caravel/user_proj_example/spinet/spinet.c index 4759a524..29997e67 100644 --- a/verilog/dv/caravel/user_proj_example/spinet/spinet.c +++ b/verilog/dv/caravel/user_proj_example/spinet/spinet.c @@ -7,7 +7,7 @@ */ #define PROJECT 3 -#define NUMNODES 4 +#define NUMNODES 6 void main() { diff --git a/verilog/dv/caravel/user_proj_example/spinet/spinet_tb.v b/verilog/dv/caravel/user_proj_example/spinet/spinet_tb.v index 9671d569..35f98a0a 100644 --- a/verilog/dv/caravel/user_proj_example/spinet/spinet_tb.v +++ b/verilog/dv/caravel/user_proj_example/spinet/spinet_tb.v @@ -18,19 +18,20 @@ module spinet_tb; localparam N = 6; // SPI signals for each node - reg [N-1:0] mosi, sck, ss; - wire [N-1:0]miso, txrdy, rxrdy; - assign mprj_io[5:0] = mosi; - assign mprj_io[11:6] = sck; - assign mprj_io[17:12] = ss; + reg mosi0, sck0, ss0; + wire [N-1:0] mosi, sck, ss; + wire [N-1:0] miso, txrdy, rxrdy; + assign mprj_io[5:0] = {mosi[5:1],mosi0}; + assign mprj_io[11:6] = {sck[5:1],sck0}; + assign mprj_io[17:12] = {ss[5:1],ss0}; assign miso = mprj_io[23:18]; assign txrdy = mprj_io[29:24]; assign rxrdy = mprj_io[35:30]; initial begin - sck = 0; - ss = ~0; - mosi = 0; + sck0 = 0; + ss0 = ~0; + mosi0 = 0; end // External clock is used by default. Make this artificially fast for the @@ -50,7 +51,7 @@ module spinet_tb; $dumpvars(0, spinet_tb); // Repeat cycles of 1000 clock edges as needed to complete testbench - repeat (15) begin + repeat (50) begin repeat (1000) @(posedge clock); end $display("%c[1;31m",27); @@ -59,45 +60,62 @@ module spinet_tb; $finish; end - reg [15:0] snd, rcv; + reg [15:0] snd, rcv, sent; + reg [N-1:0] echoed = 1; initial begin // Wait for initial reset wait (uut.la_data_in_mprj[0] === 1'b1); wait (uut.la_data_in_mprj[0] === 1'b0); - // Node 0 sends one packet to node 1 - snd <= {2'b10,3'h1,3'h0,8'h42}; - #100 ss[0] <= 0; - #50; - repeat (16) begin - #50 mosi[0] <= snd[15]; - sck[0] <= 1; - #50 rcv <= {rcv[14:0],miso[0]}; - sck[0] <= 0; - snd <= snd << 1; + // Node 0 sends one packet to each other node + for (integer i = 1; i < N; i = i + 1) begin + snd <= {2'b10,3'h0,3'h0,8'h40}; + snd[13:11] <= i; + snd[2:0] <= i; + #100 ss0 <= 0; + sent <= snd; + #50; + repeat (16) begin + #50 mosi0 <= snd[15]; + sck0 <= 1; + #50 rcv <= {rcv[14:0],miso[0]}; + sck0 <= 0; + snd <= snd << 1; + end + #100 ss0 <= 1; + $display("sent %h received: %h", sent, rcv); + if (rcv[15]) + echoed[rcv[10:8]] = 1; + end - #100 ss[0] <= 1; - // Wait for node 1 to see RXRDY - wait (rxrdy[1] != 0) - // Node 1 reads the packet + #100 ss0 <= 1; + // Read packets echoed back by other nodes snd <= 0; - ss[1] <= 0; - #50 - repeat (16) begin - #50 mosi[1] <= snd[15]; - sck[1] <= 1; - #50 rcv <= {rcv[14:0],miso[1]}; - sck[1] <= 0; - snd <= snd << 1; + while (&echoed == 0) begin + wait (rxrdy[0] === 1'b1); + ss0 <= 0; + #50; + repeat (16) begin + #50 mosi0 <= snd[15]; + sck0 <= 1; + #50 rcv <= {rcv[14:0],miso[0]}; + sck0 <= 0; + snd <= snd << 1; + end + sent <= snd; + #100 ss0 <= 1; + $display("sent %h received: %h", sent, rcv); + if (rcv[15]) + echoed[rcv[10:8]] = 1; end - #100 ss[1] <= 1; - $display("received: %h", rcv); - if (rcv == {2'b10,3'h1,3'h0,8'h42}) - $display("Monitor: Test Passed"); - else - $display("Monitor: Test Failed"); - $finish; + $display("Monitor: Test Passed"); + $finish; end + genvar node; + generate for (node = 1; node < N; node = node + 1) + echo ECHO (mosi[node], sck[node], ss[node], miso[node], txrdy[node], rxrdy[node]); + endgenerate + initial begin RSTB <= 1'b0; #2000; @@ -177,3 +195,46 @@ module spinet_tb; ); endmodule + +// SPI host emulation to read and echo packets +module echo ( + output reg mosi, + output reg sck, + output reg ss, + input miso, + input txrdy, + input rxrdy); + + reg [15:0] pkt = 0; + initial begin + ss = 1; + sck = 0; + mosi = 0; + end + always @(posedge rxrdy) begin + // receive a packet + ss <= 0; + sck <= 0; + mosi <= 0; + #50; + repeat (16) begin + #50 sck <= 1; + #50 pkt <= {pkt[14:0],miso}; + sck <= 0; + end + #100 ss <= 1; + // swap sender and receiver address + pkt[13:8] <= {pkt[10:8],pkt[13:11]}; + // send the packet back + #50 ss <= 0; + #50; + repeat (16) begin + #50 mosi <= pkt[15]; + sck <= 1; + #50 sck <= 0; + pkt <= pkt << 1; + end + #100 ss <= 1; + end + +endmodule From b7ab6627fe4dbbb1ff713c0176a2358793098771 Mon Sep 17 00:00:00 2001 From: Matt Venn Date: Wed, 25 Nov 2020 11:31:22 +0100 Subject: [PATCH 14/32] sync --- verilog/rtl/multi_project_harness | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/verilog/rtl/multi_project_harness b/verilog/rtl/multi_project_harness index af81d55a..e0454194 160000 --- a/verilog/rtl/multi_project_harness +++ b/verilog/rtl/multi_project_harness @@ -1 +1 @@ -Subproject commit af81d55a07de9fbdebf5c7adda3e653dd9855f8d +Subproject commit e0454194272f426a7b40ba3bd48b3a56537e807f From 8f85cee146a269b078470f3cf0126f2240cd7b2a Mon Sep 17 00:00:00 2001 From: Matt Venn Date: Thu, 26 Nov 2020 10:44:52 +0100 Subject: [PATCH 15/32] add gpio pads --- .../seven-segment-counter/seven_segment.gtkw | 65 +++++++++++++------ 1 file changed, 44 insertions(+), 21 deletions(-) diff --git a/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment.gtkw b/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment.gtkw index 91e9a67b..cb3e4fb8 100644 --- a/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment.gtkw +++ b/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment.gtkw @@ -1,20 +1,27 @@ [*] [*] GTKWave Analyzer v3.3.108 (w)1999-2020 BSI -[*] Wed Nov 18 13:22:40 2020 +[*] Thu Nov 26 09:42:48 2020 [*] -[dumpfile] "/home/matt/work/asic-workshop/caravel/verilog/dv/caravel/user_proj_example/seven-segment-counter/io_ports.vcd" -[dumpfile_mtime] "Wed Nov 18 13:21:30 2020" -[dumpfile_size] 107734924 -[savefile] "/home/matt/work/asic-workshop/caravel/verilog/dv/caravel/user_proj_example/seven-segment-counter/gpio.gtkw" -[timestart] 187492000 -[size] 2434 1411 -[pos] -1 -1 -*-20.000000 192189000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[dumpfile] "/home/matt/work/asic-workshop/caravel/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment.vcd" +[dumpfile_mtime] "Thu Nov 26 09:21:48 2020" +[dumpfile_size] 194118743 +[savefile] "/home/matt/work/asic-workshop/caravel/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment.gtkw" +[timestart] 242220000 +[size] 2371 1293 +[pos] 76 53 +*-22.000000 245760000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] seven_segment_tb. [treeopen] seven_segment_tb.uut. +[treeopen] seven_segment_tb.uut.gpio_control_bidir[0]. [treeopen] seven_segment_tb.uut.gpio_control_bidir[0].gpio_in_buf. +[treeopen] seven_segment_tb.uut.gpio_control_bidir[0].gpio_logic_high. +[treeopen] seven_segment_tb.uut.gpio_control_in[2]. +[treeopen] seven_segment_tb.uut.gpio_control_in[3]. +[treeopen] seven_segment_tb.uut.gpio_control_in[4]. [treeopen] seven_segment_tb.uut.gpio_control_in[4].gpio_in_buf. [treeopen] seven_segment_tb.uut.gpio_control_in[4].gpio_logic_high. +[treeopen] seven_segment_tb.uut.gpio_control_in[8]. +[treeopen] seven_segment_tb.uut.gpio_control_in[9]. [treeopen] seven_segment_tb.uut.mprj. [treeopen] seven_segment_tb.uut.mprj.mprj. [treeopen] seven_segment_tb.uut.mprj.mprj.proj_0. @@ -26,9 +33,9 @@ [treeopen] seven_segment_tb.uut.soc.soc.gpio_wb. [treeopen] seven_segment_tb.uut.soc.soc.mprj_ctrl. [sst_width] 719 -[signals_width] 682 +[signals_width] 1098 [sst_expanded] 1 -[sst_vpaned_height] 862 +[sst_vpaned_height] 710 @28 seven_segment_tb.clock seven_segment_tb.RSTB @@ -52,9 +59,6 @@ seven_segment_tb.uut.mprj.mprj.wbs_sel_i[3:0] @28 seven_segment_tb.uut.mprj.mprj.wbs_stb_i seven_segment_tb.uut.mprj.mprj.wbs_we_i -seven_segment_tb.uut.mprj.mprj.valid -@24 -seven_segment_tb.uut.mprj.mprj.wstrb[3:0] @1000200 -wbs @800200 @@ -124,7 +128,7 @@ seven_segment_tb.uut.mprj.io_in[37:0] (37)seven_segment_tb.uut.mprj.io_in[37:0] @1401200 -group_end -@c00022 +@800022 seven_segment_tb.uut.mprj.mprj.io_out[37:0] @28 (0)seven_segment_tb.uut.mprj.mprj.io_out[37:0] @@ -165,11 +169,13 @@ seven_segment_tb.uut.mprj.mprj.io_out[37:0] (35)seven_segment_tb.uut.mprj.mprj.io_out[37:0] (36)seven_segment_tb.uut.mprj.mprj.io_out[37:0] (37)seven_segment_tb.uut.mprj.mprj.io_out[37:0] -@1401200 +@1001200 -group_end +@22 +seven_segment_tb.uut.mprj.mprj.io_oeb[37:0] @1000200 -multi project -@800022 +@c00022 seven_segment_tb.mprj_io[37:0] @28 (0)seven_segment_tb.mprj_io[37:0] @@ -202,9 +208,7 @@ seven_segment_tb.mprj_io[37:0] (27)seven_segment_tb.mprj_io[37:0] (28)seven_segment_tb.mprj_io[37:0] (29)seven_segment_tb.mprj_io[37:0] -@29 (30)seven_segment_tb.mprj_io[37:0] -@28 (31)seven_segment_tb.mprj_io[37:0] (32)seven_segment_tb.mprj_io[37:0] (33)seven_segment_tb.mprj_io[37:0] @@ -258,7 +262,7 @@ seven_segment_tb.uut.mprj.mprj.io_out[37:0] @22 seven_segment_tb.uut.mprj.mprj.io_oeb[37:0] seven_segment_tb.uut.mprj.mprj.io_in[37:0] -@1001200 +@1401200 -group_end @800200 -seven seg @@ -277,11 +281,30 @@ seven_segment_tb.uut.mprj.mprj.proj_0.digit[3:0] (1)seven_segment_tb.uut.mprj.mprj.proj_0.digit[3:0] (2)seven_segment_tb.uut.mprj.mprj.proj_0.digit[3:0] (3)seven_segment_tb.uut.mprj.mprj.proj_0.digit[3:0] -@22 +@200 +- +@800022 seven_segment_tb.uut.mprj.mprj.proj_0.led_out[6:0] +@28 +(0)seven_segment_tb.uut.mprj.mprj.proj_0.led_out[6:0] +(1)seven_segment_tb.uut.mprj.mprj.proj_0.led_out[6:0] +(2)seven_segment_tb.uut.mprj.mprj.proj_0.led_out[6:0] +(3)seven_segment_tb.uut.mprj.mprj.proj_0.led_out[6:0] +(4)seven_segment_tb.uut.mprj.mprj.proj_0.led_out[6:0] +(5)seven_segment_tb.uut.mprj.mprj.proj_0.led_out[6:0] +(6)seven_segment_tb.uut.mprj.mprj.proj_0.led_out[6:0] @1001200 -group_end +-group_end @1000200 -seven seg +@28 +seven_segment_tb.uut.gpio_control_in[8].pad_gpio_out +seven_segment_tb.uut.gpio_control_in[7].pad_gpio_out +seven_segment_tb.uut.gpio_control_in[6].pad_gpio_out +seven_segment_tb.uut.gpio_control_in[5].pad_gpio_out +seven_segment_tb.uut.gpio_control_in[4].pad_gpio_out +seven_segment_tb.uut.gpio_control_in[3].pad_gpio_out +seven_segment_tb.uut.gpio_control_in[2].pad_gpio_out [pattern_trace] 1 [pattern_trace] 0 From fa5a67879e3076af4b1b21658a46ad25c527c4e4 Mon Sep 17 00:00:00 2001 From: Matt Venn Date: Thu, 26 Nov 2020 11:52:56 +0100 Subject: [PATCH 16/32] monitor actual gpio out pads --- .../seven-segment-counter/seven_segment_tb.v | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment_tb.v b/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment_tb.v index 48a5a971..5315be33 100644 --- a/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment_tb.v +++ b/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment_tb.v @@ -15,7 +15,16 @@ module seven_segment_tb; wire [37:0] mprj_io; wire [6:0] segments; - assign segments = mprj_io[8:2]; + + assign segments = { + uut.gpio_control_in[8].pad_gpio_out, + uut.gpio_control_in[7].pad_gpio_out, + uut.gpio_control_in[6].pad_gpio_out, + uut.gpio_control_in[5].pad_gpio_out, + uut.gpio_control_in[4].pad_gpio_out, + uut.gpio_control_in[3].pad_gpio_out, + uut.gpio_control_in[2].pad_gpio_out + }; // External clock is used by default. Make this artificially fast for the // simulation. Normally this would be a slow clock and the digital PLL @@ -88,13 +97,13 @@ module seven_segment_tb; end */ - wire flash_csb; + wire flash_csb; wire flash_clk; wire flash_io0; wire flash_io1; wire VDD1V8; - wire VDD3V3; + wire VDD3V3; wire VSS; assign VDD3V3 = power1; @@ -120,7 +129,7 @@ module seven_segment_tb; .vssd2 (VSS), .clock (clock), .gpio (gpio), - .mprj_io (mprj_io), + .mprj_io (mprj_io), .flash_csb(flash_csb), .flash_clk(flash_clk), .flash_io0(flash_io0), From c229f2ac97a17583b0be840296d022989b79ac05 Mon Sep 17 00:00:00 2001 From: Matt Venn Date: Thu, 26 Nov 2020 12:32:18 +0100 Subject: [PATCH 17/32] sync --- verilog/rtl/multi_project_harness | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/verilog/rtl/multi_project_harness b/verilog/rtl/multi_project_harness index e0454194..de57c12e 160000 --- a/verilog/rtl/multi_project_harness +++ b/verilog/rtl/multi_project_harness @@ -1 +1 @@ -Subproject commit e0454194272f426a7b40ba3bd48b3a56537e807f +Subproject commit de57c12e38e8cce4afcac8ce303d24e1ce342b97 From fb86a56b514db053841ed111f667e27d4926922c Mon Sep 17 00:00:00 2001 From: Matt Venn Date: Thu, 26 Nov 2020 15:12:28 +0100 Subject: [PATCH 18/32] io port changed --- .../seven-segment-counter/seven_segment.c | 19 ++++++------- .../seven-segment-counter/seven_segment.gtkw | 27 ++++++++++++++----- .../seven-segment-counter/seven_segment_tb.v | 14 +++++----- .../caravel/user_proj_example/ws2812/ws2812.c | 10 ++++--- 4 files changed, 41 insertions(+), 29 deletions(-) diff --git a/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment.c b/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment.c index 2d068f3c..4ae44afd 100644 --- a/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment.c +++ b/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment.c @@ -36,21 +36,18 @@ void main() system clock system reset - Outputs - 8:2 seven segment LEDs + 14:8 seven segment LEDs */ - //reg_mprj_io_0 = GPIO_MODE_USER_STD_INPUT_NOPULL; - //reg_mprj_io_1 = GPIO_MODE_USER_STD_INPUT_NOPULL; - reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_6 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_9 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT; /* Apply configuration */ reg_mprj_xfer = 1; diff --git a/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment.gtkw b/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment.gtkw index cb3e4fb8..997863d1 100644 --- a/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment.gtkw +++ b/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment.gtkw @@ -1,15 +1,15 @@ [*] [*] GTKWave Analyzer v3.3.108 (w)1999-2020 BSI -[*] Thu Nov 26 09:42:48 2020 +[*] Thu Nov 26 10:51:35 2020 [*] [dumpfile] "/home/matt/work/asic-workshop/caravel/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment.vcd" -[dumpfile_mtime] "Thu Nov 26 09:21:48 2020" -[dumpfile_size] 194118743 +[dumpfile_mtime] "Thu Nov 26 10:46:55 2020" +[dumpfile_size] 101432617 [savefile] "/home/matt/work/asic-workshop/caravel/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment.gtkw" -[timestart] 242220000 +[timestart] 141660000 [size] 2371 1293 -[pos] 76 53 -*-22.000000 245760000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[pos] -1 -1 +*-24.000000 192362500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] seven_segment_tb. [treeopen] seven_segment_tb.uut. [treeopen] seven_segment_tb.uut.gpio_control_bidir[0]. @@ -298,13 +298,26 @@ seven_segment_tb.uut.mprj.mprj.proj_0.led_out[6:0] -group_end @1000200 -seven seg -@28 +@29 seven_segment_tb.uut.gpio_control_in[8].pad_gpio_out +@28 seven_segment_tb.uut.gpio_control_in[7].pad_gpio_out seven_segment_tb.uut.gpio_control_in[6].pad_gpio_out seven_segment_tb.uut.gpio_control_in[5].pad_gpio_out seven_segment_tb.uut.gpio_control_in[4].pad_gpio_out seven_segment_tb.uut.gpio_control_in[3].pad_gpio_out seven_segment_tb.uut.gpio_control_in[2].pad_gpio_out +@800022 +seven_segment_tb.segments[6:0] +@28 +(0)seven_segment_tb.segments[6:0] +(1)seven_segment_tb.segments[6:0] +(2)seven_segment_tb.segments[6:0] +(3)seven_segment_tb.segments[6:0] +(4)seven_segment_tb.segments[6:0] +(5)seven_segment_tb.segments[6:0] +(6)seven_segment_tb.segments[6:0] +@1001200 +-group_end [pattern_trace] 1 [pattern_trace] 0 diff --git a/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment_tb.v b/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment_tb.v index 5315be33..70d182b4 100644 --- a/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment_tb.v +++ b/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment_tb.v @@ -17,13 +17,13 @@ module seven_segment_tb; assign segments = { - uut.gpio_control_in[8].pad_gpio_out, - uut.gpio_control_in[7].pad_gpio_out, - uut.gpio_control_in[6].pad_gpio_out, - uut.gpio_control_in[5].pad_gpio_out, - uut.gpio_control_in[4].pad_gpio_out, - uut.gpio_control_in[3].pad_gpio_out, - uut.gpio_control_in[2].pad_gpio_out + uut.gpio_control_in[14].pad_gpio_out, + uut.gpio_control_in[13].pad_gpio_out, + uut.gpio_control_in[12].pad_gpio_out, + uut.gpio_control_in[11].pad_gpio_out, + uut.gpio_control_in[10].pad_gpio_out, + uut.gpio_control_in[ 9].pad_gpio_out, + uut.gpio_control_in[ 8].pad_gpio_out }; // External clock is used by default. Make this artificially fast for the diff --git a/verilog/dv/caravel/user_proj_example/ws2812/ws2812.c b/verilog/dv/caravel/user_proj_example/ws2812/ws2812.c index c077b2e2..b04ef429 100644 --- a/verilog/dv/caravel/user_proj_example/ws2812/ws2812.c +++ b/verilog/dv/caravel/user_proj_example/ws2812/ws2812.c @@ -5,6 +5,8 @@ - Configures MPRJ pins - Observes counter value through the LED digits */ +#define reg_mprj_oeb0 (*(volatile uint32_t*)0x30000004) +#define reg_mprj_oeb1 (*(volatile uint32_t*)0x30000008) #define reg_mprj_ws2812 (*(volatile uint32_t*)0x30000100) @@ -36,13 +38,12 @@ void main() system clock system reset - Outputs - 2 data for ws2812 + 8 data for ws2812 */ - reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT; /* Apply configuration */ reg_mprj_xfer = 1; @@ -50,6 +51,8 @@ void main() // change to project 1 reg_mprj_slave = 1; + // all outputs enabled + reg_mprj_oeb0 = 0; // use logic analyser to reset the design reg_la0_ena = 0x00000000; // bits 31:0 outputs @@ -63,4 +66,3 @@ void main() uint8_t b = 100; reg_mprj_ws2812 = (led_num << 24) + (r << 16) + (g << 8) + b; } - From 0b295006a8120cfe8dbc0d195f53c04b262b4d4c Mon Sep 17 00:00:00 2001 From: Matt Venn Date: Thu, 26 Nov 2020 15:12:38 +0100 Subject: [PATCH 19/32] changed io port --- .../user_proj_example/vga-clock/vga_clock.c | 38 ++++++++------ .../vga-clock/vga_clock.gtkw | 38 +++++++++----- .../vga-clock/vga_clock_tb.v | 52 +++++++++++++++++-- 3 files changed, 93 insertions(+), 35 deletions(-) diff --git a/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock.c b/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock.c index 210e0cfe..a6fe3fc8 100644 --- a/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock.c +++ b/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock.c @@ -1,5 +1,7 @@ #include "../../defs.h" +#define reg_mprj_oeb0 (*(volatile uint32_t*)0x30000004) +#define reg_mprj_oeb1 (*(volatile uint32_t*)0x30000008) /* IO Test: - Configures MPRJ pins @@ -33,32 +35,31 @@ void main() system clock system reset - 2 adj hours - 3 adj min - 4 adj sec - + 8 adj hours + 9 adj min + 10 adj sec Outputs - 5 hsync - 6 vsync - 7-12 rrggbb + 11 hsync + 12 vsync + 13-18 rrggbb */ - reg_mprj_io_2 = GPIO_MODE_USER_STD_INPUT_NOPULL; - reg_mprj_io_3 = GPIO_MODE_USER_STD_INPUT_NOPULL; - reg_mprj_io_4 = GPIO_MODE_USER_STD_INPUT_NOPULL; - - reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_6 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_8 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_9 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_10 = GPIO_MODE_USER_STD_INPUT_NOPULL; - reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_9 = GPIO_MODE_USER_STD_OUTPUT; - reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT; reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT; reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_16 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_17 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_18 = GPIO_MODE_USER_STD_OUTPUT; + /* Apply configuration */ reg_mprj_xfer = 1; while (reg_mprj_xfer == 1); @@ -66,6 +67,9 @@ void main() // change to project 2 reg_mprj_slave = 2; + // setup oeb, low for output, high for input + reg_mprj_oeb0 = (1 << 8) + (1 << 9) + (1 << 10); + // use logic analyser to reset the design reg_la0_ena = 0x00000000; // bits 31:0 outputs reg_la0_data = 0x00000001; // reset high is on bit 0 diff --git a/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock.gtkw b/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock.gtkw index 22f2bef5..78a082e6 100644 --- a/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock.gtkw +++ b/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock.gtkw @@ -1,20 +1,22 @@ [*] [*] GTKWave Analyzer v3.3.108 (w)1999-2020 BSI -[*] Fri Nov 20 10:42:39 2020 +[*] Thu Nov 26 13:29:36 2020 [*] [dumpfile] "/home/matt/work/asic-workshop/caravel/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock.vcd" -[dumpfile_mtime] "Fri Nov 20 10:36:44 2020" -[dumpfile_size] 192004694 +[dumpfile_mtime] "Thu Nov 26 13:28:55 2020" +[dumpfile_size] 194298414 [savefile] "/home/matt/work/asic-workshop/caravel/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock.gtkw" -[timestart] 136100000 -[size] 2488 1529 +[timestart] 0 +[size] 1700 1529 [pos] -1 -1 -*-25.000000 266612500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +*-28.000000 253000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] vga_clock_tb. [treeopen] vga_clock_tb.uut. [treeopen] vga_clock_tb.uut.gpio_control_bidir[0].gpio_in_buf. [treeopen] vga_clock_tb.uut.gpio_control_in[4].gpio_in_buf. [treeopen] vga_clock_tb.uut.gpio_control_in[4].gpio_logic_high. +[treeopen] vga_clock_tb.uut.gpio_control_in[8]. +[treeopen] vga_clock_tb.uut.gpio_control_in[8].gpio_in_buf. [treeopen] vga_clock_tb.uut.mprj. [treeopen] vga_clock_tb.uut.mprj.mprj. [treeopen] vga_clock_tb.uut.mprj.mprj.proj_0. @@ -26,8 +28,8 @@ [treeopen] vga_clock_tb.uut.soc.soc.cpu.picorv32_core. [treeopen] vga_clock_tb.uut.soc.soc.gpio_wb. [treeopen] vga_clock_tb.uut.soc.soc.mprj_ctrl. -[sst_width] 719 -[signals_width] 682 +[sst_width] 506 +[signals_width] 741 [sst_expanded] 1 [sst_vpaned_height] 862 @28 @@ -53,9 +55,6 @@ vga_clock_tb.uut.mprj.mprj.wbs_sel_i[3:0] @28 vga_clock_tb.uut.mprj.mprj.wbs_stb_i vga_clock_tb.uut.mprj.mprj.wbs_we_i -vga_clock_tb.uut.mprj.mprj.valid -@24 -vga_clock_tb.uut.mprj.mprj.wstrb[3:0] @1000200 -wbs @800200 @@ -80,6 +79,8 @@ vga_clock_tb.uut.soc.soc.cpu.picorv32_core.next_insn_opcode[31:0] -multi project @22 vga_clock_tb.uut.mprj.mprj.active_project[7:0] +@23 +vga_clock_tb.uut.mprj.mprj.reg_oeb[37:0] @28 vga_clock_tb.uut.mprj.mprj.wb_rst_i @c00022 @@ -125,7 +126,7 @@ vga_clock_tb.uut.mprj.io_in[37:0] (37)vga_clock_tb.uut.mprj.io_in[37:0] @1401200 -group_end -@800022 +@c00022 vga_clock_tb.uut.mprj.mprj.io_out[37:0] @28 (0)vga_clock_tb.uut.mprj.mprj.io_out[37:0] @@ -166,13 +167,22 @@ vga_clock_tb.uut.mprj.mprj.io_out[37:0] (35)vga_clock_tb.uut.mprj.mprj.io_out[37:0] (36)vga_clock_tb.uut.mprj.mprj.io_out[37:0] (37)vga_clock_tb.uut.mprj.mprj.io_out[37:0] -@1001200 +@1401200 -group_end @1000200 -multi project @28 vga_clock_tb.uut.mprj.mprj.proj_2.reset -@29 +@22 +vga_clock_tb.uut.mprj.mprj.proj_2.hrs_u[3:0] +@28 +vga_clock_tb.uut.mprj.mprj.proj_2.hrs_d[1:0] +vga_clock_tb.adj_hrs +vga_clock_tb.uut.gpio_control_in[8].pad_gpio_in +vga_clock_tb.uut.gpio_control_in[8].pad_gpio_in +vga_clock_tb.uut.gpio_control_in[8].pad_gpio_inenb +vga_clock_tb.uut.gpio_control_in[8].pad_gpio_outenb +vga_clock_tb.uut.mprj.mprj.proj_2.adj_hrs vga_clock_tb.uut.mprj.mprj.proj_2.px_clk @24 vga_clock_tb.uut.mprj.mprj.proj_2.y_px[9:0] diff --git a/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock_tb.v b/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock_tb.v index 5b13c0dc..b2de19ce 100644 --- a/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock_tb.v +++ b/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock_tb.v @@ -16,9 +16,28 @@ module vga_clock_tb; wire [5:0] rrggbb; wire hsync, vsync; - assign hsync = mprj_io[5]; - assign vsync = mprj_io[6]; - assign rrggbb = mprj_io[12:7]; + assign hsync = uut.gpio_control_in[11].pad_gpio_out; + assign vsync = uut.gpio_control_in[12].pad_gpio_out; + assign rrggbb = { + uut.gpio_control_in[13].pad_gpio_out, + uut.gpio_control_in[14].pad_gpio_out, + uut.gpio_control_in[15].pad_gpio_out, + uut.gpio_control_in[16].pad_gpio_out, + uut.gpio_control_in[17].pad_gpio_out, + uut.gpio_control_in[18].pad_gpio_out + }; + + reg adj_hrs = 0; + reg adj_min = 0; + reg adj_sec = 0; + assign mprj_io[8] = adj_hrs; + assign mprj_io[9] = adj_min; + assign mprj_io[10] = adj_sec; +/* this doesn't work + assign uut.gpio_control_in[ 8].pad_gpio_in = adj_hrs; + assign uut.gpio_control_in[ 9].pad_gpio_in = adj_min; + assign uut.gpio_control_in[10].pad_gpio_in = adj_sec; + */ // External clock is used by default. Make this artificially fast for the // simulation. Normally this would be a slow clock and the digital PLL @@ -45,6 +64,31 @@ module vga_clock_tb; $finish; end + initial begin + // wait for reset, we have 2 before the project is ready + wait(uut.mprj.mprj.proj_2.reset == 1); + wait(uut.mprj.mprj.proj_2.reset == 0); + wait(uut.mprj.mprj.proj_2.reset == 1); + wait(uut.mprj.mprj.proj_2.reset == 0); + + // press a button + adj_hrs = 1; + wait(uut.mprj.mprj.proj_2.hrs_u == 1); + adj_hrs = 0; + $display ("adjusted hours ok"); + + adj_min = 1; + wait(uut.mprj.mprj.proj_2.min_u == 1); + adj_min = 0; + $display ("adjusted min ok"); + + adj_sec = 1; + wait(uut.mprj.mprj.proj_2.sec_u == 1); + adj_sec = 0; + $display ("adjusted sec ok"); + + end + initial begin RSTB <= 1'b0; #2000; @@ -98,7 +142,7 @@ module vga_clock_tb; .vssd2 (VSS), .clock (clock), .gpio (gpio), - .mprj_io (mprj_io), + .mprj_io (mprj_io), .flash_csb(flash_csb), .flash_clk(flash_clk), .flash_io0(flash_io0), From ede0c3a6003ed7bdc359dd5e01110d6200613d8e Mon Sep 17 00:00:00 2001 From: Matt Venn Date: Thu, 26 Nov 2020 15:15:33 +0100 Subject: [PATCH 20/32] sync --- verilog/rtl/multi_project_harness | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/verilog/rtl/multi_project_harness b/verilog/rtl/multi_project_harness index de57c12e..7cbb5a63 160000 --- a/verilog/rtl/multi_project_harness +++ b/verilog/rtl/multi_project_harness @@ -1 +1 @@ -Subproject commit de57c12e38e8cce4afcac8ce303d24e1ce342b97 +Subproject commit 7cbb5a632675e8c28a86d177f8e2075fdf64da80 From e847ae6153b70c009ebb16dd5a39faf30f09649e Mon Sep 17 00:00:00 2001 From: Matt Venn Date: Thu, 26 Nov 2020 16:38:05 +0100 Subject: [PATCH 21/32] remove submodule --- .gitmodules | 3 --- verilog/rtl/multi_project_harness | 1 - 2 files changed, 4 deletions(-) delete mode 160000 verilog/rtl/multi_project_harness diff --git a/.gitmodules b/.gitmodules index 5e8cd70c..e69de29b 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +0,0 @@ -[submodule "verilog/rtl/multi_project_harness"] - path = verilog/rtl/multi_project_harness - url = https://github.com/mattvenn/multi-project-harness.git diff --git a/verilog/rtl/multi_project_harness b/verilog/rtl/multi_project_harness deleted file mode 160000 index 7cbb5a63..00000000 --- a/verilog/rtl/multi_project_harness +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 7cbb5a632675e8c28a86d177f8e2075fdf64da80 From 9109e20f597047cc832724d16c572643d81bf8b5 Mon Sep 17 00:00:00 2001 From: Matt Venn Date: Thu, 26 Nov 2020 16:41:36 +0100 Subject: [PATCH 22/32] re-add mp harness from new url --- .gitmodules | 3 +++ verilog/rtl/multi_project_harness | 1 + 2 files changed, 4 insertions(+) create mode 160000 verilog/rtl/multi_project_harness diff --git a/.gitmodules b/.gitmodules index e69de29b..af8c0ad8 100644 --- a/.gitmodules +++ b/.gitmodules @@ -0,0 +1,3 @@ +[submodule "verilog/rtl/multi_project_harness"] + path = verilog/rtl/multi_project_harness + url = https://github.com/mattvenn/mpw-multi-project-harness diff --git a/verilog/rtl/multi_project_harness b/verilog/rtl/multi_project_harness new file mode 160000 index 00000000..7cbb5a63 --- /dev/null +++ b/verilog/rtl/multi_project_harness @@ -0,0 +1 @@ +Subproject commit 7cbb5a632675e8c28a86d177f8e2075fdf64da80 From f11705e8576550c3d1b90fda3e6749142f3fa35b Mon Sep 17 00:00:00 2001 From: Matt Venn Date: Thu, 26 Nov 2020 16:50:53 +0100 Subject: [PATCH 23/32] updates for multi_project_harness --- openlane/user_project_wrapper/config.tcl | 6 +++--- openlane/user_project_wrapper/interactive.tcl | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl index 50e0bd17..30e400a0 100644 --- a/openlane/user_project_wrapper/config.tcl +++ b/openlane/user_project_wrapper/config.tcl @@ -21,10 +21,10 @@ set ::env(VERILOG_FILES) "\ set ::env(VERILOG_FILES_BLACKBOX) "\ $script_dir/../../verilog/rtl/defines.v \ - $script_dir/../../verilog/rtl/user_proj_example.v" + $script_dir/../../verilog/rtl/multi_project_harness/multi_project_harness.v" set ::env(EXTRA_LEFS) "\ - $script_dir/../../lef/user_proj_example.lef" + $script_dir/multi_project_harness.lef" set ::env(EXTRA_GDS_FILES) "\ - $script_dir/../../gds/user_proj_example.gds" + $script_dir/multi_project_harness.gds" diff --git a/openlane/user_project_wrapper/interactive.tcl b/openlane/user_project_wrapper/interactive.tcl index dd5c0d12..c22a9a7d 100644 --- a/openlane/user_project_wrapper/interactive.tcl +++ b/openlane/user_project_wrapper/interactive.tcl @@ -10,7 +10,7 @@ init_floorplan place_io_ol -add_macro_placement mprj 1150 1700 N +add_macro_placement mprj 500 500 N manual_macro_placement f From 8eadf5d9f42387fafd383ae58b7eb08ee4ec8da7 Mon Sep 17 00:00:00 2001 From: Matt Venn Date: Thu, 26 Nov 2020 17:06:30 +0100 Subject: [PATCH 24/32] fixed testbenches with uninit wires --- .../seven-segment-counter/seven_segment.gtkw | 21 ++++++------------- .../seven-segment-counter/seven_segment_tb.v | 4 ++-- .../vga-clock/vga_clock_tb.v | 15 +++++-------- .../user_proj_example/ws2812/ws2812_tb.v | 4 ++-- 4 files changed, 15 insertions(+), 29 deletions(-) diff --git a/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment.gtkw b/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment.gtkw index 997863d1..d081a58a 100644 --- a/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment.gtkw +++ b/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment.gtkw @@ -1,15 +1,15 @@ [*] [*] GTKWave Analyzer v3.3.108 (w)1999-2020 BSI -[*] Thu Nov 26 10:51:35 2020 +[*] Thu Nov 26 15:54:45 2020 [*] [dumpfile] "/home/matt/work/asic-workshop/caravel/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment.vcd" -[dumpfile_mtime] "Thu Nov 26 10:46:55 2020" -[dumpfile_size] 101432617 +[dumpfile_mtime] "Thu Nov 26 15:53:35 2020" +[dumpfile_size] 101461023 [savefile] "/home/matt/work/asic-workshop/caravel/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment.gtkw" -[timestart] 141660000 -[size] 2371 1293 +[timestart] 0 +[size] 2488 1529 [pos] -1 -1 -*-24.000000 192362500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +*-26.000000 192362500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] seven_segment_tb. [treeopen] seven_segment_tb.uut. [treeopen] seven_segment_tb.uut.gpio_control_bidir[0]. @@ -298,15 +298,6 @@ seven_segment_tb.uut.mprj.mprj.proj_0.led_out[6:0] -group_end @1000200 -seven seg -@29 -seven_segment_tb.uut.gpio_control_in[8].pad_gpio_out -@28 -seven_segment_tb.uut.gpio_control_in[7].pad_gpio_out -seven_segment_tb.uut.gpio_control_in[6].pad_gpio_out -seven_segment_tb.uut.gpio_control_in[5].pad_gpio_out -seven_segment_tb.uut.gpio_control_in[4].pad_gpio_out -seven_segment_tb.uut.gpio_control_in[3].pad_gpio_out -seven_segment_tb.uut.gpio_control_in[2].pad_gpio_out @800022 seven_segment_tb.segments[6:0] @28 diff --git a/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment_tb.v b/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment_tb.v index 70d182b4..4bef7724 100644 --- a/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment_tb.v +++ b/verilog/dv/caravel/user_proj_example/seven-segment-counter/seven_segment_tb.v @@ -108,8 +108,8 @@ module seven_segment_tb; assign VDD3V3 = power1; assign VDD1V8 = power2; - assign USER_VDD3V3 = power3; - assign USER_VDD1V8 = power4; + wire USER_VDD3V3 = power3; + wire USER_VDD1V8 = power4; assign VSS = 1'b0; caravel uut ( diff --git a/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock_tb.v b/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock_tb.v index b2de19ce..6bb03c4a 100644 --- a/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock_tb.v +++ b/verilog/dv/caravel/user_proj_example/vga-clock/vga_clock_tb.v @@ -71,20 +71,15 @@ module vga_clock_tb; wait(uut.mprj.mprj.proj_2.reset == 1); wait(uut.mprj.mprj.proj_2.reset == 0); - // press a button + // press all the buttons! button clk_en deboucing is slow so don't want to wait around adj_hrs = 1; + adj_min = 1; + adj_sec = 1; wait(uut.mprj.mprj.proj_2.hrs_u == 1); - adj_hrs = 0; $display ("adjusted hours ok"); - - adj_min = 1; wait(uut.mprj.mprj.proj_2.min_u == 1); - adj_min = 0; $display ("adjusted min ok"); - - adj_sec = 1; wait(uut.mprj.mprj.proj_2.sec_u == 1); - adj_sec = 0; $display ("adjusted sec ok"); end @@ -121,8 +116,8 @@ module vga_clock_tb; assign VDD3V3 = power1; assign VDD1V8 = power2; - assign USER_VDD3V3 = power3; - assign USER_VDD1V8 = power4; + wire USER_VDD3V3 = power3; + wire USER_VDD1V8 = power4; assign VSS = 1'b0; caravel uut ( diff --git a/verilog/dv/caravel/user_proj_example/ws2812/ws2812_tb.v b/verilog/dv/caravel/user_proj_example/ws2812/ws2812_tb.v index 94f9c902..2f12b51c 100644 --- a/verilog/dv/caravel/user_proj_example/ws2812/ws2812_tb.v +++ b/verilog/dv/caravel/user_proj_example/ws2812/ws2812_tb.v @@ -72,8 +72,8 @@ module ws2812_tb; assign VDD3V3 = power1; assign VDD1V8 = power2; - assign USER_VDD3V3 = power3; - assign USER_VDD1V8 = power4; + wire USER_VDD3V3 = power3; + wire USER_VDD1V8 = power4; assign VSS = 1'b0; caravel uut ( From 5ba6574fb98b70789584a3de93c77a9c9b2d3cd8 Mon Sep 17 00:00:00 2001 From: Matt Venn Date: Thu, 26 Nov 2020 17:31:32 +0100 Subject: [PATCH 25/32] update readme and yaml --- README.md | 53 ++++++++++++++++++++++++++++++++--------------------- info.yaml | 17 ++++++++--------- 2 files changed, 40 insertions(+), 30 deletions(-) diff --git a/README.md b/README.md index 447fe6a9..9cc40ef3 100644 --- a/README.md +++ b/README.md @@ -1,28 +1,39 @@ -# CIIC Harness +# Multi Project Harness -A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below. +* This is a proposal for handling multiple projects in the user project area of the [Caravel harness](https://github.com/efabless/caravel) +* This is a fork of caravel with https://github.com/mattvenn/mpw-multi-project-harness added to /verilog/rtl/ +* user_project_wrapper is then adjusted to instantiate https://github.com/mattvenn/mpw-multi-project-harness/blob/main/multi_project_harness.v -

- -

+# Sub projects -## Managment SoC -The managment SoC runs firmware that can be used to: -- Configure Mega Project I/O pads -- Observe and control Mega Project signals (through on-chip logic analyzer probes) -- Control the Mega Project power supply +See https://github.com/mattvenn/mpw-multi-project-harness/blob/main/.gitmodules +for the list of currently included projects. -The memory map of the management SoC can be found [here](verilog/rtl/README) +# Preparation -## Mega Project Area -This is the user space. It has limited silicon area (TBD, about 3.1mm x 3.8mm) as well as a fixed number of I/O pads (37) and power pads (10). See [the Caravel premliminary datasheet](doc/caravel_datasheet.pdf) for details. -The repository contains a [sample mega project](/verilog/rtl/user_proj_example.v) that contains a binary 32-bit up counter.
+See https://github.com/mattvenn/mpw-multi-project-harness for details on adding new projects. -

- -

+# Simulation / Verification. -The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided: -1. Configure the Mega Project I/O pads as o/p. Observe the counter value in the testbench: [IO_Ports Test](verilog/dv/caravel/user_proj_example/io_ports). -2. Configure the Mega Project I/O pads as o/p. Use the Chip LA to load the counter and observe the o/p till it reaches 500: [LA_Test1](verilog/dv/caravel/user_proj_example/la_test1). -3. Configure the Mega Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles: [LA_Test2](verilog/dv/caravel/user_proj_example/la_test2). +For formal and cocotb simulation of each module see https://github.com/mattvenn/mpw-multi-project-harness + +For caravel system simulation see the tests under verilog/dv/caravel/user_proj_example/ + +# GDS + +See https://github.com/mattvenn/mpw-multi-project-harness/blob/main/docs/hardening.md for details on hardening each module into the main macro. +This macro's GDS/LEF is then added to openlane/user_project_wrapper + +For configuration sees: + +* openlane/user_project_wrapper/config.tcl +* openlane/user_project_wrapper/interactive.tcl + +To generate the final GDS, run this command: + + make user_project_wrapper OPENLANE_IMAGE_NAME=openlane:rc5 + +# Todo + +* when the toolchain is fully working, generate the GDS and add it to the repo +* info.yaml : update user_level_netlist diff --git a/info.yaml b/info.yaml index ffd05202..8ba42fd4 100644 --- a/info.yaml +++ b/info.yaml @@ -1,18 +1,17 @@ --- project: - description: "A template SoC for Google sponsored Open MPW shuttles for SKY130." + description: "Multi project including designs from Matt Venn, Michael Betz & Richard Miller" foundry: "SkyWater" - git_url: "https://github.com/efabless/caravel.git" - organization: "Efabless" - organization_url: "http://efabless.com" - owner: "Tim Edwards" + git_url: "https://github.com/mattvenn/multi-project-harness.git" + organization: "" + organization_url: "" + owner: "Matt Venn" process: "SKY130" - project_name: "Caravel" + project_name: "multi-project-harness" tags: - "Open MPW" - - "Test Harness" - category: "Test Harness" + category: "multi project" top_level_netlist: "verilog/rtl/caravel.v" - user_level_netlist: "verilog/gl/user_project_wrapper.v" + user_level_netlist: "verilog/rtl/multi_project_harness/multi_project_harness.v" version: "1.00" cover_image: "doc/ciic_harness.png" From dca32d1b4c583b8a19cf1bc3f922158f8a9b6d96 Mon Sep 17 00:00:00 2001 From: Matt Venn Date: Thu, 26 Nov 2020 17:36:43 +0100 Subject: [PATCH 26/32] image --- README.md | 2 ++ doc/multi-project-harness.png | Bin 0 -> 30907 bytes 2 files changed, 2 insertions(+) create mode 100644 doc/multi-project-harness.png diff --git a/README.md b/README.md index 9cc40ef3..de534662 100644 --- a/README.md +++ b/README.md @@ -4,6 +4,8 @@ * This is a fork of caravel with https://github.com/mattvenn/mpw-multi-project-harness added to /verilog/rtl/ * user_project_wrapper is then adjusted to instantiate https://github.com/mattvenn/mpw-multi-project-harness/blob/main/multi_project_harness.v +![multi project harness](doc/multi-project-harness.png) + # Sub projects See https://github.com/mattvenn/mpw-multi-project-harness/blob/main/.gitmodules diff --git a/doc/multi-project-harness.png b/doc/multi-project-harness.png new file mode 100644 index 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z6d9z9tiOSLAE{&V5*=t!kn|;Sbz^ynzZ`7fWufDQBdUfSafk zw(jFaxpL6MMH;iPYzA+{xgKnjI710 z3`i*BLb-;)X%$Isx}aG7Hju=u5qZX6hagGCf5Hp32T}rO{Bpa;$-_#Y literal 0 HcmV?d00001 From eb7b26de4f6beb5c721c409c29597170013689ff Mon Sep 17 00:00:00 2001 From: Matt Venn Date: Thu, 26 Nov 2020 18:01:49 +0100 Subject: [PATCH 27/32] add some todos --- README.md | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index de534662..903039b0 100644 --- a/README.md +++ b/README.md @@ -37,5 +37,9 @@ To generate the final GDS, run this command: # Todo -* when the toolchain is fully working, generate the GDS and add it to the repo -* info.yaml : update user_level_netlist +* when the toolchain is working, generate the GDS and add it to the repo +* info.yaml : update user_level_netlist field +* add some logo art +* test input pins in the system simulation +* how clean does the DRC result need to be? +* adapt ws2812 for default 10mhz clock rate or be able to update the timing reg From 90f793bea9620c3cf6907c5e25de4602a77b90c4 Mon Sep 17 00:00:00 2001 From: Guillem Date: Thu, 26 Nov 2020 21:45:36 +0100 Subject: [PATCH 28/32] add project 6 tb --- .../user_proj_example/ASIC_watch/ASIC_watch.c | 60 +++++++++ .../ASIC_watch/ASIC_watch_tb.v | 115 ++++++++++++++++++ .../user_proj_example/ASIC_watch/Makefile | 42 +++++++ 3 files changed, 217 insertions(+) create mode 100644 verilog/dv/caravel/user_proj_example/ASIC_watch/ASIC_watch.c create mode 100644 verilog/dv/caravel/user_proj_example/ASIC_watch/ASIC_watch_tb.v create mode 100644 verilog/dv/caravel/user_proj_example/ASIC_watch/Makefile diff --git a/verilog/dv/caravel/user_proj_example/ASIC_watch/ASIC_watch.c b/verilog/dv/caravel/user_proj_example/ASIC_watch/ASIC_watch.c new file mode 100644 index 00000000..ab714d4f --- /dev/null +++ b/verilog/dv/caravel/user_proj_example/ASIC_watch/ASIC_watch.c @@ -0,0 +1,60 @@ +#include "../../defs.h" + +#define PROJECT 6 +#define NUMNODES 6 +/* + IO Test: + - Configures MPRJ pins +*/ + +void main() +{ + /* + IO Control Registers + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | + Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | + Output: 0000_0110_0000_1111 (0x1809) = GPIO_MODE_MGNT_STD_OUTPUT + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | + + + Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | + */ + + /* + Inputs + system clock + system reset_n + + Outputs + 2 - 8 segment_hxxx + 9 - 15 segment_xhxx + 16 - 22 segment_xxhx + 23 - 29 segment_xxxh + */ + volatile uint32_t *io = ®_mprj_io_0; + for (int i = 0; i < NUMNODES; i++) { + for (int j = 0; j <= 1; j += 6) + io[i + j] = GPIO_MODE_USER_STD_INPUT_NOPULL; + for (int j = 1; j <= 29; j += 6) + io[i + j] = GPIO_MODE_USER_STD_OUTPUT; + } + + /* Apply configuration */ + reg_mprj_xfer = 1; + while (reg_mprj_xfer == 1); + + // change to project + reg_mprj_slave = PROJECT; + + // use logic analyser bit 0 as reset + reg_la0_ena = 0x00000000; // bits 31:0 outputs + reg_la0_data = 0x00000001; // reset high is on bit 0 + reg_la0_data = 0x00000000; // low + +} diff --git a/verilog/dv/caravel/user_proj_example/ASIC_watch/ASIC_watch_tb.v b/verilog/dv/caravel/user_proj_example/ASIC_watch/ASIC_watch_tb.v new file mode 100644 index 00000000..c3f9d4b2 --- /dev/null +++ b/verilog/dv/caravel/user_proj_example/ASIC_watch/ASIC_watch_tb.v @@ -0,0 +1,115 @@ +`default_nettype none + +`timescale 1 ns / 1 ps + +`include "caravel.v" +`include "spiflash.v" + +module ASIC_watch_tb; + reg clock; + reg RSTB; + reg power1, power2; + reg power3, power4; + + wire gpio; + wire [37:0] mprj_io; + + // External clock is used by default. Make this artificially fast for the + // simulation. Normally this would be a slow clock and the digital PLL + // would be the fast clock. + + always #12.5 clock <= (clock === 1'b0); + + initial begin + clock = 0; + end + + + initial begin + $dumpfile("ASIC_watch.vcd"); + $dumpvars(0, ASIC_watch_tb); + + // Repeat cycles of 1000 clock edges as needed to complete testbench + repeat (15) begin + repeat (1000) @(posedge clock); + // $display("+1000 cycles"); + end + $display("%c[1;31m",27); + $display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed"); + $display("%c[0m",27); + $finish; + end + + initial begin + RSTB <= 1'b0; + #2000; + RSTB <= 1'b1; // Release reset + end + + initial begin // Power-up sequence + power1 <= 1'b0; + power2 <= 1'b0; + power3 <= 1'b0; + power4 <= 1'b0; + #200; + power1 <= 1'b1; + #200; + power2 <= 1'b1; + #200; + power3 <= 1'b1; + #200; + power4 <= 1'b1; + end + + wire flash_csb; + wire flash_clk; + wire flash_io0; + wire flash_io1; + + wire VDD1V8; + wire VDD3V3; + wire VSS; + + assign VDD3V3 = power1; + assign VDD1V8 = power2; + wire USER_VDD3V3 = power3; + wire USER_VDD1V8 = power4; + assign VSS = 1'b0; + + caravel uut ( + .vddio (VDD3V3), + .vssio (VSS), + .vdda (VDD3V3), + .vssa (VSS), + .vccd (VDD1V8), + .vssd (VSS), + .vdda1 (USER_VDD3V3), + .vdda2 (USER_VDD3V3), + .vssa1 (VSS), + .vssa2 (VSS), + .vccd1 (USER_VDD1V8), + .vccd2 (USER_VDD1V8), + .vssd1 (VSS), + .vssd2 (VSS), + .clock (clock), + .gpio (gpio), + .mprj_io (mprj_io), + .flash_csb(flash_csb), + .flash_clk(flash_clk), + .flash_io0(flash_io0), + .flash_io1(flash_io1), + .resetb (RSTB) + ); + + spiflash #( + .FILENAME("ASIC_watch.hex") + ) spiflash ( + .csb(flash_csb), + .clk(flash_clk), + .io0(flash_io0), + .io1(flash_io1), + .io2(), // not used + .io3() // not used + ); + +endmodule diff --git a/verilog/dv/caravel/user_proj_example/ASIC_watch/Makefile b/verilog/dv/caravel/user_proj_example/ASIC_watch/Makefile new file mode 100644 index 00000000..c084f70e --- /dev/null +++ b/verilog/dv/caravel/user_proj_example/ASIC_watch/Makefile @@ -0,0 +1,42 @@ +FIRMWARE_PATH = ../.. +RTL_PATH = ../../../../rtl +IP_PATH = ../../../../ip +#MP_PATH = ../../../../rtl/multi_project_harness +BEHAVIOURAL_MODELS = ../../ + +TOOLCHAIN_PREFIX?=/home/bscuser/programs/RISCV-GNU/bin/riscv64-unknown-elf- +PDK_PATH?=/home/bscuser/hacking/skywater-pdk + +.SUFFIXES: + +PATTERN = ASIC_watch + +all: ${PATTERN:=.vcd} + +hex: ${PATTERN:=.hex} + +%.vvp: %_tb.v %.hex + iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \ + -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \ + $< -o $@ + +%.vcd: %.vvp + vvp $< + +%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s + $(TOOLCHAIN_PREFIX)gcc -mabi=ilp32 -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< + +%.hex: %.elf + $(TOOLCHAIN_PREFIX)objcopy -O verilog $< $@ + # to fix flash base address + sed -i 's/@10000000/@00000000/g' $@ + +%.bin: %.elf + $(TOOLCHAIN_PREFIX)objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ + +# ---- Clean ---- + +clean: + rm -f *.elf *.hex *.bin *.vvp *.vcd *.log + +.PHONY: clean hex all From baa1aa84ec5fb686cb5b2305bc2c450561b03a15 Mon Sep 17 00:00:00 2001 From: Bynaryman Date: Fri, 27 Nov 2020 14:15:46 +0100 Subject: [PATCH 29/32] adding tb caravel by imitation --- .../user_proj_example/ASIC_watch/ASIC_watch.c | 35 ++++++++++------ .../ASIC_watch/ASIC_watch_tb.v | 40 ++++++++++++++++++- 2 files changed, 60 insertions(+), 15 deletions(-) diff --git a/verilog/dv/caravel/user_proj_example/ASIC_watch/ASIC_watch.c b/verilog/dv/caravel/user_proj_example/ASIC_watch/ASIC_watch.c index ab714d4f..7148bab2 100644 --- a/verilog/dv/caravel/user_proj_example/ASIC_watch/ASIC_watch.c +++ b/verilog/dv/caravel/user_proj_example/ASIC_watch/ASIC_watch.c @@ -1,7 +1,10 @@ #include "../../defs.h" -#define PROJECT 6 -#define NUMNODES 6 +#define PROJECT 5 +#define NB_OUTPUTS 28 + +#define reg_mprj_oeb0 (*(volatile uint32_t*)0x30000004) +#define reg_mprj_oeb1 (*(volatile uint32_t*)0x30000008) /* IO Test: - Configures MPRJ pins @@ -32,18 +35,21 @@ void main() system reset_n Outputs - 2 - 8 segment_hxxx - 9 - 15 segment_xhxx - 16 - 22 segment_xxhx - 23 - 29 segment_xxxh + 8 - 14 segment_hxxx + 15 - 21 segment_xhxx + 22 - 28 segment_xxhx + 29 - 35 segment_xxxh */ - volatile uint32_t *io = ®_mprj_io_0; - for (int i = 0; i < NUMNODES; i++) { - for (int j = 0; j <= 1; j += 6) - io[i + j] = GPIO_MODE_USER_STD_INPUT_NOPULL; - for (int j = 1; j <= 29; j += 6) - io[i + j] = GPIO_MODE_USER_STD_OUTPUT; - } + volatile uint32_t *io = ®_mprj_io_0; + for (int i = 8 ; i < 8+NB_OUTPUTS ; i++) { + io[i] = GPIO_MODE_USER_STD_OUTPUT; + } + // for (int i = 0; i < NUMNODES; i++) { + // for (int j = 0; j <= 1; j += 6) + // io[i + j] = GPIO_MODE_USER_STD_INPUT_NOPULL; + // for (int j = 1; j <= 29; j += 6) + // io[i + j] = GPIO_MODE_USER_STD_OUTPUT; + // } /* Apply configuration */ reg_mprj_xfer = 1; @@ -52,6 +58,9 @@ void main() // change to project reg_mprj_slave = PROJECT; + // setup oeb, low for output, high for input + reg_mprj_oeb0 = (1 << 8) + (1 << 9) + (1 << 10); + // use logic analyser bit 0 as reset reg_la0_ena = 0x00000000; // bits 31:0 outputs reg_la0_data = 0x00000001; // reset high is on bit 0 diff --git a/verilog/dv/caravel/user_proj_example/ASIC_watch/ASIC_watch_tb.v b/verilog/dv/caravel/user_proj_example/ASIC_watch/ASIC_watch_tb.v index c3f9d4b2..3e3daddd 100644 --- a/verilog/dv/caravel/user_proj_example/ASIC_watch/ASIC_watch_tb.v +++ b/verilog/dv/caravel/user_proj_example/ASIC_watch/ASIC_watch_tb.v @@ -13,6 +13,42 @@ module ASIC_watch_tb; wire gpio; wire [37:0] mprj_io; + wire [6:0] segment_hxxx; + wire [6:0] segment_xhxx; + wire [6:0] segment_xxhx; + wire [6:0] segment_xxxh; + + assign segment_hxxx[0] = uut.gpio_control_in[8].pad_gpio_out; + assign segment_hxxx[1] = uut.gpio_control_in[9].pad_gpio_out; + assign segment_hxxx[2] = uut.gpio_control_in[10].pad_gpio_out; + assign segment_hxxx[3] = uut.gpio_control_in[11].pad_gpio_out; + assign segment_hxxx[4] = uut.gpio_control_in[12].pad_gpio_out; + assign segment_hxxx[5] = uut.gpio_control_in[13].pad_gpio_out; + assign segment_hxxx[6] = uut.gpio_control_in[14].pad_gpio_out; + + assign segment_xhxx[0] = uut.gpio_control_in[15].pad_gpio_out; + assign segment_xhxx[1] = uut.gpio_control_in[16].pad_gpio_out; + assign segment_xhxx[2] = uut.gpio_control_in[17].pad_gpio_out; + assign segment_xhxx[3] = uut.gpio_control_in[18].pad_gpio_out; + assign segment_xhxx[4] = uut.gpio_control_in[19].pad_gpio_out; + assign segment_xhxx[5] = uut.gpio_control_in[20].pad_gpio_out; + assign segment_xhxx[6] = uut.gpio_control_in[21].pad_gpio_out; + + assign segment_xxhx[0] = uut.gpio_control_in[22].pad_gpio_out; + assign segment_xxhx[1] = uut.gpio_control_in[23].pad_gpio_out; + assign segment_xxhx[2] = uut.gpio_control_in[24].pad_gpio_out; + assign segment_xxhx[3] = uut.gpio_control_in[25].pad_gpio_out; + assign segment_xxhx[4] = uut.gpio_control_in[26].pad_gpio_out; + assign segment_xxhx[5] = uut.gpio_control_in[27].pad_gpio_out; + assign segment_xxhx[6] = uut.gpio_control_in[28].pad_gpio_out; + + assign segment_xxxh[0] = uut.gpio_control_in[29].pad_gpio_out; + assign segment_xxxh[1] = uut.gpio_control_in[30].pad_gpio_out; + assign segment_xxxh[2] = uut.gpio_control_in[31].pad_gpio_out; + assign segment_xxxh[3] = uut.gpio_control_in[32].pad_gpio_out; + assign segment_xxxh[4] = uut.gpio_control_in[33].pad_gpio_out; + assign segment_xxxh[5] = uut.gpio_control_in[34].pad_gpio_out; + assign segment_xxxh[6] = uut.gpio_control_in[35].pad_gpio_out; // External clock is used by default. Make this artificially fast for the // simulation. Normally this would be a slow clock and the digital PLL @@ -69,7 +105,7 @@ module ASIC_watch_tb; wire VDD1V8; wire VDD3V3; wire VSS; - + assign VDD3V3 = power1; assign VDD1V8 = power2; wire USER_VDD3V3 = power3; @@ -93,7 +129,7 @@ module ASIC_watch_tb; .vssd2 (VSS), .clock (clock), .gpio (gpio), - .mprj_io (mprj_io), + .mprj_io (mprj_io), .flash_csb(flash_csb), .flash_clk(flash_clk), .flash_io0(flash_io0), From 63dea50845e5ee146e8e0f40062c373080d7f9d3 Mon Sep 17 00:00:00 2001 From: Bynaryman Date: Fri, 27 Nov 2020 14:48:36 +0100 Subject: [PATCH 30/32] remove setting high oeb since there is no input in the design --- verilog/dv/caravel/user_proj_example/ASIC_watch/ASIC_watch.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/verilog/dv/caravel/user_proj_example/ASIC_watch/ASIC_watch.c b/verilog/dv/caravel/user_proj_example/ASIC_watch/ASIC_watch.c index 7148bab2..d080bafc 100644 --- a/verilog/dv/caravel/user_proj_example/ASIC_watch/ASIC_watch.c +++ b/verilog/dv/caravel/user_proj_example/ASIC_watch/ASIC_watch.c @@ -3,8 +3,6 @@ #define PROJECT 5 #define NB_OUTPUTS 28 -#define reg_mprj_oeb0 (*(volatile uint32_t*)0x30000004) -#define reg_mprj_oeb1 (*(volatile uint32_t*)0x30000008) /* IO Test: - Configures MPRJ pins @@ -58,9 +56,6 @@ void main() // change to project reg_mprj_slave = PROJECT; - // setup oeb, low for output, high for input - reg_mprj_oeb0 = (1 << 8) + (1 << 9) + (1 << 10); - // use logic analyser bit 0 as reset reg_la0_ena = 0x00000000; // bits 31:0 outputs reg_la0_data = 0x00000001; // reset high is on bit 0 From da36169ef8bd5317828d394b5079c4f5ad48cc0c Mon Sep 17 00:00:00 2001 From: Bynaryman Date: Fri, 27 Nov 2020 15:14:30 +0100 Subject: [PATCH 31/32] add an input for crystal clock --- .../dv/caravel/user_proj_example/ASIC_watch/ASIC_watch.c | 8 +++++++- .../caravel/user_proj_example/ASIC_watch/ASIC_watch_tb.v | 8 ++++++++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/verilog/dv/caravel/user_proj_example/ASIC_watch/ASIC_watch.c b/verilog/dv/caravel/user_proj_example/ASIC_watch/ASIC_watch.c index d080bafc..3d58fbee 100644 --- a/verilog/dv/caravel/user_proj_example/ASIC_watch/ASIC_watch.c +++ b/verilog/dv/caravel/user_proj_example/ASIC_watch/ASIC_watch.c @@ -3,6 +3,8 @@ #define PROJECT 5 #define NB_OUTPUTS 28 +#define reg_mprj_oeb0 (*(volatile uint32_t*)0x30000004) + /* IO Test: - Configures MPRJ pins @@ -29,7 +31,7 @@ void main() /* Inputs - system clock + 36 - 2^15Hz crystal clock system reset_n Outputs @@ -42,6 +44,8 @@ void main() for (int i = 8 ; i < 8+NB_OUTPUTS ; i++) { io[i] = GPIO_MODE_USER_STD_OUTPUT; } + io[36] = GPIO_MODE_USER_STD_INPUT_NOPULL; + // for (int i = 0; i < NUMNODES; i++) { // for (int j = 0; j <= 1; j += 6) // io[i + j] = GPIO_MODE_USER_STD_INPUT_NOPULL; @@ -56,6 +60,8 @@ void main() // change to project reg_mprj_slave = PROJECT; + // reg_mprj_oeb0 = (1 << 36); + // use logic analyser bit 0 as reset reg_la0_ena = 0x00000000; // bits 31:0 outputs reg_la0_data = 0x00000001; // reset high is on bit 0 diff --git a/verilog/dv/caravel/user_proj_example/ASIC_watch/ASIC_watch_tb.v b/verilog/dv/caravel/user_proj_example/ASIC_watch/ASIC_watch_tb.v index 3e3daddd..ea36425c 100644 --- a/verilog/dv/caravel/user_proj_example/ASIC_watch/ASIC_watch_tb.v +++ b/verilog/dv/caravel/user_proj_example/ASIC_watch/ASIC_watch_tb.v @@ -13,6 +13,10 @@ module ASIC_watch_tb; wire gpio; wire [37:0] mprj_io; + // inputs + reg clk_32768; + + // outputs wire [6:0] segment_hxxx; wire [6:0] segment_xhxx; wire [6:0] segment_xxhx; @@ -50,14 +54,18 @@ module ASIC_watch_tb; assign segment_xxxh[5] = uut.gpio_control_in[34].pad_gpio_out; assign segment_xxxh[6] = uut.gpio_control_in[35].pad_gpio_out; + assign mprj_io[36] = clk_32768; + // External clock is used by default. Make this artificially fast for the // simulation. Normally this would be a slow clock and the digital PLL // would be the fast clock. always #12.5 clock <= (clock === 1'b0); + always #12.5 clk_32768 <= (clk_32768 === 1'b0); initial begin clock = 0; + clk_32768 = 0; end From 3810e00bfe509a3dd98b46b956ade9034b271640 Mon Sep 17 00:00:00 2001 From: Guillem Date: Sun, 29 Nov 2020 17:33:07 +0100 Subject: [PATCH 32/32] update harness --- .../user_proj_example/ASIC_watch/ASIC_watch.c | 24 ++++++++----------- .../ASIC_watch/ASIC_watch_tb.v | 7 ++++-- .../user_proj_example/ASIC_watch/Makefile | 2 +- 3 files changed, 16 insertions(+), 17 deletions(-) diff --git a/verilog/dv/caravel/user_proj_example/ASIC_watch/ASIC_watch.c b/verilog/dv/caravel/user_proj_example/ASIC_watch/ASIC_watch.c index 3d58fbee..323d8607 100644 --- a/verilog/dv/caravel/user_proj_example/ASIC_watch/ASIC_watch.c +++ b/verilog/dv/caravel/user_proj_example/ASIC_watch/ASIC_watch.c @@ -4,7 +4,8 @@ #define NB_OUTPUTS 28 #define reg_mprj_oeb0 (*(volatile uint32_t*)0x30000004) - +#define reg_mprj_oeb1 (*(volatile uint32_t*)0x30000008) +#define reg_mprj_ws2812 (*(volatile uint32_t*)0x30000500) /* IO Test: - Configures MPRJ pins @@ -31,28 +32,23 @@ void main() /* Inputs - 36 - 2^15Hz crystal clock - system reset_n + 36 - Safe mode + 37 - 2^15Hz crystal clock Outputs 8 - 14 segment_hxxx 15 - 21 segment_xhxx - 22 - 28 segment_xxhx - 29 - 35 segment_xxxh + 22 - 28 segment_xxmx + 29 - 35 segment_xxxm */ volatile uint32_t *io = ®_mprj_io_0; for (int i = 8 ; i < 8+NB_OUTPUTS ; i++) { io[i] = GPIO_MODE_USER_STD_OUTPUT; } - io[36] = GPIO_MODE_USER_STD_INPUT_NOPULL; - - // for (int i = 0; i < NUMNODES; i++) { - // for (int j = 0; j <= 1; j += 6) - // io[i + j] = GPIO_MODE_USER_STD_INPUT_NOPULL; - // for (int j = 1; j <= 29; j += 6) - // io[i + j] = GPIO_MODE_USER_STD_OUTPUT; - // } + io[36] = GPIO_MODE_USER_STD_INPUT_NOPULL; + io[37] = GPIO_MODE_USER_STD_INPUT_NOPULL; + /* Apply configuration */ reg_mprj_xfer = 1; while (reg_mprj_xfer == 1); @@ -60,7 +56,7 @@ void main() // change to project reg_mprj_slave = PROJECT; - // reg_mprj_oeb0 = (1 << 36); + reg_mprj_oeb1 = (1 << 4) + (1 << 5); //GPIO 36 and 37 as inputs // use logic analyser bit 0 as reset reg_la0_ena = 0x00000000; // bits 31:0 outputs diff --git a/verilog/dv/caravel/user_proj_example/ASIC_watch/ASIC_watch_tb.v b/verilog/dv/caravel/user_proj_example/ASIC_watch/ASIC_watch_tb.v index ea36425c..99517815 100644 --- a/verilog/dv/caravel/user_proj_example/ASIC_watch/ASIC_watch_tb.v +++ b/verilog/dv/caravel/user_proj_example/ASIC_watch/ASIC_watch_tb.v @@ -15,6 +15,7 @@ module ASIC_watch_tb; wire [37:0] mprj_io; // inputs reg clk_32768; + reg safemode; // outputs wire [6:0] segment_hxxx; @@ -54,7 +55,8 @@ module ASIC_watch_tb; assign segment_xxxh[5] = uut.gpio_control_in[34].pad_gpio_out; assign segment_xxxh[6] = uut.gpio_control_in[35].pad_gpio_out; - assign mprj_io[36] = clk_32768; + assign mprj_io[36] = safemode ; + assign mprj_io[37] = clk_32768; // External clock is used by default. Make this artificially fast for the // simulation. Normally this would be a slow clock and the digital PLL @@ -65,7 +67,8 @@ module ASIC_watch_tb; initial begin clock = 0; - clk_32768 = 0; + clk_32768 = 0; + safemode = 0; end diff --git a/verilog/dv/caravel/user_proj_example/ASIC_watch/Makefile b/verilog/dv/caravel/user_proj_example/ASIC_watch/Makefile index c084f70e..1e6a2559 100644 --- a/verilog/dv/caravel/user_proj_example/ASIC_watch/Makefile +++ b/verilog/dv/caravel/user_proj_example/ASIC_watch/Makefile @@ -4,7 +4,7 @@ IP_PATH = ../../../../ip #MP_PATH = ../../../../rtl/multi_project_harness BEHAVIOURAL_MODELS = ../../ -TOOLCHAIN_PREFIX?=/home/bscuser/programs/RISCV-GNU/bin/riscv64-unknown-elf- +TOOLCHAIN_PREFIX?=/opt/riscv32ic/bin/riscv32-unknown-elf- PDK_PATH?=/home/bscuser/hacking/skywater-pdk .SUFFIXES: