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correctly utilize SYNTH_TIE_UNDEFINED #623

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correctly utilize SYNTH_TIE_UNDEFINED #623

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32 changes: 23 additions & 9 deletions openlane/scripts/pyosys/synthesize.py
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Original file line number Diff line number Diff line change
Expand Up @@ -57,7 +57,9 @@ def openlane_proc(d: ys.Design, report_dir: str):
d.run_pass("opt_expr") # Optimize expressions


def openlane_synth(d, top, flatten, report_dir, *, booth=False, abc_dff=False):
def openlane_synth(
d, top, flatten, report_dir, *, booth=False, abc_dff=False, undriven=True
):
d.run_pass("hierarchy", "-check", "-top", top, "-nokeep_prints", "-nokeep_asserts")
openlane_proc(d, report_dir)

Expand Down Expand Up @@ -86,15 +88,26 @@ def openlane_synth(d, top, flatten, report_dir, *, booth=False, abc_dff=False):
d.run_pass("opt_clean") # Clean up after memory analysis

# Perform more aggressive optimization with faster runtime
d.run_pass(
"opt", "-fast", "-mux_undef", "-mux_bool", "-fine"
) # Fast and comprehensive optimization
# Fast and comprehensive optimization
if undriven:
d.run_pass("opt", "-fast", "-full")
else:
d.run_pass("opt", "-fast", "-mux_undef", "-mux_bool", "-fine")

# Technology mapping
d.run_pass("memory_map") # Map memories to standard cells
d.run_pass(
"opt", "-mux_undef", "-mux_bool", "-fine"
) # More optimization after memory mapping
d.run_pass("opt_muxtree")
d.run_pass("opt_reduce", "-fine", "-full")
d.run_pass("opt_merge", "-share_all")
d.run_pass("opt_share")
d.run_pass("opt_dff")
d.run_pass("opt_clean")
if undriven:
d.run_pass("opt", "-fast", "-full")
else:
d.run_pass(
"opt_expr", "-mux_undef", "-mux_bool", "-fine"
) # More optimization after memory mapping
d.run_pass("techmap") # Map logic to standard cells from the technology library
d.run_pass("opt", "-fast") # Fast optimization after technology mapping
d.run_pass("opt", "-fast") # More fast optimization
Expand Down Expand Up @@ -255,6 +268,7 @@ def synthesize(
report_dir,
booth=config["SYNTH_MUL_BOOTH"],
abc_dff=config["SYNTH_ABC_DFF"],
undriven=config.get("SYNTH_TIE_UNDEFINED") is not None,
)

d.run_pass("delete", "t:$print")
Expand Down Expand Up @@ -324,8 +338,8 @@ def run_strategy(d):
*(["-dff"] if config["SYNTH_ABC_DFF"] else []),
)

if value := config.get("SYNTH_SET_UNDEFINED"):
flag = "zero" if value == "low" else "high"
if value := config.get("SYNTH_TIE_UNDEFINED"):
flag = "-zero" if value == "low" else "-one"
d.run_pass("setundef", flag)

d.run_pass(
Expand Down
2 changes: 1 addition & 1 deletion openlane/steps/pyosys.py
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Original file line number Diff line number Diff line change
Expand Up @@ -463,7 +463,7 @@ class SynthesisCommon(VerilogStep):
"SYNTH_TIE_UNDEFINED",
Optional[Literal["high", "low"]],
"Whether to tie undefined values low or high. Explicitly provide null if you wish to simply leave them undriven.",
default="high",
default="low",
),
Variable(
"SYNTH_WRITE_NOATTR",
Expand Down
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