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The application will time out when attempting to enter OP-mode with DC slaves at low cycle rates <200 Hz.
Currently, the time jitter on the master PC might interfere with locking the DC clocks.
optimizing the rt-performance, in order to minimize jitter did not yield any improvement.
The text was updated successfully, but these errors were encountered:
The application will time out when attempting to enter OP-mode with DC slaves at low cycle rates <200 Hz.
Currently, the time jitter on the master PC might interfere with locking the DC clocks.
optimizing the rt-performance, in order to minimize jitter did not yield any improvement.
The text was updated successfully, but these errors were encountered: