We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.
You must be logged in to block users.
Contact GitHub support about this user’s behavior. Learn more about reporting abuse.
Verilog 21 7
包括同步FIFO(输入输出位宽相同),异步FIFO(输入输出位宽相同),异步FIFO(能实现输出数据位宽是输入数据位宽的1/2或2倍)
Verilog 20 5
Verilog 9 4
Verilog 8 5
Verilog 8 1
Verilog 4 3