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If the f1 is blue pill (which is not recommended due to failure to correspond to documentation, but anyway..) then the method to set system clock to 72Mhz would be using PLL multiplier of 9.
voidset_system_clock_to_72Mhz(void)
{
// Configure Flash access latency for 72 MHzFLASH->ACR=0x12;
// Enable HSE (8 MHz external crystal)RCC->CR |= (1 << 16); // HSEON: Enable HSEwhile (!(RCC->CR& (1 << 17))); // Wait for HSE to become ready (HSERDY)// Set HSE as the PLL sourceRCC->CFGR |= (1 << 16); // PLLSRC: HSE selected as PLL input// Set PLL multiplier to 9 (8 MHz * 9 = 72 MHz)RCC->CFGR |= (0b0111 << 18); // PLLMUL: PLL multiplier of 9// Set APB1 prescaler to divide by 2 (to get 36 MHz for APB1)RCC->CFGR |= (1 << 10); // PPRE1: APB1 low-speed prescaler set to 2 (36 MHz max)// Enable the PLLRCC->CR |= (1 << 24); // PLLON: Enable the PLLwhile (!(RCC->CR& (1 << 25))); // Wait for PLL to become ready (PLLRDY)// Set PLL as the system clockRCC->CFGR |= (0b10 << 0); // SW: Set PLL as the system clock (SYSCLK)
}
The text was updated successfully, but these errors were encountered:
If the f1 is blue pill (which is not recommended due to failure to correspond to documentation, but anyway..) then the method to set system clock to 72Mhz would be using PLL multiplier of 9.
The text was updated successfully, but these errors were encountered: