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top.sv
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top.sv
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/* Generated by Yosys 0.34+55 (git sha1 fa0a34062, gcc 7.5.0-6ubuntu2 -fPIC -Os) */
module top(clkin_data, in_data, out_data, probe_data);
reg [29:0] _00_;
wire [29:0] _01_;
wire [18:0] _02_;
wire [18:0] _03_;
wire [12:0] _04_;
wire [12:0] _05_;
wire [8:0] _06_;
wire [19:0] _07_;
wire celloutsig_0z;
wire [20:0] celloutsig_11z;
wire [4:0] celloutsig_12z;
wire [2:0] celloutsig_1z;
wire [10:0] celloutsig_2z;
wire celloutsig_3z;
wire [17:0] celloutsig_4z;
reg [9:0] celloutsig_5z;
wire [8:0] celloutsig_7z;
reg [19:0] celloutsig_8z;
wire celloutsig_9z;
input [127:0] clkin_data;
wire [127:0] clkin_data;
input [95:0] in_data;
wire [95:0] in_data;
output [95:0] out_data;
wire [95:0] out_data;
output [31:0] probe_data;
wire [31:0] probe_data;
assign celloutsig_4z = in_data[72:55] + { celloutsig_2z[10:5], celloutsig_1z[2:1], celloutsig_1z[1], celloutsig_0z, celloutsig_3z, celloutsig_1z[2:1], celloutsig_1z[1], celloutsig_3z, celloutsig_1z[2:1], celloutsig_1z[1] };
always_ff @(posedge clkin_data[0], posedge clkin_data[64])
if (clkin_data[64]) _00_ <= 30'h07e62dba;
else _00_ <= { in_data[91:85], _01_[22:0] };
assign celloutsig_9z = _03_ >= _02_;
assign celloutsig_3z = { _04_[12], celloutsig_1z[2:1], celloutsig_1z[1], celloutsig_1z[2:1], celloutsig_1z[1], celloutsig_0z, _04_[4:0] } > _05_;
assign celloutsig_0z = in_data[34] & ~(in_data[46]);
assign celloutsig_12z = ~ celloutsig_11z[16:12];
assign celloutsig_7z = _06_ - celloutsig_5z[8:0];
assign celloutsig_11z = { _00_[23:4], celloutsig_9z } - { celloutsig_8z[12:1], celloutsig_7z };
always_ff @(negedge clkin_data[0], negedge clkin_data[32], negedge clkin_data[64])
if (!clkin_data[64]) celloutsig_5z[0] <= 1'b0;
else if (!clkin_data[32]) celloutsig_5z[0] <= 1'b1;
else celloutsig_5z[0] <= celloutsig_4z[3];
always_ff @(negedge clkin_data[0], negedge clkin_data[33], negedge clkin_data[65])
if (!clkin_data[65]) celloutsig_5z[1] <= 1'b0;
else if (!clkin_data[33]) celloutsig_5z[1] <= 1'b1;
else celloutsig_5z[1] <= celloutsig_4z[4];
always_ff @(negedge clkin_data[0], negedge clkin_data[34], negedge clkin_data[66])
if (!clkin_data[66]) celloutsig_5z[2] <= 1'b0;
else if (!clkin_data[34]) celloutsig_5z[2] <= 1'b1;
else celloutsig_5z[2] <= celloutsig_4z[5];
always_ff @(negedge clkin_data[0], negedge clkin_data[35], negedge clkin_data[67])
if (!clkin_data[67]) celloutsig_5z[3] <= 1'b0;
else if (!clkin_data[35]) celloutsig_5z[3] <= 1'b1;
else celloutsig_5z[3] <= celloutsig_4z[6];
always_ff @(negedge clkin_data[0], negedge clkin_data[36], negedge clkin_data[68])
if (!clkin_data[68]) celloutsig_5z[4] <= 1'b0;
else if (!clkin_data[36]) celloutsig_5z[4] <= 1'b1;
else celloutsig_5z[4] <= celloutsig_4z[7];
always_ff @(negedge clkin_data[0], negedge clkin_data[37], negedge clkin_data[69])
if (!clkin_data[69]) celloutsig_5z[5] <= 1'b0;
else if (!clkin_data[37]) celloutsig_5z[5] <= 1'b1;
else celloutsig_5z[5] <= celloutsig_4z[8];
always_ff @(negedge clkin_data[0], negedge clkin_data[38], negedge clkin_data[70])
if (!clkin_data[70]) celloutsig_5z[6] <= 1'b0;
else if (!clkin_data[38]) celloutsig_5z[6] <= 1'b1;
else celloutsig_5z[6] <= celloutsig_4z[9];
always_ff @(negedge clkin_data[0], negedge clkin_data[39], negedge clkin_data[71])
if (!clkin_data[71]) celloutsig_5z[7] <= 1'b0;
else if (!clkin_data[39]) celloutsig_5z[7] <= 1'b1;
else celloutsig_5z[7] <= celloutsig_4z[10];
always_ff @(negedge clkin_data[0], negedge clkin_data[40], negedge clkin_data[72])
if (!clkin_data[72]) celloutsig_5z[8] <= 1'b0;
else if (!clkin_data[40]) celloutsig_5z[8] <= 1'b1;
else celloutsig_5z[8] <= celloutsig_4z[11];
always_ff @(negedge clkin_data[0], negedge clkin_data[41], negedge clkin_data[73])
if (!clkin_data[73]) celloutsig_5z[9] <= 1'b0;
else if (!clkin_data[41]) celloutsig_5z[9] <= 1'b1;
else celloutsig_5z[9] <= celloutsig_4z[12];
always_latch
if (clkin_data[64]) celloutsig_8z = 20'h16df4;
else if (clkin_data[96]) celloutsig_8z = _07_;
assign celloutsig_1z[2:1] = { in_data[40], celloutsig_0z } & { in_data[55], celloutsig_0z };
assign _01_[29:23] = in_data[91:85];
assign _04_[11:5] = { celloutsig_1z[2:1], celloutsig_1z[1], celloutsig_1z[2:1], celloutsig_1z[1], celloutsig_0z };
assign celloutsig_1z[0] = celloutsig_1z[1];
assign out_data[4:0] = celloutsig_12z;
endmodule