Verilog: multiple port/wire/reg declarations per line results in misanalysis

[birdybro]

Here's an example of what I mean in the title:

https://github.com/birdybro/Nand2Tetris_MiSTer/blob/master/rtl/structural/ALU.v#L35

This is valid syntax, it's just easier than putting something like this there:

module c_ALU
(
input zx,
input nx,
);

SystemVerilog analysis doesn't result in the same problem:

https://github.com/birdybro/Nand2Tetris_MiSTer/blob/master/rtl/behavioral/ALU.sv#L42

I opened a discussion because even though I know it's a bug, I was instructed by the issues template to do so.

[lildude]

This is a problem with the grammar, not Linguist. As per the troubleshooting doc, please open an issue with the upstream grammar.