forked from steveicarus/iverilog
-
Notifications
You must be signed in to change notification settings - Fork 0
/
elab_lval.cc
1601 lines (1390 loc) · 54.7 KB
/
elab_lval.cc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
* Copyright (c) 2000-2024 Stephen Williams ([email protected])
* Copyright CERN 2012-2013 / Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
# include "config.h"
# include "PExpr.h"
# include "PPackage.h"
# include "netlist.h"
# include "netmisc.h"
# include "netstruct.h"
# include "netclass.h"
# include "netdarray.h"
# include "netparray.h"
# include "netvector.h"
# include "netenum.h"
# include "compiler.h"
# include <cstdlib>
# include <iostream>
# include <climits>
# include "ivl_assert.h"
using namespace std;
/*
* These methods generate a NetAssign_ object for the l-value of the
* assignment. This is common code for the = and <= statements.
*
* What gets generated depends on the structure of the l-value. If the
* l-value is a simple name (i.e., foo <= <value>) then the NetAssign_
* is created the width of the foo reg and connected to all the
* bits.
*
* If there is a part select (i.e., foo[3:1] <= <value>) the NetAssign_
* is made only as wide as it needs to be (3 bits in this example) and
* connected to the correct bits of foo. A constant bit select is a
* special case of the part select.
*
* If the bit-select is non-constant (i.e., foo[<expr>] = <value>) the
* NetAssign_ is made wide enough to connect to all the bits of foo,
* then the mux expression is elaborated and attached to the
* NetAssign_ node as a b_mux value. The target must interpret the
* presence of a bmux value as taking a single bit and assigning it to
* the bit selected by the bmux expression.
*
* If the l-value expression is non-trivial, but can be fully
* evaluated at compile time (meaning any bit selects are constant)
* then elaboration will make a single NetAssign_ that connects to a
* synthetic reg that in turn connects to all the proper pins of the
* l-value.
*
* This last case can turn up in statements like: {a, b[1]} = c;
* rather than create a NetAssign_ for each item in the concatenation,
* elaboration makes a single NetAssign_ and connects it up properly.
*/
void PEIdent::report_mixed_assignment_conflict_(const char*category) const
{
cerr << get_fileline() << ": error: Cannot perform procedural "
"assignment to " << category << " '" << path_
<< "' because it is also continuously assigned." << endl;
}
/*
* The default interpretation of an l-value to a procedural assignment
* is to try to make a net elaboration, and see if the result is
* suitable for assignment.
*/
NetAssign_* PExpr::elaborate_lval(Design*, NetScope*, bool, bool, bool) const
{
cerr << get_fileline() << ": Assignment l-value too complex." << endl;
return 0;
}
/*
* Concatenation expressions can appear as l-values. Handle them here.
*
* If adjacent l-values in the concatenation are not bit selects, then
* merge them into a single NetAssign_ object. This can happen is code
* like ``{ ...a, b, ...}''. As long as "a" and "b" do not have bit
* selects (or the bit selects are constant) we can merge the
* NetAssign_ objects.
*
* Be careful to get the bit order right. In the expression ``{a, b}''
* a is the MSB and b the LSB. Connect the LSB to the low pins of the
* NetAssign_ object.
*/
NetAssign_* PEConcat::elaborate_lval(Design*des,
NetScope*scope,
bool is_cassign,
bool is_force,
bool is_init) const
{
if (repeat_) {
cerr << get_fileline() << ": error: Repeat concatenations make "
"no sense in l-value expressions. I refuse." << endl;
des->errors += 1;
return 0;
}
NetAssign_*res = 0;
for (unsigned idx = 0 ; idx < parms_.size() ; idx += 1) {
if (parms_[idx] == 0) {
cerr << get_fileline() << ": error: Empty expressions "
<< "not allowed in concatenations." << endl;
des->errors += 1;
continue;
}
NetAssign_*tmp = parms_[idx]->elaborate_lval(des, scope,
is_cassign, is_force, is_init);
/* If the l-value doesn't elaborate, the error was
already detected and printed. We just skip it and let
the compiler catch more errors. */
if (tmp == 0) continue;
if (tmp->expr_type() == IVL_VT_REAL) {
cerr << parms_[idx]->get_fileline() << ": error: "
<< "concatenation operand can not be real: "
<< *parms_[idx] << endl;
des->errors += 1;
continue;
}
/* A concatenation is always unsigned. */
tmp->set_signed(false);
/* Link the new l-value to the previous one. */
NetAssign_*last = tmp;
while (last->more)
last = last->more;
last->more = res;
res = tmp;
}
return res;
}
/*
* Handle the ident as an l-value. This includes bit and part selects
* of that ident.
*/
NetAssign_* PEIdent::elaborate_lval(Design*des,
NetScope*scope,
bool is_cassign,
bool is_force,
bool is_init) const
{
if (debug_elaborate) {
cerr << get_fileline() << ": PEIdent::elaborate_lval: "
<< "Elaborate l-value ident expression: " << *this << endl;
}
symbol_search_results sr;
symbol_search(this, des, scope, path_, lexical_pos_, &sr);
NetNet *reg = sr.net;
pform_name_t &member_path = sr.path_tail;
/* The l-value must be a variable. If not, then give up and
print a useful error message. */
if (reg == 0) {
if (scope->type()==NetScope::FUNC
&& scope->func_def()->is_void()
&& scope->basename()==peek_tail_name(path_)) {
cerr << get_fileline() << ": error: "
<< "Cannot assign to " << path_
<< " because function " << scope_path(scope)
<< " is void." << endl;
} else {
cerr << get_fileline() << ": error: Could not find variable ``"
<< path_ << "'' in ``" << scope_path(scope) <<
"''" << endl;
if (sr.decl_after_use) {
cerr << sr.decl_after_use->get_fileline() << ": : "
"A symbol with that name was declared here. "
"Check for declaration after use." << endl;
}
}
des->errors += 1;
return 0;
}
ivl_assert(*this, reg);
if (debug_elaborate) {
cerr << get_fileline() << ": " << __func__ << ": "
<< "Found l-value path_=" << path_
<< " as reg=" << reg->name() << endl;
cerr << get_fileline() << ": " << __func__ << ": "
<< "reg->type()=" << reg->type()
<< ", reg->unpacked_dimensions()=" << reg->unpacked_dimensions()
<< endl;
if (reg->net_type())
cerr << get_fileline() << ": " << __func__ << ": "
<< "reg->net_type()=" << *reg->net_type() << endl;
else
cerr << get_fileline() << ": " << __func__ << ": "
<< "reg->net_type()=<nil>" << endl;
const pform_name_t &base_path = sr.path_head;
cerr << get_fileline() << ": " << __func__ << ": "
<< " base_path=" << base_path
<< ", member_path=" << member_path
<< endl;
}
if (reg->get_const() && !is_init) {
cerr << get_fileline() << ": error: Assignment to const signal `"
<< reg->name() << "` is not allowed." << endl;
des->errors++;
return nullptr;
}
/* We are elaborating procedural assignments. Wires are not allowed
unless this is the l-value of a force. */
if ((reg->type() != NetNet::REG)
&& ((reg->type() != NetNet::UNRESOLVED_WIRE) || !reg->coerced_to_uwire())
&& !is_force) {
cerr << get_fileline() << ": error: '" << path_
<< "' is not a valid l-value for a procedural assignment."
<< endl;
cerr << reg->get_fileline() << ": : '" << path_ <<
"' is declared here as a " << reg->type() << "." << endl;
des->errors += 1;
return 0;
}
return elaborate_lval_var_(des, scope, is_force, is_cassign, reg,
sr.type, member_path);
}
NetAssign_*PEIdent::elaborate_lval_var_(Design *des, NetScope *scope,
bool is_force, bool is_cassign,
NetNet *reg, ivl_type_t data_type,
pform_name_t tail_path) const
{
// We are processing the tail of a string of names. For
// example, the Verilog may be "a.b.c", so we are processing
// "c" at this point.
const name_component_t&name_tail = path_.back();
// Use the last index to determine what kind of select
// (bit/part/etc) we are processing. For example, the Verilog
// may be "a.b.c[1][2][<index>]". All but the last index must
// be simple expressions, only the <index> may be a part
// select etc., so look at it to determine how we will be
// proceeding.
index_component_t::ctype_t use_sel = index_component_t::SEL_NONE;
if (!name_tail.index.empty())
use_sel = name_tail.index.back().sel;
// Special case: The l-value is an entire memory, or array
// slice. Detect the situation by noting if the index count
// is less than the array dimensions (unpacked).
if (reg->unpacked_dimensions() > name_tail.index.size()) {
return elaborate_lval_array_(des, scope, is_force, reg);
}
// If we find that the matched variable is a packed struct,
// then we can handled it with the net_packed_member_ method.
if (reg->struct_type() && !tail_path.empty()) {
NetAssign_*lv = new NetAssign_(reg);
elaborate_lval_net_packed_member_(des, scope, lv, tail_path, is_force);
return lv;
}
// If the variable is a class object, then handle it with the
// net_class_member_ method.
const netclass_t *class_type = dynamic_cast<const netclass_t *>(data_type);
if (class_type && !tail_path.empty() && gn_system_verilog())
return elaborate_lval_net_class_member_(des, scope, class_type, reg, tail_path);
// Past this point, we should have taken care of the cases
// where the name is a member/method of a struct/class.
// XXXX ivl_assert(*this, method_name.nil());
ivl_assert(*this, tail_path.empty());
bool need_const_idx = is_cassign || is_force;
if (reg->unpacked_dimensions() > 0)
return elaborate_lval_net_word_(des, scope, reg, need_const_idx, is_force);
// This must be after the array word elaboration above!
if (reg->get_scalar() &&
use_sel != index_component_t::SEL_NONE) {
cerr << get_fileline() << ": error: can not select part of ";
if (reg->data_type() == IVL_VT_REAL) cerr << "real: ";
else cerr << "scalar: ";
cerr << reg->name() << endl;
des->errors += 1;
return 0;
}
if (use_sel == index_component_t::SEL_PART) {
NetAssign_*lv = new NetAssign_(reg);
elaborate_lval_net_part_(des, scope, lv, is_force);
return lv;
}
if (use_sel == index_component_t::SEL_IDX_UP ||
use_sel == index_component_t::SEL_IDX_DO) {
NetAssign_*lv = new NetAssign_(reg);
elaborate_lval_net_idx_(des, scope, lv, use_sel, need_const_idx, is_force);
return lv;
}
if (use_sel == index_component_t::SEL_BIT) {
if (reg->darray_type()) {
NetAssign_*lv = new NetAssign_(reg);
elaborate_lval_darray_bit_(des, scope, lv, is_force);
return lv;
} else {
NetAssign_*lv = new NetAssign_(reg);
elaborate_lval_net_bit_(des, scope, lv, need_const_idx, is_force);
return lv;
}
}
ivl_assert(*this, use_sel == index_component_t::SEL_NONE);
if (reg->type()==NetNet::UNRESOLVED_WIRE && !is_force) {
ivl_assert(*this, reg->coerced_to_uwire());
report_mixed_assignment_conflict_("variable");
des->errors += 1;
return 0;
}
/* No select expressions. */
NetAssign_*lv = new NetAssign_(reg);
lv->set_signed(reg->get_signed());
return lv;
}
NetAssign_*PEIdent::elaborate_lval_array_(Design *des, NetScope *,
bool is_force, NetNet *reg) const
{
if (!gn_system_verilog()) {
cerr << get_fileline() << ": error: Assignment to an entire"
" array or to an array slice requires SystemVerilog."
<< endl;
des->errors += 1;
return 0;
}
const name_component_t&name_tail = path_.back();
if (name_tail.index.empty()) {
if ((reg->type()==NetNet::UNRESOLVED_WIRE) && !is_force) {
ivl_assert(*this, reg->coerced_to_uwire());
report_mixed_assignment_conflict_("array");
des->errors += 1;
return 0;
}
NetAssign_*lv = new NetAssign_(reg);
return lv;
}
cerr << get_fileline() << ": sorry: Assignment to an "
" array slice is not yet supported."
<< endl;
des->errors += 1;
return 0;
}
NetAssign_* PEIdent::elaborate_lval_net_word_(Design*des,
NetScope*scope,
NetNet*reg,
bool need_const_idx,
bool is_force) const
{
const name_component_t&name_tail = path_.back();
ivl_assert(*this, !name_tail.index.empty());
if (debug_elaborate) {
cerr << get_fileline() << ": PEIdent::elaborate_lval_net_word_: "
<< "Handle as n-dimensional array." << endl;
}
if (name_tail.index.size() < reg->unpacked_dimensions()) {
cerr << get_fileline() << ": error: Array " << reg->name()
<< " needs " << reg->unpacked_dimensions() << " indices,"
<< " but got only " << name_tail.index.size() << "." << endl;
des->errors += 1;
return 0;
}
// Make sure there are enough indices to address an array element.
const index_component_t&index_head = name_tail.index.front();
if (index_head.sel == index_component_t::SEL_PART) {
cerr << get_fileline() << ": error: cannot perform a part "
<< "select on array " << reg->name() << "." << endl;
des->errors += 1;
return 0;
}
// Evaluate all the index expressions into an
// "unpacked_indices" array.
list<NetExpr*>unpacked_indices;
list<long> unpacked_indices_const;
indices_flags flags;
indices_to_expressions(des, scope, this,
name_tail.index, reg->unpacked_dimensions(),
false,
flags,
unpacked_indices,
unpacked_indices_const);
NetExpr*canon_index = 0;
if (flags.invalid) {
// Nothing to do.
} else if (flags.undefined) {
cerr << get_fileline() << ": warning: "
<< "ignoring undefined l-value array access "
<< reg->name() << as_indices(unpacked_indices)
<< "." << endl;
} else if (flags.variable) {
if (need_const_idx) {
cerr << get_fileline() << ": error: array '" << reg->name()
<< "' index must be a constant in this context." << endl;
des->errors += 1;
return 0;
}
ivl_assert(*this, unpacked_indices.size() == reg->unpacked_dimensions());
canon_index = normalize_variable_unpacked(reg, unpacked_indices);
} else {
ivl_assert(*this, unpacked_indices_const.size() == reg->unpacked_dimensions());
canon_index = normalize_variable_unpacked(reg, unpacked_indices_const);
if (canon_index == 0) {
cerr << get_fileline() << ": warning: "
<< "ignoring out of bounds l-value array access "
<< reg->name() << as_indices(unpacked_indices_const)
<< "." << endl;
}
}
// Ensure invalid array accesses are ignored.
if (canon_index == 0)
canon_index = new NetEConst(verinum(verinum::Vx));
canon_index->set_line(*this);
if (debug_elaborate) {
cerr << get_fileline() << ": PEIdent::elaborate_lval_net_word_: "
<< "canon_index=" << *canon_index << endl;
}
if ((reg->type()==NetNet::UNRESOLVED_WIRE) && !is_force) {
ivl_assert(*this, reg->coerced_to_uwire());
NetEConst*canon_const = dynamic_cast<NetEConst*>(canon_index);
if (!canon_const || reg->test_part_driven(reg->vector_width() - 1, 0,
canon_const->value().as_long())) {
report_mixed_assignment_conflict_("array word");
des->errors += 1;
return 0;
}
}
NetAssign_*lv = new NetAssign_(reg);
lv->set_word(canon_index);
if (debug_elaborate)
cerr << get_fileline() << ": debug: Set array word=" << *canon_index << endl;
/* An array word may also have part selects applied to them. */
index_component_t::ctype_t use_sel = index_component_t::SEL_NONE;
if (name_tail.index.size() > reg->unpacked_dimensions())
use_sel = name_tail.index.back().sel;
if (reg->get_scalar() &&
use_sel != index_component_t::SEL_NONE) {
cerr << get_fileline() << ": error: can not select part of ";
if (reg->data_type() == IVL_VT_REAL) cerr << "real";
else cerr << "scalar";
cerr << " array word: " << reg->name()
<< as_indices(unpacked_indices) << endl;
des->errors += 1;
return 0;
}
if (use_sel == index_component_t::SEL_BIT)
elaborate_lval_net_bit_(des, scope, lv, need_const_idx, is_force);
if (use_sel == index_component_t::SEL_PART)
elaborate_lval_net_part_(des, scope, lv, is_force);
if (use_sel == index_component_t::SEL_IDX_UP ||
use_sel == index_component_t::SEL_IDX_DO)
elaborate_lval_net_idx_(des, scope, lv, use_sel,
need_const_idx, is_force);
return lv;
}
bool PEIdent::elaborate_lval_net_bit_(Design*des,
NetScope*scope,
NetAssign_*lv,
bool need_const_idx,
bool is_force) const
{
list<long>prefix_indices;
bool rc = calculate_packed_indices_(des, scope, lv->sig(), prefix_indices);
if (!rc) return false;
const name_component_t&name_tail = path_.back();
ivl_assert(*this, !name_tail.index.empty());
const index_component_t&index_tail = name_tail.index.back();
ivl_assert(*this, index_tail.msb != 0);
ivl_assert(*this, index_tail.lsb == 0);
NetNet*reg = lv->sig();
ivl_assert(*this, reg);
// Bit selects have a single select expression. Evaluate the
// constant value and treat it as a part select with a bit
// width of 1.
NetExpr*mux = elab_and_eval(des, scope, index_tail.msb, -1);
long lsb = 0;
if (mux && mux->expr_type() == IVL_VT_REAL) {
cerr << get_fileline() << ": error: Index expression for "
<< reg->name() << "[" << *mux
<< "] cannot be a real value." << endl;
des->errors += 1;
return false;
}
if (NetEConst*index_con = dynamic_cast<NetEConst*> (mux)) {
// The index has a constant defined value.
if (index_con->value().is_defined()) {
lsb = index_con->value().as_long();
mux = 0;
// The index is undefined and this is a packed array.
} else if (prefix_indices.size()+2 <= reg->packed_dims().size()) {
long loff;
unsigned long lwid;
bool rcl = reg->sb_to_slice(prefix_indices, lsb, loff, lwid);
ivl_assert(*this, rcl);
if (warn_ob_select) {
cerr << get_fileline()
<< ": warning: L-value packed array select of "
<< reg->name();
if (reg->unpacked_dimensions() > 0) cerr << "[]";
cerr << " has an undefined index." << endl;
}
lv->set_part(new NetEConst(verinum(verinum::Vx)), lwid);
return true;
// The index is undefined and this is a bit select.
} else {
if (warn_ob_select) {
cerr << get_fileline()
<< ": warning: L-value bit select of "
<< reg->name();
if (reg->unpacked_dimensions() > 0) cerr << "[]";
cerr << " has an undefined index." << endl;
}
lv->set_part(new NetEConst(verinum(verinum::Vx)), 1);
return true;
}
}
if (debug_elaborate && (reg->type()==NetNet::UNRESOLVED_WIRE)) {
cerr << get_fileline() << ": PEIdent::elaborate_lval_net_bit_: "
<< "Try to assign bits of variable which is also continuously assigned."
<< endl;
}
if (prefix_indices.size()+2 <= reg->packed_dims().size()) {
// Special case: this is a slice of a multi-dimensional
// packed array. For example:
// reg [3:0][7:0] x;
// x[2] = ...
// This shows up as the prefix_indices being too short
// for the packed dimensions of the vector. What we do
// here is convert to a "slice" of the vector.
if (mux == 0) {
long loff;
unsigned long lwid;
bool rcl = reg->sb_to_slice(prefix_indices, lsb, loff, lwid);
ivl_assert(*this, rcl);
if ((reg->type()==NetNet::UNRESOLVED_WIRE) && !is_force) {
ivl_assert(*this, reg->coerced_to_uwire());
if (reg->test_part_driven(loff+lwid-1, loff)) {
report_mixed_assignment_conflict_("slice");
des->errors += 1;
return false;
}
}
lv->set_part(new NetEConst(verinum(loff)), lwid);
} else {
unsigned long lwid;
mux = normalize_variable_slice_base(prefix_indices, mux,
reg, lwid);
if ((reg->type()==NetNet::UNRESOLVED_WIRE) && !is_force) {
ivl_assert(*this, reg->coerced_to_uwire());
report_mixed_assignment_conflict_("slice");
des->errors += 1;
return false;
}
lv->set_part(mux, lwid);
}
} else if (reg->data_type() == IVL_VT_STRING) {
ivl_assert(*this, reg->type()!=NetNet::UNRESOLVED_WIRE);
// Special case: This is a select of a string
// variable. The target of the assignment is a character
// select of a string. Force the r-value to be an 8bit
// vector and set the "part" to be the character select
// expression. The code generator knows what to do with
// this.
if (debug_elaborate) {
cerr << get_fileline() << ": debug: "
<< "Bit select of string becomes character select." << endl;
}
if (!mux)
mux = new NetEConst(verinum(lsb));
lv->set_part(mux, &netvector_t::atom2s8);
} else if (mux) {
// Non-constant bit mux. Correct the mux for the range
// of the vector, then set the l-value part select
// expression.
if (need_const_idx) {
cerr << get_fileline() << ": error: '" << reg->name()
<< "' bit select must be a constant in this context."
<< endl;
des->errors += 1;
return false;
}
mux = normalize_variable_bit_base(prefix_indices, mux, reg);
if ((reg->type()==NetNet::UNRESOLVED_WIRE) && !is_force) {
ivl_assert(*this, reg->coerced_to_uwire());
report_mixed_assignment_conflict_("bit select");
des->errors += 1;
return false;
}
lv->set_part(mux, 1);
} else if (reg->vector_width() == 1 && reg->sb_is_valid(prefix_indices,lsb)) {
// Constant bit mux that happens to select the only bit
// of the l-value. Don't bother with any select at all.
// If there's a continuous assignment, it must be a conflict.
if ((reg->type()==NetNet::UNRESOLVED_WIRE) && !is_force) {
ivl_assert(*this, reg->coerced_to_uwire());
report_mixed_assignment_conflict_("bit select");
des->errors += 1;
return false;
}
} else {
// Constant bit select that does something useful.
long loff = reg->sb_to_idx(prefix_indices,lsb);
if (warn_ob_select && (loff < 0 || loff >= (long)reg->vector_width())) {
cerr << get_fileline() << ": warning: bit select "
<< reg->name() << "[" <<lsb<<"]"
<< " is out of range." << endl;
}
if ((reg->type()==NetNet::UNRESOLVED_WIRE) && !is_force) {
ivl_assert(*this, reg->coerced_to_uwire());
if (reg->test_part_driven(loff, loff)) {
report_mixed_assignment_conflict_("bit select");
des->errors += 1;
return false;
}
}
lv->set_part(new NetEConst(verinum(loff)), 1);
}
return true;
}
bool PEIdent::elaborate_lval_darray_bit_(Design*des,
NetScope*scope,
NetAssign_*lv,
bool is_force) const
{
const name_component_t&name_tail = path_.back();
ivl_assert(*this, !name_tail.index.empty());
// For now, only support single-dimension dynamic arrays.
ivl_assert(*this, name_tail.index.size() == 1);
if ((lv->sig()->type()==NetNet::UNRESOLVED_WIRE) && !is_force) {
ivl_assert(*this, lv->sig()->coerced_to_uwire());
report_mixed_assignment_conflict_("darray word");
des->errors += 1;
return false;
}
const index_component_t&index_tail = name_tail.index.back();
ivl_assert(*this, index_tail.msb != 0);
ivl_assert(*this, index_tail.lsb == 0);
// Evaluate the select expression...
NetExpr*mux = elab_and_eval(des, scope, index_tail.msb, -1);
lv->set_word(mux);
return true;
}
bool PEIdent::elaborate_lval_net_part_(Design*des,
NetScope*scope,
NetAssign_*lv,
bool is_force) const
{
if (lv->sig()->data_type() == IVL_VT_STRING) {
cerr << get_fileline() << ": error: Cannot part select assign to a string ('"
<< lv->sig()->name() << "')." << endl;
des->errors += 1;
return false;
}
list<long> prefix_indices;
bool rc = calculate_packed_indices_(des, scope, lv->sig(), prefix_indices);
ivl_assert(*this, rc);
// The range expressions of a part select must be
// constant. The calculate_parts_ function calculates the
// values into msb and lsb.
long msb, lsb;
bool parts_defined_flag;
bool flag = calculate_parts_(des, scope, msb, lsb, parts_defined_flag);
if (!flag) return false;
NetNet*reg = lv->sig();
ivl_assert(*this, reg);
if (! parts_defined_flag) {
if (warn_ob_select) {
cerr << get_fileline()
<< ": warning: L-value part select of "
<< reg->name();
if (reg->unpacked_dimensions() > 0) cerr << "[]";
cerr << " has an undefined index." << endl;
}
// Use a width of two here so we can distinguish between an
// undefined bit or part select.
lv->set_part(new NetEConst(verinum(verinum::Vx)), 2);
return true;
}
if ((reg->type()==NetNet::UNRESOLVED_WIRE) && !is_force) {
ivl_assert(*this, reg->coerced_to_uwire());
if (reg->test_part_driven(msb, lsb)) {
report_mixed_assignment_conflict_("part select");
des->errors += 1;
return false;
}
}
const netranges_t&packed = reg->packed_dims();
long loff, moff;
if (prefix_indices.size()+1 < packed.size()) {
// If there are fewer indices then there are packed
// dimensions, then this is a range of slices. Calculate
// it into a big slice.
bool lrc, mrc;
unsigned long lwid, mwid;
lrc = reg->sb_to_slice(prefix_indices, lsb, loff, lwid);
mrc = reg->sb_to_slice(prefix_indices, msb, moff, mwid);
if (!mrc || !lrc) {
cerr << get_fileline() << ": error: ";
cerr << "Part-select [" << msb << ":" << lsb;
cerr << "] exceeds the declared bounds for ";
cerr << reg->name();
if (reg->unpacked_dimensions() > 0) cerr << "[]";
cerr << "." << endl;
des->errors += 1;
return 0;
}
assert(lwid == mwid);
moff += mwid - 1;
} else {
loff = reg->sb_to_idx(prefix_indices,lsb);
moff = reg->sb_to_idx(prefix_indices,msb);
}
if (moff < loff) {
cerr << get_fileline() << ": error: part select "
<< reg->name() << "[" << msb<<":"<<lsb<<"]"
<< " is reversed." << endl;
des->errors += 1;
return false;
}
unsigned long wid = moff - loff + 1;
// Special case: The range winds up selecting the entire
// vector. Treat this as no part select at all.
if (loff == 0 && wid == reg->vector_width()) {
return true;
}
/* If the part select extends beyond the extremes of the
variable, then output a warning. Note that loff is
converted to normalized form so is relative the
variable pins. */
if (warn_ob_select && (loff < 0 || moff >= (long)reg->vector_width())) {
cerr << get_fileline() << ": warning: Part select "
<< reg->name() << "[" << msb<<":"<<lsb<<"]"
<< " is out of range." << endl;
}
lv->set_part(new NetEConst(verinum(loff)), wid);
return true;
}
bool PEIdent::elaborate_lval_net_idx_(Design*des,
NetScope*scope,
NetAssign_*lv,
index_component_t::ctype_t use_sel,
bool need_const_idx,
bool is_force) const
{
if (lv->sig()->data_type() == IVL_VT_STRING) {
cerr << get_fileline() << ": error: Cannot index part select assign to a string ('"
<< lv->sig()->name() << "')." << endl;
des->errors += 1;
return false;
}
list<long>prefix_indices;
bool rc = calculate_packed_indices_(des, scope, lv->sig(), prefix_indices);
ivl_assert(*this, rc);
const name_component_t&name_tail = path_.back();;
ivl_assert(*this, !name_tail.index.empty());
const index_component_t&index_tail = name_tail.index.back();
ivl_assert(*this, index_tail.msb != 0);
ivl_assert(*this, index_tail.lsb != 0);
NetNet*reg = lv->sig();
ivl_assert(*this, reg);
unsigned long wid;
calculate_up_do_width_(des, scope, wid);
NetExpr*base = elab_and_eval(des, scope, index_tail.msb, -1);
if (base && base->expr_type() == IVL_VT_REAL) {
cerr << get_fileline() << ": error: Indexed part select base "
"expression for ";
cerr << lv->sig()->name() << "[" << *base;
if (index_tail.sel == index_component_t::SEL_IDX_UP) {
cerr << "+:";
} else {
cerr << "-:";
}
cerr << wid << "] cannot be a real value." << endl;
des->errors += 1;
return 0;
}
ivl_select_type_t sel_type = IVL_SEL_OTHER;
// Handle the special case that the base is constant. For this
// case we can reduce the expression.
if (NetEConst*base_c = dynamic_cast<NetEConst*> (base)) {
// For the undefined case just let the constant pass and
// we will handle it in the code generator.
if (base_c->value().is_defined()) {
long lsv = base_c->value().as_long();
long rel_base = 0;
// Get the signal range.
const netranges_t&packed = reg->packed_dims();
if (prefix_indices.size()+1 < reg->packed_dims().size()) {
// Here we are selecting one or more sub-arrays.
// Make this work by finding the indexed sub-arrays and
// creating a generated slice that spans the whole range.
long loff, moff;
unsigned long lwid, mwid;
bool lrc, mrc;
mrc = reg->sb_to_slice(prefix_indices, lsv, moff, mwid);
if (use_sel == index_component_t::SEL_IDX_UP)
lrc = reg->sb_to_slice(prefix_indices, lsv+wid-1, loff, lwid);
else
lrc = reg->sb_to_slice(prefix_indices, lsv-wid+1, loff, lwid);
if (!mrc || !lrc) {
cerr << get_fileline() << ": error: ";
cerr << "Part-select [" << lsv;
if (index_tail.sel == index_component_t::SEL_IDX_UP) {
cerr << "+:";
} else {
cerr << "-:";
}
cerr << wid << "] exceeds the declared bounds for ";
cerr << reg->name();
if (reg->unpacked_dimensions() > 0) cerr << "[]";
cerr << "." << endl;
des->errors += 1;
return 0;
}
ivl_assert(*this, lwid == mwid);
if (moff > loff) {
rel_base = loff;
wid = moff + mwid - loff;
} else {
rel_base = moff;
wid = loff + lwid - moff;
}
} else {
long offset = 0;
// We want the last range, which is where we work.
const netrange_t&rng = packed.back();
if (((rng.get_msb() < rng.get_lsb()) &&
use_sel == index_component_t::SEL_IDX_UP) ||
((rng.get_msb() > rng.get_lsb()) &&
use_sel == index_component_t::SEL_IDX_DO)) {
offset = -wid + 1;
}
rel_base = reg->sb_to_idx(prefix_indices,lsv) + offset;
}
delete base;
if ((reg->type()==NetNet::UNRESOLVED_WIRE) && !is_force) {
ivl_assert(*this, reg->coerced_to_uwire());
if (reg->test_part_driven(rel_base+wid-1, rel_base)) {
report_mixed_assignment_conflict_("part select");
des->errors += 1;
return false;
}
}
/* If we cover the entire lvalue just skip the select. */
if (rel_base == 0 && wid == reg->vector_width()) return true;
base = new NetEConst(verinum(rel_base));
if (warn_ob_select) {
if (rel_base < 0) {
cerr << get_fileline() << ": warning: " << reg->name();
if (reg->unpacked_dimensions() > 0) cerr << "[]";
cerr << "[" << lsv;
if (use_sel == index_component_t::SEL_IDX_UP) {
cerr << "+:";
} else {
cerr << "-:";
}
cerr << wid << "] is selecting before vector." << endl;
}
if (rel_base + wid > reg->vector_width()) {
cerr << get_fileline() << ": warning: " << reg->name();
if (reg->unpacked_dimensions() > 0) cerr << "[]";
cerr << "[" << lsv;
if (use_sel == index_component_t::SEL_IDX_UP) {
cerr << "+:";
} else {
cerr << "-:";
}
cerr << wid << "] is selecting after vector." << endl;
}
}
} else if (warn_ob_select) {
cerr << get_fileline() << ": warning: L-value indexed part "
<< "select of " << reg->name();
if (reg->unpacked_dimensions() > 0) cerr << "[]";
cerr << " has an undefined base." << endl;