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per review:
Need to add support for:
wire signed yxz;
xyz ends up not being recognized as a wire.
It's the "signed" keyword that confuses it.
The text was updated successfully, but these errors were encountered:
implement IsVerilogVariableSigner to address issue #12
1f1fd5e
No branches or pull requests
per review:
Need to add support for:
xyz ends up not being recognized as a wire.
It's the "signed" keyword that confuses it.
The text was updated successfully, but these errors were encountered: