diff --git a/main/CMakeLists.txt b/main/CMakeLists.txt
index a3b6578..ddf8d7c 100644
--- a/main/CMakeLists.txt
+++ b/main/CMakeLists.txt
@@ -1,111 +1,99 @@
-# Select board to compile for:
-
-# NOTE: Only one board may be enabled!
-# If none is enabled pin mappings from generic_map.h will be used.
+# NOTE: most configuration options has been moved to my_machine.h.
+# Enable these boards here and not in my_machine.h if you want to override board specific default core options.
+# NOTE: if reflashing/updating these options will not be changed, use $RST=$ to propagate them.
OPTION(BOARD_BLACKBOX_X32 "Compile for BlackBox X32" OFF)
-OPTION(BOARD_BDRING_V3P5 "Compile for v3.5 3-axis board" OFF)
-OPTION(BOARD_BDRING_V4 "Compile for bdring v4 3-axis board" OFF)
-OPTION(BOARD_BDRING_I2S6A "Compile for bdring 6-axis I2S board - untested!" OFF)
-OPTION(BOARD_ESPDUINO32 "Compile for ESPDUINO-32 Wemos D1 R32" OFF)
-OPTION(BOARD_SOURCERABBIT_4AXIS "Compile for SourceRabbit 4-axis board" OFF)
-OPTION(BOARD_PROTONEER_3XX "Compile for Protoneer v3.xx boards" OFF)
-OPTION(BOARD_FYSETC_E4 "Compile for Fysetc E4 v1.0 board" OFF)
-OPTION(BOARD_XPRO_V5 "Compile for xPro v5 board - untested!" OFF)
-OPTION(BOARD_MKS_DLC32_V2P0 "Compile for MKS DLC2" OFF)
-OPTION(BOARD_MKS_TINYBEE_V1 "Compile for MKS Tinybee v1" OFF)
-OPTION(BOARD_CNC3040 "Compile for CNC3040 controller" OFF)
-OPTION(BOARD_ROOTCNC_V2 "Compile for RootCNC v2.x controller" OFF)
-OPTION(BOARD_ROOTCNC_V3 "Compile for RootCNC v3 controller" OFF)
-OPTION(BOARD_CNC_BOOSTERPACK "Compile for CNC BoosterPack" OFF)
-OPTION(BOARD_MY_MACHINE "Compile for my_machine_map.h" OFF)
-
-OPTION(X_AXIS_GANGED "Compile with ganged X axis" OFF)
-OPTION(X_AXIS_SQUARED "Compile with auto-squared X axis" OFF)
-OPTION(Y_AXIS_GANGED "Compile with ganged Y axis" OFF)
-OPTION(Y_AXIS_SQUARED "Compile with auto-squared Y axis" OFF)
-OPTION(Z_AXIS_GANGED "Compile with ganged Z axis" OFF)
-OPTION(Z_AXIS_SQUARED "Compile with auto-squared Z axis" OFF)
-
-# Driver options
-OPTION(NOPROBE "Compile without probe support" OFF)
-OPTION(SafetyDoor "Safety door enable" OFF)
-OPTION(MPGMode "MPG mode" OFF)
-OPTION(I2SStepping "Use I2S Stepping" OFF)
-
-# The following plugin options are supported:
-
-# Networking and WebUI plugin options
-OPTION(WiFi "Wifi + protocols" OFF)
-OPTION(Ethernet "Ethernet + protocols" OFF) # NOTE: no board maps has support for this!
-OPTION(Bluetooth "Bluetooth" OFF)
-OPTION(SoftAP "Enable soft AP mode" OFF) # WiFi only
-OPTION(FtpDaemon "Enable ftp daemon" OFF) # Requires SDcard On
-OPTION(WebDAV "Enable WebDAV protocol" OFF) # Requires SDcard On
-OPTION(mDNS "Enable mDNS protocol" OFF)
-OPTION(SSDP "Enable SSDP protocol" OFF)
-OPTION(MQTTclient "Enable MQTT client API" OFF) # For use by plugin code.
-OPTION(WebUI "WebUI services" OFF)
-OPTION(WebAuth "WebUI authentication" OFF)
-
-# SD Card plugin options
-OPTION(SDcard "SD Card Streaming" OFF)
-
-# Motor plugin options
-# NOTE: SPI mode Trinamic drivers cannot currently be used with SD Card enabled!
-OPTION(TMC2130 "Trinamic TMC2130 driver support" OFF)
-OPTION(TMC2209 "Trinamic TMC2209 driver support" OFF)
-OPTION(TMC2209_HWADDR "Trinamic TMC2209 drivers uses hardware addressing" OFF)
-OPTION(TMC5160 "Trinamic TMC5160 driver support" OFF)
-OPTION(Trinamic "Trinamic driver support via I2C" OFF)
-
-# Spindle plugin options
-# NOTE: up to four spindle options can be enabled!
-OPTION(SPINDLE_HUANYANG1 "Compile with Huanyang v1 Modbus spindle support" OFF)
-OPTION(SPINDLE_HUANYANG2 "Compile with Huanyang v2 Modbus spindle support" OFF)
-OPTION(SPINDLE_GS20 "Compile with GS20 Modbus spindle support" OFF)
-OPTION(SPINDLE_YL620A "Compile with Yalang YL620A Modbus spindle support" OFF)
-OPTION(SPINDLE_MODVFD "Compile with generic MODVFD Modbus spindle support" OFF)
-OPTION(SPINDLE_H100 "Compile with H100 Modbus spindle support" OFF)
-OPTION(SPINDLE_STEPPER "Compile with stepper spindle" OFF)
-OPTION(SPINDLE_PWM0 "Compile with standard PWM spindle" OFF)
-OPTION(SPINDLE_PWM0_CLONE "Compile with standard PWM spindle + clone" OFF)
-OPTION(SPINDLE_ALL "Compile with all spindles, including standard PWM spindle" OFF)
-# RS485 communication channel option
-OPTION(RS485_DIR_OUT "Compile with RS485 direction pin enabled" OFF)
-
-# EEPROM/FRAM plugin options
-OPTION(EEPROM "Compile with I2C EEPROM support" OFF)
-OPTION(FRAM "Compile with I2C FRAM support" OFF)
-
-# Laser plugin options
-OPTION(LBCLUSTER "Compile with LaserBurn cluster support" OFF)
-OPTION(LASERCOOLANT "Compile with Laser coolant plugin support" OFF)
-
-# Keypad plugin options
-OPTION(Keypad "I2C Keypad" OFF)
-
-# Embroidery plugin options
-OPTION(Embroidery "Embroidery" OFF)
-
-# Add NGC expression support
-OPTION(NGCExpr "Add NGC expression support" OFF)
+
+# WiFi vs. Ethernet support
+ # Do not enable unless having a board that supports it!
+OPTION(Ethernet "Compile with Ethernet support" OFF)
# Add my_plugin.c to compilation, add my_plugin.c to the main folder first
OPTION(AddMyPlugin "Add my_plugin.c" OFF)
# --- Do not change anything below unless you understand what you are doing ---
+set(SRCS
+ main.c
+ driver.c
+ nvs.c
+ uart_serial.c
+ ioports.c
+ i2c.c
+ ioexpand.c
+ boards/BlackBoxX32.c
+ networking/strutils.c
+ grbl/grbllib.c
+ grbl/coolant_control.c
+ grbl/crossbar.c
+ grbl/nvs_buffer.c
+ grbl/gcode.c
+ grbl/machine_limits.c
+ grbl/messages.c
+ grbl/modbus.c
+ grbl/motion_control.c
+ grbl/nuts_bolts.c
+ grbl/override.c
+ grbl/planner.c
+ grbl/protocol.c
+ grbl/report.c
+ grbl/settings.c
+ grbl/sleep.c
+ grbl/spindle_control.c
+ grbl/state_machine.c
+ grbl/stream.c
+ grbl/stepper.c
+ grbl/stepper2.c
+ grbl/system.c
+ grbl/tool_change.c
+ grbl/alarms.c
+ grbl/errors.c
+ grbl/ngc_expr.c
+ grbl/ngc_params.c
+ grbl/ngc_flowctrl.c
+ grbl/regex.c
+ grbl/ioports.c
+ grbl/vfs.c
+ grbl/kinematics/corexy.c
+ grbl/kinematics/wall_plotter.c
+ grbl/kinematics/delta.c
+ grbl/kinematics/polar.c
+ littlefs_hal.c
+ littlefs/lfs.c
+ littlefs/lfs_util.c
+ sdcard/fs_littlefs.c
+)
+
+if(AddMyPlugin)
+set(MY_PLUGIN_SOURCE
+ my_plugin.c
+)
+else()
+set(MY_PLUGIN_SOURCE
+ grbl/my_plugin.c
+)
+endif()
+
+set(I2S_SOURCE
+ i2s_out.c
+)
+
+set(I2S_S3_SOURCE
+ i2s_out_s3.c
+)
+
set(SDCARD_SOURCE
sdcard/sdcard.c
sdcard/ymodem.c
sdcard/fs_fatfs.c
sdcard/macros.c
)
+
set(KEYPAD_SOURCE
keypad/keypad.c
keypad/macros.c
)
+
set(WEBUI_SOURCE
webui/args.c
webui/login.c
@@ -117,12 +105,15 @@ set(WEBUI_SOURCE
webui/flashfs.c
esp_webui/fs_embedded.c
)
+
set(BLUETOOTH_SOURCE
bluetooth.c
)
+
set(MODBUS_SOURCE
spindle/modbus_rtu
)
+
set(SPINDLE_SOURCE
spindle/select.c
spindle/onoff.c
@@ -137,20 +128,25 @@ set(SPINDLE_SOURCE
spindle/vfd/spindle.c
spindle/vfd/yl620.c
)
+
set(EEPROM_SOURCE
eeprom/eeprom_24LC16B.c
eeprom/eeprom_24AAxxx.c
)
+
set(NETWORKING_FTP_SOURCE
networking/ftpd.c
networking/sfifo.c
)
+
set(WIFI_SOURCE
wifi.c
)
+
set(ETHERNET_SOURCE
enet.c
)
+
set(NETWORKING_SOURCE
wifi.c
mqtt.c
@@ -170,7 +166,10 @@ set(NETWORKING_SOURCE
networking/fs_stream.c
networking/webdav.c
networking/ssdp.c
+ networking/ftpd.c
+ networking/sfifo.c
)
+
set(TRINAMIC_SPI_SOURCE
spi.c
trinamic_if.c
@@ -184,6 +183,7 @@ set(TRINAMIC_SPI_SOURCE
trinamic/tmc5160.c
trinamic/tmc5160hal.c
)
+
set(TRINAMIC_UART_SOURCE
trinamic_if.c
motors/trinamic.c
@@ -192,153 +192,52 @@ set(TRINAMIC_UART_SOURCE
trinamic/tmc2209.c
trinamic/tmc2209hal.c
)
+
set(LASER_SOURCE
laser/coolant.c
laser/lb_clusters.c
)
+
set(EMBROIDERY_SOURCE
embroidery/embroidery.c
embroidery/brother.c
embroidery/tajima.c
)
+
set(USB_SOURCE
usb_serial.c
)
-if(AddMyPlugin)
-set(MY_PLUGIN_SOURCE
- my_plugin.c
-)
+
+if("${target}" STREQUAL "esp32s3")
+list (APPEND SRCS ${USB_SOURCE})
+list (APPEND SRCS ${I2S_S3_SOURCE})
else()
-set(MY_PLUGIN_SOURCE
- grbl/my_plugin.c
-)
+list (APPEND SRCS ${I2S_SOURCE})
endif()
-set(SRCS
- main.c
- driver.c
- nvs.c
- uart_serial.c
- ioports.c
- i2c.c
- ioexpand.c
- i2s_out.c
- boards/BlackBoxX32.c
- networking/strutils.c
- grbl/grbllib.c
- grbl/coolant_control.c
- grbl/crossbar.c
- grbl/nvs_buffer.c
- grbl/gcode.c
- grbl/machine_limits.c
- grbl/messages.c
- grbl/modbus.c
- grbl/motion_control.c
- grbl/nuts_bolts.c
- grbl/override.c
- grbl/planner.c
- grbl/protocol.c
- grbl/report.c
- grbl/settings.c
- grbl/sleep.c
- grbl/spindle_control.c
- grbl/state_machine.c
- grbl/stream.c
- grbl/stepper.c
- grbl/stepper2.c
- grbl/system.c
- grbl/tool_change.c
- grbl/alarms.c
- grbl/errors.c
- grbl/ngc_expr.c
- grbl/ngc_params.c
- grbl/ngc_flowctrl.c
- grbl/regex.c
- grbl/ioports.c
- grbl/vfs.c
- grbl/kinematics/corexy.c
- grbl/kinematics/wall_plotter.c
- grbl/kinematics/delta.c
- grbl/kinematics/polar.c
- littlefs_hal.c
- littlefs/lfs.c
- littlefs/lfs_util.c
- sdcard/fs_littlefs.c
-)
-
list (APPEND SRCS ${MY_PLUGIN_SOURCE})
-
-if(Wifi OR WIFI_ENABLE EQUAL 1)
-list (APPEND SRCS ${WIFI_SOURCE})
-endif()
-
-if(Ethernet OR ETHERNET_ENABLE EQUAL 1)
-list (APPEND SRCS ${ETHERNET_SOURCE})
-endif()
-
-if(WiFi OR WIFI_ENABLE EQUAL 1 OR Ethernet OR ETHERNET_ENABLE EQUAL 1)
list (APPEND SRCS ${NETWORKING_SOURCE})
-if((SDcard OR WebUI OR SDCARD_ENABLE GREATER_EQUAL 1) AND (FtpDaemon OR FTP_ENABLE EQUAL 1))
-list (APPEND SRCS ${NETWORKING_FTP_SOURCE})
-endif()
-endif()
-
-if(Keypad OR KEYPAD_ENABLE GREATER_EQUAL 1 OR MACROS_ENABLE GREATER_EQUAL 1)
list (APPEND SRCS ${KEYPAD_SOURCE})
-endif()
-
-if(Trinamic OR TMC2130 OR TMC5160 OR TRINAMIC_SPI_ENABLE GREATER_EQUAL 1)
list (APPEND SRCS ${TRINAMIC_SPI_SOURCE})
-endif()
-
-if(TMC2209 OR TRINAMIC_UART_ENABLE GREATER_EQUAL 1)
list (APPEND SRCS ${TRINAMIC_UART_SOURCE})
-endif()
-
-if(WebUI OR WEBUI_ENABLE GREATER_EQUAL 1)
list (APPEND SRCS ${WEBUI_SOURCE})
list (APPEND SRCS ${SDCARD_SOURCE})
-elseif(SDcard OR SDCARD_ENABLE GREATER_EQUAL 1)
-list (APPEND SRCS ${SDCARD_SOURCE})
-endif()
-if(Bluetooth OR BLUETOOTH_ENABLE EQUAL 1)
list (APPEND SRCS ${BLUETOOTH_SOURCE})
-endif()
-
-if(SPINDLE_ALL OR SPINDLE_HUANYANG1 OR SPINDLE_HUANYANG2 OR SPINDLE_GS20 OR SPINDLE_YL620A OR SPINDLE_MODVFD OR SPINDLE_H100)
-OPTION(MODBUS_SPINDLE "" ON)
-else()
-OPTION(MODBUS_SPINDLE "" OFF)
-endif()
-
-if(MODBUS_SPINDLE OR VFD_ENABLE EQUAL -1 OR VFD_ENABLE GREATER_EQUAL 1 OR MODBUS_ENABLE GREATER_EQUAL 1)
list (APPEND SRCS ${MODBUS_SOURCE})
-endif()
-
-#if(MODBUS_SPINDLE OR SPINDLE_STEPPER OR VFD_ENABLE EQUAL -1 OR VFD_ENABLE GREATER_EQUAL 1)
list (APPEND SRCS ${SPINDLE_SOURCE})
-#endif()
-
-if(EEPROM OR FRAM OR BOARD_CNC_BOOSTERPACK OR DEFINED(BOARD_CNC_BOOSTERPACK) OR EEPROM_ENABLE EQUAL 1)
list (APPEND SRCS ${EEPROM_SOURCE})
-endif()
-list (APPEND SRCS ${EEPROM_SOURCE})
-if(LBCLUSTER OR LASERCOOLANT OR LB_CLUSTERS_ENABLE EQUAL 1)
list (APPEND SRCS ${LASER_SOURCE})
-endif()
-
-if(Embroidery OR EMBROIDERY_ENABLE EQUAL 1)
list (APPEND SRCS ${EMBROIDERY_SOURCE})
-endif()
-if("${target}" STREQUAL "esp32s3")
-list (APPEND SRCS ${USB_SOURCE})
+if(Ethernet OR ETHERNET_ENABLE EQUAL 1)
+list (APPEND SRCS ${ETHERNET_SOURCE})
+else()
+list (APPEND SRCS ${WIFI_SOURCE})
endif()
idf_component_register(SRCS "${SRCS}" INCLUDE_DIRS ".")
target_compile_definitions("${COMPONENT_LIB}" PUBLIC STEP_INJECT_ENABLE=1)
-
target_compile_definitions("${COMPONENT_LIB}" PUBLIC GRBL_ESP32)
idf_build_get_property(target IDF_TARGET)
@@ -346,319 +245,33 @@ if("${target}" STREQUAL "esp32s3")
target_compile_definitions("${COMPONENT_LIB}" PUBLIC GRBL_ESP32S3=1)
endif()
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC OVERRIDE_MY_MACHINE)
target_compile_definitions("${COMPONENT_LIB}" PUBLIC LITTLEFS_ENABLE=1)
-if(BOARD_BLACKBOX_X32)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC BOARD_BLACKBOX_X32)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC DEFAULT_LIMIT_SIGNALS_INVERT_MASK=7)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC DEFAULT_PROBE_SIGNAL_INVERT=1)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC DEFAULT_ENABLE_SIGNALS_INVERT_MASK=0)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC DEFAULT_STEPPER_IDLE_LOCK_TIME=255)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC MIN_FEED_RATE_OVERRIDE=1)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC MAX_FEED_RATE_OVERRIDE=999)
-elseif(BOARD_BDRING_V3P5)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC BOARD_BDRING_V3P5)
-elseif(BOARD_BDRING_V4)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC BOARD_BDRING_V4)
-elseif(BOARD_BDRING_I2S6A)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC BOARD_BDRING_I2S6A)
-elseif(BOARD_ESPDUINO32)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC BOARD_ESPDUINO32)
-elseif(BOARD_CNC_BOOSTERPACK)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC BOARD_CNC_BOOSTERPACK)
-elseif(BOARD_SOURCERABBIT_4AXIS)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC BOARD_SOURCERABBIT_4AXIS)
-elseif(BOARD_PROTONEER_3XX)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC BOARD_PROTONEER_3XX)
-elseif(BOARD_FYSETC_E4)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC BOARD_FYSETC_E4)
-elseif(BOARD_XPRO_V5)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC BOARD_XPRO_V5)
-elseif(BOARD_MKS_DLC32_V2P0)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC BOARD_MKS_DLC32_V2P0)
-elseif(BOARD_MKS_TINYBEE_V1)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC BOARD_MKS_TINYBEE_V1)
-elseif(BOARD_CNC3040)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC BOARD_CNC3040)
-elseif(BOARD_ROOTCNC_V2)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC BOARD_ROOTCNC_V2)
-elseif(BOARD_ROOTCNC_V3)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC BOARD_ROOTCNC_V3)
-elseif(BOARD_MY_MACHINE)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC BOARD_MY_MACHINE)
-endif()
-
-if(WebUI OR WEBUI_ENABLE GREATER_EQUAL 1)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC WEBUI_INFLASH=1)
-endif()
-
-if(X_AXIS_GANGED)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC X_GANGED)
-endif()
-if(X_AXIS_SQUARED)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC X_AUTO_SQUARE)
-endif()
-if(Y_AXIS_GANGED)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC Y_GANGED)
-endif()
-if(Y_AXIS_SQUARED)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC Y_AUTO_SQUARE)
-endif()
-if(Z_AXIS_GANGED)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC Z_GANGED)
-endif()
-if(Z_AXIS_SQUARED)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC Z_AUTO_SQUARE)
-endif()
-
-if(TMC2130)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC TRINAMIC_ENABLE=2130)
-endif()
-
-if(TMC2209)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC TRINAMIC_ENABLE=2209)
-if(TMC2209_HWADDR)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC TRINAMIC_UART_ENABLE=2)
-else()
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC TRINAMIC_UART_ENABLE=1)
-endif()
-endif()
-
-if(TMC5160)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC TRINAMIC_ENABLE=5160)
-endif()
-
-if(SafetyDoor)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC SAFETY_DOOR_ENABLE=1)
-endif()
-
-if(WiFi)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC WIFI_ENABLE=1)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC TELNET_ENABLE=1)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC WEBSOCKET_ENABLE=1)
-endif()
-
-if(Ethernet)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC ETHERNET_ENABLE=1)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC TELNET_ENABLE=1)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC WEBSOCKET_ENABLE=1)
-endif()
-
-if(WiFi OR Ethernet)
-if((SDcard OR WebUI) AND FtpDaemon)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC FTP_ENABLE=1)
-endif()
-if((SDcard OR WebUI) AND WebDAV)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC WEBDAV_ENABLE=1)
-endif()
-if(mDNS)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC MDNS_ENABLE=1)
-endif()
-if(SSDP)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC SSDP_ENABLE=1)
-endif()
-if(MQTTclient)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC MQTT_ENABLE=1)
-endif()
-endif()
-
-if(SoftAP)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC WIFI_SOFTAP=1)
-endif()
-
-if(Bluetooth)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC BLUETOOTH_ENABLE=1)
-endif()
-
-if(WebUI)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC WEBUI_ENABLE=3)
target_compile_definitions("${COMPONENT_LIB}" PUBLIC STDIO_FS)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC HTTP_ENABLE=1)
target_compile_definitions("${COMPONENT_LIB}" PUBLIC LWIP_HTTPD_CUSTOM_FILES=0)
target_compile_definitions("${COMPONENT_LIB}" PUBLIC LWIP_HTTPD_DYNAMIC_HEADERS=1)
target_compile_definitions("${COMPONENT_LIB}" PUBLIC LWIP_HTTPD_SUPPORT_V09=0)
target_compile_definitions("${COMPONENT_LIB}" PUBLIC LWIP_HTTPD_SUPPORT_11_KEEPALIVE=1)
target_compile_definitions("${COMPONENT_LIB}" PUBLIC LWIP_HTTPD_SUPPORT_POST=1)
target_compile_definitions("${COMPONENT_LIB}" PUBLIC LWIP_HTTPD_DYNAMIC_FILE_READ=1)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC SDCARD_ENABLE=1)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC WEBUI_AUTO_REPORT_INTERVAL=0)
-if(WebAuth)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC WEBUI_AUTH_ENABLE=1)
-endif()
-elseif(SDcard)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC SDCARD_ENABLE=1)
-endif()
-
-if(Trinamic)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC TRINAMIC_ENABLE)
-endif()
-
-if(Keypad)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC KEYPAD_ENABLE=1)
-endif()
-
-if(MPGMode)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC MPG_ENABLE=1)
-endif()
-if(NGCExpr)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC NGC_EXPRESSIONS_ENABLE=1)
-endif()
-
-if(Embroidery)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC EMBROIDERY_ENABLE=1)
-endif()
-
-if(SPINDLE_ALL)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC SPINDLE0_ENABLE=-1)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC N_SPINDLE=8)
-else()
- if(SPINDLE_HUANYANG1)
- list(APPEND SPINDLES 1)
- endif()
- if(SPINDLE_HUANYANG2)
- list(APPEND SPINDLES 2)
- endif()
- if(SPINDLE_GS20)
- list(APPEND SPINDLES 3)
- endif()
- if(SPINDLE_YL620A)
- list(APPEND SPINDLES 4)
- endif()
- if(SPINDLE_MODVFD)
- list(APPEND SPINDLES 5)
- endif()
- if(SPINDLE_H100)
- list(APPEND SPINDLES 6)
- endif()
- if(SPINDLE_PWM0)
- list(APPEND SPINDLES 11)
- endif()
- if(SPINDLE_PWM0_CLONE)
- list(APPEND SPINDLES 11)
- list(APPEND SPINDLES 17)
- endif()
- if(SPINDLE_STEPPER)
- list(APPEND SPINDLES 19)
- endif()
-endif()
-
-list(LENGTH SPINDLES SPINDLENUM)
-
-if(SPINDLENUM GREATER_EQUAL 1)
-list(GET SPINDLES 0 SPINDLE)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC SPINDLE0_ENABLE=${SPINDLE})
-endif()
-if(SPINDLENUM GREATER_EQUAL 2)
-list(GET SPINDLES 1 SPINDLE)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC SPINDLE1_ENABLE=${SPINDLE})
-endif()
-if(SPINDLENUM GREATER_EQUAL 3)
-list(GET SPINDLES 2 SPINDLE)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC SPINDLE2_ENABLE=${SPINDLE})
-endif()
-if(SPINDLENUM GREATER_EQUAL 4)
-list(GET SPINDLES 3 SPINDLE)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC SPINDLE3_ENABLE=${SPINDLE})
-endif()
-
-if(RS485_DIR_OUT)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC RS485_DIR_ENABLE=1)
-endif()
-
-if(EEPROM OR BOARD_CNC_BOOSTERPACK)
-#target_compile_definitions("${COMPONENT_LIB}" PUBLIC EEPROM_ENABLE=1)
-endif()
-
-if(FRAM)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC EEPROM_IS_FRAM=1)
-endif()
-
-if(NOPROBE)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC PROBE_ENABLE=0)
-else()
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC PROBE_ENABLE=1)
-endif()
-
-if(LBCLUSTER)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC LB_CLUSTERS_ENABLE=1)
-endif()
-
-if(LASERCOOLANT)
-target_compile_definitions("${COMPONENT_LIB}" PUBLIC LASER_COOLANT_ENABLE=1)
+if(BOARD_BLACKBOX_X32)
+target_compile_definitions("${COMPONENT_LIB}" PUBLIC BOARD_BLACKBOX_X32)
+target_compile_definitions("${COMPONENT_LIB}" PUBLIC DEFAULT_LIMIT_SIGNALS_INVERT_MASK=7)
+target_compile_definitions("${COMPONENT_LIB}" PUBLIC DEFAULT_PROBE_SIGNAL_INVERT=1)
+target_compile_definitions("${COMPONENT_LIB}" PUBLIC DEFAULT_ENABLE_SIGNALS_INVERT_MASK=0)
+target_compile_definitions("${COMPONENT_LIB}" PUBLIC DEFAULT_STEPPER_IDLE_LOCK_TIME=255)
+target_compile_definitions("${COMPONENT_LIB}" PUBLIC MIN_FEED_RATE_OVERRIDE=1)
+target_compile_definitions("${COMPONENT_LIB}" PUBLIC MAX_FEED_RATE_OVERRIDE=999)
endif()
target_add_binary_data("${COMPONENT_LIB}" "embedded/favicon.ico" BINARY)
target_add_binary_data("${COMPONENT_LIB}" "embedded/ap_login.html" BINARY)
-if(WebUI OR WEBUI_ENABLE GREATER_EQUAL 1)
target_add_binary_data("${COMPONENT_LIB}" "embedded/index.html.gz" BINARY)
-endif()
unset(BOARD_BLACKBOX_X32 CACHE)
-unset(BOARD_ROOTCNC_V2 CACHE)
-unset(BOARD_ROOTCNC_V3 CACHE)
-unset(BOARD_BDRING_V3P5 CACHE)
-unset(BOARD_BDRING_V4 CACHE)
-unset(BOARD_BDRING_I2S6A CACHE)
-unset(BOARD_CNC_BOOSTERPACK CACHE)
-unset(BOARD_ESPDUINO32 CACHE)
-unset(BOARD_SOURCERABBIT_4AXIS CACHE)
-unset(BOARD_PROTONEER_3XX CACHE)
-unset(BOARD_FYSETC_E4 CACHE)
-unset(BOARD_XPRO_V5 CACHE)
-unset(BOARD_MKS_DLC32_V2P0 CACHE)
-unset(BOARD_MKS_TINYBEE_V1 CACHE)
-unset(BOARD_CNC3040 CACHE)
-unset(BOARD_MY_MACHINE CACHE)
-
-unset(X_AXIS_GANGED CACHE)
-unset(X_AXIS_SQUARED CACHE)
-unset(Y_AXIS_GANGED CACHE)
-unset(Y_AXIS_SQUARED CACHE)
-unset(Z_AXIS_GANGED CACHE)
-unset(Z_AXIS_SQUARED CACHE)
-
-unset(SafetyDoor CACHE)
-unset(WiFi CACHE)
unset(Ethernet CACHE)
-unset(FtpDaemon CACHE)
-unset(WebDAV CACHE)
-unset(mDNS CACHE)
-unset(SSDP CACHE)
-unset(MQTTclient CACHE)
-unset(SoftAP CACHE)
-unset(Bluetooth CACHE)
-unset(Keypad CACHE)
-unset(SDcard CACHE)
-unset(Trinamic CACHE)
-unset(TMC2130 CACHE)
-unset(TMC2209 CACHE)
-unset(TMC2209_HWADDR CACHE)
-unset(TMC5160 CACHE)
-unset(WebUI CACHE)
-unset(WebAuth CACHE)
-unset(MPGMode CACHE)
-unset(NGCExpr CACHE)
-unset(Embroidery CACHE)
unset(AddMyPlugin CACHE)
-unset(SPINDLE_ALL CACHE)
-unset(SPINDLE_HUANYANG1 CACHE)
-unset(SPINDLE_HUANYANG2 CACHE)
-unset(SPINDLE_GS20 CACHE)
-unset(SPINDLE_YL620A CACHE)
-unset(SPINDLE_MODVFD CACHE)
-unset(SPINDLE_H100 CACHE)
-unset(SPINDLE_PWM0 CACHE)
-unset(SPINDLE_PWM0_CLONE CACHE)
-unset(SPINDLE_STEPPER CACHE)
-unset(MODBUS_SPINDLE CACHE)
-unset(RS485_DIR_OUT CACHE)
-unset(EEPROM CACHE)
-unset(FRAM CACHE)
-unset(NOPROBE CACHE)
-unset(LBCLUSTER CACHE)
-unset(LASERCOOLANT CACHE)
#target_compile_options("${COMPONENT_LIB}" PRIVATE -Werror -Wall -Wextra -Wmissing-field-initializers)
target_compile_options("${COMPONENT_LIB}" PRIVATE -Wimplicit-fallthrough=1 -Wno-missing-field-initializers -Wno-maybe-uninitialized -Wno-stringop-truncation)
diff --git a/main/bluetooth.c b/main/bluetooth.c
index 82380a6..d81a2ca 100644
--- a/main/bluetooth.c
+++ b/main/bluetooth.c
@@ -5,7 +5,7 @@
Part of grblHAL
- Copyright (c) 2018-2023 Terje Io
+ Copyright (c) 2018-2024 Terje Io
Some parts of the code is based on example code by Espressif, in the public domain
@@ -23,6 +23,10 @@
along with Grbl. If not, see .
*/
+#include "driver.h"
+
+#if BLUETOOTH_ENABLE == 1
+
#include
#include
#include
@@ -39,7 +43,6 @@
#include "esp_bt_device.h"
#include "esp_spp_api.h"
-#include "driver.h"
#include "bluetooth.h"
#include "grbl/grbl.h"
#include "grbl/report.h"
@@ -625,8 +628,6 @@ bool bluetooth_disable_local (void)
return true;
}
-#if BLUETOOTH_ENABLE
-
static const setting_group_detail_t bluetooth_groups [] = {
{ Group_Root, Group_Bluetooth, "Bluetooth"},
};
diff --git a/main/boards/BlackBoxX32_map.h b/main/boards/BlackBoxX32_map.h
index acbdedf..f16d121 100644
--- a/main/boards/BlackBoxX32_map.h
+++ b/main/boards/BlackBoxX32_map.h
@@ -103,15 +103,14 @@
#define COOLANT_FLOOD_PIN GPIO_NUM_21 // coolant
//#define COOLANT_MIST_PIN GPIO_NUM_21 // or mist
+#define AUXINPUT0_PIN GPIO_NUM_0 // Mode button on front panel
+#define AUXINPUT1_PIN GPIO_NUM_16
+
// Define user-control CONTROLs (cycle start, reset, feed hold) input pins.
#if SAFETY_DOOR_ENABLE
- #define SAFETY_DOOR_PIN GPIO_NUM_16
-#else
- #define AUXINPUT1_PIN GPIO_NUM_16
+ #define SAFETY_DOOR_PIN AUXINPUT1_PIN
#endif
-#define AUXINPUT0_PIN GPIO_NUM_0 // Mode button on front panel
-
// Pin mapping when using SPI mode.
// With this mapping, SD card can be used both in SPI and 1-line SD mode.
// Note that a pull-up on CS line is required in SD mode.
diff --git a/main/boards/bdring_i2s_6_axis_map.h b/main/boards/bdring_i2s_6_axis_map.h
index 3cc55aa..8e215bb 100644
--- a/main/boards/bdring_i2s_6_axis_map.h
+++ b/main/boards/bdring_i2s_6_axis_map.h
@@ -5,7 +5,7 @@
Part of grblHAL
- Copyright (c) 2020-2023 Terje Io
+ Copyright (c) 2020-2024 Terje Io
Grbl is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
diff --git a/main/boards/bdring_i2s_6pack_ext_v2_map.h b/main/boards/bdring_i2s_6pack_ext_v2_map.h
index 103c339..3713bec 100644
--- a/main/boards/bdring_i2s_6pack_ext_v2_map.h
+++ b/main/boards/bdring_i2s_6pack_ext_v2_map.h
@@ -5,7 +5,7 @@
Part of grblHAL
- Copyright (c) 2020-2023 Terje Io
+ Copyright (c) 2020-2024 Terje Io
Grbl is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
diff --git a/main/boards/bdring_v3.5_map.h b/main/boards/bdring_v3.5_map.h
index 63a57fa..d1f8f56 100644
--- a/main/boards/bdring_v3.5_map.h
+++ b/main/boards/bdring_v3.5_map.h
@@ -5,7 +5,7 @@
Part of grblHAL
- Copyright (c) 2020-2022 Terje Io
+ Copyright (c) 2020-2024 Terje Io
Grbl is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@@ -56,17 +56,19 @@
// Define driver spindle pins
#if DRIVER_SPINDLE_PWM_ENABLE
-#define SPINDLE_PWM_PIN GPIO_NUM_17
+#define SPINDLE_PWM_PIN GPIO_NUM_17
#else
-#define AUXOUTPUT0_PIN GPIO_NUM_17
+#define AUXOUTPUT0_PIN GPIO_NUM_17
#endif
#if DRIVER_SPINDLE_ENABLE
-#define SPINDLE_ENABLE_PIN GPIO_NUM_22
+#define SPINDLE_ENABLE_PIN GPIO_NUM_22
#else
-#define AUXOUTPUT1_PIN GPIO_NUM_22
+#define AUXOUTPUT1_PIN GPIO_NUM_22
#endif
+#define AUXINPUT0_PIN GPIO_NUM_35
+
// Define flood and mist coolant enable output pins.
// N/A
@@ -76,7 +78,7 @@
#define FEED_HOLD_PIN GPIO_NUM_36
#define CYCLE_START_PIN GPIO_NUM_39
#if SAFETY_DOOR_ENABLE
-#define SAFETY_DOOR_PIN GPIO_NUM_35
+#define SAFETY_DOOR_PIN AUXINPUT0_PIN
#endif
// Define probe switch input pin.
@@ -97,4 +99,3 @@
#if KEYPAD_ENABLE
#error No free pins for keypad!
#endif
-
diff --git a/main/boards/bdring_v4_map.h b/main/boards/bdring_v4_map.h
index cafc0d9..4126f57 100644
--- a/main/boards/bdring_v4_map.h
+++ b/main/boards/bdring_v4_map.h
@@ -5,7 +5,7 @@
Part of grblHAL
- Copyright (c) 2020-2023 Terje Io
+ Copyright (c) 2020-2024 Terje Io
Grbl is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@@ -59,6 +59,8 @@
#define SPINDLE_ENABLE_PIN GPIO_NUM_22
#endif
+#define AUXINPUT0_PIN GPIO_NUM_35
+
// Define flood and mist coolant enable output pins.
#define COOLANT_FLOOD_PIN GPIO_NUM_25
@@ -71,7 +73,7 @@
#define FEED_HOLD_PIN GPIO_NUM_36
#define CYCLE_START_PIN GPIO_NUM_39
#if SAFETY_DOOR_ENABLE
-#define SAFETY_DOOR_PIN GPIO_NUM_35
+#define SAFETY_DOOR_PIN AUXINPUT0_PIN
#endif
// Define probe switch input pin.
@@ -92,7 +94,7 @@
#if MODBUS_ENABLE & MODBUS_RTU_ENABLED
#define UART2_RX_PIN GPIO_NUM_22
#define UART2_TX_PIN GPIO_NUM_21
-#if RS485_DIR_ENABLE
+#if MODBUS_ENABLE & MODBUS_RTU_DIR_ENABLED
#define MODBUS_DIRECTION_PIN GPIO_NUM_2
#endif
#endif
diff --git a/main/boards/cnc_boosterpack_map.h b/main/boards/cnc_boosterpack_map.h
index 7e0fd31..0adc1d7 100644
--- a/main/boards/cnc_boosterpack_map.h
+++ b/main/boards/cnc_boosterpack_map.h
@@ -5,7 +5,7 @@
Part of grblHAL
- Copyright (c) 2020-2023 Terje Io
+ Copyright (c) 2020-2024 Terje Io
Grbl is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@@ -90,12 +90,14 @@
#define COOLANT_FLOOD_PIN IOEXPAND
#define COOLANT_MIST_PIN IOEXPAND
+#define AUXINPUT1_PIN GPIO_NUM_34
+
// Define user-control CONTROLs (cycle start, reset, feed hold) input pins.
#define RESET_PIN GPIO_NUM_35
#define FEED_HOLD_PIN GPIO_NUM_39
#define CYCLE_START_PIN GPIO_NUM_36
#if SAFETY_DOOR_ENABLE
-#define SAFETY_DOOR_PIN GPIO_NUM_34
+#define SAFETY_DOOR_PIN AUXINPUT1_PIN
#endif
// Define probe switch input pin.
@@ -110,7 +112,7 @@
#if MODBUS_ENABLE & MODBUS_RTU_ENABLED
#define UART2_RX_PIN GPIO_NUM_33
#define UART2_TX_PIN GPIO_NUM_25
-#if RS485_DIR_ENABLE
+#if MODBUS_ENABLE & MODBUS_RTU_DIR_ENABLED
#define MODBUS_DIRECTION_PIN GPIO_NUM_25
#endif
#endif
diff --git a/main/boards/cnc_boosterpack_s3_map.h b/main/boards/cnc_boosterpack_s3_map.h
index 421bcfc..6a0611d 100644
--- a/main/boards/cnc_boosterpack_s3_map.h
+++ b/main/boards/cnc_boosterpack_s3_map.h
@@ -5,7 +5,7 @@
Part of grblHAL
- Copyright (c)2023 Terje Io
+ Copyright (c)2023-2024 Terje Io
Grbl is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@@ -81,6 +81,8 @@
#define SPINDLE_ENABLE_PIN IOEXPAND
#endif
+#define AUXINPUT1_PIN GPIO_NUM_34
+
// Define flood and mist coolant enable output pins.
#define COOLANT_FLOOD_PIN IOEXPAND
#define COOLANT_MIST_PIN IOEXPAND
@@ -90,7 +92,7 @@
#define FEED_HOLD_PIN GPIO_NUM_39
#define CYCLE_START_PIN GPIO_NUM_36
#if SAFETY_DOOR_ENABLE
-#define SAFETY_DOOR_PIN GPIO_NUM_34
+#define SAFETY_DOOR_PIN AUXINPUT1_PIN
#endif
// Define probe switch input pin.
@@ -105,7 +107,7 @@
#if MODBUS_ENABLE & MODBUS_RTU_ENABLED
#define UART2_RX_PIN GPIO_NUM_33
#define UART2_TX_PIN GPIO_NUM_25
-#if RS485_DIR_ENABLE
+#if MODBUS_ENABLE & MODBUS_RTU_DIR_ENABLED
#define MODBUS_DIRECTION_PIN GPIO_NUM_25
#endif
#endif
diff --git a/main/boards/mks_tinybee_1_0_map.h b/main/boards/mks_tinybee_1_0_map.h
index 89102aa..027210a 100644
--- a/main/boards/mks_tinybee_1_0_map.h
+++ b/main/boards/mks_tinybee_1_0_map.h
@@ -6,7 +6,7 @@
Part of grblHAL
Copyright (c) 2022 Ennio Sesana
- Copyright (c) 2023 Terje Io (added SD card, ModBus and MPG options)
+ Copyright (c) 2023-2024 Terje Io (added SD card, ModBus and MPG options)
Grbl is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@@ -28,9 +28,13 @@
#define USE_I2S_OUT
#define I2S_OUT_PIN_BASE 64
+#define SERIAL2_ENABLE 1
+#define UART2_RX_PIN GPIO_NUM_16 // EXP_1
+#define UART2_TX_PIN GPIO_NUM_17 // EXP_1
+
// timer definitions
-#define STEP_TIMER_GROUP TIMER_GROUP_0
-#define STEP_TIMER_INDEX TIMER_0
+#define STEP_TIMER_GROUP TIMER_GROUP_0
+#define STEP_TIMER_INDEX TIMER_0
#define I2S_OUT_BCK GPIO_NUM_25
#define I2S_OUT_WS GPIO_NUM_26
@@ -113,16 +117,9 @@
#define PROBE_PIN GPIO_NUM_35 // MT_DET
#endif
-#if MODBUS_ENABLE & MODBUS_RTU_ENABLED
-#define UART2_RX_PIN GPIO_NUM_16 // EXP_1
-#define UART2_TX_PIN GPIO_NUM_17 // EXP_1
#if MODBUS_ENABLE & MODBUS_RTU_DIR_ENABLED
#define MODBUS_DIRECTION_PIN GPIO_NUM_13 // EXP_1
-#endif
-#endif
-
-#if MPG_MODE == 1
-#define UART2_RX_PIN GPIO_NUM_16 // EXP_1
+#elif MPG_MODE == 1
#define MPG_ENABLE_PIN GPIO_NUM_13 // EXP_1
#endif
diff --git a/main/boards/xPro_v5_map.h b/main/boards/xPro_v5_map.h
index 3e51a71..25e69c9 100644
--- a/main/boards/xPro_v5_map.h
+++ b/main/boards/xPro_v5_map.h
@@ -72,26 +72,23 @@
#define AUXOUTPUT1_PIN GPIO_NUM_4
#endif
+#define AUXINPUT0_PIN GPIO_NUM_13
+#define AUXINPUT1_PIN GPIO_NUM_0
+
// Define flood and mist coolant enable output pins.
// Only one can be enabled!
#define COOLANT_MIST_PIN GPIO_NUM_21
//#define COOLANT_FLOOD_PIN GPIO_NUM_21
// Define user-control CONTROLs (cycle start, reset, feed hold) input pins.
-#if SAFETY_DOOR_ENABLE
-#define SAFETY_DOOR_PIN GPIO_NUM_16
-#else
-#define RESET_PIN GPIO_NUM_16 //??
-#endif
+
+#define RESET_PIN GPIO_NUM_16
// Define probe switch input pin.
#if PROBE_ENABLE
#define PROBE_PIN GPIO_NUM_22
#endif
-#define AUXINPUT0_PIN GPIO_NUM_13
-#define AUXINPUT1_PIN GPIO_NUM_0
-
// Pin mapping when using SPI mode.
// With this mapping, SD card can be used both in SPI and 1-line SD mode.
// Note that a pull-up on CS line is required in SD mode.
diff --git a/main/driver.c b/main/driver.c
index e685265..a6f97d8 100644
--- a/main/driver.c
+++ b/main/driver.c
@@ -5,7 +5,7 @@
Part of grblHAL
- Copyright (c) 2018-2023 Terje Io
+ Copyright (c) 2018-2024 Terje Io
Some parts
Copyright (c) 2011-2015 Sungeun K. Jeon
@@ -37,6 +37,7 @@
#include "nvs.h"
#include "esp_log.h"
#include "sdkconfig.h"
+#include "esp32s3/clk.h"
#include "esp_ota_ops.h"
#include "soc/rtc.h"
#include "driver/gpio.h"
@@ -46,13 +47,13 @@
#include "hal/rmt_ll.h"
#include "driver/i2c.h"
#include "hal/gpio_types.h"
-
-//#include "grbl_esp32_if/grbl_esp32_if.h"
+#include "xtensa/core-macros.h"
#include "grbl/protocol.h"
#include "grbl/state_machine.h"
#include "grbl/motor_pins.h"
#include "grbl/machine_limits.h"
+#include "grbl/pin_bits_masks.h"
#if GRBL_ESP32S3
#include "usb_serial.h"
@@ -163,19 +164,26 @@ typedef struct {
static pwm_ramp_t pwm_ramp;
#endif
+#if SAFETY_DOOR_ENABLE
+static input_signal_t *door_pin;
+#endif
static periph_signal_t *periph_pins = NULL;
static input_signal_t inputpin[] = {
#ifdef RESET_PIN
+#if ESTOP_ENABLE
+ { .id = Input_EStop, .pin = RESET_PIN, .group = PinGroup_Control },
+#else
{ .id = Input_Reset, .pin = RESET_PIN, .group = PinGroup_Control },
#endif
+#endif
#ifdef FEED_HOLD_PIN
{ .id = Input_FeedHold, .pin = FEED_HOLD_PIN, .group = PinGroup_Control },
#endif
#ifdef CYCLE_START_PIN
{ .id = Input_CycleStart, .pin = CYCLE_START_PIN, .group = PinGroup_Control },
#endif
-#ifdef SAFETY_DOOR_PIN
+#if SAFETY_DOOR_BIT
{ .id = Input_SafetyDoor, .pin = SAFETY_DOOR_PIN, .group = PinGroup_Control },
#endif
#ifdef PROBE_PIN
@@ -386,6 +394,7 @@ static output_signal_t outputpin[] = {
};
static bool IOInitDone = false, rtc_started = false;
+static rtc_cpu_freq_config_t cpu;
static portMUX_TYPE mux = portMUX_INITIALIZER_UNLOCKED, debounce_mux = portMUX_INITIALIZER_UNLOCKED;
#if PROBE_ENABLE
static probe_state_t probe = {
@@ -472,6 +481,8 @@ void initRMT (settings_t *settings)
rmtItem[1].duration0 = 0;
rmtItem[1].duration1 = 0;
+// hal.max_step_rate = 4000000UL / (rmtItem[0].duration0 + rmtItem[0].duration1); // + latency
+
uint32_t channel;
for(channel = 0; channel < (N_AXIS + N_GANGED); channel++) {
@@ -578,12 +589,23 @@ IRAM_ATTR static void driver_delay_ms (uint32_t ms, void (*callback)(void))
}
}
-#ifdef DEBUGOUT
-static void debug_out (bool enable)
+
+static inline void delay_us (uint32_t us)
{
- gpio_set_level(STEPPERS_ENABLE_PIN, enable);
-}
+#if GRBL_ESP32S3
+ int32_t t = XTHAL_GET_CCOUNT() + 240 * us; // TODO: use cpu.freq_mhz?
+
+ while((XTHAL_GET_CCOUNT() - t) < 0) {
+// __asm__ __volatile__ ("nop"); // spin here until time to output step
+ }
+#else
+ uint64_t start_time = esp_timer_get_time();
+
+ while (esp_timer_get_time() - start_time < us) {
+ __asm__ __volatile__ ("nop"); // spin here until time to output step
+ }
#endif
+}
// Enable/disable steppers
static void stepperEnable (axes_signals_t enable)
@@ -795,7 +817,8 @@ IRAM_ATTR static void I2S_stepperPulseStart (stepper_t *stepper)
{
if(stepper->dir_change) {
set_dir_outputs(stepper->dir_outbits);
- i2s_out_push_sample(i2s_delay_samples);
+ if(stepper->step_outbits.value)
+ i2s_out_push_sample(i2s_delay_samples);
}
if(stepper->step_outbits.value) {
@@ -1039,9 +1062,7 @@ void stepperOutputStep (axes_signals_t step_outbits, axes_signals_t dir_outbits)
if(step_outbits.c)
DIGITAL_OUT(C_STEP_PIN, step_outbits.c);
#endif
-/* while (esp_timer_get_time() - step_pulse_start_time < i2s_step_length) {
- __asm__ __volatile__ ("nop"); // spin here until time to turn off step
- } */
+// delay_us(i2s_step_length);
i2s_out_push_sample(i2s_step_samples);
i2s_set_step_outputs((axes_signals_t){0});
}
@@ -1249,20 +1270,15 @@ IRAM_ATTR static void stepperPulseStart (stepper_t *stepper)
if(stepper->dir_change) {
set_dir_outputs(stepper->dir_outbits);
#if USE_I2S_OUT
- uint64_t start_time = esp_timer_get_time();
- while (esp_timer_get_time() - start_time < i2s_delay_length) {
- __asm__ __volatile__ ("nop"); // spin here until time to output step
- }
+ if(stepper->step_outbits.value)
+ delay_us(i2s_delay_length + 1);
#endif
}
if(stepper->step_outbits.value) {
#if USE_I2S_OUT
- uint64_t start_time = esp_timer_get_time();
i2s_set_step_outputs(stepper->step_outbits);
- while (esp_timer_get_time() - start_time < i2s_step_length) {
- __asm__ __volatile__ ("nop"); // spin here until time to turn off step
- }
+ delay_us(i2s_step_length + 1);
i2s_set_step_outputs((axes_signals_t){0});
#else
set_step_outputs(stepper->step_outbits);
@@ -1321,7 +1337,11 @@ IRAM_ATTR static void I2S_stepperGoIdle (bool clear_signals)
static void i2s_set_streaming_mode (bool stream)
{
+#if GRBL_ESP32S3
+ TIMERG0.hw_timer[STEP_TIMER_INDEX].config.tn_en = 0;
+#else
TIMERG0.hw_timer[STEP_TIMER_INDEX].config.enable = 0;
+#endif
if(!stream && hal.stepper.wake_up == I2S_stepperWakeUp && i2s_out_get_pulser_status() == STEPPING) {
i2s_out_set_passthrough();
@@ -1434,6 +1454,8 @@ inline IRAM_ATTR static limit_signals_t limitsGetState (void)
return signals;
}
+static bool fpu_hack = false; // Needed to avoid awakening the stupid meditating guru that is overly sensitive to floats!
+
// Returns system state as a control_signals_t variable.
// Each bitfield bit indicates a control signal, where triggered is 1 and not triggered is 0.
inline IRAM_ATTR static control_signals_t systemGetState (void)
@@ -1443,24 +1465,140 @@ inline IRAM_ATTR static control_signals_t systemGetState (void)
signals.value = settings.control_invert.value;
#ifdef RESET_PIN
+#if ESTOP_ENABLE
+ signals.estop = gpio_get_level(RESET_PIN);
+#else
signals.reset = gpio_get_level(RESET_PIN);
#endif
+#endif
#ifdef FEED_HOLD_PIN
signals.feed_hold = gpio_get_level(FEED_HOLD_PIN);
#endif
#ifdef CYCLE_START_PIN
signals.cycle_start = gpio_get_level(CYCLE_START_PIN);
#endif
-#ifdef SAFETY_DOOR_PIN
+#if SAFETY_DOOR_BIT
signals.safety_door_ajar = gpio_get_level(SAFETY_DOOR_PIN);
#endif
- if(settings.control_invert.value)
- signals.value ^= settings.control_invert.value;
+#if AUX_CONTROLS_ENABLED
+
+ #ifdef SAFETY_DOOR_PIN
+ if(aux_ctrl[AuxCtrl_SafetyDoor].debouncing)
+ signals.safety_door_ajar = !settings.control_invert.safety_door_ajar;
+ else
+ signals.safety_door_ajar = DIGITAL_IN(SAFETY_DOOR_PIN);
+ #endif
+ #ifdef MOTOR_FAULT_PIN
+ signals.motor_fault = DIGITAL_IN(MOTOR_FAULT_PIN);
+ #endif
+ #ifdef MOTOR_WARNING_PIN
+ signals.motor_warning = DIGITAL_IN(MOTOR_WARNING_PIN);
+ #endif
+
+ if(settings.control_invert.mask)
+ signals.value ^= settings.control_invert.mask;
+
+ #if AUX_CONTROLS_SCAN
+ uint_fast8_t i;
+ for(i = AUX_CONTROLS_SCAN; i < AuxCtrl_NumEntries; i++) {
+ if(!fpu_hack && aux_ctrl[i].enabled) {
+ signals.mask &= ~aux_ctrl[i].cap.mask;
+ if(hal.port.wait_on_input(Port_Digital, aux_ctrl[i].port, WaitMode_Immediate, FZERO) == 1)
+ signals.mask |= aux_ctrl[i].cap.mask;
+ }
+ }
+ #endif
+
+#else
+ if(settings.control_invert.mask)
+ signals.value ^= settings.control_invert.mask;
+
+#endif // AUX_CONTROLS_ENABLED
return signals;
}
+#if AUX_CONTROLS_ENABLED
+
+IRAM_ATTR static void aux_irq_handler (uint8_t port, bool state)
+{
+ uint_fast8_t i;
+ control_signals_t signals = {0};
+
+ for(i = 0; i < AuxCtrl_NumEntries; i++) {
+ if(aux_ctrl[i].port == port) {
+ if(!aux_ctrl[i].debouncing) {
+#if SAFETY_DOOR_ENABLE
+ if(i == AuxCtrl_SafetyDoor) {
+ BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ if((aux_ctrl[i].debouncing = door_pin->active = (xTimerStartFromISR(debounceTimer, &xHigherPriorityTaskWoken) == pdPASS)))
+ break;
+ }
+#endif
+ signals.mask |= aux_ctrl[i].cap.mask;
+ if(aux_ctrl[i].irq_mode == IRQ_Mode_Change)
+ signals.deasserted = hal.port.wait_on_input(Port_Digital, aux_ctrl[i].port, WaitMode_Immediate, FZERO) == 0;
+ }
+ break;
+ }
+ }
+
+ if(signals.mask) {
+ if(!signals.deasserted) {
+ fpu_hack = true;
+ signals.mask |= systemGetState().mask;
+ }
+ hal.control.interrupt_callback(signals);
+ fpu_hack = false;
+ }
+}
+
+static bool aux_attach (xbar_t *properties, aux_ctrl_t *aux_ctrl)
+{
+ bool ok;
+ uint_fast8_t i = sizeof(inputpin) / sizeof(input_signal_t);
+
+ do {
+ i--;
+ if((ok = inputpin[i].pin == properties->pin)) {
+ inputpin[i].aux_ctrl = aux_ctrl;
+ break;
+ }
+ } while(i);
+
+ return ok;
+}
+
+static bool aux_claim (xbar_t *properties, uint8_t port, void *data)
+{
+ bool ok;
+
+ ((aux_ctrl_t *)data)->port = port;
+
+ if((ok = ioport_claim(Port_Digital, Port_Input, &((aux_ctrl_t *)data)->port, xbar_fn_to_pinname(((aux_ctrl_t *)data)->function))))
+ aux_attach(properties, (aux_ctrl_t *)data);
+
+ return ok;
+}
+
+#if AUX_CONTROLS_XMAP
+
+static bool aux_claim_explicit (aux_ctrl_t *aux_ctrl)
+{
+ if((aux_ctrl->enabled = aux_ctrl->port != 0xFF && ioport_claim(Port_Digital, Port_Input, &aux_ctrl->port, xbar_fn_to_pinname(aux_ctrl->function)))) {
+ hal.signals_cap.mask |= aux_ctrl->cap.mask;
+ aux_attach(hal.port.get_pin_info(Port_Digital, Port_Input, aux_ctrl->port), aux_ctrl);
+ } else
+ aux_ctrl->port = 0xFF;
+
+ return aux_ctrl->enabled;
+}
+
+#endif
+
+#endif // AUX_CONTROLS_ENABLED
+
#ifdef PROBE_PIN
// Sets up the probe pin invert mask to
@@ -1855,6 +1993,10 @@ void debounceTimerCallback (TimerHandle_t xTimer)
inputpin[i].active = false; //gpio_get_level(inputpin[i].pin) == (inputpin[i].invert ? 0 : 1);
grp |= inputpin[i].group;
}
+#if SAFETY_DOOR_ENABLE
+ if(&inputpin[i] == door_pin)
+ aux_ctrl[AuxCtrl_SafetyDoor].debouncing = Off;
+#endif
} while(i);
if(grp & (PinGroup_Limit|PinGroup_LimitMax)) {
@@ -1933,6 +2075,7 @@ static void settings_changed (settings_t *settings, settings_changed_flags_t cha
*********************/
#if USE_I2S_OUT
+
i2s_delay_length = (uint32_t)settings->steppers.pulse_delay_microseconds;
i2s_step_length = (uint32_t)settings->steppers.pulse_microseconds;
@@ -1948,6 +2091,9 @@ static void settings_changed (settings_t *settings, settings_changed_flags_t cha
i2s_delay_samples = i2s_delay_length / I2S_OUT_USEC_PER_PULSE; // round up?
i2s_step_samples = i2s_step_length / I2S_OUT_USEC_PER_PULSE; // round up?
+
+// hal.max_step_rate = 250000UL / (i2s_delay_samples + i2s_step_samples);
+
#else
initRMT(settings);
#endif
@@ -2106,6 +2252,16 @@ static void settings_changed (settings_t *settings, settings_changed_flags_t cha
signal->active = signal->debounce && gpio_get_level(signal->pin) == (signal->invert ? 0 : 1);
}
} while(i);
+
+#if AUX_CONTROLS_ENABLED
+ for(i = 0; i < AuxCtrl_NumEntries; i++) {
+ if(aux_ctrl[i].enabled && aux_ctrl[i].irq_mode != IRQ_Mode_None) {
+ if(aux_ctrl[i].irq_mode & (IRQ_Mode_Falling|IRQ_Mode_Rising))
+ aux_ctrl[i].irq_mode = (settings->control_invert.mask & aux_ctrl[i].cap.mask) ? IRQ_Mode_Falling : IRQ_Mode_Rising;
+ hal.port.register_interrupt_handler(aux_ctrl[i].port, aux_ctrl[i].irq_mode, aux_irq_handler);
+ }
+ }
+#endif
}
}
@@ -2218,15 +2374,20 @@ static char *sdcard_mount (FATFS **fs)
.intr_flags = ESP_INTR_FLAG_IRAM
};
-#if PIN_NUM_CLK == GPIO_NUM_14
- if(spi_bus_initialize(SPI2_HOST, &bus_config, 1) != ESP_OK)
+#if GRBL_ESP32S3
+ if(spi_bus_initialize(SDSPI_DEFAULT_HOST, &bus_config, SPI_DMA_CH_AUTO) != ESP_OK)
return NULL;
-#elif PIN_NUM_CLK == GPIO_NUM_18
+#else
+ #if PIN_NUM_CLK == GPIO_NUM_14
+ if(spi_bus_initialize(SPI2_HOST, &bus_config, 1) != ESP_OK) // 1 = SPI_DMA_CH1
+ return NULL;
+ #elif PIN_NUM_CLK == GPIO_NUM_18
if(spi_bus_initialize(SPI3_HOST, &bus_config, 1) != ESP_OK)
return NULL;
-#else
+ #else
if(spi_bus_initialize(SDSPI_DEFAULT_HOST, &bus_config, 1) != ESP_OK)
return NULL;
+ #endif
#endif
bus_ok = true;
@@ -2298,6 +2459,11 @@ static bool driver_setup (settings_t *settings)
timer_isr_register(STEP_TIMER_GROUP, STEP_TIMER_INDEX, stepper_driver_isr, 0, ESP_INTR_FLAG_IRAM, NULL);
timer_enable_intr(STEP_TIMER_GROUP, STEP_TIMER_INDEX);
+#if USE_I2S_OUT
+ i2s_out_init();
+ i2s_out_set_pulse_callback(hal.stepper.interrupt_callback);
+#endif
+
/********************
* Output signals *
********************/
@@ -2505,14 +2671,14 @@ bool driver_init (void)
{
// Enable EEPROM and serial port here for Grbl to be able to configure itself and report any errors
- rtc_cpu_freq_config_t cpu;
rtc_clk_cpu_freq_get_config(&cpu);
+
#if GRBL_ESP32S3
hal.info = "ESP32-S3";
#else
hal.info = "ESP32";
#endif
- hal.driver_version = "231218";
+ hal.driver_version = "240110";
hal.driver_url = GRBL_URL "/ESP32";
#ifdef BOARD_NAME
hal.board = BOARD_NAME;
@@ -2545,8 +2711,6 @@ bool driver_init (void)
hal.stepper.enable = stepperEnable;
hal.stepper.cycles_per_tick = I2S_stepperCyclesPerTick;
hal.stepper.pulse_start = I2S_stepperPulseStart;
- i2s_out_init();
- i2s_out_set_pulse_callback(hal.stepper.interrupt_callback);
#endif
hal.stepper.motor_iterator = motor_iterator;
#ifdef GANGING_ENABLED
@@ -2613,11 +2777,6 @@ bool driver_init (void)
hal.nvs.type = NVS_None;
#endif
-#ifdef DEBUGOUT
-
- hal.debug_out = debug_out;
-#endif
-
#if DRIVER_SPINDLE_ENABLE
#if DRIVER_SPINDLE_PWM_ENABLE
@@ -2680,8 +2839,9 @@ bool driver_init (void)
hal.driver_cap.control_pull_up = On;
hal.driver_cap.limits_pull_up = On;
hal.driver_cap.probe_pull_up = On;
-#ifdef SAFETY_DOOR_PIN
- hal.signals_cap.safety_door_ajar = On;
+#if ESTOP_ENABLE
+ hal.signals_cap.e_stop = On;
+ hal.signals_cap.reset = Off;
#endif
hal.limits_cap = get_limits_cap();
hal.home_cap = get_home_cap();
@@ -2696,9 +2856,24 @@ bool driver_init (void)
if(input->group == PinGroup_AuxInput) {
if(aux_inputs.pins.inputs == NULL)
aux_inputs.pins.inputs = input;
+ input->id = (pin_function_t)(Input_Aux0 + aux_inputs.n_pins++);
input->cap.pull_mode = PullMode_UpDown;
input->cap.irq_mode = IRQ_Mode_Edges;
- aux_inputs.n_pins++;
+#if SAFETY_DOOR_ENABLE
+ if(input->pin == SAFETY_DOOR_PIN && input->cap.irq_mode != IRQ_Mode_None) {
+ door_pin = input;
+ door_pin->debounce = On;
+ aux_ctrl[AuxCtrl_SafetyDoor].port = aux_inputs.n_pins - 1;
+ }
+#endif
+#if MOTOR_FAULT_ENABLE
+ if(input->pin == MOTOR_FAULT_PIN && input->cap.irq_mode != IRQ_Mode_None)
+ aux_ctrl[AuxCtrl_MotorFault].port = aux_inputs.n_pins - 1;
+#endif
+#if MOTOR_WARNING_ENABLE
+ if(input->pin == MOTOR_WARNING_PIN && input->cap.irq_mode != IRQ_Mode_None)
+ aux_ctrl[AuxCtrl_MotorWarning].port = aux_inputs.n_pins - 1;
+#endif
}
}
@@ -2713,20 +2888,47 @@ bool driver_init (void)
ioports_init(&aux_inputs, &aux_outputs);
+#if SAFETY_DOOR_ENABLE
+ aux_claim_explicit(&aux_ctrl[AuxCtrl_SafetyDoor]);
+#elif defined(SAFETY_DOOR_PIN)
+ hal.signals_cap.safety_door_ajar = On;
+#endif
+
+#if MOTOR_FAULT_ENABLE
+ aux_claim_explicit(&aux_ctrl[AuxCtrl_MotorFault]);
+#elif defined(MOTOR_FAULT_PIN)
+ hal.signals_cap.motor_fault = On;
+#endif
+
+#if MOTOR_WARNING_ENABLE
+ aux_claim_explicit(&aux_ctrl[AuxCtrl_MotorWarning]);
+#elif defined(MOTOR_WARNING_PIN)
+ hal.signals_cap.motor_warning = On;
+#endif
+
+#if AUX_CONTROLS_ENABLED
+ for(i = AuxCtrl_ProbeDisconnect; i < AuxCtrl_NumEntries; i++) {
+ if(aux_ctrl[i].enabled) {
+ if((aux_ctrl[i].enabled = ioports_enumerate(Port_Digital, Port_Input, (pin_mode_t){ .irq_mode = aux_ctrl[i].irq_mode }, true, aux_claim, (void *)&aux_ctrl[i])))
+ hal.signals_cap.mask |= aux_ctrl[i].cap.mask;
+ }
+ }
+#endif
+
#ifdef HAS_BOARD_INIT
board_init();
#endif
#if MPG_MODE == 1
#if KEYPAD_ENABLE == 2
- if((hal.driver_cap.mpg_mode = stream_mpg_register(stream_open_instance(MPG_STREAM, 115200, NULL), true, keypad_enqueue_keycode)))
+ if((hal.driver_cap.mpg_mode = stream_mpg_register(stream_open_instance(MPG_STREAM, 115200, NULL), MPG_STREAM_DUPLEX, keypad_enqueue_keycode)))
protocol_enqueue_rt_command(modeEnable);
#else
- if((hal.driver_cap.mpg_mode = stream_mpg_register(stream_open_instance(MPG_STREAM, 115200, NULL), true, NULL)))
+ if((hal.driver_cap.mpg_mode = stream_mpg_register(stream_open_instance(MPG_STREAM, 115200, NULL), MPG_STREAM_DUPLEX, NULL)))
protocol_enqueue_rt_command(modeEnable);
#endif
#elif MPG_MODE == 2
- hal.driver_cap.mpg_mode = stream_mpg_register(stream_open_instance(MPG_STREAM, 115200, NULL), true, keypad_enqueue_keycode);
+ hal.driver_cap.mpg_mode = stream_mpg_register(stream_open_instance(MPG_STREAM, 115200, NULL), 0, keypad_enqueue_keycode);
#elif KEYPAD_ENABLE == 2
stream_open_instance(KEYPAD_STREAM, 115200, keypad_enqueue_keycode);
#endif
diff --git a/main/driver.h b/main/driver.h
index fdfa192..582b484 100644
--- a/main/driver.h
+++ b/main/driver.h
@@ -5,7 +5,7 @@
Part of grblHAL
- Copyright (c) 2018-2023 Terje Io
+ Copyright (c) 2018-2024 Terje Io
Copyright (c) 2011-2015 Sungeun K. Jeon
Copyright (c) 2009-2011 Simen Svale Skogsrud
@@ -27,63 +27,10 @@
#define __DRIVER_H__
#ifndef OVERRIDE_MY_MACHINE
-//
-// Set options from my_machine.h
-//
#include "my_machine.h"
-
-#if WEBUI_ENABLE
-#error "WebUI is not available in this setup!"
-#endif
-//
-#else
-//
-// Process options from CMakeLists.txt
-//
-
-#if WIFI_ENABLE || ETHERNET_ENABLE
-
-//#define TELNET_ENABLE 1
-//#define WEBSOCKET_ENABLE 1
-//#define NETWORK_TELNET_PORT 23
-//#define NETWORK_FTP_PORT 21
-//#define NETWORK_HTTP_PORT 80
-//#define NETWORK_WEBSOCKET_PORT 81
-
-// Ethernet settings
-//#define NETWORK_HOSTNAME "grblHAL"
-//#define NETWORK_IPMODE 1 // 0 = static, 1 = DHCP, 2 = AutoIP
-//#define NETWORK_IP "192.168.5.1"
-//#define NETWORK_GATEWAY "192.168.5.1"
-//#define NETWORK_MASK "255.255.255.0"
-
-// WiFi Station (STA) settings
-//#define NETWORK_STA_HOSTNAME "grblHAL"
-//#define NETWORK_STA_IPMODE 1 // 0 = static, 1 = DHCP, 2 = AutoIP
-//#define NETWORK_STA_IP "192.168.5.1"
-//#define NETWORK_STA_GATEWAY "192.168.5.1"
-//#define NETWORK_STA_MASK "255.255.255.0"
-
-// WiFi Access Point (AP) settings
-#if WIFI_SOFTAP
-//#define NETWORK_AP_HOSTNAME "grblHAL_AP"
-//#define NETWORK_AP_IP "192.168.5.1"
-//#define NETWORK_AP_GATEWAY "192.168.5.1"
-//#define NETWORK_AP_MASK "255.255.255.0"
-//#define NETWORK_AP_SSID "grblHAL_AP"
-//#define NETWORK_AP_PASSWORD "grblHALpwd" // Minimum 8 characters, or blank for open
-#define WIFI_MODE WiFiMode_AP; // OPTION: WiFiMode_APSTA
-#else
-#define WIFI_MODE WiFiMode_STA; // Do not change!
-#endif
-
-#endif // WIFI_ENABLE || ETHERNET_ENABLE
-
-#ifndef RS485_DIR_ENABLE
-#define RS485_DIR_ENABLE 0
#endif
-#endif // CMakeLists options
+#include "grbl/driver_opts.h"
#include "soc/rtc.h"
#include "driver/gpio.h"
@@ -98,7 +45,6 @@
#include "freertos/semphr.h"
#include "grbl/hal.h"
-#include "grbl/driver_opts.h"
#if WIFI_ENABLE && NETWORK_STA_IPMODE == 0 && WIFI_SOFTAP
#error "Cannot use static IP for station when soft AP is enabled!"
@@ -121,12 +67,23 @@
#define IOEXPAND 0xFF // Dummy pin number for I2C IO expander
+static const DRAM_ATTR float FZERO = 0.0f;
+
// end configuration
#if !(WIFI_ENABLE || ETHERNET_ENABLE) && (HTTP_ENABLE || TELNET_ENABLE || WEBSOCKET_ENABLE || FTP_ENABLE)
#error "Networking protocols requires networking enabled!"
#endif
+#if WIFI_ENABLE
+// WiFi Access Point (AP) settings
+#if WIFI_SOFTAP
+#define WIFI_MODE WiFiMode_AP; // OPTION: WiFiMode_APSTA
+#else
+#define WIFI_MODE WiFiMode_STA; // Do not change!
+#endif
+#endif // WIFI_ENABLE
+
// End configuration
#if TRINAMIC_ENABLE
@@ -137,14 +94,6 @@
#include "trinamic/common.h"
#endif
-// TODO: move to wifi.c!
-typedef struct
-{
- grbl_wifi_mode_t mode;
- wifi_sta_settings_t sta;
- wifi_ap_settings_t ap;
-} wifi_settings_t;
-
typedef struct {
uint8_t action;
uint_fast16_t address;
@@ -232,6 +181,12 @@ extern SemaphoreHandle_t i2cBusy;
#define SP1 0
#endif
+#ifdef UART3_RX_PIN
+#define SP2 1
+#else
+#define SP2 0
+#endif
+
#if MODBUS_ENABLE & MODBUS_RTU_ENABLED
#define MODBUS_TEST 1
#else
@@ -256,9 +211,9 @@ extern SemaphoreHandle_t i2cBusy;
#define KEYPAD_TEST 0
#endif
-#if (MODBUS_TEST + KEYPAD_TEST + MPG_TEST + TRINAMIC_TEST) > (SP0 + SP1)
+#if (MODBUS_TEST + KEYPAD_TEST + MPG_TEST + TRINAMIC_TEST + (DEBUGOUT ? 1 : 0)) > (SP0 + SP1 + SP2)
#error "Too many options that requires a serial port are enabled!"
-#elif (MODBUS_TEST + KEYPAD_TEST + MPG_TEST + TRINAMIC_TEST)
+#elif (MODBUS_TEST + KEYPAD_TEST + MPG_TEST + TRINAMIC_TEST + DEBUGOUT)
#define SERIAL2_ENABLE 1
#else
#define SERIAL2_ENABLE 0
@@ -266,11 +221,30 @@ extern SemaphoreHandle_t i2cBusy;
#undef SP0
#undef SP1
+#undef SP2
#undef MODBUS_TEST
#undef KEYPAD_TEST
#undef MPG_TEST
#undef TRINAMIC_TEST
+#if MPG_ENABLE
+#if MPG_STREAM == 0
+#define MPG_STREAM_DUPLEX 1
+#elif MPG_STREAM == 1
+#ifdef UART2_TX_PIN
+#define MPG_STREAM_DUPLEX 1
+#else
+#define MPG_STREAM_DUPLEX 0
+#endif
+#elif MPG_STREAM == 2
+#ifdef UART3_TX_PIN
+#define MPG_STREAM_DUPLEX 1
+#else
+#define MPG_STREAM_DUPLEX 0
+#endif
+#endif
+#endif
+
#if MPG_MODE == 1
#ifndef MPG_ENABLE_PIN
#error "MPG_ENABLE_PIN must be defined when MPG mode is enabled!"
@@ -310,11 +284,12 @@ typedef struct {
uint32_t mask;
uint8_t offset;
bool invert;
+ volatile bool active;
+ volatile bool debounce;
pin_irq_mode_t irq_mode;
pin_mode_t cap;
ioport_interrupt_callback_ptr interrupt_callback;
- volatile bool active;
- volatile bool debounce;
+ aux_ctrl_t *aux_ctrl;
const char *description;
} input_signal_t;
diff --git a/main/i2s_out.h b/main/i2s_out.h
index c3ddd6b..b4eef9a 100644
--- a/main/i2s_out.h
+++ b/main/i2s_out.h
@@ -171,6 +171,7 @@ typedef enum {
PASSTHROUGH = 0, // Static I2S mode.The i2s_out_write() reflected with very little delay
STEPPING, // Streaming step data.
WAITING, // Waiting for the step DMA completion
+ STOPPED, // ESP32-S: no output
} i2s_out_pulser_status_t;
i2s_out_pulser_status_t i2s_out_get_pulser_status (void);
diff --git a/main/i2s_out_s3.c b/main/i2s_out_s3.c
new file mode 100644
index 0000000..9f6e6db
--- /dev/null
+++ b/main/i2s_out_s3.c
@@ -0,0 +1,1010 @@
+/*
+ i2s_out_s3.c
+
+ Part of Grbl_ESP32 and grblHAL
+
+ Basic GPIO expander using the ESP32 I2S peripheral (output)
+
+ 2020 - Michiyasu Odaki
+ 2024 - Terje Io
+
+ Grbl_ESP32 is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.
+
+ Grbl is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with Grbl_ESP32. If not, see .
+*/
+
+/**
+ * Marlin 3D Printer Firmware
+ * Copyright (c) 2020 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
+ *
+ * Based on Sprinter and grbl.
+ * Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ *
+ */
+
+// !!! Work in progress, not yet functional !!!
+
+#include "driver.h"
+
+#include "grbl/report.h"
+
+#if USE_I2S_OUT
+
+//#include
+#include
+#include
+#include
+#include
+#include
+#include "hal/i2s_ll.h"
+#include "hal/gdma_ll.h"
+#include "hal/dma_types.h"
+#include "hal/interrupt_controller_hal.h"
+#include
+#include "esp_intr_alloc.h"
+#include "soc/gdma_periph.h"
+#include "soc/system_reg.h"
+#include
+
+#include "i2s_out.h"
+
+#define delay(ms) hal.delay_ms(ms, 0);
+
+//
+// Configrations for DMA connected I2S
+//
+// One DMA buffer transfer takes about 2 ms
+// I2S_OUT_DMABUF_LEN / I2S_SAMPLE_SIZE x I2S_OUT_USEC_PER_PULSE
+// = 2000 / 4 x 4
+// = 2000us = 2ms
+// If I2S_OUT_DMABUF_COUNT is 5, it will take about 10 ms for all the DMA buffer transfers to finish.
+//
+// Increasing I2S_OUT_DMABUF_COUNT has the effect of preventing buffer underflow,
+// but on the other hand, it leads to a delay with pulse and/or non-pulse-generated I/Os.
+// The number of I2S_OUT_DMABUF_COUNT should be chosen carefully.
+//
+// Reference information:
+// FreeRTOS task time slice = portTICK_PERIOD_MS = 1 ms (ESP32 FreeRTOS port)
+//
+#define I2S_SAMPLE_SIZE 4 /* 4 bytes, 32 bits per sample */
+#define DMA_SAMPLE_COUNT (I2S_OUT_DMABUF_LEN / I2S_SAMPLE_SIZE) /* number of samples per buffer */
+#define SAMPLE_SAFE_COUNT (20 / I2S_OUT_USEC_PER_PULSE) /* prevent buffer overrun (GRBL's $0 should be less than or equal 20) */
+#ifndef I2S_OUT_INIT_VAL
+#define I2S_OUT_INIT_VAL 0
+#endif
+#define I2S_OUT_DETACH_PORT_IDX 0x100
+#define I2S_LOCAL_QUEUE 0 // Set 0 for FreeRTOS queue, 8 or 16 for local queue
+
+typedef struct {
+ uint32_t **buffers;
+ uint32_t *current;
+ uint32_t rw_pos;
+ dma_descriptor_t **desc;
+ int32_t channel;
+ intr_handle_t intr_handle;
+#if !I2S_LOCAL_QUEUE
+ xQueueHandle queue;
+#endif
+} i2s_out_dma_t;
+
+typedef struct {
+ bool initialized;
+ atomic_uint_least32_t port_data; // output value
+ volatile uint32_t pulse_period;
+ uint32_t remain_time_until_next_pulse; // Time remaining until the next pulse (usec)
+ gpio_num_t ws_pin;
+ gpio_num_t bck_pin;
+ gpio_num_t data_pin;
+ volatile i2s_out_pulse_func_t pulse_func;
+ volatile i2s_out_pulser_status_t pulser_status;
+ portMUX_TYPE spinlock, pulser_spinlock;
+ i2s_out_dma_t dma;
+} i2s_sr_t;
+
+typedef struct {
+ volatile uint_fast16_t head;
+ volatile uint_fast16_t tail;
+ dma_descriptor_t *descr[I2S_LOCAL_QUEUE];
+} i2s_dma_queue_t;
+
+static const DRAM_ATTR uint32_t i2s_tx_int_flags = GDMA_LL_EVENT_TX_DONE|GDMA_LL_EVENT_TX_TOTAL_EOF;
+
+static uint32_t pd = 0;
+
+#if I2S_LOCAL_QUEUE
+static i2s_dma_queue_t dma_queue = {0};
+static on_execute_realtime_ptr on_execute_realtime, on_execute_delay;
+#endif
+
+static i2s_sr_t i2s_sr = {
+ .ws_pin = 255,
+ .bck_pin = 255,
+ .data_pin = 255,
+ .pulser_status = STOPPED,
+ .port_data = ATOMIC_VAR_INIT(0),
+ .spinlock = portMUX_INITIALIZER_UNLOCKED,
+ .pulser_spinlock = portMUX_INITIALIZER_UNLOCKED
+};
+
+// inner lock
+#define I2S_OUT_ENTER_CRITICAL() \
+ do { \
+ if (xPortInIsrContext()) { \
+ portENTER_CRITICAL_ISR(&i2s_sr.spinlock); \
+ } else { \
+ portENTER_CRITICAL(&i2s_sr.spinlock); \
+ } \
+ } while (0)
+#define I2S_OUT_EXIT_CRITICAL() \
+ do { \
+ if (xPortInIsrContext()) { \
+ portEXIT_CRITICAL_ISR(&i2s_sr.spinlock); \
+ } else { \
+ portEXIT_CRITICAL(&i2s_sr.spinlock); \
+ } \
+ } while (0)
+
+#define I2S_OUT_ENTER_CRITICAL_ISR() portENTER_CRITICAL_ISR(&i2s_sr.spinlock)
+#define I2S_OUT_EXIT_CRITICAL_ISR() portEXIT_CRITICAL_ISR(&i2s_sr.spinlock)
+
+// outer lock
+#define I2S_OUT_PULSER_ENTER_CRITICAL() \
+ do { \
+ if (xPortInIsrContext()) { \
+ portENTER_CRITICAL_ISR(&i2s_sr.pulser_spinlock); \
+ } else { \
+ portENTER_CRITICAL(&i2s_sr.pulser_spinlock); \
+ } \
+ } while (0)
+#define I2S_OUT_PULSER_EXIT_CRITICAL() \
+ do { \
+ if (xPortInIsrContext()) { \
+ portEXIT_CRITICAL_ISR(&i2s_sr.pulser_spinlock); \
+ } else { \
+ portEXIT_CRITICAL(&i2s_sr.pulser_spinlock); \
+ } \
+ } while (0)
+
+#define I2S_OUT_PULSER_ENTER_CRITICAL_ISR() portENTER_CRITICAL_ISR(&i2s_sr.pulser_spinlock)
+#define I2S_OUT_PULSER_EXIT_CRITICAL_ISR() portEXIT_CRITICAL_ISR(&i2s_sr.pulser_spinlock)
+
+//
+// Internal functions
+//
+static inline void gpio_matrix_out_check (uint8_t gpio, uint32_t signal_idx, bool out_inv, bool oen_inv)
+{
+ if (gpio != 255) {
+ PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio], PIN_FUNC_GPIO);
+ gpio_set_direction((gpio_num_t)gpio, GPIO_MODE_OUTPUT);
+ gpio_matrix_out(gpio, signal_idx, out_inv, oen_inv);
+ }
+}
+
+static inline void i2s_out_single_data (void)
+{
+#if I2S_OUT_NUM_BITS == 16
+ uint32_t port_data = atomic_load(&i2s_sr.port_data);
+ port_data <<= 16; // Shift needed. This specification is not spelled out in the manual.
+ I2S0.conf_single_data = port_data; // Apply port data in real-time (static I2S)
+#else
+ I2S0.conf_single_data = atomic_load(&i2s_sr.port_data); // Apply port data in real-time (static I2S)
+#endif
+}
+
+static inline void IRAM_ATTR i2s_clear_dma_buffer (dma_descriptor_t *dma_desc, uint32_t port_data)
+{
+ uint32_t *buf = (uint32_t *)dma_desc->buffer, i = DMA_SAMPLE_COUNT;
+
+ do {
+ *buf++ = port_data;
+ } while(--i);
+ // Restore the buffer length.
+ // The length may have been changed short when the data was filled in to prevent buffer overrun.
+ dma_desc->dw0.length = I2S_OUT_DMABUF_LEN;
+}
+
+static void IRAM_ATTR i2s_clear_o_dma_buffers (uint32_t port_data)
+{
+ for(int i = 0; i < I2S_OUT_DMABUF_COUNT; i++) {
+
+ // Initialize DMA descriptor
+ memset(i2s_sr.dma.desc[i], 0, sizeof(dma_descriptor_t));
+
+ i2s_sr.dma.desc[i]->dw0.owner = 1;
+ i2s_sr.dma.desc[i]->dw0.suc_eof = 1;
+ i2s_sr.dma.desc[i]->dw0.length = I2S_OUT_DMABUF_LEN;
+ i2s_sr.dma.desc[i]->dw0.size = I2S_OUT_DMABUF_LEN;
+ i2s_sr.dma.desc[i]->buffer = i2s_sr.dma.buffers[i];
+ i2s_sr.dma.desc[i]->next = (dma_descriptor_t *)((i < (I2S_OUT_DMABUF_COUNT - 1)) ? (i2s_sr.dma.desc[i + 1]) : i2s_sr.dma.desc[0]);
+
+ i2s_clear_dma_buffer(i2s_sr.dma.desc[i], port_data);
+ }
+}
+
+static void IRAM_ATTR i2s_out_gpio_attach (uint8_t ws, uint8_t bck, uint8_t data)
+{
+ // Route the i2s pins to the appropriate GPIO
+ gpio_matrix_out_check(data, I2S0O_SD_OUT_IDX, false, false);
+ gpio_matrix_out_check(bck, I2S0O_BCK_OUT_IDX, false, false);
+ gpio_matrix_out_check(ws, I2S0O_WS_OUT_IDX, false, false);
+}
+
+static void IRAM_ATTR i2s_out_gpio_detach (uint8_t ws, uint8_t bck, uint8_t data)
+{
+ // Route the i2s pins to the appropriate GPIO
+ gpio_matrix_out_check(ws, I2S_OUT_DETACH_PORT_IDX, false, false);
+ gpio_matrix_out_check(bck, I2S_OUT_DETACH_PORT_IDX, false, false);
+ gpio_matrix_out_check(data, I2S_OUT_DETACH_PORT_IDX, false, false);
+}
+
+static void IRAM_ATTR i2s_out_gpio_shiftout (uint32_t port_data)
+{
+ uint32_t i = I2S_OUT_NUM_BITS;
+
+ gpio_set_level(i2s_sr.ws_pin, 0);
+
+ do {
+ gpio_set_level(i2s_sr.data_pin, !!(port_data & bit(--i)));
+ gpio_set_level(i2s_sr.bck_pin, 1);
+ gpio_set_level(i2s_sr.bck_pin, 0);
+ } while(i);
+
+// gpio_set_level(i2s_sr.data_pin, 0);
+ gpio_set_level(i2s_sr.ws_pin, 1); // Latch
+ gpio_set_level(i2s_sr.ws_pin, 0);
+}
+
+static void IRAM_ATTR i2s_out_stop (void)
+{
+ hal.stream.write("stop" ASCII_EOL);
+
+ I2S_OUT_ENTER_CRITICAL();
+
+ // Stop FIFO DMA
+ gdma_ll_tx_stop(&GDMA, i2s_sr.dma.channel);
+ gdma_ll_tx_enable_interrupt(&GDMA, i2s_sr.dma.channel, i2s_tx_int_flags, i2s_sr.pulser_status != PASSTHROUGH);
+
+//! i2s_ll_tx_stop_link(&I2S0);
+// I2S0.out_link.stop = 1;
+
+ // Disconnect DMA from FIFO
+//! i2s_ll_enable_dma(&I2S0);
+// I2S0.fifo_conf.dscr_en = 0; //Unset this bit to disable I2S DMA mode. (R/W)
+
+ // stop TX module
+ i2s_ll_tx_stop(&I2S0);
+
+ // Force WS to LOW before detach
+ // This operation prevents unintended WS edge trigger when detach
+ gpio_set_level(i2s_sr.ws_pin, 0);
+
+ // Now, detach GPIO pin from I2S
+ i2s_out_gpio_detach(i2s_sr.ws_pin, i2s_sr.bck_pin, i2s_sr.data_pin);
+
+ // Force BCK to LOW
+ // After the TX module is stopped, BCK always seems to be in LOW.
+ // However, I'm going to do it manually to ensure the BCK's LOW.
+ gpio_set_level(i2s_sr.bck_pin, 0);
+
+ // Transmit recovery data to 74HC595
+ uint32_t port_data = atomic_load(&i2s_sr.port_data); // current expanded port value
+ i2s_out_gpio_shiftout(port_data);
+
+ //clear pending interrupt
+ gdma_ll_tx_clear_interrupt_status(&GDMA, i2s_sr.dma.channel, gdma_ll_tx_get_interrupt_status(&GDMA, i2s_sr.dma.channel));
+
+ I2S_OUT_EXIT_CRITICAL();
+}
+
+static bool IRAM_ATTR i2s_out_start (i2s_out_pulser_status_t pulser_status)
+{
+ static dma_descriptor_t pass_dma = {
+ .dw0.owner = 1,
+ .dw0.suc_eof = 0,
+ .dw0.length = sizeof(i2s_sr.port_data),
+ .dw0.size = sizeof(i2s_sr.port_data),
+ .buffer = &pd, // &i2s_sr.port_data,
+ .next = &pass_dma
+ };
+
+ if(!i2s_sr.initialized)
+ return false;
+
+ I2S_OUT_ENTER_CRITICAL();
+
+ if(i2s_sr.pulse_func == NULL)
+ pulser_status = PASSTHROUGH;
+
+ if(i2s_sr.pulser_status == pulser_status) {
+ I2S_OUT_EXIT_CRITICAL();
+ return true;
+ }
+ gpio_set_level(41, 0);
+
+ gdma_ll_tx_stop(&GDMA, i2s_sr.dma.channel);
+
+ //start DMA link
+ i2s_ll_tx_reset(&I2S0);
+ i2s_ll_tx_reset_fifo(&I2S0);
+// i2s_out_gpio_attach(i2s_sr.ws_pin, i2s_sr.bck_pin, i2s_sr.data_pin);
+
+ // Transmit recovery data to 74HC595
+ uint32_t port_data = atomic_load(&i2s_sr.port_data); // current expanded port value
+// i2s_out_gpio_shiftout(port_data);
+
+ if((i2s_sr.pulser_status = pulser_status) == PASSTHROUGH)
+ pd = port_data;
+ else {
+ i2s_clear_o_dma_buffers(port_data);
+#if I2S_LOCAL_QUEUE
+ dma_queue.tail = dma_queue.head;
+#endif
+ i2s_sr.dma.rw_pos = 0;
+ i2s_sr.dma.current = i2s_sr.dma.desc[0]->buffer;
+ }
+
+ gdma_ll_tx_reset_channel(&GDMA, i2s_sr.dma.channel);
+ gdma_ll_tx_set_desc_addr(&GDMA, i2s_sr.dma.channel, (uint32_t)(i2s_sr.pulser_status == PASSTHROUGH ? &pass_dma : i2s_sr.dma.desc[0]));
+// gdma_ll_tx_connect_to_periph(&GDMA, i2s_sr.dma.channel, GDMA_TRIG_PERIPH_I2S, SOC_GDMA_TRIG_PERIPH_I2S0);
+// gdma_ll_tx_set_eof_mode(&GDMA, i2s_sr.dma.channel, 0); // Not needed?
+// gdma_ll_tx_enable_data_burst(&GDMA, i2s_sr.dma.channel, true);
+// gdma_ll_tx_enable_descriptor_burst(&GDMA, i2s_sr.dma.channel, true);
+ gdma_ll_tx_clear_interrupt_status(&GDMA, i2s_sr.dma.channel, gdma_ll_tx_get_interrupt_status(&GDMA, i2s_sr.dma.channel));
+ gdma_ll_tx_enable_interrupt(&GDMA, i2s_sr.dma.channel, i2s_tx_int_flags, i2s_sr.pulser_status != PASSTHROUGH);
+
+// I2S0.tx_conf.tx_stop_en = 1; // BCK and WCK are suppressed while FIFO is empty - no ll func!
+
+ I2S0.tx_conf.tx_update = 1;
+ while (I2S0.tx_conf.tx_update);
+
+// i2s_ll_tx_start(&I2S0);
+ gdma_ll_tx_start(&GDMA, i2s_sr.dma.channel);
+
+ I2S0.tx_conf.tx_start = 1;
+/*
+// I2S0.tx_conf.tx_start = 1;
+ // Wait for the first FIFO data to prevent the unintentional generation of 0 data
+ ets_delay_us(20);
+
+ I2S0.tx_conf.tx_stop_en = 1; // BCK and WCK are suppressed while FIFO is empty - no ll func!
+*/
+ gpio_set_level(41, 1);
+
+ I2S_OUT_EXIT_CRITICAL();
+
+ return true;
+}
+
+//
+// I2S out DMA Interrupts handler
+//
+static void IRAM_ATTR i2s_out_intr_handler (void *arg)
+{
+ portBASE_TYPE high_priority_task_awoken = pdFALSE;
+
+ uint32_t irq = gdma_ll_tx_get_interrupt_status(&GDMA, i2s_sr.dma.channel);
+
+// gpio_set_level(41, 1);
+
+ if(irq & i2s_tx_int_flags) {
+
+ // Get the descriptor of the last item in the linked list
+ dma_descriptor_t *finish_desc = (dma_descriptor_t *)gdma_ll_tx_get_eof_desc_addr(&GDMA, i2s_sr.dma.channel);
+
+ // Finished stepping?
+ if(irq & GDMA_LL_EVENT_TX_TOTAL_EOF) {
+
+ i2s_out_start(PASSTHROUGH);
+ }
+
+ // If the queue is full it's because we have an underflow,
+ // more than buf_count isr without new data, remove the front buffer
+ else if((irq & GDMA_LL_EVENT_TX_DONE) && i2s_sr.pulser_status != PASSTHROUGH) {
+
+// gpio_set_level(41, 1);
+
+ uint32_t port_data = 0;
+ dma_descriptor_t *front_desc;
+
+#if I2S_LOCAL_QUEUE
+
+ I2S_OUT_PULSER_ENTER_CRITICAL_ISR();
+
+ uint32_t qptr = (dma_queue.head + 1) & (I2S_LOCAL_QUEUE - 1); // Get next head pointer
+
+ if(dma_queue.tail == qptr) {
+
+ front_desc = dma_queue.descr[dma_queue.tail++];
+
+
+ if(i2s_sr.pulser_status == STEPPING)
+ port_data = atomic_load(&i2s_sr.port_data);
+
+
+ i2s_clear_dma_buffer(front_desc, port_data);
+
+ dma_queue.tail &= (I2S_LOCAL_QUEUE - 1);
+ }
+
+ // Send a DMA complete event to the I2S bitstreamer task with finished buffer
+ if((dma_queue.descr[dma_queue.head] = finish_desc) > 100)
+ dma_queue.head = qptr;
+
+ I2S_OUT_PULSER_EXIT_CRITICAL_ISR();
+
+#else
+
+ if(xQueueIsQueueFullFromISR(i2s_sr.dma.queue)) {
+
+ // Remove a descriptor from the DMA complete event queue
+ xQueueReceiveFromISR(i2s_sr.dma.queue, &front_desc, &high_priority_task_awoken);
+
+ I2S_OUT_PULSER_ENTER_CRITICAL_ISR();
+
+ if(i2s_sr.pulser_status == STEPPING)
+ port_data = atomic_load(&i2s_sr.port_data);
+
+ I2S_OUT_PULSER_EXIT_CRITICAL_ISR();
+
+ i2s_clear_dma_buffer(front_desc, port_data);
+ }
+
+ // Send a DMA complete event to the I2S bitstreamer task with finished buffer
+ xQueueSendFromISR(i2s_sr.dma.queue, &finish_desc, &high_priority_task_awoken);
+
+#endif
+// gpio_set_level(41, 0);
+ }
+ }
+
+ gdma_ll_tx_clear_interrupt_status(&GDMA, i2s_sr.dma.channel, 0xFF);
+// gpio_set_level(41, 0);
+
+ if(high_priority_task_awoken == pdTRUE)
+ portYIELD_FROM_ISR();
+}
+
+static void IRAM_ATTR i2s_fillout_dma_buffer (dma_descriptor_t *dma_desc)
+{
+ uint32_t *buf = (uint32_t *)dma_desc->buffer;
+
+ // It reuses the oldest (just transferred) buffer with the name "current"
+ // and fills the buffer for later DMA.
+
+ i2s_sr.dma.rw_pos = 0;
+
+ //
+ // Fillout the buffer for pulse
+ //
+ // To avoid buffer overflow, all of the maximum pulse width (normally about 10us)
+ // is adjusted to be in a single buffer.
+ // DMA_SAMPLE_SAFE_COUNT is referred to as the margin value.
+ // Therefore, if a buffer is close to full and it is time to generate a pulse,
+ // the generation of the buffer is interrupted (the buffer length is shortened slightly)
+ // and the pulse generation is postponed until the next buffer is filled.
+ //
+ while (i2s_sr.dma.rw_pos < (DMA_SAMPLE_COUNT - SAMPLE_SAFE_COUNT)) {
+
+ // no data to read (buffer empty)
+ if (i2s_sr.remain_time_until_next_pulse < I2S_OUT_USEC_PER_PULSE) {
+
+ // pulser status may change in pulse phase func, so I need to check it every time.
+ if (i2s_sr.pulser_status == STEPPING) {
+
+ // fillout future DMA buffer (tail of the DMA buffer chains)
+
+ uint32_t old_rw_pos = i2s_sr.dma.rw_pos, period;
+
+ I2S_OUT_PULSER_EXIT_CRITICAL(); // Temporarily unlocked status lock as it may be locked in pulse callback.
+
+ i2s_sr.pulse_func(); // Insert steps.
+
+ I2S_OUT_PULSER_ENTER_CRITICAL(); // Lock again.
+
+ period = I2S_OUT_USEC_PER_PULSE * (i2s_sr.dma.rw_pos - old_rw_pos);
+
+ // Calculate pulse period.
+ if(i2s_sr.pulse_period >= period)
+ i2s_sr.remain_time_until_next_pulse += i2s_sr.pulse_period - period;
+ else // too fast!
+ i2s_sr.remain_time_until_next_pulse += I2S_OUT_USEC_PER_PULSE;
+
+ if (i2s_sr.pulser_status == WAITING) {
+ // i2s_out_set_passthrough() has called from the pulse function.
+ // It needs to go into pass-through mode.
+ // This DMA descriptor must be a tail of the chain.
+ dma_desc->dw0.suc_eof = 1; //?
+ dma_desc->next = NULL; // Cut the DMA descriptor ring. This allow us to identify the tail of the buffer.
+ } else if (i2s_sr.pulser_status == PASSTHROUGH) {
+ // i2s_out_reset() has called during the execution of the pulse function.
+ // I2S has already in static mode, and buffers has cleared to zero.
+ // To prevent the pulse function from being called back,
+ // we assume that the buffer is already full.
+ i2s_sr.remain_time_until_next_pulse = 0; // There is no need to fill the current buffer.
+ i2s_sr.dma.rw_pos = DMA_SAMPLE_COUNT; // The buffer is full.
+ break;
+ }
+ continue;
+ }
+ }
+ // no pulse data in push buffer (pulse off or idle or callback is not defined)
+ buf[i2s_sr.dma.rw_pos++] = atomic_load(&i2s_sr.port_data);
+ if (i2s_sr.remain_time_until_next_pulse >= I2S_OUT_USEC_PER_PULSE) {
+ i2s_sr.remain_time_until_next_pulse -= I2S_OUT_USEC_PER_PULSE;
+ } else {
+ i2s_sr.remain_time_until_next_pulse = 0;
+ }
+ }
+ // set filled length to the DMA descriptor
+ dma_desc->dw0.length = i2s_sr.dma.rw_pos * I2S_SAMPLE_SIZE;
+}
+
+//
+// I2S bitstream generator task
+//
+
+static inline void i2s_step_gen (dma_descriptor_t *dma_desc)
+{
+ i2s_sr.dma.current = (uint32_t *)dma_desc->buffer;
+ // It reuses the oldest (just transferred) buffer with the name "current"
+ // and fills the buffer for later DMA.
+
+ I2S_OUT_PULSER_ENTER_CRITICAL(); // Lock pulser status
+
+ if (i2s_sr.pulser_status == STEPPING) {
+ //
+ // Fillout the buffer for pulse
+ //
+ // To avoid buffer overflow, all of the maximum pulse width (normally about 10us)
+ // is adjusted to be in a single buffer.
+ // DMA_SAMPLE_SAFE_COUNT is referred to as the margin value.
+ // Therefore, if a buffer is close to full and it is time to generate a pulse,
+ // the generation of the buffer is interrupted (the buffer length is shortened slightly)
+ // and the pulse generation is postponed until the next buffer is filled.
+ //
+ i2s_fillout_dma_buffer(dma_desc);
+ dma_desc->dw0.length = i2s_sr.dma.rw_pos * I2S_SAMPLE_SIZE;
+ } else if (i2s_sr.pulser_status == WAITING) {
+ if (dma_desc->next == NULL) {
+ // Tail of the DMA descriptor found
+ // I2S TX module has already stopped by ISR
+ //i2s_out_stop();
+ //i2s_clear_o_dma_buffers(0); // 0 for static I2S control mode (right ch. data is always 0)
+ // You need to set the status before calling i2s_out_start()
+ // because the process in i2s_out_start() is different depending on the status.
+ i2s_out_start(PASSTHROUGH);
+ } else {
+ // Processing a buffer slightly ahead of the tail buffer.
+ // We don't need to fill up the buffer by port_data any more.
+ i2s_clear_dma_buffer(dma_desc, 0); // Essentially, no clearing is required. I'll make sure I know when I've written something.
+ i2s_sr.dma.rw_pos = 0; // If someone calls i2s_out_push_sample, make sure there is no buffer overflow
+ dma_desc->next = NULL; // Cut the DMA descriptor ring. This allow us to identify the tail of the buffer.
+ }
+ } else {
+ // Stepper paused (passthrough state, static I2S control mode)
+ // In the passthrough mode, there is no need to fill the buffer with port_data.
+ i2s_clear_dma_buffer(dma_desc, 0); // Essentially, no clearing is required. I'll make sure I know when I've written something.
+ i2s_sr.dma.rw_pos = 0; // If someone calls i2s_out_push_sample, make sure there is no buffer overflow
+ }
+
+ I2S_OUT_PULSER_EXIT_CRITICAL(); // Unlock pulser status
+}
+
+#if I2S_LOCAL_QUEUE
+
+static inline void IRAM_ATTR i2s_poll (void)
+{
+ // Get a DMA complete event from I2S isr
+ if(dma_queue.tail != dma_queue.head) {
+ I2S_OUT_PULSER_ENTER_CRITICAL(); // Lock pulser status
+
+ dma_descriptor_t *dma_desc = dma_queue.descr[dma_queue.tail];
+
+ dma_queue.tail = (dma_queue.tail + 1) & (I2S_LOCAL_QUEUE - 1);
+ I2S_OUT_PULSER_EXIT_CRITICAL(); // Lock pulser status
+
+ i2s_step_gen(dma_desc);
+ }
+}
+
+static void IRAM_ATTR i2s_poll_rt (sys_state_t state)
+{
+ on_execute_realtime(state);
+
+ i2s_poll();
+}
+
+static void IRAM_ATTR i2s_poll_dly (sys_state_t state)
+{
+ on_execute_delay(state);
+
+ i2s_poll();
+}
+
+#else
+
+static void IRAM_ATTR i2sOutTask (void *parameter)
+{
+ dma_descriptor_t *dma_desc;
+
+ while(true) {
+
+ // Wait a DMA complete event from I2S isr
+ // (Blocks until a DMA transfer has completed)
+ xQueueReceive(i2s_sr.dma.queue, &dma_desc, portMAX_DELAY);
+if((uint32_t)dma_desc > 1000)
+ i2s_step_gen(dma_desc);
+ }
+}
+
+#endif
+
+//
+// External funtions
+//
+void IRAM_ATTR i2s_out_delay (void)
+{
+ I2S_OUT_PULSER_ENTER_CRITICAL();
+
+ if (i2s_sr.pulser_status == PASSTHROUGH) {
+ // Depending on the timing, it may not be reflected immediately,
+ // so wait twice as long just in case.
+ ets_delay_us(I2S_OUT_USEC_PER_PULSE * 2);
+ } else {
+ // Just wait until the data now registered in the DMA descripter
+ // is reflected in the I2S TX module via FIFO.
+ delay(I2S_OUT_DELAY_MS);
+ }
+
+ I2S_OUT_PULSER_EXIT_CRITICAL();
+}
+
+void IRAM_ATTR i2s_out_write (uint8_t pin, uint8_t val)
+{
+ if(val)
+ atomic_fetch_or(&i2s_sr.port_data, bit(pin));
+ else
+ atomic_fetch_and(&i2s_sr.port_data, ~bit(pin));
+
+ // It needs a lock for access, but I've given up because I need speed.
+ // This is not a problem as long as there is no overlap between the status change and digitalWrite().
+// if(i2s_sr.pulser_status == PASSTHROUGH)
+// i2s_out_single_data();
+
+ pd = atomic_load(&i2s_sr.port_data);
+}
+
+bool IRAM_ATTR i2s_out_state (uint8_t pin)
+{
+ uint32_t port_data = atomic_load(&i2s_sr.port_data);
+
+ return !!(port_data & bit(pin));
+}
+
+uint32_t IRAM_ATTR i2s_out_push_sample (uint32_t num)
+{
+ if(num > SAMPLE_SAFE_COUNT)
+ return 0;
+
+ uint32_t n = num ? num : 1, port_data = atomic_load(&i2s_sr.port_data);
+
+ // push at least one sample (even if num is zero)
+ do {
+ i2s_sr.dma.current[i2s_sr.dma.rw_pos++] = port_data;
+ } while (--n);
+
+ return num;
+}
+
+i2s_out_pulser_status_t IRAM_ATTR i2s_out_get_pulser_status (void)
+{
+ I2S_OUT_PULSER_ENTER_CRITICAL();
+
+ i2s_out_pulser_status_t s = i2s_sr.pulser_status;
+
+ I2S_OUT_PULSER_EXIT_CRITICAL();
+
+ return s;
+}
+
+void IRAM_ATTR i2s_out_set_passthrough (void)
+{
+ I2S_OUT_PULSER_ENTER_CRITICAL();
+
+ if (i2s_sr.pulser_status == STEPPING) {
+ i2s_sr.pulser_status = WAITING; // Start stopping the pulser
+ delay(I2S_OUT_DELAY_MS);
+ }
+
+ I2S_OUT_PULSER_EXIT_CRITICAL();
+}
+
+void IRAM_ATTR i2s_out_set_stepping (void)
+{
+ I2S_OUT_PULSER_ENTER_CRITICAL();
+
+ if (i2s_sr.pulser_status == STEPPING) {
+ // Re-entered (fail safe)
+ I2S_OUT_PULSER_EXIT_CRITICAL();
+ return;
+ }
+
+ if(i2s_sr.pulser_status == PASSTHROUGH)
+ gdma_ll_tx_stop(&GDMA, i2s_sr.dma.channel);
+
+ // Wait for complete DMAs
+ while(i2s_sr.pulser_status == WAITING) {
+ I2S_OUT_PULSER_EXIT_CRITICAL();
+ delay(I2S_OUT_DELAY_DMABUF_MS);
+ I2S_OUT_PULSER_ENTER_CRITICAL();
+ }
+
+ // Change I2S to STEPPING
+ i2s_out_start(STEPPING);
+
+ I2S_OUT_PULSER_EXIT_CRITICAL();
+}
+
+void IRAM_ATTR i2s_out_set_pulse_period (uint32_t period)
+{
+ i2s_sr.pulse_period = period;
+}
+
+void IRAM_ATTR i2s_out_set_pulse_callback (i2s_out_pulse_func_t func)
+{
+ i2s_sr.pulse_func = func;
+}
+
+void IRAM_ATTR i2s_out_reset (void)
+{
+ I2S_OUT_PULSER_ENTER_CRITICAL();
+
+ if (i2s_sr.pulser_status == STEPPING) {
+ uint32_t port_data = atomic_load(&i2s_sr.port_data);
+ i2s_clear_o_dma_buffers(port_data);
+ }
+
+ // You need to set the status before calling i2s_out_start()
+ // because the process in i2s_out_start() is different depending on the status.
+ i2s_out_start(i2s_sr.pulser_status == WAITING ? PASSTHROUGH : i2s_sr.pulser_status);
+
+ I2S_OUT_PULSER_EXIT_CRITICAL();
+}
+
+// Hack, to be replaced with framework call?
+static int32_t allocate_dma_channel (void)
+{
+ uint32_t ch = SOC_GDMA_PAIRS_PER_GROUP;
+
+ do {
+ if(GDMA.channel[--ch].out.link.addr == 0)
+ return ch;
+ } while(ch);
+
+ return -1;
+}
+
+//
+// Initialize funtion (external function)
+//
+bool IRAM_ATTR i2s_out_init2 (i2s_out_init_t init_param)
+{
+ if(i2s_sr.initialized)
+ return false;
+
+ if((i2s_sr.dma.channel = allocate_dma_channel()) == -1)
+ return false;
+
+ atomic_store(&i2s_sr.port_data, init_param.init_val);
+
+ // To make sure hardware is enabled before any hardware register operations.
+ periph_module_reset(PERIPH_I2S0_MODULE);
+ periph_module_enable(PERIPH_I2S0_MODULE);
+// periph_module_reset(PERIPH_GDMA_MODULE);
+// periph_module_enable(PERIPH_GDMA_MODULE);
+
+ if (REG_GET_BIT(SYSTEM_PERIP_CLK_EN1_REG, SYSTEM_DMA_CLK_EN) == 0) {
+ REG_CLR_BIT(SYSTEM_PERIP_CLK_EN1_REG, SYSTEM_DMA_CLK_EN);
+ REG_SET_BIT(SYSTEM_PERIP_CLK_EN1_REG, SYSTEM_DMA_CLK_EN);
+ REG_SET_BIT(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST);
+ REG_CLR_BIT(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST);
+ }
+
+ // Route the i2s pins to the appropriate GPIO
+ i2s_out_gpio_attach(init_param.ws_pin, init_param.bck_pin, init_param.data_pin);
+
+ /**
+ * Each i2s transfer will take
+ * fpll = PLL_D2_CLK -- clka_en = 0
+ *
+ * fi2s = fpll / N + b/a -- N + b/a = clkm_div_num
+ * fi2s = 160MHz / 2
+ * fi2s = 80MHz
+ *
+ * fbclk = fi2s / M -- M = tx_bck_div_num
+ * fbclk = 80MHz / 2
+ * fbclk = 40MHz
+ *
+ * fwclk = fbclk / 32
+ *
+ * for fwclk = 250kHz(16-bit: 4uS pulse time), 125kHz(32-bit: 8uS pulse time)
+ * N = 10, b/a = 0
+ * M = 2
+ * for fwclk = 500kHz(16-bit: 2uS pulse time), 250kHz(32-bit: 4uS pulse time)
+ * N = 5, b/a = 0
+ * M = 2
+ * for fwclk = 1000kHz(16-bit: 1uS pulse time), 500kHz(32-bit: 2uS pulse time)
+ * N = 2, b/a = 2/1 (N + b/a = 2.5)
+ * M = 2
+ */
+
+ // Allocate the array of pointers to the buffers
+ if((i2s_sr.dma.buffers = (uint32_t **)malloc(sizeof(uint32_t *) * I2S_OUT_DMABUF_COUNT)) == NULL)
+ return false;
+
+ // Allocate each buffer that can be used by the DMA controller
+ for(int i = 0; i < I2S_OUT_DMABUF_COUNT; i++) {
+ if((i2s_sr.dma.buffers[i] = (uint32_t *)heap_caps_calloc(1, I2S_OUT_DMABUF_LEN, MALLOC_CAP_DMA)) == NULL)
+ return false;
+ }
+
+ // Allocate the array of DMA descriptors
+ if((i2s_sr.dma.desc = (dma_descriptor_t **)malloc(sizeof(dma_descriptor_t *) * I2S_OUT_DMABUF_COUNT)) == NULL)
+ return false;
+
+ // Allocate each DMA descriptor that will be used by the DMA controller
+ for(int i = 0; i < I2S_OUT_DMABUF_COUNT; i++) {
+ if((i2s_sr.dma.desc[i] = (dma_descriptor_t *)heap_caps_malloc(sizeof(dma_descriptor_t), MALLOC_CAP_DMA)) == NULL)
+ return false;
+ }
+
+ // Initialize
+ i2s_clear_o_dma_buffers(init_param.init_val);
+ i2s_sr.dma.rw_pos = 0;
+ i2s_sr.dma.current = NULL;
+#if !I2S_LOCAL_QUEUE
+ i2s_sr.dma.queue = xQueueCreate(I2S_OUT_DMABUF_COUNT, sizeof(uint32_t *));
+#endif
+
+ i2s_ll_tx_stop(&I2S0);
+
+// gdma_ahb_hal_connect_peri(&GDMA, i2s_sr.dma.channel, GDMA_CHANNEL_DIRECTION_TX, GDMA_TRIG_PERIPH_I2S, SOC_GDMA_TRIG_PERIPH_I2S0);
+
+ gdma_ll_enable_clock(&GDMA, 1);
+ gdma_ll_tx_reset_channel(&GDMA, i2s_sr.dma.channel);
+ gdma_ll_tx_enable_interrupt(&GDMA, i2s_sr.dma.channel, GDMA_LL_TX_EVENT_MASK, false);
+ gdma_ll_tx_clear_interrupt_status(&GDMA, i2s_sr.dma.channel, GDMA_LL_TX_EVENT_MASK);
+ gdma_ll_tx_connect_to_periph(&GDMA, i2s_sr.dma.channel, GDMA_TRIG_PERIPH_I2S, SOC_GDMA_TRIG_PERIPH_I2S0);
+ gdma_ll_tx_set_eof_mode(&GDMA, i2s_sr.dma.channel, 0); // Not needed?
+
+#if I2S_OUT_NUM_BITS == 16
+ I2S0.fifo_conf.tx_fifo_mod = 0; // 0: 16-bit dual channel data, 3: 32-bit single channel data
+ I2S0.fifo_conf.rx_fifo_mod = 0; // 0: 16-bit dual channel data, 3: 32-bit single channel data
+ I2S0.sample_rate_conf.tx_bits_mod = 16; // default is 16-bits
+ I2S0.sample_rate_conf.rx_bits_mod = 16; // default is 16-bits
+
+#else
+ i2s_ll_tx_enable_pdm(&I2S0, false); // Enables TDM
+ i2s_ll_rx_set_active_chan_mask(&I2S0, 1);
+ i2s_ll_tx_enable_msb_shift(&I2S0, 1);
+ i2s_ll_tx_set_sample_bit(&I2S0, 32, 32); // ?
+ i2s_ll_tx_set_ws_width(&I2S0, 1);
+#endif
+
+ //
+ // i2s_set_clk
+ //
+ i2s_ll_tx_set_ws_idle_pol(&I2S0, 0);
+ i2s_ll_tx_clk_set_src(&I2S0, I2S_CLK_D2CLK); // Set I2S_CLK_D2CLK as default
+ i2s_ll_mclk_use_tx_clk(&I2S0);
+
+#if I2S_OUT_NUM_BITS == 16
+ // N = 10
+ //! I2S0.clkm_conf.clkm_div_num = 10; // minimum value of 2, reset value of 4, max 256 (I²S clock divider’s integral value)
+#else
+ // N = 5
+ //! I2S0.clkm_conf.clkm_div_num = 5; // minimum value of 2, reset value of 4, max 256 (I²S clock divider’s integral value)
+ i2s_ll_mclk_div_t clk_ = {
+ .mclk_div = 2,
+ .a = 20,
+ .b = 17
+ };
+#endif
+
+ i2s_ll_tx_set_clk(&I2S0, &clk_);
+ i2s_ll_tx_enable_clock(&I2S0);
+ i2s_ll_tx_reset(&I2S0);
+ i2s_ll_tx_reset_fifo(&I2S0);
+ I2S0.tx_conf.tx_stop_en = 1;
+
+#if I2S_LOCAL_QUEUE
+
+ on_execute_realtime = grbl.on_execute_realtime;
+ grbl.on_execute_realtime = i2s_poll_rt;
+
+// on_execute_delay = grbl.on_execute_delay;
+// grbl.on_execute_delay = i2s_poll_dly;
+
+#else
+ // Create the task that will feed the buffer
+ xTaskCreatePinnedToCore(i2sOutTask,
+ "I2SOutTask",
+ 4096,
+ NULL,
+ GRBLHAL_TASK_PRIORITY + 1,
+ NULL,
+ GRBLHAL_TASK_CORE // must run the task on same core
+ );
+
+#endif
+
+ esp_err_t ret;
+
+ // Allocate and enable the I2S DMA interrupt
+
+ ret = esp_intr_alloc(gdma_periph_signals.groups[0].pairs[i2s_sr.dma.channel].tx_irq_id, /*ESP_INTR_FLAG_IRAM|ESP_INTR_FLAG_INTRDISABLED*/0, i2s_out_intr_handler, NULL, &i2s_sr.dma.intr_handle);
+/* esp_intr_alloc_intrstatus(gdma_periph_signals.groups[0].pairs[i2s_sr.dma.channel].tx_irq_id, ESP_INTR_FLAG_INTRDISABLED,
+ (uint32_t)gdma_ll_tx_get_interrupt_status_reg(&GDMA, i2s_sr.dma.channel), GDMA_LL_TX_EVENT_MASK,
+ i2s_out_intr_handler, NULL, &i2s_sr.dma.intr_handle);*/
+// esp_intr_enable(i2s_sr.dma.intr_handle);
+
+ // Default pulse callback period (usec)
+ i2s_sr.pulse_period = init_param.pulse_period;
+ i2s_sr.pulse_func = init_param.pulse_func;
+
+ // Remember GPIO pin numbers
+ i2s_sr.ws_pin = init_param.ws_pin;
+ i2s_sr.bck_pin = init_param.bck_pin;
+ i2s_sr.data_pin = init_param.data_pin;
+ i2s_sr.initialized = true;
+
+ // Transmit recovery data to 74HC595
+ i2s_out_gpio_shiftout((pd = init_param.init_val));
+
+ // Start the I2S peripheral
+ debug_writeln("hi");
+ return i2s_out_start(PASSTHROUGH);
+}
+
+/*
+ Initialize I2S out by default parameters.
+
+ return false ... already initialized
+*/
+bool IRAM_ATTR i2s_out_init (void)
+{
+ i2s_out_init_t default_param = {
+ .ws_pin = I2S_OUT_WS,
+ .bck_pin = I2S_OUT_BCK,
+ .data_pin = I2S_OUT_DATA,
+ .pulse_func = NULL,
+ .pulse_period = I2S_OUT_USEC_PER_PULSE,
+ .init_val = I2S_OUT_INIT_VAL
+ };
+
+ return i2s_out_init2(default_param);
+}
+
+#endif
diff --git a/main/ioports.c b/main/ioports.c
index 738a260..d7a93a0 100644
--- a/main/ioports.c
+++ b/main/ioports.c
@@ -3,7 +3,7 @@
Part of grblHAL
- Copyright (c) 2020-2023 Terje Io
+ Copyright (c) 2020-2024 Terje Io
Grbl is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@@ -105,7 +105,7 @@ inline static __attribute__((always_inline)) int32_t get_input (const input_sign
return value;
}
-static int32_t wait_on_input (io_port_type_t type, uint8_t port, wait_mode_t wait_mode, float timeout)
+IRAM_ATTR static int32_t wait_on_input (io_port_type_t type, uint8_t port, wait_mode_t wait_mode, float timeout)
{
int32_t value = -1;
@@ -117,18 +117,18 @@ static int32_t wait_on_input (io_port_type_t type, uint8_t port, wait_mode_t wai
return value;
}
-void ioports_event (input_signal_t *input)
+IRAM_ATTR void ioports_event (input_signal_t *input)
{
spin_lock = true;
event_port = input;
if(input->interrupt_callback) {
- uint_fast8_t idx = digital.in.n_ports;
+ uint_fast8_t port = digital.in.n_ports;
do {
- idx--;
- if(input == &aux_in[idx])
- input->interrupt_callback(ioports_map_reverse(&digital.in, idx), DIGITAL_IN(input->pin));
- } while(idx);
+ port--;
+ if(input == &aux_in[port])
+ input->interrupt_callback(ioports_map_reverse(&digital.in, port), DIGITAL_IN(input->pin));
+ } while(port);
}
spin_lock = false;
@@ -293,30 +293,85 @@ bool swap_pins (io_port_type_t type, io_port_direction_t dir, uint8_t port_a, ui
static void on_setting_changed (setting_id_t id)
{
- if(id == Settings_IoPort_InvertOut && invert_digital_out.mask != settings.ioport.invert_out.mask) {
+ bool write = false;
+ uint_fast8_t port;
- uint_fast8_t port = digital.out.n_ports;
- do {
- port--;
- if(((settings.ioport.invert_out.mask >> port) & 0x01) != ((invert_digital_out.mask >> port) & 0x01))
- gpio_set_level(aux_out[port].pin, !gpio_get_level(aux_out[port].pin));
- } while(port);
+ switch(id) {
- invert_digital_out = settings.ioport.invert_out;
+ case Settings_IoPort_InvertIn:
+ port = digital.in.n_ports;
+ do {
+ if(aux_in[--port].aux_ctrl) {
+ write = true;
+ if(settings.ioport.invert_in.mask & (1 << port))
+ settings.control_invert.mask |= aux_in[port].aux_ctrl->cap.mask;
+ else
+ settings.control_invert.mask &= ~aux_in[port].aux_ctrl->cap.mask;
+ }
+ } while(port);
+ break;
+
+ case Settings_IoPort_InvertOut:
+ if(invert_digital_out.mask != settings.ioport.invert_out.mask) {
+ port = digital.out.n_ports;
+ do {
+ port--;
+ if(((settings.ioport.invert_out.mask >> port) & 0x01) != ((invert_digital_out.mask >> port) & 0x01))
+ gpio_set_level(aux_out[port].pin, !gpio_get_level(aux_out[port].pin));
+ } while(port);
+
+ invert_digital_out = settings.ioport.invert_out;
+ }
+ break;
+
+ case Setting_ControlInvertMask:
+ port = digital.in.n_ports;
+ do {
+ if(aux_in[--port].aux_ctrl) {
+ write = true;
+ if(settings.control_invert.mask & aux_in[port].aux_ctrl->cap.mask)
+ settings.ioport.invert_in.mask |= (1 << port);
+ else
+ settings.ioport.invert_in.mask &= ~(1 << port);
+ }
+ } while(port);
+ break;
+
+ default:
+ break;
}
+
+ if(write)
+ settings_write_global();
}
static void on_settings_loaded (void)
{
-// aux_set_pullup();
- uint_fast8_t idx = digital.out.n_ports;
+ bool write = false;
+ uint_fast8_t port = digital.out.n_ports;
invert_digital_out = settings.ioport.invert_out;
if(digital.out.n_ports) do {
- idx--;
- gpio_set_level(aux_out[idx].pin, (settings.ioport.invert_out.mask >> idx) & 0x01);
- } while(idx);
+ port--;
+ gpio_set_level(aux_out[port].pin, (settings.ioport.invert_out.mask >> port) & 0x01);
+ } while(port);
+
+ port = digital.in.n_ports;
+ do {
+ if(aux_in[--port].aux_ctrl &&
+ !!(settings.control_invert.mask & aux_in[port].aux_ctrl->cap.mask) !=
+ !!(settings.ioport.invert_in.mask & (1 << port))) {
+ write = true;
+ if(settings.control_invert.mask & aux_in[port].aux_ctrl->cap.mask)
+ settings.ioport.invert_in.mask |= (1 << port);
+ else
+ settings.ioport.invert_in.mask &= ~(1 << port);
+ }
+ } while(port);
+
+ if(write)
+ settings_write_global();
}
void ioports_init (pin_group_pins_t *aux_inputs, pin_group_pins_t *aux_outputs)
diff --git a/main/my_machine.h b/main/my_machine.h
index 12f1ee7..20c2af7 100644
--- a/main/my_machine.h
+++ b/main/my_machine.h
@@ -1,11 +1,9 @@
/*
- my_machine.h - configuration for ESP32 processos
-
- NOTE: only in use if not compiling with cmake (idf.py)
+ my_machine.h - configuration for ESP32 processors
Part of grblHAL
- Copyright (c) 2020-2023 Terje Io
+ Copyright (c) 2020-2024 Terje Io
Grbl is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@@ -23,61 +21,124 @@
// NOTE: Only one board may be enabled!
// If none is enabled pin mappings from generic_map.h will be used
-//#define BOARD_ESPDUINO32
-//#define BOARD_BDRING_V3P5
-//#define BOARD_BDRING_V4
-//#define BOARD_BDRING_I2S6A // NOT production ready!
-//#define BOARD_SOURCERABBIT_4AXIS
-//#define BOARD_PROTONEER_3XX
-//#define BOARD_MKS_DLC32_V2P0 // MKS DLC32 and MKS TinyBee boards
-//#define BOARD_MY_MACHINE // Add my_machine_map.h before enabling this!
+//#define BOARD_BDRING_V3P5 //
+//#define BOARD_BDRING_V4 //
+//#define BOARD_BDRING_I2S6A //
+//#define BOARD_ESPDUINO32 //
+//#define BOARD_SOURCERABBIT_4AXIS //
+//#define BOARD_PROTONEER_3XX //
+//#define BOARD_FYSETC_E4 //
+//#define BOARD_XPRO_V5 //
+//#define BOARD_MKS_DLC32_V2P0 //
+//#define BOARD_MKS_TINYBEE_V1 //
+//#define BOARD_CNC3040 //
+//#define BOARD_BLACKBOX_X32 // NOTE: Enable in CMakeLists.txt to set board specific defaults for the core!
+//#define BOARD_ROOTCNC_V2 //
+//#define BOARD_ROOTCNC_V3 //
+//#define BOARD_CNC_BOOSTERPACK //
+//#define BOARD_MY_MACHINE // Add my_machine_map.h in the boards directory before enabling this!
// Configuration
// Uncomment to enable, for some a value > 1 may be assigned, if so the default value is shown.
-//#define VFD_ENABLE 1 // Set to 1 or 2 for Huanyang VFD spindle. More here https://github.com/grblHAL/Plugins_spindle
-//#define NETWORKING_ENABLE 1 // WiFi streaming. Requires networking plugin.
-#if NETWORKING_ENABLE
-//#define WIFI_SOFTAP 1 // Use Soft AP mode for WiFi.
-//#define WEBUI_ENABLE 0 // Not yet available, do not change.
+#if GRBL_ESP32S3
+#define USB_SERIAL_CDC 1 // Serial communication via native USB.
#endif
-//#define SDCARD_ENABLE 1 // Run gcode programs from SD card, requires sdcard plugin.
-//#define BLUETOOTH_ENABLE 1 // Enable Bluetooth streaming.
-//#define MPG_MODE_ENABLE 1 // Enable MPG mode (secondary serial port)
-//#define NOPROBE 1 // Comment out to disable probe input.
-//#define EEPROM_ENABLE 1 // I2C EEPROM support. Set to 1 for 24LC16 (2K), 3 for 24C32 (4K - 32 byte page) and 2 for other sizes. Uses eeprom plugin.
-//#define EEPROM_IS_FRAM 1 // Uncomment when EEPROM is enabled and chip is FRAM, this to remove write delay.
+// Spindle selection:
+// Up to four specific spindle drivers can be instantiated at a time
+// depending on N_SPINDLE and N_SYS_SPINDLE definitions in grbl/config.h.
+// If none are specified the default PWM spindle is instantiated.
+// Spindle definitions can be found in grbl/spindle_control.h.
+// More here https://github.com/grblHAL/Plugins_spindle
+//#define SPINDLE0_ENABLE SPINDLE_HUANYANG1
+//#define SPINDLE0_ENABLE SPINDLE_PWM0_NODIR
+//#define SPINDLE2_ENABLE SPINDLE_NONE
+//#define SPINDLE3_ENABLE SPINDLE_NONE
+// **********************
+//#define MODBUS_ENABLE 1 // Set to 1 for auto direction, 2 for direction signal on auxillary output pin.
+//#define WEBUI_ENABLE 3 // Enable ESP3D-WEBUI plugin along with networking and SD card plugins.
+//#define WEBUI_AUTH_ENABLE 1 // Enable ESP3D-WEBUI authentication.
+//#define WEBUI_INFLASH 1 // Store WebUI files in flash instead of on SD card.
+//#define WIFI_ENABLE 1 //
+//#define WIFI_SOFTAP 1 // Use Soft AP mode for WiFi.
+//#define ETHERNET_ENABLE 1 // Ethernet streaming. Uses networking plugin.
+//#define BLUETOOTH_ENABLE 1 // Set to 1 for native radio, 2 for HC-05 module.
+//#define SDCARD_ENABLE 2 // Run gcode programs from SD card. Set to 2 to enable YModem upload.
+//#define KEYPAD_ENABLE 1 // I2C keypad for jogging etc., uses keypad plugin.
+//#define PPI_ENABLE 1 // Laser PPI plugin. To be completed.
+//#define LASER_COOLANT_ENABLE 1 // Laser coolant plugin. To be completed.
+//#define LB_CLUSTERS_ENABLE 1 // LaserBurn cluster support.
+//#define FANS_ENABLE 1 // Enable fan control via M106/M107. Enables fans plugin.
+//#define EMBROIDERY_ENABLE 1 // Embroidery plugin. To be completed.
+//#define TRINAMIC_ENABLE 2130 // Trinamic TMC2130 stepper driver support. NOTE: work in progress.
+//#define TRINAMIC_ENABLE 5160 // Trinamic TMC5160 stepper driver support. NOTE: work in progress.
+//#define TRINAMIC_I2C 1 // Trinamic I2C - SPI bridge interface.
+//#define TRINAMIC_DEV 1 // Development mode, adds a few M-codes to aid debugging. Do not enable in production code.
+//#define EEPROM_ENABLE 16 // I2C EEPROM/FRAM support. Set to 16 for 2K, 32 for 4K, 64 for 8K, 128 for 16K and 256 for 16K capacity.
+//#define EEPROM_IS_FRAM 1 // Uncomment when EEPROM is enabled and chip is FRAM, this to remove write delay.
+#define ESTOP_ENABLE 0 // When enabled only real-time report requests will be executed when the reset pin is asserted.
+ // NOTE: if left commented out the default setting is determined from COMPATIBILITY_LEVEL.
+//#define PROBE_ENABLE 0 // Uncomment to disable probe input.
+
+// Optional control signals:
+// These will be assigned to aux input pins. Use the $pins command to check which pins are assigned.
+// NOTE: If not enough pins are available assignment will silently fail.
+//#define SAFETY_DOOR_ENABLE 1
+//#define MOTOR_FAULT_ENABLE 1
+//#define MOTOR_WARNING_ENABLE 1
+//#define PROBE_DISCONNECT_ENABLE 1
+//#define STOP_DISABLE_ENABLE 1
+//#define BLOCK_DELETE_ENABLE 1
+//#define SINGLE_BLOCK_ENABLE 1
+//#define LIMITS_OVERRIDE_ENABLE 1
-#if NETWORKING_ENABLE
-#define NETWORK_PARAMETERS_OK 1
-#define WEBSOCKET_ENABLE 1 // Websocket daemon - requires networking enabled.
-#define TELNET_ENABLE 1 // Telnet daemon - requires networking enabled.
-//#define WIFI_SOFTAP 1 // Use Soft AP mode for WiFi.
-//#define WEBUI_ENABLE 0 // Not yet available, do not change.
-#ifdef SDCARD_ENABLE
-//#define FTP_ENABLE 1 // Ftp daemon - requires SD card enabled.
+// If the selected board map supports more than three motors ganging and/or auto-squaring
+// of axes can be enabled here.
+//#define X_GANGED 1
+//#define X_AUTO_SQUARE 1
+//#define Y_GANGED 1
+//#define Y_AUTO_SQUARE 1
+//#define Z_GANGED 1
+//#define Z_AUTO_SQUARE 1
+// For ganged axes the limit switch input (if available) can be configured to act as a max travel limit switch.
+// NOTE: If board map already has max limit inputs defined this configuration will be ignored.
+//#define X_GANGED_LIM_MAX 1
+//#define Y_GANGED_LIM_MAX 1
+//#define Z_GANGED_LIM_MAX 1
+//
+
+#if WIFI_ENABLE || ETHERNET_ENABLE || WEBUI_ENABLE
+#define TELNET_ENABLE 1 // Telnet daemon - requires WiFi streaming enabled.
+#define WEBSOCKET_ENABLE 1 // Websocket daemon - requires WiFi streaming enabled.
+//#define MDNS_ENABLE 0 // mDNS daemon. Do NOT enable here, enable in CMakeLists.txt!
+//#define SSDP_ENABLE 1 // SSDP daemon - requires HTTP enabled.
+//#define MQTT_ENABLE 1 // MQTT client API, only enable if needed by plugin code.
+#if SDCARD_ENABLE || WEBUI_ENABLE
+//#define FTP_ENABLE 1 // Ftp daemon - requires SD card enabled.
+//#define HTTP_ENABLE 1 // http daemon - requires SD card enabled.
+//#define WEBDAV_ENABLE 1 // webdav protocol - requires http daemon and SD card enabled.
+#endif
+// The following symbols have the default values as shown, uncomment and change as needed.
+//#define NETWORK_STA_HOSTNAME "grblHAL"
+//#define NETWORK_STA_IPMODE 1 // 0 = static, 1 = DHCP, 2 = AutoIP
+//#define NETWORK_STA_IP "192.168.5.1"
+//#define NETWORK_STA_GATEWAY "192.168.5.1"
+//#define NETWORK_STA_MASK "255.255.255.0"
+#if WIFI_SOFTAP > 0
+//#define NETWORK_AP_SSID "grblHAL_AP"
+//#define NETWORK_AP_PASSWORD "grblHALap"
+//#define NETWORK_AP_HOSTNAME "grblHAL_AP"
+//#define NETWORK_AP_IPMODE 0 // Do not change!
+//#define NETWORK_AP_IP "192.168.4.1" // Do not change!
+//#define NETWORK_AP_GATEWAY "192.168.4.1" // Do not change!
+//#define NETWORK_AP_MASK "255.255.255.0"
#endif
-//#define NETWORK_HOSTNAME "grblHAL"
-//#define NETWORK_IPMODE 1 // 0 = static, 1 = DHCP, 2 = AutoIP
-//#define NETWORK_IP "192.168.5.1"
-//#define NETWORK_GATEWAY "192.168.5.1"
-//#define NETWORK_MASK "255.255.255.0"
-//#define NETWORK_TELNET_PORT 23
+//#define NETWORK_FTP_PORT 21
+//#define NETWORK_TELNET_PORT 23
+//#define NETWORK_HTTP_PORT 80
+#if HTTP_ENABLE
//#define NETWORK_WEBSOCKET_PORT 81
-//#define NETWORK_HTTP_PORT 80
-
-// WiFi Access Point (AP) settings
-#if WIFI_SOFTAP
-#define NETWORK_AP_HOSTNAME "grblHAL_AP"
-#define NETWORK_AP_IP "192.168.5.1"
-#define NETWORK_AP_GATEWAY "192.168.5.1"
-#define NETWORK_AP_MASK "255.255.255.0"
-#define NETWORK_AP_SSID "grblHAL"
-#define NETWORK_AP_PASSWORD "GrblPassword" // Minimum 8 characters, or blank for open
-#define WIFI_MODE WiFiMode_AP; // OPTION: WiFiMode_APSTA
#else
-#define WIFI_SOFTAP 0
-#define WIFI_MODE WiFiMode_STA; // Do not change!
-#endif
-
+//#define NETWORK_WEBSOCKET_PORT 80
#endif
+#endif // WIFI_ENABLE
diff --git a/main/spi.c b/main/spi.c
index 625440d..b075727 100644
--- a/main/spi.c
+++ b/main/spi.c
@@ -3,7 +3,7 @@
Part of grblHAL driver for ESP32
- Copyright (c) 2020-2021 Terje Io
+ Copyright (c) 2020-2024 Terje Io
Grbl is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@@ -21,6 +21,8 @@
#include "driver.h"
+#if SPI_ENABLE
+
#include "driver/sdspi_host.h"
#include "driver/spi_master.h"
@@ -131,3 +133,6 @@ uint8_t spi_put_byte (uint8_t byte)
return spi_device_polling_transmit(handle, &t) == ESP_OK ? 0 : 0xFF;
}
+
+#endif
+
diff --git a/main/trinamic_if.c b/main/trinamic_if.c
index e5a47f2..834548b 100644
--- a/main/trinamic_if.c
+++ b/main/trinamic_if.c
@@ -3,7 +3,7 @@
Part of grblHAL
- Copyright (c) 2020-2022 Terje Io
+ Copyright (c) 2020-2024 Terje Io
Grbl is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@@ -21,7 +21,7 @@
#include "driver.h"
-#if defined(BOARD_XPRO_V5) // || defined(BOARD_CNC_BOOSTERPACK)
+#if defined(BOARD_XPRO_V5)|| defined(BOARD_BLOX) // || defined(BOARD_CNC_BOOSTERPACK)
#include
#include
@@ -160,8 +160,6 @@ static void if_init (uint8_t motors, axes_signals_t axisflags)
#if TRINAMIC_UART_ENABLE
-#include "esp32-hal-uart.h"
-
static io_stream_t tmc_uart = {0};
TMC_uart_write_datagram_t *tmc_uart_read (trinamic_motor_t driver, TMC_uart_read_datagram_t *dgr)
@@ -261,10 +259,13 @@ void board_init (void)
trinamic_if_init(&driver_if);
#endif
- const io_stream_t *uart = serial2Init(230400);
+ const io_stream_t *stream;
+
+ if((stream = stream_open_instance(TRINAMIC_STREAM, 230400, NULL)) == NULL)
+ stream = stream_null_init(230400);
- if(uart) {
- memcpy(&tmc_uart, uart, sizeof(io_stream_t));
+ if(stream) {
+ memcpy(&tmc_uart, stream, sizeof(io_stream_t));
tmc_uart.disable_rx(true);
tmc_uart.set_enqueue_rt_handler(stream_buffer_all);
} // else output POS failure?
diff --git a/main/uart_serial.c b/main/uart_serial.c
index 9dc1182..92e3b7b 100644
--- a/main/uart_serial.c
+++ b/main/uart_serial.c
@@ -4,7 +4,7 @@
Part of grblHAL
- Copyright (c) 2023 Terje Io
+ Copyright (c) 2023-2024 Terje Io
Grbl is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@@ -112,6 +112,13 @@ static enqueue_realtime_command_ptr enqueue_realtime_command2 = protocol_enqueue
static const io_stream_t *serial2Init (uint32_t baud_rate);
#endif
+#if SERIAL3_ENABLE
+static uart_t uart3;
+static stream_rx_buffer_t rxbuffer3 = {0};
+static enqueue_realtime_command_ptr enqueue_realtime_command3 = protocol_enqueue_realtime_command;
+static const io_stream_t *serial3Init (uint32_t baud_rate);
+#endif
+
static io_stream_properties_t serial[] = {
{
.type = StreamType_Serial,
@@ -139,6 +146,22 @@ static io_stream_properties_t serial[] = {
.claim = serial2Init
}
#endif // SERIAL2_ENABLE
+#if SERIAL3_ENABLE
+ {
+ .type = StreamType_Serial,
+ .instance = 2,
+ .flags.claimable = On,
+ .flags.claimed = Off,
+ .flags.connected = On,
+ .flags.can_set_baud = On,
+ #ifdef UART3_TX_PIN
+ .flags.modbus_ready = On,
+ #else
+ .flags.rx_only = On,
+ #endif
+ .claim = serial3Init
+ }
+#endif // SERIAL3_ENABLE
};
void serialRegisterStreams (void)
@@ -201,6 +224,32 @@ void serialRegisterStreams (void)
#endif // SERIAL2_ENABLE
+#if SERIAL3_ENABLE
+
+ #ifdef UART3_TX_PIN
+ static const periph_pin_t tx2 = {
+ .function = Output_TX,
+ .group = PinGroup_UART3,
+ .pin = UART3_TX_PIN,
+ .mode = { .mask = PINMODE_OUTPUT },
+ .description = "Tertiary UART"
+ };
+
+ hal.periph_port.register_pin(&tx2);
+ #endif
+
+ static const periph_pin_t rx2 = {
+ .function = Input_RX,
+ .group = PinGroup_UART3,
+ .pin = UART3_RX_PIN,
+ .mode = { .mask = PINMODE_NONE },
+ .description = "Tertiary UART"
+ };
+
+ hal.periph_port.register_pin(&rx2);
+
+#endif // SERIAL3_ENABLE
+
stream_register_streams(&streams);
}
@@ -228,6 +277,10 @@ static void uartConfig (uart_t *uart, uint32_t baud_rate)
uart_ll_set_mode(uart->dev, UART_MODE_UART);
#if GRBL_ESP32S3
+
+ periph_module_reset((periph_module_t)(PERIPH_UART0_MODULE + uart->num));
+ periph_module_enable((periph_module_t)(PERIPH_UART0_MODULE + uart->num));
+
#else
switch(uart->num) {
@@ -258,14 +311,30 @@ static void uartConfig (uart_t *uart, uint32_t baud_rate)
// Note: UART0 pin mappings are set at boot, no need to set here unless override is required
-#if SERIAL2_ENABLE
- if(uart->num == 1)
+#if SERIAL2_ENABLE || SERIAL3_ENABLE
+
+ switch(uart->num) {
+
+ #if SERIAL2_ENABLE
+ case 1:
#ifdef UART2_TX_PIN
- uart_set_pin(uart->num, UART2_TX_PIN, UART2_RX_PIN, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE);
+ uart_set_pin(uart->num, UART2_TX_PIN, UART2_RX_PIN, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE);
#else
- uart_set_pin(uart->num, UART_PIN_NO_CHANGE, UART2_RX_PIN, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE);
+ uart_set_pin(uart->num, UART_PIN_NO_CHANGE, UART2_RX_PIN, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE);
#endif
-#endif
+ break;
+ #endif
+ #if SERIAL3_ENABLE
+ case 2:
+ #ifdef UART3_TX_PIN
+ uart_set_pin(uart->num, UART3_TX_PIN, UART3_RX_PIN, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE);
+ #else
+ uart_set_pin(uart->num, UART_PIN_NO_CHANGE, UART3_RX_PIN, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE);
+ #endif
+ break;
+ #endif
+}
+#endif // SERIAL2_ENABLE || SERIAL3_ENABLE
UART_MUTEX_UNLOCK(uart);
}
@@ -772,3 +841,237 @@ static const io_stream_t *serial2Init (uint32_t baud_rate)
}
#endif // SERIAL2_ENABLE
+
+#if SERIAL3_ENABLE
+
+static void IRAM_ATTR _uart3_isr (void *arg)
+{
+ uint32_t c, cnt = uart_ll_get_rxfifo_len(uart3.dev), iflags = uart_ll_get_intsts_mask(uart3.dev);
+
+ uart_ll_clr_intsts_mask(uart3.dev, iflags);
+
+ if(iflags & UART_INTR_RXFIFO_OVF)
+ rxbuffer3.overflow = On;
+
+ while(cnt) {
+
+ cnt--;
+ c = _uart_ll_read_rxfifo(uart3.dev);
+
+ if(!enqueue_realtime_command3(c)) {
+
+ uint32_t bptr = (rxbuffer3.head + 1) & RX_BUFFER_SIZE_MASK; // Get next head pointer
+
+ if(bptr == rxbuffer3.tail) // If buffer full
+ rxbuffer3.overflow = On; // flag overflow,
+ else {
+ rxbuffer3.data[rxbuffer3.head] = (char)c; // else add data to buffer
+ rxbuffer3.head = bptr; // and update pointer
+ }
+ }
+ }
+}
+
+uint16_t static serial3Available (void)
+{
+ uint16_t head = rxbuffer3.head, tail = rxbuffer3.tail;
+
+ return BUFCOUNT(head, tail, RX_BUFFER_SIZE);
+}
+
+uint16_t static serial3TxCount (void)
+{
+ return uart_ll_is_tx_idle(uart3.dev) ? 0 : (uint16_t)_uart_ll_get_txfifo_count(uart3.dev) + 1;
+}
+
+uint16_t static serial3RXFree (void)
+{
+ uint16_t head = rxbuffer3.head, tail = rxbuffer3.tail;
+
+ return (RX_BUFFER_SIZE - 1) - BUFCOUNT(head, tail, RX_BUFFER_SIZE);
+}
+
+bool static serial3PutC (const char c)
+{
+ UART_MUTEX_LOCK(&uart3);
+ serialPutC(c);
+ while(_uart_ll_get_txfifo_count(uart3.dev) == uart3.tx_len) {
+ if(!hal.stream_blocking_callback())
+ return false;
+ }
+
+ _uart_ll_write_txfifo(uart3.dev, c);
+
+ UART_MUTEX_UNLOCK(&uart3);
+
+ return true;
+}
+
+void static serial3WriteS (const char *data)
+{
+ char c, *ptr = (char *)data;
+
+ while((c = *ptr++) != '\0')
+ serial3PutC(c);
+}
+
+//
+// Writes a number of characters from a buffer to the serial output stream, blocks if buffer full
+//
+void static serial3Write (const char *s, uint16_t length)
+{
+ char *ptr = (char *)s;
+
+ while(length--)
+ serial3PutC(*ptr++);
+}
+
+int16_t static serial3Read (void)
+{
+ UART_MUTEX_LOCK(&uart3);
+
+ int16_t data;
+ uint16_t bptr = rxbuffer3.tail;
+
+ if(bptr == rxbuffer3.head) {
+ UART_MUTEX_UNLOCK(&uart3);
+ return -1; // no data available else EOF
+ }
+
+ data = rxbuffer3.data[bptr++]; // Get next character, increment tmp pointer
+ rxbuffer3.tail = bptr & (RX_BUFFER_SIZE - 1); // and update pointer
+
+ UART_MUTEX_UNLOCK(&uart3);
+
+ return data;
+}
+
+IRAM_ATTR static void serial3Flush (void)
+{
+ UART_MUTEX_LOCK(&uart3);
+
+ _uart_flush(&uart3, false);
+
+ rxbuffer3.tail = rxbuffer3.head;
+ rxbuffer3.overflow = Off;
+
+ UART_MUTEX_UNLOCK(&uart3);
+}
+
+IRAM_ATTR static void serial3TxFlush (void)
+{
+ UART_MUTEX_LOCK(&uart3);
+
+ _uart_flush(&uart3, true);
+
+ UART_MUTEX_UNLOCK(&uart3);
+}
+
+IRAM_ATTR static void serial3Cancel (void)
+{
+ UART_MUTEX_LOCK(&uart3);
+
+ rxbuffer3.data[rxbuffer3.head] = ASCII_CAN;
+ rxbuffer3.tail = rxbuffer3.head;
+ rxbuffer3.head = (rxbuffer3.tail + 1) & (RX_BUFFER_SIZE - 1);
+
+ UART_MUTEX_UNLOCK(&uart3);
+}
+
+static bool serial3SuspendInput (bool suspend)
+{
+ bool ok;
+
+ UART_MUTEX_LOCK(&uart3);
+
+ ok = stream_rx_suspend(&rxbuffer3, suspend);
+
+ UART_MUTEX_UNLOCK(&uart3);
+
+ return ok;
+}
+
+IRAM_ATTR static bool serial3Disable (bool disable)
+{
+ UART_MUTEX_LOCK(&uart3);
+
+ uart_ll_disable_intr_mask(uart3.dev, rx_int_flags);
+
+ if(!disable) {
+ // Clear and enable interrupts
+ _uart_flush(&uart3, false);
+ rxbuffer3.tail = rxbuffer3.head;
+ uart_ll_clr_intsts_mask(uart3.dev, rx_int_flags);
+ uart_ll_ena_intr_mask(uart3.dev, rx_int_flags);
+ }
+
+ UART_MUTEX_UNLOCK(&uart3);
+
+ return true;
+}
+
+static bool serial3SetBaudRate (uint32_t baud_rate)
+{
+ uartSetBaudRate(&uart3, baud_rate);
+
+ return true;
+}
+
+static bool serial3EnqueueRtCommand (char c)
+{
+ return enqueue_realtime_command3(c);
+}
+
+static enqueue_realtime_command_ptr serial3SetRtHandler (enqueue_realtime_command_ptr handler)
+{
+ enqueue_realtime_command_ptr prev = enqueue_realtime_command3;
+
+ if(handler)
+ enqueue_realtime_command3 = handler;
+
+ return prev;
+}
+
+static const io_stream_t *serial3Init (uint32_t baud_rate)
+{
+ static const io_stream_t stream = {
+ .type = StreamType_Serial,
+ .instance = 2,
+ .state.connected = true,
+ .read = serial3Read,
+ .write = serial3WriteS,
+ .write_n = serial3Write,
+ .write_char = serial3PutC,
+ .enqueue_rt_command = serial3EnqueueRtCommand,
+ .get_rx_buffer_free = serial3RXFree,
+ .get_rx_buffer_count = serial3Available,
+ .get_tx_buffer_count = serial3TxCount,
+ .reset_write_buffer = serial3TxFlush,
+ .reset_read_buffer = serial3Flush,
+ .cancel_read_buffer = serial3Cancel,
+ .suspend_read = serial3SuspendInput,
+ .set_baud_rate = serial3SetBaudRate,
+ .disable_rx = serial3Disable,
+ .set_enqueue_rt_handler = serial3SetRtHandler
+ };
+
+ if(serial[2].flags.claimed)
+ return NULL;
+
+ serial[2].flags.claimed = On;
+
+ memcpy(&uart3, &_uart_bus_array[2], sizeof(uart_t)); // use UART 2
+
+ uartConfig(&uart3, baud_rate);
+
+ serial3Flush();
+#ifdef UART3_TX_PIN
+ uartEnableInterrupt(&uart3, _uart3_isr, true);
+#else
+ uartEnableInterrupt(&uart3, _uart3_isr, false);
+#endif
+
+ return &stream;
+}
+
+#endif // SERIAL3_ENABLE
diff --git a/main/usb_serial.c b/main/usb_serial.c
index d4547c3..674aa5a 100644
--- a/main/usb_serial.c
+++ b/main/usb_serial.c
@@ -79,15 +79,17 @@ static void usb_out_chars (const char *buf, int length)
}
}
+/*
static int32_t usb_in_chars (char *buf, uint32_t length)
{
uint32_t count = 0;
- if (usb_connected() && tud_cdc_available())
- count = tud_cdc_read(buf, length);
+ if(usb_connected() && tud_cdc_available())
+ count = tud_cdc_read(buf, length);
return count ? count : -1;
}
+*/
//
// Returns number of characters in USB input buffer
@@ -308,46 +310,3 @@ const io_stream_t *usb_serialInit (void)
return &stream;
}
-
-//
-// This function get called from the foreground process,
-// used here to get characters off the USB serial input stream and buffer
-// them for processing by grbl. Real time command characters are stripped out
-// and submitted for realtime processing.
-//
-static void execute_realtime (uint_fast16_t state)
-{
- static volatile bool lock = false;
- static char tmpbuf[BLOCK_RX_BUFFER_SIZE];
-
- if(lock)
- return;
-
- char c, *dp;
- int32_t avail, free;
-
- lock = true;
-
- if(usb_connected() && (avail = (int32_t)tud_cdc_available())) {
-
- dp = tmpbuf;
- free = (int32_t)usb_serialRxFree();
- free = free > BLOCK_RX_BUFFER_SIZE ? BLOCK_RX_BUFFER_SIZE : free;
- avail = usb_in_chars(tmpbuf, (uint32_t)(avail > free ? free : avail));
-
- if(avail > 0) while(avail--) {
- c = *dp++;
- if(!enqueue_realtime_command(c)) {
- uint_fast16_t next_head = BUFNEXT(rxbuf.head, rxbuf); // Get next head pointer
- if(next_head == rxbuf.tail) // If buffer full
- rxbuf.overflow = On; // flag overflow,
- else {
- rxbuf.data[rxbuf.head] = c; // else add character data to buffer
- rxbuf.head = next_head; // and update pointer
- }
- }
- }
- }
-
- lock = false;
-}
diff --git a/main/wifi.c b/main/wifi.c
index 90b197c..3c4ad21 100644
--- a/main/wifi.c
+++ b/main/wifi.c
@@ -5,7 +5,7 @@
Part of grblHAL
- Copyright (c) 2018-2023 Terje Io
+ Copyright (c) 2018-2024 Terje Io
Some parts of the code is based on example code by Espressif, in the public domain
@@ -50,6 +50,11 @@
#include "grbl/nvs_buffer.h"
#include "grbl/protocol.h"
+typedef struct {
+ grbl_wifi_mode_t mode;
+ wifi_sta_settings_t sta;
+ wifi_ap_settings_t ap;
+} wifi_settings_t;
/* The event group allows multiple bits for each event,
but we only care about one event - are we connected
@@ -121,7 +126,7 @@ void wifi_release_aplist (void)
char *iptoa (void *ip)
{
- static char aip[INET6_ADDRSTRLEN];
+ static char aip[INET6_ADDRSTRLEN + 20]; // + 20 due to compiler issue?
inet_ntop(AF_INET, ip, aip, INET6_ADDRSTRLEN);
@@ -402,7 +407,7 @@ static void msg_ap_disconnected (sys_state_t state)
static void msg_sta_active (sys_state_t state)
{
- char buf[50];
+ char buf[50 + 45]; // + 45 due to compiler issue?
sprintf(buf, "[MSG:WIFI STA ACTIVE, IP=%s]" ASCII_EOL, iptoa(&ap_list.ip_addr));
@@ -606,12 +611,11 @@ static bool init_adapter (esp_netif_t *netif, network_settings_t *settings)
return network.ip_mode == IpMode_DHCP;
}
-static wifi_mode_t settingToMode(grbl_wifi_mode_t mode)
+static wifi_mode_t settingToMode (grbl_wifi_mode_t mode)
{
return mode == WiFiMode_AP ? WIFI_MODE_AP :
mode == WiFiMode_STA ? WIFI_MODE_STA :
- mode == WiFiMode_APSTA ? WIFI_MODE_APSTA :
- WIFI_MODE_NULL;
+ mode == WiFiMode_APSTA ? WIFI_MODE_APSTA : WIFI_MODE_NULL;
}
bool wifi_start (void)
diff --git a/sdkconfig.s3 b/sdkconfig.s3
new file mode 100644
index 0000000..9e9e5d9
--- /dev/null
+++ b/sdkconfig.s3
@@ -0,0 +1,1479 @@
+#
+# Automatically generated file. DO NOT EDIT.
+# Espressif IoT Development Framework (ESP-IDF) Project Configuration
+#
+CONFIG_IDF_CMAKE=y
+CONFIG_IDF_TARGET_ARCH_XTENSA=y
+CONFIG_IDF_TARGET="esp32s3"
+CONFIG_IDF_TARGET_ESP32S3=y
+CONFIG_IDF_FIRMWARE_CHIP_ID=0x0009
+
+#
+# SDK tool configuration
+#
+CONFIG_SDK_TOOLPREFIX="xtensa-esp32-elf-"
+# CONFIG_SDK_TOOLCHAIN_SUPPORTS_TIME_WIDE_64_BITS is not set
+# end of SDK tool configuration
+
+#
+# Build type
+#
+CONFIG_APP_BUILD_TYPE_APP_2NDBOOT=y
+# CONFIG_APP_BUILD_TYPE_ELF_RAM is not set
+CONFIG_APP_BUILD_GENERATE_BINARIES=y
+CONFIG_APP_BUILD_BOOTLOADER=y
+CONFIG_APP_BUILD_USE_FLASH_SECTIONS=y
+# end of Build type
+
+#
+# Application manager
+#
+CONFIG_APP_COMPILE_TIME_DATE=y
+# CONFIG_APP_EXCLUDE_PROJECT_VER_VAR is not set
+# CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR is not set
+# CONFIG_APP_PROJECT_VER_FROM_CONFIG is not set
+CONFIG_APP_RETRIEVE_LEN_ELF_SHA=16
+# end of Application manager
+
+#
+# Bootloader config
+#
+CONFIG_BOOTLOADER_OFFSET_IN_FLASH=0x0
+CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
+# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG is not set
+# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_PERF is not set
+# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_NONE is not set
+# CONFIG_BOOTLOADER_LOG_LEVEL_NONE is not set
+# CONFIG_BOOTLOADER_LOG_LEVEL_ERROR is not set
+# CONFIG_BOOTLOADER_LOG_LEVEL_WARN is not set
+CONFIG_BOOTLOADER_LOG_LEVEL_INFO=y
+# CONFIG_BOOTLOADER_LOG_LEVEL_DEBUG is not set
+# CONFIG_BOOTLOADER_LOG_LEVEL_VERBOSE is not set
+CONFIG_BOOTLOADER_LOG_LEVEL=3
+# CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_8V is not set
+CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V=y
+# CONFIG_BOOTLOADER_FACTORY_RESET is not set
+# CONFIG_BOOTLOADER_APP_TEST is not set
+CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE=y
+CONFIG_BOOTLOADER_WDT_ENABLE=y
+# CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE is not set
+CONFIG_BOOTLOADER_WDT_TIME_MS=9000
+# CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE is not set
+# CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP is not set
+# CONFIG_BOOTLOADER_SKIP_VALIDATE_ON_POWER_ON is not set
+# CONFIG_BOOTLOADER_SKIP_VALIDATE_ALWAYS is not set
+CONFIG_BOOTLOADER_RESERVE_RTC_SIZE=0
+# CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC is not set
+CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT=y
+# end of Bootloader config
+
+#
+# Security features
+#
+CONFIG_SECURE_BOOT_SUPPORTS_RSA=y
+CONFIG_SECURE_TARGET_HAS_SECURE_ROM_DL_MODE=y
+# CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT is not set
+# CONFIG_SECURE_BOOT is not set
+# CONFIG_SECURE_FLASH_ENC_ENABLED is not set
+# end of Security features
+
+#
+# Boot ROM Behavior
+#
+CONFIG_BOOT_ROM_LOG_ALWAYS_ON=y
+# CONFIG_BOOT_ROM_LOG_ALWAYS_OFF is not set
+# CONFIG_BOOT_ROM_LOG_ON_GPIO_HIGH is not set
+# CONFIG_BOOT_ROM_LOG_ON_GPIO_LOW is not set
+# end of Boot ROM Behavior
+
+#
+# Serial flasher config
+#
+CONFIG_ESPTOOLPY_BAUD_OTHER_VAL=115200
+# CONFIG_ESPTOOLPY_NO_STUB is not set
+# CONFIG_ESPTOOLPY_OCT_FLASH is not set
+# CONFIG_ESPTOOLPY_FLASHMODE_QIO is not set
+# CONFIG_ESPTOOLPY_FLASHMODE_QOUT is not set
+CONFIG_ESPTOOLPY_FLASHMODE_DIO=y
+# CONFIG_ESPTOOLPY_FLASHMODE_DOUT is not set
+CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR=y
+CONFIG_ESPTOOLPY_FLASHMODE="dio"
+# CONFIG_ESPTOOLPY_FLASHFREQ_120M is not set
+# CONFIG_ESPTOOLPY_FLASHFREQ_80M is not set
+CONFIG_ESPTOOLPY_FLASHFREQ_40M=y
+# CONFIG_ESPTOOLPY_FLASHFREQ_20M is not set
+CONFIG_ESPTOOLPY_FLASHFREQ="40m"
+# CONFIG_ESPTOOLPY_FLASHSIZE_1MB is not set
+# CONFIG_ESPTOOLPY_FLASHSIZE_2MB is not set
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
+# CONFIG_ESPTOOLPY_FLASHSIZE_8MB is not set
+# CONFIG_ESPTOOLPY_FLASHSIZE_16MB is not set
+# CONFIG_ESPTOOLPY_FLASHSIZE_32MB is not set
+# CONFIG_ESPTOOLPY_FLASHSIZE_64MB is not set
+# CONFIG_ESPTOOLPY_FLASHSIZE_128MB is not set
+CONFIG_ESPTOOLPY_FLASHSIZE="4MB"
+CONFIG_ESPTOOLPY_FLASHSIZE_DETECT=y
+CONFIG_ESPTOOLPY_BEFORE_RESET=y
+# CONFIG_ESPTOOLPY_BEFORE_NORESET is not set
+CONFIG_ESPTOOLPY_BEFORE="default_reset"
+CONFIG_ESPTOOLPY_AFTER_RESET=y
+# CONFIG_ESPTOOLPY_AFTER_NORESET is not set
+CONFIG_ESPTOOLPY_AFTER="hard_reset"
+# CONFIG_ESPTOOLPY_MONITOR_BAUD_CONSOLE is not set
+# CONFIG_ESPTOOLPY_MONITOR_BAUD_9600B is not set
+# CONFIG_ESPTOOLPY_MONITOR_BAUD_57600B is not set
+CONFIG_ESPTOOLPY_MONITOR_BAUD_115200B=y
+# CONFIG_ESPTOOLPY_MONITOR_BAUD_230400B is not set
+# CONFIG_ESPTOOLPY_MONITOR_BAUD_921600B is not set
+# CONFIG_ESPTOOLPY_MONITOR_BAUD_2MB is not set
+# CONFIG_ESPTOOLPY_MONITOR_BAUD_OTHER is not set
+CONFIG_ESPTOOLPY_MONITOR_BAUD_OTHER_VAL=115200
+CONFIG_ESPTOOLPY_MONITOR_BAUD=115200
+# end of Serial flasher config
+
+#
+# Partition Table
+#
+# CONFIG_PARTITION_TABLE_SINGLE_APP is not set
+# CONFIG_PARTITION_TABLE_SINGLE_APP_LARGE is not set
+# CONFIG_PARTITION_TABLE_TWO_OTA is not set
+CONFIG_PARTITION_TABLE_CUSTOM=y
+CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv"
+CONFIG_PARTITION_TABLE_FILENAME="partitions.csv"
+CONFIG_PARTITION_TABLE_OFFSET=0x8000
+CONFIG_PARTITION_TABLE_MD5=y
+# end of Partition Table
+
+#
+# Compiler options
+#
+CONFIG_COMPILER_OPTIMIZATION_DEFAULT=y
+# CONFIG_COMPILER_OPTIMIZATION_SIZE is not set
+# CONFIG_COMPILER_OPTIMIZATION_PERF is not set
+# CONFIG_COMPILER_OPTIMIZATION_NONE is not set
+# CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE is not set
+# CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT is not set
+CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE=y
+CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL=0
+# CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT is not set
+CONFIG_COMPILER_HIDE_PATHS_MACROS=y
+# CONFIG_COMPILER_CXX_EXCEPTIONS is not set
+# CONFIG_COMPILER_CXX_RTTI is not set
+CONFIG_COMPILER_STACK_CHECK_MODE_NONE=y
+# CONFIG_COMPILER_STACK_CHECK_MODE_NORM is not set
+# CONFIG_COMPILER_STACK_CHECK_MODE_STRONG is not set
+# CONFIG_COMPILER_STACK_CHECK_MODE_ALL is not set
+# CONFIG_COMPILER_WARN_WRITE_STRINGS is not set
+# CONFIG_COMPILER_DISABLE_GCC8_WARNINGS is not set
+# CONFIG_COMPILER_DUMP_RTL_FILES is not set
+# end of Compiler options
+
+#
+# Component config
+#
+
+#
+# Application Level Tracing
+#
+# CONFIG_APPTRACE_DEST_JTAG is not set
+CONFIG_APPTRACE_DEST_NONE=y
+CONFIG_APPTRACE_LOCK_ENABLE=y
+# end of Application Level Tracing
+
+#
+# ESP-ASIO
+#
+# CONFIG_ASIO_SSL_SUPPORT is not set
+# end of ESP-ASIO
+
+#
+# Bluetooth
+#
+# CONFIG_BT_ENABLED is not set
+# end of Bluetooth
+
+#
+# CoAP Configuration
+#
+CONFIG_COAP_MBEDTLS_PSK=y
+# CONFIG_COAP_MBEDTLS_PKI is not set
+# CONFIG_COAP_MBEDTLS_DEBUG is not set
+CONFIG_COAP_LOG_DEFAULT_LEVEL=0
+# end of CoAP Configuration
+
+#
+# Driver configurations
+#
+
+#
+# ADC configuration
+#
+# CONFIG_ADC_FORCE_XPD_FSM is not set
+CONFIG_ADC_DISABLE_DAC=y
+# CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3 is not set
+# end of ADC configuration
+
+#
+# MCPWM configuration
+#
+# CONFIG_MCPWM_ISR_IN_IRAM is not set
+# end of MCPWM configuration
+
+#
+# SPI configuration
+#
+# CONFIG_SPI_MASTER_IN_IRAM is not set
+CONFIG_SPI_MASTER_ISR_IN_IRAM=y
+# CONFIG_SPI_SLAVE_IN_IRAM is not set
+CONFIG_SPI_SLAVE_ISR_IN_IRAM=y
+# end of SPI configuration
+
+#
+# TWAI configuration
+#
+# CONFIG_TWAI_ISR_IN_IRAM is not set
+# CONFIG_TWAI_ERRATA_FIX_LISTEN_ONLY_DOM is not set
+# end of TWAI configuration
+
+#
+# UART configuration
+#
+# CONFIG_UART_ISR_IN_IRAM is not set
+# end of UART configuration
+
+#
+# GDMA Configuration
+#
+# CONFIG_GDMA_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_GDMA_ISR_IRAM_SAFE is not set
+# end of GDMA Configuration
+# end of Driver configurations
+
+#
+# eFuse Bit Manager
+#
+# CONFIG_EFUSE_CUSTOM_TABLE is not set
+# CONFIG_EFUSE_VIRTUAL is not set
+CONFIG_EFUSE_MAX_BLK_LEN=256
+# end of eFuse Bit Manager
+
+#
+# ESP-TLS
+#
+CONFIG_ESP_TLS_USING_MBEDTLS=y
+CONFIG_ESP_TLS_USE_DS_PERIPHERAL=y
+# CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS is not set
+# CONFIG_ESP_TLS_SERVER is not set
+# CONFIG_ESP_TLS_PSK_VERIFICATION is not set
+# CONFIG_ESP_TLS_INSECURE is not set
+# end of ESP-TLS
+
+#
+# ESP32S3-Specific
+#
+CONFIG_ESP32S3_REV_MIN_0=y
+# CONFIG_ESP32S3_REV_MIN_1 is not set
+# CONFIG_ESP32S3_REV_MIN_2 is not set
+CONFIG_ESP32S3_REV_MIN_FULL=0
+CONFIG_ESP_REV_MIN_FULL=0
+CONFIG_ESP32S3_REV_MAX_FULL_STR_OPT=y
+CONFIG_ESP32S3_REV_MAX_FULL=99
+CONFIG_ESP_REV_MAX_FULL=99
+# CONFIG_ESP32S3_DEFAULT_CPU_FREQ_80 is not set
+CONFIG_ESP32S3_DEFAULT_CPU_FREQ_160=y
+# CONFIG_ESP32S3_DEFAULT_CPU_FREQ_240 is not set
+CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ=160
+
+#
+# Cache config
+#
+CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB=y
+# CONFIG_ESP32S3_INSTRUCTION_CACHE_32KB is not set
+CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE=0x4000
+# CONFIG_ESP32S3_INSTRUCTION_CACHE_4WAYS is not set
+CONFIG_ESP32S3_INSTRUCTION_CACHE_8WAYS=y
+CONFIG_ESP32S3_ICACHE_ASSOCIATED_WAYS=8
+# CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_16B is not set
+CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_32B=y
+CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE=32
+# CONFIG_ESP32S3_INSTRUCTION_CACHE_WRAP is not set
+# CONFIG_ESP32S3_DATA_CACHE_16KB is not set
+CONFIG_ESP32S3_DATA_CACHE_32KB=y
+# CONFIG_ESP32S3_DATA_CACHE_64KB is not set
+CONFIG_ESP32S3_DATA_CACHE_SIZE=0x8000
+# CONFIG_ESP32S3_DATA_CACHE_4WAYS is not set
+CONFIG_ESP32S3_DATA_CACHE_8WAYS=y
+CONFIG_ESP32S3_DCACHE_ASSOCIATED_WAYS=8
+# CONFIG_ESP32S3_DATA_CACHE_LINE_16B is not set
+CONFIG_ESP32S3_DATA_CACHE_LINE_32B=y
+# CONFIG_ESP32S3_DATA_CACHE_LINE_64B is not set
+CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE=32
+# CONFIG_ESP32S3_DATA_CACHE_WRAP is not set
+# end of Cache config
+
+# CONFIG_ESP32S3_SPIRAM_SUPPORT is not set
+# CONFIG_ESP32S3_TRAX is not set
+CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM=0x0
+# CONFIG_ESP32S3_ULP_COPROC_ENABLED is not set
+CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM=0
+CONFIG_ESP32S3_DEBUG_OCDAWARE=y
+CONFIG_ESP32S3_BROWNOUT_DET=y
+CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_7=y
+# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_6 is not set
+# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_5 is not set
+# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_4 is not set
+# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_3 is not set
+# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_2 is not set
+# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_1 is not set
+CONFIG_ESP32S3_BROWNOUT_DET_LVL=7
+CONFIG_ESP32S3_TIME_SYSCALL_USE_RTC_FRC1=y
+# CONFIG_ESP32S3_TIME_SYSCALL_USE_RTC is not set
+# CONFIG_ESP32S3_TIME_SYSCALL_USE_FRC1 is not set
+# CONFIG_ESP32S3_TIME_SYSCALL_USE_NONE is not set
+CONFIG_ESP32S3_RTC_CLK_SRC_INT_RC=y
+# CONFIG_ESP32S3_RTC_CLK_SRC_EXT_CRYS is not set
+# CONFIG_ESP32S3_RTC_CLK_SRC_EXT_OSC is not set
+# CONFIG_ESP32S3_RTC_CLK_SRC_INT_8MD256 is not set
+CONFIG_ESP32S3_RTC_CLK_CAL_CYCLES=1024
+CONFIG_ESP32S3_DEEP_SLEEP_WAKEUP_DELAY=2000
+# CONFIG_ESP32S3_NO_BLOBS is not set
+# CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM is not set
+# CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE is not set
+# end of ESP32S3-Specific
+
+#
+# ADC-Calibration
+#
+# end of ADC-Calibration
+
+#
+# Common ESP-related
+#
+CONFIG_ESP_ERR_TO_NAME_LOOKUP=y
+# end of Common ESP-related
+
+#
+# Ethernet
+#
+CONFIG_ETH_ENABLED=y
+CONFIG_ETH_USE_SPI_ETHERNET=y
+# CONFIG_ETH_SPI_ETHERNET_DM9051 is not set
+# CONFIG_ETH_SPI_ETHERNET_W5500 is not set
+# CONFIG_ETH_SPI_ETHERNET_KSZ8851SNL is not set
+# CONFIG_ETH_USE_OPENETH is not set
+# end of Ethernet
+
+#
+# Event Loop Library
+#
+# CONFIG_ESP_EVENT_LOOP_PROFILING is not set
+CONFIG_ESP_EVENT_POST_FROM_ISR=y
+CONFIG_ESP_EVENT_POST_FROM_IRAM_ISR=y
+# end of Event Loop Library
+
+#
+# GDB Stub
+#
+# end of GDB Stub
+
+#
+# ESP HTTP client
+#
+CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS=y
+# CONFIG_ESP_HTTP_CLIENT_ENABLE_BASIC_AUTH is not set
+CONFIG_ESP_HTTP_CLIENT_ENABLE_DIGEST_AUTH=y
+# end of ESP HTTP client
+
+#
+# HTTP Server
+#
+CONFIG_HTTPD_MAX_REQ_HDR_LEN=512
+CONFIG_HTTPD_MAX_URI_LEN=512
+CONFIG_HTTPD_ERR_RESP_NO_DELAY=y
+CONFIG_HTTPD_PURGE_BUF_LEN=32
+# CONFIG_HTTPD_LOG_PURGE_DATA is not set
+# CONFIG_HTTPD_WS_SUPPORT is not set
+# end of HTTP Server
+
+#
+# ESP HTTPS OTA
+#
+# CONFIG_OTA_ALLOW_HTTP is not set
+# end of ESP HTTPS OTA
+
+#
+# ESP HTTPS server
+#
+# CONFIG_ESP_HTTPS_SERVER_ENABLE is not set
+# end of ESP HTTPS server
+
+#
+# Hardware Settings
+#
+
+#
+# MAC Config
+#
+CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA=y
+CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP=y
+CONFIG_ESP_MAC_ADDR_UNIVERSE_BT=y
+CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH=y
+# CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES_TWO is not set
+CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES_FOUR=y
+CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES=4
+# end of MAC Config
+
+#
+# Sleep Config
+#
+CONFIG_ESP_SLEEP_POWER_DOWN_FLASH=y
+CONFIG_ESP_SLEEP_RTC_BUS_ISO_WORKAROUND=y
+CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND=y
+CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND=y
+CONFIG_ESP_SLEEP_MSPI_NEED_ALL_IO_PU=y
+# end of Sleep Config
+
+#
+# RTC Clock Config
+#
+CONFIG_RTC_CLOCK_BBPLL_POWER_ON_WITH_USB=y
+# end of RTC Clock Config
+# end of Hardware Settings
+
+#
+# IPC (Inter-Processor Call)
+#
+CONFIG_ESP_IPC_TASK_STACK_SIZE=1024
+CONFIG_ESP_IPC_USES_CALLERS_PRIORITY=y
+CONFIG_ESP_IPC_ISR_ENABLE=y
+# end of IPC (Inter-Processor Call)
+
+#
+# LCD and Touch Panel
+#
+
+#
+# LCD Peripheral Configuration
+#
+CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE=32
+# CONFIG_LCD_RGB_ISR_IRAM_SAFE is not set
+# end of LCD Peripheral Configuration
+# end of LCD and Touch Panel
+
+#
+# ESP NETIF Adapter
+#
+CONFIG_ESP_NETIF_IP_LOST_TIMER_INTERVAL=120
+CONFIG_ESP_NETIF_TCPIP_LWIP=y
+# CONFIG_ESP_NETIF_LOOPBACK is not set
+CONFIG_ESP_NETIF_TCPIP_ADAPTER_COMPATIBLE_LAYER=y
+# end of ESP NETIF Adapter
+
+#
+# PHY
+#
+CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE=y
+# CONFIG_ESP_PHY_INIT_DATA_IN_PARTITION is not set
+CONFIG_ESP_PHY_MAX_WIFI_TX_POWER=20
+CONFIG_ESP_PHY_MAX_TX_POWER=20
+# CONFIG_ESP_PHY_REDUCE_TX_POWER is not set
+CONFIG_ESP_PHY_ENABLE_USB=y
+CONFIG_ESP_PHY_RF_CAL_PARTIAL=y
+# CONFIG_ESP_PHY_RF_CAL_NONE is not set
+# CONFIG_ESP_PHY_RF_CAL_FULL is not set
+CONFIG_ESP_PHY_CALIBRATION_MODE=0
+# end of PHY
+
+#
+# Power Management
+#
+# CONFIG_PM_ENABLE is not set
+CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP=y
+CONFIG_PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP=y
+# end of Power Management
+
+#
+# ESP Ringbuf
+#
+# CONFIG_RINGBUF_PLACE_FUNCTIONS_INTO_FLASH is not set
+# CONFIG_RINGBUF_PLACE_ISR_FUNCTIONS_INTO_FLASH is not set
+# end of ESP Ringbuf
+
+#
+# ESP System Settings
+#
+# CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT is not set
+CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT=y
+# CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT is not set
+# CONFIG_ESP_SYSTEM_PANIC_GDBSTUB is not set
+# CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME is not set
+CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK=y
+CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP=y
+
+#
+# Memory protection
+#
+# end of Memory protection
+
+CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE=32
+CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE=2304
+CONFIG_ESP_MAIN_TASK_STACK_SIZE=3584
+CONFIG_ESP_MAIN_TASK_AFFINITY_CPU0=y
+# CONFIG_ESP_MAIN_TASK_AFFINITY_CPU1 is not set
+# CONFIG_ESP_MAIN_TASK_AFFINITY_NO_AFFINITY is not set
+CONFIG_ESP_MAIN_TASK_AFFINITY=0x0
+CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE=2048
+CONFIG_ESP_CONSOLE_UART_DEFAULT=y
+# CONFIG_ESP_CONSOLE_USB_CDC is not set
+# CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG is not set
+# CONFIG_ESP_CONSOLE_UART_CUSTOM is not set
+# CONFIG_ESP_CONSOLE_NONE is not set
+# CONFIG_ESP_CONSOLE_SECONDARY_NONE is not set
+CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG=y
+CONFIG_ESP_CONSOLE_UART=y
+CONFIG_ESP_CONSOLE_MULTIPLE_UART=y
+CONFIG_ESP_CONSOLE_UART_NUM=0
+CONFIG_ESP_CONSOLE_UART_BAUDRATE=115200
+CONFIG_ESP_INT_WDT=y
+CONFIG_ESP_INT_WDT_TIMEOUT_MS=300
+CONFIG_ESP_INT_WDT_CHECK_CPU1=y
+CONFIG_ESP_TASK_WDT=y
+# CONFIG_ESP_TASK_WDT_PANIC is not set
+CONFIG_ESP_TASK_WDT_TIMEOUT_S=5
+CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0=y
+CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1=y
+# CONFIG_ESP_PANIC_HANDLER_IRAM is not set
+# CONFIG_ESP_DEBUG_STUBS_ENABLE is not set
+CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4=y
+# end of ESP System Settings
+
+#
+# High resolution timer (esp_timer)
+#
+# CONFIG_ESP_TIMER_PROFILING is not set
+CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER=y
+CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER=y
+CONFIG_ESP_TIMER_TASK_STACK_SIZE=3584
+CONFIG_ESP_TIMER_INTERRUPT_LEVEL=1
+# CONFIG_ESP_TIMER_SUPPORTS_ISR_DISPATCH_METHOD is not set
+CONFIG_ESP_TIMER_IMPL_SYSTIMER=y
+# end of High resolution timer (esp_timer)
+
+#
+# Wi-Fi
+#
+CONFIG_ESP32_WIFI_ENABLED=y
+CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10
+CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32
+# CONFIG_ESP32_WIFI_STATIC_TX_BUFFER is not set
+CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER=y
+CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=1
+CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM=32
+# CONFIG_ESP32_WIFI_CSI_ENABLED is not set
+CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y
+CONFIG_ESP32_WIFI_TX_BA_WIN=6
+CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y
+CONFIG_ESP32_WIFI_RX_BA_WIN=6
+CONFIG_ESP32_WIFI_NVS_ENABLED=y
+CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_0=y
+# CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_1 is not set
+CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752
+CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32
+CONFIG_ESP32_WIFI_IRAM_OPT=y
+CONFIG_ESP32_WIFI_RX_IRAM_OPT=y
+CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE=y
+# CONFIG_ESP_WIFI_SLP_IRAM_OPT is not set
+# CONFIG_ESP_WIFI_FTM_ENABLE is not set
+# CONFIG_ESP_WIFI_STA_DISCONNECTED_PM_ENABLE is not set
+# CONFIG_ESP_WIFI_GCMP_SUPPORT is not set
+# CONFIG_ESP_WIFI_GMAC_SUPPORT is not set
+CONFIG_ESP_WIFI_SOFTAP_SUPPORT=y
+# CONFIG_ESP_WIFI_SLP_BEACON_LOST_OPT is not set
+CONFIG_ESP_WIFI_ESPNOW_MAX_ENCRYPT_NUM=7
+# end of Wi-Fi
+
+#
+# Core dump
+#
+# CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH is not set
+# CONFIG_ESP_COREDUMP_ENABLE_TO_UART is not set
+CONFIG_ESP_COREDUMP_ENABLE_TO_NONE=y
+# end of Core dump
+
+#
+# FAT Filesystem support
+#
+# CONFIG_FATFS_CODEPAGE_DYNAMIC is not set
+# CONFIG_FATFS_CODEPAGE_437 is not set
+# CONFIG_FATFS_CODEPAGE_720 is not set
+# CONFIG_FATFS_CODEPAGE_737 is not set
+# CONFIG_FATFS_CODEPAGE_771 is not set
+# CONFIG_FATFS_CODEPAGE_775 is not set
+CONFIG_FATFS_CODEPAGE_850=y
+# CONFIG_FATFS_CODEPAGE_852 is not set
+# CONFIG_FATFS_CODEPAGE_855 is not set
+# CONFIG_FATFS_CODEPAGE_857 is not set
+# CONFIG_FATFS_CODEPAGE_860 is not set
+# CONFIG_FATFS_CODEPAGE_861 is not set
+# CONFIG_FATFS_CODEPAGE_862 is not set
+# CONFIG_FATFS_CODEPAGE_863 is not set
+# CONFIG_FATFS_CODEPAGE_864 is not set
+# CONFIG_FATFS_CODEPAGE_865 is not set
+# CONFIG_FATFS_CODEPAGE_866 is not set
+# CONFIG_FATFS_CODEPAGE_869 is not set
+# CONFIG_FATFS_CODEPAGE_932 is not set
+# CONFIG_FATFS_CODEPAGE_936 is not set
+# CONFIG_FATFS_CODEPAGE_949 is not set
+# CONFIG_FATFS_CODEPAGE_950 is not set
+CONFIG_FATFS_CODEPAGE=850
+# CONFIG_FATFS_LFN_NONE is not set
+CONFIG_FATFS_LFN_HEAP=y
+# CONFIG_FATFS_LFN_STACK is not set
+CONFIG_FATFS_MAX_LFN=255
+CONFIG_FATFS_API_ENCODING_ANSI_OEM=y
+# CONFIG_FATFS_API_ENCODING_UTF_16 is not set
+# CONFIG_FATFS_API_ENCODING_UTF_8 is not set
+CONFIG_FATFS_FS_LOCK=0
+CONFIG_FATFS_TIMEOUT_MS=10000
+CONFIG_FATFS_PER_FILE_CACHE=y
+# CONFIG_FATFS_USE_FASTSEEK is not set
+# end of FAT Filesystem support
+
+#
+# Modbus configuration
+#
+CONFIG_FMB_COMM_MODE_TCP_EN=y
+CONFIG_FMB_TCP_PORT_DEFAULT=502
+CONFIG_FMB_TCP_PORT_MAX_CONN=5
+CONFIG_FMB_TCP_CONNECTION_TOUT_SEC=20
+CONFIG_FMB_COMM_MODE_RTU_EN=y
+CONFIG_FMB_COMM_MODE_ASCII_EN=y
+CONFIG_FMB_MASTER_TIMEOUT_MS_RESPOND=150
+CONFIG_FMB_MASTER_DELAY_MS_CONVERT=200
+CONFIG_FMB_QUEUE_LENGTH=20
+CONFIG_FMB_PORT_TASK_STACK_SIZE=4096
+CONFIG_FMB_SERIAL_BUF_SIZE=256
+CONFIG_FMB_SERIAL_ASCII_BITS_PER_SYMB=8
+CONFIG_FMB_SERIAL_ASCII_TIMEOUT_RESPOND_MS=1000
+CONFIG_FMB_PORT_TASK_PRIO=10
+# CONFIG_FMB_PORT_TASK_AFFINITY_NO_AFFINITY is not set
+CONFIG_FMB_PORT_TASK_AFFINITY_CPU0=y
+# CONFIG_FMB_PORT_TASK_AFFINITY_CPU1 is not set
+CONFIG_FMB_PORT_TASK_AFFINITY=0x0
+CONFIG_FMB_CONTROLLER_SLAVE_ID_SUPPORT=y
+CONFIG_FMB_CONTROLLER_SLAVE_ID=0x00112233
+CONFIG_FMB_CONTROLLER_NOTIFY_TIMEOUT=20
+CONFIG_FMB_CONTROLLER_NOTIFY_QUEUE_SIZE=20
+CONFIG_FMB_CONTROLLER_STACK_SIZE=4096
+CONFIG_FMB_EVENT_QUEUE_TIMEOUT=20
+# CONFIG_FMB_TIMER_PORT_ENABLED is not set
+# CONFIG_FMB_TIMER_USE_ISR_DISPATCH_METHOD is not set
+# end of Modbus configuration
+
+#
+# FreeRTOS
+#
+# CONFIG_FREERTOS_UNICORE is not set
+CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF
+CONFIG_FREERTOS_TICK_SUPPORT_SYSTIMER=y
+CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL1=y
+# CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL3 is not set
+CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER=y
+CONFIG_FREERTOS_HZ=1000
+CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION=y
+# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE is not set
+# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL is not set
+CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y
+# CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK is not set
+CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y
+CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=1
+# CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE is not set
+CONFIG_FREERTOS_ASSERT_DISABLE=y
+CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=2304
+CONFIG_FREERTOS_ISR_STACKSIZE=1536
+# CONFIG_FREERTOS_LEGACY_HOOKS is not set
+CONFIG_FREERTOS_MAX_TASK_NAME_LEN=16
+CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION=y
+# CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP is not set
+CONFIG_FREERTOS_TIMER_TASK_PRIORITY=1
+CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH=2048
+CONFIG_FREERTOS_TIMER_QUEUE_LENGTH=10
+CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0
+# CONFIG_FREERTOS_USE_TRACE_FACILITY is not set
+# CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS is not set
+CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER=y
+CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER=y
+# CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE is not set
+# CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH is not set
+CONFIG_FREERTOS_DEBUG_OCDAWARE=y
+CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT=y
+# CONFIG_FREERTOS_PLACE_SNAPSHOT_FUNS_INTO_FLASH is not set
+# end of FreeRTOS
+
+#
+# Hardware Abstraction Layer (HAL) and Low Level (LL)
+#
+CONFIG_HAL_ASSERTION_EQUALS_SYSTEM=y
+# CONFIG_HAL_ASSERTION_DISABLE is not set
+CONFIG_HAL_DEFAULT_ASSERTION_LEVEL=0
+# end of Hardware Abstraction Layer (HAL) and Low Level (LL)
+
+#
+# Heap memory debugging
+#
+CONFIG_HEAP_POISONING_DISABLED=y
+# CONFIG_HEAP_POISONING_LIGHT is not set
+# CONFIG_HEAP_POISONING_COMPREHENSIVE is not set
+CONFIG_HEAP_TRACING_OFF=y
+# CONFIG_HEAP_TRACING_STANDALONE is not set
+# CONFIG_HEAP_TRACING_TOHOST is not set
+# CONFIG_HEAP_ABORT_WHEN_ALLOCATION_FAILS is not set
+# end of Heap memory debugging
+
+#
+# jsmn
+#
+# CONFIG_JSMN_PARENT_LINKS is not set
+# CONFIG_JSMN_STRICT is not set
+# end of jsmn
+
+#
+# libsodium
+#
+# end of libsodium
+
+#
+# Log output
+#
+# CONFIG_LOG_DEFAULT_LEVEL_NONE is not set
+CONFIG_LOG_DEFAULT_LEVEL_ERROR=y
+# CONFIG_LOG_DEFAULT_LEVEL_WARN is not set
+# CONFIG_LOG_DEFAULT_LEVEL_INFO is not set
+# CONFIG_LOG_DEFAULT_LEVEL_DEBUG is not set
+# CONFIG_LOG_DEFAULT_LEVEL_VERBOSE is not set
+CONFIG_LOG_DEFAULT_LEVEL=1
+CONFIG_LOG_MAXIMUM_EQUALS_DEFAULT=y
+# CONFIG_LOG_MAXIMUM_LEVEL_WARN is not set
+# CONFIG_LOG_MAXIMUM_LEVEL_INFO is not set
+# CONFIG_LOG_MAXIMUM_LEVEL_DEBUG is not set
+# CONFIG_LOG_MAXIMUM_LEVEL_VERBOSE is not set
+CONFIG_LOG_MAXIMUM_LEVEL=1
+CONFIG_LOG_COLORS=y
+CONFIG_LOG_TIMESTAMP_SOURCE_RTOS=y
+# CONFIG_LOG_TIMESTAMP_SOURCE_SYSTEM is not set
+# end of Log output
+
+#
+# LWIP
+#
+CONFIG_LWIP_LOCAL_HOSTNAME="espressif"
+# CONFIG_LWIP_NETIF_API is not set
+# CONFIG_LWIP_TCPIP_CORE_LOCKING is not set
+# CONFIG_LWIP_CHECK_THREAD_SAFETY is not set
+CONFIG_LWIP_DNS_SUPPORT_MDNS_QUERIES=y
+# CONFIG_LWIP_L2_TO_L3_COPY is not set
+# CONFIG_LWIP_IRAM_OPTIMIZATION is not set
+CONFIG_LWIP_TIMERS_ONDEMAND=y
+CONFIG_LWIP_MAX_SOCKETS=10
+# CONFIG_LWIP_USE_ONLY_LWIP_SELECT is not set
+# CONFIG_LWIP_SO_LINGER is not set
+CONFIG_LWIP_SO_REUSE=y
+CONFIG_LWIP_SO_REUSE_RXTOALL=y
+# CONFIG_LWIP_SO_RCVBUF is not set
+# CONFIG_LWIP_NETBUF_RECVINFO is not set
+CONFIG_LWIP_IP4_FRAG=y
+CONFIG_LWIP_IP6_FRAG=y
+# CONFIG_LWIP_IP4_REASSEMBLY is not set
+# CONFIG_LWIP_IP6_REASSEMBLY is not set
+# CONFIG_LWIP_IP_FORWARD is not set
+# CONFIG_LWIP_STATS is not set
+# CONFIG_LWIP_ETHARP_TRUST_IP_MAC is not set
+CONFIG_LWIP_ESP_GRATUITOUS_ARP=y
+CONFIG_LWIP_GARP_TMR_INTERVAL=60
+CONFIG_LWIP_ESP_MLDV6_REPORT=y
+CONFIG_LWIP_MLDV6_TMR_INTERVAL=40
+CONFIG_LWIP_TCPIP_RECVMBOX_SIZE=32
+CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y
+# CONFIG_LWIP_DHCP_DISABLE_CLIENT_ID is not set
+CONFIG_LWIP_DHCP_DISABLE_VENDOR_CLASS_ID=y
+# CONFIG_LWIP_DHCP_RESTORE_LAST_IP is not set
+CONFIG_LWIP_DHCP_OPTIONS_LEN=68
+CONFIG_LWIP_DHCP_COARSE_TIMER_SECS=1
+
+#
+# DHCP server
+#
+CONFIG_LWIP_DHCPS=y
+CONFIG_LWIP_DHCPS_LEASE_UNIT=60
+CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8
+# end of DHCP server
+
+# CONFIG_LWIP_AUTOIP is not set
+CONFIG_LWIP_IPV6=y
+# CONFIG_LWIP_IPV6_AUTOCONFIG is not set
+CONFIG_LWIP_IPV6_NUM_ADDRESSES=3
+# CONFIG_LWIP_IPV6_FORWARD is not set
+# CONFIG_LWIP_NETIF_STATUS_CALLBACK is not set
+CONFIG_LWIP_NETIF_LOOPBACK=y
+CONFIG_LWIP_LOOPBACK_MAX_PBUFS=8
+
+#
+# TCP
+#
+CONFIG_LWIP_MAX_ACTIVE_TCP=16
+CONFIG_LWIP_MAX_LISTENING_TCP=16
+CONFIG_LWIP_TCP_HIGH_SPEED_RETRANSMISSION=y
+CONFIG_LWIP_TCP_MAXRTX=12
+CONFIG_LWIP_TCP_SYNMAXRTX=12
+CONFIG_LWIP_TCP_MSS=1440
+CONFIG_LWIP_TCP_TMR_INTERVAL=250
+CONFIG_LWIP_TCP_MSL=60000
+CONFIG_LWIP_TCP_FIN_WAIT_TIMEOUT=20000
+CONFIG_LWIP_TCP_SND_BUF_DEFAULT=5744
+CONFIG_LWIP_TCP_WND_DEFAULT=5744
+CONFIG_LWIP_TCP_RECVMBOX_SIZE=6
+CONFIG_LWIP_TCP_QUEUE_OOSEQ=y
+# CONFIG_LWIP_TCP_SACK_OUT is not set
+# CONFIG_LWIP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES is not set
+CONFIG_LWIP_TCP_OVERSIZE_MSS=y
+# CONFIG_LWIP_TCP_OVERSIZE_QUARTER_MSS is not set
+# CONFIG_LWIP_TCP_OVERSIZE_DISABLE is not set
+CONFIG_LWIP_TCP_RTO_TIME=1500
+# end of TCP
+
+#
+# UDP
+#
+CONFIG_LWIP_MAX_UDP_PCBS=16
+CONFIG_LWIP_UDP_RECVMBOX_SIZE=6
+# end of UDP
+
+#
+# Checksums
+#
+# CONFIG_LWIP_CHECKSUM_CHECK_IP is not set
+# CONFIG_LWIP_CHECKSUM_CHECK_UDP is not set
+CONFIG_LWIP_CHECKSUM_CHECK_ICMP=y
+# end of Checksums
+
+CONFIG_LWIP_TCPIP_TASK_STACK_SIZE=3072
+# CONFIG_LWIP_TCPIP_TASK_AFFINITY_NO_AFFINITY is not set
+CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU0=y
+# CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU1 is not set
+CONFIG_LWIP_TCPIP_TASK_AFFINITY=0x0
+# CONFIG_LWIP_PPP_SUPPORT is not set
+CONFIG_LWIP_IPV6_MEMP_NUM_ND6_QUEUE=3
+CONFIG_LWIP_IPV6_ND6_NUM_NEIGHBORS=5
+# CONFIG_LWIP_SLIP_SUPPORT is not set
+
+#
+# ICMP
+#
+CONFIG_LWIP_ICMP=y
+# CONFIG_LWIP_MULTICAST_PING is not set
+# CONFIG_LWIP_BROADCAST_PING is not set
+# end of ICMP
+
+#
+# LWIP RAW API
+#
+CONFIG_LWIP_MAX_RAW_PCBS=16
+# end of LWIP RAW API
+
+#
+# SNTP
+#
+CONFIG_LWIP_SNTP_MAX_SERVERS=1
+# CONFIG_LWIP_DHCP_GET_NTP_SRV is not set
+CONFIG_LWIP_SNTP_UPDATE_DELAY=3600000
+# end of SNTP
+
+#
+# Hooks
+#
+# CONFIG_LWIP_HOOK_TCP_ISN_NONE is not set
+CONFIG_LWIP_HOOK_TCP_ISN_DEFAULT=y
+# CONFIG_LWIP_HOOK_TCP_ISN_CUSTOM is not set
+CONFIG_LWIP_HOOK_IP6_ROUTE_NONE=y
+# CONFIG_LWIP_HOOK_IP6_ROUTE_DEFAULT is not set
+# CONFIG_LWIP_HOOK_IP6_ROUTE_CUSTOM is not set
+CONFIG_LWIP_HOOK_ND6_GET_GW_NONE=y
+# CONFIG_LWIP_HOOK_ND6_GET_GW_DEFAULT is not set
+# CONFIG_LWIP_HOOK_ND6_GET_GW_CUSTOM is not set
+CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_NONE=y
+# CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_DEFAULT is not set
+# CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_CUSTOM is not set
+# end of Hooks
+
+# CONFIG_LWIP_DEBUG is not set
+# end of LWIP
+
+#
+# mbedTLS
+#
+CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC=y
+# CONFIG_MBEDTLS_DEFAULT_MEM_ALLOC is not set
+# CONFIG_MBEDTLS_CUSTOM_MEM_ALLOC is not set
+CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN=y
+CONFIG_MBEDTLS_SSL_IN_CONTENT_LEN=16384
+CONFIG_MBEDTLS_SSL_OUT_CONTENT_LEN=4096
+# CONFIG_MBEDTLS_DYNAMIC_BUFFER is not set
+# CONFIG_MBEDTLS_DEBUG is not set
+
+#
+# mbedTLS v2.28.x related
+#
+# CONFIG_MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH is not set
+# CONFIG_MBEDTLS_X509_TRUSTED_CERT_CALLBACK is not set
+# CONFIG_MBEDTLS_SSL_CONTEXT_SERIALIZATION is not set
+CONFIG_MBEDTLS_SSL_KEEP_PEER_CERTIFICATE=y
+# end of mbedTLS v2.28.x related
+
+#
+# Certificate Bundle
+#
+CONFIG_MBEDTLS_CERTIFICATE_BUNDLE=y
+CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_FULL=y
+# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_CMN is not set
+# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_NONE is not set
+# CONFIG_MBEDTLS_CUSTOM_CERTIFICATE_BUNDLE is not set
+CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_MAX_CERTS=200
+# end of Certificate Bundle
+
+# CONFIG_MBEDTLS_ECP_RESTARTABLE is not set
+# CONFIG_MBEDTLS_CMAC_C is not set
+CONFIG_MBEDTLS_HARDWARE_AES=y
+CONFIG_MBEDTLS_AES_USE_INTERRUPT=y
+CONFIG_MBEDTLS_HARDWARE_MPI=y
+CONFIG_MBEDTLS_HARDWARE_SHA=y
+CONFIG_MBEDTLS_ROM_MD5=y
+# CONFIG_MBEDTLS_ATCA_HW_ECDSA_SIGN is not set
+# CONFIG_MBEDTLS_ATCA_HW_ECDSA_VERIFY is not set
+CONFIG_MBEDTLS_HAVE_TIME=y
+# CONFIG_MBEDTLS_HAVE_TIME_DATE is not set
+CONFIG_MBEDTLS_ECDSA_DETERMINISTIC=y
+CONFIG_MBEDTLS_SHA512_C=y
+CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT=y
+# CONFIG_MBEDTLS_TLS_SERVER_ONLY is not set
+# CONFIG_MBEDTLS_TLS_CLIENT_ONLY is not set
+# CONFIG_MBEDTLS_TLS_DISABLED is not set
+CONFIG_MBEDTLS_TLS_SERVER=y
+CONFIG_MBEDTLS_TLS_CLIENT=y
+CONFIG_MBEDTLS_TLS_ENABLED=y
+
+#
+# TLS Key Exchange Methods
+#
+# CONFIG_MBEDTLS_PSK_MODES is not set
+CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y
+CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA=y
+CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y
+CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y
+CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y
+CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA=y
+CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y
+# end of TLS Key Exchange Methods
+
+CONFIG_MBEDTLS_SSL_RENEGOTIATION=y
+# CONFIG_MBEDTLS_SSL_PROTO_SSL3 is not set
+CONFIG_MBEDTLS_SSL_PROTO_TLS1=y
+CONFIG_MBEDTLS_SSL_PROTO_TLS1_1=y
+CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y
+# CONFIG_MBEDTLS_SSL_PROTO_GMTSSL1_1 is not set
+# CONFIG_MBEDTLS_SSL_PROTO_DTLS is not set
+CONFIG_MBEDTLS_SSL_ALPN=y
+CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS=y
+CONFIG_MBEDTLS_X509_CHECK_KEY_USAGE=y
+CONFIG_MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE=y
+CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS=y
+
+#
+# Symmetric Ciphers
+#
+CONFIG_MBEDTLS_AES_C=y
+# CONFIG_MBEDTLS_CAMELLIA_C is not set
+# CONFIG_MBEDTLS_DES_C is not set
+CONFIG_MBEDTLS_RC4_DISABLED=y
+# CONFIG_MBEDTLS_RC4_ENABLED_NO_DEFAULT is not set
+# CONFIG_MBEDTLS_RC4_ENABLED is not set
+# CONFIG_MBEDTLS_BLOWFISH_C is not set
+# CONFIG_MBEDTLS_XTEA_C is not set
+CONFIG_MBEDTLS_CCM_C=y
+CONFIG_MBEDTLS_GCM_C=y
+# CONFIG_MBEDTLS_NIST_KW_C is not set
+# end of Symmetric Ciphers
+
+# CONFIG_MBEDTLS_RIPEMD160_C is not set
+
+#
+# Certificates
+#
+CONFIG_MBEDTLS_PEM_PARSE_C=y
+CONFIG_MBEDTLS_PEM_WRITE_C=y
+CONFIG_MBEDTLS_X509_CRL_PARSE_C=y
+CONFIG_MBEDTLS_X509_CSR_PARSE_C=y
+# end of Certificates
+
+CONFIG_MBEDTLS_ECP_C=y
+CONFIG_MBEDTLS_ECDH_C=y
+CONFIG_MBEDTLS_ECDSA_C=y
+# CONFIG_MBEDTLS_ECJPAKE_C is not set
+CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED=y
+CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED=y
+CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y
+CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED=y
+CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED=y
+CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED=y
+CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED=y
+CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED=y
+CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED=y
+CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED=y
+CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED=y
+CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED=y
+CONFIG_MBEDTLS_ECP_NIST_OPTIM=y
+# CONFIG_MBEDTLS_POLY1305_C is not set
+# CONFIG_MBEDTLS_CHACHA20_C is not set
+# CONFIG_MBEDTLS_HKDF_C is not set
+# CONFIG_MBEDTLS_THREADING_C is not set
+# CONFIG_MBEDTLS_LARGE_KEY_SOFTWARE_MPI is not set
+# CONFIG_MBEDTLS_SECURITY_RISKS is not set
+# end of mbedTLS
+
+#
+# mDNS
+#
+CONFIG_MDNS_MAX_SERVICES=10
+CONFIG_MDNS_TASK_PRIORITY=1
+CONFIG_MDNS_TASK_STACK_SIZE=4096
+# CONFIG_MDNS_TASK_AFFINITY_NO_AFFINITY is not set
+CONFIG_MDNS_TASK_AFFINITY_CPU0=y
+# CONFIG_MDNS_TASK_AFFINITY_CPU1 is not set
+CONFIG_MDNS_TASK_AFFINITY=0x0
+CONFIG_MDNS_SERVICE_ADD_TIMEOUT_MS=2000
+# CONFIG_MDNS_STRICT_MODE is not set
+CONFIG_MDNS_TIMER_PERIOD_MS=100
+# CONFIG_MDNS_NETWORKING_SOCKET is not set
+CONFIG_MDNS_MULTIPLE_INSTANCE=y
+# end of mDNS
+
+#
+# ESP-MQTT Configurations
+#
+CONFIG_MQTT_PROTOCOL_311=y
+CONFIG_MQTT_TRANSPORT_SSL=y
+CONFIG_MQTT_TRANSPORT_WEBSOCKET=y
+CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE=y
+# CONFIG_MQTT_MSG_ID_INCREMENTAL is not set
+# CONFIG_MQTT_SKIP_PUBLISH_IF_DISCONNECTED is not set
+# CONFIG_MQTT_REPORT_DELETED_MESSAGES is not set
+# CONFIG_MQTT_USE_CUSTOM_CONFIG is not set
+# CONFIG_MQTT_TASK_CORE_SELECTION_ENABLED is not set
+# CONFIG_MQTT_CUSTOM_OUTBOX is not set
+# end of ESP-MQTT Configurations
+
+#
+# Newlib
+#
+CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y
+# CONFIG_NEWLIB_STDOUT_LINE_ENDING_LF is not set
+# CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR is not set
+# CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF is not set
+# CONFIG_NEWLIB_STDIN_LINE_ENDING_LF is not set
+CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y
+# CONFIG_NEWLIB_NANO_FORMAT is not set
+# end of Newlib
+
+#
+# NVS
+#
+# CONFIG_NVS_ASSERT_ERROR_CHECK is not set
+# end of NVS
+
+#
+# OpenSSL
+#
+# CONFIG_OPENSSL_DEBUG is not set
+CONFIG_OPENSSL_ERROR_STACK=y
+# CONFIG_OPENSSL_ASSERT_DO_NOTHING is not set
+CONFIG_OPENSSL_ASSERT_EXIT=y
+# end of OpenSSL
+
+#
+# OpenThread
+#
+# CONFIG_OPENTHREAD_ENABLED is not set
+# end of OpenThread
+
+#
+# PThreads
+#
+CONFIG_PTHREAD_TASK_PRIO_DEFAULT=5
+CONFIG_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072
+CONFIG_PTHREAD_STACK_MIN=768
+CONFIG_PTHREAD_DEFAULT_CORE_NO_AFFINITY=y
+# CONFIG_PTHREAD_DEFAULT_CORE_0 is not set
+# CONFIG_PTHREAD_DEFAULT_CORE_1 is not set
+CONFIG_PTHREAD_TASK_CORE_DEFAULT=-1
+CONFIG_PTHREAD_TASK_NAME_DEFAULT="pthread"
+# end of PThreads
+
+#
+# SPI Flash driver
+#
+# CONFIG_SPI_FLASH_VERIFY_WRITE is not set
+# CONFIG_SPI_FLASH_ENABLE_COUNTERS is not set
+CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y
+# CONFIG_SPI_FLASH_ROM_IMPL is not set
+CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS=y
+# CONFIG_SPI_FLASH_DANGEROUS_WRITE_FAILS is not set
+# CONFIG_SPI_FLASH_DANGEROUS_WRITE_ALLOWED is not set
+# CONFIG_SPI_FLASH_USE_LEGACY_IMPL is not set
+# CONFIG_SPI_FLASH_SHARE_SPI1_BUS is not set
+# CONFIG_SPI_FLASH_BYPASS_BLOCK_ERASE is not set
+CONFIG_SPI_FLASH_YIELD_DURING_ERASE=y
+CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS=20
+CONFIG_SPI_FLASH_ERASE_YIELD_TICKS=1
+CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE=8192
+# CONFIG_SPI_FLASH_SIZE_OVERRIDE is not set
+# CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED is not set
+# CONFIG_SPI_FLASH_OVERRIDE_CHIP_DRIVER_LIST is not set
+
+#
+# Auto-detect flash chips
+#
+CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP=y
+CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP=y
+CONFIG_SPI_FLASH_SUPPORT_GD_CHIP=y
+CONFIG_SPI_FLASH_SUPPORT_WINBOND_CHIP=y
+# CONFIG_SPI_FLASH_SUPPORT_BOYA_CHIP is not set
+# CONFIG_SPI_FLASH_SUPPORT_TH_CHIP is not set
+CONFIG_SPI_FLASH_SUPPORT_MXIC_OPI_CHIP=y
+# end of Auto-detect flash chips
+
+CONFIG_SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE=y
+# end of SPI Flash driver
+
+#
+# SPIFFS Configuration
+#
+CONFIG_SPIFFS_MAX_PARTITIONS=3
+
+#
+# SPIFFS Cache Configuration
+#
+CONFIG_SPIFFS_CACHE=y
+CONFIG_SPIFFS_CACHE_WR=y
+# CONFIG_SPIFFS_CACHE_STATS is not set
+# end of SPIFFS Cache Configuration
+
+CONFIG_SPIFFS_PAGE_CHECK=y
+CONFIG_SPIFFS_GC_MAX_RUNS=10
+# CONFIG_SPIFFS_GC_STATS is not set
+CONFIG_SPIFFS_PAGE_SIZE=256
+CONFIG_SPIFFS_OBJ_NAME_LEN=32
+# CONFIG_SPIFFS_FOLLOW_SYMLINKS is not set
+CONFIG_SPIFFS_USE_MAGIC=y
+CONFIG_SPIFFS_USE_MAGIC_LENGTH=y
+CONFIG_SPIFFS_META_LENGTH=4
+CONFIG_SPIFFS_USE_MTIME=y
+
+#
+# Debug Configuration
+#
+# CONFIG_SPIFFS_DBG is not set
+# CONFIG_SPIFFS_API_DBG is not set
+# CONFIG_SPIFFS_GC_DBG is not set
+# CONFIG_SPIFFS_CACHE_DBG is not set
+# CONFIG_SPIFFS_CHECK_DBG is not set
+# CONFIG_SPIFFS_TEST_VISUALISATION is not set
+# end of Debug Configuration
+# end of SPIFFS Configuration
+
+#
+# TCP Transport
+#
+
+#
+# Websocket
+#
+CONFIG_WS_TRANSPORT=y
+CONFIG_WS_BUFFER_SIZE=1024
+# end of Websocket
+# end of TCP Transport
+
+#
+# TinyUSB Stack
+#
+CONFIG_TINYUSB=y
+CONFIG_TINYUSB_DEBUG_LEVEL=0
+
+#
+# TinyUSB task configuration
+#
+# CONFIG_TINYUSB_NO_DEFAULT_TASK is not set
+CONFIG_TINYUSB_TASK_PRIORITY=7
+CONFIG_TINYUSB_TASK_STACK_SIZE=4096
+# end of TinyUSB task configuration
+
+#
+# Descriptor configuration
+#
+CONFIG_TINYUSB_DESC_USE_ESPRESSIF_VID=y
+CONFIG_TINYUSB_DESC_USE_DEFAULT_PID=y
+CONFIG_TINYUSB_DESC_BCD_DEVICE=0x0100
+CONFIG_TINYUSB_DESC_MANUFACTURER_STRING="Espressif Systems"
+CONFIG_TINYUSB_DESC_PRODUCT_STRING="Espressif Device"
+CONFIG_TINYUSB_DESC_SERIAL_STRING="123456"
+CONFIG_TINYUSB_DESC_CDC_STRING="Espressif CDC Device"
+# end of Descriptor configuration
+
+#
+# Massive Storage Class (MSC)
+#
+# CONFIG_TINYUSB_MSC_ENABLED is not set
+# end of Massive Storage Class (MSC)
+
+#
+# Communication Device Class (CDC)
+#
+CONFIG_TINYUSB_CDC_ENABLED=y
+CONFIG_TINYUSB_CDC_RX_BUFSIZE=64
+CONFIG_TINYUSB_CDC_TX_BUFSIZE=64
+# end of Communication Device Class (CDC)
+# end of TinyUSB Stack
+
+#
+# Unity unit testing library
+#
+CONFIG_UNITY_ENABLE_FLOAT=y
+CONFIG_UNITY_ENABLE_DOUBLE=y
+# CONFIG_UNITY_ENABLE_64BIT is not set
+# CONFIG_UNITY_ENABLE_COLOR is not set
+CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y
+# CONFIG_UNITY_ENABLE_FIXTURE is not set
+# CONFIG_UNITY_ENABLE_BACKTRACE_ON_FAIL is not set
+# end of Unity unit testing library
+
+#
+# USB-OTG
+#
+CONFIG_USB_OTG_SUPPORTED=y
+CONFIG_USB_HOST_CONTROL_TRANSFER_MAX_SIZE=256
+CONFIG_USB_HOST_HW_BUFFER_BIAS_BALANCED=y
+# CONFIG_USB_HOST_HW_BUFFER_BIAS_IN is not set
+# CONFIG_USB_HOST_HW_BUFFER_BIAS_PERIODIC_OUT is not set
+
+#
+# Root Hub configuration
+#
+CONFIG_USB_HOST_DEBOUNCE_DELAY_MS=250
+CONFIG_USB_HOST_RESET_HOLD_MS=30
+CONFIG_USB_HOST_RESET_RECOVERY_MS=30
+CONFIG_USB_HOST_SET_ADDR_RECOVERY_MS=10
+# end of Root Hub configuration
+# end of USB-OTG
+
+#
+# Virtual file system
+#
+CONFIG_VFS_SUPPORT_IO=y
+CONFIG_VFS_SUPPORT_DIR=y
+CONFIG_VFS_SUPPORT_SELECT=y
+CONFIG_VFS_SUPPRESS_SELECT_DEBUG_OUTPUT=y
+CONFIG_VFS_SUPPORT_TERMIOS=y
+
+#
+# Host File System I/O (Semihosting)
+#
+CONFIG_VFS_SEMIHOSTFS_MAX_MOUNT_POINTS=1
+# end of Host File System I/O (Semihosting)
+# end of Virtual file system
+
+#
+# Wear Levelling
+#
+# CONFIG_WL_SECTOR_SIZE_512 is not set
+CONFIG_WL_SECTOR_SIZE_4096=y
+CONFIG_WL_SECTOR_SIZE=4096
+# end of Wear Levelling
+
+#
+# Wi-Fi Provisioning Manager
+#
+CONFIG_WIFI_PROV_SCAN_MAX_ENTRIES=16
+CONFIG_WIFI_PROV_AUTOSTOP_TIMEOUT=30
+# CONFIG_WIFI_PROV_BLE_FORCE_ENCRYPTION is not set
+# end of Wi-Fi Provisioning Manager
+
+#
+# Supplicant
+#
+CONFIG_WPA_MBEDTLS_CRYPTO=y
+# CONFIG_WPA_WAPI_PSK is not set
+# CONFIG_WPA_SUITE_B_192 is not set
+# CONFIG_WPA_DEBUG_PRINT is not set
+# CONFIG_WPA_TESTING_OPTIONS is not set
+# CONFIG_WPA_WPS_STRICT is not set
+# CONFIG_WPA_11KV_SUPPORT is not set
+# CONFIG_WPA_MBO_SUPPORT is not set
+# CONFIG_WPA_DPP_SUPPORT is not set
+# end of Supplicant
+# end of Component config
+
+#
+# Compatibility options
+#
+# CONFIG_LEGACY_INCLUDE_COMMON_HEADERS is not set
+# end of Compatibility options
+
+# Deprecated options for backward compatibility
+CONFIG_TOOLPREFIX="xtensa-esp32-elf-"
+# CONFIG_LOG_BOOTLOADER_LEVEL_NONE is not set
+# CONFIG_LOG_BOOTLOADER_LEVEL_ERROR is not set
+# CONFIG_LOG_BOOTLOADER_LEVEL_WARN is not set
+CONFIG_LOG_BOOTLOADER_LEVEL_INFO=y
+# CONFIG_LOG_BOOTLOADER_LEVEL_DEBUG is not set
+# CONFIG_LOG_BOOTLOADER_LEVEL_VERBOSE is not set
+CONFIG_LOG_BOOTLOADER_LEVEL=3
+# CONFIG_APP_ROLLBACK_ENABLE is not set
+# CONFIG_FLASH_ENCRYPTION_ENABLED is not set
+# CONFIG_FLASHMODE_QIO is not set
+# CONFIG_FLASHMODE_QOUT is not set
+CONFIG_FLASHMODE_DIO=y
+# CONFIG_FLASHMODE_DOUT is not set
+# CONFIG_MONITOR_BAUD_9600B is not set
+# CONFIG_MONITOR_BAUD_57600B is not set
+CONFIG_MONITOR_BAUD_115200B=y
+# CONFIG_MONITOR_BAUD_230400B is not set
+# CONFIG_MONITOR_BAUD_921600B is not set
+# CONFIG_MONITOR_BAUD_2MB is not set
+# CONFIG_MONITOR_BAUD_OTHER is not set
+CONFIG_MONITOR_BAUD_OTHER_VAL=115200
+CONFIG_MONITOR_BAUD=115200
+CONFIG_COMPILER_OPTIMIZATION_LEVEL_DEBUG=y
+# CONFIG_COMPILER_OPTIMIZATION_LEVEL_RELEASE is not set
+# CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED is not set
+# CONFIG_OPTIMIZATION_ASSERTIONS_SILENT is not set
+CONFIG_OPTIMIZATION_ASSERTIONS_DISABLED=y
+CONFIG_OPTIMIZATION_ASSERTION_LEVEL=0
+# CONFIG_CXX_EXCEPTIONS is not set
+CONFIG_STACK_CHECK_NONE=y
+# CONFIG_STACK_CHECK_NORM is not set
+# CONFIG_STACK_CHECK_STRONG is not set
+# CONFIG_STACK_CHECK_ALL is not set
+# CONFIG_WARN_WRITE_STRINGS is not set
+# CONFIG_DISABLE_GCC8_WARNINGS is not set
+# CONFIG_ESP32_APPTRACE_DEST_TRAX is not set
+CONFIG_ESP32_APPTRACE_DEST_NONE=y
+CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y
+CONFIG_ADC2_DISABLE_DAC=y
+# CONFIG_EVENT_LOOP_PROFILING is not set
+CONFIG_POST_EVENTS_FROM_ISR=y
+CONFIG_POST_EVENTS_FROM_IRAM_ISR=y
+CONFIG_ESP_SYSTEM_PD_FLASH=y
+CONFIG_ESP32C3_LIGHTSLEEP_GPIO_RESET_WORKAROUND=y
+CONFIG_IPC_TASK_STACK_SIZE=1024
+CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y
+# CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION is not set
+CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20
+CONFIG_ESP32_PHY_MAX_TX_POWER=20
+# CONFIG_ESP32_REDUCE_PHY_TX_POWER is not set
+CONFIG_ESP_SYSTEM_PM_POWER_DOWN_CPU=y
+# CONFIG_ESP32S2_PANIC_PRINT_HALT is not set
+CONFIG_ESP32S2_PANIC_PRINT_REBOOT=y
+# CONFIG_ESP32S2_PANIC_SILENT_REBOOT is not set
+# CONFIG_ESP32S2_PANIC_GDBSTUB is not set
+CONFIG_ESP32S2_ALLOW_RTC_FAST_MEM_AS_HEAP=y
+CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32
+CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304
+CONFIG_MAIN_TASK_STACK_SIZE=3584
+CONFIG_CONSOLE_UART_DEFAULT=y
+# CONFIG_CONSOLE_UART_CUSTOM is not set
+# CONFIG_ESP_CONSOLE_UART_NONE is not set
+CONFIG_CONSOLE_UART=y
+CONFIG_CONSOLE_UART_NUM=0
+CONFIG_CONSOLE_UART_BAUDRATE=115200
+CONFIG_INT_WDT=y
+CONFIG_INT_WDT_TIMEOUT_MS=300
+CONFIG_INT_WDT_CHECK_CPU1=y
+CONFIG_TASK_WDT=y
+# CONFIG_TASK_WDT_PANIC is not set
+CONFIG_TASK_WDT_TIMEOUT_S=5
+CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y
+CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1=y
+# CONFIG_ESP32_DEBUG_STUBS_ENABLE is not set
+CONFIG_TIMER_TASK_STACK_SIZE=3584
+# CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH is not set
+# CONFIG_ESP32_ENABLE_COREDUMP_TO_UART is not set
+CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE=y
+CONFIG_MB_MASTER_TIMEOUT_MS_RESPOND=150
+CONFIG_MB_MASTER_DELAY_MS_CONVERT=200
+CONFIG_MB_QUEUE_LENGTH=20
+CONFIG_MB_SERIAL_TASK_STACK_SIZE=4096
+CONFIG_MB_SERIAL_BUF_SIZE=256
+CONFIG_MB_SERIAL_TASK_PRIO=10
+CONFIG_MB_CONTROLLER_SLAVE_ID_SUPPORT=y
+CONFIG_MB_CONTROLLER_SLAVE_ID=0x00112233
+CONFIG_MB_CONTROLLER_NOTIFY_TIMEOUT=20
+CONFIG_MB_CONTROLLER_NOTIFY_QUEUE_SIZE=20
+CONFIG_MB_CONTROLLER_STACK_SIZE=4096
+CONFIG_MB_EVENT_QUEUE_TIMEOUT=20
+# CONFIG_MB_TIMER_PORT_ENABLED is not set
+# CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK is not set
+CONFIG_TIMER_TASK_PRIORITY=1
+CONFIG_TIMER_TASK_STACK_DEPTH=2048
+CONFIG_TIMER_QUEUE_LENGTH=10
+# CONFIG_L2_TO_L3_COPY is not set
+# CONFIG_USE_ONLY_LWIP_SELECT is not set
+CONFIG_ESP_GRATUITOUS_ARP=y
+CONFIG_GARP_TMR_INTERVAL=60
+CONFIG_TCPIP_RECVMBOX_SIZE=32
+CONFIG_TCP_MAXRTX=12
+CONFIG_TCP_SYNMAXRTX=12
+CONFIG_TCP_MSS=1440
+CONFIG_TCP_MSL=60000
+CONFIG_TCP_SND_BUF_DEFAULT=5744
+CONFIG_TCP_WND_DEFAULT=5744
+CONFIG_TCP_RECVMBOX_SIZE=6
+CONFIG_TCP_QUEUE_OOSEQ=y
+# CONFIG_ESP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES is not set
+CONFIG_TCP_OVERSIZE_MSS=y
+# CONFIG_TCP_OVERSIZE_QUARTER_MSS is not set
+# CONFIG_TCP_OVERSIZE_DISABLE is not set
+CONFIG_UDP_RECVMBOX_SIZE=6
+CONFIG_TCPIP_TASK_STACK_SIZE=3072
+# CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY is not set
+CONFIG_TCPIP_TASK_AFFINITY_CPU0=y
+# CONFIG_TCPIP_TASK_AFFINITY_CPU1 is not set
+CONFIG_TCPIP_TASK_AFFINITY=0x0
+# CONFIG_PPP_SUPPORT is not set
+CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5
+CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072
+CONFIG_ESP32_PTHREAD_STACK_MIN=768
+CONFIG_ESP32_DEFAULT_PTHREAD_CORE_NO_AFFINITY=y
+# CONFIG_ESP32_DEFAULT_PTHREAD_CORE_0 is not set
+# CONFIG_ESP32_DEFAULT_PTHREAD_CORE_1 is not set
+CONFIG_ESP32_PTHREAD_TASK_CORE_DEFAULT=-1
+CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT="pthread"
+CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS=y
+# CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_FAILS is not set
+# CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED is not set
+CONFIG_USB_ENABLED=y
+CONFIG_USB_DEBUG_LEVEL=0
+# CONFIG_USB_DO_NOT_CREATE_TASK is not set
+CONFIG_USB_TASK_PRIORITY=7
+CONFIG_USB_DESC_USE_ESPRESSIF_VID=y
+CONFIG_USB_DESC_USE_DEFAULT_PID=y
+CONFIG_USB_DESC_BCDDEVICE=0x0100
+CONFIG_USB_DESC_MANUFACTURER_STRING="Espressif Systems"
+CONFIG_USB_DESC_PRODUCT_STRING="Espressif Device"
+CONFIG_USB_DESC_SERIAL_STRING="123456"
+CONFIG_USB_DESC_CDC_STRING="Espressif CDC Device"
+# CONFIG_USB_MSC_ENABLED is not set
+CONFIG_USB_CDC_ENABLED=y
+CONFIG_USB_CDC_RX_BUFSIZE=64
+CONFIG_USB_CDC_TX_BUFSIZE=64
+CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT=y
+CONFIG_SUPPORT_TERMIOS=y
+CONFIG_SEMIHOSTFS_MAX_MOUNT_POINTS=1
+# End of deprecated options