Implementation of a 32-bit RISC-V CPU core in SystemVerilog
- RV32I Base Integer Instructions
- Single-cycle CPU implementation
- Implement on FPGA (OrangeCrab?)
- Pipelining
- Add an ML accelerator
-
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32-bit RISC-V CPU core in SystemVerilog
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hallofstairs/risc-v-core
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32-bit RISC-V CPU core in SystemVerilog
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