D-Flip-Flop, Edge-Detection

[PaulKappmeyer]

So, I was trying to build some memory-units (SR-Latch, D-Latch) and right now I am struggling with a D-Flip-Flop.
First of all, I know that I can use the build-in ones, but I am trying to build one from basic logic-gates (just for fun).
I tried to build an edge-detection with an And-Gate and an Inverter-Gate. This works – in the sense of producing a short high pulse – but now my Nor-Gates are oscillating.
I also tried the single gate step mode, in which I can follow the short pulse and see the oscillation, but unfortunately, I cannot find a solution to that.

So my question is: What is wrong with the circuit? Or is it just not possible to build such circuit?

Btw. very nice tool, please keep up!

D-Flip-Flop.dig.txt

[hneemann]

It is possible to build an edge-controlled D-FF in this way. An example is included.
If you use a single inverter and an And gate, the pulse is too short. If you use the single gate mode, you can see why 😄

If you use three inverters in a row, the pulse will be longer and it will work.

[PaulKappmeyer]

Thank you very much! :)

[jongena]

Hello, I am interested in this case, but cannot find the example that Mr. Neemann mentions
Also, I tried the single gate mode ... but as I am not so much familiar with all this... how should I see the that some signals are too short ?

Can you explain or illustrate ?

Thank you !

[hneemann]

You can find an example in examples/sequential/D-T.dig.

If only one inverter is used, the Nor gates lose their switching pulse even before both gates have switched. The change of a RS-FF takes two gate propagation times, because two gates have to switch one after the other.
However, the switching pulse lasts only one gate propagation time if only one inverter is used.

[jongena]

Many thanks for the reply.