CHANGELOG.md

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• Added LogicNet, inOuts, and TriStateBuffer to enable multi-directional wires, ports, and drivers. Includes support for "wire-only" operations supporting multiple drivers.
• Deprecated CustomSystemVerilog in favor of SystemVerilog, which has similar functionality but supports inOut ports, and collapses all ports into a single ports argument, as well as some other new features like custom definitions and parameter passthroughs.
• Breaking: ExternalSystemVerilogModule and InlineSystemVerilog now extend SystemVerilog instead of CustomSystemVerilog, meaning the instantiationVerilog API arguments have been modified.
• Breaking: Increased minimum Dart SDK version to 3.0.0.
• Breaking: Interface.connectIO has an additional optional named argument for inOutTags. Implementations of Interface which override connectIO will need to be updated.
• Fixed a bug where expressionlessInputs may not have been honored in non-inline custom SystemVerilog modules.
• Fixed a bug where in some cases an xor between two LogicValues could cause an exception due to a false width mismatch.
• Added better checking, error handling, and message when module hierarchy cannot be properly resolved (e.g. self-containing modules, modules within multiple hierarchies).
• Breaking: Updated APIs for Synthesizer.synthesize and down the stack to use a Function to calculate the instance type of a module instead of a Map look-up table.
• Added srcConnections API to Logic to make it easier to trace drivers of subtypes of Logic which contain multiple drivers.
• Breaking: Const constructor updated so that specified width takes precedence over the inherent width of a provided LogicValue val.

0.5.3

• Added beta version of the ROHD DevTools Extension to aid in ROHD hardware debug by displaying module hierarchy and signal information visually and interactively (#435).
• Added absolute value (abs()) to both Logic and LogicValue (#442).
• Added assignSubset for performing an assignment on a subset of a LogicArray (#456).
• Made conditional assignments more optimistic with partially invalid values (#459).
• Upgraded the simulator to support cancelling actions and registering actions at the current time (#468).
• Fixed a bug where SystemVerilog generation could mishandle naming collisions between Logics and LogicArrays (#473).
• Added new checks to help catch SystemVerilog generation issues in cases where built-in functionality is overridden.

0.5.2

• Added APIs for accessing indices of a List<Logic> using another Logic: Logic.selectFrom and List<Logic>.selectIndex (#438).
• Added/fixed support for compiling ROHD to JavaScript via bug fixes, compile-time arithmetic precision consideration, and testing (#445).
• Added isZero to LogicValue.
• Improved Pipeline abstraction via bug fixes, better error checking, improved documentation, and new APIs (#447).
• Improved performance of construction of Combinational.ssa (#443).
• Updated Simulator.endSimulation API to return a Future which completes once the simulation has ended (#455).
• Fixed bugs where certain non-synthesizable function calls on LogicStructures (e.g. for verification) could add additional hardware (which did not affect functionality) and also cause unexpected behavior on previousValue (#457).
• Fixed bugs where certain APIs on Logic (e.g. changed, previousValue) could have incorrect behavior after a Simulator.reset (#458).
• Fixed a bug where LogicValue.clog2 was inaccurate in rare scenarios.
• Fixed a bug that caused a crash when comparing certain LogicValues.
• Fixed a bug where conversions between BigInts and LogicValues could result in incorrect arithmetic operations.
• Fixed a bug where FiniteStateMachine-generated mermaid diagrams were missing "default next state" cases (#454).
• Allowed generated SystemVerilog to contain assignments to z (floating) if explicitly connected to a constant z (#441).

0.5.1

• Fixed bugs and improved controllability around naming of internal signals and collapsing of inlineable functionality, leading to significantly more readable generated SystemVerilog (#439).
• Fixed a bug where identical module definitions with different reserved definition names would merge incorrectly in generated outputs(#345).
• Improved organization of port and internal signal declarations in generated outputs.
• Fixed bugs where generated SystemVerilog could flag lint issues due to unsafe truncation of signals in cases like + and << (#423).

0.5.0

• Added LogicArray for N-dimensional packed and unpacked (and mixed) arrays. Added LogicStructure for grouping sets of related signals together in a convenient way (#375).
• Added a ConditionalGroup which can group a collection of other Conditionals into one Conditional object.
• Breaking: some APIs which previously returned ConditionalAssign now return a Conditional, such as the < operator for Logic.
• Updated LogicValue.of which now accepts a dynamic input and tries its best to build what you're looking for. Added LogicValue.ofIterable to replace the old LogicValue.of.
• Added previousValue to Logic to make testbench and modelling easier for things like clock edge sampling.
• Breaking: Modified the way Combinational sensitivities are implemented to improve performance and prevent some types of simulation/synthesis mismatch bugs. Added Combinational.ssa as a method to safely build procedural logic. Combinational will now throw fatal exceptions in cases of "write after read" violations. (#344)
• Deprecated getReceivers, getDrivers, and getConditionals in always blocks like Combinational and Sequential in favor of simpler and more efficient APIs receivers, drivers, and conditionals.
• Breaking: shorthand notation APIs for incr, decr, mulAssign, and divAssign have been modified.
• Replaced IfBlock with If.block (deprecated IfBlock).
• Replaced StateMachine with FiniteStateMachine (deprecated StateMachine).
• Added support for multi-trigger (e.g. async reset) to abstractions like FiniteStateMachine and Pipeline. Deprecated clk on FiniteStateMachine and Pipeline.
• Added ability to generate an FSM diagram in mermaid from a FiniteStateMachine.
• Added PairInterface to make it easier to build and use simple Interfaces.
• Breaking: connectIO in Interface now accepts Iterables instead of only Sets.
• Improved numerous Exceptions throughout to provide more specific information about errors and make them easier to catch and handle.
• Upgraded some operations to avoid generating unnecessary hardware and SystemVerilog when configured to leave a signal unchanged (e.g. getRange, swizzle, slice, etc.).
• Added extension to generate randomized LogicValues from a Random.
• Added replication operations to LogicValue and Logic.
• Added equalsWithDontCare to LogicValue for comparisons where invalid bits are "don't-care".
• Improved timestamps in generated outputs to make timezones apparent.
• Added the flop function to construct FlipFlops in an easier way.
• Added the cases function to construct simple Case statements in an easier way.
• Added APIs for configuring reset and reset values in Sequential and flip flops.
• Added APIs for adding an enable to flip flops.
• Implemented a variety of performance enhancements for both build and simulation.
• Added tryInput and tryOutput to Module and tryPort to Interface to more easily handle conditionally present ports by leveraging Dart's null safety by returning null if the port does not exist (instead of an exception).
• Added gt and gte to Logic to make APIs more consistent.
• Added clog2 to LogicValue.
• Added neq and pow to both Logic and LogicValue.
• Made LogicValue implement Comparable, enabling things like sorting.
• Enabled WaveDumper to recursively create necessary directories for specified output paths.
• Fixed a bug where ports could be created with an empty string as the name (#281).
• Fixed a bug where generated SystemVerilog for arithmetic shift-right operations would sometimes be incorrect (#295).
• Fixed a bug where SynthBuilder would not flag an error when run on a Module that hadn't yet been built (#246).
• Disallowed signals from being connected directly to themselves in a combinational loop.
• Fixed a bug where non-synthesizable deposits on undriven signals could affect the generated output SystemVerilog by inserting a non-floating constant (#254).
• Reinstated an accidentally removed exception for when signal width mismatch occurs (#311).
• Fixed a bug where indexing a constant value could generate invalid SystemVerilog.
• Fixed a bug where constants and values that could be interpreted as negative 64-bit values would sometimes generate a - sign in output SystemVerilog.
• Fixed bugs so Ifs that are illegally constructed throw an Exception (#382).
• Fixed a bug where FiniteStateMachine could create an inferred latch (#390).
• Fixed an issue where Case statements with multiple matches would throw an Exception instead of driving x on the output, which could cause spurious crashes during glitch simulation (#107).
• Fixed a number of bugs related to logical, shift, math, and comparison operations related to width and sign interpretation.
• Fixed a bug where Case and CaseZ would not use the properly edge-sampled value in Sequential blocks (#348).
• Fixed bugs where logic that is driven by floating signals would sometimes drive z instead of x on outputs (#235).

0.4.2

• Added a GitHub Codespace to the repository as a quick way to experiment with ROHD without any environment setup.
• Added Conditional operations similar to ++x (incr), --x (decr), x *= (mulAssign), and x /= (divAssign) to Logic (#141).
• Fixed a bug where generated SystemVerilog could perform index accesses on single-bit signals (#204).
• Expanded capability to construct single-Conditional more succinctly via Else.s (#225).
• Fixed a bug where sensitivities for Combinationals were excessively pessimistic (#233).
• Improved exceptions raised by Logic.put to include context on which signal was affected to help with debug (#243).
• Optimized WaveDumper to only periodically write data to the VCD file to improve performance (#242).
• Made endIndex in getRange an optional positional argument with a default value of width, enabling a more convenient method for collecting all bits from some index until the end (#228).
• Added an exception in cases where names of interface ports are invalid/unsanitary (#234).
• Upgraded the Simulator so that it would await asynchronous registered actions (#252).
• Deprecated Logic.hasValidValue and Logic.isFloating in favor of similar operations on Logic.value (#198).
• Added Logic.isIn, which generates logic computing whether the signal is equal to any values in a (optionally mixed) list of constants or other signals (#7).

0.4.1

• Fixed a bug where Modules could have invalid names in generated SystemVerilog (#138).
• Fixed a bug where Logics could have invalid names in generated SystemVerilog.
• Added a feature allowing access of an index of a Logic via another Logic (#153).
• Fixed a bug where multiple sequential driver issues might not be caught during ROHD simulation (#114).
• Improved Exceptions in ROHD with better error messages and more granular exception types to make handling easier.
• Improved generated SystemVerilog for sign extension and added capability for replication (#157).
• Fixed a bug where signal names and module instance names could collide in generated SystemVerilog (#205).
• Fixed a bug where in some cases modules might not be properly detected as sub-modules, leading to erroneous omission in generated outputs.
• Added capability to perform modulo and shift operations on Logic via a constant values (#208).
• Completed a fix for a bug where shifting a Logic by a constant would throw an exception (#170).
• Modified the mechanism by which signal propagation occurs between Logics so that connected Logics share an underlying value-holding entity (#199). One significant implication is that modifying a value of a Logic (e.g. via put or inject) will now affect the value of both downstream and upstream connected Logics instead of only downstream. This change also can significantly improve simulation performance in connection-heavy designs. Additionally, this change helps mitigate an issue where very long combinational chains of logic can hit the stack size limit (#194).
• Fixed a bug where large unsigned values on LogicValues would convert to incorrect int values (#212).
• Added an extension on BigInt to perform unsigned conversion to an int.
• Added a capability to construct some Conditional types (e.g. If) which have only a single Conditional more succinctly (#12).
• Optimized some operations in LogicValue for performance (#215).
• Added a shortcut to create a 0-width LogicValue called LogicValue.empty (#202).
• Fixed a bug where equal LogicValues could have unequal hash codes (#206). The fix also improved internal representation consistency for LogicValues, which could provide a significant performance improvement when wide values are used often.

0.4.0

• Fixed a bug where generated SystemVerilog could apply bit slicing to an expression (#163).
• Fixed a bug where constant collapsing in SystemVerilog could erroneously remove constant assignments (#159).
• Fixed a bug where Combinational could have an incomplete sensitivity list causing incorrect simulation behavior (#158).
• Significantly improved simulation performance of Combinational (#106).
• Upgraded and made lints more strict within ROHD, leading to some quality and documentation improvements.
• Added a feature allowing negative indexing to access relative to the end of a Logic or LogicValue (#99).
• Breaking: Increased minimum Dart SDK version to 2.18.0.
• Fixed a bug when parsing unsigned large binary integers (#183).
• Exposed SynthesisResults from the SynthBuilder, making it easier to generate SystemVerilog modules into independent files (#172).
• Breaking: Renamed topModuleName to definitionName in ExternalSystemVerilogModule (#169).
• Added the mux function as a shortcut for building a Mux and returning the output of it (#13).
• Deprecation: Improved naming of ports on basic gates, old port names remain accessible but deprecated for now (#135).
• Fixed list of reserved SystemVerilog keywords for sanitization (#168).

0.3.2

• Added the StateMachine abstraction for finite state machines.
• Added support for the modulo % operator.
• Added ability to register actions to be executed at the end of the simulation.
• Modified the WaveDumper to write to the .vcd file asynchronously to improve simulation performance while waveform dumping is enabled (#3)

0.3.1

• Fixed a bug (introduced in v0.3.0) where WaveDumper doesn't properly dump multi-bit values to VCD (#129).

0.3.0

• Breaking: Merged LogicValue and LogicValues into one type called LogicValue.
• Deprecation: Aligned LogicValue to Logic by renaming length to width.
• Breaking: Logic.put no longer accepts List<LogicValue>, swizzle it together instead.
• Deprecated Logic.valueInt and Logic.valueBigInt; instead use equivalent functions on Logic.value.
• Deprecated bit on both LogicValue and Logic; instead just check width.
• Added ability in LogicValue.toString to decide whether or not to include the width annotation through includeWidth argument.
• Fixed a bug related to zero-width construction of LogicValues (#90).
• Fixed a bug where generated constants in SystemVerilog had no width, which can cause issues in some cases (e.g. swizzles) (#89)
• Added capability to convert binary strings to ints with underscore separators using bin (#56).
• Added getRange and reversed on Logic and slice on LogicValue to improve consistency.
• Using slice in reverse-index order now reverses the order.
• Added the ability to extend signals (e.g. zeroExtend and signExtend) on both Logic and LogicValue (#101).
• Improved flexibility of IfBlock.
• Added withSet on LogicValue and Logic to make it easier to assign subsets of signals and values (#101).
• Fixed a bug where 0-bit signals would sometimes improperly generate 0-bit constants in generated SystemVerilog (#122).
• Added capability to reserve instance names, as well as provide and reserve definition names, for Modules and their corresponding generated outputs.

0.2.0

• Updated implementation to avoid Iterable.forEach to make debug easier.
• Added ofBool to LogicValue and LogicValues (#34).
• Breaking: updated Interface API so that getPorts returns a Map from port names to Logic signals instead of just a list, which makes it easier to work with when names are uniquified.
• Breaking: removed setPort from Interface. Use setPorts instead.
• Deprecated swizzle and rswizzle global functions and replaced them with extensions on Lists of certain types including Logic, LogicValue, and LogicValues (#70).
• Breaking: renamed ExternalModule to ExternalSystemVerilogModule since it is specifically for SystemVerilog.
• Breaking: made topModuleName a required named parameter in ExternalSystemVerilogModule to reduce confusion.
• Added simulationHasEnded bool to Simulator.
• Updated Simulator to allow for injected actions to return Futures which will be awaited.
• Fixed bug where Simulator warns about maximum simulation time when not appropriate.
• Fixed a bug where ExternalSystemVerilogModule could enter infinite recursion.
• Some improvements to SimCompare to properly check values at the end of a tick and support a wider variety of values in Vectors.
• Fixed a bug related to Sequential signal sampling where under certain scenarios, signals would pass through instead of being flopped (#79).
• Deprecated a number of from functions and replaced them with of to more closely follow Dart conventions (#72).

0.1.2

• Optimized construction of LogicValues to improve performance
• Renamed FF to Sequential (marked FF as deprecated) (breaking: removed clk signal)
• Added Sequential.multi for multi-edge-triggered blocks (#42)
• Improved exception and error messages (#64)

0.1.1

• Fix Interface.connectIO bug when no tags specified (#38)
• Fix uniquified Interface.getPorts bug (#59)

0.1.0

• The first formally versioned release of ROHD.