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Sequential outputs as clock inputs to other Sequentials trigger late in the simulator #191

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mkorbel1 opened this issue Nov 1, 2022 · 1 comment · May be fixed by #192
Open

Sequential outputs as clock inputs to other Sequentials trigger late in the simulator #191

mkorbel1 opened this issue Nov 1, 2022 · 1 comment · May be fixed by #192
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mkorbel1 commented Nov 1, 2022

Describe the bug

If the output of one Sequential is used as a clock trigger to another Sequential, the phased simulator can sometimes detect the edge and drive the outputs of the downstream Sequential one tick late.

This breaks clock dividers.

To Reproduce

Create a clock divider and connect a flop to the output of the divided clock.

Expected behavior

Divided clock properly triggers edge detection on Sequentials.

Actual behavior

Divided clock doesn't trigger edges properly, causing incorrect Sequential behavior.

Additional: Dart SDK info

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Additional: pubspec.yaml

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Additional: Context

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@mkorbel1 mkorbel1 added the bug Something isn't working label Nov 1, 2022
mkorbel1 added a commit to mkorbel1/rohd that referenced this issue Nov 1, 2022
@mkorbel1
Fix bug related to clock divider simulation, fix intel#191
9d51ac3
@mkorbel1 mkorbel1 linked a pull request Nov 1, 2022 that will close this issue
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@mkorbel1 mkorbel1 self-assigned this Nov 4, 2022
@mkorbel1 mkorbel1 mentioned this issue Feb 7, 2023
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mkorbel1 commented Dec 5, 2024

Some useful articles:
https://forum.digilent.com/topic/18256-frequency-divider-in-systemverilog/
https://zipcpu.com/blog/2017/06/02/generating-timing.html

Perhaps rather that supporting all the same things SV does, we should restrict clock division to certain approaches and just detect when it's not one of those?

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Fix bug related to clock divider simulation, fix #191 mkorbel1/rohd
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