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The current implementation (#298, #423) for handling width expansion (e.g. from adding, shift left, multiplication, etc.) avoids lint errors successfully, but still hits some lint warnings and is also somewhat ugly.
A nicer way to generate it might look something like this:
assign{cout, out}= a + b + cin;
Desired solution
Upgrade modules to generate prettier SV that avoids both lint errors and warnings
Alternatives considered
No response
Additional details
No response
The text was updated successfully, but these errors were encountered:
We should investigate free/open-source linting tools for checking and CI flows to help catch issues and prevent regressions. Perhaps verilator's linting can help? https://projectf.io/posts/verilog-lint-with-verilator/
Motivation
The current implementation (#298, #423) for handling width expansion (e.g. from adding, shift left, multiplication, etc.) avoids lint errors successfully, but still hits some lint warnings and is also somewhat ugly.
A nicer way to generate it might look something like this:
Desired solution
Upgrade modules to generate prettier SV that avoids both lint errors and warnings
Alternatives considered
No response
Additional details
No response
The text was updated successfully, but these errors were encountered: