From 4fa15f47ad73e6a45216b0f689a01c83da6447e3 Mon Sep 17 00:00:00 2001 From: liuyic00 Date: Sat, 6 Jan 2024 17:46:49 +0800 Subject: [PATCH] fix: add width of exceptionNO (#16) --- .../rvspeccore/core/spec/instset/csr/ExceptionSupport.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/rvspeccore/core/spec/instset/csr/ExceptionSupport.scala b/src/main/scala/rvspeccore/core/spec/instset/csr/ExceptionSupport.scala index 91e206c..3bc6c01 100644 --- a/src/main/scala/rvspeccore/core/spec/instset/csr/ExceptionSupport.scala +++ b/src/main/scala/rvspeccore/core/spec/instset/csr/ExceptionSupport.scala @@ -120,7 +120,7 @@ trait ExceptionSupport extends BaseCore { // 看看产生的是中断还是异常 // 仲裁之后的统一执行 尾部折叠判断优先级 val exceptionVec = WireInit(VecInit(Seq.fill(16)(false.B))) - val exceptionNO = MuxCase(0.U, Priority.excPriority.map(i => exceptionVec(i) -> i.U)) + val exceptionNO = MuxCase(0.U, Priority.excPriority.map(i => exceptionVec(i) -> i.U(5.W))) def exceptionSupportInit() = { illegalInstruction := true.B }