diff --git a/src/main/scala/rvspeccore/checker/ConnectHelper.scala b/src/main/scala/rvspeccore/checker/ConnectHelper.scala
index a19c316..74398bf 100644
--- a/src/main/scala/rvspeccore/checker/ConnectHelper.scala
+++ b/src/main/scala/rvspeccore/checker/ConnectHelper.scala
@@ -101,6 +101,8 @@ object ConnectCheckerResult extends ConnectHelper {
     checker.io.result.reg := regVec
     checker.io.result.pc  := DontCare
 
+    checker.io.result.internal := DontCare
+
     if (checker.io.mem != None) {
       val mem     = Wire(new MemSig)
       val dtlbmem = Wire(new TLBSig)
diff --git a/src/test/scala/rvspeccore/checker/ConnectHelperSpec.scala b/src/test/scala/rvspeccore/checker/ConnectHelperSpec.scala
index 20630d0..eb0521c 100644
--- a/src/test/scala/rvspeccore/checker/ConnectHelperSpec.scala
+++ b/src/test/scala/rvspeccore/checker/ConnectHelperSpec.scala
@@ -22,8 +22,6 @@ class ConnectHelperSpec extends AnyFlatSpec with ChiselScalatestTester {
     val csr = ConnectCheckerResult.makeCSRSource()
     csr := now.csr
     ConnectCheckerResult.setChecker(checker)
-
-    checker.io.result.internal := DontCare
   }
 
   it should "pass RiscvTests without mem check" in {