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cpuops.cpp
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cpuops.cpp
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/*
* Snes9x - Portable Super Nintendo Entertainment System (TM) emulator.
*
* (c) Copyright 1996 - 2001 Gary Henderson ([email protected]) and
* Jerremy Koot ([email protected])
*
* Super FX C emulator code
* (c) Copyright 1997 - 1999 Ivar ([email protected]) and
* Gary Henderson.
* Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_.
*
* DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson.
* C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_.
* C4 C code (c) Copyright 2001 Gary Henderson ([email protected]).
*
* DOS port code contains the works of other authors. See headers in
* individual files.
*
* Snes9x homepage: http://www.snes9x.com
*
* Permission to use, copy, modify and distribute Snes9x in both binary and
* source form, for non-commercial purposes, is hereby granted without fee,
* providing that this license information and copyright notice appear with
* all copies and any derived work.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event shall the authors be held liable for any damages
* arising from the use of this software.
*
* Snes9x is freeware for PERSONAL USE only. Commercial users should
* seek permission of the copyright holders first. Commercial use includes
* charging money for Snes9x or software derived from Snes9x.
*
* The copyright holders request that bug fixes and improvements to the code
* should be forwarded to them so everyone can benefit from the modifications
* in future versions.
*
* Super NES and Super Nintendo Entertainment System are trademarks of
* Nintendo Co., Limited and its subsidiary companies.
*/
/**********************************************************************************************/
/* CPU-S9xOpcodes.CPP */
/* This file contains all the opcodes */
/**********************************************************************************************/
#include "snes9x.h"
#include "memmap.h"
#include "debug.h"
#include "missing.h"
#include "apu.h"
#include "sa1.h"
START_EXTERN_C
/*
extern uint8 A1, A2, A3, A4, W1, W2, W3, W4;
extern uint8 Ans8;
extern uint16 Ans16;
extern uint32 Ans32;
extern uint8 Work8;
extern uint16 Work16;
extern uint32 Work32;
extern signed char Int8;
extern short Int16;
extern long Int32;
*/
END_EXTERN_C
#include "cpuexec.h"
#include "cpuaddr.h"
#include "cpuops.h"
#include "cpumacro.h"
#include "apu.h"
/* ADC *************************************************************************************** */
static void Op69M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = Immediate8 (reg, icpu, cpu);
ADC8 (OpAddress, reg, icpu, cpu);
}
static void Op69M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = Immediate16 (reg, icpu, cpu);
ADC16 (OpAddress, reg, icpu, cpu);
}
static void Op65M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = Direct (reg, icpu, cpu);
ADC8 (OpAddress, reg, icpu, cpu);
}
static void Op65M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = Direct (reg, icpu, cpu);
ADC16 (OpAddress, reg, icpu, cpu);
}
static void Op75M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndexedX (reg, icpu, cpu);
ADC8 (OpAddress, reg, icpu, cpu);
}
static void Op75M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndexedX (reg, icpu, cpu);
ADC16 (OpAddress, reg, icpu, cpu);
}
static void Op72M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndirect (reg, icpu, cpu);
ADC8 (OpAddress, reg, icpu, cpu);
}
static void Op72M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndirect (reg, icpu, cpu);
ADC16 (OpAddress, reg, icpu, cpu);
}
static void Op61M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndexedIndirect (reg, icpu, cpu);
ADC8 (OpAddress, reg, icpu, cpu);
}
static void Op61M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndexedIndirect (reg, icpu, cpu);
ADC16 (OpAddress, reg, icpu, cpu);
}
static void Op71M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndirectIndexed (reg, icpu, cpu);
ADC8 (OpAddress, reg, icpu, cpu);
}
static void Op71M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndirectIndexed (reg, icpu, cpu);
ADC16 (OpAddress, reg, icpu, cpu);
}
static void Op67M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndirectLong (reg, icpu, cpu);
ADC8 (OpAddress, reg, icpu, cpu);
}
static void Op67M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndirectLong (reg, icpu, cpu);
ADC16 (OpAddress, reg, icpu, cpu);
}
static void Op77M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndirectIndexedLong (reg, icpu, cpu);
ADC8 (OpAddress, reg, icpu, cpu);
}
static void Op77M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndirectIndexedLong (reg, icpu, cpu);
ADC16 (OpAddress, reg, icpu, cpu);
}
static void Op6DM1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = Absolute (reg, icpu, cpu);
ADC8 (OpAddress, reg, icpu, cpu);
}
static void Op6DM0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = Absolute (reg, icpu, cpu);
ADC16 (OpAddress, reg, icpu, cpu);
}
static void Op7DM1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = AbsoluteIndexedX (reg, icpu, cpu);
ADC8 (OpAddress, reg, icpu, cpu);
}
static void Op7DM0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = AbsoluteIndexedX (reg, icpu, cpu);
ADC16 (OpAddress, reg, icpu, cpu);
}
static void Op79M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = AbsoluteIndexedY (reg, icpu, cpu);
ADC8 (OpAddress, reg, icpu, cpu);
}
static void Op79M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = AbsoluteIndexedY (reg, icpu, cpu);
ADC16 (OpAddress, reg, icpu, cpu);
}
static void Op6FM1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = AbsoluteLong (reg, icpu, cpu);
ADC8 (OpAddress, reg, icpu, cpu);
}
static void Op6FM0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = AbsoluteLong (reg, icpu, cpu);
ADC16 (OpAddress, reg, icpu, cpu);
}
static void Op7FM1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = AbsoluteLongIndexedX (reg, icpu, cpu);
ADC8 (OpAddress, reg, icpu, cpu);
}
static void Op7FM0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = AbsoluteLongIndexedX (reg, icpu, cpu);
ADC16 (OpAddress, reg, icpu, cpu);
}
static void Op63M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = StackRelative (reg, icpu, cpu);
ADC8 (OpAddress, reg, icpu, cpu);
}
static void Op63M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = StackRelative (reg, icpu, cpu);
ADC16 (OpAddress, reg, icpu, cpu);
}
static void Op73M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = StackRelativeIndirectIndexed (reg, icpu, cpu);
ADC8 (OpAddress, reg, icpu, cpu);
}
static void Op73M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = StackRelativeIndirectIndexed (reg, icpu, cpu);
ADC16 (OpAddress, reg, icpu, cpu);
}
/**********************************************************************************************/
/* AND *************************************************************************************** */
static void Op29M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
reg->AL &= *cpu->PC++;
#ifdef VAR_CYCLES
cpu->Cycles += cpu->MemSpeed;
#endif
SETZN8 (reg->AL);
}
static void Op29M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
#ifdef FAST_LSB_WORD_ACCESS
reg->A.W &= *(uint16 *) cpu->PC;
#else
reg->A.W &= *cpu->PC + (*(cpu->PC + 1) << 8);
#endif
cpu->PC += 2;
#ifdef VAR_CYCLES
cpu->Cycles += cpu->MemSpeedx2;
#endif
SETZN16 (reg->A.W);
}
static void Op25M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = Direct (reg, icpu, cpu);
AND8 (OpAddress, reg, icpu, cpu);
}
static void Op25M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = Direct (reg, icpu, cpu);
AND16 (OpAddress, reg, icpu, cpu);
}
static void Op35M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndexedX (reg, icpu, cpu);
AND8 (OpAddress, reg, icpu, cpu);
}
static void Op35M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndexedX (reg, icpu, cpu);
AND16 (OpAddress, reg, icpu, cpu);
}
static void Op32M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndirect (reg, icpu, cpu);
AND8 (OpAddress, reg, icpu, cpu);
}
static void Op32M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndirect (reg, icpu, cpu);
AND16 (OpAddress, reg, icpu, cpu);
}
static void Op21M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndexedIndirect (reg, icpu, cpu);
AND8 (OpAddress, reg, icpu, cpu);
}
static void Op21M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndexedIndirect (reg, icpu, cpu);
AND16 (OpAddress, reg, icpu, cpu);
}
static void Op31M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndirectIndexed (reg, icpu, cpu);
AND8 (OpAddress, reg, icpu, cpu);
}
static void Op31M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndirectIndexed (reg, icpu, cpu);
AND16 (OpAddress, reg, icpu, cpu);
}
static void Op27M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndirectLong (reg, icpu, cpu);
AND8 (OpAddress, reg, icpu, cpu);
}
static void Op27M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndirectLong (reg, icpu, cpu);
AND16 (OpAddress, reg, icpu, cpu);
}
static void Op37M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndirectIndexedLong (reg, icpu, cpu);
AND8 (OpAddress, reg, icpu, cpu);
}
static void Op37M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndirectIndexedLong (reg, icpu, cpu);
AND16 (OpAddress, reg, icpu, cpu);
}
static void Op2DM1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = Absolute (reg, icpu, cpu);
AND8 (OpAddress, reg, icpu, cpu);
}
static void Op2DM0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = Absolute (reg, icpu, cpu);
AND16 (OpAddress, reg, icpu, cpu);
}
static void Op3DM1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = AbsoluteIndexedX (reg, icpu, cpu);
AND8 (OpAddress, reg, icpu, cpu);
}
static void Op3DM0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = AbsoluteIndexedX (reg, icpu, cpu);
AND16 (OpAddress, reg, icpu, cpu);
}
static void Op39M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = AbsoluteIndexedY (reg, icpu, cpu);
AND8 (OpAddress, reg, icpu, cpu);
}
static void Op39M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = AbsoluteIndexedY (reg, icpu, cpu);
AND16 (OpAddress, reg, icpu, cpu);
}
static void Op2FM1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = AbsoluteLong (reg, icpu, cpu);
AND8 (OpAddress, reg, icpu, cpu);
}
static void Op2FM0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = AbsoluteLong (reg, icpu, cpu);
AND16 (OpAddress, reg, icpu, cpu);
}
static void Op3FM1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = AbsoluteLongIndexedX (reg, icpu, cpu);
AND8 (OpAddress, reg, icpu, cpu);
}
static void Op3FM0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = AbsoluteLongIndexedX (reg, icpu, cpu);
AND16 (OpAddress, reg, icpu, cpu);
}
static void Op23M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = StackRelative (reg, icpu, cpu);
AND8 (OpAddress, reg, icpu, cpu);
}
static void Op23M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = StackRelative (reg, icpu, cpu);
AND16 (OpAddress, reg, icpu, cpu);
}
static void Op33M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = StackRelativeIndirectIndexed (reg, icpu, cpu);
AND8 (OpAddress, reg, icpu, cpu);
}
static void Op33M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = StackRelativeIndirectIndexed (reg, icpu, cpu);
AND16 (OpAddress, reg, icpu, cpu);
}
/**********************************************************************************************/
/* ASL *************************************************************************************** */
static void Op0AM1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
A_ASL8 (reg, icpu, cpu);
}
static void Op0AM0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
A_ASL16 (reg, icpu, cpu);
}
static void Op06M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = Direct (reg, icpu, cpu);
ASL8 (OpAddress, reg, icpu, cpu);
}
static void Op06M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = Direct (reg, icpu, cpu);
ASL16 (OpAddress, reg, icpu, cpu);
}
static void Op16M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndexedX (reg, icpu, cpu);
ASL8 (OpAddress, reg, icpu, cpu);
}
static void Op16M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndexedX (reg, icpu, cpu);
ASL16 (OpAddress, reg, icpu, cpu);
}
static void Op0EM1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = Absolute (reg, icpu, cpu);
ASL8 (OpAddress, reg, icpu, cpu);
}
static void Op0EM0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = Absolute (reg, icpu, cpu);
ASL16 (OpAddress, reg, icpu, cpu);
}
static void Op1EM1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = AbsoluteIndexedX (reg, icpu, cpu);
ASL8 (OpAddress, reg, icpu, cpu);
}
static void Op1EM0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = AbsoluteIndexedX (reg, icpu, cpu);
ASL16 (OpAddress, reg, icpu, cpu);
}
/**********************************************************************************************/
/* BIT *************************************************************************************** */
static void Op89M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
icpu->_Zero = reg->AL & *cpu->PC++;
#ifdef VAR_CYCLES
cpu->Cycles += cpu->MemSpeed;
#endif
}
static void Op89M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
#ifdef FAST_LSB_WORD_ACCESS
icpu->_Zero = (reg->A.W & *(uint16 *) cpu->PC) != 0;
#else
icpu->_Zero = (reg->A.W & (*cpu->PC + (*(cpu->PC + 1) << 8))) != 0;
#endif
#ifdef VAR_CYCLES
cpu->Cycles += cpu->MemSpeedx2;
#endif
cpu->PC += 2;
}
static void Op24M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = Direct (reg, icpu, cpu);
BIT8 (OpAddress, reg, icpu, cpu);
}
static void Op24M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = Direct (reg, icpu, cpu);
BIT16 (OpAddress, reg, icpu, cpu);
}
static void Op34M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndexedX (reg, icpu, cpu);
BIT8 (OpAddress, reg, icpu, cpu);
}
static void Op34M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndexedX (reg, icpu, cpu);
BIT16 (OpAddress, reg, icpu, cpu);
}
static void Op2CM1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = Absolute (reg, icpu, cpu);
BIT8 (OpAddress, reg, icpu, cpu);
}
static void Op2CM0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = Absolute (reg, icpu, cpu);
BIT16 (OpAddress, reg, icpu, cpu);
}
static void Op3CM1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = AbsoluteIndexedX (reg, icpu, cpu);
BIT8 (OpAddress, reg, icpu, cpu);
}
static void Op3CM0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = AbsoluteIndexedX (reg, icpu, cpu);
BIT16 (OpAddress, reg, icpu, cpu);
}
/**********************************************************************************************/
/* CMP *************************************************************************************** */
static void OpC9M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
int32 Int32 = (int) reg->AL - (int) *cpu->PC++;
icpu->_Carry = Int32 >= 0;
SETZN8 ((uint8) Int32);
#ifdef VAR_CYCLES
cpu->Cycles += cpu->MemSpeed;
#endif
}
static void OpC9M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
#ifdef FAST_LSB_WORD_ACCESS
int32 Int32 = (long) reg->A.W - (long) *(uint16 *) cpu->PC;
#else
int32 Int32 = (long) reg->A.W -
(long) (*cpu->PC + (*(cpu->PC + 1) << 8));
#endif
icpu->_Carry = Int32 >= 0;
SETZN16 ((uint16) Int32);
cpu->PC += 2;
#ifdef VAR_CYCLES
cpu->Cycles += cpu->MemSpeedx2;
#endif
}
static void OpC5M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = Direct (reg, icpu, cpu);
CMP8 (OpAddress, reg, icpu, cpu);
}
static void OpC5M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = Direct (reg, icpu, cpu);
CMP16 (OpAddress, reg, icpu, cpu);
}
static void OpD5M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndexedX (reg, icpu, cpu);
CMP8 (OpAddress, reg, icpu, cpu);
}
static void OpD5M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndexedX (reg, icpu, cpu);
CMP16 (OpAddress, reg, icpu, cpu);
}
static void OpD2M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndirect (reg, icpu, cpu);
CMP8 (OpAddress, reg, icpu, cpu);
}
static void OpD2M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndirect (reg, icpu, cpu);
CMP16 (OpAddress, reg, icpu, cpu);
}
static void OpC1M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndexedIndirect (reg, icpu, cpu);
CMP8 (OpAddress, reg, icpu, cpu);
}
static void OpC1M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndexedIndirect (reg, icpu, cpu);
CMP16 (OpAddress, reg, icpu, cpu);
}
static void OpD1M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndirectIndexed (reg, icpu, cpu);
CMP8 (OpAddress, reg, icpu, cpu);
}
static void OpD1M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndirectIndexed (reg, icpu, cpu);
CMP16 (OpAddress, reg, icpu, cpu);
}
static void OpC7M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndirectLong (reg, icpu, cpu);
CMP8 (OpAddress, reg, icpu, cpu);
}
static void OpC7M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndirectLong (reg, icpu, cpu);
CMP16 (OpAddress, reg, icpu, cpu);
}
static void OpD7M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndirectIndexedLong (reg, icpu, cpu);
CMP8 (OpAddress, reg, icpu, cpu);
}
static void OpD7M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndirectIndexedLong (reg, icpu, cpu);
CMP16 (OpAddress, reg, icpu, cpu);
}
static void OpCDM1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = Absolute (reg, icpu, cpu);
CMP8 (OpAddress, reg, icpu, cpu);
}
static void OpCDM0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = Absolute (reg, icpu, cpu);
CMP16 (OpAddress, reg, icpu, cpu);
}
static void OpDDM1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = AbsoluteIndexedX (reg, icpu, cpu);
CMP8 (OpAddress, reg, icpu, cpu);
}
static void OpDDM0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = AbsoluteIndexedX (reg, icpu, cpu);
CMP16 (OpAddress, reg, icpu, cpu);
}
static void OpD9M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = AbsoluteIndexedY (reg, icpu, cpu);
CMP8 (OpAddress, reg, icpu, cpu);
}
static void OpD9M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = AbsoluteIndexedY (reg, icpu, cpu);
CMP16 (OpAddress, reg, icpu, cpu);
}
static void OpCFM1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = AbsoluteLong (reg, icpu, cpu);
CMP8 (OpAddress, reg, icpu, cpu);
}
static void OpCFM0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = AbsoluteLong (reg, icpu, cpu);
CMP16 (OpAddress, reg, icpu, cpu);
}
static void OpDFM1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = AbsoluteLongIndexedX (reg, icpu, cpu);
CMP8 (OpAddress, reg, icpu, cpu);
}
static void OpDFM0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = AbsoluteLongIndexedX (reg, icpu, cpu);
CMP16 (OpAddress, reg, icpu, cpu);
}
static void OpC3M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = StackRelative (reg, icpu, cpu);
CMP8 (OpAddress, reg, icpu, cpu);
}
static void OpC3M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = StackRelative (reg, icpu, cpu);
CMP16 (OpAddress, reg, icpu, cpu);
}
static void OpD3M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = StackRelativeIndirectIndexed (reg, icpu, cpu);
CMP8 (OpAddress, reg, icpu, cpu);
}
static void OpD3M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = StackRelativeIndirectIndexed (reg, icpu, cpu);
CMP16 (OpAddress, reg, icpu, cpu);
}
/**********************************************************************************************/
/* CMX *************************************************************************************** */
static void OpE0X1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
int32 Int32 = (int) reg->XL - (int) *cpu->PC++;
icpu->_Carry = Int32 >= 0;
SETZN8 ((uint8) Int32);
#ifdef VAR_CYCLES
cpu->Cycles += cpu->MemSpeed;
#endif
}
static void OpE0X0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
#ifdef FAST_LSB_WORD_ACCESS
int32 Int32 = (long) reg->X.W - (long) *(uint16 *) cpu->PC;
#else
int32 Int32 = (long) reg->X.W -
(long) (*cpu->PC + (*(cpu->PC + 1) << 8));
#endif
icpu->_Carry = Int32 >= 0;
SETZN16 ((uint16) Int32);
cpu->PC += 2;
#ifdef VAR_CYCLES
cpu->Cycles += cpu->MemSpeedx2;
#endif
}
static void OpE4X1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = Direct (reg, icpu, cpu);
CMX8 (OpAddress, reg, icpu, cpu);
}
static void OpE4X0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = Direct (reg, icpu, cpu);
CMX16 (OpAddress, reg, icpu, cpu);
}
static void OpECX1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = Absolute (reg, icpu, cpu);
CMX8 (OpAddress, reg, icpu, cpu);
}
static void OpECX0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = Absolute (reg, icpu, cpu);
CMX16 (OpAddress, reg, icpu, cpu);
}
/**********************************************************************************************/
/* CMY *************************************************************************************** */
static void OpC0X1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
int32 Int32 = (int) reg->YL - (int) *cpu->PC++;
icpu->_Carry = Int32 >= 0;
SETZN8 ((uint8) Int32);
#ifdef VAR_CYCLES
cpu->Cycles += cpu->MemSpeed;
#endif
}
static void OpC0X0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
#ifdef FAST_LSB_WORD_ACCESS
int32 Int32 = (long) reg->Y.W - (long) *(uint16 *) cpu->PC;
#else
int32 Int32 = (long) reg->Y.W -
(long) (*cpu->PC + (*(cpu->PC + 1) << 8));
#endif
icpu->_Carry = Int32 >= 0;
SETZN16 ((uint16) Int32);
cpu->PC += 2;
#ifdef VAR_CYCLES
cpu->Cycles += cpu->MemSpeedx2;
#endif
}
static void OpC4X1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = Direct (reg, icpu, cpu);
CMY8 (OpAddress, reg, icpu, cpu);
}
static void OpC4X0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = Direct (reg, icpu, cpu);
CMY16 (OpAddress, reg, icpu, cpu);
}
static void OpCCX1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = Absolute (reg, icpu, cpu);
CMY8 (OpAddress, reg, icpu, cpu);
}
static void OpCCX0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = Absolute (reg, icpu, cpu);
CMY16 (OpAddress, reg, icpu, cpu);
}
/**********************************************************************************************/
/* DEC *************************************************************************************** */
static void Op3AM1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
A_DEC8 (reg, icpu, cpu);
}
static void Op3AM0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
A_DEC16 (reg, icpu, cpu);
}
static void OpC6M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = Direct (reg, icpu, cpu);
DEC8 (OpAddress, reg, icpu, cpu);
}
static void OpC6M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = Direct (reg, icpu, cpu);
DEC16 (OpAddress, reg, icpu, cpu);
}
static void OpD6M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndexedX (reg, icpu, cpu);
DEC8 (OpAddress, reg, icpu, cpu);
}
static void OpD6M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndexedX (reg, icpu, cpu);
DEC16 (OpAddress, reg, icpu, cpu);
}
static void OpCEM1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = Absolute (reg, icpu, cpu);
DEC8 (OpAddress, reg, icpu, cpu);
}
static void OpCEM0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = Absolute (reg, icpu, cpu);
DEC16 (OpAddress, reg, icpu, cpu);
}
static void OpDEM1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = AbsoluteIndexedX (reg, icpu, cpu);
DEC8 (OpAddress, reg, icpu, cpu);
}
static void OpDEM0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = AbsoluteIndexedX (reg, icpu, cpu);
DEC16 (OpAddress, reg, icpu, cpu);
}
/**********************************************************************************************/
/* EOR *************************************************************************************** */
static void Op49M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
reg->AL ^= *cpu->PC++;
#ifdef VAR_CYCLES
cpu->Cycles += cpu->MemSpeed;
#endif
SETZN8 (reg->AL);
}
static void Op49M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
#ifdef FAST_LSB_WORD_ACCESS
reg->A.W ^= *(uint16 *) cpu->PC;
#else
reg->A.W ^= *cpu->PC + (*(cpu->PC + 1) << 8);
#endif
cpu->PC += 2;
#ifdef VAR_CYCLES
cpu->Cycles += cpu->MemSpeedx2;
#endif
SETZN16 (reg->A.W);
}
static void Op45M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = Direct (reg, icpu, cpu);
EOR8 (OpAddress, reg, icpu, cpu);
}
static void Op45M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = Direct (reg, icpu, cpu);
EOR16 (OpAddress, reg, icpu, cpu);
}
static void Op55M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndexedX (reg, icpu, cpu);
EOR8 (OpAddress, reg, icpu, cpu);
}
static void Op55M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndexedX (reg, icpu, cpu);
EOR16 (OpAddress, reg, icpu, cpu);
}
static void Op52M1 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{
long OpAddress = DirectIndirect (reg, icpu, cpu);
EOR8 (OpAddress, reg, icpu, cpu);
}
static void Op52M0 (struct SRegisters * reg, struct SICPU * icpu, struct SCPUState * cpu)
{