diff --git a/.ccsproject b/.ccsproject new file mode 100644 index 0000000..4ccd18a --- /dev/null +++ b/.ccsproject @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/.cproject b/.cproject new file mode 100644 index 0000000..c775d77 --- /dev/null +++ b/.cproject @@ -0,0 +1,143 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..3df573f --- /dev/null +++ b/.gitignore @@ -0,0 +1 @@ +/Debug/ diff --git a/.launches/PUMA260.launch b/.launches/PUMA260.launch new file mode 100644 index 0000000..8b15c1d --- /dev/null +++ b/.launches/PUMA260.launch @@ -0,0 +1,21 @@ + + + + + + + + + + + + + + + + + + + + + diff --git a/.launches/SMS.launch b/.launches/SMS.launch new file mode 100644 index 0000000..2779ea1 --- /dev/null +++ b/.launches/SMS.launch @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/.project b/.project new file mode 100644 index 0000000..713de6b --- /dev/null +++ b/.project @@ -0,0 +1,40 @@ + + + TIVA-Task-Scheduler + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + utils/uartstdio.c + 1 + TIVAWARE/utils/uartstdio.c + + + + + TIVAWARE + file:/C:/ti/TivaWare_C_Series-2.1.4.178 + + + diff --git a/.settings/org.eclipse.cdt.codan.core.prefs b/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 0000000..f653028 --- /dev/null +++ b/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,3 @@ +eclipse.preferences.version=1 +inEditor=false +onBuild=false diff --git a/.settings/org.eclipse.cdt.debug.core.prefs b/.settings/org.eclipse.cdt.debug.core.prefs new file mode 100644 index 0000000..2adc7b1 --- /dev/null +++ b/.settings/org.eclipse.cdt.debug.core.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.debug.core.toggleBreakpointModel=com.ti.ccstudio.debug.CCSBreakpointMarker diff --git a/.settings/org.eclipse.core.resources.prefs b/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 0000000..84767e5 --- /dev/null +++ b/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,16 @@ +eclipse.preferences.version=1 +encoding//Debug/ControlLoop/subdir_rules.mk=UTF-8 +encoding//Debug/ControlLoop/subdir_vars.mk=UTF-8 +encoding//Debug/EIB/subdir_rules.mk=UTF-8 +encoding//Debug/EIB/subdir_vars.mk=UTF-8 +encoding//Debug/MotorDriver/subdir_rules.mk=UTF-8 +encoding//Debug/MotorDriver/subdir_vars.mk=UTF-8 +encoding//Debug/TaskScheduler/subdir_rules.mk=UTF-8 +encoding//Debug/TaskScheduler/subdir_vars.mk=UTF-8 +encoding//Debug/makefile=UTF-8 +encoding//Debug/objects.mk=UTF-8 +encoding//Debug/sources.mk=UTF-8 +encoding//Debug/subdir_rules.mk=UTF-8 +encoding//Debug/subdir_vars.mk=UTF-8 +encoding//Debug/utils/subdir_rules.mk=UTF-8 +encoding//Debug/utils/subdir_vars.mk=UTF-8 diff --git a/README.md b/README.md new file mode 100644 index 0000000..b4c3442 --- /dev/null +++ b/README.md @@ -0,0 +1,2 @@ +# PUMA260 +An embedded board for controlling a PUMA260 Robot Arm. diff --git a/TaskScheduler/TaskScheduler.c b/TaskScheduler/TaskScheduler.c new file mode 100644 index 0000000..98df68e --- /dev/null +++ b/TaskScheduler/TaskScheduler.c @@ -0,0 +1,16 @@ +#include "TaskScheduler.h" + +static volatile TaskScheduler scheduler; + +void InitializeTaskScheduler(uint32_t timerBase){ +} + +void AddTask(Task *pTask){ + +} +void RemoveTask(Task *pTask){ + +} +void DisableTask(Task *pTask){ + +} diff --git a/TaskScheduler/TaskScheduler.h b/TaskScheduler/TaskScheduler.h new file mode 100644 index 0000000..5544571 --- /dev/null +++ b/TaskScheduler/TaskScheduler.h @@ -0,0 +1,29 @@ +#ifndef TIVA_TASK_SCHEDULER_H +#define TIVA_TASK_SCHEDULER_H + +#include +#include + +struct Task_tag; +typedef struct Task_tag Task; + +struct Task_tag { + uint32_t taskTimerTicks; + float taskPeriod; + void (*pCallback)(void); + bool taskEnabled; + Task *pNextTask; +}; + +typedef struct TaskScheduler_tag{ + uint32_t timerBase; + Task *pTaskListRoot; +} TaskScheduler; + +void InitializeTaskScheduler(uint32_t timerBase); + +void AddTask(Task *pTask); +void RemoveTask(Task *pTask); +void DisableTask(Task *pTask); + +#endif diff --git a/main.c b/main.c new file mode 100644 index 0000000..c947ade --- /dev/null +++ b/main.c @@ -0,0 +1,90 @@ +//Standard includes +#include +#include +#include +#include + +//Tivaware includes +#include "inc/hw_memmap.h" +#include "driverlib/gpio.h" +#include "driverlib/rom.h" +#include "driverlib/sysctl.h" +#include "driverlib/pin_map.h" +#include "driverlib/pwm.h" +#include "driverlib/adc.h" +#include "driverlib/ssi.h" +#include "driverlib/uart.h" +#include "utils/uartstdio.h" + +//System clock running at 120MHz +#define SYS_CLK 120000000 + +void EnableClock(void); +void EnablePeripherals(); +void InitConsole(void); + +//Copies val to the buffer as an ascii string. Arg1 is the number of places before decimal, arg2 is after. +void sprintfloat(char *Buffer, float val, int arg1){ + int LeftSide = (int)val; + int RightSide = (int)(pow(10,arg1) * (val - LeftSide)); //Remove the portion to the left of the decimal + sprintf(Buffer, "%i.%i", LeftSide, RightSide); +} + +int main(void) +{ + EnableClock(); + EnablePeripherals(); +} + +void EnableClock(void){ + + SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ | + SYSCTL_OSC_MAIN | + SYSCTL_USE_PLL | + SYSCTL_CFG_VCO_480), SYS_CLK); +} + +/* + Enables all peripherals needed for this motor driver test +*/ +void EnablePeripherals(void){ + InitConsole(); +} + +//Initializes UART0 to be used as a console. +void InitConsole(void){ + // + // Enable GPIO port A which is used for UART0 pins. + // TODO: change this to whichever GPIO port you are using. + // + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + + // + // Configure the pin muxing for UART0 functions on port A0 and A1. + // This step is not necessary if your part does not support pin muxing. + // TODO: change this to select the port/pin you are using. + // + GPIOPinConfigure(GPIO_PA0_U0RX); + GPIOPinConfigure(GPIO_PA1_U0TX); + + // + // Enable UART0 so that we can configure the clock. + // + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + + // + // Use the internal 16MHz oscillator as the UART clock source. + // + UARTClockSourceSet(UART0_BASE, UART_CLOCK_PIOSC); + + // + // Select the alternate (UART) function for these pins. + // TODO: change this to select the port/pin you are using. + // + GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1); + + // + // Initialize the UART for console I/O. + // + UARTStdioConfig(0, 115200, 16000000); +} diff --git a/targetConfigs/Tiva TM4C1294NCPDT.ccxml b/targetConfigs/Tiva TM4C1294NCPDT.ccxml new file mode 100644 index 0000000..72cd1da --- /dev/null +++ b/targetConfigs/Tiva TM4C1294NCPDT.ccxml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/targetConfigs/readme.txt b/targetConfigs/readme.txt new file mode 100644 index 0000000..d783fef --- /dev/null +++ b/targetConfigs/readme.txt @@ -0,0 +1,9 @@ +The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based +on the device and connection settings specified in your project on the Properties > General page. + +Please note that in automatic target-configuration management, changes to the project's device and/or +connection settings will either modify an existing or generate a new target-configuration file. Thus, +if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively, +you may create your own target-configuration file for this project and manage it manually. You can +always switch back to automatic target-configuration management by checking the "Manage the project's +target-configuration automatically" checkbox on the project's Properties > General page. \ No newline at end of file diff --git a/tm4c1294ncpdt.cmd b/tm4c1294ncpdt.cmd new file mode 100644 index 0000000..ee18ce7 --- /dev/null +++ b/tm4c1294ncpdt.cmd @@ -0,0 +1,45 @@ +/****************************************************************************** + * + * Default Linker Command file for the Texas Instruments TM4C1294NCPDT + * + * This is derived from revision 15071 of the TivaWare Library. + * + *****************************************************************************/ + +--retain=g_pfnVectors + +MEMORY +{ + FLASH (RX) : origin = 0x00000000, length = 0x00100000 + SRAM (RWX) : origin = 0x20000000, length = 0x00040000 +} + +/* The following command line options are set as part of the CCS project. */ +/* If you are building using the command line, or for some reason want to */ +/* define them here, you can uncomment and modify these lines as needed. */ +/* If you are using CCS for building, it is probably better to make any such */ +/* modifications in your CCS project and leave this file alone. */ +/* */ +/* --heap_size=0 */ +/* --stack_size=256 */ +/* --library=rtsv7M4_T_le_eabi.lib */ + +/* Section allocation in memory */ + +SECTIONS +{ + .intvecs: > 0x00000000 + .text : > FLASH + .const : > FLASH + .cinit : > FLASH + .pinit : > FLASH + .init_array : > FLASH + + .vtable : > 0x20000000 + .data : > SRAM + .bss : > SRAM + .sysmem : > SRAM + .stack : > SRAM +} + +__STACK_TOP = __stack + 512; diff --git a/tm4c1294ncpdt_startup_ccs.c b/tm4c1294ncpdt_startup_ccs.c new file mode 100644 index 0000000..ba49f31 --- /dev/null +++ b/tm4c1294ncpdt_startup_ccs.c @@ -0,0 +1,275 @@ +//***************************************************************************** +// +// Startup code for use with TI's Code Composer Studio. +// +// Copyright (c) 2011-2014 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Software License Agreement +// +// Texas Instruments (TI) is supplying this software for use solely and +// exclusively on TI's microcontroller products. The software is owned by +// TI and/or its suppliers, and is protected under applicable copyright +// laws. You may not combine this software with "viral" open-source +// software in order to form a larger program. +// +// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +// DAMAGES, FOR ANY REASON WHATSOEVER. +// +//***************************************************************************** + +#include + +//***************************************************************************** +// +// Forward declaration of the default fault handlers. +// +//***************************************************************************** +void ResetISR(void); +static void NmiSR(void); +static void FaultISR(void); +static void IntDefaultHandler(void); + +//***************************************************************************** +// +// External declaration for the reset handler that is to be called when the +// processor is started +// +//***************************************************************************** +extern void _c_int00(void); + +//***************************************************************************** +// +// Linker variable that marks the top of the stack. +// +//***************************************************************************** +extern uint32_t __STACK_TOP; + +//***************************************************************************** +// +// External declarations for the interrupt handlers used by the application. +// +//***************************************************************************** +// To be added by user + +//***************************************************************************** +// +// The vector table. Note that the proper constructs must be placed on this to +// ensure that it ends up at physical address 0x0000.0000 or at the start of +// the program if located at a start address other than 0. +// +//***************************************************************************** +#pragma DATA_SECTION(g_pfnVectors, ".intvecs") +void (* const g_pfnVectors[])(void) = +{ + (void (*)(void))((uint32_t)&__STACK_TOP), + // The initial stack pointer + ResetISR, // The reset handler + NmiSR, // The NMI handler + FaultISR, // The hard fault handler + IntDefaultHandler, // The MPU fault handler + IntDefaultHandler, // The bus fault handler + IntDefaultHandler, // The usage fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // SVCall handler + IntDefaultHandler, // Debug monitor handler + 0, // Reserved + IntDefaultHandler, // The PendSV handler + IntDefaultHandler, // The SysTick handler + IntDefaultHandler, // GPIO Port A + IntDefaultHandler, // GPIO Port B + IntDefaultHandler, // GPIO Port C + IntDefaultHandler, // GPIO Port D + IntDefaultHandler, // GPIO Port E + IntDefaultHandler, // UART0 Rx and Tx + IntDefaultHandler, // UART1 Rx and Tx + IntDefaultHandler, // SSI0 Rx and Tx + IntDefaultHandler, // I2C0 Master and Slave + IntDefaultHandler, // PWM Fault + IntDefaultHandler, // PWM Generator 0 + IntDefaultHandler, // PWM Generator 1 + IntDefaultHandler, // PWM Generator 2 + IntDefaultHandler, // Quadrature Encoder 0 + IntDefaultHandler, // ADC Sequence 0 + IntDefaultHandler, // ADC Sequence 1 + IntDefaultHandler, // ADC Sequence 2 + IntDefaultHandler, // ADC Sequence 3 + IntDefaultHandler, // Watchdog timer + IntDefaultHandler, // Timer 0 subtimer A + IntDefaultHandler, // Timer 0 subtimer B + IntDefaultHandler, // Timer 1 subtimer A + IntDefaultHandler, // Timer 1 subtimer B + IntDefaultHandler, // Timer 2 subtimer A + IntDefaultHandler, // Timer 2 subtimer B + IntDefaultHandler, // Analog Comparator 0 + IntDefaultHandler, // Analog Comparator 1 + IntDefaultHandler, // Analog Comparator 2 + IntDefaultHandler, // System Control (PLL, OSC, BO) + IntDefaultHandler, // FLASH Control + IntDefaultHandler, // GPIO Port F + IntDefaultHandler, // GPIO Port G + IntDefaultHandler, // GPIO Port H + IntDefaultHandler, // UART2 Rx and Tx + IntDefaultHandler, // SSI1 Rx and Tx + IntDefaultHandler, // Timer 3 subtimer A + IntDefaultHandler, // Timer 3 subtimer B + IntDefaultHandler, // I2C1 Master and Slave + IntDefaultHandler, // CAN0 + IntDefaultHandler, // CAN1 + IntDefaultHandler, // Ethernet + IntDefaultHandler, // Hibernate + IntDefaultHandler, // USB0 + IntDefaultHandler, // PWM Generator 3 + IntDefaultHandler, // uDMA Software Transfer + IntDefaultHandler, // uDMA Error + IntDefaultHandler, // ADC1 Sequence 0 + IntDefaultHandler, // ADC1 Sequence 1 + IntDefaultHandler, // ADC1 Sequence 2 + IntDefaultHandler, // ADC1 Sequence 3 + IntDefaultHandler, // External Bus Interface 0 + IntDefaultHandler, // GPIO Port J + IntDefaultHandler, // GPIO Port K + IntDefaultHandler, // GPIO Port L + IntDefaultHandler, // SSI2 Rx and Tx + IntDefaultHandler, // SSI3 Rx and Tx + IntDefaultHandler, // UART3 Rx and Tx + IntDefaultHandler, // UART4 Rx and Tx + IntDefaultHandler, // UART5 Rx and Tx + IntDefaultHandler, // UART6 Rx and Tx + IntDefaultHandler, // UART7 Rx and Tx + IntDefaultHandler, // I2C2 Master and Slave + IntDefaultHandler, // I2C3 Master and Slave + IntDefaultHandler, // Timer 4 subtimer A + IntDefaultHandler, // Timer 4 subtimer B + IntDefaultHandler, // Timer 5 subtimer A + IntDefaultHandler, // Timer 5 subtimer B + IntDefaultHandler, // FPU + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // I2C4 Master and Slave + IntDefaultHandler, // I2C5 Master and Slave + IntDefaultHandler, // GPIO Port M + IntDefaultHandler, // GPIO Port N + 0, // Reserved + IntDefaultHandler, // Tamper + IntDefaultHandler, // GPIO Port P (Summary or P0) + IntDefaultHandler, // GPIO Port P1 + IntDefaultHandler, // GPIO Port P2 + IntDefaultHandler, // GPIO Port P3 + IntDefaultHandler, // GPIO Port P4 + IntDefaultHandler, // GPIO Port P5 + IntDefaultHandler, // GPIO Port P6 + IntDefaultHandler, // GPIO Port P7 + IntDefaultHandler, // GPIO Port Q (Summary or Q0) + IntDefaultHandler, // GPIO Port Q1 + IntDefaultHandler, // GPIO Port Q2 + IntDefaultHandler, // GPIO Port Q3 + IntDefaultHandler, // GPIO Port Q4 + IntDefaultHandler, // GPIO Port Q5 + IntDefaultHandler, // GPIO Port Q6 + IntDefaultHandler, // GPIO Port Q7 + IntDefaultHandler, // GPIO Port R + IntDefaultHandler, // GPIO Port S + IntDefaultHandler, // SHA/MD5 0 + IntDefaultHandler, // AES 0 + IntDefaultHandler, // DES3DES 0 + IntDefaultHandler, // LCD Controller 0 + IntDefaultHandler, // Timer 6 subtimer A + IntDefaultHandler, // Timer 6 subtimer B + IntDefaultHandler, // Timer 7 subtimer A + IntDefaultHandler, // Timer 7 subtimer B + IntDefaultHandler, // I2C6 Master and Slave + IntDefaultHandler, // I2C7 Master and Slave + IntDefaultHandler, // HIM Scan Matrix Keyboard 0 + IntDefaultHandler, // One Wire 0 + IntDefaultHandler, // HIM PS/2 0 + IntDefaultHandler, // HIM LED Sequencer 0 + IntDefaultHandler, // HIM Consumer IR 0 + IntDefaultHandler, // I2C8 Master and Slave + IntDefaultHandler, // I2C9 Master and Slave + IntDefaultHandler, // GPIO Port T + IntDefaultHandler, // Fan 1 + 0, // Reserved +}; + +//***************************************************************************** +// +// This is the code that gets called when the processor first starts execution +// following a reset event. Only the absolutely necessary set is performed, +// after which the application supplied entry() routine is called. Any fancy +// actions (such as making decisions based on the reset cause register, and +// resetting the bits in that register) are left solely in the hands of the +// application. +// +//***************************************************************************** +void +ResetISR(void) +{ + // + // Jump to the CCS C initialization routine. This will enable the + // floating-point unit as well, so that does not need to be done here. + // + __asm(" .global _c_int00\n" + " b.w _c_int00"); +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a NMI. This +// simply enters an infinite loop, preserving the system state for examination +// by a debugger. +// +//***************************************************************************** +static void +NmiSR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a fault +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +FaultISR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives an unexpected +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +}